ST7PLITES5Y0M6TR [STMICROELECTRONICS]
8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI; 8位微控制器的单电压闪存存储器，数据EEPROM ， ADC ，定时器， SPI
| 型号： | ST7PLITES5Y0M6TR |
| 厂家： | 
ST |
| 描述： | 8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| 文件： | 总124页 (文件大小：2150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7LITE0xY0, ST7LITESxY0
8-bit microcontroller with single voltage
Flash memory, data EEPROM, ADC, timers, SPI
■ Memories
– 1K or 1.5 Kbytes single voltage Flash Pro-
gram memory with read-out protection, In-Cir-
cuit and In-Application Programming (ICP and
IAP). 10 K write/erase cycles guaranteed,
data retention: 20 years at 55 °C.
SO16
150”
DIP16
– 128 bytes RAM.
– 128 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55 °C.
QFN20
■ Clock, Reset and Supply Management
– One 12-bit Auto-reload Timer (AT) with output
compare function and PWM
– 3-level low voltage supervisor (LVD) and aux-
iliary voltage detector (AVD) for safe power-
on/off procedures
■ 1 Communication Interface
– SPI synchronous serial interface
– Clock sources: internal 1MHz RC 1% oscilla-
tor or external clock
■ A/D Converter
– PLL x4 or x8 for 4 or 8 MHz internal clock
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
– 8-bit resolution for 0 to V
DD
– Fixed gain Op-amp for 11-bit resolution in 0 to
250 mV range (@ 5V V
)
DD
■ Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 4 external interrupt lines (on 4 vectors)
■ I/O Ports
– 5 input channels
■ Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode de-
tection
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– 13 multifunctional bidirectional I/O lines
– 9 alternate function lines
– 6 high sink outputs
■ 2 Timers
■ Development Tools
– One 8-bit Lite Timer (LT) with prescaler in-
cluding: watchdog, 1 realtime base and 1 in-
put capture.
– Full hardware/software development package
Device Summary
ST7LITESxY0 (ST7SUPERLITE)
ST7LITE0xY0
ST7LITE05Y0
Features
ST7LITES2Y0
ST7LITES5Y0
ST7LITE02Y0
ST7LITE09Y0
1.5K
Program memory - bytes
RAM (stack) - bytes
1K
1K
1.5K
1.5K
128 (64)
-
128 (64)
128 (64)
128 (64)
128 (64)
128
Data EEPROM - bytes
-
-
-
LT Timer w/ Wdg,
LT Timer w/ Wdg,
LT Timer w/ Wdg,
LT Timer w/ Wdg,
Peripherals
AT Timer w/ 1 PWM, AT Timer w/ 1 PWM, AT Timer w/ 1 PWM,
AT Timer w/ 1 PWM, SPI,
8-bit ADC w/ Op-Amp
SPI
SPI, 8-bit ADC
SPI
Operating Supply
CPU Frequency
Operating Temperature
Packages
2.4V to 5.5V
1MHz RC 1% + PLLx4/8MHz
-40°C to +85°C
SO16 150”, DIP16, QFN20
Rev 6
1/124
November 2007
1
Table of Contents
ST7LITE0xY0, ST7LITESxY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Table of Contents
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.4 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . . 93
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 102
13.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 112
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 114
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD-
WARE WATCHDOG OPTION 121
16.3 IN-CIRCUIT DEBUGGING WITH HARDWARE WATCHDOG . . . . . . . . . . . . . . . . . . . 121
16.4 RECOMMENDATIONS WHEN LVD IS ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 121
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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Table of Contents
To obtain the most recent version of this datasheet,
please check at www.st.com
Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 121.
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1
ST7LITE0xY0, ST7LITESxY0
1 DESCRIPTION
The
ST7LITE0x
and
ST7SUPERLITE
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
(ST7LITESx) are members of the ST7 microcon-
troller family. All ST7 devices are based on a com-
mon industry-standard 8-bit core, featuring an en-
hanced instruction set.
The ST7LITE0x and ST7SUPERLITE feature
FLASH memory with byte-by-byte In-Circuit Pro-
gramming (ICP) and In-Application Programming
(IAP) capability.
For easy reference, all parametric data are located
in section 13 on page 81.
Under software control, the ST7LITE0x and
ST7SUPERLITE devices can be placed in WAIT,
SLOW, or HALT mode, reducing power consump-
tion when the application is in idle or standby state.
Figure 1. General Block Diagram
Internal
CLOCK
1 MHz. RC OSC
+
PLL x 4 or x 8
LITE TIMER
w/ WATCHDOG
LVD/AVD
V
DD
PA7:0
(8 bits)
POWER
SUPPLY
PORT A
V
SS
12-BIT AUTO-
RELOAD TIMER
RESET
CONTROL
8-BIT CORE
ALU
SPI
FLASH
MEMORY
(1 or 1.5K Bytes)
PB4:0
(5 bits)
PORT B
8-BIT ADC
RAM
(128 Bytes)
DATA EEPROM
(128 Bytes)
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1
ST7LITE0xY0, ST7LITESxY0
2 PIN DESCRIPTION
Figure 2. 20-Pin QFN Package Pinout
20 19 18 17
16
15
PA1 (HS)
1
RESET
NC
e3
e0
PA2 (HS)/ATPWM0
PA3 (HS)
2
3
4
5
6
14
13
12
11
NC
NC
NC
PA4 (HS)
MISO/AIN2/PB2
SCK/AIN1/PB1
ei1
9
ei2
7
PA5 (HS)/ICCDATA
8
10
(HS) 20mA High sink capability
eix associated external interrupt vector
Figure 3. 16-Pin SO and DIP Package Pinout
k
V
PA0 (HS)/LTIC
1
ei0 16
15
SS
V
PA1 (HS)
2
DD
RESET
3
PA2 (HS)/ATPWM0
14
SS/AIN0/PB0
PA3 (HS)
4
5
6
7
8
ei3
13
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
PA4 (HS)
12
PA5 (HS)/ICCDATA
PA6/MCO/ICCCLK
PA7
11
ei2
10
ei1
9
(HS) 20mA high sink capability
ei associated external interrupt vector
x
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ST7LITE0xY0, ST7LITESxY0
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
In/Output level: C= CMOS 0.15V /0.85V with input trigger
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
OD = open drain, PP = push-pull
– Output:
Table 1. Device Pin Description
Pin n°
Level
Port / Control
Input Output
Main
Pin Name
Function
(after reset)
Alternate Function
18
19
1
1
2
3
V
V
S
S
Ground
SS
DD
Main power supply
RESET
I/O
C
C
X
X
X
Top priority non maskable interrupt (active low)
T
T
ADC Analog Input 0 or SPI Slave
Select (active low)
20
4
PB0/AIN0/SS
I/O
I/O
X
X
ei3
X
X
X
X
Port B0
ADC Analog Input 1 or SPI Clock
Caution: No negative current in-
jection allowed on this pin. For
details, refer to section 13.2.2 on
page 82
6
5
PB1/AIN1/SCK
C
X
X
X
Port B1
T
ADC Analog Input 2 or SPI Mas-
ter In/ Slave Out Data
5
7
6
7
PB2/AIN2/MISO
PB3/AIN3/MOSI
I/O
I/O
C
C
X
X
X
X
X
X
X
X
X
Port B2
Port B3
T
T
ADC Analog Input 3 or SPI Mas-
ter Out / Slave In Data
ei2
ei1
ADC Analog Input 4 or External
clock input
8
9
8
9
PB4/AIN4/CLKIN I/O
C
C
X
X
X
X
X
X
X
Port B4
Port A7
T
T
PA7
I/O
Main Clock Output/In Circuit
Communication Clock.
Caution: During normal opera-
tion this pin must be pulled- up,
internally or externally (external
pull-up of 10k mandatory in noisy
environment). This is to avoid en-
tering ICC mode unexpectedly
during a reset. In the application,
even if the pin is configured as
output, any reset will put it back in
input pull-up
PA6 /MCO/
ICCCLK
10 10
I/O
C
X
X
X
X
Port A6
T
PA5/
ICCDATA
11 11
I/O C HS
X
X
X
X
Port A5
In Circuit Communication Data
T
12 12 PA4
14 13 PA3
I/O C HS
X
X
X
X
X
X
X
X
Port A4
Port A3
T
I/O C HS
T
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ST7LITE0xY0, ST7LITESxY0
Pin n°
Level
Port / Control
Input Output
Main
Pin Name
Function
(after reset)
Alternate Function
15 14 PA2/ATPWM0
16 15 PA1
I/O C HS
X
X
X
X
X
X
X
X
X
X
Port A2
Port A1
Port A0
Auto-Reload Timer PWM0
Lite Timer Input Capture
T
I/O C HS
X
T
17 16 PA0/LTIC
I/O C HS
ei0
T
Note:
In the interrupt input column, “ei ” defines the associated external interrupt vector. If the weak pull-up col-
x
umn (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
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ST7LITE0xY0, ST7LITESxY0
3 REGISTER & MEMORY MAP
As shown in Figure 4 and Figure 5, the MCU is ca-
pable of addressing 64K bytes of memories and I/
O registers.
The highest address bytes contain the user reset
and interrupt vectors.
The size of Flash Sector 0 is configurable by Op-
tion byte.
The available memory locations consist of up to
128 bytes of register locations, 128 bytes of RAM,
128 bytes of data EEPROM and up to 1.5 Kbytes
of user program memory. The RAM space in-
cludes up to 64 bytes for the stack from 0C0h to
0FFh.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
Figure 4. Memory Map (ST7LITE0x)
0000h
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
007Fh
0080h
00BFh
00C0h
RAM
(128 Bytes)
64 Bytes Stack
00FFh
0100h
00FFh
Reserved
0FFFh
1000h
1000h
RCCR0
Data EEPROM
(128 Bytes)
RCCR1
1001h
107Fh
1080h
see section 7.1 on page 24
1.5K FLASH
PROGRAM MEMORY
Reserved
F9FFh
FA00h
FA00h
0.5 Kbytes
SECTOR 1
FBFFh
FC00h
Flash Memory
(1.5K)
1 Kbytes
SECTOR 0
FFFFh
FFDFh
FFE0h
FFDEh
RCCR0
Interrupt & Reset Vectors
(see Table 6)
RCCR1
FFDFh
FFFFh
see section 7.1 on page 24
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REGISTER AND MEMORY MAP (Cont’d)
Figure 5. Memory Map (ST7SUPERLITE)
0000h
0080h
HW Registers
Short Addressing
RAM (zero page)
(see Table 2)
007Fh
00BFh
00C0h
0080h
RAM
(128 Bytes)
64 Bytes Stack
00FFh
0100h
00FFh
Reserved
1K FLASH
PROGRAM MEMORY
FBFFh
FC00h
FC00h
0.5 Kbytes
SECTOR 1
FDFFh
FE00h
Flash Memory
(1K)
0.5 Kbytes
SECTOR 0
FFFFh
FFDFh
FFE0h
Interrupt & Reset Vectors
FFDEh
FFDFh
RCCR0
RCCR1
(see Table 6)
FFFFh
see section 7.1 on page 24
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ST7LITE0xY0, ST7LITESxY0
REGISTER AND MEMORY MAP (Cont’d)
Legend: x=undefined, R/W=read/write
Table 2. Hardware Register Map
Register
Label
Reset
Address
Block
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Remarks
Status
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
00h
00h
40h
R/W
R/W
R/W
Port A
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
E0h
00h
00h
R/W
R/W
R/W
Port B
2)
0006h to
000Ah
Reserved area (5 bytes)
000Bh
000Ch
LITE
TIMER
LTCSR
LTICR
Lite Timer Control/Status Register
Lite Timer Input Capture Register
xxh
xxh
R/W
Read Only
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
AUTO-RELOAD
TIMER
PWM0CSR PWM 0 Control/Status Register
R/W
0014h to
0016h
Reserved area (3 bytes)
0017h AUTO-RELOAD DCR0H
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
00h
00h
R/W
R/W
0018h
TIMER
DCR0L
0019h to
002Eh
Reserved area (22 bytes)
0002Fh
00030h
FLASH
FCSR
Flash Control/Status Register
00h
00h
R/W
R/W
EEPROM
EECSR
Data EEPROM Control/Status Register
0031h
0032h
0033h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
0034h
0035h
0036h
ADCCSR
ADCDR
ADCAMP
A/D Control Status Register
A/D Data Register
A/D Amplifier Control Register
00h
00h
00h
R/W
Read Only
R/W
ADC
0037h
ITC
EICR
External Interrupt Control Register
00h
R/W
0038h
0039h
MCCSR
RCCR
Main Clock Control/Status Register
RC oscillator Control Register
00h
FFh
R/W
R/W
CLOCKS
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1
ST7LITE0xY0, ST7LITESxY0
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
R/W
003Ah
SI
SICSR
System Integrity Control/Status Register
Reserved area (69 bytes)
0xh
003Bh to
007Fh
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
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4 FLASH PROGRAM MEMORY
4.1 Introduction
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Commu-
nication) which allows an ST7 plugged on a print-
ed circuit board (PCB) to communicate with an ex-
ternal programming device connected via cable.
ICP is performed in three steps:
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Program-
ming.
Switch the ST7 to ICC mode (In-Circuit Communi-
cations). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory contain-
ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
– Download ICP Driver code in RAM from the
ICCDATA pin
■ ICP (In-Circuit Programming)
– Execute ICP Driver code in RAM to program
the FLASH memory
■ IAP (In-Application Programming)
■ ICT (In-Circuit Testing) for downloading and
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Read-out and write protection
4.3 PROGRAMMING MODES
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM can be programmed or
erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM can be programmed or erased with-
out removing the device from the application
board.
– In-Application Programming. In this mode,
sector 1 and data EEPROM can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory ar-
eas except Sector 0, which is write/erase protect-
ed to allow recovery in case errors occur during
the programming operation.
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FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET: device reset
– V : device power supply ground
SS
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– CLKIN: main clock input for external source
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
– V : application board power supply (option-
DD
al, see Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
4. Pin 9 has to be connected to the CLKIN pin of
the ST7 when the clock is not available in the ap-
plication or if the selected clock option is not pro-
grammed in the option byte.
Caution: During normal operation, ICCCLK pin
must be pulled- up, internally or externally (exter-
nal pull-up of 10K mandatory in noisy environ-
ment). This is to avoid entering ICC mode unex-
pectedly during a reset. In the application, even if
the pin is configured as output, any reset will put it
back in input pull-up.
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
APPLICATION BOARD
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
POWER SUPPLY
See Note 1 and Caution
See Note 1
APPLICATION
I/O
ST7
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FLASH PROGRAM MEMORY (Cont’d)
4.5 Memory Protection
Write/erase protection is enabled through the
FMP_W bit in the option byte.
There are two different types of memory protec-
tion: Read Out Protection and Write/Erase Protec-
tion which can be applied individually.
4.6 Related Documentation
4.5.1 Read out Protection
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
Even if no protection can be considered as totally
unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
4.7 Register Description
2
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
Both program and data E memory are protected.
In flash devices, this protection is removed by re-
programming the option. In this case, both pro-
2
gram and data E memory are automatically
erased, and the device can be reprogrammed.
7
0
0
Read-out protection selection depends on the de-
vice type:
0
0
0
0
OPT
LAT
PGM
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing op-
erations.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos-
sible to both overwrite and erase program memo-
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
2
ry. It does not apply to E data. Its purpose is to
provide advanced security to applications and pre-
vent any change being made to the memory con-
tent.
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
Table 3. FLASH Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
FCSR
Reset Value
OPT
0
LAT
0
PGM
0
002Fh
0
0
0
0
0
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5 DATA EEPROM
5.1 INTRODUCTION
5.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non-volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Up to 32 bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Read-out protection
Figure 7. EEPROM Block Diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
EEPROM
ROW
ADDRESS
DECODER
4
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
32 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
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DATA EEPROM (Cont’d)
5.3 MEMORY ACCESS
the value is latched inside the 32 data latches ac-
cording to its address.
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 8 describes these different memory
access modes.
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: Only the five Least
Significant Bits of the address can change.
Read Operation (E2LAT = 0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the EECSR register is
cleared.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
On this device, Data EEPROM can also be used to
execute machine code. Take care not to write to
the Data EEPROM while executing from it. This
would result in an unexpected code being execut-
ed.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
Write Operation (E2LAT = 1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
It is not possible to read the latched data.
This note is illustrated by the Figure 10.
Figure 8. Data EEPROM Programming Flowchart
READ MODE
E2LAT = 0
WRITE MODE
E2LAT = 1
E2PGM = 0
E2PGM = 0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
1
E2LAT
CLEARED BY HARDWARE
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DATA EEPROM (Cont’d)
2
Figure 9. Data E PROM Write Operation
⇓ Row / Byte ⇒
0
1
2
3
...
30 31
Physical Address
00h...1Fh
0
1
ROW
DEFINITION
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Read operation possible
Programming cycle
Byte 1 Byte 2
PHASE 1
Byte 32
PHASE 2
Writing data latches
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note: If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not
be guaranteed.
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DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
Wait mode
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT = 1, then the
data bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler or when the microcontroller enters Active Halt
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while E2LAT = 0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by RESET
action), the integrity of the data in memory will not
be guaranteed.
5.6 DATA EEPROM READ-OUT PROTECTION
Active Halt mode
The read-out protection is enabled through an op-
tion bit (see option byte section).
Refer to Wait mode.
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out (including a re-write protection).
In Flash devices, when this protection is removed
by reprogramming the Option Byte, the entire Pro-
gram memory and EEPROM is first automatically
erased.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 10. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA
LATCHES
t
PROG
LAT
PGM
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DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EEC-
SR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT E2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: If the E2PGM bit is cleared during the pro-
gramming cycle, the memory data is not guaran-
teed.
Table 4. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
E2LAT
0
E2PGM
0
0030h
0
0
0
0
0
0
Reset Value
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6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
6.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
6.3 CPU REGISTERS
The six CPU registers shown in Figure 11 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 11. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
H I N Z C
X 1 X X X
1
1
1
1
CONDITION CODE REGISTER
RESET VALUE =
8
1
15
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Bit 2 = N Negative.
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
th
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible
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CPU REGISTERS (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 00 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
0
0
0
7
1
0
1
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 12.
SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 12).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 64 bytes deep, the 10 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP5 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 12. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
event
@ 00C0h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 00FFh
Stack Higher Address = 00FFh
00C0h
Stack Lower Address =
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ST7LITE0xY0, ST7LITESxY0
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
ST7FLITE05/
ST7FLITES5
ST7FLITE09
Address
securing the application in critical situations (for
RCCR
Conditions
=5V
example in case of a power brown-out), and re-
ducing the number of external components.
Address
V
DD
1000h and
FFDEh
RCCR0
RCCR1
T =25°C
FFDEh
Main features
A
f
=1MHz
RC
■ Clock Management
V
=3.0V
DD
1001h and-
FFDFh
– 1 MHz internal RC oscillator (enabled by op-
tion byte)
T =25°C
FFDFh
A
f
=700KHz
RC
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 4 or 8
(enabled by option byte)
– These two bytes are systematically programmed
by ST, including on FASTROM devices. Conse-
quently, customers intending to us e FASTROM
service must not use these two bytes.
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
– RCCR0 and RCCR1 calibration values will be
erased if the read-out protection bit is reset after
it has been set. See “Read out Protection” on
page 15.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The ST7 contains an internal RC oscillator with an
accuracy of 1% for a given device, temperature
and voltage. It must be calibrated to obtain the fre-
quency required in the application. This is done by
software writing a calibration value in the RCCR
(RC Control Register).
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequen-
cy from the RC oscillator or the external clock by 4
or 8 to obtain f
of 4 or 8 MHz. The PLL is ena-
OSC
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be load-
ed in the RCCR. Predefined calibration values are
bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
– The x4 PLL is intended for operation with V in
DD
the 2.4V to 3.3V range
stored in EEPROM for 3.0 and 5V V supply volt-
DD
ages at 25°C, as shown in the following table.
– The x8 PLL is intended for operation with V in
DD
the 3.3V to 5.5V range
Notes:
Refer to Section 15.1 for the option byte descrip-
tion.
– See “ELECTRICAL CHARACTERISTICS” on
page 81. for more information on the frequency
and accuracy of the RC oscillator.
If the PLL is disabled and the RC oscillator is ena-
bled, then f
1MHz.
OSC =
– To improve clock stability and frequency accura-
cy, it is recommended to place a decoupling ca-
If both the RC oscillator and the PLL are disabled,
is driven by the external clock.
f
OSC
pacitor, typically 100nF, between the V and
DD
V
pins as close as possible to the ST7 device.
SS
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1
ST7LITE0xY0, ST7LITESxY0
Figure 13. PLL Output Frequency Timing
Diagram
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
LOCKED bit set
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
4/8 x
input
freq.
t
STAB
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
t
LOCK
clock f
or f
/32.
OSC
OSC
0: Normal mode (f
f
CPU = OSC
t
STARTUP
1: Slow mode (f
f
/32)
CPU = OSC
t
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
.
7
0
STARTUP
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
is set. Full PLL accuracy (ACC ) is reached after
PLL
a stabilization time of t
(see Figure 13 and
STAB
Bits 7:0 = CR[7:0] RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
13.3.4 Internal RC Oscillator and PLL)
Refer to section 8.4.4 on page 36 for a description
of the LOCKED bit in the SICSR register.
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
7
0
0
MCO SMS
0
0
0
0
0
Bits 7:2 = Reserved, must be kept cleared.
Table 5. Clock Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MCCSR
MCO
0
SMS
0
0038h
0039h
0
0
0
0
0
0
Reset Value
RCCR
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
CR1
1
CR0
1
Reset Value
25/124
1
ST7LITE0xY0, ST7LITESxY0
SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)
Figure 14. Clock Management Block Diagram
CR7 CR6 CR5 CR4 CR3 CR2 CR1
CR0
RCCR
1MHz
8MHz
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz
f
Tunable
1% RC Oscillator
OSC
4MHz
Option byte
0 to 8 MHz
/2 DIVIDER
CLKIN
Option byte
f
LTIMER
8-BIT
(1ms timebase @ 8 MHzf
)
LITE TIMER COUNTER
OSC
f
f
/32
OSC
OSC
/32 DIVIDER
1
0
f
CPU
TO CPU AND
PERIPHERALS
f
OSC
(except LITE
TIMER)
MCCSR
MCO SMS
0
7
f
CPU
MCO
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1
ST7LITE0xY0, ST7LITESxY0
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
The reset sequence manager includes three RE-
SET sources as shown in Figure 16:
The RESET vector fetch phase duration is 2 clock
cycles.
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
Figure 13).
(see
STARTUP
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 11.2.1 on page 53 for further details.
Figure 15. RESET Sequence Phases
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
RESET
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
INTERNAL RESET
Active Phase
FETCH
VECTOR
256 CLOCK CYCLES
The basic RESET sequence consists of 3 phases
as shown in Figure 15:
■ Active Phase depending on the RESET source
■ 256 CPU clock cycle delay
■ RESET vector fetch
Figure 16.Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
FILTER
RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET 1)
PULSE
GENERATOR
LVD RESET
Note 1: See “Illegal Opcode Reset” on page 78. for more details on illegal opcode reset conditions.
27/124
1
ST7LITE0xY0, ST7LITESxY0
RESET SEQUENCE MANAGER (Cont’d)
7.4.2 Asynchronous External RESET pin
A proper reset signal for a slow rising V supply
can generally be provided by an external RC net-
work connected to the RESET pin.
DD
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
7.4.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
A RESET signal originating from an external
source must have a duration of at least t
in
h(RSTL)in
■ Voltage Drop RESET
order to be recognized (see Figure 17). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 17.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
DD
IT-
The LVD filters spikes on V larger than t
to
DD
g(VDD)
avoid parasitic resets.
7.4.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 17.
7.4.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
signal is held low until V
is over the minimum
w(RSTL)out
DD
level specified for the selected f
frequency.
OSC
Figure 17. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 TCPU
)
VECTOR FETCH
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ST7LITE0xY0, ST7LITESxY0
8 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: Maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 18.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
8.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It is serviced according to the flowchart in Figure
18.
8.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the HALT low power
mode.
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– The PC, X, A and CC registers are saved onto
the stack.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of a NANDed source
(as described in the I/O ports section), a low level
on an I/O pin, configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit is cleared and the main program resumes.
8.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
Priority Management
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
In the case when several interrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping Table).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
Interrupts and Low Power Mode
– Writing “0” to the corresponding bit in the status
register or
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT” column in the Interrupt Mapping Ta-
ble).
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: The clearing sequence resets the internal
latch. A pending interrupt (that is, waiting for being
enabled) will therefore be lost if the clear se-
quence is executed.
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ST7LITE0xY0, ST7LITESxY0
INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
N
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
RESET
TRAP
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Highest
Priority
Software Interrupt
Not used
0
1
ei0
ei1
ei2
ei3
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Not used
N/A
2
yes
3
4
5
6
Not used
7
SI
AVD interrupt
SICSR
PWM0CSR
ATCSR
no
no
8
AT TIMER Output Compare Interrupt
AT TIMER Overflow Interrupt
LITE TIMER Input Capture Interrupt
LITE TIMER RTC Interrupt
SPI Peripheral Interrupts
Not used
AT TIMER
9
yes
no
10
11
12
13
LTCSR
LITE TIMER
SPI
LTCSR
yes
yes
SPICSR
Lowest
Priority
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ST7LITE0xY0, ST7LITESxY0
INTERRUPTS (Cont’d)
EXTERNAL INTERRUPT CONTROL REGISTER
(EICR)
Notes:
1. These 8 bits can be written only when the I bit in
the CC register is set.
Read/Write
Reset Value: 0000 0000 (00h)
2. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be
used to clear unwanted pending interrupts. Refer
to section “External interrupt function” on page 42.
7
0
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
Table 7. Interrupt Sensitivity Bits
Bit 7:6 = IS3[1:0] ei3 sensitivity
These bits define the interrupt sensitivity for ei3
(Port B0) according to Table 7.
ISx1 ISx0
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Bit 5:4 = IS2[1:0] ei2 sensitivity
These bits define the interrupt sensitivity for ei2
(Port B3) according to Table 7.
Falling edge only
Rising and falling edge
Bit 3:2 = IS1[1:0] ei1 sensitivity
These bits define the interrupt sensitivity for ei1
(Port A7) according to Table 7.
Bit 1:0 = IS0[1:0] ei0 sensitivity
These bits define the interrupt sensitivity for ei0
(Port A0) according to Table 7.
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ST7LITE0xY0, ST7LITESxY0
8.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Provided the minimum V value (guaranteed for
DD
the oscillator frequency) is above V
MCU can only be in two modes:
, the
IT-(LVD)
– under full software control
– in static safe reset
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 12.2.1 on page 78 for further details.
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
8.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
ates a static reset when the V supply voltage is
DD
below a V
reference value. This means that
IT-(LVD)
it secures the power-up as well as the power-down
keeping the ST7 in reset.
Notes:
The V
reference value for a voltage drop is
IT-(LVD)
lower than the V
reference value for power-
The LVD is an optional function which can be se-
lected by option byte. See section 15.1 on page
112.
IT+(LVD)
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
It allows the device to be used without any external
RESET circuitry.
The LVD Reset circuitry generates a reset when
V
is below:
DD
If the LVD is disabled, an external circuitry must be
used to ensure a proper power-on reset.
– V
when V is rising
IT+(LVD)
DD
– V
when V is falling
It is recommended to make sure that the V sup-
IT-(LVD)
DD
DD
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
The LVD function is illustrated in Figure 19.
The voltage threshold can be configured by option
byte to be low, medium or high. See section 15.1
on page 112.
Caution: If an LVD reset occurs after a watchdog
reset has occurred, the LVD will take priority and
will clear the watchdog flag.
Figure 19. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
(LVD)
IT-
(LVD)
RESET
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ST7LITE0xY0, ST7LITESxY0
Figure 20. Reset and Supply Management Block Diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
AVD Interrupt Request
RESET
SICSR
(RSM)
LOC LVD AVD AVD
0
0
0
0
KED RF
F
IE
0
7
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
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ST7LITE0xY0, ST7LITESxY0
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
8.4.2 Auxiliary Voltage Detector (AVD)
8.4.2.1 Monitoring the V Main Supply
DD
The Voltage Detector function (AVD) is based on
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see section 15.1 on page 112).
an analog comparison between a V
and
IT-(AVD)
V
reference value and the V
main sup-
IT+(AVD)
DD
ply voltage (V
). The V
reference value
AVD
IT-(AVD)
If the AVD interrupt is enabled, an interrupt is gen-
for falling voltage is lower than the V
refer-
IT+(AVD)
erated when the voltage crosses the V
IT-(AVD)
or
IT+(LVD)
ence value for rising voltage in order to avoid par-
asitic detection (hysteresis).
V
threshold (AVDF bit is set).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 21.
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD functions only if the LVD is en-
abled through the option byte.
The interrupt on the rising edge is used to inform
the application that the V warning state is over
DD
Figure 21. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
IT-(LVD)
AVDF bit
0
1
RESET
1
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT Cleared by
reset
INTERRUPT Cleared by
hardware
LVD RESET
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ST7LITE0xY0, ST7LITESxY0
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
8.4.3 Low Power Modes
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode
WAIT
Description
Enable Exit
Control from
Exit
from
Halt
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
Event
Flag
Interrupt Event
Bit
Wait
The SICSR register is frozen.
AVD event
AVDF AVDIE
Yes
No
HALT
The AVD remains active but the AVD inter-
rupt cannot be used to exit from Halt mode.
8.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
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ST7LITE0xY0, ST7LITESxY0
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
8.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to Figure
21 for additional details
Reset Value: 0000 0x00 (0xh)
0: V over AVD threshold
DD
7
0
1: V under AVD threshold
DD
LOCK
ED
0
0
0
0
LVDRF AVDF AVDIE
Bit 0 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
Bit 7:4 = Reserved, must be kept cleared.
Bit 3 = LOCKED PLL Locked Flag
This bit is set by hardware. It is cleared only by a
power-on reset. It is set automatically when the
PLL reaches its operating frequency.
0: PLL not locked
0: AVD interrupt disabled
1: AVD interrupt enabled
1: PLL locked
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description in Section 11.1 for more
details. When the LVD is disabled by OPTION
BYTE, the LVDRF bit value is undefined.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
Table 8. System Integrity Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
LOCKED LVDRF
AVDF
0
AVDIE
0
003Ah
0
0
0
0
0
x
Reset Value
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ST7LITE0xY0, ST7LITESxY0
9 POWER SAVING MODES
9.1 INTRODUCTION
9.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 22): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
main oscillator frequency (f
).
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
lower frequency.
OSC
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Notes:
SLOW-WAIT mode is activated when entering
WAIT mode while the device is already in SLOW
mode.
Figure 22. Power Saving Mode Transitions
SLOW mode has no effect on the Lite Timer which
is already clocked at F
.
OSC/32
High
RUN
Figure 23. SLOW Mode Clock Transition
f
/32
f
OSC
OSC
SLOW
WAIT
f
CPU
f
OSC
SLOW WAIT
ACTIVE HALT
HALT
SMS
NORMAL RUN MODE
REQUEST
Low
POWER CONSUMPTION
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POWER SAVING MODES (Cont’d)
9.3 WAIT MODE
Figure 24. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
WFI INSTRUCTION
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of
the interrupt or Reset service routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
ON
OFF
ON
0
Refer to Figure 24.
CPU
I BIT
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
1)
I BIT
X
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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POWER SAVING MODES (Cont’d)
9.4 ACTIVE-HALT AND HALT MODES
Figure 25. ACTIVE-HALT Timing Overview
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the LTCSR/ATCSR reg-
ister status as shown in the following table:.
ACTIVE
HALT
256 CPU
CYCLE DELAY
RUN
RUN
1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[Active Halt Enabled]
FETCH
VECTOR
ATCSR
OVFIE
bit
LTCSR
TBIE bit
ATCSR ATCSR
CK1 bit CK0 bit
Meaning
Figure 26. ACTIVE-HALT Mode Flow-chart
0
0
0
1
x
x
0
1
x
1
x
x
1
x
0
0
x
1
x
1
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
OFF
0
ACTIVE-HALT
mode disabled
HALT INSTRUCTION
(Active Halt enabled)
I BIT
ACTIVE-HALT
mode enabled
N
9.4.1 ACTIVE-HALT MODE
RESET
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when active halt mode is enabled.
Y
N
INTERRUPT 3)
OSCILLATOR
PERIPHERALS 2)
CPU
Y
ON
OFF
ON
The MCU can exit ACTIVE-HALT mode on recep-
tion of a Lite Timer / AT Timer interrupt or a RE-
SET.
I BIT
X 4)
– When exiting ACTIVE-HALT mode by means of
a RESET, a 256 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation
by fetching the reset vector which woke it up (see
Figure 26).
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
– When exiting ACTIVE-HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 26).
I BITS
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the Lite Timer RTC and AT Timer interrupts
can exit the MCU from ACTIVE-HALT mode.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
Caution: As soon as ACTIVE-HALT is enabled,
executing a HALT instruction while the Watchdog
is active does not generate a RESET if the
WDGHALT bit is reset.
This means that the device cannot spend more
than a defined delay in this power saving mode.
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POWER SAVING MODES (Cont’d)
9.4.2 HALT MODE
Figure 28. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when active halt mode is disa-
bled.
HALT INSTRUCTION
(Active Halt disabled)
ENABLE
WATCHDOG
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 6, “Interrupt
Mapping,” on page 30) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
CPU cycle delay is used to stabilize the oscillator.
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up (see Figure 28).
0
DISABLE
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
N
RESET
Y
N
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I BIT
X 4)
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 112 for more details).
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
Figure 27. HALT Timing Overview
I BITS
256 CPU CYCLE
FETCH RESET VECTOR
OR SERVICE INTERRUPT
RUN
HALT
RUN
DELAY
Notes:
RESET
OR
INTERRUPT
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
HALT
INSTRUCTION
[Active Halt disabled]
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 6, “Interrupt Mapping,” on page 30 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after a delay of t
(see Figure 13).
STARTUP
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POWER SAVING MODES (Cont’d)
9.4.2.1 HALT Mode Recommendations
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
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10 I/O PORTS
10.1 INTRODUCTION
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it may mask the others.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
External interrupts are hardware interrupts. Fetch-
ing the corresponding interrupt vector automatical-
ly clears the request latch. Changing the sensitivity
of a particular external interrupt clears this pending
interrupt. This can be used to clear unwanted
pending interrupts.
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
Spurious interrupts
When enabling/disabling an external interrupt by
setting/resetting the related OR register bit, a spu-
rious interrupt is generated if the pin level is low
and its edge sensitivity includes falling/rising edge.
This is due to the edge detector input which is
switched to '1' when the external interrupt is disa-
bled by the OR register.
10.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
To avoid this unwanted interrupt, a "safe" edge
sensitivity (rising edge for enabling and falling
edge for disabling) has to be selected before
changing the OR register bit and configuring the
appropriate sensitivity again.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
Caution: In case a pin level change occurs during
these operations (asynchronous signal input), as
interrupts are generated according to the current
sensitivity, it is advised to disable all interrupts be-
fore and to reenable them after the complete pre-
vious sequence in order to avoid an external inter-
rupt occurring on the unwanted edge.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 29
This corresponds to the following steps:
1. To enable an external interrupt:
10.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
– set the interrupt mask with the SIM instruction
(in cases where a pin level change could oc-
cur)
– select rising edge
– enable the external interrupt through the OR
register
– select the desired sensitivity if different from
rising edge
– reset the interrupt mask with the RIM instruc-
tion (in cases where a pin level change could
occur)
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Note: Writing the DR register modifies the latch
value but does not affect the pin status.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
2. To disable an external interrupt:
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
– set the interrupt mask with the SIM instruction
SIM (in cases where a pin level change could
occur)
– select falling edge
– disable the external interrupt through the OR
register
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
– select rising edge
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– reset the interrupt mask with the RIM instruc-
tion (in cases where a pin level change could
occur)
10.2.2 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming under the following
conditions:
Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
– When the signal is coming from an on-chip pe-
ripheral, the I/O pin is automatically configured in
output mode (push-pull or open drain according
to the peripheral).
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
– When the signal is going to an on-chip peripher-
al, the I/O pin must be configured in floating input
mode. In this case, the pin state is also digitally
readable by addressing the DR register.
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
Notes:
V
SS
DD
– Input pull-up configuration can cause unexpect-
ed value at the input of the alternate peripheral
input.
1
V
Floating
Note: When switching from input to output mode,
the DR register has to be written first to drive the
correct level on the pin as soon as the port is con-
figured as an output.
– When an on-chip peripheral use a pin as input
and output, this pin has to be configured in input
floating mode.
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I/O PORTS (Cont’d)
Figure 29. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
FROM
OTHER
BITS
x
POLARITY
SELECTION
Table 9. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
On
Off
Output
Off
Open Drain (logic level)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
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I/O PORTS (Cont’d)
Table 10. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
V
DD
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
10.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
10.6 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 30 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
10.3 UNUSED I/O PINS
Unused I/O pins must be connected to fixed volt-
age levels. Refer to Section 13.8.
10.4 LOW POWER MODES
Figure 30. Interrupt I/O Port State Transitions
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
01
00
10
11
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
The I/O port register configurations are summa-
rised as follows.
Table 11. Port Configuration
Input (DDR=0)
Output (DDR=1)
OR = 0
Port
Pin name
PA7
OR = 0
floating
floating
floating
floating
floating
floating
floating
OR = 1
pull-up interrupt
pull-up
OR = 1
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
open drain
open drain
open drain
open drain
open drain
open drain
open drain
Port A
PA6:1
PA0
pull-up interrupt
pull-up
PB4
PB3
pull-up interrupt
pull-up
Port B
PB2:1
PB0
pull-up interrupt
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I/O PORTS (Cont’d)
Table 12. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
Reset Value
MSB
0
LSB
0
0000h
0001h
0002h
0003h
0004h
0005h
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PADDR
Reset Value
MSB
0
LSB
0
PAOR
Reset Value
MSB
0
LSB
0
PBDR
Reset Value
MSB
1
LSB
0
PBDDR
Reset Value
MSB
0
LSB
0
PBOR
Reset Value
MSB
0
LSB
0
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11 ON-CHIP PERIPHERALS
11.1 LITE TIMER (LT)
11.1.1 Introduction
■ Watchdog
– Enabled by hardware or software (configura-
The Lite Timer can be used for general-purpose
timing functions. It is based on a free-running 8-bit
upcounter with two software-selectable timebase
periods, an 8-bit input capture register and watch-
dog function.
ble by option byte)
– Optional reset on HALT instruction (configura-
ble by option byte)
– Automatically resets the device unless disable
bit is refreshed
– Software reset (Forced Watchdog reset)
– Watchdog reset status flag
11.1.2 Main Features
■ Realtime Clock
– 8-bit upcounter
– 1 ms or 2 ms timebase period (@ 8 MHz f
– Maskable timebase interrupt
■ Input Capture
)
OSC
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
Mode capability
Figure 31. Lite Timer Block Diagram
f
LTIMER
To 12-bit AT TImer
f
WDG
WATCHDOG
WATCHDOG RESET
f
/32
OSC
/2
1
0
Timebase
1 or 2 ms
(@ 8 MHz
8-bit UPCOUNTER
f
LTIMER
f
)
OSC
LTICR
8
8-bit
LTIC
INPUT CAPTURE
REGISTER
LTCSR
WDG
RF
ICIE
7
ICF
TB
TBIE
TBF
WDGE WDGD
0
LTTB INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
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LITE TIMER (Cont’d)
11.1.3 Functional Description
watchdog reset, first watchdog has to be activated
by setting the WDGE bit and then the WDGRF bit
has to be set.
The value of the 8-bit counter cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of f
/32. A
The WDGRF bit also acts as a flag, indicating that
the Watchdog was the source of the reset. It is au-
tomatically cleared after it has been read.
OSC
counter overflow event occurs when the counter
rolls over from F9h to 00h. If f = 8 MHz, then
OSC
the time period between two counter overflow
events is 1 ms. This period can be doubled by set-
ting the TB bit in the LTCSR register.
Caution: When the WDGRF bit is set, software
must clear it, otherwise the next time the watchdog
is enabled (by hardware or software), the micro-
controller will be immediately reset.
When the timer overflows, the TBF bit is set by
hardware and an interrupt request is generated if
the TBIE is set. The TBF bit is cleared by software
reading the LTCSR register.
Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGE bit in
the LTCSR is not used.
11.1.3.1 Watchdog
The watchdog is enabled using the WDGE bit.
The normal Watchdog timeout is 2ms (@ = 8 MHz
OSC
Refer to the Option Byte description in the "device
configuration and ordering information" section.
f
), after which it then generates a reset.
Using Halt Mode with the Watchdog (option)
To prevent this watchdog reset occuring, software
must set the WDGD bit. The WDGD bit is cleared
If the Watchdog reset on HALT option is not se-
lected by option byte, the Halt mode can be used
when the watchdog is enabled.
by hardware after t
. This means that software
WDG
must write to the WDGD bit at regular intervals to
prevent a watchdog reset occurring. Refer to Fig-
ure 32.
In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the Lite Timer
stops counting and is no longer able to generate a
Watchdog reset until the microcontroller receives
an external interrupt or a reset.
If the watchdog is not enabled immediately after
reset, the first watchdog timeout will be shorter
than 2ms, because this period is counted starting
from reset. Moreover, if a 2ms period has already
elapsed after the last MCU reset, the watchdog re-
set will take place as soon as the WDGE bit is set.
For these reasons, it is recommended to enable
the Watchdog immediately after reset or else to
set the WDGD bit before the WGDE bit so a
watchdog reset will not occur for at least 2ms.
If an external interrupt is received, the WDG re-
starts counting after 256 CPU clocks. If a reset is
generated, the Watchdog is disabled (reset state).
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
A Watchdog reset can be forced at any time by
setting the WDGRF bit. To generate a forced
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LITE TIMER (Cont’d)
Figure 32. Watchdog Timing Diagram
HARDWARE CLEARS
WDGD BIT
t
WDG
(2ms @ 8 MHz f
)
OSC
f
WDG
WDGD BIT
INTERNAL
WATCHDOG
RESET
SOFTWARE SETS
WDGD BIT
WATCHDOG RESET
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LITE TIMER (Cont’d)
Input Capture
11.1.5 Interrupts
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the LTIC pin. When an input capture
occurs, the ICF bit is set and the LTICR register
contains the value of the free-running upcounter.
An interrupt is generated if the ICIE bit is set. The
ICF bit is cleared by reading the LTICR register.
Exit
from
Active-
Halt
Enable
Control from from
Bit
Exit Exit
Interrupt Event
Event
Flag
Wait Halt
Timebase
Event
TBF
ICF
TBIE
ICIE
Yes
No
Yes
No
IC Event
The LTICR is a read only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
Note: The TBF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
11.1.4 Low Power Modes
Timebase and IC events generate an interrupt if
the enable bit is set in the LTCSR register and the
interrupt mask in the CC register is reset (RIM in-
struction).
Mode
Description
No effect on Lite timer
SLOW
(this peripheral is driven directly by
f
/32)
OSC
WAIT
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
ACTIVE HALT
HALT
Figure 33. Input Capture Timing Diagram
4µs
(@ 8 MHz f
)
OSC
f
CPU
f
/32
OSC
CLEARED
BY S/W
READING
LTIC REGISTER
8-bit COUNTER
LTIC PIN
01h
02h
03h
04h
05h
06h
07h
ICF FLAG
07h
LTICR REGISTER
xxh
04h
t
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LITE TIMER (Cont’d)
11.1.6 Register Description
0: No counter overflow
1: A counter overflow has occurred
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 2 = WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to
force a watchdog reset. It is set by hardware when
a watchdog reset occurs and cleared by hardware
or by software. It is cleared by hardware only when
an LVD reset occurs. It can be cleared by software
after a read access to the LTCSR register.
0: No watchdog reset occurred.
7
0
ICIE
ICF
TB
TBIE
TBF WDGR WDGE WDGD
Bit 7 = ICIE Interrupt Enable
1: Force a watchdog reset (write), or, a watchdog
reset occurred (read).
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
Bit 6 = ICF Input Capture Flag
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
1: Watchdog enabled
Bit 0 = WDGD Watchdog Reset Delay
0: No input capture
1: An input capture has occurred
This bit is set by software. It is cleared by hard-
ware at the end of each t
period.
WDG
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
0: Watchdog reset not delayed
1: Watchdog reset delayed
LITE TIMER INPUT CAPTURE REGISTER
Bit 5 = TB Timebase period selection
(LTICR)
This bit is set and cleared by software.
Read only
Reset Value: 0000 0000 (00h)
0: Timebase period = t
1: Timebase period = t
MHz)
* 8000 (1ms @ 8 MHz)
* 16000 (2ms @ 8
OSC
OSC
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bit 4 = TBIE Timebase Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
Bit 3 = TBF Timebase Interrupt Flag
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
Table 13. Lite Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
LTCSR
Reset Value
ICIE
0
ICF
x
TB
0
TBIE
0
TBF
0
WDGRF
0
WDGE
0
WDGD
0
0B
0C
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
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11.2 12-BIT AUTORELOAD TIMER (AT)
11.2.1 Introduction
■ PWM signal generator
■ Frequency range 2KHz-4MHz (@ 8 MHz f
– Programmable duty-cycle
– Polarity control
– Maskable Compare interrupt
■ Output Compare Function
)
CPU
The 12-bit Autoreload Timer can be used for gen-
eral-purpose timing functions. It is based on a free-
running 12-bit upcounter with a PWM output chan-
nel.
11.2.2 Main Features
■ 12-bit upcounter with 12-bit autoreload register
(ATR)
■ Maskable overflow interrupt
Figure 34. Block Diagram
OVF INTERRUPT
REQUEST
ATCSR
7
0
0
0
0
CK1 CK0 OVF OVFIECMPIE
CMP INTERRUPT
REQUEST
CMPF0
f
LTIMER
(1 ms timebase
@ 8MHz)
f
COUNTER
12-BIT UPCOUNTER
Update on OVF Event
CNTR
ATR
f
CPU
12-BIT AUTORELOAD VALUE
OE0 bit
DCR0L
DCR0H
CMPF0 bit
OE0 bit
OP0 bit
Preload
Preload
0
1
POL-
ARITY
COMP-
PARE
f
PWM
PWM0
on OVF Event
IF OE0=1
12-BIT DUTY CYCLE VALUE (shadow)
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12-BIT AUTORELOAD TIMER (Cont’d)
11.2.3 Functional Description
PWM Mode
When a upcounter overflow occurs (OVF event),
the ATR value is loaded in the upcounter, the
preloaded Duty cycle value is transferred to the
Duty Cycle register and the PWM0 signal is set to
a high level. When the upcounter matches the
DCRx value the PWM0 signals is set to a low level.
To obtain a signal on the PWM0 pin, the contents
of the DCR0 register must be greater than the con-
tents of the ATR register.
This mode allows a Pulse Width Modulated sig-
nals to be generated on the PWM0 output pin with
minimum core processing overhead. The PWM0
output signal can be enabled or disabled using the
OE0 bit in the PWMCR register. When this bit is
set the PWM I/O pin is configured as output push-
pull alternate function.
The polarity bit can be used to invert the output
signal.
Note: CMPF0 is available in PWM mode (see
PWM0CSR description on page 57).
The maximum available resolution for the PWM0
duty cycle is:
PWM Frequency and Duty Cycle
The PWM signal frequency (f
) is controlled by
PWM
Resolution = 1 / (4096 - ATR)
the counter period and the ATR register value.
Note: To get the maximum resolution (1/4096), the
ATR register must be 0. With this maximum reso-
lution and assuming that DCR=ATR, a 0% or
100% duty cycle can be obtained by changing the
polarity .
f
= f / (4096 - ATR)
PWM
COUNTER
Following the above formula, if f
maximum value of f
value = 4094), and the minimum value is 2 kHz
(ATR register value = 0).
is 8 MHz, the
CPU
is 4 Mhz (ATR register
PWM
Caution: As soon as the DCR0H is written, the
compare function is disabled and will start only
when the DCR0L value is written. If the DCR0H
write occurs just before the compare event, the
signal on the PWM output may not be set to a low
level. In this case, the DCRx register should be up-
dated just after an OVF event. If the DCR and ATR
values are close, then the DCRx register shouldbe
updated just before an OVF event, in order not to
miss a compare event and to have the right signal
applied on the PWM output.
Note: The maximum value of ATR is 4094 be-
cause it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the
DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution
below.
Figure 35. PWM Function
4095
DUTY CYCLE
REGISTER
(DCR0)
AUTO-RELOAD
REGISTER
(ATR)
000
t
WITH OE0=1
AND OP0=0
WITH OE0=1
AND OP0=1
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12-BIT AUTORELOAD TIMER (Cont’d)
Figure 36. PWM Signal Example
f
COUNTER
ATR= FFDh
FFFh
COUNTER
FFDh
FFEh
FFDh
FFEh
FFFh
FFDh
FFEh
DCR0=FFEh
t
Output Compare Mode
The compare between DCRx or the shadow regis-
ter and the timer counter is locked until DCR0L is
written.
To use this function, the OE bit must be 0, other-
wise the compare is done with the shadow register
instead of the DCRx register. Software must then
write a 12-bit value in the DCR0H and DCR0L reg-
isters. This value will be loaded immediately (with-
out waiting for an OVF event).
11.2.4 Low Power Modes
Mode
Description
The input frequency is divided
by 32
SLOW
The DCR0H must be written first, the output com-
pare function starts only when the DCR0L value is
written.
WAIT
No effect on AT timer
AT timer halted except if CK0=1,
CK1=0 and OVFIE=1
AT timer halted
ACTIVE-HALT
HALT
When the 12-bit upcounter (CNTR) reaches the
value stored in the DCR0H and DCR0L registers,
the CMPF0 bit in the PWM0CSR register is set
and an interrupt request is generated if the CMPIE
bit is set.
11.2.5 Interrupts
Note: The output compare function is only availa-
ble for DCRx values other than 0 (reset value).
Exit
Enable Exit Exit
from
Interrupt
Event
Event
Flag
Control from from
1)
Active-
Halt
Bit
Wait Halt
Caution: At each OVF event, the DCRx value is
written in a shadow register, even if the DCR0L
value has not yet been written (in this case, the
shadow register will contain the new DCR0H value
and the old DCR0L value), then:
Overflow
Event
2)
OVF OVFIE Yes No
Yes
CMP Event CMPFx CMPIE Yes No
No
Notes:
– If OE=1 (PWM mode): the compare is done be-
tween the timer counter and the shadow register
(and not DCRx)
1. The interrupt events are connected to separate
interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in
the ATCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
– if OE=0 (OCMP mode): the compare is done be-
tween the timer counter and DCRx. There is no
PWM signal.
2. only if CK0=1and CK1=0
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12-BIT AUTORELOAD TIMER (Cont’d)
11.2.6 Register Description
hardware after a reset. It allows to mask the inter-
rupt generation when CMPF bit is set.
0: CMPF interrupt disabled
TIMER CONTROL STATUS REGISTER (ATC-
SR)
Read / Write
1: CMPF interrupt enabled
Reset Value: 0000 0000 (00h)
COUNTER REGISTER HIGH (CNTRH)
Read only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
CK1
CK0
OVF OVFIE CMPIE
15
8
Bit 7:5 = Reserved, must be kept cleared.
0
0
0
0
CN11 CN10 CN9
CN8
Bit 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
COUNTER REGISTER LOW (CNTRL)
Read only
Reset Value: 0000 0000 (00h)
Counter Clock Selection
CK1 CK0
7
0
OFF
0
0
1
1
0
1
0
1
f
(1 ms timebase @ 8 MHz)
LTIMER
CN7
CN6
CN5
CN4
CN3
CN2
CN1
CN0
f
CPU
Reserved
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter is incre-
mented continuously as soon as a counter clock is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. The CNTRH register can be in-
cremented between the two reads, and in order to
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR register. It indicates the
transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Caution:
be accurate when f
=f
, the software
TIMER CPU
When set, the OVF bit stays high for 1 f
COUNTER
should take this into account when CNTRL and
CNTRH are read. If CNTRL is close to its highest
value, CNTRH could be incremented before it is
read.
cycle, (up to 1ms depending on the clock selec-
tion).
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR register.
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and clear by
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12-BIT AUTORELOAD TIMER (Cont’d)
AUTO RELOAD REGISTER (ATRH)
Read / Write
Reset Value: 0000 0000 (00h)
PWM0 DUTY CYCLE REGISTER LOW (DCR0L)
Read / Write
Reset Value: 0000 0000 (00h)
15
8
7
0
0
0
0
0
ATR11 ATR10 ATR9 ATR8
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
AUTO RELOAD REGISTER (ATRL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. The high
register must be written first.
7
0
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
In PWM mode (OE0=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWM0 output signal (see Figure 35). In Output
Compare mode, (OE0=0 in the PWMCR register)
they define the value to be compared with the 12-
bit upcounter value.
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = ATR[11:0] Autoreload Register.
This is a 12-bit register which is written by soft-
ware. The ATR register value is automatically
loaded into the upcounter when an overflow oc-
curs. The register value is used to set the PWM
frequency.
PWM0
CONTROL/STATUS
REGISTER
(PWM0CSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
PWM0 DUTY CYCLE REGISTER HIGH (DCR0H)
Read / Write
Reset Value: 0000 0000 (00h)
0
0
0
0
0
0
OP0 CMPF0
15
8
Bit 7:2= Reserved, must be kept cleared.
0
0
0
0
DCR11 DCR10 DCR9 DCR8
Bit 1 = OP0 PWM0 Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
Bit 0 = CMPF0 PWM0 Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWM0CSR register. It indicates
that the upcounter value matches the DCR0 regis-
ter value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
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12-BIT AUTORELOAD TIMER (Cont’d)
PWM OUTPUT CONTROL REGISTER (PWMCR)
Read/Write
Bits 7:1 = Reserved, must be kept cleared.
Reset Value: 0000 0000 (00h)
Bit 0 = OE0 PWM0 Output enable.
This bit is set and cleared by software.
0: PWM0 output Alternate Function disabled (I/O
pin free for general purpose I/O)
7
0
0
0
0
0
0
0
0
OE0
1: PWM0 output enabled
Table 14. Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ATCSR
Reset Value
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
0D
0E
0F
10
11
12
13
17
18
0
0
0
0
0
0
CNTRH
Reset Value
CN11
0
CN10
0
CN9
0
CN8
0
0
CNTRL
Reset Value
CN7
0
CN6
0
CN5
0
CN4
0
CN3
0
CN2
0
CN1
0
CN0
0
ATRH
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0
0
0
0
ATRL
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
PWMCR
Reset Value
OE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM0CSR
Reset Value
OP
0
CMPF0
0
DCR0H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
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11.3 SERIAL PERIPHERAL INTERFACE (SPI)
11.3.1 Introduction
software overhead for clearing status flags and to
initiate the next transmission sequence.
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
11.3.3 General Description
Figure 37 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
11.3.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ Six master mode frequencies (f
/4 max.)
CPU
■ f
/2 max. slave mode frequency (see note)
CPU
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
Figure 37. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.3.1 Functional Description
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 38.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 41) but master and slave
must be programmed with the same timing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 38. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 40)
There are two cases depending on the data/clock
timing relationship (see Figure 39):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.3.5.3).
– SS internal must be held high continuously
Figure 39. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 40. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.3.3 Master Mode Operation
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
11.3.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
How to operate the SPI in master mode
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 41).
To operate the SPI in master mode, perform the
following steps in order:
Note: The slave must have the same CPOL
1. Write to the SPICR register:
and CPHA settings as the master.
– Select the clock frequency by configuring the
– Manage the SS pin as described in Section
11.3.3.2 and Figure 39. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
41 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
11.3.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high.
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
Important note: if the SPICSR register is not writ-
ten first, the SPICR register setting (MSTR bit)
may be not taken into account.
When data transfer is complete:
– The SPIF bit is set by hardware
The transmit sequence begins when software
writes a byte in the SPIDR register.
11.3.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read to the SPIDR register.
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 11.3.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4 Clock Phase and Clock Polarity
Figure 41, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 41).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 41. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5 Error Flags
not cleared the SPIF bit issued from the previously
transmitted byte.
11.3.5.1 Master Mode Fault (MODF)
When an Overrun occurs:
Master mode fault occurs when the master device
has its SS pin pulled low.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
When a Master mode fault occurs:
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The OVR bit is cleared by reading the SPICSR
register.
– The MSTR bit is reset, thus forcing the device
into slave mode.
11.3.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
MODF bit is set.
2. A write to the SPICR register.
Write collisions can occur both in master and slave
mode. See also Section 11.3.3.2 Slave Select
Management.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
11.3.5.2 Overrun Condition (OVR)
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
Clearing the WCOL bit is done through a software
sequence (see Figure 42).
Figure 42. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF =0
WCOL=0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
RESULT
2nd Step
Read SPIDR
WCOL=0
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5.4 Single Master Systems
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 43).
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 43. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
MCU
SCK
Slave
MCU
Slave
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.6 Low Power Modes
SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see Section
11.3.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the MCU is woken up by
an interrupt with “exit from HALT mode” ca-
pability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
11.3.7 Interrupts
HALT
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of Trans-
fer Event
SPIF
Yes
Yes
Master Mode Fault
Event
SPIE
MODF
OVR
Yes
Yes
No
No
11.3.6.1 Using the SPI to wakeup the MCU from
Halt mode
Overrun Error
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
fers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.3.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable.
Table 15. SPI Master mode SCK Frequency
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 15 SPI Master
mode SCK Frequency.
Serial Clock
SPR2 SPR1 SPR0
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
0: Divider by 2 enabled
1: Divider by 2 disabled
f
f
f
/16
/32
/64
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
f
/128
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.3.5.1 Master Mode Fault
(MODF)).
CPU
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
7
0
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
SPIF
WCOL OVR MODF
-
SOD SSM SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
Bit 1 = SSM SS Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
11.3.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 42).
0: No write collision occurred
1: A write collision has been detected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 11.3.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
D7
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
1: Overrun error detected
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.3.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICR register. This
bit is cleared by a software sequence (An access
to the SPICSR register while MODF=1 followed by
a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
0: No master mode fault detected
1: A fault in master mode has been detected
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 37).
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 16. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
31
32
33
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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11.4 8-BIT A/D CONVERTER (ADC)
11.4.1 Introduction
11.4.3 Functional Description
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 5 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 5 different sources.
11.4.3.1 Analog Power Supply
The block diagram is shown in Figure 44.
V
and V are the high and low level reference
SS
DD
voltage pins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
For more details, refer to the Electrical character-
istics section.
11.4.3.2 Input Voltage Amplifier
11.4.2 Main Features
The input voltage can be amplified by a factor of 8
by enabling the AMPSEL bit in the ADAMP regis-
ter.
■ 8-bit conversion
■ Up to 5 channels with multiplexed input
■ Linear successive approximation
■ Dual input range
When the amplifier is enabled, the input range is
0V to 250 mV.
– 0 to V or
DD
For example, if V = 5V, then the ADC can con-
DD
– 0V to 250mV
vert voltages in the range 0V to 250mV with an
ideal resolution of 2.4mV (equivalent to 11-bit res-
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
olution with reference to a V to V range).
SS
DD
For more details, refer to the Electrical character-
istics section.
■ Fixed gain operational amplifier (x8) (not
Note: The amplifier is switched on by the ADON
bit in the ADCCSR register, so no additional start-
up time is required when the amplifier is selected
by the AMPSEL bit.
available on ST7LITES5 devices)
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ST7LITE0xY0, ST7LITESxY0
Figure 44. ADC Block Diagram
f
f
ADC
DIV 4
CPU
1
0
DIV 2
0
1
(ADCAMP Register)
0
SLOW
bit
7
EOC SPEEDADON
0
0
CH2 CH1 CH0
ADCCSR
3
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
x 1 or
x 8
ANALOG
MUX
C
ADC
AINx
AMPSEL bit
(ADCAMP Register)
ADCDR
D7 D6 D5 D4 D3 D2 D1 D0
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8-BIT A/D CONVERTER (ADC) (Cont’d)
11.4.3.3 Digital A/D Conversion Result
ADC Configuration
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
If the input voltage (V ) is greater than or equal
AIN
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
scale) without overflow indication.
In the CSR register:
– Select the CH[2:0] bits to assign the analog
channel to be converted.
If input voltage (V ) is lower than or equal to
AIN
V
(low-level voltage reference) then the con-
SSA
ADC Conversion
version result in the DR register is 00h.
In the CSR register:
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
R
is the maximum recommended impedance
When a conversion is complete
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
– The EOC bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
11.4.3.4 A/D Conversion Phases
A write to the ADCCSR register (with ADON set)
aborts the current conversion, resets the EOC bit
and starts a new conversion.
The A/D conversion is based on two conversion
phases as shown in Figure 45:
■ Sample capacitor loading [duration: t
]
SAMPLE
Figure 45. ADC Conversion Timings
During this phase, the V
input voltage to be
AIN
measured is loaded into the C
capacitor.
sample
ADC
ADON
t
CONV
ADCCSR WRITE
OPERATION
■ A/D conversion [duration: t
]
HOLD
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
t
HOLD
HOLD
CONTROL
and the C
sample capacitor is disconnected
ADC
from the analog input pin to get the optimum
analog to digital conversion accuracy.
t
SAMPLE
EOC BIT SET
■ The total conversion time:
t
t
+ t
CONV = SAMPLE HOLD
11.4.4 Low Power Modes
While the ADC is on, these two phases are contin-
uously repeated.
Mode
WAIT
Description
No effect on A/D Converter
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilization time before ac-
curate conversions can be performed.
HALT
11.4.3.5 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 11.4.6 for the bit defini-
tions and to Figure 45 for the timings.
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
11.4.5 Interrupts
None
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8-BIT A/D CONVERTER (ADC) (Cont’d)
11.4.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write
DATA REGISTER (ADCDR)
Read Only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
EOC SPEED ADON
0
0
CH2
CH1
CH0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = EOC Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
Bits 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
0: Conversion is not complete
Note: Reading this register reset the EOC flag.
1: Conversion can be read from the DR register
AMPLIFIER CONTROL REGISTER (ADCAMP)
Read/Write
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Reset Value: 0000 0000 (00h)
7
0
0
0
Bit 5 = ADON A/D Converter and Amplifier On
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
AMP-
SEL
0
0
0
SLOW
0
Bit 7:4 = Reserved. Forced by hardware to 0.
Note: Amplifier not available on ST7LITES5
Bit 3 = SLOW Slow mode
devices
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
Bits 4:3 = Reserved. must always be cleared.
f
SLOW SPEED
ADC
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
f
/2
0
0
1
0
1
x
CPU
f
CPU
f
/4
CPU
1
Channel Pin
CH2
CH1
CH0
Bit 2 = AMPSEL Amplifier Selection Bit
AIN0
AIN1
AIN2
AIN3
AIN4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
This bit is set and cleared by software. For
ST7LITES5 devices, this bit must be kept at its re-
set value (0).
0: Amplifier is not selected
1: Amplifier is selected
Note: When AMPSEL=1 it is mandatory that f
ADC
Notes:
be less than or equal to 2 MHz.
1. The number of pins AND the channel selection
varies according to the device. Refer to the device
pinout.
Bits 1:0 = Reserved. Forced by hardware to 0.
2. A write to the ADCCSR register (with ADON set)
aborts the current conversion, resets the EOC bit
and starts a new conversion.
Note: If ADC settings are changed by writing the
ADCAMP register while the ADC is running, a
dummy conversion is needed before obtaining re-
sults with the new settings.
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ST7LITE0xY0, ST7LITESxY0
Table 17. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
CH2
0
CH1
0
CH0
0
34h
35h
0
0
ADCDR
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
SLOW
0
AMPSEL
0
ADCAMP
Reset Value
36h
0
0
0
0
0
0
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ST7LITE0xY0, ST7LITESxY0
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdi-
vided in two submodes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in seven main
groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
Immediate
Direct
ld A,#$55
ld A,$55
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Indexed
Indirect
ld A,($55,X)
ld A,([$55],X)
jrne loop
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 18. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Destination/
Source
Length
(Bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed ld A,($10,X)
Indexed ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
0000..FFFF
00..1FE
Indirect Indexed ld A,([$10],X)
Indirect Indexed ld A,([$10.w],X) 0000..FFFF
1)
1)
Direct
jrne loop
PC-128/PC+127
PC-128/PC+127
00..FF
Indirect
Direct
jrne [$10]
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip 00..FF
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
Note:
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (cont’d)
12.1.1 Inherent
12.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (Short)
NOP
The address is a byte, thus requires only 1 byte af-
ter the opcode, but only allows 00 - FF addressing
space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (Long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Subroutine Return
Interrupt Subroutine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
12.1.4 Indexed (No Offset, Short, Long)
SIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
RIM
SCF
The indirect addressing mode consists of three
submodes:
RCF
Reset Carry Flag
Reset Stack Pointer
Load
RSP
Indexed (No Offset)
LD
There is no offset (no extra byte after the opcode),
and allows 00 - FF addressing space.
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only 1 byte after
the opcode and allows 00 - 1FE addressing space.
CPL, NEG
MUL
Indexed (Long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
12.1.5 Indirect (Short, Long)
SWAP
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
12.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
The pointer address follows the opcode. The indi-
rect addressing mode consists of two submodes:
Indirect (Short)
Immediate Instruction
Function
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
LD
Load
CP
Compare
BCP
Bit Compare
Indirect (Long)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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ST7LITE0xY0, ST7LITESxY0
ST7 ADDRESSING MODES (cont’d)
12.1.6 Indirect Indexed (Short, Long)
12.1.7 Relative Mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
Indirect Instructions
JRxx
Conditional Jump
Call Relative
The indirect indexed addressing mode consists of
two submodes:
CALLR
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 19. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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ST7LITE0xY0, ST7LITESxY0
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a prebyte
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The instructions are described with 1 to 4 bytes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PIX 92 Replace an instruction using direct, di-
rect bit or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the de-
vice against unexpected behavior, a system of ille-
gal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
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INSTRUCTION GROUPS (cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
A
M
M
M
M
Addition
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
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ST7LITE0xY0, ST7LITESxY0
INSTRUCTION GROUPS (cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
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13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
13.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 47.
13.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 47. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean 3Σ).
IN
13.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
DD
DD
voltage range), V =3.3V (for the 3V≤V ≤3.6V
voltage range) and
V
=2.7V (for the
DD
2.4V≤V ≤3V voltage range). They are given only
DD
as design guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 46.
Figure 46. Pin loading conditions
ST7 PIN
C
L
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13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
- V
Ratings
Maximum value
7.0
Unit
V
Supply voltage
DD
SS
V
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
IN
ESD(HBM)
see section 13.7.2 on page 93
V
Electrostatic discharge voltage (Human Body Model)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
75
150
20
40
- 25
5
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on RESET pin
I
IO
mA
2) & 4)
2)
I
INJ(PIN)
5)
Injected current on PB1 pin
+5
5
6)
Injected current on any other pin
6)
ΣI
Total injected current (sum of all I/O and control pins)
20
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
T
Maximum junction temperature (see Section 14.2 THERMAL CHARACTERISTICS)
J
Notes:
1. Directly connecting the I/O pins to V or V could damage the device if an unexpected change of the I/O configura-
DD
SS
tion occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be
done through a pull-up or pull-down resistor (typical: 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V
DD
or V according to their reset configuration. For reset pin, please refer to Figure 80.
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
INJ(PIN)
while a negative injection is induced by V <V
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
.
SS
IN
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. No negative current injection allowed on PB1 pin.
6. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
mum current injection on four I/O port pins of the device.
maxi-
INJ(PIN)
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13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions: Suffix 6 Devices
T = -40 to +85°C unless otherwise specified.
A
Symbol
Parameter
Supply voltage
Conditions
= 8 MHz. max.,
Min
2.4
3.3
Max
5.5
Unit
f
f
OSC
V
V
DD
= 16 MHz. max.
5.5
OSC
3.3V≤ V ≤5.5V
up to 16
External clock frequency on
CLKIN pin
DD
f
MHz
CLKIN
2.4V≤V <3.3V
up to 8
DD
Figure 48. f
Maximum Operating Frequency Versus VDD Supply Voltage
CLKIN
FUNCTIONALITY
GUARANTEED
IN THIS AREA
f
[MHz]
CLKIN
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
1
0
SUPPLY VOLTAGE [V]
5.5
2.7
2.0
2.4
3.3
3.5
4.0
4.5
5.0
Note: For further information on clock management and f
on page 24
description, refer to Figure 14 in section 7
CLKIN
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13.3.2 Operating Conditions with Low Voltage Detector (LVD)
T = -40 to 85°C, unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
Unit
1)
4.00
3.40
2.65
4.25
3.60
2.90
4.50
3.80
3.15
Reset release threshold
1)
1)
V
IT+
(LVD)
(V rise)
DD
V
1)
High Threshold
Med. Threshold
Low Threshold
3.80
3.20
2.40
4.05
3.40
2.70
4.30
3.65
2.90
Reset generation threshold
1)
1)
V
V
IT-
(LVD)
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
IT-
(LVD)
200
mV
µs/V
ns
hys
IT+
(LVD)
2)
Vt
V
rise time rate
DD
20
20000
150
POR
t
I
Filtered glitch delay on V
DD
Not detected by the LVD
g(VDD)
DD(LVD
)
LVD/AVD current consumption
220
µA
Notes:
1. Not tested in production.
2. Not tested in production. The V rise time rate condition is needed to ensure a correct device power-on and LVD reset.
DD
When the V slope is outside these values, the LVD may not ensure a proper reset of the MCU.
DD
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
T = -40 to 85°C, unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
Unit
4.40
3.90
3.20
4.70
4.10
3.40
5.00
4.30
3.60
1=>0 AVDF flag toggle threshold
V
IT+
(AVD)
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
4.30
3.70
2.90
4.60
3.90
3.20
4.90
4.10
3.40
0=>1 AVDF flag toggle threshold
V
V
IT-
(AVD)
(V fall)
DD
AVD voltage threshold hysteresis
V
-V
IT-
(AVD)
150
mV
V
hys
IT+
(AVD)
fall
Voltage drop between AVD flag set
and LVD reset activation
∆V
V
0.45
IT-
DD
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13.3.4 Internal RC Oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol
Parameter
Internal RC Oscillator operating voltage
x4 PLL operating voltage
Conditions Min
Typ
Max
5.5
Unit
V
2.4
2.4
3.3
DD(RC)
V
V
3.3
V
DD(x4PLL)
DD(x8PLL)
x8 PLL operating voltage
5.5
PLL input clock (f
cycles
)
PLL
t
PLL Startup time
60
STARTUP
The RC oscillator and PLL characteristics are temperature-dependent and are grouped in two tables.
13.3.4.1 Devices with “6” order code suffix (tested for T = -40 to +85°C) @ V = 4.5 to 5.5V
A
DD
Typ
Symbol
Parameter
Conditions
RCCR = FF (reset value), T =25°C, V =5V
Min
Max
Unit
760
Internal RC oscillator fre-
quency
A
DD
1)
f
kHz
RC
2 )
RCCR = RCCR0 ,T =25°C, V =5V
1000
A
DD
T =25°C,V =4.5 to 5.5V
-1
-5
+1
%
%
%
A
DD
Accuracy of Internal RC
oscillator with
RCCR=RCCR0
ACC
T =-40 to +85°C, V =5V
+2
RC
A
DD
2)
3)
3)
T =0 to +85°C, V =4.5 to 5.5V
-2
+2
A
DD
RC oscillator current con-
sumption
3)
I
T =25°C,V =5V
970
µA
DD(RC)
A
DD
2)
t
f
t
t
RC oscillator setup time T =25°C,V =5V
10
µs
MHz
ms
ms
%
su(RC)
A
DD
3)
x8 PLL input clock
1
PLL
5)
PLL Lock time
2
4
LOCK
STAB
5)
PLL Stabilization time
x8 PLL Accuracy
PLL jitter period
4)
f
f
f
= 1MHz@T =25°C, V =4.5 to 5.5V
0.1
RC
RC
RC
A
DD
ACC
PLL
4)
= 1MHz@T =-40 to +85°C, V =5V
0.1
%
A
DD
6)
t
= 1MHz
8
kHz
%
w(JIT)
6)
JIT
PLL jitter (∆f
/f )
CPU CPU
1
PLL
3)
I
PLL current consumption T =25°C
600
µA
DD(PLL)
A
Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device.
DD
SS
2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24
3. Data based on characterization results, not tested in production
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy
PLL
STAB
5. After the LOCKED bit is set ACC
6. Guaranteed by design.
is max. 10% until t
has elapsed. See Figure 13 on page 25.
PLL
STAB
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ST7LITE0xY0, ST7LITESxY0
OPERATING CONDITIONS (Cont’d)
13.3.4.2 Devices with ‘”6” order code suffix (tested for T = -40 to +85°C) @ V = 2.7 to 3.3V
A
DD
Symbol
Parameter
Conditions
RCCR = FF (reset value), T =25°C, V = 3.0V
Min
Typ
560
700
Max
Unit
Internal RC oscillator fre-
quency
A
DD
1)
f
kHz
RC
2)
RCCR=RCCR1 ,T =25°C, V = 3V
A
DD
T =25°C,V =3V
-2
+2
+25
15
%
%
%
A
DD
Accuracy of Internal RC
ACC
oscillator when calibrated T =25°C,V =2.7 to 3.3V
-25
-15
RC
A
DD
2)3)
with RCCR=RCCR1
T =-40 to +85°C, V =3V
A
DD
RC oscillator current con-
sumption
3)
I
T =25°C,V =3V
700
µA
DD(RC)
A
DD
2)
t
f
t
t
RC oscillator setup time T =25°C,V =3V
10
µs
MHz
ms
ms
%
su(RC)
A
DD
3)
x4 PLL input clock
0.7
2
PLL
5)
PLL Lock time
LOCK
STAB
5)
PLL Stabilization time
x4 PLL Accuracy
PLL jitter period
4
4)
4)
f
f
f
= 1MHz@T =25°C, V =2.7 to 3.3V
0.1
0.1
RC
RC
RC
A
DD
ACC
PLL
= 1MHz@T =40 to +85°C, V = 3V
%
A
DD
6)
t
= 1MHz
8
1
kHz
%
w(JIT)
6)
JIT
PLL jitter (∆f
/f
)
PLL
CPU CPU
3)
I
PLL current consumption T =25°C
190
µA
DD(PLL)
A
Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device.
DD
SS
2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24.
3. Data based on characterization results, not tested in production
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy
PLL
STAB
5. After the LOCKED bit is set ACC
6. Guaranteed by design.
is max. 10% until t
has elapsed. See Figure 13 on page 25.
PLL
STAB
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ST7LITE0xY0, ST7LITESxY0
OPERATING CONDITIONS (Cont’d)
Figure 49. RC Osc Freq vs V
@ T =25°C
Figure 51. Typical RC oscillator Accuracy vs
DD
A
(Calibrated with RCCR1: 3V @ 25°C)
temperature @ V =5V
DD
(Calibrated with RCCR0: 5V @ 25°C
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
2
(
)
*
1
0
(
)
*
-1
-2
-3
-4
(
)
*
-5
-45
0
25
85
125
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
Temperature (°C)
(
) tested in production
VDD (V)
*
Figure 50. RC Osc Freq vs V
DD
Figure 52. RC Osc Freq vs V and RCCR Value
DD
(Calibrated with RCCR0: 5V@ 25°C)
1.80
1.60
1.40
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45°
0°
1.00
0.80
0.60
0.40
0.20
0.00
rccr=00h
rccr=64h
rccr=80h
rccr=C0h
rccr=FFh
25°
90°
105°
130°
2.5
3
3.5
4
4.5
5
5.5
6
2.4 2.7
3
3.3 3.75
4
4.5
5
5.5
6
Vdd (V)
Vdd (V)
Figure 53. PLL ∆f
/f
versus time
CPU CPU
/f
∆f
CPU CPU
Max
0
t
Min
t
t
w(JIT)
w(JIT)
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ST7LITE0xY0, ST7LITESxY0
OPERATING CONDITIONS (Cont’d)
Figure 54. PLLx4 Output vs CLKIN frequency
Figure 55. PLLx8 Output vs CLKIN frequency
7.00
6.00
5.00
11.00
9.00
7.00
5.00
3.00
1.00
3.3
5.5
5
4.00
3
2.7
4.5
4
3.00
2.00
1.00
0.85
0.9
1
1.5
2
2.5
1
1.5
2
2.5
3
External Input Clock Frequency (MHz)
External Input Clock Frequency (MHz)
Note: f
= f
/2*PLL4
Note: f
= f
/2*PLL8
CLKIN
OSC
CLKIN
OSC
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ST7LITE0xY0, ST7LITESxY0
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 Supply Current
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
4.50
Max
7.00
Unit
1)
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
Supply current in SLOW WAIT mode
f
f
f
f
=8MHz
CPU
CPU
CPU
CPU
2)
1.75
0.75
0.65
0.50
TBD
5
2.70
1.13
1
=8MHz
mA
3)
4)
=250kHz
=250kHz
I
DD
10
-40°C≤T ≤+85°C
A
5)
TBD
100
Supply current in HALT mode
-40°C≤T ≤+105°C
µA
A
T = +85°C
A
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (CLKIN)
DD
SS
driven by external square wave, LVD disabled.
3. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
CPU
OSC DD
V
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with f
based on f
divided by 32. All I/O pins in input mode with a static value at
CPU
OSC
V
or V (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
DD
SS
5. All I/O pins in output mode with a static value at V (no load), LVD disabled. Data based on characterization results,
SS
tested in production at V max and f
max.
CPU
DD
Figure 56. Typical I in RUN vs. f
Figure 57. Typical I in SLOW vs. f
DD CPU
DD
CPU
8MHz
5.0
250kHz
125kHz
62.5kHz
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
4MHz
4.0
1MHz
3.0
2.0
1.0
0.0
2.4
2.7
3.7
4.5
5
5.5
2.4
2.7
3.7
4.5
5
5.5
Vdd (V)
Vdd (V)
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ST7LITE0xY0, ST7LITESxY0
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
Figure 58. Typical I in WAIT vs. f
Figure 60. Typical I vs. Temperature
DD
DD
CPU
at V = 5V and f
= 8MHz
DD
CPU
8MHz
2.0
4MHz
1.5
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
1MHz
1.0
0.5
0.0
RUN
WAIT
SLOW
2.4
2.7
3.7
4.5
5
5.5
SLOW WAIT
Vdd (V)
-45
25
90
130
Temperature (°C)
Figure 59. Typical I in SLOW-WAIT vs. f
DD
CPU
250kHz
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
125kHz
62.5kHz
2.4
2.7
3.7
4.5
5
5.5
Vdd (V)
13.4.2 On-chip peripherals
Symbol
Parameter
Conditions
Typ
150
250
50
Unit
f
f
f
f
=4MHz
V
=3.0V
CPU
CPU
CPU
CPU
DD
DD
DD
DD
DD
DD
1)
I
12-bit Auto-Reload Timer supply current
DD(AT)
=8MHz
=4MHz
=8MHz
V
V
V
V
V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
2)
I
SPI supply current
µA
DD(SPI)
300
780
1100
3)
I
ADC supply current when converting
f
=4MHz
DD(ADC)
ADC
1. Data based on a differential I measurement between reset configuration (timer stopped) and a timer running in PWM
DD
mode at f =8MHz.
cpu
2. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
3. Data based on a differential I measurement between reset configuration and continuous A/D conversions with am-
DD
plifier off.
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ST7LITE0xY0, ST7LITESxY0
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
13.5.1 General Timings
1)
2)
Symbol
Parameter
Conditions
Min
2
Typ
3
Max
12
Unit
tCPU
ns
t
Instruction cycle time
f
f
=8MHz
c(INST)
CPU
250
10
375
1500
22
3)
tCPU
µs
Interrupt reaction time
t
=8MHz
v(IT)
CPU
t
= ∆t
+ 10
c(INST)
1.25
2.75
v(IT)
13.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
0.7xV
Typ
Max
Unit
V
CLKIN input pin high level voltage
CLKIN input pin low level voltage
V
DD
CLKINH
DD
SS
V
V
V
0.3xV
CLKINL
DD
t
t
4)
w(CLKINH)
see Figure 61
CLKIN high or low time
15
w(CLKINL)
ns
t
t
4)
r(CLKIN)
CLKIN rise or fall time
15
1
f(CLKIN)
I
CLKIN Input leakage current
V
≤V ≤V
DD
µA
L
SS
IN
Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆t
ish the current instruction execution.
is the number of t
cycles needed to fin-
c(INST)
CPU
4. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 61. Typical Application with an External Clock Source
90%
VCLKINH
10%
VCLKINL
tfCLKIN)
tw(CLKINH)
tr(CLKIN)
tw(CLKINL)
fOSC
EXTERNAL
CLOCK SOURCE
IL
CLKIN
ST72XXX
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13.6 MEMORY CHARACTERISTICS
T = -40°C to 105°C, unless otherwise specified
A
13.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
13.6.2 FLASH Program Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2.4
5.5
10
V
Operating voltage for Flash write/erase
DD
prog
RET
2)
T =−40 to +105°C
5
Programming time for 1~32 bytes
ms
A
t
t
T =+25°C
0.24
0.48
Programming time for 1.5 kBytes
s
A
4)
3)
Data retention
T =+55°C
20
years
cycles
A
7)
N
Write erase cycles
T =+25°C
10K
RW
A
Read / Write / Erase
modes
= 8MHz, V = 5.5V
6)
2.6
mA
f
I
Supply current
CPU
DD
DD
No Read/No Write Mode
Power down mode / HALT
100
0.1
µA
µA
0
13.6.3 EEPROM Data Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Operating voltage for EEPROM
write/erase
2.4
5.5
10
V
t
V
DD
T =−40 to +105°C
5
Programming time for 1~32 bytes
ms
A
prog
4)
3)
t
Data retention
T =+55°C
20
years
cycles
ret
A
7)
N
Write erase cycles
T =+25°C
300K
RW
A
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the T decreases.
A
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
6. Guaranteed by Design. Not tested in production.
7. Design target value pending full product characterization.
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13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
13.7.1 Functional EMS (Electro Magnetic
Susceptibility)
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Based on a simple running application on the
product (toggling two -+LEDs through I/O ports),
the product is stressed by two electro magnetic
events until a failure occurs (indicated by the
LEDs).
Software recommendations:
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
■ FTB: A Burst of Fast Transient voltage (positive
– Critical Data corruption (control registers...)
Prequalification trials:
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
13.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
Level/
Symbol
Parameter
Conditions
Class
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
2B
FESD
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
V
=5V, T =+25°C, f =8MHz
DD
A
OSC
V
through 100pF on V and V pins to induce a func-
3B
FFTB
DD DD
conforms to IEC 1000-4-4
tional disturbance
13.7.2 EMI (Electromagnetic interference)
emission test is in line with the norm
SAE J 1752/3 which specifies the board and the
loading of each pin.
Based on a simple application running on the
product (toggling two LEDs through the I/O ports),
the product is monitored in terms of emission. This
Table 20: EMI emissions
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
=5V, T =+25°C,
SO16 package,
conforming to SAE J 1752/3
1/4MHz
1/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
8
14
32
28
4
V
DD
A
27
26
3.5
dBµV
S
Peak level
EMI
-
Note:
1. Data based on characterization results, not tested in production.
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ST7LITE0xY0, ST7LITESxY0
EMC CHARACTERISTICS (Cont’d)
13.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
13.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). This test conforms to the JESD22-
A114A standard.
Based on two different tests (ESD and LU) using
specific measurement methods, the product is
stressed in order to determine its performance in
terms of electrical sensitivity.
ESD absolute maximum ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
T =+25°C
conforming to JESD22-A114
Electro-static discharge voltage
(Human Body Model)
A
V
4000
V
ESD(HBM)
Notes:
1. Data based on characterization results, not tested in production.
13.7.3.2 Static Latch-Up
(applied to each input, output and configurable I/
O pin) are performed on each sample. These
test are compliant with the EIA/JESD 78 IC
latch-up standard.
■ LU: Two complementary static tests are
required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to
each power supply pin) and a current injection
Electrical Sensitivities
1)
Symbol
Parameter
Static latch-up class
Conditions
Class
T =+25°C
A
LU
II level A
conforming to JESD78A
Note:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
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ST7LITE0xY0, ST7LITESxY0
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Input low level voltage
Input high level voltage
Schmitt trigger voltage
Conditions
Min
Typ
Max
Unit
V
V
SS - 0.3
0.3xVDD
V
IL
V
0.7xVDD
VDD + 0.3
IH
V
400
400
mV
1)
hys
hysteresis
I
Input leakage current
V
SS≤V ≤V
DD
1
L
IN
µA
Static current consumption induced by
I
Floating input mode
2)
S
each floating input pin
V
V
=5V
=3V
50
120
160
5
250
V =V
SS
DD
DD
3)
IN
R
Weak pull-up equivalent resistor
kΩ
pF
ns
PU
C
I/O pin capacitance
IO
1)
t
Output high to low level fall time
25
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
1)
t
Output low to high level rise time
25
4)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 66). Static peak current value taken at a fixed V value,
IN
based on design simulation and technology characteristics, not tested in production. This value depends on V and tem-
DD
perature values.
3. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 63).
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 62. Two typical applications with unused I/O pin configured as input
VDD
ST7XXX
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally
(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
Figure 63. Typical I vs. V with V =V
SS
PU
DD
IN
l
90
80
70
60
50
40
30
20
10
0
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
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1
ST7LITE0xY0, ST7LITESxY0
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Max
Unit
I =+5mA T ≤85°C
1.0
1.2
IO
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 65)
T ≥85°C
A
I =+2mA T ≤85°C
0.4
0.5
IO
A
T ≥85°C
A
1)
V
OL
I =+20mA,T ≤85°C
1.3
1.5
IO
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 66)
T ≥85°C
A
I =+8mA T ≤85°C
0.75
0.85
IO
A
T ≥85°C
A
I =-5mA, T ≤85°C
V
V
-1.5
IO
A
DD
DD
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 72)
-1.6
T ≥85°C
A
2)
V
OH
I =-2mA T ≤85°C
V
V
-0.8
-1.0
IO
A
DD
DD
T ≥85°C
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 64)
V
I =+2mA T ≤85°C
0.5
0.6
IO
A
T ≥85°C
A
1)3)
V
OL
I =+8mA T ≤85°C
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
0.5
0.6
IO
A
T ≥85°C
A
I =-2mA T ≤85°C
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
V
V
-0.8
-1.0
2)3)
1)3)
IO
A
DD
DD
V
OH
T ≥85°C
A
I =+2mA T ≤85°C
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
0.6
0.7
IO
A
T ≥85°C
A
V
OL
I =+8mA T ≤85°C
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
0.6
0.7
IO
A
T ≥85°C
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 69)
I =-2mA T ≤85°C
V
V
-0.9
-1.0
2)3)
IO
A
DD
DD
V
OH
T ≥85°C
A
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
.
IO
VDD
3. Not tested in production, based on characterization results.
96/124
1
ST7LITE0xY0, ST7LITESxY0
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 64. Typical V at V =3.3V (standard)
Figure 66. Typical V at V =5V (high-sink)
OL DD
OL
DD
2.50
2.00
1.50
1.00
0.50
0.00
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45°C
0°C
-45
0°C
25°C
90°C
130°C
25°C
90°C
130°C
6
7
8
9
10
15
lio (mA)
20
25
30
35
40
0.01
1
2
3
lio (mA)
Figure 67. Typical V at V =3V (high-sink)
Figure 65. Typical V at V =5V (standard)
OL
DD
OL
DD
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45
-45°C
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
0.01
1
2
3
4
5
lio (mA)
6
7
8
9
10
15
lio (mA)
Figure 68. Typical V -V at V =2.4V
DD OH
DD
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45°C
0°C
25°C
90°C
130°C
-0.01
-1
-2
lio (mA)
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1
ST7LITE0xY0, ST7LITESxY0
Figure 69. Typical V -V at V =2.7V
Figure 71. Typical V -V at V =4V
DD OH DD
DD OH
DD
1.20
1.00
0.80
0.60
0.40
0.20
0.00
2.50
2.00
1.50
1.00
0.50
0.00
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
-0.01
-1
-2
-0.01
-1
-2
-3
-4
-5
lio(mA)
lio (mA)
Figure 72. Typical V -V at V =5V
Figure 70. Typical V -V at V =3V
DD OH
DD
DD OH
DD
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
-0.01
-1
-2
-3
-4
-5
-0.01
-1
-2
-3
lio (mA)
lio (mA)
Figure 73. Typical V vs. V (standard I/Os)
OL
DD
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.06
0.05
0.04
0.03
0.02
0.01
0.00
-45
-45
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
2.7
3.3
5
2.4
2.7
3.3
5
VDD (V)
VDD (V)
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ST7LITE0xY0, ST7LITESxY0
Figure 74. Typical V vs. V (high-sink I/Os)
OL
DD
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45
-45
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
3
5
2.4
3
5
VDD (V)
VDD (V)
Figure 75. Typical V -V vs. V
DD OH
DD
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
2.7
3
4
5
4
5
VDD
VDD (V)
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ST7LITE0xY0, ST7LITESxY0
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
T = -40°C to 105°C, unless otherwise specified
A
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
V
V
V
SS - 0.3
0.3xVDD
IL
V
Input high level voltage
0.7xVDD
V
DD + 0.3
IH
1)
V
Schmitt trigger voltage hysteresis
2
V
hys
I =+5mA T ≤85°C
1.0
1.2
IO
A
0.5
T ≤105°C
A
2)
V
Output low level voltage
V
V
=5V
=5V
V
OL
DD
DD
I =+2mA T ≤85°C
0.4
0.5
IO
A
0.2
T ≤105°C
A
3) 1)
R
Pull-up equivalent resistor
20
20
40
30
80
kΩ
µs
µs
ns
ON
t
Generated reset pulse duration
Internal reset sources
w(RSTL)out
4)
t
t
External reset pulse hold time
h(RSTL)in
Filtered glitch duration
200
g(RSTL)in
Notes:
1. Data based on characterization results, not tested in production.
2. The I current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 82 and the
IO
IO
sum of I (I/O ports and control pins) must not exceed I
.
VSS
3. The R
ILmax
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
DD
ON
V
and V
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t
can be ignored.
h(RSTL)in
100/124
1
ST7LITE0xY0, ST7LITESxY0
CONTROL PIN CHARACTERISTICS (Cont’d)
1)2)3)4)
Figure 76. RESET pin protection when LVD is enabled.
V
ST72XXX
DD
Optional
(note 3)
Required
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01µF
1MΩ
WATCHDOG
ILLEGALOPCODE 5)
LVD RESET
PULSE
GENERATOR
1)
Figure 77. RESET pin protection when LVD is disabled.
V
ST72XXX
DD
R
ON
Filter
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
0.01µF
WATCHDOG
PULSE
GENERATOR
ILLEGALOPCODE 5)
Required
Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the V max. level specified in section 13.9.1 on page 100. Otherwise the reset will not be taken into account
IL
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
section 13.2.2 on page 82.
in
INJ(RESET)
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in Table 1
on page 7 and notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
Note 5: See “Illegal Opcode Reset” on page 78. for more details on illegal opcode reset conditions
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ST7LITE0xY0, ST7LITESxY0
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
/128 =
0.0625
Max
/4 =
CPU
Unit
Master
Slave
f
f
f
CPU
f
=8MHz
=8MHz
2
f
CPU
SCK =
MHz
SPI clock frequency
1/t
/2 =
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
T + 50
CPU
f(SCK)
1)
4)
t
SS setup time
Slave
Slave
su(SS)
1)
t
SS hold time
120
h(SS)
1)
1)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
w(SCKL)
1)
t
Master
Slave
100
100
su(MI)
Data input setup time
Data input hold time
1)
t
su(SI)
1)
1)
t
Master
Slave
100
100
h(MI)
ns
t
h(SI)
1)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
1)
t
dis(SO)
1)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
Master (after enable edge)
1)
t
0
0
1)
1)
t
120
t
Figure 78. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
tv(SO)
th(SO)
tdis(SO)
tr(SCK)
tf(SCK)
see
note 2
MISO OUTPUT
see note 2
MSB OUT
BIT6 OUT
LSB OUT
tsu(SI)
th(SI)
LSB IN
MSB IN
BIT1 IN
MOSI INPUT
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
4. Depends on f
. For example, if f
=8MHz, then T
= 1/f
=125ns and t
=175ns
CPU
CPU
CPU
CPU
su(SS)
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1
ST7LITE0xY0, ST7LITESxY0
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 79. SPI Slave Timing Diagram with CPHA=11)
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
tdis(SO)
tv(SO)
th(SO)
tr(SCK)
tf(SCK)
see
note 2
see
note 2
MISO OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
tsu(SI)
th(SI)
MSB IN
LSB IN
BIT1 IN
MOSI INPUT
Figure 80. SPI Master Timing Diagram 1)
SS INPUT
tc(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
tsu(MI)
MISO INPUT
MSB IN
BIT6 IN
LSB IN
tv(MO)
th(MO)
LSB OUT
See note 2
MSB OUT
BIT6 OUT
See note 2
MOSI OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
103/124
ST7LITE0xY0, ST7LITESxY0
13.11 8-BIT ADC CHARACTERISTICS
T = -40°C to 85°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MHz
V
f
ADC clock frequency
4
ADC
V
R
Conversion voltage range
External input resistor
V
V
AIN
SS
DD
1)
10
kΩ
AIN
C
Internal sample and hold capacitor
Stabilization time after ADC enable
V
=5V
3
pF
ADC
STAB
DD
2)
t
0
µs
t
Conversion time (t
+t )
SAMPLE HOLD
3
CONV
f
=8MHz, f
=4MHz
CPU
ADC
t
Sample capacitor loading time
Hold conversion time
4
8
SAMPLE
1/f
ADC
t
HOLD
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. Data based on characterization results, not tested in production.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
Figure 81. Typical Application with ADC
VDD
VT
0.6V
2kΩ(max)
RAIN
AINx
8-Bit A/D
Conversion
VAIN
C
VT
0.6V
AIN
IL
1µA
CADC
3pF
ST7XX
104/124
ST7LITE0xY0, ST7LITESxY0
ADC CHARACTERISTICS (Cont’d)
1)
2)
Figure 82. R
max. vs f
with C =0pF
Figure 83. Recommended C /R
values
AIN
ADC
AIN
AIN AIN
45
40
35
30
25
20
15
10
5
1000
100
10
Cain 10 nF
Cain 22 nF
Cain 47 nF
4 MHz
2 MHz
1 MHz
1
0
0.1
0
10
30
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
Notes:
1. C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
PARASITIC
pacitance (3pF). A high C
value will downgrade conversion accuracy. To remedy this, f
should be reduced.
PARASITIC
ADC
2. This graph shows that depending on the input signal variation (f ), C
can be increased for stabilization and to allow
AIN
AIN
the use of a larger serial resistor (R
. It is valid for all f
frequencies ≤ 4MHz.
AIN)
ADC
13.11.1 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
alog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may switch
while the analog inputs are being sampled by the
A/D converter. Do not toggle digital outputs on the
same I/O port as the A/D input being converted.
Properly place components and route the signal
traces on the PCB to shield the analog inputs. An-
105/124
ST7LITE0xY0, ST7LITESxY0
ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with V =5.0V
DD
T = -40°C to 85°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
Max
Unit
2)
E
Total unadjusted error
1
T
O
G
D
2)
E
E
E
Offset error
-0.5 / +1
1
2)
Gain Error
f
f
=4MHz,f
=2MHz,V =5.0V
LSB
CPU
CPU
ADC
DD
2)
2)
1)
Differential linearity error
1
2)
1)
E
E
Integral linearity error
1
L
T
2)
Total unadjusted error
2
2)
E
E
E
Offset error
-0.5 / 3.5
-2 / 0
O
G
D
2)
Gain Error
=8MHz,f
=4MHz,V =5.0V
LSB
ADC
DD
1)
Differential linearity error
1
2)
1)
E
Integral linearity error
1
L
Notes:
1. Data based on characterization results over the whole temperature range, monitored in production.
2. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being
performed on any analog input.
Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative
current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 13.8 does not affect the ADC
INJ(PIN)
INJ(PIN)
–
106/124
ST7LITE0xY0, ST7LITESxY0
ADC CHARACTERISTICS (Cont’d)
Figure 84. ADC Accuracy Characteristics with Amplifier disabled
Digital Result ADCDR
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
255
254
253
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
E =Total Unadjusted Error: maximum deviation
T
(2)
between the actual and the ideal transfer curves.
ET
E =Offset Error: deviation between the first actual
O
(3)
transition and the first ideal one.
7
6
5
4
3
2
1
E =Gain Error: deviation between the last ideal
(1)
G
transition and the last actual one.
E =Differential Linearity Error: maximum deviation
D
EO
between actual steps and the ideal one.
EL
E =Integral Linearity Error: maximum deviation
L
between any actual transition and the end point
correlation line.
ED
1 LSBIDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
253 254 255 256
VDDA
VSSA
Figure 85. ADC Accuracy Characteristics with Amplifier enabled
Digital Result ADCDR
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E =Total Unadjusted Error: maximum deviation
T
(2)
between the actual and the ideal transfer curves.
ET
E =Offset Error: deviation between the first actual
O
(3)
transition and the first ideal one.
n+7
n+6
n+5
n+4
n+3
n+2
n+1
E =Gain Error: deviation between the last ideal
(1)
G
transition and the last actual one.
E =Differential Linearity Error: maximum deviation
D
EO
between actual steps and the ideal one.
EL
E =Integral Linearity Error: maximum deviation
L
between any actual transition and the end point
correlation line.
ED
n=Amplifier Offset
1 LSBIDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
100 101 102 103
250 mV
VSS
Note: When the AMPSEL bit in the ADCDRL register is set, it is mandatory that f
be less than or equal
ADC
to 2 MHz. (if f
=8MHz. then SPEED=0, SLOW=1).
CPU
107/124
ST7LITE0xY0, ST7LITESxY0
ADC CHARACTERISTICS (Cont’d)
Vout (ADC input)
Vmax
Noise
Vmin
Vin
0V
(OPAMP input)
0V
250mV
Symbol
Parameter
Conditions
=5V
Min
4.5
0
Typ
Max
5.5
Unit
V
V
V
V
V
Amplifier operating voltage
Amplifier input voltage
Amplifier offset voltage
DD(AMP)
IN
V
250
mV
mV
mV
DD
200
OFFSET
STEP
3)
Step size for monotonicity
Output Voltage Response
Amplified Analog input Gain
5
Linearity
Gain factor
Vmax
Linear
2)
1)
1)
7
8
9
Output Linearity Max Voltage
Output Linearity Min Voltage
2.2
200
2.4
V
V
V
= 250mV,
INmax
=5V
Vmin
mV
DD
Notes:
1. Data based on characterization results over the whole temperature range, not tested in production.
2. For precise conversion results it is recommended to calibrate the amplifier at the following two points:
– offset at V = 0V
INmin
– gain at full scale (for example V =250mV)
IN
3. Monotonicity guaranteed if V increases or decreases in steps of min. 5mV.
IN
108/124
ST7LITE0xY0, ST7LITESxY0
14 PACKAGE CHARACTERISTICS
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
These packages have a Lead-free second level in-
terconnect. The category of second Level Inter-
connect is marked on the package and on the in-
ner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to solder-
ing conditions are also marked on the inner box la-
bel.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
14.1 PACKAGE MECHANICAL DATA
Figure 86. 20-Lead Very thin Fine pitch Quad Flat No-Lead Package
1)
mm
inches
Typ
Dim.
A
Min Typ Max Min
Max
0.80 0.85 0.90 0.0315 0.0335 0.0354
A1 0.00 0.02 0.05
0.0008 0.0020
0.0008
A3
b
0.02
0.25 0.30 0.35 0.0098 0.0118 0.0138
5.00 0.1969
D
D2 3.10 3.25 3.35 0.1220 0.1280 0.1319
6.00 0.2362
E2 4.10 4.25 4.35 0.1614 0.1673 0.1713
E
e
L
0.80
0.45 0.50 0.55 0.0177 0.0197 0.0217
0.08 0.0031
Number of Pins
20
0.0315
ddd
N
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.
109/124
ST7LITE0xY0, ST7LITESxY0
Figure 87. 16-Pin Plastic Dual In-Line Package, 300-mil Width
1)
mm
Min Typ Max
5.33
inches
Typ
Dim
A
Min
Max
E
0.2098
A1 0.38
0.0150
A2
A
A2 2.92 3.30 4.95 0.1150 0.1299 0.1949
0.36 0.46 0.56 0.0142 0.0181 0.0220
A1
b
L
b2 1.14 1.52 1.78 0.0449 0.0598 0.0701
b3 0.76 0.99 1.14 0.0299 0.0390 0.0449
c
E1
b2
b
eB
e
D1
c
0.20 0.25 0.36 0.0079 0.0098 0.0142
18.67 19.18 19.69 0.7350 0.7551 0.7752
b3
D
D
D1 0.13
0.0051
e
2.54
7.62 7.87 8.26 0.3000 0.3098 0.3252
E1 6.10 6.35 7.11 0.2402 0.2500 0.2799
0.1000
E
L
2.92 3.30 3.81 0.1150 0.1299 0.1500
eB
10.92
0.4299
Number of Pins
N
16
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.
Figure 88. 16-Pin Plastic Small Outline Package, 150-mil Width
1)
mm
inches
Typ
L
Dim.
Min Typ Max Min
Max
45×
A1
A
1.35
1.75 0.0531
0.25 0.0039
0.51 0.0130
0.25 0.0075
0.0689
0.0098
0.0201
0.0098
A1
A
A1 0.10
B
C
0.33
0.19
e
α
B
C
H
10.0
0.3858
0
D
9.80
3.80
0.3937
0.1575
D
E
e
4.00 0.1496
1.27
0.0500
9
8
16
1
H
α
L
5.80
0°
6.20 0.2283
0.2441
8°
8°
0°
E
0.40
1.27 0.0157
0.0500
Number of Pins
N
16
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.
110/124
ST7LITE0xY0, ST7LITESxY0
14.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance
(junction to ambient)
SO16
DIP16
95
TBD
R
°C/W
thJA
1)
T
Maximum junction temperature
150
500
°C
Jmax
2)
P
Power dissipation
mW
Dmax
Notes:
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula P = (T -T ) / R .
thJA
D
J
A
The power dissipation of an application can be defined by the user with the formula: P =P +P
D
INT
PORT
where P
is the chip internal power (I xV ) and P
is the port power dissipation depending on the
PORT
INT
DD DD
ports used in the application.
111/124
ST7LITE0xY0, ST7LITESxY0
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (FASTROM).
The FASTROM factory coded parts contain the
code supplied by the customer. This implies that
FLASH devices have to be configured by the cus-
tomer using the Option Bytes while the FASTROM
devices are factory-configured.
ST7PLITE0x and ST7PLITES2/S5 devices are
Factory Advanced Service Technique ROM (FAS-
TROM) versions: they are factory-programmed
XFlash devices.
ST7FLITE0x and ST7FLITES2/S5 XFlash devices
are shipped to customers with a default program
memory content (FFh). The OSC option bit is pro-
grammed to 0 by default.
15.1 OPTION BYTES
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
Bit 1 = FMP_R Read-out protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
Erasing the option bytes when the FMP_R option
is selected will cause the whole memory to be
erased first, and the device can be reprogrammed.
Refer to Section 4.5 and the ST7 Flash Program-
ming Reference Manual for more details.
The option bytes can be accessed only in pro-
gramming mode (for example using a standard
ST7 programming tool).
OPTION BYTE 0
Bits 7:4 = Reserved, must always be 1.
0: Read-out protection off
1: Read-out protection on
Bits 3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 ac-
cording to the following table.
Bit 0 = FMP_W FLASH write protection
This option indicates if the FLASH program mem-
ory is write protected.
Sector 0 Size
SEC1
SEC0
Warning: When this option is selected, the pro-
gram memory (and the option bit itself) can never
be erased or programmed again.
0: Write protection off
0.5k
1k
0
0
1
0
1
x
1)
1.5k
1: Write protection on
Note 1: Configuration available for ST7LITE0x de-
vices only.
112/124
ST7LITE0xY0, ST7LITESxY0
OPTION BYTES (Cont’d)
OPTION BYTE 1
Bit 7 = PLLx4x8 PLL Factor selection.
0: PLLx4
1: PLLx8
Bit 4 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
Note: If the RC oscillator is selected, then to im-
prove clock stability and frequency accuracy, it is
recommended to place a decoupling capacitor,
Bit 6 = PLLOFF PLL disabled
0: PLL enabled
1: PLL disabled (by-passed)
typically 100nF, between the V and V pins as
DD
SS
close as possible to the ST7 device.
Bit 5 = Reserved, must always be 1.
Table 21. List of valid option combinations
Operating conditions
Option Bits
V
range
Clock Source
PLL
off
x4
x8
off
x4
x8
off
x4
x8
off
x4
x8
Typ f
OSC
PLLOFF
PLLx4x8
DD
CPU
0.7MHz @3V
0
0
-
1
0
-
1
0
-
Internal RC 1%
2.8MHz @3V
-
2.4V - 3.3V
3.3V - 5.5V
0-4MHz
1
1
-
1
0
-
1
0
-
External clock
Internal RC 1%
External clock
4MHz
-
1MHz @5V
0
-
1
-
1
-
-
8MHz @5V
0-8MHz
-
0
1
-
0
1
-
1
1
-
8 MHz
1
0
1
Note: see Clock Management Block diagram in Figure 14
Bits 3:2 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se-
lected threshold as shown in Table 22.
Bit 1 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Table 22. LVD Threshold Configuration
Bit 0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Configuration
LVD1 LVD0
1
1
0
0
1
0
1
0
LVD Off
Highest Voltage Threshold (∼4.1V)
Medium Voltage Threshold (∼3.5V)
Lowest Voltage Threshold (∼2.8V)
OPTION BYTE 0
OPTION BYTE 1
7
0
7
0
FMP FMP PLL PLL
WDG WDG
SW HALT
Reserved
SEC1 SEC0
OSC LVD1 LVD0
R
W
x4x8 OFF
Default
Value
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
113/124
ST7LITE0xY0, ST7LITESxY0
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the FASTROM con-
tents and the list of the selected options (if any).
The FASTROM contents are to be sent on dis-
kette, or by electronic means, with the S19 hexa-
decimal file generated by the development tool. All
unused bytes must be set to FFh. The selected op-
tions are communicated to STMicroelectronics us-
ing the correctly completed OPTION LIST append-
ed.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
114/124
ST7LITE0xY0, ST7LITESxY0
Figure 89. Ordering information scheme
Example:
ST7
F
LITES5
Y
0
M
6
TR
Family
ST7 Microcontroller Family
Memory type
F: Flash
P: FASTROM
Sub-family
LITES2, LITES5, LITE02, LITE05 or LITE09
No. of pins
Y = 16
Memory size
0 = 1K (LITESx versions) or 1.5K (LITE0x versions)
Package
B = DIP
M = SO
U = QFN
Temperature range
6 = -40 °C to 85 °C
Shipping Option
TR = Tape & Reel packing
Blank = Tube (DIP16 or SO16) or Tray (QFN20)
For a list of available options (e.g. data EEPROM, package) and orderable part numbers or for
further information on any aspect of this device, please contact the ST Sales Office nearest to you.
115/124
ST7LITE0xY0, ST7LITESxY0
ST7LITE0xY0 AND ST7LITESxY0 FASTROM MICROCONTROLLER OPTION LIST
(Last update: November 2007)
Customer
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No
Reference/FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*FASTROM code name is assigned by STMicroelectronics.
FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Memory size (check only one option):
Device type (check only one option):
[ ] 1 K
[ ] 1.5 K
[ ] ST7PLITES2Y0
[ ] ST7PLITE02Y0
[ ] ST7PLITES5Y0
[ ] ST7PLITE05Y0
[ ] ST7PLITE09Y0
Warning: Addresses 1000h, 1001h, FFDEh and FFDFh are reserved areas for ST to program RCCR0 and
RCCR1 (see section 7.1 on page 24).
Conditioning (check only one option):
PDIP16
[ ] Tube
SO16
QFN20
[ ] Tape & Reel
[ ] Tape & Reel
[ ] Tube
[ ] Tray
Special Marking:
[ ] No
[ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count:
PDIP16 (15 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
SO16 (11 char. max) : _ _ _ _ _ _ _ _ _ _ _
Sector 0 size:
[ ] 0.5K
[ ] 1K
[ ] 1.5K
Readout Protection:
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled
FLASH write Protection:
Clock Source Selection:
[ ] Internal RC
[ ] External Clock
[ ] PLLx4
PLL
[ ] Disabled
[ ] Disabled
[ ] PLLx8
LVD Reset
[ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
Watchdog Selection:
Watchdog Reset on Halt:
[ ] Software Activation
[ ] Disabled
[ ] Hardware Activation
[ ] Enabled
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature:
Important note: Not all configurations are available. See Table 21 on page 113 for authorized option byte
combinations and “Ordering information scheme” on page 115.
Please download the latest version of this option list from:
www.st.com
116/124
ST7LITE0xY0, ST7LITESxY0
15.3 DEVELOPMENT TOOLS
Development tools for the ST7 microcontrollers in-
clude a complete range of hardware systems and
software tools from STMicroelectronics and third-
party tool suppliers. The range of tools includes
solutions to help you evaluate microcontroller pe-
ripherals, develop and debug your application, and
program your microcontrollers.
guage debugger, editor, project manager and inte-
grated programming interface.
15.3.3 Programming tools
During the development cycle, the ST7-DVP3 and
ST7-EMU3 series emulators and the RLink pro-
vide in-circuit programming capability for program-
ming the Flash microcontroller on your application
board.
15.3.1 Starter kits
ST offers complete, affordable starter kits. Starter
kits are complete, affordable hardware/software
tool packages that include features and samples
to help you quickly start developing your applica-
tion.
ST also provides a low-cost dedicated in-circuit
programmer, the ST7-STICK, as well as ST7
Socket Boards which provide all the sockets re-
quired for programming any of the devices in a
specific ST7 sub-family on a platform that can be
used with any tool with in-circuit programming ca-
pability for ST7.
15.3.2 Development and debugging tools
Application development for ST7 is supported by
fully optimizing C Compilers and the ST7 Assem-
bler-Linker toolchain, which are all seamlessly in-
tegrated in the ST7 integrated development envi-
ronments in order to facilitate the debugging and
fine-tuning of your application. The Cosmic C
Compiler is available in a free version that outputs
up to 16KBytes of code.
For production programming of ST7 devices, ST’s
third-party tool partners also provide a complete
range of gang and automated programming solu-
tions, which are ready to integrate into your pro-
duction environment.
15.3.4 Order Codes for Development and
Programming Tools
The range of hardware tools includes full-featured
ST7-EMU3 series emulators, cost effective ST7-
DVP3 series emulators and the low-cost RLink
in-circuit debugger/programmer. These tools are
supported by the ST7 Toolset from STMicroelec-
tronics, which includes the STVD7 integrated de-
velopment environment (IDE) with high-level lan-
Table 23 below lists the ordering codes for the
ST7LITE0/ST7LITES development and program-
ming tools. For additional ordering codes for spare
parts and accessories, refer to the online product
selector at www.st.com/mcu.
15.3.5 Order codes for ST7LITE0/ST7LITES development tools
Table 23. Development tool order codes for the ST7LITE0/ST7LITES family
1)
MCU
In-circuit Debugger, RLink Series
Emulator
Programming Tool
Starter Kit
Starter Kit with
without Demo
Demo Board
Board
ST Socket
Boards and
EPBs
ST7FLITE02,
ST7FLITE05,
ST7FLITE09,
ST7FLITES2,
ST7FLITES5
In-circuit
Programmer
DVP Series EMU Series
ST7MDT10- ST7MDT10- STX-RLINK
2)
2)
4)
STX-RLINK
ST7FLITE-SK/RAIS
ST7SB10-SU0
4)5)
3)
DVP3
EMU3
ST7-STICK
Notes:
1. Available from ST or from Raisonance, www.raisonance.com
2. USB connection to PC
3. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide
for connection kit ordering information
4. Add suffix /EU, /UK or /US for the power supply for your region
5. Parallel port connection to PC
117/124
ST7LITE0xY0, ST7LITESxY0
15.4 ST7 APPLICATION NOTES
Table 24. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658
AN1720
AN1755
AN1756
SERIAL NUMBERING IMPLEMENTATION
MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN-
PUT VOLTAGES
AN1812
EXAMPLE DRIVERS
SCI COMMUNICATION BETWEEN ST7 AND PC
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
EMULATED 16-BIT SLAVE SPI
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
SOFTWARE UART USING 12-BIT ART
118/124
ST7LITE0xY0, ST7LITESxY0
Table 24. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN1947
ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
GENERAL PURPOSE
AN1476
AN1526
AN1709
AN1752
LOW COST POWER SUPPLY FOR HOME APPLIANCES
ST7FLITE0 QUICK REFERENCE NOTE
EMC DESIGN FOR ST MICROCONTROLLERS
ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1103
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
AN1604
AN2200
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
HOW TO USE ST7MDT1-TRAIN WITH ST72F264
GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB
PRODUCT OPTIMIZATION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
TOR
AN1530
AN1605
AN1636
AN1828
AN1946
AN1953
AN1971
USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
PFC FOR ST7MC STARTER KIT
ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN1039
ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
ST7 MATH UTILITY ROUTINES
119/124
ST7LITE0xY0, ST7LITESxY0
Table 24. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN1071
AN1106
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1477
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
USING THE ST72521 EMULATOR TO DEBUG AN ST72324 TARGET APPLICATION
EMULATED DATA EEPROM WITH XFLASH MEMORY
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
ST7 CUSTOMER ROM CODE RELEASE INFORMATION
DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711
AN1827
AN2009
AN2030
SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
BACK EMF DETECTION DURING PWM ON TIME BY ST7MC
120/124
ST7LITE0xY0, ST7LITESxY0
16 KNOWN LIMITATIONS
16.1 Execution of BTJX Instruction
Description
tings, devices programmed with the Hardware
watchdog option cannot be reprogrammed using
this tool.
Executing a BTJx instruction jumps to a random
address in the following conditions: the jump goes
to a lower address (jump backward) and the test is
performed on a data located at the address
00FFh.
16.3 In-Circuit Debugging with Hardware
Watchdog
In Circuit Debugging is impacted in the same way
as In Circuit Programming by the activation of the
hardware watchdog in ICC mode. Please refer to
Section 16.2.
16.2 In-Circuit Programming of devices
previously programmed with Hardware
Watchdog option
Description
16.4 Recommendations when LVD is enabled
In-Circuit Programming of devices configured with
Hardware Watchdog (WDGSW bit in option byte 1
programmed to 0) requires certain precautions
(see below).
When the LVD is enabled, it is recommended not
to connect a pull-up resistor or capacitor. A 10nF
pull-down capacitor is required to filter noise on
the reset line.
In-Circuit Programming uses ICC mode. In this
mode, the Hardware Watchdog is not automatical-
ly deactivated as one might expect. As a conse-
quence, internal resets are generated every 2 ms
by the watchdog, thus preventing programming.
16.5 Clearing Active Interrupts Outside
Interrupt Routine
The device factory configuration is Software
Watchdog so this issue is not seen with devices
that are programmed for the first time. For the
same reason, devices programmed by the user
with the Software Watchdog option are not impact-
ed.
When an active interrupt request occurs at the
same time as the related flag or interrupt mask is
being cleared, the CC register may be corrupted.
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e. when:
The only devices impacted are those that have
previously been programmed with the Hardware
Watchdog option.
– The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
Workaround
– The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine
Devices configured with Hardware Watchdog
must be programmed using a specific program-
ming mode that ignores the option byte settings. In
this mode, an external clock, normally provided by
the programming tool, has to be used. In ST tools,
this mode is called "ICP OPTIONS DISABLED".
– The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Sockets on ST programming tools (such as
ST7MDT10-EPB) are controlled using "ICP OP-
TIONS DISABLED" mode. Devices can therefore
be reprogrammed by plugging them in the ST Pro-
gramming Board socket, whatever the watchdog
configuration.
Perform SIM and RIM operation before and after
resetting an active interrupt request
Ex:
SIM
When using third-party tools, please refer the
manufacturer's documentation to check how to ac-
cess specific programming modes. If a tool does
not have a mode that ignores the option byte set-
reset flag or interrupt mask
RIM
121/124
ST7LITE0xY0, ST7LITESxY0
17 REVISION HISTORY
Table 25. Revision History
Date
Revision
Description of changes
Revision number incremented from 2.5 to 3.0 due to Internal Document Management Sys-
tem change
Changed all references of ADCDAT to ADCDR
Added EMU3 Emulator Programming Capability in Table 23
Clarification of read-out protection
Altered note 1 for section 13.2.3 on page 82 removing references to RESET
Alteration of f
on page 90
for SLOW and SLOW-WAIT modes in Section 13.4.1 table and Figure 59
CPU
Removed sentence relating to an effective change only after overflow for CK[1:0], page 56
Added illegal opcode detection to page 1, section 8.4 on page 32, section 12 on page 75
Clarification of Flash read-out protection, section 4.5.1 on page 15
27-Oct-04
3
f
value of 1MHz quoted as Typical instead of a Minimum in section 14.3.5.2 on page 92
PLL
Updated F
in section 13.10.1 on page 102 to F
/4 and F
/2
SCK
CPU
CPU
section 8.4.4 on page 36: Changed wording in AVDIE and AVDF bit descriptions to “...when
the AVDF bit is set”
Socket Board development kit details added in Table 24 on page 115
PWM Signal diagram corrected, Figure 36 on page 55
Corrected count of reserved bits between 003Bh to 007Fh, Table 2 on page 11
Inserted note that RCCR0 and RCCR1 are erased if read-only flag is reset, section 7.1 on
page 24
Added QFN20 package
Modified section 2 on page 6
Changed Read operation paragraph in section 5.3 on page 17
Modified note below Figure 9 on page 18 and modified section 5.5 on page 19
Modified note to section 7.1 on page 24
Added note on illegal opcode reset to section 7.4.1 on page 27
Added note 2 to EICR description on page 31
Modified External Interrupt Function in section 10.2.1 on page 42
Changed text on input capture before section 11.1.4 on page 51
Modified text in section 11.1.5 on page 51
Added important note in section 11.3.3.3 on page 62
Changed note 1 in section 13.2 on page 82
Modified values in section 13.2.2 on page 82
Modified note 2 in section 13.3.4.1 on page 85 and section 13.3.4.2 on page 86
Added note on clock stability and frequency accuracy to section 13.3.4.1 on page 85, section
13.3.4.2 on page 86, section 7.1 on page 24 and to OSC option bit in Section 15.1 on page
21-July-06
4
113
Changed I value and note 2 in section 13.8.1 on page 95
S
Added note in Figure 62 on page 95
Changed Figure 76 on page 101 and removed EMC protection circuitry in Figure 77 on page
101 (device works correctly without these components)
Changed section 13.10.1 on page 102 (t
Modified Figure 79 (CPHA=1) and Figure 80 on page 103 (t
t
t
)
su(SS), v(MO) and h(MO)
t
)
v(MO) , h(MO)
Added ECOPACK information to section 14 on page 109
Modified Figure 88 on page 110 (A1 and A swapped in the diagram)
Modified Table 21 on page 112
Modified section 15.2 on page 114
Updated option list on page 116
Changed section 15.3 on page 117
Removed erratasheet section
Added Section 16.4 and section 16.5 on page 121
Revision History continued overleaf ...
122/124
ST7LITE0xY0, ST7LITESxY0
Removed QFN20 pinout and mechanical data.
Modified text in External Interrupt Function section in section 10.2.1 on page 42
Modified Table 24 on page 116 (and QFN20 rows in grey).
Added “External Clock Source” on page 91 and Figure 61 on page 91
Modified description of CNTR[11:0] bits in section 11.2.6 on page 56
Updated option list on page 116
09-Oct-06
5
Changed section 15.3 on page 117
Title of the document modified
Modified LOCKED bit description in section 8.4.4 on page 36
In Table 1 on page 7 and section 13.2.2 on page 82, note “negative injection not allowed on
PB0 and PB1 pins” replaced by “negative injection not allowed on PB1 pin”
Added QFN20 package pinout (with new QFN20 mechanical data): Figure 2 on page 6 and
Figure 86 on page 109
Modified section 8.4.4 on page 36
Removed one note in section 11.1.3.1 on page 49
Modified section 13.7 on page 93
19-Nov-07
6
Modified “PACKAGE MECHANICAL DATA” on page 109 (values in inches rounded to 4 dec-
imal digits)
Modified section 15.2 on page 114 (“Ordering information scheme” on page 115 added and
table removed) and option list on page 116
Removed “soldering information” section
Modified section 15.3.5 on page 117
123/124
ST7LITE0xY0, ST7LITESxY0
Notes:
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
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124/124
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