ST7PMC1K4B6 [STMICROELECTRONICS]
8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™; 8位MCU与嵌套中断,闪存, 10位ADC ,无刷电机控制, 5个定时器, SPI , LINSCI ™型号: | ST7PMC1K4B6 |
厂家: | ST |
描述: | 8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™ |
文件: | 总309页 (文件大小:5008K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ST7MC1xx/ST7MC2xx
8-bit MCU with nested interrupts, Flash, 10-bit ADC,
brushless motor control, five timers, SPI, LINSCI™
Features
■ Memories
– 8K to 60K dual voltage Flash Program memo-
ry or ROM with read-out protection capability,
In-application programming and In-circuit pro-
gramming.
LQFP80
14 x 14
LQFP64
14 x 14
LQFP44 LQFP32 7x 7
10 x 10
– 384 to 1.5K RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 40 years at 85°C
event detector
■ Clock, reset and supply management
■ 2 Communication interfaces
– Enhanced reset system
– SPI synchronous serial interface
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators and by-pass for external clock, clock
security system.
– LINSCI™ asynchronous serial interface
■ Brushless motor control peripheral
– 6 high sink PWM output channels for sine-
wave or trapezoidal inverter control
– Motor safety including asynchronous emer-
gency stop and write-once registers
– Four power saving modes: Halt, Active-halt,
– 4 analog inputs for rotor position detection
(sensorless/hall/tacho/encoder)
– Permanent magnet motor coprocessor includ-
ing multiplier, programmable filters, blanking
windows and event counters
Wait and Slow
■ Interrupt management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– MCES top level interrupt pin
– 16 external interrupt lines (on 3 vectors)
– Operational amplifier and comparator for cur-
rent/voltage mode regulation and limitation
■ Up to 60 I/O ports
■ Analog peripheral
– up to 60 multifunctional bidirectional I/O lines
– 10-bit ADC with 16 input pins
– up to 41 alternate function lines
– up to 12 high sink outputs
■ In-circuit Debug
■ Instruction set
■ 5 timers
– 8-bit data manipulation
– Main clock controller with: Real-time base,
– 63 basic instructions with illegal opcode de-
Beep and clock-out capabilities
tection
– Configurable window watchdog timer
– 17 main Addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input, PWM and
pulse generator modes
■ Development tools
– 8-bit PWM Auto-reload timer with: 2 input cap-
tures, 4 PWM outputs, output compare and
time base interrupt, external clock with
Table 1. Device summary
– Full hardware/software development package
ST7MC2N6 1)/ ST7MC2S4 / ST7MC2S6 / ST7MC2S7 / ST7MC2S9
/ ST7MC2R6 / ST7MC2R7 / ST7MC2R9 / ST7MC2M9
Features
ST7MC1K2 / ST7MC1K4
Program memory - bytes
RAM (stack) - bytes
8K
384 (256)
16K
16K
32K
1024 (256)
48K
60K
1536 (256)
768 (256) 768 (256)
Watchdog, 16-bit Timer A, LINSCI™, 10-bit ADC, MTC, 8-bit PWM ART, ICD
Peripherals
SPI, 16-bit Timer B
-
Operating
Supply vs. Frequency
4.5 to 5.5V with f
≤8MHz
CPU
-40°C to +85°C
/-40°C to +125°C
-40°C to
+85°C
LQFP32
-40°C to +85°C
-40°C to +125°C
-40°C to
+125°C
Temperature Range
-40°C to +85 °C
1)
Package
LQFP32
LQFP44 SDIP56 /LQFP64 LQFP64/44 LQFP80/64 LQFP44
Note 1: For development only. No production
April 2009
Rev 13
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1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC) . 37
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 47
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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10.2 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . 107
10.6 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.7 OPERATIONAL AMPLIFIER (OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 271
12.12 MOTOR CONTROL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
12.13 OPERATIONAL AMPLIFIER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
12.14 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
14 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . 290
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 292
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
15.1 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
15.2 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 300
15.3 TIMD SET SIMULTANEOUSLY WITH OC INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . 300
15.4 LINSCI LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
15.5 MISSING DETECTION OF BLDC “Z EVENT” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
15.6 INJECTED CURRENT ON PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
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15.7 RESET VALUE OF UNAVAILABLE PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
15.8 MAXIMUM VALUES OF AVD THRESHOLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
15.9 EXTERNAL INTERRUPT MISSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please also pay special attention to the Section “IMPORTANT NOTES” on page 299.
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ST7MC1xx/ST7MC2xx
1 INTRODUCTION
The ST7MCx device is member of the ST7 micro-
controller family designed for mid-range applica-
tions with a Motor Control dedicated peripheral.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with FLASH, ROM or
FASTROM program memory.
Under software control, all devices can be placed
in Wait, Slow, Active-halt or Halt mode, reducing
power consumption when the application is in idle
or stand-by state.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
Figure 1. Device Block Diagram
PROGRAM
MEMORY
(8K - 60K Bytes)
8-BIT CORE
ALU
RESET
CONTROL
V
PP
RAM
(384 - 1536Bytes)
V
V
SS
DD
LVD
AVD
OSC
1)
PH7:0
1)
1)
PORT H
PORT G
(8-bits)
1)
OSC1
OSC2
PG7:0
(8-bits)
SCI/LIN
WATCHDOG
PWM ART
PORT A
PORT D
TIMER A
1)
PD7:0
(8-bits)
PA7:0
(8-bits)
10-BIT ADC
PORT B
V
AREF
V
SSA
PB7:0
(8-bits)
MTC VOLT INPUT
1
PORT E
1
SPI
PE5:0
(6-bits)
1
TIMER B
PORT C
PC7:0
(8-bits)
1
PORT F
MOTOR CONTROL
MCES
PF5:0
(6-bits)
1
MCC/RTC/BEEP
DEBUG MODULE
On some devices only, see Table 1, “ST7MC Device Pin Description,” on page 12
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1
ST7MC1xx/ST7MC2xx
2 PIN DESCRIPTION
Figure 2. 80-Pin LQFP 14x14 Package Pinout
PD3 / ICAP1_A / AIN13
PD2 / ICAP2_A / AIN12
PD1 (HS) / OCMP1_A
PD0 / OCMP2_A / AIN11
PH3
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
(HS) MCO3
(HS) MCO4
(HS) MCO5
MCES
2
ei0
3
4
PG0
5
PH2
PH1
PH0
PG1
6
PG2
7
PG3
8
PF5 (HS)
PF4 (HS)
PF3 (HS) / BEEP
PF2 / MCO / AIN10
PF1 / MCZEM / AIN9
9
OSC1
OSC2
VSS_1
VDD_1
10
11
12
13
14
15
16
17
18
19
20
PWM3 / PA0
PWM2 / (HS) PA1
PWM1 / PA2
PF0 / MCDEM / AIN8
RESET
V
AIN0 / PWM0 / PA3
ARTCLK / (HS) PA4
AIN1 / ARTIC1 / PA5
ARTIC2 / PA6
ei1
ei1
DD_0
VSS_0
VSSA
VAREF
ei2
ei2
PC7 / MCPWMW / AIN7
AIN2 / PA7
(HS) 20mA high sink capability
eix associated external interrupt vector
* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
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1
ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont’d)
Figure 3. 64-Pin LQFP 14x14 Package Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PD3 / ICAP1_A / AIN13
PD2 / ICAP2_A / AIN12
PD1 (HS) / OCMP1_A
PD0 / OCMP2_A / AIN11
PF5 (HS)
(HS) MCO3
(HS) MCO4
(HS) MCO5
MCES
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
ei0
4
OSC1
5
PF4 (HS)
OSC2
6
V
V
_1
_1
PF3 (HS) / BEEP
PF2 / MCO / AIN10
PF1 / MCZEM / AIN9
PF0 / MCDEM / AIN8
RESET
7
SS
DD
8
PWM3 / PA0
PWM2 / (HS) PA1
PWM1 / PA2
9
10
11
12
13
14
15
16
V
AIN0 / PWM0 / PA3
ARTCLK / (HS) PA4
AIN1 / ARTIC1 / PA5
ARTIC2 / PA6
DD_0
ei1
ei1
V
SS_0
V
V
SSA
ei2
AREF
PC7 / MCPWMW / AIN7
AIN2 / PA7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(HS) 20mA high sink capability
eix associated external interrupt vector
* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
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1
ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont’d)
Figure 4. 32-Pin SDIP Package Pinouts
ICCSEL / VPP
MCO0
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PD7 (HS) / TDO
2
PD6 (HS) / RDI
MCO1
3
PD5 / AIN15 / ICCDATA
PD4 / EXTCLK_A / AIN14 / ICCCLK
PD3 / ICAP1_A / AIN13
PD2 / ICAP2_A / MCZEM / AIN12
PD1 (HS) / OCMP1_A / MCPWMV / MCDEM
PD0 / OCMP2_A / MCPWMW / AIN11
RESET
MCO2
4
MCO3
5
ei0
MCO4
6
MCO5
7
MCES
8
OSC1
9
OSC2
10
11
12
13
14
15
16
VDD_0
AIN0 / PWM0 / PA3
AIN1 / ARTIC1 / PA5
MCVREF / PB0
MCIA / PB1
MCIB / PB2
MCIC / PB3
VSS_0
ei1
VAREF
PC4 / MCCREF *
OAZ / MCCFI1 / AIN6
PC3 / OAN
ei2
PC2 / OAP
(HS) 20mA high sink capability
eix associated external interrupt vector
* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
8/309
1
ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont’d)
Figure 5. 56-Pin SDIP Package Pinouts
1
OCMP1_B / PE1
ICAP2_B / PE2
ICAP1_B / PE3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PE0 (HS) / OCMP2_B
2
V
V
_2
DD
3
_2
SS
4
V
/ICCSEL
PD7 (HS) / TDO
PD6 (HS) / RDI
PP
5
(HS) MCO0
(HS) MCO1
(HS) MCO2
(HS) MCO3
(HS) MCO4
(HS) MCO5
6
PD5 / AIN15 / ICCDATA
7
PD4 /EXTCLK_A / AIN14 / ICCCLK
ei0
8
PD3 / ICAP1_A / AIN13
PD2 / ICAP2_A / AIN12
PD1 (HS) / OCMP1_A
PD0 / OCMP2_A / AIN11
PF3 (HS) / BEEP
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MCES
OSC1
PF1 / MCZEM / AIN9
PF0 / MCDEM / AIN8
RESET
OSC2
Vss_1
Vdd_1
V
PWM2 / (HS) PA1
AIN0 / PWM0 / PA3
ARTCLK / (HS) PA4
AIN1 / ARTIC1 / PA5
DD_0
V
SS_0
ei1
ei1
V
SSA
V
AREF
PC7 / MCPWMW / AIN7
ARTIC2 / PA6
PC6 / MCPWMV
PC5 / MCPWMU
MCVREF / PB0
MCIA / PB1
MCIB / PB2
PC4 / MCCREF *
OAZ / MCCFI1 / AIN6
PC3 / OAN
MCIC / PB3
MISO / PB4
AIN3 / MOSI / PB5
SCK / (HS) PB6
AIN4 / SS /(HS) PB7
PC2 / OAP
ei2
PC1 / MCCFI0/AIN5
PC0(HS)
ei2
(HS) 20mA high sink capability
eix associated external interrupt vector
* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
9/309
1
ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont’d)
Figure 6. 44-Pin LQFP Package Pinouts
44 43 42 41 40 39 38 37 36 35 34
(HS) MCO3
(HS) MCO4
(HS) MCO5
MCES
PD4 /EXTCLK_A / AIN14 / ICCCLK
PD3 / ICAP1_A / AIN13
1
33
32
31
30
29
28
27
26
25
24
23
2
ei0
PD2 / ICAP2_A / MCZEM / AIN12
PD1 (HS) / OCMP1_A / MCPWMV/MCDEM
PD0 / OCMP2_A / AIN11
3
4
OSC1
5
OSC2
RESET
6
V
_1
SS
V
7
DD_0
V
_1
DD
V
8
SS_0
AIN0 / PWM0 / PA3
AIN1 / ARTIC1 / PA5
MCVREF / PB0
V
9
SSA
ei1
10
11
V
ei2
AREF
PC7 / MCPWMW / AIN7
12 13 14 15 16 17 18 19 20 21 22
(HS) 20mA high sink capability
eix associated external interrupt vector
* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
10/309
1
ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont’d)
Figure 7. 32-Pin LQFP 7x7 Package Pinout
32 31 30 29 28 27 26 25
(HS) MCO3
(HS) MCO4
24
23
22
21
20
19
18
17
PD3 / ICAP1_A / AIN13
1
2
3
4
5
6
7
8
PD2 / ICAP2_A / MCZEM / AIN12
PD1 (HS) / OCMP1_A / MCPWMV / MCDEM
PD0 / OCMP2_A / MCPWMW /AIN11
RESET
ei0
(HS) MCO5
MCES
OSC1
OSC2
V
DD_0
AIN0 / PWM0 / PA3
AIN1 / ARTIC1 / PA5
V
ei2
SS_0
ei1
9 10 11 12 13 14 15 16
V
AREF
(HS) 20mA high sink capability
eix associated external interrupt vector
* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
11/309
1
ST7MC1xx/ST7MC2xx
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, See “ELECTRICAL CHARACTERISTICS” on page 247.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V with Schmitt trigger
T
DD
DD
T = Refer to the G&H ports Characteristics in section 12.8.1 on page 264
T
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt , ana = analog
OD = open drain, PP = push-pull
– Output:
Refer to “I/O PORTS” on page 54 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 1. ST7MC Device Pin Description
Pin n°
Level
Port
Main
function
(after
1)
2)
Input
Output
Pin Name
Alternate function
reset)
1
2
3
4
5
6
7
8
1
2
3
4
-
8
9
1
2
3
4
-
5
6
7
8
-
1
2
3
4
-
MCO3 (HS)
MCO4 (HS)
MCO5 (HS)
O
O
O
I
HS
X
X
X
Motor Control Output 3
Motor Control Output 4
Motor Control Output 5
MTC Emergency Stop
Port G0
HS
HS
10
11
-
3)
MCES
C
X
X
X
X
X
T
T
T
T
T
PG0
PG1
PG2
PG3
I/O T
I/O T
I/O T
I/O T
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
Port G1
-
-
-
-
-
Port G2
-
-
-
-
-
Port G3
External clock input or Resonator
oscillator inverter input
4)
9
5
12
5
9
5
OSC1
I
4)
10
11
12
13
6
7
8
9
13
14
15
-
6
7
8
-
10
-
6
-
OSC2
I/O
S
Resonator oscillator inverter output
Digital Ground Voltage
5)
V
V
ss_1
dd_1
5)
-
-
S
Digital Main Supply Voltage
Port A0 PWM Output 3
Port A1 PWM Output 2
Port A2 PWM Output 1
-
-
PA0/PWM3
PA1/PWM2
PA2PWM1
I/O C
X
X
X
X
X
X
X
X
X
X
X
X
T
14 10 16
15 11
-
-
-
I/O C HS
T
-
-
-
-
I/O C
T
PA3/PWM0/
AIN0
PWM Out- ADC Ana-
Port A3
16 12 17
17 13 18
9
-
11
-
7
-
I/O C
X
X
ei1
X
X
X
X
X
X
T
put 0
log Input 0
PA4 (HS)/ART-
CLK
I/O C HS
Port A4 PWM-ART External Clock
T
PWM-ART
ADC Analog
Port A5 Input Cap-
Input 1
PA5 / ARTIC1/
AIN1
18 14 19 10 12
8
I/O C
X
ei1 X
X
X
T
ture 1
PWM-ART Input Capture
19 15 20
-
-
-
-
-
-
PA6 / ARTIC2 I/O C
X
X
ei1
ei1 X
X
X
X
X
Port A6
2
T
T
20 16
-
PA7/AIN2
I/O C
Port A7 ADC Analog Input 2
12/309
1
ST7MC1xx/ST7MC2xx
Table 1. ST7MC Device Pin Description
Pin n°
Level
Port
Main
1)
function
(after
2)
Input
Output
Pin Name
Alternate function
reset)
21 17 21 11 13
9
PB0/MCVREF I/O C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B0 MTC Voltage Reference
Port B1 MTC Input A
T
T
T
T
22 18 22 12 14 10 PB1/MCIA
23 19 23 13 15 11 PB2/MCIB
24 20 24 14 16 12 PB3/MCIC
I/O C
I/O C
I/O C
Port B2 MTC Input B
Port B3 MTC Input C
SPI Master In / Slave Out
25 21 25 15
-
-
PB4/MISO
I/O C
X
X
X
X
Port B4
Data
T
T
SPI Master
ADC Ana-
PB5/MOSI/
AIN3
26 22 26 16
27 23 27 17
28 24 28 18
-
-
-
-
-
-
I/O C
X
X
X
X
X
X
X
X
X
X
Port B5 Out / Slave
log Input 3
In Data
PB6/SCK
I/O C HS
ei2
Port B6 SPI Serial Clock
T
SPI Slave
ADC Ana-
PB7/SS/AIN4 I/O C HS
ei2
Port B7 Select (ac-
log Input 4
T
tive low)
29
30
31
32
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PG4
PG5
PG6
PG7
PC0
I/O T
I/O T
I/O T
I/O T
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port G4
Port G5
Port G6
Port G7
Port C0
MTC Cur-
T
T
T
T
33 25 29
I/O C HS
ei2
T
6)
PC1/MCCFI0
/AIN5
rent Feed- ADC Ana-
34 26 30
-
-
-
I/O C
X
ei2
X
X
X
Port C1
T
back Input log Input 5
6)
0
35 27 31 19 17 13 PC2/OAP
36 28 32 20 18 14 PC3/OAN
I/O C
I/O C
X
X
ei2 X
X ei2 X
X
X
X
X
Port C2 OPAMP Positive Input
Port C3 OPAMP Negative Input
T
T
MTC Cur-
OAZ/
Opamp rent Feed- ADCanalog
Output back Input Input 6
6)
37 29 33 21 19 15 MCCFI1 /
I/O
X
AIN6
6)
1
MTC Current Feedback
Reference
38 30 34 22 20 16 PC4/MCCREF I/O C
PC5/MCPW-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port C4
9)
T
T
T
39 31 35
-
-
-
I/O C
Port C5 MTC PWM Output U
MU
PC6/
MCPWMV
8)
40 32 36
-
-
-
I/O C
Port C6 MTC PWM Output V
8)
PC7/
ADC Ana-
log
Input 7
MTC PWM
Output W
8)
41 33 37 23
-
-
MCPWMW / I/O C
AIN7
X
X
X
X
Port C7
8)
T
42 34 38 24 21 17
43 35 39 25
V
V
V
V
I
Analog Reference Voltage for ADC
Analog Ground Voltage
AREF
5)
-
-
S
SSA
5)
44 36 40 26 22 18
45 37 41 27 23 19
S
Digital Ground Voltage
SS_0
5)
S
Digital Main Supply Voltage
Top priority non maskable interrupt
DD_0
46 38 42 28 24 20 RESET
I/O C
T
13/309
1
ST7MC1xx/ST7MC2xx
Table 1. ST7MC Device Pin Description
Pin n°
Level
Port
Main
function
(after
1)
2)
Input
Output
Pin Name
Alternate function
reset)
MTC De-
magnetiza- ADC Ana-
PF0/
MCDEM /
AIN8
7)
47 39 43
48 40 44
-
-
-
I/O C
X
X
X
X
X
Port F0
T
tion
Output
log Input 8
7)
7)
PF1/MCZEM /
AIN9
MTC BEMF ADC Ana-
-
-
-
-
-
-
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
Port F1
Port F2
7)
T
T
Output
Main Clock ADC Ana-
Out (f /2) log Input 10
log Input 9
PF2/MCO/
AIN10
49 41
-
osc
50 42 45
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF3/BEEP
PF4
I/O C HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port F3 Beep Signal Output
T
51 43
52 44
-
-
-
-
-
-
I/O C HS
Port F4
Port F5
Port H0
Port H1
Port H2
Port H3
T
PF5
I/O C HS
T
53
54
55
56
-
-
-
-
PH0
I/O T
I/O T
I/O T
I/O T
T
T
T
T
PH1
PH2
PH3
Timer A Output Compare
2
PD0/
OCMP2_A/
MCPWMW /
AIN11
57 45 46 29 25 21
I/O C
X
X
X
X
X
X
X
Port D0
Port D1
8)
8)
T
MTC PWM Output W
ADC Analog Input 11
Timer A Output Compare
1
PD1 (HS)/
OCMP1_A/
MCPWMV /
MCDEM
58 46 47 30 26 22
I/O C HS
ei0
8)
8)
T
MTC PWM Output V
7)
7)
MTC Demagnetization
Timer A Input Capture 2
PD2/ICAP2_A/
7)
7)
59 47 48 31 27 23 MCZEM
AIN12
/
I/O C
I/O C
X
X
ei0
X
X
X
X
X
Port D2 MTC BEMF
T
T
ADC Analog Input 12
Timer A
Port D3 Input
Capture 1
ADC
Analog
Input 13
PD3/ICAP1_A/
AIN13
60 48 49 32 28 24
ei0 X
Timer A External Clock
source
PD4/
61 49 50 33 29 25 EXTCLK_A/IC- I/O C
CCLK/AIN14
X
X
ei0
X
X
X
X
X
X
Port D4
T
T
ICC Clock Output
ADC Analog Input 14
ICC Data Input
PD5/ICCDA-
TA/AIN15
62 50 51 34 30 26
I/O C
ei0
ei0
Port D5
ADC Analog Input 15
63 51 52 35 31 27 PD6/RDI
64 52 53 36 32 28 PD7/TDO
I/O C HS
X
X
X
X
X
X
Port D6 SCI Receive Data In
Port D7 SCI Transmit Data Output
Digital Ground Voltage
Digital Main Supply Voltage
Port H4
T
I/O C HS
X
T
65 53 54
66 54 55
-
-
-
-
-
-
-
-
-
-
-
-
V
V
S
S
SS_2
DD_2
67
68
-
-
-
-
PH4
PH5
I/O T
I/O T
X
X
X
X
X
X
X
X
T
Port H5
T
14/309
1
ST7MC1xx/ST7MC2xx
Table 1. ST7MC Device Pin Description
Pin n°
Level
Port
Main
1)
function
(after
2)
Input
Output
Pin Name
Alternate function
reset)
69
70
-
-
-
-
-
-
-
-
-
-
PH6
PH7
I/O T
I/O T
X
X
X
X
X
X
X
X
Port H6
Port H7
T
T
PE0/
OCMP2_B
Timer B Output Compare
2
71 55 56 37
-
-
-
-
I/O C HS
X
X
X
X
X
X
X
X
Port E0
Port E1
T
PE1/
OCMP1_B
Timer B Output Compare
1
72 56
1
38
I/O C
X
X
T
73 57
74 58
2
3
39
40
-
-
-
-
PE2/ICAP2_B I/O C
PE3/ICAP1_B/ I/O C
X
X
X
X
X
X
X
X
Port E2 Timer B Input Capture 2
Port E3 Timer B Input Capture 1
T
T
PE4/
EXTCLK_B
Timer B External Clock
75 59
76 60
-
-
-
-
-
-
-
-
I/O C
X
X
X
X
X
X
X
X
Port E4
source
T
T
PE5
I/O C
X
Port E5
Must be tied low. In the program-
ming mode when available, this pin
acts as the programming voltage in-
77 61
4
41
1
29
I
V
/ICCSEL
PP
put V ./ ICC mode pin. See section
PP
12.9.2 on page 269
78 62
79 63
80 64
5
6
7
42
43
44
2
3
4
30 MCO0 (HS)
31 MCO1 (HS)
32 MCO2 (HS)
O
O
O
HS
HS
HS
X
X
X
MTC Output Channel 0
MTC Output Channel 1
MTC Output Channel 2
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input
2. If two alternate function outputs are enabled at the same time on a given pin (for instance, MCPWMV
and MCDEM on PD1 on LQFP32), the two signals will be ORed on the output pin.
3. MCES is a floating input. To disable this function, a pull-up resistor must be used.
4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscilla-
tor; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
5. It is mandatory to connect all available V and V
pins to the supply voltage and all VSS and VSSA
DDA
DD
pins to ground.
6. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows:
- either to use PC1 as a standard I/O and map MCCFI on OAZ (MCCFI1) with or without using the oper-
ational amplifier (selected case after reset),
- or to map MCCFI on PC1 (MCCFI0) and use the amplifier for another function.
The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL for
more details.
7. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins.
MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages.
8. MCPWMV is mapped on PC6 on 80 and 64-pin packages and on PD1 on 44,and 32-pins packages.
MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package.
9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the register MCRA), the pin PC4 is configured
15/309
1
ST7MC1xx/ST7MC2xx
to an alternate function. PC4 is no longer usable as a digital I/O.l
10. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up
configuration after reset. The configuration of these pads must be kept at reset state to avoid added cur-
rent consumption. Refer to section 15.7 on page 303
16/309
1
ST7MC1xx/ST7MC2xx
3 REGISTER & MEMORY MAP
As shown in Figure 8, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
The highest address bytes contain the user reset
and interrupt vectors.
The available memory locations consist of 128
bytes of register locations, up to 2Kbytes of RAM
and up to 60Kbytes of user program memory. The
RAM space includes up to 256 bytes for the stack
from 0100h to 01FFh.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
Figure 8. Memory Map
0000h
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
007Fh
0080h
00FFh
0100h
RAM
(1536/1024
768/384 Bytes)
1000h
256 Bytes Stack
60 KBytes
01FFh
0200h
067Fh
0680h
4000h
8000h
16-bit Addressing
RAM
48 KBytes
32 KBytes
Reserved
01FFh
or 037Fh
or 047Fh
or 067Fh
0FFFh
1000h
Program Memory
(60K, 48K, 32K, 16K, 8K)
C000h
16 KBytes
8 KBytes
FFDFh
FFE0h
E000h
FFFFh
Interrupt & Reset Vectors
(see Table 8)
FFFFh
As shown in Figure 9, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
ry. The RAM space includes up to 256 bytes for
the stack from 0100h to 01FFh.
The available memory locations consist of 128
bytes of register locations, up to 1536 bytes of
RAM and up to 60 Kbytes of user program memo-
The highest address bytes contain the user reset
and interrupt vectors.
17/309
1
ST7MC1xx/ST7MC2xx
Table 2. Hardware Register Map
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
R/W
R/W
R/W
Port A
00h
00h
2)
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W
Port B
Port C
Port D
Port E
Port F
Port G
Port H
00h
00h
1)
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
R/W
R/W
R/W
00h
00h
1)
0009h
000Ah
000Bh
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
R/W
R/W
R/W
00h
00h
1)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
R/W
R/W
R/W
2)
2)
00h
00h
1)
000Fh
0010h
0011h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
R/W
R/W
R/W
00h
00h
1)
0012h
0013h
0014h
PGDR
PGDDR
PGOR
Port G Data Register
Port G Data Direction Register
Port G Option Register
00h
R/W
R/W
R/W
00h
00h
1)
0015h
0016h
0017h
PHDR
PHDDR
PHOR
Port H Data Register
Port H Data Direction Register
Port H Option Register
00h
R/W
R/W
R/W
00h
00h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
SCISR
SCIDR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Control Register 3
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
xxh
00h
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCIBRR
SCICR1
SCICR2
SCICR3
SCIERPR
SCIETPR
LINSCI™
0020h
Reserved Area (1 Byte)
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
18/309
1
ST7MC1xx/ST7MC2xx
Table 2. Hardware Register Map
Register
Label
Reset
Address
Block
Register Name
Remarks
Status
0024h
0025h
0026h
0027h
0028h
ITSPR0
ITSPR1
ITSPR2
ITSPR3
EICR
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register
FFh
FFh
FFh
FFh
00h
R/W
R/W
R/W
R/W
R/W
ITC
0029h
FLASH
FSCR
Flash Control/Status Register
00h
7Fh
7Fh
R/W
R/W
R/W
WDGCR
WDGWR
Window Watchdog Control Register
Window Watchdog Window Register
002Ah
002Bh
WATCHDOG
002Ch
002Dh
MCCSR
MCCBCR
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
00h
00h
R/W
R/W
MCC
ADC
002Eh
002Fh
0030h
ADCCSR
ADCDRMSB Data Register MSB
ADCDRLSB Data Register LSB
Control/Status Register
00h
00h
00h
R/W
Read Only
Read Only
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TACLR
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
SIM
SICSR
System Integrity Control/Status Register
000x000x b R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
19/309
1
ST7MC1xx/ST7MC2xx
Table 2. Hardware Register Map
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
MTIM
Timer Counter High Register
Timer Counter Low Register
Capture Zn-1 Register
Capture Zn Register
Compare Cn+1 Register
Demagnetization Register
An Weight Register
Prescaler & Sampling Register
Interrupt Mask Register
Interrupt Status Register
Control Register A
Control Register B
Control Register C
Phase State Register
D event Filter Register
Current feedback Filter Register
Reference Register
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0Fh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0Fh
FFh
R/W
MTIML
MZPRV
MZREG
MCOMP
MDREG
MWGHT
MPRSR
MIMR
MISR
MCRA
MCRB
MCRC
MPHST
MDFR
MCFR
MREF
MPCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MTC
(page 0)
PWM Control Register
MREP
Repetition Counter Register
Compare Phase W Preload Register High
Compare Phase W Preload Register Low
Compare Phase V Preload Register High
Compare Phase V Preload Register Low
Compare Phase U Preload Register High
Compare Phase U Preload Register Low
Compare Phase 0 Preload Register High
Compare Phase 0 Preload Register Low
MCPWH
MCPWL
MCPVH
MCPVL
MCPUH
MCPUL
MCP0H
MCP0L
0050h
0051h
0052h
0053h
0054h
0055h
0056h
MDTG
MPOL
MPWME
MCONF
MPAR
MZRF
Dead Time Generator Enable
Polarity Register
PWM Register
Configuration Register
Parity Register
Z event Filter Register
Sampling Clock Register
FFh
3Fh
00h
02h
00h
0Fh
00h
MTC
(page 1)
see MTC
description
MSCR
0057h to
006Ah
Reserved Area (4 Bytes)
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
Debug Control Register
Debug Status Register
Debug Breakpoint 1 MSB Register
Debug Breakpoint 1 LSB Register
Debug Breakpoint 2 MSB Register
Debug Breakpoint 2 LSB Register
00h
10h
FFh
FFh
FFh
FFh
R/W
Read Only
R/W
R/W
R/W
DM
R/W
20/309
1
ST7MC1xx/ST7MC2xx
Table 2. Hardware Register Map
Register
Label
Reset
Address
Block
Register Name
Remarks
Status
0074h
0075h
0076h
0077h
0078h
PWMDCR3 PWM AR Timer Duty Cycle Register 3
PWMDCR2 PWM AR Timer Duty Cycle Register 2
PWMDCR1 PWM AR Timer Duty Cycle Register 1
PWMDCR0 PWM AR Timer Duty Cycle Register 0
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
PWMCR
PWM AR Timer Control Register
0079h
007Ah
007Bh
PWM ART
ARTCSR
ARTCAR
ARTARR
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
00h
00h
00h
R/W
R/W
R/W
007Ch
007Dh
007Eh
ARTICCSR AR Timer Input Capture Control/Status Reg.
00h
00h
00h
R/W
Read Only
Read Only
ARTICR1
ARTICR2
AR Timer Input Capture Register 1
AR Timer Input Capture Register 2
007Fh
OPAMP
OACSR
OPAMP Control/Status Register
00h
R/W
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
21/309
1
ST7MC1xx/ST7MC2xx
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba-
sis using an external V supply.
PP
The first two sectors have a fixed size of 4 Kbytes
(see Figure 9). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
Table 3. Sectors available in Flash devices
Flash Size (bytes)
Available Sectors
4K
8K
Sector 0
Sectors 0,1
Sectors 0,1, 2
4.2 MAIN FEATURES
■ 3 Flash programming modes:
> 8K
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
4.3.1 Read-out Protection
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
Read-out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry. Even if no protection can be considered as to-
tally unbreakable, the feature provides a very high
level of protection for a general purpose microcon-
troller.
In Flash devices, this protection is removed by re-
programming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection
■ Register Access Security System (RASS) to
Read-out protection selection depends on the de-
vice type:
prevent accidental programming or erasing
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
4.3 STRUCTURE
The Flash memory is organised in sectors and can
be used for both code and data storage.
– In ROM devices it is enabled by mask option
specified in the Option List.
Figure 9. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
22/309
1
ST7MC1xx/ST7MC2xx
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC INTERFACE
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
ICC (In-Circuit Communication) needs a minimum
of four and up to six pins to be connected to the
programming tool (see Figure 10). These pins are:
– ICCSEL/V : programming voltage
PP
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
– RESET: device reset
– V : application board power supply (see Fig-
DD
– V : device power supply ground
ure 10, Note 3)
SS
Figure 10. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
(See Note 3)
OPTIONAL
HE10 CONNECTOR TYPE
9
7
5
6
3
1
2
(See Note 4)
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
C
C
L2
L1
See Note 1
APPLICATION
I/O
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
agement IC with open drain output and pull-up
resistor > 1K, no additional components are need-
ed. In all cases the user must ensure that no exter-
nal reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R > 1K or a reset man-
4. Pin 9 has to be connected to the OSC1 or OS-
CIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
23/309
1
ST7MC1xx/ST7MC2xx
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (IN-CIRCUIT PROGRAMMING)
4.7 RELATED DOCUMENTATION
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
4.8 REGISTER DESCRIPTION
FLASH CONTROL/STATUS REGISTER (FCSR)
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 10). For more details
on the pin locations, refer to the device pinout de-
scription.
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
0
4.6 IAP (IN-APPLICATION PROGRAMMING)
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI or
other type of serial interface and program it in the
Flash. IAP mode can be used to program any of
the Flash sectors except Sector 0, which is write/
erase protected to allow recovery in case errors
occur during the programming operation.
24/309
1
ST7MC1xx/ST7MC2xx
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The six CPU registers shown in Figure 11 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power Halt and Wait modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 11. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE =
8
1
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
25/309
1
ST7MC1xx/ST7MC2xx
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
Reset Value: 111x1xxx
7
0
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred.
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
26/309
1
ST7MC1xx/ST7MC2xx
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 12.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 12).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 12. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
27/309
1
ST7MC1xx/ST7MC2xx
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 13.
Main features
■ Reset Sequence Manager (RSM)
■ 1 Crystal/Ceramic resonator oscillator
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
For more details, refer to dedicated parametric
section.
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
– Clock Security System (CSS) with the VCO of
the PLL, providing a backup safe oscillator
– Clock Detector
– PLL which can be used to multiply the fre-
quency by 2 if the clock frequency input is
8MHz
Figure 13. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT
f
OSC
f
CLOCK SECURITY SYSTEM
f
MAIN CLOCK
CONTROLLER
WITH REALTIME
CPU
CLK
PLL
f
MTC
8Mhz
16Mhz
lock
OSC2
OSC1
CLOCK (MCC/RTC)
1/2
Safeosc
OSCILLATOR
f
OSC
DIV2 OPT
CKSEL
SICSR, page 1
VCO
EN CK EN
CK
SEL
LO PLL
PA
GE
0
0
0
Clock Detector
RESET SEQUENCE
MANAGER
WATCHDOG
TIMER (WDG)
AVD Interrupt Request
RESET
SICSR, page 0
PA
GE IE
CSS CSS
IE
AVD AVD
LVD
RF
WDG
D
RF
(RSM)
0
F
CSS Interrupt Request
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
*
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
* It is recommended to decouple the power supply by placing a 0.1µF capacitor as close as possible to V
DD
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1
ST7MC1xx/ST7MC2xx
6.1 OSCILLATOR
The main clock of the ST7 can be generated by a
crystal or ceramic resonator oscillator or an exter-
nal source.
Table 4. ST7 Clock Sources
Hardware Configuration
The associated hardware configurations are
shown in Table 4. Refer to the electrical character-
istics section for more details.
ST7
OSC1
OSC2
NC
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is not connect-
ed.
EXTERNAL
SOURCE
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. In this mode, the resonator and the load
capacitors have to be placed as close as possible
to the oscillator pins in order to minimize output
distortion and start-up stabilization time.
ST7
OSC1
OSC2
This oscillator is not stopped during the RESET
phase to avoid losing time in its start-up phase.
C
C
L2
L1
LOAD
CAPACITORS
See Electrical Characteristics for more details.
Note: When crystal oscillator is used as a clock
source, a risk of failure may exist if no series resis-
tors are implemented.
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1
ST7MC1xx/ST7MC2xx
6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application.
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
The RESET vector fetch phase duration is 2 clock
cycles.
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 11.2.1 on page 244 for further de-
tails.
Figure 14. RESET Sequence Phases
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
RESET
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
Active Phase
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (selected by
option byte)
■ RESET vector fetch
6.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
A RESET signal originating from an external
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 16). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in Halt mode.
Figure 15. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET 1)
LVD RESET
PULSE
GENERATOR
Note 1: See “Illegal Opcode Reset” on page 244. for more details on illegal opcode reset conditions.
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1
ST7MC1xx/ST7MC2xx
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.2.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
6.2.3 External Power-On RESET
■ Voltage Drop RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 16.
DD
IT-
signal is held low until V
is over the minimum
DD
The LVD filters spikes on V larger than t
to
level specified for the selected f
frequency.
DD
g(VDD)
OSC
avoid parasitic resets.
A proper reset signal for a slow rising V supply
DD
can generally be provided by an external RC net-
work connected to the RESET pin.
6.2.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Figure 16. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU
VECTOR FETCH
)
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ST7MC1xx/ST7MC2xx
6.3 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD), Auxiliary Voltage
Detector (AVD) and Clock Security System (CSS)
functions. It is managed by the SICSR register.
The LVD function is illustrated in Figure 17.
Provided the minimum V value (guaranteed for
DD
the oscillator frequency) is above V , the MCU
IT-
can only be in two modes:
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 11.2.1 on page 244 for further de-
tails.
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
6.3.1 Low Voltage Detector (LVD)
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
The Low Voltage Detector function (LVD) gener-
ates a static reset when the V supply voltage is
DD
below a V reference value. This means that it
IT-
secures the power-up as well as the power-down
keeping the ST7 in reset.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
The V reference value for a voltage drop is lower
IT-
than the V reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD is an optional function which can be se-
lected by option byte.
The LVD Reset circuitry generates a reset when
DD
It is recommended to make sure that the V sup-
DD
V
is below:
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
– V when V is rising
IT+
DD
– V when V is falling
IT-
DD
Figure 17. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
IT-
RESET
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ST7MC1xx/ST7MC2xx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.3.2 Auxiliary Voltage Detector (AVD)
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 18.
The Voltage Detector function (AVD) is based on
an analog comparison between a V
and
IT-(AVD)
V
reference value and the V
main sup-
IT+(AVD)
DD
ply. The V reference value for falling voltage is
The interrupt on the rising edge is used to inform
IT-
lower than the V reference value for rising volt-
the application that the V warning state is over.
IT+
DD
age in order to avoid parasitic detection (hystere-
sis).
If the voltage rise time t is less than 256 or 4096
rv
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
The output of the AVD comparator is directly read-
able by the application software through a real-
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte (see sec-
tion 14.1 on page 290).
ated when V
is reached.
IT+(AVD)
If t is greater than 256 or 4096 cycles then:
rv
– If the AVD interrupt is enabled before the
V
threshold is reached, then 2 AVD inter-
IT+(AVD)
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
6.3.2.1 Monitoring the V Main Supply
DD
If the AVD interrupt is enabled, an interrupt is gen-
– If the AVD interrupt is enabled after the V
threshold is reached then only one AVD interrupt
will occur.
IT+(AVD)
erated when the voltage crosses the V
or
IT+(AVD)
V
threshold (AVDF bit toggles).
IT-(AVD)
Figure 18. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
t
VOLTAGE RISE TIME
rv
IT-(LVD)
AVDF bit
0
1
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
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ST7MC1xx/ST7MC2xx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.3.3 Clock Security System (CSS)
6.3.4 Low Power Modes
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a PLL which can provide a
backup clock. The PLL can be enabled or disabled
by option byte or by software. It requires an 8-MHz
input clock and provides a 16-MHz output clock.
Mode
Wait
Description
No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.
The CRSR register is frozen.
The CSS (including the safe oscillator) is
disabled until Halt mode is exited. The pre-
vious CSS configuration resumes when the
MCU is woken up by an interrupt with “exit
from Halt mode” capability or from the coun-
ter reset value when the MCU is woken up
by a RESET. The AVD remains active, and
an AVD interrupt can be used to exit from
Halt mode.
6.3.3.1 Safe Oscillator Control
Halt
The safe oscillator of the CSS block is made of a
PLL.
If the clock signal disappears (due to a broken or
disconnected resonator...) the PLL continues to
provide a lower frequency, which allows the ST7 to
perform some rescue operations.
6.3.4.1 Interrupts
Note: The clock signal must be present at start-up.
Otherwise, the ST7MC will not start and will be
maintained in RESET conditions.
The CSS or AVD interrupt events generate an in-
terrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).
6.3.3.2 Limitation detection
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the SICSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
Enable Exit
Control from
Bit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
These two bits are described in the SICSR register
description.
CSS event detection
(safe oscillator acti- CSSD CSSIE
vated as main clock)
1)
Yes
Yes
No
AVD event
AVDF AVDIE
Yes
Note 1: This interrupt allows to exit from Active-
halt mode.
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ST7MC1xx/ST7MC2xx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.3.5 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 0)
Read/Write
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the PLL is disabled (PLLEN=0), the CSSIE
bit has no effect.
Reset Value: 000x 000x (00h)
7
0
AVD
IE
PAG
E
AVD LVD
RF
CSS CSS WDG
0
F
IE
D
RF
Bit 1 = CSSD Clock security system detection
This bit indicates a disturbance on the main clock
Bit 7 = PAGE SICSR Register Page Selection
This bit selects the SICSR register page. It is set
and cleared by software
0: Access to SICSR register mapped in page 0.
1: Access to SICSR register mapped in page 1.
signal (f
): the clock stops (at least for a few cy-
OSC
cles). It is set by hardware and cleared by reading
the SICSR register when the original oscillator re-
covers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the PLL is disabled (PLLEN=0), the CSSD
bit value is forced to 0.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the AVD interrupt routine.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
0: AVD interrupt disabled
1: AVD interrupt enabled
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the VDIE bit is set, an interrupt request is gener-
ated when the AVDF bit changes value.
Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET Sources
LVDRF WDGRF
0: V over V
threshold
threshold
IT-(AVD)
DD
IT+ (AVD)
1: V under V
External RESET pin
Watchdog
0
0
1
0
1
DD
LVD
X
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Bit 3 = Reserved, must be kept cleared.
Bit 2 = CSSIE Clock security syst
.
interrupt enable
This bit enables the interrupt when a disturbance
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ST7MC1xx/ST7MC2xx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1)
Reset Value: 00000000 (00h)
Bit 3 = PLLEN PLL Enable
This bit enables the PLL and the clock detector. It
is set and cleared by software.
7
0
0
0: PLL and Clock Detector (CKD) disabled
1: PLL and Clock Detector (CKD) enabled
VCO LO
EN CK
PLL
EN
PA
GE
CK-
SEL
0
0
Notes:
1. During ICC session, this bit is set to 1.
2. PLL cannot be disabled if PLL clock source is
selected (CKSEL= 1).
Bit 7 = PAGE SICSR Register Page Selection
This bit selects the SICSR register page. It is set
and cleared by software
0: Access to SICSR register mapped in page 0.
1: Access to SICSR register mapped in page 1.
Bit 2 = Reserved, must be kept cleared.
Bit 6 = Reserved, must be kept cleared.
Bit 1 = CKSEL Clock Source Selection
This bit selects the clock source: oscillator clock or
clock from the PLL. It is set and cleared by soft-
ware. It can also be set by option byte (PLL opt)
0: Oscillator clock selected
Bit 5 = VCOEN VCO Enable
This bit is set and cleared by software.
0: VCO (Voltage Controlled Oscillator) connected
to the output of the PLL charge pump (default
mode), to obtain a 16-MHz output frequency
(with an 8-MHz input frequency).
1: PLL clock selected
Notes:
1. During ICC session, this bit is set to 1. Then,
1: VCO tied to ground in order to obtain a 10-MHz
CKSEL can be reset in order to run with f
.
OSC
frequency (f
)
vco
2. Clock from the PLL cannot be selected if the
PLL is disabled (PLLEN =0)
3. If the clock source is selected by PLL option bit,
CKSEL bit selection has no effect.
Notes:
1. During ICC session, this bit is set to 1 in order to
have an internal frequency which does not depend
on the input clock. Then, it can be reset in order to
run faster with an external oscillator.
Bit 0 = Reserved, must be kept cleared.
Bit 4 = LOCK PLL Locked
This bit is read only. It is set by hardware. It is set
automatically when the PLL reaches its operating
frequency.
0: PLL not locked
1: PLL locked
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ST7MC1xx/ST7MC2xx
6.4
MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin sus-
pends the clock during Active-halt mode.
■
a programmable CPU clock prescaler
■
a clock-out signal to supply external devices
6.4.3
Real-time Clock Timer (RTC)
■
a real-time clock timer with interrupt capability
The counter of the real-time clock timer allows an
interrupt to be generated based on an accurate
real-time clock. Four different time bases depend-
Each function can be used independently and si-
multaneously.
6.4.1
Programmable CPU Clock Prescaler
ing directly on f
are available. The whole
OSC2
functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages Slow power saving mode (See
Section 8.2 SLOW MODE for more details).
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters Active-halt mode when the HALT
instruction is executed. See Section 8.4 ACTIVE-
HALT AND HALT MODES for more details.
The prescaler selects the f
main clock frequen-
CPU
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
6.4.4
Beeper
6.4.2
Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f clock to drive
The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).
OSC2
Figure 19.
Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0
MCCBCR
BEEP
MCO
BEEP SIGNAL
GENERATOR
RTC
DIV128
COUNTER
MCCSR
MCO
CP0 SMS TB1 TB0 OIE OIF
MCC/RTC INTERRUPT
(AND TO MTC
PERIPHERAL)
fCLK
fOSC2
DIV 2, 4, 8, 16
DIV 2, 4, 8, 16
DIV 2
CPU CLOCK
TO CPU AND
PERIPHERALS
fCPU
DIV 2
fADC
TO MOTOR
CONTROL
PERIPHERAL
fMTC
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ST7MC1xx/ST7MC2xx
MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d)
6.4.5
Low Power Modes
Bit 6:5 = CP[1:0] CPU clock prescaler
Mode
Description
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from Wait mode.
Wait
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from Active-halt mode.
f
in Slow mode
CP1
CP0
Active-
halt
CPU
f
f
f
/ 2
/ 4
0
0
1
1
0
1
0
1
OSC2
OSC2
OSC2
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from Halt” capability.
/ 8
Halt
f
/ 16
OSC2
6.4.6
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = f
Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
OSC2
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
See Section 8.2 SLOW MODE and Section 6.4
MAIN CLOCK CONTROLLER WITH REAL-TIME
CLOCK AND BEEPER (MCC/RTC) for more de-
tails.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Time base overflow
event
1)
Bit 3:2 = TB[1:0] Time base control
OIF
OIE
Yes
No
These bits select the programmable divider time
base. They are set and cleared by software.
Note:
The MCC/RTC interrupt wakes up the MCU from
Active-halt mode, not from Halt mode.
Time Base
Counter
TB1 TB0
Prescaler
f
=4MHz
f
=8MHz
OSC2
OSC2
16000
32000
80000
200000
4ms
2ms
4ms
0
0
1
1
0
1
0
1
8ms
20ms
50ms
6.4.7
Register Description
10ms
25ms
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
Reset Value: 0000 0000 (00h
)
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real-time clock.
7
0
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active-halt
mode.
1: MCO alternate function enabled (f
port)
on I/O
OSC2
When this bit is set, calling the ST7 software HALT
instruction enters the Active-halt power saving
mode
.
Note: To reduce power consumption, the MCO
function is not active in Active-halt mode.
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ST7MC1xx/ST7MC2xx
MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d)
MCC BEEP CONTROL REGISTER (MCCBCR)
Read/Write
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
Reset Value: 0000 0000 (00h)
7
0
0
0: Timeout not reached
1: Timeout reached
AD- ADC
STS IE
0
0
0
BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Bit 7:4 = Reserved, must be kept cleared.
Bit 3 = ADSTS A/D Converter Sample Time
Stretch
This bit is set and cleared by software to enable or
disable the A/D Converter sample time stretch fea-
ture.
0: AD sample time stretch disabled (for standard
impedance analog inputs)
1 AD sample time stretch enabled (for high imped-
ance analog inputs)
Bit 2 = ADCIE A/D Converter Interrupt Enable
This bit is set and cleared by software to enable or
disable the A/D Converter interrupt.
0: AD Interrupt disabled
1 AD Interrupt enabled
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1
BC0
Beep mode with f
=8MHz
OSC2
0
0
1
1
0
1
0
1
Off
~2-KHz
Output
Beep signal
~50% duty cycle
~1-KHz
~500-Hz
The beep output signal is available in Active-halt
mode but has to be disabled to reduce the con-
sumption.
Table 5. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR, page0
Reset Value
PAGE
0
VDIE
0
VDF
0
LVDRF
x
CFIE
0
CSSD
0
WDGRF
x
0040h
0040h
002Ch
002Dh
0
SICSR, page1
Reset Value
PAGE
0
VCOEN
0
LOCK
x
PLLEN
0
CKSEL
0
0
0
0
MCCSR
Reset Value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
MCCBCR
Reset Value
ADSTS
0
ADCIE
0
BC1
0
BC0
0
0
0
0
0
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ST7MC1xx/ST7MC2xx
7 INTERRUPTS
7.1 INTRODUCTION
each interrupt vector (see Table 6). The process-
ing flow is shown in Figure 20
The ST7 enhanced interrupt management pro-
vides the following features:
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable top level event: MCES
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 6. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
I0
0
7.2 MASKING AND PROCESSING FLOW
Level 0 (main)
Level 1
Low
0
1
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
Level 2
0
0
Level 3 (= interrupt disable)
High
1
1
Figure 20. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
MCES
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
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1
ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
ing to the flowchart in Figure 20 as a MCES top
level interrupt.
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
See the RESET chapter for more details.
Figure 21 describes this decision process.
Maskable Sources
Figure 21. Priority Decision Process
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
PENDING
INTERRUPTS
Different
Same
SOFTWARE
PRIORITY
■ MCES (MTC Emergency Stop)
This hardware interrupt occurs when a specific
edge is detected on the dedicated MCES pin or
when an error is detected by the micro in the motor
speed measurement. The interrupt request is
maintained as long as the MCES pin is low if the
interrupt is enabled by the EIM bit in the MIMR reg-
ister.
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
■ External Interrupts
External interrupts allow the processor to exit from
Halt low power mode.
External interrupt sensitivity is software selectable
through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and MCES can be consid-
ered as having the highest software priority in the
decision process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from Halt mode except those mentioned in the
“Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 20). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit Halt
mode.
■ TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
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ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the Wait
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the Halt modes (see column “Exit from
Halt” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting Halt
mode, the first one serviced can only be an inter-
rupt with exit from Halt mode capability and it is se-
lected through the same decision process shown
in Figure 21.
The following Figure 22 and Figure 23 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 23. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, MCES. The software priority
is given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced
after the first one serviced.
Figure 22. Concurrent Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
MCES
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 23. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
MCES
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
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1
ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level
I1
1
I0
0
Level 0 (main)
Level 1
Low
These four registers contain the interrupt software
priority of each interrupt vector.
0
1
Level 2
0
0
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondence is shown in the following table.
Level 3 (= interrupt disable*)
High
1
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFE1h-FFE0h
I1_13 and I0_13 bits
*Note: MCES, TRAP and RESET events can in-
terrupt a level 3 program.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, TRAP and MCES vectors have no
software priorities. When one is serviced, the I1
and I0 bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the MCES can be read and written but
they are not significant in the interrupt process
management.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
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ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
Table 7. Dedicated Interrupt Instruction Set
Instruction
New Description
Entering Halt mode
Function/Example
I1
H
I0
N
Z
C
HALT
IRET
JRM
1
0
Interrupt routine return
Jump if I1:0=11 (level 3)
Jump if I1:0<>11
Pop CC, A, X, PC
I1:0=11 ?
I1
H
I0
N
Z
C
JRNM
POP CC
RIM
I1:0<>11 ?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
1
TRAP
WFI
1
Wait for interrupt
1
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
Table 8. Interrupt Mapping
Exit
from
Halt
Source
Block
Register
Label
Priority
Order
Address
Vector
N°
Description
1)
RESET
TRAP
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
N/A
Software interrupt
Motor Control Emergency Stop
or Speed error interrupt
MISR
MCRC
0
1
MCES
no
FFFAh-FFFBh
FFF8h-FFF9h
Highest
Priority
MCC/RTC Main clock controller time base interrupt
MCCSR
SICSR
yes
CSS
Safe oscillator activation interrupt
2
3
ei0
External interrupt port
yes
yes
yes
no
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
ei1
External interrupt port
N/A
4
ei2
External interrupt port
5
Event U or Current Loop or Sampling Out MISR/MCONF
6
MTC
Event R or Event Z
MISR
no
7
Event C or Event D
no
8
SPI
SPI peripheral interrupts
SPICSR
TASR
yes
no
9
TIMER A
TIMER B
TIMER A peripheral interrupts
TIMER B peripheral interrupts
10
11
TBSR
no
Lowest
Priority
LINSCI™ LINSCI™ Peripheral interrupts
AVD/
ADC
SCISR
no
Auxiliary Voltage detector interrupt
ADC End of conversion interrupt
SICSR
ADCSR
12
13
yes
no
FFE2h-FFE3h
FFE0h-FFE1h
PWM ART overflow interrupt
PWM ART input capture interrupts
ARTCSR
ARTICCSR
PWM ART
Note 1. Valid for Halt and Active-halt modes except for the MCC/RTC or CSS interrupt source which exits from Active-
halt mode only.
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ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
The pending interrupts are cleared writing a differ-
ent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
Note: External interrupts are masked when an I/O
■ Rising edge
(configured as input interrupt) of the same inter-
■ Falling and rising edge
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
rupt vector is forced to V
.
SS
7.6.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 24). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3).
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1
ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
Figure 24. External Interrupt Control bits
EICR
IS30 IS31
PORT D [6:4] INTERRUPTS
PDOR.6
PDDDR.6
SENSITIVITY
CONTROL
PD6
PD5
PD6
ei0 INTERRUPT SOURCE
PD4
IPA BIT
EICR
PORT D [3:1] INTERRUPTS
IS30
IS31
PDOR.3
PDDDR.3
SENSITIVITY
CONTROL
PD3
PD2
PD1
ei0 INTERRUPT SOURCE
PD3
EICR
PORT A3, PORT A[7:5] INTERRUPTS
IS20
IS21
PAOR.7
PADDR.7
SENSITIVITY
CONTROL
PA7
PA6
PA5
PA3
PA7
ei1 INTERRUPT SOURCE
EICR
PORT C [3:1] INTERRUPTS
IS10
IS11
PCOR.3
PCDDR.3
SENSITIVITY
CONTROL
PC3
PC3
ei2 INTERRUPT SOURCE
PC2
PC1
IPB BIT
EICR
PORT C0, PORT B[7:6] INTERRUPTS
IS10
IS11
PCOR.0
PCDDR.0
SENSITIVITY
CONTROL
PC0
ei2 INTERRUPT SOURCE
PC0
PB7
PB6
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1
ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read/Write
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Reset Value: 0000 0000 (00h)
Bit 5 = IPB Interrupt polarity for port C
7
0
This bit is used to invert the sensitivity of the port
C[3:1] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
IS11 IS10 IPB IS21 IS20 IS31 IS30 IPA
0: No sensitivity inversion
Bit 7:6 = IS1[1:0] ei2 sensitivity
1: Sensitivity inversion
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port C3..1)
Bit 4:3= IS2[1:0] ei1sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
- ei1 (port A3, A5...A7)
External Interrupt Sensitivity
IS11 IS10
IPB bit =0
IPB bit =1
Falling edge &
low level
Rising edge
& high level
0
0
IS21 IS20
External Interrupt Sensitivity
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Rising and falling edge
Falling edge only
Rising and falling edge
- ei2 (port C0, B7..6)
IS11 IS10
External Interrupt Sensitivity
Bit 2:1= IS3[1:0] ei0sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
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1
ST7MC1xx/ST7MC2xx
EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont’d)
- ei0 (port D6..4)
Bit 0 = IPA Interrupt polarity for port D
External Interrupt Sensitivity
This bit is used to invert the sensitivity of the port D
[6:4] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
IS31 IS30
IPA bit =0
IPA bit =1
Falling edge &
low level
Rising edge
& high level
0
0
0: No sensitivity inversion
1: Sensitivity inversion
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
Rising and falling edge
- ei0 (port D3..1)
IS31 IS30
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
48/309
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ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
Table 9. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ei1
ei0
MCC + SI
MCES
ei2
0024h
0025h
0026h
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
ISPR0
Reset Value
1
1
MTC C/D
MTC R/Z
MTC U/CL
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
ISPR1
Reset Value
SCI
TIMER B
TIMER A
SPI
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
ISPR2
Reset Value
PWMART
AVD
0027h
0028h
I1_15
1
I0_15
1
I1_14
1
I0_14
1
I1_13
1
I0_13
1
I1_12
1
I0_12
1
ISPR3
Reset Value
EICR
Reset Value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
0
0
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ST7MC1xx/ST7MC2xx
8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 25): Slow, Wait (Slow-wait), Active-
halt and Halt.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (Run mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
Slow mode is controlled by three bits in the MCC-
SR register: the SMS bit which enables or disables
Slow mode and two CPx bits which select the in-
ternal slow frequency (f
).
CPU
(f
).
In this mode, the master clock frequency (f
)
OSC2
OSC2
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
CPU
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
(f
).
Note: Slow-wait mode is activated when entering
the Wait mode while the device is already in Slow
mode.
Figure 25. Power Saving Mode Transitions
Figure 26. Slow Mode Clock Transitions
High
RUN
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
f
OSC2
SLOW
WAIT
00
01
CP1:0
SMS
SLOW WAIT
ACTIVE HALT
HALT
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
Low
POWER CONSUMPTION
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ST7MC1xx/ST7MC2xx
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
Figure 27. Wait Mode Flow-chart
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
10
WFI INSTRUCTION
I[1:0] BITS
All peripherals remain active. During Wait mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
Wait mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
10
Refer to Figure 27.
I[1:0] BITS
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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1
ST7MC1xx/ST7MC2xx
POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
Figure 28. Active-halt Timing Overview
Active-halt and Halt modes are the two lowest
power consumption modes of the MCU. They are
both entered by executing the ‘HALT’ instruction.
The decision to enter either in Active-halt or Halt
mode is given by the MCC/RTC interrupt enable
flag (OIE bit in MCCSR register).
ACTIVE
HALT
256 OR 4096 CPU
CYCLE DELAY
RUN
RUN
1)
RESET
OR
HALT
INSTRUCTION
[MCCSR.OIE=1]
INTERRUPT
FETCH
VECTOR
MCCSR Power Saving Mode entered when HALT
OIE bit
instruction is executed
Halt mode
Active-halt mode
Figure 29. Active-halt Mode Flow-chart
0
1
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
OFF
10
2)
HALT INSTRUCTION
(MCCSR.OIE=1)
8.4.1 ACTIVE-HALT MODE
I[1:0] BITS
Active-halt mode is the lowest power consumption
mode of the MCU with a real-time clock available.
It is entered by executing the ‘HALT’ instruction
when the OIE bit of the Main Clock Controller Sta-
tus register (MCCSR) is set (see section 6.4 on
page 37 for more details on the MCCSR register).
N
RESET
N
Y
INTERRUPT 3)
The MCU can exit Active-halt mode on reception
of either an MCC/RTC interrupt, a specific inter-
rupt (see Table 8, “Interrupt Mapping,” on
page 44) or a RESET. When exiting Active-halt
mode by means of an interrupt, no 256 or 4096
CPU cycle delay occurs. The CPU resumes oper-
ation by servicing the interrupt or by fetching the
reset vector which woke it up (see Figure 29).
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
Y
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
When entering Active-halt mode, the I[1:0] bits in
the CC register are forced to ‘10b’ to enable inter-
rupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
In Active-halt mode, only the main oscillator and its
associated counter (MCC/RTC) are running to
keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits Active-
halt mode by means of a RESET.
2. Peripheral clocked with an external clock source
The safeguard against staying locked in Active-
halt mode is provided by the oscillator interrupt.
can still be active.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering Active-halt mode while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
3. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from Active-halt mode
(such as external interrupt). Refer to Table 8, “In-
terrupt Mapping,” on page 44 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
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1
ST7MC1xx/ST7MC2xx
POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
Figure 31. Halt Mode Flow-chart
The Halt mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see section 6.4 on page 37 for more de-
tails on the MCCSR register).
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WATCHDOG
DISABLE
0
WDGHALT 1)
1
The MCU can exit Halt mode on reception of either
a specific interrupt (see Table 8, “Interrupt Map-
ping,” on page 44) or a RESET. When exiting Halt
mode by means of a RESET or an interrupt, the
oscillator is immediately turned on and the 256 or
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 31).
WATCHDOG
RESET
OSCILLATOR
OFF
OFF
OFF
10
PERIPHERALS 2)
CPU
I[1:0] BITS
When entering Halt mode, the I[1:0] bits in the CC
register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
N
RESET
Y
N
INTERRUPT 3)
In Halt mode, the main oscillator is turned off caus-
ing all internal processing to be stopped, including
the operation of the on-chip peripherals. All periph-
erals are not clocked except the ones which get
their clock supply from another clock generator
(such as an external or auxiliary oscillator).
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I[1:0] BITS
XX 4)
The compatibility of Watchdog operation with Halt
mode is configured by the “WDGHALT” option bit
of the option byte. The HALT instruction when ex-
ecuted while the Watchdog system is enabled, can
generate a Watchdog RESET (see section 14.1 on
page 290 for more details).
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
Figure 30. Halt Timing Overview
I[1:0] BITS
XX 4)
256 OR 4096 CPU
CYCLE DELAY
RUN
HALT
RUN
FETCH RESET VECTOR
OR SERVICE INTERRUPT
RESET
OR
INTERRUPT
Notes:
HALT
INSTRUCTION
[MCCSR.OIE=0]
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from Halt mode (such as external interrupt). Refer
to Table 8, “Interrupt Mapping,” on page 44 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
53/309
1
ST7MC1xx/ST7MC2xx
9 I/O PORTS
9.1 INTRODUCTION
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt sources, these
are first detected according to the sensitivity bits in
the EICR register and then logically ORed.
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
9.2 FUNCTIONAL DESCRIPTION
Each port has two main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: Bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 32
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
V
9.2.1 Input Modes
SS
1
V
Floating
DD
The input configuration is selected by clearing the
corresponding DDR register bit.
9.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Different input modes can be selected by software
through the OR register.
Notes:
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register as this might
corrupt the DR content for I/Os configured as input.
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
54/309
1
ST7MC1xx/ST7MC2xx
I/O PORTS (Cont’d)
Figure 32. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
x
Table 10. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Note: The diode to V is not implemented in the
DD
Off - implemented not activated
On - implemented and activated
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
55/309
1
ST7MC1xx/ST7MC2xx
I/O PORTS (Cont’d)
Table 11. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
56/309
1
ST7MC1xx/ST7MC2xx
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Figure 33. Interrupt I/O Port State Transitions
01
00
10
11
Analog alternate function
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
= DDR, OR
XX
9.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Mode
Wait
Halt
Description
No effect on I/O ports. External interrupts
cause the device to exit from Wait mode.
No effect on I/O ports. External interrupts
cause the device to exit from Halt mode.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 33 on page 57. Other
transitions are potentially risky and should be
avoided, since they are likely to present unwanted
side-effects such as spurious interrupt generation.
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
57/309
1
ST7MC1xx/ST7MC2xx
I/O PORTS (Cont’d)
9.5.1 I/O Port Implementation
Interrupt Ports
The I/O port register configurations are summa-
rised as follows.
PA6, PA3, PB6, PC3, PC1, PD5, PD4, PD2 (with
pull-up)
MODE
DDR
OR
0
Standard Ports
floating input
0
0
1
1
PA4, PA2:0, PB5:0, PC7:4,
PD7:6, PE5:0, PF5:0, PG7:0, PH7:0
pull-up interrupt input
open drain output
push-pull output
1
0
MODE
DDR
OR
0
1
floating input
pull-up input
0
0
1
1
1
open drain output
push-pull output
0
PA7, PA5, PB7, PC2, PC0, PD6, PD3, PD1 (with-
1
out pull-up)
MODE
DDR
OR
0
floating input
0
0
1
1
floating interrupt input
open drain output
push-pull output
1
0
1
Table 12. Port Configuration
Input
Output
Port
Pin name
PA7, PA5
OR = 0
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
OR = 1
floating interrupt
pull-up interrupt
pull-up
OR = 0
OR = 1
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
Port A
PA6, PA3
PA2:0
PB7
floating interrupt
pull-up interrupt
pull-up
Port B
Port C
Port D
PB6
PB5:0
PC7:4
pull-up
PC3, PC1
PC2, PC0
PD7, PD0
PD6, PD3, PD1
PD5, PD4, PD2
PE5:0
pull-up interrupt
floating interrupt
pull-up
floating interrupt
pull-up interrupt
pull-up
Port E
Port F
Port G
Port H
PF5:0
pull-up
PG7:0
pull-up
PH7:0
pull-up
58/309
1
ST7MC1xx/ST7MC2xx
I/O PORTS (Cont’d)
Table 13. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
PEDDR
PEOR
PFDR
PFDDR
PFOR
PGDR
PGDDR
PGOR
PHDR
PHDDR
PHOR
59/309
1
ST7MC1xx/ST7MC2xx
10 ON-CHIP PERIPHERALS
10.1 WINDOW WATCHDOG (WWDG)
10.1.1 Introduction
ter is reloaded outside the window (see Figure
37)
The Window Watchdog is used to detect the oc-
currence of a software fault, usually generated by
external interference or by unforeseen logical con-
ditions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the contents of the downcounter before the T6
bit becomes cleared. An MCU reset is also gener-
ated if the 7-bit downcounter value (in the control
register) is refreshed before the downcounter has
reached the window register value. This implies
that the counter must be refreshed in a limited win-
dow.
■ Hardware/Software
Watchdog
activation
(selectable by option byte)
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
10.1.3 Functional Description
The counter value stored in the WDGCR register
(bits T[6:0]), is decremented every 16384 f
cycles (approx.), and the length of the timeout pe-
riod can be programmed by the user in 64 incre-
ments.
OSC2
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit downcounter (T[6:0] bits) rolls
over from 40h to 3Fh (T6 becomes cleared), it ini-
tiates a reset cycle pulling low the reset pin for typ-
ically 30μs. If the software reloads the counter
while the counter is greater than the value stored
in the window register, then a reset is generated.
10.1.2 Main Features
■ Programmable free-running downcounter
■ Conditional reset
– Reset (if watchdog activated) when the down-
counter value becomes less than 40h
– Reset (if watchdog activated) if the downcoun-
Figure 34. Watchdog Block Diagram
RESET
WATCHDOG WINDOW REGISTER (WDGWR)
-
W5
W0
W6
W1
W4
W2
W3
comparator
= 1 when
T6:0 > W6:0
CMP
Write WDGCR
WATCHDOG CONTROL REGISTER (WDGCR)
T5
T0
WDGA T6
T1
T4
T2
T3
6-BIT DOWNCOUNTER (CNT)
MCC/RTC
f
OSC2
DIV 64
WDG PRESCALER
DIV 4
12-BIT MCC
RTC COUNTER
TB[1:0] bits
(MCCSR
Register)
MSB
LSB
0
6 5
11
60/309
1
ST7MC1xx/ST7MC2xx
WINDOW WATCHDOG (Cont’d)
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This operation
must occur only when the counter value is lower
than the window register value. The value to be
stored in the WDGCR register must be between
FFh and C0h (see Figure 35):
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see Figure 36).
The window register (WDGWR) contains the
high limit of the window: To prevent a reset, the
downcounter must be reloaded when its value is
lower than the window register value and greater
than 3Fh. Figure 37 describes the window watch-
dog process.
– Enabling the watchdog:
When Software Watchdog is selected (by option
byte), the watchdog is disabled after a reset. It is
enabled by setting the WDGA bit in the WDGCR
register, then it cannot be disabled again except
by a reset.
Note: The T6 bit can be used to generate a soft-
ware reset (the WDGA bit is set and the T6 bit is
cleared).
– Watchdog Reset on Halt option
When Hardware Watchdog is selected (by option
byte), the watchdog is always active and the
WDGA bit is not used.
If the watchdog is activated and the watchdog re-
set on halt option is selected, then the HALT in-
struction will generate a Reset.
– Controlling the downcounter:
10.1.4 Using Halt Mode with the WDG
This downcounter is free-running: It counts down
even if the watchdog is disabled. When the
watchdog is enabled, the T6 bit must be set to
prevent generating an immediate reset.
If Halt mode with Watchdog is enabled by option
byte (no watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 35. Ap-
proximate Timeout Duration). The timing varies
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1
ST7MC1xx/ST7MC2xx
WINDOW WATCHDOG (Cont’d)
10.1.5 How to Program the Watchdog Timeout
more precision is needed, use the formulae in Fig-
ure 36.
Figure 35 shows the linear relationship between
the 6-bit value to be loaded in the Watchdog Coun-
ter (CNT) and the resulting timeout duration in mil-
liseconds. This can be used for a quick calculation
without taking the timing variations into account. If
Caution: When writing to the WDGCR register, al-
ways write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 35. Approximate Timeout Duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz f
OSC2
62/309
1
ST7MC1xx/ST7MC2xx
WINDOW WATCHDOG (Cont’d)
Figure 36. Exact Timeout Duration (t
and t
)
max
min
WHERE:
t
t
t
= (LSB + 128) x 64 x t
min0
OSC2
= 16384 x t
= 125ns if f
max0
OSC2
OSC2
= 8 MHz
OSC2
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
TB0 Bit
Selected MCCSR
Timebase
MSB
LSB
(MCCSR Reg.) (MCCSR Reg.)
0
0
1
1
0
1
0
1
2ms
4ms
4
8
59
53
35
54
10ms
25ms
20
49
To calculate the minimum Watchdog Timeout (t ):
min
MSB
4
IF
-------------
THEN
ELSE
CNT <
t
= tmin0 + 16384 × CNT × t
min
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
⎠
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
min
min0
⎝
MSB
MSB
To calculate the maximum Watchdog Timeout (t
):
max
MSB
4
IF
-------------
THEN
t
CNT ≤
= tmax0 + 16384 × CNT × t
max osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
ELSE
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
max
max0
⎝
⎠
MSB
MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog
Timeout (ms)
Max. Watchdog
Timeout (ms)
Value of T[5:0] Bits in
WDGCR Register (Hex.)
t
t
min
max
00
3F
1.496
128
2.048
128.552
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1
ST7MC1xx/ST7MC2xx
WINDOW WATCHDOG (Cont’d)
Figure 37. Window Watchdog Timing Diagram
T[5:0] CNT downcounter
WDGWR
3Fh
time
(step = 16384/fOSC2
)
Refresh not allowed Refresh Window
T6 bit
Reset
10.1.6 Low Power Modes
Mode Description
Slow No effect on Watchdog: The downcounter continues to decrement at normal speed.
Wait
No effect on Watchdog: The downcounter continues to decrement.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
Halt
0
0
If an interrupt is received (refer to interrupt table mapping to see interrupts
which can occur in halt mode), the Watchdog restarts counting after 256 or
4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 10.1.8 below.
0
1
1
x
A reset is generated instead of entering halt mode.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
Active-
halt
10.1.7 Hardware Watchdog Option
10.1.8 Using Halt Mode with the WDG
(WDGHALT option)
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
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ST7MC1xx/ST7MC2xx
WINDOW WATCHDOG (Cont’d)
10.1.9 Interrupts
None.
WINDOW REGISTER (WDGWR)
Read/Write
Reset Value: 0111 1111 (7Fh)
10.1.10 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
7
0
-
W6
W5
W4
W3 W2 W1
W0
Reset Value: 0111 1111 (7Fh)
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
7
0
These bits contain the window value to be com-
pared to the downcounter.
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
cy-
OSC2
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
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1
ST7MC1xx/ST7MC2xx
Table 14. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Ah
002Bh
WDGWR
Reset Value
0
0
W6
1
W5
1
W4
1
W3
1
W2
1
W1
1
W0
1
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1
ST7MC1xx/ST7MC2xx
10.2 PWM AUTO-RELOAD TIMER (ART)
10.2.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare/capture capabilities and of a
7-bit prescaler clock source.
– Up to two input capture functions
– External event detector
– Up to two external interrupt sources
The three first modes can be used together with a
single counter frequency.
These resources allow five possible operating
modes:
The timer can be used to wake up the MCU from
Wait and Halt modes.
– Generation of up to 4 independent PWM signals
– Output compare and Time base interrupt
Figure 38. PWM Auto-Reload Timer Block Diagram
OCRx
DCRx
OEx
OPx
PWMCR
REGISTER
REGISTER
LOAD
PORT
ALTERNATE
FUNCTION
POLARITY
CONTROL
PWMx
COMPARE
8-BIT COUNTER
(CAR REGISTER)
ARR
REGISTER
LOAD
INPUT CAPTURE
CONTROL
ICRx
LOAD
ARTICx
REGISTER
ICSx
ICIEx
ICFx
ICCSR
ICx INTERRUPT
f
EXT
ARTCLK
f
COUNTER
f
CPU
MUX
f
INPUT
PROGRAMMABLE
PRESCALER
ARTCSR
EXCL CC2
CC1
CC0
TCE FCRL OIE
OVF
OVF INTERRUPT
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ST7MC1xx/ST7MC2xx
ON-CHIP PERIPHERALS (Cont’d)
10.2.2 Functional Description
Counter
Counter and Prescaler Initialization
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris-
ing edge of the clock signal.
After RESET, the counter and the prescaler are
cleared and f
= f
.
INPUT
CPU
The counter can be initialized by:
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (ARTCAR).
– Writing to the ARTARR register and then setting
the FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the ARTCSR reg-
ister.
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARTARR register (the prescaler is not affected).
– Writing to the ARTCAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Counter clock and prescaler
The counter clock frequency is given by:
Direct access to the prescaler is not possible.
CC[2:0]
f
= f
/ 2
INPUT
COUNTER
Output compare control
The timer counter’s input clock (f
) feeds the
INPUT
The timer compare function is based on four differ-
ent comparisons with the counter (one for each
PWMx output). Each comparison is made be-
tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy-
cle register (PWMDCRx) at each overflow of the
counter.
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(ARTCSR). Thus the division factor of the prescal-
n
er can be set to 2 (where n = 0, 1,..7).
This f
frequency source is selected through
INPUT
the EXCL bit of the ARTCSR register and can be
either the f or an external input frequency f
.
EXT
CPU
This double buffering method avoids glitch gener-
ation when changing the duty cycle on the fly.
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Figure 39. Output compare control
f
COUNTER
ARTARR=FDh
FFh
COUNTER
OCRx
FDh
FEh
FDh
FEh
FFh
FDh
FEh
FFh
FEh
FDh
PWMDCRx
FEh
FDh
PWMx
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ST7MC1xx/ST7MC2xx
ON-CHIP PERIPHERALS (Cont’d)
Independent PWM signal generation
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during Halt mode.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR reg-
ister.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The maximum available resolution for the PWMx
duty cycle is:
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
f
= f
/ (256 - ARTARR)
PWM
COUNTER
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
Figure 40. PWM Auto-reload Timer Function
255
DUTY CYCLE
REGISTER
(PWMDCRx)
AUTO-RELOAD
REGISTER
(ARTARR)
000
t
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 41. PWM Signal from 0% to 100% Duty Cycle
f
COUNTER
ARTARR=FDh
FFh
COUNTER
FDh
FEh
FDh
FEh
FFh
FDh
FEh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
t
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1
ST7MC1xx/ST7MC2xx
ON-CHIP PERIPHERALS (Cont’d)
Output compare and Time base interrupt
External clock and event detector mode
Using the f external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARTARR register
On overflow, the OVF flag of the ARTCSR register
is set and an overflow interrupt request is generat-
ed if the overflow interrupt enable bit, OIE, in the
ARTCSR register, is set. The OVF flag must be re-
set by the user software. This interrupt can be
used as a time base in the application.
EXT
is used to select the n
number of events to
EVENT
be counted before setting the OVF flag.
n
= 256 - ARTARR
EVENT
Caution: The external clock function is not availa-
ble in Halt mode. If Halt mode is used in the appli-
cation, prior to executing the HALT instruction, the
counter must be disabled by clearing the TCE bit
in the ARTCSR register to avoid spurious counter
increments.
Figure 42. External Event Detector Example (3 counts)
f
=f
EXT COUNTER
ARTARR=FDh
FFh
COUNTER
OVF
FDh
FEh
FDh
FEh
FFh
FDh
ARTCSR READ
ARTCSR READ
INTERRUPT
IF OIE=1
INTERRUPT
IF OIE=1
t
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1
ST7MC1xx/ST7MC2xx
ON-CHIP PERIPHERALS (Cont’d)
Input capture function
This mode allows the measurement of external
signal pulse widths through ARTICRx registers.
External interrupt capability
This mode allows the Input capture capabilities to
be used as external interrupt sources. The inter-
rupts are generated on the edge of the ARTICx
signal.
Each input capture can generate an interrupt inde-
pendently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status regis-
ter (ARTICCSR).
The edge sensitivity of the external interrupts is
programmable (CSx bit of ARTICCSR register)
and they are independently enabled through CIEx
bits of the ARTICCSR register. After fetching the
interrupt vector, the CFx flags can be read to iden-
tify the interrupt source.
These input capture interrupts are enabled
through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is soft-
ware programmable through the CSx bits of the
ARTICCSR register.
During Halt mode, the external interrupts can be
used to wake up the micro (if the CIEx bit is set).
The read only input capture registers (ARTICRx)
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fetching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload coun-
ter cycle time (1/f
).
COUNTER
Note: During Halt mode, if both input capture and
external clock are enabled, the ARTICRx register
value is not guaranteed if the input capture pin and
the external clock change simultaneously.
Figure 43. Input Capture Timing Diagram
f
COUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
INTERRUPT
04h
ARTICx PIN
CFx FLAG
xxh
ICRx REGISTER
t
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1
ST7MC1xx/ST7MC2xx
ON-CHIP PERIPHERALS (Cont’d)
10.2.3 Register Description
CONTROL / STATUS REGISTER (ARTCSR)
Read/Write
0: New transition not yet reached
1: Transition reached
COUNTER ACCESS REGISTER (ARTCAR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Reset Value: 0000 0000 (00h)
EXCL CC2
CC1
CC0
TCE FCRL
OIE
OVF
7
0
Bit 7 = EXCLExternal Clock
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
Bit 7:0 = CA[7:0] Counter Access Data
1: External clock.
These bits can be set and cleared either by hard-
ware or by software. The ARTCAR register is used
to read or write the auto-reload counter “on the fly”
(while it is counting).
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from f
.
INPUT
f
With f
INPUT
=8 MHz CC2 CC1 CC0
COUNTER
f
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INPUT
AUTO-RELOAD REGISTER (ARTARR)
Read/Write
f
f
f
/ 2
/ 4
/ 8
/ 16
/ 32
/ 64
/ 128
INPUT
INPUT
INPUT
Reset Value: 0000 0000 (00h)
f
f
f
INPUT
INPUT
INPUT
7
0
f
INPUT
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Bit 3 = TCE Timer Counter Enable
Bit 7:0 = AR[7:0]Counter Auto-Reload Data
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
These bits are set and cleared by software. They
are used to hold the auto-reload value which is au-
tomatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
Bit 2 = FCRLForce Counter Re-Load
This bit is write-only and any attempt to read it will
yieldalogicalzero.Whenset,itcausesthecontents
of ARTARR register to be loaded into the counter,
and the content of the prescaler register to be
cleared in order to initialize the timer before starting
to count.
This register has two PWM management func-
tions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
Bit 1 = OIEOverflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
0: Overflow Interrupt disable.
1: Overflow Interrupt enable.
PWM Frequency vs Resolution:
f
PWM
ARTARR
value
Resolution
Min
Max
0
8-bit
~0.244 kHz
~0.244 kHz
~0.488 kHz
~0.977 kHz
~1.953 kHz
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
Bit 0 = OVFOverflow Flag
This bit is set by hardware and cleared by software
reading the ARTCSR register. It indicates the tran-
sition of the counter from FFh to the ARTARR val-
[ 0..127 ]
> 7-bit
> 6-bit
> 5-bit
> 4-bit
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
ue
.
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1
ST7MC1xx/ST7MC2xx
ON-CHIP PERIPHERALS (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read/Write
DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
OE3
OE2
OE1
OE0
OP3
OP2
OP1
OP0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
Bit 7:4 = OE[3:0] PWM Output Enable
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
A PWMDCRx register is associated with the OCRx
register of each PWM channel to determine the
second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR regis-
ters allow the duty cycle to be set independently
for each PWM channel.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
Note: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately reversed.
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ST7MC1xx/ST7MC2xx
ON-CHIP PERIPHERALS (Cont’d)
INPUT CAPTURE
INPUT CAPTURE REGISTERS (ARTICRx)
Read only
CONTROL / STATUS REGISTER (ARTICCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
IC7
IC6
IC5
IC4
IC3
IC2
IC1
IC0
0
CS2
CS1
CIE2 CIE1
CF2
CF1
Bit 7:0 = IC[7:0] Input Capture Data
Bit 7:6 = Reserved, always read as 0.
These read only bits are set and cleared by hard-
ware. An ARTICRx register contains the 8-bit
auto-reload counter value transferred by the input
capture channel x event.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
determine the trigger event polarity on the corre-
sponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel inter-
rupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by
software reading the corresponding ARTICRx reg-
ister. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x.
1: An input capture has occurred on channel x.
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1
ST7MC1xx/ST7MC2xx
PWM AUTO-RELOAD TIMER (Cont’d)
Table 15. PWM Auto-Reload Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PWMDCR3
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
Reset Value
PWMDCR2
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR1
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMCR
OE3
0
OE2
0
OE1
0
OE0
0
OP3
0
OP2
0
OP1
0
OP0
0
Reset Value
ARTCSR
EXCL
0
CC2
0
CC1
0
CC0
0
TCE
0
FCRL
0
OIE
0
OVF
0
Reset Value
ARTCAR
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
Reset Value
ARTARR
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
Reset Value
ARTICCSR
CS2
0
CS1
0
CIE2
0
CIE1
0
CF2
0
CF1
0
0
0
Reset Value
ARTICR1
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset Value
ARTICR2
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset Value
75/309
1
ST7MC1xx/ST7MC2xx
10.3 16-BIT TIMER
10.3.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
10.3.3 Functional Description
10.3.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some devices of the ST7 family have two on-chip
16-bit timers. They are completely independent,
and do not share any resources. They are syn-
chronized after a Device reset as long as the timer
clock frequencies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
This description covers one or two 16-bit timers. In
the devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
10.3.2 Main Features
■ Programmableprescaler:fCPU dividedby2,4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slowerthantheCPUclockspeed)withthechoice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 16 Clock
Control Bits. The value in the counter register re-
peats every 131 072, 262 144 or 524 288 CPU
clock cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
■ Reduced Power Mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 44.
*Note: Some timer pins may not available (not
bonded) in some devices. Refer to the device pin
out description.
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1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
Figure 44. Timer Block Diagram
INTERNAL BUS
f
CPU
16-BIT TIMER PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See Device Interrupt Vector Table)
TIMER INTERRUPT
77/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +Δt
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (Device awakened by an interrupt)
or from the reset count (Device awakened by a
Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
10.3.3.2 External Clock
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronised with the falling edge
of the internal CPU clock.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
78/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
Figure 45. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 46. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 47. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is run-
ning.
79/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
10.3.3.3 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 49).
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
4. In One pulse Mode and PWM mode only the
input capture 2 can be used.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
80/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
Figure 48. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 49. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The active edge is the rising edge.
Note: The time between an event on the ICAPi pin
and the appearance of the corresponding flag is
from 2 to 3 CPU clock cycles. This depends on the
moment when the ICAP event happens relative to
the timer clock.
81/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
10.3.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
Δt f
PRESC
* CPU
Δ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
Δt
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 16
Clock Control Bits)
PRESC
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Δ OCiR = Δt f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
Δt
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
82/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
Notes:
Forced Compare Output capability
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
3. In both internal and external clock modes, OCFi
and OCMPi are set while the counter value
equals the OCiR register value (see Figure 51
for an example with f
and Figure 52 for an
CPU/2
example with f
). This behavior is the same
CPU/4
in OPM or PWM mode.
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 50. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
83/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
Figure 51. Output Compare Timing Diagram, f
=f
/2
TIMER CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 52. Output Compare Timing Diagram, f
=f
/4
TIMER CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
84/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
10.3.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use one pulse mode:
CPU
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 16
Clock Control Bits)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 53).
– Select the timer clock CC[1:0] (see Table 16
Clock Control Bits).
One pulse mode cycle
Notes:
ICR1 = Counter
When
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
When a valid event occurs on the ICAP1 pin, the
counter value is loaded in the ICR1 register. The
counter is then initialized to FFFCh, the OLVL2 bit
is output on the OCMP1 pin and the ICF1 bit is set.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
85/309
1
ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
Figure 53. One Pulse Mode Timing Example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 54. Pulse Width Modulation Mode Timing Example
34E2 FFFC
34E2
COUNTER
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note:
86/309
ST7MC1xx/ST7MC2xx
16-BIT TIMER
10.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation cycle
Note:
i
i
Procedure
i
Notes:
ST7MC1xx/ST7MC2xx
16-BIT TIMER
10.3.4 Low Power Modes
No effect on 16-bit Timer.
Timer interrupts cause the Device to exit from Wait mode.
Wait
Halt
16-bit Timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count
when the Device is woken up by an interrupt with “exit from Halt mode” capability or from the counter reset
value when the Device is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the Device is woken up by an interrupt with “exit from Halt mode” capability, the ICFi bit is set, and
the counter value present when exiting from Halt mode is captured into the ICiR register.
10.3.5 Interrupts
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note:
10.3.6 Summary of Timer modes
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
3)
See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode
1
(Cont’d)
Bit 4 =
Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 =
Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 =
Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 =
Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 =
Output Compare Interrupt Enable.
Bit 1 =
Input Edge 1.
0: Interrupt is inhibited.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
1: A rising edge triggers the capture.
Bit 5 =
Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
Bit 0 =
Output Level 1.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
89/309
1
(Cont’d)
Bit 4 =
Pulse Width Modulation.
0: PWM mode is not active.
Read/Write
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 =
Clock Control.
Bit 7 =
Output Compare 1 Pin Enable.
The timer clock mode depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
fCPU / 4
fCPU / 2
fCPU / 8
0
0
1
0
1
0
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
External Clock (where
available)
1
1
Bit 6 =
Output Compare 2 Pin Enable.
: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
Bit 1 =
Input Edge 2.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 =
One Pulse Mode.
0: One Pulse Mode is not active.
Bit 0 =
External Clock Edge.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
90/309
1
(Cont’d)
Reading or writing the ACLR register does
not clear TOF.
Read Only
Reset Value: 0000 0000 (00h)
Bit 4 =
The three least significant bits are not used.
7
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
0
0
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 =
Bit 3 =
0: No input capture (reset value).
0: No match (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 6 =
Bit 2 =
0: No match (reset value).
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
0: Timer enabled
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 5 =
1: Timer prescaler, counter and outputs disabled
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Bits 1:0 = Reserved, must be kept cleared.
91/309
1
(Cont’d)
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
92/309
1
(Cont’d)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
7
0
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
93/309
1
(Cont’d)
Timer A: 32
Timer B: 42 Reset Value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer A: 31
Timer B: 41 Reset Value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
OCF1
0
Timer A: 33
Timer B: 43 Reset Value
ICF1
0
TOF
0
ICF2
0
OCF2
0
TIMD
0
-
0
-
0
Timer A: 34
Timer B: 44 Reset Value
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer A: 35
Timer B: 45 Reset Value
MSB
-
LSB
-
Timer A: 36
Timer B: 46 Reset Value
MSB
-
LSB
-
Timer A: 37
Timer B: 47 Reset Value
MSB
-
LSB
-
Timer A: 3E
Timer B: 4E Reset Value
MSB
-
LSB
-
Timer A: 3F
Timer B: 4F Reset Value
MSB
-
LSB
-
Timer A: 38
Timer B: 48 Reset Value
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Timer A: 39
Timer B: 49 Reset Value
MSB
1
LSB
0
Timer A: 3A
Timer B: 4A Reset Value
MSB
1
LSB
1
Timer A: 3B
Timer B: 4B Reset Value
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
Timer A: 3C
Timer B: 4C Reset Value
MSB
-
LSB
-
Timer A: 3D
Timer B: 4D Reset Value
MSB
-
LSB
-
-
-
-
-
-
-
94/309
1
(cont’d)
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
Figure 55 on page 96 shows the serial peripheral
interface (SPI) block diagram. There are three reg-
isters:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
■ Full duplex synchronous transfers (on three
The SPI is connected to external devices through
four pins:
lines)
■ Simplex synchronous transfers (on two lines)
■ Master or slave operation
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ 6 master mode frequencies (f
/4 max.)
CPU
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ f
/2 max. slave mode frequency (see note)
CPU
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
■ Write collision, Master Mode Fault and Overrun
flags
In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
95/309
1
(cont’d)
Data/Address Bus
Read
Interrupt
request
Read Buffer
7
0
8-bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
CONTROL
7
0
SPR0
MSTR
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
96/309
1
(cont’d)
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 56.
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Four possible data/clock timing relationships may
be chosen (see Figure 59 on page 100) but master
and slave must be programmed with the same tim-
ing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-bit SHIFT REGISTER
8-bit SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
97/309
1
(cont’d)
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 58).
There are two cases depending on the data/clock
timing relationship (see Figure 57):
If CPHA = 1 (data latched on second clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.4.5.3).
– SS internal must be held high continuously
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
SSM bit
SSI bit
SS external pin
1
0
SS internal
98/309
1
(cont’d)
While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
In slave mode, the serial clock is received on the
SCK pin from the master device.
The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 59).
To operate the SPI in master mode, perform the
following steps in order:
The slave must have the same CPOL
and CPHA settings as the master.
1. Write to the SPICR register:
– Select the clock frequency by configuring the
– Manage the SS pin as described in Section
10.4.3.2 and Figure 57. If CPHA = 1 SS must
be held low continuously. If CPHA = 0 SS
must be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
59 shows the four possible configurations.
The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
if the SPICSR register is not writ-
ten first, the SPICR register setting (MSTR bit)
may be not taken into account.
When data transfer is complete:
– The SPIF bit is set by hardware.
The transmit sequence begins when software
writes a byte in the SPIDR register.
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware.
1. An access to the SPICSR register while the
SPIF bit is set
2. A write or a read to the SPIDR register
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.4.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register
99/309
1
(cont’d)
Figure 59 shows an SPI transfer with the four com-
binations of the CPHA and CPOL bits. The dia-
gram may be interpreted as a master or slave tim-
ing diagram where the SCK pin, the MISO pin and
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 59).
The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge.
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
100/309
1
ST7MC1xx/ST7MC2xx
SERIAL PERIPHERAL INTERFACE (cont’d)
10.4.5 Error Flags
10.4.5.2 Overrun Condition (OVR)
10.4.5.1 Master Mode Fault (MODF)
An overrun condition occurs when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master de-
vice’s SS pin is pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
10.4.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 10.4.3.2 Slave Select
Management.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: A "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multimaster configuration the device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multimaster conflict and allows software to
handle this using an interrupt routine and either
perform a reset or return to an application default
state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 60).
Figure 60. Clearing the WCOL Bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF = 0
WCOL = 0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
RESULT
Note: Writing to the SPIDR register in-
stead of reading it does not reset the
WCOL bit.
2nd Step
Read SPIDR
WCOL = 0
101/309
1
ST7MC1xx/ST7MC2xx
SERIAL PERIPHERAL INTERFACE (cont’d)
10.4.5.4 Single Master and Multimaster
Configurations
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Single Master System
A typical single master system may be configured
using a device as the master and four devices as
slaves (see Figure 61).
Multimaster System
A multimaster system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multimaster system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line,
the master allows only one active slave device
during a transmission.
Figure 61. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
Slave
SCK
Slave
Device
SCK
Slave
Device
SCK
Slave
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
102/309
1
ST7MC1xx/ST7MC2xx
SERIAL PERIPHERAL INTERFACE (cont’d)
10.4.6 Low Power Modes
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
Wait
SPI interrupt events cause the device to exit
from Wait mode.
Caution: The SPI can wake up the device from
Halt mode only if the Slave Select signal (external
SS pin or the SSI bit in the SPICSR register) is low
when the device enters Halt mode. So, if Slave se-
lection is configured as external (see Section
10.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI opera-
tion resumes when the device is woken up by
an interrupt with “exit from Halt mode” capa-
bility. The data received is subsequently read
from the SPIDR register when the software is
running (interrupt vector fetching). If several
data are received before the wake-up event,
then an overrun error is generated. This error
can be detected after the fetch of the inter-
rupt routine that woke up the Device.
Halt
10.4.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of
Transfer Event
SPIF
Yes
10.4.6.1 Using the SPI to wake up the device
from Halt mode
Master Mode
Fault Event
SPIE
Yes
MODF
OVR
No
In slave configuration, the SPI is able to wake up
the device from Halt mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
103/309
1
ST7MC1xx/ST7MC2xx
10.4.8 Register Description
SPI CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
SPIE
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 2 = CPHA
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register)
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE
Note: The slave must have the same CPOL and
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 10.4.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
CPHA settings as the master.
Bits 1:0 = SPR[1:0]
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2
Table 18. SPI Master Mode SCK Frequency
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 18 SPI Master
Mode SCK Frequency.
Serial Clock
SPR2
SPR1
SPR0
f
f
/4
/8
1
CPU
CPU
0
1
0
1
0
0: Divider by 2 enabled
1: Divider by 2 disabled
0
1
0
f
f
f
/16
/32
/64
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
1
f
/128
CPU
Bit 4 = MSTR
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 10.4.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
104/309
1
ST7MC1xx/ST7MC2xx
SERIAL PERIPHERAL INTERFACE (cont’d)
SPI CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
7
0
SPIF WCOL OVR MODF
-
SOD
SSM
SSI
1: SPI output disabled
Bit 7 = SPIF
Bit 1 = SSM
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
10.4.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE = 1 in the SPICR register. It is cleared by
a software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Bit 0 = SSI
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
Bit 6 = WCOL
1: Slave deselected
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 60).
SPI DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
0: No write collision occurred
1: A write collision has been detected
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 5 = OVR S
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.4.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Overrun error detected
Bit 4 = MODF
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.4.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE = 1 in the SPICR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF = 1 fol-
lowed by a write to the SPICR register).
0: No master mode fault detected
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 55).
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
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ST7MC1xx/ST7MC2xx
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 19. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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ST7MC1xx/ST7MC2xx
10.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
10.5.1 Introduction
■ 6 interrupt sources
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error
The LIN-dedicated features support the LIN (Local
Interconnect Network) protocol for both master
and slave nodes.
– Parity interrupt
■ Parity control:
– Transmits parity bit
This chapter is divided into SCI Mode and LIN
mode sections. For information on general SCI
communications, refer to the SCI mode section.
For LIN applications, refer to both the SCI mode
and LIN mode sections.
– Checks parity of received data byte
■ Reduced power consumption mode
10.5.3 LIN Features
– LIN Master
10.5.2 SCI Features
– 13-bit LIN Synch Break generation
– LIN Slave
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
– Automatic Header Handling
■ Independently programmable transmit and
receive baud rates up to 500K baud
– Automatic baud rate resynchronization based
on recognition and measurement of the LIN
Synch Field (for LIN slave nodes)
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ 2 receiver wake-up modes:
– Address bit (MSB)
– Automatic baud rate adjustment (at CPU fre-
quency precision)
– 11-bit LIN Synch Break detection capability
– LIN Parity check on the LIN Identifier Field
(only in reception)
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
– LIN Error management
– LIN Header Timeout
– Hot plugging support
■ Separate enable bits for Transmitter and
Receiver
■ Overrun, Noise and Frame error detection
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LINSCI™ SERIAL COMMUNICATION INTERFACE (cont’d)
10.5.4 General Description
– A conventional type for commonly-used baud
rates
The interface is externally connected to another
device by two pins:
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
– A LIN baud rate generator with automatic resyn-
chronization
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as characters comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the character is com-
plete
This interface uses three types of baud rate gener-
ator:
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
Figure 62. SCI Block Diagram (in Conventional Baud Rate Generator Mode)
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Receive Shift Register
Transmit Data Register (TDR)
TDO
RDI
Transmit Shift Register
SCICR1
R8
SCID
PCE
WAKE
T8
M
PS PIE
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
SCISR
SCICR2
OR/
LHE
TIE TCIE RIE ILIE TE RE RWU SBK
NF
TDRE
RDRF
IDLE
TC
FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.5.5 SCI Mode - Functional Description
Conventional Baud Rate Generator Mode
10.5.5.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 63).
The block diagram of the Serial Control Interface
in conventional baud rate generator mode is
shown in Figure 62.
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
It uses four registers:
– 2 control registers (SCICR1 and SCICR2)
– A status register (SCISR)
An Idle character is interpreted as a continuous
logic high level for 10 (or 11) full bit times.
A Break character is a character with a sufficient
number of low level bits to break the normal data
format followed by an extra “1” bit to acknowledge
the start bit.
– A baud rate register (SCIBRR)
Extended Prescaler Mode
Two additional prescalers are available in extend-
ed prescaler mode. They are shown in Figure 64.
– An extended prescaler receiver register (SCIER-
PR)
– An extended prescaler transmitter register (SCI-
ETPR)
Figure 63. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Character
Parity
Data Character
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Bit8
Bit0
Bit7
Bit
Start
Bit
Idle Line
Start
Bit
Extra
’1’
Break Character
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Character
Data Character
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit0
Start
Bit
Idle Line
Start
Bit
Extra
’1’
Break Character
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.5.5.2 Transmitter
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
When a character transmission is complete (after
the stop bit) the TC bit is set and an interrupt is
generated if the TCIE is set and the I[1:0] bits are
cleared in the CCR register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 62).
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Procedure
– Select the M bit to define the word length.
Break Characters
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
Setting the SBK bit loads the shift register with a
break character. The break character length de-
pends on the M bit (see Figure 63).
– Set the TE bit to send a preamble of 10 (M = 0)
or 11 (M = 1) consecutive ones (Idle Line) as first
transmission.
As long as the SBK bit is set, the SCI sends break
characters to the TDO pin. After clearing this bit by
software, the SCI inserts a logic 1 bit at the end of
the last break character to guarantee the recogni-
tion of the start bit of the next character.
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Idle Line
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Setting the TE bit drives the SCI to send a pream-
ble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s
(idle line) before the first character.
In this case, clearing and then setting the TE bit
during a transmission sends a preamble (idle line)
after the current word. Note that the preamble du-
ration (10 or 11 consecutive ‘1’s depending on the
M bit) does not take into account the stop bit of the
previous character.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, that is, before writing the next byte in the
SCIDR.
This flag generates an interrupt if the TIE bit is set
and the I[|1:0] bits are cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.5.5.3 Receiver
– The OR bit is set.
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I[|1:0] bits are cleared in the CCR register.
Character reception
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 62).
Noise Error
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
Procedure
When noise is detected in a character:
– Select the M bit to define the word length.
– The NF bit is set at the rising edge of the RDRF
bit.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Data is transferred from the Shift register to the
SCIDR register.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
The NF bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
– An interrupt is generated if the RIE bit is set and
the I[1:0] bits are cleared in the CCR register.
Framing Error
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a desynchroniza-
tion or excessive noise.
Clearing the RDRF bit is performed by the following
software sequence done by:
– A break is received.
1. An access to the SCISR register
2. A read to the SCIDR register.
When the framing error is detected:
– the FE bit is set by hardware
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
– Data is transferred from the Shift register to the
SCIDR register.
Idle Line
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
When an idle line is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I[|1:0] bits are
cleared in the CCR register.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
Overrun Error
Break Character
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
– When a break character is received, the SCI
handles it as a framing error. To differentiate a
break character from a framing error, it is neces-
sary to read the SCIDR. If the received value is
00h, it is a break character. Otherwise it is a
framing error.
When an overrun error occurs:
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.5.5.4 Conventional Baud Rate Generation
10.5.5.5 Extended Baud Rate Generation
The baud rates for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
f
f
CPU
CPU
Rx =
Tx =
The extended baud rate generator block diagram
is described in Figure 64.
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
Note: The extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
CPU
f
f
CPU
CPU
PR = 13 and TR = RR = 1, the transmit and re-
ceive baud rates are 38400 baud.
Rx =
16 ERPR*(PR*RR)
Tx =
16 ETPR*(PR*TR)
*
*
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
with:
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
Figure 64. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.5.5.6 Receiver Muting and Wake-up Feature
ceived an address character (most significant bit
= ’1’), the receivers are waken up. The receivers
which are not addressed set RWU bit to enter in
mute mode. Consequently, they will not treat the
next characters constituting the next part of the
message.
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non-addressed receivers.
10.5.5.7 Parity Control
The non-addressed devices may be placed in
sleep mode by means of the muting function.
Hardware byte Parity control (generation of parity
bit in transmission and parity checking in recep-
tion) can be enabled by setting the PCE bit in the
SCICR1 register. Depending on the character for-
mat defined by the M bit, the possible SCI charac-
ter formats are as listed in Table 20.
Setting the RWU bit by software puts the SCI in
sleep mode:
All the reception status bits can not be set.
All the receive interrupts are inhibited.
Note: In case of wake-up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
A muted receiver may be woken up in one of the
following ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Idle Line Detection
Table 20. Character Formats
M bit
PCE bit
Character format
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data | PB | STB |
Receiver wakes up by Idle Line detection when the
Receive line has recognized an Idle Line. Then the
RWU bit is reset by hardware but the IDLE bit is
not set.
0
1
0
1
0
1
This feature is useful in a multiprocessor system
when the first characters of the message deter-
mine the address and when each message ends
by an idle line: As soon as the line becomes idle,
every receivers is waken up and analyse the first
characters of the message which indicates the ad-
dressed receiver. The receivers which are not ad-
dressed set RWU bit to enter in mute mode. Con-
sequently, they will not treat the next characters
constituting the next part of the message. At the
end of the message, an idle line is sent by the
transmitter: this wakes up every receivers which
are ready to analyse the addressing characters of
the new message.
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Even parity: The parity bit is calculated to obtain
an even number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain
an odd number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 1 if odd parity is selected (PS bit = 1).
In such a system, the inter-characters space must
be smaller than the idle time.
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Address Mark Detection
Receiver wakes up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is
selected (PS = 1). If the parity check fails, the PE
flag is set in the SCISR register and an interrupt is
generated if PCIE is set in the SCICR1 register.
This feature is useful in a multiprocessor system
when the most significant bit of each character
(except for the break character) is reserved for Ad-
dress Detection. As soon as the receivers re-
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.5.6 Low Power Modes
10.5.7 Interrupts
Mode
Description
Enable Exit
Control from from
Exit
Event
Flag
Interrupt Event
No effect on SCI.
SCI interrupts cause the device to exit from
Wait mode.
Bit
Wait
Halt
Wait
TransmitDataRegister
Empty
TDRE
TC
TIE
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited.
Halt
Transmission Com-
plete
TCIE
RIE
Received Data Ready
to be Read
RDRF
Yes
No
Overrun Error or LIN
Synch Error Detected
OR/
LHE
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
LIN Header Detection LHDF LHIE
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.5.8 SCI Mode Register Description
STATUS REGISTER (SCISR)
Read Only
Bit 3 = OR
The OR bit is set by hardware when the word cur-
rently being received in the shift register is ready to
be transferred into the RDR register whereas
RDRF is still set. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR regis-
ter followed by a read to the SCIDR register).
0: No Overrun error
Reset Value: 1100 0000 (C0h)
7
0
1)
1)
1)
1)
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE
1: Overrun error detected
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
Note: When this bit is set, RDR register contents
will not be lost but the shift register will be overwrit-
ten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Character Noise flag
This bit is set by hardware when noise is detected
on a received character. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a read to the SCIDR register).
0: No noise
Bit 6 = TC
This bit is set by hardware when transmission of a
character containing Data is complete. An inter-
rupt is generated if TCIE = 1 in the SCICR2 regis-
ter. It is cleared by a software sequence (an ac-
cess to the SCISR register followed by a write to
the SCIDR register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error
Note: TC is not set after the transmission of a Pre-
amble or a Break.
This bit is set by hardware when a desynchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
Bit 5 = RDRF
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Framing error
1: Framing error or break character detected
Note: This bit does not generate an interrupt as it
appears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both a frame error and
an overrun error, it will be transferred and only the
OR bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE
This bit is set by hardware when an Idle Line is de-
tected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
Bit 0 = PE Parity error
This bit is set by hardware when a byte parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the sta-
tus register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
0: No Idle Line is detected
1: Idle Line is detected
0: No parity error
1: Parity error detected
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (that is, a new idle line
occurs).
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method
Reset Value: x000 0000 (x0h)
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
7
0
1: Address Mark
1)
R8
T8
SCID
M
WAKE
PS
PIE
PCE
Note: If the LINE bit is set, the WAKE bit is deacti-
vated and replaced by the LHDM bit.
1)
This bit has a different function in LIN mode, please
refer to the LIN mode register description.
Bit 2 = PCE Parity control enable
Bit 7 = R8 Receive data bit 8
This bit is set and cleared by software. It selects
the hardware parity control (generation and detec-
tion for byte parity, detection only for LIN parity).
0: Parity control disabled
This bit is used to store the 9th bit of the received
word when M = 1.
1: Parity control enabled
Bit 6 = T8 Transmit data bit 8
This bit is used to store the 9th bit of the transmit-
ted word when M = 1.
Bit 1 = PS Parity selection
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
1: Odd parity
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 0 = PIE Parity interrupt enable
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). The parity error involved can be a byte
parity error (if bit PCE is set and bit LPE is reset) or
a LIN parity error (if bit PCE is set and bit LPE is
set).
Bit 4 = M Word length
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
1: Receiver is enabled and begins searching for a
start bit
Bit 1 = RWU Receiver wake-up
7
0
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
1)
1)
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
1)
0: Receiver in active mode
This bit has a different function in LIN mode, please
1: Receiver in mute mode
refer to the LIN mode register description.
Notes:
Bit 7 = TIE Transmitter interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: In SCI interrupt is generated whenever
TDRE = 1 in the SCISR register
– Before selecting Mute mode (by setting the RWU
bit) the SCI must first receive a data byte, other-
wise it cannot function in Mute mode with wake-
up by Idle line detection.
– In Address Mark Detection Wake-Up configura-
tion (WAKE bit = 1) the RWU bit cannot be mod-
ified by software while the RDRF bit is set.
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1
in the SCISR register
Bit 0 = SBK Send break
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 5 = RIE Receiver interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1
or RDRF = 1 in the SCISR register
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Bit 4 = ILIE Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register.
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
Bit 3 = TE Transmitter enable
This bit enables the transmitter. It is set and
cleared by software.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 62).
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 62).
Bit 2 = RE Receiver enable
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled in the SCISR register
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
BAUD RATE REGISTER (SCIBRR)
Read/Write
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
1
0
1
0
1
0
1
Reset Value: 0000 0000 (00h)
0
0
7
0
4
1
0
1
8
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
16
32
64
128
Note: When LIN slave mode is disabled, the SCI-
BRR register controls the conventional baud rate
generator.
1
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bits 2:0 = SCR[2:0] SCI Receiver rate divider
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
PR Prescaling factor
SCP1
SCP0
1
3
0
1
0
1
0
RR dividing factor
SCR2
SCR1
SCR0
4
1
1
2
0
1
0
1
0
1
0
1
13
0
0
4
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the transmit rate clock in conven-
tional Baud Rate Generator mode.
1
0
1
8
16
32
64
128
1
120/309
1
ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 64) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255).
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 64) is divided by the binary factor set in the
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active af-
ter a reset.
The extended baud rate generator is not active af-
ter a reset.
Note: In LIN slave mode, the Conventional and
Extended Baud Rate Generators are disabled.
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode)
10.5.9 LIN Mode - Functional Description.
Slave
The block diagram of the Serial Control Interface,
in LIN slave mode is shown in Figure 66.
Set the LSLV bit in the SCICR3 register to enter
LIN slave mode. In this case, setting the SBK bit
will have no effect.
It uses six registers:
In LIN Slave mode the LIN baud rate generator is
selected instead of the Conventional or Extended
Prescaler. The LIN baud rate generator is com-
mon to the transmitter and the receiver.
– 3 control registers: SCICR1, SCICR2 and
SCICR3
– 2 status registers: the SCISR register and the
LHLR register mapped at the SCIERPR address
Then the baud rate can be programmed using
LPR and LPRF registers.
– A baud rate register: LPR mapped at the SCI-
BRR address and an associated fraction register
LPFR mapped at the SCIETPR address
Note: It is mandatory to set the LIN configuration
first before programming LPR and LPRF, because
the LIN configuration uses a different baud rate
generator from the standard one.
The bits dedicated to LIN are located in the
SCICR3. Refer to the register descriptions in Sec-
tion 10.5.10for the definitions of each bit.
10.5.9.1 Entering LIN Mode
10.5.9.2 LIN Transmission
To use the LINSCI in LIN mode the following con-
figuration must be set in SCICR3 register:
In LIN mode the same procedure as in SCI mode
has to be applied for a LIN transmission.
– Clear the M bit to configure 8-bit word length.
To transmit the LIN Header the proceed as fol-
lows:
– Set the LINE bit.
Master
– First set the SBK bit in the SCICR2 register to
start transmitting a 13-bit LIN Synch Break
To enter master mode the LSLV bit must be reset
In this case, setting the SBK bit will send 13 low
bits.
– reset the SBK bit
– Load the LIN Synch Field (0x55) in the SCIDR
register to request Synch Field transmission
Then the baud rate can programmed using the
SCIBRR, SCIERPR and SCIETPR registers.
– Wait until the SCIDR is empty (TDRE bit set in
the SCISR register)
In LIN master mode, the Conventional and / or Ex-
tended Prescaler define the baud rate (as in stand-
ard SCI mode)
– Load the LIN message Identifier in the SCIDR
register to request Identifier transmission.
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 65. LIN Characters
8-bit Word length (M bit is reset)
Next Data Character
Data Character
Next
Start
Bit
Start
Bit
Stop
Bit2
Bit6
Bit7
Bit3 Bit4
Bit5
Bit0 Bit1
Bit
Start
Bit
Idle Line
LIN Synch Field
LIN Synch Break = 13 low bits
Start
Bit
Extra
‘1’
LIN Synch Field
Bit2
Next
Start
Bit
Start
Bit
Stop
Bit
Bit6
Bit7
Bit0 Bit1
Bit3 Bit4
Bit5
Measurement for baud rate autosynchronization
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 66. SCI Block Diagram in LIN Slave Mode
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Receive Shift Register
Transmit Data Register (TDR)
TDO
RDI
Transmit Shift Register
SCICR1
R8
SCID
PCE
WAKE
T8
M
PS PIE
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CONTROL
RECEIVER
CLOCK
SCISR
SCICR2
OR/
LHE
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE
RDRF
IDLE
TC
NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
f
CPU
LIN SLAVE BAUD RATE
SCICR3
LDUM LINE
LASE LHDM LHIE LHDF LSF
LSLV
AUTO SYNCHRONIZATION
UNIT
SCIBRR
CONVENTIONAL BAUD RATE
LPR7
LPR0
GENERATOR
+
EXTENDED PRESCALER
0
f
CPU
1
/ LDIV
/16
LIN SLAVE BAUD RATE GENERATOR
124/309
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.5.9.3 LIN Reception
Note:
In LIN mode the reception of a byte is the same as
in SCI mode but the LINSCI has features for han-
dling the LIN Header automatically (identifier de-
tection) or semiautomatically (Synch Break detec-
tion) depending on the LIN Header detection
mode. The detection mode is selected by the
LHDM bit in the SCICR3.
In LIN slave mode, the FE bit detects all frame er-
ror which does not correspond to a break.
Identifier Detection (LHDM = 1):
This case is the same as the previous one except
that the LHDF and the RDRF flags are set only af-
ter the entire header has been received (this is
true whether automatic resynchronization is ena-
bled or not). This indicates that the LIN Identifier is
available in the SCIDR register.
Additionally, an automatic resynchronization fea-
ture can be activated to compensate for any clock
deviation, for more details please refer to Section
10.5.9.5 LIN Baud Rate.
Notes:
During LIN Synch Field measurement, the SCI
state machine is switched off: No characters are
transferred to the data register.
LIN Header Handling by a Slave
Depending on the LIN Header detection method
the LINSCI will signal the detection of a LIN Head-
er after the LIN Synch Break or after the Identifier
has been successfully received.
LIN Slave parity
In LIN Slave mode (LINE and LSLV bits are set)
LIN parity checking can be enabled by setting the
PCE bit.
Note:
It is recommended to combine the Header detec-
tion function with Mute mode. Putting the LINSCI
in Mute mode allows the detection of Headers only
and prevents the reception of any other charac-
ters.
In this case, the parity bits of the LIN Identifier
Field are checked. The identifier character is rec-
ognized as the third received character after a
break character (included):
This mode can be used to wait for the next Header
without being interrupted by the data bytes of the
current message in case this message is not rele-
vant for the application.
parity bits
Synch Break Detection (LHDM = 0):
When a LIN Synch Break is received:
LIN Synch
Break
LIN Synch
Field
Identifier
Field
– The RDRF bit in the SCISR register is set. It in-
dicates that the content of the shift register is
transferred to the SCIDR register, a value of
0x00 is expected for a Break.
The bits involved are the two MSB positions (7th
and 8th bits if M = 0; 8th and 9th bits if M = 0) of
the identifier character. The check is performed as
specified by the LIN specification:
– The LHDF flag in the SCICR3 register indicates
that a LIN Synch Break Field has been detected.
– An interrupt is generated if the LHIE bit in the
SCICR3 register is set and the I[1:0] bits are
cleared in the CCR register.
stop bit
parity bits
start bit
– Then the LIN Synch Field is received and meas-
ured.
identifier bits
ID0 ID1 ID2 ID3 ID4 ID5 P0 P1
– If automatic resynchronization is enabled (LA-
SE bit = 1), the LIN Synch Field is not trans-
ferred to the shift register: There is no need to
clear the RDRF bit.
Identifier Field
P0= ID0 ⊕ ID1 ⊕ ID2 ⊕ ID4
P1= ID1 ⊕ ID3 ⊕ ID4 ⊕ ID5
M = 0
– If automatic resynchronization is disabled (LA-
SE bit = 0), the LIN Synch Field is received as
a normal character and transferred to the
SCIDR register and RDRF is set.
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1
ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.5.9.4 LIN Error Detection
LIN Header Error Flag
edge of the Synch Field. Let us refer to this peri-
od deviation as D:
If the LHE flag is set, it means that:
D > 15.625%
The LIN Header Error Flag indicates that an invalid
LIN Header has been detected.
When a LIN Header Error occurs:
– The LHE flag is set
If LHE flag is not set, it means that:
D < 16.40625%
– An interrupt is generated if the RIE bit is set and
the I[1:0] bits are cleared in the CCR register.
If 15.625% ≤D < 16.40625%, then the flag can
be either set or reset depending on the dephas-
ing between the signal on the RDI line and the
CPU clock.
If autosynchronization is enabled (LASE bit = 1),
this can mean that the LIN Synch Field is corrupt-
ed, and that the SCI is in a blocked state (LSF bit is
set). The only way to recover is to reset the LSF bit
and then to clear the LHE bit.
– The second check is based on the measurement
of each bit time between both edges of the Synch
Field: this checks that each of these bit times is
large enough compared to the bit time of the cur-
rent baud rate.
– The LHE bit is reset by an access to the SCISR
register followed by a read of the SCIDR register.
When LHE is set due to this error then the SCI
goes into a blocked state (LSF bit is set).
LHE/OVR Error Conditions
When Auto Resynchronization is disabled (LASE
bit = 0), the LHE flag detects:
LIN Header Time-out Error
When the LIN Identifier Field Detection Method is
used (by configuring LHDM to 1) or when LIN
auto-resynchronization is enabled (LASE bit = 1),
– That the received LIN Synch Field is not equal to
55h.
– That an overrun occurred (as in standard SCI
mode)
the
LINSCI
automatically
monitors
the
T
condition given by the LIN protocol.
HEADER_MAX
– Furthermore, if LHDM is set it also detects that a
LIN Header Reception Timeout occurred (only if
LHDM is set).
If the entire Header (up to and including the STOP
bit of the LIN Identifier Field) is not received within
the maximum time limit of 57 bit times then a LIN
Header Error is signalled and the LHE bit is set in
the SCISR register.
When the LIN auto-resynchronization is enabled
(LASE bit = 1), the LHE flag detects:
– That the deviation error on the Synch Field is
outside the LIN specification which allows up to
+/-15.5% of period deviation between the slave
and master oscillators.
Figure 67. LIN Header Reception Timeout
– A LIN Header Reception Timeout occurred.
LIN Synch
Break
LIN Synch
Field
Identifier
Field
If T
> T
then the LHE flag is
HEADER
HEADER_MAX
set. Refer to Figure 67. (only if LHDM is set to 1)
– An overflow during the Synch Field Measure-
ment, which leads to an overflow of the divider
registers. If LHE is set due to this error then the
SCI goes into a blocked state (LSF bit is set).
T
HEADER
The time-out counter is enabled at each break de-
tection. It is stopped in the following conditions:
- A LIN Identifier Field has been received
- An LHE error occurred (other than a timeout er-
ror).
– That an overrun occurred on Fields other than
the Synch Field (as in standard SCI mode)
Deviation Error on the Synch Field
- A software reset of LSF bit (transition from high to
low) occurred during the analysis of the LIN Synch
Field or
The deviation error is checking by comparing the
current baud rate (relative to the slave oscillator)
with the received LIN Synch Field (relative to the
master oscillator). Two checks are performed in
parallel:
If LHE bit is set due to this error during the LIN
Synchr Field (if LASE bit = 1) then the SCI goes
into a blocked state (LSF bit is set).
– The first check is based on a measurement be-
tween the first falling edge and the last falling
126/309
1
ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
If LHE bit is set due to this error during Fields other
than LIN Synch Field or if LASE bit is reset then
the current received Header is discarded and the
SCI searches for a new Break Field.
LIN Header Length
Even if no timeout occurs on the LIN Header, it is
possible to have access to the effective LIN head-
er Length (T
) through the LHL register.
HEADER
Note on LIN Header Time-out Limit
This allows monitoring at software level the
condition given by the LIN protocol.
T
FRAME_MAX
According to the LIN specification, the maximum
length of a LIN Header which does not cause a
This feature is only available when LHDM bit = 1
or when LASE bit = 1.
timeout
BIT_MASTER
is
equal
to
1.4 * (34 + 1) = 49
T
.
Mute Mode and Errors
T
refers to the master baud rate.
BIT_MASTER
In mute mode when LHDM bit = 1, if an LHE error
occurs during the analysis of the LIN Synch Field
or if a LIN Header Time-out occurs then the LHE
bit is set but it does not wake up from mute mode.
In this case, the current header analysis is discard-
ed. If needed, the software has to reset LSF bit.
Then the SCI searches for a new LIN header.
When checking this timeout, the slave node is de-
synchronized for the reception of the LIN Break
and Synch fields. Consequently, a margin must be
allowed, taking into account the worst case: This
occurs when the LIN identifier lasts exactly 10
T
periods. In this case, the LIN Break
BIT_MASTER
and Synch fields last 49 - 10 = 39T
riods.
pe-
BIT_MASTER
In mute mode, if a framing error occurs on a data
(which is not a break), it is discarded and the FE bit
is not set.
Assuming the slave measures these first 39 bits
with a desynchronized clock of 15.5%. This leads
to a maximum allowed Header Length of:
When LHDM bit = 1, any LIN header which re-
spects the following conditions causes a wake-up
from mute mode:
39 x (1/0.845) T
+ 10T
BIT_MASTER
BIT_MASTER
= 56.15 T
- A valid LIN Break Field (at least 11 dominant bits
followed by a recessive bit)
BIT_SLAVE
A margin is provided so that the time-out occurs
when the header length is greater than 57
- A valid LIN Synch Field (without deviation error)
T
T
periods. If it is less than or equal to 57
periods, then no timeout occurs.
BIT_SLAVE
BIT_SLAVE
- A LIN Identifier Field without framing error. Note
that a LIN parity error on the LIN Identifier Field
does not prevent wake-up from mute mode.
- No LIN Header Time-out should occur during
Header reception.
Figure 68. LIN Synch Field Measurement
= CPU period
t
CPU
t
= 16.LP.t
CPU
t
= Baud Rate period
BR
BR
SM = Synch Measurement Register (15 bits)
t
BR
LIN Synch Field
Next
LIN Synch Break
Extra
’1’
Start
Bit
Start
Stop
Bit2
Bit6
Bit7
Bit5
Bit0 Bit1
Bit3 Bit4
Bit
Bit
Measurement = 8.T = SM.t
BR
CPU
LPR(n+1)
LPR(n)
LPR = t / (16.t
) = Rounding (SM / 128)
CPU
BR
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1
ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.5.9.5 LIN Baud Rate
mitter are both set to the same value, depending
on the LIN Slave baud rate generator:
Baud rate programming is done by writing a value
in the LPR prescaler or performing an automatic
resynchronization as described below.
f
CPU
Automatic Resynchronization
Tx = Rx =
(16 LDIV)
*
To automatically adjust the baud rate based on
measurement of the LIN Synch Field:
with:
– Write the nominal LIN Prescaler value (usually
depending on the nominal baud rate) in the
LPFR / LPR registers.
LDIV is an unsigned fixed point number. The man-
tissa is coded on 8 bits in the LPR register and the
fraction is coded on 4 bits in the LPFR register.
– Set the LASE bit to enable the Auto Synchroni-
zation Unit.
If LASE bit = 1 then LDIV is automatically updated
at the end of each LIN Synch Field.
When Auto Synchronization is enabled, after each
LIN Synch Break, the time duration between five
Three registers are used internally to manage the
auto-update of the LIN divider (LDIV):
falling edges on RDI is sampled on f
and the
CPU
- LDIV_NOM (nominal value written by software at
LPR/LPFR addresses)
result of this measurement is stored in an internal
15-bit register called SM (not user accessible)
(See Figure 68). Then the LDIV value (and its as-
sociated LPFR and LPR registers) are automati-
cally updated at the end of the fifth falling edge.
During LIN Synch field measurement, the SCI
state machine is stopped and no data is trans-
ferred to the data register.
- LDIV_MEAS (results of the Field Synch meas-
urement)
- LDIV (used to generate the local baud rate)
The control and interactions of these registers is
explained in Figure 69 and Figure 70. It depends
on the LDUM bit setting (LIN Divider Update Meth-
od)
10.5.9.6 LIN Slave Baud Rate Generation
In LIN mode, transmission and reception are driv-
en by the LIN baud rate generator
Note:
As explained in Figure 69 and Figure 70, LDIV
can be updated by two concurrent actions: a
transfer from LDIV_MEAS at the end of the LIN
Sync Field and a transfer from LDIV_NOM due
to a software write of LPR. If both operations
occur at the same time, the transfer from
LDIV_NOM has priority.
Note: LIN Master mode uses the Extended or
Conventional prescaler register to generate the
baud rate.
If LINE bit = 1 and LSLV bit = 1 then the Conven-
tional and Extended Baud Rate Generators are
disabled: the baud rate for the receiver and trans-
128/309
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 69. LDIV Read / Write Operations When LDUM = 0
Write LPFR
Write LPR
LIN Sync Field
Measurement
MANT(7:0) FRAC(3:0)
Write LPR
LDIV_NOM
LDIV_MEAS
MANT(7:0) FRAC(3:0)
Update
at end of
Synch Field
Baud Rate
Generation
MANT(7:0) FRAC(3:0)
LDIV
Read LPR
Read LPFR
Figure 70. LDIV Read / Write Operations When LDUM = 1
Write LPFR
Write LPR
LIN Sync Field
Measurement
MANT(7:0) FRAC(3:0)
RDRF = 1
LDIV_NOM
LDIV_MEAS
MANT(7:0) FRAC(3:0)
Update
at end of
Synch Field
Baud Rate
Generation
MANT(7:0) FRAC(3:0)
LDIV
Read LPR
Read LPFR
129/309
1
ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.5.9.7 LINSCI Clock Tolerance
Consequently, the clock frequency should not vary
more than 6/16 (37.5%) within one bit.
LINSCI Clock Tolerance when unsynchronized
The sampling clock is resynchronized at each start
bit, so that when receiving 10 bits (one start bit, 1
data byte, 1 stop bit), the clock deviation should
not exceed 3.75%.
When LIN slaves are unsynchronized (meaning no
characters have been transmitted for a relatively
long time), the maximum tolerated deviation of the
LINSCI clock is +/-15%.
10.5.9.8 Clock Deviation Causes
If the deviation is within this range then the LIN
Synch Break is detected properly when a new re-
ception occurs.
The causes which contribute to the total deviation
are:
This is made possible by the fact that masters
send 13 low bits for the LIN Synch Break, which
can be interpreted as 11 low bits (13 bits -15% =
11.05) by a “fast” slave and then considered as a
LIN Synch Break. According to the LIN specifica-
tion, a LIN Synch Break is valid when its duration
– D
: Deviation due to transmitter error.
TRA
Note: The transmitter can be either a master
or a slave (in case of a slave listening to the
response of another slave).
– D
: Error due to the LIN Synch measure-
MEAS
ment performed by the receiver.
is greater than t
= 10. This means that the
SBRKTS
– D : Error due to the baud rate quantiza-
tion of the receiver.
QUANT
LIN Synch Break must last at least 11 low bits.
Note: If the period desynchronization of the slave
is +15% (slave too slow), the character “00h”
which represents a sequence of 9 low bits must
not be interpreted as a break character (9 bits +
15% = 10.35). Consequently, a valid LIN Synch
break must last at least 11 low bits.
– D
: Deviation of the local oscillator of the
REC
receiver: This deviation can occur during the
reception of one complete LIN message as-
suming that the deviation has been compen-
sated at the beginning of the message.
– D
: Deviation due to the transmission line
TCL
LINSCI Clock Tolerance when Synchronized
(generally due to the transceivers)
When synchronization has been performed, fol-
lowing reception of a LIN Synch Break, the LINS-
CI, in LIN mode, has the same clock deviation tol-
erance as in SCI mode, which is explained below:
All the deviations of the system should be added
and compared to the LINSCI clock tolerance:
D
+ D
+D
+ D
+ D
< 3.75%
TCL
TRA
MEAS
QUANT
REC
During reception, each bit is oversampled 16
times. The mean of the 8th, 9th and 10th samples
is considered as the bit value.
Figure 71.Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
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1
ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.5.9.9 Error due to LIN Synch measurement
Consequently, at a given CPU frequency, the
maximum possible nominal baud rate (LPR
should be chosen with respect to the maximum tol-
erated deviation given by the equation:
)
MIN
The LIN Synch Field is measured over eight bit
times.
This measurement is performed using a counter
clocked by the CPU clock. The edge detections
are performed using the CPU clock cycle.
D
+ 2 / (128*LDIV ) + 1 / (2*16*LDIV
)
TRA
MIN
MIN
+ D
+ D
< 3.75%
TCL
REC
This leads to a precision of 2 CPU clock cycles for
the measurement which lasts 16*8*LDIV clock cy-
cles.
Example:
A nominal baud rate of 20Kbits/s at T
= 125ns
CPU
Consequently, this error (D
) is equal to:
MEAS
(8 MHz) leads to LDIV
= 25d.
NOM
2 / (128*LDIV ).
MIN
LDIV
= 25 - 0.15*25 = 21.25
MIN
LDIV
corresponds to the minimum LIN prescal-
MIN
D
D
= 2 / (128*LDIV ) * 100 = 0.00073%
MIN
MEAS
er content, leading to the maximum baud rate, tak-
ing into account the maximum deviation of +/-15%.
= 1 / (2*16*LDIV ) * 100 = 0.0015%
QUANT
MIN
10.5.9.10 Error due to Baud Rate Quantization
LIN Slave systems
The baud rate can be adjusted in steps of 1 / (16 *
LDIV). The worst case occurs when the “real”
baud rate is in the middle of the step.
For LIN Slave systems (the LINE and LSLV bits
are set), receivers wake up by LIN Synch Break or
LIN Identifier detection (depending on the LHDM
bit).
This leads to a quantization error (D
) equal
QUANT
to 1 / (2*16*LDIV ).
MIN
Hot Plugging Feature for LIN Slave Nodes
10.5.9.11 Impact of Clock Deviation on
Maximum Baud Rate
In LIN Slave Mute Mode (the LINE, LSLV and
RWU bits are set) it is possible to hot plug to a net-
work during an ongoing communication flow. In
this case the SCI monitors the bus on the RDI line
until 11 consecutive dominant bits have been de-
tected and discards all the other bits received.
The choice of the nominal baud rate (LDIV
)
)
NOM
will influence both the quantization error (D
QUANT
and the measurement error (D
). The worst
MEAS
case occurs for LDIV
.
MIN
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.5.10 LIN Mode Register Description
framing error is detected (if the stop bit is dominant
(0) and at least one of the other bits is recessive
(1). It is not set when a break occurs, the LHDF bit
is used instead as a break flag (if the LHDM
bit = 0). It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
7
0
0: No Framing error
1: Framing error detected
TDRE
TC
RDRF IDLE
LHE
NF
FE
PE
Bits 7:4 = Same function as in SCI mode, please
refer to Section 10.5.8 SCI Mode Register De-
scription.
Bit 0 = PE Parity error.
This bit is set by hardware when a LIN parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the sta-
tus register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
Bit 3 = LHE LIN Header Error.
During LIN Header this bit signals three error
types:
0: No LIN parity error
1: LIN Parity error detected
– The LIN Synch Field is corrupted and the SCI is
blocked in LIN Synch State (LSF bit = 1).
– A timeout occurred during LIN Header reception
CONTROL REGISTER 1 (SCICR1)
Read/Write
Reset Value: x000 0000 (x0h)
– An overrun error was detected on one of the
header field (see OR bit description in Section
10.5.8 SCI Mode Register Description)).
An interrupt is generated if RIE = 1 in the SCICR2
register. If blocked in the LIN Synch State, the LSF
bit must first be reset (to exit LIN Synch Field state
and then to be able to clear LHE flag). Then it is
cleared by the following software sequence: An
access to the SCISR register followed by a read to
the SCIDR register.
7
0
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bits 7:3 = Same function as in SCI mode, please
refer to Section 10.5.8 SCI Mode Register De-
scription.
0: No LIN Header error
1: LIN Header error detected
Bit 2 = PCE Parity control enable.
This bit is set and cleared by software. It selects
the hardware parity control for LIN identifier parity
check.
Note:
Apart from the LIN Header this bit signals an Over-
run Error as in SCI mode, (see description in Sec-
tion 10.5.8 SCI Mode Register Description)
0: Parity control disabled
1: Parity control enabled
When a parity error occurs, the PE bit in the
SCISR register is set.
Bit 2 = NF Noise flag
In LIN Master mode (LINE bit = 1 and LSLV bit = 0)
this bit has the same function as in SCI mode,
please refer to Section 10.5.8 SCI Mode Register
Description
Bit 1 = Reserved
In LIN Slave mode (LINE bit = 1 and LSLV bit = 1)
this bit has no meaning.
Bit 0 = Same function as in SCI mode, please refer
to Section 10.5.8 SCI Mode Register Description.
Bit 1 = FE Framing error.
In LIN slave mode, this bit is set only when a real
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
1: LDIV is updated at the next received character
(when RDRF = 1) after a write to the LPR regis-
ter
Notes:
7
0
- If no write to LPR is performed between the set-
ting of LDUM bit and the reception of the next
character, LDIV will be updated with the old value.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
- After LDUM has been set, it is possible to reset
the LDUM bit by software. In this case, LDIV can
be modified by writing into LPR / LPFR registers.
Bits 7:2 Same function as in SCI mode, please re-
fer to Section 10.5.8 SCI Mode Register Descrip-
tion.
Bit 1 = RWU Receiver wake-up.
Bits 6:5 = LINE, LSLV LIN Mode Enable Bits.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
These bits configure the LIN mode:
LINE
LSLV
Meaning
0
x
0
1
LIN mode disabled
LIN Master Mode
LIN Slave Mode
0: Receiver in active mode
1: Receiver in mute mode
1
Notes:
– Mute mode is recommended for detecting only
the Header and avoiding the reception of any
other characters. For more details please refer to
Section 10.5.9.3 LIN Reception.
The LIN Master configuration enables:
The capability to send LIN Synch Breaks (13 low
bits) using the SBK bit in the SCICR2 register.
The LIN Slave configuration enables:
– In LIN slave mode, when RDRF is set, the soft-
ware can not set or clear the RWU bit.
– The LIN Slave Baud Rate generator. The LIN
Divider (LDIV) is then represented by the LPR
and LPFR registers. The LPR and LPFR reg-
isters are read/write accessible at the address
of the SCIBRR register and the address of the
SCIETPR register
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
– Management of LIN Headers.
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
– LIN Synch Break detection (11-bit dominant).
– LIN Wake-Up method (see LHDM bit) instead
of the normal SCI Wake-Up method.
– Inhibition of Break transmission capability
(SBK has no effect)
CONTROL REGISTER 3 (SCICR3)
Read/Write
Reset Value: 0000 0000 (00h)
– LIN Parity Checking (in conjunction with the
PCE bit)
7
0
Bit 4 = LASE LIN Auto Synch Enable.
This bit enables the Auto Synch Unit (ASU). It is
set and cleared by software. It is only usable in LIN
Slave mode.
LDUM LINE LSLV
LASE
LHDM LHIE LHDF LSF
Bit 7 = LDUM LIN Divider Update Method.
This bit is set and cleared by software and is also
cleared by hardware (when RDRF = 1). It is only
used in LIN Slave mode. It determines how the LIN
Divider can be updated by software.
0: LDIV is updated as soon as LPR is written (if no
Auto Synchronization update occurs at the
same time).
0: Auto Synch Unit disabled
1: Auto Synch Unit enabled.
Bit 3 = LHDM LIN Header Detection Method
This bit is set and cleared by software. It is only us-
able in LIN Slave mode. It enables the Header De-
tection Method. In addition if the RWU bit in the
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
SCICR2 register is set, the LHDM bit selects the
Wake-Up method (replacing the WAKE bit).
0: LIN Synch Break Detection Method
Figure 72. LSF Bit Set and Clear
11 dominant bits
parity bits
1: LIN Identifier Field Detection Method
LSF bit
Bit 2 = LHIE LIN Header Interrupt Enable
This bit is set and cleared by software. It is only us-
able in LIN Slave mode.
LIN Synch
Break
LIN Synch
Field
Identifier
Field
0: LIN Header Interrupt is inhibited.
1: An SCI interrupt is generated whenever
LHDF = 1.
LIN DIVIDER REGISTERS
Bit 1 = LHDF LIN Header Detection Flag
This bit is set by hardware when a LIN Header is
detected and cleared by a software sequence (an
access to the SCISR register followed by a read of
the SCICR3 register). It is only usable in LIN Slave
mode.
LDIV is coded using the two registers LPR and LP-
FR. In LIN Slave mode, the LPR register is acces-
sible at the address of the SCIBRR register and
the LPFR register is accessible at the address of
the SCIETPR register.
0: No LIN Header detected.
LIN PRESCALER REGISTER (LPR)
Read/Write
Reset Value: 0000 0000 (00h)
1: LIN Header detected.
Notes: The header detection method depends on
the LHDM bit:
7
0
– If LHDM = 0, a header is detected as a LIN
Synch Break.
LPR7 LPR6 LPR5 LPR4 LPR3 LPR2 LPR1 LPR0
– If LHDM = 1, a header is detected as a LIN
Identifier, meaning that a LIN Synch Break
Field + a LIN Synch Field + a LIN Identifier
Field have been consecutively received.
LPR[7:0] LIN Prescaler (mantissa of LDIV)
These 8 bits define the value of the mantissa of the
LIN Divider (LDIV):
Bit 0 = LSF LIN Synch Field State
LPR[7:0]
00h
Rounded Mantissa (LDIV)
This bit indicates that the LIN Synch Field is being
analyzed. It is only used in LIN Slave mode. In
Auto Synchronization Mode (LASE bit = 1), when
the SCI is in the LIN Synch Field State it waits or
counts the falling edges on the RDI line.
SCI clock disabled
01h
1
...
...
FEh
FFh
254
255
It is set by hardware as soon as a LIN Synch Break
is detected and cleared by hardware when the LIN
Synch Field analysis is finished (See Figure 72).
This bit can also be cleared by software to exit LIN
Synch State and return to idle mode.
0: The current character is not the LIN Synch Field
1: LIN Synch Field State (LIN Synch Field under-
going analysis)
Caution: LPR and LPFR registers have different
meanings when reading or writing to them. Conse-
quently bit manipulation instructions (BRES or
BSET) should never be used to modify the
LPR[7:0] bits, or the LPFR[3:0] bits.
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN PRESCALER FRACTION REGISTER
(LPFR)
will effectively update LDIV and so the clock gen-
eration.
Read/Write
2. In LIN Slave mode, if the LPR[7:0] register is
equal to 00h, the transceiver and receiver input
clocks are switched off.
Reset Value: 0000 0000 (00h)
7
0
LPFR LPFR LPFR LPFR
Examples of LDIV coding:
Example 1: LPR = 27d and LPFR = 12d
This leads to:
0
0
0
0
3
2
1
0
Mantissa (LDIV) = 27d
Bits 7:4 = Reserved.
Bits 3:0 = LPFR[3:0] Fraction of LDIV
Fraction (LDIV) = 12/16 = 0.75d
Therefore LDIV = 27.75d
These 4 bits define the fraction of the LIN Divider
(LDIV):
Example 2: LDIV = 25.62d
This leads to:
LPFR[3:0]
Fraction (LDIV)
0h
1h
...
0
LPFR = rounded(16*0.62d)
= rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh
1/16
...
Eh
Fh
14/16
15/16
Example 3: LDIV = 25.99d
This leads to:
1. When initializing LDIV, the LPFR register must
be written first. Then, the write to the LPR register
LPFR = rounded(16*0.99d)
= rounded(15.84d) = 16d
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1
ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN HEADER LENGTH REGISTER (LHLR)
Read Only
LHL[1:0]
Fraction (57 - T
)
HEADER
0h
1h
2h
3h
0
Reset Value: 0000 0000 (00h).
1/4
1/2
3/4
7
0
LHL7 LHL6 LHL5 LHL4 LHL3 LHL2 LHL1 LHL0
Example of LHL coding:
Note: In LIN Slave mode when LASE = 1 or LHDM
= 1, the LHLR register is accessible at the address
of the SCIERPR register.
Example 1: LHL = 33h = 001100 11b
LHL(7:3) = 1100b = 12d
LHL(1:0) = 11b = 3d
Otherwise this register is always read as 00h.
This leads to:
Bits 7:0 = LHL[7:0] LIN Header Length.
Mantissa (57 - T
) = 12d
HEADER
This is a read-only register, which is updated by
hardware if one of the following conditions occurs:
- After each break detection, it is loaded with
“FFh”.
Fraction (57 - T
Therefore:
) = 3/4 = 0.75
HEADER
(57 - T
and T
) = 12.75d
= 44.25d
HEADER
- If a timeout occurs on T
00h.
, it is loaded with
HEADER
HEADER
- After every successful LIN Header reception (at
the same time than the setting of LHDF bit), it is
loaded with a value (LHL) which gives access to
the number of bit times of the LIN header length
HEADER
below:
Example 2:
57 - T
= 36.21d
HEADER
LHL(1:0) = rounded(4*0.21d) = 1d
(T
). The coding of this value is explained
LHL(7:2) = Mantissa (36.21d) = 36d = 24h
Therefore LHL(7:0) = 10010001 = 91h
LHL Coding:
T
= 57
HEADER_MAX
LHL(7:2) represents the mantissa of (57 - T
ER
Example 3:
HEAD-
)
57 - T
= 36.90d
HEADER
LHL(1:0) represents the fraction (57 - T
)
HEADER
LHL(1:0) = rounded(4*0.90d) = 4d
Mantissa
(57 - T
Mantissa
The carry must be propagated to the matissa:
LHL(7:2) = Mantissa (36.90d) + 1 = 37d =
Therefore LHL(7:0) = 10110000 = A0h
LHL[7:2]
)
(T
)
HEADER
HEADER
0h
1h
0
57
1
56
...
1
...
...
39h
3Ah
3Bh
...
56
57
58
...
0
Never Occurs
...
3Eh
3Fh
62
63
Never Occurs
Initial value
136/309
1
ST7MC1xx/ST7MC2xx
SERIAL COMMUNICATION INTERFACE (Cont’d)
Table 21. SCI Register Map and Reset Values
Addr.
Register Name
SCI1SR
7
6
5
4
3
2
1
0
(Hex.)
TDRE
TC
1
RDRF
0
IDLE
OR/LHE
NF
0
FE
0
PE
0
0018h
Reset Value
SCI1DR
1
DR7
-
0
DR4
-
0
DR3
-
DR6
-
DR5
-
DR2
-
DR1
-
DR0
-
0019h
001Ah
Reset Value
SCP1
LPR7
0
SCP0
LPR6
0
SCT2
LPR5
0
SCT1
LPR4
0
SCT0
LPR3
0
SCR2
LPR2
0
SCR1
LPR1
0
SCR0
LPR0
0
SCI1BRR
LPR (LIN Slave Mode)
Reset Value
SCI1CR1
R8
T8
SCID
0
M
WAKE
0
PCE
0
PS
0
PIE
0
001Bh
001Ch
001Dh
Reset Value
SCI1CR2
x
0
0
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
Reset Value
SCI1CR3
0
LDUM
0
LINE
0
LSLV
0
LASE
0
LHDM
0
LHIE
0
LHDF
0
LSF
0
Reset Value
SCI1ERPR
ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0
LHL7
LHL6
LHL5
LHL4
LHL3
LHL2
LHL1
LHL0
001Eh
001Fh
LHLR (LIN Slave Mode)
Reset Value
0
0
0
0
0
0
0
0
ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0
SCI1TPR
0
0
0
0
0
0
0
0
LPRF3
0
LPRF2 LPRF1 LPRF0
LPRF (LIN Slave Mode)
Reset Value
0
0
0
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ST7MC1xx/ST7MC2xx
10.6 MOTOR CONTROLLER (MTC)
10.6.1 Introduction
Table 22. MTC Functional Blocks
The ST7 Motor Controller (MTC) can be seen as a
Three-Phase Pulse Width Modulator multiplexed
on six output channels and a Back Electromotive
Force (BEMF) zero-crossing detector for sensor-
less control of Permanent Magnet Direct Current
(PM BLDC) brushless motors.
Section
Input Detection Block
Input Pins
Page
146
146
149
150
151
153
Sensorless Mode
D Event detection
The MTC is particularly suited to driving brushless
motors (either induction or permanent magnet
types) and supports operating modes like:
Z Event Detection
Demagnetization (D) Event
Z Event Generation (BEMF Zero Crossing) 155
– Commutation step control with motor voltage
regulation and current limitation
Protection for ZH event detection
Position Sensor Mode
Sampling block
157
158
159
162
164
164
165
166
168
169
171
172
175
180
185
185
185
186
186
186
188
188
190
191
191
194
199
200
200
201
201
201
205
205
206
206
– Commutation step control with motor current
regulation, i.e. direct torque control
Commutation Noise Filter
Speed Sensor Mode
Tachogenerator Mode
Encoder Mode
– Position Sensor or sensorless motor phase com-
mutation control (six-step mode)
– BEMF zero-crossing detection with high sensitiv-
ity. The integrated phase voltage comparator is
directly referred to the full BEMF voltage without
any attenuation. A BEMF voltage down to
200 mV can be detected, providing high noise
immunity and self-commutated operation in a
large speed range.
Summary
Delay Manager
Switched Mode
Autoswitched Mode
Debug Option
– Realtime motor winding demagnetization detec-
tion for fine-tuning the phase voltage masking
time to be applied before BEMF monitoring.
Checks and Controls for simulated events
Speed Measurement Mode
Summary
– Automatic and programmable delay between
BEMF zero-crossing detection and motor phase
commutation.
PWM Manager
Voltage Mode
Over Current Handling in Voltage mode
Current Mode
– PWM generation for three-phase sinewave or
three-channel independent PWM signals.
Current Feedback Comparator
Current feedback amplifier
Measurement Window
Channel Manager
MPHST Phase State Register
Emergency Feature
Dead Time Generator
Programmable Chopper
PWM Generator Block
Main Features
Functional Description
Prescaler
PWM Operating mode
Repetition Down-Counter
PWM interrupt generation
Timer Re-synchronisation
PWM generator initialization and start-up
138/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Table 23. MTC Registers
10.6.2 Main Features
■ Two on-chip analog comparators, one for BEMF
zero-crossing detection, the other for current
regulation or limitation
■ Seven selectable reference voltages for the
hysteresis comparator (0.2 V, 0.6 V, 1 V, 1.5 V,
2 V, 2.5 V, 3.5 V) and the possibility to select an
external reference pin (MCVREF).
Register
page
(RPGS
bit)
Register
Description
Page
MTIM
Timer Counter Register
0
207
207
Timer LSB (mode depend-
ent)
MTIML
0
■ 8-bit timer (MTIM) with three compare registers
and two capture features, which may be used as
the Delay manager of a speed measurement
unit
MZPRV Capture Z Register
0
0
0
0
0
0
0
0
0
0
0
0
0
207
207
207
207
208
208
208
209
210
212
213
214
216
n-1
MZREG Capture Z Register
n
MCOMP Compare C
Register
n+1
MDREG Demagnetization Reg.
■ Measurement window generator for BEMF
MWGHT A Weight Register
n
zero-crossing detection
MPRSR Prescaler & Sampling Reg.
■ Filter option for the zero-crossing detection.
■ Auto-calibrated prescaler with 16 division steps
■ 8x8-bit multiplier
■ Phase input multiplexer
■ Sophisticated output management:
MIMR
MISR
Interrupt Mask Register
Interrupt Status Register
Control Register A
MCRA
MCRB
MCRC
Control Register B
Control Register C
– The six output channels can be split into two
MPHST Phase State Register
groups (high & low)
MDFR
D Event Filter Register
– The PWM signal can be multiplexed on high,
low or both groups, alternatively or simultane-
ously, for six-step motor drives
Current Feedback Filter
Register
MCFR
0
215
– 12-bit PWM generator with full modulation ca-
pability (0 and 100% duty cycle), edge or cent-
er-aligned patterns
– Dedicated interrupt for PWM duty cycles up-
dating and associated PWM repetition coun-
ter.
MREF
MPCR
MREP
Reference register
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
217
218
219
219
219
219
219
220
220
220
220
221
222
223
224
225
226
227
PWM Control Register
Repetition Counter Reg.
MCPWH Compare W Register High
MCPWL Compare W Register Low
MCPVH Compare V Register High
MCPVL Compare V Register Low
MCPUH Compare U Register High
MCPUL Compare U Register Low
MCP0H Compare 0 Register High
MCP0L Compare 0 Register Low
– Programmable deadtime insertion unit.
– Programmable High frequency Chopper in-
sertion and high current PWM outputs for di-
rect optocoupler drives.
– The output polarity is programmable channel
by channel.
– A programmable bit (active low) forces the
outputs in HiZ, Low or High state, depending
on option byte 1 (refer to “ST7FMC Device
Configuration And Ordering Information” sec-
tion).
– An “emergency stop” input pin (active low)
asynchronously forces the outputs in HiZ, Low
or High state, depending on option byte 1 (re-
fer to “ST7FMC Device Configuration And Or-
dering Information” section).
MDTG
MPOL
Dead Time Generator reg.
Polarity Register
MPWME PWM register
MCONF Configuration register
MPAR
MZFR
MSCR
Parity register
Z Event Filter Register
Sampling Clock Register
139/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.3 Application Example: PM BLDC motor
drive
The end of demagnetization event (D), is also de-
tected by the MTC or simulated with a timer com-
pare feature when no detection is possible.
This example shows a six-step command se-
quence for a 3-phase permanent magnet DC
brushless motor (PM BLDC motor). Figure 74
shows the phase steps and voltage, while Table
24 shows the relevant phase configurations.
The MTC manages these three events always in
the same order: Z generates C after a delay com-
puted in realtime, then waits for D in order to ena-
ble the peripheral to detect another Z event.
To run this kind of motor efficiently, an autoswitch-
ing mode has to be used, i.e. the position of the ro-
tor must self-generate the powered winding com-
mutation. The BEMF zero crossing (Z event) on
the non-excited winding is used by the MTC as a
rotor position sensor. The delay between this
event and the commutation is computed by the
The BEMF zero-crossing event (Z), can also be
detected by the MTC or simulated with a timer
compare feature when no detection is possible.
The speed regulation is managed by the micro-
controller, by means of an adjustable reference
current level in case of current control, or by direct
PWM duty-cycle adjustment in case of voltage
control.
MTC and the hardware commutation event C is
n
automatically generated after this delay.
After the commutation occurs, the MTC waits until
the winding is completely demagnetized by the
free-wheeling diode: during this phase the winding
is tied to 0V or to the HV high voltage rail and no
BEMF can be read. At the end of this phase a new
BEMF zero-crossing detection is enabled.
140/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 73. Chronogram of Events (in Autoswitched Mode)
.
C
event
H
Z
or Z event
S
H
D
event
H
D event
S
Cn processing
Wait for C
Wait for D
n
n
Wait for Z
T
Z
n
D
C
n
n
t
Voltage on phase A
Voltage on phase B
Voltage on phase C
BEMF
sampling
P signal when sampled
(Output of the
V
DD
analog MUX)
V
REF
V
(Threshold value for
SS
Input comparator)
141/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 74. Example of Command Sequence for 6-step Mode (typical 3-phase PM BLDC Motor
Control)
Σ
Σ
Σ
Σ
Σ
Σ
Σ
Σ
Σ
3
1
2
3
4
5
6
1
2
Step
HV
Switch
0
1
2
3
4
T0
T2
T4
B
I
I
6
1
I
4
I
3
5
I
A
2
C
I
5
Node
HV
HV/2
0
A
B
C
T1
T3
T5
HV
HV/2
0
HV
HV/2
0
Note: Control & sampling PWM influence is not represented on these simplified chronograms.
Σ
Σ
Σ
Σ
Σ
Σ
5
6
1
2
3
4
HV
C
2
C
4
D
2
HV/2
Superimposed voltage
(BEMF induced by rotor)
- approx. HV/2 (PWM on)
- approx. 0V (PWM off)
0V
Z
D
Z
5
5
2
t
PWM off pulses
Demagnetization
Commutation delay
Wait for BEMF = 0
142/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
All detections of Z events are done during a short
the low side winding voltage is also held at 0V by
the low side ON switch and the complete BEMF
voltage is present on the third winding: detection is
then possible.
n
measurement window while the high side switch is
turned off. For this reason the PWM signal is ap-
plied on the high side switches.
When the high side switch is off, the high side
winding is tied to 0V by the free-wheeling diode,
Table 24. Step Configuration Summary
Configuration
Step
Σ
Σ
Σ
Σ
Σ
Σ
6
1
2
3
4
5
Current direction
High side
A to B
A to C
T0
B to C
T2
B to A
T2
C to A
T4
C to B
T4
T0
T3
Low side
T5
T5
T1
T1
T3
OO[5:0] bits in MPHST register
001001
100001
100100
000110
010010
011000
Measurement done on:
IS[1:0] bits in MPHST register
Back EMF shape
MCIC
10
MCIB
01
MCIA
00
MCIC
10
MCIB
01
MCIA
00
Falling
Rising
Falling
Rising
Falling
Rising
CPB bit in MCRB register
(ZVD bit = 0)
0
1
0
1
0
1
Voltage on measured point at the
start of demagnetization
0V
HV
0V
HV
0V
HV
HDM-SDM bits in MCRB register
10
11
10
11
10
11
PWM side selection to accelerate
demagnetization
Low Side High Side Low Side High Side Low Side High Side
Driver selection to accelerate de-
magnetization
T3
T0
T5
T2
T1
T4
For a detailed description of the MTC registers,
see Section 10.6.13.
The variable voltage levels to be applied on the
motor terminals come from continuously varying
duty cycle, from one PWM period to the other (re-
fer to Figure 75 on page 144). The PWM counter
generates a dedicated Update event (U event)
which:
10.6.4 Application Example: AC Induction
Motor Drive
Although the command sequence is rather differ-
ent between a PM BLDC and an AC three-phase
induction motor, the Motor Controller can be con-
figured to generate three-phase sinusoidal voltag-
es.
– updates automatically the compare registers set-
ting the duty cycle to avoid time critical issues
and ensure glitchless PWM operation.
– generates a dedicated U interrupt in which the
values for the next coming update event are
loaded in compare preload registers.
A timer with three independent PWM channels is
available for this purpose. Based on each of the
PWM reference signal, two complemented PWM
signals with deadtime are generated on the output
pins (6 in total), to drive directly an inverter with tri-
ple half bridge topology.
The shape of the output voltage (voltage, frequen-
cy, sinewave, trapezoid, ...) is completely man-
aged by the applicative software, in charge of
computing the compare values to be loaded for a
given PWM duty-cycle (refer to Figure 76).
143/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Finally, the PWM modulated voltage generated by
the power stage is smoothed by the motor induct-
ance to get sinusoidal currents in the stator wind-
ings.
perform speed acquisition of the most common
speed sensor, without the need of an additional
standard timer.
This speed measurement timer with clear-on-cap-
ture and clock prescaler auto-setting allows to
keep the CPU load to a minimum level while taking
benefit of the embedded input comparator and
edge detector.
The induction motor being asynchronous, there is
no need to synchronize the rotor position to the
sinewave generation phase in most of the applica-
tions.
Part of the MTC dedicated to delay computation
and event sampling can thus be reconfigured to
Figure 75. Complementary PWM generation for three-phase induction motor (1 phase represented)
U event
Compare preload
register processing
MCP0
MCPU
PWM generator
counter
PWM Ref
Signal
MCO1
MCO0
Dead time
insertion
144/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 76. Typical command signals of a three-phase induction motor
HV
Phase A *
Phase B *
T0
T2
T4
B
Phase C *
A
C
PWM
period
PWM output
Duty Cycle
T1
T3
T5
PWM output
Duty Cycle
99% 100% 99%
51%
50%
49%
PWM output
Duty Cycle
1%
0%
1%
* These simplified chronograms represent the phase voltages after low-pass filtering of the
PWM outputs reference signals
145/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.5 Functional Description
to Table 35 for set-up information). The block dia-
gram is shown in Figure 78 for the Position Sen-
sor/Sensorless modes (TES[1:0] = 00) and in Fig-
ure 88 for the Speed Sensor mode (TES[1:0] = 01,
10, 11).
The MTC can be split into five main parts as
shown in the simplified block diagram in Figure 77.
Each of these parts may be configured for different
purposes:
■ INPUT DETECTION BLOCK with a comparator,
an input multiplexer and an incremental encoder
interface, which may work as:
10.6.6.1 Input Pins
The MCIA, MCIB and MCIC input pins can be
used as analog or as digital pins.
– A BEMF zero-crossing detector
– A Speed Sensor Interface
– In sensorless mode, the analog inputs are used
to measure the BEMF zero crossing and to de-
tect the end of demagnetization if required.
■ The DELAY MANAGER with an 8/16-bit timer
and an 8x8 bit multiplier, which may work as a:
– In sensor mode, the analog inputs are used to
get the Hall sensor information.
– 8-bit delay manager
– Speed Measurement unit
– In speed sensor mode (e.g. tachogenerator), the
inputs are used as digital pins. When using an
AC tachogenerator, a small external circuit may
be needed to convert the incoming signal into a
square wave signal which can be treated by the
MTC.
■ The
PWM
MANAGER,
including
a
measurement window generator,
selector and a current comparator.
a
mode
■ The CHANNEL MANAGER with the PWM
multiplexer, polarity programming, deadtime
insertion and high frequency chopping
capability and emergency HiZ configuration
input.
■ The THREE-PHASE PWM GENERATOR with
12-bit free-running counter and repetition
counter.
Due to the presence of diodes, these pins can per-
manently support an input current of 5mA. In sen-
sorless mode, this feature enables the inputs to be
connected to each motor phase through a single
resistor.
A multiplexer, programmed by the IS[1:0] bits in
the MPHST register selects the input pins and
connects them to the control logic in either sensor-
less or tachogenerator mode. In encoder mode, it
is mandatory to connect sensor digital outputs to
the MCIA and MCIB pins.
10.6.6 Input Detection Block
This block can operate in Position sensor mode, in
sensorless mode or in Speed Sensor mode. The
mode is selected via the SR bit in the MCRA reg-
ister and the TES[1:0] bits in MPAR register (refer
146/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 77. Simplified MTC Block Diagram
BEMF ZERO-CROSSING
DETECTOR
DELAY MANAGER
or SPEED MEASURE UNIT (not represented)
MCIA
MCIB
MCIC
BEMF=0
[Z]
MTIM
TIMER
DELAY
WEIGHT
CAPTURE Zn
MCVREF
TACHO
Int/Ext
Encoder Unit
=?
DELAY = WEIGHT x Zn
INPUT DETECTION
COMMUTE [C]
MCO5
MCO4
MCO3
MCO2
MCO1
MCO0
MEASUREMENT
WINDOW
GENERATOR
(I)
CURRENT
VOLTAGE
(V)
(I)
(V)
MODE
U, V, W
NMCES
OAP
OAON bit
Phases
+
-
CFAV bit
OAN
OAZ(MCCFI1)
PWM MANAGER
MCCFI0
V
DD
ADC
R
1
MCCREF
(V)
(I)
Phase U
CHANNEL
MANAGER
R
2
C
12-bit THREE-PHASE
PWM GENERATOR
R
3
1
12-bit counter
(V)
PCN bit
Phase U
Phase V
Phase W
MCPWMU
MCPWMV
MCPWMW
[Z] : Back EMF Zero-crossing event
Z : Time elapsed between two consecutive Z events
n
[C] : Commutation event
C : Time delayed after Z event to generate C event
n
(I): Current mode
(V): Voltage mode
147/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 78. Input Stage in Sensorless or Sensor Mode (bits TES[1:0] = 00)
Event Detection
Input Comparator Block
Input Block
MPHST Register
Input Sel Reg
IS[1:0]
MDFR Register
DWF[3:0]
n
1
2
SR bit
MCIA
MCIB
C
MZFR Register
ZWF[3:0]
S,H
A
B
C
00
MCRA Register
01
10
+
-
Sample
D
Q
MCIC
CP
D
S,H
C
MCVREF
S,H
111
V
REF
MCRC Register
MCONF Register
SPLG bit
DS[3:0] bits
VR[2:0]
MCRC Register
f
SCF
Sampling frequency
I
12-bit PWM generator Signal U
MCRA Register
V0C1 bit
V
Notes
:
Updated/Shifted on R
Reg
MCRA Register
PZ bit
MCRB Register MPOL Register
Updated with Reg
on C
n+1
CPB bit*
ZVD bit
I
C
urrent Mode
Voltage Mode
n
V
events:
Commutation
BEMF Zero-crossing
End Of Demagnetization
Emergency Stop
Ratio Updated (+1 or -1)
Multiplier Overflow
Z Event Generation
C
Z
MPOL Register
REO bit
D
S,H
D
S,H
C
S,H
E
+/-
R
O
or
or
or
to Z Generation
H
1
2
Branch taken after C event
Branch taken after D event
Sample
2
1
D Event Generation
MCRA Register
SR bit
or
to D Generation
H
CPB bit* HDM bit*
n
n
MCRB Register
* = Preload register, changes taken into account at next C event
148/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.2 Sensorless Mode
voltage is near to ground voltage (instead of V /2
DD
when the excited windings are powered) and the
complete BEMF voltage is present on the non-ex-
cited winding terminal, referred to the ground ter-
minal.
This mode is used to detect BEMF zero crossing
and end of demagnetization events.
The analog phase multiplexer connects the non-
excited motor winding to an analog 100mV hyster-
esis comparator referred to a selectable reference
voltage.
The zero crossing sampling frequency is then de-
fined, in current mode, by the measurement win-
dow generator frequency (SA[3:0] bits in the
MPRSR register) or, in voltage mode, by the PWM
generator frequency and phase U duty cycle.
IS[1:0] bits in MPHST register allow to select the
input which will be drive to the comparator (either
MCIA, B or C). Be careful that the comparator is
OFF until CKE and/or DAC bit are set in MCRA
register.
During a short period after a phase commutation
(C event), the winding where the back-emf will be
read is no longer excited but needs a demagneti-
sation phase during which the BEMF cannot be
read. A demagnetization current goes through the
free-wheeling diodes and the winding voltage is
stuck at the high voltage or to the ground terminal.
For this reason an “end of demagnetization event”
D must be detected on the winding before the de-
tector can sense a BEMF zero crossing.
The VR[2:0] bits in the MCRC register select the
reference voltage from seven internal values de-
pending on the noise level and the application volt-
age supply. The reference voltage can also be set
externally through the MCVREF pin when the
VR[2:0] bits are set.
Table 25. Threshold voltage setting
For the end-of-demagnetization detection, no spe-
cial PWM configuration is needed, the comparator
VR2 VR1 VR0
Vref voltage threshold
Threshold voltage set by
external MCVREF pin
sensing is done at a selectable frequency (f
see Table 82.
),
SCF
1
1
1
So, the three events: C (commutation), D (demag-
netization) and Z (BEMF zero crossing) must al-
ways occur in this order in autoswitched mode
when hard commutation is selected.
1
1
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
3.5V*
2.5V*
2V*
The comparator output is processed by a detector
that automatically recognizes the D or Z event, de-
pending on the CPB or ZVD edge and level config-
uration bits as described in Table 30.
1.5V*
1V*
0.6V*
0.2V*
To avoid wrong detection of D and Z events, a
blanking window filter is implemented for spike fil-
tering. In addition, by means of an event counter,
software can filter several consecutive events up
to a programmed limit before generating the D or Z
event internally. This is shown in Figure 79 and
Figure 80.
*Typical value for V =5V.
DD
BEMF detections are performed during the meas-
urement window, when the excited windings are
free-wheeling through the low side switches and
diodes. At this stage the common star connection
149/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.3 D Event detection
C to D window fil-
DWF3 DWF2 DWF1 DWF0 ter in Sensorless SR=1
Mode (SR=0)
In sensorless mode, the D Window Filter becomes
active after each C event. It blanks out the D event
during the time window defined by the DWF[3:0]
bits in the MDFR register (see Table 26). The reset
value is 200µs.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5 µs
10 µs
15 µs
20 µs
25 µs
30 µs
35 µs
40 µs
60 µs
80 µs
100 µs
120 µs
140 µs
160 µs
180 µs
200 µs
This Window Filter becomes active after both
hardware and software C events.
The D Event Filter becomes active after the D Win-
dow Filter. It counts the number of consecutive D
events up to a limit defined by the DEF[3:0] bits in
the MDFR register. The reset value is 1. The D bit
is set when the counter limit is reached.
Sampling is done at a selectable frequency
(f
), see Table 82.
SCF
The D event filter is active only for a hardware D
event (D ). For a simulated (D ) event, it is forced
H
S
to 1.
Figure 79. D Window and Event Filter Flowchart
C
Note: Times are indicated for 4 MHz f
PERIPH
Table 27. D Event filter Setting
WINDOW
FILTER
DEF3 DEF2 DEF1 DEF0 D event Limit SR=1
End of
No
Blanking Window
?
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
Yes
4
Sampling
5
EVENT
FILTER
6
7
D
Event
?
No
Yes
8
9
10
11
12
13
14
15
16
No
Reset counter
Limit=1?
Yes
Increment counter
Counter=Limit?
No
Yes
Set the D bit
150/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.4 Z Event Detection
Table 28. Z Window filter Setting
In sensorless mode, the Z window filter becomes
active after each D event. It blanks out the Z event
during the time window defined by the ZWF[3:0]
bits in the MZFR register (see Table 28). The reset
value is 200µs. This Window Filter becomes active
after both hardware and software D events.
D to Z window fil-
ZWF3 ZWF2 ZWF1 ZWF0 ter in Sensorless SR=1
Mode (SR=0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5 µs
10 µs
15 µs
20 µs
25 µs
30 µs
35 µs
40 µs
60 µs
80 µs
100 µs
120 µs
140 µs
160 µs
180 µs
200 µs
The Z Event Filter becomes active after the Z Win-
dow Filter. It counts the number of consecutive Z
events up to a limit defined by the ZEF[3:0] bits in
the MZFR register. The reset value is 1. The Z bit
is set when the counter limit is reached.
No
Win-
dow
Filter
after
D
Sampling is done at a selectable frequency
(f
), see Table 82.
SCF
The Z event filter is active only for a hardware Z
event (Z ). For a simulated (Z ) event, it is forced
event
H
S
to 1. Z event filter is also active in sensor mode.
Figure 80. Z Window and Event Filter Flowchart
D
WINDOW
FILTER
Note: Times are indicated for 4 MHz f
PERIPH
End of
Blanking
Window
No
Table 29. Z Event filter Setting
ZEF3 ZEF2 ZEF1 ZEF0
Z event Limit
?
Yes
Sampling
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
EVENT
FILTER
Yes
3
Z
Event
?
No
4
5
6
No
Reset counter
Limit=1?
Yes
7
8
Increment counter
9
10
11
12
13
14
15
16
No
Counter=Limit?
Yes
Set the Z bit
151/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Table 30 shows the event control selected by the
ZVD and CPB bits. In most cases, the D and Z
events have opposite edge polarity, so the ZVD bit
is usually 0.
Table 30. ZVD and CPB Edge Selection Bits
ZVD bit
CPB bit
Event generation vs input data sampled
DWF
DWF
ZWF
ZEF
DEF
0
0
C
D
Z
Z
H
ZEF
ZWF
0
1
1
1
0
1
DEF
DEF
C
D
H
ZEF
ZEF
DWF
ZWF
C
D
Z
Z
H
DWF
ZWF
DEF
C
D
H
Note: The ZVD bit is located in the MPOL register, the CPB bit is in the MCRB register.
Legend:
DWF= D window filter
DEF= D event filter
ZWF = Z window filter
ZEF = Z event filter
Refer also to Table 34 on page 162.
152/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.5 Demagnetization (D) Event
not precede a D event because the latter could
H
be detected as a Z event.
At the end of the demagnetization phase, current
no longer goes through the free-wheeling diodes.
The voltage on the non-excited winding terminal
goes from one of the power rail voltages to the
common star connection voltage plus the BEMF
voltage. In some cases (if the BEMF voltage is
positive and the free-wheeling diodes are at
ground for example) this end of demagnetization
can be seen as a voltage edge on the selected
MCIx input and it is called a hardware demagneti-
Simulated demagnetization can also be always
used if the HDM bit is reset and the SDM bit is set.
This mode works as a programmable masking
time between the C and Z events. To drive the
H
motor securely, the masking time must be always
greater than the real demagnetization time in order
to avoid a spurious Z event.
When an event occurs, (either D or D ) the DI bit
H
S
in the MISR register is set and an interrupt request
is generated if the DIM bit of register MIMR is set.
zation event D . See Table 30.
H
The D event filter can be used to select the
number of consecutive D events needed to gener-
Caution 1: Due to the alternate automatic capture
and compare of the MTIM timer with MDREG reg-
ate the D event.
H
ister by D and D events, the MDREG register
H S
should be manipulated with special care.
If enabled by the HDM bit in the MCRB register,
the current value of the MTIM timer is captured in
register MDREG when this event occurs in order
to be able to simulate the demagnetization phase
for the next steps.
Caution 2: Due to the event generation protection
in the MZREG, MCOMP and MDREG registers for
Soft Event generation ( See “Built-in Checks and
Controls for simulated events” on page 175.), the
value written in the MDREG register in soft demag-
netisation mode (SDM=1) is checked by hardware
after the C event. If this value is less than or equal
to the MTIM counter value at this moment, the
Software demagnetisation event is generated im-
mediately and the MTIM current value overwrites
the value in the MDREG register to be able to re-
use the right demagnetisation time for another
simulated event generation.
When enabled by the SDM bit in the MCRB regis-
ter, demagnetization can also be simulated by
comparing the MTIM timer with the MDREG regis-
ter. This kind of demagnetization is called simulat-
ed demagnetization D .
S
If the HDM and SDM bits are both set, the first
event that occurs, triggers a demagnetization
event. For this to work correctly, a D event must
S
Figure 81. D Event Generation Mechanism
D
C
S,H
§
MTIM [8-bit Up Counter]
To Z event detection
8
2
1
D
Sample
H
§
MDREG [D ]
n
SPLG bit
MCRC
or
Register
Compare
MCRB Register
CPB bit* HDM bit*
n
n
SDM* bit
MDFR Register
DWF[3:0]
SR bit
MCRB Register
MCRA Register
DWF[3:0]
DEF[3:0]
D
S
MDFR Register
D
H
D
D
D
S
H
D = D & HDM bit + D & SDM bit
H
S
F(x)
To interrupt generator
HDM bit
SDM bit
§
Register updated on R event
* = Preload register, changes taken into account at next C event
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Table 31. Demagnetisation (D) Event Generation (example for ZVD=0)
HDM
Meaning
CPB bit = 1
CPB bit = 0
bit
D = D = Output Compare [MDREG, MTIM registers]
S
Undershoot due to
Weak / null
motor parasite or first
sampling
undershoot and
BEMF positive
Σ
Σ
2
2
Σ
5
HVV
HV
HVV
D
C
S
C
H
Simulated Mode
D
H
S
0
(SDM bit =1 and
HDM bit = 0)
D
(*)
S
C
H
HV/2
HV/2
HV/2
(*)
(*)
0V
0V
0V
Z
Z
Z
D = D
D = D + D
H
H
S
(Hardware detection only)
(Hardware detection or Output compare true)
Undershoot due to
motor parasite or first
Weak / null
undershoot and
sampling
BEMF positive
Σ
Σ
2
2
Σ
5
HV
HV
HV
C
H
Hardware/Simulat-
ed Mode
D
S
C
H
1
D
(*)
S
(SDM bit = 1 and
HDM bit = 1)
C
H
HV/2
HV/2
HV/2
(*)
(*)
0V
0V
0V
Z
D
D
H
H
Z
Z
(*) Note: This is a zoom to the additional voltage induced by the rotor (Back EMF)
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1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.6 Z Event Generation (BEMF Zero
Crossing)
BEMF sensing (high side group). It has to be con-
figured whatever the sampling mode.
When both C and D events have occurred, the
PWM may be switched to another group of outputs
(depending on the OS[2:0] bits in the MCRB regis-
ter) and the real BEMF zero crossing sampling can
start (see Figure 87). After Z event, the PWM can
also be switched to another group of outputs be-
fore the next C event.
When enabled by the HZ bit in MCRC register, the
current value of the MTIM timer is captured in reg-
ister MZREG when this event occurs in order to be
able to compute the real delay in the delay manag-
er part for hardware commutation but also to be
able to simulate zero-crossing events for other
steps.
A BEMF voltage is present on the non-powered
terminal but referred to the common star connec-
When enabled by the SZ bit set in the MCRC reg-
ister, a zero-crossing event can also be simulated
by comparing the MTIM timer value with the
MZREG register. This kind of zero-crossing event
tion of the motor whose voltage is equal to V /2.
DD
When a winding is free-wheeling (during PWM off-
time) its terminal voltage changes to the other
power rail voltage, this means if the PWM is ap-
plied on the high side driver, free-wheeling will be
done through the low side diode and the terminal
will be 0V.
is called simulated zero-crossing Z .
S
If both HZ and SZ bits are set in MCRC register,
the first event that occurs, triggers a zero-crossing
event.
Depending on the edge and level selection (ZVD
and CPB) bits and when PWM is applied on the
correct group, a BEMF zero crossing detection (ei-
This is used to force the common star connection
to 0V in order to read the BEMF referred to the
ground terminal.
ther Z or Z ) sets the ZI bit in the MISR register
H
S
and generates an interrupt if the ZIM bit is set in
the MIMR register.
Consequently, BEMF reading (i.e. comparison
with a voltage close to 0V) can only be done when
the PWM is applied on the high side drivers. When
the BEMF signal crosses the threshold voltage
close to zero, it is called a hardware zero-crossing
Caution 1: Due to the alternate automatic capture
and compare of the MTIM timer with MZREG reg-
ister by Z and Z events, the MZREG register
H
S
should be manipulated with special care.
event Z . A filter can be implemented on the Z
H
H
event detection (see Figure 83).
Caution 2: Due to the event generation protection
in the MZREG, MCOMP and MDREG registers for
Soft Event generation, the value written in the
MZREG register in simuated zero-crossing mode
(SZ=1) is checked by hardware after the D (either
The Z event filter register (MZFR) is used to select
the number of consecutive Z events needed to
generate the Z event. Alternatively, the PZ bit
H
can be used to enable protection as described in
Figure 83. on page 157
D or D ) event. If this value is less than or equal
H
S
to the MTIM counter value at this moment, the sim-
ulated zero-crossing event is generated immedi-
ately and the MTIM current value overwrites the
value in the MZREG register. See “Built-in Checks
and Controls for simulated events” on page 175.
For this reason the MTC outputs can be split in two
groups called LOW and HIGH and the BEMF read-
ing will be done only when PWM is applied on one
of these two groups. The REO bit in the MPOL
register is used to select the group to be used for
The Z event also triggers some timer/multiplier op-
erations, for more details see Section 10.6.7
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 82. Z Event Generation
MCRA Register
PZ bit
MCRB Register MPOL Register
CPB bit*
ZVD bit
n
§
MTIM [8-bit Up Counter] (MSB)
8
MPOL Register
REO bit
Z
H
D
S,H
S,H
§
MZREG [Z ]
n
C
or
or
or
2
1
Sample
Compare
MCRC Register
HZ bit
To D detection
MCRC Register
SZ bit
MZFR register
ZWF[3:0]
SPLG bit
DS[3:0]
bits
ZWF[3:0]
ZEF[3:0]
Z
MZFR register
S
Z
Z
Z
H
S
H
Z = Z & HZ bit+ Z & SZ bit
H
S
Z
F(x)
SZ bit
HZ bit
To interrupt generator
§
Register updated on R event
* = Preload register, changes taken into account at next C event
156/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.7 Protection for Z event detection
once this state is detected, the Z event is gener-
H
H
ated without any verification that the state at the
comparator output of the previous sample was 1.
The purpose of this protection filter is to be sure
that the state of the comparator output at the sam-
ple before was really the opposite of the current
To avoid an erroneous detection of a hardware
zero-crossing event, a filter can be enabled by set-
ting the PZ bit in the MCRA register. This filter will
ensure the detection of a Z event on an edge
H
transition between D event and Z event.
H
state which is generating the Z event. With this
H
Without this protection, Z event detection is done
H
filter, the Z event generation is done on edge
H
directly on the current sample in comparison with
the expected state at the output of the phase com-
parator. For example, if a falling edge transition
(meaning a transition from 1 to 0 at the output of
transition level comparison.
This filter is not needed in sensor mode (SR=1)
and for simulated zero-crossing event (Z ) gener-
S
ation.
the phase comparator) is configured for Z event
H
through the CPB bit in MCRB register, then, the
state 0 is expected at the comparator output and
When the PZ bit is set, the Z event filter ZEF[3:0] in
the MZFR register is ignored.
Figure 83. Protection of Z event detection
H
V Voltage mode
I Current mode
Rz Rising edge zero-crossing
Fz Falling edge zero-crossing
C Commutation event
Current sample
Fz
C
Previous sample
Falling/Rising Edge
+
MCRB register MPOL register
R
S
R
Q
Q
Q
Q
D
D
ZVD bit
CPB* bit
-
CP
CP
Phase
Comparator
Fz
S
Direct/Filter PZ
MCRA register
bit 1
F
C Rz
Z
Rz
D
R
S
Q
D
V
Instantaneous
edge
Sampling clock
CP
Q
I
157/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.8 Position Sensor Mode
done at a selectable frequency (f
82. This means that Z event position sensoring is
more precise than it is in sensorless mode.
), see Table
SCF
In position sensor mode (SR=1 in MCRA register),
the rotor position information is given to the periph-
eral by means of logical data on the three inputs
MCIA, MCIB and MCIC (Hall sensors).
There is no minimum off time required for current
control PWM in sensor mode so the minimum off
time is set automatically to 0µs as soon as the SR
bit is set in the MCRA register and a true 100%
duty cycle can be set in the PWM compare U reg-
ister for the PWM generation in voltage mode.
For each step one of these three inputs is selected
(IS[1:0] bits in register MPHST) in order to detect
the Z event. Be careful that the phase comparator
is OFF until CKE and /or DAC bits are set in MCRA
register.
In Sensor mode, the ZEF[3:0] bits in the MZFR
register are active and can be used to define the
number of consecutive Z samples needed to gen-
erate the active event.
In sensor mode, Demagnetization and the related
features (such as the special PWM configuration,
D or D management, programmable filter) are
S
H
not available (see Table 32)
Procedure for reading sensor inputs in Direct
Access mode: In Direct Access mode, the sen-
sors can be read either when the clock are ena-
bled or disabled (depending on CKE it in MCRA
register). To read the sensor data the following
steps have to be performed:
Table 32. Demagnetisation access
SR bit
Demagnetisation feature
availabilty
MCRA register
1
0
NO
1. Select Direct Access Mode (DAC bit in MCRA
register)
YES
2. Select the appropriate MCIx input pin by means
of the IS[1:0] bits in the MPHST register
In sensor mode configuration the rotor detection
doesn’t need a particular phase configuration to
perform the measurement and a Z event can be
read from any detection window. The sampling is
3. Read the comparator output (HST bit in the
MREF register)
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.9 Sampling block
cycle can be set in the 12-bit PWM generator com-
pare register in voltage mode.
For a full digital solution, the phase comparator
output sampling frequency is the frequency of the
PWM signal applied to the switches and the sam-
pling for the Z event detection in sensorless mode
is done at the end of the off time of this PWM sig-
nal to avoid to have to re-create a virtual ground
because when the PWM signal is off, the star point
is at ground due to the free-wheeling diode. That’s
why, the sampling for Z event detection is done by
default during the OFF-state of the PWM signal
and therefore at the PWM frequency.
Specific applications can require sampling for the
Z event detection only during the ON time of the
PWM signal. This can happen when the PWM sig-
nal is applied only on the low side switches for Z
event detection. In this case, during the OFF time
of the PWM signal, the phase voltage is tied to the
application voltage V and no back-EMF signal can
be seen. During the ON time of the PWM signal,
the phase voltage can be compared to the neutral
point voltage and the Z event can be detected.
Therefore, it is possible to add a programmable
delay before sampling (which is normally done
when the PWM signal is switched ON) to perform
the sampling during the ON time of the PWM sig-
nal. This delay is set with the DS [3:0] bits in the
MCONF register.
In current mode, this PWM signal is generated by
a combination of the output of the measurement
window generator (SA[3:0] bits), the output of the
current comparator and a minimum OFF time set
by the OT[3:0] bits for system stabilisation.
In voltage mode, this PWM signal is generated by
the 12-bit PWM generator signal in the compare U
register with still a minimum OFF time required if
the sampling is done at the end of the OFF time of
the PWM signal for system stabilisation. The PWM
signal is put OFF as soon as the current feedback
reaches the current input limitation. This can add
an OFF time to the one programmed with the 12-
bit Timer.
Table 33. Delay length before sampling
Delay added to
DS3
DS2
DS1
DS0
sample at Ton
No delay added.
Sample during
Toff
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.5 µs
5 µs
For D event detection in sensorless mode, no spe-
cific PWM configuration is needed and the sam-
pling frequency (f
see Table 82) is completely
SCF,
7.5 µs
10 µs
independent from the PWM signal.
In sensor mode, the D event detection is not need-
ed as the MCIA, MCIB and MCIC pins are the dig-
ital signals coming from the hall sensors so no
specific PWM configuration is needed and the
sampling for the Z detection event is done at
12.5 µs
15 µs
17.5 µs
20 µs
f
, completely independent from the PWM sig-
22.5 µs
25 µs
SCF
nal.
In sensorless mode, if a virtual ground is created
by the addition of an external circuit, sampling for
the Z event detection can be completely independ-
ent from the PWM signal applied to the switches.
Setting the SPLG bit in the MCRC register allows a
27.5 µs
30 μs
32.5 μs
35 μs
37.5 μs
PERIPH
sampling frequency of f
for Z event detection
SCF
Note: Times are indicated for 4 MHz f
independent from the PWM signal after getting the
D (end of demagnetisation) event. This means that
the sampling order is given whatever the PWM
signal (during the ON time or the OFF time). As
soon as the SPLG bit is set in the MCRC register,
the minimum OFF time needed for the PWM signal
in current mode is set to 0µs and a true 100% duty
As soon as a delay is set in the DS[3:0] bits, the
minimum OFF time for the PWM signal is no long-
er required and it is automatically set to 0µs in cur-
rent mode in the internal sampling clock and a true
100% duty cycle can be set in the 12-bit PWM
generator compare U register if needed.
159/309
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Depending on the frequency and the duty cycle of
the PWM signal, the delay inserted before sam-
pling could cause it sample the signal OFF time in-
stead of the ON time. In this case an interrupt can
be generated and the sample will not be taken into
acount. When a sample occurs outside the PWM
signal ON time, the SOI bit in the MCONF register
is set and an interrupt request is generated if the
SOM bit is set in the MCONF register. This inter-
rupt is enabled only if a delay value has been set in
the DS[3:0] bits. In this case, the sampling is done
at the PWM frequency but only during the ON time
of the PWM signal. Figure 84 and Figure 85 shows
in detail the generation of the sampling order when
the delay is added.
For complete flexibility, the possibility of sampling
at f high frequency during the ON time of the
SCF
PWM signal is also available when the SPLG bit is
set as if there is a delay value in the DS[3:0] bits.
This means that when the sampling is to be per-
formed, after the delay a sampling window at f
SCF
frequency is opened until the next OFF time of the
PWM signal. The Sampling Out interrupt will be
generated if the delay added is longer than the
duty cycle of the PWM signal. As the SPLG bit is
set and a value has been put in the DS[3:0] bits,
no minimum off time is required for the PWM sig-
nal and it is automatically set to 0µs in current
mode. A true 100% duty cycle can be also set in
the 12-bit Timer in voltage mode. Figure 86 shows
in detail the sampling at f
ing ON time.
high frequency dur-
SCF
Figure 84. Adding the Delay to sample during ON time for Z detection
New
sample
T
Sampling
DS[3:0]
DS[3:0]
PWM signal
PWM OFF
time
Current
sample
Figure 85. Sampling Out interrupt generation
T
Sampling
To interrupt generator
SO
DS[3:0]
PWM signal
PWM OFF
time
New sample during next
OFF time. Sample not taken into
account. SO interrupt generated.
SO
Current
sample
160/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
In conclusion, there are 4 sampling types that are
available for Z event detection in sensorless
mode.
always done at the selected f
frequency (see
SCF
Table 82), independently of the PWM signal (ei-
ther during ON or OFF time). Table 34 explains the
different sampling types in sensorless and in sen-
sor mode.
1. Sampling at the end of the OFF time of the
PWM signal at the PWM frequency
Note 2: When the MOE bit in the MCRA register is
reset (MCOx outputs in reset state), and the SR bit
in the MCRA register is reset (sensorless mode)
and the SPLG bit in the MCRC register is reset
(sampling at PWM frequency) then, depending on
the state of the ZSV bit in the MSCR register, Z
event sampling can run or be stopped (and D
event is sampled).
2. Sampling, at a programmable frequency inde-
pendent of the PWM state (during ON time or
OFF time of the signal). Sampling is done at
f
, see Table 82.
SCF
3. Sampling during the ON time of the PWM sig-
nal by adding a delay at PWM frequency
4. Sampling, at a programmable frequency during
the ON time (addition of a programmable delay)
Note 3: When BEMF sampling is performed at the
end of the PWM signal off-time, the inputs in OFF-
state are grounded or put in HiZ as selected by the
DISS bit in the MSCR register.
of the PWM signal. Sampling is done at f
see Table 82.
,
SCF
Note 1: The sampling type is applied only for Z
event detection after the D event has occured.
Whatever the sampling type for Z event detection,
the sampling of the signal for D event detection is
Note 4: The ZEF[3:0] event counter in the MZFR
register is active in all configurations.
Figure 86. Sampling during ON time at f
SCF
f
SCF
during
ON time
DS[3:0]
DS[3:0]
PWM signal
PWM OFF
state
Current
sample
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1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.10 Commutation Noise Filter
that, with sampling at 1MHz (1µs), due to this filter,
1 sample are ignored directly after the commuta-
tion.
For D event detection and for Z event detection
(when SPLG bit is set while DS[3:0] bits are reset),
sampling is done at f
during the PWM ON or
This filter is active all the time for the D event and
it is active for the Z event when the SPLG bit is set
and DS[3:0] bits are cleared (meaning that the Z
event is sampled at high frequency during the
PWM ON or OFF time).
SCF
OFF time (“Sampling block” on page 159). To
avoid any erroneous detection due to PWM com-
mutation noise, an hardware filter of 1µs (for f
PER-
= 4Mhz) when PWM is put ON and when PWM
IPH
is put OFF has been implemented. This means
Table 34. Sensor/sensorless mode and D & Z event selection
Sampling
DS[3:0]
SR SPLG
bit bit
Event detection behaviour for
Window and
Event Filters
Behaviour of the
output PWM
Mode OS[2:0]
bits use
sampling clock
Z event
bits
detection
At the end of
the off time of
the PWM sig-
nal
“Before D” behaviour,
“between D and Z” be-
haviour and “after Z”
behaviour
D: f
SCF
Sensors
not used
0
0
0
0
1
0
1
0
1
x
000
000
Enabled Z: SA&OT config.
PWM frequency
During off time
or ON time of
the PWM sig-
nal
“Before D” behaviour,
“between D and Z” be-
haviour and “after Z”
behaviour
D: f
Sensors
not used
SCF
Enabled
Z: f
SCF
“Before D” behaviour,
“between D and Z” be-
haviour and “after Z”
behaviour
D: f
SCF
Not
equal to
000
During ON
Enabled Z: SA&OT config. time of the
Sensors
not used
PWM signal
PWM frequency
“Before D” behaviour,
“between D and Z” be-
haviour and “after Z”
behaviour
Not
equal to
000
During ON
time of the
PWM signal
D: f
Sensors
not used
SCF
Enabled
Z: f
SCF
During OFF No Z Window Filter
time or ON Only Z Event Filter “Before Z” behaviour
time of the
Position
Sensors
used
OS1 dis-
abled
xxx
Z: f
SCF
is active in
Sensor mode
and “after Z” behaviour
PWM signal
Note: For f
selection, see Table 82
SCF
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1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 87. Functional Diagram of Z Detection after D Event
D or D
S
H
Begin
Z Window Filter turned on
ZWF[3:0] bits in MZFR register
Switch Sampling Clock[D] -> Sampling Clock[Z]
No
Side change on
Output PWM
?
Yes
Change the side according to OS[2:0]
Wait for next sampling clock edge
No
Read enable
by REO
?
Yes
No
Filter
off
?
Yes
Read enabled
End
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1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.11 Speed Sensor Mode
tive; set-up is done with the TES[1:0] bits (keeping
in mind that TES[1:0] = 00 configuration is re-
served for Position Sensor / Sensorless Modes).
This mode is entered whenever the Tacho Edge
Selection bits in the MPAR register are not both re-
set (TES[1:0] = 01, 10 or 11). The corresponding
block diagram is shown in Figure 88.
Having only one edge selected eliminates any in-
coming signal dissymmetry, which may due to
pole-to-pole magnet dissymmetry or from a com-
parator threshold with low level signals.
Either Incremental Encoder or Tachogenerator-
type speed sensor can be selected with the IS[1:0]
bits in the MPHST register.
Figure 89 presents the signals generated internal-
ly with different tacho input and TES bit settings.
10.6.6.12 Tachogenerator Mode (IS[1:0] = 00, 01
or 10)
Note on Hall Sensors: This configuration is also
suitable for motors using 3 hall sensors for position
detection and not driven in six-step mode (refer to
“Speed Measurement Mode” on page 180).
Note on initializing the Input Stage: As the
IS[1:0] bits in the MPHST register are preload bits
(new values taken into account at C event), the in-
itialization value of the IS[1:0] bits has to be en-
tered in Direct Access mode. This is done by set-
ting the DAC bit in the MCRA register during the
speed sensor input initialization routine.
Any of the MCIx input pins can be used as a tacho-
generator input, with a digital signal (externally
amplified for instance); the two remaining pins can
be used as standard I/O ports.
A digital multiplexer connects the chosen MCIx in-
put to an edge detection block. Input selection is
done with the IS[1:0] bits in the MPHST register.
An edge selection block is used to select one of
three ways to trigger capture events: rising edge,
falling edge or both rising and falling edge sensi-
Figure 88. Input Stage in Speed Sensor Mode (TES[1:0] bits = 01, 10, 11)
Event Detection
Input Comparator Block
Input Block
Encoder
Clock
In1 Incremental
Encoder
Clk
D
Direction
In2
interface
MPHST Register
IS[1:0]
EDIR bit
MCRC Register
Input Sel
n
MCIA
MCIB
MCIC
MPAR Register
TES[1:0]
§
Tacho or
00
01
10
Encoder
Tacho
Capture
§
Tacho or
or
or
Encoder
§
Tacho or
Free I/O
§
= According to IS[1:0] bits setting
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.13 Encoder Mode (IS[1:0] = 11)
The Incremental Encoder Interface block aims at
extracting these signals. As input logic is both ris-
ing and falling edge sensitive (independently from
TES[1:0] bits setting), resulting clock frequency is
four times the one of the input signals, thus in-
creasing resolution for measurements.
Figure 90 shows the signals delivered by a stand-
ard digital incremental encoder and associated in-
formation:
– Two 90° phased square signals with variable
frequency proportional to the speed; they
must be connected to MCIA and MCIB input
pins,
It may be noticed that Direction bit (EDIR bit in
MCRC register) is read only and that it does’nt af-
fect counting direction of clocked timer (cf Section
). As a result, one cannot extract position informa-
tion from encoder inputs during speed reversal.
– Clock derived from incoming signal edges,
– Direction information determined by the rela-
tive phase shift of input signals ( + or -90°).
Figure 89. Tacho Capture events configured by the TES[1:0] bits
Tacho
input
TES[1:0]=11
TES[1:0]=01
TES[1:0]=10
Tacho
Capture
Figure 90. Incremental Encoder output signals and derived information
MCIA
Encoder
inputs
MCIB
Encoder
Clock
Direction
(EDIR bit)
Sampling of MCIA to determine direction
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Note
given by the sampling of MCIA with MCIB falling
edges.
If only one encoder output is available, it may be
input either on MCIA or MCIB and an encoder
clock signal will still be generated (in this case the
frequency will be 50% less than with two inputs.
10.6.6.14 Summary
Input Detection block set-up for the different avail-
able modes is summarized in the Table 35.
The state of EDIR bit will depend on signals
present on MCIA and MCIB pins, the result will be
Table 35. Input Detection Block set-up
TES[1:0] bits
SR
bit
IS[1:0] bits
Input Detection
Block Mode
Sensor Type
Edge sensitivity
(Tacho Edge
Selection)
(Input Selection)
00
01
10
Position Sensor
Hall, Optical,... Both rising and falling edges
1
0
00
00
00
01
10
Sensorless
N/A
N/A
Any configuration dif-
ferent from 00:
Incremental
Encoder
Both rising and falling edges
(imposed)
11
01 10 11
00
01
10
Rising edge
Falling edge
01
Speed Sensor
x
00
01
10
Tachogenerator,
Hall, Optical...
10
11
00
01
10
Both rising and falling edges
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Note on using the 3 MCIx pins as standard
I/Os: When none of the MCIx pins are needed in
the application (for instance when driving an in-
duction motor in open loop), they can be used as
standard I/O ports, by configuring the Motor Con-
troller as follows: PCN=1, TES≠0 and IS=11. This
disables the MCIx alternate functions and switch-
es off the phase comparator. The state of the MCIx
pins is summarized in Table 36.
Table 36. MCIx pin configuration summary
Input
PCN TES SR IS[1:0]
MCIA
MCIB
MCIC
Detection
Comments
Block Mode
00 Analog Input Hi-Z or GND Hi-Z or GND
01 Hi-Z or GND Analog Input Hi-Z or GND
10 Hi-Z or GND Hi-Z or GND Analog input
All MCIx pins are reserved
for the MTC peripheral
Sensorless
NA
0
11
NA
NA
NA
00
00 Analog Input Standard I/O Standard I/O
01 Standard I/O Analog Input Standard I/O
10 Standard I/O Standard I/O Analog Input
0
Position
Sensor
From 1 to 3 MCIx pins reserved
depending on sensor
1
x
All MCIx pins are standard I/Os.
Phase comparator is OFF
11 Standard I/O Standard I/O Standard I/O
NA
NA
≠0
xx
NA
NA
NA
00 Analog Input Standard I/O Standard I/O
01 Standard I/O Analog Input Standard I/O
Phase comparator is ON.
The IS[1:0] bits must not be modified
to avoid spurious event detection
in Motor Controller
NA
NA
10 Standard I/O Standard I/O Analog Input
00
x
All MCIx pins are standard I/Os.
Recommended configuration:
phase comparator OFF
11 Standard I/O Standard I/O Standard I/O
1
00
Digital Input Standard I/O Standard I/O
Speed Sensor
Tachogenerator
01 Standard I/O Digital Input Standard I/O
10 Standard I/O Standard I/O Digital Input
≠00
x
Phase comparator is OFF
Speed Sensor
Encoder
11
Digital Input Digital Input Standard I/O
*When PCN=0, TES=0 SR=0, inputs in OFF-state are put in HiZ or grounded depending on the value of
the DISS bit in the MSCR register.
Notes:
1. Analog input: Based on analog comparator and analog voltage reference. The corresponding digital
I/O is disabled and data in the DR register is not representative of data on the input.
2. Digital input: Use of standard V , V I/O level. This input can also be read via the associated I/O port.
IL
IH
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.7 Delay Manager
Figure 91. Overview of MTIM Timer in Switched and Autoswitched Mode
MCRA register
T
ratio
SWA bit
ck
Z
1
0
§
clr
8-bit Up Counter MTIM
8
C
Z
D
H
H
§
§
MDREG [D ]
MZREG [Z ]
n
n
Z
/ Z
H
S
Compare
Compare
MCRB register
SDM* bit
MCRC register
SZ bit
Filter /C
MDFR register
DWF[3:0]
Filter /D
MZFR register
ZWF[3:0]
D
Z
S
S
§
MZPRV [Z
]
n-1
To interrupt generator
To interrupt generator
To interrupt generator
C
H,S
D
S,H
§
MCOMP [C
]
n+1
Z
H,S
Compare
MCRC register
SC bit
§
C
/ C
S
= Register updated on R event
H
This part of the MTC contains all the time-related
functions, its architecture is based on an 8-bit shift
left/shift right timer shown in Figure 91. The MTIM
timer includes:
The MTIM timer module can work in two main
modes when driving synchronous motors in six-
steps mode.
In switched mode the user must process the step
duration and commutation time by software.
– An auto-updated prescaler
– A capture/compare register for simulated de-
magnetization simulation (MDREG)
In autoswitched mode the commutation action is
performed automatically depending on the rotor
position information and register contents. This is
– Two cascaded capture and one compare regis-
ters (MZREG and MZPRV) for storing the times
between two consecutive BEMF zero crossings
called the hardware commutation event C . When
H
enabled by the SC bit in the MCRC register, com-
mutation can also be simulated by writing a value
directly in the MCOMP register that is compared
with the MTIM value. This is called simulated com-
(Z events) and for zero-crossing event simula-
H
tion (Z )
S
– An 8x8 bit multiplier for auto computing the next
commutation time
mutation C (See “Built-in Checks and Controls for
S
simulated events” on page 175.).
– One compare register for phase commutation
generation (MCOMP)
Both in switched mode and autoswitched mode , if
the SC bit in the MCRC register is set (software
commutation enabled), no comparison between
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
the MCOMP and MTIM register is enabled before
a write access in the MCOMP register. This means
that if the SC bit is set and no write access is done
MCOMP. When the MTIM timer reaches this value
a commutation occurs (C event) and the MTIM
timer is reset.
At this time all registers with a preload function are
loaded (registers marked with (*) in Section
10.6.13). The CI bit of MISR is set and if the CIM
bit in the MIMR register is set an interrupt is gener-
ated.
after in the MCOMP register, no C commutation
S
event will occur.
In Speed Measurement mode, when using encod-
er or tachogenerator speed sensors (i.e. both
TES[1:0] bits in the MPAR register are not reset
The MTIM timer prescaler (Step ratio bits ST[3:0]
in the MPRSR register) is user programmable. Ac-
cess to this register is not allowed while the MTIM
timer is running (access is possible only before the
starting the timer by means of the CKE bit) but the
prescaler contents can be incremented/decre-
mented at the next commutation event by setting
the RMI (decrement) or RPI (increment) bits in the
MISR register. When this method is used, at the
next commutation event the prescaler value will be
updated but also all the MTIM timer-related regis-
ters will be shifted in the appropriate direction to
keep their value. After it has been taken into ac-
count, (at commutation) the RPI or RMI bit is reset
by hardware. See Table 38.
Only one update per step is allowed, so if both RPI
and RMI bits are set together by software, this
does not affect the MISR register: the write access
to these two bits together is not taken into account
and the previous state is kept. This means that if
either RPI or RMI bit was set before the write ac-
cess of both bits at the same time, this bit (RPI or
RMI) is kept at 1. If none of them was set before
the simultaneous write access, none of them will
be set after the write access.
and the input detection block is set-up to process
sensor signals), motor speed can be measured
but it is not possible drive a motor in six-step
mode, either sensored or sensorless.
Speed Measurement mode is useful for motors
supplied with 3-phase sinewave-modulated PWM
signals:
– AC induction motors,
– Permanent Magnet AC (PMAC) motors (al-
though it needs three position sensors, they
can be handled just like tachogenerator sig-
nals).
This mode uses only part of the Delay Manager’s
resources. For more details refer to “Speed Meas-
urement Mode” on page 180.
Table 37. Switched and Autoswitched modes
SWA
bit
MCOMP User
access
Commutation Type
0
1
Switched mode
Read/Write
Read/Write
Autoswitched mode
10.6.7.1 Switched Mode
In switched mode, BEMF and demagnetization de-
tection are already possible in order to pass in au-
toswitched mode as soon as possible but Z and D
events do not affect the timer contents.
In this mode, if an MTIM overflow occurs, it re-
starts counting from 0x00h and the OI overflow
flag in the MCRC register is set if the TES[1:0] bits
= 00.
This feature allows the motor to be run step-by-
step. This is useful when the rotor speed is still too
low to generate a BEMF. It can also run other
kinds of motor without BEMF generation such as
induction motors or switch reluctance motors. This
mode can also be used for autoswitching with all
computation for the next commutation time done
by software (hardware multiplier not used) and us-
ing the powerful interrupt set of the peripheral.
Caution: In this mode, MCOMP must never be
written to 0.
In this mode, the step time is directly written by
software in the commutation compare register
Table 38. Step Update
CKE SWA Clock
Ratio Increment
(Slow Down)
Write the ST[3:0] value directly in the MPRSR register
Ratio Decrement
(Speed-Up)
Mode
x
TES[1:0]
Read
bit
bit
State
xx
00
00
0
x
Disabled
Set RPI bit in the MISR reg- Set RMI bit in the MISR reg-
ister till next commutation ister till next commutation
Switched
1
1
0
1
Enabled
Enabled
Always
possible
Autoswitched
Speed
Automatically updated according to MZREG value
01 10 11
1
x
Enabled
measure
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 92. Step Ratio Functional Diagram
f
PERIPH
R+
MTIM Timer = 100h?
+1
1 / 2
4
MPRSR Register
ST[3:0] Bits
1 / 2Ratio
Tratio
ck
-1
Zn < 55h?
R-
2 MHz - 62.5 Hz
MTIM Timer control over T
and register operation
ratio
MTIM Timer Overflow
Z Capture with MTIM Timer Underflow (Zn < 55h)
Begin
Begin
No
No
Ratio < Fh?
Ratio > 0?
Yes
Yes
Ratio = Ratio + 1
Ratio = Ratio - 1
MZREG = MZREG x 2
MZPRV = MZPRV x 2
MDREG = MDREG x 2
Counter = Counter x 2
MZREG = MZREG / 2
MZPRV = MZPRV/2
MDREG = MDREG/2
MCOMP = MCOMP/2**
Counter = Counter/2
Compute MCOMP
End
End
Slow-down control
** Only in Auto-switched mode (SWA=1 in MCRA register)
Speed-up control
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.7.2 Autoswitched Mode
cur because no comparison will be done between
MCOMP and MTIM. Therefore, it is recommended
in autoswitched mode, when using software com-
mutation feature (SC bit is set) and for a normal
event sequence, the corresponding value to be
put in MCOMP has to be written during the Z inter-
rupt routine (because MTIM has just been reset),
so that there is no spurious comparison. If the SC
bit is set during a Z event interrupt, then , the result
of the 8*8 bits hardware multiplication can be over-
written by software in the MCOMP register. When
simulated commutation mode is enabled, the
event sequence is no longer respected, meaning
that the peripheral will accept consecutive commu-
tation events and not necessarily wait for a D
In this mode, using the hardware commutation
event C (SC bit reset in MCRC register), the
H
MCOMP register content is automatically comput-
ed in real-time as described below and in Figure
93.
The C (either C or C ) event has no effect on the
S
H
contents of the MTIM timer.
When a Z event occurs the MTIM timer value is
H
captured in the MZREG register, the previous cap-
tured value is shifted into the MZPRV register and
the MTIM timer is reset. See Figure 73.
When a Z event occurs, the value written in the
S
MZREG register is shifted into the MZPRV register
and the MTIM timer is reset.
event after a C event. In this case the MCOMP
s
register can be written immediately after the previ-
ous C event, in the C interrupt service routine for
example.
One of these two registers, (when the SC bit = 0 in
the MCRC register and depending on the DCB bit
in the MCRA register), is multiplied with the con-
tents of the MWGHT register and divided by 256.
The result is loaded in the MCOMP compare reg-
ister, which automatically triggers the next hard-
Figure 93. C Processor Block
H
§
MZREG [Z ]
n
ware commutation (C event).
H
Note: The result of the 8*8 bit multiplication, once
written in the MCOMP register is compared with
the current MTIM value to check that the MCOMP
value is not already less than the MTIM value due
Z /Z
H
S
§
MZPRV [Z
]
n-1
to the multiplication time. If MCOMP<=MTIM, a C
H
MCRA Register
DCB bit
event is generated immediately and the MCOMP
value is overwritten by the MTIM value.
n-1
n
Table 39. Multiplier Result
MWGHT [a
]
n+1
DCB bit
Commutation Delay
8
8
0
1
MCOMP = MWGHT x MZPRV / 256
MCOMP = MWGHT x MZREG / 256
MCRA Register
MCRC register
A x B / 256
After each shift operation the multiply is recomput-
ed for greater precision.
SWA bit =1 &
SC bit =0
Using either the MZREG or MZPRV register de-
pends on the motor symmetry and type.
8
§
MCOMP [C
]
n+1
The MWGHT register gives directly the phase shift
between the motor driven voltage and the BEMF.
This parameter generally depends on the motor
and on the speed.
§
= Register updated on R event
Setting the SC bit in the MCRC register enables
Note 1: An overflow of the MTIM timer generates
an RPI interrupt if the RIM bit is set.
Note 2: When simulated commutation mode is en-
abled, the D and Z event are not ignored by the
peripheral, this means that if a Z event happens,
the MTIM 8 bit internal counter will be reset.
the simulated commutation event (C ) generation.
S
This means that a write access is possible to the
MCOMP register and the MTIM value will be com-
pared directly with the value written by software in
the MCOMP register to generate the C event.
S
The comparison is enabled as soon as a write ac-
cess is done to the MCOMP register. This means
that if the SC bit is set and no write access is done
to the MCOMP register, the C event will never oc-
Note 3: To generate consecutive simulated com-
mutations (C ), the successive value has to be
S
written in the MCOMP register only after a C event
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
generation. Otherwise, the C event will never oc-
cur.
– If the prescaler contents reach the value 15, it
can no longer be automatically incremented.
When the timer reaches the value FFh, the pres-
caler and all the relevant registers remain un-
changed and no interrupt is generated, the timer
restarts counting from 0x00h and if the TES[1:0]
bits = 00, the OI bit in the MCRC register is set at
each overflow (it has to be reset by software).
The RPI bit is no longer set. The PWM is still gen-
erated and the D and Z detection circuitry still
work, enabling the capture of the maximum timer
value.
Note 4: When simulated commutation mode is en-
abled, the built-in check is active, so if the value
written in the MCOMP register is less than or equal
to MTIM, the C event is generated and the data in
the MCOMP register are overwritten by the MTIM
value.
Auto-updated Step Ratio Register:
a) In switched mode: the MTIM timer is driven by
software only and any prescaler change has to be
done by software (see page 169 for more details).
The automatically updated registers are: MTIM,
MZREG, MZPRV, MCOMP and MDREG. Access
to these registers is summarized in Table 41.
b) In autoswitched mode: an auto-updated pres-
caler always configures the MTIM timer for best
accuracy. Figure 92 shows the process of updat-
ing the Step Ratio bits:
10.6.7.3 Debug Option
In both Switched Mode and Autoswitched Mode,
setting the bit DG in MPWME register enables the
Debug Option. This option consists of outputting
the C, D and Z signals in real time on pins MCZEM
and MCDEM. This is very useful during the debug
phase of the application. Figure 94 shows the sig-
nals output on pins MCDEM and MCZEM with the
debug option.
– When the MTIM timer value reaches 100h, the
prescaler is automatically incremented in order
to slow down the MTIM timer and avoid an over-
flow. To keep consistent values, the MTIM regis-
ter and all the relevant registers are shifted right
(divided by two). The RPI bit in the MISR register
is set and an interrupt is generated (if RIM is set).
The timer restarts counting from its median value
0x80h and if the TES[1:0] bits = 00, the OI bit in
the MCRC register is set.
Note 1: When the delay coefficient equals 0/256
(C event immediately after Z event), a glitch ap-
pears on MCZEM pin to be able to see the event
even in this case.
– When a Z-event occurs, if the MTIM timer value
is below 55h, the prescaler is automatically dec-
remented in order to speed up the MTIM timer
and keep precision better than 1.2%. The MTIM
register and all the relevant registers are shifted
left (multiplied by two). The RMI bit in the MISR
register is set and an interrupt is generated if RIM
is set.
This option is also available in Speed measure-
ment mode with different signal outputs (see Fig-
ure 94):
– MCDEM toggles when a capture event is gener-
ated,
– MCZEM toggles every time a U event is gener-
ated.
– If the prescaler contents reach the value 0, it can
no longer be automatically decremented, the
MTC continues working with the same prescaler
value, i.e. with a lower accuracy. No RMI in-
terrrupt can be generated.
These signals are only available if the TES[1:0]
bits = 10, 01 or 11.
Note 2: In sensor mode, the MCDEM output pin
toggles at each C event. The MCZEM pin outputs
the Z event.
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 94. Output on pins MCDEM and MCZEM with debug option (DG bit=1)
MCDEM
MCZEM
C
C
C
C
Z
D
D
Z
Z
D
Debug outputs in Sensorless mode
MCDEM
MCZEM
C
Z
C
Z
C
Z
C
Z
C
Z
Debug outputs in Sensor mode
MCDEM
C
C
C
C
C
C
C
C
C
C
MCZEM
U events
Debug outputs in Speed Measurement mode (TES[1:0] bits equal to 01, 10 or 11).
173/309
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Note on using the auto-updated MTIM timer:
The auto-updated MTIM timer works accurately
within its operating range but some care has to be
taken when processing timer-dependent data such
as the step duration for regulation or demagnetiza-
tion.
These configuration bits are:
CPB, HDM, SDM and OS2 in the MCRB register
and IS[1:0], OO[5:0] in the MPHST register.
Note on initializing the MTC: As shown in Table 41
all the MTIM timer registers are in read-write mode
until the MTC clock is enabled (with the CKE bit).
This allows the timer, prescaler and compare reg-
isters to be properly initialized for start-up.
In sensorless mode, the motor has to be started in
switched mode until a BEMF voltage is present on
the inputs. This means the prescaler ST[3:0] bits
and MCOMP register have to be modified by soft-
ware. When running the ST[3:0] bits can only be
incremented / decremented, so the initial value is
very important.
For example if an overflow occurs when calculat-
ing
a
simulated end of demagnetization
(MCOMP+demagnetisation_time>FFh), the value
that is stored in MDREG will be:
80h+(MCOMP+demagnetization_time-FFh)/2.
Note on commutation interrupts: It is good prac-
tice to modify the configuration for the next step as
soon as possible, i.e within the commutation inter-
rupt routine.
All registers that need to be changed at each step
have a preload register that enables the modifica-
tions for a complete new configuration to be per-
formed at the same time (at C event in normal
mode or when writing the MPHST register in direct
access mode).
When starting directly in autoswitched mode (in
sensor mode for example), write an appropriate
value in the MZREG and MZPRV register to per-
form a step calculation as soon as the clock is en-
abled.
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.7.4 Built-in Checks and Controls for
simulated events
the register has to be greater than the current val-
ue of the MTIM timer when writing in the registers.
If the value written in the registers (MDREG,
MZREG or MCOMP) is already less than the cur-
rent value of MTIM, the simulated event will never
be generated and the system will be stopped.
As described in Figure 91. on page 168, MZREG,
MDREG and MCOMP registers are capture/com-
pare registers. The Compare registers are write
accessible and can be used to generate simulated
events. The value of the MTIM timer is compared
with the value written in the registers and when the
MTIM value reaches the corresponding register
value, the simulated event is generated. Simulated
event generation is enabled when the correspond-
ing bits are set:
For this reason, built-in checks and controls have
been implemented in the MTIM timer.
If the value written in one of those registers in sim-
ulated event generation mode is less than or equal
to the current value of the timer when it is com-
pared, the simulated event is generated immedi-
ately and the value of the MTIM timer at the time
the simulated event occurs overwrites the value in
the registers. Like that the value in the register re-
ally corresponds to the simulated event generation
and can be re-used to generate the next simulated
event.
– In the MCRB register for simulated demagneti-
sation
– SDM for simulated demagnetisation
– In the MCRC register for simulated zero-crossing
and commutation.
– SC for simulated commutation
– SZ for simulated zero-crossing event.
To avoid a system stop, special attention is need-
ed when writing in the register to generate the cor-
responding simulated event. The value written in
So, the value written in the registers able to gener-
ate simulated events is checked by hardware and
compare to the current MTIM value to verify that it
is greater.
Figure 95. Simulated demagnetisation / zero-crossing event generation (SC=0)
After C interrupt
After D interrupt
MDREG value checked
MZREG value checked
if MDREG<=MTIM
if MZREG<=MTIM
Immediate Z generation
S
Immediate D generation
S
Z
Z
H
H
Z
S
Z
S
D
S
D
D
H
S
C
H
C
C
H
H
During C interrupt
Z
Simulated zero-crossing
Simulated demagnetisation
Hardware zero-crossing
Hardware commutation
S
D
Simulated or Hardware D/Z events
Value written in MDREG/MZREG if
simulated event generation
S
H
Z
C
H
t
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
When using hardware commutation C , the se-
Z event occurs, the MTIM timer is reset. In Simu-
lated Commutation mode, the sequence D -> Z is
expected, and this order must be repected.
H
quence of events needed is C then D and finally
H
Z events and the value written in the registers are
checked at different times.
As the sequence of events may not be the same
when using simulated commutation, as soon as
the SC bit is set, the capture/compare feature and
protection on MCOMP register is reestablished
only after a write to the MCOMP register. This
means that as soon as the SC bit is set, if no write
access is done to the MCOMP register, no com-
mutation event will be generated, whatever the
value of MCOMP compared to MTIM at the time
SC is set. This does not depend on the running
mode: switched or autoswitched mode (SWA bit).
If software commutation event is used with a nor-
mal sequence of events C-->D-->Z, it is recom-
mended to write the MCOMP register during the Z
interrupt routine to avoid any spurious comparison
If SDM bit is set, meaning simulated demagnetisa-
tion, a value must be written in the MDREG regis-
ter to generate the simulated demagnetisation.
This value must be written after the C (either C or
s
C ) event preceding the simulated demagnetisa-
H
tion.
If SZ bit is set, meaning simulated zero-crossing
event, a value must be written in the MZREG reg-
ister to generate the simulated zero-crossing. This
value must be written after the D event (D or D )
H
S
preceding the simulated zero-crossing.
When using simulated commutation (C ), the re-
S
sult of the 8*8 hardware multiplication of the delay
manager is not taken in account and must be over-
written if the SC bit has been set in a Z event inter-
rupt and the sequence of events is broken mean-
ing that several consecutive simulated commuta-
tions can be implemented.
as several consecutive C events can be generat-
s
ed.
Note that two different simulated events can be
used in the same step (like D followed by Z ).
S
S
Note also that for more precision, it is recommend-
ed to use the value captured from the preceding
hardware event to compute the value used to gen-
erate simulated events.
As soon as the SC bit is set in the MCRC register,
the system won’t necessarily expect a D event af-
ter a C event. This can be used for an application
in sensor mode with only one Hall Effect sensor for
example.
Figure 95, Figure 96 and Figure 97 shows details
of simulated event generation.
Be careful that the D and Z events are not ignored
by the peripheral, this means that for example if a
176/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 96. Simulated commutation event generation with only 1 Hall effect sensor (SC bit =1)
After C interrupt
C interrupt
MCOMP is written for Cs event
SC reset in MCRB
if MCOMP<=MTIM
Immediate CS generation
Next C event = CH with 8*8 bit multiplication
Z
Z
Z
D
D
CS
CS
CS
CS
CH
CH
C interrupt
SC set in MCRC
Z zero-crossing event
D Demagnetisation event
C
C
Hardware commutation
Simulated commutation
H
S
t
Note: If the SC bit is set during Z event interrupt,
then the 8*8 bit hardware multiplication result must
be overwritten in the MCOMP register. Otherwise,
when the SC bit is set, the result of the multiplica-
tion is not taken into account after a Z event.
Figure 97. Simulated commutation and Z event
SC bit is reset
SC bit is set during Z IT
SC bit is already set when Z IT
the result of the
the hardware multiplication is taken
into account but the value in MCOMP
can be overwritten
occurs. The hardware multipli-
-cation is not taken into account
A value has to be written
hardware multiplication is put
in MCOMP-->C and compared
H
in the MCOMP register
with MTIM once written
Z
Z
Z
Z
D
D
D
C
H
C
s
C
s
MCOMP
register
Z zero-crossing event
D Demagnetisation event
C
C
Hardware commutation
Simulated commutation
H
S
t
177/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
The Figure 98 gives the step ratio register value
(left axis) and the number of BEMF sampling dur-
ing one electrical step with the corresponding ac-
curacy on the measure (right axis) as a function of
the mechanical frequency.
At f
=4MHz, the range covered by the Step Ra-
MTC
tio mechanism goes from 2.39 to 235000 (pole
pair x rpm) with a minimum accuracy of 1.2% on
the step period.
To read the number of samples for Zn within one
step (right Y axis), select the mechanical frequen-
cy on the X axis and the sampling frequency curve
used for BEMF detection (PWM frequency or
measurement window frequency). For example,
for N.Frpm = 15,000 and a sampling frequency of
15kHz, there are approximately 10 samples in one
step and there is a 10% error rate on the measure-
ment.
For a given prescaler value (step ratio register) the
mechanical frequency can vary between two fixed
values shown on the graph as the segment ends.
In autoswitched mode, this register is automatical-
ly incremented/decremented when the step fre-
quency goes out of this segment.
Figure 98. Step Ratio Bits decoding and accuracy results and BEMF Sampling Rate
avg Zn ~ 55h 1.2%
avg Zn ~ 7Fh 0.6%
ST[3:0]
avg Zn ~ FFh 0.4%
Step Ratio (Decimal)
BEMF
samples
ΔZn/Zn
0
1
2
1
100%
3
Fn+1 = 2.Fn
4
200 Hz
avg Zn ~ 55h 1.2%
5
15 kHz
6
3.Fn+1 = 6.Fn
avg Zn ~ 7Fh 0.6%
avg Zn ~ FFh 0.4%
7
2
4
50%
3.Fn
8
Fn
9
10
11
12
13
14
15
10 10%
0%
N.Frpm
F
= 6.N.F
= N.F / 10 ⇔ N.F = 10.F
step
step
rpm
F
: Electrical step frequency
step
N: Pole pair number
178/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Table 40. Step Frequency/Period Range (4MHz)
Step Ratio Bits
Maximum
Minimum
Minimum
Step Period
Maximum
Step Period
ST[3:0] in MPRSR
Register
Step Frequency
Step Frequency
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
23.5 kHz
11.7 kHz
5.88 kHz
2.94 kHz
1.47 kHz
735 Hz
7.85 kHz
3.93 kHz
1.96 kHz
980 Hz
42.5 μs
85 μs
127.5 μs
255 μs
510 μs
170 μs
340 μs
680 μs
1.36 ms
2.72 ms
5.44 ms
10.9 ms
21.8 ms
43.6 ms
87 ms
1.02 ms
2.04 ms
4.08 ms
8.16 ms
16.32 ms
32.6 ms
65.2 ms
130 ms
261 ms
522 ms
1.04 s
490 Hz
245 Hz
367 Hz
123 Hz
183 Hz
61.3 Hz
30.7 Hz
15.4 Hz
7.66 Hz
3.83 Hz
1.92 Hz
0.958 Hz
0.479 Hz
0.240 Hz
91.9 Hz
45.9 Hz
22.9 Hz
11.4 Hz
5.74 Hz
2.87 Hz
1.43 Hz
0.718 Hz
174 ms
349 ms
697 ms
1.40 s
2.08 s
4.17 s
Table 41. Modes of Accessing MTIM Timer-Related Registers
State of MCRA / MCRB / MPAR Register Bits
Access to MTIM Timer Related Registers
Read Only
Access
RST bit TES[1:0] SWA bit CKE bit
Mode
Read / Write Access
MTIM, MTIML, MZPRV, MZREG,
MCOMP, MDREG, ST[3:0]
0
xx
x
0
1
Configuration Mode
MCOMP, MDREG, MZREG, MZPRV
RMI bit of MISR:
0: No action
1: Decrement ST[3:0]
0
00
0
Switched Mode
MTIM, ST[3:0]
RPI bit of MISR:
0: No action
1: Increment ST[3:0]
MDREG, MCOMP, MZREG, MZPRV,
RMI, RPI bit of MISR:
Set by hardware, (increment ST[3:0])
Cleared by software
0
0
00
1
x
1
1
Autoswitched Mode MTIM, ST[3:0]
MDREG,MZREG, MZPRV,
01
10
11
MTIM, MTIML,
Speed Sensor Mode
ST[3:0]
RMI, RPI bit of MISR, :
Set by hardware, (increment or decre-
ment ST[3:0]), cleared by software.
179/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.7.5 Speed Measurement Mode
counting the number of clock cycles issued by the
Incremental Encoder Interface (Encoder Clock)
during a fixed time window (refer to Figure 100).
Motor speed can be measured using two methods
depending on sensor type: period measurement or
pulse counting. Typical sensor handling is de-
scribed here.
The tachogenerator has a much lower ppr rate
than the encoder (typically factor 10). In this con-
text, it is more meaningful to measure the period
between Tacho Captures (i.e. relevant transitions
of the incoming signals). Accuracy is imposed by
the reference clock, i.e. the CPU clock (refer to
Figure 99).
Incremental encoders allows accurate speed
measurement by providing a large number of puls-
es per revolution (ppr) with ppr rates up to several
thousands; the higher the ppr rate, the higher the
resolution. The proposed method consists of
Figure 99. Tachogenerator period acquisition using MTIM timer
Decreasing Speed
Comparator
Output
Tacho
Capture
Compare
Value
S
MTIM Counter
Value
Interrupts
C
C
C
C
C
C
C
To interrupt generator
(Capture Event)
To interrupt generator
(Speed Error Event)
S
C
Figure 100. Encoder Clock frequency measure using MTIM timer
Decreasing Speed
Encoder
Clock
Capture
(triggered by software
or Real-time Clock)
MTIM Counter
Value
Interrupts
C
C
C
C
C
C
C
To interrupt generator
(Capture Event)
C
180/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Hall sensors (or equivalent sensors providing posi-
tion information) are widely used for motor control.
There are two cases to be considered:
[MTIM:MTIML] is cleared. The counting direction
is not affected by the EDIR bit when using an en-
coder sensor.
– BLDC motor or six-step synchronous motor
drive; “Sensor Mode” is recommended in this
case, as most tasks are performed by hardware
in the Delay Manager
A 16-bit capture register is used to store the cap-
tured value of the extended MTIM counter: the
speed result will be either a period in clock cycles
or a number of encoder pulses. This 16-bit register
is mapped in the MZREG and MZPRV register ad-
dresses. To ensure that the read value is not cor-
rupted between the high and low byte accesses, a
read access to the MSB of this register (MZREG)
locks the LSB (ie MZPRV content is locked) until it
is read and any other capture event in between
these two accesses is discarded.
– BLAC, asynchronous or motors supplied with 3-
phase sinewave-modulated PWM signals in gen-
eral; in this case “Speed Sensor Mode” allows
high accuracy speed measurement (the Sensor
Mode of the Delay Manager being unsuitable for
sinewave generation). Position information is
handled by software to lock the statoric field to
the rotoric one for driving synchronous motors.
A compare unit allows a maximum value to be en-
tered for the tacho periods. If the 16-bit counter
[MTIM:MTIML] exceeds this value, a Speed Error
interrupt is generated. This may be used to warn
the user that the tachogenerator signal is lost
(wires disconnected, motor stalled,...). As 8-bit ac-
curacy is sufficient for this purpose, only the MS-
Byte of the counter (i.e. MTIM) is compared to 8-bit
compare register, mapped in the MDREG register
location. The LSByte is nevertheless compared
with a fixed FFh value. Available values for com-
parison are therefore FFFFh, FEFFh, FDFFh, ...,
01FFh, 00FFh.
Hall sensors are usually arranged in a 120° config-
uration. In that case they provide 3 ppr with both
rising and falling edge triggering; the tachogenera-
tor measurement method can therefore be ap-
plied. The main difference lies in the fact that one
must use the position information they provide.
This can be done using the three MCIx pins and
the analog multiplexer to know which of the 3 sen-
sors toggled; an interrupt is generated just after
the expected transition (refer to Figure 101).
As described in Figure 102, the MTIM Timer is re-
configured depending on the selected sensor. This
means that most of Delay Manager registers are
used for a different purpose, with modified func-
tionalities.
Note: This functionality is not useful when using
an encoder. With an encoder, user must monitor
the captured values by software during the period-
ic capture interrupts: for instance, when driving an
AC motor, if the values are too low compared to
the stator frequency, a software interrupt may be
triggered.
For greater precision, the MTIM Up-counter is ex-
tended to 16 bits using MTIM and an additional
MTIML register. On a capture event, the current
counter value is captured and the counter
Figure 101. Hall sensor period acquisition using MTIM timer
1 mechanical cycle
MCIA: Hall Sensor 1
MCIB: Hall Sensor 2
MCIC: Hall Sensor 3
Period measurements
1-2
2-3
3-1
1-2
2-3
3-1
Tacho Capture
Interrupts
C
C
C
C
C
C
C
C
C
C
C
C
C
181/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 102. Overview of MTIM Timer in Speed Measurement Mode
f
f
Registers: MSCR* MPHST* MPAR*
MTC
PERIPH
(4MHz)
(16MHz)
Bits:
TES[1:0]
ECM IS[1:0]
Encoder
Clock
MPAR* and MPHST*
Registers
Tacho Capture
MTIM Read access
RTC interrupt
IS[1:0] bits
C
TES[1:0] bits
RPI
MTIM Register = 100h?
+1
4
Ratio
MPRSR Register
ST[3:0] Bits
1 / 2
Tratio
-1
MZREG < 55h?
RMI
16 MHz - 500 Hz
Clock
§
§
C
MTIM
MTIML
clr
16-bit Up Counter
LSbits
MSbits
C
C
MZREG
MZPRV
16-bit Capture Register
FFh (Fixed)
MDREG
Compare
Compare
S
Notes:
§
*
= Register updated on R event
To interrupt generator
(Capture Event)
To interrupt generator
(Ratio Increment Event)
C
S
RPI
RMI
= Register set-up described in
Speed Sensor Mode Section
To interrupt generator
(Speed Error Event)
To interrupt generator
(Ratio Decrement Event)
182/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
A logic block manages capture operations de-
pending on the sensor type. A capture is initiated
on an active edge (“Tacho capture” event) when
using a tachogenerator.
vided by two). The RPI bit in the MISR register is
set and an interrupt is generated (if RIM is set).
– When a capture event occurs, if the
[MTIM:MTIML] timer value is below 5500h, the
prescaler is automatically decremented in order
to speed up the counter and keep precision bet-
ter than 0.005% (1/5500h). The MTIM and
MTIML registers are shifted left (multiplied by
two). The RMI bit in the MISR register is set and
an interrupt is generated if RIM is set.
If an encoder is used, the capture is triggered on
two events depending on the Encoder Capture
Mode bit (ECM) in the MZFR register:
– Reading the MSB of the counter in manual
mode (ECM = 1)
– Interrupt from the Real-time Clock in automat-
ic mode (ECM = 0)
The clock source of the counter is selected de-
pending on sensor type:
– If the prescaler contents reach the value 0, it can
no longer be automatically decremented, the
[MTIM:MTIML] timer continues working with the
same prescaler value, i.e. with a lower accuracy.
No RMI interrrupt can be generated.
– Motor Control Peripheral clock (16 MHz) with
tachogenerator or Hall sensors
– Encoder Clock
– If the prescaler contents reach the value 15, it
can no longer be automatically incremented.
When the timer reaches the value FFFFh, the pr-
escaler and all the relevant registers remain un-
changed and no interrupt is generated, the timer
clock is disabled, and its contents stay at FFFFh.
The capture logic block still works, enabling the
capture of the maximum timer value.
In order to optimize the accuracy of the measure-
ment for a wide speed range, the auto-updated pr-
escaler functionality is used with slight modifica-
tions compared to Sensor/Sensorless Modes (re-
fer to Figure 103 and Table 38).
– When the [MTIM:MTIML] timer value reaches
FFFFh, the prescaler is automatically increment-
ed in order to slow down the counter and avoid
an overflow. To keep consistent values, the
MTIM and MTIML registers are shifted right (di-
The only automatically updated registers for the
Speed Sensor Mode are MTIM and MTIML. Ac-
cess to Delay manager registers in Speed Sensor
Mode is summarised in Table 41.
Figure 103. Auto-updated prescaler functional diagram
[MTIM:MTIML] Timer Overflow
(MTIM = MTIML = FFh)
Capture with [MTIM:MTIML] Timer < 5500h
(MZREG < 55h)
Begin
Begin
No
No
Ratio < Fh?
Ratio > 0?
Yes
Yes
Ratio = Ratio + 1
Ratio = Ratio - 1
Counter = Counter/2
Counter = 0
End
End
Slow-down control
Speed-up control
183/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Three kinds of interrupt can be generated in
Speed Sensor Mode, as summarized in Figure
104:
Measurement Mode: In order to set-up the
[MTIM:MTIML] counter properly before any speed
measurement, the following procedure must be
applied:
– The peripheral clock must be disabled (resetting
the CKE bit in the MCRA register) to allow write
access to ST[3:0], MTIM and MTIML (refer to Ta-
ble 41),
– C interrupt, when a capture event occurs; this in-
terrupt shares resources (Mask bit and Flag) with
the Commutation event in Switched/Au-
toswitched Mode, as these modes are mutually
exclusive.
– MTIM, MTIML must be reset and appropriate val-
ues must be written in the ST[3:0] prescaler
adapt to the frequency of the signal being meas-
ured and to allow speed measurement with suffi-
cient resolution.
– RPI/RMI interrupts occur when the ST[3:0] bits of
the MPSR register are changed, either automat-
ically or by hardware.
– S interrupt occurs when a Speed Error happens
(i.e. a successful comparison between
Note on MTIML: The Least Significant Byte of the
counter (MTIML) is not used when working in Po-
sition Sensor or Sensorless Modes.
Debug option: a signal reflecting the capture
events may be output on a standard I/O port for de-
bugging purposes. Refer to section10.6.7.3 on
page 172 for more details.
[MTIM:MTIML] and [MDREG:FF]). This interrupt
has the same channel as the Emergency Stop in-
terrupt (MCES), as it also warns the user about
abnormal system operation. The respective Flag
bits have to be tested in the interrupt service rou-
tine to differentiate Speed Errors from Emergen-
cy Stop events.
These interrupts may be masked individually.
Note on Delay Manager Initialization in Speed
Figure 104. Prescaler auto-change example
CAPTURE
EVENTS
[MTIM:MTIML]
FFFFh
FAFFh
USUAL
WORKING
RANGE
8000h
5500h
C
C
C
C
C
S
RPI
RMI
Notes:
[MTIM:MTIML] Input Clock:
Fx (ST[3:0] = n)
Fx / 2 (ST[3:0] = n+1)
Events:
Capture
Speed Error
C
S
RPI Ratio Increment
RMI Ratio Decrement
184/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.7.6 Summary
The use of the Delay manager registers for the
various available modes is summarized in Table
42.
Table 42. MTIM Timer-related Registers
Name
Reset Value
Switched / Auto Switched Mode
Speed Measurement Mode
16-bit Timer MSB Value
16-bit Timer LSB Value
Capture of 16-bit Timer MSB
Capture of 16-bit Timer LSB
N/A
MTIM
00h
Timer Value
MTIML
MZREG
MZPRV
MCOMP
00h
N/A
00h
Capture/compare Zn
Capture Zn-1
00h
00h
Compare Cn+1
Compare for Speed Error
interrupt generation
MDREG
00h
Demagnetization Dn
age reference depending on the maximum current
acceptable for the motor. This current limitation is
10.6.8 PWM Manager
generated with the V
voltage by means of an
DD
The PWM manager controls the motor via the six
output channels in voltage mode or current mode
depending on the V0C1 bit in the MCRA register.
A block diagram of this part is given in Figure 106.
external resistor divider but can also be adjusted
with an external reference voltage (≤5 V). The ex-
ternal components are adjusted by the user de-
pending on the application needs. In Voltage
mode, it is mandatory to set a current limitation. As
this limitation is set for safety purposes, an inter-
rupt can be generated when the motor current
feedback reaches the current limitation in voltage
mode. This is the current limitation interrupt and it
is enabled by setting the corresponding CLM bit in
the MIMR register. This is useful in voltage mode
for security purposes.
10.6.8.1 Voltage Mode
In Voltage mode (V0C1 bit = ”0”), the PWM signal
which is applied to the switches is generated by
the 12-bit PWM Generator compare U.
Its duty cycle is programmed by software (refer to
the PWM Generator section) as required by the
application (speed regulation for example).
The current comparator is used for safety purpos-
es as a current limitation. For this feature, the de-
tected current must be present on the MCCFI pin
and the current limitation must be present on pin
MCCREF. This current limitation is fixed by a volt-
The PWM signal is directed to the channel manag-
er that connects it to the programmed outputs (see
Figure 106).
185/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.8.2 Over Current Handling in Voltage
mode
the PWMU, PWMV or PWMW bits in the MPWME
register. The PWM signal is filtered through an ex-
ternal RC filter on pin MCCREF.
When the current limitation interrupt is enabled by
setting the CLIM bit in the MIMR register (available
only in Voltage mode), the OCV bit in MCRB reg-
ister will determine the effect of this interrupt on
the MCOx outputs as shown in Table 43.
The detected current input must be present on the
MCCFI pin.
10.6.8.4 Current Feedback Comparator
Two programmable filters are implemented:
Table 43. OCV bit effect
– A blanking window ( Current Window Filter) after
PWM has been switched ON to avoid spurious
PWM OFF states caused by parasitic noise
CLIM bit CLI bit OCV bit Output effect Interrupt
Normal running
0
0
1
1
0
1
0
1
x
x
x
0
No
– An event counter (Current Feedback Filter) to
prevent PWM being turned OFF when the first
comparator edge is detected.
mode
PWM is put OFF
on Current loop
effect
No
Figure 105. Current Window and Feedback
Filters
Normal running
mode
No
PWM is put OFF
on Current loop
effect
PWM on
Yes
All MCOx outputs
are put in reset
state (MOE re-
CURRENT
WINDOW
FILTER
1
1
1
Yes
End of
No
1)
Blanking Window
?
set)
For safety purposes, it can be necessary to put all
MCOx outputs in reset state (high impedance,
high state or low state depending on the setting
made by the option byte) on a current limitation in-
terrupt. This is the purpose of the OCV bit. When a
current limitation interrupt occurs, if the OCV bit is
reset, the effect on the MCOx outputs is only to put
the PWM signal OFF on the concerned outputs. If
the OCV bit is set, when the current limitation inter-
rupt occurs, all the MCOx outputs are put in reset
state.
Yes
CURRENT
FEEDBACK
FILTER
Yes
Current >
Limit
?
No
No
Reset counter
Limit=1?
Note 1: Only this functionality (CLIM = CLI = OCV
= 1) is valid when the 3 PWM channels are ena-
bled (PCN bit =1 in the MDTG register). It can also
be used as an over-current protection for three-
phase PWM application (only if voltage mode is
selected)
Increment counter
10.6.8.3 Current Mode
Yes
No
Counter=
Limit?
In current mode, the PWM output signal is gener-
ated by a combination of the output of the meas-
urement window generator (see Figure 107) and
the output of the current comparator, and is direct-
ed to the output channel manager as well (Figure
108).
Yes
Set the CL bit
The current reference is provided to the compara-
tor by Phase U, V or W of the PWM Generator (up
to 12-bit accuracy) the signal from the three com-
pare registers U, V or W can be output by setting
186/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Table 44. Current Window filter Setting
Table 45. Current Feedback Filter Setting
CFW2 CFW1 CFW0
Blanking window length
Nb of Feedback Samples
CFF2 CFF1 CFF0
needed to turn OFF PWM
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Blanking window off
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
0.5 µs
1 µs
1.5 µs
2 µs
2.5 µs
3 µs
3.5 µs
Note: Times are indicated for 4 MHz f
PERIPH
The Current Window filter is activated each time
the PWM is turned ON. It blanks the output of the
current comparator during the time set by the
CFW[2:0] bits in the MCFR register. The reset val-
ue is 000b (blanking window off).
The ON time of the resulting PWM starts at the
end of the measurement window (rising edge),
and ends either at the beginning of the next meas-
urement window (falling edge), or when the cur-
rent level is reached.
The Current feedback filter sets the number of
consecutive valid samples (when current is above
the limit) needed to generate the active CL event
used to turn OFF the PWM. The reset value is 1.
Note: Be careful that the current comparator is
OFF until the CKE and/or DAC bits are set in the
MCRA register.
The sampling of the current comparator is done at
f
/4.
PERIPH
187/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.8.5 Current feedback amplifier
means that the current feedback has to be on the
MCCFI0 pin to be directly connected to the com-
parator and the OAP, OAN and OAZ (MCCFI1)
pins can be used to amplify another signal. Both
the OAZ(MCCFI1) and MCCFI0 pins can be con-
nected to an ADC entry. See (Figure 106).
In both current and voltage mode, the current
feedback from the motor can be amplified before
entering the comparator. This is done by an inte-
grated Op-amp that can be used when the OAON
bit is set in the OACSR register and the CFAV bit
in the MREF register is reset. This allows the three
points of the Op-amp to be accessed for a pro-
grammable gain. The CFAV bit in the MREF regis-
ter selects the MCCFI0 or OAZ(MCCFI1) pin as
the comparator input as shown in the following ta-
ble.
Note: The MCCFI0 pin is not available in LQFP32;
SDIP32 and LQFP44 devices. In this case, the
CFAV bit must be reset. The choice to use the Op-
amp or not is made with the OAON bit.
10.6.8.6 Measurement Window
In current mode, the measurement window fre-
quency can be programmed between 390Hz and
50KHz by the means of the SA[3:0] bits in the
MPRSR register.
Table 46. Comparator input selection
CFAV bit
Meaning
Select OAZ(MCCFI1) as the current
comparator input
Note: These frequencies are given for a 4 MHz
peripheral input frequency for a BLDC drive
(XT16, XT8 bits in MCONF register).
0
Select MCCFI0 as the current compara-
tor input
1
In sensorless mode this measurement window can
be used to detect BEMF zero crossing events. Its
width can be defined between 2.5μs and 40μs as a
minimum in sensorless mode by the OT[3:0] bits in
the MPWME register.
If the amplifier is not used for current feedback, it
can be used for other purposes. In this case, the
OAON bit in the OACSR register and the CFAV bit
in the MREF register both have to be set. This
Figure 106. Current Feedback
MREF Register
PWME[U:V:W] bit
MCPWMU/V/W
12-Bit PWM generator
LEGEND:
(I): Current mode
(V): Voltage mode
CLI: Current limitation inter-
rupt
MREF
Register
OACSR
Register
CFAV bit
OAON bit
OAP
OAN
+
-
MCFR register
V
DD
CFF[2:0] bits
R
OAZ
1ext
(I)
(MCCFI1)
+
-
CLI
MCCFI0
(V)
R
Filter
V
CREF
ADC
2ext
MCCREF
To Phase State
Control
C
R
D
EXT
CFW[2:0] bits
MCFR register
V
MAX = V
Q
Q
CREF
DD
Power down mode
CP
S
Internal clock
Sampling frequency
I
12-bit PWM generator/Compare U
V
MCRA Register
V0C1 bit
188/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
This sets the minimum off time of the PWM signal
generated by this internal clock. This off time can
vary depending on the output of the current feed-
back comparator. In sensor mode (SR=1) and
when the sampling for the Z event is done during
the PWM ON time in sensorless mode (SPLG bit is
set in MCRC register and /or DS[3:0] bits with a
value other than 000 in MCONF register), there is
no minimum OFF time required anymore, the min-
imum off time is set automatically to 0µs and the
OFF time of the PWM signal is controlled only by
the current regulation loop.
Warning: If the off time value set is superior than
the period of the PWM signal (for example 40µs off
time for a 50KHz (25µs period) PWM frequency),
then the signal output on MCOx pins selected is a
100% duty cycle signal (always at 1).
Table 48. Off time table
Sensor Mode
(SR=1) or sam-
Off Time sen-
pling duringON
sorless mode
OT3 OT2 OT1 OT0
time in sensor-
less (SPLG =1
and/or DS[3:0]
bits)
(SR=0)
Table 47. Sampling Frequency Selection
(DS[3:0]=0)
SA3 SA2 SA1 SA0
Sampling Frequency
50.0 KHz
40.0 KHz
33.33 KHz
25.0 KHz
20.0 KHz
18.1 KHz
15.4 KHz
12.5 KHz
10 KHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.5 µs
5 µs
7.5 µs
10 µs
12.5 µs
15 µs
17.5 µs
20 µs
No minimum off
time
22.5 µs
25 µs
6.25 KHz
3.13 KHz
1.56 KHz
1.25 KHz
961 Hz
27.5 µs
30 µs
32.5 μs
35 μs
37.5 μs
40 μs
625 Hz
390 Hz
Note: Times are indicated for 4 MHz f
Note: Times are indicated for 4 MHz f
PERIPH
PERIPH
Figure 107. Sampling clock generation block
MPRSR Register
SA[3:0] bits
Frequency
OFF time
0
4
f
T
sampling
PERIPH
Frequency logic
Sampling
Clock
Off-Time logic
(measurement window)
T
off
2
The BEMF is sampled at the end of OFF time
in sensorless mode
OT[3:0] bits
.
MPWME Register
Note: The MTC controller input frequency (f
) is 4 MHz in this example,
PERIPH
It can be configured to 8MHz with the XT16: XT8 bits in the MCONF register
189/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.9 Channel Manager
– A multiplexer to direct the PWM to the low and/
or high channel group
The channel manager consists of:
– A tristate buffer asynchronously driven by an
emergency input
– A Phase State register with preload and polarity
function
The block diagram is shown in Figure 108.
Figure 108. Channel Manager Block Diagram
MCRA Register
V0C1 bit
Notes:
Reg
Updated/Shifted on
R
PWM generator
Updated with Reg
on C
n+1
Reg
n
PWM Generator
V
I
V
I
I
Current Mode
Voltage Mode
V
S Q
Sampling frequency
events:
Commutation
C
Z
OFF time
BEMF
Zero-crossing
D
S,H
Current comparator
output
End Of
Demagnetization
E
+/-
Emergency Stop
Ratio Updated (+1 or -1)
Filter
Sensorless Sensor
R
MCFR Register
CFF[2:0] bits
O
1
Multiplier
Overflow
R
Branch taken after C event
Branch taken after D event
2
Sampling
Clock
MCRA Register
DAC bit
“1”
MCRA Register
SR bit
C
MPHST Register
OO bits*
Phase Register*
6
MCRB Register
OS[2:0] bits*
n
3
MPAR Register
OE[5:0] bits
6
Channel [5:0]
8
Dead
Time
Dead
Time
Dead
Time
MDTG Register
2
Channel [5:0]
6
MREF Register
High frequency chopper
HFE[1:0] bits
HFRQ[2:0] bits
5
MPOL Register
OP[5:0] bits
x6
OCV bit
6
1
1
MCRA Register
MOE bit
CLIM bit
x6
1
CLI bit
1
* = Preload register, changes taken into account at next C event.
190/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.9.1 MPHST Phase State Register
grammed using the OE[5:0] bits in the MPAR reg-
ister.
A preload register enables software to asynchro-
nously update the channel configuration for the
next step (during the previous commutation inter-
rupt routine for example): the OO[5:0] bits in the
MPHST register are copied to the Phase register
on a C event.
Table 51. Meaning of the OE[5:0] Bits
OE[5:0]
Channel group
High channel
Low channel
0
1
Table 49. Output State
The multiplexer directs the PWM to the upper
channel, the lower channel or both of them alter-
natively or simultaneously according to the periph-
eral state.
OP[5:0] bit
OO[5:0] bit
MCO[5:0] Pin
1 (OFF)
0
0
1
1
0
1
0
1
0-(PWM allowed)
0 (OFF)
This means that the PWM can affect any of the up-
per or lower channels allowing the selection of the
most appropriate reference potential when free-
wheeling the motor in order to:
1-(PWM allowed)
Direct access to the phase register is also possible
when the DAC bit in the MCRA register is set.
– Improve system efficiency
– Speed up the demagnetization phase
– Enable Back EMF zero crossing detection.
Note: In Direct Access Mode (DAC bit is set in
MCRA register):
The OS[2:0] bits in the MCRB register allow the
PWM configuration to be configured for each case
as shown in Figure 110 and Figure 109.
1: A C event is generated as soon as there is a
write access to OO[5:0] bits in MPHST register,
2: The PWM application is selected by the OS0 bit
in the MCRB register,
3: Regardless of the value of the CKE bit in the
MCRA register, the MTIM Clock is disabled and D
and Z events are not detected.
During demagnetization, the OS2 bit is used to
control PWM mode, and it is latched in a preload
register so it can be modified when a commutation
event occurs and the configuration is active imme-
diately.
Table 50. DAC and MOE Bit Meaning
The OS1 bit is used to control the PWM between
the D and Z events to control back-emf detection.
MOE
bit
DAC
bit
Effect on Output
OS0 bit will allow to control the PWM signal be-
tween Z event and next C event.
0
x
Reset state*
Standard
Note about demagnetization speed-up: during
demagnetization the voltage on the winding has to
be as high as possible in order to reduce the de-
magnetization time. Software can apply a different
PWM configuration on the outputs between the C
and D events, to force the free wheeling on the ap-
propriate diodes to maximize the demagnetization
voltage.
1
0
running mode
MPHST register value (depending on
MPOL, MPAR register values and
PWM setting) see Table 74
1
1
*Note: The reset state of the outputs can be either
high impedance, low or high state depending on
the corresponding option bit.
10.6.9.2 Emergency Feature
The polarity register is used to match the polarity
of the power drivers keeping the same control log-
ic and software. If one of the OPx bits in the MPOL
register is set, this means the switch x is ON when
When the NMCES pin goes low
– The tristate output buffer is put in reset state
asynchronously
MCOx is V
.
– The MOE bit in the MCRA register is reset
DD
Each output status depends also on the momen-
tary state of the PWM, its group (low or high), and
the peripheral state.
– An interrupt request is sent to the CPU if the EIM
bit in the MIMR register is set
This bit can be connected to an alarm signal from
the drivers, thermal sensor or any other security
component.
PWM Features
The outputs can be split in two PWM groups in or-
der to differentiate the high side and the low side
switches. This output property can be pro-
This feature functions even if the MCU oscillator is
off.
191/309
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 109. PWM application in Voltage or Current sensorless mode (see Table 61)
OS0 PWM behaviour after Z
OS2 PWM behaviour after C
and before D
OS1 PWM behaviour after D
and before Z
and before next C
0
1
High Channels
Low Channels
0
1
High Channels
Low Channels
0
1
High Channels
Low Channels
Step
OS2
OS1
OS0
Demagnetization
Delay
WaitZevent
1
0
0
High
1 Low
000
001
0
1
High
Low
0 High
010
011
1
Low
High
Low
High
0
1
0
1
100
101
Low
High
0
1
Low
High
0
1
110
111
Low
High
Low
0
1
192/309
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 110. PWM application in Voltage or Current Sensor Mode (see Table 62)
(sensor mode: SR=1)
OS1 Not Used
OS0 PWM behaviour after Z
OS2 PWM behaviour after C
and before next C
and before Z
-
0
1
High Channels
Low Channels
0
1
High Channels
Low Channels
Step
OS2
Wait Z event
OS0
Delay
1
xx
0
0
1
High
Low
0x0
0x1
0
High
Low
High
Low
1
0
1x0
1x1
1
0
1
High
Low
In sensor mode, there is no demagnetisation event and the PWM behaviour can be
changed before and after Z event
193/309
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.9.3 Dead Time Generator
For each of the three PWM channels, there is one
6-bit Dead Time generator available.
When using typical triple half bridge topology for
power converters, precautions must be taken to
avoid short circuits in half bridges. This is ensured
by driving high and low side switches with comple-
mentary signals and by managing the time be-
tween the switching-off and the switching-on in-
stants of the adjacent switches.
It generates two output signals: A and B.
The A output signal is the same as the input phase
signal except for the rising edge, which is delayed
relative to the input signal rising edge.
The B output signal is the opposite of the input
phase signal except the rising edge which is de-
layed relative to the input signal falling edge.
This time is usually known as deadtime and has to
be adjusted depending on the devices connected
to the PWM outputs and their characteristics (in-
trinsic delays of level-shifters, delays due to power
switches,...).
Figure 111 shows the relationship between the
output signals of the deadtime register and its in-
puts.
If the delay is greater than the width of the active
phase (A or B) then the corresponding pulse is not
generated (see Figure 112 and Figure 113).
When driving motors in six-step mode, the dead-
time generator function also allows synchronous
rectification to be performed on the switch adja-
cent to the one where PWM is applied to reduce
conduction losses.
Figure 111. Dead Time waveforms
Reference
5V
0V
5V
Input signal
Output A
0V
Delay
5V
0V
Output B
Delay
Figure 112. Dead time waveform with delay greater than the negative PWM pulse
5V
Input
0V
5V
Output A
Delay
0V
5V
0V
Output B
194/309
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 113. Dead Time waveform with delay greater than the positive PWM pulse
5V
Input
0V
5V
Output A
0V
5V
Output B
0V
Delay
Table 52. Dead time programming and example
T
Dead time range
dtg
DTG5 DTG4
T
Deadtime expression Deadtime value
(DTG[4..0]+1) x T From 1 to 32 T
dtg
dtg
@16MHz F
125ns
@ 16MHz F
mtc
mtc
0
1
1
X
0
1
2xT
4xT
8xT
0.125µs to 4µs
4.25µs to 8µs
8.5µs to 16µs
mtc
mtc
mtc
dtg
250ns
(DTG[3..0]+17) x T
From 17 to 32 T
dtg
dtg
500ns
The deadtime delay is the same for each of the
channels and is programmable with the DTG[5..0]
bits in the MDTG register.
The dead time generator is enabled/disabled us-
ing the DTE bit.
The resolution is variable and depends on the
DTG5 and DTG4 bits. Table 52 summarizes the
set-up of the deadtime generator.
The effect of the DTE bit depends on the PCN bit
value.
If the PCN bit is set:
IT
is the period of the Dead Time Generator in-
mtc
■ DTE is read only. To reset it, first reset the PCN
put clock (F
= 16 MHz in most cases, not affect-
mtc
bit, then reset DTE and set PCN to 1 again.
ed by the XT16:XT8 prescaler bits in the MCONF
register).
■ If DTE=0, the high and low side outputs are
simply complemented (no deadtime insertion,
DTG[5:0] bits are not significant); this is to allow
the use of an external dead time generator.
For safety reasons and since the deadtime de-
pends only on external component characteristics
(level-shifter delay, power components switching
duration,...) the register used to set-up deadtime
duration can be written only once after the MCU
reset. This prevents a corrupted program counter
modifying this system critical set-up, which may
cause excessive power dissipation or destructive
shoot-through in the power stage half bridges.
Note: The reset value of the MDTG register is FFh
so when configuring the dead time, it is mandatory
to follow one the two following sequences:
■ To use dead t imes while the PCN bit is set; from
reset state write the MDTG value at once. The
DTE bit will be read back as 1 whatever the
programming value (read only if PCN=1)
■ To use dead times while the PCN bit is reset,
write first the dead time value in DTG[5:0], then
reset the PCN bit, or do both actions at the same
time.
When using the three independent U, V and W
PWM signals (PCN bit set) (see Figure 114) to
drive the MCOx outputs, deadtime is added as
shown in Figure 111.
195/309
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 114. Channel Manager Output Block Diagram with PWM generator delivering 3 PWM signals
PWM generator signals
W
V
U
MDTG Register
PCN bit = 1
8
Dead
Time
Dead
Time
Dead
Time
Channel [5:4] Channel [3:2] Channel [1:0]
High frequency chopper
MREF Register
2
HFE[1:0] bits
HFRQ[2:0] bits
5
MPOL Register
OP[5:0] bits
x6
x6
OCV bit
6
1
MRCA Register
MOE bit
CLIM bit
1
1
CLI bit
1
Note: The output of the current limitation comparator can be used when 3 PWM signals are enabled if the
VOC1 bit =0 in the MCRA register.
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
If the PCN bit is reset, one of the three PWM sig-
nals (the one set by the compare U register pair) or
the output of the measurement window generator
(depending on if the driving mode is voltage or cur-
rent) is used to provide six-step signals through
the PWM manager (to drive a PM BLDC motor for
instance).
Table 53. Dead Time generator outputs
PCN = 0; DTE =1; x= 0, 2, 4
On/Off x
On/Off x+1
MCOx+1
output
MCOx output
(OOx bit) (OOx+1 bit)
0
1 (pwm*)
PWM
PWM
1 (pwm*)
0
PWM
PWM
In that case, DTE behaves like a standard bit (with
multiple write capability). When the deadtime gen-
erator is enabled (bit DTE=1), some restrictions
are applied, summarized in Table 53:
■ Channels are now grouped by pairs:
Channel[0:1], Channel[2:3], Channel[4:5]; a
deadtime generator is allocated to each of these
pairs (see cautions below);
■ The input signal of the deadtime generator is the
active output of the PWM manager for the
corresponding channel. For instance, if we
consider the Channel[0:1] pair, it may be either
Channel0 or Channel1.
■ When both channels of a pair are inactive, the
corresponding outputs will also stay inactive
(this is mandatory to allow BEMF zero-crossing
detection).
1
1 (pwm*)
0
0
1
0
0
0
0
0
1
0
1 (pwm*)
1
0
1
0
1
0
0
* PWM generation enabled
Warning: Grouping channels by pairs imposes the
external connections between the MCO outputs
and power devices; the user must therefore pay at-
tention to respect the “recommended schematics”
described in Figure 123. on page 228 and Figure
124
Note: As soon as the channels are grouped in
pairs, special care has to be taken in configuring
the MPAR register for a PM BLDC drive. If both
channels of the same pair are both labelled “high”
for example and if the PWM is applied on high
channels, the active MCO output x (OOx=1 bit in
the MPHST register) outputs PWM and the paired
MCO output x+1 (OOx+1bit in the MPHST regis-
ter) outputs PWM and vice versa.
Table 53 summarizes the functionality of the dead-
time generator when the PCN bit is reset. 1(pwm*)
means that the corresponding channel is active (1
in the corresponding bit in the MPHST register),
and a PWM signal is applied on it (using the MPAR
register and the OS[2:0] bits in MCRB register).
PWM represents the complementary signals (al-
though the duty cycle is slightly different due to
deadtime insertion). 0 means that the channel is
inactive and 1 means that the channel is active
and a logic level 1 is applied on it (no PWM signal).
Caution: When PCN=0 and a complementary
PWM is applied (DTE=1) on one channel of a pair,
if both channels are active, this corresponds in
output to both channels OFF. This is for security
purpose to avoid cross-conduction.
Caution: To clear the DTE bit from reset state of
MDTG register (FFh), the PCN bit must be cleared
before.
197/309
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 115. Channel Manager Output Block Diagram with PWM generator delivering 1 PWM signal
PWM generator
U channel
V
V
S
Q
I
I
Sampling frequency
R
OFF time
Sensorless Sensor
Current comparator
output
Sampling
Clock
“1”
Phase Register*
n
MPAR Register
OE[5:0] bits
6
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
MDTG Register
PCN bit = 0
8
Dead
Time
Dead
Time
Dead
Time
Channel [5:4] Channel [3:2] Channel [1:0]
High frequency chopper
6
MREF Register
2
HFE[1:0] bits
HFRQ[2:0] bits
5
MPOL Register
x6
x6
OP[5:0] bits
MCRA Register
MOE bit
OCV bit
6
1
1
CLIM bit
1
CLI bit
1
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.9.4 Programmable Chopper
Table 55. Chopping frequency
Depending on the application hardware (use of a
pulse transformer, for example), a chopper may be
needed for the PWM signal. The MREF register al-
lows the chopping frequency and mode to be pro-
grammed.
Chopping
frequency
Chopping
frequency
HFRQ2 HFRQ1 HFRQ0
F
= 16MHz
= 8MHz
mtc
F
= 4MHz
mtc
F
mtc
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100 KHz
200 KHz
400 KHz
500 KHz
800 KHz
1 MHz
50 KHz
The HFE[1:0] bits program the channels on which
chopping is to be applied. The chopped PWM sig-
nal may be needed for high side switches only, low
side switches or both of them in the same time
(see Table 54).
100 KHz
200 KHz
250 KHz
400 KHz
500 KHz
666.66 MHz
1 MHz
Table 54. Chopping mode
1.33 MHz
2 MHz
HFE[1:0] bits
HFE1 HFE0
Chopping mode
PCN bit =0
PCN bit =1
OFF
0
0
OFF
Note: When the PCN bit = 0:
Low side switches
MCO1, 3, 5
– If complementary PWM signals are not applied
(DTE bit = 0), the high and low drivers are fixed
by the MPAR register. Figure 108, Figure 114
and Figure 115 indicate where the HFE[1:0] bits
are taken into account depending on the PWM
application.
0
1
Low channels only
High side switches
MCO0, 2, 4
1
1
0
1
High channels only
Both Low and High Both high and low
channels sides
– If complementary PWM signals are applied (DTE
bit = 1), the channels are paired as explained in
“Dead Time Generator” on page 194. This
means that the high and low channels are fixed
and the HFE[1:0] bits indicate where to apply the
chopper. Figure 116 shows typical complemen-
tary PWM signals with high frequency chopping
enabled on both high and low drivers.
The chopping frequency can any of the 8 values
from 100KHz to 2MHz selected by the HFRQ[2:0]
bits in the MREF register (see Table 55).
Figure 116. Complementary PWM signals with chopping frequency on high and low side drivers
Reference
5V
Input signal
0V
Output A
5V
0V
Delay
5V
0V
Output B
Delay
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1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.10 PWM Generator Block
frequency carrier may be added. This is the case
of AC induction motors or PMAC motors for in-
stance, supplied with 120° shifted sinewaves in
voltage mode.
The PWM generator block produces three inde-
pendent PWM signals based on a single carrier
frequency with individually adjustable duty cycles.
10.6.10.1 Main Features
Depending on the motor driving method, one or
three of these signals may be redirected to the oth-
er functional blocks of the motor control peripheral,
using the PCN bit in the MDTG register.
■ 12-bit PWM free-running Up/Down Counter with
up to 16MHz input clock (F ).
mtc
■ Edge-aligned
and
center-aligned
PWM
operating modes
When driving PM BLDC motors in six-step mode
(voltage mode only, either sensored or sensor-
less) a single PWM signal (Phase U) is used to
supply the Input Stage, PWM and Channel Man-
ager blocks according to the selected modes.
■ Possibility to re-load compare registers twice
per PWM period in center-aligned mode
■ Full-scale PWM generation
■ PWM update interrupt generation
■ 8-bit repetition counter
■ 8-bit PWM mode
■ Timer re-synchronisation feature
For other kind of motors requiring independent
PWM control for each of the three phases, all
PWM signals (Phases U, V and W) are directed to
the channel manager, in which deadtime or a high
Figure 117. PWM generator block diagram
MREP Register
U
12-bit Compare 0 Register
Repetition
counter
U
Clear or Up/Down
MPCR Register
MPCR Register
CMS bit
F
Prescaler
PCP[2:0] bits
mtc
Up to 16MHz
12-bit PWM Counter
U
U
U
13-bit Compare U Register
13-bit Compare V Register
13-bit Compare W Register
Notes:
Preload registers transferred
to active registers on U event
Reg
event:
U
Update of compare registers
PWM interrupt generation
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.10.2 Functional Description
10.6.10.4 PWM Operating mode
The 3 PWM signals are generated using a free-
running 12-bit PWM Counter and three 13-bit
Compare registers for phase U, V and W: MCM-
PU, MCMPV and MCMPW registers.
The PWM generator can work in center-aligned or
edge-aligned mode depending on the CMS bit set-
ting in the MPCR register.
Figure 118 shows the corresponding counting se-
quence .
A fourth 12-bit register is needed to set-up the
PWM carrier frequency: MCMP0 register.
It offers also an 8-bit mode to get a full 8-bit range
with a single compare register write access by set-
ting the PMS bit in MPCR register.
Each of these compare registers is buffered with a
preload register. Transfer from preload to active
registers is done synchronously with PWM counter
underflow or overflow depending on configuration.
This allows to write compare values without risks
of spurious PWM transitions.
The comparisons described here are performed
between the PWM Counter value extended to 13
bits and the 13-bit Compare register. Having a
compare range greater than the counter range is
mandatory to get a full PWM range (i.e. up to
100% modulation). This principle is maintained for
8-bit PWM operations.
The block diagram of the PWM generator is shown
on Figure 117.
■ Center-aligned Mode (CMS bit = 1)
10.6.10.3 Prescaler
In this operating mode, the PWM Counter counts
up to the value loaded in the 12-bit Compare 0 reg-
ister then counts down until it reaches zero and re-
starts counting up.
The 12-bit PWM Counter clock is supplied through
a 3-bit prescaler to allow the generation of lower
PWM carrier frequencies. It divides F by 1, 2, 3,
mtc
..., 8 to get F
.
mtc-pwm
The PWM signals are set to ‘0’ when the PWM
Counter reaches, in up-counting, the correspond-
ing 13-bit Compare register value and they are set
to ‘1’ when the PWM Counter reaches the 13-bit
Compare value again in down-counting.
This prescaler is accessed through three bits
PCP[2:0] in MPCR register; this register is buff-
ered: the new value is taken into account after a
PWM update event.
Figure 118. Counting sequence in center-aligned and edge-aligned mode
center-aligned
0
0
1
1
2
2
....
15
15
16
16
15
....
2
1
0
0
1
1
mode
T
edge-aligned
mode
.....
0
1
.....
16
T
T = PWM period, Value of 12-bit Compare 0 Register= 16
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
If the 13-bit Compare register value is greater than
If the 13-bit Compare register value is 0, the corre-
sponding PWM output signal is held at ‘0’.
th
the extended Compare 0 Register (the 13 bit is
set to ‘0’), the corresponding PWM output signal is
held at ‘1’.
Figure 119 shows some center-aligned PWM
waveforms in an example where the Compare 0
register value = 8.
Figure 119. Center-aligned PWM Waveforms (Compare 0 Register = 8)
0
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
0
1
1
2
3
4
‘1’
‘0’
1 Compare Register value = 4
2 Compare Register value = 7
3 Compare Register value > = 8
4 Compare Register value = 0
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
■ Edge-aligned Mode (CMS bit = 0)
If the 13-bit Compare register value is greater than
th
the extended Compare 0 register (the 13 bit is
In this operating mode, the PWM Counter counts
up to the value loaded in the 12-bit Compare Reg-
ister. Then the PWM Counter is cleared and it re-
starts counting up.
set to ‘0’), the corresponding PWM output signal is
held at ‘1’.
If the 13-bit Compare register value = 0, the corre-
sponding PWM output signal is held at ‘0’.
The PWM signals are set to ‘0’ when the PWM
Counter reaches, in up-counting, the correspond-
ing 13-bit Compare register value and they are set
to ‘1’ when the PWM Counter is cleared.
Figure 120 shows some edge-aligned PWM wave-
forms in an example where the Compare 0 register
value = 8.
Figure 120. Edge-aligned PWM Waveforms (Compare 0 Register = 8)
0
1
2
3
4
5
6
7
8
0
1
1
2
3
4
‘1’
‘0’
1 Compare Register value = 4
2 Compare Register value = 8
3 Compare Register value > 8
4 Compare Register value = 0
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
■ 12-bit Mode (PMS bit = 0 in the MPCR register)
source savings when computing three-phase duty
cycles during PWM interrupt routines. In this
mode, the Compare 0 and Compare U, V, W reg-
isters have the same size (8 bits). The extension of
the MCMPx registers is done in using the OVFx
bits in the MPCR register (refer to Figure 121).
These bits force the related duty-cycles to 100%
and are reset by hardware on occurence of a
PWM update event.
This mode is useful for MCMP0 values ranging
from 9 bits to 12 bits. Figure 121 presents the way
Compare 0 and Compare U, V, W should be load-
ed). It requires loading two bytes in the MCMPxH
and MCMPxL registers (i.e. MCMP0, MCMPU,
MCMPV and MCMPW 16-bit registers) following
the sequence described below:
– write to the MCMPxL register (LSB) first
– then write to the MCMPxH register (MSB).
Note about read access to registers with
preload: during read accesses, values read are
the content of the preload registers, not the active
registers.
Note about compare register active bit loca-
tions: the 13 active bits of the MCMPx registers
are left-aligned. This allows temporary calculations
to be done with 16-bit precision, round-up is done
automatically to the 13-bit format when loading the
values of the MCMPx registers.
The 16-bit value is then ready to be transferred in
the active register as soon as an update event oc-
curs. This sequence is necessary to avoid poten-
tial conflicts with update interrupts causing the
hardware transfer from preload to active registers:
if an update event occurs in the middle of the
above sequence, the update is effective only when
the MSB has been written.
Note about MCMP0x registers: the configuration
MCMP0H=MCMP0L=0 is not allowed
■ 8-bit PWM mode (PMS bit = 1 in MPCR register)
This mode is useful whenever the MCMP0 value is
less or equal to 8-bits. It allows significant CPU re-
Figure 121. Comparison between 12-bit and 8-bit PWM mode
b7
b0 b7
b0
b0
PWM frequency
set-up
MCMP0H
b7
MCMP0L
b0 b7
12-bit PWM mode
(PMS bit = 0)
Phase x duty
cycle set-up
Ext
MCMPxH
MCMPxL
b0 b7
b7
b0
b0
PWM frequency
set-up
8-bit PWM mode
(PMS bit = 1)
MCMP0H
b7
MCMP0L
b0 b7
Phase x duty
cycle set-up
OvfX
MCMPxH
b7
MCMPxL
b0
OvfU OvfV OvfW
Equivalent bit location
Bit extending comparison range
Bit not available
MPCR
Ext
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.10.5 Repetition Down-Counter
aligned mode, i.e. one T
period. When refresh-
mtc
ing compare registers only once per PWM period
in center-aligned mode, maximum resolution is
Both in center-aligned and edge-aligned modes,
the four Compare registers (one Compare 0 and
three for the U, V and W phases) are updated
when the PWM counter underflow or overflow and
the 8-bit Repetition down-counter has reached ze-
ro.
2xT
, due to the symmetry of the pattern.
mtc
The repetition down counter is an auto-reload
type; the repetition rate will be maintained as de-
fined by the MREP register value (refer to Figure
122).
This means that data are transferred from the
preload compare registers to the compare regis-
ters every N cycles of the PWM Counter, where N
is the value of the 8-bit Repetition register in edge
-aligned mode. When using center-aligned mode,
the repetition down-counter is decremented every
time the PWM counter overflows or underflows. Al-
though this limits the maximum number of repeti-
tion to 128 PWM cycles, this makes it possible to
update the duty cycle twice per PWM period. As a
result, the effective PWM resolution in that case is
equal to the resolution we can get using edge-
10.6.10.6 PWM interrupt generation
A PWM interrupt is generated synchronously with
the “U” update event, which allows to refresh com-
pare values by software before the next update
event. As a result, the refresh rate for phases duty
cycles is directly linked to MREP register setting.
A signal reflecting the update events may be out-
put on a standard I/O port for debugging purposes.
Refer to section10.6.7.3 on page 172 for more de-
tails.
Figure 122. Update rate examples depending on mode and MREP register settings
Center-aligned mode
Edge-aligned mode
12-bit PWM
Counter
U
MREP = 0
MREP = 1
U
U
MREP = 2
MREP = 3
U
MREP = 3
and
re-synchronization
U
(by SW)
(by SW)
U
U Event: Preload registers transferred to active registers and PWM interrupt generated
U Event if transition from MREP = 0 to MREP = 1 occurs when 12-bit counter is equal
to MCP0.
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.10.7 Timer Re-synchronisation
MCMPxH must have been written, following the
mandatory LSB/MSB sequence, before setting
CKE bit). It consequently generates a U
interrupt.
The 12-bit timer can be re-synchronized by a sim-
ple write access with FFh value in the MISR regis-
ter. Re-synchronization means that the 12-bit
counter is reset and all the compare preload regis-
ters MCP0, MCPU, MCPV, MCPW are transferred
to the active registers.
10.6.11 Low Power Modes
Before executing a HALT or WFI instruction, soft-
ware must stop the motor, and may choose to put
the outputs in high impedance.
To re-synchronize the 12-bit timer properly , the
following procedure must be applied:
Mode
Description
– 1. Load the new values in the preload compare
registers
No effect on MTC interface.
MTC interrupts exit from Wait mode.
MTC registers are frozen.
Wait
– 2. Load FFh value in the MISR register (this will
reset the counter and transfer the compare
preload registers in the active registers: U event)
In Halt mode, the MTC interface is in-
active. The MTC interface becomes
operational again when the MCU is
woken up by an interrupt with “exit
from Halt mode” capability.
– 3. Reset the PUI flag by loading 7Fh in the MISR
register. Refer to Note 2 on page 209
Halt
Note: Loading FFh value in the MISR register will
have no effect on any other flag than the PUI flag
and will generate a PWM update interrupt if the
PUM bit is set.
10.6.12 Interrupts
Interrupt Event
Enable Exit Exit
Control from from
Warning: In switched mode (SWA bit is reset), the
procedure is the same and loading FFh in the
MISR register will have no effect on flags except
on the PUI flag. As a consequence, it is recom-
mended to avoid setting RMI and RPI flags at the
same time in switched mode because none of
them will be taken into account.
Event
Flag
Bit
Wait Halt
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
Ratio increment
Ratio decrement
Speed Error
RPI
RMI
SEI
EI
RIM
SEM
EIM
Emergency Stop
Current Limitation
BEMF Zero-Crossing
CLI
ZI
CLIM
ZIM
10.6.10.8 PWM generator initialization and
start-up
End of Demagnetization DI
DIM
Commutation or
CI
The three-phase generator counter stays in reset
state (i.e. stopped and equal to 0), as long as MTC
peripheral clock is disabled (CKE = 0).
CIM
Yes No
Capture
PWM Update
Sampling Out
PUI
SOI
PUM
SOM
Yes No
Yes Not
Setting the CKE bit has two actions on the PWM
generator:
The MTC interrupt events are connected to the
three interrupt vectors (see Interrupts chapter).
■ It starts the PWM counter
■ It forces the update of all registers with preload
registers transferred on U update event, i.e.
MREP, MPCR, MCMP0, MCMPU, MCMPV,
MCMPW (in 12-bit mode, both MCMPxL and
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.13 Register Description
CAPTURE Z REGISTER (MZREG)
n
Read/Write
Reset Value: 0000 0000 (00h)
TIMER COUNTER REGISTER (MTIM)
Read /Write
Reset Value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ZC7
ZC6
ZC5
ZC4
ZC3
ZC2
ZC1
ZC0
T7
T6
T5
T4
T3
T2
T1
T0
Bits 7:0 = ZC[7:0]: Current Z Value or Speed cap-
ture MSB.
Bits 7:0 = T[7:0]: MTIM Counter Value.
These bits contain the current captured BEMF val-
These bits contain the current value of the 8-bit up
counter. In Speed Measurement Mode, when us-
ing Encoder sensor and MTIM captures triggered
by SW (refer to Figure 102) a read access to MTIM
register causes a capture of the [MTIM:MTIML]
register pair to the [MZREG: MZPRV] registers.
ue (Z ) in Switched and Autoswitched mode or the
N
MSB of the captured value of the [MTIM:MTIML]
registers in Speed Sensor Mode. A read access to
MZREG in this case disable the Speed captures
up to MZPRV reading (refer to Section 10.6.7.5
Speed Measurement Mode on page 180).
TIMER COUNTER REGISTER LSB (MTIML)
Read /Write
Reset Value: 0000 0000 (00h)
COMPARE C
REGISTER (MCOMP)
n+1
Read/Write
Reset Value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
TL7
TL6
TL5
TL4
TL3
TL2
TL1
TL0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
Bits 7:0 = TL[7:0]: MTIM Counter Value LSB.
These bits contain the current value of the least
significant byte of the MTIM up counter, when
used in Speed Measurement Mode (i.e. as a 16-bit
timer)
Bits 7:0 = DC[7:0]: Next Compare Value.
These bits contain the compare value for the next
commutation (C ).
N+1
DEMAGNETIZATION REGISTER (MDREG)
Read/Write
Reset Value: 0000 0000 (00h)
CAPTURE Z
REGISTER (MZPRV)
n-1
Read /Write
Reset Value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DN7
DN6
DN5
DN4
DN3
DN2
DN1
DN0
ZP7
ZP6
ZP5
ZP4
ZP3
ZP2
ZP1
ZP0
Bits 7:0 = DN[7:0]: D Value.
These bits contain the compare value for simulat-
Bits 7:0 = ZP[7:0]: Previous Z Value or Speed
capture LSB.
ed demagnetization (D ) and the captured value
N
These bits contain the previous captured BEMF
for hardware demagnetization (D ) in Switched
H
value (Z ) in Switched and Autoswitched mode
and Autoswitched mode.
N-1
or the LSB of the captured value of the
[MTIM:MTIML] registers in Speed Sensor Mode.
In Speed Sensor Mode, the register contains the
value used for comparison with MTIM registers to
generate a Speed Error event.
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1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
A WEIGHT REGISTER (MWGHT)
INTERRUPT MASK REGISTER (MIMR)
Read/Write
Reset Value: 0000 0000 (00h)
N
Read/Write
Reset Value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PUM SEM
RIM
CLIM
EIM
ZIM
DIM
CIM
Bits 7:0 = AN[7:0]: A Weight Value.
Bit 7 = PUM: PWM Update Mask bit.
0: PWM Update interrupt disabled
1: PWM Update interrupt enabled
These bits contain the A weight value for the mul-
N
tiplier. In autoswitched mode the MCOMP register
is automatically loaded with:
Z x MWGHT
ZN-1 x MWGHT
256(d)
n
or
(*)
Bit 6 = SEM: Speed Error Mask bit.
0: Speed Error interrupt disabled
1: Speed Error interrupt enabled
256(d)
when a Z event occurs.
(*) depending on the DCB bit in the MCRA regis-
ter.
Bit 5 = RIM: Ratio update Interrupt Mask bit.
0: Ratio update interrupts (R+ and R-) disabled
1: Ratio update interrupts (R+ and R-) enabled
PRESCALER & SAMPLING REGISTER
(MPRSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 4 = CLIM: Current Limitation Interrupt Mask bit.
0: Current Limitation interrupt disabled
1: Current Limitation interrupt enabled
7
6
5
4
3
2
1
0
This interrupt is available only in Voltage Mode
(VOC1 bit=0 in MCRA register) and occurs when
the Motor current feedback reaches the external
current limitation value.
SA3
SA2
SA1
SA0
ST3
ST2
ST1
ST0
Bits 7:4 = SA[3:0]: Sampling Ratio.
These bits contain the sampling ratio value for cur-
rent mode. Refer to Table 47, “Sampling Frequen-
cy Selection,” on page 189.
Bit 3 = EIM: Emergency stop Interrupt Mask bit.
0: Emergency stop interrupt disabled
1: Emergency stop interrupt enabled
Bits 3:0 = ST[3:0]: Step Ratio.
These bits contain the step ratio value. It acts as a
prescaler for the MTIM timer and is auto incre-
mented/decremented with each R+ or R- event.
Refer to Table 40, “Step Frequency/Period Range
(4MHz),” on page 179 and Table 41, “Modes of
Accessing MTIM Timer-Related Registers,” on
page 179.
Bit 2 = ZIM: Back EMF Zero-crossing Interrupt
Mask bit.
0: BEMF Zero-crossing Interrupt disabled
1: BEMF Zero-crossing Interrupt enabled
Bit 1 = DIM: End of Demagnetization Interrupt
Mask bit.
0: End of Demagnetization interrupt disabled
1: End of Demagnetization interrupt enabled if the
HDM or SDM bit in the MCRB register is set
Bit 0 = CIM: Commutation / Capture Interrupt
Mask bit
0: Commutation / Capture Interrupt disabled
1: Commutation / Capture Interrupt enabled
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
INTERRUPT STATUS REGISTER (MISR)
Read/Write
1: Emergency stop interrupt pending
Reset Value: 0000 0000 (00h)
Bit 2 = ZI: BEMF Zero-crossing interrupt flag.
0: No BEMF Zero-crossing Interrupt pending
1: BEMF Zero-crossing Interrupt pending
7
6
5
4
3
2
1
0
PUI
RPI
RMI
CLI
EI
ZI
DI
CI
Bit 1 = DI: End of Demagnetization interrupt flag.
0: No End of Demagnetization interrupt pending
1: End of Demagnetization interrupt pending
Bit 7 = PUI: PWM Update Interrupt flag.
This bit is set by hardware when all the PWM
Compare register are transferred from the preload
to the active registers. The corresponding interrupt
allows the user to refresh the preload registers be-
fore the next PWM update event defined with
MREP register.
Bit 0 = CI: Commutation / Capture interrupt flag
0: No Commutation / Capture Interrupt pending
1: Commutation / Capture Interrupt pending
0: No PWM Update interrupt pending
1: PWM Update Interrupt pending
Note 1: Loading value FFh in the MISR register
will reset the PWM generator counter and transfer
the compare preload registers in the active regis-
ters by generating a U event (PUI bit set to 1). Re-
fer to “Timer Re-synchronisation” on page 206.
Bit 6 = RPI: Ratio Increment interrupt flag.
Autoswitched mode (SWA bit =1):
0: No R+ interrupt pending
1: R+ Interrupt pending
Note 2: When several MTC interrupts are enabled
at the same time the BRES instruction must not be
used to avoid unwanted clearing of status flags: if
a second interrupt occurs while BRES is executed
(which performs a read-modify-write sequence) to
clear the flag of a first interrupt, the flag of the sec-
ond interrupt may also be cleared and the corre-
sponding interrupt routine will not be serviced. It is
thus recommended to use a load instruction to
clear the flag, with a value equal to the logical
complement of the bit. For instance, to clear the
PUI flag:
Switched mode (SWA bit =0):
0: No R+ action
1: The hardware will increment the ST[3:0] bits
when the next commutation occurs and shift all
timer registers right.
Speed Sensor mode (SWA bit =x, TES[1:0] bits
=01, 10, 11):
0: No R+ interrupt pending
1: R+ Interrupt pending
Bit 5 = RMI: Ratio Decrement interrupt flag.
Autoswitched mode (SWA bit =1):
0: No R- interrupt pending
1: R- Interrupt pending
Switched mode (SWA bit =0):
0: No R- action
1: The hardware will decrement the ST[3:0] bits
when the next commutation occurs and shift all
timer registers left.
ld MISR, # 0x7F.
Note 3: In Autoswitched mode (SWA=1 in the
MRCA register): As all bits in the MISR register are
status flags, they are set by internal hardware sig-
nals and must be cleared by software. Any attempt
to write them to 1 will have no effect (they will be
read as 0) without interrupt generation.
Speed Sensor mode (SWA bit =x, TES[1:0] bits
=01, 10, 11):
0: No R- interrupt pending
1: R- Interrupt pending
In Switched mode (SWA=0 in the MRCA regis-
ter):
To avoid any losing any interrupts when modifying
the RMI and RPI bits the following instruction se-
quence is recommended:
Bit 4 = CLI: Current Limitation interrupt flag.
0: No Current Limitation interrupt pending
1: Current Limitation interrupt pending
ld MISR, # 0x9F ; reset both RMI & RPI bits
ld MISR, # 0xBF ; set RMI bit
ld MISR, # 0xDF ; set RPI bit
Bit 3 = EI: Emergency stop Interrupt flag.
0: No Emergency stop interrupt pending
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
CONTROL REGISTER A (MCRA)
Read/Write
Reset Value: 0000 0000 (00h)
Table 56. Output configuration summary
CKE MOE DAC Peripheral
Effect on MCOx
Output
bit bit
bit
Clock
0
0
x
Disabled
Reset state
7
6
5
4
3
2
1
0
Peripheral frozen (see
note 1 below)
0
1
0
Disabled
MOE
CKE
SR
DAC V0C1 SWA
PZ
DCB
Direct access via
MPHST
0
1
1
Disabled
Bit 7 = MOE: Output Enable bit.
0: Outputs disabled
(only logical level)
Reset state
1
1
0
1
x
Enabled
Enabled
1: Outputs enabled
Standard
0
MCO[5:0] Output pin
State
running mode.
MOE bit
Direct access via
MPHST (PWM can be
applied)
0
1
Reset state
1
1
1
Enabled
Output enabled
Note 1: “Peripheral frozen” configuration is not
recommended, as the peripheral may be stopped
in a unknown state (depending on PWM generator
outputs,etc.). It is better practice to exit from run
mode by first setting output state (by toggling ei-
ther MOE or DAC bits) and then to disabling the
clock if needed.
Notes:
– The reset state is either high impedance, high or
low state depending on the corresponding option
bit.
– When the MOE bit in the MCRA register is reset
(MCOx outputs in reset state), and the SR bit in
the MCRA register is reset (sensorless mode)
and the SPLG bit in the MCRC register is reset
(sampling at PWM frequency) then, depending
on the state of the ZSV bit in the MSCR register,
Z event sampling can run or be stopped (and D
event is sampled).
Note 2: In Direct Access Mode (DAC=1), when
CKE=0 (Peripheral Clock disabled) only logical
level can be applied on the MCOx outputs when
they are enabled whereas when CKE=1 (Peripher-
al Clock enabled), a PWM signal can be applied
on them. Refer to Table 74, “DeadTime generator
set-up,” on page 221
Bit 6 = CKE: Clock Enable Bit.
Note 3: When clocks are disabled (CKE bit reset)
while outputs are enabled (MOE bit set), the ef-
fects on the MCOx outputs where PWM signal is
applied depend on the running mode selected:
0: Motor Control peripheral Clocks disabled
1: Motor Control peripheral Clocks enabled
Note: Clocks disabled means that all peripheral in-
ternal clocks (Delay manager, internal sampling
clock, PWM generator) are disabled. Therefore,
the peripheral can no longer detect events and the
preload registers do not operate.
– in voltage mode (VOC1 bit=0), the MCOx out-
puts where PWM signal is applied stay at level 1.
– in current mode (VOC1 bit=1), the MCOx outputs
where PWM signal is applied are put to level 0.
When Clocks are disabled, write accesses are al-
lowed, so for example, MTIM counter register can
be reset by software.
In all cases, MCOx outputs where a level 1 was
applied before disabling the clocks stay at level 1.
That is why it is recommended to disable the
MCOx outputs (reset MOE bit) before disabling the
clocks. This will put all the MCOx outputs under re-
set state defined by the corresponding option bit.
210/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Effect on PWM generator: the PWM generator
12-bit counter is reset as soon as CKE = 0; this en-
sures that the PWM signals start properly in all
cases. When these bits are set, all registers with
preload on Update event are transferred to active
registers.
Table 58. DAC Bit Meaning
MOE
bit
DAC
bit
Effect on Output
Reset state depending on the option
bit
0
1
x
Standard
0
running mode.
Bit 5 = SR: Sensor ON/OFF.
0: Sensorless mode
1: Position Sensor mode
MPHST register value (depending on
MPOL, MPAR register values and
PWM setting) see Table 74
1
1
Table 57. Sensor Mode Selection
Bit 3 = V0C1: Voltage/Current Mode
0: Voltage Mode
SR
bit
OS[2:0]
bits
Behaviour of the output
PWM
Mode
1: Current Mode
“Between C &D” behaviour,
n
OS[2:0]
bits
enabled
Sensors
not used
“between D&Z” behaviour
0
1
and “between Z&C ” be-
n+1
Bit 2 = SWA: Switched/Autoswitched Mode
0: Switched Mode
1: Autoswitched Mode
haviour
“Between C &Z” behaviour
n
Sensors
used
OS1
disabled
and “between Z&C ” be-
n+1
Note 1 : after reset, in autoswitched mode (SWA
=1) , the motor control peripheral is waiting for a C
commutation event.
haviour
See also Table 61 and Table 62
Note 2: After reset, a C event is immediately gen-
erated when CKE and SWA are simultaneaously
set due to a nil value of MCOMP.
Bit 4 = DAC: Direct Access to phase state register.
0: No Direct Access (reset value). In this mode the
preload value of the MPHST and MCRB regis-
ters is taken into account at the C event.
1: Direct Access enabled. In this mode, write a val-
ue in the MPHST register to access the outputs
directly.
Note: In Direct Access Mode (DAC bit is set in
MCRA register), a C event is generated as soon
as there is a write access to the OO[5:0] bits in
MPHST register. In this case, the PWM low/high
selection is done by the OS0 bit in the MCRB
register.
Bit 1 = PZ: Protection from parasitic Zero-crossing
event detection
0: Protection disabled
1: Protection enabled
Note: If the PZ bit is set, the Z event filter
(ZEF[3:0] in the MZFR register is ignored.
Bit 0 = DCB: Data Capture bit
0: Use MZPRV (Z -1) for multiplication
N
1: Use MZREG (Z ) for multiplication
N
Table 59. Multiplier Result
DCB bit
Commutation Delay
0
1
MCOMP = MWGHT x MZPRV / 256
MCOMP = MWGHT x MZREG / 256
211/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
CONTROL REGISTER B (MCRB)
Read/Write
Reset Value: 0000 0000 (00h)
Note 1: This feature is also available when using
the three PWM outputs (PCN bit=1 in the MDTG
register), providing that the VOC1bit = 0 (MCRA
register). See section 10.6.8.2 on page 186
7
0
6
5
4
3
2
1
0
Bits 2:0 = OS2*, OS[1:0]: Operating output mode
Selection bits
CPB* HDM* SDM* OCV OS2* OS1
OS0
Refer to the Step behaviour diagrams (Figure 109,
Figure 110) and Table 61, “Step Behaviour/ sen-
sorless mode,” on page 212.
Bit 7= Reserved, must be kept at reset value.
These bits are used to define the various PWM
output configurations.
Bit 6= CPB*: Compare Bit for Zero-crossing detec-
tion.
0: Zero crossing detection on falling edge
1: Zero crossing detection on rising edge
Note: OS2 is the only preload bit.
Table 61. Step Behaviour/ sensorless mode
PWM after
PWMafter
C and
before D
PWM after
D and
before Z
Bit 5= HDM*: Hardware Demagnetization event
Mask bit
0: Hardware Demagnetization disabled
1: Hardware Demagnetization enabled
OS2
bit
OS1
bit
Z and
before next
C
OS0
On high
0
1
0
1
0
1
0
1
channels
On High
Channels
0
1
0
1
On low
channels
Bit 4= SDM*: Simulated Demagnetization event
Mask bit
0: Simulated Demagnetization disabled
1: Simulated Demagnetization enabled
On High
Channels
0
On high
channels
On Low
Channels
On low
channels
Bit 3 = OCV: Over Current Handling in Voltage
mode
0: Over Current protection is OFF
1:Over current protection is ON
On high
channels
On High
Channels
On low
channels
On Low
Channels
This bit acts as follows
1
On high
channels
On Low
Channels
Table 60. Over current handling
On low
channels
CLIM bit CLI bit OCV bit
Output effect
Interrupt
Normal running
mode
0
0
1
1
0
1
0
1
x
x
x
0
No
Note: For more details, see Step behaviour dia-
grams (Figure 109 and Figure 110).
PWM is put off as
Current loop effect
No
No
* Preload bits, new value taken into account at the
next C event. A C event is generated at each write
to MPHST in Direct Access mode.
Normal running
mode
PWM is put off as
Current loop effect
Yes
All MCOx outputs
are put in reset
state (MOE reset)
1
1
1
Yes
1)
212/309
1
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Table 62. PWM mode when SR=1
PWM after
SEI: Speed error interrupt flag
0: No Tacho Error interrupt pending
1: Tacho Error interrupt pending
PWM after Z
Unused OS0 and before
next C
OS2
bit
OS1
bit
C and
before Z
Bit 6= EDIR/HZ : Encoder Direction bit/ Hardware
zero-crossing event bit
On high
0
channels
x
On High
Channels
0
1
x
x
Position Sensor or Sensorless mode (TES[1:0]
bits =00):
On low
1
channels
HZ: Hardware zero-crossing event bit
This Read/Write bit selects if the Z event is hard-
ware or not.
0: No hardware zero-crossing event
1: Hardware zero-crossing event
On high
0
channels
x
On Low
Channels
On low
1
channels
Speed Sensor mode (TES[1:0] bits =01, 10, 11):
Table 63. PWM mode when DAC=1
EDIR:Encoder Direction bit
This bit is Read only. As the rotation direction de-
pends on encoder outputs and motor phase con-
nections, this bit cannot indicate absolute direc-
tion. It therefore gives the relative phase-shift (i.e.
advance/delay) between the two signals in quad-
rature output by the encoder (see Figure 90).
0: MCIA input delayed compared to MCIB input.
1: MCIA input in advance compared to MCIB input
OS2
bit
OS1
bit
PWM on
outputs
On high
Unused
Unused OS0
0
channels
x
x
x
x
On low
channels
1
Warning: As the MCRB register contains preload
bits with, it has to be written as a complete byte. A
Bit Set or Bit Reset instruction on a non-preload bit
will have the effect of resetting all the preload bits.
Bit 5 = SZ: Simulated zero-crossing event bit
0: No simulated zero-crossing event
1: Simulated zero-crossing event
Bit 4 = SC: Simulated commutation event bit
0: Hardware commutation event in auto-switched
mode (SWA = 1 in MCRA register)
1: Simulated commutation event in auto-switched
mode (SWA = 1 in MCRA register).
CONTROL REGISTER C (MCRC)
Read/Write (except EDIR bit)
Reset Value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
Bit 3 = SPLG: Sampling Z event at high frequency
in sensorless mode (SR=0)
SEI / EDIR/
OI HZ
SZ
SC
SPLG VR2
VR1
VR0
This bit enables sampling at high frequency in sen-
sorless mode independently of the PWM signal or
only during ON time if the DS[3:0] bits in the
MCONF register contain a value. Refer to
Table 77, “Sampling Delay,” on page 224
0: Normal mode (Z sampling at PWM frequency at
the end of the off time)
Bit 7= SEI/OI: Speed Error interrupt flag / MTIM
Overflow flag
Position Sensor or Sensorless mode (TES[1:0]
bits =00):
OI: MTIM Overflow flag
1: Z event sampled at f
(see Table 82)
SCF
This flag signals an overflow of the MTIM timer. It
has to be cleared by software.
0: No MTIM timer overflow
Note: When the SPLG bit is set, there is no mini-
mum OFF time programmed by the OT [3:0] bits,
the OFF time is forced to 0µs. This means that in
current mode, the OFF time of the PWM signal will
come only from the current loop.
1: MTIM timer overflow
Note: No interrupt is associated with this flag
Speed Sensor mode (TES[1:0] bits =01, 10, 11):
213/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Bits 2:0 = VR[2:0]: BEMF/demagnetisation Refer-
ence threshold
PHASE STATE REGISTER (MPHST)
Read/Write
Reset Value: 0000 0000 (00h)
These bits select the Vref value as shown in the
Table 64. The Vref value is used for BEMF and
Demagnetisation detection.
7
6
5
4
3
2
1
0
IS1*
IS0* OO5* OO4* OO3* OO2* OO1* OO0*
Table 64. Threshold voltage setting
VR2 VR1 VR0
Vref voltage threshold
Threshold voltage set by ex-
ternal MCVREF pin
1
1
1
Bit 7:6 = IS[1:0]*: Input Selection bits
1
1
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
3.5V*
2.5V*
2V*
These bits mainly select the input to connect to
comparator as shown in Table 65. The fourth con-
figuration (IS[1:0] = 11) specifies that an incremen-
tal encoder is used (in that case MCIA and MCIB
digital signals are directly connected to the incre-
mental encoder interface and the analog multi-
plexer is bypassed.
1.5V*
1V*
0.6V*
0.2V*
Table 65. Input Channel Selection
IS1
0
IS0
0
Channel selected
*Typical values for V =5V
DD
MCIA
0
1
MCIB
MCIC
1
0
1
1
Both MCIA and MCIB: Encoder Mode
Bits 5:0 =OO[5:0]*: Channel On/Off bits
These bits are used to switch channels on/off at
the next C event if the DAC bit =0 or directly if
DAC=1
0: Channel Off, the relevant switch is OFF, no
PWM possible
1: Channel On the relevant switch is ON, PWM is
possible (not signifiant when PCN or DTE bit is
set).
Table 66. OO[5:0] Bit Meaning
OO[5:0]
Output Channel State
0
1
Inactive
Active
* Preload bits, new value taken into account at
next C event.
Caution: As the MPHST register contains bits with
preload, the whole register has to be written at
once. This means that a Bit Set or Bit Reset in-
struction on only one bit without preload will have
the effect of resetting all the bits with preload.
214/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
MOTOR CURRENT FEEDBACK REGISTER
(MCFR)
Bits 2:0 = CFW[2:0]: Current Window Filter bits:
Read/Write
Reset Value: 0000 0000 (00h)
These bits select the length of the blanking win-
dow activated each time PWM is turned ON. The
filter blanks the output of the current comparator.
7
6
5
4
3
2
1
0
RPGS RST CFF2 CFF1 CFF0 CFW2 CFW1 CFW0
Table 68. Current Feedback Window Setting
CFW2 CFW1 CFW0
Blanking Window
Bit 7= RPGS: Register Page Selection:
0: Access to registers mapped in page 0
1: Access to registers mapped in page 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Blanking window off
0.5µs
1µs
Bit 6= RST: Reset MTC registers.
Software can set this bit to reset all MTC registers
without resetting the ST7.
0: No MTC register reset
1: Reset all MTC registers
1.5µs
2µs
2.5µs
3µs
3.5µs
Bits 5:3 = CFF[2:0]: Current Feedback Filter bits
These bits select the number of consecutive valid
samples (when the current is above the limit)
needed to generate the active event. Sampling is
Note: Times are indicated for 4 MHz f
PERIPH
done at f
/4.
PERIPH
Table 67. Current Feedback Filter Setting
CFF2 CFF1 CFF0 Current Feedback Samples
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
215/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
MOTOR D EVENT FILTER REGISTER (MDFR)
Read/Write
Bit 3:0 = DWF[3:0]: D Window Filter bits
These bits select the length of the blanking win-
dow activated at each C event. The filter blanks
the D event detection.
Reset Value: 0000 1111 (0Fh)
7
6
5
4
3
2
1
0
DEF3 DEF2 DEF1 DEF0 DWF3 DWF2 DWF1 DWF0
Table 70. D Window Filter setting
C to D
Window
Bits 7:4 = DEF[3:0]: D Event Filter bits
These bits select the number of valid consecutive
D events (when the D event is detected) needed to
generate the active event. Sampling is done at the
DWF3 DWF2 DWF1 DWF0
Filter in
Sensorless
mode (SR=0)
SR=1
selected f
frequency, see Table 82.
SCF
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5µs
10µs
15µs
20µs
25µs
30µs
35µs
40µs
60µs
80µs
100µs
120µs
140µs
160µs
180µs
200µs
Table 69. D Event filter Setting
D event
Samples
DEF3 DEF2 DEF1 DEF0
SR=1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note: Times are indicated for 4 MHz f
PERIPH
216/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
REFERENCE REGISTER (MREF)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 4:3 = HFE[1:0]: Chopping mode selection
These bits select the chopping mode as shown in
the following table.
7
6
5
4
3
2
1
0
Table 71. Chopping mode
HFE1 HFE0
Chopping mode
OFF
HST
CL
CFAV HFE1 HFE0 HFRQ2 HFRQ1 HFRQ0
0
0
1
1
0
1
0
1
On Low channels only
On High channels only
Both High and Low channels
Bit 7 = HST: Hysteresis Comparator Value.
This read only bit contains the hysteresis compa-
rator output.
0: Demagnetisation/BEMF comparator is under
V
Bits 2:0 = HFRQ[2:0] : Chopper frequency selec-
tion
REF
1: Demagnetisation/BEMF comparator is above
V
REF
These bits select the chopping frequency.
Bit 6 = CL: Current Loop Comparator Value.
This read only bit contains the current loop compa-
rator output value.
0: Current detect voltage is under V
1: Current detect voltage is above V
Table 72. Chopping frequency selection
Chopping
Chopping
frequency
CREF
CREF
frequency
HFRQ2 HFRQ1 HFRQ0
F
F
= 16MHz
= 8MHz
mtc
F
= 4MHz
mtc
Bit 5= CFAV: Current Feedback Amplifier entry
Validation
0: OAZ(MCCFI1) is the current comparator entry
1: MCCFI0 is the current comparator entry
mtc
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100 KHz
200 KHz
400 KHz
500 KHz
800 KHz
1 MHz
50 KHz
100 KHz
200 KHz
250 KHz
400 KHz
500 KHz
1.33 MHz
2 MHz
666.66 MHz
1 MHz
Note: The chopper signal has a 50% duty cycle.
217/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
PWM CONTROL REGISTER (MPCR)
Read/Write
Bit 4 = OVFW: Phase W 100% duty cycle Selec-
tion.
0: Duty cycle defined by MCPWH:MCPWL regis-
ter.
1: Duty cycle set at 100% on phase W at next up-
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
Reset Value: 0000 0000 (00h)
7
0
PMS OVFU OVFV OVFW CMS PCP2 PCP1 PCP0
Bit 7 = PMS: PWM Mode Selection.
0: Standard mode: bit b7 in the MCPxH register
represents the extension bit.
1: “8-bit” mode: bit b7 (extension bit) in the MCPxH
register is located in the MPCR register (OVFx
bits); the number of active bits in MCPxH and
MCPxL is decreased to b15:b8 instead of
b15:b3.
Bit 3 = CMS: PWM Counter Mode Selection.
0: Edge-aligned mode
1: Center-aligned mode
Bits 2:0 = PCP[2:0] PWM counter prescaler value.
This value divides the F
frequency by N, where
mtc
N is PCP[2:0] value. Table 73 shows the resulting
frequency of the PWM counter input clock.
Bit 6 = OVFU: Phase U 100% duty cycle Selec-
tion.
0: Duty cycle defined by MCPUH:MCPUL register.
1: Duty cycle set at 100% on phase U at next up-
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
Table 73. PWM clock prescaler
PCP2 PCP1 PCP0 PWM counter input clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
F
mtc
/2
F
mtc
mtc
mtc
mtc
mtc
mtc
mtc
F
F
F
F
F
F
/3
/4
/5
/6
/7
/8
Bit 5 = OVFV: Phase V 100% duty cycle Selection.
0: Duty cycle defined by MCPVH:MCPVL register.
1: Duty cycle set at 100% on phase V at next up-
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
218/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
REPETITION COUNTER REGISTER (MREP)
Read/Write
COMPARE PHASE W PRELOAD REGISTER
LOW (MCPWL)
Reset Value: 0000 0000 (00h)
Read/Write (except bits 2:0)
Reset Value: 0000 0000 (00h)
7
0
7
0
-
REP7 REP6 REP5 REP4 REP3 REP2 REP1 REP0
CPWL CPWL CPWL CPWL CPWL
7
-
-
6
5
4
3
Bits 7:0 = REP[7:0] Repetition counter value (N).
This register allows the user to set-up the update
rate of the PWM counter compare register (i.e. pe-
riodic transfers from preload to active registers),
as well as the PWM Update interrupt generation
rate, if these interrupts are enabled.
Bits 7:5 = CPWL[7:3] Low bits of phase W preload
value.
Bits 2:0 = Reserved.
COMPARE PHASE V PRELOAD REGISTER
HIGH (MCPVH)
Each time the MREP related Down-Counter
reaches zero, the Compare registers are updated,
a U interrupt is generated and it re-starts counting
from the MREP value.
Read/Write
Reset Value: 0000 0000 (00h)
After a microcontroller reset, setting the CKE bit in
the MCRA register (i.e. enabling the clock for the
MTC peripheral) forces the transfer from the
MREP preload register to its active register and
generates a U interrupt. During run-time (while
CKE bit = 1) a new value entered in the MREP
preload register is taken into account after a U
event.
7
0
CPVH7 CPVH6 CPVH5 CPVH4 CPVH3 CPVH2 CPVH1 CPVH0
Bit 7:0 = CPVH[7:0] Most Significant Byte of
phase V preload value
As shown in Figure 122, (N+1) value corresponds
to:
COMPARE PHASE V PRELOAD REGISTER
LOW (MCPVL)
Read/Write (except bits 2:0)
– The number of PWM periods in edge-aligned
mode
Reset Value: 0000 0000 (00h)
– The number of half PWM periods in center-
aligned mode.
7
0
-
–
CPVL7 CPVL6 CPVL5 CPVL4 CPVL3
-
-
COMPARE PHASE W PRELOAD REGISTER
HIGH (MCPWH)
Bits 7:5 = CPVL[7:3] Low bits of phase V preload
value.
Read/Write
Reset Value: 0000 0000 (00h)
Bits 2:0 = Reserved.
7
0
CPWH CPWH CPWH CPWH CPWH CPWH CPWH CPWH
7
6
5
4
3
2
1
0
Bits 7:0 = CPWH[7:0] Most Significant Byte of
phase W preload value
219/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
COMPARE PHASE U PRELOAD REGISTER
HIGH (MCPUH)
COMPARE
(MCP0L)
0
PRELOAD REGISTER LOW
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 1111 1111 (FFh)
7
0
7
0
CPUH CPUH CPUH CPUH CPUH CPUH CPUH CPUH
CP0L7 CP0L6 CP0L5 CP0L4 CP0L3 CP0L2 CP0L1 CP0L0
7
6
5
4
3
2
1
0
Bits 7:0 = CP0L[7:0] Low byte of Compare 0
preload value.
Bits 7:0 = CPUH[7:0] Most Significant Byte of
phase U preload value
Note 1: The 16-bit Compare registers MCMPOx,
MCMPUx, MCMPVx, MCMPWx MSB and LSB
parts have to be written sequentially before being
taken into account when an update event occurs;
refer to section 10.6.10.4 on page 201 for details.
COMPARE PHASE U PRELOAD REGISTER
LOW (MCPUL)
Read/Write Read/Write (except bits 2:0)
Reset Value: 0000 0000 (00h)
7
0
-
Note 2: The CPB, HDM, SDM, OS2 bits in the
MCRB and the bits OE[5:0] are marked with *. It
means that these bits are taken into account at the
following commutation event (in normal mode) or
when a value is written in the MPHST register
when in direct access mode. For more details, re-
fer to the description of the DAC bit in the MCRA
register. The use of a Preload register allows all
the registers to be updated at the same time.
CPUL7 CPUL6 CPUL5 CPUL4 CPUL3
-
-
Bits 7:5 = CPUL[7:3] Low bits of phase U preload
value.
Bits 2:0 = Reserved.
COMPARE
(MCP0H)
0 PRELOAD REGISTER HIGH
Warning: Access to Preload registers
Special care has to be taken with Preload regis-
ters, especially when using the ST7 BSET and
BRES instructions on MTC registers.
Read/Write (except bits 7:4)
Reset Value: 0000 1111 (0Fh)
7
0
For instance, while writing to the MPHST register,
you will write the value in the preload register.
However, while reading at the same address, you
will get the current value in the register and not the
value of the preload register.
-
-
-
-
CP0H3 CP0H2 CP0H1 CP0H0
Bits 7:4 = Reserved.
Excepted for three-phase PWM generator’s regis-
ters, all preload registers are loaded in the active
registers at the same time. In normal mode this is
done automatically when a C event occurs, how-
ever in direct access mode (DAC bit=1) the
preload registers are loaded as soon as a value is
written in the MPHST register.
Bits 3:0 = CP0H[3:0] Most Significant Bits of Com-
pare 0 preload value.
Caution: Access to write-once bits
Special care has to be taken with write-once bits in
MPOL and MDTG registers; these bits have to be
accessed first during the set-up. Any access to the
other bits (not write-once) through a BRES or a
BSET instruction will lock the content of write-once
bits (no possibility for the core do distinguish indi-
vidual bit access: Read/write internal signal acts
on a whole register only). This protection is then
only unlocked after a processor hardware reset.
220/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
DEAD TIME GENERATOR REGISTER (MDTG)
Read/Write (except bits 5:0 write once-only)
Reset Value: 1111 1111 (FFh)
When the PCN bit is reset (e.g. for PM BLDC mo-
tors), in Direct Access mode (DAC=1), if the DTE
bit is reset, PWM signals can be applied on the
MCOx outputs but not complementary PWM. Of
course, logical levels can be also applied on the
outputs.
7
0
PCN
DTE DTG5 DTG4 DTG3 DTG2 DTG1 DTG0
If the DTE bit is set (PCN=0 and DAC=1), chan-
nels are paired and complementary PWM signals
can be output on the MCOx pins. This will follow
the rules detailed in Table 53, “Dead Time genera-
tor outputs,” on page 197 as the channels are
grouped in pairs.
Bit 7 = PCN: Number of PWM Channels .
0: Only PWM U signal is output to the PWM man-
ager for six-step mode motor control (e.g. PM
BLDC motors)
1: The three PWM signals U, V and W are output
to the channel manager (e.g. for three-phase
sinewave generation)
In this case, the PWM application is selected by
the OS0 bit in the MCRB register.
It is also possible to add a chopper on the PWM
signal output using bits HFE[1:0] and HFRQ[2:0] in
the MREF register.
Bit 6 = DTE*: Dead Time Generator Enable
0: Disable the Dead Time generator
1: Enable the Dead Time generator and apply
complementary PWM signal to the adjacent
switch
* write once-only bit if PCN bit is set, read/write if
PCN bit is reset. To clear the DTE bit if PCN=1,
it is mandatory to clear the PCN bit first.
Caution 1: The PWM mode will be selected via
the 00[5:0] bits in the MPHST register, the OE[5:0]
bits in the MPAR register and the OS2 and OS0
bits in the MCRB register as shown in Table 62,
“PWM mode when SR=1,” on page 213.
Caution 2: When driving motors with three inde-
pendent pairs of complementary PWM signals
(PCN=1), disabling the deadtime generator
(DTE=0) causes the deadtime to be null: high and
low side signals are exactly complemented.
Table 74. DeadTime generator set-up
PCN bit DTE bit Complementary PWM
DAC in MDTG in MDTG
register register
applied to adjacent
switch
It is therefore recommended not to disable the
deadtime generator (it may damage the power
stage), unless deadtimes are inserted externally.
0
0
0
0
0
1
0
1
1
NO
YES
YES
Bits 5:0 = DTG[5:0]* Dead time generator set-up.
YES, but
0
1
1
0
0
0
These bits set-up the deadtime duration and reso-
lution. Refer to Table 52, “Dead time programming
and example,” on page 195 for details.
WITHOUT deadtime
NO Complementary
PWM
1
1
0
1
1
1
YES
YES
With F
= 16MHz dead time values range from
125ns mttoc 16µs with steps of 125ns, 250ns and
500ns.
YES, but
1
1
0
* Write-once bits; once write-accessed these bits
cannot be re-written unless the processor is reset
(See “Caution: Access to write-once bits” on
page 220.).
WITHOUT deadtime
Note 1: This table is true on condition that the CKE
bit is set (Peripheral clock enabled) and the MOE
bit is set (MCOx outputs enabled). See Table 56,
“Output configuration summary,” on page 210
221/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
POLARITY REGISTER (MPOL)
Read/Write (some bits write-once)
Reset Value: 0011 1111 (3Fh)
7
6
5
4
3
2
1
0
ZVD
REO
OP5
OP4
OP3
OP2
OP1
OP0
Bit 7 = ZVD: Z vs D edge polarity.
0: Zero-crossing and End of Demagnetisation
have opposite edges
1: Zero-crossing and End of Demagnetisation
have same edge
Bit 6 = REO: Read on High or Low channel bit
0: Read the BEMF signal on High channels
1: Read on Low channels
Note: This bit always has to be configured whatev-
er the sampling method.
Bits 5:0 = OP[5:0]*: Output channel polarity.
These bits are used together with the OO[5:0] bits
in the MPHST register to control the output chan-
nels.
0: Output channel is Active Low
1: Output channel is Active High.
* Write-once bits; once write-accessed these bits
cannot be re-written unless the processor is reset
(See “Caution: Access to write-once bits” on
page 220.).
Table 75. Output Channel State Control
OP[5:0] bit
OO[5:0] bit
MCO[5:0] pin
1 (Off)
0
0
1
1
0
1
0
1
0 (PWM possible)
0 (Off)
1 (PWM possible)
Warning: OP[5:0] bits in the MPOL register must
be configured as required by the application be-
fore enabling the MCO[5:0] outputs with the MOE
bit in the MCRA register.
222/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
PWM REGISTER (MPWME)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 3:0 = OT[3:0]: Off Time selection
These bits are used to select the OFF time in sen-
sorless current mode as shown in the following ta-
ble.
7
6
5
4
3
2
1
0
Table 76. OFF time bits
Sensor Mode
DG PWMW PWMV PWMU OT3
OT2
OT1
OT0
(SR=1) or sam-
Off Time sen-
pling during ON
sorless mode
Bit 7 = DG:Debug Option.
OT3 OT2 OT1 OT0
ime in sensor-
less (SPLG =1
and/or DS [3:0]
bits)
This bit is used to enter debug mode. As a result,
C, D and Z events are output on 2 pins MCDEM
and MCZEM in Switched and Autoswitched mode,
C and U events are output in Speed Measurement
mode. Refer to section10.6.7.3 on page 172 for
more details
(SR=0)
(DS[3:0]=0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.5 µs
5 µs
0: Normal mode
1: Debug mode
7.5 µs
10 µs
12.5 µs
15 µs
Bit 6 = PWMW: PWM W output control
0: PWM on Compare Register W is not output on
MCPWMW pin
1: PWM on Compare Register W is output on
MCPWMW pin
17.5 µs
20 µs
No minimum off -
time
22.5 µs
25 µs
Bit 5 = PWMV: PWM V output control
0: PWM on Compare Register V is not output on
MCPWMV pin
1: PWM on Compare Register V is output on MCP-
WMV pin
27.5 µs
30 µs
32.5 μs
35 μs
37.5 μs
40 μs
Bit 4 = PWMU: PWM U output control
0: PWM on Compare Register U is not output on
MCPWMU pin
Note: Times are indicated for 4 MHz f
PERIPH
1: PWM on Compare Register U is output on
MCPWMU pin
223/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
CONFIGURATION REGISTER (MCONF)
Read/Write
Reset Value: 0000 0010 (02h)
during the next Toff. In this case, the sample is dis-
carded.
0: No Sampling Out Interrupt Pending
1: Sampling Out Interrupt Pending
7
6
5
4
3
2
1
0
Bit 2 = SOM: Sampling Out Mask bit.
DS3
DS2
DS1
DS0
SOI
SOM XT16
XT8
This interrupt is available only for Z event sampling
as D event sampling is always done at f
frequency.
0: Sampling Out interrupt disabled
1: Sampling Out interrupt enabled
high
SCF
Bits 7:4 = DS[3:0]: Delay for sampling at Ton
These bits are used to define the delay inserted
before sampling in order to sample during PWM
ON time.
This interrupt is available only when a delay has
been set in the DS[3:0] bits in the MCONF register.
Table 77. Sampling Delay
DS3 DS2 DS1 DS0 Delay added to sample at Ton
Note: It is recommended to disable the sampling
out interrupt when software Z event is enabled (SZ
bit in MCRC register is set) and if the value in the
DS[3:0] bits is modified to change the sampling
method during the application.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No delay added. Sample during Toff
2.5 µs
5 µs
7.5 µs
10 µs
Bits [1:0] = XT16:XT8 BLDC drive Motor Control
Peripheral input frequency selection:
12.5 µs
15 µs
Table 78. Peripheral frequency
17.5 µs
20 µs
XT16
XT8 Peripheral frequency
22.5 µs
25 µs
0
0
1
0
1
0
f
f
f
f
=f
PERIPH MTC
=f
/2
/4
/4
PERIPH MTC
27.5 µs
30 μs
32.5 μs
35 μs
=f
PERIPH MTC
=f
PERIPH MTC
1
1
(same as XT16=1,XT8=0)
37.5 μs
Caution: It is recommended to set the peripheral
Note: Times are indicated for 4 MHz f
frequency to 4MHz. Setting f
=f
is used
PERIPH
PERIPH MTC
mainly when f = 4MHz (for low power consump-
clk
tion).
Bit 3 = SOI Sampling Out Interrupt flag.
This interrupt indicates that the sampling that
should have been done during Ton has occured
224/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
PARITY REGISTER (MPAR)
Read/Write
Table 79. Tacho edges and input mode selection
TES 1 TES 0 Edge sensitivity Operating Mode
Reset Value: 0000 0000 (00h)
Position Sensor or
0
0
Not applicable
Sensorless
Speed Sensor
Speed Sensor
7
6
5
4
3
2
1
0
0
1
1
0
Rising edge
Falling edge
TES1 TES0 OE5
OE4
OE3
OE2
OE1
OE0
Rising and falling
edges
1
1
Speed Sensor
Bits 7:6 = TES[1:0] : Tacho Edge Selection bits
The primary function of these bits is to select the
edge sensitivity of the tachogenerator capture log-
ic; clearing both TES[1:0] bits specifies that the In-
put Detection block does not operate in Speed
Sensor Mode but either in Position Sensor or Sen-
sorless Mode for a six-step motor drive).
Bits 5:0 = OE[5:0]: Output Parity Mode.
0: Output channel is High
1: Output channel Low
Note: These bits are not significant when PCN=1
(configuration with three independent phases).
225/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
MOTOR Z EVENT FILTER REGISTER (MZFR)
Read/Write
Bits 3:0 = ZWF[3:0]: Z Window Filter bits
These bits select the length of the blanking win-
dow activated at each D event. The filter blanks
the Z event detection until the end of the time win-
dow.
Reset Value: 0000 1111 (0Fh)
7
6
5
4
3
2
1
0
Table 81. Z Window filter Setting
ZEF3 ZEF2 ZEF1 ZEF0 ZWF3 ZWF2 ZWF1 ZWF0
D to Z window fil-
ZWF3 ZWF2 ZWF1 ZWF0 ter in Sensorless SR=1
Mode (SR=0)
Bits 7:4 = ZEF[3:0]: Z Event Filter bits
These bits select the number of valid consecutive
Z events (when the Z event is detected) needed to
generate the active event. Sampling is done at the
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5 µs
10 µs
15 µs
20 µs
25 µs
30 µs
35 µs
40 µs
60 µs
80 µs
100 µs
120 µs
140 µs
160 µs
180 µs
200 µs
selected f
frequency (see Table 82.) or at
SCF
PWM frequency.
Table 80. Z Event filter Setting
No
Win-
dow
Filter
after
D
ZEF3 ZEF2 ZEF1 ZEF0
Z event Samples
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
event
4
5
6
7
8
Note: Times are indicated for 4 MHz f
PERIPH
9
10
11
12
13
14
15
16
226/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
MOTOR SAMPLING CLOCK REGISTER
Table 82. Sampling Clock Frequency
(MSCR)
SCF1 SCF0
f
SCF
Read/Write
Reset Value: 0000 0000 (00h)
0
0
1
1
0
1
0
1
1 MHz (every 1µs)
500 kHz (every 2µs)
250 kHz (every 4µs)
125 kHz (every 8µs)
7
6
0
5
0
4
0
3
2
1
0
ZSV
SCF1 SCF0 ECM DISS
Note: Times are indicated for 4 MHz f
Bit 1 = ECM: Encoder Capture Mode
This bit is used to select the source of events
which trigger the capture of the [MTIM:MTIML]
counter when using Encoder speed sensor (see
Figure 90).
PERIPH
Bit 7 = ZSV Z Event Sampling Validation when
MOE bit is reset
This bit enables/disables Z event sampling in ei-
ther mode (sampling at PWM frequency or at f
frequency selected by SCF[1:0] bits)
0: Z event sampling disabled
SCF
0: Real-time Clock interrupts
1: Read access on MTIM register
1: Z event sampling enabled
Bits 6:4 = Reserved, must be kept cleared.
Bit 0 = DISS Data Input Selection
This setting is effective only if PCN=0, TES=00
and SR=0.
0: Unused MCIx inputs are grounded
1: Unused MCIx inputs are put in HiZ
Bits 3:2 = SCF[1:0] Sampling Clock Frequency
These bits select the sampling clock frequency
(f
) used to count D & Z events.
SCF
227/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 123. General view of the MTC for PM BLDC motor control
s
v i e r r d
t i b V O C
t i I b C L
t i b M C L I
t i E b M O
R e O L M P
g
R E e M W M P
g
N
O A O
g
R e
p e r h o p n c y u e C e q F r H i g h
E F M R
e m T i
D e a
e
T i m
D e a d
m T e i
a d D e
= 0
P C N b i t
d
e r g i s t r e T G D M
5
C h
t i s b
0
C h
C h 2 3 C h
C h 4
1
C h
M P A R R e g
t i b 0 : ] 2 [ W C F
n
O S
n
R e T g S
M P H
t
b 0 i : ] 2 F F C [
S R b i t
Compare U
V
I
V
2
I
g e R M R M I
g e R S R M I
1
/ C i l t F e r
D W F [ 3
0 : ]
/ D e r F i l t
0 : ] 3 Z W F [
228/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 124. General view of the MTC configured for Induction motor control (proposal)
s r e v i d r
t i b V O C
t i b I C L
t i b I M L C
t i
b
M O E
g
R L e O M P
N O O A
P A M R R
g
R e
g e
p e r h o p c y C u e e n q F r H i g h
E F M R
e
d
T i m
D e a
e
d
T i m
D e a
e m T i
a d D e
= 1 b N i t P C
g i s t r e e T G M D
r
g e R M R M I
R R e g M I S
229/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Table 83. MTC Page 0 Register Map and Reset Values
Register Name
MTIM
7
6
5
4
3
2
1
0
T7
0
T6
0
T5
0
T4
0
T3
0
T2
0
T1
0
T0
0
Reset Value
MTIML
Reset Value
TL7
0
TL6
0
TL5
0
TL4
0
TL3
0
TL2
0
TL1
0
TL0
0
MZPRV
Reset Value
ZP7
0
ZP6
0
ZP5
0
ZP4
0
ZP3
0
ZP2
0
ZP1
0
ZP0
0
MZREG
Reset Value
ZC7
0
ZC6
0
ZC5
0
ZC4
0
ZC3
0
ZC2
0
ZC1
0
ZC0
0
MCOMP
Reset Value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
MDREG
Reset Value
DN7
0
DN6
0
DN5
0
DN4
0
DN3
0
DN2
0
DN1
0
DN0
0
MWGHT
Reset Value
AN7
0
AN6
0
AN5
0
AN4
0
AN3
0
AN2
0
AN1
0
AN0
0
MPRSR
Reset Value
SA3
0
SA2
0
SA1
0
SA0
0
ST3
0
ST2
0
ST1
0
ST0
0
MIMR
Reset Value
PUM
0
SEM
0
RIM
0
CLIM
0
EIM
0
ZIM
0
DIM
0
CIM
0
MISR
Reset Value
PUI
0
RPI
0
RMI
0
CLI
0
EI
0
ZI
0
DI
0
CI
0
MCRA
Reset Value
MOE
0
CKE
0
SR
0
DAC
0
V0C1
0
SWA
0
PZ
0
DCB
0
MCRB
Reset Value
CPB
0
HDM
0
SDM
0
OCV
0
OS2
0
OS1
0
OS0
0
0
MCRC
Reset Value
SEI / OI EDIR / HZ
SZ
0
SC
0
SPLG
0
VR2
0
VR1
0
VR0
0
0
0
OO0
0
MPHST
Reset Value
IS1
0
IS0
0
OO5
0
OO4
0
OO3
0
OO2
0
OO1
0
MDFR
Reset Value
DEF3
0
DEF2
0
DEF1
0
DEF0
0
DWF3
1
DWF2
1
DWF1
1
DWF0
1
MCFR
Reset Value
RPGS
0
RST
0
CFF2
0
CFF1
0
CFF0
0
CFW2
0
CFW1
0
CFW0
0
CFAV
0
MREF
Reset Value
HST
0
CL
0
HFE1
0
HFE0
0
HFRQ2
0
HFRQ1
0
HFRQ0
0
OVFV
0
MPCR
Reset Value
PMS
0
OVFU
0
OVFW
0
CMS
0
PCP2
0
PCP1
0
PCP0
0
MREP
Reset Value
REP7
0
REP6
0
REP5
0
REP4
0
REP3
0
REP2
0
REP1
0
REP0
0
MCPWH
CPWH7 CPWH6 CPWH5 CPWH4
CPWH3 CPWH2 CPWH1 CPWH0
Reset Value
0
0
0
0
0
0
0
0
230/309
ST7MC1xx/ST7MC2xx
Register Name
MCPWL
7
6
5
4
3
2
1
0
CPWL7
0
CPWL6
0
CPWL5
0
CPWL4
0
CPWL3
0
0
0
0
Reset Value
MCPVH
Reset Value
CPVH7
0
CPVH6
0
CPVH5
0
CPVH4
0
CPVH3
0
CPVH2
0
CPVH1
0
CPVH0
0
MCPVL
Reset Value
CPVL7
0
CPVL6
0
CPVL5
0
CPVL4
0
CPVL3
0
0
0
0
MCPUH
Reset Value
CPUH7
0
CPUH6
0
CPUH5
0
CPUH4
0
CPUH3
0
CPUH2
0
CPUH1
0
CPUH0
0
MCPUL
Reset Value
CPUL7
0
CPUL6
0
CPUL5
0
CPUL4
0
CPUL3
0
0
0
0
MCP0H
Reset Value
CP0H3
1
CP0H2
1
CP0H1
1
CP0H0
1
0
0
0
0
MCP0L
Reset Value
CP0L7
1
CP0L6
1
CP0L5
1
CP0L4
1
CP0L3
1
CP0L2
1
CP0L1
1
CP0L0
1
Table 84. MTC Page 1 Register Map and Reset Values
Register Name
MDTG
7
6
5
4
3
2
1
0
PCN
1
DTE
1
DTG5
1
DTG4
1
DTG3
1
DTG2
1
DTG1
1
DTG0
1
Reset Value
MPOL
Reset Value
ZVD
0
REO
0
OP5
1
OP4
1
OP3
1
OP2
1
OP1
1
OP0
1
MPWME
Reset Value
DG
0
PWMW
0
PWMV
0
PWMU
0
OT3
0
OT2
0
OT1
0
OT0
0
MCONF
DS3
0
DS2
0
DS1
0
DS0
0
SOI
0
SOM
0
XT16
1
XT8
0
Reset Value
MPAR
Reset Value
TES1
0
TES0
0
OE5
0
OE4
0
OE3
0
OE2
0
OE1
0
OE0
0
MZFR
Reset Value
ZEF3
0
ZEF2
0
ZEF1
0
ZEF0
0
ZWF3
1
ZWF2
1
ZWF1
1
ZWF0
1
MSCR
Reset Value
ZSV
0
SCF1
0
SCF0
0
ECM
0
DISS
0
0
0
0
231/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Figure 125. Page Mapping for Motor Control
PAGE 1
RPGS bit =1 in MCFR register
PAGE 0
MTIM
50
51
MDTG
MPOL
MTIML
MZPRV
MZREG
MCOMP
52
53
54
MPWME
MCONF
MPAR
MZFR
55
56
MDREG
MWGHT
MPRSR
MSCR
MIMR
MISR
MCRA
MCRB
MCRC
MPHST
MDFR
MCFR
MREF
MPCR
MREP
MCPWH
MCPWL
MCPVH
MCPVL
MCPUH
MCPUL
MCPOH
MCPOL
10.6.14 Related Documentation
AN1904: ST7MC Three-phase AC Induction Motor
Control Software Library
AN1947: ST7MC PMAC Sine Wave Motor Control
Software Library
AN1905: ST7MC Three-Phase BLDC Motor Con-
trol Software Library
AN2009: PWM Management For 3-phase BLDC
Motor Drives Using The ST7FMC
AN1946: Sensorless BLDC Motor Control And
BEMF Sampling Methods With ST7MC
AN2030: Back EMF Detection During PWM On
Time By ST7MC
232/309
ST7MC1xx/ST7MC2xx
10.7 OPERATIONAL AMPLIFIER (OA)
10.7.1 Introduction
The input/output pins are connected to the Op-
Amp as soon as it is switched ON (through the
OACSR register).
The ST7 Op-Amp module is designed to cover
various types of microcontroller applications
where analog signals amplifiers are used.
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the “I/O ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
It may be used to perform a variety of functions
such as: differential voltage amplifier, comparator/
threshold detector, ADC zooming, impedance
adaptor, general purpose operational amplifier.
The output is not connected (HiZ) when the Op-
Amp is OFF. However the pin can still be used as
an ADC or MTC input in this case.
10.7.2 Main Features
This module includes:
■ 1 stand alone Op-Amp that may be externally
When the Op-Amp is ON the output is connected
to a dedicated pin which is not a standard I/O port.
The output can be also be connected to the ADC
or the MTC. The switches are controlled software
(refer to the MTC and ADC chapters).
connected using I/O pins
■ Op-Amp output can be internally connected to
the ADC inputs as well as to the motor control
current feedback comparator input
■ Input offset compensation with optional average
10.7.4 Input Offset Compensation
■ On/Off bit to reduce power consumption and to
enable the input/output connections with
external pins
The Op-Amp incorporates a method to minimize
the input offset which is dependant on process lot.
It is useable by setting the OFFCMP bit of the con-
trol register, which launch the compensation cycle.
The CMPVR bit is set by hardware as soon as this
cycle is completed. The compensation is valid as
long as the OFFCMP bit is high. It can be re-per-
formed by cycling OFFCMP ‘0’ then ‘1’.
10.7.3 General Description
This Op-Amp can be used with 3 external pins
(see device pinout description) and can be inter-
nally connected to the ADC and the Motor Control
cells. The gain must be fixed with external compo-
nents.
The compensation can be improved by averaging
the calculation (over 16 times) setting the AVGC-
MP bit.
233/309
ST7MC1xx/ST7MC2xx
OP-AMP MODULE (Cont’d)
10.7.5 Op-Amp Programming
The flowchart for Op-Amp operation is shown in
Figure 126
Figure 126. Normal Op-Amp Operation
Power On Reset
OACSR = 0000 0000
External components always connected
(1)
Write OACSR = x0010xx0
Wait for Amplifier to wake up (T
)
wakeup
No
Compensation Offset ?
Yes
(4)
Write OACSR = x0p1 pxx0
p : same as before
No
Yes
Average Compensation ?
(2b)
(2a)
Write OACSR = x111 0xx0
Wait for 24576*TCPU cycles
Read CMPOVR = 1
Write OACSR = x101 0xx0
Wait for 1536*TCPU cycles
Read CMPOVR = 1
#OFFCMP & AVGCMP
should be set simultenaously
Need
closed loop gain > 20dB @ 100kHz ?
Yes
(3) #
Write OACSR = x1p1 1xx0
p : same as before
No
Yes
Re-compensate
Offset ?
Op-Amp useable
#The HIGHGAIN bit can also be written in step (1) or (2)
No
234/309
ST7MC1xx/ST7MC2xx
OP-AMP MODULE (Cont’d)
10.7.6 Low power modes
10.7.8 Register Description
Note: The Op-Amp can be disabled by resetting
the OAON bit. This feature allows reduced power
consumption when the amplifier is not used.
CONTROL/STATUS REGISTER (OACSR)
Read/Write (except bit 7 read only)
Reset Value: 0000 0000(00h)
Mode
Description
7
6
5
4
3
2
0
1
0
0
0
No effect on Op-Amp
Op-Amp disabled
Wait
CMP
OVR
AVG OAO HIGH
CMP GAIN
OFF
CMP
N
After wake-up from Halt mode, the Op-
Amp requires a stabilization time (see
Electrical characteristics) (to be defined)
Halt
Bit 7 = CMPOVR Compensation Completed
This read-only bit contains the offset compensa-
tion status.
10.7.7 Interrupts
0: No offset compensation if OFFCMP = 0, or
Offset compensation cycle not completed if
OFFCMP = 1
None.
1: Offset compensation completed if OFFCMP = 1
Bit 6 = OFFCMP Offset Compensation
0: Reset offset compensation values
1: Request to start offset compensation
Bit 5 = AVGCMP Average Compensation
0: One-shot offset compensation
1: Average offset compensation over 16 times
Bit 4 = OAON Amplifier On
0: Op-Amp powered off
1: Op-Amp on
Bit 3 = HIGHGAIN Gain range selection
This bit must be programmed depending on the
application. It can be used to ensure 35dB open
loop gain when high, it must be low when the
closed loop gain is below 20dB for stability rea-
sons.
0: Closed loop gain up to 20dB
1: Closed loop gain more than 20dB
Bits 2:0 = Reserved, must be kept cleared.
235/309
ST7MC1xx/ST7MC2xx
10.8 10-BIT A/D CONVERTER (ADC)
10.8.1 Introduction
■ Conversion complete status flag
■ Maskable interrupt
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 127.
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
10.8.3 Functional Description
10.8.3.1 Analog References
V
and V
are the high and low level refer-
REF-
REF+
The result of the conversion is stored in 2 8-bit
Data Registers. The A/D converter is controlled
through a Control/Status Register.
ence voltage pins. Conversion accuracy may
therefore be impacted by voltage drops and noise
on these lines. V
can be supplied by an inter-
REF+
mediate supply between V
and V
to
10.8.2 Main Features
■ 10-bit conversion
■ Up to 16 channels with multiplexed input
■ 2 software-selectable sample times
DDA
SSA
change the conversion voltage range. V
must
REF-
be tied to V
. An internal resistor bridge is im-
SSA
plemented between V
and V
pins, with a
REF+
REF-
typical value of 15kΩ
■ External positive reference voltage V
can
10.8.3.2 Analog Power Supply
and V are the supply and ground pins
REF+
be independent from supply
V
DDA
SSA
■ Linear successive approximation
■ Data registers (DR) which contain the results
providing power to the converter part. They must
be tied to V and V respectively.
DD
SS
Figure 127. ADC Block Diagram
f
ADC
PRESCALER
EOC PRSC1PRSC0ADON CS3 CS2 CS1 CS0
ADCCSR
4
IT
request
AIN0
AIN1
ADSTSADCIE
MCCBCR
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRMSB
ADCDRLSB
D9 D8 D7 D6 D5 D4
D3
D2
0
0
0
0
0
0
D1
D0
236/309
ST7MC1xx/ST7MC2xx
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.3.3 Digital A/D Conversion Result
10.8.3.4 A/D Conversion
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input. If the application used the high-im-
pedance analog inputs, then the sample time
should be stretched by setting the ADSTS bit in
the MCCBCR register.
If the input voltage (V ) is greater than V
AIN
REF+
(high-level voltage reference) then the conversion
result is FFh in the ADCDRMSB register and 03h
in the ADCDRLSB register (without overflow indi-
cation).
In the ADCCSR register:
If the input voltage (V ) is lower than V
(low-
REF-
AIN
level voltage reference) then the conversion result
in the ADCDRMSB and ADCDRLSB registers is
00 00h.
– Select the CS[3:0] bits to assign the analog
channel to convert.
ADC Conversion mode
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRMSB and
ADCDRLSB registers. The accuracy of the con-
version is described in the Electrical Characteris-
tics Section.
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
R
is the maximum recommended impedance
AIN
– The EOC bit is kept low by hardware during the
conversion.
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
Note: Changing the A/D channel during conver-
sion will stop the current conversion and start con-
version of the newly selected channel.
R
is the value of the resistive bridge imple-
REF
mented in the device between V
and V
REF+
REF-.
237/309
ST7MC1xx/ST7MC2xx
10-BIT A/D CONVERTER (ADC) (Cont’d)
When a conversion is complete:
To guarantee consistency:
– The EOC bit is set by hardware
– The ADCDRMSB and the ADCDRLSB are
locked when the ADCCRLSB is read
– The ADCDRMSB and the ADCDRLSB are un-
locked when the MSB is read or when ADON
is reset.
– An interrupt request is generated if the ADCIE
bit in the MCCBCR register is set (see section
6.4.7 on page 38).
– The result is in the ADCDR registers and re-
mains valid until the next conversion has end-
ed.
Thus, it is mandatory to read the ADCDRMSB just
after reading the ADCDRLSB. Otherwise the AD-
CDR register will not be updated until the AD-
CDRMSB is read.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit or wait for EOC interrupt
2. Read ADCDRLSB
10.8.4 Low Power Modes
3. Read ADCDRMSB
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
The EOC bit is reset by hardware once the AD-
CDRMSB is read.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit or wait for EOC interrupt
2. Read ADCDRMSB
Mode
Description
Wait
No effect on A/D Converter
A/D Converter disabled.
The EOC bit is reset by hardware once the AD-
CDRMSB is read.
After wake up from Halt mode, the A/D
Converter requires a stabilization time
Halt
t
(see Electrical Characteristics)
STAB
Changing the conversion channel
before accurate conversions can be
performed.
The application can change channels during con-
version. In this case the current conversion is
stopped and the A/D converter starts converting
the newly selected channel.
10.8.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Interrupt
Event
Event
Flag
ADCCR consistency
Wait
If an End Of Conversion event occurs after soft-
ware has read the ADCDRLSB but before it has
read the ADCDRMSB, there would be a risk that
the two values read would belong to different sam-
ples.
End of Conver-
sion
1)
EOC ADCIE
Yes
No
1)
The ADCIE bit is in the MCCBCR register (see
section 6.4.7 on page 38)
238/309
ST7MC1xx/ST7MC2xx
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
DATA REGISTER (ADCDRMSB)
Read Only
7
0
Reset Value: 0000 0000 (00h)
EOC PRSC1 PRSC0 ADON CS3
CS2
CS1
CS0
7
0
Bit 7 = EOC End of Conversion
D9
D8
D7
D6
D5
D4
D3
D2
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRMSB register.
0: Conversion is not complete
Bit 7:0 = D[9:2] MSB of Analog Converted Value
This register contains the MSB of the converted
analog value.
1: Conversion complete
Bit 6:5 = PRSC[1:0] ADC clock prescaler selection
These bits are set and cleared by software.
DATA REGISTER (ADCDRLSB)
Read Only
f
PRSC1
PRSC0
ADC
4MHz
2MHz
1MHz
0
0
1
0
1
0
Reset Value: 0000 0000 (00h)
7
0
0
Bit 4 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
0
0
0
0
0
D1
D0
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
This register contains the LSB of the converted an-
alog value.
Bit 3:0 = CS[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
*The number of channels is device dependent. Refer to
the device pinout description.
239/309
ST7MC1xx/ST7MC2xx
10-BIT A/D CONVERTER (ADC) (Cont’d)
Table 85. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
PRSC1
0
PRSC0
0
ADON
0
CS3
0
CS2
0
CS1
0
CS0
0
2E
2F
30
ADCDRMSB
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRLSB
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
D1
0
D0
0
240/309
ST7MC1xx/ST7MC2xx
11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The CPU features 17 different addressing modes
which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 86. CPU Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
ld A,$10
00..FF
Direct
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Direct
Indexed
Indexed
Indexed
Direct
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Direct
Short
Long
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF 00..FF
00..1FE 00..FF
Short
Long
Indexed
Indexed
0000..FFFF 00..FF
PC+/-127
Relative
Relative
Bit
Indirect
Direct
jrne [$10]
PC+/-127
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
Bit
Relative btjt $10,#7,skip
Relative btjt [$10],#7,skip
Bit
Indirect
241/309
ST7MC1xx/ST7MC2xx
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
11.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
11.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
SWAP
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
242/309
ST7MC1xx/ST7MC2xx
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
11.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 87. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
243/309
ST7MC1xx/ST7MC2xx
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The instructions are described with one to four op-
codes.
PIX 92
Replace an instruction using di-
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
The whole instruction becomes:
PC-2
PC-1
PC
End of previous instruction
Prebyte
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
11.2.1 Illegal Opcode Reset
opcode
In order to provide enhanced robustness to the de-
vice against unexpected behaviour, a system of il-
legal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
244/309
ST7MC1xx/ST7MC2xx
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. INT pin = 1
Jump if ext. INT pin = 0
Jump if H = 1
(ext. INT pin high)
(ext. INT pin low)
H = 1 ?
JRH
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
245/309
ST7MC1xx/ST7MC2xx
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2's compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
246/309
ST7MC1xx/ST7MC2xx
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
Figure 129. Pin input voltage
ferred to V
.
SS
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
ST7 PIN
V
IN
devices with an ambient temperature at T =25°C
A
and T =T max (given by the selected temperature
A
A
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean 3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V. They are given only as de-
A
DD
sign guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 128.
Figure 128. Pin loading conditions
ST7 PIN
C
L
12.1.5 Pin input voltage
The input voltage measurement on a pin of the de-
vice is described in Figure 129.
247/309
ST7MC1xx/ST7MC2xx
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
12.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
Unit
V
- V
- V
Supply voltage
6.5
DD
SS
SS
V
Programming Voltage
13
V
PP
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
IN
|ΔV
| and |ΔV
|
SSx
Variations between different digital power pins
Variations between digital and analog ground pins
Electro-static discharge voltage (Human Body Model)
50
50
DDx
mV
|V
- V
|
SSx
SSA
V
ESD(HBM)
see section 12.7.3 on page 263
Electro-static discharge voltage
(Charged Device Model)
V
ESD(CDM)
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
32-pin devices
44-pin devices
75
Total current into V power lines
(source)
125
DD
I
3)
VDD
56, 64, 80-pin
devices
175
32-pin devices
44-pin devices
75
Total current out of V ground lines
(sink)
125
SS
I
3)
VSS
56, 64, 80-pin
devices
175
mA
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
25
50
- 25
5
I
IO
Output current source by any I/Os and control pin
Injected current on V pin
PP
Injected current on RESET pin
5
2) & 4)
2)
I
INJ(PIN)
Injected current on OSC1 and OSC2 pins
5
5)
Injected current on any other pin
5
5)
ΣI
Total injected current (sum of all I/O and control pins)
20
INJ(PIN)
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to V or V
.
DD
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
INJ(PIN)
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
while a negative injection is induced by V <V
.
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy with VDD=5.0V” on
page 284.
For best reliability, it is recommended to avoid negative injection of more than 1.6mA
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
248/309
ST7MC1xx/ST7MC2xx
ABSOLUTE MAXIMUM RATINGS (Cont’d)
12.2.3 Thermal Characteristics
Symbol
Ratings
Storage temperature range
Value
Unit
T
-65 to +150
°C
STG
T
Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)
J
249/309
ST7MC1xx/ST7MC2xx
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
f
Internal clock frequency versus V
0
8
MHz
CPU
DD
No Flash Write/Erase. Analog
parameters not guaranteed
Extended operating voltage
3.8
5.5
1)
V
V
DD
Standard operating voltage
4.5
4.5
-40
-40
5.5
5.5
85
Operating voltage for flash Write/Erase
Ambient temperature range
V
= 11.4 to 12.6V
PP
6 Suffix Version
C Suffix Version
°C
T
A
125
Figure 130. f
Max Versus VDD
CPU
f
[MHz]
CPU
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS
OTHERWISE
SPECIFIED
IN THE TABLES
OF PARAMETRIC
DATA)
8
6
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
1
0
3.5
3.8 4.0
4.5
5.5
SUPPLY VOLTAGE [V]
Note 1: Clock Detector, ADC, comparator and OPAMP functionalities guaranteed only within 4.5-5.5V
voltage range.
Note:
Some temperature ranges are only available with a specific package and memory size. Refer to Ordering
Information.
Warning: Do not connect 12V to V before V is powered on, as this may damage the device.
PP
DD
250/309
ST7MC1xx/ST7MC2xx
OPERATING CONDITIONS (Cont’d)
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V , f
, and T .
A
DD OSC
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Reset release threshold
V
3.90
4.20
4.50
IT+(LVD)
(V rise)
DD
V
Reset generation threshold
V
V
3.80
20
4.00
200
4.35
IT-(LVD)
hys(LVD)
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
mV
μs/V
ms/V
IT+(LVD) IT-(LVD)
1)
Vt
V
rise time rate
DD
POR
100
40
1)
Width of filtered glitches on V
(which are not detected by the LVD)
DD
t
ns
g(VDD)
Notes:
1. Data based on characterization results, not tested in production.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating condition for V , f
, and T .
DD OSC
A
2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1⇒0 AVDF flag toggle threshold
DD
V
4.35
4.70
4.90
4.70
IT+(AVD)
(V rise)
V
0⇒1 AVDF flag toggle threshold
V
V
4.20
4.50
200
450
IT-(AVD)
(V fall)
DD
1)
AVD voltage threshold hysteresis
V
V
-V
mV
mV
hyst(AVD)
IT+(AVD) IT-(AVD)
Voltage drop between AVD flag set
ΔV
-V
)
IT-
IT-(AVD) IT-(LVD)
and LVD reset activated
Notes:
1. Data based on characterization results, not tested in production.
2. See “MAXIMUM VALUES OF AVD THRESHOLDS” on page 304..
251/309
ST7MC1xx/ST7MC2xx
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for Halt mode for which the clock is stopped).
12.4.1 Run and Slow modes (Flash devices)
1)
Symbol
Parameter
Conditions
Typ
Max
Unit
2)
Supply current in Run mode
(see Figure 131)
f
f
=16MHz, f
=8MHz
12
18
mA
OSC
CPU
I
DD
2)
Supply current in Slow mode
(see Figure 132)
=16MHz, f
=500kHz
5
8
mA
OSC
CPU
Figure 131. Typical I in Run vs. f
Figure 132. Typical I in Slow vs. f
CPU
DD
CPU
DD
16.0
14.0
12.0
10.0
8.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6.0
4.0
2.0
0.0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Fcpu Mhz
Fcpu Mhz
Notes:
1. Data based on characterization results, tested in production at V max. and f
max.
DD
CPU
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at V or V (no load)
DD
SS
- All peripherals in reset state.
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In Slow and Slow-wait mode, f is based on f
divided by 32.
OSC
CPU
To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the peripheral power
consumption.
252/309
ST7MC1xx/ST7MC2xx
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.2 Wait and Slow-wait Modes
1)
Symbol
Parameter
Conditions
Typ
Max
Unit
2)
Supply current in Wait mode
(see Figure 133)
f
f
=16MHz, f
=8MHz
CPU
8
12
OSC
I
mA
DD
2)
Supply current in Slow-wait mode
(see Figure 134)
=16MHz, f
=500kHz
3.5
5
OSC
CPU
Figure 133. Typical I in Wait vs. f
Figure 134. Typical I in Slow-wait vs. f
CPU
DD
CPU
DD
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.5
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Fcpu Mhz
Fcpu Mhz
Notes:
1. Data based on characterization results, tested in production at V max. and f
max.
DD
CPU
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at V or V (no load)
DD
SS
- All peripherals in reset state.
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In Slow and Slow-wait mode, f is based on f
divided by 32.
OSC
CPU
To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the peripheral power
consumption.
253/309
ST7MC1xx/ST7MC2xx
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.3 Halt and Active-halt modes
Symbol
Parameter
Conditions
Typ
1
Max
10
Unit
μA
-40°C≤T ≤+85°C
A
1)
Supply current in Halt mode
V
=5.5V
DD
I
-40°C≤T ≤+125°C
50
DD
A
2)
Supply current in Active-halt mode
16Mhz external clock
1
1.5
mA
1. All I/O pins in push-pull output mode (when applicable) with a static value at V or V (no load), PLL and LVD dis-
DD
SS
CPU
abled. Data based on characterization results, tested in production at V max. and f
max.
DD
2. All I/O pins in input mode with a static value at V or V . Tested in production at V max and f max with clock
DD
DD
SS
DD
cpu
input OSC1 driven by an external square wave; V applied on OSC2 to reduce oscillator consumption. Consumption
may be slightly different with a quartz or resonator.
12.4.4 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for Halt mode).
Symbol
Parameter
LVD supply current
PLL supply current
Conditions
Typ
180
700
Max
Unit
I
Halt mode
= 5V
280
DD(LVD)
μA
I
V
DD
DD(PLL)
254/309
ST7MC1xx/ST7MC2xx
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.5 On-Chip Peripherals
Symbol
Parameter
Conditions
Typ
50
Unit
1)
I
16-bit Timer supply current
f
f
f
f
f
f
f
=8MHz
V
V
V
V
V
V
V
=5.0V
DD(TIM)
CPU
CPU
CPU
CPU
CPU
ADC
CPU
DD
DD
DD
DD
DD
DD
DD
2)
I
ART PWM supply current
=8MHz
=8MHz
=8MHz
=8MHz
=4MHz
=8MHz
=5.0V
=5.0V
=5.0V
=5.0V
=5.0V
=5.0V
75
DD(ART)
3)
I
SPI supply current
400
400
500
400
1500
DD(SPI)
4)
I
SCI supply current
μA
DD(SCI)
5)
I
MTC supply current
DD(MTC)
6)
I
ADC supply current when converting
DD(ADC)
7)
I
OPAMP supply current
DD(OPAMP)
Notes:
1. Data based on a differential I
measurement between reset configuration (timer counter running at f
/4) and timer
CPU
DD
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential I
(only TCE bit set)
measurement betwwen reset configuration (timer stopped) and timer counter enable
DD
3. Data based on a differential I
measurement between reset configuration (SPI disabled) and a permanent SPI master
DD
communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consumption.
4. Data based on a differential I measurement between SCI low power state (SCID=1) and a permanent SCI data trans-
DD
mit sequence.
5. Data based on a differential I measurement between reset configuration (motor control disabled) and the whole mo-
DD
tor control cell enable in speed measurement mode. MCO outputs are not validated.
6. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
7. Data based on a differential measurement between reset configuration (OPAMP disabled) and amplification of a sin-
ewave (no load, A
=1, V =5V).
DD
VCL
255/309
ST7MC1xx/ST7MC2xx
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
12.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
375
1500
22
CPU
2)
tCPU
μs
Interrupt reaction time
t
v(IT)
t
= Δt
+ 10
=8MHz
1.25
2.75
v(IT)
c(INST)
CPU
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
12.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
0.7xV
V
DD
OSC1H
DD
V
V
V
0.3xV
DD
OSC1L
SS
t
t
1)
w(OSC1H)
see Figure 135
OSC1 high or low time
25
w(OSC1L)
ns
t
t
1)
r(OSC1)
OSC1 rise or fall time
5
1
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
SS IN DD
μA
L
Figure 135. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
V
DD
OSC2
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST7FMC
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
256/309
ST7MC1xx/ST7MC2xx
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
12.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MHz
kΩ
1)
f
Oscillator Frequency
4
16
OSC
R
Feedback resistor
92
F
Recommended load capacitance ver-
sus equivalent serial resistance of the
C
C
L1
L2
See table below
pF
crystal or ceramic resonator (R )
S
2)
Typical Ceramic Resonators
f
CL1
[pF]
CL2
[pF]
OSC
Supplier
3)
(MHz)
Reference
4
8
CSTCR4M00G53-R0
CSTCE8M00G52-R0
CSTCE16M0V53-R0
(15)
(10)
(15)
(15)
(10)
(15)
16
Figure 136. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
R
F
C
L2
ST7FMC
Notes:
1. When PLL is used, please refer to the PLL characteristics chapter and to the “supply, reset and clock management”
description chapter (f min. is 8 Mhz with PLL).
OSC
2. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators,
please consult www.murata.com
3. SMD = [-R0: Plastic tape package (ý =180mm), -B0: Bulk]
LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]
257/309
ST7MC1xx/ST7MC2xx
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
12.5.4 Clock Security System with PLL
Table 88. PLL Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
MHz
MHz
μs
f
PLL input frequency range
7
8
OSC
Output Frequency
Output frequency when the PLL attain lock.
PLL Lock Time (LOCKED = 1)
16
50
2
t
100
Lock
Jitter
Jitter in the output clock
%
CPU clock frequency when VCO is con-
nected to ground (ICD internal clock or
back up oscillator )
f
3
MHz
CPU
Table 89. Clock Detector Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
1)
f
t
t
Detected Minimum Input Frequency
500
KHz
Detect
setup
hold
Time needed to detect OSCIN once CKD is
enabled
3
3
μs
μs
Time needed to detect that OSCIN stops
Notes:
1. Data based on characterization results, not tested in production.
258/309
ST7MC1xx/ST7MC2xx
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Figure 137. PLL And Clock Detector Signal Start Up Sequence
OSCIN
PLLEN
16Mhz
f
= 6 Mhz
1)
VCO
(PLL and CKD)
PLL CLOCK
t lock
LOCK
PLL clock
2)
OSCIN Clock
CKSEL
f
CLK
3)
t
CSSD
CSSIE
hold
t
setup
4)
INTERRUPT
Notes:
1. Lock does not go low without resetting the PLLEN bit.
2. Before setting the CKSEL bit by software in order to switch to the PLL clock, a period of t
elapsed.
must have
lock
3. 2 clock cycles are missing after CKSEL = 1
4. CKSEL bit must be set before enabling the CSS interrupt (CSSIE=1).
259/309
ST7MC1xx/ST7MC2xx
12.6 MEMORY CHARACTERISTICS
12.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
Halt mode (or RESET)
1.6
V
RM
12.6.2 FLASH Memory
DUAL VOLTAGE HDFLASH MEMORY
2)
2)
Symbol
Parameter
Conditions
Read mode
Min
0
Typ
Max
8
Unit
f
Operating frequency
MHz
CPU
Write / Erase mode
4.5V ≤VDD ≤5.5V
1
8
3)
V
Programming voltage
11.4
12.6
V
PP
Read (V =12V)
200
30
µA
mA
μs
PP
4) 5)
I
V
current
PP
PP
Write / Erase
t
Internal V stabilization time
10
25
VPP
RET
PP
T =85°C
40
15
7
A
t
Data retention
T =105°C
years
A
T =125°C
A
N
Write erase cycles
T =25°C
100
cycles
°C
RW
A
T
T
Programming or erasing tempera-
ture range
PROG
-40
85
ERASE
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in hardware registers
DD
(only in Halt mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. V must be applied only during the programming or erasing operation and not permanently for reliability reasons.
PP
4. Data based on simulation results, not tested in production
5. In Write/Erase mode the I supply current consumption is the same as in Run mode (section 12.4.1 on page 252)
DD
260/309
ST7MC1xx/ST7MC2xx
12.7 EMC CHARACTERISTICS
highly dependent on the user application and the
software in particular.
Susceptibility tests are performed on a sample ba-
sis during product characterization.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
12.7.1 Functional EMS (Electro Magnetic
Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
– Critical Data corruption (control registers...)
Prequalification trials:
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to V and V through
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
12.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
Level/
Symbol
Parameter
Conditions
Class
V
f
=5V, T =+25°C,
OSC
DD
A
=8MHz, LVD OFF
4A
2B
Voltage limits to be applied on
any I/O pin to induce a function- Flash/ROM devices
al disturbance
conforms to IEC 1000-4-2
V
FESD
V
f
=5V, T =+25°C,
DD
A
=8MHz, LVD ON
OSC
conforms to IEC 1000-4-2
V
=5V, T =+25°C, f
=8MHz,
OSC
Fast transient voltage burst lim-
Flash devices
DD
A
4A
3B
conforms to IEC 1000-4-4
its to be applied through 100pF
on V and V pins to induce
V
FFTB
V
=5V, T =+25°C, f =8MHz,
DD
DD
DD
A
OSC
ROM devices
a functional disturbance
conforms to IEC 1000-4-4
261/309
ST7MC1xx/ST7MC2xx
EMC CHARACTERISTICS (Cont’d)
12.7.2 EMI (Electromagnetic interference)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
Device/ Package
8/4MHz 16/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
8
8
6
12
9
V
=5V,
DD
dBμV
T =+25°C
A
S
Peak level
Flash/LQFP64
EMI
conforming to
SAE J 1752/3
1
1.5
2.5
-
Notes:
1. Data based on characterization results, not tested in production.
2. Refer to Application Note AN1709 for data on other package types
262/309
ST7MC1xx/ST7MC2xx
EMC CHARACTERISTICS (Cont’d)
12.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
12.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Three models can be simulated: Hu-
man Body Model, Machine Model and Charged
Device Model. This test conforms to the JESD22-
A114A/A115A/C101-A standard.
Based on two different tests (ESD and LU) using
specific measurement methods, the product is
stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
V
Electro-static discharge voltage
(Charged Device Model)
T =+25°C
V
250
A
ESD(CDM)
Notes:
1. Data based on characterization results, not tested in production.
12.7.3.2 Static Latch-Up
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard.
■ LU: two complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
Electrical Sensitivities
1)
Symbol
Parameter
Static latch-up class
Conditions
Class
T =+25°C
A
A
A
A
LU
T =+125°C
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
263/309
ST7MC1xx/ST7MC2xx
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
V
Input low level voltage
0.3xVDD
IL
V
Input high level voltage
CMOS ports
G & H ports
0.7xVDD
IH
2)
2)
V
Schmitt trigger voltage hysteresis
Input low level voltage
1
V
hys
V
0.8
IL
V
V
Input high level voltage
2.8
IH
V
Schmitt trigger voltage hysteresis
Injected Current on an I/O
400
mV
hys
3)
I
+5/-2
25
INJ(PIN)
3
V
V
=5V
mA
ΣI
Total injected current (sum of all I/O
and control pins)
DD
INJ(PIN)
)
I
Input leakage current
SS≤V ≤V
1
L
IN DD
μA
Static current consumption induced
by each floating input pin
I
Floating input mode
200
4)
S
5)
R
Weak pull-up equivalent resistor
V =V
SS
50
1
90
5
250
kΩ
PU
IN
C
I/O pin capacitance
pF
IO
1)
t
Output high to low level fall time
25
25
C =50pF
f(IO)out
r(IO)out
L
ns
1)
Between 10% and 90%
t
Output low to high level rise time
6)
t
External interrupt pulse time
t
CPU
w(IT)in
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
INJ(PIN)
while a negative injection is induced by V <V
.
IN
SS
Refer to section 12.2.2 on page 248 for more details. For PD7, refer to ‘INJECTED CURRENT ON PD7” on page 303.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 138). Static peak current value taken at a fixed V value,
IN
based on design simulation and technology characteristics, not tested in production. This value depends on V and tem-
DD
perature values.
5. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 139). This data is based on characterization results, tested in production at V max.
DD
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
264/309
ST7MC1xx/ST7MC2xx
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 138. Two typical Applications with
unused I/O Pin
Figure 139. Typical I vs. V with V =V
PU DD IN SS
Temperature
(-45 ºC)
Temperature
(25 ºC)
V
ST7MC
DD
90
80
70
60
50
40
30
20
10
0
Temperature
(90 ºC)
Temperature
(130 ºC)
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
10kΩ
ST7MC
3.5
4
4.5
5
5.5
VDD (V)
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
Figure 140. Typical R vs. V with V =V
PU
DD
IN
SS
Temperature
(-45 ºC)
Temperature
(25 ºC)
300
250
200
150
100
50
Temperature
(90 ºC)
Temperature
(130 ºC)
0
3.5
4
4.5
VDD (V)
5
5.5
265/309
ST7MC1xx/ST7MC2xx
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 141)
I
I
I
=+5mA
=+2mA
1.2
IO
IO
IO
0.5
1)
V
OL
=+20mA, T ≤85°C
1.3
1.5
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 142)
T ≥85°C
A
V
I
I
=+8mA
0.6
IO
IO
=-5mA, T ≤85°C
V
V
-1.4
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 143)
DD
DD
2)
-1.6
T ≥85°C
V
A
OH
I
=-2mA
V
-0.7
IO
DD
Figure 141. Typical V at V =5V (standard)
Figure 143. Typical V -V at V =5V
DD OH DD
OL
DD
Vol [V] at Vdd=5V
2.5
Vdd-Voh [V] at Vdd=5V
6
Ta=-40°C
2
Ta=85°C
5
4
3
2
1
Ta=25°C
1.5
Ta=125°C
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
1
0.5
0
0
2
4
6
8
10
-8
-6
-4
Iio [mA]
-2
0
Iio [mA]
Figure 142. Typical V at V =5V (high-sink)
OL
DD
Vol [V] at Vdd=5V
2
Ta=-40°C
Ta=85°C
1.5
Ta=25°C
Ta=125°C
1
0.5
0
0
5
10
15
Iio [mA]
20
25
30
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
.
IO
VDD
266/309
ST7MC1xx/ST7MC2xx
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
V
V
0.3xVDD
IL
V
Input high level voltage
0.7xVDD
IH
2)
V
Schmitt trigger voltage hysteresis
1
V
hys
I
I
=+5mA
=+2mA
0.5
0.2
2
1.2
0.5
IO
IO
3)
V
Output low level voltage
V
=5V
DD
V
OL
I
Driving current on RESET pin
Weak pull-up equivalent resistor
Generated reset pulse duration
mA
kΩ
μs
IO
R
V =V V =5V
SS, DD
50
80
30
150
ON
IN
t
Internal reset sources
w(RSTL)out
4)
t
External reset pulse hold time
2.5
μs
h(RSTL)in
5)
t
Filtered glitch duration
450
ns
g(RSTL)in
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t can be ignored.
h(RSTL)in
5. The reset network protects the device against parasitic resets.
267/309
ST7MC1xx/ST7MC2xx
CONTROL PIN CHARACTERISTICS (Cont’d)
1)2)3)4)
Figure 144. RESET pin protection when LVD is enabled.
V
ST72XXX
DD
Optional
(note 3)
Required
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01μF
1MΩ
WATCHDOG
ILLEGAL
PULSE
GENERATOR
5)
OPCODE
LVD RESET
1)
Figure 145. RESET pin protection when LVD is disabled.
V
ST72XXX
DD
R
ON
Filter
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
0.01μF
WATCHDOG
PULSE
GENERATOR
ILLEGALOPCODE 5)
Required
Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD, illegal opcode or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the V max. level specified in section 12.9.1 on page 267. Otherwise the reset will not be taken into account
IL
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
section 12.2.2 on page 248.
in
INJ(RESET)
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩpull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
Note 5: Please refer to “Illegal Opcode Reset” on page 244 for more details on illegal opcode reset conditions
268/309
ST7MC1xx/ST7MC2xx
CONTROL PIN CHARACTERISTICS (Cont’d)
12.9.2 ICCSEL/V Pin
PP
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
Symbol
Parameter
Conditions
Min
Max
Unit
V
1)
V
Input low level voltage
V
0.2
IL
IH
L
SS
1) 2)
V
I
Input high level voltage
Input leakage current
ICC mode entry
V =V
V
-0.1 12.6
1
DD
μA
IN
SS
3)
Figure 146. Two typical Applications with V Pin
PP
ICCSEL/V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST7MC
ST7MC
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. V is also used to program the flash, refer to the Flash characteristics.
PP
3. When the ICC mode is not required by the application ICCSEL/V pin must be tied to V
.
SS
PP
269/309
ST7MC1xx/ST7MC2xx
12.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
,
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
DD
f
, and T unless otherwise specified.
OSC
A
12.10.1 8-Bit PWM-ART Auto-Reload Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
125
0
ns
CPU
f
ART external clock frequency
PWM repetition rate
f
f
/2
CPU
EXT
MHz
f
0
/2
CPU
PWM
Res
PWM resolution
8
bit
PWM
V
PWM/DAC output step voltage
V
=5V, Res=8-bits
20
mV
OS
DD
12.10.2 16-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
t
t
w(ICAP)in
CPU
2
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
250
0
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
f
/4
MHz
MHz
bit
EXT
CPU
f
0
/4
CPU
PWM
Res
PWM resolution
16
PWM
270/309
ST7MC1xx/ST7MC2xx
12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
=8MHz
f
f
f
/4
CPU
2
CPU
f
f
CPU
SCK
SPI clock frequency
MHz
1/t
Slave
=8MHz
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
1)
4)
t
t
SS setup time
Slave
Slave
(4 x T
) + 50
CPU
su(SS)
1)
t
SS hold time
120
h(SS)
Master
Slave
100
90
w(SCKH)
SCK high and low time
t
w(SCKL)
t
t
Master
Slave
100
100
su(MI)
Data input setup time
Data input hold time
su(SI)
t
t
Master
Slave
100
100
h(MI)
ns
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
Master (after enable edge)
t
0
0
t
120
t
Figure 147. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
4. Depends on f
. For example, if f
=8MHz, then T
= 1/f
=125ns and t
=550ns
su(SS)
CPU
CPU
CPU
CPU
271/309
ST7MC1xx/ST7MC2xx
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 148. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 149. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
INPUT
MSB IN
BIT6 IN
LSB IN
t
t
v(MO)
h(MO)
LSB OUT
See note 2
MSB OUT
BIT6 OUT
See note 2
MOSI
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
272/309
ST7MC1xx/ST7MC2xx
12.12 MOTOR CONTROL CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
12.12.1 Internal Reference Voltage
1)
Symbol
Parameter
Conditions
VR [2:0] = 000
Min
Typ
Max
Unit
V
*0.04
DD
Voltage threshold (VR [2:0] = 000)
Example: V -V
= 5V
= 5V
= 5V
= 5V
= 5V
= 5V
= 5V
0.2
DD
SSA
SSA
SSA
SSA
SSA
SSA
SSA
VR [2:0]= 001
V
*0.12
DD
Voltage threshold (VR [2:0] = 001)
Voltage threshold (VR [2:0] = 010)
Voltage threshold (VR [2:0] = 011)
Voltage threshold (VR [2:0] = 100)
Voltage threshold (VR [2:0] = 101)
Voltage threshold (VR [2:0] = 110)
Example: V -V
0.6
*0.2
DD
VR [2:0] = 010
V
DD
DD
DD
DD
DD
Example: V -V
1.0
DD
VR [2:0]= 011
V
*0.3
V
V
REF
Example: V -V
1.5
DD
VR [2:0] = 100
V
V
V
*0.4
Example: V -V
2.0
DD
VR [2:0]= 101
*0.5
Example: V -V
2.5
DD
VR [2:0] = 110
*0.7
Example: V -V
3.5
2.5
DD
Δ V
/
REF
REF
Tolerance on V
10
%
REF
V
Note:
1. Unless otherwise specified, typical data are based on TA=25°C and V -V =5V. They are given only as design guide-
DD SS
lines and are not tested.
273/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROL CHARACTERISTICS (Cont’d)
12.12.2 Input Stage (comparator + sampling)
Symbol
Parameter
Conditions
Min
Typ
Max
+ 0.1
Unit
Comparator input volt-
age range
V
V
- 0.1
V
V
IN
SSA
DD
1)
V
Comparator offset error
Input offset current
5
40
mV
offset
I
1
μA
offset
Comparator propagation
delay
t
35
3
100
ns
propag
Time waited before sampling when com-
parator is turned ON, i.e. CKE=1 or
2)
t
Start-up filter duration
μs
startup
DAC=1 (with f
= 4MHz)
PERIPH
Time needed to generate a capture in
tachogenerator mode as soon as the MCI
input toggles
4 / f
mtc
Time needed to capture MTIM in MZREG
(BEMF) when sampling during PWM sig-
nal OFF time as soon as MCO becomes
ON
3 / f
1 / f
(see Figure 150)
(see Figure 150)
mtc
Time needed to set/reset the HST bit
when sampling during PWM signal OFF
time as soon as MCO becomes ON
(BEMF)
mtc
Time needed to generate Z event (MTIM
captured in MZREG) as soon as the com-
1 / f
1 / f
+ 3 / f
+ 3 / f
(see Figure 151)
SCF
mtc
parator toggles (when sampling at f
)
SCF
3)
Time needed to generate D event (MTIM
captured in MDREG) as soon as the com-
parator toggles
t
Digital sampling delay
sampling
(see Figure 151)
SCF
mtc
Time needed to set/reset the HST bit
when sampling during PWM signal ON
time after a delay (DS>0) as soon as
MCO becomes ON
Delay programmed in DS bits
(MCONF) +1 / f
mtc
(see Figure 152)
Delay programmed in DS bits
(MCONF)
Time needed to generate Z event (MTIM
in MZREG) when sampling during PWM
signal ON time after a delay (DS>0) as
soon as MCO becomes ON
+ 3 / f
mtc
(see Figure 152)
Delay programmed in DS bits
(MCONF)
Time needed to generate Z event (MTIM
captured in MZREG) when sampling dur-
+ 1 / f
+ 3 / f
ing PWM signal ON time at f
delay (DS>0)
after a
SCF
mtc
SCF
(see Figure 152)
Note:
1. The comparator accuracy is dependent of the environment. The offset value is given for a comparison done with all
digital I/Os stable. Negative injection current on the I/Os close to the inputs may reduce the accuracy. In particular care
must be taken to avoid switching on I/Os close to the inputs when the comparator is in use. This phenomenon is even
more critical when a big external serial resistor is added on the inputs.
2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during start-up.
3. This delay represents the number of clock cycles needed to generate an event as soon as the comparator output
or MCO outputs change.
Example: In tachogenerator mode, this means that capture is performed on the 4th clock cycle after comparator commu-
tation., i.e. there is a variation of (1/f ) or (1 / f
) depending on the case.
SCF
mtc
274/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROL CHARACTERISTICS (Cont’d)
Figure 150. Example 1: Waveforms for Zero-crossing Detection with Sampling at the end of PWM
off-time
Sampling time
f
mtc
MCOx
Comparator
Output
Sample
HST (MCRC)
MTIM
A5
A7
A6
MZREG
XX
A5
Figure 151. Example 2: Waveforms for Zero-crossing Detection with Sampling at f
SCF
Sampling time
f
f
mtc
SCF
Comparator
Output
Sample
HST (MCRC)
MTIM
A5
A6
A7
MZREG
XX
A6
275/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROL CHARACTERISTICS (Cont’d)
Figure 152. Example 3: Waveforms for Zero-crossing Detection with Sampling after a Delay during
PWM On-time
Sampling time
f
mtc
MCOx
Comparator
output
Delay from DS bits
sample
HST (MCRC)
MTIM
A5
A7
A6
MZREG
XX
A6
Figure 153. Example 4: Waveforms for zero-crossing detection with sampling after a delay
at f
SCF
Sampling time
f
f
mtc
SCF
MCOx
comparator
output
Delay from DS bits
sample
HST (MCRC)
MTIM
A5
A6
A7
MZREG
XX
A7
276/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROL CHARACTERISTICS (Cont’d)
Figure 154. Example 5: Waveforms for sensor HST update timing diagram for a newly selected
phase input
Sampling time
f
f
= 2 x fcpu
mtc
SCF
write IS[1:0] = 01
MCIx
d
Comparator
output
sample
HST (MCRC)
IS[1:0] (MPHST)
XX
01
Sampling of sensor input is done at f
for input selection, you have to wait:
, so after writing IS[1:0] in the MPHST register
SCF
1) 1/f
to resynchronize the data and set the MCIx bit
mtc
2) 100ns corresponding to the comparator & multiplexer propagation delay (d)
3) 1/f to sample the comparator output
SCF
4) 1/fmtc to resynchronize the data and set the HST bit
Example with f
SCF[1:0]
= f
= 4MHz :
PERIPH
mtc
00
01
10
11
f
1MHz 500kHz 250kHz 125kHz
SCF
Secure
waiting
time
2µs
3µs
5µs
9µs
to read HST
277/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROL CHARACTERISTICS (Cont’d)
12.12.3 Input Stage (Current Feedback Comparator + Sampling)
Symbol
Parameter
Conditions
Min
- 0.1
Typ
Max
V + 0.1
DD
Unit
V
V
Comparator input voltage range
Comparator offset error
Input offset current
V
IN
SSA
1)
V
5
40
mV
μA
offset
offset
I
1
Comparator propagation
delay
t
35
3
100
ns
1)
propag
Time waited before sampling
when comparator is turned
ON, i.e. CKE=1 or DAC=1
2)
t
Start-up filter duration
μs
startup
(with f
= 4MHz)
PERIPH
Time needed to turn OFF the
MCOs when comparator out-
put rises (CFF=0)
4 / f
(see Figure 155)
(see Figure 155)
MTC
MTC
Time between a comparator
toggle (current loop event)
and bit CL becoming set
(CFF=0)
2 / f
3)
t
Digital sampling delay
sampling
Time needed to turn OFF the
MCOs when comparator out-
put rises (CFF=x)
(1+x) * (4 / f
) + (3 / f
)
)
PERIPH
mtc
(see Figure 156)
Time between a comparator
toggle (current loop event)
and bit CL becoming set
(CFF=x)
(1+x) * (4 / f
) + (1 / f
PERIPH
mtc
(see Figure 156)
Notes:
1. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of
the comparator and must be avoided:
– Negative injection current on the I/Os close to the comparator inputs
– Switching on I/Os close to the comparator inputs
– Negative injection current on not used comparator input (MCCFI0 or MCCFI1)
– Switching with a high dV/dt on not used comparator input (MCCFI0 or MCCFI1)
These phenomena are even more critical when a big external serial resistor is added on the inputs.
2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during start-up.
3.This delay represents the number of clock cycles needed to generate an event as soon as the comparator ouput chang-
es.
Example: When CFF=0 (detection is based on a single detection), MCO outputs are turned OFF at the 4th clock cycle
after comparator commutation, i.e. there is a variation of (1/f ) or (4 / f
) depending on the case.
PERIPH
mtc
278/309
ST7MC1xx/ST7MC2xx
MOTOR CONTROL CHARACTERISTICS (Cont’d)
Figure 155. Example 1: Waveforms For Overcurrent Detection with Current Feedback Filter OFF
Sampling time
f
mtc
Comparator
Output
Sample
CL (MCRC)
MCOx
Figure 156. Example 2: waveforms for overcurrent detection with current feedback filter ON
(CFF=001 => 2 consecutive samples are needed to validate the overcurrent event)
Sampling time
f
f
mtc
/4
PERIPH
Comparator
Output
Sample
CL (MCRC)
MCOx
279/309
ST7MC1xx/ST7MC2xx
12.13 OPERATIONAL AMPLIFIER CHARACTERISTICS
Subject to general operating conditions for f
, and T unless otherwise specified.
A
OSC
o
(T = -40..+125 C, V -V
= 4.5..5.5V unless otherwise specified
A
DD SSA
Parameter
Symbol
Conditions
Min Typ Max
Unit
Resistive Load (max 500µA @
5V)
R
10
kΩ
L
C
Capacitive Load at V
pin
OUT
150
pF
V
L
V
Common Mode Input Range
Input Offset Voltage ( + or - )
V
V
/2
DD
CMIR
SSA
3)
4)
V
After calibration, V =1V
2.5 10
8.5
mV
io
IC
5)
o
with respect to temperature
μV/ C
Input Offset Voltage Drift from
the calibrated Voltage, temper- with respect to common mode input
ature conditions
5)
ΔV
1
mV/V
mV/V
io
5)
with respect to supply
3.1
Common Mode Rejection
HIGHGAIN=0 @ 100kHz
Ratio
CMR
SVR
74
dB
Supply Voltage Rejection
@ 100kHz
2)
50
65
12
dB
V/mV
mV
Ratio
2)
A
Voltage Gain
R =10kΩ
(1.5)
vd
L
High Level Output Saturation
2)
2)
V
R =10kΩ
60 90
30 90
SAT_OH
L
Voltage (V -V
)
DD OUT
Low Level Output Saturation
Voltage
V
R =10kΩ
mV
SAT_OL
L
2)
2)
V
= V / 2, measured at HIGHGAIN=0 1.3
1.5
3
2
4
OAP
DD
0dB gain, feedback resistor
ratio = 10 (20dB inverting con-
figuration)
GBP
Gain Bandwidth Product
Slew Rate while rising
MHz
2)
2)
HIGHGAIN=1 2.6
HIGHGAIN=0
+
2)
SR
1
2
V/μs
V/μs
(A
=1, R =10kΩ, C =150pF, V =1.75V to
L L i
VCL
1)
2.75V)
HIGHGAIN=0
(A =1, R =10kΩ, C =150pF, V =1.75V to
-
2)
6)
SR
Slew Rate while falling
Phase Margin
2.5
7.5
VCL
L
L
i
1)
2.75V)
HIGHGAIN=0
HIGHGAIN=1
73
75
Φm
degrees
Wakeup time for the opamp
from off state
6)
T
0.8
1.6
μs
wakeup
Note:
1. A
= closed loop gain
VCL
2. Data based on characterization results, not tested in production.
3. after offset compensation has been performed.
4. The amplifier accuracy is dependent on the environment. The offset value is given for a measurement done with all
digital I/Os stable. Negative injection current on the I/Os close to the inputs may reduce the accuracy. In particular care
must be taken to avoid switching on I/Os close to the inputs when the opamp is in use. This phenomenon is even more
critical when a big external serial resistor is added on the inputs.
5. The Data provided from simulations (not tested in production) to guide the user when re-calibration is needed.
6. The Data provided from simulations (not tested in production).
280/309
ST7MC1xx/ST7MC2xx
12.14 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
Symbol
Parameter
Analog Reference Voltage
ADC clock frequency
Conditions
Min
Typ
Max
Unit
V
V
f
3
V
DD
AREF
ADC
4
MHz
V
1)
V
Conversion voltage range
V
V
AREF
AIN
SSA
Positive input leakage current for
analog input
1
μA
μA
I
lkg
V <V | I |< 400µA on
Negative input leakage current on
analog pins
IN
SS, IN
5
6
adjacent analog pin
R
C
External input impedance
see
kΩ
AIN
AIN
Figure
157 and
Figure
External capacitor on analog input
pF
f
Variation freq. of analog input signal
Hz
AIN
2)3)4)
158
C
Internal sample and hold capacitor
Conversion time (Sample+Hold)
6
pF
ADC
3.5
μs
f
=8MHz, f
=4MHz,
CPU
ADC
ADSTS bit in MCCBCR
register = 0
- Sample capacitor loading time
- Hold conversion time
4
10
1/f
ADC
t
ADC
Conversion time (Sample+Hold)
6.5
μs
f
=8MHz, f
=4MHz,
CPU
ADC
ADSTS bit in MCCBCR
register = 1
- Sample capacitor loading time
- Hold conversion time
16
10
1/f
ADC
R
Analog Reference Input Resistor
11
kΩ
AREF
3)
4)
Figure 157. R
max. vs f
with C =0pF
Figure 158. Recommended C
& R
AIN
ADC
AIN
AIN AIN values.
45
40
35
30
25
20
15
10
5
1000
Cain 10 nF
Cain 22 nF
Cain 47 nF
2 MHz
1 MHz
100
10
1
0
0.1
0
10
30
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
281/309
ST7MC1xx/ST7MC2xx
10-BIT ADC CHARACTERISTICS (Cont’d)
Figure 159. Typical Application with ADC
V
DD
V
T
0.6V
R
2kΩ(max)
AIN
AINx
10-Bit A/D
Conversion
V
AIN
C
V
0.6V
AIN
T
I
L
C
6pF
ADC
1μA
V
DD
V
AREF
R
AREF
0.1μF
V
SSA
ST7MC
Notes:
1. When V
pins are not available on the pinout, the ADC refer to V
.
SS
SSA
2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
3. C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
PARASITIC
pacitance (3pF). A high C
value will downgrade conversion accuracy. To remedy this, f
should be reduced.
PARASITIC
ADC
4. This graph shows that depending on the input signal variation (f ), C
can be increased for stabilization time and
AIN
AIN
decreased to allow the use of a larger serial resistor (R
.
AIN)
282/309
ST7MC1xx/ST7MC2xx
10-BIT ADC CHARACTERISTICS (Cont’d)
12.14.1 Analog Power Supply and Reference
Pins
digital ground plane via a single point on the
PCB.
Depending on the MCU pin count, the package
– Filter power to the analog power planes. It is rec-
ommended to connect capacitors, with good high
frequency characteristics, between the power
and ground lines, placing 0.1µF and optionally, if
needed 10pF capacitors as close as possible to
the ST7 power supply pins and a 1 to 10µF ca-
pacitor close to the power source (see Figure
160).
may feature separate V
and V
analog
AREF
SSA
power supply pins. These pins supply power to the
A/D converter cell and function as the high and low
reference voltages for the conversion. In some
packages, V
and V
pins are not available
AREF
SSA
(refer to section 2 on page 6). In this case the an-
alog supply and reference pads are internally
bonded to the V and V pins.
DD
SS
– The analog and digital power supplies should be
connected in a star network. Do not use a resis-
Separation of the digital and analog power pins al-
low board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines (see Section
12.14.2 General PCB Design Guidelines).
tor, as V
is used as a reference voltage by
AREF
the A/D converter and any resistance would
cause a voltage drop and a loss of accuracy.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
12.14.2 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
– Use separate digital and analog planes. The an-
alog ground plane should be connected to the
Figure 160. Power Supply Filtering
ST7MC
10pF
(if needed)
1 to 10μF
0.1μF
V
V
SS
ST7
DIGITAL NOISE
FILTERING
DD
V
DD
POWER
SUPPLY
SOURCE
10pF
V
V
0.1μF
(if needed)
AREF
EXTERNAL
NOISE
FILTERING
SSA
283/309
ST7MC1xx/ST7MC2xx
10-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with V =5.0V
DD
2)
Symbol
|E |
Parameter
Conditions
Typ
4
Max
Unit
1)
Total unadjusted error
T
1)
|E |
Offset error
2.5
2
4
4
O
V
f
=3.0V to 5.0V, f
=8MHz,
CPU
1)
AREF
|E |
Gain Error
LSB
G
=4MHz, R <10kΩ
ADC
AIN
1)
|E |
Differential linearity error
2
4.5
4.5
D
1)
|E |
Integral linearity error
2
L
Notes:
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion
being performed on another analog input. The effect of negative injection current on analog pins is specified in Section
12.14.
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 12.8 does not affect the ADC
INJ(PIN)
INJ(PIN)
2. Data based on characterization results, monitored in production to guarantee 99.73% within max value from -40°C
to 125°C ( 3σ distribution limits).
Figure 161. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
1022
1021
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
SSA
AREF
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 4 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
2. Data based on characterization results with T =25°C.
A
3. Data based on characterization results over the whole temperature range, monitored in production.
284/309
ST7MC1xx/ST7MC2xx
13 PACKAGE CHARACTERISTICS
In order to meet environmental requirements, ST
offers these devices in different grades of ECO-
PACK® packages, depending on their level of en-
vironmental compliance. ECOPACK® specifica-
tions, grade definitions and product status are
available at: www.st.com. ECOPACK® is an ST
trademark.
13.1 PACKAGE MECHANICAL DATA
Figure 162. 80-Pin Low Profile Quad Flat Package
1)
mm
inches
Typ
Dim.
A
Min Typ Max Min
1.60
Max
0.0630
0.0059
D
D1
A
A2
A1 0.05
0.15 0.0020
A1
b
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b
C
0.22 0.32 0.38 0.0087 0.0126 0.0150
0.09 0.20 0.0035 0.0079
D
16.00
14.00
16.00
14.00
0.65
0.6299
0.5512
0.6299
0.5512
0.0256
3.5°
e
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
c
L
0.45 0.60 0.75 0.0177 0.0236 0.0295
1.00 0.0394
Number of Pins
80
L1
L
h
L1
N
285/309
ST7MC1xx/ST7MC2xx
PACKAGE CHARACTERISTICS (Cont’d)
Figure 163. 64-Pin Low Profile Quad Flat Package (14x14)
1)
A
A2
mm
inches
Typ
D
D1
Dim.
A
Min Typ Max Min
1.60
Max
0.0630
0.0059
A1
b
A1 0.05
0.15 0.0020
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b
c
0.30 0.37 0.45 0.0118 0.0146 0.0177
0.09 0.20 0.0035 0.0079
D
16.00
14.00
16.00
14.00
0.80
0.6299
0.5512
0.6299
0.5512
0.0315
3.5°
e
D1
E
E
E1
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.0177 0.0236 0.0295
1.00 0.0394
Number of Pins
64
L
L1
L1
c
N
h
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.
Figure 164. 44-Pin Low Profile Quad Flat Package
1)
mm
inches
Typ
Dim.
A
A
D
D1
Min Typ Max Min
Max
A2
1.60
0.0630
0.0059
A1
b
A1 0.05
0.15 0.0020
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b
C
0.30 0.37 0.45 0.0118 0.0146 0.0177
0.09 0.20 0.0035 0.0079
D
12.00
10.00
12.00
10.00
0.80
0.4724
0.3937
0.4724
0.3937
0.0315
3.5°
e
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.0177 0.0236 0.0295
1.00 0.0394
Number of Pins
44
c
L1
L1
L
h
N
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.
5PACKAGE CHARACTERISTICS (Cont’d)
6
286/309
ST7MC1xx/ST7MC2xx
PACKAGE CHARACTERISTICS (Cont’d)
Figure 165. 32-Pin Low Profile Quad Flat Package
1)
mm
inches
Typ
Dim.
A
Min Typ Max Min
Max
D
A
1.60
0.0630
0.0059
D1
A2
A1 0.05
0.15 0.0020
A1
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b
C
0.30 0.37 0.45 0.0118 0.0146 0.0177
0.09 0.20 0.0035 0.0079
e
b
D
9.00
7.00
9.00
7.00
0.80
3.5°
0.3543
0.2756
0.3543
0.2756
0.0315
3.5°
E
E1
D1
E
E1
e
c
L1
θ
0°
7°
0°
7°
L
L
0.45 0.60 0.75 0.0177 0.0236 0.0295
1.00 0.0394
Number of Pins
32
h
L1
N
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.
Figure 166. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
1)
mm
inches
Typ
Dim.
Min Typ Max Min
Max
A
6.35 0.2500
E
A1 0.38
0.0150
A
A2
A1
A2 3.18
4.95 0.1252
0.1949
C
b
0.41
0.89
0.0161
0.0350
E1
eA
eB
E
b2
b
e
b2
D
C
D
E
0.20
0.38 0.0079
53.21 1.9799
0.0150
2.0949
0.015
50.29
GAGE PLANE
15.01
0.5909
E1 12.32
14.73 0.4850
0.5799
e
1.78
0.0701
0.6000
eA
eB
15.24
eB
17.78
0.7000
0.2000
L
2.92
5.08 0.1150
Number of Pins
N
56
Note 1. Values in inches are converted from mm
and rounded to 4 decimal digits.
287/309
ST7MC1xx/ST7MC2xx
PACKAGE CHARACTERISTICS (Cont’d)
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
LQFP80 14x14
55
55
68
80
63
45
LQFP64 14x14
LQFP44 10x10
LQFP32 7x7
SDIP32 400mil
SDIP56 600mil
R
°C/W
thJA
1)
T
Maximum junction temperature
150
500
°C
Jmax
2)
P
Power dissipation
mW
Dmax
Notes:
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula P = (T -T ) / R .
thJA
D
J
A
The power dissipation of an application can be defined by the user with the formula: P =P +P
D
INT
PORT
where P
is the chip internal power (I x V ) and P
is the port power dissipation depending on
PORT
INT
DD
DD
the ports used in the application.
288/309
ST7MC1xx/ST7MC2xx
13.3 SOLDERING INFORMATION
In accordance with the RoHS European directive,
all STMicroelectronics packages have been con-
Backward and forward compatibility:
The main difference between Pb and Pb-free sol-
dering process is the temperature range.
verted to lead-free technology, named ECO-
TM
PACK
.
TM
– ECOPACK LQFP, SDIP and SO packages
TM
■ ECOPACK packages are qualified according
to the JEDEC STD-020C compliant soldering
profile.
are fully compatible with Lead (Pb) containing
soldering process (see application note AN2034)
– LQFP, SDIP and SO Pb-packages are compati-
ble with Lead-free soldering process, neverthe-
less it's the customer's duty to verify that the Pb-
packages maximum temperature (mentioned on
the Inner box label) is compatible with their Lead-
free soldering temperature.
■ Detailed information on the STMicroelectronics
TM
ECOPACK transition program is available on
www.st.com/stonline/leadfree/, with specific
technical Application notes covering the main
technical aspects related to lead-free
conversion (AN2033, AN2034, AN2035,
AN2036).
Table 90. Soldering Compatibility (wave and reflow soldering process)
Package
SDIP & PDIP
LQFP and SO
Plating material devices
Sn (pure Tin)
NiPdAu (Nickel-palladium-Gold)
Pb solder paste
Pb-free solder paste
Yes
Yes
Yes *
Yes *
* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label)
is compatible with their Lead-free soldering process.
289/309
ST7MC1xx/ST7MC2xx
14 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in ROM
versions and in user programmable versions
(FLASH) as well as in factory coded versions
(FASTROM). ST7MC are ROM devices. ST7PMC
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are programmed
Flash devices.
ST7FMC Flash devices are shipped to customers
with a default content (FFh), while ROM/FAS-
TROM factory coded parts contain the code sup-
plied by the customer. This implies that Flash de-
vices have to be configured by the customer using
the Option Bytes while the ROM devices are facto-
ry-configured.
14.1 FLASH OPTION BYTES
STATIC OPTION BYTE 0
STATIC OPTION BYTE 1
7
0
7
0
WDG
VD
PKG
MCO
1
1
0
1
0
1
2
1
1
Default
value
1
1
1
1
1
1
1
1
1
1
1
1
The option bytes allow the hardware configuration
of the microcontroller to be selected. They have no
address in the memory map and can be accessed
only in programming mode (for example using a
standard ST7 programming tool). The default con-
tent of the FLASH is fixed to FFh. This means that
all the options have “1” as their default value.
Selected Low Voltage Detector
VD1
VD0
1
1
0
1
LVD and AVD Off
OPT2 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
Halt mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
OPTION BYTE 0
OPT7= WDG HALT Watchdog and Halt mode
This option bit determines if a RESET is generated
when entering Halt mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
Note: When the PLL clock is selected (CKSEL=0),
the reset clock cycle selection is forced to 4096
CPU cycles.
OPT1= DIV2 Divider by 2
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: DIV2 divider disabled with OSCIN = 8MHz
0: DIV2 divider enabled (in order to have 8 MHz re-
quired for the PLL with OSCIN =16 Mhz))
1: Software (watchdog to be enabled by software)
OPT0= FMP_R Flash memory read-out protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
This protection is based on a read/write protection
of the memory in test modes and ICP mode. Eras-
ing the option bytes when the FMP_R option is se-
lected causes the whole user memory to be
erased first and the device can be reprogrammed.
Refer to the ST7 Flash Programming Reference
Manual and section 4.3.1 on page 22 for more de-
tails.
OPT5 = CKSEL Clock Source Selection.
1)
0: PLL clock selected
1: Oscillator clock selected
Note 1: Even if PLL clock is selected, a clock signal must
always be present (refer to Figure 13. on page 28)
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD).
Selected Low Voltage Detector
VD1
VD0
LVD and AVD On
0
0
0
1
0: Read-out protection enabled
LVD On and AVD Off
1: Read-out protection disabled
290/309
ST7MC1xx/ST7MC2xx
ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPTION BYTE 1
OPT7:5= PKG[2:0] package selection
These option bits are used to select the device
package.
OPT1:0 = MCO Motor Control Output Options
MCO port under reset.
Motor Control Output
bit 1
bit 0
Selected Package
LQFP32 / SDIP32
LQFP44
PKG2
PKG1
PKG0
HiZ
Low
High
HiZ
0
0
1
1
0
1
0
1
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
SDIP 56
LQFP64
LQFP80
OPT4:2= Reserved
291/309
ST7MC1xx/ST7MC2xx
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
The FASTROM or ROM contents are to be sent on
diskette, or by electronic means, with the hexadec-
imal file in .S19 format generated by the develop-
ment tool. All unused bytes must be set to FFh.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended.
Refer to Application Note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 167. Ordering information scheme
Example:
ST7
F
MC1
K
2
T
6
Family
ST7 microcontroller family
Memory type
F: Flash
P: FASTROM
Sub-family
MC1 or MC2
No. of pins
K = 32
S = 44
N = 56
R = 64
M = 80
Memory size
2 = 8K
4 = 16K
6 = 32K
7 = 48K
9 = 60K
Package
T = LQFP
B = Plastic DIP
Temperature range
6 = -40 °C to 85 °C
3 = -40 °C to 125 °C
For a list of available options (e.g. memory size, package) and orderable part numbers or for further information
on any aspect of this device, please contact the ST Sales Office nearest to you.
292/309
ST7MC1xx/ST7MC2xx
ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
ST7MC MICROCONTROLLER OPTION LIST
(Last update: September 2008)
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM or FASTROM Code* : . . . . . . . . . . . .
*The ROM or FASTROM code name is assigned by STMicroelectronics.
ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device type/memory size/package (check only one option):
--------------------
-------------------- ------------------- --------------------
---------------
-------------------
|
|
|
|
|
|
|
|
|
|
|
|
-
16K
8K
32K
48K
60K
ROM
---------------
-------------------
--------------------
-------------------- ------------------- --------------------
LQFP32: |
LQFP44: |
[ ]
|
|
|
|
|
|
|
|
|
|
[ ]
-------------------- ------------------- --------------------
--------------------
---------------
-------------------
|
|
|
|
|
|
|
|
|
|
|
|
-
48K
8K
16K
32K
60K
FASTROM
---------------
-------------------
-------------------- ------------------- --------------------
--------------------
LQFP32: |
LQFP44: |
LQFP64: |
LQFP80: |
[ ]
|
|
|
|
[ ]
[ ]
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
[ ]
[ ]
[ ]
[ ]
Conditioning (check only one option):
[ ] Tape & Reel
Special Marking
[ ] Tray
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)
[ ] - 40°C to + 125°C
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Temperature range
[ ] - 40°C to + 85°C
MCO (Motor Control Output
state under reset)
DIV2
[ ] Hiz
[ ] Disabled
[ ] Oscillator clock
[ ] Software Activation
[ ] Reset
[ ] Disabled
[ ] Low
[ ] High
[ ] Enabled
[ ] PLL clock
[ ] Hardware Activation
[ ] No reset
CKSEL
Watchdog Selection
Halt when Watchdog on
Readout Protection
LVD Reset
[ ] Enabled
[ ] Enabled
[ ] Disabled
AVD Interrupt (if LVD enabled) [ ] Disabled
Reset Delay [ ] 256 Cycles
[ ] Enabled
[ ] 4096 Cycles
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
Date
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please download the latest version of this option list from:
http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list
293/309
ST7MC1xx/ST7MC2xx
ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.3 DEVELOPMENT TOOLS
Development tools for the ST7 microcontrollers in-
clude a complete range of hardware systems and
software tools from STMicroelectronics and third-
party tool suppliers. The range of tools includes
solutions to help you evaluate microcontroller pe-
ripherals, develop and debug your application, and
program your microcontrollers.
The range of hardware tools includes full-featured
ST7-EMU2B series emulators and the low-cost
RLink in-circuit debugger/programmer. These
tools are supported by the ST7 Toolset from ST-
Microelectronics, which includes the STVD7 inte-
grated development environment (IDE) with high-
level language debugger, editor, project manager
and integrated programming interface.
14.3.1 Starter kits
14.3.3 Programming tools
ST offers complete, affordable starter kits and
full-featured that allow you to evaluate microcon-
troller features and quickly start developing ST7
applications. Starter kits are complete hardware/
software tool packages that include features and
samples to to help you quickly start developing
your application.
During the development cycle, the ST7-EMU3 se-
ries emulators and the RLink provide in-circuit
programming capability for programming the Flash
microcontroller on your application board.
ST also provides a low-cost dedicated in-circuit
programmer, the ST7-STICK, as well as ST7
Socket Boards which provide all the sockets re-
quired for programming any of the devices in a
specific ST7 sub-family on a platform that can be
used with any tool with in-circuit programming ca-
pability for ST7.
14.3.2 Development and debugging tools
Application development for ST7 is supported by
fully optimizing C Compilers and the ST7 Assem-
bler-Linker toolchain, which are all seamlessly in-
tegrated in the ST7 integrated development envi-
ronments in order to facilitate the debugging and
fine-tuning of your application. The Cosmic C
Compiler is available in a free version that outputs
up to 16K of code.
For production programming of ST7 devices, ST’s
third-party tool partners also provide a complete
range of gang and automated programming solu-
tions, which are ready to integrate into your pro-
duction environment.
14.3.4 Order codes for ST7MC development tools
Table 91. Development tool order codes for the ST7MC family
MCU
Starter kit
Emulator
Programming tool
1)2)
ST7MC1
ST7MC2
ST7-STICK
ST7MC-KIT/BLDC
ST7MDT50-EMU3
3)
STX-RLINK
1. Add suffix /EU, /UK or /US for the power supply for your region
2. Parallel port connection to PC
3. RLink with ST7 tool set
For additional ordering codes for spare parts and accessories, refer to the online product selector at
www.st.com/mcu.
294/309
ST7MC1xx/ST7MC2xx
ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.3.5 PACKAGE/SOCKET FOOTPRINT PROPOSAL
Table 92. Suggested List of Socket Types
Package / Probe
LQFP64 14x14
Socket Reference
3303262
Emulator Adapter
3303351
CAB
CAB
LQFP80 14x14
LQFP32 7x7
LQFP44 10x10
SDIP32
YAMAICHI
IRONWOOD
YAMAICHI
Standard
Standard
IC149-080-*51-*5
SF-QFE32SA-L-01
IC149-044-*52-*5
YAMAICHI
ICP-080-7
IRONWOOD
YAMAICHI
Standard
SK-UGA06/32A-01
ICP-044-5
SDIP56
Standard
295/309
ST7MC1xx/ST7MC2xx
14.4 ST7 APPLICATION NOTES
Table 93. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658
AN1720
AN1755
AN1756
SERIAL NUMBERING IMPLEMENTATION
MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN-
PUT VOLTAGES
AN1812
EXAMPLE DRIVERS
SCI COMMUNICATION BETWEEN ST7 AND PC
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
EMULATED 16-BIT SLAVE SPI
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
SOFTWARE UART USING 12-BIT ART
296/309
ST7MC1xx/ST7MC2xx
Table 93. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN1947
ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
GENERAL PURPOSE
AN1476
AN1526
AN1709
AN1752
LOW COST POWER SUPPLY FOR HOME APPLIANCES
ST7FLITE0 QUICK REFERENCE NOTE
EMC DESIGN FOR ST MICROCONTROLLERS
ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1103
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
AN1604
AN2200
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
HOW TO USE ST7MDT1-TRAIN WITH ST72F264
GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB
PRODUCT OPTIMIZATION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
TOR
AN1530
AN1605
AN1636
AN1828
AN1946
AN1953
AN1971
USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
PFC FOR ST7MC STARTER KIT
ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN1039
ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
ST7 MATH UTILITY ROUTINES
297/309
ST7MC1xx/ST7MC2xx
Table 93. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN1071
AN1106
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1477
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
USING THE ST72521 EMULATOR TO DEBUG AN ST72324 TARGET APPLICATION
EMULATED DATA EEPROM WITH XFLASH MEMORY
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
ST7 CUSTOMER ROM CODE RELEASE INFORMATION
DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711
AN1827
AN2009
AN2030
SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
BACK EMF DETECTION DURING PWM ON TIME BY ST7MC
298/309
ST7MC1xx/ST7MC2xx
15 IMPORTANT NOTES
15.1 FLASH/FASTROM DEVICES ONLY
The following table gives the limitations and the
impacted devices.
The behaviors described in the following sections
are present on Rev A, B or C ST7FMC and
ST7PMC devices only.
They are identifiable:
- on the device package, by the last letter of the
Trace Code marked on the device package.
- on the box, by the last 3 digits of the Internal
Sales Type printed in the box label.
See also Figure 170. on page 306
Table 94. Device Identification
Limitations
Device
Type
Trace Code marked on device /
Internal Sales Type on box label
Flash
“xxxxxxxxxB”/
X
X
X
X
X
X
X
X
X
X
X
X
❍
❍
❍
❍
X
❍
❍
❍
❍
X
Devices ST7FMCxxxxx$XY
FASTROM
Devices
“xxxxxxxxxB” /
ST7PMCxxxxx$XY
Flash
“xxxxxxxxxC”/
X
X
❍
❍
❍
❍
Devices ST7FMCxxxxx$XY
FASTROM
Devices
“xxxxxxxxxC” /
ST7PMCxxxxx$XY
X
X
Flash
“xxxxxxxxxA”/
❍
❍
❍
❍
Devices ST7FMCxxxxx$XY
FASTROM
Devices
“xxxxxxxxxA” /
ST7PMCxxxxx$XY
X
X
Legend: Limitation present = X ; Limitation not present = ❍.
299/309
ST7MC1xx/ST7MC2xx
IMPORTANT NOTES (Cont’d)
15.2 CLEARING ACTIVE INTERRUPTS OUTSIDE
INTERRUPT ROUTINE
15.3 TIMD SET SIMULTANEOUSLY WITH OC
INTERRUPT
When an active interrupt request occurs at the
same time as the related flag or interrupt mask is
being cleared, the CC register may be corrupted.
If the 16-bit timer is disabled at the same time as
the output compare event occurs then the output
compare flag gets locked and cannot be cleared
before the timer is enabled again.
Concurrent interrupt context
15.3.1 Impact on the application
The symptom does not occur when the interrupts
are handled normally, i.e. when:
If the output compare interrupt is enabled, then the
output compare flag cannot be cleared in the timer
interrupt routine. Consequently the interrupt serv-
ice routine is called repeatedly and the application
gets stuck which causes the watchdog reset if en-
abled by the application.
- The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
- The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine
- The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
15.3.2 Workaround
Disable the timer interrupt before disabling the tim-
er. While enabling, first enable the timer, then en-
able the timer interrupts.
Perform the following to disable the timer
– TACR1 or TBCR1 = 0x00h; // Disable the com-
pare interrupt.
Perform SIM and RIM operation before and after
resetting an active interrupt request
– TACSR | or TBCSR |= 0x40; // Disable the timer.
– Perform the following to enable the timer again
Ex:
SIM
– TACSR & or TBCSR & = ~0x40; // Enable the
timer.
reset flag or interrupt mask
RIM
– TACR1 or TBCR1 = 0x40; // Enable the compare
interrupt.
15.4 LINSCI LIMITATIONS
Nested interrupt context
15.4.1 LINSCI wrong break duration
SCI Mode
The symptom does not occur when the interrupts
are handled normally, i.e. when:
- The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine with high-
er or identical priority level
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
- The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Occurrence
PUSH CC
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
SIM
reset flag or interrupt mask
POP CC
300/309
ST7MC1xx/ST7MC2xx
IMPORTANT NOTES (Cont’d)
Workaround
- the synch field (10 bits),
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
- the identifier field (10 bits).
Every LIN frame starts with a break character.
Adding an idle character increases the length of
each header by 10 bits. When the problem occurs,
the header length is increased by 11 bits and be-
comes ((14+11)+10+10+1)=45 bits.
To conclude, the problem is not always critical for
LIN communication if the software keeps the time
between the sync field and the ID smaller than 4
bits, i.e. 208us at 19200 baud.
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
The workaround is the same as for SCI mode but
considering the low probability of occurrence (1%),
it may be baetter to keep the break generation se-
quence as it is.
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
15.4.2 Header Time-out does not prevent wake-
up from mute Mode
LIN mode
If the LINE bit in the SCICR3 is set and the M bit in
the SCICR1 register is reset, the LINSCI is in LIN
master mode. A single break character is sent by
setting and resetting the SBK bit in the SCICR2
register. In some cases, the break character may
have a longer duration than expected:
Normally, when LINSCI is configured in LIN slave
mode, if a header time-out occurs during a LIN
header reception (i.e. header length > 57 bits), the
LIN Header Error bit (LHE) is set, an interrupt oc-
curs to inform the application but the LINSCI
should stay in mute mode, waiting for the next
header reception.
- 24 bits instead of 13 bits
Occurrence
Problem Description
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
The LINSCI sampling period is Tbit / 16. If a LIN
Header time-out occurs between the 9th and the
15th sample of the Identifier Field Stop Bit (refer to
Figure 168), the LINSCI wakes up from mute
mode. Nevertheless, LHE is set and LIN Header
Detection Flag (LHDF) is kept cleared.
Analysis
In addition, if LHE is reset by software before this
15th sample (by accessing the SCISR register and
reading the SCIDR register in the LINSCI interrupt
routine), the LINSCI will generate another LINSCI
interrupt (due to the RDRF flag setting).
The LIN protocol specifies a minimum of 13 bits for
the break duration, but there is no maximum value.
Nevertheless, the maximum length of the header
is specified as (14+10+10+1)x1.4=49 bits. This is
composed of:
- the synch break field (14 bits),
301/309
ST7MC1xx/ST7MC2xx
Figure 168. Header Reception Event Sequence
LIN Synch
Break
LIN Synch
Field
Identifier
Field
T
HEADER
ID field STOP bit
Critical
Window
Active mode is set
(RWU is cleared)
RDRF flag is set
302/309
ST7MC1xx/ST7MC2xx
IMPORTANT NOTES (Cont’d)
Impact on application
Workaround
Software may execute the interrupt routine twice
after header reception.
The problem can be detected in the LINSCI inter-
rupt routine. In case of timeout error (LHE is set
and LHLR is loaded with 00h), the software can
check the RWU bit in the SCICR2 register. If RWU
is cleared, it can be set by software. Refer to Fig-
ure 169. Workaround is shown in bold characters.
Moreover, in reception mode, as the receiver is no
longer in mute mode, an interrupt will be generat-
ed on each data byte reception.
Figure 169. LINSCI Interrupt routine
@interrupt void LINSCI_IT ( void ) /* LINSCI interrupt routine */
{
/* clear flags */
SCISR_buffer = SCISR;
SCIDR_buffer = SCIDR;
if ( SCISR_buffer & LHE )/* header error ? */
{
if (!LHLR)/* header time-out? */
{
if ( !(SCICR2 & RWU) )/* active mode ? */
{
_asm("sim");/* disable interrupts */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
_asm("rim");/* enable interrupts */
}
}
}
}
Example using Cosmic compiler syntax
15.5 MISSING DETECTION OF BLDC “Z
EVENT”
15.6 INJECTED CURRENT ON PD7
On rev.B silicon, the parameter Iinj(pin), injected
current on I/O pins (see section 12.8.1 on page
264), is limited at 0 (instead of -2mA) for the pin
PD7. This limitation is no longer present on rev.C
and A silicon and all I/O pins have the max values
+5/-2 mA.
For a BLDC drive, the Dead Time generator is en-
abled through the MDTG register (PCN=0 and
DTE=1). If the duty cycle of the PWM signal gen-
erated to drive the motor is lower than the pro-
grammed deadtime, the Z event sampling will be
missing.
15.7 RESET VALUE OF UNAVAILABLE PINS
Workaround
On A silicon versions, some ports (Ports A, C and
E) have less than 8 pins. The bits associated to the
unavailable pins must always be kept at reset
state.
The complementary PWM must be disabled by re-
setting the DTE bit in the MDTG register (see page
221).
As the current in the motor is very low in this case,
the MOSFET body diode can be used.
303/309
ST7MC1xx/ST7MC2xx
15.8
THRESHOLDS
MAXIMUM
VALUES
OF
AVD
Case 1: Writing to PxOR or PxDDR with Global In-
terrupts Enabled:
LD A,#01
On rev. A silicon versions, the max. values of AVD
thresholds are not tested in production.
LD sema,A
LD A,PFDR
AND A,#02
; set the semaphore to '1'
15.9 EXTERNAL INTERRUPT MISSED
LD X,A
; store the level before writing to
To avoid any risk if generating a parasitic interrupt,
the edge detector is automatically disabled for one
clock cycle during an access to either DDR and
OR. Any input signal edge during this period will
not be detected and will not generate an interrupt.
PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
This case can typically occur if the application re-
freshes the port configuration registers at intervals
during runtime.
LD PFOR,A ; Write to PFOR
LD A,PFDR
Workaround
AND A,#02
The workaround is based on software checking
the level on the interrupt pin before and after writ-
ing to the PxOR or PxDDR registers. If there is a
level change (depending on the sensitivity pro-
grammed for this pin) the interrupt routine is in-
voked using the call instruction with three extra
PUSH instructions before executing the interrupt
routine (this is to make the call compatible with the
IRET instruction at the end of the interrupt service
routine).
LD Y,A
; store the level after writing to
PxOR/PxDDR
LD A,X
; check for falling edge
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema
edge is detected
; check the semaphore status if
But detection of the level change does not make
sure that edge occurs during the critical 1 cycle du-
ration and the interrupt has been missed. This may
lead to occurrence of same interrupt twice (one
hardware and another with software call).
CP A,#01
jrne OUT
call call_routine; call the interrupt routine
To avoid this, a semaphore is set to '1' before
checking the level change. The semaphore is
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore
status is checked and if it is '1' this means that the
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction.
OUT:LD A,#00
LD sema,A
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
There is another possible case i.e. if writing to
PxOR or PxDDR is done with global interrupts dis-
abled (interrupt mask bit set). In this case, the
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is
done after the global interrupts are enabled (inter-
rupt mask bit reset) and by checking the status of
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in-
voked with the call instruction.
.ext1_rt
; entry to interrupt routine
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
SIM
; set the interrupt mask
To implement the workaround, the following soft-
ware sequence is to be followed for writing into the
PxOR/PxDDR registers. The example is for for
Port PF1 with falling edge interrupt sensitivity. The
software sequence is given for both cases (global
interrupt disabled/enabled).
LD A,PFDR
AND A,#$02
LD X,A
; store the level before writing to
PxOR/PxDDR
LD A,#$90
304/309
ST7MC1xx/ST7MC2xx
LD PFDDR,A; Write into PFDDR
LD A,#$ff
CP A,#$01
jrne OUT
LD PFOR,A
LD A,PFDR
AND A,#$02
; Write to PFOR
call call_routine; call the interrupt routine
RIM
OUT:
RIM
LD Y,A
PxDDR
; store the level after writing to PxOR/
; check for falling edge
JP while_loop
.call_routine ; entry to call_routine
PUSH A
LD A,X
cp A,#$02
jrne OUT
TNZ Y
PUSH X
PUSH CC
.ext1_rt
; entry to interrupt routine
jrne OUT
LD A,#$01
LD A,#$00
LD sema,A
IRET
LD sema,A ; set the semaphore to '1' if edge is
detected
RIM
; reset the interrupt mask
LD A,sema ; check the semaphore status
305/309
ST7MC1xx/ST7MC2xx
IMPORTANT NOTES (Cont’d)
Figure 170. Revision Marking on Box Label and Device Marking
TYPE xxxx
Internalxxx$xx
Trace Code
LAST 2 DIGITS AFTER $
IN INTERNAL SALES TYPE
ON BOX LABEL
INDICATE SILICON REV.
LAST LETTER OF TRACE CODE
ON DEVICE INDICATES
SILICON REV.
306/309
ST7MC1xx/ST7MC2xx
16 REVISION HISTORY
Table 95. Revision History
Date
Revision
Description of Changes
Added one sales type (ST7FMC1K4T6)
Changed port description for MCES in Table 1, “ST7MC Device Pin Description,” on
page 12 and added note 3
Changed register addresses in Table 15, “PWM Auto-Reload Timer Register Map and Re-
set Values,” on page 74
Changed title of Figure 123 on page 227 and Figure 124
Changed Table 36 on page 166
Changed MTIM timer value to 100h in section “b” on page 171
Changed text above Figure 98. on page 177 (15kHz instead of 20kHz and replaced f
April-2005
6
=
CPU
4MHz by f
= 4MHz) and changed Figure 98 (15kHz instead of 20kHz)
MTC
Changed Figure 107. on page 188
Changed Figure 108. on page 189
Changed Figure 115 on page 197
Changed description of OO[5:0] bits in the MPHST register (section 10.6.13 on page 206)
Changed min and max values for R in section 12.9.1 on page 266
ON
Changed Figure 144 and Figure 145. on page 267 and notes
Added ST7FMC1K2T3 and ST7FMC1K6TC sales types (updated device summary on 1st
page and “Supported part numbers” on page 292)
Changed V and V in section 12.3.2 on page 250
IT-
IT+
Removed note 1 in section 12.4.4 on page 253
Changed I in section 12.8.1 on page 263 and removed note 1 for V and V
IH
July-2005
7
INJ(PIN)
IL
Changed R max in section 12.9.1 on page 266 and removed note 1 for V , V and R
ON
IL
IH
ON
Removed subsection in Important Notes Section 14 : “Op-Amp input offset voltage”
Notes for Table in Section 12.13 updated, removing link to ”Op-Amp input offset voltage”
Flash memory data retention changed (first page and Section 12.6.2)
Removed references to true open drain I/Os.Updated Table 1 on page 12: replaced
6)
MCZEM5) by MCZEM , and replaced Port H0, Port H1, Port H2 and Port H3 respectively
by Port H4, Port H5, Port H6 and Port H7 (in the rows corresponding to PH4, PH5, PH6 and
PH7 in the “Pin name column”
Updated note 8 in Table 1 on page 12
Added section 5 on page 24
Added note to section 6.1 on page 28
Added note to section 6.2.1 on page 29 and updated Figure 15. on page 29
Changed section 10.5.5.2 on page 110 (when a character transmission is complete, etc.)
Modified Table 34 on page 161 (window and event filters column)
Replaced MISR register by MIMR register in the 3rd paragraph of “Switched Mode” on page
168
Removed caution and added notes 3 and 4 below Figure 93. on page 170 in section 10.6.7.2
on page 170
Nov-2005
8
In section 10.6.6.11 on page 163 and in Figure 94 on page 172, replace “TES[1:0] = 00,01
or 10” by “TES[1:0] = 00,10 or 11”
Changed V
min value in section 12.3.3 on page 250
IT+(AVD)
Changed section 12.5.3 on page 256
Changed I parameter description and note 4 in section 12.8.1 on page 263
s
Updated note 3 in section 12.8.1 on page 263
Added note to Figure 138. on page 264
Removed 32K ROM versions: changed “Supported part numbers” on page 290 and “ST7MC
MICROCONTROLLER OPTION LIST” on page 291
Changed “FLASH/FASTROM DEVICES ONLY” on page 297 (added table) and added “RE-
SET VALUE OF UNAVAILABLE PINS” on page 300
Modified section 15.5 on page 300
Added Important Notes subsection section 15.5 on page 300: “Injected Current On PD7”
307/309
ST7MC1xx/ST7MC2xx
Table 95. Revision History
Date
Revision
Description of Changes
Added two sales types: ST7FMC2S4T3 and ST7FMC2S6T3
Changed QFP package name: TQFP replaced by LQFP
Changed “Master Mode Operation” on page 98: added important note
Changed “Interrupt Mapping” on page 43: modified interrupt n°13
Added note to V in Figure 13. on page 27
DD
Modified Figure 24. on page 45.
Changed section 7.7 on page 46 (IPB, IS3[1:0] and IPA descriptions)
Changed Table 36 on page 166 and added notes
Changed SWA bit description after Table 58 on page 210
Added note to section 12.3.3 on page 250
Mar-06
9
Changed R max values in section 12.9.1 on page 266
ON
Added Figure 154. on page 276
Changed notes to “THERMAL CHARACTERISTICS” on page 288
Added text on ECOPACK packages in Section 13 PACKAGE CHARACTERISTICS and
changed Section 13.3 SOLDERING INFORMATION
Added “EXTERNAL INTERRUPT MISSED” on page 303
Added Section 15.7 MAXIMUM VALUES OF AVD THRESHOLDS
Modified MCES description in Section 7.2 on page 41
Modified name of bit 5 in the SPICSR register in Table 19 on page 106
Modifed section 10.4.3.3 on page 99 (added title “how to operate the SPI in Master mode)
Modified table in section 12.7.1 on page 261
Modified section 12.11.1 on page 271 (t
t
t
) and added note1 to t
su(SS), v(MO) and h(MO) su(SS)
and t
h(SS)
19-June-06
10
Removed EMC protection circuitry in Figure 145 on page 268 (device works correctly with-
out these components)
Modified description of DIV2 bit in section 14.1 on page 290
Changed Table 91 on page 293: removed ST7MC1K2B6 and ST7PMC1K2B6 (SDIP32
package)
Modified “ST7MC MICROCONTROLLER OPTION LIST” on page 293
Added revision history for revisions 6 and 7
Added caution to section 6.2.1 on page 30
Modified Figure 149 on page 272 (t
t
)
v(MO) , h(MO)
08-Dec-06
11
Replaced CPHA=0 with CPHA=1 in Figure 148. on page 272
Modified section 14.3 on page 294
Added one sales type (ST7FMC2S7T6) and modified Table 91 on page 293
Title of the document changed.
Modified Table 1, “Device summary,” on page 1
Removed SDIP32 package and part numbers for automotive products
Removed reference to ST7MC1K6
Added footnote to Table 1, “ST7MC Device Pin Description,” on page 12 indicating that it is
mandatory to connect all available V and V
pins to the supply voltage and all V and
DD
DDA
SS
V
pins to ground.
SSA
Values in inches rounded to 4 decimal digits (instead of 3 decimal digits) in Section 13.1
PACKAGE MECHANICAL DATA.
25-Sep-08
12
“Output Compare” on page 82: Changed text of note 3 and removed compare register i latch
signal from Figure 52. "Output Compare Timing Diagram, fTIMER =fCPU/4" page 84.
Modified t
values in Section 12.6.2 FLASH Memory
RET
Modified Section 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity).
Added “TIMD SET SIMULTANEOUSLY WITH OC INTERRUPT” on page 300.
Modified section 14.2 on page 292. (Figure 167 on page 292 and “ST7MC MICROCON-
TROLLER OPTION LIST” on page 293)
V
removed in section 12.2.1 on page 248 and section 12.7.3 on page 263
ESD(MM)
02-Apr-09
13
Modified GPB values (and conditions) in section 12.13 on page 280
Modified ECOPACK text in section 13 on page 285
308/309
ST7MC1xx/ST7MC2xx
Notes:
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309/309
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