ST92185B1BJ1/XXX [STMICROELECTRONICS]
16-BIT, MROM, 24MHz, MICROCONTROLLER, PDIP42, 0.600 INCH, PLASTIC, SDIP-42;
| 型号： | ST92185B1BJ1/XXX |
| 厂家： | 
ST |
| 描述： | 16-BIT, MROM, 24MHz, MICROCONTROLLER, PDIP42, 0.600 INCH, PLASTIC, SDIP-42 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总178页 (文件大小：2126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST92185
16K/24K/32K ROM HCMOS MCU with
on-screen-display
■ Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
■ 0°C to +70°C operating temperature range
■ Up to 24 MHz. operation @ 5V 10%
■ Min. instruction cycle time: 165ns at 24 MHz.
■ 16, 24 or 32 Kbytes ROM
■ 256 bytes RAM of Register file (accumulators or
PSDIP56
PSDIP42
index registers)
■ 256 bytes of on-chip static RAM
■ 2 Kbytes of TDSRAM (Display Storage RAM)
■ 28 fully programmable I/O pins
■ Serial Peripheral Interface
■ Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
■ Enhanced display controller with:
– 26 rows of 40 characters or 24 rows of 80
characters
– Serial and Parallel attributes
TQFP64
– 10x10 dot matrix, 512 ROM characters, defin-
able by user
See end of Datasheet for ordering information
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
■ Rich instruction set and 14 addressing modes
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
intensity color, transluccy and half-tone
modes
■ Versatile
development
tools,
including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
■ Integrated Sync Extractor and Sync Controller
■ 14-bit VoltagSynthesis for tuning reference
■ Pin-compatible EPROM and OTP devices
voltage
available (ST92E195D7D1, ST92T195D7B1)
■ Up 6 external interrupts plus one Non-
■ Pin-compatible with the ST92195 family with
Maskable Interrupt
embedded teletext decoder
■ 8 x 8-bit programmable PWM outputs with 5V
Device Summary
open-drain or push-pull capability
Program
Memory
VPS/
WSS
■ 16-bit watchdog timer with 8-bit prescaler
■ One 16-bit standard timer with 8-bit prescaler
■ 4-channel A/D converter; 5-bit guaranteed
Device
TDSRAM
ST92185B1
ST92185B2
ST92185B3
16K ROM
24K ROM
32K ROM
2K
2K
2K
No
No
No
September 2009
Doc ID 9885 Rev 2
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1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.3 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.4 TV Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.5 On Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.6 Voltage Synthesis Tuning Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.7 PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.8 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.9 Standard Timer (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.10 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1 I/O Port Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2.2 I/O Port Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.1 Central Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.3 Register Pointing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.4 Paged Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.5 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.6 Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.1 Addressing 16-Kbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.2 Addressing 64-Kbyte Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7.1 DPR[3:0]: Data Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7.2 CSR: Code Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7.3 ISR: Interrupt Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7.4 DMASR: DMA Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.8.1 Normal Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.8.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.8.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Table of Contents
3.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.1 Priority level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.2 Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.9 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.10 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 RESET / STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.5 RESET CONTROL UNIT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5 TIMING AND CLOCK CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1 FREQUENCY MULTIPLIERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.5.1 Pin Declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.5.2 Pin Declared as an Alternate Function Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.5.3 Pin Declared as an Alternate Function Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.1.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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7.1.4 WDT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.1.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2.3 Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.2.4 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.3 DISPLAY STORAGE RAM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.3.3 Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.4 ON SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.4.2 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.4.4 Programming the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.4.5 Vertical Scrolling Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.4.6 Display Memory Mapping Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.4.7 Font Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.4.8 Font Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.4.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.4.10 Application Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.5 SYNC CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.5.1 H/V Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.5.2 Field Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.5.3 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.5.4 Sync Controller Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.5.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.6.2 Device-Specific Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.6.4 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.6.5 Working With Other Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.6.6 I2C-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.6.7 S-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.6.8 IM-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.6.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.7 A/D CONVERTER (A/D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
178
4/178
Table of Contents
7.8 VOLTAGE SYNTHESIS TUNING CONVERTER (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.8.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.8.2 Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.8.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.9 PWM GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.9.2 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
9.2 ECOPACK
9.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
9.3.1 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5/178
ST92185 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
and interrupt controller keep running at a frequen-
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low power WFI).
The ST92185B microcontroller is developed and
manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The ST92185B MCU supports low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 28 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
1.1.4 TV Peripherals
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
A set of on-chip peripherals form a complete sys-
tem for TV set and VCR applications:
– Voltage Synthesis
– Display RAM
– OSD
Two basic addressable spaces are available: the
Memory space and the Register File, which in-
cludes the control and status registers of the on-
chip peripherals.
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 char-
acter set. The character resolution is 10x10 dot.
Four character sizes are supported. Serial at-
tributes allow the user to select foreground and
background colors, character size and fringe back-
ground. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.
1.1.2 Power Saving Modes
To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Note: The OSD cell is common to all ST92x195
family devices. However, its capabilities are limit-
ed by a TDSRAM memory size of 2Kbytes on the
ST92185 family. Certain display modes using
more than 2Kbytes of memory are not available.
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
6/178
ST92185 - GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
1.1.6 Voltage Synthesis Tuning Control
standards. The SPI uses a single data line for data
input and output. A second line is used for a syn-
chronous clock signal.
14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique can be used to generate tuning voltages
for TV set applications. The tuning voltage is out-
put on one of two separate output pins.
1.1.9 Standard Timer (STIM)
The ST92185B has one Standard Timer (STIM0)
that includes a programmable 16-bit down counter
and an associated 8-bit prescaler with Single and
Continuous counting modes.
1.1.7 PWM Output
Control of TV settings can be made with up to
eight 8-bit PWM outputs, with a maximum frequen-
cy of 23,437Hz at 8-bit resolution (INTCLK = 12
MHz). Low resolutions with higher frequency oper-
ation can be programmed.
1.1.10 Analog/Digital Converter (ADC)
In addition there is a 4-channel Analog to Digital
Converter with integral sample and hold, fast
5.75µs conversion time and 6-bit guaranteed reso-
lution.
1.1.8 Serial Peripheral Interface (SPI)
The SPI bus is used to communicate with external
devices via the SPI, or I²C bus communication
7/178
ST92185 - GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
Figure 1. ST92185B Block Diagram
24/32 Kbytes
ROM
I/O
PORT 0
P0[7:0]
P2[5:0]
8
6
4
8
256 bytes
RAM
I/O
PORT 2
2 Kbytes
TDSRAM
TRI
I/O
PORT 3
P3[7:4]
P4[7:0]
256 bytes
Register File
I/O
PORT 4
8/16-bit
CPU
MMU
NMI
I/O
PORT 5
2
P5[1:0]
INT[7:4]
Interrupt
Management
INT2
INT0
ST9+ CORE
RCCU
AIN[4:1]
EXTRG
ADC
OSCIN
OSCOUT
RESET
RESETO
VSYNC
SYNC
CONTROL
16-BIT
TIMER/
HSYNC/CSYNC
CSO
WATCHDOG
FREQ.
MULTIP.
ON
SCREEN
DISPLAY
PXFM
SDO/SDI
SCK
SPI
R/G/B/FB
TSLU
HT
TIMING AND
CLOCKCTRL
MCFM
PWM
D/A CON-
VERTER
PWM[7:0]
STANDARD
TIMER
STOUT
VOLTAGE
SYNTHESIS
VSO[2:1]
All alternate functions (Italic characters) are mapped on Ports 0, 2, 3, 4 and 5
8/178
ST92185 - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
RESET Reset (input, active low). The ST9+ is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
VSYNC Vertical Sync. Vertical video synchronisa-
tion input to OSD. Positive or negative polarity.
HSYNC/CSYNC Horizontal/Composite sync. Hori-
zontal or composite video synchronisation input to
OSD. Positive or negative polarity.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
R/G/B Red/Green/Blue. Video color analog DAC
outputs.
AVDD3 Analog V of PLL. This pin must be tied
DD
FB Fast Blanking. Video analog DAC output.
to V externally.
DD
V
V
Main power supply voltage (5V 10%, digital)
DD
GND Digital circuit ground.
: On EPROM/OTP devices, V
is the pro-
PP
PP
AGND Analog circuit ground (must be tied exter-
nally to digital GND).
gramming voltage pin. V should be tied to GND
PP
in user mode.
AVDD1, AVDD2 Analog power supplies (must be
MCFM Analog pin for the display pixel frequency
multiplier.
tied externally to V ).
DD
CVBSO, JTDO, JTCK, JTMS Test pins: leave
floating.
OSCIN, OSCOUT Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
TEST0 Test pin: must be tied to AVDD2.
JTRST0 Test pin: must be tied to GND.
Figure 2. 56-Pin Package Pin-Out
INT7/P2.0
P2.1/INT5/AIN1
1
56
RESET
P0.7
P0.6
2
3
4
55 P2.2/INT0/AIN2
54 P2.3/INT6/VS01
53 P2.4/NMI
P0.5
P0.4
5
6
52 P2.5/AIN3/INT4/VS02
51 OSCIN
P0.3
AIN4/P0.2
7
8
9
50 OSCOUT
49 P4.7/PWM7/EXTRG/STOUT
48 P4.6/PWM6
47 P4.5/PWM5
46 P4.4/PWM4
45 P4.3/PWM3/TSLU/HT
44 P4.2/PWM2
43 P4.1/PWM1
42 P4.0/PWM0
41 VSYNC
40 HSYNC/CSYNC
39 AVDD1
38 PXFM
37 JTRSTO
36 GND
35 AGND
34 N.C
33 N.C
32 JTMS
31 AVDD2
30 CVBSO
29 N.C
P0.1
P0.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDI/SDO/P5.1
SCK/INT2/P5.0
V
DD
JTDO
N.C
V
PP
AVDD3
TEST0
MCFM
JTCK
9/178
ST92185 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure 3. ST92185B Required External components (56-pin package)
10/178
ST92185 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure 4.. 42-Pin Package Pin-Out
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
4
5
6
7
8
P2.1/INT5/AIN1
INT7/P2.0
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
RESET
P0.7
P0.6
P0.5
P0.4
P0.3
AIN4/P0.2
P0.1
9
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P0.0
10
11
12
13
14
15
16
17
18
19
20
21
CSO/RESET0/P3.7
P3.6
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
P3.5
P3.4
B
G
HSYNC/CSYNC
TEST0
PXFM
R
FB
SDI/SDO/P5.1
SCK/INT2/P5.0
MCFM
V
GND
DD
11/178
ST92185 - GENERAL DESCRIPTION
Figure 5. ST92185B Required External Components (42-pin package)
12/178
ST92185 - GENERAL DESCRIPTION
Figure 6. 64-Pin Package Pin-Out
64
48
V
GND
1
SS
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
HSYNC/CSYNC
AVDD1
FB
PXFM
JTRST0
SDO/SDI/P5.1
INT2/SCK/P5.0
GND
V
DD
N.C.
JTDO
16
32
Note: N.C = Not connected
13/178
ST92185 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
P0[7:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]
I/O Port Lines (Input/Output, TTL or CMOS com-
patible).
Important: Note that open-drain outputs are for
logic levels only and are not true open drain.
1.2.1 I/O Port Alternate Functions.
28 lines grouped into I/O ports, bit programmable
as general purpose I/O or as Alternate functions
(see I/O section).
Each pin of the I/O ports of the ST92185B may as-
sume software programmable Alternate Functions
(see Table 1).
Table 1. ST92185B I/O Port Alternate Function Summary
Pin No.
Port
General
Purpose I/O
Alternate Functions
Name
SDIP42 SDIP56
P0.0
10
9
10
9
I/O
I/O
I
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
8
8
AIN4
A/D Analog Data Input 4
7
7
I/O
I/O
I/O
I/O
I/O
I
6
6
5
5
4
4
3
3
1
1
INT7
AIN1
INT5
INT0
AIN2
INT6
VSO1
NMI
External Interrupt 7
I
A/D Analog Data Input 1
External Interrupt 5
P2.1
P2.2
42
41
56
55
I
I
External Interrupt 0
I
A/D Analog Data Input 2
External Interrupt 6
I
P2.3
P2.4
40
39
54
53
Allportsuseable
for general pur-
pose I/O (input,
output or bidi-
rectional)
O
I
Voltage Synthesis Output 1
Non Maskable Interrupt Input
A/D Analog Data Input 3
External Interrupt 4
AIN3
INT4
VSO2
I
P2.5
38
52
I
O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
Voltage Synthesis Output 2
P3.4
P3.5
P3.6
14
13
12
14
13
12
RESET0
CSO
Internal Reset Output
Composite Sync output
PWM Output 0
P3.7
11
11
P4.0
P4.1
P4.2
28
29
30
42
43
44
PWM0
PWM1
PWM2
PWM3
TSLU
HT
PWM Output 1
PWM Output 2
PWM Output 3
P4.3
P4.4
31
32
45
46
Translucency Digital Output
Half-tone Output
PWM Output 4
PWM4
14/178
ST92185 - GENERAL DESCRIPTION
Pin No.
Port
General
Purpose I/O
Alternate Functions
Name
SDIP42 SDIP56
P4.5
33
34
47
48
PWM5
PWM6
EXTRG
PWM7
STOUT
INT2
O
O
I
PWM Output 5
P4.6
PWM Output 6
A/D Converter External Trigger Input
PWM Output 7
Allportsuseable
for general pur-
pose I/O (input,
output or bidi-
rectional)
P4.7
35
49
O
O
I
Standard Timer Output
External Interrupt 2
SPI Serial Clock
P5.0
P5.1
20
19
20
19
SCK
O
O
I
SDO
SPI Serial Data Out
SPI Serial Data In
SDI
15/178
ST92185 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
1.2.2 I/O Port Styles
Pins
P0[7:0]
P2[5,4,3,2]
P2[1,0]
P3.7
P3[6,5,4]
P4[7:0]
P5[1:0]
Weak Pull-Up
Port Style
Standard I/O
Standard I/O
Schmitt trigger
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Reset Values
BID / OD / TTL
BID / OD / TTL
BID / OD / TTL
AF / PP / TTL
BID / OD / TTL
BID / OD / TTL
BID / OD / TTL
no
no
no
yes
no
no
no
Legend:
AF= Alternate Function, BID = Bidirectional, OD = Open Drain
PP = Push-Pull, TTL = TTL Standard Input Levels
How to Read this Table
Example 1: ADC trigger digital input
AF: EXTRG, Port: P4.7, Port Style: Standard I/O.
Write the port configuration bits (for TTL level):
P4C2.7=1
To configure the I/O ports, use the information in
this table and the Port Bit Configuration Table in
the I/O Ports Chapter on page 69.
P4C1.7=0
Port Style= the hardware characteristics fixed for
each port line.
P4C0.7=1
Enable the ADC trigger by software as described
in the ADC chapter.
Inputs:
– If port style = Standard I/O, either TTL or CMOS
input level can be selected by software.
Example 2: PWM 0 output
AF: PWM0, Port: P4.0
– If port style = Schmitt trigger, selecting CMOS or
TTL input by software has no effect, the input will
always be Schmitt Trigger.
Write the port configuration bits (for output push-
pull):
Weak Pull-Up = This column indicates if a weak
P4C2.0=0
pull-up is present or not.
P4C1.0=1
– If WPU = yes, then the WPU can be enabled/dis-
able by software
P4C0.0=1
Example 3: ADC analog input
– If WPU = no, then enabling the WPU by software
has no effect
AF: AIN1, Port : P2.1, Port style: does not apply to
analog inputs
Write the port configuration bits:
P2C2.1=1
Alternate Functions (AF) = More than one AF
cannot be assigned to an external pin at the same
time:
P2C1.1=1
An alternate function can be selected as follows.
AF Inputs:
P2C0.1=1
– AF is selected implicitly by enabling the corre-
sponding peripheral. Exception to this are ADC
analog inputs which must be explicitly selected
as AF by software.
AF Outputs or Bidirectional Lines:
– In the case of Outputs or I/Os, AF is selected
explicitly by software.
16/178
ST92185 - GENERAL DESCRIPTION
1.3 MEMORY MAP
Internal ROM
Internal RAM, 256 bytes
The ROM memory is mapped in a single continu-
ous area starting at address 0000h in MMU seg-
ment 00h.
The internal RAM is mapped in MMU segment
20h; from address FF00h to FFFFh.
Internal TDSRAM
The Internal TDSRAM is mapped starting at ad-
dress 8000h in MMU segment 22h. It is a fully stat-
ic memory.
Start
Address
End
Address
Device
ST92185B1
Size
16K
24K
32K
0000h
0000h
0000h
3FFFh
5FFFh
7FFFh
Start
Address
End
Address
ST92185B2
ST92185B3
Device
Size
ST92185B1/B2/B3
2K
8000h
87FFh
Figure 7. ST92185B Memory Map
2287FFh
2Kbytes
22FFFFh
PAGE 91 - 16 Kbytes
PAGE 90 - 16 Kbytes
PAGE 89 - 16 Kbytes
PAGE 88 - 16 Kbytes
Reserved
22C000h
22BFFFh
TDSRAM
228000h
228000h
227FFFh
SEGMENT 22h
64 Kbytes
Reserved
Reserved
224000h
223FFFh
220000h
21FFFFh
SEGMENT 21h
64 Kbytes
Reserved
210000h
20FFFFh
20FFFFh
Internal
RAM
PAGE 83 - 16 Kbytes
PAGE 82 - 16 Kbytes
PAGE 81 - 16 Kbytes
PAGE 80 - 16 Kbytes
20C000h
20BFFFh
Reserved
Reserved
256 bytes
20FF00h
SEGMENT 20h
64 Kbytes
208000h
207FFFh
204000h
203FFFh
Reserved
200000h
00FFFFh
PAGE 3 - 16 Kbytes
PAGE 2 - 16 Kbytes
PAGE 1 - 16 Kbytes
PAGE 0 - 16 Kbytes
007FFFh
005FFFh
32 Kbytes
24 Kbytes
00C000h
00BFFFh
Internal ROM
003FFFh SEGMENT 0
64 Kbytes
008000h
007FFFh
max. 64 Kbytes
Internal ROM
16K bytes
004000h
003FFFh
000000h
000000h
17/178
ST92185 - GENERAL DESCRIPTION
1.4 REGISTER MAP
The following pages contain a list of ST92185B
registers, grouped by peripheral or function.
In particular, double-check that any registers with
“undefined” reset values have been correctly ini-
tialised.
Be very careful to correctly program both:
Warning: Note that in the EIVR and each IVR reg-
ister, all bits are significant. Take care when defin-
ing base vector addresses that entries in the Inter-
rupt Vector table do not overlap.
– The set of registers dedicated to a particular
function or peripheral.
– Registers common to other functions.
Group F Pages Register Map
Register
Page
0
2
3
11
21
32 33
35
38
Res
39
55
59
VS
62
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
Res.
Res.
Res.
Res.
SPI
RCCU
(PLL)
Port 3
Res.
Res.
TCC
WCR
TDSRAM
TSU
Res.
MMU
Res.
WDT
Res.
Port 2
Res.
OSD
PWM
Res.
Res
Res.
Port 5
Res.
Res.
Res.
EXT
INT
MMU
SYNC
Res.
STIM
Port 0
Port 4
A/D
Res.
18/178
ST92185 - GENERAL DESCRIPTION
Table 2. Detailed Register Map
Group F
Reset
Doc.
Reg.
No.
Register
Page
Dec.
Block
Description
Value
Hex.
Name
Page
R224
R226
R227
R228
R229
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R240
R241
R242
R248
R249
R250
R252
R253
R254
P0DR
P2DR
P3DR
P4DR
P5DR
CICR
Port 0 Data Register
Port 2 Data Register
FF
FF
FF
FF
FF
87
00
xx
I/O
Port
0:5
Port 3 Data Register
66
Port 4 Data Register
Port 5 Data Register
Central Interrupt Control Register
Flag Register
53
26
28
28
30
30
33
33
33
33
53
54
54
54
55
55
78
78
78
78
79
150
150
FLAGR
RP0
N/A
Pointer 0 Register
RP1
Pointer 1 Register
xx
PPR
Page Pointer Register
xx
Core
MODER
USPHR
USPLR
SSPHR
SSPLR
EITR
Mode Register
E0
xx
User Stack Pointer High Register
User Stack Pointer Low Register
System Stack Pointer High Reg.
System Stack Pointer Low Reg.
External Interrupt Trigger Register
External Interrupt Pending Reg.
External Interrupt Mask-bit Reg.
External Interrupt Priority Level Reg.
External Interrupt Vector Register
Nested Interrupt Control
xx
xx
xx
00
00
00
FF
x6
00
FF
FF
FF
12
7F
xx
EIPR
EIMR
INT
EIPLR
EIVR
NICR
0
WDTHR
WDTLR
WDTPR
WDTCR
WCR
Watchdog Timer High Register
Watchdog Timer Low Register
Watchdog Timer Prescaler Reg.
Watchdog Timer Control Register
Wait Control Register
WDT
SPI
SPIDR
SPICR
P0C0
SPI Data Register
SPI Control Register
00
00
00
00
00
00
00
00
00
00
Port 0 Configuration Register 0
Port 0 Configuration Register 1
Port 0 Configuration Register 2
Port 2 Configuration Register 0
Port 2 Configuration Register 1
Port 2 Configuration Register 2
Port 3 Configuration Register 0
Port 3 Configuration Register 1
Port 3 Configuration Register 2
I/O
Port
0
P0C1
P0C2
P2C0
I/O
Port
2
2
P2C1
66
P2C2
P3C0
I/O
Port
3
P3C1
P3C2
19/178
ST92185 - GENERAL DESCRIPTION
Group F
Page
Dec.
Reset
Value
Hex.
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R244
R245
R246
R240
R241
R242
R243
R240
R241
R242
R243
R244
R248
R249
P4C0
P4C1
P4C2
P5C0
P5C1
P5C2
STH
Port 4 Configuration Register 0
Port 4 Configuration Register 1
Port 4 Configuration Register 2
Port 5 Configuration Register 0
Port 5 Configuration Register 1
Port 5 Configuration Register 2
Counter High Byte Register
Counter Low Byte Register
Standard Timer Prescaler Register
Standard Timer Control Register
Data Page Register 0
00
00
00
00
00
00
FF
FF
FF
14
xx
xx
xx
xx
00
xx
I/O
Port
4
3
66
I/O
Port
5
83
83
83
83
38
38
38
38
39
39
39
STL
11
STIM
STP
STC
DPR0
DPR1
DPR2
DPR3
CSR
Data Page Register 1
Data Page Register 2
MMU
Data Page Register 3
21
Code Segment Register
ISR
Interrupt Segment Register
DMA Segment Register
DMASR
xx
Ext.Mem. R246
EMR2
External Memory Register 2
0F
56
R240
R241
R242
R243
R244
R245
R246
R247
R248
HBLANKR
HPOSR
VPOSR
FSCCR
HSCR
Horizontal Blank Register
Horizontal Position Register
03
03
00
00
2A
00
00
00
00
00
00
00
00
FF
FF
xF
70
00
x0
x0
00
00
02
121
121
121
122
123
124
125
125
126
127
129
130
130
131
131
131
132
132
132
132
140
141
87
Vertical Position Register
Full Screen Color Control Register
Header & Status Control Register
National Character Set Control Register
Cursor Horizontal Position Register
Cursor Vertical Position Register
Scrolling Control Low Register
NCSR
CHPOSR
CVPOSR
SCLR
32
R249
OSD
SCHR
Scrolling Control High Register
R250
DCM0R
DCM1R
TDPR
Display Control Mode 0 Register
Display Control Mode 1 Register
TDSRAM Pointer Register
R251
R252
R253
R254
R255
R240
R241
R246
R247
DE0R
Display Enable 0 Control Register
Display Enable 1 Control Register
Display Enable 2 Control Register
Default Color Register
DE1R
DE2R
DCR
CAPVR
TDPPR
TDHSPR
SCCS0R
SCCS1R
CONFIG
Cursor Absolute Vertical Position Register
TDSRAM Page Pointer Register
TDSRAM Header/Status Pointer Register
Sync Controller Control and Status Register 0
Sync Controller Control and Status Register 1
TDSRAM Interface Configuration Register
33
R242
SYNC
35
38
R243
TDSRAM R252
20/178
ST92185 - GENERAL DESCRIPTION
Group F
Page
Dec.
Reset
Doc.
Reg.
No.
Register
Name
Block
TCC
Description
Value
Hex.
Page
R251
R252
R253
R254
R251
PXCCR
SLCCR
MCCR
PLL Clock Control Register
Slicer Clock Control Register
Main Clock Control Register
Skew Clock Control Register
PLL Configuration Register
00
00
00
00
07
66
66
65
65
61
39
55
SKCCR
PCONF
RCCU
2x,4x
or 00
R254
SDRATH
Clock Slow Down Unit Ratio Register
61
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R254
R255
R240
R241
R242
CM0
CM1
Compare Register 0
Compare Register 1
Compare Register 2
Compare Register 3
Compare Register 4
Compare Register 5
Compare Register 6
Compare Register 7
Autoclear Register
00
00
00
00
00
00
00
00
FF
00
0C
00
00
00
00
xx
163
163
163
163
163
163
163
163
164
164
164
165
165
160
160
155
154
155
CM2
CM3
CM4
CM5
PWM
CM6
59
CM7
ACR
CCR
Counter Register
PCTL
OCPL
OER
Prescaler and Control Register
Output Complement Register
Output Enable Register
Data and Control Register 1
Data Register 2
VSDR1
VSDR2
ADDTR
ADCLR
ADINT
VS
Channel i Data Register
Control Logic Register
AD Interrupt Register
62
ADC
00
01
Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register
description for details.
21/178
ST92185 - DEVICE ARCHITECTURE
2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE
The ST9 Core or Central Processing Unit (CPU)
features a highly optimised instruction set, capable
of handling bit, byte (8-bit) and word (16-bit) data,
as well as BCD and Boolean formats; 14 address-
ing modes are available.
which hold data and control bits for the on-chip
peripherals and I/Os.
– A single linear memory space accommodating
both program and data. All of the physically sep-
arate memory areas, including the internal ROM,
internal RAM and external memory are mapped
in this common address space. The total ad-
dressable memory space of 4 Mbytes (limited by
the size of on-chip memory and the number of
external address pins) is arranged as 64 seg-
ments of 64 Kbytes. Each segment is further
subdivided into four pages of 16 Kbytes, as illus-
trated in Figure 1. A Memory Management Unit
uses a set of pointer registers to address a 22-bit
memory field using 16-bit address-based instruc-
tions.
Four independent buses are controlled by the
Core: a 16-bit Memory bus, an 8-bit Register data
bus, an 8-bit Register address bus and a 6-bit In-
terrupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
Core.
This multiple bus architecture affords a high de-
gree of pipelining and parallel operation, thus mak-
ing the ST9 family devices highly efficient, both for
numerical calculation, data handling and with re-
gard to communication with on-chip peripheral re-
sources.
2.2.1 Register File
The Register File consists of (see Figure 2):
2.2 MEMORY SPACES
– 224 general purpose registers (Group 0 to D,
registers R0 to R223)
There are two separate memory spaces:
– The Register File, which comprises 240 8-bit
registers, arranged as 15 groups (Group 0 to E),
each containing sixteen 8-bit registers plus up to
64 pages of 16 registers mapped in Group F,
– 6 system registers in the System Group (Group
E, registers R224 to R239)
– Up to 64 pages, depending on device configura-
tion, each containing up to 16 registers, mapped
to Group F (R240 to R255), see Figure 3.
Figure 8. Single Program and Data Memory Address Space
Data
Code
Address
16K Pages 64K Segments
255
254
3FFFFFh
63
253
3F0000h
3EFFFFh
252
251
250
249
248
247
62
3E0000h
up to 4 Mbytes
135
134
133
132
21FFFFh
Reserved
33
210000h
20FFFFh
11
10
9
02FFFFh
2
020000h
01FFFFh
8
7
6
1
5
010000h
00FFFFh
4
3
2
0
1
0
000000h
22/178
ST92185 - DEVICE ARCHITECTURE
MEMORY SPACES (Cont’d)
Figure 9. Register Groups
Figure 10. Page Pointer for Group F mapping
PAGE 63
UP TO
255
240
239
64 PAGES
F PAGED REGISTERS
E SYSTEM REGISTERS
224
PAGE 5
223
D
R255
PAGE 0
C
B
A
9
8
7
6
5
4
3
2
1
R240
R234
R224
PAGE POINTER
224
GENERAL
PURPOSE
REGISTERS
15
0
0
0
VA00432
R0
VA00433
Figure 11. Addressing the Register File
REGISTER FILE
255
F PAGED REGISTERS
240
239
E
D
C
B
A
9
8
7
6
5
4
3
SYSTEM REGISTERS
224
223
GROUP D
R195
(R0C3h)
R207
(1100)(0011)
GROUP C
R195
R192
GROUP B
2
1
0
15
0
0
VR000118
23/178
ST92185 - DEVICE ARCHITECTURE
MEMORY SPACES (Cont’d)
2.2.2 Register Addressing
Therefore if the Page Pointer, R234, is set to 5, the
instructions:
Register File registers, including Group F paged
registers (but excluding Group D), may be ad-
dressed explicitly by means of a decimal, hexa-
decimal or binary address; thus R231, RE7hand
R11100111b represent the same register (see
Figure 4). Group D registers can only be ad-
dressed in Working Register mode.
spp #5
ld R242, r4
will load the contents of working register r4 into the
third register of page 5 (R242).
These paged registers hold data and control infor-
mation relating to the on-chip peripherals, each
peripheral always being associated with the same
pages and registers to ensure code compatibility
between ST9 devices. The number of these regis-
ters therefore depends on the peripherals which
are present in the specific ST9 family device. In
other words, pages only exist if the relevant pe-
ripheral is present.
Note that an upper case “R” is used to denote this
direct addressing mode.
Working Registers
Certain types of instruction require that registers
be specified in the form “rx”, where x is in the
range 0 to 15: these are known as Working Regis-
ters.
Note that a lower case “r” is used to denote this in-
direct addressing mode.
Table 3. Register File Organization
Two addressing schemes are available: a single
group of 16 working registers, or two separately
mapped groups, each consisting of 8 working reg-
isters. These groups may be mapped starting at
any 8 or 16 byte boundary in the register file by
means of dedicated pointer registers. This tech-
nique is described in more detail in Section 1.3.3,
and illustrated in Figure 5 and in Figure 6.
Hex.
Address
Decimal
Address
Register
File Group
Function
Paged
Registers
F0-FF
E0-EF
240-255
224-239
Group F
Group E
System
Registers
D0-DF
C0-CF
B0-BF
A0-AF
90-9F
80-8F
70-7F
60-6F
50-5F
40-4F
30-3F
20-2F
10-1F
00-0F
208-223
192-207
176-191
160-175
144-159
128-143
112-127
96-111
80-95
Group D
Group C
Group B
Group A
Group 9
Group 8
Group 7
Group 6
Group 5
Group 4
Group 3
Group 2
Group 1
Group 0
System Registers
The 16 registers in Group E (R224 to R239) are
System registers and may be addressed using any
of the register addressing modes. These registers
are described in greater detail in Section 1.3.
Paged Registers
General
Purpose
Registers
Up to 64 pages, each containing 16 registers, may
be mapped to Group F. These are addressed us-
ing any register addressing mode, in conjunction
with the Page Pointer register, R234, which is one
of the System registers. This register selects the
page to be mapped to Group F and, once set,
does not need to be changed if two or more regis-
ters on the same page are to be addressed in suc-
cession.
64-79
48-63
32-47
16-31
00-15
24/178
ST92185 - DEVICE ARCHITECTURE
2.3 SYSTEM REGISTERS
The System registers are listed in Table 2 System
Registers (Group E). They are used to perform all
the important system settings. Their purpose is de-
scribed in the following pages. Refer to the chapter
dealing with I/O for a description of the PORT[5:0]
Data registers.
Note: If an MFT is not included in the ST9 device,
then this bit has no effect.
Bit 6 = TLIP: Top Level Interrupt Pending.
This bit is set by hardware when a Top Level Inter-
rupt Request is recognized. This bit can also be
set by software to simulate a Top Level Interrupt
Request.
0: No Top Level Interrupt pending
1: Top Level Interrupt pending
Table 4. System Registers (Group E)
R239 (EFh)
R238 (EEh)
R237 (EDh)
R236 (ECh)
R235 (EBh)
R234 (EAh)
R233 (E9h)
R232 (E8h)
R231 (E7h)
R230 (E6h)
R229 (E5h)
R228 (E4h)
R227 (E3h)
R226 (E2h)
R225 (E1h)
R224 (E0h)
SSPLR
SSPHR
USPLR
Bit 5 = TLI: Top Level Interrupt bit.
0: Top Level Interrupt is acknowledged depending
on the TLNM bit in the NICR Register.
1: Top Level Interrupt is acknowledged depending
on the IEN and TLNM bits in the NICR Register
(described in the Interrupt chapter).
USPHR
MODE REGISTER
PAGE POINTER REGISTER
REGISTER POINTER 1
REGISTER POINTER 0
FLAG REGISTER
CENTRAL INT. CNTL REG
PORT5 DATA REG.
PORT4 DATA REG.
PORT3 DATA REG.
PORT2 DATA REG.
PORT1 DATA REG.
PORT0 DATA REG.
Bit 4 = IEN: Interrupt Enable .
This bit is cleared by interrupt acknowledgement,
and set by interrupt return (iret). IEN is modified
implicitly by iret, eiand diinstructions or by an
interrupt acknowledge cycle. It can also be explic-
itly written by the user, but only when no interrupt
is pending. Therefore, the user should execute a
di instruction (or guarantee by other means that
no interrupt request can arrive) before any write
operation to the CICR register.
0: Disable all interrupts except Top Level Interrupt.
1: Enable Interrupts
2.3.1 Central Interrupt Control Register
Please refer to the ”INTERRUPT” chapter for a de-
tailed description of the ST9 interrupt philosophy.
Bit 3 = IAM: Interrupt Arbitration Mode.
This bit is set and cleared by software to select the
arbitration mode.
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
R230 - Read/Write
Register Group: E (System)
Reset Value: 1000 0111 (87h)
0: Concurrent Mode
1: Nested Mode.
Bits 2:0 = CPL[2:0]: Current Priority Level.
7
0
These three bits record the priority level of the rou-
tine currently running (i.e. the Current Priority Lev-
el, CPL). The highest priority level is represented
by 000, and the lowest by 111. The CPL bits can
be set by hardware or software and provide the
reference according to which subsequent inter-
rupts are either left pending or are allowed to inter-
rupt the current interrupt service routine. When the
current interrupt is replaced by one of a higher pri-
ority, the current priority value is automatically
stored until required in the NICR register.
GCEN TLIP TLI IEN
IAM CPL2 CPL1 CPL0
Bit 7 = GCEN: Global Counter Enable.
This bit is the Global Counter Enable of the Multi-
function Timers. The GCEN bit is ANDed with the
CE bit in the TCR Register (only in devices featur-
ing the MFT Multifunction Timer) in order to enable
the Timers when both bits are set. This bit is set af-
ter the Reset cycle.
25/178
ST92185 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
2.3.2 Flag Register
decw),
Test (tm, tmw, tcm, tcmw, btset).
The Flag Register contains 8 flags which indicate
the CPU status. During an interrupt, the flag regis-
ter is automatically stored in the system stack area
and recalled at the end of the interrupt service rou-
tine, thus returning the CPU to its original status.
Inmostcases,theZeroflagissetwhenthecontents
of the register being used as an accumulator be-
come zero, following one of the above operations.
This occurs for all interrupts and, when operating
in nested mode, up to seven versions of the flag
register may be stored.
Bit 5 = S: Sign Flag.
The Sign flag is affected by the same instructions
as the Zero flag.
FLAG REGISTER (FLAGR)
R231- Read/Write
Register Group: E (System)
Reset value: 0000 0000 (00h)
The Sign flag is set when bit 7 (for a byte opera-
tion) or bit 15 (for a word operation) of the register
used as an accumulator is one.
7
0
Bit 4 = V: Overflow Flag.
The Overflow flag is affected by the same instruc-
tions as the Zero and Sign flags.
C
Z
S
V
DA
H
-
DP
When set, the Overflow flag indicates that a two's-
complement number, in a result register, is in er-
ror, since it has exceeded the largest (or is less
than the smallest), number that can be represent-
ed in two’s-complement notation.
Bit 7 = C: Carry Flag.
The carry flag is affected by:
Addition (add, addw, adc, adcw),
Subtraction (sub, subw, sbc, sbcw),
Compare (cp, cpw),
Shift Right Arithmetic (sra, sraw),
Shift Left Arithmetic (sla, slaw),
Swap Nibbles (swap),
Rotate (rrc, rrcw, rlc, rlcw, ror,
rol),
Decimal Adjust (da),
Multiply and Divide (mul, div, divws).
Bit 3 = DA: Decimal Adjust Flag.
The DA flag is used for BCD arithmetic. Since the
algorithm for correcting BCD operations is differ-
ent for addition and subtraction, this flag is used to
specify which type of instruction was executed
last, so that the subsequent Decimal Adjust (da)
operation can perform its function correctly. The
DA flag cannot normally be used as a test condi-
tion by the programmer.
When set, it generally indicates a carry out of the
most significant bit position of the register being
used as an accumulator (bit 7 for byte operations
and bit 15 for word operations).
Bit 2 = H: Half Carry Flag.
The carry flag can be set by the Set Carry Flag
(scf) instruction, cleared by the Reset Carry Flag
(rcf) instruction, and complemented by the Com-
plement Carry Flag (ccf) instruction.
The H flag indicates a carry out of (or a borrow in-
to) bit 3, as the result of adding or subtracting two
8-bit bytes, each representing two BCD digits. The
H flag is used by the Decimal Adjust (da) instruc-
tion to convert the binary result of a previous addi-
tion or subtraction into the correct BCD result. Like
the DA flag, this flag is not normally accessed by
the user.
Bit 6 = Z: Zero Flag. The Zero flag is affected by:
Addition (add, addw, adc, adcw),
Subtraction (sub, subw, sbc, sbcw),
Compare (cp, cpw),
Shift Right Arithmetic (sra, sraw),
Shift Left Arithmetic (sla, slaw),
Swap Nibbles (swap),
Bit 1 = Reserved bit (must be 0).
Rotate (rrc, rrcw, rlc, rlcw, ror,
rol),
Bit 0 = DP: Data/Program Memory Flag.
This bit indicates the memory area addressed. Its
value is affected by the Set Data Memory (sdm)
and Set Program Memory (spm) instructions. Re-
fer to the Memory Management Unit for further de-
tails.
Decimal Adjust (da),
Multiply and Divide (mul, div, divws),
Logical (and, andw, or, orw, xor,
xorw, cpl),
Increment and Decrement (inc, incw, dec,
26/178
ST92185 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
If the bit is set, data is accessed using the Data
Pointers (DPRs registers), otherwise it is pointed
to by the Code Pointer (CSR register); therefore,
the user initialization routine must include a Sdm
instruction. Note that code is always pointed to by
the Code Pointer (CSR).
specifies the location of the lower 8-register block,
while the srp0and srp1instructions automatical-
ly select the twin 8-register group mode and spec-
ify the locations of each 8-register block.
There is no limitation on the order or position of
these register groups, other than that they must
start on an 8-register boundary in twin 8-register
mode, or on a 16-register boundary in single 16-
register mode.
Note: In the current ST9 devices, the DP flag is
only for compatibility with software developed for
the first generation of ST9 devices. With the single
memory addressing space, its use is now redun-
dant. It must be kept to 1 with a Sdminstruction at
the beginning of the program to ensure a normal
use of the different memory pointers.
The block number should always be an even
number in single 16-register mode. The 16-regis-
ter group will always start at the block whose
number is the nearest even number equal to or
lower than the block number specified in the srp
instruction. Avoid using odd block numbers, since
this can be confusing if twin mode is subsequently
selected.
2.3.3 Register Pointing Techniques
Two registers within the System register group,
are used as pointers to the working registers. Reg-
ister Pointer 0 (R232) may be used on its own as a
single pointer to a 16-register working space, or in
conjunction with Register Pointer 1 (R233), to
point to two separate 8-register spaces.
Thus:
srp #3will be interpreted as srp #2 and will al-
low using R16 ..R31 as r0 .. r15.
For the purpose of register pointing, the 16 register
groups of the register file are subdivided into 32 8-
register blocks. The values specified with the Set
Register Pointer instructions refer to the blocks to
be pointed to in twin 8-register mode, or to the low-
er 8-register block location in single 16-register
mode.
In single 16-register mode, the working registers
are referred to as r0 to r15. In twin 8-register
mode, registers r0to r7are in the block pointed
to by RP0 (by means of the srp0 instruction),
while registers r8to r15are in the block pointed
to by RP1 (by means of the srp1instruction).
The Set Register Pointer instructions srp, srp0
and srp1 automatically inform the CPU whether
the Register File is to operate in single 16-register
mode or in twin 8-register mode. The srpinstruc-
tion selects the single 16-register group mode and
Caution: Group D registers can only be accessed
as working registers using the Register Pointers,
or by means of the Stack Pointers. They cannot be
addressed explicitly in the form “Rxxx”.
27/178
ST92185 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
POINTER 0 REGISTER (RP0)
R232 - Read/Write
Register Group: E (System)
Reset Value: xxxx xx00 (xxh)
POINTER 1 REGISTER (RP1)
R233 - Read/Write
Register Group: E (System)
Reset Value: xxxx xx00 (xxh)
7
0
0
7
0
0
RG4 RG3 RG2 RG1 RG0 RPS
0
RG4 RG3 RG2 RG1 RG0 RPS
0
Bits 7:3 = RG[4:0]: Register Group number.
This register is only used in the twin register point-
ing mode. When using the single register pointing
mode, or when using only one of the twin register
groups, the RP1 register must be considered as
RESERVED and may NOT be used as a general
purpose register.
These bits contain the number (in the range 0 to
31) of the register block specified in the srp0 or
srp instructions. In single 16-register mode the
number indicates the lower of the two 8-register
blocks to which the 16 working registers are to be
mapped, while in twin 8-register mode it indicates
the 8-register block to which r0 to r7 are to be
mapped.
Bits 7:3 = RG[4:0]: Register Group number.
These bits contain the number (in the range 0 to
31) of the 8-register block specified in the srp1in-
struction, to which r8to r15are to be mapped.
Bit 2 = RPS: Register Pointer Selector.
This bit is set by the instructions srp0and srp1to
indicate that the twin register pointing mode is se-
lected. The bit is reset by the srpinstruction to in-
dicate that the single register pointing mode is se-
lected.
Bit 2 = RPS: Register Pointer Selector.
This bit is set by the srp0and srp1instructions to
indicate that the twin register pointing mode is se-
lected. The bit is reset by the srpinstruction to in-
dicate that the single register pointing mode is se-
lected.
0: Single register pointing mode
1: Twin register pointing mode
0: Single register pointing mode
1: Twin register pointing mode
Bits 1:0: Reserved. Forced by hardware to zero.
Bits 1:0: Reserved. Forced by hardware to zero.
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ST92185 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
Figure 12. Pointing to a single group of 16
registers
Figure 13. Pointing to two groups of 8 registers
REGISTER
GROUP
BLOCK
NUMBER
REGISTER
GROUP
BLOCK
NUMBER
REGISTER
FILE
REGISTER
FILE
31
30
29
28
27
26
25
REGISTER
POINTER 0
&
REGISTER
POINTER 1
F
E
D
31
30
29
28
27
26
25
REGISTER
POINTER 0
set by:
F
E
D
srp #2
set by:
instruction
srp0 #2
&
srp1 #7
points to:
instructions
point to:
addressed by
BLOCK 7
9
8
7
6
5
4
3
2
1
0
4
9
8
7
6
5
4
3
2
1
0
4
r15
r8
GROUP 3
3
2
1
0
3
2
1
0
r15
r0
r7
r0
GROUP 1
addressed by
BLOCK 2
GROUP 1
addressed by
BLOCK 2
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ST92185 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
2.3.4 Paged Registers
need to refresh it unless a different page is re-
quired.
Up to 64 pages, each containing 16 registers, may
be mapped to Group F. These paged registers
hold data and control information relating to the
on-chip peripherals, each peripheral always being
associated with the same pages and registers to
ensure code compatibility between ST9 devices.
The number of these registers depends on the pe-
ripherals present in the specific ST9 device. In oth-
er words, pages only exist if the relevant peripher-
al is present.
Bits 1:0: Reserved. Forced by hardware to 0.
2.3.5 Mode Register
The Mode Register allows control of the following
operating parameters:
– Selection of internal or external System and User
Stack areas,
The paged registers are addressed using the nor-
mal register addressing modes, in conjunction with
the Page Pointer register, R234, which is one of
the System registers. This register selects the
page to be mapped to Group F and, once set,
does not need to be changed if two or more regis-
ters on the same page are to be addressed in suc-
cession.
– Management of the clock frequency,
– Enabling of Bus request and Wait signals when
interfacing to external memory.
MODE REGISTER (MODER)
R235 - Read/Write
Register Group: E (System)
Reset value: 1110 0000 (E0h)
Thus the instructions:
spp #5
ld R242, r4
7
0
SSP
USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP
will load the contents of working register r4 into the
third register of page 5 (R242).
Warning: During an interrupt, the PPR register is
not saved automatically in the stack. If needed, it
should be saved/restored by the user within the in-
terrupt routine.
Bit 7 = SSP: System Stack Pointer.
This bit selects an internal or external System
Stack area.
0: External system stack area, in memory space.
1: Internal system stack area, in the Register File
(reset state).
PAGE POINTER REGISTER (PPR)
R234 - Read/Write
Register Group: E (System)
Reset value: xxxx xx00 (xxh)
Bit 6 = USP: User Stack Pointer.
This bit selects an internal or external User Stack
area.
0: External user stack area, in memory space.
1: Internal user stack area, in the Register File (re-
set state).
7
0
0
PP5 PP4 PP3 PP2 PP1 PP0
0
Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2.
This bit controls the divide-by-2 circuit operating
on the crystal oscillator clock (CLOCK1).
0: Clock divided by 1
Bits 7:2 = PP[5:0]: Page Pointer.
These bits contain the number (in the range 0 to
63) of the page specified in the spp instruction.
Once the page pointer has been set, there is no
1: Clock divided by 2
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ST92185 - DEVICE ARCHITECTURE
Note: Disregard this bit if BREQ pin is not availa-
ble.
Bits 4:2 = PRS[2:0]: CPUCLK Prescaler.
These bits load the prescaler division factor for the
internal clock (INTCLK). The prescaler factor se-
lects the internal clock frequency, which can be di-
vided by a factor from 1 to 8. Refer to the Reset
and Clock Control chapter for further information.
Bit 0 = HIMP: High Impedance Enable.
When any of Ports 0, 1, 2 or 6 depending on de-
vice configuration, are programmed as Address
and Data lines to interface external Memory, these
lines and the Memory interface control lines (AS,
DS, R/W) can be forced into the High Impedance
Bit 1 = BRQEN: Bus Request Enable.
0: External Memory Bus Request disabled
1: External Memory Bus Request enabled on
BREQ pin (where available).
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ST92185 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
state by setting the HIMP bit. When this bit is reset,
it has no effect.
Code Segment Register is also pushed onto the
System Stack.
Setting the HIMP bit is recommended for noise re-
duction when only internal Memory is used.
– Subroutine Calls
When a callinstruction is executed, only the PC
is pushed onto stack, whereas when a calls in-
struction (call segment) is executed, both the PC
and the Code Segment Register are pushed onto
the System Stack.
If Port 1 and/or 2 are declared as an address AND
as an I/O port (for example: P10... P14 = Address,
and P15... P17 = I/O), the HIMP bit has no effect
on the I/O lines.
– Link Instruction
2.3.6 Stack Pointers
The link or linku instructions create a C lan-
guage stack frame of user-defined length in the
System or User Stack.
Two separate, double-register stack pointers are
available: the System Stack Pointer and the User
Stack Pointer, both of which can address registers
or memory.
All of the above conditions are associated with
their counterparts, such as return instructions,
which pop the stored data items off the stack.
The stack pointers point to the “bottom” of the
stacks which are filled using the push commands
and emptied using the pop commands. The stack
pointer is automatically pre-decremented when
data is “pushed” in and post-incremented when
data is “popped” out.
User Stack
The User Stack provides a totally user-controlled
stacking area.
The User Stack Pointer consists of two registers,
R236 and R237, which are both used for address-
ing a stack in memory. When stacking in the Reg-
ister File, the User Stack Pointer High Register,
R236, becomes redundant but must be consid-
ered as reserved.
The push and pop commands used to manage the
System Stack may be addressed to the User
Stack by adding the suffix “u”. To use a stack in-
struction for a word, the suffix “w”is added. These
suffixes may be combined.
Stack Pointers
When bytes (or words) are “popped” out from a
stack, the contents of the stack locations are un-
changed until fresh data is loaded. Thus, when
data is “popped” from a stack area, the stack con-
tents remain unchanged.
Both System and User stacks are pointed to by
double-byte stack pointers. Stacks may be set up
in RAM or in the Register File. Only the lower byte
will be required if the stack is in the Register File.
The upper byte must then be considered as re-
served and must not be used as a general purpose
register.
Note: Instructions such as: pushuw RR236 or
pushw RR238, as well as the corresponding
pop instructions (where R236 & R237, and R238
& R239 are themselves the user and system stack
pointers respectively), must not be used, since the
pointer values are themselves automatically
changed by the pushor popinstruction, thus cor-
rupting their value.
The stack pointer registers are located in the Sys-
tem Group of the Register File, this is illustrated in
Table 2 System Registers (Group E).
Stack Location
Care is necessary when managing stacks as there
is no limit to stack sizes apart from the bottom of
any address space in which the stack is placed.
Consequently programmers are advised to use a
stack pointer value as high as possible, particular-
ly when using the Register File as a stacking area.
System Stack
The System Stack is used for the temporary stor-
age of system and/or control data, such as the
Flag register and the Program counter.
The following automatically push data onto the
System Stack:
Group D is a good location for a stack in the Reg-
ister File, since it is the highest available area. The
stacks may be located anywhere in the first 14
groups of the Register File (internal stacks) or in
RAM (external stacks).
– Interrupts
When entering an interrupt, the PC and the Flag
Register are pushed onto the System Stack. If the
ENCSR bit in the EMR2 register is set, then the
Note. Stacks must not be located in the Paged
Register Group or in the System Register Group.
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ST92185 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
USER STACK POINTER HIGH REGISTER
(USPHR)
R236 - Read/Write
SYSTEM STACK POINTER HIGH REGISTER
(SSPHR)
R238 - Read/Write
Register Group: E (System)
Reset value: undefined
Register Group: E (System)
Reset value: undefined
7
0
7
0
USP15 USP14 USP13 USP12 USP11 USP10 USP9 USP8
SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8
USER STACK POINTER LOW REGISTER
(USPLR)
R237 - Read/Write
SYSTEM STACK POINTER LOW REGISTER
(SSPLR)
R239 - Read/Write
Register Group: E (System)
Reset value: undefined
Register Group: E (System)
Reset value: undefined
7
0
7
0
USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0
SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Figure 14. Internal Stack Mode
Figure 15. External Stack Mode
REGISTER
FILE
REGISTER
FILE
STACK POINTER (LOW)
STACK POINTER (LOW)
&
points to:
F
F
STACK POINTER (HIGH)
point to:
MEMORY
E
E
STACK
D
D
STACK
4
3
2
1
0
4
3
2
1
0
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ST92185 - DEVICE ARCHITECTURE
2.4 MEMORY ORGANIZATION
Code and data are accessed within the same line-
ar address space. All of the physically separate
memory areas, including the internal ROM, inter-
nal RAM and external memory are mapped in a
common address space.
The mapping of the various memory areas (inter-
nal RAM or ROM, external memory) differs from
device to device. Each 64-Kbyte physical memory
segment is mapped either internally or externally;
if the memory is internal and smaller than 64
Kbytes, the remaining locations in the 64-Kbyte
segment are not used (reserved).
The ST9 provides a total addressable memory
space of 4 Mbytes. This address space is ar-
ranged as 64 segments of 64 Kbytes; each seg-
ment is again subdivided into four 16 Kbyte pages.
Refer to the Register and Memory Map Chapter
for more details on the memory map.
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ST92185 - DEVICE ARCHITECTURE
2.5 MEMORY MANAGEMENT UNIT
The CPU Core includes a Memory Management
Unit (MMU) which must be programmed to per-
form memory accesses (even if external memory
is not used).
sub-divided into 2 main groups: a first group of four
8-bit registers (DPR[3:0]), and a second group of
three 6-bit registers (CSR, ISR, and DMASR). The
first group is used to extend the address during
Data Memory access (DPR[3:0]). The second is
used to manage Program and Data Memory ac-
cesses during Code execution (CSR), Interrupts
Service Routines (ISR or CSR), and DMA trans-
fers (DMASR or ISR).
The MMU is controlled by 7 registers and 2 bits
(ENCSR and DPRREM) present in EMR2, which
may be written and read by the user program.
These registers are mapped within group F, Page
21 of the Register File. The 7 registers may be
Figure 16. Page 21 Registers
Page 21
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
Relocation of P[3:0] and DPR[3:0] Registers
SSPLR
SSPLR
SSPHR
USPLR
USPHR
MODER
PPR
SSPHR
USPLR
USPHR
MODER
PPR
DMASR
ISR
RP1
RP1
DMASR
ISR
DMASR
ISR
MMU
RP0
RP0
FLAGR
CICR
FLAGR
CICR
EMR2
EMR1
CSR
DPR3
DPR2
1
EMR2
EMR1
CSR
P3DR
P2DR
P1DR
P0DR
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
P5DR
P4DR
DPR3
DPR2
DPR1
DPR0
EMR2
EMR1
CSR
EM
MMU
DPR0
DPR3
DPR2
DPR1
DPR0
MMU
Bit DPRREM=0
(default setting)
Bit DPRREM=1
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ST92185 - DEVICE ARCHITECTURE
2.6 ADDRESS SPACE EXTENSION
To manage 4 Mbytes of addressing space, it is
necessary to have 22 address bits. The MMU
adds 6 bits to the usual 16-bit address, thus trans-
lating a 16-bit virtual address into a 22-bit physical
address. There are 2 different ways to do this de-
pending on the memory involved and on the oper-
ation being performed.
are involved in the following virtual address rang-
es:
DPR0: from 0000h to 3FFFh;
DPR1: from 4000h to 7FFFh;
DPR2: from 8000h to BFFFh;
DPR3: from C000h to FFFFh.
2.6.1 Addressing 16-Kbyte Pages
The contents of the selected DPR register specify
one of the 256 possible data memory pages. This
8-bit data page number, in addition to the remain-
ing 14-bit page offset address forms the physical
22-bit address (see Figure 10).
This extension mode is implicitly used to address
Data memory space if no DMA is being performed.
The Data memory space is divided into 4 pages of
16 Kbytes. Each one of the four 8-bit registers
(DPR[3:0], Data Page Registers) selects a differ-
ent 16-Kbyte page. The DPR registers allow ac-
cess to the entire memory space which contains
256 pages of 16 Kbytes.
A DPR register cannot be modified via an address-
ing mode that uses the same DPR register. For in-
stance, the instruction “POPW DPR0” is legal only
if the stack is kept either in the register file or in a
memory location above 8000h, where DPR2 and
DPR3 are used. Otherwise, since DPR0 and
DPR1 are modified by the instruction, unpredicta-
ble behaviour could result.
Data paging is performed by extending the 14 LSB
of the 16-bit address with the contents of a DPR
register. The two MSBs of the 16-bit address are
interpreted as the identification number of the DPR
register to be used. Therefore, the DPR registers
Figure 17. Addressing via DPR[3:0]
16-bit virtual address
MMU registers
DPR0
00
DPR1
01
DPR2
10
DPR3
11
8 bits
14 LSB
22-bit physical address
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ST92185 - DEVICE ARCHITECTURE
ADDRESS SPACE EXTENSION (Cont’d)
2.6.2 Addressing 64-Kbyte Segments
Most of these registers do not have a default value
after reset.
This extension mode is used to address Data
memory space during a DMA and Program mem-
ory space during any code execution (normal code
and interrupt routines).
2.7.1 DPR[3:0]: Data Page Registers
The DPR[3:0] registers allow access to the entire 4
Mbyte memory space composed of 256 pages of
16 Kbytes.
Three registers are used: CSR, ISR, and DMASR.
The 6-bit contents of one of the registers CSR,
ISR, or DMASR define one out of 64 Memory seg-
ments of 64 Kbytes within the 4 Mbytes address
space. The register contents represent the 6
MSBs of the memory address, whereas the 16
LSBs of the address (intra-segment address) are
given by the virtual 16-bit address (see Figure 11).
2.7.1.1 Data Page Register Relocation
If these registers are to be used frequently, they
may be relocated in register group E, by program-
ming bit 5 of the EMR2-R246 register in page 21. If
this bit is set, the DPR[3:0] registers are located at
R224-227 in place of the Port 0-3 Data Registers,
which are re-mapped to the default DPR's loca-
tions: R240-243 page 21.
2.7 MMU REGISTERS
The MMU uses 7 registers mapped into Group F,
Page 21 of the Register File and 2 bits of the
EMR2 register.
Data Page Register relocation is illustrated in Fig-
ure 9.
Figure 18. Addressing via CSR, ISR, and DMASR
16-bit virtual address
MMU registers
ISR
DMASR
CSR
1
2
3
1
2
Fetching program
instruction
Data Memory
accessed in DMA
6 bits
Fetching interrupt
instruction or DMA
3
access to Program
Memory
22-bit physical address
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ST92185 - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
DATA PAGE REGISTER 0 (DPR0)
R240 - Read/Write
DATA PAGE REGISTER 2 (DPR2)
R242 - Read/Write
Register Page: 21
Register Page: 21
Reset value: undefined
Reset value: undefined
This register is relocated to R224 if EMR2.5 is set.
This register is relocated to R226 if EMR2.5 is set.
7
0
7
0
DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0
DPR2_7 DPR2_6 DPR2_5 DPR2_4 DPR2_3 DPR2_2 DPR2_1 DPR2_0
Bits 7:0 = DPR0_[7:0]: These bits define the 16-
Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to ex-
tend the address during a Data Memory access.
The DPR0 register is used when addressing the
virtual address range 0000h-3FFFh.
Bits 7:0 = DPR2_[7:0]: These bits define the 16-
Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR2 register is involved when the virtual address
is in the range 8000h-BFFFh.
DATA PAGE REGISTER 1 (DPR1)
R241 - Read/Write
DATA PAGE REGISTER 3 (DPR3)
R243 - Read/Write
Register Page: 21
Register Page: 21
Reset value: undefined
Reset value: undefined
This register is relocated to R225 if EMR2.5 is set.
This register is relocated to R227 if EMR2.5 is set.
7
0
7
0
DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0
DPR3_7 DPR3_6 DPR3_5 DPR3_4 DPR3_3 DPR3_2 DPR3_1 DPR3_0
Bits 7:0 = DPR1_[7:0]: These bits define the 16-
Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to ex-
tend the address during a Data Memory access.
The DPR1 register is used when addressing the
virtual address range 4000h-7FFFh.
Bits 7:0 = DPR3_[7:0]: These bits define the 16-
Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR3 register is involved when the virtual address
is in the range C000h-FFFFh.
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ST92185 - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
2.7.2 CSR: Code Segment Register
ISR and ENCSR bit (EMR2 register) are also de-
scribed in the chapter relating to Interrupts, please
refer to this description for further details.
This register selects the 64-Kbyte code segment
being used at run-time to access instructions. It
can also be used to access data if the spminstruc-
tion has been executed (or ldpp, ldpd, lddp).
Only the 6 LSBs of the CSR register are imple-
mented, and bits 6 and 7 are reserved. The CSR
register allows access to the entire memory space,
divided into 64 segments of 64 Kbytes.
Bits 7:6 = Reserved, keep in reset state.
Bits 5:0 = ISR_[5:0]: These bits define the 64-
Kbyte memory segment (among 64) which con-
tains the interrupt vector table and the code for in-
terrupt service routines and DMA transfers (when
the PS bit of the DAPR register is reset). These
bits are used as the most significant address bits
(A21-16). The ISR is used to extend the address
space in two cases:
To generate the 22-bit Program memory address,
the contents of the CSR register is directly used as
the 6 MSBs, and the 16-bit virtual address as the
16 LSBs.
Note: The CSR register should only be read and
not written for data operations (there are some ex-
ceptions which are documented in the following
paragraph). It is, however, modified either directly
by means of the jps and calls instructions, or
indirectly via the stack, by means of the retsin-
struction.
– Whenever an interrupt occurs: ISR points to the
64-Kbyte memory segment containing the inter-
rupt vector table and the interrupt service routine
code. See also the Interrupts chapter.
– During DMA transactions between the peripheral
and memory when the PS bit of the DAPR regis-
ter is reset : ISR points to the 64 K-byte Memory
segment that will be involved in the DMA trans-
action.
CODE SEGMENT REGISTER (CSR)
R244 - Read/Write
Register Page: 21
Reset value: 0000 0000 (00h)
7
0
0
2.7.4 DMASR: DMA Segment Register
DMA SEGMENT REGISTER (DMASR)
R249 - Read/Write
Register Page: 21
Reset value: undefined
0
CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 CSR_0
Bits 7:6 = Reserved, keep in reset state.
7
0
0
Bits 5:0 = CSR_[5:0]: These bits define the 64-
Kbyte memory segment (among 64) which con-
tains the code being executed. These bits are
used as the most significant address bits (A21-16).
DMA
DMA
DMA
DMA
DMA
DMA
0
SR_5 SR_4 SR_3 SR_2 SR_1 SR_0
Bits 7:6 = Reserved, keep in reset state.
2.7.3 ISR: Interrupt Segment Register
INTERRUPT SEGMENT REGISTER (ISR)
R248 - Read/Write
Bits 5:0 = DMASR_[5:0]: These bits define the 64-
Kbyte Memory segment (among 64) used when a
DMA transaction is performed between the periph-
eral's data register and Memory, with the PS bit of
the DAPR register set. These bits are used as the
most significant address bits (A21-16). If the PS bit
is reset, the ISR register is used to extend the ad-
dress.
Register Page: 21
Reset value: undefined
7
0
0
0
ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
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ST92185 - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
Figure 19. Memory Addressing Scheme (example)
4M bytes
3FFFFFh
294000h
16K
DPR3
DPR2
DPR1
DPR0
240000h
23FFFFh
20C000h
16K
16K
200000h
1FFFFFh
040000h
03FFFFh
64K
64K
030000h
DMASR
020000h
ISR
010000h
00C000h
16K
64K
CSR
000000h
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ST92185 - DEVICE ARCHITECTURE
2.8 MMU USAGE
2.8.1 Normal Program Execution
Program memory is organized as a set of 64-
Kbyte segments. The program can span as many
segments as needed, but a procedure cannot
stretch across segment boundaries. jps, calls
and retsinstructions, which automatically modify
the CSR, must be used to jump across segment
boundaries. Writing to the CSR is forbidden during
normal program execution because it is not syn-
chronized with the opcode fetch. This could result
in fetching the first byte of an instruction from one
memory segment and the second byte from anoth-
er. Writing to the CSR is allowed when it is not be-
ing used, i.e during an interrupt service routine if
ENCSR is reset.
used instead of the CSR, and the interrupt stack
frame is kept exactly as in the original ST9 (only
the PC and flags are pushed). This avoids the
need to save the CSR on the stack in the case of
an interrupt, ensuring a fast interrupt response
time. The drawback is that it is not possible for an
interrupt service routine to perform segment
calls/jps: these instructions would update the
CSR, which, in this case, is not used (ISR is used
instead). The code size of all interrupt service rou-
tines is thus limited to 64 Kbytes.
If, instead, bit 6 of the EMR2 register is set, the
ISR is used only to point to the interrupt vector ta-
ble and to initialize the CSR at the beginning of the
interrupt service routine: the old CSR is pushed
onto the stack together with the PC and the flags,
and then the CSR is loaded with the ISR. In this
case, an iret will also restore the CSR from the
stack. This approach lets interrupt service routines
access the whole 4-Mbyte address space. The
drawback is that the interrupt response time is
slightly increased, because of the need to also
save the CSR on the stack. Compatibility with the
original ST9 is also lost in this case, because the
interrupt stack frame is different; this difference,
however, would not be noticeable for a vast major-
ity of programs.
Note that a routine must always be called in the
same way, i.e. either always with callor always
with calls, depending on whether the routine
ends with ret or rets. This means that if the rou-
tine is written without prior knowledge of the loca-
tion of other routines which call it, and all the pro-
gram code does not fit into a single 64-Kbyte seg-
ment, then calls/retsshould be used.
In typical microcontroller applications, less than 64
Kbytes of RAM are used, so the four Data space
pages are normally sufficient, and no change of
DPR[3:0] is needed during Program execution. It
may be useful however to map part of the ROM
into the data space if it contains strings, tables, bit
maps, etc.
Data memory mapping is independent of the value
of bit 6 of the EMR2 register, and remains the
same as for normal code execution: the stack is
the same as that used by the main program, as in
the ST9. If the interrupt service routine needs to
access additional Data memory, it must save one
(or more) of the DPRs, load it with the needed
memory page and restore it before completion.
If there is to be frequent use of paging, the user
can set bit 5 (DPRREM) in register R246 (EMR2)
of Page 21. This swaps the location of registers
DPR[3:0] with that of the data registers of Ports 0-
3. In this way, DPR registers can be accessed
without the need to save/set/restore the Page
Pointer Register. Port registers are therefore
moved to page 21. Applications that require a lot of
paging typically use more than 64 Kbytes of exter-
nal memory, and as ports 0, 1 and 2 are required
to address it, their data registers are unused.
2.8.3 DMA
Depending on the PS bit in the DAPR register (see
DMA chapter) DMA uses either the ISR or the
DMASR for memory accesses: this guarantees
that a DMA will always find its memory seg-
ment(s), no matter what segment changes the ap-
plication has performed. Unlike interrupts, DMA
transactions cannot save/restore paging registers,
so a dedicated segment register (DMASR) has
been created. Having only one register of this kind
means that all DMA accesses should be pro-
grammed in one of the two following segments:
the one pointed to by the ISR (when the PS bit of
the DAPR register is reset), and the one refer-
enced by the DMASR (when the PS bit is set).
2.8.2 Interrupts
The ISR register has been created so that the in-
terrupt routines may be found by means of the
same vector table even after a segment jump/call.
When an interrupt occurs, the CPU behaves in
one of 2 ways, depending on the value of the ENC-
SR bit in the EMR2 register (R246 on Page 21).
If this bit is reset (default condition), the CPU
works in original ST9 compatibility mode. For the
duration of the interrupt service routine, the ISR is
41/178
ST92185 - INTERRUPTS
3 INTERRUPTS
3.1 INTRODUCTION
3.2 INTERRUPT VECTORING
The ST9 responds to peripheral and external
events through its interrupt channels. Current pro-
gram execution can be suspended to allow the
ST9 to execute a specific response routine when
such an event occurs, providing that interrupts
have been enabled, and according to a priority
mechanism. If an event generates a valid interrupt
request, the current program status is saved and
control passes to the appropriate Interrupt Service
Routine.
The ST9 implements an interrupt vectoring struc-
ture which allows the on-chip peripheral to identify
the location of the first instruction of the Interrupt
Service Routine automatically.
When an interrupt request is acknowledged, the
peripheral interrupt module provides, through its
Interrupt Vector Register (IVR), a vector to point
into the vector table of locations containing the
start addresses of the Interrupt Service Routines
(defined by the programmer).
The ST9 CPU can receive requests from the fol-
lowing sources:
Each peripheral has a specific IVR mapped within
its Register File pages.
– On-chip peripherals
The Interrupt Vector table, containing the address-
es of the Interrupt Service Routines, is located in
the first 256 locations of Memory pointed to by the
ISR register, thus allowing 8-bit vector addressing.
For a description of the ISR register refer to the
chapter describing the MMU.
– External pins
– Top-Level Pseudo-non-maskable interrupt
According to the on-chip peripheral features, an
event occurrence can generate an Interrupt re-
quest which depends on the selected mode.
The user Power on Reset vector is stored in the
first two physical bytes in memory, 000000h and
000001h.
Up to eight external interrupt channels, with pro-
grammable input trigger edge, are available. In ad-
dition, a dedicated interrupt channel, set to the
Top-level priority, can be devoted either to the ex-
ternal NMI pin (where available) to provide a Non-
Maskable Interrupt, or to the Timer/Watchdog. In-
terrupt service routines are addressed through a
vector table mapped in Memory.
The Top Level Interrupt vector is located at ad-
dresses 0004h and 0005h in the segment pointed
to by the Interrupt Segment Register (ISR).
With one Interrupt Vector register, it is possible to
address several interrupt service routines; in fact,
peripherals can share the same interrupt vector
register among several interrupt channels. The
most significant bits of the vector are user pro-
grammable to define the base vector address with-
in the vector table, the least significant bits are
controlled by the interrupt module, in hardware, to
select the appropriate vector.
Figure 20. Interrupt Response
n
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
Note: The first 256 locations of the memory seg-
ment pointed to by ISR can contain program code.
3.2.1 Divide by Zero trap
CLEAR
The Divide by Zero trap vector is located at ad-
dresses 0002h and 0003h of each code segment;
it should be noted that for each code segment a
Divide by Zero service routine is required.
INTERRUPT
PENDING BIT
IRET
INSTRUCTION
Warning. Although the Divide by Zero Trap oper-
ates as an interrupt, the FLAG Register is not
pushed onto the system Stack automatically. As a
result it must be regarded as a subroutine, and the
service routine must end with the RETinstruction
(not IRET).
VR001833
42/178
ST92185 - INTERRUPTS
INTERRUPT VECTORING (Cont’d)
3.2.2 Segment Paging During Interrupt
Routines
3.3 INTERRUPT PRIORITY LEVELS
The ST9 supports a fully programmable interrupt
priority structure. Nine priority levels are available
to define the channel priority relationships:
The ENCSR bit in the EMR2 register can be used
to select between original ST9 backward compati-
bility mode and ST9+ interrupt management
mode.
– The on-chip peripheral channels and the eight
external interrupt sources can be programmed
within eight priority levels. Each channel has a 3-
bit field, PRL (Priority Level), that defines its pri-
ority level in the range from 0 (highest priority) to
7 (lowest priority).
ST9 backward compatibility mode (ENCSR = 0)
If ENCSR is reset, the CPU works in original ST9
compatibility mode. For the duration of the inter-
rupt service routine, ISR is used instead of CSR,
and the interrupt stack frame is identical to that of
the original ST9: only the PC and Flags are
pushed.
– The 9th level (Top Level Priority) is reserved for
the Timer/Watchdog or the External Pseudo
Non-Maskable Interrupt. An Interrupt service
routine at this level cannot be interrupted in any
arbitration mode. Its mask can be both maskable
(TLI) or non-maskable (TLNM).
This avoids saving the CSR on the stack in the
event of an interrupt, thus ensuring a faster inter-
rupt response time.
3.4 PRIORITY LEVEL ARBITRATION
It is not possible for an interrupt service routine to
perform inter-segment calls or jumps: these in-
structions would update the CSR, which, in this
case, is not used (ISR is used instead). The code
segment size for all interrupt service routines is
thus limited to 64K bytes.
The 3 bits of CPL (Current Priority Level) in the
Central Interrupt Control Register contain the pri-
ority of the currently running program (CPU priori-
ty). CPL is set to 7 (lowest priority) upon reset and
can be modified during program execution either
by software or automatically by hardware accord-
ing to the selected Arbitration Mode.
ST9+ mode (ENCSR = 1)
During every instruction, an arbitration phase
takes place, during which, for every channel capa-
ble of generating an Interrupt, each priority level is
compared to all the other requests (interrupts or
DMA).
If ENCSR is set, ISR is only used to point to the in-
terrupt vector table and to initialize the CSR at the
beginning of the interrupt service routine: the old
CSR is pushed onto the stack together with the PC
and flags, and CSR is then loaded with the con-
tents of ISR.
If the highest priority request is an interrupt, its
PRL value must be strictly lower (that is, higher pri-
ority) than the CPL value stored in the CICR regis-
ter (R230) in order to be acknowledged. The Top
Level Interrupt overrides every other priority.
In this case, iretwill also restore CSR from the
stack. This approach allows interrupt service rou-
tines to access the entire 4 Mbytes of address
space. The drawback is that the interrupt response
time is slightly increased, because of the need to
also save CSR on the stack.
3.4.1 Priority level 7 (Lowest)
Interrupt requests at PRL level 7 cannot be ac-
knowledged, as this PRL value (the lowest possi-
ble priority) cannot be strictly lower than the CPL
value. This can be of use in a fully polled interrupt
environment.
Full compatibility with the original ST9 is lost in this
case, because the interrupt stack frame is differ-
ent.
3.4.2 Maximum depth of nesting
ENCSR Bit
Mode
Pushed/Popped
Registers
0
1
No more than 8 routines can be nested. If an inter-
rupt routine at level N is being serviced, no other
Interrupts located at level N can interrupt it. This
guarantees a maximum number of 8 nested levels
including the Top Level Interrupt request.
ST9 Compatible
ST9+
PC, FLAGR,
CSR
PC, FLAGR
Max. Code Size
for interrupt
service routine
64KB
No limit
Within 1 segment Across segments
43/178
ST92185 - INTERRUPTS
PRIORITY LEVEL ARBITRATION (Cont’d)
3.4.3 Simultaneous Interrupts
The IAM control bit in the CICR Register selects
Concurrent Arbitration mode or Nested Arbitration
Mode.
If two or more requests occur at the same time and
at the same priority level, an on-chip daisy chain,
specific to every ST9 version, selects the channel
3.5.1 Concurrent Mode
with the highest position in the chain, as shown in
Table 5.
This mode is selected when the IAM bit is cleared
(reset condition). The arbitration phase, performed
during every instruction, selects the request with
the highest priority level. The CPL value is not
modified in this mode.
Table 5. Daisy Chain Priority for the ST92185B
Highest Position
INTA0 INT0/WDT
INTA1 INT1/Standard Timer
INTB0 INT2/SPI
INTB1 INT3/AD Converter
INTC0 INT4/SYNC (EOFVBI)
INTC1 INT5/SYNC (FLDST)
INTD0 INT6
Start of Interrupt Routine
The interrupt cycle performs the following steps:
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
Lowest Position
INTD1 INT7
– If ENCSR is set, CSR is pushed onto system
stack.
3.4.4 Dynamic Priority Level Modification
The main program and routines can be specifically
prioritized. Since the CPL is represented by 3 bits
in a read/write register, it is possible to modify dy-
namically the current priority value during program
execution. This means that a critical section can
have a higher priority with respect to other inter-
rupt requests. Furthermore it is possible to priori-
tize even the Main Program execution by modify-
ing the CPL during its execution. See Figure 21
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwise ISR is used in place of CSR until
iretinstruction.
End of Interrupt Routine
The Interrupt Service Routine must be ended with
the iret instruction. The iret instruction exe-
cutes the following operations:
Figure 21. Example of Dynamic priority
level modification in Nested Mode
INTERRUPT 6 HAS PRIORITY LEVEL 6
Priority Level
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
CPL is set to 7
4
by MAIN program
ei
INT6
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
5
6
7
MAIN
CPL is set to 5
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
CPL6 > CPL5:
INT6 pending
INT 6
– If ENCSR is reset, CSR is used instead of ISR.
CPL=6
Normal program execution thus resumes at the in-
terrupted instruction. All pending interrupts remain
pending until the next ei instruction (even if it is
executed during the interrupt service routine).
MAIN
CPL=7
Note: In Concurrent mode, the source priority level
is only useful during the arbitration phase, where it
is compared with all other priority levels and with
the CPL. No trace is kept of its value during the
ISR. If other requests are issued during the inter-
rupt service routine, once the global CICR.IEN is
re-enabled, they will be acknowledged regardless
of the interrupt service routine’s priority. This may
cause undesirable interrupt response sequences.
3.5 ARBITRATION MODES
The ST9 provides two interrupt arbitration modes:
Concurrent mode and Nested mode. Concurrent
mode is the standard interrupt arbitration mode.
Nested mode improves the effective interrupt re-
sponse time when service routine nesting is re-
quired, depending on the request priority levels.
44/178
ST92185 - INTERRUPTS
ARBITRATION MODES (Cont’d)
Examples
Example 1
In the following two examples, three interrupt re-
quests with different priority levels (2, 3 & 4) occur
simultaneously during the interrupt 5 service rou-
tine.
In the first example, (simplest case, Figure 22) the
eiinstruction is not used within the interrupt serv-
ice routines. This means that no new interrupt can
be serviced in the middle of the current one. The
interrupt routines will thus be serviced one after
another, in the order of their priority, until the main
program eventually resumes.
Figure 22. Simple Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected and
- IEN unchanged by the interrupt routines
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
0
1
2
3
4
5
6
7
Priority Level of
Interrupt Request
INT 2
CPL = 7
INT 3
CPL = 7
INT 2
INT 3
INT 4
INT 4
CPL = 7
INT 5
CPL = 7
ei
INT 5
MAIN
MAIN
CPL = 7
CPL is set to 7
45/178
ST92185 - INTERRUPTS
ARBITRATION MODES (Cont’d)
Example 2
In the second example, (more complex, Figure
23), each interrupt service routine sets Interrupt
Enable with the eiinstruction at the beginning of
the routine. Placed here, it minimizes response
time for requests with a higher priority than the one
being serviced.
ice routines being executed in the opposite order
of their priority.
It is therefore recommended to avoid inserting
the eiinstruction in the interrupt service rou-
tine in Concurrent mode. Use the ei instruc-
tion only in nested mode.
The level 2 interrupt routine (with the highest prior-
ity) will be acknowledged first, then, when the ei
instruction is executed, it will be interrupted by the
level 3 interrupt routine, which itself will be inter-
rupted by the level 4 interrupt routine. When the
level 4 interrupt routine is completed, the level 3 in-
terrupt routine resumes and finally the level 2 inter-
rupt routine. This results in the three interrupt serv-
WARNING: If, in Concurrent Mode, interrupts are
nested (by executing ei in an interrupt service
routine), make sure that either ENCSR is set or
CSR=ISR, otherwise the iretof the innermost in-
terrupt will make the CPU use CSR instead of ISR
before the outermost interrupt service routine is
terminated, thus making the outermost routine fail.
Figure 23. Complex Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected
- IEN set to 1 during interrupt service routine execution
0
Priority Level of
INTERRUPT 2 HAS PRIORITY LEVEL 2
Interrupt Request
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
1
2
3
4
5
6
7
INT 2
INT 2
CPL = 7
CPL = 7
INT 3
CPL = 7
INT 3
CPL = 7
ei
INT 2
INT 3
INT 4
ei
ei
INT 4
CPL = 7
INT 5
INT 5
CPL = 7
CPL = 7
ei
ei
INT 5
MAIN
MAIN
CPL is set to 7
CPL = 7
46/178
ST92185 - INTERRUPTS
ARBITRATION MODES (Cont’d)
3.5.2 Nested Mode
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
The difference between Nested mode and Con-
current mode, lies in the modification of the Cur-
rent Priority Level (CPL) during interrupt process-
ing.
– CPL is saved in the special NICR stack to hold
the priority level of the suspended routine.
– Priority level of the acknowledged routine is
stored in CPL, so that the next request priority
will be compared with the one of the routine cur-
rently being serviced.
The arbitration phase is basically identical to Con-
current mode, however, once the request is ac-
knowledged, the CPL is saved in the Nested Inter-
rupt Control Register (NICR) by setting the NICR
bit corresponding to the CPL value (i.e. if the CPL
is 3, the bit 3 will be set).
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
stack.
The CPL is then loaded with the priority of the re-
quest just acknowledged; the next arbitration cycle
is thus performed with reference to the priority of
the interrupt service routine currently being exe-
cuted.
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
Start of Interrupt Routine
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwise ISR is used in place of CSR until
iretinstruction.
The interrupt cycle performs the following steps:
Figure 24. Simple Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN unchanged by the interrupt routines
Priority Level of
Interrupt Request
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
INT 0
CPL=0
0
1
2
3
4
CPL6 > CPL3:
INT6 pending
INT0
INT 2
CPL=2
INT 2
CPL=2
INT6
INT 3
INT2
CPL=3
INT2
INT3
INT4
INT 4
CPL=4
CPL2 < CPL4:
Serviced next
5
INT 5
CPL=5
ei
6
INT 6
CPL=6
INT5
7
MAIN
MAIN
CPL is set to 7
CPL=7
47/178
ST92185 - INTERRUPTS
ARBITRATION MODES (Cont’d)
End of Interrupt Routine
– If ENCSR is reset, CSR is used instead of ISR,
unless the program returns to another nested
routine.
The iret Interrupt Return instruction executes
the following steps:
The suspended routine thus resumes at the inter-
rupted instruction.
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
Figure 24 contains a simple example, showing that
if the ei instruction is not used in the interrupt
service routines, nested and concurrent modes
are equivalent.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
Figure 25 contains a more complex example
showing how nested mode allows nested interrupt
processing (enabled inside the interrupt service
routinesi using the ei instruction) according to
their priority level.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
– The priority level of the interrupted routine is
popped from the special register (NICR) and
copied into CPL.
Figure 25. Complex Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN set to 1 during the interrupt routine execution
Priority Level of
Interrupt Request
0
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
INT 0
CPL=0
CPL6 > CPL3:
INT6 pending
1
2
3
INT0
INT 2
INT 2
INT 2
CPL=2
INT6
CPL=2
CPL=2
INT 3
ei
INT2
CPL=3
ei
INT2
INT3
INT4
4
5
6
7
INT 4
CPL=4
INT 4
CPL=4
CPL2 < CPL4:
Serviced just after ei
ei
INT 5
CPL=5
INT 5
CPL=5
ei
INT 6
CPL=6
ei
INT5
MAIN
CPL is set to 7
MAIN
CPL=7
48/178
ST92185 - INTERRUPTS
3.6 EXTERNAL INTERRUPTS
The standard ST9 core contains 8 external inter-
rupts sources grouped into four pairs.
Figure 26 shows an example of priority levels.
Figure 27 gives an overview of the External inter-
rupt control bits and vectors.
Table 6. External Interrupt Channel Grouping
– The source of the interrupt channel INTA0 can
be selected between the external pin INT0 (when
IA0S = “1”, the reset value) or the On-chip Timer/
Watchdog peripheral (when IA0S = “0”).
External Interrupt
Channel
INT7
INT6
INTD1
INTD0
INT5
INT4
INTC1
INTC0
– INTA1: by selecting INTS equal to 0, the stand-
ard Timer is chosen as the interrupt.
INT3
INT2
INTB1
INTB0
– The source of the interrupt channel INTB0 can
be selected between the external pin INT2 (when
(SPEN,BMS)=(0,0)) or the SPI peripheral.
INT1
INT0
INTA1
INTA0
– INTB1: setting AD-INT.0 to 1 selects the ADC as
the interrupt source for channel INTB1.
Each source has a trigger control bit TEA0,..TED1
(R242,EITR.0,..,7 Page 0) to select triggering on
the rising or falling edge of the external pin. If the
Trigger control bit is set to “1”, the corresponding
pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page
0) is set on the input pin rising edge, if it is cleared,
the pending bit is set on the falling edge of the in-
put pin. Each source can be individually masked
– Setting bit 2 of the CSYCT to 1 selects EOFVBI
interrupt as the source for INTC0. Setting this bit
to 0 selects external interrupt on INT4.
– Setting FSTEN (bit 3 of the CSYCT register) to 1
selects FLDST interrupt for channel INTC1. Set-
ting this bit to 0 selects external interrupt INT5.
through
the
corresponding
control
bit
Interrupt channels INTD0 and INTD1 have an in-
put pin as source. However, the input line may be
multiplexed with an on-chip peripheral I/O or con-
nected to an input pin that performs also another
function.
IMA0,..,IMD1 (EIMR.7,..,0). See Figure 27.
The priority level of the external interrupt sources
can be programmed among the eight priority lev-
els with the control register EIPLR (R245). The pri-
ority level of each pair is software defined using
the bits PRL2, PRL1. For each pair, the even
channel (A0,B0,C0,D0) of the group has the even
priority level and the odd channel (A1,B1,C1,D1)
has the odd (lower) priority level.
Warning: When using channels shared by both
external interrupts and peripherals, special care
must be taken to configure their control registers
for both peripherals and interrupts.
Table 7. Internal/External Interrupt Source
Figure 26. Priority Level Examples
Internal Interrupt
Source
External Interrupt
Source
Channel
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
1
0
0
0
1
0
0
1
EIPLR
INTA0
INTA1
INTB0
INTB1
Timer/Watchdog
Standard Timer
SPI Interrupt
INT0
None
INT2
None
SOURCE PRIORITY
SOURCE PRIORITY
INT.D0: 100=4
INT.D1: 101=5
INT.A0: 010=2
INT.A1: 011=3
A/D Converter
EOFVBI
(SYNC inter)
INTC0
INTC1
INT4
INT5
INT.C0: 000=0
INT.C1: 001=1
INT.B0: 100=4
INT.B1: 101=5
FLDST
(SYNC inter)
VR000151
n
INTD0
INTD1
none
none
INT6
INT7
49/178
ST92185 - INTERRUPTS
EXTERNAL INTERRUPTS (Cont’d)
Figure 27. External Interrupts Control Bits and
Vectors
n
Watchdog/Timer
End of count
IA0S
TEA0
V6
V7
V5 V4 0
0
0
0
VECTOR
“0”
“1”
Priority level
PL2A PL1A
0
INT A0
request
Mask bit
Pending bit IPA0
IMA0
INT 0 pin
INT 2 pin
INT 4 pin
*
INTS
V6
V7
V5 V4 0
0
0
1
Std. Timer
Not connected
VECTOR
“0”
Priority level
INT A1
request
PL2A PL1A
1
“1”
Mask bit
Pending bit IPA1
IMA1
SPEN,BMS
TEB0
SPI Interrupt
V6
V7
PL2B PL1B
V5 V4 0
1
0
0
VECTOR
Priority level
“1,x”
“0,0”
0
INT B0
request
Mask bit
Pending bit IPB0
IMB0
*
ADINT
V6
V7
V5 V4 0
1
0
1
VECTOR
Priority level
ADC
Not connected
“0”
“1”
PL2B PL1B
INT B1
request
1
Mask bit
IMB1
Pending bit IPB1
VBEN
“1”
EOFVBI
(SYNC inter)
TEC0
V6
V7
PL2C PL1C
V5 V4 1
0
0
0
VECTOR
Priority level
INT C0
request
0
Pending bit IPC0
Mask bit
“0”
IMC0
FSTEN
TEC1
FLDST
(SYNC inter)
V6
V7
V5 V4 1
0
0
1
VECTOR
Priority level
“1”
“0”
INT C1
request
PL2C PL1C
1
INT 5 pin
INT 6 pin
Pending bit IPC1
Mask bit
IMC1
TED0
TED1
V6
V7
PL2D PL1D
V5 V4 1
1
0
0
VECTOR
Priority level
0
INT D0
request
Mask bit
IMD0
Pending bit IPD0
V6
V7
V5 V4 1
1
0
1
VECTOR
Priority level
INT D1
request
PL2D PL1D
1
INT 7 pin
Mask bit
IMD1
Pending bit IPD1
*
Shared channels, see warning
n
50/178
ST92185 - INTERRUPTS
3.7 TOP LEVEL INTERRUPT
The Top Level Interrupt channel can be assigned
either to the external pin NMI or to the Timer/
Watchdog according to the status of the control bit
EIVR.TLIS (R246.2, Page 0). If this bit is high (the
reset condition) the source is the external pin NMI.
If it is low, the source is the Timer/ Watchdog End
Of Count. When the source is the NMI external
pin, the control bit EIVR.TLTEV (R246.3; Page 0)
selects between the rising (if set) or falling (if reset)
edge generating the interrupt request. When the
selected event occurs, the CICR.TLIP bit (R230.6)
is set. Depending on the mask situation, a Top
Level Interrupt request may be generated. Two
kinds of masks are available, a Maskable mask
and a Non-Maskable mask. The first mask is the
CICR.TLI bit (R230.5): it can be set or cleared to
enable or disable respectively the Top Level Inter-
rupt request. If it is enabled, the global Enable In-
terrupt bit, CICR.IEN (R230.4) must also be ena-
bled in order to allow a Top Level Request.
Warning. The interrupt machine cycle of the Top
Level Interrupt does not clear the CICR.IEN bit,
and the corresponding iretdoes not set it. Fur-
thermore the TLI never modifies the CPL bits and
the NICR register.
3.8 ON-CHIP PERIPHERAL INTERRUPTS
The general structure of the peripheral interrupt
unit is described here, however each on-chip pe-
ripheral has its own specific interrupt unit contain-
ing one or more interrupt channels, or DMA chan-
nels. Please refer to the specific peripheral chap-
ter for the description of its interrupt features and
control registers.
The on-chip peripheral interrupt channels provide
the following control bits:
– Interrupt Pending bit (IP). Set by hardware
when the Trigger Event occurs. Can be set/
cleared by software to generate/cancel pending
interrupts and give the status for Interrupt polling.
The second mask NICR.TLNM (R247.7) is a set-
only mask. Once set, it enables the Top Level In-
terrupt request independently of the value of
CICR.IEN and it cannot be cleared by the pro-
gram. Only the processor RESET cycle can clear
this bit. This does not prevent the user from ignor-
ing some sources due to a change in TLIS.
– Interrupt Mask bit (IM). If IM = “0”, no interrupt
request is generated. If IM =“1” an interrupt re-
quest is generated whenever IP = “1” and
CICR.IEN = “1”.
– Priority Level (PRL, 3 bits). These bits define
the current priority level, PRL=0: the highest pri-
ority, PRL=7: the lowest priority (the interrupt
cannot be acknowledged)
The Top Level Interrupt Service Routine cannot be
interrupted by any other interrupt or DMA request,
in any arbitration mode, not even by a subsequent
Top Level Interrupt request.
– Interrupt Vector Register (IVR, up to 7 bits).
The IVR points to the vector table which itself
contains the interrupt routine start address.
Figure 28. Top Level Interrupt Structure
n
WATCHDOG ENABLE
WDEN
CORE
RESET
TLIP
WATCHDOG TIMER
END OF COUNT
PENDING
TOP LEVEL
MUX
INTERRUPT
REQUEST
MASK
OR
NMI
TLIS
TLTEV
TLNM
TLI
VA00294
IEN
n
51/178
ST92185 - INTERRUPTS
3.9 INTERRUPT RESPONSE TIME
cycles (DIVWS and MUL instructions) or 49 for
other instructions.
The interrupt arbitration protocol functions com-
pletely asynchronously from instruction flow and
requires 5 clock cycles. One more CPUCLK cycle
is required when an interrupt is acknowledged.
Requests are sampled every 5 CPUCLK cycles.
For a non-maskable Top Level interrupt, the re-
sponse time between a user event and the start of
the interrupt service routine can range from a min-
imum of 22 clock cycles to a maximum of 51 clock
cycles (DIV instruction), 49 clock cycles (DIVWS
and MUL instructions) or 45 for other instructions.
If the interrupt request comes from an external pin,
the trigger event must occur a minimum of one
INTCLK cycle before the sampling time.
In order to guarantee edge detection, input signals
must be kept low/high for a minimum of one
INTCLK cycle.
When an arbitration results in an interrupt request
being generated, the interrupt logic checks if the
current instruction (which could be at any stage of
execution) can be safely aborted; if this is the
case, instruction execution is terminated immedi-
ately and the interrupt request is serviced; if not,
the CPU waits until the current instruction is termi-
nated and then services the request. Instruction
execution can normally be aborted provided no
write operation has been performed.
An interrupt machine cycle requires a basic 18 in-
ternal clock cycles (CPUCLK), to which must be
added a further 2 clock cycles if the stack is in the
Register File. 2 more clock cycles must further be
added if the CSR is pushed (ENCSR =1).
The interrupt machine cycle duration forms part of
the two examples of interrupt response time previ-
ously quoted; it includes the time required to push
values on the stack, as well as interrupt vector
handling.
For an interrupt deriving from an external interrupt
channel, the response time between a user event
and the start of the interrupt service routine can
range from a minimum of 26 clock cycles to a max-
imum of 55 clock cycles (DIV instruction), 53 clock
In Wait for Interrupt mode, a further cycle is re-
quired as wake-up delay.
52/178
ST92185 - INTERRUPTS
3.10 INTERRUPT REGISTERS
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
the IEN bit when interrupts are disabled or when
no peripheral can generate interrupts. For exam-
ple, if the state of IEN is not known in advance,
and its value must be restored from a previous
push of CICR on the stack, use the sequence DI;
POP CICRto make sure that no interrupts are be-
ing arbitrated when CICR is modified.
R230 - Read/Write
Register Group: System
Reset value: 1000 0111 (87h)
7
0
GCEN TLIP TLI
IEN IAM CPL2 CPL1 CPL0
Bit 3 = IAM: Interrupt Arbitration Mode.
This bit is set and cleared by software.
0: Concurrent Mode
Bit 7 = GCEN: Global Counter Enable.
This bit enables the 16-bit Multifunction Timer pe-
ripheral.
1: Nested Mode
0: MFT disabled
Bit 2:0 = CPL[2:0]: Current Priority Level.
These bits define the Current Priority Level.
CPL=0 is the highest priority. CPL=7 is the lowest
priority. These bits may be modified directly by the
interrupt hardware when Nested Interrupt Mode is
used.
1: MFT enabled
Bit 6 = TLIP: Top Level Interrupt Pending.
This bit is set by hardware when Top Level Inter-
rupt (TLI) trigger event occurs. It is cleared by
hardware when a TLI is acknowledged. It can also
be set by software to implement a software TLI.
0: No TLI pending
EXTERNAL INTERRUPT TRIGGER REGISTER
(EITR)
R242 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
1: TLI pending
Bit 5 = TLI: Top Level Interrupt.
This bit is set and cleared by software.
0: A Top Level Interrupt is generared when TLIP is
set, only if TLNM=1 in the NICR register (inde-
pendently of the value of the IEN bit).
1: A Top Level Interrupt request is generated when
IEN=1 and the TLIP bit are set.
7
0
TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0
Bit 7 = TED1: INTD1 Trigger Event
Bit 6 = TED0: INTD0 Trigger Event
Bit 5 = TEC1: INTC1 Trigger Event
Bit 4 = TEC0: INTC0 Trigger Event
Bit 3 = TEB1: INTB1 Trigger Event
Bit 2 = TEB0: INTB0 Trigger Event
Bit 1 = TEA1: INTA1 Trigger Event
Bit 0 = TEA0: INTA0 Trigger Event
Bit 4 = IEN: Interrupt Enable.
This bit is cleared by the interrupt machine cycle
(except for a TLI).
It is set by the iretinstruction (except for a return
from TLI).
It is set by the EIinstruction.
It is cleared by the DI instruction.
0: Maskable interrupts disabled
1: Maskable Interrupts enabled
Note: The IEN bit can also be changed by soft-
ware using any instruction that operates on regis-
ter CICR, however in this case, take care to avoid
spurious interrupts, since IEN cannot be cleared in
the middle of an interrupt arbitration. Only modify
These bits are set and cleared by software.
0: Select falling edge as interrupt trigger event
1: Select rising edge as interrupt trigger event
53/178
ST92185 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT PENDING REGISTER
(EIPR)
Bit 3 = IMB1: INTB1 Interrupt Mask
Bit 2 = IMB0: INTB0 Interrupt Mask
Bit 1 = IMA1: INTA1 Interrupt Mask
Bit 0 = IMA0: INTA0 Interrupt Mask
R243 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
These bits are set and cleared by software.
0: Interrupt masked
7
0
1: Interrupt not masked (an interrupt is generated if
the IPxx and IEN bits = 1)
IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0
Bit 7 = IPD1: INTD1 Interrupt Pending bit
Bit 6 = IPD0: INTD0 Interrupt Pending bit
Bit 5 = IPC1: INTC1 Interrupt Pending bit
Bit 4 = IPC0: INTC0 Interrupt Pending bit
Bit 3 = IPB1: INTB1 Interrupt Pending bit
Bit 2 = IPB0: INTB0 Interrupt Pending bit
Bit 1 = IPA1: INTA1 Interrupt Pending bit
Bit 0 = IPA0: INTA0 Interrupt Pending bit
EXTERNAL INTERRUPT PRIORITY LEVEL
REGISTER (EIPLR)
R245 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
7
0
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
These bits are set by hardware on occurrence of a
trigger event (as specified in the EITR register)
and are cleared by hardware on interrupt acknowl-
edge. They can also be set by software to imple-
ment a software interrupt.
Bit 7:6 = PL2D, PL1D: INTD0, D1 Priority Level.
Bit 5:4 = PL2C, PL1C: INTC0, C1 Priority Level.
Bit 3:2 = PL2B, PL1B: INTB0, B1 Priority Level.
Bit 1:0 = PL2A, PL1A: INTA0, A1 Priority Level.
These bits are set and cleared by software.
0: No interrupt pending
1: Interrupt pending
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for Channels A0, B0, C0 and D0 and
at 1 for Channels A1, B1, C1 and D1.
EXTERNAL INTERRUPT MASK-BIT REGISTER
(EIMR)
Hardware
R244 - Read/Write
PL2x PL1x
Priority
0 (Highest)
bit
0
1
Register Page: 0
Reset value: 0000 0000 (00h)
0
0
1
1
0
1
0
1
1
7
0
0
1
2
3
IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0
0
1
4
5
Bit 7 = IMD1: INTD1 Interrupt Mask
Bit 6 = IMD0: INTD0 Interrupt Mask
Bit 5 = IMC1: INTC1 Interrupt Mask
Bit 4 = IMC0: INTC0 Interrupt Mask
0
1
6
7 (Lowest)
54/178
ST92185 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT VECTOR REGISTER
0: WAITN pin disabled
1: WAITN pin enabled (to stretch the external
memory access cycle).
(EIVR)
R246 - Read/Write
Register Page: 0
Reset value: xxxx 0110b (x6h)
Note: For more details on Wait mode refer to the
section describing the WAITN pin in the External
Memory Chapter.
7
0
V7
V6
V5
V4 TLTEV TLIS IAOS EWEN
NESTED INTERRUPT CONTROL (NICR)
R247 - Read/Write
Register Page: 0
Bit 7:4 = V[7:4]: Most significant nibble of External
Interrupt Vector.
These bits are not initialized by reset. For a repre-
sentation of how the full vector is generated from
V[7:4] and the selected external interrupt channel,
refer to Figure 27.
Reset value: 0000 0000 (00h)
7
0
TLNM HL6 HL5 HL4 HL3 HL2 HL1 HL0
Bit 7 = TLNM: Top Level Not Maskable.
This bit is set by software and cleared only by a
hardware reset.
0: Top Level Interrupt Maskable. A top level re-
quest is generated if the IEN, TLI and TLIP bits
=1
Bit 3 = TLTEV: Top Level Trigger Event bit.
This bit is set and cleared by software.
0: Select falling edge as NMI trigger event
1: Select rising edge as NMI trigger event
1: Top Level Interrupt Not Maskable. A top level
request is generated if the TLIP bit =1
Bit 2 = TLIS: Top Level Input Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
1: NMI is TL interrupt source
Bit 6:0 = HL[6:0]: Hold Level x
These bits are set by hardware when, in Nested
Mode, an interrupt service routine at level x is in-
terrupted from a request with higher priority (other
than the Top Level interrupt request). They are
cleared by hardware at the iretexecution when
the routine at level x is recovered.
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source
1: External Interrupt pin is INTA0 source
Bit 0 = EWEN: External Wait Enable.
This bit is set and cleared by software.
55/178
ST92185 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL MEMORY REGISTER 2 (EMR2)
terrupt response time. The drawback is that it is
not possible for an interrupt service routine to
perform inter-segment calls or jumps: these in-
structions would update the CSR, which, in this
case, is not used (ISR is used instead). The
code segment size for all interrupt service rou-
tines is thus limited to 64K bytes.
1: ISR is only used to point to the interrupt vector
table and to initialize the CSR at the beginning
of the interrupt service routine: the old CSR is
pushed onto the stack together with the PC and
flags, and CSR is then loaded with the contents
of ISR. In this case, iretwill also restore CSR
from the stack. This approach allows interrupt
service routines to access the entire 4 Mbytes of
address space; the drawback is that the inter-
rupt response time is slightly increased, be-
cause of the need to also save CSR on the
stack. Full compatibility with the original ST9 is
lost in this case, because the interrupt stack
frame is different; this difference, however,
should not affect the vast majority of programs.
R246 - Read/Write
Register Page: 21
Reset value: 0000 1111 (0Fh)
7
0
1
0
ENCSR
0
0
1
1
1
Bit 7, 5:0 = Reserved, keep in reset state. Refer to
the external Memory Interface Chapter.
Bit 6 = ENCSR: Enable Code Segment Register.
This bit is set and cleared by software. It affects
the ST9 CPU behaviour whenever an interrupt re-
quest is issued.
0: The CPU works in original ST9 compatibility
mode. For the duration of the interrupt service
routine, ISR is used instead of CSR, and the in-
terrupt stack frame is identical to that of the orig-
inal ST9: only the PC and Flags are pushed.
This avoids saving the CSR on the stack in the
event of an interrupt, thus ensuring a faster in-
56/178
ST92185 - RESET AND CLOCK CONTROL UNIT (RCCU)
4 RESET AND CLOCK CONTROL UNIT (RCCU)
4.1 INTRODUCTION
The Reset Control Unit comprises two distinct sec-
tions:
– A Watchdog end of count.
The RESET input is schmitt triggered.
– An oscillator that uses an external quartz crystal.
Note: The memorized Internal Reset (called RE-
SETO) will be maintained active for a duration of
32768 Oscin periods (about 8 ms for a 4 MHz crys-
tal) after the external input is released (set high).
– The Reset/Stop Manager, which detects and
flags Hardware, Software and Watchdog gener-
ated resets.
This RESETO internal Reset signal is output on
the I/O port bit P3.7 (active low) during the whole
reset phase until the P3.7 configuration is changed
by software. The true internal reset (to all macro-
cells) will only be released 511 Reference clock
periods after the Memorized Internal reset is re-
leased.
4.2 RESET / STOP MANAGER
The RESET/STOP Manager resets the device
when one of the three following triggering events
occurs:
– A hardware reset, consequence of a low level on
the RESET pin.
It is possible to know which was the last RESET
triggering event, by reading bits 5 and 6 of register
SDRATH.
– A software reset, consequence of an HALT in-
struction when enabled.
Figure 29. Reset Overview
n
True
Build-up Counter
Internal
Reset
RESET
RCCU
Memorized
Reset
RESETO
57/178
ST92185 - RESET AND CLOCK CONTROL UNIT (RCCU)
4.3 OSCILLATOR CHARACTERISTICS
The on-chip oscillator circuit uses an inverting gate
circuit with tri-state output.
Figure 30. Crystal Oscillator
CRYSTAL CLOCK
Notes: Owing to the Q factor required, Ceramic
Resonators may not provide a reliable oscillator
source.
ST9
The oscillator can not support quartz crystal or ce-
ramic working at the third harmonic without exter-
nal tank circuits.
OSCOUT
OSCIN
OSCOUT must not be used to drive external cir-
cuits.
Halt mode is set by means of the HALTinstruction.
In this mode the parallel resistor, R, is disconnect-
ed and the oscillator is disabled. This forces the in-
ternal clock to a high level and OSCOUT to a high
impedance state.
C
C
L1
L2
VR02116A
Note: Depending on the application it may be bet-
ter not to implement CL1
To exit the HALTcondition and restart the oscilla-
tor, an external RESET pulse is required.
It should be noted that, if the Watchdog function is
enabled, a HALTinstruction will not disable the os-
cillator. This to avoid stopping the Watchdog if a
HALTcode is executed in error. When this occurs,
the CPU will be reset when the Watchdog times
out or when an external reset is applied.
Figure 31. Internal Oscillator Schematic
HALT
When an HALT instruction is executed, the main
crystal oscillator is stoped and any spurious clock
are ignored. Other analog systems such as the on-
chip line PLL or the whole Video chain (Sync Ex-
traction) must be stopped separately by the soft-
ware as they will induce static consumption.
R
R
R
OUT
IN
OSCIN
OSCOUT
VR02086A
Table 8. Oscillator Transconductance
gm
Min
Typ
Max
mA/V
0.77
1.5
2.4
Figure 32. External Clock
n
EXTERNAL CLOCK
OSCOUT
NC
OSCIN
CLOCK
INPUT
VR02116B
58/178
ST92185 - RESET AND CLOCK CONTROL UNIT (RCCU)
OSCILLATOR CHARACTERISTICS (Cont’d)
The following table is relative to the fundamental
quartz crystal only; assuming:
Table 9. Crystal Specification (C0 ≤ 7 pF)
CL1=CL2=
Freq.
MHz.
– Rs: parasitic series resistance of the quartz crys-
tal (upper limit)
39 pF
Rs Max
– C0: parasitic capacitance of the crystal (upper
limit, ≤ 7 pF)
8
4
65
260
– C1,C2: maximum total capacitance on pins OS-
CIN/OSCOUT (value including external capaci-
tance tied to the pin plus the parasitic
Legend:
Rs: Parasitic Series Resistance of the quartz crystal (up-
per limit) C0: Parasitic capacitance of the quartz crystal
(upper limit, < 7 pF)
capacitance of the board and device).
CL1, CL2: Maximum Total Capacitance on pins OSCIN
and OSCOUT (the value includes the external capaci-
tance tied to the pin plus the parasitic capacitance of the
board and of the device)
gm: Transconductance of the oscillator
Note.The tables are relative to the fundamental quartz
crystal only (not ceramic resonator).
59/178
ST92185 - RESET AND CLOCK CONTROL UNIT (RCCU)
4.4 CLOCK CONTROL REGISTERS
MODE REGISTER (MODER)
R235 - Read/Write
Register Group: E (System)
Reset Value: 1110 0000 (E0h)
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Reset Value: 0111 1111 (7Fh)
7
0
7
0
DIV2 PRS2 PRS1 PRS0
0
WDGEN WDM2 WDM1 WDM0 WPM2 WPM1 WPM0
1
1
0
0
Bit 7:6 = Bits described in Device Architecture
chapter.
Bit 7 = Reserved, read as “0”.
Bit 6 = WDGEN: refer to Timer/Watchdog chapter.
Bit 5 = DIV2: OSCIN Divided by 2.
This bit controls the divide by 2 circuit which oper-
ates on the OSCIN Clock.
WARNING. Resetting this bit to zero has the effect
of setting the Timer/Watchdog to the Watchdog
mode. Unless this is desired, this must be set to
“1”.
0: No division of OSCIN Clock
1: OSCIN clock is internally divided by 2
Bit 5:3 = WDM[2:0]: Data Memory Wait Cycles.
These bits contain the number of INTCLK cycles
to be added automatically to external Data memo-
ry accesses. WDM = 0 gives no additional wait cy-
cles. WDM = 7 provides the maximum 7 INTCLK
cycles (reset condition).
Bit 4:2 = PRS[2:0]: Clock Prescaling.
These bits define the prescaler value used to
prescale CPUCLK from INTCLK. When they are
reset, the CPUCLK is not prescaled, and is equal
to INTCLK; in all other cases, the internal clock is
prescaled by the value of these three bits plus one.
Bit 1:0 = Bits described in Device Architecture
chapter.
Bit 2:0 = WPM[2:0]: Program Memory Wait Cy-
cles.
These bits contain the number of INTCLK cycles
to be added automatically to external Program
memory accesses. WPM = 0 gives no additional
wait cycles, WPM = 7 provides the maximum 7
INTCLK cycles (reset condition).
Note: The number of clock cycles added refers to
INTCLK and NOT to CPUCLK.
WARNING. The reset value of the Wait Control
Register gives the maximum number of Wait cy-
cles for external memory. To get optimum per-
formance from the ST9 when used in single-chip
mode (no external memory) the user should write
the WDM2,1,0 and WPM2,1,0 bits to “0”.
60/178
ST92185 - RESET AND CLOCK CONTROL UNIT (RCCU)
4.5 RESET CONTROL UNIT REGISTERS
The RCCU consists of two registers. They are
PCONF and SDRATH. Unless otherwise stated,
unused register bits must be kept in their reset val-
ue in order to avoid problems with the device be-
haviour.
CLOCK SLOW DOWN UNIT RATIO REGISTER
(SDRATH)
R254 - Read/Write
Register Page: 55
Reset value:
0010 0xxx (2xh) after software reset
0100 0xxx (4xh) after watchdog reset
0000 0000 (00h) after external reset
PLL CONFIGURATION REGISTER (PCONF)
R251 - Read/Write
Register Page: 55
Reset value: 0000 0111 (07h)
7
0
0
x
WDGRES SFTRES
0
0
x
x
7
0
1
Bit 7 = Reserved bit. Leave in its reset state.
SRESEN
0
0
0
0
1
1
Bit 6 = WDGRES. Watchdog Reset. WDGRES is
automatically set if the last reset was a watchdog
Reset. This is a read only bit.
Bit 7= SRESEN. Software Reset Enable.
0: RCCU PLL and CSDU are turned off when a
HALT instruction is performed.
1: RCCU will reset the microcontroller when a
HALT instruction is performed.
Bit 5 = SFTRES. Software Reset. SFTRES is au-
tomatically set if the last reset was a software Re-
set. This is a read only bit.
Bit 6:0= Reserved bits. Leave in their reset state.
Bit 4:0 = Reserved bits. Please leave in their reset
state.
61/178
ST92185 - TIMING AND CLOCK CONTROLLER
5 TIMING AND CLOCK CONTROLLER
5.1 FREQUENCY MULTIPLIERS
Three on-chip frequency multipliers generate the
proper frequencies for: the Core/Real time Periph-
erals, the Display related time base.
For both the Core and the Display frequency mul-
tipliers, a 4 bit programmable feed-back counter
allows the adjustment of the multiplying factor to
the application need (a 4 MHz or 8 MHz crystal is
assumed).
Figure 33. Timing and Clock Controller Block Diagram
Hsync
SKHPLS
SKDIV2
PXFM
Synchronized DOTCK / 2 to Display
(2X Pixel clock for 1X width characters)
Divide
by 2
Skew Corrector
Frequency
Multiplier
Async.
Handler
(Synchronized DOTCK)
Divide
SKDIV2
to Display Storage RAM (TRI)
by 2
SKWL(3:0)
SKWEN
4 MHz real time
MCFM
SLDIV2
Frequency
Multiplier
FMEN
FML(3:0)
Divide
by 2
Divide
by 2
Memory Wait
BREQ
OSCIN
WFI
Fimf
Xtal
Oscillator
Prescaler
1 to 8
Clock
Control
CPUCLK
Div-2
OSCOUT
INTCLK
Asynch.
Handler
FMEN
FMSL
MODER.5
Main Clock Controller
ST9 Clock Control Unit (RCCU)
VR02095A
62/178
ST92185 - TIMING AND CLOCK CONTROLLER
FREQUENCY MULTIPLIERS (Cont’d)
For the Off-chip filter components please refer to
the Required External Components figure provid-
ed in the first section of the data sheet.
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
5
6
12 MHz
14 MHz
16 MHz
18 MHz
24 MHz
7
The frequency multipliers are off during and upon
exiting from the reset phase. The user must pro-
gram the desired multiplying factor, start the multi-
plier and then wait for its stability.
8
11
Note: 24 MHz is the max. CPU authorized frequency.
Once the Core/Peripherals multiplier is stabilized,
the Main Clock controller can be re-programmed
(through the FMSL bit, MCCR.6) to provide the fi-
nal frequency (INTCLK) to the CPU.
Table 11. DOTCK/2 frequency choices
SKW
DOTCK/2
(3:0)
The frequency multipliers are automatically
switched off when the µP enters in HALT mode
(the HALT mode forces the control register to its
reset status).
8
9
18 MHz
20 MHz(*)
22 MHz
10
11
24 MHz (**)
Table 10. Examples of CPU speed choice
(*) Preferred values for 4/3.
Crystal
Frequency
FML
(3:0)
Internal Frequency
(Fimf)
(**) 16/9 screen formats.
Note: 18 MHz is the min. DOTCK/2 authorized frequency.
4 MHz
4
10 MHz
Table 12. External PLL Filter Stabilisation time
Clock Pin Name
MCFM
Clock Name
Main Clock PLL Filter Input Pin
Pixel Clock PLL Filter Input Pin
Control Register
MCCR
Stabilization Period
35 ms.
PXFM
PXCCR
35 ms
63/178
ST92185 - TIMING AND CLOCK CONTROLLER
Figure 34. Programming the MCCR
Set the PLL frequency
FML (3:0)
Example:
spp
#27h ;Set the page
Start the PLL by setting
FMEN = 1
ld MCCR, #04h ;Set FML bits to the value needed e.g. 10 MHz
or MCCR, #80h ;Starts the PLL
Wait for stabilization time
Wait for Clock
Stabilization
or MCCR, #40h ;Validate the PLL as the main CPU Clock
Validate PLL as Main
CPU Clock
Figure 35. Programming the SKCCR, PXCCR
Set the PLL frequency
SKW (3:0)
Example:
spp
#27h ;Set the page
Start the PLL by setting
SKWEN = 1
ld SKCCR, #04h ;Set SKW bits to the value needed
or SKCCR, #80h ;Starts the PLL
Wait for stabilization time
Wait for Clock
Stabilization
or PXCCR, #80h ;PLL is fed as DOTCK to the TDSRAM & OSDPLL
Validate PLL is fed to
TDSRAM and OSD
64/178
ST92185 - TIMING AND CLOCK CONTROLLER
5.2 REGISTER DESCRIPTION
MAIN CLOCK CONTROL REGISTER (MCCR)
R253 - Read/ Write
SKEW CLOCK CONTROL REGISTER (SKCCR)
R254 - Read/ Write
Register Page: 39
Register Page: 39
Reset value: 0000 0000 (00h)
Reset value: 0000 0000 (00h)
7
6
5
0
4
0
3
2
1
0
7
6
5
0
4
0
3
2
1
0
FMEN FMSL
FML3 FML2 FML1 FML0
SKW
EN
SKDIV2
SKW3 SKW2 SKW1 SKW0
The HALT mode forces the register to its initializa-
tion state.
The HALT mode forces the register to its initializa-
tion state.
Bit 7 = FMEN. Frequency Multiplier Enable bit.
0: FM disabled (reset state), low-power consump-
tion mode.
1: FM is enabled, providing clock to the CPU. The
FMEN bit must be set only after programming
the FML(3:0) bits.
Bit 7= SKWEN. Frequency Multiplier Enable bit.
0: FM disabled (reset state), low-power consump-
tion mode.
1: FM is enabled, supplying the clock to the Skew
corrector. The SKWEN bit must be set only after
programming the SKW(3-0) bits.
Bit 6= FMSL. Frequency Multiplier Select bit.
This bit controls the choice of the ST9+ core inter-
nal frequency between the external crystal fre-
quency and the Main Clock issued by the frequen-
cy multiplier.
Bit 6= SKDIV2. Divide-by-2 enable
This bit determines whether a divide-by-2 down-
scaling factor is applied to the output of the Skew
Corrector.
0 = Divide-by-2 enabled
In order to secure the application, the ST9+ core
internal frequency is automatically switched back
to the external crystal frequency if the frequency
multiplier is switched off (FMEN =0) regardless of
the value of the FMSL bit. Care must be taken to
reset the FMSL bit before any frequency multiplier
can restart (FMEN set back to 1).
1 = Divide-by-2 disabled
Bit 5:4 = These bits are reserved.
Bit 3:0 = SKW[3:0]. Frequency bits
These 4 bits program the down-counter inserted in
the feedback loop of the Frequency Multiplier
which generates the internal multiplied frequency
DOTCK. The DOTCK value is calculated as fol-
lows :
After reset, the external crystal frequency is al-
ways sent to the ST9+ Core.
Bit 5:4 = These bits are reserved.
F(DOTCK) = Crystal frequency * [ (SKW(3:0) + 1) ]
Bit 3:0 = FML[3:0] Frequency bits.
These 4 bits program the down-counter inserted in
the feed-back loop of the Frequency Multiplier
which generates the internal multiplied frequency
Fimf. The Fimf value is calculated as follows :
Fimf = Crystal frequency * [ (FML(3:0) + 1) ] /2
65/178
ST92185 - TIMING AND CLOCK CONTROLLER
REGISTER DESCRIPTION (Cont’d)
PLL CLOCK CONTROL REGISTER (PXCCR)
R251 - Read/Write
Bit 7:5 = These bits are reserved.
Register Page: 39
Bit 4= VMOD: Video mode selection.
This bit is used to select either 50Hz or 60Hz video
mode. It is set and cleared by software.
0: 50 Hz.
Reset value: 0000 0000 (00h)
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
1: 60 Hz.
PXCE
Bit 3:0= These bits are reserved.
Bit 7= PXCE. Pixel Clock Enable bit.
0: Pixel and TDSRAM interface clocks are blocked
1: Pixel clock is sent to the display controller and
TDSRAM interface.
5.2.1 Register Mapping
The Timing Controller has 4 dedicated registers,
mapped in a ST9+ register file page (the page ad-
dress is 39 (27h)), as follows :
Bit 6:0= These bits are reserved.
Page 39 (27h)
FEh
FDh
FCh
FBh
Skew Corrector Control Register
Main Clock Control Register
SLicer Clock Control Register
Pixel Clock Control Register
SKCCR
MCCR
SLICER
CLOCK
CONTROL
REGISTER
(SLCCR)
R252 - Read/ Write
Register Page: 39
Reset value: 0000 0000 (00h)
SLCCR
PXCCR
7
0
6
0
5
0
4
3
0
2
0
1
0
0
0
VMOD
The HALT mode forces the register to its initializa-
tion state.
66/178
ST92185 - I/O PORTS
6 I/O PORTS
6.1 INTRODUCTION
6.2 SPECIFIC PORT CONFIGURATIONS
ST9 devices feature flexible individually program-
mable multifunctional input/output lines. Refer to
the Pin Description Chapter for specific pin alloca-
tions. These lines, which are logically grouped as
8-bit ports, can be individually programmed to pro-
vide digital input/output and analog input, or to
connect input/output signals to the on-chip periph-
erals as alternate pin functions. All ports can be in-
dividually configured as an input, bi-directional,
output or alternate function. In addition, pull-ups
can be turned off for open-drain operation, and
weak pull-ups can be turned on in their place, to
avoid the need for off-chip resistive pull-ups. Ports
configured as open drain must never have voltage
Refer to the Pin Description chapter for a list of the
specific port styles and reset values.
6.3 PORT CONTROL REGISTERS
Each port is associated with a Data register
(PxDR) and three Control registers (PxC0, PxC1,
PxC2). These define the port configuration and al-
low dynamic configuration changes during pro-
gram execution. Port Data and Control registers
are mapped into the Register File as shown in Fig-
ure 1. Port Data and Control registers are treated
just like any other general purpose register. There
are no special instructions for port manipulation:
any instruction that can address a register, can ad-
dress the ports. Data can be directly accessed in
the port register, without passing through other
memory or “accumulator” locations.
on the port pin exceeding V (refer to the Electri-
DD
cal Characteristics section). Depending on the
specific port, input buffers are software selectable
to be TTL or CMOS compatible, however on Sch-
mitt trigger ports, no selection is possible.
Figure 36. I/O Register Map
GROUP E
GROUP F
GROUP F
PAGE 3
GROUP F
PAGE 43
PAGE 2
Reserved
P3C2
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
P7DR
P7C2
P9DR
P9C2
P9C1
P9C0
P8DR
P8C2
P8C1
P8C0
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
P3C1
P7C1
P3C0
P7C0
Reserved
P2C2
P6DR
P6C2
System
Registers
P2C1
P6C1
P2C0
P6C0
Reserved
P1C2
Reserved
P5C2
E5h
E4h
E3h
E2h
E1h
E0h
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
R229
R228
R227
R226
R225
R224
P1C1
P5C1
Reserved
P1C0
P5C0
Reserved
P0C2
Reserved
P4C2
P0C1
P4C1
P0C0
P4C0
67/178
ST92185 - I/O PORTS
PORT CONTROL REGISTERS (Cont’d)
During Reset, ports with weak pull-ups are set in
bidirectional/weak pull-up mode and the output
Data Register is set to FFh. This condition is also
held after Reset, except for Ports 0 and 1 in ROM-
less devices, and can be redefined under software
control.
Each pin of an I/O port may assume software pro-
grammable Alternate Functions (refer to the de-
vice Pin Description and to Section 1.5). To output
signals from the ST9 peripherals, the port must be
configured as AF OUT. On ST9 devices with A/D
Converter(s), configure the ports used for analog
inputs as AF IN.
Bidirectional ports without weak pull-ups are set in
high impedance during reset. To ensure proper
levels during reset, these ports must be externally
The basic structure of the bit Px.n of a general pur-
pose port Px is shown in Figure 3.
connected to either V
or V through external
DD
SS
Independently of the chosen configuration, when
the user addresses the port as the destination reg-
ister of an instruction, the port is written to and the
data is transferred from the internal Data Bus to
the Output Master Latches. When the port is ad-
dressed as the source register of an instruction,
the port is read and the data (stored in the Input
Latch) is transferred to the internal Data Bus.
pull-up or pull-down resistors.
Other reset conditions may apply in specific ST9
devices.
6.4 INPUT/OUTPUT BIT CONFIGURATION
By programming the control bits PxC0.n and
PxC1.n (see Figure 2) it is possible to configure bit
Px.n as Input, Output, Bidirectional or Alternate
Function Output, where X is the number of the I/O
port, and n the bit within the port (n = 0 to 7).
When Px.n is programmed as an Input:
(See Figure 4).
– The Output Buffer is forced tristate.
When programmed as input, it is possible to select
the input level as TTL or CMOS compatible by pro-
gramming the relevant PxC2.n control bit.
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of each instruc-
tion execution.
This option is not available on Schmitt trigger ports.
– The data stored in the Output Master Latch is
copied into the Output Slave Latch at the end of
the execution of each instruction. Thus, if bit Px.n
is reconfigured as an Output or Bidirectional, the
data stored in the Output Slave Latch will be re-
flected on the I/O pin.
The output buffer can be programmed as push-
pull or open-drain.
A weak pull-up configuration can be used to avoid
external pull-ups when programmed as bidirec-
tional (except where the weak pull-up option has
been permanently disabled in the pin hardware as-
signment).
68/178
ST92185 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
Figure 37. Control Bits
Bit 7
Bit n
Bit 0
PxC2
PxC1
PxC0
PxC27
PxC17
PxC07
PxC2n
PxC1n
PxC0n
PxC20
PxC10
PxC00
n
Table 13. Port Bit Configuration Table (n = 0, 1... 7; X = port number)
General Purpose I/O Pins
A/D Pins
PXC2n
PXC1n
PXC0n
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
PXn Configuration
PXn Output Type
BID
BID
OD
OUT
PP
OUT
OD
IN
IN
AF OUT AF OUT
AF IN
(1)
WP OD
HI-Z
HI-Z
PP
OD
HI-Z
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
CMOS
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
Analog
Input
PXn Input Type
(1)
For A/D Converter inputs.
Legend:
X
= Port
n
= Bit
AF
= Alternate Function
BID = Bidirectional
CMOS= CMOS Standard Input Levels
HI-Z = High Impedance
IN
= Input
OD = Open Drain
OUT = Output
PP
= Push-Pull
TTL = TTL Standard Input Levels
WP = Weak Pull-up
69/178
ST92185 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
Figure 38. Basic Structure of an I/O Port Pin
I/O PIN
PUSH-PULL
TRISTATE
OPEN DRAIN
WEAK PULL-UP
TTL / CMOS
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
INTERRUPTS
OUTPUT SLAVE LATCH
ALTERNATE
FROM
FUNCTION
PERIPHERAL
OUTPUT
INPUT
BIDIRECTIONAL
ALTERNATE
FUNCTION
OUTPUT
INPUT
OUTPUT
BIDIRECTIONAL
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
Figure 39. Input Configuration
Figure 40. Output Configuration
I/O PIN
I/O PIN
OPEN DRAIN
PUSH-PULL
TTL / CMOS
TTL
TRISTATE
(or Schmitt Trigger)
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
OUTPUT SLAVE LATCH
INTERRUPTS
INTERRUPTS
OUTPUT MASTER LATCH
INPUT LATCH
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
INTERNAL DATA BUS
n
n
n
70/178
ST92185 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
When Px.n is programmed as an Output:
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of the execution
of the instruction.
(Figure 5)
– The Output Buffer is turned on in an Open-drain
or Push-pull configuration.
– The signal from an on-chip function is allowed to
load the Output Slave Latch driving the I/O pin.
Signal timing is under control of the alternate
function. If no alternate function is connected to
Px.n, the I/O pin is driven to a high level when in
Push-Pull configuration, and to a high imped-
ance state when in open drain configuration.
– The data stored in the Output Master Latch is
copied both into the Input Latch and into the Out-
put Slave Latch, driving the I/O pin, at the end of
the execution of the instruction.
When Px.n is programmed as Bidirectional:
(Figure 6)
Figure 41. Bidirectional Configuration
– The Output Buffer is turned on in an Open-Drain
or Weak Pull-up configuration (except when dis-
abled in hardware).
I/O PIN
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of the execution
of the instruction.
WEAK PULL-UP
OPEN DRAIN
TTL
(or Schmitt Trigger)
– The data stored in the Output Master Latch is
copied into the Output Slave Latch, driving the I/
O pin, at the end of the execution of the instruc-
tion.
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
INTERRUPTS
WARNING: Due to the fact that in bidirectional
mode the external pin is read instead of the output
latch, particular care must be taken with arithme-
tic/logic and Boolean instructions performed on a
bidirectional port pin.
OUTPUT MASTER LATCH
INPUT LATCH
These instructions use a read-modify-write se-
quence, and the result written in the port register
depends on the logical level present on the exter-
nal pin.
INTERNAL DATA BUS
n
n
This may bring unwanted modifications to the port
output register content.
Figure 42. Alternate Function Configuration
For example:
I/O PIN
Port register content, 0Fh
external port value, 03h
(Bits 3 and 2 are externally forced to 0)
OPEN DRAIN
PUSH-PULL
TTL
(or Schmitt Trigger)
A bsetinstruction on bit 7 will return:
Port register content, 83h
external port value, 83h
(Bits 3 and 2 have been cleared).
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
INTERRUPTS
To avoid this situation, it is suggested that all oper-
ations on a port, using at least one bit in bidirec-
tional mode, are performed on a copy of the port
register, then transferring the result with a load in-
struction to the I/O port.
FROM
PERIPHERAL
OUTPUT
INPUT LATCH
When Px.n is programmed as a digital Alter-
nate Function Output:
INTERNAL DATA BUS
(Figure 7)
n
n
n
n
n
n
– The Output Buffer is turned on in an Open-Drain
or Push-Pull configuration.
71/178
ST92185 - I/O PORTS
6.5 ALTERNATE FUNCTION ARCHITECTURE
Each I/O pin may be connected to three different
types of internal signal:
6.5.3 Pin Declared as an Alternate Function
Output
– Data bus Input/Output
– Alternate Function Input
– Alternate Function Output
6.5.1 Pin Declared as I/O
The user must select the AF OUT configuration
using the PxC2, PxC1, PxC0 bits. Several Alter-
nate Function outputs may drive a common pin. In
such case, the Alternate Function output signals
are logically ANDed before driving the common
pin. The user must therefore enable the required
Alternate Function Output by software.
A pin declared as I/O, is connected to the I/O buff-
er. This pin may be an Input, an Output, or a bidi-
rectional I/O, depending on the value stored in
(PxC2, PxC1 and PxC0).
WARNING: When a pin is connected both to an al-
ternate function output and to an alternate function
input, it should be noted that the output signal will
always be present on the alternate function input.
6.5.2 Pin Declared as an Alternate Function
Input
A single pin may be directly connected to several
Alternate Function inputs. In this case, the user
must select the required input mode (with the
PxC2, PxC1, PxC0 bits) and enable the selected
Alternate Function in the Control Register of the
peripheral. No specific port configuration is re-
quired to enable an Alternate Function input, since
the input buffer is directly connected to each alter-
nate function module on the shared pin. As more
than one module can use the same input, it is up to
the user software to enable the required module
as necessary. Parallel I/Os remain operational
even when using an Alternate Function input. The
exception to this is when an I/O port bit is perma-
nently assigned by hardware as an A/D bit. In this
case , after software programming of the bit in AF-
OD-TTL, the Alternate function output is forced to
logic level 1. The analog voltage level on the cor-
responding pin is directly input to the A/D (See Fig-
ure 8).
6.6 I/O STATUS AFTER WFI, HALT AND RESET
The status of the I/O ports during the Wait For In-
terrupt, Halt and Reset operational modes is
shown in the following table. The External Memory
Interface ports are shown separately. If only the in-
ternal memory is being used and the ports are act-
ing as I/O, the status is the same as shown for the
other I/O ports.
Ext. Mem - I/O Ports
Mode
I/O Ports
P1, P2,
P6, P9
P0
High Imped-
ance or next
address (de-
pending on
the last
memory op-
eration per-
formed on
Port)
Next
Not Affected (clock
WFI
Address outputs running)
Figure 43. A/D Input Configuration
I/O PIN
High Imped-
ance
Next
Not Affected (clock
TOWARDS
A/D CONVERTER
HALT
Address outputs stopped)
TRISTATE
GND
Bidirectional Weak
Alternate function push- Pull-up (High im-
RESET
pull (ROMless device)
pedance when disa-
bled in hardware).
INPUT
OUTPUT SLAVE LATCH
BUFFER
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
72/178
ST92185 - TIMER/WATCHDOG (WDT)
7 ON-CHIP PERIPHERALS
7.1 TIMER/WATCHDOG (WDT)
Important Note: This chapter is a generic descrip-
tion of the WDT peripheral. However depending
on the ST9 device, some or all of WDT interface
signals described may not be connected to exter-
nal pins. For the list of WDT pins present on the
ST9 device, refer to the device pinout description
in the first section of the data sheet.
The main WDT registers are:
– Control register for the input, output and interrupt
logic blocks (WDTCR)
– 16-bit counter register pair (WDTHR, WDTLR)
– Prescaler register (WDTPR)
The hardware interface consists of up to five sig-
nals:
7.1.1 Introduction
The Timer/Watchdog (WDT) peripheral consists of
a programmable 16-bit timer and an 8-bit prescal-
er. It can be used, for example, to:
– WDIN External clock input
– WDOUT Square wave or PWM signal output
– INT0 External interrupt input
– Generate periodic interrupts
– NMI Non-Maskable Interrupt input
– Measure input signal pulse widths
– Request an interrupt after a set number of events
– Generate an output signal waveform
– HW0SW1 Hardware/Software Watchdog ena-
ble.
– Act as a Watchdog timer to monitor system in-
tegrity
Figure 44. Timer/Watchdog Block Diagram
INMD1 INMD2
INEN
INPUT
&
1
WDIN
WDTRH, WDTRL
WDTPR
END OF
16-BIT
CLOCK CONTROL LOGIC
MUX
8-BIT PRESCALER
COUNT
DOWNCOUNTER
WDT
CLOCK
INTCLK/4
WROUT
OUTEN
OUTMD
OUTPUT CONTROL LOGIC
1
NMI
1
INT0
1
WDOUT
1
HW0SW1
INTERRUPT
MUX
IAOS
CONTROL LOGIC
WDGEN
TLIS
RESET
TOP LEVEL INTERRUPT REQUEST
INTA0 REQUEST
1
Pin not present on some ST9 devices.
73/178
ST92185 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.2 Functional Description
7.1.2.1 External Signals
7.1.2.4 Single/Continuous Mode
The S_C bit allows selection of single or continu-
ous mode.This Mode bit can be written with the
Timer stopped or running. It is possible to toggle
the S_C bit and start the counter with the same in-
struction.
The HW0SW1 pin can be used to permanently en-
able Watchdog mode. Refer to Section 0.1.3.1.
The WDIN Input pin can be used in one of four
modes:
Single Mode
– Event Counter Mode
On reaching the End Of Count condition, the Timer
stops, reloads the constant, and resets the Start/
Stop bit. Software can check the current status by
reading this bit. To restart the Timer, set the Start/
Stop bit.
– Gated External Input Mode
– Triggerable Input Mode
– Retriggerable Input Mode
The WDOUT output pin can be used to generate a
square wave or a Pulse Width Modulated signal.
Note: If the Timer constant has been modified dur-
ing the stop period, it is reloaded at start time.
An interrupt, generated when the WDT is running
as the 16-bit Timer/Counter, can be used as a Top
Level Interrupt or as an interrupt source connected
to channel A0 of the external interrupt structure
(replacing the INT0 interrupt input).
Continuous Mode
On reaching the End Of Count condition, the coun-
ter automatically reloads the constant and restarts.
It is stopped only if the Start/Stop bit is reset.
7.1.2.5 Input Section
The counter can be driven either by an external
clock, or internally by INTCLK divided by 4.
If the Timer/Counter input is enabled (INEN bit) it
can count pulses input on the WDIN pin. Other-
wise it counts the internal clock/4.
7.1.2.2 Initialisation
The prescaler (WDTPR) and counter (WDTRL,
WDTRH) registers must be loaded with initial val-
ues before starting the Timer/Counter. If this is not
done, counting will start with reset values.
For instance, when INTCLK = 24MHz, the End Of
Count rate is:
2.79 seconds for Maximum Count
(Timer Const. = FFFFh, Prescaler Const. = FFh)
7.1.2.3 Start/Stop
166 ns for Minimum Count
The ST_SP bit enables downcounting. When this
bit is set, the Timer will start at the beginning of the
following instruction. Resetting this bit stops the
counter.
(Timer Const. = 0000h, Prescaler Const. = 00h)
The Input pin can be used in one of four modes:
– Event Counter Mode
If the counter is stopped and restarted, counting
will resume from the last value unless a new con-
stant has been entered in the Timer registers
(WDTRL, WDTRH).
– Gated External Input Mode
– Triggerable Input Mode
– Retriggerable Input Mode
A new constant can be written in the WDTRH,
WDTRL, WDTPR registers while the counter is
running. The new value of the WDTRH, WDTRL
registers will be loaded at the next End of Count
(EOC) condition while the new value of the
WDTPR register will be effective immediately.
The mode is configurable in the WDTCR.
7.1.2.6 Event Counter Mode
In this mode the Timer is driven by the external
clock applied to the input pin, thus operating as an
event counter. The event is defined as a high to
low transition of the input signal. Spacing between
trailing edges should be at least 8 INTCLK periods
(or 333ns with INTCLK = 24MHz).
End of Count is when the counter is 0.
When Watchdog mode is enabled the state of the
ST_SP bit is irrelevant.
Counting starts at the next input event after the
ST_SP bit is set and stops when the ST_SP bit is
reset.
74/178
ST92185 - TIMER/WATCHDOG (WDT)
7.1.3 Watchdog Timer Operation
TIMER/WATCHDOG (Cont’d)
7.1.2.7 Gated Input Mode
This mode can be used for pulse width measure-
ment. The Timer is clocked by INTCLK/4, and is
started and stopped by means of the input pin and
the ST_SP bit. When the input pin is high, the Tim-
er counts. When it is low, counting stops. The
maximum input pin frequency is equivalent to
INTCLK/8.
This mode is used to detect the occurrence of a
software fault, usually generated by external inter-
ference or by unforeseen logical conditions, which
causes the application program to abandon its
normal sequence of operation. The Watchdog,
when enabled, resets the MCU, unless the pro-
gram executes the correct write sequence before
expiry of the programmed time period. The appli-
cation program must be designed so as to correct-
ly write to the WDTLR Watchdog register at regu-
lar intervals during all phases of normal operation.
7.1.2.8 Triggerable Input Mode
The Timer (clocked internally by INTCLK/4) is
started by the following sequence:
– setting the Start-Stop bit, followed by
– a High to Low transition on the input pin.
To stop the Timer, reset the ST_SP bit.
7.1.2.9 Retriggerable Input Mode
7.1.3.1
Hardware
Watchdog/Software
Watchdog
The HW0SW1 pin (when available) selects Hard-
ware Watchdog or Software Watchdog.
If HW0SW1 is held low:
In this mode, the Timer (clocked internally by
INTCLK/4) is started by setting the ST_SP bit. A
High to Low transition on the input pin causes
counting to restart from the initial value. When the
Timer is stopped (ST_SP bit reset), a High to Low
transition of the input pin has no effect.
– The Watchdog is enabled by hardware immedi-
ately after an external reset. (Note: Software re-
set or Watchdog reset have no effect on the
Watchdog enable status).
– The initial counter value (FFFFh) cannot be mod-
ified, however software can change the prescaler
value on the fly.
7.1.2.10 Timer/Counter Output Modes
Output modes are selected by means of the OUT-
EN (Output Enable) and OUTMD (Output Mode)
bits of the WDTCR register.
– The WDGEN bit has no effect. (Note: it is not
forced low).
If HW0SW1 is held high, or is not present:
No Output Mode
(OUTEN = “0”)
– The Watchdog can be enabled by resetting the
WDGEN bit.
The output is disabled and the corresponding pin
is set high, in order to allow other alternate func-
tions to use the I/O pin.
7.1.3.2 Starting the Watchdog
In Watchdog mode the Timer is clocked by
INTCLK/4.
Square Wave Output Mode
(OUTEN = “1”, OUTMD = “0”)
If the Watchdog is software enabled, the time base
must be written in the timer registers before enter-
ing Watchdog mode by resetting the WDGEN bit.
Once reset, this bit cannot be changed by soft-
ware.
The Timer outputs a signal with a frequency equal
to half the End of Count repetition rate on the WD-
OUT pin. With an INTCLK frequency of 20MHz,
this allows a square wave signal to be generated
whose period can range from 400ns to 6.7 sec-
onds.
If the Watchdog is hardware enabled, the time
base is fixed by the reset value of the registers.
Pulse Width Modulated Output Mode
(OUTEN = “1”, OUTMD = “1”)
Resetting WDGEN causes the counter to start, re-
gardless of the value of the Start-Stop bit.
The state of the WROUT bit is transferred to the
output pin (WDOUT) at the End of Count, and is
held until the next End of Count condition. The
user can thus generate PWM signals by modifying
the status of the WROUT pin between End of
Count events, based on software counters decre-
mented by the Timer Watchdog interrupt.
In Watchdog mode, only the Prescaler Constant
may be modified.
If the End of Count condition is reached a System
Reset is generated.
75/178
ST92185 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.3.3 Preventing Watchdog System Reset
7.1.3.4 Non-Stop Operation
In order to prevent a system reset, the sequence
AAh, 55h must be written to WDTLR (Watchdog
Timer Low Register). Once 55h has been written,
the Timer reloads the constant and counting re-
starts from the preset value.
In Watchdog Mode, a Haltinstruction is regarded
as illegal. Execution of the Haltinstruction stops
further execution by the CPU and interrupt ac-
knowledgment, but does not stop INTCLK, CPU-
CLK or the Watchdog Timer, which will cause a
System Reset when the End of Count condition is
reached. Furthermore, ST_SP, S_C and the Input
Mode selection bits are ignored. Hence, regard-
less of their status, the counter always runs in
Continuous Mode, driven by the internal clock.
To reload the counter, the two writing operations
must be performed sequentially without inserting
other instructions that modify the value of the
WDTLR register between the writing operations.
The maximum allowed time between two reloads
of the counter depends on the Watchdog timeout
period.
The Output mode should not be enabled, since in
this context it is meaningless.
Figure 45. Watchdog Timer Mode
COUNT
VALUE
TIMER START COUNTING
RESET
WRITE WDTRH,WDTRL
WDGEN=0
SOFTWARE FAIL
(E.G. INFINITE LOOP)
OR PERIPHERAL FAIL
WRITE AAh,55h
INTO WDTRL
PRODUCE
COUNT RELOAD
VA00220
76/178
ST92185 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.4 WDT Interrupts
Figure 46. Interrupt Sources
The Timer/Watchdog issues an interrupt request
at every End of Count, when this feature is ena-
bled.
TIMER WATCHDOG
A pair of control bits, IA0S (EIVR.1, Interrupt A0 se-
lection bit) and TLIS (EIVR.2, Top Level Input Se-
lection bit) allow the selection of 2 interrupt sources
(Timer/Watchdog End of Count, or External Pin)
handled in two different ways, as a Top Level Non
Maskable Interrupt (Software Reset), or as a
source for channel A0 of the external interrupt logic.
RESET
WDGEN (WCR.6)
A block diagram of the interrupt logic is given in
Figure 3.
0
Note: Software traps can be generated by setting
the appropriate interrupt pending bit.
MUX
INTA0 REQUEST
INT0
1
Table 1 below, shows all the possible configura-
tions of interrupt/reset sources which relate to the
Timer/Watchdog.
IA0S (EIVR.1)
A reset caused by the watchdog will set bit 6,
WDGRES of R242 - Page 55 (Clock Flag Regis-
ter). See section CLOCK CONTROL REGIS-
TERS.
0
1
MUX
TOP LEVEL
INTERRUPT REQUEST
NMI
TLIS (EIVR.2)
VA00293
Table 14. Interrupt Configuration
Control Bits
Enabled Sources
INTA0
Operating Mode
WDGEN
IA0S
TLIS
Reset
Top Level
0
0
0
0
0
0
1
1
0
1
0
1
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
SW TRAP
SW TRAP
Ext Pin
SW TRAP
Ext Pin
SW TRAP
Ext Pin
Watchdog
Watchdog
Watchdog
Watchdog
Ext Pin
1
1
1
1
0
0
1
1
0
1
0
1
Ext Reset
Ext Reset
Ext Reset
Ext Reset
Timer
Timer
Ext Pin
Ext Pin
Timer
Ext Pin
Timer
Timer
Timer
Timer
Timer
Ext Pin
Legend:
WDG = Watchdog function
SW TRAP = Software Trap
Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0
interrupts), only the INTA0 interrupt is taken into account.
77/178
ST92185 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.5 Register Description
TIMER/WATCHDOG PRESCALER REGISTER
(WDTPR)
The Timer/Watchdog is associated with 4 registers
mapped into Group F, Page 0 of the Register File.
R250 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
WDTHR: Timer/Watchdog High Register
WDTLR: Timer/Watchdog Low Register
WDTPR: Timer/Watchdog Prescaler Register
WDTCR: Timer/Watchdog Control Register
7
0
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Three additional control bits are mapped in the fol-
lowing registers on Page 0:
Bits 7:0 = PR[7:0] Prescaler value.
A programmable value from 1 (00h) to 256 (FFh).
Watchdog Mode Enable, (WCR.6)
Top Level Interrupt Selection, (EIVR.2)
Interrupt A0 Channel Selection, (EIVR.1)
Warning: In order to prevent incorrect operation of
the Timer/Watchdog, the prescaler (WDTPR) and
counter (WDTRL, WDTRH) registers must be ini-
tialised before starting the Timer/Watchdog. If this
is not done, counting will start with the reset (un-in-
itialised) values.
Note: The registers containing these bits also con-
tain other functions. Only the bits relevant to the
operation of the Timer/Watchdog are shown here.
Counter Register
This 16-bit register (WDTLR, WDTHR) is used to
load the 16-bit counter value. The registers can be
read or written “on the fly”.
WATCHDOG TIMER CONTROL REGISTER
(WDTCR)
R251- Read/Write
Register Page: 0
Reset value: 0001 0010 (12h)
TIMER/WATCHDOG HIGH REGISTER (WDTHR)
R248 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
7
0
ST_SP S_C INMD1 INMD2 INEN OUTMD WROUT OUTEN
7
0
R15 R14 R13 R12 R11 R10
R9
R8
Bit 7 = ST_SP: Start/Stop Bit.
This bit is set and cleared by software.
0: Stop counting
Bits 7:0 = R[15:8] Counter Most Significant Bits.
1: Start counting (see Warning above)
TIMER/WATCHDOG LOW REGISTER (WDTLR)
R249 - Read/Write
Bit 6 = S_C: Single/Continuous.
This bit is set and cleared by software.
0: Continuous Mode
Register Page: 0
Reset value: 1111 1111b (FFh)
1: Single Mode
7
0
Bits 5:4 = INMD[1:2]: Input mode selection bits.
R7
R6
R5
R4
R3
R2
R1
R0
These bits select the input mode:
INMD1
INMD2
INPUT MODE
Event Counter
Bits 7:0 = R[7:0] Counter Least Significant Bits.
0
0
1
1
0
1
0
1
Gated Input (Reset value)
Triggerable Input
Retriggerable Input
78/178
ST92185 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
Bit 3 = INEN: Input Enable.
This bit is set and cleared by software.
0: Disable input section
by the user program. At System Reset, the Watch-
dog mode is disabled.
Note: This bit is ignored if the Hardware Watchdog
option is enabled by pin HW0SW1 (if available).
1: Enable input section
Bit 2 = OUTMD: Output Mode.
This bit is set and cleared by software.
0: The output is toggled at every End of Count
1: The value of the WROUT bit is transferred to the
output pin on every End Of Count if OUTEN=1.
EXTERNAL INTERRUPT VECTOR REGISTER
(EIVR)
R246 - Read/Write
Register Page: 0
Reset value: xxxx 0110 (x6h)
Bit 1 = WROUT: Write Out.
7
x
0
x
The status of this bit is transferred to the Output
pin when OUTMD is set; it is user definable to al-
low PWM output (on Reset WROUT is set).
x
x
x
x
TLIS IA0S
Bit 2 = TLIS: Top Level Input Selection.
Bit 0 = OUTEN: Output Enable bit.
This bit is set and cleared by software.
0: Disable output
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
1: NMI is TL interrupt source
1: Enable output
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source
1: External Interrupt pin is INTA0 source
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Warning: To avoid spurious interrupt requests,
the IA0S bit should be accessed only when the in-
terrupt logic is disabled (i.e. after the DI instruc-
tion). It is also necessary to clear any possible in-
terrupt pending requests on channel A0 before en-
abling this interrupt channel. A delay instruction
(e.g. a NOP instruction) must be inserted between
the reset of the interrupt pending bit and the IA0S
write instruction.
Reset value: 0111 1111 (7Fh)
7
x
0
x
WDGEN
x
x
x
x
x
Bit 6 = WDGEN: Watchdog Enable (active low).
Resetting this bit via software enters the Watch-
dog mode. Once reset, it cannot be set anymore
Other bits are described in the Interrupt section.
79/178
ST92185 - STANDARD TIMER (STIM)
7.2 STANDARD TIMER (STIM)
Important Note: This chapter is a generic descrip-
tion of the STIM peripheral. Depending on the ST9
device, some or all of the interface signals de-
scribed may not be connected to external pins. For
the list of STIM pins present on the particular ST9
device, refer to the pinout description in the first
section of the data sheet.
– triggerable input mode,
– retriggerable input mode.
STOUT can be used to generate a Square Wave
or Pulse Width Modulated signal.
The Standard Timer is composed of a 16-bit down
counter with an 8-bit prescaler. The input clock to
the prescaler can be driven either by an internal
clock equal to INTCLK divided by 4, or by
CLOCK2 derived directly from the external oscilla-
tor, divided by device dependent prescaler value,
thus providing a stable time reference independ-
ent from the PLL programming or by an external
clock connected to the STIN pin.
7.2.1 Introduction
The Standard Timer includes a programmable 16-
bit down counter and an associated 8-bit prescaler
with Single and Continuous counting modes capa-
bility. The Standard Timer uses an input pin (STIN)
and an output (STOUT) pin. These pins, when
available, may be independent pins or connected
as Alternate Functions of an I/O port bit.
The Standard Timer End Of Count condition is
able to generate an interrupt which is connected to
one of the external interrupt channels.
STIN can be used in one of four programmable in-
put modes:
The End of Count condition is defined as the
Counter Underflow, whenever 00h is reached.
– event counter,
– gated external input mode,
Figure 47. Standard Timer Block Diagram
n
INMD1 INMD2
INEN
INPUT
&
1
STIN
STH,STL
STP
(See Note 2)
CLOCK CONTROL LOGIC
MUX
16-BIT
8-BIT PRESCALER
DOWNCOUNTER
STANDARD TIMER
CLOCK
INTCLK/4
END OF
COUNT
CLOCK2/x
OUTMD2
OUTMD1
1
STOUT
OUTPUT CONTROL LOGIC
EXTERNAL
1
INTERRUPT
INTERRUPT
INTS
CONTROL LOGIC
INTERRUPT REQUEST
Note 1: Pin not present on all ST9 devices.
Note 2: Depending on device, the source of the INPUT & CLOCK CONTROL LOGIC block
may be permanently connected either to STIN or the RCCU signal CLOCK2/x. In devices without STIN and CLOCK2, the
INEN bit must be held at 0.
80/178
ST92185 - STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
7.2.2 Functional Description
7.2.2.1 Timer/Counter control
bles the input mode selected by the INMD2 and
INMD1 bits. If the input is disabled (INEN="0"), the
values of INMD2 and INMD1 are not taken into ac-
count. In this case, this unit acts as a 16-bit timer
(plus prescaler) directly driven by INTCLK/4 and
transitions on the input pin have no effect.
Start-stop Count. The ST-SP bit (STC.7) is used
in order to start and stop counting. An instruction
which sets this bit will cause the Standard Timer to
start counting at the beginning of the next instruc-
tion. Resetting this bit will stop the counter.
Event Counter Mode (INMD1 = "0", INMD2 = "0")
The Standard Timer is driven by the signal applied
to the input pin (STIN) which acts as an external
clock. The unit works therefore as an event coun-
ter. The event is a high to low transition on STIN.
Spacing between trailing edges should be at least
the period of INTCLK multiplied by 8 (i.e. the max-
imum Standard Timer input frequency is 3 MHz
with INTCLK = 24MHz).
If the counter is stopped and restarted, counting
will resume from the value held at the stop condi-
tion, unless a new constant has been entered in
the Standard Timer registers during the stop peri-
od. In this case, the new constant will be loaded as
soon as counting is restarted.
A new constant can be written in STH, STL, STP
registers while the counter is running. The new
value of the STH and STL registers will be loaded
at the next End of Count condition, while the new
value of the STP register will be loaded immedi-
ately.
Gated Input Mode (INMD1 = "0", INMD2 = “1”)
The Timer uses the internal clock (INTCLK divided
by 4) and starts and stops the Timer according to
the state of STIN pin. When the status of the STIN
is High the Standard Timer count operation pro-
ceeds, and when Low, counting is stopped.
WARNING:Inordertopreventincorrectcountingof
theStandardTimer,theprescaler(STP)andcounter
(STL, STH) registers must be initialised before the
starting of the timer. If this is not done, counting will
start with the reset values (STH=FFh, STL=FFh,
STP=FFh).
TriggerableInputMode(INMD1=“1”,INMD2=“0”)
The Standard Timer is started by:
a) setting the Start-Stop bit, AND
b) a High to Low (low trigger) transition on STIN.
Single/Continuous Mode.
The S-C bit (STC.6) selects between the Single or
Continuous mode.
In order to stop the Standard Timer in this mode, it
is only necessary to reset the Start-Stop bit.
SINGLE MODE: at the End of Count, the Standard
Timer stops, reloads the constant and resets the
Start/Stop bit (the user programmer can inspect
the timer current status by reading this bit). Setting
the Start/Stop bit will restart the counter.
Retriggerable Input Mode (INMD1 = “1”, INMD2
= “1”)
In this mode, when the Standard Timer is running
(with internal clock), a High to Low transition on
STIN causes the counting to start from the last
constant loaded into the STL/STH and STP regis-
ters. When the Standard Timer is stopped (ST-SP
bit equal to zero), a High to Low transition on STIN
has no effect.
CONTINUOUS MODE: At the End of the Count, the
counter automatically reloads the constant and re-
starts.ItisonlystoppedbyresettingtheStart/Stopbit.
The S-C bit can be written either with the timer
stopped or running. It is possible to toggle the S-C
bit and start the Standard Timer with the same in-
struction.
7.2.2.3 Time Base Generator (ST9 devices
without Standard Timer Input STIN)
For devices where STIN is replaced by a connec-
tion to CLOCK2, the condition (INMD1 = “0”,
INMD2 = “0”) will allow the Standard Timer to gen-
erate a stable time base independent from the PLL
programming.
7.2.2.2 Standard Timer Input Modes (ST9
devices with Standard Timer Input STIN)
Bits INMD2, INMD1 and INEN are used to select
the input modes. The Input Enable (INEN) bit ena-
81/178
ST92185 - STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
7.2.2.4 Standard Timer Output Modes
ic is disabled (i.e. after the DI instruction). It is also
necessary to clear any possible interrupt pending
requests on the corresponding external interrupt
channel before enabling it. A delay instruction (i.e.
a NOP instruction) must be inserted between the
reset of the interrupt pending bit and the INTS
write instruction.
OUTPUT modes are selected using 2 bits of the
STC register: OUTMD1 and OUTMD2.
No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”)
The output is disabled and the corresponding pin
is set high, in order to allow other alternate func-
tions to use the I/O pin.
Square Wave Output Mode (OUTMD1 = “0”,
7.2.4 Register Mapping
OUTMD2 = “1”)
Depending on the ST9 device there may be up to 4
Standard Timers (refer to the block diagram in the
first section of the data sheet).
The Standard Timer toggles the state of the
STOUT pin on every End Of Count condition. With
INTCLK = 24MHz, this allows generation of a
square wave with a period ranging from 333ns to
5.59 seconds.
Each Standard Timer has 4 registers mapped into
Page 11 in Group F of the Register File
In the register description on the following page,
register addresses refer to STIM0 only.
PWM Output Mode (OUTMD1 = “1”)
The value of the OUTMD2 bit is transferred to the
STOUT output pin at the End Of Count. This al-
lows the user to generate PWM signals, by modi-
fying the status of OUTMD2 between End of Count
events, based on software counters decremented
on the Standard Timer interrupt.
STD Timer Register
Register Address
R240 (F0h)
STIM0
STIM1
STIM2
STIM3
STH0
STL0
STP0
STC0
STH1
STL1
STP1
STC1
STH2
STL2
STP2
STC2
STH3
STL3
STP3
STC3
R241 (F1h)
R242 (F2h)
R243 (F3h)
R244 (F4h)
R245 (F5h)
R246 (F6h)
R247 (F7h)
R248 (F8h)
R249 (F9h)
R250 (FAh)
R251 (FBh)
R252 (FCh)
R253 (FDh)
R254 (FEh)
R255 (FFh)
7.2.3 Interrupt Selection
The Standard Timer may generate an interrupt re-
quest at every End of Count.
Bit 2 of the STC register (INTS) selects the inter-
rupt source between the Standard Timer interrupt
and the external interrupt pin. Thus the Standard
Timer Interrupt uses the interrupt channel and
takes the priority and vector of the external inter-
rupt channel.
If INTS is set to “1”, the Standard Timer interrupt is
disabled; otherwise, an interrupt request is gener-
ated at every End of Count.
Note: When enabling or disabling the Standard
Timer Interrupt (writing INTS in the STC register)
an edge may be generated on the interrupt chan-
nel, causing an unwanted interrupt.
Note: The four standard timers are not implement-
ed on all ST9 devices. Refer to the block diagram
of the device for the number of timers.
To avoid this spurious interrupt request, the INTS
bit should be accessed only when the interrupt log-
82/178
ST92185 - STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
7.2.5 Register Description
STANDARD TIMER CONTROL REGISTER
(STC)
COUNTER HIGH BYTE REGISTER (STH)
R240 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
R243 - Read/Write
Register Page: 11
Reset value: 0001 0100 (14h)
7
0
7
0
ST-SP S-C INMD1 INMD2 INEN INTS OUTMD1 OUTMD2
ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 ST.8
Bit 7 = ST-SP: Start-Stop Bit.
This bit is set and cleared by software.
0: Stop counting
Bits 7:0 = ST.[15:8]: Counter High-Byte.
1: Start counting
COUNTER LOW BYTE REGISTER (STL)
R241 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
Bit 6 = S-C: Single-Continuous Mode Select.
This bit is set and cleared by software.
0: Continuous Mode
7
0
1: Single Mode
ST.7 ST.6 ST.5 ST.4 ST.3 ST.2 ST.1 ST.0
Bits 5:4 = INMD[1:2]: Input Mode Selection.
These bits select the Input functions as shown in
Section 0.1.2.2, when enabled by INEN.
Bits 7:0 = ST.[7:0]: Counter Low Byte.
Writing to the STH and STL registers allows the
user to enter the Standard Timer constant, while
reading it provides the counter’s current value.
Thus it is possible to read the counter on-the-fly.
INMD1 INMD2 Mode
0
0
1
1
0
1
0
1
Event Counter mode
Gated input mode
Triggerable mode
Retriggerable mode
STANDARD TIMER PRESCALER REGISTER
(STP)
R242 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
Bit 3 = INEN: Input Enable.
This bit is set and cleared by software. If neither
the STIN pin nor the CLOCK2 line are present,
INEN must be 0.
7
0
0: Input section disabled
1: Input section enabled
STP.7 STP.6 STP.5 STP.4 STP.3 STP.2 STP.1 STP.0
Bit 2 = INTS: Interrupt Selection.
0: Standard Timer interrupt enabled
1: Standard Timer interrupt is disabled and the ex-
ternal interrupt pin is enabled.
Bits 7:0 = STP.[7:0]: Prescaler.
The Prescaler value for the Standard Timer is pro-
grammed into this register. When reading the STP
register, the returned value corresponds to the
programmed data instead of the current data.
00h: No prescaler
Bits 1:0 = OUTMD[1:2]: Output Mode Selection.
These bits select the output functions as described
in Section 0.1.2.4.
01h: Divide by 2
FFh: Divide by 256
OUTMD1 OUTMD2 Mode
0
0
1
0
1
x
No output mode
Square wave output mode
PWM output mode
83/178
ST92185 - DISPLAY STORAGE RAM INTERFACE
7.3 DISPLAY STORAGE RAM INTERFACE
7.3.1 Introduction
The necessary time slots are provided to each unit
for realtime response.
The Display RAM (TDSRAM) is used to hold the
OSD data for display.
FEATURES:
■ Memory mapped in CPU Memory Space
■ Direct CPU access without significant slowdown
It can be shared by the following units:
– Display Unit (DIS). This OSD generator is de-
scribed in a separate chapter.
– CPU accesses for control.
Figure 48. General Block Diagram
VR02094B
84/178
ST92185 - DISPLAY STORAGE RAM INTERFACE
7.3.2.1 TV Line Timesharing
TDSRAM (Cont’d)
7.3.2 Functional Description
The Data Storage RAM Interface (TRI) manages
the data flows between the different sub-units (dis-
play and CPU interface) and the internal RAM. A
specific set of buses (8 bit data TRIDbus, 13 bit
address TRIAbus) is dedicated to these data
flows.
During a TV line, to maintain maximum perform-
ance, a continuous cycle is run repetitively. This
cycle is divided in 8 sub-cycles called "slots".
This 8-slot cycle is repeated continuously until the
next TV line-start occurs (horizontal sync pulse de-
tected). When a horizontal sync pulse is detected,
the running slot is completed and the current cycle
is broken.
As this TDSRAM interface has to manage TV ori-
ented real time signals (On-Screen-Display):
– Its timing generator uses the same frequency
generator as for the Display (Pixel frequency
multiplier),
The following naming convention is used: "CPU"
stands for direct CPU access slot, "DIS" stands for
Display reading slot. Each slot represents a single
byte exchange (read or write) between the TD-
SRAM memory and the other units:
– Its controller is hardware synchronized to the ba-
sic horizontal and vertical sync signals got
through the CSYNC Controller,
Display Reading (DIS). 1 byte is read from the
TDSRAM and sent to the display unit, the address
being defined by the display address generator.
– Its architecture gives priority to the TV real time
constraints: whenever there is any access con-
tention between the CPU (only in case of direct
CPU access) and one of the hardware units, the
CPU automatically enters a "wait" configuration
until its request is serviced.
CPU Access (CPU). 1 byte is exchanged (read or
written) between the TDSRAM and the CPU, the
address being defined by the CPU address bus.
85/178
ST92185 - DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
7.3.3 Initialisation
Use the CONFIG register to initialise and start
the TRI. Note: The DON bit can only be changed
while GEN=0
7.3.3.1 Clock Initialisation
Before initialising the TRI, first initialise the pixel
clock. Refer to the Application Examples in the
OSD chapter and to the RCCU chapter for a de-
scription of the clock control registers.
Example:
spp #0x26
ld config, #0x02 ; DON,GEN=0
or config, #0x01 ; set GEN=1
7.3.3.2 TRI Initialisation
It is recommended to wait for a stable clock issued
from the Pixel frequency multiplier before enabling
the TDSRAM interface.
During and after a reset, the TDSRAM interface is
forced into its "disable" mode where the sequencer
is forced into its idle state.
86/178
ST92185 - DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
7.3.4 Register Description
Bit 1 = DON: Display ON/OFF.
0: No display reading allowed (display slot com-
RAM INTERFACE CONFIGURATION REGIS-
TER (CONFIG )
R252 - Read/Write
Register Page: 38
Reset Value: 0000 0010 (02h)
pletely used for CPU access).
1: Display reading enabled during the respective
access slot.
Note: DON can be changed only when the TRI is
off (GEN = 0).
7
0
0
<
Bit 0 = GEN: RAM Interface General Enable.
0: TRI off. Display reading and CPU accesses are
not allowed. When GEN=0, the Automatic Wait
Cycle insertion, while trying to access the
TDSRAM, is disabled.
0
0
0
0
0
DON GEN
Bit 7:2 = Reserved, keep in reset state.
1: TRI on.
87/178
ST92185 - ON SCREEN DISPLAY (OSD)
7.4 ON SCREEN DISPLAY (OSD)
7.4.1 Introduction
A smart pixel processing unit provides enhanced
features such as rounding or fringe for a better pic-
ture quality. Other smart functions such as true
Scrolling and cursor modes allow designing a high
quality display application.
The OSD displays Teletext or other character data
and menus on a TV screen.
In serial mode, characters are coded on one byte.
The display is fully compliant with the WST Tele-
text level 1.5.
7.4.2 General Features
■ Serial Character Mode supporting Teletext level
In parallel mode, characters are coded on two
bytes, one byte being the font address (character
code), the second byte being used for attribute
control, which can be combined with the serial at-
tribute capabilities. In this mode, the display meets
a significant part of the WST Teletext level 2 spec-
ification.
1.5
■ Parallel Character Mode for TV character
displays (for example channel selection or
volume control menus)
■ 40 or 80 characters/row
■ Full Page Mode:
23 rows plus 1 Header and 2 Status Rows
In order to save memory resources (reduce sys-
tem cost), two display modes are provided with ei-
ther a page mode display mode (teletext stan-
dard, 26 rows) or a line mode (up to 12 rows) for
non teletext specific menus.
■ Line Mode:
Up to 12 rows plus 1 Header and 2 Status Rows.
■ 4/3 or 16/9 screen format
■ Synchronization to TV deflection, by Hsync and
The OSD is seen by the ST9 as a peripheral which
has registers mapped in the Paged Register
space.
Vsync or Csync.
■ Box Mode: Display text inside and outside box
solid, transparant or blank
The character codes to be displayed are taken
from the TDSRAM memory. They are addressed
by the display with the real time sequencer
through the TDSRAM interface character by char-
acter.
■ Rounding and Fringing
■ Cursor Control
■ Concealing
■ Scrolling
The font ROM contains 512 characters. The stan-
dard European font contains all characters re-
quired to support Eastern and Western European
languages. Each character can be defined by the
user with the OSD Screen/Font Editor. All fonts
(except the G1 mosaic font) are fully definable by
masking the pixel ROM content.
■ Semi-transparent mode (text windowing inside
video picture)
■ Half-Tone mode (reduces video intensity inside
a box)
■ Normal character size 10 x 10 dots.
■ Other character sizes available as follows:
Display is done under control of the ST9 CPU and
the vertical and horizontal TV synchro lines.
(SH: Single Height, SW: Single Width, DH: Double
Height, DW: Double Width, DS: Double Size)
The OSD provides the Red, Green, Blue signals
and the Fast Blanking switching signal through
four analog outputs. The three Color outputs use a
3-level DAC which can generate half-intensity col-
ors in addition to the standard saturated colors.
Both Serial and
Parallel Mode
SH x SW = 10 * 10 dots
Parallel Display Mode
only
SH x DW = 10 * 20 dots
DS=DH x DW = 20 * 20
dots
DH x SW = 20 * 10 dots
The Display block diagram is shown on Figure 1.
88/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
■ Serial character attributes:
– National Character set selection
– National Character mode selection
– Foreground Color (8 possibilities in Serial Full
page display mode)
– Global Double Height display (Zooming Func-
tion)
– Background Color (8 possibilities)
– Flash / Steady
– Global Fringe Enable
– Start Box / End Box
– Global Rounding Enable
■ Cursor Control:
– Double height
– Horizontal position (by character)
– Vertical position (by row)
– Flash, Steady or Underline Cursor Modes
– Conceal / display
– Fringe
– Contiguous Mosaic / Separated Mosaic
– Hold / Release Mosaic
– G0 font switch (in triple G0 mode)
– Color Cursor with inverted foreground / invert-
ed background
■ Scrolling Control:
■ Parallel character attributes (in parallel display
– Vertical scrolling available:
Programmable rolling window if Normal
Height and 40 char/row
mode):
– Underline
– Double height & Double width
– Upper Half-Character
– Top-Down or Bottom-Up shift
– Freeze Display
■ Character fonts:
– Smooth Rounding
– Box mode
576 different characters available:
– Font Selection G0/Extended menu
– Selection of 15 background Colors
– Selection of 8 foreground Colors
■ Global Screen attributes:
– 128 mosaic matrix characters (G1), hardware
defined (64 contiguous, 64 separated).
– 512 character ROM fonts, all user defined:
– 96-character basic character set (G0)
– Fine and coarse Horizontal Adjustment (for
the whole 26 rows)
– 128 characters shared between G2 X/26 and
Menu characters
– Vertical Adjustment (for the whole page)
– Blanking Adjustment
– 96 Extended Menu Characters
– Two national character set modes (mutually
exclusive ROM options):
– Default Background Color (up 15 colors with
use of half-intensity attribute)
Single G0 mode
– Default Foreground Color (up 15 colors with
use of half-intensity attribute)
A font combining 83 characters from
the G0 basic set (latin) and 13 charac-
ters selected from 15 National charac-
ter subsets
– Semi transparent display (active only on back-
ground)
Triple G0 mode allowing different alpha-
bets
– Translucency: OSD background color mixed
with video picture.
Three 96-character fonts (e.g. latin,
arabic, cyrillic ...)
– Full screen Color (15)
National
Set
G2 (X26+
Menu)
Extended
Menu
G1
(mosaic)
Mode
G0
Triple G0
Single G0
3*96
1*83
N/A
128
128
96
96
64
64
15*13
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 49. Display Block Diagram
RAM INTERFACE
RAM @
Gen RAM Add
Row Counter
Comp 10/20 Comp VPOS
Char Counter
Comp 10/20
Comp HPOS
Pixel Counter
Line Counter
Scroll N Row
Scroll 1 Row
HPOS
CURSOR
CONTROL
SCROLLING
CONTROL
VPOS
Char Cursor
Row Cursor
Mode Ctrl
Gen PLA Cmd
Gen ROM Add
MOSAIC
PLA
PIXEL
CONTROL
ROM
Serial/Parallel Attributes
Shift Register (10b)
TSLU
Full Screen
R
G
Def. Backg
Def. Foreg
B
Cur. Backg
Pixel Control
L1/L1+
Cur. Foreg
L1/L1+
Fast Blanking
mux
mux
FB
TRB
Char Decoding
Attributes Decoding
ST9 Access
On Hsync
Character Code
Parallel Attributes
On Ckpix
RAM INTERFACE
VR02112E
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.3 Functional Description
7.4.3.1 Screen Display Area
The three special rows, a Header and two Status
rows have specific meanings and behaviour. They
are always displayed the same way (40 charac-
ters) and at the same place. In these rows, size at-
tributes, scrolling and 80-character modes are not
allowed.
The screen is divided in 26 rows of basically 40
characters. From row 1 to row 23, it is possible to
display 80 characters per row with the following re-
strictions:
All row content, including the Header and Status
rows, is fully user-definable.
– Serial mode only
– No rounding or fringe
Figure 50. Definition of Displayed Areas
ROW 0 “HEADER”
26 LINES
(TEXT PAGE)
“FULL SCREEN”
AREA
ROW 24 “STATUS ROW 0”
ROW 25 “STATUS ROW 1”
40/80 CHARACTERS
Figure 51. Screen Display Area.
91/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.3.2 Color Processing
A set of colors defines the final color of the current
pixel.
The color of any pixel on screen is the result of a
priority processing among several layers which
are (going from the lowest priority to the highest
one):
In general, the character matrix content is dis-
played as it is, the pixel processing adding the
shape and the color information received from the
current attributes. Only three kinds of attributes al-
ter the displayed pixel. They are the following:
■ Full Screen Color where nothing is processed
■ Default Background Color (it assumes pixel is
7.4.3.5 Rounding
off)
Rounding can be enabled for the whole display us-
ing the GRE global attribute bit (See Figure 1) In
this effect one half-dot is added in order to smooth
the diagonal lines. This processing is built into the
hardware. The half-dot is painted as foreground.
This half-dot is field-sensitive for minimum vertical
size (Figure 4).
An extra ‘smooth rounding’ capability is also built-
in (see Figure 5). In smooth rounding, a pixel is
added even if dots make an ‘L’. This capability is
activated using a parallel attribute (See Table 4)
■ Serial Background Color (pixel off, but
background color serial attributes activated)
■ Parallel Background Color (pixel off, but
background color parallel attribute activated)
■ Default Foreground Color (pixel on, but no
foreground attribute activated)
■ Serial Foreground Color (pixel on and
foreground serial attribute activated)
■ Parallel Foreground Color (pixel on and
foreground parallel attribute activated)
7.4.3.6 Underline
Color processing is also the result of register con-
trol bits (for global color attributes) and color ori-
ented attribute bits (from serial or parallel at-
tributes), refer to the Figure 0.1.4.3
In this effect the last TV line of the character is dis-
played as foreground (Figure 4).
7.4.3.7 Fringe
7.4.3.3 Pixel Clock Control
The fringe is a half-dot black border surrounding
completely the character foreground. This half-dot
is field sensitive for minimum vertical size (Figure
4).
The pixel clock is generated outside of the display
macrocell by the on-chip Pixel Frequency multipli-
er which provides great frequency flexibility con-
trolled by software (refer to the RCCU chapter).
For example, reconfiguring the application from a
4/3 screen format to a 16/9 format is just a matter
of increasing the pixel frequency (i.e. reprogram-
ming the pixel frequency multiplier to its new val-
ue).
7.4.3.8 Translucency
Certain video processors are able to mix the RGB
and video signals. This function of the chroma pro-
cessor is then driven by the TSLU output pin of the
ST9 device. See Figure 7.
7.4.3.9 Half-Tone
The output signal of the pixel frequency multiplier
is rephased by the Skew Corrector to be perfectly
in phase with the horizontal sync signal which
drives the display.
If the HT signal is activated, for example, while a
text box is displayed and a transparant back-
ground selected for all the display (MM bit =1 in
the FSCCR register), the HT signal performs a
contrast reduction to the background inside the
box. See Figure 8.
7.4.3.4 Display Character
Each character is made up of a 10 x 10 dots ma-
trix. All character matrix contents are fully user de-
finable and are stored in the pixel ROM (except the
G1 mosaic set which is hardware defined).
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 52. Display Character scheme
NORMAL MODE
ROUNDING MODE
FRINGE MODE
Background
Foreground
Fringe
Background
Foreground
Smooth Rounding
Underline
VR02112B
Figure 53. Rounding and Fringe Effects
Dot (four pixels)
Added pixel
Added pixel
Added pixel
Smooth Rounding Effect
Global Rounding Effect
Fringe Effect
93/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4 Programming the Display
■ Cursor Control
■ Scrolling Control
7.4.4.1 Global Attributes
All the characteristics of the display are managed
by programmable attributes:
■ Global Attributes
■ Serial Attributes
■ Parallel Attributes (active until a superseding
serial or parallel attribute).
Table 15. Global Attributes
These global attributes are defined through their
corresponding registers (see the Register Descrip-
tion).
Control
Global Attributes
Description
Register
DCM0R
R250 (FAh)
Page 32
0= Display Off (Default)
Display Enable (DE)
1= Display On
0= 4/3 Screen Format (Default)
4/3 or 16/9 Format (SF)
DCM0R
DCM0R
1= 16/9 Screen Format
0= Reveal any text defined as concealed by serial attributes (Default)
1= Conceal any text defined as concealed by serial attributes
Conceal Enable (CE)
0= Fringe Disabled (Default)
1= If SWE in NCSR register is reset, it acts as Fringe enable (toggle with
serial attribute 1Bh). Active on the whole page but not in 80-character
mode.
Fringe Enable (FRE)
DCM0R
0= Global fringe mode off
Global Fringe Enable (GFR)
DCM0R
DCM0R
1= Display all text in page in fringe mode
0= Disabled (Default)
Global Rounding Enable
(GRE)
1= Rounding active on the whole page but not in 80-character mode.
0=Disabled (default)
1=Enabled
Semi-transparent Mode
(STE)
DCM0R
The Fast Blanking signal is toggled with the double pixel clock rate on Back-
ground and full screen area in 40 character mode.
Note: Semi-transparent mode shows a visible grid on screen.
NCSR R245
(F5h) Page
32 and FSC-
CR R243
The TSLU signal is active when the OSD displays the background and full
screen area and is inactive during foreground or if no display. This output
pin is used with a Chroma processor to mix the video input with the RGB to
get full translucency.
Translucency (HTC and
TSLE)
Page 32
NCSR R245
(F5h) Page
The HT signal is active when the OSD displays the background and full
Half-Tone (HTC and TSLE) screen area and is inactive during foreground or if no display. The HT signal 32 and FSC-
is used with a video processor to perform a contrast reduction.
CR R243
Page 32
0=Single page (40 Characters per row) (default)
40/80 Chars/Row (S/D)
DCM0R
1= Two pages are displayed contiguously (80 Characters per row). In this
mode, only serial mode is available.
DCM1R
R251 (FBh)
Page 32
0=Display when Fast Blanking output is low (default)
1=Display when Fast Blanking output is high
Fast Blanking Active Level
Serial/Parallel Mode (SPM)
0= Serial Mode (Default)
DCM1R
DCM1R
1= Parallel Mode
0 = Full Page Mode (Default) 23 lines plus 1 header and two status lines.
1= Line Mode
Page or Line Display Mode
(PM)
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 16. Global Attributes (Cont’d)
Global Attributes
Control
Register
Description
FSCCR
R243 (F3h)
Page 32
Box Control ModeText In/
Out
Text In/ Text Out Box configurable with 3 bits. Refer to FSCCR register de-
scription for details.
Refer to the register description for bit settings. Active on the whole page,
this setting adjusts the vertical delay between the rising edge of Vsync and
the beginning of the display area. The display color in this delay adjustment
area is defined by the Full Screen color.
VPOSR
R242 (F2h)
Page 32
Vertical Adjustment
Refer to the register description for bit settings. Active on the whole page,
this adjustment is the horizontal delay between the rising edge of Hsync
and the beginning of the display area. The display in this delay area is the
full row color.
HPOSR
R241 (F1h)
Page 32
Horizontal Adjustment
Two kinds of horizontal adjustment are available. When the tube is in a 4/3
format, only a horizontal delay is necessary before starting the active dis-
play area. When the tube is in 16/9 format, an additional horizontal adjust-
ment is necessary to keep the display area centered on the screen.
NCSR R245
(F5h) Page
32
National Character Subset Refer to the register description for bit settings. Chooses which national font
Selection
sub-set is to be used with the G0 character set.
0 = Single G0 character set mode (default)
Single G0 or Triple G0 mode 1 = Triple G0 character set mode
selection
NCSR
In applications with multiple alphabets in the same display, it is possible to
switch from one character set to another on the fly (see serial attributes).
SCLR
Active on the whole page with header, but not on the status rows. When
R248 (F8h)
Global Double Height
Global Double Height is active, either the top half or the bottom half of the and SCHR
screen is visible.
R249 (F9h)
Page 32
DCR R240
(F0h) Page
33
This color is displayed as background color if no serial or parallel attributes
are defined for the displayed row.
Background default color
Foreground default color
Full screen color
This color is displayed as foreground color if no serial or parallel attributes
are defined for the displayed row. These default colors are selected at each DCR
beginning of a line and are defined by means of the corresponding register.
FSCCR
R243 (F3h)
Page 32
Color displayed outside of the vertical display area.
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 54. Semi-Transparent Display Scheme and Fast Blanking Behaviour
NORMAL DISPLAY
SEMI TRANSPARENT DISPLAY
Fringe
line 3 Field odd
line 4 Field even
Solid Background
Solid Foreground + Rounding
Video
LINE 3 NORMAL DISPLAY
LINE 4 NORMAL DISPLAY
LINE 3 SEMI TRANSPARANT DISPLAY
CKPIX
CKPIX
R, G, B
R, G, B
FB
RGB
FB
VIDEO
LINE 4 SEMI TRANSPARANT DISPLAY
CKPIX
CKPIX
R, G, B
FB
R, G, B
FB
VR02112C
Figure 55. Translucent Display Scheme
line 3
Fringe
Solid Background
Solid Foreground + Rounding
Video
NORMAL DISPLAY LINE 3
CKPIX
R, G, B(40c)
FB
TSLU
VR02112J
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 56. Half-Tone Display Scheme
VIDEO PROCESSOR
RGB
Switch
Rout
Gout
Internal Red
Contrast
Internal Green
Reduction
Bout
Internal Blue
HT
R G B FB
ST9 MCU
97/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.2 Row Attributes
Row Enable Bits
The header and status row attributes are set using
the HSCR R244 (F4h) Page 32 register. The row
enable bits as set in registers DE0R .. 2 R253
..255 Page 32.
1 bit per row, for rows from 1 to 23, in page mode.
Serial Attributes
Serial Mode is selected by resetting the SPM bit in
register DCM1R R251 (FBh) Page 32.
Header Enable
Serial attributes are active until the end of the line
or a superseding serial attribute.
When the display is in line mode, row 0, called the
header, is also usable. It no longer acts as a head-
er but simply as an additional row.
In this display mode, the attribute code and the
character code are in the same memory area (Fig-
ure 9).
Status Row Enable
The display of the two status rows can be enabled
individually.
The attribute takes the place of an alpha charac-
ter, and the OSD displays a space character de-
fined on 1 byte in Serial Mode:
Figure 57. Example of a Row in Serial Mode
FLASHING
Display
A A
A R O Z A A
D
Z
A
Propagation
can be half intensity
Default background
Default foreground
global
Length of row = 40 Characters
Memory location
Fh
Bb
Sty
Sc
A
A
Z A R D O Z A A A
Characters
Steady attribute
Black background attribute
Foreground color attribute
Flashing attribute
VR02115A
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 17. Serial Attribute Codes
b[7:3]
00000
00001
00010
00011
b[2:0]
Foreground Color
(Alpha Chars)
Black
Foreground Color
(Mosaic Chars)
Black (3)
Red
000
001
010
011
100
101
110
111
Flash
Steady (1, 2)
Box OFF (1)
Box ON
Conceal (2)
Red
Contiguous Mosaic (1, 2)
Separated Mosaic (2)
Fringe or 2nd G0 font (3, 4)
Black Background (1, 2)
New Background (2)
Hold Mosaic (2)
Green
Green
Yellow
Yellow
Blue
Normal Height (1,2)
Double Height
Blue
Magenta
Cyan
Magenta
Cyan
White (1)
White
Release Mosaic (1)
Notes:
To respect the Teletext Norm, the box in serial
mode, starts when two Box-on attributes are en-
countered, and stops when two Box-offs are en-
countered.
(1) Presumed at the start of each display row or
can be defined in global register
(2) Action “set at” (on current character) others are
“set after” (on next character)
Double Height: The upper halves of the charac-
ters are displayed in the current row, the corre-
sponding lower halves of characters are displayed
(with same display attributes) in the next row (in-
formation received for this row must be ignored).
Note: When a serial double height attribute is de-
coded in Row 23, the characters of the first status
row are not displayed. To avoid this effect, remove
the serial double height attribute from Row 23.
(3) ALWAYS active (even in Full Page Serial
Mode, i.e. for Text Level 1)
(4) Toggles action if the Fringe Enable is set (bit 5
in register DCM0R R250 (FAh) Page 32. Selects a
second G0 if the Switch Enable bit is set (bit 5 in
register NCSR R245 (F5h) Page 32)
Flash: (/= Steady) The next characters are dis-
played with the foreground color alternatively
equal to background and foreground on a period
based on Vsync (32 Vsync: foreground, 16 Vsync:
background) until a Steady serial attribute.
Figure 58. Mosaic Characters
Fringe: If the Fringe Enable bit is set in the global
attribute register DCM0R R250 (FAh) Page 32, the
next characters are displayed with a black fringe
(half dot) until the decoding of another fringe at-
tribute coded 1Bh (toggle effect).
Conceal: (/= Reveal) The next characters are dis-
played as space characters (Background color)
until a foreground color character is encountered.
Conceal mode is set by the conceal enable control
bit in the register DCM0R R250 (FAh) Page 32.
Separated Mosaic
Contiguous Mosaic
Note: Hold Mosaic: (/= Release) The last mosaic
character is repeated once instead of the current
space character.
Boxing: A part of the page (where this bit is active)
is inserted in a specific window depending on 3
control bits defined in the FSCCR register. (see
Figure 11)
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 59. Example of Boxing Attribute in Serial Mode
TEXT outside box
not displayed*
TEXT inside box is visible*
Display
b o
>
<
x
Propagation
Default background
Length of row = 40 Characters
Memory location
Nb
SC
BF BF
Bb
BO
BO
A
b
< o x >
A
A
BOX-OFF attribute
BOX-ON attribute
Default foreground
VR02115B
*Depending on FSCCR
Figure 60. Example of Double Height Attribute in Serial Mode
3 contiguous Rows displayed in serial mode
Display
D
A B C
E F
OZ
D
AR
Z
A A
Z A R D O Z A A A
FLASHING
on screen, the 2nd line is overlapped
Memory Location
DH
Bb
NS
Z A R
C
D O Z D
E F
A B
1 2 3
H
N
4 5 6
I D D E
Sc
Sty
Fh
A
A
Z A R D O Z A A A
VR02115C
.
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.3 Parallel Attributes
Figure 61. Example of Row in Parallel Mode
Display
A A A * * Z A R D O Z * A A A
Propagation
Default foreground
Default background
Foreground (full intensity)
Background (half intensity)
global
Attributes Location
Characters Location
A
A R O Z
D * A A A
A
Z
A
* *
VR02115D
Each character is defined on 2 bytes in Parallel
Mode (see Figure 13.)
control bit. The Double Height action is not propa-
gated in the row.
Note: When a parallel double height attribute is
decoded in Row 23, the characters of the first sta-
tus row are not affected and are still displayed.
Parallel Mode is selected by setting the SPM bit in
the DCM1R register R251 (FBh) Page 32.
It requires 2 bytes per character. Display charac-
ters are coded through a second byte processed in
parallel with the character code.
UH: Upper Half. This bit is active when the current-
ly displayed row writes the upper half-character in
case of double height or double size attribute.
It does not handle Teletext and is used mainly for
TV menus (e.g. for channel searching or volume
control).
DW: Double Width (see above).
BX: Boxing window.
The attribute can be one of two types defined by
SR: Smooth Rounding.
most significant bit (PS):
FR, FG, FB: Foreground color.
BR, BG, BB: Background color.
HI: Half Intensity (background only).
CSS: Character extended menu code selection.
PS: Parallel attribute selection
– Color attribute
– Shape attribute
US: Underline / Separate Mosaic graphics (see
above).
DH: Double Height: The half character is displayed
in the current row depending on the Upper Height
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 18. Parallel Color and Shape Attributes.
BIT
0
NAME
BR
FUNCTION
REMARKS
Background Red
Background Green
Background Blue
Half-Intensity
1
BG
2
BB
3
HI
Only for Background.
4
FR
Foreground Red
Foreground Green
Foreground Blue
Parallel Attribute Selection
5
FG
6
FB
7
PS= 0
Color mode of parallel attributes
G2-Menu characters or G1/Extended menu charac-
ters selection
0
CSS
Character set selection
1
2
US
DH
Underline/Seperated mosaic
Double height
Dual function depending on character code
The character is 20 pixels high .
The character is 20 pixels wide. Available in Parallel
mode or in Line mode. Characters are stretched hor-
izontally, to occupy in addition, the next character
space. It is possible to mix it with double height. To
display a double width character the attribute must be
“double width” on the character and “simple width” on
the next which can be a serial attribute. In this case
the first character is memorised. If two “double width”
attributes are on two adjacent characters, the first half
of the second is displayed instead of the second half
of the first one.
3
DW
Double width
4
5
6
7
UH
BX
Upper half character (if 1)
Box mode
Active only if Double Height or Size requested
Boxing window created (if 1)
SR
Smooth rounding
Special rounding effect (See Figure 5)
Shape mode of parallel attributes
PS= 1
Parallel Attribute Selection
Double Size: (available in Parallel mode or in Line mode) by setting Double Width plus Double Height at-
tributes.
Figure 62. Parallel Color and Shape Attributes
DW SS
Attribute
location
4F
31
80
88
31
Character
location
A B
A B
A
A B
B
VR02115E
102/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.4 Font Selection using Parallel Attributes
CSS has two kinds of behaviour:
Parallel attributes have an immediate effect. They
are applied to the associated character. These at-
tributes can also have a “serial” effect, the defined
attribute being still defined on the following charac-
ters: this is known as attribute propagation.
– If PS is set once, the CSS attribute is applied on
the current character only.
– If PS is set twice, the CSS of the first character
with PS=1 is propagated.
Note: The value stored as a preceding CSS value
is forced when alpha or mosaic color serial at-
tributes are used. Alpha serial attributes reset the
memorized CSS: Mosaic serial attributes set the
memorized CSS.
Shape attributes (US,DH,BX,SR) are propagated
when PS is toggled to 0. In the same way, color at-
tributes are propagated when PS is toggled to 1.
Table 19. Font Selection using Parallel Attributes
Parallel
Character
Definition
Character Code
Attribute
00..1F
20..7F
80..FF
00..1F
32 Control Characters (serial attributes function table)
96 Basic Characters chosen from G0 or G1 font
PS= 0
128 extended characters G2-based X/26 and Menu Characters
32 Control Characters (serial attributes function table)
PS= 1
CSS= 0: G0 or G1 selection depending on color serial attribute
CSS= 1: G1 selection
20..7F
80..FF
CSS used for character
set selection
CSS= 0: Select G2-based X/26 + Menu
CSS= 1: Select extended Menu + 32 reserved characters
In the example in Table 6,, a string of six charac-
ters is displayed. In the line “Display with” we can
see that, starting from Char(n) and ending with
Char n+2, the CSS setting made at Char (n-2) is
propagated.
Table 20. Example of Character Set Selection
Char(n-2) Char(n-1) Char(n) Char(n+1) Char(n+2)
Char(n+3)
1
PS=
1
1
0
0
1
CSS=
CSSn-2
CSSn-2
CSSn-2
CSSn-1
CSSn-1
CSSn-2
none
none
CSSn+2
CSSn+2
CSSn-2
CSSn+3
CSSn+3
CSSn+2
Display with
Stored CSS
CSSn-2
CSSn-2
CSSn-2
CSSn-2
103/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 63. Parallel Mode Display Example 1 Showing Character and Attribute Byte Pairs:
RAM content in Parallel Mode
Parallel Attribute
Characters
DS
DH
UH=1 UH=1
DH DH
UH =0 UH=0
DH
A
A
A
A
A
X
I
SA
NF
A
A
A
A
B
B
NF
NF
I
I
A
A
NC DW NC SS SS NC
NC
NC
NC
NC
UH=1
DS
SS DW SS DW SS NC
NF
UH=0
NF : New Foreground (Serial Attribute)
SA : Serial Attribute
SS : Simple Size b7 = 0
NC : New Colour b7 = 0
DW : Double Width b7 = 1 DS : Double Size b7 = 1
Display
A
A
A
A A
A
A
A B
A
VR02112F
Parallel Mode Display Example 2:
Me n u
1
B a
s
s
T r e b l e
104/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.5 Rules When Using Size Attributes
7.4.4.6 Example of using Double Width
Attribute
Secondary effects can be generated when the
shape format is not respected.
In parallel mode, double width on character can be
obtained using the following rule (Figure 16):
The 3 figures below describe the combination of
parallel size attributes to obtain the different char-
acter sizes:
It is important to set Double Width (bit 3 of the
shape attribute) on the current character attribute
and Single Size on the following one. The second
character location can be either a serial attribute or
another character.
· Double Width
· Double Height
· Double Size
On the contrary, if a new color or a Double Width
attribute is set in the second attribute location, the
second part of the character is overlapped.
Figure 64. Double Width Examples
A
B
A
Double width
Double width
first half of the second
character is displayed
Double
width
Double
New color
Simple size
width
Attributes
location
DW NC
DW SS
Characters
location
A B
A
NF
New foreground
(parallel attribute)
New foreground
(serial attribute)
1 ROW
1 ROW
VR02115G
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ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.7 Example of using Double Height
Attribute
acter to magnify in the two rows. Set Bit 2 DH of
the shape attribute in the two locations and set or
reset bit 4 UH to define if it is the top or bottom
half-character.
In parallel mode, Double Height characters can be
obtained as follows. The Double Height attribute
concerns two consecutive rows. Repeat the char-
Figure 65. Double Height Example
Double height
Shape
Propagation with
color
Display
A
B
Previous/default color
Double height
upper half
Double height
lower half
DH
UH=1
DH
UH=0
Attributs
location
New color
Characters
location
B
B
A
A
VR02115H
2 ROWS
106/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.8 Example of using Double Size Attribute
be repeated on the two rows. Bits 2 and 3 of the
shape attribute must be set on the two locations. In
addition bit 4 must be set or reset to define the top
or bottom half-character.
In parallel mode, Double Size characters can be
obtained as follows. This attribute concerns two
consecutive rows. The character to magnify must
Figure 66. Double Size Examples
Display
Double size
A
Double size
lower half
Double size
upper half
Double Height
DS
UH=1
DH
DH
Attribute
location
DS
UH=0
Double Height
A
NF
NF
Character
location
A
2 ROWS
VR02115J
107/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.9 Example of using Underline Attribute
characters, set the US bit on the attribute associat-
ed with the lower part of the character.
In parallel mode, the Underline mode on character
can be obtained simply by setting the bit 1 ‘US’ of
the shape attribute. To underline double height
The underline attribute is ignored in the upper half-
character.
Figure 67. Underline Example
Display
UL
Double height
DH DH
UH=1 UH=1
Attribute
location
DH
UH=0
DH
UH=0
Underline (US=1)
Underline (US=1)
Character
location
U L
L
U
VR02115K
2 ROWS
108/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.10 Attribute Rules
not cover the following characters of the row
(different from double height in serial mode).
The default colors for foreground and background
are defined through the register DCR R240 (F0h)
Page 33.
Figure 68. Rule for Serial and Parallel Color
Combination
A display defined in parallel mode can accept a se-
rial color attribute, and propagation is available un-
til a new color attribute (serial or parallel) is en-
countered.
Highest priority
PARALLEL COLOR
defined in TDSRAM
■ Rule for Shape Attributes:
– In parallel mode, shape attributes are not
propagated on the following characters of the
row except if this character has a colour at-
tribute. The propagation lasts as long as a co-
lour attribute is applied to a character.
SERIAL COLOR
defined in TDSRAM
DEFAULT COLOR
defined in page register
– In parallel mode, the double height (bit 2 of the
shape attribute) is active only on its own char-
acter. Setting one double height attribute does
Lowest priority
109/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.11 Cursor Control
■ Horizontal position (by character)
■ Vertical position (by row)
In Line mode, the scrolling window must be entire-
ly filled by programmed rows (each scrolled loca-
tion is defined by one of the 11 available rows).
Notes:
■ Color or Underline Cursor Modes
1. 80-characters combined with scrolling can only
be used in Line mode
■ Color Cursor with inverted foreground / inverted
background
2. In Parallel (Level 1+) mode, scrolling is possible
without serial attributes DS and DH.
■ Flash or Steady mode Color Cursor
Cursor display is controlled using two registers:
– Cursor Horizontal Position R246 (F6h) Page 32
– Cursor Vertical Position R247 (F7h) Page 32.
Notes:
Use these two registers to control scrolling:
– Scrolling Control Low R248 (F8h) Page 32
– Scrolling Control High R249 (F9h) Page 32
1. Cursor operation in “Underline” mode: any
screen location where the foreground color is
identical to the background color behaves as a
“lost cursor” (i.e. cursor not visible). Assuming a
serial mode display, the screen location placed
on the lower row after a double height character
will lead to a “lost cursor”.
7.4.5.1 RGB & FB DAC and TSLU Outputs
The R, G, B and FB pins of the ST92195/
ST92R195 are analog outputs controlled by true
Digital to Analog Converters. These outputs are
specially designed to directly drive the Video Pro-
cessor.
2. Ghost fringing: assuming a cursor operation in
color inversion mode, assuming a serial mode
display, assuming the fringe is activated, the
screen location placed on the lower row after a
double height character may show a “ghost
fringing” effect (the ghost color being an
inverted background one).
The R, G and B outputs are referred to Ground
and they can drive up to 1.0V; they are loaded on-
chip by a 0.5K ohms typical load.
The effective DAC output level is controlled by a 3
bit digital code issued by the display control logic
with respect to the real time value of R, G or B and
the Half-Intensity control bit, as follows:
3. Static or flash cursor Mode: the horizontal cur-
sor value indicates the character position (i.e.
first character pointed with a “1” value); in
Underline Mode, the horizontal cursor value
gives the position minus “1”.
R/G/B DAC code
Display aspect during FB
No Color
0
0
1
0
1
1
0
1
1
Half-Intensity Color
Full-Intensity Color
7.4.5 Vertical Scrolling Control
■ Top-Down or Bottom-Up shift
■ Freeze Display function
The FB (fast switch) output is also referred to
Ground and can drive up to 3.0V with an on-chip
0.5K ohm load. This analog FB output provides the
best phase matching with the R, G, B signals.
■ Shift speed control
■ Double Height Display scrolling
An example of the Fast Blanking Signal is shown
in Figure 6.
Scrolling is performed in a programmable rolling
window if the characters are in normal height.
The TLSU pin is a digital output (0-5V).
110/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6 Display Memory Mapping Examples
7.4.6.1 Building a Serial Mode Full Page 40-
Char Display
The display content is stored in TDSRAM, (2 to 8K
bytes starting at address 8000h). Use register
TDPR R252 (FCh) Page 32 to address the memo-
ry blocks containing the display data. Two 4-bit ad-
dress pointers (bits PG and HS) must be given that
point to separate blocks containing the display
page and the header/status rows.
Page Location:
The 1 Kbyte block of page content is stored in the
TDSRAM location pointed to by the PG3..PG0
bits.
Header & Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits.
Alternatively, the PG and HS pointers can be writ-
ten to the TDPPR R246 Page 33 and TDHSPR
R247 Page 33 registers.
Row Scrolling Buffer Location:
The scrolling buffer corresponds to the 40 bytes
following the Row 23 when the scrolling feature is
used.
Figure 69. Serial Mode (40 Characters) - Page Mapping
1K TDSRAM
TDPR
Value (hex)
PG3..PG0
Row 1
Block
Number(1K)
TDSRAM
Address (hex)
0
1
2
3
4
5
6
7
8000
8400
8800
8C00
9000
9400
9800
9C00
0
2
2K
4
6K
6
8K
8
Row 23
Scrolling Buffer
Free Space
A
C
E
Resolution 1K bytes
Figure 70. Serial Mode (40 Characters) - Header and Status Mapping
Block Number
TDSRAM
TDPR Value
(0.5K)
Address (hex.) (Hex.) HS3..HS0
0
1
2
3
4
5
6
7
8000
8200
8400
8600
8800
8A00
8C00
8E00
9000
9200
9400
9600
9800
9A00
9C00
9E00
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2K
0.5K TDSRAM
Header
Status Row 0
Status Row 1
6K
Free Space
8K
8
9
10
11
12
13
14
15
Resolution 0.5K bytes
111/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6.2 Building a Parallel Mode, 40-Char, Full
Page Display
Header & Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits. The Header/Status attributes are
stored in this block at offset 80h.
Page Location:
The pair of adjacent 1 Kbyte blocks of page con-
tent is stored in the TDSRAM location pointed to
by the PG3..PG0 bits. The first block contains the
characters, the second block contains the attribute
bytes.
Row Scrolling Buffer Location:
The scrolling buffer corresponds to the 40 bytes
following Row 23 when the scrolling feature is
used.
Figure 71. Parallel Mode (40 Characters) - Page Mapping
1K TDSRAM
Row 1 Char.
1K TDSRAM
Row 1 Attr.
Block
TDSRAM
TDSRAM
TDPR
Number Address (hex) Address (hex) Value (hex)
(2K)
Char.
8000
8800
9000
9800
Attr.
8400
8C00
9400
9C00
PG3..PG0
0
1
2
3
0
4
2K
6K
8K
8
Row 23 Char.
Scrolling Buffer
Free Space
Row 23 Attr.
Scrolling Buffer
Free Space
C
Resolution 2K bytes
Figure 72. Parallel Mode (40 Characters) - Header and Status Mapping
TDPR
Value (hex)
HS3..HS0
Block
Number (0.5K)
TDSRAM
Address (hex)
0.5K TDSRAM
Header Char.
0
1
2
3
4
5
6
7
8
8000
8200
8400
8600
8800
8A00
8C00
8E00
9000
9200
9400
9600
9800
9A00
9C00
9E00
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Status Row 0 Char.
Status Row 1 Char.
Free Space
2K
80h
Header Attr.
6K
Status Row 0 Attr.
Status Row 1 Attr.
Free Space
8K
9
10
11
12
13
14
15
Resolution 0.5K bytes
112/178
ST92185 - ON SCREEN DISPLAY (OSD)
Header & Status Rows Location:
ON SCREEN DISPLAY (Cont’d)
7.4.6.3 Building a Serial Mode, 40-Char, Line
Mode Display
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits. The Row attribute (row count) is
stored in this block at offset 100h and contains 12
bytes for line mode (see DCM1R register descrip-
tion).
Half-Page Location:
The 0.5 Kbyte block of half-page content is stored
in the TDSRAM location pointed to by the
PG3..PG0 bits.
Row Scrolling Buffer Location:
The scrolling buffer corresponds to Row 12 when
the scrolling feature is used (in this case 11 rows
are scrolled).
Figure 73. Serial (40 Characters) Line Mode Mapping
0.5K TDSRAM
0.5K TDSRAM
TDPR
Value
(Hex.)
PG3..PG0
Block
Number
(0.5K)
TDSRAM
Address
(hex.)
Header Char.
Status Row 0
Status Row 1
Free Space
Row Attr.
Row 1
0
1
2
3
4
5
6
7
8
8000
8200
8400
8600
8800
8A00
8C00
8E00
9000
9200
9400
9600
9800
9A00
9C00
9E00
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2K
100h
Row 11
Row 12/ Scrolling Buffer
Free Space
6K
Free Space
8K
Resolution 0.5K bytes
Resolution 0.5K bytes
9
10
11
12
13
14
15
See Figure 22 for
Address Values
113/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6.4 Building a Parallel Mode, 40 Char, Line
mode Display
Header & Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits.
Half-Page Location:
The pair of adjacent 0.5 Kbyte blocks of half page
content is stored in the TDSRAM location pointed
to by the PG3..PG0 bits. One block contains the
characters, the other block contains the attribute
bytes.
The Header/Status attributes are stored in this
block at offset 80h.
The Row attribute (row count) is stored in this
block at offset 100h and contains 12 bytes for line
mode (see DCM1R register description).
Row Scrolling Buffer Location:
The scrolling buffer corresponds to the Row 12
when the scrolling feature is used (in this case 11
rows are scrolled).
Figure 74. Parallel (40 Characters) Line Mode Mapping
0.5K TDSRAM
Row 1 Char.
0.5K TDSRAM
Row 1 Attr.
0.5K TDSRAM
Header Char.
Status Row 0
Status Row 1
Free Space
Header Attr.
Status Row 0
Status Row 1
Free Space
Row Attr.
80h
Row 11 Char.
Row 12/Scrolling Buffer
Free Space
Row 11 Attr.
Row 12/Scrolling Buffer
Free Space
100h
Free Space
Resolution 1K bytes
Resolution 0.5K bytes
See Figure 21 for Address Values
See Figure 22 for Address Values
114/178
ST92185 - ON SCREEN DISPLAY (OSD)
Header & Status Rows Location:
ON SCREEN DISPLAY (Cont’d)
7.4.6.5 Building a Serial Mode, 80 Char, Full
Page Display
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits.
Half-Page Location:
The pair of adjacent 1 Kbyte blocks of page con-
tent is stored in the TDSRAM location pointed to
by the PG3..PG0 bits. The first block contains the
left side of the page, the second block contains the
right side of the page.
Row Scrolling Buffer Location:
The scrolling buffer corresponds to the 40 bytes
following the Row 23 when the scrolling feature is
used.
Figure 75. Serial Mode (80 Characters) - Page Mapping
1K TDSRAM
Row 1 Left
1K TDSRAM
Row 1 Right
0.5K TDSRAM
Header
Status Row 0
Status Row 1
Free Space
Row 23
Row 23
Scrolling Buffer
Scrolling Buffer
Free Space
Free Space
Resolution 2K bytes
Resolution 0.5K bytes
See Figure 23 for Address Values
See Figure 22 for Address Values
115/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6.6 Building a Serial Mode, 80 Char, Line
Mode Display
Header/Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits.
Half-Page Location:
The pair of 0.5 Kbyte blocks of half page content is
stored in the TDSRAM location pointed to by the
PG3..PG0 bits. The first block contains the left half
rows, the other block contains the right half rows.
The Row attribute (row count) is stored in this
block at offset 100h and contains 12 bytes for line
mode (see DCM1R register description).
Row Scrolling Buffer Location:
The scrolling buffer corresponds to Row 12 when
the scrolling feature is used (in this case 11 rows
are scrolled).
Figure 76. Serial (80 Characters) Line Mode Mapping
0.5K TDSRAM
Row 1 Left
0.5K TDSRAM
Row 1 Right
TDSRAM
TDSRAM
TDPR
Block
Number(1K)
Address Left Address Right Value (hex)
(hex)
8000
8400
8800
8C00
9000
9400
9800
9C00
(hex)
8200
8600
8A00
8E00
9200
9600
9A00
9E00
PG3..PG0
0
1
2
3
4
5
6
7
0
2
2K
4
6K
6
8K
8
Row 11
Row 11
A
C
E
Row 12/Scroll Buffer Row 12/Scroll Buffer
Free Space
Free Space
Resolution 1K bytes
Figure 77. Serial (80 Characters) Line Mode - Header and Status Mapping
0.5K TDSRAM
Header
Status Row 0
Status Row 1
See Figure 22 for Address Values
Free Space
Row Attr.
100h
Free Space
Resolution 0.5K bytes
116/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.7 Font Mapping
– In Serial Mode (Level 1), only 256 Character
Codes are available using an 8-bit code. The
character codes plus some serial attributes and
some additional programmable options address
566 chars: 256 + 182 NS chars + 128 mosaics in
single G0 mode.
G0 is the basic character font.
G1 is the mosaic font. It is not stored in ROM but is
implemented in hardware. In serial mode it is ad-
dressed by a serial attribute (See Figure 3). In par-
allel mode it is accessed by bit 0 (CSS) of the par-
allel shape attribute and bit 1 (US) for separated
mosaic (See Figure 4).
– In Parallel Mode (Enhanced Level 1), 512 Char-
acter Codes are available using a 9-bit code. The
character codes plus some serial and parallel at-
tributes, and some additional programmable op-
tions address 662 chars: 256 + 182 NS chars +
128 mosaic + 96 extended chars. in single G0
mode.
G2 is a font of X/26 based + Menu shared charac-
ters.
An Extended Menu character font available in par-
allel mode. It is accessed via bit 0 (CSS) in the par-
allel shape attribute (Character Set Selection).
The Extended Menu font is not accessible in serial
mode.
Display ROM Font Entry:
The user must define his own fonts for:
– 278 characters: - 15 x 13 G0 National Character
subsets + 83 G0 Character set
7.4.8 Font Mapping Modes
There are two font mapping modes selected
or
by the NCM bit in the NCSR register R245 (F5h)
Page 32:
– 288 characters: 3 x 96-character character sets
– 128 G2 based X/26 and Menu characters
– 96 Extended Menu characters
Single G0 mode
A set combining 83 characters from
the G0 basic set plus 13 characters
selected from 15 National character
subsets. The National character sub-
sets are selected by four bits (NC3:0)
in the NCSR register R245 (F5h)
Page 32.
Table 21. Triple G0 Mode - Font Mapping
ROM
Address
Character
Code
CSS
Font Usage
000h to 01Fh 0E0h to 0FFh
020h to 07Fh 020h to 07Fh
080h to 0FFh 080h to 0FFh
100h to 15Fh 020h to 07Fh
160h to 1BFh 020h to 07Fh
1C0h to 1FFh 0A0h to 0DFh
1
Extended menu
G0 set 0
Triple G0 mode
0
G2 + Menu
G0 set 1
(or serial
mode)
Three 96-character character sets
(G0-0, G0-1 and G0-2) for multi al-
phabet applications. Character set
selection is done by four bits (NC1:0
or NC3:2) in the NCSR register R245
(F5h) Page 32.
G0 set 2
1
Extended menu
117/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 22. National Character Subset Mapping
(Ordered by their G0 address)
1st
23h
8th
2nd
24h
9th
3rd
40h
10th
7Bh
4th
5Bh
11th
7Ch
5th
5Ch
12th
7Dh
6th
5Dh
13th
7Eh
7th
5Eh
5Fh
60h
Figure 78. Font Mapping
Addresses
0
1F
7F 80
FF
G2 BASED
+ MENU
G0 + OPTIONAL NATIONAL SET
(96 CODES)
SERIAL
ATTRIBUTES
(32 CODES)
SERIAL MODE
(128 CODES)
G1* (32)
G1* (32)
Char. Codes
80
7F
FF
FF
0
1F
3F
5F
*If Serial Attributes 19, 1A are used
Addresses
0
1F
7F 80
G2 BASED
+ MENU
SERIAL
G0 + OPTIONAL NATIONAL SET
(96 CODES)
PARALLEL MODE ATTRIBUTES
(PS=x, CSS=0)
(128 CODES)
(32 CODES)
Char. Codes
80
7F
FF
0
1F
Addresses
100
11F
17F 180
19F
1FF
EXTENDED
SERIAL
PARALLEL MODE ATTRIBUTES
RESERVED
(32)
G1 (32)
G0 (32)
G1 (32)
MENU CHARACTERS
(96 CODES)
(PS=1, CSS=1)
(32 CODES)
Char. Codes
0
1F
3F
5F
7F 80
9F
FF
118/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 23. Single G0 Mode - Font Mapping
ROM Address
000h to 01Fh
020h to 07Fh
080h to 0FFh
100h to 10Ch
10Dh to 119h
11Ah to 126h
127h to 133h
134h to 140h
141h to 14Dh
14Eh to 15Ah
15Bh to 167h
168h to 174h
175h to 181h
182h to 18Eh
18Fh to 19Bh
19Ch to 1A8h
1A9h to 1B5h
1C0h to 1FFh
Character Code
0E0h to 0FFh
CSS
1
Font Usage
Extended menu
NC(3:0)
020h to 07Fh
G0 + National Character Subset 0 (96 chars)
G2 + Menu (128 chars)
0000b
080h to 0FFh
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
0A0h to 0DFh
National Character Subset 1 (13 chars)
National Character Subset 2 (13 chars)
National Character Subset 3 (13 chars)
National Character Subset 4 (13 chars)
National Character Subset 5 (13 chars)
National Character Subset 6 (13 chars)
National Character Subset 7 (13 chars)
National Character Subset 8 (13 chars)
National Character Subset 9 (13 chars)
National Character Subset 10 (13 chars)
National Character Subset 11 (13 chars)
National Character Subset 12 (13 chars)
National Character Subset 13 (13 chars)(Free for user)
National Character Subset 14 (13 chars) (Menu chars.)
Extended menu
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
0
1
Table 24. National Character Subsets
Subset Name
Subset No.
(Decimal)
Character Code (Hex)
23 24 40 5B 5C 5D 5E 5F 60 7B 7C 7D 7E
Czech/Slovak
English
3
0
Estonian
French
9
1
German
Italian
4
6
Lettish/
10
8
Lithuanian
Polish
Portugese/
Spanish
5
Rumanian
7
Serbian/
Croatian/
Slovenian
12
2
Swedish/
Finnish
Turkish
11
119/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 79. Pan-European Font (East/West) Character Codes (Hex.)
National Character Subset 0
Extended
Menu
G0_0
G2-Menu
National
Char.
Subsets
1..14d
Extended
Menu
Figure 80. OSD Picture in Parallel Mode
120/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY(Cont’d)
7.4.9 Register Description
VERTICAL POSITION REGISTER (VPOSR)
R242 - Read/Write
HORIZONTAL BLANK REGISTER (HBLANKR)
R240 - Read/Write
Register Page: 32
Reset Value: 0000 0011 (03h)
Register Page: 32
Reset Value: 0000 0000 (00h)
7
0
0
0
VP5
VP4
VP3
VP2
VP1
VP0
7
0
HB7
HB6
HB5
HB4
HB3
HB2
HB1
HB0
Bit 7:6 = Reserved, keep in reset state.
It controls the length of the Horizontal Blank which
follows the horizontal sync pulse.
Bit 5:0 = VP[5:0]: The vertical start position is cal-
culated with a line downcounter decremented on
each Hsync by VP[5:0]. The Display of the first row
begins when the counter turns to zero.
Bit 7:0 = HB[7:0]: The horizontal blank period is
calculated with a pixel down counter loaded on
each Hsync by HB[7:0]. During this period, FB = 0
and (R, G, B) = black.
Vert delay = (VP5*32 + VP4*16 + VP3*8 + VP2*4
+ VP1*2 + VP0) * Tline (Tline= 64 µs)
Thblank = [(HB7*128 + HB6*64 + HB5*32 +
HB4*16 + HB3*8 + HB2*4 + HB1*2 + HB0) * Tpix]
HORIZONTAL POSITION REGISTER (HPOSR)
R241 - Read/Write
Register Page: 32
Reset Value: 0000 0011 (03h)
7
0
HP7
HP6
HP5
HP4
HP3
HP2
HP1
HP0
Bit 7:0 = HP[7:0]: The horizontal start position is
calculated with a pixel down-counter loaded on
each Hsync by HP[7:0]. The first character display
starts when the counter turns to zero.
Hori delay= [(HP7*128 + HP6*64 + HP5*32 +
HP4*16 + HP3*8 + HP2*4 + HP1*2 + HP0) * Tpix]
+ Thblank
121/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
FULL SCREEN COLOR CONTROL REGISTER
(FSCCR)
Bit 4 = HTC: Half-Tone/Translucency Control Bit
This bit allows the selection of TSLU or HT as al-
ternate function output.
0: TSLU is selected as I/O pin alternate function
1: HT is selected as I/O pin alternate function
R243 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
7
0
Bit 3:0 = FSC[3:0]: Full Screen Color control bits:
FSC[3:0]= (Half-intensity, R, G, B)
BE
TIO
MM
HTC FSC3 FSC2 FSC1 FSC0
Table of Color Values (hex)
Bit 7 = BE: Box Enable, see Table 11.
Bit 6 = TIO: Text out/not in, see Table 11.
Bit 5 = MM: Mixed Mode, see Table 11.
0 Black
1 Blue
8 Black
9 Dark blue
A Dark green
B Dark cyan
C Dark red
D Dark magenta
E Dark yellow
F Grey
2 Green
3 Cyan
4 Red
Note: When Flash and Box attributes are decoded
at the same time on the characters of a header
(when BE=1, MM=1, TIO=1) the full screen over
the characters is displayed as transparant.
5 Magenta
6 Yellow
7 White
Table 25. Box Mode/Translucency Configurations
BE TIO MM
If Translucency is not used
Solid Background for all the display
If Translucency is used
Translucent Background for all the display
Transparent Background for all the display
0
0
x
x
0
1
Transparent Background for all the display
Text inside box translucent, Text outside box
blanked
1
1
0
0
0
1
Text inside box solid, Text outside box blanked
Text inside box with solid background Text out- Text inside box with translucent background Text
side box with transparent background
outside box with transparent background
Text inside box not displayed, transparent back-
ground. Text outside box with translucent back-
ground
Text inside box not displayed, transparent back-
ground. Text outside box with solid background
1
1
1
1
0
1
Text inside box with transparent background.
Text outside box with solid background
Text inside box with transparent background. Text
outside box with translucent background
122/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
HEADER & STATUS CONTROL REGISTER
(HSCR)
Bit 4,2 = NS[1:0]: Serial/Parallel Mode Status
Rows display control bits. If the corresponding bit
is reset, the Status Row uses only serial attributes.
If the corresponding bit is set, the Status Row uses
parallel attributes (except size attributes).
R244 - Read/Write
Register Page: 32
Reset Value: 0010 1010 (2Ah)
7
0
Bit 1 = EH: Enable Header display control bit. If
set, the Header row is displayed; if reset, the
Header row is filled with the full screen color.
0
0
ES1
NS1
ES0
NS0
EH
NH
Bit 7:6 = Reserved.
Bit 0 = NH: Serial/Parallel Mode Header display
control bit. If the bit is reset, the Header uses only
serial attributes. If the bit is set, the Header uses of
parallel attributes.
Bit 5,3 = ES[1:0]: Enable Status Rows [1:0] dis-
play control bits. If the bit is reset, the correspond-
ing Status Row is filled with the full screen color; if
the bit is set, the corresponding Status Row is dis-
played (Status Row 1 is assumed to be the bottom
one).
123/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
NATIONAL CHARACTER SET REGISTER
(NCSR)
– either a single G0 alphabet with up to 15 national
sub-sets,
R245 - Read/Write
– or 3 different G0 alphabets.
Register Page: 32
Reset Value: 0000 0000 (00h)
If NCM is reset, a single G0 alphabet configuration
is activated and the 15 national sub-sets are se-
lected through the NC[3:0] bits.
7
0
If NCM is set, a triple G0 alphabet configuration is
activated, the selection of the G0 set used for the
display is done through either NC[3:2] or NC[1:0]
bits, depending upon the SWE control bit and the
serial attribute 1Bh values.
TSLE
0
SWE NCM NC3
NC2
NC1
NC0
The register bit values are sampled and then acti-
vated only at each field start (on Vsync pulse).
Bit 7 = TSLE: Translucency/Half-Tone Output En-
able bit.
0: Translucency/Half-Tone signal disabled
1: Translucency/Half-Tone is enabled. Translu-
cency or Half-Tone realtime control signal is
routed in the TSLU/HT pin (depending on the
HTC bit in the FSCCR register).
Bit 3:0 = NC[3:0]: National Character Set Selec-
tion.
If the NCM bit is reset, these bits define which na-
tional sub-set has to be used to complete the basic
currently used G0 alphabet set.
If the NCM is set, these bits define which G0 is
used.
Note: Translucent display depends also on the
BE, TIO and MM bits, see Table 11.
Figure 81. National Characters Selection
0
1
NCM
Bit 6 = Reserved.
Bit 5 = SWE: G0 Switch Enable Control Bit.
In case of a multiple G0 alphabet configuration
(NCM=1), this bit allows to switch from a first to a
second predefined G0 alphabet, using a single se-
rial attribute (1Bh). In case of a single G0 alphabet
configuration (NCM=0), the SWE bit will have no
effect.
1
0
NC[3:0]
SWE
NS0
NS1
SERIAL ATTR. 1Bh
TOGGLE
NC[1:0]
If SWE is reset, the used G0 alphabet is pointed
through NC[1:0].
G0-0
G0-1
G0-2
NC[1:0]
NC[3:2]
If SWE is set, the used G0 alphabet is pointed
through NC[3:2] and NC[1:0] toggled by 1Bh serial
attribute.
NS14
G0-0
G0-0
G0-1
G0-2
G0-1
G0-2
15 NATIONAL 3 G0 SETS
CHAR. SETS
Bit 4 = NCM: National Character Mode control bit.
This bit reconfigures a part of the font set as defin-
ing:
124/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
CURSOR HORIZONTAL POSITION REGISTER
(CHPOSR)
TV fields followed by a "1" state during the 16 next
TV fields. This flag provides a 1Hz time reference
for an easy software control of all flashing effects
(assuming a 50 Hz TV signal, the FON total period
will be 0.96 seconds).
R246 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
This bit is READ ONLY. Trying to write any value
will have no effect.
7
0
0
CHP6 CHP5 CHP4 CHP3 CHP2 CHP1 CHP0
Bit 6:5 = CM[1:0]: Cursor Mode control bits.
Bit 7 = Reserved.
CM1 CM0
Cursor Mode
Cursor Disable
0
0
Static Cursor (inverted foreground & invert-
ed background colours)
Bit 6:0 = CHP[6:0]: Cursor Horizontal Position.
0
1
The cursor is positioned by character.
Flash Cursor (flash from current to inverted
colours & vice versa)
1
1
0
1
CHP= 0 points to the first character
CHP= 39d points to the end of the row (single
page display)
CHP= 79d points to the last character in the row
(double page display)
Cursor done with Underline (use of current
foreground color)
Bit 4:0 = CVP[4:0]: Cursor Vertical Position.
The cursor is positioned by row. The cursor is al-
ways single size.
CURSOR VERTICAL POSITION REGISTER
(CVPOSR)
R247 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
CVP= 0 locates the cursor on the Header row
CVP= 25d locates the cursor on the last Status
row.
7
0
FON CM1 CM0 CVP4 CVP3 CVP2 CVP1 CVP0
Bit 7 = FON: "Flash On" flag bit.
The FON bit remains at "0" during 32 consecutive
125/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
SCROLLING CONTROL LOW REGISTER
(SCLR)
Bit 6 = FSC: Freeze scrolling
Note: The 2 control bits SCE and FSC must be set
to "1" before enabling the Global double height
(see the DH bit in the SCHR register).
R248 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
Bit 5 = SS: Scrolling Speed Control bit.
0: The display is shifted by 2 TV lines at each TV
frame (i.e. after 2 Vertical sync pulses).
1: The display is shifted by 4 TV lines at each TV
frame.
7
0
SCE
FSC
SS
FRS4 FRS3 FRS2 FRS1 FRS0
Bit 7 = SCE: Scrolling Enable
Before enabling scrolling, the scrolling area must
be defined by the FRS[4:0] and LRS[4:0] bits. The
scrolling direction is defined by the UP/D bit.
0: Disable scrolling
Bit 4:0 = FRS[4:0]: These bits define the upper-
most Row value to be scrolled (rows are num-
bered from 1 to 23). In case of global double height
mode programming, FRS[4:0] must mandatorily
be equal to 00000.
1: Enable scrolling
Table 26. Scrolling Control Bits
DH
SCE
FSC
UP/D FRS[4:0] LRS[4:0]
Meaning
0
0
x
x
1
0
1
0
x
x
x
0
0
x
x
x
x
x
No Global Double Height, No Scrolling
No Global Double Height, Scroll up
0
1
1
0
x
x
No Global Double Height, Scroll down
Global Double Height, No Scrolling, Display top half
Global Double Height, No Scrolling, Display bottom half
126/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
SCROLLING CONTROL HIGH REGISTER
(SCHR)
Bit 6 = EER: End of Extra Row flag bit.
This bit is forced to "1" by hardware when the last
line of the extra row is displayed in case of scroll-
ing in normal height. This bit is Read only.
R249 - Read/Write
Register Page: 32
Reset Value: 0000 0000b (00h)
In Global double height, the EER bit is set to "1"
each time the last line of a new displayed row ap-
pears.
7
0
DH
EER UP/D LRS4 LRS3 LRS2 LRS1 LRS0
Bit 5 = UP/D: Scrolling Up/Down
This bit has two functions: to control the scrolling
direction and to select the half part of the page in
Global Double Height display.
Scrolling direction:
Bit 7 = DH: Global Double Height control bit.
This bit must only be used in Page Mode. When
DH is set, the display is turned in double height in-
cluding the header, excluding the vertical offset
before the display area. The status rows are not
affected by the DH bit and they remain in normal
height. Depending on the value of the UP/D con-
trol bit, when DH is set, the first or second half of
the page is displayed in double height. This bit as-
sumes a zooming function.
0: Top-Down shift
1: Bottom-up shift
Half-page selection:
When DH is set, if UP/D is set, the upper half of the
page is displayed (i.e. Header and the page rows 1
to 11).
When DH is set, if UP/D is reset, the lower half of
the page is displayed (i.e. rows 12 to 23 and the
Status rows).
Notes:
– In global double height, when the top half page
is displayed, if row 11 has a double height at-
tribute, the first status row is corrupted. To avoid
this effect, save row 11, remove the serial double
height attribute from this row and display the up-
per part of the page. Then, before displaying the
lower part of the page, restore the serial DH at-
tribute in row 11.
The UP/D control bit must be defined before set-
ting the Global height (DH bit); changing UP/D af-
ter DH is set, will not change the already selected
half page.
Bit 4:0 = LRS[4:0]: Last row to be scrolled (1 to
23). In case of scrolling in global double height, the
Last row must be equal to 0x 10111 to display the
status row in the two half pages.
– When the bottom half page is displayed, if row 23
has a double height attribute, the first status row
is not displayed. To avoid this effect remove the
serial double height attribute from row 23.
127/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 82. Memory Management for Scrolling Window
Freeze off
after 5 Vsync
Freeze on
after 5 Vsync
New TDSRAM address
after EER=1
Normal Height
ROW A
ROW B
ROW C
ROW A
ROW B
ROW A
ROW B
ROW C
T0
3 rows to be
scrolled
ROW A
ROW B
ROW C
TDSRAM
ROW C
CONTENT
DISPLAY
AREA
EER=0
EER=0
ROW D
Row 24
ROW A
ROW A
ROW A
ROW B
ROW B
ROW B
T + 5 VSYNC
ROW C
ROW D
ROW C
ROW D
ROW C
ROW D
NEW
TDSRAM
CONTENT
ROW B
ROW C
ROW D
ROW E
Row 24
ROW A
ROW B
ROW C
ROW D
ROW B
ROW C
ROW D
ROW B
T + 10 VSYNC
ROW C
ROW D
EER=1
EER=0
ROW A
ROW A
ROW B
ROW B
ROW B
ROW C
T + 15 VSYNC
ROW C
ROW D
ROW C
ROW D
ROW D
ROW E
A = First row to scroll
C= Last row to scroll
E= Extra row
128/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
DISPLAY CONTROL MODE
(DCM0R)
0
REGISTER
1: Conceal any text defined as concealed by serial
attributes
R250 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
Bit 3 = GFR: Global Fringe Enable control bit.
If this bit is set, the whole display is in fringe mode
(except if a Double page display mode is pro-
grammed).
7
0
DE
STE
FRE
CE
GFR GRE
SF
S/D
Bit 2 = GRE: Global Rounding Enable control bit.
If this bit is set, the whole display is in rounding
mode (except if a Double page display mode is
programmed).
Bit 7 = DE: Display Enable control bit.
If DE is reset, no display will be performed. If DE is
set, a display will be done as defined through the
various control bits.
Bit 1 = SF: Screen Format control bit.
0: Configures the Display for 4/3 TV screen format.
1: A fixed offset of 128 Pixel clock periods is added
before any character is displayed; the Full
Screen Color attribute is used while the offset is
running.
Bit 6 = STE: Semi-Transparent Enable bit.
This bit is active only in Single page display mode.
While the Display is disabled, the horizontal and
vertical sequencers are forced in their reset state
and the RGB & FB DACs are not off (still present-
ing on-chip resistors to Ground).
The SF bit intended for displaying on 16/9 TV
screen format tubes, the display picture will be re-
centered.
Note: This mode shows a visible grid on the
screen.
Bit 0 = S/D: Single or Double page control bit.
0: A single page is displayed on screen (i.e. 40-
character width).
1: A set of two pages is displayed contiguously
(i.e. 80-character width).
Bit 5 = FRE: Fringe Enable control bit.
If this bit is set, and the SWE bit is reset (refer to
the National Character Set Register description)
the serial attribute 1Bh has a fringe toggle func-
tion.
Note: In 80 characters per row and in full page
mode, line 25 of each field is displayed as a
transparant line (as this line is not in the visible
part of the screen, this should not present a limita-
tion).
FRE
SWE
1Bh Serial attribute acts as:
No Action
0
0
1
1
0
1
0
1
G0 Toggle
Fringe Toggle
G0 Toggle
Programming a Double page display will automat-
ically mask the Fringe, Rounding and Parallel
Mode control bits. Their register values are not
changed and they will automatically recover their
initial effect if the display is switched back in a Sin-
gle page mode.
Bit 4 = CE: Conceal Enable control bit.
0: Reveal any text defined as concealed by serial
attributes (Default)
129/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
DISPLAY CONTROL MODE
(DCM1R)
1
REGISTER
mode, i.e. a character or attribute is coded with a
single byte. If the SPM bit is set, the display is
done in Parallel mode, i.e. a character or an at-
tribute is coded on two bytes.
R251 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
TDSRAM POINTER REGISTER (TDPR)
R252 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
EXTF FBL
PM
SPM
7
0
Bit 7:4 = Reserved bits, keep in reset state.
HS3
HS2
HS1
HS0
PG3
PG2
PG1
PG0
Bit 3 = EXTF: External Font.
Bit 7:4 = HS[3:0]: Location of the current Header
Only when the emulator is used, this bit selects the
font memory containing a user-defined OSD font.
In normal user application, this bit has no effect.
0: Internal font memory of the emulator chip.
1: External font RAM of the emulator board.
and Status Rows in the TDSRAM.
Bit 3:0 = PG[3:0]: Location of the current Page
content (rows 1 to 23) in the TDSRAM. For more
details, refer to Section .
Bit 2 = FBL: Fast Blanking Active Level control bit.
The FBL bit must be reset if the on-screen display
is done while the FB output is low. The FBL bit
must be set if the on-screen display is done while
the FB output is high. This bit also controls the
TSLU AF output polarity with the same rule as for
FB.
The HS[3:0] and PG[3:0] bits described by the
R246 and R247 registers in page 32. Display loca-
tions, Head/Stat location, Page location, are phys-
ically the same: these sets of address bits can be
modified through two different programming ac-
cesses.
Bit 1 = PM: Line Mode control bit.
If PM is reset, the display is working in Full page
mode, i.e. the screen is composed of one header,
23 text rows plus 2 status rows. If PM is set, the
display works in Line mode.
Line mode allows up to 12 rows to be displayed
anywhere on the screen. The row attribute (see
TDSRAM mapping) contains the row numbers on
the screen. The byte position of the row attribute
conrresponds to the row in the TDSRAM. For ex-
ample, if the 3rd byte of the row attribute contains
6, the 3rd row in TDSRAM will be displayed as the
6th row on the screen.
Bit 0 = SPM: Serial/Parallel Mode control bit.
If the SPM bit is reset, the display is done in Serial
130/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
DISPLAY ENABLE 0 CONTROL REGISTER
(DE0R)
DISPLAY ENABLE 2 CONTROL REGISTER
(DE2R)
R253 -Read/Write
R255 -Read/Write
Register Page: 32
Reset Value: 1111 1111 (FFh)
Register Page: 32
Reset Value: x111 1111 (xFh)
7
0
7
0
R8
R7
R6
R5
R4
R3
R2
R1
x
R23
R22
R21
R20
R19
R18
R17
Bit 7:0 = R[8:1]: Row display enable control bit.
When the “Ri” bit is set (Reset value), the corre-
sponding row (with row in the page, numbered
from 1 to 23) will be displayed. When the “Ri” bit is
reset, the full screen color is displayed.
Bit 7 = Reserved
.
Bit 6:0 = R[23:17]: Row display enable control bit.
When the “Ri” bit is set (Reset value), the corre-
sponding row (with row in the page, numbered
from 1 to 23) will be displayed. When the “Ri” bit is
reset, the full screen color is displayed.
DISPLAY ENABLE 1 CONTROL REGISTER
(DE1R)
R254 -Read/Write
Register Page: 32
Reset Value: 1111 1111 (FFh)
7
0
R16
R15
R14
R13
R12
R11
R10
R9
Bit 7:0 = R[16:9]: Row display enable control bit.
When the “Ri” bit is set (Reset value), the corre-
sponding row (with row in the page, numbered
from 1 to 23) will be displayed. When the “Ri” bit is
reset, the full screen color is displayed.
131/178
ST92185 - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
DEFAULT COLOR REGISTER (DCR)
R240 - Read/Write
TDSRAM PAGE POINTER REGISTER (TDPPR)
R246 - Read/Write
Register Page: 33
Register Page: 33
Reset Value: 0111 0000 (70h)
Reset Value: xxx0 0000 (x0h)
7
0
7
0
DFG3 DFG2 DFG1 DFG0 DBG3 DBG2 DBG1 DBG0
x
x
x
0
PG3
PG2
PG1
PG0
Bit 7:4 = DFG[3:0]: Default Foreground Color.
DFG[3:0] = (Half-Intensity, R, G, B)
Bit 7:4 = Reserved, keep in reset state.
Bit 3:0 = PG[3:0]: Page Pointer
Bit 3:0 = DBG[3:0]: Default Background Color
Location of the current Page content (rows 1 to 23)
in the TDSRAM. For more details, refer to the Dis-
play Memory Mapping Section .
DBG[3:0] = (Half-Intensity, R, G, B)
Table of Color Values (hex)
0 Black
1 Blue
8 Black
TDSRAM HEADER/STATUS POINTER REGIS-
TER (TDHSPR)
9 Dark blue
A Dark green
B Dark cyan
C Dark red
D Dark magenta
E Dark yellow
F Grey
2 Green
3 Cyan
4 Red
R247 - Read/Write
Register Page: 33
Reset Value: xxx0 0000 (x0h)
5 Magenta
6 Yellow
7 White
7
0
x
x
x
0
HS3
HS2
HS1
HS0
Bit 7:4 = Reserved, keep in reset state.
CURSOR ABSOLUTE VERTICAL POSITION
REGISTER (CAPVR)
R241 - Read/Write
Bit 3:0 = HS[3:0]: Header/Status Rows Pointer
Location of the current Header and Status Rows in
the TDSRAM. For more details, refer to the Dis-
play Memory Mapping paragraph Section .
Register Page: 33
Reset Value: 0000 0000 (00h)
7
0
0
0
0
ACP4 ACP3 ACP2 ACP1 ACP0
Bit 7:5 = Reserved, keep in reset state.
Bit 4:0 = ACP[4:0]: Absolute Vertical Position of
the cursor in case of double height or scrolling.
132/178
ST92185 - ON SCREEN DISPLAY (OSD)
7.4.10 Application Software Examples
Before starting an OSD Display, it is very important to start all the internal clock/timings
To understand the software routines given below, make a thorough study of the chapters on the Reset
and Clock Control Unit (RCCU) and the TDSRAM Interface.
Initialization of the Internal Clock
;=========================================================================
;
MAIN CLOCK INIT
;=========================================================================
CLOCKS::
;--------- CPU MAIN CLOCK ------------
; C K M A I N provided by the freq. multplier
spp #TCCR_PG; Timings & clock Controller registers page
; page 39 or 27
ld MCCR,#0x05; program the frequency multiplier down
; counter in the feed-back loop (253 =FD)
; freq=(5+1)*2 =12Mhz
; freq=(7+1)*2 =16Mhz
; freq=(8+1)*2 =18Mhz
ld MCCR,#0x85; enable the freq. multiplier
srp #BK20
ldw rr0,#0x2FFF;
time_stab1:
; for frequency multiplier stabilization
decw rr0; change CPU source clock & wait clock stabilization
cpw rr0,#0x00;
jxnz time_stab1;
ld MCCR,#0xC5 ; select the freq. multiplier as main clock
pop ppr
;=========================================================================
SYNCHRO START
;=========================================================================
spp #SYCR_PG ; set page pointer to page 23h or 35 decimal
;
ld CSYCTR,#000h; R243, Hsync and Vsync from deflection part
(external)
ld CSYSUR,#0C4h; R242 Sync Controller Set-up register
; Standard mode, Positive polarity of Hsync & Vsync
; delay on Hsync/Vsync HSF(3:0)=9
;=========================================================================
DISPLAY PIXEL CLOCK
;
;=========================================================================
;
spp #TCCR_PG; Timings & clock Controller registers page
; set page pointer to page 39 decimal
ld SKCCR, #0x09; FE, Skew clock control register
; program the frequency multiplier down
; counter in the feed-back loop
133/178
ST92185 - ON SCREEN DISPLAY (OSD)
; dot_freq= 4Mhz(4+1)=20Mhz (4/3)
; dot_freq= 4Mhz(5+1)=24Mhz (16/9)
; divide by 2
ld SKCCR, #0x89; enable the freq. multiplier
srp #BK20
ldw rr0,#0x0FFF;
time_stab2:
; for frequency multiplier stabilization
decw rr0; SKEW clock stabilization
cpw rr0,#0x00 ;
jxnz time_stab2;
ld PXCCR,#0x80;(PXCCR) start Pixel Line PLL
spp #TDSR_PG2; page 26h, TDSRAM Controller registers third page
srp #000h
ld CONFIG, #003h; FC, ram Interface Configuration register
; enable display and Dram access
;=======================================================================
Initialization of the OSD in Serial Mode
;=======================================================================
;
INIT DISPLAY ROUTINE
;=======================================================================
INIT::
;-----------Display Position & Black Reference
spp #DMP1_PG; page 020h Display memory map registers page
ld HBLANKR,#0x45; HBLANKR register [7: 0]; reset=03
; important delay for black reference on RGB cathod
ld HPOSR,#0x35; HPOSR register [7:0]; reset=03
ld VPOSR,#0x10; VPOSR register [5:0]; reset=00
;-----------------
spp #DMP1_PG; page 020h Display memory map registers page
; F3, Full Screen Color register
ld FSCCR, #0x01 ; no subtitle mode
; BE, Box enable
; TIO, Text in/out
; MM, Mixed Mode
; FSC[3:0]=half blue full screen
ld HSCR, #03Fh; bit5,
; ES1 , NS1, ES0, NS0, EH, NH
; 0x3F > set header and status in level 1+
(parallel)
4,
3,
2, 1,
0
;
; 0x2a > set header and status in level 1
; F5, National Characters register
ld NC, #010h; SWE, NCM, NC[3:0]
;------- Scrolling INIT ----------
spp #DMP1_PG; page 020h Display memory map registers page
134/178
ST92185 - ON SCREEN DISPLAY (OSD)
; F8, Scrolling Control Line register
ld SCLR ,#000h ; SCE, FSC, SS, FIRSTROWSCRO[4:0]
; F9, Scrolling Control Horizontal register
ld SCHR ,#02fh ; DH, ER, UP/D, LASTROWSCRO[4:0]
;------- Cursor position
; F8, Scrolling Control Line register
ld SCLR ,#000h ; SCE, FSC, SS, FIRSTROWSCRO[4:0]
; F9, Scrolling Control Horizontal register
ld SCHR ,#02fh ; DH, ER, UP/D, LASTROWSCRO[4:0]
; F6, Cursor Horizontal Position register
ld CHPOSR , #005h; CURSOR HPOS [6:0]
; F7, Cursor Vertical Position register
ld CVPOSR , #000h; FON, CM[1:0], CURSOR VPOS[4:0]
;------- Control
; FA, Control Mode 0 register
ld DCM0R,#0a0h; DE, STE, FRE, CE, GFR, GRE, SF=4/3, S/D=40
; display enable
; solid mode
; toggle fringe enable
ld DCM1R,#0x04; register 251 (FBh) Control Mode 1 register
; DAT[6:4]/bits 7,6,5 & TDR/bit4
; FNEX=0, on-chip font
; FBL=1 fastblanking active high
; PM =0 Full page mode
; SPM =0 serial mode
;--------Dram location: header/status rows, current display
; FC, Dram Location register
ld TDPR, #080h; HS[3:0], AD[3:0]
; for header bit12=1
;------- foreground/background
spp #DMP2_PG; page 021h Display memory map registers page
ld DC, #07Fh ; reg. F0h, DFG [3:0], DBG [3:0]
; FG full white
; BG grey (half white)
;-----------------------------
spp #DMP1_PG; page 020h Display memory map registers page
ld DE0R, #0FFh; ROWEN [8:1]
ld DE1R, #0FFh; ROWEN [16:9]
ld DE2R, #0FFh; ROWEN [23:17]
ret
=======================================================================
135/178
ST92185 - SYNC CONTROLLER
7.5 SYNC CONTROLLER
sharing by the Display Controller and the CPU (for
more details refer to the TDSRAM Controller chap-
ter). Field information is also available for the Dis-
play Controller.
The SYNC Controller receives Horizontal / Vertical
sync information coming from the chassis. The
VSYNC and HSYNC inputs use schmitt triggers to
guarantee sufficient noise rejection.
The SYNC Controller unit also generates two in-
terrupt sources corresponding respectively the TV
field start and to the end of VBI event (“VBI” stands
for Vertical Blank Interval).
The SYNC Controller unit provides the H internal
sync signal to the Display Skew Corrector, which
rephases the Pixel clock.
The SYNC Controller implements also a “Compos-
ite Sync” signal generator which provides a com-
posite sync output signal (called CSO) available
through an I/O port alternate function.
It provides also the H and V internal sync signals
to the TDSRAM Controller to perform correct TV
line counting, thus generating the necessary time
windows for a proper TDSRAM access real time
Figure 83. Sync Controller Block Diagram
n
Vout
VSYNC
VPOL
(to DISPLAY, etc.)
VSEP
FLDST
interrupt
Vertical
Pulse
shaper
Sync Extr.
HSYNC
CSYNC
HPOL
VDLY
Vcso
VPOL
Field
(from Sync Ext.)
MOD1
Vertical Pulse
Generator
Vertical
Controller
MOD0
MOD0
4 MHz
1
0
MOD1
0
1
Equalization Pulse
& Line Sequencer
CSO_AF
Hpls
Internal
H generator
(64 µs)
Composite Sync.
Generator
(MOD0+MOD1)*VSEP
HSF(3:0)
Vout
Hpls
FLDEV
Field
detect.
pgmble
delay
Skew
Hint
Corrector
Vout
Pulse
shaper
VDLY
HPOL
VPOL
EOFVBI
VBIEN
FLDEV
MOD0
MOD1
EOFVBI
interrupt
line counter
FLDST
VSEP
HSF(3:0)
FSTEN
HFLG
Hout (to DISPLAY, etc.)
SCCS0 Register
SCCS1R Register
VR02092A
136/178
ST92185 - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.1 H/V Polarity Control
ning of the line 25 counted from the deflection cir-
cuitry (i.e. from VSYNC); and is called the “End OF
VBI” interrupt. A flag is associated to this interrupt,
called “EOFVBI” (SCCS1R.7). This flag is set to
“1” by hardware when the line 25 starts. It must be
cleared by software.
Two control bits manage the H/V polarities. HPOL
(SCCS0R.6) manages the HSYNC polarity (a pos-
itive polarity assumes the leading edge is the ris-
ing one). VPOL (SCCS0R.7) controls the VSYNC
polarity.
These two interrupts EOFVBI and FLDST are re-
spectively attached to the INT4 and INT5 external
interrupt inputs of the ST9+ Core. The leading
edges of the 2 interrupt requests are the falling
ones. (For more details, refer to the Interrupts
chapter).
7.5.2 Field Detection
Field detection is necessary information for the
Display controller for fringe and rounding features.
To determine correctly the field in case of using
separate H and V input signals, it is necessary to
provide an internal compensation of the hardware
delay generated on VSYNC (VSYNC is generally
issued by integrating the equalization pulses).
Therefore the VSYNC leading edge is compared
to the leading edge of an internally delayed
HSYNC.
7.5.4 Sync Controller Working Modes
Different working modes are available fully control-
led by software.
The first two working modes assume that TV de-
flection sync signals are available and stable.
The delay applied to HSYNC is software program-
mable through the SCCS0R (3:0) bits (from 0 to 63
µs). It must be calculated by the user as being the
time constant (modulo 64 µs) used to extract
VSYNC by the other components of the chassis.
The last two modes assume that no TV signal is
available. The chip works in a free-running mode
providing standard TV Sync signals based on the
main internal 4 MHz clock.
Switching from one mode to any other is done un-
der full software control, through the programming
of two control bits called as MOD1 and MOD0.
These control bits are described in the SCCS1R
register
7.5.3 Interrupt Generation
The SYNC Controller unit can provide two different
interrupts to the ST9+ Core. The first interrupt ap-
pears at each beginning of field upon detection of
the Vertical Sync pulse coming from the deflection
circuitry (i.e. from VSYNC); it is called the “Field
start” interrupt. A flag is associated to this inter-
rupt, called “FLDST” (SCCS1R.6). This flag is set
to “1” by hardware when the Vertical Sync pulse
appears. It must be cleared by software.
7.5.4.1 Standard Sync Input Mode
This mode is accessed when both MOD1 and
MOD0 bits are reset.
In this mode, the µP receives the chassis synchro
through two separate inputs. These are VSYNC
and HSYNC. It also assumes the VSEP
(SCCS0R.5) is reset.
The second interrupt appears at the end of each
Vertical Blank Interval. It is generated at the begin-
137/178
ST92185 - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.4.2 Composite Sync Input Mode
The CSYNC signal characteristics are assumed to
perfectly respect the STV2160 TXTOUT pin spec-
ification which is reviewed in Figure 84 & Figure
85.
This mode is very similar to the “Standard Sync In-
put Mode” described above. It is also accessed
when both MOD1 and MOD0 bits are reset.
The vertical sync signal is extracted from the
CSYNC signal by the mean of an Up/Down coun-
ter used as a digital integrator. The counter works
in “Up” mode during the sync pulses.
In Composite Sync mode, a single CSYNC/
HSYNC input pin is used to enter both the horizon-
tal and vertical sync pulses (VSEP control bit is set
to 1). In this mode, the VSYNC pin must be tied to
VSS on the application board to prevent a floating
CMOS input configuration.
Two time constants can be programmed using the
VDLY control bit (refer to the register description).
The smallest one corresponds to 16µs; the second
one being 32µs.
Figure 84. STV2160 TXTOUT Timings
n
1st TV Field
3
4
5
623
624
1
2
6
625
8µs
8µs
58µs 38µs 8µs
TXTOUT
2nd TV Field
311
319
312
313
314
315
6µs
316
317
318
VR02092B
8µs
8µs
58µs 8µs
TXTOUT
138/178
ST92185 - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.4.3 Free-Running Monitor Sync Mode
This mode is accessed when the MOD1 bit is set.
Sync output (CSO) is generated for a 50Hz format.
For both formats, the TV line period is 64µs.
The Composite Sync alternate function Output
(CSO) can be activated or disabled under control
of the VSEP bit.
In this mode, the chassis HSYNC and VSYNC sig-
nals are not used. They are replaced by the sync
signals which are fully Crystal based (use of the in-
ternal main 4 MHz Clock).
In Free-Running Monitor Sync mode, the VPOL
control bit is used to control whether an interlaced
or non-interlaced TV context must be generated.
When the non-interlaced context is programmed,
only the “1st TV Field” configuration is generated.
Two free-running monitor modes are available:
when the MOD0 bit is reset the Composite Sync
output (CSO) is generated for a 60Hz format;
when the MOD0 bit is set to “1” the Composite
Figure 85. Even/Odd Field Timings
n
1st TV Field
d1
d2
d1
3
3
4
4
5
5
(50 Hz Mode)
(60 Hz Mode)
623
523
624
524
1
1
2
2
6
6
622
522
625
525
d2 = 2.25 µs
d1 = 4.75 µs
2nd TV Field
d1
d2
310
260
(50 Hz Mode)
311
261
319
269
312
262
313
263
314
264
315
265
316
266
317
267
318
268
(60 Hz Mode)
VR02092C
139/178
ST92185 - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.5 Register Description
For other cases:
MOD1 MOD0 VSEP
CSO alternate function
SYNC CONTROLLER CONTROL AND STATUS
REGISTER 0 (SCCS0R)
R242 - Read/Write
Register Page: 35
Reset value: 0000 0000 (00h)
0
x
x
1
1
0
1
1
x
x
x
0
1
0
1
disabled
disabled
enabled
disabled
enabled
0
VPOL HPOL VSEP VDLY HSF3 HSF2 HSF1 HSF0
Bit 4= VDLY. Vertical Delay control bit.
This bit is active only if the Composite Sync mode
is enabled. The selection of this bit can effect
noise margin (longer delay is better) and the field
detection.
0: Vertical is generated after detecting a pulse
greater than 16µs
Bit 7= VPOL. VSYNC Polarity
When MOD[1:0] are reset, this bit configures the
polarity of the VSYNC input.
0: Negative polarity (leading edge is falling edge)
1: Positive polarity (leading edge is rising edge)
1: Vertical is generated after detecting a pulse
greater than 32µs
For other cases:
MOD1 MOD0 VPOL
0
x
x
1
1
0
1
1
x
x
x
0
1
0
1
VSYNC polarity control
interlaced
Bit 3:0= HSF. Horizontal Shift for Field detection.
These 4 bits program the delay, in steps of 4µs,
applied to the HSYNC pulse in order to properly
determine the field information by comparison with
VSYNC. This value is a chassis constant depend-
ing upon the way the separate H/V signals are
generated.
non-interlaced
interlaced
non-interlaced
Bit 6= HPOL. HSYNC/CSYNC Polarity.
0: Negative polarity (leading edge is falling edge)
1: Positive polarity (leading edge is rising edge)
Bit 5= VSEP. Separate Sync
When MOD[1:0] are reset:
0: The standard mode using two inputs (VSYNC
and HSYNC) is activated.
1: The Composite Sync mode is activated; the
HSYNC/CSYNC input will be used to get both H
and V signals.
140/178
ST92185 - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
SYNC CONTROLLER CONTROL AND STATUS
REGISTER 1 (SCCS1R)
Bit 4= HFLG: Horizontal Sync Flag.
This bit is read-only. It just copies the Horizontal
sync transient information issued by the horizontal
pulse shape unit. The bit is read at “1” at during
each H sync pulse and lasts to “1” up to 4 µs.
R243 - Read/Write
Register Page: 35
Reset value: 0000 0000 (00h)
7
0
Bit 3= FSTEN: Field Start Interrupt Enable.
0: The FLDST interrupt is disabled and the exter-
nal interrupt pin becomes the interrupt input.
1: The FLDST interrupt is enabled and the inter-
rupt from the external pin is disabled.
EOFVBI FLDST FLDEV HFLG FSTEN VBIEN MOD1 MOD0
Bit 7= EOFVBI: End Of VBI Flag.
This bit is set to “1” by hardware at the beginning
of the line 25 of the current field, when the End of
VBI interrupt request is sent to the Core. The
EOFVBI flag must be reset by software before the
end of the current field.
Bit 2= VBIEN: VBI Interrupt Enable.
0: The EOFVBI interrupt is disabled and the exter-
nal interrupt pin becomes the interrupt input.
1: The EOFVBI interrupt is enabled and the inter-
rupt from the external pin is disabled.
Bit 6= FLDST: Field Start Flag.
Bit 1:0= MOD[1:0]:
This bit is set to “1” by hardware on the leading
edge of the vertical sync pulse when the field start
interrupt request is forwarded to the Core. The
FLDST flag must be reset by software before the
end of the current field.
H & V sync
MOD1 MOD0
CSO
CSO generator
sources
chassis
sync pulses
0
0
1
0
1
0
no
-
reserved
reserved
from Xtal
(60 Hz)
on-chip timing genera-
tor; free-running
yes
yes
Bit 5= FLDEV: Field Even Flag.
This bit is read-only. It indicates which field is cur-
rently running;
0: First field is running
1: Second field is running
from Xtal
(50 Hz)
on-chip timing genera-
tor; free-running
1
1
n
141/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
7.6 SERIAL PERIPHERAL INTERFACE (SPI)
7.6.1 Introduction
■ Master operation only
■ 4 Programmable bit rates
■ Programmable clock polarity and phase
■ Busy Flag
The Serial Peripheral Interface (SPI) is a general
purpose on-chip shift register peripheral. It allows
communication with external peripherals via an
SPI protocol bus.
■ End of transmission interrupt
In addition, special operating modes allow re-
■ Additional hardware to facilitate more complex
2
duced software overhead when implementing I C-
protocols
bus and IM-bus communication standards.
7.6.2 Device-Specific Options
The SPI uses up to 3 pins: Serial Data In (SDI),
Serial Data Out (SDO) and Synchronous Serial
Clock (SCK). Additional I/O pins may act as device
selects or IM-bus address identifier signals.
Depending on the ST9 variant and package type,
the SPI interface signals may not be connected to
separate external pins. Refer to the Peripheral
Configuration Chapter for the device pin-out.
The main features are:
■ Full duplex synchronous transfer if 3 I/O pins are
used
Figure 86. Block Diagram
SDI SCK/INT2
SDO
READ BUFFER
SERIAL PERIPHERAL INTERFACE DATA REGISTER
( SPIDR )
R253
*
DATA BUS
END OF
TRANSMISSION
INT2
POLARITY
1
0
PHASE
MULTIPLEXER
BAUD RATE
INTERNAL
SERIAL
CLOCK
INTCLK
R254
TO MSPI
CONTROL
LOGIC
SPEN BMS ARB BUSY CPOL CPHA SPR1 SPR0
SERIAL PERIPHERAL CONTROL REGISTER ( SPICR )
ST9 INTERRUPT
INTB0
* Common for Transmit and Receive
VR000347
n
142/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
7.6.3.1 Input Signal Description
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.3 Functional Description
The SPI, when enabled, receives input data from
the internal data bus to the SPI Data Register
(SPIDR). A Serial Clock (SCK) is generated by
controlling through software two bits in the SPI
Control Register (SPICR). The data is parallel
loaded into the 8 bit shift register during a write cy-
cle. This is shifted out serially via the SDO pin,
MSB first, to the slave device, which responds by
sending its data to the master device via the SDI
pin. This implies full duplex transmission if 3 I/O
pins are used with both the data-out and data-in
synchronized with the same clock signal, SCK.
Thus the transmitted byte is replaced by the re-
ceived byte, eliminating the need for separate “Tx
empty” and “Rx full” status bits.
Serial Data In (SDI)
Data is transferred serially from a slave to a mas-
ter on this line, most significant bit first. In an S-
2
BUS/I C-bus configuration, the SDI line senses
the value forced on the data line (by SDO or by an-
2
other peripheral connected to the S-bus/I C-bus).
7.6.3.2 Output Signal Description
Serial Data Out (SDO)
The SDO pin is configured as an output for the
master device. This is obtained by programming
the corresponding I/O pin as an output alternate
function. Data is transferred serially from a master
to a slave on SDO, most significant bit first. The
master device always allows data to be applied on
the SDO line one half cycle before the clock edge,
in order to latch the data for the slave device. The
SDO pin is forced to high impedance when the SPI
is disabled.
When the shift register is loaded, data is parallel
transferred to the read buffer and becomes availa-
ble to the CPU during a subsequent read cycle.
The SPI requires three I/O port pins:
2
During an S-Bus or I C-Bus protocol, when arbi-
tration is lost, SDO is set to one (thus not driving
the line, as SDO is configured as an open drain).
SCK
SDO
SDI
Serial Clock signal
Serial Data Out
Serial Data In
Master Serial Clock (SCK)
An additional I/O port output bit may be used as a
slave chip select signal. Data and Clock pins I²C
Bus protocol are open-drain to allow arbitration
and multiplexing.
The master device uses SCK to latch the incoming
data on the SDI line. This pin is forced to a high im-
pedance state when SPI is disabled (SPEN,
SPICR.7 = “0”), in order to avoid clock contention
from different masters in a multi-master system.
The master device generates the SCK clock from
INTCLK. The SCK clock is used to synchronize
data transfer, both in to and out of the device,
through its SDI and SDO pins. The SCK clock
type, and its relationship with data is controlled by
the CPOL (Clock Polarity) and CPHA (Clock
Phase) bits in the Serial Peripheral Control Regis-
ter (SPICR). This input is provided with a digital fil-
ter which eliminates spikes lasting less than one
INTCLK period.
Figure 2 below shows a typical SPI network.
Figure 87. A Typical SPI Network
Two bits, SPR1 and SPR0, in the Serial Peripheral
Control Register (SPICR), select the clock rate.
Four frequencies can be selected, two in the high
frequency range (mostly used with the SPI proto-
col) and two in the medium frequency range
(mostly used with more complex protocols).
n
143/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 88. SPI I/O Pins
n
7.6.4 Interrupt Structure
The SPI peripheral is associated with external in-
terrupt channel B0 (pin INT2). Multiplexing be-
tween the external pin and the SPI internal source
is controlled by the SPEN and BMS bits, as shown
in Table 1 Interrupt Configuration.
SCK
SDO
SPI
SDI
The two possible SPI interrupt sources are:
– End of transmission (after each byte).
2
– S-bus/I C-bus start or stop condition.
PORT
BIT
SDI
Care should be taken when toggling the SPEN
and/or BMS bits from the “0,0” condition. Before
changing the interrupt source from the external pin
to the internal function, the B0 interrupt channel
should be masked. EIMR.2 (External Interrupt
Mask Register, bit 2, IMBO) and EIPR.2 (External
Interrupt Pending Register bit 2, IMP0) should be
“0” before changing the source. This sequence of
events is to avoid the generating and reading of
spurious interrupts.
LATCH
PORT
BIT
SCK
INT2
LATCH
PORT
BIT
SDO
LATCH
A delay instruction lasting at least 4 clock cycles
(e.g. 2 NOPs) should be inserted between the
SPEN toggle instruction and the Interrupt Pending
bit reset instruction.
INT2
The INT2 input Function is always mapped togeth-
er with the SCK input Function, to allow Start/Stop
2
bit detection when using S-bus/I C-bus protocols.
A start condition occurs when SDI goes from “1” to
“0” and SCK is “1”. The Stop condition occurs
when SDI goes from “0” to “1” and SCK is “1”. For
both Stop and Start conditions, SPEN = “0” and
BMS = “1”.
Table 27. Interrupt Configuration
SPEN BMS
Interrupt Source
External channel INT2
0
0
1
0
1
2
S-bus/I C bus start or stop condition
X
End of a byte transmission
144/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.5 Working With Other Protocols
Each transmission consists of nine clock pulses
(SCL line). The first 8 pulses transmit the byte
(MSB first), the ninth pulse is used by the receiver
to acknowledge.
The SPI peripheral offers the following facilities for
2
operation with S-bus/I C-bus and IM-bus proto-
cols:
2
■ Interrupt request on start/stop detection
■ Hardware clock synchronisation
Figure 89. S-Bus / I C-bus Peripheral
Compatibility without S-Bus Chip Select
■ Arbitration lost flag with an automatic set of data
line
Note that the I/O bit associated with the SPI should
be returned to a defined state as a normal I/O pin
before changing the SPI protocol.
The following paragraphs provide information on
how to manage these protocols.
2
7.6.6 I C-bus Interface
2
The I C-bus is a two-wire bidirectional data-bus,
the two lines being SDA (Serial DAta) and SCL
(Serial CLock). Both are open drain lines, to allow
arbitration. As shown in Figure 5, data is toggled
with clock low. An I²C bus start condition is the
transition on SDI from 1 to 0 with the SCK held
high. In a stop condition, the SCK is also high and
the transition on SDI is from 0 to 1. During both of
these conditions, if SPEN = 0 and BMS = 1 then
an interrupt request is performed.
145/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
2
Table 28. Typical I C-bus Sequences
Phase
Software
Hardware
Notes
SPICR.CPOL, CPHA = 0, 0
SPICR.SPEN = 0
SPICR.BMS = 1
SCK pin set as AF output
SDI pin set as input
Set SDO port bit to 1
Set polarity and phase
SPI disable
START/STOP interrupt
Enable
SCK, SDO in HI-Z
SCL, SDA = 1, 1
INITIALIZE
SDO pin set as output
Open Drain
Set SDO port bit to 0
SDA = 0, SCL = 1
interrupt request
START condition
receiver START detection
START
SPICR.SPEN = 1
SDO pin as Alternate Func- Start transmission
tion output load data into
SPIDR
SCL = 0
Managed by interrupt rou-
tine load FFh when receiv-
ing end of transmission
detection
TRANSMISSION
Interrupt request at end of
byte transmission
SPICR.SPEN = 0
Poll SDA line
Set SDA line
SCK, SDO in HI-Z
SCL, SDA = 1
SPI disable
only if transmitting
only if receiving
only if transmitting
ACKNOWLEDGE
STOP
SPICR.SPEN = 1
SCL = 0
SDO pin set as output
Open Drain
SPICR.SPEN = 0
Set SDO port bit to 1
SDA = 1
interrupt request
STOP condition
Figure 90. SPI Data and Clock Timing (for I2C protocol)
th
1st BYTE
n
BYTE
SDA
AcK
AcK
SCL
1
2
8
9
1
2
8
9
CLOCK PULSE
CLOCK PULSE
FOR ACKNOWLEDGEMENT
DRIVEN BY SW
FOR ACKNOWLEDGEMENT
DRIVEN BY SOFTWARE
START
STOP
CONDITION
CONDITION
VR000188
n
146/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
The data on the SDA line is sampled on the low to
high transition of the SCL line.
ferent clock sources and different frequencies can
be interfaced.
2
SPI working with an I C-bus
Arbitration Lost
2
To use the SPI with the I C-bus protocol, the SCK
When several masters are sending data on the
SDA line, the following takes place: if the transmit-
ter sends a “1” and the SDA line is forced low by
another device, the ARB flag (SPICR.5) is set and
the SDO buffer is disabled (ARB is reset and the
SDO buffer is enabled when SPIDR is written to
again). When BMS is set, the peripheral clock is
supplied through the INT2 line by the external
clock line (SCL). Due to potential noise spikes
(which must last longer than one INTCLK period to
be detected), RX or TX may gain a clock pulse.
Referring to Figure 6, if device ST9-1 detects a
noise spike and therefore gains a clock pulse, it
will stop its transmission early and hold the clock
line low, causing device ST9-2 to freeze on the 7th
bit. To exit and recover from this condition, the
BMS bit must be reset; this will cause the SPI logic
to be reset, thus aborting the current transmission.
An End of Transmission interrupt is generated fol-
lowing this reset sequence.
line is used as SCL; the SDI and SDO lines, exter-
nally wire-ORed, are used as SDA. All output pins
must be configured as open drain (see Figure 4).
2
Table 2. illustrates the typical I C-bus sequence,
comprising 5 phases: Initialization, Start, Trans-
mission, Acknowledge and Stop. It should be not-
ed that only the first 8 bits are handled by the SPI
peripheral; the ACKNOWLEDGE bit must be man-
aged by software, by polling or forcing the SCL
and SDO lines via the corresponding I/O port bits.
2
During the transmission phase, the following I C-
bus features are also supported by hardware.
Clock Synchronization
2
In a multimaster I C-bus system, when several
masters generate their own clock, synchronization
is required. The first master which releases the
SCL line stops internal counting, restarting only
when the SCL line goes high (released by all the
other masters). In this manner, devices using dif-
Figure 91. SPI Arbitration
ST9-1
ST9-2
INTERNAL SERIAL
CLOCK
INTERNAL SERIAL
CLOCK
SCK
SCK
0
0
MSPI
MSPI
CONTROL
CONTROL
LOGIC
LOGIC
1
1
INT 2
INT 2
BHS
BHS
ST9-2-SCK
1
1
2
2
3
3
4
5
5
6
6
7
7
8
SPIKE
4
ST9-1-SCK
VR001410
n
n
147/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.7 S-Bus Interface
The S-bus is a three-wire bidirectional data-bus,
SPI Working with S-bus
2
possessing functional features similar to the I C-
The S-bus protocol uses the same pin configura-
2
bus. As opposed to the I C-bus, the Start/Stop
2
tion as the I C-bus for generating the SCL and
conditions are determined by encoding the infor-
mation on 3 wires rather than on 2, as shown in
Figure 8. The additional line is referred as SEN.
SDA lines. The additional SEN line is managed
through a standard ST9 I/O port line, under soft-
ware control (see Figure 4).
2
Figure 92. Mixed S-bus and I C-bus System
SCL
SDA
SEN
1
2
3
4
5
6
STOP
VA00440
START
n
Figure 93. S-bus Configuration
n
148/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.8 IM-bus Interface
The IM-bus features a bidirectional data line and a
clock line; in addition, it requires an IDENT line to
distinguish an address byte from a data byte (Fig-
line is set to the Open-Drain configuration, the in-
coming data bits that are set to “1” do not affect the
SDO/SDI line status (which defaults to a high level
due to the FFh value in the transmit register), while
incoming bits that are set to “0” pull the input line
low.
2
ure 10). Unlike the I C-bus protocol, the IM-bus
protocol sends the least significant bit first; this re-
quires a software routine which reverses the bit or-
der before sending, and after receiving, a data
byte. Figure 9 shows the connections between an
IM-bus peripheral and an ST9 SPI. The SDO and
SDI pins are connected to the bidirectional data
pin of the peripheral device. The SDO alternate
function is configured as Open-Drain (external
2.5KΩ pull-up resistors are required).
With this type of configuration, data is sent to the
peripheral by writing the data byte to the SPIDR
register. To receive data from the peripheral, the
user should write FFh to the SPIDR register, in or-
der to generate the shift clock pulses. As the SDO
In software it is necessary to initialise the ST9 SPI
by setting both CPOL and CPHA to “1”. By using a
general purpose I/O as the IDENT line, and forcing
it to a logical “0” when writing to the SPIDR regis-
ter, an address is sent (or read). Then, by setting
this bit to “1” and writing to SPIDR, data is sent to
the peripheral. When all the address and data
pairs are sent, it is necessary to drive the IDENT
line low and high to create a short pulse. This will
generate the stop condition.
Figure 94. ST9 and IM-bus Peripheral
V
DD
2x
2.5 K
SCK
SDI
CLOCK
DATA
SDO
IDENT
PORTX
IM-BUS
SLAVE
DEVICE
ST9 MCU
IM-BUS
PROTOCOL
VR001427
n
Figure 95. IM bus Timing
IDENT
CLOCK LINE
LSB
2
3
6
MSB
2
MSB
1
5
DATA LINE
LSB
1
3
4
5
6
4
VR000172
149/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.9 Register Description
1: Both alternate functions SCK and SDO are ena-
bled.
It is possible to have up to 3 independent SPIs in
the same device (refer to the device block dia-
gram). In this case they are named SPI0 thru
SPI2. If the device has one SPI converter it uses
the register adresses of SPI0. The register map is
the following:
Note: furthermore, SPEN (together with the BMS
bit) affects the selection of the source for interrupt
channel B0. Transmission starts when data is writ-
ten to the SPIDR Register.
2
Register
SPIn
SPI0
SPI0
SPI1
SPI1
SPI2
SPI2
Page
Bit 6 = BMS: S-bus/I C-bus Mode Selector.
0: Perform a re-initialisation of the SPI logic, thus
allowing recovery procedures after a RX/TX fail-
ure.
SPIDR R253
SPICR R254
SPIDR1 R253
SPICR1 R254
SPIDR2 R245
SPICR2 R246
0
0
7
7
7
7
2
1: Enable S-bus/I C-bus arbitration, clock synchro-
nization and Start/ Stop detection (SPI used in
2
an S-bus/I C-bus protocol).
Note: when the BMS bit is reset, it affects (togeth-
er with the SPEN bit) the selection of the source
for interrupt channel B0.
Note: In the register description on the following
pages, register and page numbers are given using
the example of SPI0.
Bit 5 = ARB: Arbitration flag bit.
This bit is set by hardware and can be reset by
software.
0: S-bus/I C-bus stop condition is detected.
1: Arbitration lost by the SPI in S-bus/I C-bus
SPI DATA REGISTER (SPIDR)
R253 - Read/Write
Register Page: 0
Reset Value: undefined
2
2
mode.
Note: when ARB is set automatically, the SDO pin
is set to a high value until a write instruction on
SPIDR is performed.
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 4 = BUSY: SPI Busy Flag.
Bit 7:0 = D[0:7]: SPI Data.
This bit is set by hardware. It allows the user to
monitor the SPI status by polling its value.
0: No transmission in progress.
This register contains the data transmitted and re-
ceived by the SPI. Data is transmitted bit 7 first,
and incoming data is received into bit 0. Transmis-
sion is started by writing to this register.
1: Transmission in progress.
Bit 3 = CPOL: Transmission Clock Polarity.
Note: SPIDR state remains undefined until the
CPOL controls the normal or steady state value of
the clock when data is not being transferred.
Please refer to the following table and to Figure 11
to see this bit action (together with the CPHA bit).
end of transmission of the first byte.
SPI CONTROL REGISTER (SPICR)
R254 - Read/Write
Register Page: 0
Reset Value: 0000 0000 (00h)
Note: As the SCK line is held in a high impedance
state when the SPI is disabled (SPEN = “0”), the
SCK pin must be connected to V
or to V
SS
CC
through a resistor, depending on the CPOL state.
Polarity should be set during the initialisation rou-
tine, in accordance with the setting of all peripher-
als, and should not be changed during program
execution.
7
0
SPEN BMS ARB BUSY CPOL CPHA SPR1 SPR0
Bit 7 = SPEN: Serial Peripheral Enable.
0: SCK and SDO are kept tristate.
150/178
ST92185 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Bit 2 = CPHA: Transmission Clock Phase.
Bit 1:0 = SPR[1:0]: SPI Rate.
CPHA controls the relationship between the data
on the SDI and SDO pins, and the clock signal on
the SCK pin. The CPHA bit selects the clock edge
used to capture data. It has its greatest impact on
the first bit transmitted (MSB), because it does (or
does not) allow a clock transition before the first
data capture edge. Figure 11 shows the relation-
ship between CPHA, CPOL and SCK, and indi-
cates active clock edges and strobe times.
These two bits select one (of four) baud rates, to
be used as SCK.
Clock
Divider
SCK Frequency
(@ INTCLK = 24MHz)
SPR1 SPR0
0
0
1
1
0
1
0
1
8
16
128
256
3000kHz
(T = 0.33μs)
(T = 0.67μs)
(T = 5.33μs)
(T = 10.66μs)
1500kHz
187.5kHz
93.75kHz
SCK
(in Figure 11)
CPOL
CPHA
0
0
1
1
0
1
0
1
(a)
(b)
(c)
(d)
Figure 96. SPI Data and Clock Timing
151/178
ST92185 - A/D CONVERTER (A/D)
7.7 A/D CONVERTER (A/D)
7.7.1 Introduction
■ Single/Continuous Conversion Mode
■ External/Internal source Trigger (Alternate
The 8 bit Analog to Digital Converter uses a fully
differential analog configuration for the best noise
immunity and precision performance. The analog
voltage references of the converter are connected
synchronization)
■ Power Down mode (Zero Power Consumption)
■ 1 Control Logic Register
■ 1 Data Register
to the internal AV & AV analog supply pins of
DD
SS
the chip if they are available, otherwise to the ordi-
nary V and V supply pins of the chip. The
DD
SS
guaranteed accuracy depends on the device (see
Electrical Characteristics). A fast Sample/Hold al-
lows quick signal sampling for minimum warping
effect and conversion error.
7.7.3 General Description
Depending on the device, up to 8 analog inputs
can be selected by software.
Different conversion modes are provided: single,
continuous, or triggered. The continuous mode
performs a continuous conversion flow of the se-
lected channel, while in the single mode the se-
lected channel is converted once and then the log-
ic waits for a new hardware or software restart.
7.7.2 Main Features
■ 8-bit resolution A/D Converter
■ Single Conversion Time (including Sampling
Time):
A data register (ADDTR) is available, mapped in
page 62, allowing data storage (in single or contin-
uous mode).
– 138 internal system clock periods in slow
mode (~5.6 µs @25Mhz internal system
clock);
The start conversion event can be managed by
software, writing the START/STOP bit of the Con-
trol Logic Register or by hardware using either:
– 78 INTCLK periods in fast mode (~6.5 µs @
12MHZ internal system clock)
■ Sample/Hold: Tsample=
– An external signal on the EXTRG triggered input
(negative edge sensitive) connected as an Alter-
nate Function to an I/O port bit
– 84 INTCLK periods in slow mode (~3.4 µs
@25Mhz internal system clock)
– 48 INTCLK periods in fast mode (~4 µs
@12Mhz internal system clock)
– An On Chip Event generated by another periph-
eral, such as the MFT (Multifunction Timer).
■ Up to 4 Analog Inputs (the number of inputs is
device dependent, see device pinout)
Figure 97. A/D Converter Block Diagram
n
SUCCESSIVE
APPROXIMATION
REGISTER
Ain0
Ain1
ANALOG
S/H
MUX
DATA
REGISTER
Ainx
EXTRG
CONTROL LOGIC
INTRG
(On Chip Event)
152/178
ST92185 - A/D CONVERTER (A/D)
A/D CONVERTER (Cont’d)
The conversion technique used is successive ap-
proximation, with AC coupled analog fully differen-
tial comparators blocks plus a Sample and Hold
logic and a reference generator.
These events can be enabled or masked by pro-
gramming the TRG bit in the ADCLR Register.
The effect of alternate synchronization is to set the
STR bit, which is cleared by hardware at the end of
each conversion in single mode. In continuous
mode any trigger pulse following the first one will
be ignored. The synchronization source must pro-
vide a pulse (1.5 internal system clock, 125ns @
12 MHz internal clock) of minimum width, and a
period greater (in single mode) than the conver-
sion time (~6.5us @ 12 MHz internal clock). If a
trigger occurs when the STR bit is still '1' (conver-
sions still in progress), it is ignored (see Electrical
Characteristics).
The internal reference (DAC) is based on the use
of a binary-ratioed capacitor array. This technique
allows the specified monotonicity (using the same
ratioed capacitors as sampling capacitor). A Pow-
er Down programmable bit sets the A/D converter
analog section to a zero consumption idle status.
7.7.3.1 Operating Modes
The two main operating modes, single and contin-
uous, can be selected by writing 0 (reset value) or
1 into the CONT bit of the Control Logic Register.
WARNING: If the EXTRG or INTRG signals are al-
ready active when TRG bit is set, the conversion
starts immediately.
Single Mode
In single mode (CONT=0 in ADCLR) the STR bit is
forced to '0' after the end of channel i-th conver-
sion; then the A/D waits for a new start event. This
mode is useful when a set of signals must be sam-
pled at a fixed frequency imposed by a Timer unit
or an external generator (through the alternate
synchronization feature). A simple software rou-
tine monitoring the STR bit can be used to save
the current value before a new conversion ends
(so to create a signal samples table within the in-
ternal memory or the Register File). Furthermore,
if the R242.0 bit (register AD-INT, bit 0) is set, at
the end of conversion a negative edge on the con-
nected external interrupt channel (see Interrupts
Chapter) is generated to allow the reading of the
converted data by means of an interrupt routine.
7.7.3.3 Power-Up Operations
Before enabling any A/D operation mode, set the
POW bit of the ADCLR Register at least 60 µs be-
fore the first conversion starts to enable the bias-
ing circuits inside the analog section of the con-
verter. Clearing the POW bit is useful when the
A/D is not used so reducing the total chip power
consumption. This state is also the reset configu-
ration and it is forced by hardware when the core is
in HALT state (after a HALT instruction execution).
7.7.3.4 Register Mapping
It is possible to have two independent A/D convert-
ers in the same device. In this case they are
named A/D 0 and A/D 1. If the device has one A/D
converter it uses the register addresses of A/D 0.
The register map is the following:
Continuous Mode
In continuous mode (CONT=1 in ADCLR) a con-
tinuous conversion flow is entered by a start event
on the selected channel until the STR bit is reset
by software.
Register Address
ADn
A/D 0
A/D 0
A/D 0
A/D 0
A/D 1
A/D 1
A/D 1
A/D 1
Page 62 (3Eh)
ADDTR0
ADCLR0
ADINT0
F0h
F1h
At the end of each conversion, the Data Register
(ADCDR) content is updated with the last conver-
sion result, while the former value is lost. When the
conversion flow is stopped, an interrupt request is
generated with the same modality previously de-
scribed.
F2h
F3-F7h
F8h
Reserved
ADDTR1
ADCLR1
ADINT1
F9h
FAh
7.7.3.2 Alternate Synchronization
FB-FFh
Reserved
This feature is available in both single/continuous
modes. The negative edge of external EXTRG sig-
nal or the occurrence of an on-chip event generat-
ed by another peripheral can be used to synchro-
nize the conversion start with a trigger pulse.
If two A/D converters are present, the registers are
renamed, adding the suffix 0 to the A/D 0 registers
and 1 to the A/D 1 registers.
153/178
ST92185 - A/D CONVERTER (A/D)
A/D CONVERTER (Cont’d)
7.7.4 Register Description
0: External/Internal Trigger disabled.
1: Either a negative (falling) edge on the EXTRG
pin or an On Chip Event writes a “1” into the
STR bit, enabling start of conversion.
A/D CONTROL LOGIC REGISTER (ADCLR)
R241 - Read/Write
Register Page: 62
Reset value: 0000 0000 (00h)
Note: Triggering by on chip event is available on
devices with the multifunction timer (MFT) periph-
eral.
7
0
C2
C1
C0
FS TRG POW CONT STR
Bit 2 = POW: Power Enable.
This bit is set and cleared by software.
0: Disables all power consuming logic.
1: Enables the A/D logic and analog circuitry.
This 8-bit register manages the A/D logic opera-
tions. Any write operation to it will cause the cur-
rent conversion to be aborted and the logic to be
re-initialized to the starting configuration.
Bit 1 = CONT: Continuous/Single Mode Select.
This bit it set and cleared by software.
0: Single mode: after the current conversion ends,
the STR bit is reset by hardware and the con-
verter logic is put in a wait status. To start anoth-
er conversion, the STR bit has to be set by soft-
ware or hardware.
Bit 7:5 = C[2:0]: Channel Address.
These bits are set and cleared by software. They
select channel iconversion as follows:
C2
C1
C0
Channel Enabled
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Channel 0
Channel 1
Channel 2
Channel 4
Channel 3
1: Select Continuous Mode, a continuous flow of
A/D conversions on the selected channel, start-
ing when the STR bit is set.
Bit 0 = STR: Start/Stop.
This bit is set and cleared by software. It is also set
by hardware when the A/D is synchronized with an
external/internal trigger.
Bit 4 = FS: Fast/Slow.
This bit is set and cleared by software.
0: Fast mode. Single conversion time: 78 x
INTCLK (5.75µs at INTCLK = 12 MHz)
1: Slow mode. Single conversion time: 138 x
INTCLK (11.5µs at INTCLK = 12 MHz)
0: Stop conversion on channel i. An interrupt is
generated if the STR was previously set and the
AD-INT bit is set.
1: Start conversion on channel i
Note: Fast conversion mode is only allowed for in-
WARNING: When accessing this register, it is rec-
ommended to keep the related A/D interrupt chan-
nel masked or disabled to avoid spurious interrupt
requests.
ternal speeds which do not exceed 12 MHz.
Bit 3 = TRG: External/Internal Trigger Enable.
This bit is set and cleared by software.
154/178
ST92185 - A/D CONVERTER (A/D)
A/D CONVERTER (Cont’d)
A/D CHANNEL iDATA REGISTER (ADDTR)
R240 - Read/Write
A/D INTERRUPT REGISTER (ADINT)
Register Page: 62
Register Page: 62
R242 - Read/write
Reset value: undefined
Reset value: 0000 0001 (01h)
7
0
7
0
0
R.7
R.6
R.5
R.4
R.3
R.2
R.1
R.0
0
0
0
0
0
0
AD-INT
The result of the conversion of the selected chan-
nel is stored in the 8-bit ADDTR, which is reloaded
with a new value every time a conversion ends.
Bit 7:1 = Reserved.
Bit 0 = AD-INT: AD Converter Interrupt Enable.
This bit is set and cleared by software. It allows the
interrupt source to be switched between the A/D
Converter and an external interrupt pin (See Inter-
rupts chapter).
Bit 7:0 = R[7:0]: Channel iconversion result.
0: A/D Interrupt disabled. External pin selected as
interrupt source.
1: A/D Interrupt enabled
155/178
ST92185 - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
7.8 VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
7.8.1 Description
7.8.2 Output Waveforms
The on-chip Voltage Synthesis (VS) converter al-
lows the generation of a tuning reference voltage
in a TV set application. The peripheral is com-
posed of a 14-bit counter that allows the conver-
sion of the digital content in a tuning voltage, avail-
able at the VS output pin, by using PWM (Pulse
Width Modulation) and BRM (Bit Rate Modulation)
techniques. The 14-bit counter gives 16384 steps
which allow a resolution of approximately 2 mV
over a tuning voltage of 32 V. This corresponds to
a tuning resolution of about 40 KHz per step in
UHF band (the actual value will depend on the
characteristics of the tuner).
Included inside the VS are the register latches, a
reference counter, PWM and BRM control circuit-
ry. The clock for the 14-bit reference counter is de-
rived from the main system clock (referred to as
INTCLK) after a division by 4. For example, using
an internal 12 MHz on-chip clock (see Timing &
Clock Controller chapter) leads to a 3 MHz input
for the VS counter.
From the point of view of the circuit, the seven
most significant bits control the coarse tuning,
while the seven least significant bits control the
fine tuning. From the application and software
point of view, the 14 bits can be considered as one
binary number.
The tuning word consists of a 14-bit word con-
tained in the registers VSDR1 (R254) and VSDR2
(R255) both located in page 59.
As already mentioned the coarse tuning consists
of a PWM signal with 128 steps: we can consider
the fine tuning to cover 128 coarse tuning cycles.
Coarse tuning (PWM) is performed using the sev-
en most significant bits. Fine tuning (BRM) is per-
formed using the the seven least significant bits.
With all “0”s loaded, the output is 0. As the tuning
voltage increases from all “0”s, the number of puls-
es in one period increases to 128 with all pulses
being the same width. For values larger than 128,
the PWM takes over and the number of pulses in
one period remains constant at 128, but the width
changes. At the other end of the scale, when al-
most all “1”s are loaded, the pulses will start to link
together and the number of pulses will decrease.
The VS Tuning Converter is implemented with 2
separate outputs (VSO1 and VSO2) that can drive
2 separate Alternate Function outputs of 2 stand-
ard I/O port bits. A control bit allows you to choose
which output is activated (only one output can be
activated at a time).
When a VS output is not selected because the VS
is disabled or because the second output is select-
ed, it stays at a logical “one” level, allowing you to
use the corresponding I/O port bit either as a nor-
mal I/O port bit or for a possible second Alternate
Function output.
When all “1”s are loaded, the output will be almost
100% high but will have a low pulse (1/16384 of
the high pulse).
A second control bit allows the VS function to be
started (or stopped) by software.
156/178
ST92185 - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
VOLTAGE SYNTHESIS (Cont’d)
PWM Generation
greater than Low time) the average output voltage
is higher. The external components of the RC net-
work should be selected for the filtering level re-
quired for control of the system variable.
The counter increments continuously, clocked at
INTCLK divided by 4. Whenever the 7 least signif-
icant bits of the counter overflow, the VS output is
set.
Figure 98. Typical PWM Output Filter
The state of the PWM counter is continuously
compared to the value programmed in the 7 most
significant bits of the tuning word. When a match
occurs, the output is reset thus generating the
PWM output signal on the VS pin.
1K
OUTPUT
VOLTAGE
PWM OUT
This Pulse Width modulated signal must be fil-
tered, using an external RC network placed as
close as possible to the associated pin. This pro-
vides an analog voltage proportional to the aver-
age charge passed to the external capacitor. Thus
for a higher mark/space ratio (High time much
R
ext
C
ext
Figure 99. PWM Generation
COUNTER
OVERFLOW
127
OVERFLOW
OVERFLOW
7-BIT PWM
VALUE
000
t
t
PWM OUTPUT
INTCLK/4 x 128
157/178
ST92185 - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
VOLTAGE SYNTHESIS (Cont’d)
Figure 100. PWM Simplified Voltage Output After Filtering (2 examples)
V
DD
PWMOUT
0V
V
(mV)
V
ripple
V
DD
OUTPUT
VOLTAGE
OUTAVG
0V
"CHARGE"
"DISCHARGE"
"CHARGE"
"DISCHARGE"
V
DD
PWMOUT
0V
V
DD
V
(mV)
ripple
OUTPUT
VOLTAGE
0V
V
OUTAVG
VR01956
"CHARGE"
"DISCHARGE"
"CHARGE"
"DISCHARGE"
158/178
ST92185 - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
VOLTAGE SYNTHESIS (Cont’d)
BRM Generation
Table 29. 7-Bit BRM Pulse Addition Positions
The BRM bits allow the addition of a pulse to wid-
en a standard PWM pulse for specific PWM cy-
cles. This has the effect of “fine-tuning” the PWM
Duty cycle (without modifying the base duty cycle),
thus, with the external filtering, providing additional
fine voltage steps.
No. of Pulses added at the
Fine Tuning
following Cycles
0000001
0000010
0000100
0001000
0010000
0100000
1000000
64
32, 96
16, 48, 80, 112
8, 24,... 104, 120
4, 12,... 116, 124
2, 6,... 122, 126
1, 3,... 125, 127
The incremental pulses (with duration of T
/
INTCLK
4) are added to the beginning of the original PWM
pulse and thus cause the PWM high time to be ex-
tended by this time with a corresponding reduction
in the low time. The PWM intervals which are add-
ed to are specified in the lower 7 bits of the tuning
word and are encoded as shown in the following
table.
The BRM values shown may be combined togeth-
er to provide a summation of the incremental pulse
intervals specified.
The pulse increment corresponds to the PWM res-
olution.
Figure 101. Simplified Filtered Voltage Output Schematic with BRM added
=
=
=
V
DD
PWMOUT
0V
V
DD
BRM = 1
BRM = 0
OUTPUT
VOLTAGE
0V
TINTCLK/4
BRM
EXTENDED PULSE
159/178
ST92185 - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
VOLTAGE SYNTHESIS (Cont’d)
7.8.3 Register Description
VS DATA AND CONTROL REGISTER
(VSDR1)
1
VS DATA AND CONTROL REGISTER
(VSDR2)
2
R254 - Read/Write
R255 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
Register Page: 59
Reset Value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
7
0
VSE VSWP VD13 VD12 VD11 VD10 VD9
VD8
VD7
VD6
VD5
VD4
VD3
VD2
VD1
VD0
Bit 7 = VSE: VS enable bit.
Bit 7:0 = VD[7:0] Tuning word bits.
0: VS Tuning Converter disabled (i.e. the clock is
not forwarded to the VS counter and the 2 out-
puts are set to 1 (idle state)
These bits are the 8 least significant data bits of
the VS Tuning word. All bits are accessible. Bits
VD6 - VD0 form the BRM pulse selection. VD7 is
the LSB of the 7 bits forming the PWM selection.
1: VS Tuning Converter enabled.
Bit 6 = VSWP: VS Output Select
This bit controls which VS output is enabled to out-
put the VS signal.
0: VSO1 output selected
1: VSO2 output selected
Bit 5:0 = VD[13:8] Tuning word bits.
These bits are the 6 most significant bits of the
Tuning word forming the PWM selection. The
VD13 bit is the MSB.
160/178
ST92185 - PWM GENERATOR
7.9 PWM GENERATOR
7.9.1 Introduction
quency range from 1465 Hz up to 23437 Hz can
be achieved.
Higher frequencies, with lower resolution, can be
achieved by using the autoclear register. As an ex-
ample, with a 12 MHz Internal clock, a maximum
PWM repetition rate of 93750 Hz can be reached
with 6-bit resolution.
The PWM (Pulse Width Modulated) signal genera-
tor allows the digital generation of up to 8 analog
outputs when used with an external filtering net-
work.
The unit is based around an 8-bit counter which is
driven by a programmable 4-bit prescaler, with an
input clock signal equal to the internal clock
INTCLK divided by 2. For example, with a 12 MHz
Internal clock, using the full 8-bit resolution, a fre-
Note: The number of output pins is device de-
pendant. Refer to the device pinout description.
Figure 102. PWM Block Diagram.
INTCLK/2
Control Logic
Autoclear
8 Bit Counter
4 Bit Presc.
Compare 7
Compare 6
Compare 5
PWM7
Compare 4
Compare 3
Compare 2
Compare 1
Compare 0
PWM0
VR01765
161/178
ST92185 - PWM GENERATOR
PWM GENERATOR (Cont’d)
Up to 8 PWM outputs can be selected as Alternate
Functions of an I/O port. Each output bit is inde-
pendently controlled by a separate Compare Reg-
ister. When the value programmed into the Com-
pare Register and the counter value are equal, the
corresponding output bit is set. The output bit is re-
set by a counter clear (by overflow or autoclear),
generating the variable PWM signal.
7.9.2 Register Mapping
The ST9 can have one or two PWM Generators.
Each has 13 registers mapped in page 59 (PWM0)
or page 58 (PWM1). In the register description on
the following pages, the register page refers to
PWM0 only.
Register
Address
Register
Function
Each output bit can also be complemented or dis-
abled under software control.
R240
CM0
CM1
CM2
CM3
CM4
CM5
CM6
CM7
ACR
CRR
PCTLR
OCPLR
OER
—
Ch. 0 Compare Register
Ch. 1 Compare Register
Ch. 2 Compare Register
Ch. 3 Compare Register
Ch. 4 Compare Register
Ch. 5 Compare Register
Ch. 6 Compare Register
Ch. 7 Compare Register
Autoclear Register
R241
R242
R243
R244
R245
R246
R247
R248
R249
Counter Read Register
Prescaler/ Reload Reg.
Output Complement Reg.
Output Enable Register
Reserved
R250
R251
R252
R253- R255
Figure 103. PWM Action When Compare Register = 0 (no complement)
PWM
CLOCK
Counter=1
Counter=Autoclear value
Counter=0
PWM
OUTPUT
VR0A1814
Figure 104. PWM Action When Compare Register = 3 (no complement)
PWM
CLOCK
Counter=3
Counter=Autoclear value
Counter=0
PWM
OUTPUT
VR001814
162/178
ST92185 - PWM GENERATOR
PWM GENERATOR (Cont’d)
7.9.2.1 Register Description
COMPARE REGISTER 4 (CM4)
R244 - Read/Write
COMPARE REGISTER 0 (CM0)
R240 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
Register Page: 59
Reset Value: 0000 0000 (00h)
7
0
7
0
CM4.7 CM4.6 CM4.5 CM4.4 CM4.3 CM4.2 CM4.1 CM4.0
CM0.7 CM0.6 CM0.5 CM0.4 CM0.3 CM0.2 CM0.1 CM0.0
This is the compare register controlling PWM out-
put 4.
This is the compare register controlling PWM out-
put 0. When the programmed content is equal to
the counter content, a SET operation is performed
on PWM output 0 (if the output has not been com-
plemented or disabled).
COMPARE REGISTER 5 (CM5)
R245 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
Bit 7:0 = CM0.[7:0]: PWM Compare value Chan-
nel 0.
7
0
CM5.7 CM5.6 CM5.5 CM5.4 CM5.3 CM5.2 CM5.1 CM5.0
COMPARE REGISTER 1 (CM1)
R241 - Read/Write
This is the compare register controlling PWM out-
put 5.
Register Page: 59
Reset Value: 0000 0000 (00h)
7
0
COMPARE REGISTER 6 (CM6)
R246 - Read/Write
CM1.7 CM1.6 CM1.5 CM1.4 CM1.3 CM1.2 CM1.1 CM1.0
Register Page: 59
This is the compare register controlling PWM out-
put 1.
Reset Value: 0000 0000 (00h)
7
0
CM6.7 CM6.6 CM6.5 CM6.4 CM6.3 CM6.2 CM6.1 CM6.0
COMPARE REGISTER 2 (CM2)
R242 - Read/Write
This is the compare register controlling PWM out-
put 6.
Register Page: 59
Reset Value: 0000 0000 (00h)
7
0
CM2.7 CM2.6 CM2.5 CM2.4 CM2.3 CM2.2 CM2.1 CM2.0
COMPARE REGISTER 7 (CM7)
R247 - Read/Write
This is the compare register controlling PWM out-
put 2.
Register Page: 59
Reset Value: 0000 0000 (00h)
7
0
COMPARE REGISTER 3 (CM3)
R243 - Read/Write
CM7.7 CM7.6 CM7.5 CM7.4 CM7.3 CM7.2 CM7.1 CM7.0
Register Page: 59
Reset Value: 0000 0000 (00h)
This is the compare register controlling PWM out-
put 7.
7
0
CM3.7 CM3.6 CM3.5 CM3.4 CM3.3 CM3.2 CM3.1 CM3.0
This is the compare register controlling PWM out-
put 3.
163/178
ST92185 - PWM GENERATOR
PWM GENERATOR (Cont’d)
AUTOCLEAR REGISTER (ACR)
R248 - Read/Write
PRESCALER AND CONTROL REGISTER
(PCTL)
Register Page: 59
R250 - Read/Write
Reset Value: 1111 1111 (FFh)
Register Page: 59
Reset Value: 0000 1100 (0Ch)
7
0
7
0
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
PR3 PR2 PR1 PR0
1
1
CLR CE
This register behaves exactly as a 9th compare
Register, but its effect is to clear the CRR counter
register, so causing the desired PWM repetition
rate.
Bit 7:4 = PR[3:0] PWM Prescaler value.
These bits hold the Prescaler preset value. This is
reloaded into the 4-bit prescaler whenever the
prescaler (DOWN Counter) reaches the value 0,
so determining the 8-bit Counter count frequency.
The value 0 corresponds to the maximum counter
frequency which is INTCLK/2. The value Fh corre-
sponds to the maximum frequency divided by 16
(INTCLK/32).
The reset condition generates the free running
mode. So, FFh means count by 256.
Bit 7:0 = AC[7:0]: Autoclear Count Value.
When 00 is written to the Compare Register, if the
ACR register = FFh, the PWM output bit is always
set except for the last clock count (255 set and 1
reset; the converse when the output is comple-
mented). If the ACR content is less than FFh, the
PWM output bit is set for a number of clock counts
equal to that content (see Figure 2).
The reset condition initializes the Prescaler to the
Maximum Counter frequency.
PR[3:0]
Divider Factor Frequency
0
1
1
2
INTCLK/2 (Max.)
Writing the Compare register constant equal to the
ACR register value causes the output bit to be al-
ways reset (or set if complemented).
INTCLK/4
INTCLK/6
..
2
3
..
..
Example: If 03h is written to the Compare Regis-
ter, the output bit is reset when the CRR counter
reaches the ACR register value and set when it
reaches the Compare register value (after 4 clock
counts, see Figure 3). The action will be reversed
if the output is complemented. The PWM mark/
space ratio will remain constant until changed by
software writing a new value in the ACR register.
Fh
16
INTCLK/32 (Min.)
Bit 3:2 = Reserved. Forced by hardware to “1”
Bit 1 = CLR: Counter Clear.
This bit when set, allows both to clear the counter,
and to reload the prescaler. The effect is also to
clear the PWM output. It returns “0” if read.
COUNTER REGISTER (CRR)
R249 - Read Only
Register Page: 59
Reset Value: 0000 0000 (00h)
Bit 0 = CE: Counter Enable.
This bit enables the counter and the prescaler
when set to “1”. It stops both when reset without
affecting their current value, allowing the count to
be suspended and then restarted by software “on
fly”.
7
0
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
This read-only register returns the current counter
value when read.
The 8 bit Counter is initialized to 00h at reset, and
is a free running UP counter.
Bit 7:0 = CR[7:0]: Current Counter Value.
164/178
ST92185 - PWM GENERATOR
PWM GENERATOR (Cont’d)
OUTPUT COMPLEMENT REGISTER (OCPL)
R251- Read/Write
OUTPUT ENABLE REGISTER (OER)
R252 - Read/Write
Register Page 59
Register Page: 59
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
OCPL.7OCPL.6OCPL.5OCPL.4OCPL.3OCPL.2OCPL.1OCPL.0
OE.7 OE.6 OE.5 OE.4 OE.3 OE.2 OE.1 OE.0
This register allows the PWM output level to be
complemented on an individual bit basis.
These bits are set and cleared by software.
0: Force the corresponding PWM output to logic
level 1. This allows the port pins to be used for
normal I/O functions or other alternate functions
(if available).
In default mode (reset configuration), each com-
parison true between a Compare register and the
counter has the effect of setting the corresponding
output.
1: Enable the corresponding PWM output.
At counter clear (either by autoclear comparison
true, software clear or overflow when in free run-
ning mode), all the outputs are cleared.
Example: Writing 03h into the OE Register will en-
able only PWM outputs 0 and 1, while outputs 2, 3,
4, 5, 6 and 7 will be forced to logic level “1”.
By setting each individual bit (OCPL.x) in this reg-
ister, the logic value of the corresponding output
will be inverted (i.e. reset on comparison true and
set on counter clear).
Bit 7 = OE.7: Output Enable PWM Output 7.
Bit 6 = OE.6: Output Enable PWM Output 6.
Bit 5 = OE.5: Output Enable PWM Output 5.
Bit 4 = OE.4: Output Enable PWM Output 4.
Bit 3 = OE.3: Output Enable PWM Output 3.
Bit 2 = OE.2: Output Enable PWM Output 2.
Bit 1 = OE.1: Output Enable PWM Output 1.
Bit 0 = OE.0: Output Enable PWM Output 0.
Example: When set to “1”, the OCPL.1 bit comple-
ments the PWM output 1.
Bit 7 = OCPL.7: Complement PWM Output 7.
Bit 6 = OCPL.6: Complement PWM Output 6.
Bit 5 = OCPL.5: Complement PWM Output 5.
Bit 4 = OCPL.4: Complement PWM Output 4.
Bit 3 = OCPL.3: Complement PWM Output 3.
Bit 2 = OCPL.2: Complement PWM Output 2.
Bit 1 = OCPL.1: Complement PWM Output 1.
Bit 0 = OCPL.0: Complement PWM Output 0.
165/178
ST92185 - ELECTRICAL CHARACTERISTICS
8 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
- 0.3 to V + 6.5
Unit
V
V
V
V
V
Supply Voltage
Analog Ground
V
V
V
V
V
V
V
DD
SS
SS
DD
SS
SS
SSA
SS
- 0.3 to V + 0.3
V
SSA
DDA
I
SS
Analog Supply Voltage
Input Voltage
-0.3 to V +0.3
V
DD
- 0.3 to V +0.3
V
DD
- 0.3 to V +0.3
DD
V
Analog Input Voltage (A/D Converter)
V
AI
- 0.3 to V
+0.3
DDA
V
Output Voltage
- 0.3 to V + 0.3
V
O
SS
DD
T
Storage Temperature
Pin Injected Current
- 55 to + 150
- 5 to + 5
°C
mA
STG
I
Maximum Accumulated Pin
Injected Current In Device
INJ
- 50 to +5 0
mA
Note: Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Value
Symbol
Parameter
Unit
Min.
0
Max.
70
T
Operating Temperature
Supply Voltage
°C
V
A
V
V
4.5
4.5
3.3
5.5
5.5
8.7
24
DD
Analog Supply Voltage (PLL)
External Oscillator Frequency
Internal Clock Frequency (INTCLK)
V
DDA
OSCE
OSCI
f
f
MHz
MHz
166/178
ST92185 - ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(VDD= 5V +/-10%; T = 0 to 70°C; unless otherwise specified)
A
Value
Symbol
Parameter
Clock In high level
Test Conditions
External clock
Unit
Min.
0.7 V
Max.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IHCK
ILCK
IH
DD
Clock in low level
External clock
TTL
0.3 V
DD
Input high level
2.0
Input low level
TTL
0.8
IL
Input high level
CMOS
CMOS
0.8 V
IH
DD
DD
Input low level
0.2 V
0.3 V
IL
DD
DD
Reset in high level
0.7 V
IHRS
ILRS
HYRS
IHY
Reset in low level
Reset in hysteresis
P2.(1:0) input hysteresis
HSYNC/VSYNC input high level
HSYNC/VSYNC input low level
HSYNC/VSYNC input hysteresis
Output high level
0.3
0.9
0.7 V
IHVH
ILVH
HYHV
OH
DD
0.3 V
DD
0.5
-0.8
Push-pull Ild=-0.8mA
Push-pull ld=+1.6mA
bidir. state
V
DD
Output low level
0.4
OL
I
Weak pull-up current
V
V
= 3V
= 7V
50
µA
WPU
OL
OL
350
+10
+10
+10
+10
I
I
I
I
I/O pin input leakage current
Reset pin input
0<V <V
-10
-10
-10
-10
µA
µA
µA
µA
LKIO
IN
DD
DD
0<V <V
LKRS
LKAD
LKOS
IN
A/D pin input leakage current
OSCIN pin input leakage current
alternate funct. op. drain
0<V <V
IN
DD
167/178
ST92185 - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
PIN CAPACITANCE
(VDD= 5V +/-10%; T = 0 to 70°C; unless otherwise specified))
A
Value
Symbol
Parameter
Conditions
Unit
min
max
C
Pin Capacitance Digital Input/Output
10
pF
IO
CURRENT CONSUMPTION
(VDD= 5V +/-10%; T = 0 to 70°C; unless otherwise specified)
A
Value
typ.
70
Symbol
Parameter
Conditions
Unit
min
max
I
I
I
I
Run Mode Current
notes 1,2; all On
Timing Controller On
notes 1,4
100
mA
mA
µA
DD1
Run Mode Analog Current
35
10
40
50
DDA1
DD2
(pin V
)
DDA
HALT Mode Current
100
100
HALT Mode Analog Current
notes 1,4
µA
DDA2
(pin V
)
DDA
Notes:
1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor.
The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode.
2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to V , HSYNC is driven by a 15625Hz clock.
SS
All peripherals working including Display.
3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to V , HSYNC is driven by a 15625Hz clock.
SS
The TDSRAM interface and the Slicers are working; the Display controller is not working.
4. VSYNC and HSYNC tied to V . External CLOCK pin (OSCIN) is hold low. All peripherals are disabled.
SS
EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode)
(VDD= 5V +/-10%; T = 0 to 70°C; unless otherwise specified))
A
Conditions
INTCLK=24 MHz.
TpC+12
Value
min
Unit
Symbol
Parameter
max
T
T
low level pulse width
high level pulse width
95
95
ns
ns
wLR
wHR
TpC+12
TpC is the INTCLK clock period.
168/178
ST92185 - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
SPI TIMING TABLE
(VDD= 5V +/-10%; T = 0 to 70°C; Cload= 50pF)
A
Value
Symbol
Parameter
Condition
Unit
min
max
T
T
T
T
T
T
Input Data Set-up Time
Input Data Hold Time
SCK to Output Data Valid
Output Data Hold Time
SCK Low Pulse Width
SCK High Pulse Width
tbd
ns
ns
ns
ns
ns
ns
sDI
(1)
OSCIN/2 as internal Clock
1INTCLK +100ns
hDI
tbd
dOV
hDO
wSKL
wSKH
tbd
tbd
tbd
(1) TpC is the OSCIN clock period; TpMC is the “Main Clock Frequency” period.
SKEW CORRECTOR TIMING TABLE
(VDD= 5V +/-10%, T = 0 to 70°C, unless otherwise specified)
A
max
Value
Symbol
Parameter
Conditions
Unit
T
Jitter on RGB output
36 MHz Skew corrector clock frequency
5*
ns
jskw
(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope
of 100 fields
169/178
ST92185 - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
OSD DAC CHARACTERISTICS (ROM DEVICES ONLY)
(VDD= 5V +/-10%, T = 0 to 70°C, unless otherwise specified).
A
Value
typical
500
Symbol
Parameter
Output impedance: FB,R,G,B
Output voltage: FB,R,G,B
Conditions
Unit
min
max
300
700
Ohm
Cload= 20pF
RL = 100K
code= 111
code= 011
code= 000
FB= 1
1.000
0.450
0.025
2.7
1.250
0.500
0.080
3.4
V
V
V
V
V
%
2.4
0
FB= 0
0.025
0.080
+/-5
Global voltage accuracy
OSD DAC CHARACTERISTICS (EPROM AND OTP DEVICES ONLY)
(VDD= 5V +/-10%, T = 0 to 70°C, unless otherwise specified).
A
Value
typical
500
Symbol
Parameter
Conditions
Unit
min
max
Output impedance: FB,R,G,B
Output voltage: FB,R,G,B
300
700
Ohm
Cload= 20pF
RL = 100K
code= 111
code= 011
code= 000
FB= 1
1.100
0.600
0.200
1.400
0.800
0.350
V
V
V
V
V
%
V
-0.8
DD
FB= 0
0.400
+/-5
Global voltage accuracy
170/178
ST92185 - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE
(VDD= 5V +/-10%; T = 0 to 70°C; unless otherwise specified
A
Value
OSCIN divide by
OSCIN divide
by 1; min/max
Symbol
Parameter
Pulse Width
Unit
2;min/max
min
max
1.5
T
T
T
T
ns
ns
low
high
ext
str
INTCLK
Pulse Distance
78+1
INTCLK
Period/fast Mode
Start Conversion Delay
µs
0.5
1.5
INTCLK
Core Clock issued by Timing Controller
T
T
T
T
Pulse Width
ns
ns
µs
ns
low
high
ext
str
Pulse Distance
Period/fast Mode
Start Conversion Delay
A/D CONVERTER. ANALOG PARAMETERS TABLE
(VDD= 5V +/-10%; T = 0 to 70°C; unless otherwise specified))
A
Value
min
Unit
Parameter
typ (*)
Note
max
(**)
V
Analog Input Range
V
V
DD
SS
Conversion Time Fast/Slow
78/138
INTCLK
INTCLK
µs
(1,2)
(1)
Sample Time Fast/Slow
Power-up Time
51.5/87.5
60
Resolution
8
3
4
2
bits
Differential Non Linearity
Integral Non Linearity
Absolute Accuracy
Input Resistance
5
5
3
LSBs
LSBs
LSBs
Kohm
pF
(4)
(4)
(4)
(3)
1.5
Hold Capacitance
1.92
Notes: (*) The values are expected at 25 Celsius degrees with V = 5V
DD
(**) 'LSBs' , as used here, as a value of V /256
DD
(1) @ 24 MHz external clock
(2) including Sample time
(3) it must be considered as the on-chip series resistance before the sampling capacitor
(4) DNL ERROR= max {[V(i) -V(i-1)] / LSB-1}
INL ERROR= max {[V(i) -V(0)] / LSB-i}
ABSOLUTE ACCURACY= overall max conversion error
171/178
ST92185 - GENERAL INFORMATION
9 GENERAL INFORMATION
9.1 PACKAGE MECHANICAL DATA
Figure 105. 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width
mm
inches
Dim.
A
Min Typ Max Min Typ Max
6.35
0.250
0.195
A1 0.38
0.015
A2 3.18
4.95 0.125
b
0.41
0.89
0.016
0.035
b2
C
D
E
0.20
0.38 0.008
53.21 1.980
0.015
2.095
50.29
15.01
0.591
E1 12.32
14.73 0.485
0.580
e
1.78
0.070
0.600
eA
eB
15.24
17.78
0.700
0.200
L
2.92
5.08 0.115
PDIP56S
Number of Pins
N
56
Figure 106. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width
mm
Min Typ Max Min Typ Max
5.08 0.200
inches
Dim.
A
A1 0.51
0.020
A2 3.05 3.81 4.57 0.120 0.150 0.180
b
b2
C
0.46 0.56
1.02 1.14
0.018 0.022
0.040 0.045
0.23 0.25 0.38 0.009 0.010 0.015
36.58 36.83 37.08 1.440 1.450 1.460
D
E
15.24
16.00 0.600
0.630
E1 12.70 13.72 14.48 0.500 0.540 0.570
e
1.78
0.070
0.600
eA
15.24
eB
18.54
0.730
0.060
eC 0.00
1.52 0.000
PDIP42S
L
2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N
42
172/178
ST92185 - GENERAL INFORMATION
PACKAGE MECHANICAL DATA (Cont’d)
Figure 107. 64-Pin Thin Quad Flat Package
mm
inches
Dim
Min Typ Max Min Typ Max
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
B
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
D
16.00
14.00
12.00
16.00
14.00
12.00
0.80
0.630
0.551
0.472
0.630
0.551
0.472
0.031
D1
D3
E
E1
E3
e
K
0° 3.5° 7°
0.45 0.60 0.75 0.018 0.024 0.030
L
L1
1.00
0.039
L1
L
Number of Pins
N
64
ND
16
NE
16
K
Figure 108. 56-Pin Shrink Ceramic Dual In Line Package, 600-mil Width
mm
inches
Dim.
Min Typ Max Min Typ Max
4.17 0.164
A
A1 0.76
0.030
B
0.38 0.46 0.56 0.015 0.018 0.022
B1 0.76 0.89 1.02 0.030 0.035 0.040
C
D
0.23 0.25 0.38 0.009 0.010 0.015
50.04 50.80 51.56 1.970 2.000 2.030
D1
48.01
1.890
E1 14.48 14.99 15.49 0.570 0.590 0.610
e
1.78
0.070
G
14.12 14.38 14.63 0.556 0.566 0.576
G1 18.69 18.95 19.20 0.736 0.746 0.756
G2 1.14 0.045
G3 11.05 11.30 11.56 0.435 0.445 0.455
G4 15.11 15.37 15.62 0.595 0.605 0.615
CDIP56SW
L
S
2.92
5.08 0.115
0.200
1.40
0.055
Number of Pins
N
56
173/178
ST92185 - GENERAL INFORMATION
Figure 109. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width
mm
Min Typ Max Min Typ Max
4.01 0.158
inches
Dim.
A
A1 0.76
0.030
B
0.38 0.46 0.56 0.015 0.018 0.022
B1 0.76 0.89 1.02 0.030 0.035 0.040
C
D
0.23 0.25 0.38 0.009 0.010 0.015
36.68 37.34 38.00 1.444 1.470 1.496
D1
35.56
1.400
E1 14.48 14.99 15.49 0.570 0.590 0.610
e
1.78
0.070
G
14.12 14.38 14.63 0.556 0.566 0.576
G1 18.69 18.95 19.20 0.736 0.746 0.756
G2 1.14 0.045
G3 11.05 11.30 11.56 0.435 0.445 0.455
G4 15.11 15.37 15.62 0.595 0.605 0.615
L
S
2.92
5.08 0.115
0.200
CDIP42SW
0.89
0.035
Number of Pins
N
42
Figure 110. 64-Pin Ceramic Quad Flat Package
mm
Min Typ Max Min Typ Max
3.27 0.129
inches
Dim
A
A1
B
0.50
0.020
0.30 0.35 0.45 0.012 0.014 0.018
0.13 0.15 0.23 0.005 0.006 0.009
16.65 17.20 17.75 0.656 0.677 0.699
C
D
D1 13.57 13.97 14.37 0.534 0.550 0.566
D3
e
12.00
0.80
0.472
0.031
G
12.70
0.500
G2
L
0.96
0.038
0.35 0.80
8.31
0.014 0.031
0.327
0
Number of Pins
64
N
CQFP064W
174/178
ST92185 - GENERAL INFORMATION
®
9.2 ECOPACK
In order to meet environmental requirements, ST
offers these devices in different grades of ECO-
tions, grade definitions and product status are
®
available at: www.st.com. ECOPACK is an ST
®
PACK packages, depending on their level of en-
trademark.
®
vironmental compliance. ECOPACK specifica-
9.3 ORDERING INFORMATION
Each device is available for production in a user
programmable version (OTP) as well as in factory
coded version (ROM). OTP devices are shipped to
customer with a default blank content FFh, while
ROM factory coded parts contain the code sent by
customer. The common EPROM versions for de-
bugging and prototyping features the maximum
memory size and peripherals of the family. Care
must be taken to only use resources available on
the target device.
9.3.1 Transfer Of Customer Code
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
must be set to FFh.
Figure 111. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE
/
XXX
DEVICE
Code name (defined by STMicroelectronics)
1= standard 0 to +70 °C
BN= Plastic SDIP56
BJ= Plastic SDIP42
T= Plastic TQFP64
ST92185B1
ST92185B2
ST92185B3
175/178
ST92185 - GENERAL INFORMATION
STMicroelectronics OPTION LIST
ST92185B
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM Code* : . . . . . . . . . . . . . . . . . .
*The ROM code name assigned by ST.
STMicroelectronics reference:
Device:
[ ] ST92185B1B1
[ ] ST92185B2B1
[ ] ST92185B3B1
Package : [ ] SDIP42
[ ] SDIP56
[ ] TQFP64
Temperature Range : 0 to 70 C
Software Development:
[ ] STMicroelectronics
[ ] Customer
[ ] External laboratory
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"
For marking, one line is possible with maximum 14 characters. Authorized characters are let-
ters, digits, '.', '-', '/' and spaces only.
Please consult your local ST Microelectronics sales office for other marking details if required.
Notes
:
OSD Code
: [ ] OSD File Filename [........ .OSD]
Quantity forecast : [..................] k units per year
For a period of : [..................] years
Preferred Production start dates : [../../..] (YY/MM/DD)
Date
Customer Signature :
176/178
ST92185 - REVISION HISTORY
10 REVISION HISTORY
Rev.
Main Changes
Date
1.0
First release on DMS
01/11/00
16K ROM added / TQFP64 added
1.1
p1, changed device summary; added one feature (pin-compatible with...) and changed one feature 03/15/00
(Pin-compatible EPROM, etc.). Added Option List.
Added Section 10 on page 177. Updated Figure 3 on page 10 and Figure 5 on page 12. Changed
Non-linearity values in A/D Converter Analog Parameters Table. Modified Table 9 on page 59.
Modified Section 4.2 on page 57.
11 Oct
2001
1.2
16 Jan
1.3
2.0
Modification of the absolute maximum rating of the Supply Voltage value in Section 8 on page 166.
2002
Updated dates.
09 Sep
2009
Added Doc ID and revision numbers.
177/178
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