ST9291N4_技术文档

ST9291

16-48K ROM HCMOS MCU WITH

ON SCREEN DISPLAY AND VOLTAGE TUNING OUTPUT

FUNCTIONAL DESCRIPTION

Register oriented 8/16 bit CORE with

RUN, WFI and HALT modes

Minimum instruction cycle time: 500ns

(12MHz internal)

16 to 48K bytes of ROM,

384/640 bytes of RAM,

224 generalpurpose registers available as RAM,

accumulatorsor index registers (Register File)

42-lead Shrink DIP package or

56-lead Shrink DIP package

Interrupt handler and Serial Peripheral Interface

as standard features

PSDIP42

31 (42 pin package) / 42 (56 pin package) fully

programmable I/O pins

34 character x15 rows software programmable

On Screen Display module with colour, italic, un-

derline, flash, transparent and fringe attribute

options

14-bit Voltage Synthesis for tuning reference

voltage.

8 8-bit PWM D/A outputswith repetition frequency

2 to 32kHz and 12V Open Drain Capability

16 bit Timer with 8 bit Prescaler, able to be used

as a Watchdog Timer

16-bit programmable Slice Timer with 8-bit pres-

caler

PSDIP56

3 channel Analog to Digital Converter, with inte-

gral sample and hold, fast 5.75µs conversion

time, 6-bit guaranteedresolution

(Ordering Information at the end of the Datasheet)

Rich Instruction Set and 14 Addressing modes

Division-by-Zero trap generation

DEVICE SUMMARY

Versatile Developmenttools, including assembler,

linker, C-compiler, archiver, graphic oriented de-

buggerand hardware emulators

Real Time Operating System

Windowed EPROM parts available for prototyp-

ing and pre-production developmentphases

Device

ROM

16K

24K

32K

48K

RAM

384

640

384

640

PACKAGE

PSDIP42/56

ST9291J2/N2

ST9291J3/N3

ST9291J4/N4

ST9291J5/N5

ST9291J6/N6

ST9291J7/N7

July 1995

1/20

ST9291

Figure 2. 56 Pin Shrink DIP Pinout

Figure 1. 42 Pin Shrink DIP Pinout

56

55

54

1

2

3

42

41

40

1

2

3

24

31

19

26

20

21

23

22

27

28

30

29

VR01740B

VR01740A

ST9291J Pin Description

ST9291N Pin Description

name

1

2

P2.1/INT5/AIN1

P2.0/INT7

RESET

P0.7

56

55

54

53

52

51

50

49

48

47

46

45

44

43

P2.2/INT0/AIN2

P2.3/INT6/VSO1

P2.4/NMI

P2.5/AIN3/VSO2

P1.0

1

2

3

4

5

6

7

8

P2.0/INT7

RESET

P0.7

42

41

40

39

38

37

36

35

P2.1/INT5/AIN1

P2.2/INT0/AIN2

P2.3/INT6/VSO1

P2.4/NMI

3

4

P0.6

5

P0.6

P0.5

P2.5/AIN3/VSO2

OSCIN

6

P0.5

N.C^.(1)

P1.1

P0.4

7

P1.2

P0.3

OSCOUT

8

P0.4

P1.3

P0.2

P4.7/PWM7/

EXTRG (AD)

9

P0.3

P1.4

10

11

12

13

14

P0.2

P1.5

9

P0.1

34

33

32

31

30

29

28

27

26

25

24

23

22

P4.6/PWM6

P4.5/PWM5

P4.4/PWM4

P4.3/PWM3

P4.2/PWM2

P4.1/PWM1

P4.0/PWM0

VSYNC

P0.1

P1.6

10

11

12

13

14

15

16

17

18

19

20

21

P0.0

N.C.⁽¹⁾

P1.7

P3.7

OSCIN

(2)

P3.6

V_DD

OSCOUT

N.C.⁽¹⁾

P4.7/PWM7/

EXTRG (AD)

P3.5

15

42

P3.4

16

17

18

19

20

21

22

23

24

25

26

27

28

P3.7

41

40

39

38

37

36

35

34

33

32

31

30

29

P4.6/PWM6

P4.5/PWM5

P4.4/PWM4

P4.3/PWM3

P4.2/PWM2

P4.1/PWM1

P4.0/PWM0

VSYNC

P3.3/B

P3.2/G

P3.1/R

P3.0/FB

P5.1/SDIO

P5.0/SCK/INT2

V_DD

P3.6

P3.5

HSYNC

P3.4

AV_DD

P3.3/B

P3.2/G

P3.1/R

P3.0/FB

P5.3

PLLR

PLLF

V_SS

HSYNC

Notes (N Package only) :

P5.2

AV_DD

1. N.C. means “not connected”

2. Pins 14 and 28 (V ) are internally connected

DD

P5.1/SDIO

P5.0/SCK/INT2

PLLR

PLLF

(2)

V_DD

V_SS

2/20

ST9291

GENERAL DESCRIPTION

The ST9291 is a ROM member of the ST9 family of

microcontrollers, completely developed and pro-

duced by SGS-THOMSON Microelectronics using

a proprietary n-well HCMOS process.

nals, timer inputs and outputs, analog inputs, ex-

ternal interrupts, OSD (On Screen Display) output

and serial or parallel I/O.

Three basic memory spaces are available to sup-

port this wide range of configurations: Program

Memory, Data Memory and the Register File,

which includes the control and status registers of

the on-chip peripherals.

The ROM parts are fully compatible with their

EPROM and OTP (One-Time Programmable) ver-

sions, which may be used for the prototyping and

pre-productionphases of development.

The nucleus of the ST9291 is the advanced ST9

Core which includes the Central Processing Unit

(CPU), the Register File, a 16-bit Timer/Watchdog

with 8-bit Prescaler, a Serial Peripheral Interface

supporting S-bus, I²C-bus and IM-bus Interface,

plus two 8-bit I/O ports. The Core has independent

memory and register buses allowing a high degree

of pipelining to add to the efficiency of the code

execution speed of the extensive instruction set.

The human interface is provided by the On Screen

Display module, this can produce up to 15 lines of

up to 34 characters from a ROM defined 128 char-

acter set. The 9x13 character can be modified by 4

different pixel sizes, with character rounding, and

formed into words with colour and format attrib-

utes.

A 14-bit VS (Voltage Synthesis) output using the

PWM (Pulse Width Modulation)/BRM (Bit Rate

Modulation)is present to generate tuning voltages

for low-mid range TV set applications. The tuning

voltage is output on one of two separate output

pins.

The powerful I/O capabilities demanded by micro-

controller applications are fulfilled by the ST9291

with up to 32/42 I/O lines dedicated to digital In-

put/Output. These lines are grouped into up to six

I/O Ports and can be configured on a bit basis un-

der software control to provide timing, status sig-

A 16-bit Slice Timer with an 8-bit Prescaler is also

present.

Figure 3. ST9291 Block Diagram

16-Bit TIMER/WATCHDOG+SPI

16 k / 48 k Bytes

384 / 640 Bytes

RAM

256 Bytes

REGISTER FILE

SLICE

TIMER

VOLTAGE

SYNTHESIS

ROM or EPROM ⁽¹⁾

CPU

MEMORY BUS ( Address & Data )

REGISTER BUS ( Address & Data )

I/O PORT 4

P.W.M.

A / D

Converter

I/O PORT 5

( SPI )

I/O PORT 2

( Analog Inputs )

On Screen

Display

I/O PORT

3

I/O PORT 0

8

D / A

Outputs

Converter

PLL

VSYNC

HSYNC

7

8

6

2

AV_DD

Note : 42 SDIP shown

VR01995E

PLLR

PLLF

Note 1. EPROM version only

3/20

ST9291

GENERAL DESCRIPTION (Continued)

The control of TV or Satellite receiver setting can

be done by up to eight 8-bit PWM outputs, with a

frequency maximum of 23,437Hz at 8-bit resolu-

tion (INTCLK = 12MHz). Low resolutions with

higher frequency operation can be programmed.

(24MHz maximum), or an external source to the

on-chip clock oscillator and buffer. OSCIN is thein-

put of the oscillator inverter and internal clock gen-

erator; OSCOUT is the output of the oscillator

inverter.

In additionthereis a3 channelAnalog to DigitalCon-

verterwith integralsample andhold,fast5.75µscon-

version time and 6-bit guaranteedresolution.

AV_DD. Analog V_DDof PLL. This pin must be tied to

V_DDexternally to the ST9291.

V_DD. Main Power Supply Voltage(5V±10%)

V_SS. Digital Circuit Ground.

PIN DESCRIPTION

P0.0-P0.7, P2.0-P2.5, P3.0-P3.7, P4.0-P4.7,

P5.0-P5.1 (J suffix)

VSYNC. Vertical Sync. Vertical video synchronisa-

tion inputto OSD. Positive or negativepolarity.

P0.0-P0.7, P1.0-P1.7, P2.0-P2.5, P3.0-P3.7,

P4.0-P4.7, P5.0-P5.3 (N suffix) I/O Port Lines (In-

put/Output,TTL or CMOS compatible). 32/42 lines

grouped into I/O ports, bit programmable under

program controlas generalpurposeI/O oras Alter-

nate functions (see next section).

HSYNC. Horizontal Sync. Horizontal video syn-

chronisationinput to OSD. Positive or negativepo-

larity.

PLLF. PLL Filter input. Filter input for the OSD for

PLL feed-back.

P4.0 - P4.7 are high voltage (12V) open drain out-

puts. The voltage in open drain output mode for all

PLLR. PLL Resistor connection pin. For resistor

connection to select the PLL gain adjust.

other I/O bits must not exceed V_DD

.

RESET. Reset (input, active low). The ST9 is initial-

ised bythe Reset signal.With thedeactivationof RE-

SET, program execution begins from the Program

memory location pointed to by the vector contained

in program memory locations 00h and 01h.

I/O Port Alternate Functions.

Each pin of the I/O ports of the ST9291 may as-

sume software programmable Alternative Func-

tions as shown in the Pin Configuration Drawings.

Table 1 shows the Functions allocated to each I/O

Port pin.

OSCIN, OSCOUT. Oscillator (input and output).

These pins connect a parallel-resonant crystal

4/20

ST9291

PIN DESCRIPTION (Continued)

Table 1.ST9291 I/O Port Alternative Function Summary

I/O PORT

Pin Assignment

Name

Function

Alternate Function

Port.bit

P0.0

9291J

10

9

9291N

12

11

10

9

I/O

I

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P3.0

P3.1

P3.2

P3.3

8

7

6

8

5

6

4

5

3

4

-

52

51

50

49

48

47

46

45

2

-

INT7

External Interrupt 7 with Schmitt Trigger

External Interrupt 5 with Schmitt Trigger

A/D Analog Input 1

1

INT5

AIN1

INT0

AIN2

INT6

VSO1

NMI

AIN3

VSO2

FB

I

42

41

40

39

38

18

17

16

15

1

I

1

I

External Interrupt 0

56

55

54

53

23

22

21

20

I

A/D Analog Input 2

I

External Interrupt 6

O

Voltage Synthesis Output 1

Non-Maskable Interrupt

I

A/D Analog Input 3

O

Voltage Synthesis Output 2

Fast Blanking OSD output

Red Video Colour OSD output

Green Video Colour OSD output

Blue Video Colour OSD output

O

R

O

G

O

B

O

5/20

ST9291

PIN DESCRIPTION (Continued)

Table 1. ST9291 I/O Port Alternative Function Summary (Continued)

I/O PORT

Pin Assignment

9291J 9291N

14 19

Name

Function

Alternate Function

Port.bit

P3.4

I/O

O

P3.5

P3.6

P3.7

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

P5.0

P5.1

P5.2

P5.3

Notes.

13

12

-

18

17

16

35

36

37

38

39

40

41

42

27

26

25

24

PWM0

PWM Output 0

28

29

30

31

32

33

34

35

20

19

-

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

EXTRG

SCK

O

PWM Output 1

PWM Output 2

PWM Output 3

PWM Output 4

PWM Output 5

PWM Output 6

PWM Output 7

A/D External Trigger

O

I

(1)

O

SPI Serial Clock

INT2

I

External Interrupt 2 ⁽¹⁾

SPI Serial Data Input/Output ⁽¹⁾

SDIO

I/O

-

1. The alternate functions of SCK/INT2 and SDIO may be swapped by using the SWAP Register Function.

2. Schmitt trigger options are available as a mask option for any input pin.

6/20

ST9291

1 CORE DESCRIPTION

1.1 CORE ARCHITECTURE

1.1.1 INTRODUCTION

1.1.2 ADDRESS SPACES

The Core or Central Processing Unit (CPU) of the

ST9 includes the 8 bit Arithmetic LogicUnit and the

16 bit Program Counter, System and User Stack

Pointers. The microcoded Instruction Set is highly

optimised for both byte (8 bit) and word (16 bit)

data, BCD and Boolean data types, with 14 ad-

dressing modes.

Three independent buses are controlled by the

Core, a 16 bit Memory bus, an 8 bit Register ad-

dressing bus and a 6 bit Interrupt/DMA bus con-

nected to the interrupt and DMA controllers in the

on-chip peripheralsandthe Core. This multiple bus

architecture allows a high degree of pipelining and

parallel operation, giving the ST9 its efficiency in

both numerical calculations and communication

with the on-chip peripherals.

The ST9 has three separate address spaces:

Register File: 240 8-bit registers plus up to 64

pages of 16 bytes each, located in the on-chip

peripherals.

-

Data memory with up to 64K (65536) bytes

-

Program memory with up to 64K (65536) bytes

The Data and Program memory spaces will be ad-

dressed in further detail in section 1.3.

1.1.2.1 Register File

The Register File consists of:

224 general purpose registers R0 to R223

-

16 systemregisters in the System Group

(R224 to R239).

I/O pages depending on the configuration of

-

the ST9, each containing up to 16 registers,

with paging facilities based on the top group

(R240 to R255).

Figure 1-4. Address Spaces

64K

DATA

PROGRAM

MEMORY

REGISTER

FILE

VA00430

7/20

ST9291

ADDRESS SPACES (Continued)

Figure 1-5. Register Grouping

Figure 1-6. Page Pointer Configuration

PAGE 63

UP TO

255

240

64 PAGES

F PAGED REGISTERS

239

E SYSTEM REGISTERS

224

PAGE 5

223

D

R255

PAGE 0

C

B

A

9

8

7

6

5

4

3

2

1

R240

PAGE POINTER

R224

224

GENERAL

PURPOSE

REGISTERS

15

0

R0

VA00432

VA00433

Figure 1-7. Addressing the Register File

REGISTER FILE

255

F

PAGE REGISTERS

240

239

224

223

E SYSTEM REGISTERS

D

C

B

A

9

GROUP D

R207

R195

(R0C3h)

(1100) (0011)

8

7

6

5

4

3

GROUP C

R195

R192

GROUP B

2

1

0

15

0

VR000118

8/20

ST9291

ADDRESS SPACES (Continued)

1.1.2.2 Addressing Registers

1.1.2.3 Input/Output Ports

All registersin the Register File and pages can be

specified by using a decimal, hex or binary ad-

dress, e.g. R231, RE7h or R11100111b is the

same register.

The Input/Output ports are located in two areas.

The port registers for Ports 0-5 are located at the

bottom of the System register group in locations

R224 to R229.

The registers can be referred to by their hexadeci-

mal group address, so that registers R0-R15 form

group 0, R160-R175 form group A and so on.

Each Port has three associated Control registers,

which determine the individual pin modes (I/O,

Open-Drain etc). These registers are located in

pages 2 and 3.

Working Register Addresses

The 8-bit register address is formed by 2 nibbles,

for example, for register R195 or RC3h or

R11000011, 1100 specifies the 13th group (i.e.

group C) and 0011 specifies the 3rd register in that

group.

Table 1-2. Register File Organization

Hex.

Address

Decimal

Address

Register File

Group

Working registers are addressed by supplying the

least significant nibble in the instruction and adding

it to the most significant nibble found in the Regis-

ter Pointer (R233). Working register addressing is

shown in Figure 1-7.

Function

Paged

Registers

F0-FF

E0-EF

240-255

224-239

Group F

Group E

System

Registers

System Registers

The 16 system registers at addresses R224 to

R239 form Group E.

The system registers are addressable using any of

the 4 register addressing modes and the most sig-

nificant nibble will, in all cases, be 14 (0Eh).

D0-DF

C0-CF

B0-BF

A0-AF

90-9F

80-8F

70-7F

60-6F

50-5F

40-4F

30-3F

20-2F

10-1F

00-0F

208-223

192-207

176-191

160-175

144-159

128-143

112-127

96-111

80-95

Group D

Group C

Group B

Group A

Group 9

Group 8

Group 7

Group 6

Group 5

Group 4

Group 3

Group 2

Group 1

Group 0

Paged Registers

There are a maximum of 64 pageseach containing

16 registers. These are addressed using the regis-

ter addressingmodes with the addition of the Page

Pointer register, R234. This register selects the

page to be addressed in group F and once set,

does not need to be changed if two or more regis-

ters on the same page are to be addressed in suc-

cession.

General

Purpose

Registers

Therefore if the Page Pointer, R234, is set to 5, the

instructions

spp 5

ld R242, r4

64-79

48-63

will load the contentsof working register r4 into the

third register (R242) of page 5.

32-47

These paged registers hold data and control regis-

ters related to the on-chipperipherals, and thus the

configuration depends upon the peripheral organi-

sation of each ST9 family member. i.e. pagesonly

exist if the peripheral exists.

16-31

00-15

Available pages are shown in Table 1-3.

9/20

ST9291

ADDRESS SPACES (Continued)

Table 1-3. Group F Peripheral Organization

Applicable for ST9291

HEX

00

02

03

0B

11

28

40

29

41

2A

42

3B

59

3E

62

DEC

R255

R254

R253

R252

R251

R250

R249

R248

R247

R246

R245

R244

R243

R242

R241

R240

RFF

RFE

RFD

RFC

RFB

RFA

RF9

RF8

RF7

RF6

RF5

RF4

RF3

RF2

RF1

RF0

SWAP RESER

RFF

RFE

RFD

RFC

RFB

RFA

RF9

RF8

RF7

RF6

RF5

RF4

RF3

RF2

RF1

RF0

VSO

RESER

SPI

PORT 3

RESER

WCR

RESER RESER

PORT 2

T/WD

RESER

OSD

RESER

CHAR

OSD

RESER

1 to 16 17 to 32

PWM

EXT INT PORT1 PORT 5

RESER RESER

OSD

CHAR

33 to 36

SLICE

PORT 0 PORT 4 TIMER

A/D

RESER

CONV

10/20

ST9291

1.1.3 SYSTEM REGISTERS

Following is the description of System Registers.

For PORT0 to PORT5 Registers, please refer to

I/O Port Chapter.

1.1.3.1 Central Interrupt Control Register

This Register CICR is located in the system Regis-

ter Group at the address R230 (E6h). Please refer

to “INTERRUPT” and “DMA” chapters in order to

get the background of the ST9 interrupt philoso-

phy.

Figure 1-8. System Register

CICR R230 (E6h) System Read/Write

Central Interrupt Control Register

Reset Value : 1000 0111

R239 (EFh)

R238 (EEh)

R237 (EDh)

R236 (ECh)

R235 (EBh)

R234 (EAh)

R233 (E9h)

R232 (E8h)

R231 (E7h)

R230 (E6h)

R229 (E5h)

R228 (E4h)

R227 (E3h)

R226 (E2h)

R225 (E1h)

R224 (E0h)

SYS. STACK POINTER LOW

SYS. STACK POINTER HIGH

USER STACK POINTER LOW

USER STACK POINTER HIGH

MODE REGISTER

PAGE POINTER

REGISTER POINTER 1

REGISTER POINTER 0

FLAGS

7

0

GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0

b7 = GCEN: Global Counter Enable. This bit is the

Global Counter Enableof the Multifunction Timers.

The GCEN bit is ANDed with the CE (Counter En-

able) bit of the Timer Control Register (explained in

the Timer chapter) in order to enable the Timers

when both bits are set. This bit is set after the Re-

set cycle.

b6 = TLIP: Top Level Interrupt Pending. This bit is

automatically set when a Top Level Interrupt Re-

quest is recognized. This bit can also be set by

Software in order to simulate a Top Level Interrupt

Request.

CENTRAL INT. CNTL REG

PORT5

PORT4

b5 = TLI: Top Level Interrrupt bit. When this bit is

set, a Top Level interrupt request isacknowledged

depending on the IEN bit and the TLNM bit (in

Nested Interrupt Control Register). If the TLM bit is

reset the top level interrupt acknowledgement de-

pends on the TLNM alone.

PORT3

PORT2

PORT1

PORT0

b4 = IEN: Enable Interrupt. This bit, (when set), al-

lows interrupts to be accepted. When reset no in-

terrupts other than the NMI can be acknowledged.

It is cleared by interrupt acknowledgementfor con-

current mode and set by interrupt return (iret). It

can be managed by hardware and software (ei

and di instruction).

b3 = IAM: Interrupt Arbitration Mode. This bit cov-

ers the selection of the two arbitration modes, the

Concurrent Mode being indicated by the value “0”

and the Fully Automatic Nested Mode by the value

“1”. This bit is under software control.

b2-b0 = CPL2-CPL0: Current Priority Level. These

three bits record the priority level of the interrupt

presently under service (i.e. the Current Priority

Level, CPL). For these priority levels 000 is the

highest priority and 111 is the lowest priority. The

CPL bits can be set by hardware or software and

give the referenceby which following interrupts are

either left pending or able to interrupt the current

interrupt. When the present interrupt is replaced by

one of a greaterpriority, the current priority value is

automatically stored until required.

11/20

ST9291

SYSTEM REGISTERS (Continued)

1.1.3.2 Flag Register

b5 = S: Sign Flag. The Sign flag is affected by the

same instructions as the Zero flag.

The Flag Register contains 8 flags indicating the

statusof theST9. During an interrupt theflag register

is automatically stored in the system stack area and

recalled at the end of the interrupt service routine so

that the ST9 is returned to the original status. This

occurs for all interrupts and, when operating in the

nested mode, up to seven versions of the flag regis-

ter may be stored.

The Sign flag is set when bit 7 (for byte operation)

or bit 15(for word operation)of the register usedas

an accumulator is one.

b4 = V: Overflow Flag. The Overflow flag is af-

fected by the same instructions as the Zero and

Sign flags.

When set, the Overflow flag indicates that a two’s-

complementnumber, in a result register, is in error,

since it has exceeded the largest (or is less than

the smallest), number that can be represented in

twos-complement notation.

FLAGR R231 (E7h) System Read/Write

Flag Register

Reset value: undefined

b3 = DA: Decimal Adjust Flag. The Decimal Adjust

flag is used for BCD arithmetic. Since the algorithm

for correcting BCD operations is different for addi-

tion and subtraction, this flag is used to specify

which type of instruction was executedlast, so that

the subsequentDecimal Adjust (da) operation can

perform its function correctly.

7

0

C

Z

S

V

DA

H

UF

DP

b7 = C: Carry Flag. The carry flag C is affected by

the following instructions:

Addition (add, addw, adc, adcw),

Subtraction (sub, subw, sbc, sbcw),

Compare (cp, cpw),

The Decimal Adjust flag cannot normally be used

as a test condition by the programmer.

b2 = H: Half Carry Flag. The Half Carry flag indi-

cates a carry out of (or a borrow into) bit 3, as the

result of adding or subtractingtwo 8-bit bytes, each

representingtwo BCD digits. The Half Carry flag is

used by the Decimal Adjust (da) instruction to con-

vert the binary result of a previous addition or sub-

traction into the correct BCD result.

Shift Right Arithmetic (sra, sraw),

Rotate (rrc, rrcw, rlc, rlcw, ror, rol),

Decimal Adjust (da),

Multiply and Divide (mul, div, divws).

When set, it generally indicates a carry out of the

most significant bit position of the register being

used as an accumulator(bit 7 for byte andbit 15 for

word operations).

Like the Decimal Adjust flag, this flag is not nor-

mally accessed by the user.

The carry flag can be set by the Set Carry Flag (scf)

instruction, cleared bythe Reset Carry Flag (rcf) in-

struction, and complemented (changed to “0” if “1”,

andvice versa) bythe ComplementCarryFlag (ccf)

instruction.

b1 = UF: User Flag. Bit 1 in the flag register (UF) is

available to the user, but it must be set or cleared

by an instruction.

b0 = DP: Data/Program Memory Flag. This bit in

the flag register indicates which memory area is

addressed. Its value is affected by the Set Data

Memory (sdm) and Set Program Memory (spm) in-

structions.

b6 = Z: Zero Flag. The Zero flag is affected by the

following instructions:

Addition (add, addw, adc, adcw),

Subtraction (sub, subw, sbc, sbcw),

Compare (cp, cpw),

Shift Right Arithmetic (sra, sraw),

Rotate (rrc, rrcw, rlc, rlcw, ror, rol),

Decimal Adjust (da),

Multiply and Divide (mul, div, divws),

Logical (and, andw, or, orw, xor, xorw,

cpl),

If the bit is set, the ST9 addresses the Data Mem-

ory Area; when the bit is cleared, the ST9 ad-

dresses the Program Memory Area. By reading

this bit, the user can verify in which memory area

the processor is working. The user writes this bit

with the sdm or spm instructions.

Increment and Decrement (inc, incw, dec,

decw),

Test (tm, tmw, tcm, tcmw, btset).

In most cases, the Zero flag is set when the register

being used as an accumulator register is zero, follow-

ing one of the above operations.

12/20

ST9291

SYSTEM REGISTERS (Continued)

1.1.3.3 Register Pointing Techniques

REGISTER POINTER 1

Two registers, R232 and R233, within the system

register group, are available for register pointing.

R232 and R233 may be used togetheras a single

pointer for a 16 register working space or sepa-

rately for two 8 register spaces, in which case

R232 becomesRegister Pointer 0 (RP0) andR233

becomes Register Pointer 1 (RP1).

RP1 R233 (E9h) System Read/Write

Register Pointer 1

Reset Value : undefined

7

0

RG7 RG6 RG5 RG4 RG3 RPS D1

D0

The instructions srp, srp0 and srp1 (the Set

Register Pointer instructions) automatically inform

the ST9 whetherthe RegisterFile isto operatewith

a single 16-register group or two 8-register groups.

The srp0 and srp1 instructions automatically set

the twin 8-register group mode while the srp in-

struction sets the single 16-register group mode.

There is no limitation on the order or positions of

these chosen register groups other than they must

be on 8 or 16 register boundaries.

This register is used only with double register

pointing mode; otherwise, using single register

pointingmode, the RP1R register has to be consid-

ered as reserved and not usable as a general pur-

pose register.

b7-b3 =RG7-RG3: Register Groupnumber. These

bits contain the number (from 0 to 31) of the group

of 8 working registers indicated in the instructions

srp1. Bit 7 is the MSB.

b2 = RPS: Register Pointer Selector. This bit is

automatically set by the instructions srp0 and

srp1 to indicate that a double register pointing

mode is used. Otherwise the instruction srp reset

the RPS bit to zero to indicate that a single register

pointing mode is used.

The addressing of working registers involves use of

the Register Pointer value plus an offsetvalue given

by the numberof the addressedworking register.

When addressing a register, the most significant

nibble (bits 4-7) gives the group address and the

least significant nibble (bits 0-3) gives the register

within that group.

b1,b0 = D1,D0: These bits are hardware fixed to

zero and are not affected by any writing instruction

trying to modify their value.

REGISTER POINTER 0

Note. If working in twin 8-register group mode but

only using srp0 (i.e. only using one 8-register

group) the unused register (R233) is to be consid-

ered as reserved and not usable as a general pur-

pose register.

RP0 R232 (E8h) System Read/Write

Register Pointer 0

Reset Value : undefined

7

0

The group of registers immediately below the sys-

tem registers (i.e. group D, R208-R223) can only

be accessed via the Register Pointers. To address

group D then, it is necessary to set the Register

Pointer to group D and then use the addressing

procedure for working registers. The programmer

is required to remember that the group D should be

used as a stacking area. This point is also covered

in the Stack Pointers paragraph.

RG7 RG6 RG5 RG4 RG3 RPS D1

D0

b7-b3 = RG7-RG3:Register Groupnumber. These

bits contain the number (from 0 to 31) of the group

of working registers indicated in the instructions

srp0 or srp. When using a 16-register group, a

number between 0 and 31 must be used in the srp

instruction indicatingone of the two adjacent8-reg-

ister group of working registers used. RG7 is the

MSB.

b2 = RPS: Register Pointer Selector. This bit is set

by the instructionssrp0 and srp1 to indicatethat a

double register pointing mode is used. Otherwise,

the instruction srp resetstheRPS bitto zero to indi-

cate that a single register pointing mode is used.

b1,b0 = D1,D0: These bits arefixed by hardware to

zero and are not affected by any writing instruction

trying to modify their value.

13/20

ST9291

SYSTEM REGISTERS (Continued)

EXAMPLES

Using the Twin 8-Register Group

Using the Single 16 Register Group

When working in the twin working group mode, the

registers pointed by Register Pointer0 (RP0R), are

referred as r0-r7 and those pointed by Register

Pointer1 (RP1R), are referred to as r8-r15, regard-

less of their absolute addresses. In this mode,

when operating with the first 8 working registers

(i.e. r0 - r7) the working register number acts as an

offset which is added to the value in Register

Pointer 0.

When the system is operating in the single 16-reg-

ister group mode, the registers are referred to as

r0-r15. In this mode, the offset value (i.e. the num-

ber of the working register referred to) is supplied

in theaddress (preceded by a small r, e.g. r5) and

is added to the Register Pointer 0 value to give the

absolute address.

For example, if the Register Pointer contains the

value 70h, then working register r7 would have the

absolute address, R77h.

So if Register Pointer 0 contains the value 96, then

working register 0 has the absolute address 96,

working register 5 has the absolute address 101,

and so on. The second group of working registers,

r8-r15, hasthe offset values 0 to 7 respectively(i.e.

r8 has the offset value 0, r9 has the offset value 1,

and so on), this offset value being added to the

value in Register Pointer 1.

In this mode, the single 16-registers group will al-

ways start from the lowest even number equal or

lower to the number given in the instruction.

Example: srp #3 is equivalent to srp #2.

For example, given that the value in Register

Pointer 1 is 32, then working register 12 supplies

an offset value of 4 (given by 12 minus 8) to the

value in Register Pointer 1 to give an absolute ad-

dress of 36.

Figure 1-9. Single 16 Register pointing Mode

Figure 1-10. Double Register pointing Mode

255

GROUP F

240

239

240

239

REGISTER POINTER 1

GROUP E

REGISTER POINTER 0

224

GROUP 8

r7

r0

r15

WORKING REGISTER

WORKING

GROUP 4

REGISTER

r15

r8

r0

GROUP 3

0

VA00098

0

VA00097

14/20

ST9291

SYSTEM REGISTERS (Continued)

1.1.3.5 Mode Registers

1.1.3.4 Page Configuration

This register MODER is located in the System

Register Group at the address 235.

The pages are available to be used for the storage

of control information (such as interrupt vector

pointers) relevant to particular peripherals. There

are up to 64 pages (each with 16 registers) based

on registers R240-R255. These paged registers

are addressable via the page pointer register

(PPR), which is system register R234.

Using this register it is possible:

to select either internal or external System and

User Stack area,

-

to manage the clock frequency

-

To address a paged register the page pointer regis-

ter (R234) must be loaded with the relevant page

numberusing thespp instruction(Set PagePointer)

and subsequently any address from the top (F)

group (R240-R255)will be referred to that page.

to enable the Bus request and Wait signals

when interfacing external memory.

MODER R235 (EBh) System Read/Write

Mode Register

Reset value : 1110 0000

For example if register 23 contains the value 44,

the following sequence loads the third register

R242 on page 5 with the value 44.

7

0

spp 5

SSP USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP

ld R242, R23

b7 = SSP: System Stack Pointer. This bit selects

internal (in the Register File) or external (in the ex-

ternal Data Memory) System Stack area, logical

“1” for internal, and logical “0” for external. After

Reset the value of this bit is “1”.

PPR R234 (EAh) System Read/Write

Page Pointer Register

Reset value : undefined

7

0

b6 = USP: User Stack Pointer. Same as bit 7 for

the User Stack Pointer;

PP7 PP6 PP5 PP4 PP3 PP2 D1

D0

b5 =DIV2: OSCINClock Divided by 2. This bit con-

trols the divide by 2 circuit which operates on the

OSCIN Clock. A logical “1” value means that the

OSCIN clock is internally divided by 2, and a logical

“0” value means that no division of the OSCIN

Clock occurs.

b7-b2 = PP7-PP2: Page Pointer. These bits con-

tain the number (between 0 to 63) of the page cho-

sen by the instructionssp (Set Page Pointer). PP7

is the MSB of the page address. Once the page

pointer has been set, there is no need to refresh it

unless a different page is required.

b4-b2 = PRS2-PRS0: ST9 CPUCLK Prescaler.

These bits load the prescaling module of the inter-

nal clock (INTCLK). The prescaling value selects

the frequency of the ST9 clock, which can be di-

vided by 1 to 8. See Clock chapter for more infor-

mation.

b1-b0 = D1,D0: These bits are fixedby hardwareto

zero and are not affected by any writing instruction

trying to modify their value.

PAGE 0 containsthe control registers of:

the external interrupt

-

b1 = BRQEN: Bus Request Enable. This bit must

be held to “0”.

the watchdog timer

-

b0 = HIMP: High Impedance Enable. This bit must

be held to “0”.

the wait logic states

-

the serial peripheral interface (SPI)

15/20

ST9291

SYSTEM REGISTERS (Continued)

1.1.3.6 Stack Pointers

The System Stack area and The System Stack

Pointer

There are two separate, double register stack

pointers available (named System Stack Pointer

and User Stack Pointer), both of which can ad-

dress registers or memory.

The System Stack area is used for the storage of

temporarily suspended system and/or control reg-

isters, i.e. the Flag register and the Program

counter, while interrupts are being serviced. For

subroutine execution only the Program Counter

needs to be saved in the System stack area.

The stack pointers pointto thebottom of the stacks

which are filled using the push commands and

emptied using the pop commands. The stack

pointer is automatically pre-decremented when

data is “pushed in” and post-incremented when

data is “popped out”.

There are two situations when this occurs automat-

ically, one being when an interrupt occurs and the

other when the instruction call subroutine is used.

When the system stack area is in theRegister File,

the stack pointer, which points to the bottom of the

stack, onlyneeds one byte for addressing, in which

case the System Stack Pointer Low Register

(R239) is sufficient for addressing purposes. As a

result the System Stack Pointer High Register

(R238) becomes redundant BUT must be consid-

ered as reserved (please refer also to “spurious”

memory access section). Clearly when the stack is

external a full word address is necessary and so

both registers are used to point, the even register

providing the MSB and the odd register providing

the LSB.

For example, the register address space is se-

lected for a stack and the corresponding stack

pointer register contains 220. When a byte of data

is “pushed”into the stack, the stack pointerregister

is decremented to 219, then the data byte is

“loaded” into register 219. Conversely, if a stack

pointer register contains 189 and a byte of data is

“popped” out, the byte of data is then extracted

fromthe stack and then the stack pointerregister is

incremented to 190.

The push and pop commands used to manage

the system stack area are made applicable to the

user stack by adding the suffix U, while to use a

stack instruction for a word a W is added.

The User Stack area and User Stack Pointer

The User Stack area is completely free from all in-

terference from automaticoperationsand so it pro-

vides a totally user controlled stacking area, that

area being in any part of the memory which is of a

RAM nature, or the first 14 groups of the general

Register File i.e. not in the System register or

Paged group.

For example push inserts data into the system

stack, but an added U indicates the user stack and

W means a word, so the instruction pushuw loads

a wordinto the bottomof the user stack.

If the User Stack Pointer register contains 223

(working in register space) the instruction pushuw

will decrement User Stack Pointer register to 222

and then load a word into register R222 and R221.

The User Stack Pointer consists of two registers,

R236 and R237, which are both used for address-

ing an external stack, while, when stacking in the

Register File, the User Stack Pointer High Regis-

ter, R236, becomes redundantbut must be consid-

ered as reserved.

When bytes (or words) are “popped out” the values

in those registers are left unchanged until fresh

data is loaded into those locations. Thus when

data is “popped” out from a stack area, the stack

content remains unchanged.

Note. Stacks must not be located in the pages or

the system register area.

16/20

ST9291

SYSTEM REGISTERS (Continued)

Stack location

223 into the User Stack Pointer Low Register. The

Programmer will not need to remember to set the

Register Pointer to 208 to gain access to registers

in the D-group, a problem outlined in Register

Pointing Techniques paragraph.

Stacks may be located anywhere in the first 14

groups of the Register File (internal stacks) or the

data memory (external stacks). It is not necessary

to set the data memory using the instruction sdm

as externalstack instructions automaticallyuse the

data memory.

Care is necessary when managing stacks as there

is no limit to stack sizes apart from the bottom of

any address space in which the stack is placed.

Consequently programmers are advised to use a

stack pointer value as high as possible, particularly

when using the Register File as a stacking area.

This will also benefit programmers who may locate

the stacks in group D using, for example the in-

struction ld R237, #223 which loads the value

Figure 1-11. System and/or User Stack in

Register Stack Mode

Figure 1-12. System and/or User Stack in

Memory Stack Mode

REGISTER FILE

R255

DATA MEMORY

SYSTEM REGISTERS

STACK POINTER L

STACK POINTER H

STACK POINTER L

STACK POINTER H

STACK

R0

VA00434

VA00435

USP R236 (ECh) System Read/Write

User Stack Pointer High Byte

Reset value: undefined

System Stack Pointer High Byte

Reset value: undefined

7

0

7

0

SSP15 SSP14 SSP13SSP12 SSP11SSP10 SSP9 SSP8

USP15USP14USP13USP12USP11USP10 USP9 USP8

SSP R239 (EFh) System Read/Write

System Stack Pointer Low Byte

Reset value: undefined

USP R237 (EDh) System Read/Write

User Stack Pointer Low Byte

Reset value: undefined

7

0

7

0

SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0

USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0

SSP R238 (EEh) System Read/Write

1.2 MEMORY

17/20

ST9291

1.2.1 INTRODUCTION

The memory of the ST9291 is functionallydivided

into two areas, the Register File and Memory. The

Memory may optionallybe divided into two spaces,

Program Memory for Program code and Data

Memory for Data.

peripherals and the external interrupt sources.

Each vector is contained in two consecutive byte

locations, the high order address held in the lower

(even) byte, the low order address held in the up-

per (odd) byte, forming the address which is

loaded into the Program Counter when selected

by the interrupt vector provided by the interrupt

source. This should point to the relevant Interrupt

Service routine provided by the User for immedi-

ate response to the interrupt.

The memory spaces are selected by the execution

of the SDM and SPM instructions (Set Data Mem-

ory and Set ProgramMemory, respectively).There

is no need to use either of these instructions again

until the memory area required is to be changed.

1.2.1.2 Data Space

1.2.1.1 Program Space

The ST9291 addresses the 640 bytes of on-chip

RAM memory from addresses FD80h to FFFFh in

both Program and Data Space. On-chip general

purpose Registers may be used as additional RAM

memory for minimum chip count systems.

The Program memory space of the ST9291 con-

sists of 48K bytes of on-chip ROM (addressedfrom

0 to BFFF) and 640 bytes of on-chip RAM (ad-

dressed from FD80h to FFFFh); refer to the mem-

ory map tables and drawing on the following page

for the memory mapping for other ROM sizes. The

first 256 memory locations from address 0 to

00FFh (hexadecimal) hold the Reset Vector, the

Top-Level (Pseudo Non-Maskable) interrupt, the

Divide by Zero Trap vector and, optionally, the

interrupt vector table for use with the on-chip

The Data Space is selected by the execution of

the SDM instruction. All subsequent memory ref-

erences will access the Data Space. When a

separate Data Space is not required, data may

stored in RAM or ROM memory within the Pro-

gram Space.

18/20

ST9291

MEMORY (Continued)

Table 1-4. ROM and RAM Address Configuration

ROM Size

(Bytes)

RAM Size

(Bytes)

Device Suffix

ROM Addresses

RAM Addresses

0 - 16383

dec

hex

dec

hex

dec

hex

dec

hex

dec

hex

dec

hex

64896 - 65279

FD80 - FEFF

64896 - 65535

FD80 - FFFF

64896 - 65299

FD80 - FEFF

64896 - 65535

FD80 - FFFF

64896 - 65535

FD80 - FFFF

64896 - 65555

FD80 - FFFF

dec

hex

dec

hex

dec

hex

dec

hex

dec

hex

dec

hex

J2/N2

16K

384

640

384

640

0000 - 3FFF

0 - 16383

J3/N3

J4/N4

J5/N5

J6/N6

J7/N7

16K

24K

32K

48K

0000 - 3FFF

0 - 24575

0000 - 5FFF

0 - 24575

0000 - 5FFF

0 - 32767

0000 - 7FFF

00000 - 49151

0000 - BFFF

Figure 1-13. ST9291 Memory Map

65535

64896

RAM

49151

48K

32767

32K

ROM

24575

16383

24K

ROM

16K

ROM

0

PROGRAM

DATA

INTERNAL RAM

MAPPED BOTH INTO PROGRAM AND DATA SPACE

VR01354I

19/20

ST9291

Notes:

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the

express written approval of SGS-THOMSON Microelectronics.

2

Purchase of I C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I C Patent.

2

Rights to use these components in an I C system is granted provided that the system conforms to the I C Standard

Specification as defined by Philips.

SGS-THOMSON Microelectronics Group of Companies

Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

20/20


型号：	ST9291N4
厂家：	ST
描述：	16-48K ROM HCMOS MCU WITH ON SCREEN DISPLAY AND VOLTAGE TUNINGOUTPUT 16-48K ROM HCMOS MCU与屏幕显示和电压TUNINGOUTPUT 输出元件
文件：	总20页 (文件大小：170K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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