ST92F120V9 [STMICROELECTRONICS]
8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD; 8月16号位闪存单片机系列RAM ， EEPROM和J1850 BLPD
| 型号： | ST92F120V9 |
| 厂家： | 
ST |
| 描述： | 8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD |
| 文件： | 总324页 (文件大小：3643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST92F120
8/16-BIT FLASH MCU FAMILY
WITH RAM, EEPROM AND J1850 BLPD
DATASHEET
■ Memories
– Internal Memory: up to 128 Kbytes Single
Voltage FLASH, 2 to 4 Kbytes RAM, 1K byte
TM
emulated EEPROM (E3PROM
)
– 224 general purpose registers (register file)
available as RAM, accumulators or index
pointers
PQFP100
■ Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN,
WFI, SLOW, HALT and STOP modes
■ Communication Interfaces
– 0-24 MHz Operation (internal Clock), 4.5 - 5.5
Volt voltage range
– 2 Serial Communication Interfaces with asyn-
chronous and synchronous capabilities. Soft-
ware Management and synchronous mode
supported
– PLL Clock Generator (3-5 MHz crystal)
– Min. instruction time: 83 ns (24 MHz int.
clock)
■ Interrupt Management
– 77 I/O pins
– Serial Peripheral Interface (SPI) with Selecta-
ble Master/Slave mode
– J1850 Byte Level Protocol Decoder (JBLPD)
(on J versions only)
– 4 external fast interrupts + 1 NMI
– Full I²C multiple Master/Slave Interface sup-
porting Access Bus
■ 8-bit Analog to Digital Converter allowing up
to 16 input channels
■ DMA Controller for reduced processor
– Up to 16 pins programmable as wake-up or
additional external interrupt with multi-level in-
terrupt handler
■ Timers
– 16-bit Timer with 8 bit Prescaler, able to be
used as a Watchdog Timer with a large range
of service time (HW/SW enabling through
dedicated pin)
overhead
■ Instruction Set
– Rich Instruction Set with 14 Addressing
Modes
– 16-bit Standard Timer that can be used to
generate a time base independent of PLL
Clock Generator
– Division-by-zero trap generation
■ Development Tools
– Two 16-bit independent Extended Function
Timers (EFTs) with Prescaler, 2 Input Cap-
tures and two Output Compares
– Versatile Development Tools, including As-
sembler, Linker, C-Compiler, Archiver,
Source Level Debugger, Hardware Emulators
and Real Time Operating System
– Two 16-bit Multifunction Timers, with Prescal-
er, 2 Input Captures and 2 Output Compares
DEVICE SUMMARY
Features
FLASH - bytes
RAM - bytes
ST92F120V9
ST92F120JV9
ST92F120V1
ST92F120JV1
60K
2K
128K
4K
E3PROM - bytes
Network Interface
Temp. Range
Packages
1K
--
J1850
--
o
J1850
o
o
o
-40 C to 105 C or -40 C to 85 C
PQFP100
Rev. 2.6
September 2002
1/324
9
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20
2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3 SINGLE VOLTAGE FLASH & EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.4 WRITE OPERATION EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.6 PROTECTION STRATEGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7 FLASH IN-SYSTEM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3 ST92F120 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 67
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.9 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.10 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.11 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . . . 81
6 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 DMA PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3 DMA TRANSACTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4 DMA CYCLE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.5 SWAP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.6 DMA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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Table of Contents
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.2 CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.3 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.6 RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.7 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8 EXTERNAL MEMORY INTERFACE (EXTMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.2 EXTERNAL MEMORY SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.3 EXTENDED FUNCTION TIMER (EFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.4 MULTIFUNCTION TIMER (MFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) . . . . . . . . . . . . 179
10.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
10.7 I2C BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
10.8 J1850 BYTE LEVEL PROTOCOL DECODER (JBLPD) . . . . . . . . . . . . . . . . . . . . . . . . . 238
10.9 EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) . . . . . . . . . . . . . . . . . . . 279
11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
12 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
13 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
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ST92F120 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92F120 microcontroller is developed and
manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The new-generation ST9 MCU
devices now also support low power consumption
and low voltage operation for power-efficient and
low-cost embedded systems.
ter File, which includes the control and status reg-
isters of the on-chip peripherals.
1.1.2 External Memory Interface
100-pin devices have a 16-bit external address
bus allowing them to address up to 64K bytes of
external memory.
1.1.3 Flash and E3PROM Memories
In the ST92F120, the embedded Flash memory
cell is used to implement emulated EEPROM ca-
pability for applications that require regular up-
dates of single-byte parameters.
1.1.4 On-chip Peripherals
1.1.1 ST9+ Core
Two 16-bit MultiFunction Timers, each with an 8
bit Prescaler and 12 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other system
timing functions by the usage of the two associat-
ed DMA channels for each timer.
The advanced Core consists of the Central
Processing Unit (CPU), the Register File, the Inter-
rupt and DMA controller, and the Memory Man-
agement Unit. The MMU allows a single linear ad-
dress space of up to 4 Mbytes.
Four independent buses are controlled by the
Core: a 16-bit memory bus, an 8-bit register data
bus, an 8-bit register address bus and a 6-bit inter-
rupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
core.
Two Extended Function Timers provide further
timing and signal generation capabilities.
A Standard Timer can be used to generate a sta-
ble time base independent from the PLL.
2
2
An I C interface provides fast I C and Access Bus
support.
This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.
The SPI is a synchronous serial interface for Mas-
ter and Slave device communication. It supports
single master and multimaster systems.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
A J1850 Byte Level Protocol Decoder is available
(on some devices only) for communicating with a
J1850 network.
In addition, there is an 16 channel Analog to Digital
Converters with integral sample and hold, fast
conversion time and 8-bit resolution.
Completing the device are two or one full duplex
Serial Communications Interfaces with an integral
generator, asynchronous and synchronous capa-
bility (fully programmable format) and associated
address/wake-up option, plus two DMA channels.
The powerful I/O capabilities demanded by micro-
controller applications are fulfilled by the
ST92F120 with 77 I/O lines dedicated to digital In-
put/Output. These lines are grouped into up to ten
8-bit I/O Ports and can be configured on a bit basis
under software control to provide timing, status
signals, an address/data bus for interfacing to the
external memory, timer inputs and outputs, analog
inputs, external interrupts and serial or parallel I/O.
Two memory spaces are available to support this
wide range of configurations: a combined Pro-
gram/Data Memory Space and the internal Regis-
Finally, a programmable PLL Clock Generator al-
lows the usage of standard 3 to 5 MHz crystals to
obtain a large range of internal frequencies up to
24MHz. Low power Run (SLOW), Wait For Inter-
rupt, low power Wait For Interrupt, STOP and
HALT modes are also available.
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ST92F120 - GENERAL DESCRIPTION
Figure 1. ST92F120JV: Architectural Block Diagram
Ext. MEM.
ADDRESS
DATA
Port0
A[7:0]
D[7:0]
FLASH
60/128 Kbytes
EEPROM
1K byte
Ext. MEM.
ADDRESS
Port1
A[15:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:1]
P4[7:0]
P5[7:0]
P6[5:0]
P7[7:0]
P8[7:0]
P9[7:0]
RAM
2/4 Kbytes
AS
DS
RW
Fully
Prog.
I/Os
256 bytes
WAIT
Register File
NMI
RW
DS2
8/16 bit
CPU
J1850
JBLPD
(optional)
VPWI
VPWO
Interrupt
Management
INT[6:0]
WKUP[15:0]
SDAI
SDAO
SCLI
ST9 CORE
2
I C BUS
OSCIN
OSCOUT
SCLO
RESET
CLOCK2/8
CLOCK2
INTCLK
RCCU
WDOUT
HW0SW1
WDIN
WATCHDOG
SPI
MISO
MOSI
SCK
SS
STOUT
ST. TIMER
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
A0IN[7:0]
EXTRG
A/D CONV. 0
A/D CONV. 1
EF TIMER 0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
A1IN[7:0]
TXCLK0
RXCLK0
SIN0
EF TIMER 1
DCD0
SCI 0
TINPA0
TOUTA0
TINPB0
TOUTB0
SOUT0
CLKOUT0
RTS0
MF TIMER 0
MF TIMER 1
TXCLK1
RXCLK1
SIN1
TINPA1
TOUTA1
TINPB1
TOUTB1
DCD1
SCI 1 *
SOUT1
CLKOUT1
RTS1
All alternate functions (Italic characters) are mapped on Port2, Port3, Port4, Port5, Port6, Port7, Port8 and Port9
* Available on some versions only
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ST92F120 - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the begin-
ning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (RW), and
Data signals are valid for memory transfers.
P1[7:3], P3[3:1], P4[3:0], P6.1, P8[7:0], P9[7:0]
Additional I/O Port Lines available on PQFP100
versions only.
AV Analog V of the Analog to Digital Convert-
DD
DD
er (common for A/D 0 and A/D 1).
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a
write cycle, data out is valid at the leading edge of
DS. During a read cycle, Data In must be valid pri-
or to the trailing edge of DS. When the ST9 ac-
cesses on-chip memory, DS is held high during
the whole memory cycle.
AV Analog V of the Analog to Digital Convert-
er (common for A/D 0 and A/D 1).
SS
SS
V
Main Power Supply Voltage. Four pins are
DD
available. The pins are internally connected.
V
Digital Circuit Ground. Four pins are availa-
SS
ble. The pins are internally connected.
V
Power Supply Voltage for Flash test pur-
TEST
RESET. Reset (input, active low). The ST9 is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
poses. This pin is bonded and must be kept to 0 in
User mode.
V
3V regulator output (on future versions, i.e.
REG
ST92F124 and ST92F150).
1.2.1 Electromagnetic Compatibility (EMC)
To reduce the electromagnetic interference the fol-
lowing features have been implemented:
RW. Read/Write (output, 3-state). Read/Write de-
termines the direction of data transfer for external
memory transactions. RW is low when writing to
external memory, and high for all other transac-
tions.
– A low power oscillator is included with a control-
led gain to reduce EMI and the power consump-
tion in Halt mode.
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal, or
an external source to the on-chip clock oscillator
and buffer. OSCIN is the input of the oscillator in-
verter and internal clock generator; OSCOUT is
the output of the oscillator inverter.
– Four pairs of digital power supply pins (V
,
DD
V
) are located on each side of the package.
SS
– Digital and analog power supplies are complete-
ly separated.
– Digital power supplies for internal logic and I/O
ports are separated internally.
HW0SW1. When connected to V
pull-up resistor, the software watchdog option is
through a 1K
DD
– Internal decoupling capacitance is located be-
tween V and V
.
selected. When connected to V through a 1K
DD
SS
SS
pull-down resistor, the hardware watchdog option
is selected.
Note: Each pair of digital V /V pins should be
externally connected by a 10 µF chemical pulling
DD SS
capacitor and a 100 nF ceramic chip capacitor.
VPWO. This pin is the output line of the J1850 pe-
ripheral (JBLPD). It is available only on some de-
vices. On devices without JBLPD peripheral, this
pin must not be connected.
1.2.2 I/O Port Alternate Functions
Each pin of the I/O ports of the ST92F120 may as-
sume software programmable Alternate Functions
as shown in Section 1.3.
P0[7:0], P1[2:0] or P1[7:0](Input/Output, TTL or
CMOS compatible). 16 lines providing the external
memory interface for addressing 2K or 64 K bytes
of external memory.
1.2.3 Termination of Unused Pins
P0[7:0], P1[2:0], P2[7:0], P3[7:4], P4[7:4],
P5[7:0], P6[5:2,0], P7[7:0] I/O Port Lines (Input/
Output, TTL or CMOS compatible). I/O lines
grouped into I/O ports of 8 bits, bit programmable
under software control as general purpose I/O or
as alternate functions.
The ST9 device is implemented using CMOS tech-
nology; therefore unused pins must be properly
terminated in order to avoid application reliability
problems. In fact, as shown in Figure 2, the stand-
ard input circuitry is based on the CMOS inverter
structure.
6/324
9
ST92F120 - GENERAL DESCRIPTION
Figure 2. CMOS Basic Inverter
value, during a particular phase of the RESET rou-
tine there could be an undetermined status at the
input section.
V
DD
Usage of pull-ups and/or pull-downs is preferable
in place of direct connection to V or V . If pull-
DD
SS
up or pull-down resistors are used, inputs can be
forced for test purposes to a different value, and
outputs can be programmed to both digital levels
without generating high current drain due to the
conflict.
P
N
OUT
IN
Anyway, during system verification flow, attention
must be paid to reviewing the connection of each
pin, in order to avoid potential problems.
V
1.2.4 Avoidance of Pin Damage
SS
Although integrated circuit data sheets provide the
user with conservative limits and conditions in or-
der to prevent damage, sometimes it is useful for
the hardware system designer to know the internal
failure mechanisms: the risk of exposure to illegal
voltages and conditions can be reduced by smart
protection design.
When an input is kept at logic zero, the N-channel
transistor is off, while the P-channel is on and can
conduct. The opposite occurs when an input is
kept at logic one. CMOS transistors are essentially
linear devices with relatively broad switching
points. During commutation, the input passes
through midsupply, and there is a region of input
voltage values where both P and N-channel tran-
sistors are on. Since normally the transitions are
fast, there is a very short time in which a current
can flow: once the switching is completed there is
no longer current. This phenomenon explains why
the overall current depends on the switching rate:
the consumption is directly proportional to the
number of transistors inside the device which are
in the linear region during transitions, charging and
discharging internal capacitances.
It is not possible to classify and to predict all the
possible damage resulting from violating maxi-
mum ratings and conditions, due to the large
number of variables that come into play in defining
the failures: in fact, when an overvoltage condition
is applied, the effects on the device can vary sig-
nificantly depending on lot-to-lot process varia-
tions, operating temperature, external interfacing
of the ST9 with other devices, etc.
In the following sections, background technical in-
formation is given in order to help system design-
ers to reduce risk of damage to the ST9 device.
In order to avoid extra power supply current, it is
important to bias input pins properly when not
used. In fact, if the input impedance is very high,
pins can float, when not connected, either to a
midsupply level or can oscillate (injecting noise in
the device).
1.2.4.1 Electrostatic Discharge and Latchup
CMOS integrated circuits are generally sensitive
to exposure to high voltage static electricity, which
can induce permanent damage to the device: a
typical failure is the breakdown of thin oxides,
which causes high leakage current and sometimes
shorts.
Depending on the specific configuration of each
I/O pin on different ST9 devices, it can be more or
less critical to leave unused pins floating. For this
reason, on most pins, the configuration after RE-
SET enables an internal weak pull-up transistor in
order to avoid floating conditions. For other pins
this is intrinsically forbidden, like for the true open-
drain pins. In any case, the application software
must program the right state for unused pins to
avoid conflicts with external circuitry (whichever it
is: pull-up, pull-down, floating, etc.).
Latchup is another typical phenomenon occurring
in integrated circuits: unwanted turning on of para-
sitic bipolar structures, or silicon-controlled rectifi-
ers (SCR), may overheat and rapidly destroy the
device. These unintentional structures are com-
posed of P and N regions which work as emitters,
bases and collectors of parasitic bipolar transis-
tors: the bulk resistance of the silicon in the wells
and substrate act as resistors on the SCR struc-
The suggested method of terminating unused I/O
is to connect an external individual pull-up or pull-
down for each pin, even though initialization soft-
ware can force outputs to a specified and defined
ture. Applying voltages below V or above V
and when the level of current is able to generate a
,
SS
DD
7/324
9
ST92F120 - GENERAL DESCRIPTION
voltage drop across the SCR parasitic resistor, the
SCR may be turned on; to turn off the SCR it is
necessary to remove the power supply from the
device.
count, for those applications and systems where
ST9 pins are exposed to illegal voltages and high
current injections, the user is strongly recommend-
ed to implement hardware solutions which reduce
the risk of damage to the microcontroller: low-pass
filters and clamp diodes are usually sufficient in
preventing stress conditions.
The present ST9 design implements layout and
process solutions to decrease the effects of elec-
trostatic discharges (ESD) and latchup. Of course
it is not possible to test all devices, due to the de-
structive nature of the mechanism; in order to
guarantee product reliability, destructive tests are
carried out on groups of devices, according to
STMicroelectronics internal Quality Assurance
standards and recommendations.
The risk of having out-of-range voltages and cur-
rents is greater for those signals coming from out-
side the system, where noise effect or uncon-
trolled spikes could occur with higher probability
than for the internal signals; it must be underlined
that in some cases, adoption of filters or other ded-
icated interface circuitries might affect global mi-
crocontroller performance, inducing undesired tim-
ing delays, and impacting the global system
speed.
1.2.4.2 Protective Interface
Although ST9 input/output circuitry has been de-
signed taking ESD and Latchup problems into ac-
Figure 3. Digital Input/Output - Push-Pull
I/O CIRCUITRY
P
OUTPUT
BUFFER
PIN
N
EN
P
P
P
INPUT
BUFFER
N
N
EN
ESD PROTECTION
CIRCUITRY
PORT CIRCUITRY
8/324
1
ST92F120 - GENERAL DESCRIPTION
1.2.4.3 Internal Circuitry: Digital I/O pin
limit conditions, avoiding permanent damage to
the logic circuitry.
In Figure 3 a schematic representation of an ST9
pin able to operate either as an input or as an out-
put is shown. The circuitry implements a standard
input buffer and a push-pull configuration for the
output buffer. It is evident that although it is possi-
ble to disable the output buffer when the input sec-
tion is used, the MOS transistors of the buffer itself
can still affect the behaviour of the pin when ex-
posed to illegal conditions. In fact, the P-channel
transistor of the output buffer implements a direct
All I/O pins can generally be programmed to work
also as open-drain outputs, by simply writing in the
corresponding register of the I/O Port. The gate of
the P-channel of the output buffer is disabled: it is
important to highlight that physically the P-channel
transistor is still present, so the diode to V
DD
works. In some applications it can occur that the
voltage applied to the pin is higher than the V
DD
value (supposing the external line is kept high,
while the ST9 power supply is turned off): this con-
dition will inject current through the diode, risking
permanent damages to the device.
diode to V (P-diffusion of the drain connected to
DD
the pin and N-well connected to V ), while the N-
DD
channel of the output buffer implements a diode to
V
(P-substrate connected to VSS and N-diffu-
SS
In any case, programming I/O pins as open-drain
can help when several pins in the system are tied
to the same point: of course software must pay at-
tention to program only one of them as output at
any time, to avoid output driver contentions; it is
advisable to configure these pins as output open-
drain in order to reduce the risk of current conten-
tions.
sion of the drain connected to the pin). In parallel
to these diodes, dedicated circuitry is implemented
to protect the logic from ESD events (MOS, diodes
and input series resistor).
The most important characteristic of these extra
devices is that they must not disturb normal oper-
ating modes, while acting during exposure to over
Figure 4. Digital Input/Output - True Open Drain Output
I/OCIRCUITRY
OUTPUT
BUFFER
PIN
N
EN
P
P
INPUT
BUFFER
N
N
EN
ESD PROTECTION
CIRCUITRY
PORT CIRCUITRY
9/324
1
ST92F120 - GENERAL DESCRIPTION
In Figure 5 a true open-drain pin schematic is
1.2.4.4 Internal Circuitry: Analog Input pin
shown. In this case all paths to V
are removed
DD
Figure 5 shows the internal circuitry used for ana-
log input. It is substantially a digital I/O with an
added analog multiplexer for the A/D Converter in-
put signal selection.
(P-channel driver, ESD protection diode, internal
weak pull-up) in order to allow the system to turn
off the power supply of the microcontroller and
keep the voltage level at the pin high without in-
jecting current in the device. This is a typical con-
dition which can occur when several devices inter-
face a serial bus: if one device is not involved in
the communication, it can be disabled by turning
off its power supply to reduce the system current
consumption.
The presence of the multiplexer P-channel and N-
channel can affect the behaviour of the pin when
exposed to illegal voltage conditions. These tran-
sistors are controlled by a low noise logic, biased
through AV
and AV
including P-channel N-
DD
SS
well: it is important to always verify the input volt-
age value with respect to both analog power sup-
ply and digital power supply, in order to avoid un-
intended current injections which (if not limited)
could destroy the device.
When an illegal negative voltage level is applied to
the ST9 I/O pins (both versions, push-pull and true
open-drain output) the clamp diode is always
present and active (see ESD protection circuitry
and N-channel driver).
Figure 5. Digital Input/Output - Push-Pull Output - Analog Multiplexer Input
I/OCIRCUITRY
P
OUTPUT
PIN
BUFFER
N
EN
P
P
P
INPUT
BUFFER
N
N
EN
N
E
SD PROTECTION
CIRCUITRY
AVDD
P
PORT CIRCUITRY
10/324
9
ST92F120 - GENERAL DESCRIPTION
1.2.4.5 Power Supply and Ground
sitions (typical of electrostatic discharges). Other
paths are implemented through diodes: they limit
As already said for the I/O pins, in order to guaran-
tee ST9 compliancy with respect to Quality Assur-
ance recommendations concerning ESD and
Latchup, dedicated circuits are added to the differ-
ent power supply and ground pins (digital and an-
alog). These structures create preferred paths for
the high current injected during discharges, avoid-
ing damage to active logic and circuitry. It is impor-
tant for the system designer to take this added cir-
cuitry into account, which is not always transpar-
ent with respect to the relative level of voltages ap-
plied to the different power supply and ground
pins. Figure 6 shows schematically the protection
net implemented on ST9 devices, composed of di-
odes and other special structures.
the possibility of positively differentiating AV
DD
and V (i.e. AV
are valid for AV
> V ); similar considerations
DD
DD
SS
DD
and V
due to the back-to-
SS
back diode structure implemented between the
two pins. Anyway, it must be highlighted that, be-
cause V
and AV
are connected to the sub-
SS
SS
strate of the silicon die (even though in different ar-
eas of the die itself), they represent the reference
point from which all other voltages are measured,
and it is recommended to never differentiate AV
SS
from V
.
SS
Note: If more than one pair of pins for V
and
SS
V
is available on the device, they are connected
DD
internally and the protection net diagram remains
the same as shown in Figure 6.
The clamp structure between the V
and V
SS
DD
pins is designed to be active during very fast tran-
Figure 6. Power Supply and Ground Configuration
N
P
AV
AV
DD
V
V
V
SS
SS
TEST
DD
P
N
11/324
9
ST92F120 - GENERAL DESCRIPTION
Figure 7. ST92F120: Pin Configuration (Top-view PQFP100)
100 99 98 97 96 95 93 92 91 90 89 88 87 86 85 84 83 82 81
94
RXCLK1/P9.3
DCD1/P9.4
80
79
78
P8.6/A1IN1
P8.5/A1IN2
P8.4/A1IN3
1
2
3
RTS1/P9.5
CLOCK2/P9.6
4
P8.3/A1IN4
P8.2/A1IN5
77
76
75
74
73
72
5
P9.7
6
WAIT/WKUP5/P5.0
WKUP6/WDOUT/P5.1
SIN0/WKUP2/P5.2
WDIN/SOUT0/P5.3
TXCLK0/CLKOUT0/P5.4
RXCLK0/WKUP7/P5.5
DCD0/WKUP8/P5.6
WKUP9/RTS0/P5.7
ICAPA1/P4.0
P8.1/A1IN6/WKUP15
P8.0/A1IN7/WKUP14
VPWO
P6.5/WKUP10/INTCLK/VPWI
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
7
8
9
10
11
12
13
14
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
P4.1 15
OCMPA1/P4.2
16
17
18
19
20
21
V
ST92F120
DD
V
V
SS
SS
V
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6 22
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
23
24
25
26
27
28
29
30
DS
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
P1.7/A15
P1.6/A14
P1.5/A13
P1.4/A12
53
52
51
3132 33 34 35 36 3738 39 40 41 42 43 44 45 46 47 48 49 50
N.C. = Not connected (no physical bonding wire)
must be kept low in standard operating mode.
* V
TEST
**On future versions.
12/324
9
ST92F120 - GENERAL DESCRIPTION
Table 2. ST92F120 Primary Function Pins
Table 1. ST92F120 Power Supply Pins
Name
Function
Name
Function
18
42
65
93
17
41
64
92
82
83
AS
DS
Address Strobe
Data Strobe
56
55
32
94
95
Main Power Supply Voltage
( pins internally connected)
V
DD
SS
RW
Read/Write
OSCIN
OSCOUT
Oscillator Input
Oscillator Output
Digital Circuit Ground
RESET Reset to initialize the Microcontroller 96
Watchdog HW/SW enabling selec-
V
(pins internally connected)
HW0SW1
97
tion
AV
AV
Analog Circuit Supply Voltage
Analog Circuit Ground
J1850 JBLPD Output. On devices
without JBPLD peripheral, this pin
must not be connected.
DD
VPWO
73
SS
Must be kept low in standard operating
mode
V
44
TEST
3V Regulator output
(on future versions,
i.e. ST92F124 and ST92F150)
31
43
V
REG
Figure 8. Recommended Connections for V
REG
PQFP100
300 nF
300 nF
Note : For future compatibility with shrinked versions, the V
of 600 nF (total). Special care should be taken to minimize the distance between the ST9 microcontroller
and the capacitors.
pins should be connected to a minimum
REG
13/324
9
ST92F120 - GENERAL DESCRIPTION
1.3 I/O PORTS
Port 0 and Port 1 provide the external memory in-
terface. All the ports of the device can be pro-
grammed as Input/Output or in Input mode, com-
patible with TTL or CMOS levels (except where
Schmitt Trigger is present). Each bit can be pro-
grammed individually (Refer to the I/O ports chap-
ter).
the NMI and VPWI input function pins mapped on
Port 6 [5:4] (see Table 4).
All inputs which can be used for detecting interrupt
events have been configured with a “standard”
Schmitt Trigger, apart from, as already said, the
NMI pin which implements the “High Hysteresis”
version. In this way, all interrupt lines are guaran-
teed as “level sensitive”.
Internal Weak Pull-up
As shown in Table 3, not all input sections imple-
ment a Weak Pull-up. This means that the pull-up
must be connected externally when the pin is not
used or programmed as bidirectional.
Push-Pull/OD Output
The output buffer can be programmed as push-
pull or open-drain: attention must be paid to the
fact that the open-drain option corresponds only to
a disabling of P-channel MOS transistor of the
buffer itself: it is still present and physically con-
nected to the pin. Consequently it is not possible to
increase the output voltage on the pin over
TTL/CMOS Input
For all those port bits where no input schmitt trig-
ger is implemented, it is always possible to pro-
gram the input level as TTL or CMOS compatible
by programming the relevant PxC2.n control bit.
Refer I/O Ports Chapter to the section titled “Input/
Output Bit Configuration”.
V
+0.3 Volt, to avoid direct junction biasing.
DD
Pure Open-Drain Output
The user can increase the voltage on an I/O pin
Schmitt Trigger Input
over V +0.3 Volt where the P-channel MOS tran-
DD
sistor is physically absent: this is allowed on all
“Pure Open Drain” pins. Of course, in this case the
push-pull option is not available and any weak
pull-up must implemented externally.
Two different kind of Schmitt Trigger circuitries are
implemented: Standard and High Hysteresis.
Standard Schmitt Trigger is widely used (see Ta-
ble 3), while the High Hysteresis one is present on
Table 3. I/O Port Characteristics
Input
Output
Weak Pull-Up
Reset State
Bidirectional
Bidirectional
Port 0[7:0]
Port 1[7:0]
TTL/CMOS
TTL/CMOS
Push-Pull/OD
Push-Pull/OD
No
No
Port 2[1:0]
Port 2[3:2]
Port 2[5:4]
Port 2[7:6]
Schmitt trigger
TTL/CMOS
Schmitt trigger
TTL/CMOS
Push-Pull/OD
Pure OD
Push-Pull/OD
Push-Pull/OD
Yes
No
Yes
Yes
Input
Input CMOS
Input
Input CMOS
Port 3[2:1]
Port 3.3
Port 3[7:4]
Schmitt trigger
TTL/CMOS
Schmitt trigger
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Yes
Yes
Yes
Input
Input CMOS
Input
Port 4.0, Port 4.4
Port 4.1
Port 4.2, Port 4.5
Port 4.3
Schmitt trigger
Schmitt trigger
TTL/CMOS
Schmitt trigger
Schmitt trigger inside I/O cell Pure OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
No
Input
Yes
Yes
Yes
No
Bidirectional WPU
Input CMOS
Input
Port 4[7:6]
Input
Port 5[2:0], Port 5[7:4] Schmitt trigger
Push-Pull/OD
Push-Pull/OD
No
Yes
Input
Input CMOS
Port 5.3
TTL/CMOS
Port 6[3:0]
Port 6[5:4]
Schmitt trigger
High hysteresis Schmitt trigger Push-Pull/OD
inside I/O cell
Push-Pull/OD
Yes
Input
Yes (inside I/O cell) Input
Port 7[7:0]
Schmitt trigger
Push-Pull/OD
Yes
Input
Port 8[1:0]
Port 8[7:2]
Schmitt trigger
Schmitt trigger
Push-Pull/OD
Push-Pull/OD
Yes
Yes
Input
Bidirectional WPU
Port 9[7:0]
Schmitt trigger
Push-Pull/OD
Yes
Bidirectional WPU
Legend: WPU = Weak Pull-Up, OD = Open Drain
14/324
9
ST92F120 - GENERAL DESCRIPTION
How to Configure the I/O Ports
To configure the I/O ports, use the information in
Table 3, Table 4 and the Port Bit Configuration Ta-
ble in the I/O Ports Chapter (See page 120).
Example 1: SCI input
AF: SIN0, Port: P5.2, Input note: Schmitt Trigger.
Write the port configuration bits:
P5C2.2=1
P5C1.2=0
P5C0.2 =1
Input Note = the hardware characteristics fixed for
each port line in Table 3.
– If Input note = TTL/CMOS, either TTL or CMOS
input level can be selected by software.
Enable the SCI peripheral by software as de-
scribed in the SCI chapter.
– If Input note = Schmitt trigger, selecting CMOS
or TTL input by software has no effect, the input
will always be Schmitt Trigger.
Example 2: SCI output
AF: SOUT0, Port: P5.3, Output note:
Push-Pull/OD.
Alternate Functions (AF) = More than one AF
cannot be assigned to an I/O pin at the same time:
Write the port configuration bits (for AF OUT PP):
P5C2.3=0
P5C1.3=1
P5C0.3 =1
An alternate function can be selected as follows.
AF Inputs:
– AF is selected implicitly by enabling the corre-
sponding peripheral. Exception to this are A/D in-
puts which must be explicitly selected as AF by
software.
Example 3: External Memory I/O
AF: A0/D0, Port : P0.0, Input Note: TTL/CMOS
Write the port configuration bits:
AF Outputs or Bidirectional Lines:
P0C2.0=1
P0C1.0=1
P0C0.0 =1
– In the case of Outputs or I/Os, AF is selected ex-
plicitly by software.
Example 4: Analog input
AF: A0IN0, Port : 7.0, Input Note: does not apply
to analog input
Write the port configuration bits:
P7C2.0=1
P7C1.0=1
P7C0.0 =1
15/324
9
ST92F120 - GENERAL DESCRIPTION
Table 4. I/O Port Alternate Functions
Port
Name
General
Purpose I/O
Pin No.
Alternate Functions
I/O Address/Data bit 0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.1
57
58
59
60
61
62
63
66
45
46
47
48
51
52
53
54
33
34
35
36
37
38
39
40
24
A0/D0
A1/D1
A2/D2
A3/D3
A4/D4
A5/D5
A6/D6
A7/D7
A8
I/O Address/Data bit 1
I/O Address/Data bit 2
I/O Address/Data bit 3
I/O Address/Data bit 4
I/O Address/Data bit 5
I/O Address/Data bit 6
I/O Address/Data bit 7
I/O Address bit 8
A9
I/O Address bit 9
A10
I/O Address bit 10
I/O Address bit 11
I/O Address bit 12
I/O Address bit 13
I/O Address bit 14
I/O Address bit 15
A11
A12
A13
A14
A15
TINPA0
TINPB0
TOUTA0
TOUTB0
TINPA1
TINPB1
TOUTA1
TOUTB1
ICAPB0
ICAPA0
OCMPA0
OCMPB0
EXTCLK0
SS
I
I
Multifunction Timer 0 - Input A
Multifunction Timer 0 - Input B
Multifunction Timer 0 - Output A
Multifunction Timer 0 - Output B
Multifunction Timer 1 - Input A
Multifunction Timer 1 - Input B
Multifunction Timer 1 - Output A
Multifunction Timer 1 - Output B
Ext. Timer 0 - Input Capture B
Ext. Timer 0 - Input Capture A
Ext. Timer 0 - Output Compare A
Ext. Timer 0 - Output Compare B
Ext. Timer 0 - Input Clock
All ports useable
for general pur-
pose I/O (input,
output or bidirec-
tional)
O
O
I
I
O
O
I
I
P3.2
P3.3
P3.4
25
26
27
O
O
I
I
SPI - Slave Select
P3.5
P3.6
28
29
MISO
I/O SPI - Master Input/Slave Output Data
I/O SPI - Master Output/Slave Input Data
MOSI
SCK
I
I
SPI - Serial Input Clock
Wake-up Line 0
P3.7
P4.0
30
14
WKUP0
SCK
O
I
SPI - Serial Output Clock
Ext. Timer 1 - Input Capture A
ICAPA1
16/324
9
ST92F120 - GENERAL DESCRIPTION
Port
Name
General
Purpose I/O
Pin No.
Alternate Functions
P4.1
P4.2
15
16
I/O
O
I
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
WKUP4
EXTRG
STOUT
SDA
Ext. Timer 1 - Output Compare A
Ext. Timer 1 - Input Capture B
Ext. Timer 1 - Output Compare B
Ext. Timer 1 - Input Clock
Wake-up Line 4
P4.3
P4.4
19
20
O
I
I
I
A/D 0 and A/D 1 - Ext. Trigger
Standard Timer Output
P4.5
P4.6
21
22
O
I/O
2
I C Data
WKUP1
SCL
I
I/O
I
Wake-up Line 1
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
23
6
2
I C Clock
WAIT
External Wait Request
Wake-up Line 5
WKUP5
WKUP6
WDOUT
SIN0
I
I
Wake-up Line 6
7
O
I
Watchdog Timer Output
SCI0 - Serial Data Input
Wake-up Line 2
All ports useable
for general pur-
pose I/O (input,
output or bidirec-
tional)
8
WKUP2
SOUT0
WDIN
I
O
I
SCI0 - Serial Data Output
Watchdog Timer Input
SCI0 - Transmit Clock Input
SCI0 - Clock Output
SCI0 - Receive Clock Input
Wake-up Line 7
9
TXCLK0
CLKOUT0
RXCLK0
WKUP7
DCD0
I
10
11
12
13
O
I
I
I
SCI0 - Data Carrier Detect
Wake-up Line 8
WKUP8
WKUP9
RTS0
I
I
Wake-up Line 9
O
I
SCI0 - Request To Send
External Interrupt 0
External Interrupt 1
CLOCK2 divided by 8
External Interrupt 6
Read/Write
INT0
P6.0
P6.1
P6.2
67
68
69
INT1
I
CLOCK2/8
INT6
O
I
RW
O
I
INT2
External Interrupt 2
External Interrupt 4
Data Strobe 2
INT4
I
DS2
O
17/324
9
ST92F120 - GENERAL DESCRIPTION
Port
Name
General
Purpose I/O
Pin No.
Alternate Functions
External Interrupt 3
INT3
INT5
I
I
P6.3
P6.4
70
71
External Interrupt 5
NMI
I
Non Maskable Interrupt
Wake-up Line 10
WKUP10
VPWI
I
P6.5
72
I
JBLPD input
INTCLK
A0IN0
O
I
Internal Main Clock
P7.0
P7.1
P7.2
P7.3
84
85
86
87
A/D 0 - Analog Data Input 0
A/D 0 - Analog Data Input 1
A/D 0 - Analog Data Input 2
A/D 0 - Analog Data Input 3
Wake-up Line 3
A0IN1
I
A0IN2
I
A0IN3
I
WKUP3
A0IN4
I
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
88
89
90
91
74
75
I
A/D 0 - Analog Data Input 4
A/D 0 - Analog Data Input 5
Wake-up Line 11
A0IN5
I
WKUP11
A0IN6
I
I
A/D 0 - Analog Data Input 6
Wake-up Line 12
WKUP12
A0IN7
I
I
A/D 0 - Analog Data Input 7
Wake-up Line 13
All ports useable
for general pur-
pose I/O (input,
output or bidirec-
tional)
WKUP13
A1IN7
I
I
A/D 1 - Analog Data Input 7
Wake-up Line 14
WKUP14
A1IN6
I
I
A/D 1 - Analog Data Input 6
Wake-up Line 15
WKUP15
A1IN5
I
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
76
77
78
79
80
81
98
99
I
A/D 1 - Analog Data Input 5
A/D 1 - Analog Data Input 4
A/D 1 - Analog Data Input 3
A/D 1 - Analog Data Input 2
A/D 1 - Analog Data Input 1
A/D 1 - Analog Data Input 0
SCI1 - Serial Data Input
SCI1 - Serial Data Output
SCI1 - Transmit Clock input
SCI1 - Clock Input
A1IN4
I
A1IN3
I
A1IN2
I
A1IN1
I
A1IN0
I
SIN1
I
SOUT1
TXCLK1
CLKOUT1
RXCLK1
DCD1
O
I
P9.2
100
O
I
P9.3
P9.4
P9.5
P9.6
P9.7
1
2
3
4
5
SCI1 - Receive Clock Input
SCI1 - Data Carrier Detect
SCI1 - Request To Send
CLOCK2 internal signal
I
RTS1
O
O
I/O
CLOCK2
18/324
9
ST92F120 - GENERAL DESCRIPTION
1.4 OPERATING MODES
To optimize the performance versus the power
consumption of the device, the ST92F120 sup-
ports different operating modes that can be dy-
namically selected depending on the performance
and functionality requirements of the application at
a given moment.
after a wake-up line is activated (16 wake-up lines
plus NMI pin). See the RCCU and Wake-up Man-
agement Unit paragraphs in the following for the
details. The difference with the HALT mode con-
sists in the way the CPU exits this state: when the
STOP is executed, the status of the registers is re-
corded, and when the system exits from the STOP
mode the CPU continues the execution with the
same status, without a system reset.
RUN MODE: This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
When the MCU enters STOP mode the Watchdog
stops counting. After the MCU exits from STOP
mode, the Watchdog resumes counting from
where it left off.
SLOW MODE: Power consumption can be signifi-
cantly reduced by running the CPU and the pe-
ripherals at reduced clock speed using the CPU
Prescaler and CCU Clock Divider.
When the MCU exits from STOP mode, the oscil-
lator, which was sleeping too, requires about 5 ms
to restart working properly (at a 4 MHz oscillator
frequency). An internal counter is present to guar-
antee that all operations after exiting STOP Mode,
take place with the clock stabilised.
WAIT FOR INTERRUPT MODE: The Wait For In-
terrupt (WFI) instruction suspends program exe-
cution until an interrupt request is acknowledged.
During WFI, the CPU clock is halted while the pe-
ripheral and interrupt controller keep running at a
frequency depending on the CCU programming.
The counter is active only when the oscillation has
already taken place. This means that 1-2 ms must
be added to take into account the first phase of the
oscillator restart.
LOW POWER WAIT FOR INTERRUPT MODE:
Combining SLOW mode and Wait For Interrupt
mode it is possible to reduce the power consump-
tion by more than 80%.
HALT MODE: When executing the HALT instruc-
tion, and if the Watchdog is not enabled, the CPU
and its peripherals stop operating and the status of
the machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
STOP MODE: When the STOP is requested by
executing the STOP bit writing sequence (see
dedicated section on Wake-up Management Unit
paragraph), and if NMI is kept low, the CPU and
the peripherals stop operating. Operations resume
19/324
9
ST92F120 - DEVICE ARCHITECTURE
2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE
The ST9 Core or Central Processing Unit (CPU)
features a highly optimised instruction set, capable
of handling bit, byte (8-bit) and word (16-bit) data,
as well as BCD and Boolean formats; 14 address-
ing modes are available.
which hold data and control bits for the on-chip
peripherals and I/Os.
– A single linear memory space accommodating
both program and data. All of the physically sep-
arate memory areas, including the internal ROM,
internal RAM and external memory are mapped
in this common address space. The total ad-
dressable memory space of 4 Mbytes (limited by
the size of on-chip memory and the number of
external address pins) is arranged as 64 seg-
ments of 64 Kbytes. Each segment is further
subdivided into four pages of 16 Kbytes, as illus-
trated in Figure 1. A Memory Management Unit
uses a set of pointer registers to address a 22-bit
memory field using 16-bit address-based instruc-
tions.
Four independent buses are controlled by the
Core: a 16-bit Memory bus, an 8-bit Register data
bus, an 8-bit Register address bus and a 6-bit In-
terrupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
Core.
This multiple bus architecture affords a high de-
gree of pipelining and parallel operation, thus mak-
ing the ST9 family devices highly efficient, both for
numerical calculation, data handling and with re-
gard to communication with on-chip peripheral re-
sources.
2.2.1 Register File
The Register File consists of (see Figure 2):
2.2 MEMORY SPACES
– 224 general purpose registers (Group 0 to D,
registers R0 to R223)
There are two separate memory spaces:
– The Register File, which comprises 240 8-bit
registers, arranged as 15 groups (Group 0 to E),
each containing sixteen 8-bit registers plus up to
64 pages of 16 registers mapped in Group F,
– 6 system registers in the System Group (Group
E, registers R224 to R239)
– Up to 64 pages, depending on device configura-
tion, each containing up to 16 registers, mapped
to Group F (R240 to R255), see Figure 3.
Figure 9. Single Program and Data Memory Address Space
Data
Code
Address
16K Pages
64K Segments
255
254
253
252
251
250
249
248
247
3FFFFFh
63
62
3F0000h
3EFFFFh
3E0000h
up to 4 Mbytes
135
134
133
132
21FFFFh
Reserved
33
210000h
20FFFFh
11
10
9
8
7
6
5
4
3
02FFFFh
2
1
0
020000h
01FFFFh
010000h
00FFFFh
2
1
0
000000h
20/324
9
ST92F120 - DEVICE ARCHITECTURE
MEMORY SPACES (Cont’d)
Figure 10. Register Groups
Figure 11. Page Pointer for Group F mapping
PAGE 63
UP TO
255
240
64 PAGES
F PAGED REGISTERS
239
E SYSTEM REGISTERS
224
PAGE 5
223
D
R255
PAGE 0
C
B
A
9
8
7
6
5
4
3
2
1
R240
R234
R224
PAGE POINTER
224
GENERAL
PURPOSE
REGISTERS
15
0
0
0
VA00432
VA00433
R0
Figure 12. Addressing the Register File
REGISTER FILE
255
F PAGED REGISTERS
240
239
E
D
C
B
A
9
SYSTEM REGISTERS
224
223
GROUP D
R195
R207
(R0C3h)
(0011)
(1100)
8
7
6
5
4
3
GROUP C
R195
R192
GROUP B
2
1
0
15
0
0
VR000118
21/324
9
ST92F120 - DEVICE ARCHITECTURE
MEMORY SPACES (Cont’d)
2.2.2 Register Addressing
Therefore if the Page Pointer, R234, is set to 5, the
instructions:
Register File registers, including Group F paged
registers (but excluding Group D), may be ad-
dressed explicitly by means of a decimal, hexa-
decimal or binary address; thus R231, RE7hand
R11100111b represent the same register (see
Figure 4). Group D registers can only be ad-
dressed in Working Register mode.
spp #5
ld R242, r4
will load the contents of working register r4 into the
third register of page 5 (R242).
These paged registers hold data and control infor-
mation relating to the on-chip peripherals, each
peripheral always being associated with the same
pages and registers to ensure code compatibility
between ST9 devices. The number of these regis-
ters therefore depends on the peripherals which
are present in the specific ST9 family device. In
other words, pages only exist if the relevant pe-
ripheral is present.
Note that an upper case “R” is used to denote this
direct addressing mode.
Working Registers
Certain types of instruction require that registers
be specified in the form “rx”, where x is in the
range 0 to 15: these are known as Working Regis-
ters.
Note that a lower case “r” is used to denote this in-
direct addressing mode.
Table 5. Register File Organization
Two addressing schemes are available: a single
group of 16 working registers, or two separately
mapped groups, each consisting of 8 working reg-
isters. These groups may be mapped starting at
any 8 or 16 byte boundary in the register file by
means of dedicated pointer registers. This tech-
nique is described in more detail in Section 1.3.3,
and illustrated in Figure 5 and in Figure 6.
Hex.
Address
Decimal
Address
Register
File Group
Function
Paged
Registers
F0-FF
E0-EF
240-255
224-239
Group F
Group E
System
Registers
D0-DF
C0-CF
B0-BF
A0-AF
90-9F
80-8F
70-7F
60-6F
50-5F
40-4F
30-3F
20-2F
10-1F
00-0F
208-223
192-207
176-191
160-175
144-159
128-143
112-127
96-111
80-95
Group D
Group C
Group B
Group A
Group 9
Group 8
Group 7
Group 6
Group 5
Group 4
Group 3
Group 2
Group 1
Group 0
System Registers
The 16 registers in Group E (R224 to R239) are
System registers and may be addressed using any
of the register addressing modes. These registers
are described in greater detail in Section 1.3.
Paged Registers
General
Purpose
Registers
Up to 64 pages, each containing 16 registers, may
be mapped to Group F. These are addressed us-
ing any register addressing mode, in conjunction
with the Page Pointer register, R234, which is one
of the System registers. This register selects the
page to be mapped to Group F and, once set,
does not need to be changed if two or more regis-
ters on the same page are to be addressed in suc-
cession.
64-79
48-63
32-47
16-31
00-15
22/324
9
ST92F120 - DEVICE ARCHITECTURE
2.3 SYSTEM REGISTERS
The System registers are listed in Table 2 System
Registers (Group E). They are used to perform all
the important system settings. Their purpose is de-
scribed in the following pages. Refer to the chapter
dealing with I/O for a description of the PORT[5:0]
Data registers.
Note: If an MFT is not included in the ST9 device,
then this bit has no effect.
Bit 6 = TLIP: Top Level Interrupt Pending.
This bit is set by hardware when a Top Level Inter-
rupt Request is recognized. This bit can also be
set by software to simulate a Top Level Interrupt
Request.
Table 6. System Registers (Group E)
0: No Top Level Interrupt pending
1: Top Level Interrupt pending
R239 (EFh)
R238 (EEh)
R237 (EDh)
R236 (ECh)
R235 (EBh)
R234 (EAh)
R233 (E9h)
R232 (E8h)
R231 (E7h)
R230 (E6h)
R229 (E5h)
R228 (E4h)
R227 (E3h)
R226 (E2h)
R225 (E1h)
R224 (E0h)
SSPLR
SSPHR
USPLR
Bit 5 = TLI: Top Level Interrupt bit.
0: Top Level Interrupt is acknowledged depending
on the TLNM bit in the NICR Register.
1: Top Level Interrupt is acknowledged depending
on the IEN and TLNM bits in the NICR Register
(described in the Interrupt chapter).
USPHR
MODE REGISTER
PAGE POINTER REGISTER
REGISTER POINTER 1
REGISTER POINTER 0
FLAG REGISTER
CENTRAL INT. CNTL REG
PORT5 DATA REG.
PORT4 DATA REG.
PORT3 DATA REG.
PORT2 DATA REG.
PORT1 DATA REG.
PORT0 DATA REG.
Bit 4 = IEN: Interrupt Enable .
This bit is cleared by interrupt acknowledgement,
and set by interrupt return (iret). IEN is modified
implicitly by iret, eiand diinstructions or by an
interrupt acknowledge cycle. It can also be explic-
itly written by the user, but only when no interrupt
is pending. Therefore, the user should execute a
di instruction (or guarantee by other means that
no interrupt request can arrive) before any write
operation to the CICR register.
0: Disable all interrupts except Top Level Interrupt.
1: Enable Interrupts
2.3.1 Central Interrupt Control Register
Please refer to the ”INTERRUPT” chapter for a de-
tailed description of the ST9 interrupt philosophy.
Bit 3 = IAM: Interrupt Arbitration Mode.
This bit is set and cleared by software to select the
arbitration mode.
0: Concurrent Mode
1: Nested Mode.
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
R230 - Read/Write
Register Group: E (System)
Reset Value: 1000 0111 (87h)
Bits 2:0 = CPL[2:0]: Current Priority Level.
7
0
These three bits record the priority level of the rou-
tine currently running (i.e. the Current Priority Lev-
el, CPL). The highest priority level is represented
by 000, and the lowest by 111. The CPL bits can
be set by hardware or software and provide the
reference according to which subsequent inter-
rupts are either left pending or are allowed to inter-
rupt the current interrupt service routine. When the
current interrupt is replaced by one of a higher pri-
ority, the current priority value is automatically
stored until required in the NICR register.
GCE
N
TLIP TLI
IEN
IAM CPL2 CPL1 CPL0
Bit 7 = GCEN: Global Counter Enable.
This bit is the Global Counter Enable of the Multi-
function Timers. The GCEN bit is ANDed with the
CE bit in the TCR Register (only in devices featur-
ing the MFT Multifunction Timer) in order to enable
the Timers when both bits are set. This bit is set af-
ter the Reset cycle.
23/324
9
ST92F120 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
2.3.2 Flag Register
decw),
Test (tm, tmw, tcm, tcmw, btset).
The Flag Register contains 8 flags which indicate
the CPU status. During an interrupt, the flag regis-
ter is automatically stored in the system stack area
and recalled at the end of the interrupt service rou-
tine, thus returning the CPU to its original status.
Inmostcases, theZeroflag issetwhenthe contents
of the register being used as an accumulator be-
come zero, following one of the above operations.
This occurs for all interrupts and, when operating
in nested mode, up to seven versions of the flag
register may be stored.
Bit 5 = S: Sign Flag.
The Sign flag is affected by the same instructions
as the Zero flag.
FLAG REGISTER (FLAGR)
R231- Read/Write
Register Group: E (System)
Reset value: 0000 0000 (00h)
The Sign flag is set when bit 7 (for a byte opera-
tion) or bit 15 (for a word operation) of the register
used as an accumulator is one.
7
0
Bit 4 = V: Overflow Flag.
The Overflow flag is affected by the same instruc-
tions as the Zero and Sign flags.
C
Z
S
V
DA
H
-
DP
When set, the Overflow flag indicates that a two's-
complement number, in a result register, is in er-
ror, since it has exceeded the largest (or is less
than the smallest), number that can be represent-
ed in two’s-complement notation.
Bit 7 = C: Carry Flag.
The carry flag is affected by:
Addition (add, addw, adc, adcw),
Subtraction (sub, subw, sbc, sbcw),
Compare (cp, cpw),
Shift Right Arithmetic (sra, sraw),
Shift Left Arithmetic (sla, slaw),
Swap Nibbles (swap),
Rotate (rrc, rrcw, rlc, rlcw, ror,
rol),
Decimal Adjust (da),
Multiply and Divide (mul, div, divws).
Bit 3 = DA: Decimal Adjust Flag.
The DA flag is used for BCD arithmetic. Since the
algorithm for correcting BCD operations is differ-
ent for addition and subtraction, this flag is used to
specify which type of instruction was executed
last, so that the subsequent Decimal Adjust (da)
operation can perform its function correctly. The
DA flag cannot normally be used as a test condi-
tion by the programmer.
When set, it generally indicates a carry out of the
most significant bit position of the register being
used as an accumulator (bit 7 for byte operations
and bit 15 for word operations).
Bit 2 = H: Half Carry Flag.
The carry flag can be set by the Set Carry Flag
(scf) instruction, cleared by the Reset Carry Flag
(rcf) instruction, and complemented by the Com-
plement Carry Flag (ccf) instruction.
The H flag indicates a carry out of (or a borrow in-
to) bit 3, as the result of adding or subtracting two
8-bit bytes, each representing two BCD digits. The
H flag is used by the Decimal Adjust (da) instruc-
tion to convert the binary result of a previous addi-
tion or subtraction into the correct BCD result. Like
the DA flag, this flag is not normally accessed by
the user.
Bit 6 = Z: Zero Flag. The Zero flag is affected by:
Addition (add, addw, adc, adcw),
Subtraction (sub, subw, sbc, sbcw),
Compare (cp, cpw),
Shift Right Arithmetic (sra, sraw),
Shift Left Arithmetic (sla, slaw),
Swap Nibbles (swap),
Bit 1 = Reserved bit (must be 0).
Rotate (rrc, rrcw, rlc, rlcw, ror,
rol),
Bit 0 = DP: Data/Program Memory Flag.
This bit indicates the memory area addressed. Its
value is affected by the Set Data Memory (sdm)
and Set Program Memory (spm) instructions. Re-
fer to the Memory Management Unit for further de-
tails.
Decimal Adjust (da),
Multiply and Divide (mul, div, divws),
Logical (and, andw, or, orw, xor,
xorw, cpl),
Increment and Decrement (inc, incw, dec,
24/324
9
ST92F120 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
If the bit is set, data is accessed using the Data
Pointers (DPRs registers), otherwise it is pointed
to by the Code Pointer (CSR register); therefore,
the user initialization routine must include a Sdm
instruction. Note that code is always pointed to by
the Code Pointer (CSR).
specifies the location of the lower 8-register block,
while the srp0and srp1instructions automatical-
ly select the twin 8-register group mode and spec-
ify the locations of each 8-register block.
There is no limitation on the order or position of
these register groups, other than that they must
start on an 8-register boundary in twin 8-register
mode, or on a 16-register boundary in single 16-
register mode.
Note: In the current ST9 devices, the DP flag is
only for compatibility with software developed for
the first generation of ST9 devices. With the single
memory addressing space, its use is now redun-
dant. It must be kept to 1 with a Sdminstruction at
the beginning of the program to ensure a normal
use of the different memory pointers.
The block number should always be an even
number in single 16-register mode. The 16-regis-
ter group will always start at the block whose
number is the nearest even number equal to or
lower than the block number specified in the srp
instruction. Avoid using odd block numbers, since
this can be confusing if twin mode is subsequently
selected.
2.3.3 Register Pointing Techniques
Two registers within the System register group,
are used as pointers to the working registers. Reg-
ister Pointer 0 (R232) may be used on its own as a
single pointer to a 16-register working space, or in
conjunction with Register Pointer 1 (R233), to
point to two separate 8-register spaces.
Thus:
srp #3will be interpreted as srp #2 and will al-
low using R16 ..R31 as r0 .. r15.
For the purpose of register pointing, the 16 register
groups of the register file are subdivided into 32 8-
register blocks. The values specified with the Set
Register Pointer instructions refer to the blocks to
be pointed to in twin 8-register mode, or to the low-
er 8-register block location in single 16-register
mode.
In single 16-register mode, the working registers
are referred to as r0 to r15. In twin 8-register
mode, registers r0to r7are in the block pointed
to by RP0 (by means of the srp0 instruction),
while registers r8to r15are in the block pointed
to by RP1 (by means of the srp1instruction).
The Set Register Pointer instructions srp, srp0
and srp1 automatically inform the CPU whether
the Register File is to operate in single 16-register
mode or in twin 8-register mode. The srpinstruc-
tion selects the single 16-register group mode and
Caution: Group D registers can only be accessed
as working registers using the Register Pointers,
or by means of the Stack Pointers. They cannot be
addressed explicitly in the form “Rxxx”.
25/324
9
ST92F120 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
POINTER 0 REGISTER (RP0)
R232 - Read/Write
Register Group: E (System)
POINTER 1 REGISTER (RP1)
R233 - Read/Write
Register Group: E (System)
Reset Value: xxxx xx00 (xxh)
Reset Value: xxxx xx00 (xxh)
7
0
0
7
0
0
RG4 RG3 RG2 RG1 RG0 RPS
0
RG4 RG3 RG2 RG1 RG0 RPS
0
Bits 7:3 = RG[4:0]: Register Group number.
This register is only used in the twin register point-
ing mode. When using the single register pointing
mode, or when using only one of the twin register
groups, the RP1 register must be considered as
RESERVED and may NOT be used as a general
purpose register.
These bits contain the number (in the range 0 to
31) of the register block specified in the srp0 or
srp instructions. In single 16-register mode the
number indicates the lower of the two 8-register
blocks to which the 16 working registers are to be
mapped, while in twin 8-register mode it indicates
the 8-register block to which r0 to r7 are to be
mapped.
Bits 7:3 = RG[4:0]: Register Group number.
These bits contain the number (in the range 0 to
31) of the 8-register block specified in the srp1in-
struction, to which r8to r15are to be mapped.
Bit 2 = RPS: Register Pointer Selector.
This bit is set by the instructions srp0and srp1to
indicate that the twin register pointing mode is se-
lected. The bit is reset by the srpinstruction to in-
dicate that the single register pointing mode is se-
lected.
Bit 2 = RPS: Register Pointer Selector.
This bit is set by the srp0and srp1instructions to
indicate that the twin register pointing mode is se-
lected. The bit is reset by the srpinstruction to in-
dicate that the single register pointing mode is se-
lected.
0: Single register pointing mode
1: Twin register pointing mode
0: Single register pointing mode
1: Twin register pointing mode
Bits 1:0: Reserved. Forced by hardware to zero.
Bits 1:0: Reserved. Forced by hardware to zero.
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ST92F120 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
Figure 13. Pointing to a single group of 16
registers
Figure 14. Pointing to two groups of 8 registers
REGISTER
GROUP
BLOCK
NUMBER
REGISTER
GROUP
BLOCK
NUMBER
REGISTER
FILE
REGISTER
FILE
31
30
29
28
27
26
25
REGISTER
POINTER 0
&
REGISTER
POINTER 1
F
E
D
31
30
29
28
27
26
25
REGISTER
POINTER 0
set by:
F
E
D
srp #2
set by:
instruction
srp0 #2
&
srp1 #7
points to:
instructions
point to:
addressed by
BLOCK 7
9
8
7
6
5
4
3
2
1
0
4
9
8
7
6
5
4
3
2
1
0
4
r15
r8
GROUP 3
3
2
1
0
3
2
1
0
r15
r0
r7
r0
GROUP 1
addressed by
BLOCK 2
GROUP 1
addressed by
BLOCK 2
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SYSTEM REGISTERS (Cont’d)
2.3.4 Paged Registers
– Management of the clock frequency,
Up to 64 pages, each containing 16 registers, may
be mapped to Group F. These paged registers
hold data and control information relating to the
on-chip peripherals, each peripheral always being
associated with the same pages and registers to
ensure code compatibility between ST9 devices.
The number of these registers depends on the pe-
ripherals present in the specific ST9 device. In oth-
er words, pages only exist if the relevant peripher-
al is present.
– Enabling of Bus request and Wait signals when
interfacing to external memory.
MODE REGISTER (MODER)
R235 - Read/Write
Register Group: E (System)
Reset value: 1110 0000 (E0h)
7
0
SSP
USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP
The paged registers are addressed using the nor-
mal register addressing modes, in conjunction with
the Page Pointer register, R234, which is one of
the System registers. This register selects the
page to be mapped to Group F and, once set,
does not need to be changed if two or more regis-
ters on the same page are to be addressed in suc-
cession.
Bit 7 = SSP: System Stack Pointer.
This bit selects an internal or external System
Stack area.
0: External system stack area, in memory space.
1: Internal system stack area, in the Register File
(reset state).
Thus the instructions:
Bit 6 = USP: User Stack Pointer.
This bit selects an internal or external User Stack
area.
0: External user stack area, in memory space.
1: Internal user stack area, in the Register File (re-
set state).
spp #5
ld R242, r4
will load the contents of working register r4 into the
third register of page 5 (R242).
Warning: During an interrupt, the PPR register is
not saved automatically in the stack. If needed, it
should be saved/restored by the user within the in-
terrupt routine.
Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2.
This bit controls the divide-by-2 circuit operating
on the crystal oscillator clock (CLOCK1).
0: Clock divided by 1
PAGE POINTER REGISTER (PPR)
R234 - Read/Write
1: Clock divided by 2
Register Group: E (System)
Reset value: xxxx xx00 (xxh)
Bits 4:2 = PRS[2:0]: CPUCLK Prescaler.
These bits load the prescaler division factor for the
internal clock (INTCLK). The prescaler factor se-
lects the internal clock frequency, which can be di-
vided by a factor from 1 to 8. Refer to the Reset
and Clock Control chapter for further information.
7
0
0
PP5 PP4 PP3 PP2 PP1 PP0
0
Bits 7:2 = PP[5:0]: Page Pointer.
Bit 1 = BRQEN: Bus Request Enable.
0: External Memory Bus Request disabled
1: External Memory Bus Request enabled on
BREQ pin (where available).
These bits contain the number (in the range 0 to
63) of the page specified in the spp instruction.
Once the page pointer has been set, there is no
need to refresh it unless a different page is re-
quired.
Note: Disregard this bit if BREQ pin is not availa-
ble.
Bits 1:0: Reserved. Forced by hardware to 0.
Bit 0 = HIMP: High Impedance Enable.
When a port is programmed as Address and Data
lines to interface external Memory, these lines and
the Memory interface control lines (AS, DS, R/W)
can be forced into the High Impedance state.
0: External memory interface lines in normal state
1: High Impedance state.
2.3.5 Mode Register
The Mode Register allows control of the following
operating parameters:
– Selection of internal or external System and User
Stack areas,
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ST92F120 - DEVICE ARCHITECTURE
Note: Setting the HIMP bit is recommended for
noise reduction when only internal Memory is
used.
– Subroutine Calls
When a callinstruction is executed, only the PC
is pushed onto stack, whereas when a calls in-
struction (call segment) is executed, both the PC
and the Code Segment Register are pushed onto
the System Stack.
If the memory access ports are declared as an ad-
dress AND as an I/O port (for example: P10... P14
= Address, and P15... P17 = I/O), the HIMP bit has
no effect on the I/O lines.
– Link Instruction
The link or linku instructions create a C lan-
guage stack frame of user-defined length in the
System or User Stack.
2.3.6 Stack Pointers
Two separate, double-register stack pointers are
available: the System Stack Pointer and the User
Stack Pointer, both of which can address registers
or memory.
All of the above conditions are associated with
their counterparts, such as return instructions,
which pop the stored data items off the stack.
The stack pointers point to the “bottom” of the
stacks which are filled using the push commands
and emptied using the pop commands. The stack
pointer is automatically pre-decremented when
data is “pushed” in and post-incremented when
data is “popped” out.
User Stack
The User Stack provides a totally user-controlled
stacking area.
The User Stack Pointer consists of two registers,
R236 and R237, which are both used for address-
ing a stack in memory. When stacking in the Reg-
ister File, the User Stack Pointer High Register,
R236, becomes redundant but must be consid-
ered as reserved.
The push and pop commands used to manage the
System Stack may be addressed to the User
Stack by adding the suffix “u”. To use a stack in-
struction for a word, the suffix “w” is added. These
suffixes may be combined.
Stack Pointers
Both System and User stacks are pointed to by
double-byte stack pointers. Stacks may be set up
in RAM or in the Register File. Only the lower byte
will be required if the stack is in the Register File.
The upper byte must then be considered as re-
served and must not be used as a general purpose
register.
When bytes (or words) are “popped” out from a
stack, the contents of the stack locations are un-
changed until fresh data is loaded. Thus, when
data is “popped” from a stack area, the stack con-
tents remain unchanged.
Note: Instructions such as: pushuw RR236 or
pushw RR238, as well as the corresponding
pop instructions (where R236 & R237, and R238
& R239 are themselves the user and system stack
pointers respectively), must not be used, since the
pointer values are themselves automatically
changed by the pushor popinstruction, thus cor-
rupting their value.
The stack pointer registers are located in the Sys-
tem Group of the Register File, this is illustrated in
Table 2 System Registers (Group E).
Stack Location
Care is necessary when managing stacks as there
is no limit to stack sizes apart from the bottom of
any address space in which the stack is placed.
Consequently programmers are advised to use a
stack pointer value as high as possible, particular-
ly when using the Register File as a stacking area.
System Stack
The System Stack is used for the temporary stor-
age of system and/or control data, such as the
Flag register and the Program counter.
Group D is a good location for a stack in the Reg-
ister File, since it is the highest available area. The
stacks may be located anywhere in the first 14
groups of the Register File (internal stacks) or in
RAM (external stacks).
The following automatically push data onto the
System Stack:
– Interrupts
When entering an interrupt, the PC and the Flag
Register are pushed onto the System Stack. If the
ENCSR bit in the EMR2 register is set, then the
Code Segment Register is also pushed onto the
System Stack.
Note. Stacks must not be located in the Paged
Register Group or in the System Register Group.
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ST92F120 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
USER STACK POINTER HIGH REGISTER
(USPHR)
R236 - Read/Write
SYSTEM STACK POINTER HIGH REGISTER
(SSPHR)
R238 - Read/Write
Register Group: E (System)
Reset value: undefined
Register Group: E (System)
Reset value: undefined
7
0
7
0
USP15 USP14 USP13 USP12 USP11 USP10 USP9 USP8
SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8
USER STACK POINTER LOW REGISTER
(USPLR)
R237 - Read/Write
SYSTEM STACK POINTER LOW REGISTER
(SSPLR)
R239 - Read/Write
Register Group: E (System)
Reset value: undefined
Register Group: E (System)
Reset value: undefined
7
0
7
0
USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0
SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Figure 15. Internal Stack Mode
Figure 16. External Stack Mode
REGISTER
FILE
REGISTER
FILE
STACK POINTER (LOW)
STACK POINTER (LOW)
&
points to:
F
F
STACK POINTER (HIGH)
point to:
MEMORY
E
E
STACK
D
D
STACK
4
3
2
1
0
4
3
2
1
0
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ST92F120 - DEVICE ARCHITECTURE
2.4 MEMORY ORGANIZATION
Code and data are accessed within the same line-
ar address space. All of the physically separate
memory areas, including the internal ROM, inter-
nal RAM and external memory are mapped in a
common address space.
The mapping of the various memory areas (inter-
nal RAM or ROM, external memory) differs from
device to device. Each 64-Kbyte physical memory
segment is mapped either internally or externally;
if the memory is internal and smaller than 64
Kbytes, the remaining locations in the 64-Kbyte
segment are not used (reserved).
The ST9 provides a total addressable memory
space of 4 Mbytes. This address space is ar-
ranged as 64 segments of 64 Kbytes; each seg-
ment is again subdivided into four 16 Kbyte pages.
Refer to the Register and Memory Map Chapter
for more details on the memory map.
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ST92F120 - DEVICE ARCHITECTURE
2.5 MEMORY MANAGEMENT UNIT
The CPU Core includes a Memory Management
Unit (MMU) which must be programmed to per-
form memory accesses (even if external memory
is not used).
sub-divided into 2 main groups: a first group of four
8-bit registers (DPR[3:0]), and a second group of
three 6-bit registers (CSR, ISR, and DMASR). The
first group is used to extend the address during
Data Memory access (DPR[3:0]). The second is
used to manage Program and Data Memory ac-
cesses during Code execution (CSR), Interrupts
Service Routines (ISR or CSR), and DMA trans-
fers (DMASR or ISR).
The MMU is controlled by 7 registers and 2 bits
(ENCSR and DPRREM) present in EMR2, which
may be written and read by the user program.
These registers are mapped within group F, Page
21 of the Register File. The 7 registers may be
Figure 17. Page 21 Registers
Page 21
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
Relocation of P[3:0] and DPR[3:0] Registers
SSPLR
SSPLR
SSPHR
USPLR
USPHR
MODER
PPR
SSPHR
USPLR
USPHR
MODER
PPR
DMASR
ISR
RP1
RP0
RP1
RP0
DMASR
ISR
DMASR
ISR
MMU
FLAGR
CICR
FLAGR
CICR
EMR2
EMR1
CSR
DPR3
DPR2
1
EMR2
EMR1
CSR
P3DR
P2DR
P1DR
P0DR
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
P5DR
P4DR
DPR3
DPR2
DPR1
DPR0
EMR2
EMR1
CSR
EM
MMU
DPR0
DPR3
DPR2
DPR1
DPR0
MMU
Bit DPRREM=0
(default setting)
Bit DPRREM=1
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ST92F120 - DEVICE ARCHITECTURE
2.6 ADDRESS SPACE EXTENSION
To manage 4 Mbytes of addressing space, it is
necessary to have 22 address bits. The MMU
adds 6 bits to the usual 16-bit address, thus trans-
lating a 16-bit virtual address into a 22-bit physical
address. There are 2 different ways to do this de-
pending on the memory involved and on the oper-
ation being performed.
are involved in the following virtual address rang-
es:
DPR0: from 0000h to 3FFFh;
DPR1: from 4000h to 7FFFh;
DPR2: from 8000h to BFFFh;
DPR3: from C000h to FFFFh.
2.6.1 Addressing 16-Kbyte Pages
The contents of the selected DPR register specify
one of the 256 possible data memory pages. This
8-bit data page number, in addition to the remain-
ing 14-bit page offset address forms the physical
22-bit address (see Figure 10).
This extension mode is implicitly used to address
Data memory space if no DMA is being performed.
The Data memory space is divided into 4 pages of
16 Kbytes. Each one of the four 8-bit registers
(DPR[3:0], Data Page Registers) selects a differ-
ent 16-Kbyte page. The DPR registers allow ac-
cess to the entire memory space which contains
256 pages of 16 Kbytes.
A DPR register cannot be modified via an address-
ing mode that uses the same DPR register. For in-
stance, the instruction “POPW DPR0” is legal only
if the stack is kept either in the register file or in a
memory location above 8000h, where DPR2 and
DPR3 are used. Otherwise, since DPR0 and
DPR1 are modified by the instruction, unpredicta-
ble behaviour could result.
Data paging is performed by extending the 14 LSB
of the 16-bit address with the contents of a DPR
register. The two MSBs of the 16-bit address are
interpreted as the identification number of the DPR
register to be used. Therefore, the DPR registers
Figure 18. Addressing via DPR[3:0]
16-bit virtual address
MMU registers
DPR0
00
DPR1
01
DPR2
10
DPR3
SB
11
M
2
8 bits
14 LSB
22-bit physical address
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ADDRESS SPACE EXTENSION (Cont’d)
2.6.2 Addressing 64-Kbyte Segments
Most of these registers do not have a default value
after reset.
This extension mode is used to address Data
memory space during a DMA and Program mem-
ory space during any code execution (normal code
and interrupt routines).
2.7.1 DPR[3:0]: Data Page Registers
The DPR[3:0] registers allow access to the entire 4
Mbyte memory space composed of 256 pages of
16 Kbytes.
Three registers are used: CSR, ISR, and DMASR.
The 6-bit contents of one of the registers CSR,
ISR, or DMASR define one out of 64 Memory seg-
ments of 64 Kbytes within the 4 Mbytes address
space. The register contents represent the 6
MSBs of the memory address, whereas the 16
LSBs of the address (intra-segment address) are
given by the virtual 16-bit address (see Figure 11).
2.7.1.1 Data Page Register Relocation
If these registers are to be used frequently, they
may be relocated in register group E, by program-
ming bit 5 of the EMR2-R246 register in page 21. If
this bit is set, the DPR[3:0] registers are located at
R224-227 in place of the Port 0-3 Data Registers,
which are re-mapped to the default DPR's loca-
tions: R240-243 page 21.
2.7 MMU REGISTERS
The MMU uses 7 registers mapped into Group F,
Page 21 of the Register File and 2 bits of the
EMR2 register.
Data Page Register relocation is illustrated in Fig-
ure 9.
Figure 19. Addressing via CSR, ISR, and DMASR
16-bit virtual address
MMU registers
ISR
DMASR
CSR
1
2
3
1
2
Fetching program
instruction
Data Memory
accessed in DMA
6 bits
Fetching interrupt
instruction or DMA
3
access to Program
Memory
22-bit physical address
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ST92F120 - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
DATA PAGE REGISTER 0 (DPR0)
R240 - Read/Write
Register Page: 21
DATA PAGE REGISTER 2 (DPR2)
R242 - Read/Write
Register Page: 21
Reset value: undefined
Reset value: undefined
This register is relocated to R224 if EMR2.5 is set.
This register is relocated to R226 if EMR2.5 is set.
7
0
7
0
DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0
_7 _6 _5 _4 _3 _2 _1 _0
DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2
_7 _6 _5 _4 _3 _2 _1 _0
Bits 7:0 = DPR0_[7:0]: These bits define the 16-
Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to ex-
tend the address during a Data Memory access.
The DPR0 register is used when addressing the
virtual address range 0000h-3FFFh.
Bits 7:0 = DPR2_[7:0]: These bits define the 16-
Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR2 register is involved when the virtual address
is in the range 8000h-BFFFh.
DATA PAGE REGISTER 1 (DPR1)
R241 - Read/Write
Register Page: 21
DATA PAGE REGISTER 3 (DPR3)
R243 - Read/Write
Register Page: 21
Reset value: undefined
Reset value: undefined
This register is relocated to R225 if EMR2.5 is set.
This register is relocated to R227 if EMR2.5 is set.
7
0
7
0
DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1
_7 _6 _5 _4 _3 _2 _1 _0
DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3
_7 _6 _5 _4 _3 _2 _1 _0
Bits 7:0 = DPR1_[7:0]: These bits define the 16-
Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to ex-
tend the address during a Data Memory access.
The DPR1 register is used when addressing the
virtual address range 4000h-7FFFh.
Bits 7:0 = DPR3_[7:0]: These bits define the 16-
Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR3 register is involved when the virtual address
is in the range C000h-FFFFh.
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ST92F120 - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
2.7.2 CSR: Code Segment Register
ISR and ENCSR bit (EMR2 register) are also de-
scribed in the chapter relating to Interrupts, please
refer to this description for further details.
This register selects the 64-Kbyte code segment
being used at run-time to access instructions. It
can also be used to access data if the spminstruc-
tion has been executed (or ldpp, ldpd, lddp).
Only the 6 LSBs of the CSR register are imple-
mented, and bits 6 and 7 are reserved. The CSR
register allows access to the entire memory space,
divided into 64 segments of 64 Kbytes.
Bits 7:6 = Reserved, keep in reset state.
Bits 5:0 = ISR_[5:0]: These bits define the 64-
Kbyte memory segment (among 64) which con-
tains the interrupt vector table and the code for in-
terrupt service routines and DMA transfers (when
the PS bit of the DAPR register is reset). These
bits are used as the most significant address bits
(A21-16). The ISR is used to extend the address
space in two cases:
To generate the 22-bit Program memory address,
the contents of the CSR register is directly used as
the 6 MSBs, and the 16-bit virtual address as the
16 LSBs.
Note: The CSR register should only be read and
not written for data operations (there are some ex-
ceptions which are documented in the following
paragraph). It is, however, modified either directly
by means of the jps and calls instructions, or
indirectly via the stack, by means of the retsin-
struction.
– Whenever an interrupt occurs: ISR points to the
64-Kbyte memory segment containing the inter-
rupt vector table and the interrupt service routine
code. See also the Interrupts chapter.
– During DMA transactions between the peripheral
and memory when the PS bit of the DAPR regis-
ter is reset : ISR points to the 64 K-byte Memory
segment that will be involved in the DMA trans-
action.
CODE SEGMENT REGISTER (CSR)
R244 - Read/Write
Register Page: 21
Reset value: 0000 0000 (00h)
7
0
0
2.7.4 DMASR: DMA Segment Register
DMA SEGMENT REGISTER (DMASR)
R249 - Read/Write
0
CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 CSR_0
Register Page: 21
Reset value: undefined
Bits 7:6 = Reserved, keep in reset state.
7
0
0
Bits 5:0 = CSR_[5:0]: These bits define the 64-
Kbyte memory segment (among 64) which con-
tains the code being executed. These bits are
used as the most significant address bits (A21-16).
DMA
DMA
DMA
DMA
DMA
DMA
0
SR_5 SR_4 SR_3 SR_2 SR_1 SR_0
Bits 7:6 = Reserved, keep in reset state.
2.7.3 ISR: Interrupt Segment Register
INTERRUPT SEGMENT REGISTER (ISR)
R248 - Read/Write
Register Page: 21
Bits 5:0 = DMASR_[5:0]: These bits define the 64-
Kbyte Memory segment (among 64) used when a
DMA transaction is performed between the periph-
eral's data register and Memory, with the PS bit of
the DAPR register set. These bits are used as the
most significant address bits (A21-16). If the PS bit
is reset, the ISR register is used to extend the ad-
dress.
Reset value: undefined
7
0
0
0
ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
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ST92F120 - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
Figure 20. Memory Addressing Scheme (example)
4M bytes
3FFFFFh
16K
294000h
DPR3
DPR2
DPR1
DPR0
240000h
23FFFFh
20C000h
16K
16K
200000h
1FFFFFh
040000h
03FFFFh
64K
64K
030000h
DMASR
020000h
ISR
010000h
00C000h
16K
64K
CSR
000000h
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ST92F120 - DEVICE ARCHITECTURE
2.8 MMU USAGE
2.8.1 Normal Program Execution
Program memory is organized as a set of 64-
Kbyte segments. The program can span as many
segments as needed, but a procedure cannot
stretch across segment boundaries. jps, calls
and retsinstructions, which automatically modify
the CSR, must be used to jump across segment
boundaries. Writing to the CSR is forbidden during
normal program execution because it is not syn-
chronized with the opcode fetch. This could result
in fetching the first byte of an instruction from one
memory segment and the second byte from anoth-
er. Writing to the CSR is allowed when it is not be-
ing used, i.e during an interrupt service routine if
ENCSR is reset.
used instead of the CSR, and the interrupt stack
frame is kept exactly as in the original ST9 (only
the PC and flags are pushed). This avoids the
need to save the CSR on the stack in the case of
an interrupt, ensuring a fast interrupt response
time. The drawback is that it is not possible for an
interrupt service routine to perform segment
calls/jps: these instructions would update the
CSR, which, in this case, is not used (ISR is used
instead). The code size of all interrupt service rou-
tines is thus limited to 64 Kbytes.
If, instead, bit 6 of the EMR2 register is set, the
ISR is used only to point to the interrupt vector ta-
ble and to initialize the CSR at the beginning of the
interrupt service routine: the old CSR is pushed
onto the stack together with the PC and the flags,
and then the CSR is loaded with the ISR. In this
case, an iret will also restore the CSR from the
stack. This approach lets interrupt service routines
access the whole 4-Mbyte address space. The
drawback is that the interrupt response time is
slightly increased, because of the need to also
save the CSR on the stack. Compatibility with the
original ST9 is also lost in this case, because the
interrupt stack frame is different; this difference,
however, would not be noticeable for a vast major-
ity of programs.
Note that a routine must always be called in the
same way, i.e. either always with callor always
with calls, depending on whether the routine
ends with ret or rets. This means that if the rou-
tine is written without prior knowledge of the loca-
tion of other routines which call it, and all the pro-
gram code does not fit into a single 64-Kbyte seg-
ment, then calls/retsshould be used.
In typical microcontroller applications, less than 64
Kbytes of RAM are used, so the four Data space
pages are normally sufficient, and no change of
DPR[3:0] is needed during Program execution. It
may be useful however to map part of the ROM
into the data space if it contains strings, tables, bit
maps, etc.
Data memory mapping is independent of the value
of bit 6 of the EMR2 register, and remains the
same as for normal code execution: the stack is
the same as that used by the main program, as in
the ST9. If the interrupt service routine needs to
access additional Data memory, it must save one
(or more) of the DPRs, load it with the needed
memory page and restore it before completion.
If there is to be frequent use of paging, the user
can set bit 5 (DPRREM) in register R246 (EMR2)
of Page 21. This swaps the location of registers
DPR[3:0] with that of the data registers of Ports 0-
3. In this way, DPR registers can be accessed
without the need to save/set/restore the Page
Pointer Register. Port registers are therefore
moved to page 21. Applications that require a lot of
paging typically use more than 64 Kbytes of exter-
nal memory, and as ports 0, 1 and 2 are required
to address it, their data registers are unused.
2.8.3 DMA
Depending on the PS bit in the DAPR register (see
DMA chapter) DMA uses either the ISR or the
DMASR for memory accesses: this guarantees
that a DMA will always find its memory seg-
ment(s), no matter what segment changes the ap-
plication has performed. Unlike interrupts, DMA
transactions cannot save/restore paging registers,
so a dedicated segment register (DMASR) has
been created. Having only one register of this kind
means that all DMA accesses should be pro-
grammed in one of the two following segments:
the one pointed to by the ISR (when the PS bit of
the DAPR register is reset), and the one refer-
enced by the DMASR (when the PS bit is set).
2.8.2 Interrupts
The ISR register has been created so that the in-
terrupt routines may be found by means of the
same vector table even after a segment jump/call.
When an interrupt occurs, the CPU behaves in
one of 2 ways, depending on the value of the ENC-
SR bit in the EMR2 register (R246 on Page 21).
If this bit is reset (default condition), the CPU
works in original ST9 compatibility mode. For the
duration of the interrupt service routine, the ISR is
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
3 SINGLE VOLTAGE FLASH & EEPROM
3.1 INTRODUCTION
The Flash circuitry contains one array divided in
two main parts that can each be read independ-
ently. The first part contains the main Flash array
for code storage, a reserved array (TestFlash) for
system routines and a 128-byte area available as
one time programmable memory (OTP). The sec-
ond part contains the two dedicated Flash sectors
used for EEPROM Hardware Emulation.
The write operations of the two parts are managed
by an embedded Program/Erase Controller, that
uses a dedicated ROM. Through a dedicated RAM
buffer the Flash and the EEPROM can be written
in blocks of 16 bytes.
Figure 21. Flash Memory Structure (Example for 128K Flash device)
8 sense +
8 program load
Address
Data
230000h
231F80h
TestFlash
8 Kbytes
User OTP and Protection registers
Register
Interface
000000h
010000h
RAM buffer
16 bytes
Sector F0
64 Kbytes
Sector F1
48 Kbytes
Program / Erase
Controller
01C000h
01E000h
Sector F2
8 Kbytes
Sector F3
8 Kbytes
228000h
22C000h
Sector E0
4 Kbytes
Sector E1
4 Kbytes
8 sense +
8 program load
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
3.2 FUNCTIONAL DESCRIPTION
3.2.1 Structure
reserved for the Non-Volatile Protection registers
and cannot be used as a storage area (see Sec-
tion 3.6 PROTECTION STRATEGY for more de-
tails).
The Flash memory is composed of three parts
(see following table):
– 1 reserved sector for system routines (TestFlash
including user OTP area)
3.2.2 EEPROM Emulation
A hardware EEPROM emulation is implemented
using special flash sectors E0 and E1 to emulate
an EEPROM memory whose size is 1/4 of a sector
(1 Kbyte). This EEPROM can be directly ad-
dressed from 220000h to 2203FFh.
– 4 main sectors for code
– 2 sectors of the same size for EEPROM emula-
tion
The last 128 bytes of the TestFlash are available
to the user as an OTP area. The user can program
these bytes, but cannot erase them. The last 4
bytes of this OTP area (231FFCh to 231FFFh ) are
(see Section 3.5.1 Hardware EEPROM Emulation
for more details).
Table 7. Memory Structure for 128K Flash Device
Sector
Addresses
Max Size
TestFlash (TF) (Reserved)
230000h to 231F7Fh
8064 bytes
OTP Area
Protection Registers (reserved)
231F80h to 231FFBh
231FFCh to 231FFFh
124 bytes
4 bytes
Flash 0 (F0)
Flash 1 (F1)
000000h to 00FFFFh
010000h to 01BFFFh
01C000h to 01DFFFh
01E000h to 01FFFFh
228000h to 228FFFh
22C000h to 22CFFFh
220000h to 2203FFh
64 Kbytes
48 Kbytes
8 Kbytes
8 Kbytes
4 Kbytes
4 Kbytes
1 Kbyte
Flash 2 (F2)
Flash 3 (F3)
EEPROM 0 (E0)
EEPROM 1 (E1)
Emulated EEPROM
Table 8. Memory Structure for 60K Flash Device
Sector
Addresses
Max Size
TestFlash (TF) (Reserved)
230000h to 231F7Fh
8064 bytes
OTP Area
Protection Registers (reserved)
231F80h to 231FFBh
231FFCh to 231FFFh
124 bytes
4 bytes
Flash 0 (F0)
Reserved
000000h to 000FFFh
001000h to 00FFFFh
010000h to 01BFFFh
01C000h to 01DFFFh
228000h to 228FFFh
22C000h to 22CFFFh
220000h to 2203FFh
4 Kbytes
60 Kbytes
48 Kbytes
8 Kbytes
4 Kbytes
4 Kbytes
1Kbyte
Flash 1 (F1)
Flash 2 (F2)
EEPROM 0 (E0)
EEPROM 1 (E1)
Emulated EEPROM
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
FUNCTIONAL DESCRIPTION (Cont’d)
3.2.3 Operation
Control and Status registers are mapped in mem-
ory (segment 22h), as shown in the following fig-
ure.
The memory has a register interface mapped in
memory space (segment 22h). All operations are
enabled through the FCR (Flash Control Register)
ECR (EEPROM Control Register).
Figure 22. Control and Status Register Map
All operations on the Flash must be executed from
another memory (internal RAM, EEPROM, exter-
nal memory).
Register Interface
224000h
224001h
224002h
224003h
FCR
ECR
FESR0
FESR1
Flash (including TestFlash) and EEPROM have
duplicated sense amplifiers, so that one can be
read while the other is written. However simultane-
ous Flash and EEPROM write operations are for-
bidden.
During a write operation, if the power supply drops
or the RESET pin is activated, the write operation
is immediately interrupted. In this case the user
must repeat the last write operation following pow-
er on or reset.
An interrupt can be generated at the end of a
Flash or an EEPROM write operation: this inter-
rupt is multiplexed with an external interrupt EX-
TINTx (device dependent) to generate an interrupt
INTx.
The status of a write operation inside the Flash
and the EEPROM memories can be monitored
through the FESR[1:0] registers.
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3.3 REGISTER DESCRIPTION
3.3.1 Control Registers
ation in Flash memory. The Chip Erase operation
allows to erase all the Flash locations to FFh. The
operation is limited to Flash code (sectors F0-F3;
TestFlash and EEPROM sectors excluded). The
execution starts by setting the FWMS bit. It is not
necessary to pre-program the sectors to 00h, be-
cause this is done automatically. This bit is auto-
matically reset at the end of the Chip Erase opera-
tion.
FLASH CONTROL REGISTER (FCR)
Address: 224000h - Read/Write
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
FWM FPAG FCHI FBYT FSEC FSUS
FBUS
Y
PROT
0: Deselect chip erase
1: Select chip erase
S
E
P
E
T
P
The Flash Control Register is used to enable all
the operations for the Flash and the TestFlash
memories. The write access to the TestFlash is
possible only in Test mode, except the OTP area
of the TestFlash that can be programmed in user
mode (but not erased).
Bit 4 = FBYTE: Flash byte program (Read/Write).
This bit must be set to select the Byte Program op-
eration in Flash memory. The Byte Program oper-
ation allows “0”s to be programmedin place of “1”s.
Data to be programmed and an address in which
to program must be provided (through an LD in-
struction, for example) before starting execution
by setting bit FWMS. This bit is automatically reset
at the end of the Byte Program operation.
0: Deselect byte program
Bit 7 = FWMS: Flash Write Mode Start (Read/
Write).
This bit must be set to start every write/erase oper-
ation in Flash memory. At the end of the write/
erase operation or during a Sector Erase Suspend
this bit is automatically reset. To resume a sus-
pended Sector Erase operation, this bit must be
set again. Resetting this bit by software does not
stop the current write operation.
1: Select byte program
Bit 3 = FSECT: Flash sector erase (Read/Write).
This bit must be set to select the Sector Erase op-
eration in Flash memory. The Sector Erase opera-
tion erases all the Flash locations to FFh. From 1
to 4 sectors (F0, ..,F3) can be simultaneously
erased, while TF must be individually erased. Sec-
tors to be simultaneously erased can be entered
before starting the execution by setting the FWMS
bit. An address located in the sector to erase must
be provided (through an LD instruction, for exam-
ple), while the data to be provided is don’t care. It
is not necessary to pre-program the sectors to
00h, because this is done automatically. This bit is
automatically reset at the end of the Sector Erase
operation.
0: No effect
1: Start Flash write
Bit 6 = FPAGE: Flash Page program (Read/Write).
This bit must be set to select the Page Program
operation in Flash memory. The Page Program
operation allows to program “0”s in place of “1”s.
From 1 to 16 bytes can be entered (in any order,
no need for an ordered address sequence) before
starting the execution by setting the FWMS bit . All
the addresses must belong to the same page (only
the 4 LSBs of address can change). Data to be
programmed and addresses in which to program
must be provided (through an LD instruction, for
example). Data contained in page addresses that
are not entered are left unchanged. This bit is au-
tomatically reset at the end of the Page Program
operation.
0: Deselect sector erase
1: Select sector erase
Bit 2 = FSUSP: Flash sector erase suspend
(Read/Write).
This bit must be set to suspend the current Sector
Erase operation in Flash memory in order to read
data to or from program data to a sector not being
erased. The Erase Suspend operation resets the
Flash memory to normal read mode (automatically
resetting bit FBUSY) in a maximum time of 15µs.
0: Deselect page program
1: Select page program
Bit 5 = FCHIP: Flash CHIP erase (Read/Write).
This bit must be set to select the Chip Erase oper-
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REGISTER DESCRIPTION (Cont’d)
When in Erase Suspend the memory accepts only
the following operations: Read, Erase Resume
and Byte Program. Updating the EEPROM memo-
ry is not possible during a Flash Erase Suspend.
EEPROM CONTROL REGISTER (ECR)
Address: 224001h - Read/Write
Reset value: 000x x000 (xxh)
The FSUSP bit must be reset (and FWMS must be
set again) to resume a suspended Sector Erase
operation.
0: Resume sector erase when FWMS is set again.
1: Suspend Sector erase
7
6
5
4
3
2
1
0
EWM EPAG ECHI
FEIE EBUS
WFIS
S
E
P
N
Y
The EEPROM Control Register is used to enable
all the operations for the EEPROM memory in de-
vices with EEPROM hardware emulation.
Bit 1 = PROT: Set Protection (Read/Write).
This bit must be set to select the Set Protection op-
eration. The Set Protection operation allows “0”s in
place of “1”s to be programmed in the four Non
Volatile Protection registers. From 1 to 4 bytes can
be entered (in any order, no need for an ordered
address sequence) before starting the execution
by setting the FWMS bit . Data to be programmed
and addresses in which to program must be pro-
vided (through an LD instruction, for example).
Protection contained in addresses that are not en-
tered are left unchanged. This bit is automatically
reset at the end of the Set Protection operation.
0: Deselect protection
The ECR also contains two bits (WFIS and FEIEN)
that are related to both Flash and EEPROM mem-
ories.
Bit 7 = EWMS: EEPROM Write Mode Start.
This bit must be set to start every write/erase oper-
ation in the EEPROM memory. At the end of the
write/erase operation this bit is automatically reset.
Resetting by software this bit does not stop the
current write operation.
0: No effect
1: Start EEPROM write
1: Select protection
Bit 6 = EPAGE: EEPROM page update.
This bit must be set to select the Page Update op-
eration in EEPROM memory. The Page Update
operation allows to write a new content: both “0”s
in place of “1”s and “1”s in place of “0”s. From 1 to
16 bytes can be entered (in any order, no need for
an ordered address sequence) before starting the
execution by setting bit EWMS. All the addresses
must belong to the same page (only the 4 LSBs of
address can change). Data to be programmed and
addresses in which to program must be provided
(through an LD instruction, for example). Data
contained in page addresses that are not entered
are left unchanged. This bit is automatically reset
at the end of the Page Update operation.
Bit 0 = FBUSY: Flash Busy (Read Only).
This bit is automatically set during Page Program,
Byte Program, Sector Erase or Set Protection op-
erations when the first address to be modified is
latched in Flash memory, or during Chip Erase op-
eration when bit FWMS is set. When this bit is set
every read access to the Flash memory will output
invalid data (FFh equivalent to a NOP instruction),
while every write access to the Flash memory will
be ignored. At the end of the write operations or
during a Sector Erase Suspend, this bit is auto-
matically reset and the memory returns to read
mode. After an Erase Resume this bit is automati-
cally set again. The FBUSY bit remains high for a
maximum of 10 µs after Power-Up and when exit-
ing Power-Down mode, meaning that the Flash
memory is not yet ready to be accessed.
0: Deselect page update
1: Select page update
0: Flash not busy
1: Flash busy
Bit 5 = ECHIP: EEPROM chip erase.
This bit must be set to select the Chip Erase oper-
ation in the EEPROM memory. The Chip Erase
operation allows to erase all the EEPROM loca-
tions to (E0 and E1 sectors) FFh. The execution
starts by setting bit EWMS. This bit is automatical-
ly reset at the end of the Chip Erase operation.
0: Deselect chip erase
1: Select chip erase
Bit 4:3 = Reserved.
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
REGISTER DESCRIPTION (Cont’d)
Bit 2 = WFIS: Wait For Interrupt Status.
Bit 0 = EBUSY: EEPROM Busy (Read Only).
If this bit is reset, the WFI instruction puts the
Flash macrocell in Stand-by mode (immediate
read possible, but higher consumption: 100 µA); if
it is set, the WFI instruction puts the Flash macro-
cell in Power-Down mode (recovery time of 10µs
needed before reading, but lower consumption:
10µA). The Stand-by mode or the Power-Down
mode will be entered only at the end of any current
Flash or EEPROM write operation.
This bit is automatically set during a Page Update
operation when the first address to be modified is
latched in the EEPROM memory, or during Chip
Erase operation when bit EWMS is set. At the end
of the write operation or during a Sector Erase
Suspend this bit is automatically reset and the
memory returns to read mode. When this bit is set
every read access to the EEPROM memory will
output invalid data (FFh equivalent to a NOP in-
struction), while every write access to the EEP-
ROM memory will be ignored. At the end of the
write operation this bit is automatically reset and
the memory returns to read mode. Bit EBUSY re-
mains high for a maximum of 10ms after Power-
Up and when exiting Power-Down mode, meaning
that the EEPROM memory is not yet ready to be
accessed.
In the same way following an HALT or a STOP in-
struction, the Memory enters Power-Down mode
only after the completion of any current write oper-
ation.
0: Flash in Standby mode on WFI
1: Flash in Power-Down mode on WFI
Note: HALT or STOP mode can be exited without
problems, but the user should take care when ex-
iting WFI Power Down mode. If WFIS is set, the
user code must reset the XT_DIV16 bit in the
R242 register (page 55) before executing the WFI
instruction. When exiting WFI mode, this gives the
Flash enough time to wake up before the interrupt
vector fetch.
0: EEPROM not busy
1: EEPROM busy
Bit 1 = FEIEN: Flash & EEPROM Interrupt enable.
This bit selects the source of interrupt channel
INTx between the external interrupt pin and the
Flash/EEPROM End of Write interrupt. Refer to
the Interrupt chapter for the channel number.
0: External interrupt enabled
1: Flash & EEPROM Interrupt enabled
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
Table 9. FESSx bit Values
REGISTER DESCRIPTION (Cont’d)
3.3.2 Status Registers
During a Flash or an EEPROM write operation any
attempt to read the memory under modification will
output invalid data (FFh equivalent to a NOP in-
struction). This means that the Flash memory is
not fetchable when a write operation is active: the
write operation commands must be given from an-
other memory (EEPROM, internal RAM, or exter-
nal memory).
FBUSY
EBUSY
FESSx=1
meaning
FEERR
FSUSP
Sector Erase
Suspended in
sector x
0
0
0
0
1
0
Don’t care
Two Status Registers (FESR[1:0] are available to
check the status of the current write operation in
Flash and EEPROM memories.
FLASH & EEPROM STATUS REGISTER 1
(FESR1)
Address: 224003h -Read Only
Reset value: 0000 0000 (00h)
FLASH & EEPROM STATUS REGISTER 0
(FESR0)
Address: 224002h -Read/Write
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
SWE
R
ERER PGER
7
6
5
4
3
2
1
0
FEER FESS FESS FESS FESS FESS FESS FESS
Bit 7 = ERER. Erase error (Read Only).
R
6
5
4
3
2
1
0
This bit is set by hardware when an Erase error oc-
curs during a Flash or an EEPROM write opera-
tion. This error is due to a real failure of a Flash
cell, that can not be erased anymore. This kind of
error is fatal and the sector where it occurred must
be discarded (if it was in one of the EEPROM sec-
tors, the hardware emulation can not be used any-
more). This bit is automatically cleared when bit
FEERR of the FESR0 register is cleared by soft-
ware.
Bit 7 = FEERR: Flash or EEPROM write ERRor
(Read/Write).
This bit is set by hardware when an error occurs
during a Flash or an EEPROM write operation. It
must be cleared by software.
0: Write OK
1: Flash or EEPROM write error
0: Erase OK
1: Erase error
Bits 6:0 = FESS[6:0]. Flash and EEPROM Status
Sector 6-0 (Read Only).
These bits are set by hardware and give the status
of the 7 Flash and EEPROM sectors (TF, E1, E0,
F3, F2, F1, F0). The meaning of FESSx bit for sec-
tor x is given by the following table:
Bit 6 = PGER. Program error (Read Only).
This bit is automatically set when a Program error
occurs during a Flash or an EEPROM write opera-
tion. This error is due to a real failure of a Flash
cell, that can not be programmed anymore. The
byte where this error occurred must be discarded
(if it was in the EEPROM memory, the byte must
be reprogrammed to FFh and then discarded, to
avoid the error occurring again when that byte is
internally moved). This bit is automatically cleared
when bit FEERR of the FESR0 register is cleared
by software.
Table 9. FESSx bit Values
FBUSY
FESSx=1
meaning
FEERR
FSUSP
EBUSY
Write Error in
Sector x
1
-
-
0: Program OK
1: Flash or EEPROM Programming error
Write operation
on-going in sec-
tor x
0
1
-
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
REGISTER DESCRIPTION (Cont’d)
Bit 5 = SWER. Swap or 1 over 0 Error (Read On-
ly).
This bit has two different meanings, depending on
whether the current write operation is to Flash or
EEPROM memory.
Once the error has been discovered the user must
take to end the stopped Erase Phase 0 on the old
sector (through another predefined routine in Test-
Flash: Complete Swap = 23002Fh). The byte
where the error occurred must be reprogrammed
to FFh and then discarded, to avoid the error oc-
curring again when that byte is internally moved.
In Flash memory, this bit is automatically set when
trying to program at 1 bits previously set at 0 (this
does not happen when programming the Protec-
tion bits). This error is not due to a failure of the
Flash cell, but only flags that the desired data has
not been written.
This bit is automatically cleared when bit FEERR
of the FESR0 register is cleared by software.
Bits 4:0 = Reserved.
In the EEPROM memory, this bit is automatically
set when a Program error occurs during the swap-
ping of the unselected pages to the new sector
when the old sector is full (see Section 3.5.1 Hard-
ware EEPROM Emulation for more details).
This error is due to a real failure of a Flash cell,
that can not be programmed anymore. When this
error is detected, the embedded algorithm auto-
matically exits the Page Update operation at the
end of the Swap phase, without performing the
Erase Phase 0 on the full sector. In this way the
old data are kept, and through predefined routines
in TestFlash (Find Wrong Pages = 230029h and
Find Wrong Bytes = 23002Ch), the user can com-
pare the old and the new data to find where the er-
ror occurred.
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
3.4 WRITE OPERATION EXAMPLE
Each operation (both Flash and EEPROM) is acti-
vated by a sequence of instructions like the follow-
ing:
The load instructions are used to set the address-
es (in the Flash or in the EEPROM memory space)
and the data to be modified.
The last instruction is used to start the write oper-
ation, by setting the start bit (FWMS for Flash op-
erations, EWMS for EEPROM operation) in the
Control register.
OR
LD
LD
..
LD
CR, #OPMASK ;Operation selection
ADD1, #DATA1;1st Add and Data
ADD2, #DATA2;2nd Add and Data
...., ......
Once selected, but not yet started, one operation
can be cancelled by resetting the operation selec-
tion bit. Any latched address and data will be reset.
ADDn, #DATAn;nth Add and Data
;n range = (1 to 16)
Caution: during the Flash Page Program or the
EEPROM Page Update operation it is forbidden to
change the page address: only the last page ad-
dress is effectively kept and all programming will
effect only that page.
OR
CR, #80h
;Operation start
The first instruction is used to select the desired
operation by setting its corresponding selection bit
in the Control Register (FCR for Flash operations,
ECR for EEPROM operations).
A summary of the available Flash and EEPROM
write operations are shown in the following tables:
Table 10. Flash Write Operations
Operation
Byte Program
Page Program
Sector Erase
Selection bit
FBYTE
Addresses and Data
1 byte
Start bit
FWMS
FWMS
FWMS
None
Typical Duration
10 µs
FPAGE
FSECT
FSUSP
FCHIP
From 1 to 16 bytes
From 1 to 4 sectors
None
160 µs (16 bytes)
1.5 s (1 sector)
15 µs
Sector Erase Suspend
Chip Erase
None
FWMS
FWMS
3 s
Set Protection
PROT
From 1 to 4 bytes
40 µs (4 bytes)
Table 11. EEPROM Write Operations
Operation
Page Update
Chip Erase
Selection bit
EPAGE
Addresses and Data
From 1 to 16 bytes
None
Start bit
EWMS
EWMS
Typical Duration
30 ms
ECHIP
70 ms
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3.5 EEPROM
3.5.1 Hardware EEPROM Emulation
ROM inside the two dedicated Flash sectors E0
and E1.
Note: This section provides general information
only. Users do not have to be concerned with the
hardware EEPROM emulation.
The structure of the hardware emulation is shown
in Figure 23.
The last 256 bytes of the two EEPROM dedicated
sectors (229000h to 2290FFh for sector E0 and
22D000h to 22D0FFh for sector E1) are reserved
for the Non Volatile pointers used for the hardware
Emulation.
Each one of the two EEPROM dedicated Flash
sectors E0 and E1 is divided in 4 blocks of the
same size of the EEPROM to emulate (1Kbyte
max).
Each one of the 4 blocks is then divided in up to 64
pages of 16 bytes, the size of the available RAM
buffer.
When the EEPROM is directly addressed through
the addresses 220000h to 2203FFh, a Hardware
Emulation mechanism is automatically activated,
so avoiding the user having to manage the Non
Volatile pointers that are used to map the EEP-
The RAM buffer is used internally to temporarily
store the new content of the page to update, dur-
ing the Page Program operation (both in Flash and
in EEPROM).
Figure 23. Segment 22h Structure (Example for 128K Flash device)
EEPROM sector E0 EEPROM sector E1
228000h
228400h
228800h
228C00h
Page 0 - 16 byte
Page 1 - 16 byte
22C000h
22C400h
22C800h
22CC00h
Page 0 - 16 byte
Page 1 - 16 byte
Page 2 to 61
Page 2 to 61
Page 62 - 16 byte
Page 63 - 16 byte
Page 0 - 16 byte
Page 1 - 16 byte
Page 62 - 16 byte
Page 63 - 16 byte
Page 0 - 16 byte
Page 1 - 16 byte
Page 2 to 61
Page 2 to 61
Page 62 - 16 byte
Page 63 - 16 byte
Page 0 - 16 byte
Page 1 - 16 byte
Page 62 - 16 byte
Page 63 - 16 byte
Page 0 - 16 byte
Page 1 - 16 byte
Page 2 to 61
Page 2 to 61
Page 62 - 16 byte
Page 63 - 16 byte
Page 0 - 16 byte
Page 1 - 16 byte
Page 62 - 16 byte
Page 63 - 16 byte
Page 0 - 16 byte
Page 1 - 16 byte
Page 2 to 61
Page 2 to 61
Page 62 - 16 byte
Page 63 - 16 byte
Page 62 - 16 byte
Page 63 - 16 byte
229000h
220000h
22D000h
224000h
Non Volatile Status
256 byte
Non Volatile Status
256 byte
HW emulated EEPROM
User Registers
FCR, ECR, FESR1-0 - 4 byte
64 pages
1 Kbyte
RAM buffer
Page buffer - 16 byte
2203FFh
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ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
EEPROM (Cont’d)
3.5.2 EEPROM Update Operation
The update of the EEPROM content can be made
by pages of 16 consecutive bytes. The Page Up-
date operation allows up to 16 bytes to be loaded
into the RAM buffer that replace the ones already
contained in the specified address.
on the complementary sector, if the 4 erase phas-
es have not yet been executed. When the selected
page is copied to the complementary sector, the
remaining 63 pages are also copied to the first
block of the new sector; then the first erase phase
is executed on the previous full sector. All this is
executed in a hidden manner, and the End Page
Update Interrupt is generated only after the end of
the complete operation.
Each time a Page Update operation is executed in
the EEPROM, the RAM buffer content is pro-
grammed in the next free block relative to the
specified page (the RAM buffer is previously auto-
matically filled with old data for all the page ad-
dresses not selected for updating). If all the 4
blocks of the specified page in the current EEP-
ROM sector are full, the page content is copied to
the complementary sector, that becomes the new
current one.
At Reset the two status pages are read in order to
detect which is the sector that is currently mapping
the EEPROM, and in which block each page is
mapped. A system defined routine written in Test-
Flash is executed at reset, so that any previously
aborted write operation is restarted and complet-
ed.
After that the specified page has been copied to
the next free block, one erase phase is executed
Figure 24. Hardware Emulation Flow
Emulation Flow
Reset
Program selected
Page from RAM buffer
in next free block
Read Status Pages
new
sector ?
Yes
Yes
Map EEPROM
in current sector
No
Copy all other Pages
into RAM buffer;
then program them
in next free block
Write operation
to complete ?
Yes
Complete
Write operation
Update
No
Complementary
sector erased ?
Status page
No
1/4 erase of
Wait for
complementary sector
Update commands
Page
Update
Update
Status Page
Command
End Page
Update
Interrupt
(to Core)
49/324
9
ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
3.6 PROTECTION STRATEGY
The protection bits are stored in the last 4 loca-
tions of the TestFlash (from 231FFCh) (see Figure
25).
TestFlash, and consequently to the Protection
Registers.
All the available protections are forced active dur-
ing reset, then in the initialisation phase they are
read from the TestFlash.
NON VOLATILE ACCESS PROTECTION REG-
ISTER (NVAPR)
Address: 231FFCh - Read/Write
Delivery value: 1111 1111 (FFh)
The protections are stored in 2 Non Volatile Regis-
ters. Other 2 Non Volatile Registers can be used
as a password to re-enable test modes once they
have been disabled.
7
1
6
5
4
3
2
1
0
The protections can be programmed using the Set
Protection operation (see Control Registers para-
graph), that can be executed from all the internal
or external memories except the Flash or Test-
Flash itself.
APRO APBR APEE APEX PWT2 PWT1 PWT0
Bit 7 = Reserved.
Bit 6 = APRO: Flash Access Protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the Flash
address space (EEPROM excluded), unless the
current instruction is fetched from the TestFlash or
from the Flash itself.
The TestFlash area (230000h to 231F7Fh) is al-
ways protected against write access.
Figure 25. Protection Map
Protection
0: Flash protection on
1: Flash protection off
231FFCh
231FFDh
231FFEh
231FFFh
NVAPR
NVWPR
NVPWD0
NVPWD1
Bit 5 = APBR: TestFlash Access Protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the Test-
Flash address space, unless the current instruc-
tion is fetched from the TestFlash itself.
0: TestFlash protection on
3.6.1 Non Volatile Registers
1: TestFlash protection off
The 4 Non Volatile Registers used to store the pro-
tection bits for the different protection features are
one time programmable by the user, but they are
erasable in Test mode (if not disabled).
Bit 4 = APEE: EEPROM Access Protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the EEP-
ROM address space, unless the current instruc-
tion is fetched from the TestFlash or from the
Flash, or from the EEPROM itself.
0: EEPROM protection on
1: EEPROM protection off
Access to these registers is controlled by the pro-
tections related to the TestFlash where they are
mapped. Since the code to program the Protection
Registers cannot be fetched by the Flash or the
TestFlash memories, this means that, once the
APRO or APBR bits in the NVAPR register are
programmed, it is no longer possible to modify any
of the protection bits. For this reason the NV Pass-
word, if needed, must be set with the same Set
Protection operation used to program these bits.
For the same reason it is strongly advised to never
program the WPBR bit in the NVWPR register, as
this will prevent any further write access to the
Bit 3 = APEX: Access Protection from External
Memory.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the ad-
dress space of one of the internal memories (Test-
Flash, Flash, EEPROM, RAM), if the current in-
struction is fetched from an external memory.
50/324
9
ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
PROTECTION STRATEGY (Cont’d)
Bits 2:0 = PWT[2:0]: Password Attempt 2-0.
Bit 5 = WPBR: TestFlash Write Protection.
This bit, if programmed at 0, disables any write ac-
cess to the TestFlash address space. This protec-
tion cannot be temporarily disabled.
0: TestFlash write protection on
If the TMDIS bit in the NVWPR register (231FFDh)
is programmed to 0, every time a Set Protection
operation is executed with Program Addresses
equal to NVPWD1-0 (231FFE-Fh), the two provid-
ed Program Data are compared with the
NVPWD1-0 content; if there is not a match one of
PWT2-0 bits is automatically programmed to 0:
when these three bits are all programmed to 0 the
test modes are disabled forever. In order to inten-
tionally disable test modes forever, it is sufficient to
set a random Password and then to make 3 wrong
attempts to enter it.
1: TestFlash write protection off
Note: it is strongly advised to never program the
WPBR bit in the NVWPR register, as this will pre-
vent any further write access to the protection reg-
isters.
Bit 4 = WPEE: EEPROM Write Protection.
This bit, if programmed to 0, disables any write ac-
cess to the EEPROM address space. This protec-
tion can be temporary disabled by executing the
Set Protection operation and writing 1 into this bit.
To restore the protection it needs to reset the mi-
cro or to execute another Set Protection operation
and write 0 to this bit.
NON VOLATILE WRITE PROTECTION REGIS-
TER (NVWPR)
Address: 231FFDh - Read/Write
Delivery value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
0: EEPROM write protection on
1: EEPROM write protection off
TMDI PWO WPB WPE WPRS WPRS WPRS WPRS
S
K
R
E
3
2
1
0
Bits 3:0 = WPRS[3:0]: ROM Segments 3-0 Write
Protection.
Bit 7 = TMDIS: Test mode disable (Read Only).
This bit, if set to 1, allows to bypass all the protec-
tions in test and EPB modes. If programmed to 0,
on the contrary, all the protections remain active
also in test mode. The only way to enable the test
modes if this bit is programmed to 0, is to execute
the Set Protection operation with Program Ad-
dresses equal to NVPWD1-0 (231FFF-Eh) and
Program Data matching with the content of
NVPWD1-0. This bit is read only: it is automatically
programmed to 0 when NVPWD1-0 are written for
the first time.
These bits, if programmed to 0, disable any write
access to the 4 Flash sectors address spaces.
These protections can be temporary disabled by
executing the Set Protection operation and writing
1 into these bits. To restore the protection it needs
to reset the micro or to execute another Set Pro-
tection operation and write 0 into these bits.
0: ROM Segments 3-0 write protection on
1: ROM Segments 3-0 write protection off
NON VOLATILE PASSWORD (NVPWD1-0)
Address: 231FFF-231FFEh - Write Only
Delivery value: 1111 1111 (FFh)
0: Test mode disabled
1: Test mode enabled
Bit 6 = PWOK: Password OK (Read Only).
If the TMDIS bit is programmed to 0, when the Set
Protection operation is executed with Program Ad-
dresses equal to NVPWD[1:0] and Program Data
matching with NVPWD[1:0] content, the PWOK bit
is automatically programmed to 0. When this bit is
programmed to 0 TMDIS protection is bypassed
and the test and EPB modes are enabled.
0: Password OK
7
6
5
4
3
2
1
0
PWD PWD PWD PWD PWD PWD PWD PWD
7
6
5
4
3
2
1
0
Bits 7:0 = PWD[7:0]: Password bits 7:0 (Write On-
ly).
These bits must be programmed with the Non Vol-
atile Password that must be provided with the Set
Protection operation to disable (first write access)
or to reenable (second write access) the test and
EPB modes. The first write access fixes the pass-
word value and resets the TMDIS bit of NVWPR
1: Password not OK
51/324
9
ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
(231FFDh). The second write access, with Pro-
gram Data matching with NVPWD[1:0] content, re-
sets the PWOK bit of NVWPR.
grammed. If the value 1 is detected on the SOUT0
pin and the Flash is virgin, a HALT instruction is
executed, waiting for a hardware Reset.
These two registers can be accessed only in write
mode (a read access returns FFh).
3.7.1 Code Update Routine
The TestFlash Code Update routine is called auto-
matically if the SOUT0 pin is held low during pow-
er-on.
3.6.2 Temporary Unprotection
On user request the memory can be configured so
as to allow the temporary unprotection also of all
access protections bits of NVAPR (write protection
bits of NVWPR are always temporarily unprotecta-
ble).
The Code Update routine performs the following
operations:
■ Enables the SCI0 peripheral in synchronous
mode
Bit APEX can be temporarily disabled by execut-
ing the Set Protection operation and writing 1 into
this bit, but only if this write instruction is executed
from an internal memory (Flash and Test Flash ex-
cluded).
■ Transmits a synchronization datum (25h);
■ Waits for an address match (23h) with a timeout
of 10ms (@ f
4 MHz)
OSC
■ If the match is not received before the timeout,
the execution returns to the Power-On routine
Bit APEE can be temporarily disabled by execut-
ing the Set Protection operation and writing 1 into
this bit, but only if this write instruction is executed
from the memory itself to unprotect (EEPROM).
■ If the match is received, the SCI0 transmits a
new datum (21h) to tell the external device that
it is ready to receive the data to be loaded in
RAM (that represents the code of the in-system
programming routine).
Bits APRO and APBR can be temporarily disabled
through a direct write at NVAPR location, by over-
writing at 1 these bits, but only if this write instruc-
tion is executed from the memory itself to unpro-
tect.
■ Receives two data representing the number of
bytes to be loaded (max. 4 Kbytes)
■ Receive the specified number of bytes (each
one preceded by the transmission of a Ready to
Receive character: (21h) and writes them in
internal RAM starting from address 200010h.
The first 4 words should be the interrupt vectors
of the 4 possible SCI interrupts, to be used by
the in-system programming routine.
To restore the access protection bits it needs to re-
set the micro or to execute a Set Protection opera-
tion and write 0 into the desired bits.
When an internal memory (Flash, TestFlash or
EEPROM) is protected in access, also the data ac-
cess through a DMA of a peripheral is forbidden (it
returns FFh). To read data in DMA mode from a
protected memory, first it is necessary to tempo-
rarily unprotect that memory.
■ Transmit a last datum (21h) as a request for end
of communications.
■ Receives
the
end
of
communication
confirmation datum (any byte other than 25h).
■ Resets all the unused RAM locations to FFh;
■ Calls address 200018h in internal RAM.
■ After completion of the in-system programming
routine, an HALT instruction is executed and an
Hardware Reset is needed.
The temporary unprotection allows also to update
a protected code.
3.7 FLASH IN-SYSTEM PROGRAMMING
The Code Update routine initializes the SCI0 pe-
ripheral as shown in the following table:
The Flash memory can be programmed in-system
through a serial interface (SCI0).
Exiting from reset, the ST9 executes the initializa-
tion from the TestFlash code (written in Test-
Flash), where it checks the value of the SOUT0
pin. If it is at 0, this means that the user wishes to
update the Flash code, otherwise normal execu-
tion continues. In this second case, the TestFlash
code reads the reset vector.
Table 12. SCI0 Registers (page 24) initialization
Register
IVR - R244
ACR - R245
IDPR - R249
CHCR - R250
Value
10h
Notes
Vector Table in 0010h
Address Match is 23h
SCI interrupt priority is 0
8 Data Bits
23h
00h
83h
If the Flash is virgin (read content is always FFh),
its reset vector contains FFFFh. This is interpreted
by the TestFlash code as a flag indicating that the
Flash memory is virgin and needs to be pro-
rec. clock: ext RXCLK0
trx clock: int CLKOUT0
CCR - R251
E8h
00h
BRGHR - R252
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9
ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
Note: Four interrupt routines are used by the code
update routine: SCI Receiver Error Interrupt rou-
tine (vector in 0010h), SCI address Match Interrupt
routine (vector in 0012h), SCI Receiver Data
Ready Interrupt routine (vector in 0014h) and SCI
Transmitter Buffer Empty Interrupt routine (vector
in 0016h).
Register
Value
04h
Notes
BRGLR - R253
SICR - R254
SOCR - R255
Baud Rate Divider is 4
Synchronous Mode
83h
01h
In addition, the Code Update routine remaps the
interrupts in the TestFlash (ISR = 23h), and config-
ures I/O Ports P5.3 (SOUT0) and and P5.4
(CLKOUT0) as Alternate Functions.
Figure 26. Flash in-system Programming
TestFlash Code
Internal RAM (User Code Example)
Start
In-system
prog routine
Initialization
Address
Match
Interrupt
(from SCI)
No
Flash
virgin ?
Yes
No
Yes
SOUT0
= 0 ?
Erase sectors
Jump to Flash
Enable Serial
Interface
Main
User
Code
Load 1st table
of data in RAM
through S.I.
Test
Flash
WFI
Code Update
Routine
Prog 1st table
of data from
RAM in Flash
Load 2nd table
of data in RAM
through SCI
Enable DMA
Load in-system
prog routine
in internal RAM
through SCI.
Inc. Address
No
Last
Address ?
Yes
Call in-system
prog routine
RET
HALT
53/324
9
ST92F120 - REGISTER AND MEMORY MAP
4 REGISTER AND MEMORY MAP
4.1 INTRODUCTION
The ST92F120 register map, memory map and
peripheral options are documented in this section.
Use this reference information to supplement the
functional descriptions given elsewhere in this
document.
memory, the address where the routine starts has
to be written in 000006h (one word) while the seg-
ement where the routine is located has to be writ-
ten in 000009h (one byte).
This routine is called at least once every time that
the TestFlash executes an EEPROM write opera-
tion. If the write operation has a long duration, the
user routine is called with a rate fixed by location
000008h with an internal clock frequency of 2
MHz, location 000008h fixes the number of mill-
seconds to wait between two calls of the user rou-
tine.
4.2 MEMORY CONFIGURATION
The Program memory space of the ST92F120 up
to 128K bytes of directly addressable on-chip
memory, is fully available to the user.
4.2.1 Reset Vector Location
In 128k devices, the reset vector is located in
01E000h.
Table 13. User Routine Parameters
Location
Size
Description
In 60k devices, the reset vector is located in
000000h.
000006h to
000007h
2 bytes
User routine address
4.2.2 Location of Vector for External Watchdog
Refresh
000008h
000009h
1 byte
1 byte
ms rate at 2 MHz.
User routine segment
If an external watchdog is used, it must be re-
freshed during TestFlash execution by a user writ-
ten routine. This routine has to be located in Flash
If location 000006h to 000007h is virgin (FFFFh),
the user routine is not called.
54/324
9
ST92F120 - REGISTER AND MEMORY MAP
Figure 27. ST92F120JV1Q7/ST92F120V1Q7 User Memory Map (part 1)
01FFFFh
PAGE 7h - 16 Kbytes
PAGE 6h - 16 Kbytes
PAGE 5h - 16 Kbytes
PAGE 4h - 16 Kbytes
PAGE 3h - 16 Kbytes
PAGE 2h - 16 Kbytes
PAGE 1h - 16 Kbytes
PAGE 0h - 16 Kbytes
SECTOR F3
8 Kbytes
01C000h
01BFFFh
SEGMENT 1h
64 Kbytes
018000h
017FFFh
SECTOR F2
8 Kbytes
014000h
013FFFh
010000h
00FFFFh
SECTOR F1
48 Kbytes
00C000h
00BFFFh
SEGMENT 0h
64 Kbytes
008000h
007FFFh
SECTOR F0
64 Kbytes
004000h
003FFFh
000000h
FLASH - 128 Kbytes
22FFFFh
PAGE 8Bh - 16 Kbytes
PAGE 8Ah - 16 Kbytes
PAGE 89h - 16 Kbytes
PAGE 88h - 16 Kbytes
22C000h
22BFFFh
SEGMENT 22h
64 Kbytes
228000h
227FFFh
224000h
223FFFh
220000h
2203FFh
1 Kbyte
220000h
Emulated EEPROM - 1 Kbyte
55/324
9
ST92F120 - REGISTER AND MEMORY MAP
Figure 28. ST92F120JV1Q7/ST92F120V1Q7 User Memory Map (part 2)
23FFFFh
PAGE 8Fh - 16 Kbytes
23C000h
23BFFFh
PAGE 8Eh - 16 Kbytes
PAGE 8Dh - 16 Kbytes
PAGE 8Ch - 16 Kbytes
SEGMENT 23h
64 Kbytes
238000h
237FFFh
234000h
233FFFh
230000h
231FFFh
8 Kbytes
128 bytes
4 bytes
230000h
TESTFLASH - 8 Kbytes
FLASH OTP - 128 bytes
231FFFh
231F80h
231FFFh
231FFCh
FLASH OTP Protection - 4 bytes
22FFFFh
PAGE 8Bh - 16 Kbytes
PAGE 8Ah - 16 Kbytes
PAGE 89h - 16 Kbytes
PAGE 88h - 16 Kbytes
22C000h
22BFFFh
SEGMENT 22h
64 Kbytes
228000h
227FFFh
224000h
223FFFh
220000h
224003h
4 bytes
224000h
FLASH Registers - 4 bytes
Not Available
56/324
9
ST92F120 - REGISTER AND MEMORY MAP
Figure 29. ST92F120 User Memory Map (part 3)
20FFFFh
PAGE 83h - 16 Kbytes
20C000h
20BFFFh
PAGE 82h - 16 Kbytes
SEGMENT 20h
64 Kbytes
208000h
207FFFh
PAGE 81h - 16 Kbytes
204000h
203FFFh
PAGE 80h- 16 Kbytes
200000h
200FFFh
2007FFh
4 Kbytes
2 Kbytes
200000h
Not Available
RAM
4.3 ST92F120 REGISTER MAP
– Registers common to other functions.
– In particular, double-check that any registers
with “undefined” reset values have been correct-
ly initialised.
Table 15 contains the map of the group F periph-
eral pages.
The common registers used by each peripheral
are listed in Table 14.
Caution: Note that in the EIVR and each IVR reg-
ister, all bits are significant. Take care when defin-
ing base vector addresses that entries in the Inter-
rupt Vector table do not overlap.
Be very careful to correctly program both:
– The set of registers dedicated to a particular
function or peripheral.
Table 14. Common Registers
Function or Peripheral
Common Registers
SCI, MFT
A/D
CICR + NICR + DMA REGISTERS + I/O PORT REGISTERS
CICR + NICR + I/O PORT REGISTERS
CICR + NICR + EXTERNAL INTERRUPT REGISTERS +
I/O PORT REGISTERS
SPI, WDT, STIM
I/O PORTS
EXTERNAL INTERRUPT
RCCU
I/O PORT REGISTERS + MODER
INTERRUPT REGISTERS + I/O PORT REGISTERS
INTERRUPT REGISTERS + MODER
57/324
9
ST92F120 - REGISTER AND MEMORY MAP
Table 15. Group F Pages Register Map
Resources available on the ST92F120 device:
Reg.
Page
21 23
0
2
3
7
8
9
10
11
20
24
25
28
29
43
55
57
61
63
R255
Res
R254 Res.
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
Res.
Res.
Res
Res.
Res.
Res. Res.
Res.
Res.
Res. Res.
R241
Res.
R240
58/324
9
ST92F120 - REGISTER AND MEMORY MAP
Table 16. Detailed Register Map
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R224
R225
R226
R227
R228
R229
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R240
R241
R242
R244
R245
R246
R248
R249
R250
R252
R253
R254
CICR
FLAGR
RP0
Central Interrupt Control Register
Flag Register
87
00
xx
23
24
26
26
28
28
30
30
30
30
Pointer 0 Register
RP1
Pointer 1 Register
xx
PPR
Page Pointer Register
xx
Core
MODER
USPHR
USPLR
SSPHR
SSPLR
P0DR
P1DR
P2DR
P3DR
P4DR
P5DR
EITR
Mode Register
E0
xx
User Stack Pointer High Register
User Stack Pointer Low Register
System Stack Pointer High Reg.
System Stack Pointer Low Reg.
Port 0 Data Register
xx
N/A
xx
xx
FF
FF
FF
FF
FF
FF
00
00
00
FF
x6
00
FF
FF
FF
12
7F
00
00
00
00
00
00
FF
00
00
FE
00
00
Port 1 Data Register
I/O
Port
0:5
Port 2 Data Register
118
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
External Interrupt Trigger Register
External Interrupt Pending Reg.
External Interrupt Mask-bit Reg.
External Interrupt Priority Level Reg.
External Interrupt Vector Register
Nested Interrupt Control
78
79
EIPR
EIMR
79
INT
EIPLR
EIVR
79
130
80
0
NICR
WDTHR
WDTLR
WDTPR
WDTCR
WCR
Watchdog Timer High Register
Watchdog Timer Low Register
Watchdog Timer Prescaler Reg.
Watchdog Timer Control Register
Wait Control Register
129
129
129
129
130
WDT
P0C0
Port 0 Configuration Register 0
Port 0 Configuration Register 1
Port 0 Configuration Register 2
Port 1 Configuration Register 0
Port 1 Configuration Register 1
Port 1 Configuration Register 2
Port 2 Configuration Register 0
Port 2 Configuration Register 1
Port 2 Configuration Register 2
Port 3 Configuration Register 0
Port 3 Configuration Register 1
Port 3 Configuration Register 2
I/O
Port
0
P0C1
P0C2
P1C0
I/O
Port
1
P1C1
P1C2
2
118
P2C0
I/O
Port
2
P2C1
P2C2
P3C0
I/O
Port
3
P3C1
P3C2
59/324
9
ST92F120 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R244
R245
R246
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
P4C0
P4C1
P4C2
P5C0
P5C1
P5C2
P6C0
P6C1
P6C2
P6DR
P7C0
P7C1
P7C2
P7DR
SPDR0
SPCR0
SPSR0
SPPR0
Port 4 Configuration Register 0
Port 4 Configuration Register 1
Port 4 Configuration Register 2
Port 5 Configuration Register 0
Port 5 Configuration Register 1
Port 5 Configuration Register 2
Port 6 Configuration Register 0
Port 6 Configuration Register 1
Port 6 Configuration Register 2
Port 6 Data Register
FD
00
00
FF
00
00
3F
00
00
FF
FF
00
00
FF
00
00
00
00
I/O
Port
4
I/O
Port
5
3
118
I/O
Port
6
Port 7 Configuration Register 0
Port 7 Configuration Register 1
Port 7 Configuration Register 2
Port 7 Data Register
I/O
Port
7
SPI0 Data Register
214
214
215
215
SPI0 Control Register
7
SPI
SPI0 Status Register
SPI0 Prescaler Register
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9
ST92F120 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240 REG0HR1
R241 REG0LR1
R242 REG1HR1
R243 REG1LR1
R244 CMP0HR1
R245 CMP0LR1
R246 CMP1HR1
Capture Load Register 0 High
Capture Load Register 0 Low
Capture Load Register 1 High
Capture Load Register 1 Low
Compare 0 Register High
Compare 0 Register Low
Compare 1 Register High
Compare 1 Register Low
Timer Control Register
xx
xx
xx
xx
00
00
00
00
00
00
00
00
00
00
00
00
xx
xx
xx
C7
FC
xx
xx
xx
C7
xx
xx
xx
xx
00
00
00
00
00
00
00
00
00
00
00
00
169
169
169
169
169
169
169
169
170
171
172
172
173
174
174
176
169
169
169
169
178
176
177
177
178
169
169
169
169
169
169
169
169
170
171
172
172
173
174
174
176
R247
R248
R249
R250
R251
R252
R253
CMP1LR1
TCR1
8
TMR1
Timer Mode Register
MFT1
MFT0,1
MFT0
T_ICR1
PRSR1
OACR1
OBCR1
External Input Control Register
Prescaler Register
Output A Control Register
Output B Control Register
Flags Register
R254 T_FLAGR1
R255
R244
R245
R246
R247
R248
R240
R241
R242
R243
IDMR1
DCPR1
DAPR1
T_IVR1
IDCR1
IOCR
Interrupt/DMA Mask Register
DMA Counter Pointer Register
DMA Address Pointer Register
Interrupt Vector Register
Interrupt/DMA Control Register
I/O Connection Register
DMA Counter Pointer Register
DMA Address Pointer Register
Interrupt Vector Register
Interrupt/DMA Control Register
Capture Load Register 0 High
Capture Load Register 0 Low
Capture Load Register 1 High
Capture Load Register 1 Low
Compare 0 Register High
Compare 0 Register Low
Compare 1 Register High
Compare 1 Register Low
Timer Control Register
9
DCPR0
DAPR0
T_IVR0
IDCR0
R240 REG0HR0
R241 REG0LR0
R242 REG1HR0
R243 REG1LR0
R244 CMP0HR0
R245 CMP0LR0
R246 CMP1HR0
R247
R248
R249
R250
R251
R252
R253
CMP1LR0
TCR0
10
TMR0
Timer Mode Register
T_ICR0
PRSR0
OACR0
OBCR0
External Input Control Register
Prescaler Register
Output A Control Register
Output B Control Register
Flags Register
R254 T_FLAGR0
R255 IDMR0
Interrupt/DMA Mask Register
61/324
9
ST92F120 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R243
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R248
R249
R245
R246
STH
STL
Counter High Byte Register
Counter Low Byte Register
FF
FF
FF
14
00
00
00
00
00
00
00
A0
xx
xx
xx
xx
xx
xx
00
x0
xx
xx
xx
xx
00
xx
xx
80
1F
134
134
134
134
227
228
230
231
231
232
232
232
233
234
234
234
235
235
235
236
35
11
STIM
STP
Standard Timer Prescaler Register
Standard Timer Control Register
STC
2
I2DCCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I2CADR
I2CISR
I2CIVR
I2CRDAP
I2CRDC
I2CTDAP
I2CTDC
I2CECCR
I2CIMR
DPR0
I C Control Register
2
I C Status Register 1
2
I C Status Register 2
2
I C Clock Control Register
2
I C Own Address Register 1
2
I C Own Address Register 2
2
I C Data Register
2
I C General Call Address
20
I2C
2
I C Interrupt Status Register
2
I C Interrupt Vector Register
Receiver DMA Source Addr. Pointer
Receiver DMA Transaction Counter
Transmitter DMA Source Addr. Pointer
Transmitter DMA Transaction Counter
Extended Clock Control Register
2
I C Interrupt Mask Register
Data Page Register 0
Data Page Register 1
DPR1
35
DPR2
Data Page Register 2
35
MMU
DPR3
Data Page Register 3
35
21
CSR
Code Segment Register
Interrupt Segment Register
DMA Segment Register
External Memory Register 1
External Memory Register 2
36
ISR
36
DMASR
EMR1
36
115
116
EXTMI
EMR2
62/324
9
ST92F120 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R243
R244
STATUS
TXDATA
RXDATA
TXOP
Status Register
Transmit Data Register
40
xx
xx
00
00
40
xx
00
xx
10
00
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
x0
xx
xx
xx
xx
xx
00
xx
xx
03
01
259
260
261
261
266
266
267
268
270
270
270
272
274
274
274
274
194
194
194
194
196
196
196
196
198
198
199
200
201
202
202
202
203
Receive Data Register
Transmit Opcode Register
System Frequency Selection Register
Control Register
CLKSEL
R245 CONTROL
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R248
R249
R250
R251
R252
R253
R254
R255
PADDR
ERROR
IVR
Physiscal Address Register
Error Register
23
JBLPD
Interrupt Vector Register
PRLR
Priority Level Register
IMR
Interrupt Mask Register
OPTIONS
CREG0
CREG1
CREG2
CREG3
RDCPR0
RDAPR0
TDCPR0
TDAPR0
S_IVR0
ACR0
Options and Register Group Selection
Current Register 0
Current Register 1
Current Register 2
Current Register 4
Receiver DMA Transaction Counter Pointer
Receiver DMA Source Address Pointer
Transmitter DMA Transaction Counter Pointer
Transmitter DMA Destination Address Pointer
Interrupt Vector Register
Address/Data Compare Register
Interrupt Mask Register
IMR0
S_ISR0
RXBR0
TXBR0
IDPR0
Interrupt Status Register
24
SCI0
Receive Buffer Register
Transmitter Buffer Register
Interrupt/DMA Priority Register
Character Configuration Register
Clock Configuration Register
Baud Rate Generator High Reg.
Baud Rate Generator Low Register
Synchronous Input Control
Synchronous Output Control
CHCR0
CCR0
BRGHR0
BRGLR0
SICR0
SOCR0
63/324
9
ST92F120 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R243
R244
R245
R246
R247
R248
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
RDCPR1
RDAPR1
TDCPR1
TDAPR1
S_IVR1
ACR1
Receiver DMA Transaction Counter Pointer
Receiver DMA Source Address Pointer
Transmitter DMA Transaction Counter Pointer
Transmitter DMA Destination Address Pointer
Interrupt Vector Register
xx
xx
xx
xx
xx
xx
x0
xx
xx
xx
xx
xx
00
xx
xx
03
01
xx
xx
xx
xx
FF
FC
FF
FC
80
00
80
00
00
00
00
00
194
194
194
194
196
196
196
196
198
198
199
200
201
202
202
202
203
147
147
147
147
148
148
148
148
149
149
149
149
151
151
151
151
Address/Data Compare Register
Interrupt Mask Register
IMR1
S_ISR1
RXBR1
TXBR1
IDPR1
Interrupt Status Register
25
SCI1
Receive Buffer Register
Transmitter Buffer Register
Interrupt/DMA Priority Register
Character Configuration Register
Clock Configuration Register
Baud Rate Generator High Reg.
Baud Rate Generator Low Register
Synchronous Input Control
CHCR1
CCR1
BRGHR1
BRGLR1
SICR1
SOCR1
IC1HR0
IC1LR0
IC2HR0
IC2LR0
CHR0
Synchronous Output Control
Input Capture 1 High Register
Input Capture 1 Low Register
Input Capture 2 High Register
Input Capture 2 Low Register
Counter High Register
CLR0
Counter Low Register
ACHR0
ACLR0
OC1HR0
OC1LR0
OC2HR0
OC2LR0
CR1_0
CR2_0
SR0
Alternate Counter High Register
Alternate Counter Low Register
Output Compare 1 High Register
Output Compare 1 Low Register
Output Compare 2 High Register
Output Compare 2 Low Register
Control Register 1
28
EFT0
Control Register 2
Status Register
CR3_0
Control Register 3
64/324
9
ST92F120 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R248
R249
R250
R251
R252
R253
R254
R255
R240
IC1HR1
IC1LR1
IC2HR1
IC2LR1
CHR1
Input Capture 1 High Register
Input Capture 1 Low Register
Input Capture 2 High Register
Input Capture 2 Low Register
Counter High Register
xx
xx
147
147
147
147
148
148
148
148
149
149
149
149
151
151
151
151
xx
xx
FF
FC
FF
FC
80
CLR1
Counter Low Register
ACHR1
ACLR1
OC1HR1
OC1LR1
OC2HR1
OC2LR1
CR1_1
CR2_1
SR1
Alternate Counter High Register
Alternate Counter Low Register
Output Compare 1 High Register
Output Compare 1 Low Register
Output Compare 2 High Register
Output Compare 2 Low Register
Control Register 1
29
EFT1
00
80
00
00
Control Register 2
00
Status Register
00
CR3_1
P8C0
Control Register 3
00
Port 8 Configuration Register 0
Port 8 Configuration Register 1
Port 8 Configuration Register 2
Port 8 Data Register
03
I/O
Port
8
P8C1
00
P8C2
00
P8DR
FF
00
43
118
P9C0
Port 9 Configuration Register 0
Port 9 Configuration Register 1
Port 9 Configuration Register 2
Port 9 Data Register
I/O
Port
9
P9C1
00
P9C2
00
P9DR
FF
00
CLKCTL
Clock Control Register
101
102
102
86
55
57
RCCU
R242 CLK_FLAG
Clock Flag Register
48, 28 or 08
xx
R246
R249
R250
R251
R252
R253
R254
R255
PLLCONF
WUCTRL
WUMRH
WUMRL
WUTRH
WUTRL
WUPRH
WUPRL
PLL Configuration Register
Wake-Up Control Register
Wake-Up Mask Register High
Wake-Up Mask Register Low
Wake-Up Trigger Register High
Wake-Up Trigger Register Low
Wake-Up Pending Register High
Wake-Up Pending Register Low
00
00
87
00
87
WUIMU
00
88
00
88
00
88
00
88
65/324
9
ST92F120 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
D0R1
D1R1
Channel 0 Data Register
Channel 1 Data Register
Channel 2 Data Register
Channel 3 Data Register
Channel 4 Data Register
Channel 5 Data Register
Channel 6 Data Register
Channel 7 Data Register
Channel 6 Lower Threshold Reg.
Channel 7 Lower Threshold Reg.
Channel 6 Upper Threshold Reg.
Channel 7 Upper Threshold Reg.
Compare Result Register
Control Logic Register
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
0F
00
0F
x2
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
0F
00
0F
x2
283
283
283
283
283
283
283
283
284
284
284
284
284
285
286
286
283
283
283
283
283
283
283
283
284
284
284
284
284
285
286
286
D2R1
D3R1
D4R1
D5R1
D6R1
D7R1
61
A/D 1
LT6R1
LT7R1
UT6R1
UT7R1
CRR1
CLR1
AD_ICR1
AD_IVR1
D0R0
Interrupt Control Register
Interrupt Vector Register
Channel 0 Data Register
Channel 1 Data Register
Channel 2 Data Register
Channel 3 Data Register
Channel 4 Data Register
Channel 5 Data Register
Channel 6 Data Register
Channel 7 Data Register
Channel 6 Lower Threshold Reg.
Channel 7 Lower Threshold Reg.
Channel 6 Upper Threshold Reg.
Channel 7 Upper Threshold Reg.
Compare Result Register
Control Logic Register
D1R0
D2R0
D3R0
D4R0
D5R0
D6R0
D7R0
63
A/D 0
LT6R0
LT7R0
UT6R0
UT7R0
CRR0
CLR0
AD_ICR0
AD_IVR0
Interrupt Control Register
Interrupt Vector Register
Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register
description for details.
66/324
9
ST92F120 - INTERRUPTS
5 INTERRUPTS
5.1 INTRODUCTION
5.2 INTERRUPT VECTORING
The ST9 responds to peripheral and external
events through its interrupt channels. Current pro-
gram execution can be suspended to allow the
ST9 to execute a specific response routine when
such an event occurs, providing that interrupts
have been enabled, and according to a priority
mechanism. If an event generates a valid interrupt
request, the current program status is saved and
control passes to the appropriate Interrupt Service
Routine.
The ST9 implements an interrupt vectoring struc-
ture which allows the on-chip peripheral to identify
the location of the first instruction of the Interrupt
Service Routine automatically.
When an interrupt request is acknowledged, the
peripheral interrupt module provides, through its
Interrupt Vector Register (IVR), a vector to point
into the vector table of locations containing the
start addresses of the Interrupt Service Routines
(defined by the programmer).
The ST9 CPU can receive requests from the fol-
lowing sources:
Each peripheral has a specific IVR mapped within
its Register File pages.
– On-chip peripherals
The Interrupt Vector table, containing the address-
es of the Interrupt Service Routines, is located in
the first 256 locations of Memory pointed to by the
ISR register, thus allowing 8-bit vector addressing.
For a description of the ISR register refer to the
chapter describing the MMU.
– External pins
– Top-Level Pseudo-non-maskable interrupt
According to the on-chip peripheral features, an
event occurrence can generate an Interrupt re-
quest which depends on the selected mode.
The user Power on Reset vector address is speci-
fied in Section 4.2.1. If an external watchdog is
used, refer to Section 4.2.2. If an external watch-
dog is not used, locations 000006h to 000007h
must contain FFFFh for correct operation.
Up to eight external interrupt channels, with pro-
grammable input trigger edge, are available. In ad-
dition, a dedicated interrupt channel, set to the
Top-level priority, can be devoted either to the ex-
ternal NMI pin (where available) to provide a Non-
Maskable Interrupt, or to the Timer/Watchdog. In-
terrupt service routines are addressed through a
vector table mapped in Memory.
The Top Level Interrupt vector is located at ad-
dresses 0004h and 0005h in the segment pointed
to by the Interrupt Segment Register (ISR).
With one Interrupt Vector register, it is possible to
address several interrupt service routines; in fact,
peripherals can share the same interrupt vector
register among several interrupt channels. The
most significant bits of the vector are user pro-
grammable to define the base vector address with-
in the vector table, the least significant bits are
controlled by the interrupt module, in hardware, to
select the appropriate vector.
Figure 30. Interrupt Response
n
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
Note: The first 256 locations of the memory seg-
ment pointed to by ISR can contain program code.
CLEAR
INTERRUPT
PENDING BIT
5.2.1 Divide by Zero Trap
The Divide by Zero trap vector is located at ad-
dresses 0002h and 0003h of each code segment;
it should be noted that for each code segment a
Divide by Zero service routine is required.
IRET
INSTRUCTION
Caution. Although the Divide by Zero Trap oper-
ates as an interrupt, the FLAG Register is not
pushed onto the system Stack automatically. As a
result it must be regarded as a subroutine, and the
service routine must end with the RET instruction
(not IRET).
VR001833
67/324
9
ST92F120 - INTERRUPTS
5.2.2 Segment Paging During Interrupt
Routines
5.3 INTERRUPT PRIORITY LEVELS
The ST9 supports a fully programmable interrupt
priority structure. Nine priority levels are available
to define the channel priority relationships:
The ENCSR bit in the EMR2 register can be used
to select between original ST9 backward compati-
bility mode and ST9+ interrupt management
mode.
– The on-chip peripheral channels and the eight
external interrupt sources can be programmed
within eight priority levels. Each channel has a 3-
bit field, PRL (Priority Level), that defines its pri-
ority level in the range from 0 (highest priority) to
7 (lowest priority).
ST9 Backward Compatibility Mode (ENCSR= 0)
If ENCSR is reset, the CPU works in original ST9
compatibility mode. For the duration of the inter-
rupt service routine, ISR is used instead of CSR,
and the interrupt stack frame is identical to that of
the original ST9: only the PC and Flags are
pushed.
– The 9th level (Top Level Priority) is reserved for
the Timer/Watchdog or the External Pseudo
Non-Maskable Interrupt. An Interrupt service
routine at this level cannot be interrupted in any
arbitration mode. Its mask can be both maskable
(TLI) or non-maskable (TLNM).
This avoids saving the CSR on the stack in the
event of an interrupt, thus ensuring a faster inter-
rupt response time.
It is not possible for an interrupt service routine to
perform inter-segment calls or jumps: these in-
structions would update the CSR, which, in this
case, is not used (ISR is used instead). The code
segment size for all interrupt service routines is
thus limited to 64K bytes.
5.4 PRIORITY LEVEL ARBITRATION
The 3 bits of CPL (Current Priority Level) in the
Central Interrupt Control Register contain the pri-
ority of the currently running program (CPU priori-
ty). CPL is set to 7 (lowest priority) upon reset and
can be modified during program execution either
by software or automatically by hardware accord-
ing to the selected Arbitration Mode.
ST9+ mode (ENCSR = 1)
If ENCSR is set, ISR is only used to point to the in-
terrupt vector table and to initialize the CSR at the
beginning of the interrupt service routine: the old
CSR is pushed onto the stack together with the PC
and flags, and CSR is then loaded with the con-
tents of ISR.
During every instruction, an arbitration phase
takes place, during which, for every channel capa-
ble of generating an Interrupt, each priority level is
compared to all the other requests (interrupts or
DMA).
In this case, iretwill also restore CSR from the
stack. This approach allows interrupt service rou-
tines to access the entire 4 Mbytes of address
space. The drawback is that the interrupt response
time is slightly increased, because of the need to
also save CSR on the stack.
If the highest priority request is an interrupt, its
PRL value must be strictly lower (that is, higher pri-
ority) than the CPL value stored in the CICR regis-
ter (R230) in order to be acknowledged. The Top
Level Interrupt overrides every other priority.
Full compatibility with the original ST9 is lost in this
case, because the interrupt stack frame is differ-
ent.
5.4.1 Priority level 7 (Lowest)
Interrupt requests at PRL level 7 cannot be ac-
knowledged, as this PRL value (the lowest possi-
ble priority) cannot be strictly lower than the CPL
value. This can be of use in a fully polled interrupt
environment.
ENCSR Bit
Mode
0
1
ST9 Compatible
ST9+
5.4.2 Maximum depth of nesting
Pushed/Popped
Registers
PC, FLAGR,
CSR
PC, FLAGR
No more than 8 routines can be nested. If an inter-
rupt routine at level N is being serviced, no other
Interrupts located at level N can interrupt it. This
guarantees a maximum number of 8 nested levels
including the Top Level Interrupt request.
Max. Code Size
for interrupt
service routine
64KB
No limit
Within 1 segment Across segments
5.4.3 Simultaneous Interrupts
If two or more requests occur at the same time and
at the same priority level, an on-chip daisy chain,
specific to every ST9 version, selects the channel
68/324
9
ST92F120 - INTERRUPTS
with the highest position in the chain, as shown in
Table 17
Nested mode improves the effective interrupt re-
sponse time when service routine nesting is re-
quired, depending on the request priority levels.
Table 17. Daisy Chain Priority
The IAM control bit in the CICR Register selects
Concurrent Arbitration mode or Nested Arbitration
Mode.
Highest Position INTA0 / Watchdog Timer
INTA1 / Standard Timer
INTB0 / Extended Function Timer 0
INTB1 / Extended Function Timer 1
INTC0 / EEPROM/Flash
INTC1 / SPI
5.5.1 Concurrent Mode
This mode is selected when the IAM bit is cleared
(reset condition). The arbitration phase, performed
during every instruction, selects the request with
the highest priority level. The CPL value is not
modified in this mode.
INTD0 / RCCU
INTD1 / WKUP MGT
Start of Interrupt Routine
Multifunction Timer 0
The interrupt cycle performs the following steps:
JBLPD
2
I C bus Interface
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
A/D Converter 0
A/D Converter 1
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
Multifunction Timer 1
Serial Communication Interface 0
– If ENCSR is set, CSR is pushed onto system
stack.
Serial Communication Interface 1
Lowest Position
– The Flag register is pushed onto system stack.
5.4.4 Dynamic Priority Level Modification
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
The main program and routines can be specifically
prioritized. Since the CPL is represented by 3 bits
in a read/write register, it is possible to modify dy-
namically the current priority value during program
execution. This means that a critical section can
have a higher priority with respect to other inter-
rupt requests. Furthermore it is possible to priori-
tize even the Main Program execution by modify-
ing the CPL during its execution. See Figure 31.
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwise ISR is used in place of CSR until
iretinstruction.
End of Interrupt Routine
The Interrupt Service Routine must be ended with
the iret instruction. The iret instruction exe-
cutes the following operations:
Figure 31. Example of Dynamic priority
level modification in Nested Mode
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
INTERRUPT 6 HAS PRIORITY LEVEL 6
Priority Level
CPL is set to 7
by MAIN program
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
4
ei
INT6
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
5
6
7
MAIN
CPL is set to 5
– If ENCSR is reset, CSR is used instead of ISR.
CPL6 > CPL5:
INT6 pending
Normal program execution thus resumes at the in-
terrupted instruction. All pending interrupts remain
pending until the next ei instruction (even if it is
executed during the interrupt service routine).
INT 6
CPL=6
MAIN
Note: In Concurrent mode, the source priority level
is only useful during the arbitration phase, where it
is compared with all other priority levels and with
the CPL. No trace is kept of its value during the
ISR. If other requests are issued during the inter-
rupt service routine, once the global CICR.IEN is
CPL=7
5.5 ARBITRATION MODES
The ST9 provides two interrupt arbitration modes:
Concurrent mode and Nested mode. Concurrent
mode is the standard interrupt arbitration mode.
69/324
9
ST92F120 - INTERRUPTS
ARBITRATION MODES (Cont’d)
re-enabled, they will be acknowledged regardless
of the interrupt service routine’s priority. This may
cause undesirable interrupt response sequences.
Example 1
In the first example, (simplest case, Figure 32) the
eiinstruction is not used within the interrupt serv-
ice routines. This means that no new interrupt can
be serviced in the middle of the current one. The
interrupt routines will thus be serviced one after
another, in the order of their priority, until the main
program eventually resumes.
Examples
In the following two examples, three interrupt re-
quests with different priority levels (2, 3 & 4) occur
simultaneously during the interrupt 5 service rou-
tine.
Figure 32. Simple Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected and
- IEN unchanged by the interrupt routines
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
0
1
2
3
4
5
6
7
Priority Level of
Interrupt Request
INT 2
CPL = 7
INT 3
CPL = 7
INT 2
INT 3
INT 4
INT 4
CPL = 7
INT 5
CPL = 7
ei
INT 5
MAIN
MAIN
CPL = 7
CPL is set to 7
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ST92F120 - INTERRUPTS
ARBITRATION MODES (Cont’d)
Example 2
In the second example, (more complex, Figure
33), each interrupt service routine sets Interrupt
Enable with the eiinstruction at the beginning of
the routine. Placed here, it minimizes response
time for requests with a higher priority than the one
being serviced.
ice routines being executed in the opposite order
of their priority.
It is therefore recommended to avoid inserting
the ei instruction in the interrupt service rou-
tine in Concurrent mode. Use the ei instruc-
tion only in nested mode.
The level 2 interrupt routine (with the highest prior-
ity) will be acknowledged first, then, when the ei
instruction is executed, it will be interrupted by the
level 3 interrupt routine, which itself will be inter-
rupted by the level 4 interrupt routine. When the
level 4 interrupt routine is completed, the level 3 in-
terrupt routine resumes and finally the level 2 inter-
rupt routine. This results in the three interrupt serv-
CAUTION: If, in Concurrent Mode, interrupts are
nested (by executing ei in an interrupt service
routine), make sure that either ENCSR is set or
CSR=ISR, otherwise the iretof the innermost in-
terrupt will make the CPU use CSR instead of ISR
before the outermost interrupt service routine is
terminated, thus making the outermost routine fail.
Figure 33. Complex Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected
- IEN set to 1 during interrupt service routine execution
0
Priority Level of
Interrupt Request
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
1
2
3
4
5
6
7
INT 2
INT 2
CPL = 7
CPL = 7
INT 3
CPL = 7
INT 3
CPL = 7
ei
INT 2
INT 3
INT 4
ei
ei
INT 4
CPL = 7
INT 5
INT 5
CPL = 7
CPL = 7
ei
ei
INT 5
MAIN
MAIN
CPL is set to 7
CPL = 7
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9
ST92F120 - INTERRUPTS
ARBITRATION MODES (Cont’d)
5.5.2 Nested Mode
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
The difference between Nested mode and Con-
current mode, lies in the modification of the Cur-
rent Priority Level (CPL) during interrupt process-
ing.
– CPL is saved in the special NICR stack to hold
the priority level of the suspended routine.
– Priority level of the acknowledged routine is
stored in CPL, so that the next request priority
will be compared with the one of the routine cur-
rently being serviced.
The arbitration phase is basically identical to Con-
current mode, however, once the request is ac-
knowledged, the CPL is saved in the Nested Inter-
rupt Control Register (NICR) by setting the NICR
bit corresponding to the CPL value (i.e. if the CPL
is 3, the bit 3 will be set).
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
stack.
The CPL is then loaded with the priority of the re-
quest just acknowledged; the next arbitration cycle
is thus performed with reference to the priority of
the interrupt service routine currently being exe-
cuted.
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
Start of Interrupt Routine
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwise ISR is used in place of CSR until
iretinstruction.
The interrupt cycle performs the following steps:
Figure 34. Simple Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN unchanged by the interrupt routines
Priority Level of
Interrupt Request
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
INT 0
0
1
2
3
4
CPL=0
CPL6 > CPL3:
INT6 pending
INT0
INT 2
CPL=2
INT 2
INT6
CPL=2
INT 3
INT2
CPL=3
INT2
INT3
INT4
INT 4
CPL=4
CPL2 < CPL4:
Serviced next
5
INT 5
CPL=5
ei
6
INT 6
INT5
CPL=6
7
MAIN
CPL is set to 7
MAIN
CPL=7
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9
ST92F120 - INTERRUPTS
ARBITRATION MODES (Cont’d)
End of Interrupt Routine
– If ENCSR is reset, CSR is used instead of ISR,
unless the program returns to another nested
routine.
The iret Interrupt Return instruction executes
the following steps:
The suspended routine thus resumes at the inter-
rupted instruction.
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
Figure 34 contains a simple example, showing that
if the ei instruction is not used in the interrupt
service routines, nested and concurrent modes
are equivalent.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
Figure 35 contains a more complex example
showing how nested mode allows nested interrupt
processing (enabled inside the interrupt service
routinesi using the ei instruction) according to
their priority level.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
– The priority level of the interrupted routine is
popped from the special register (NICR) and
copied into CPL.
Figure 35. Complex Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN set to 1 during the interrupt routine execution
Priority Level of
Interrupt Request
0
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
INT 0
CPL=0
CPL6 > CPL3:
INT6 pending
1
2
3
INT0
INT 2
INT 2
INT 2
INT6
CPL=2
CPL=2
CPL=2
INT 3
ei
INT2
CPL=3
ei
INT2
INT3
INT4
4
5
6
7
INT 4
CPL=4
INT 4
CPL=4
CPL2 < CPL4:
Serviced just after ei
ei
INT 5
CPL=5
INT 5
CPL=5
ei
INT 6
ei
INT5
CPL=6
MAIN
CPL is set to 7
MAIN
CPL=7
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ST92F120 - INTERRUPTS
5.6 EXTERNAL INTERRUPTS
5.6.1 Standard External Interrupts
External
Interrupt
Source
Channel
Internal Interrupt Source
The standard ST9 core contains 8 external inter-
rupts sources grouped into four pairs.
INTA0
INTA1
INTB0
INTB1
INTC0
INTC1
INTD0
INTD1
Timer/Watchdog
Standard Timer
INT0
INT1
INT2
INT3
INT4
INT5
INT6
Table 18. External Interrupt Channel Grouping
External
Extended Function Timer 0
Extended Function Timer 1
EEPROM/Flash
Channel
I/O Port Pin
Interrupt
P8[1:0] P7[7:5]
P6[7,5] P5[7:5, 2:0] P4[7,4]
WKUP[0:15]
INTD1
SPI Interrupt
INT6
INT5
INT4
INT3
INT2
INT1
INT0
INTD0
INTC1
INTC0
INTB1
INTB0
INTA1
INTA0
P6.1
P6.3
P6.2
P6.3
P6.2
P6.0
P6.0
RCCU
Wake-up Management Unit
– The source of interrupt channel A0 can be se-
lected between the external pin INT0 or the
Timer/Watchdog peripheral using the IA0S bit in
the EIVR register (R246 Page 0).
Each source has a trigger control bit TEA0,..TED1
(R242,EITR.0,..,7 Page 0) to select triggering on
the rising or falling edge of the external pin. If the
Trigger control bit is set to “1”, the corresponding
pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page
0) is set on the input pin rising edge, if it is cleared,
the pending bit is set on the falling edge of the in-
put pin. Each source can be individually masked
– The source of interrupt channel A1 can be se-
lected between the external pin INT1 or the
Standard Timer using the INTS bit in the STC
register (R232 Page 11).
– The source of the interrupt channel B0 can be
selected between the external pin INT2 or the
on-chip Extended Function Timer 0 using the
EFTIS bit in the CR3 register (R255 Page 28).
through
the
corresponding
control
bit
IMA0,..,IMD1 (EIMR.7,..,0). See Figure 37.
– The source of interrupt channel B1 can be se-
lected between external pin INT3 or the on-chip
Extended Function Timer 1 using the EFTIS bit
in the CR3 register (R255 Page 29).
Figure 36. Priority Level Examples
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
1
0
0
0
1
0
0
1
EIPLR
– The source of the interrupt channel C0 can be
selected between external pin INT4 or the On-
chip EEPROM/Flash Memory using bit FEIEN
in the ECR register (Address 224001h).
SOURCE PRIORITY
SOURCE PRIORITY
100=4
INT.D0:
INT.A0: 010=2
INT.A1: 011=3
INT.D1: 101=5
– The source of interrupt channel C1 can be se-
lected between external pin INT5 or the on-chip
SPI using the SPIS bit in the SPCR0 register
(R241 Page 7).
INT.C0: 000=0
INT.C1: 001=1
INT.B0: 100=4
INT.B1: 101=5
VR000151
– The source of interrupt channel D0 can be se-
lected between external pin INT6 or the Reset
and Clock Unit RCCU using the INT_SEL bit in
the CLKCTL register (R240 Page 55).
The priority level of the external interrupt sources
can be programmed among the eight priority lev-
els with the control register EIPLR (R245). The pri-
ority level of each pair is software defined using
the bits PRL2,PRL1. For each pair, the even chan-
nel (A0,B0,C0,D0) of the group has the even prior-
ity level and the odd channel (A1,B1,C1,D1) has
the odd (lower) priority level.
– The source of interrupt channel D1 selected be-
tween the NMI pin and the WUIMU Wakeup/In-
terrupt Lines using the ID1S bit in the WUCRTL
register (R248 Page 9).
Caution: When using external interrupt channels
shared by both external interrupts and peripherals,
special care must be taken to configure control
registers both for peripheral and interrupts.
Figure 36 shows an example of priority levels.
Figure 37 gives an overview of the external inter-
rupts and vectors.
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ST92F120 - INTERRUPTS
EXTERNAL INTERRUPTS (Cont’d)
Figure 37. External Interrupts Control Bits and Vectors
Watchdog/Timer
End of count
IA0S
TEA0
V6
V5 V4
V7
0
0
0
X
0
VECTOR
Priority level
“0”
INT A0
request
X
X
Mask bit
Pending bit IPA0
IMA0
“1”
INT 0 pin*
INT 1 pin*
INTS
TEA1
STD Timer
V6
V6
V7
V5 V4 0
0
X
1
VECTOR
“0”
Priority level
INT A1
request
1
X
X
Mask bit
Pending bit IPA1
IMA1
“1”
EFTIS
TEB0
TEB1
TEC0
EFT0 Timer
V7
V5 V4 0
1
X
0
VECTOR
Priority level
“1”
INT B0
request
0
X
X
INT 2 pin*
INT 3 pin*
Mask bit
Pending bit IPB0
IMB0
“0”
EFTIS
EFT1 Timer
V6
V6
V5 V4
V7
0
1
X
1
VECTOR
Priority level
“0”
INT B1
request
1
X
X
“1”
Mask bit
IMB1
Pending bit IPB1
FEIEN
EEPROM/Flash
“1”
“0”
V5 V4
1
V7
0
X
0
VECTOR
Priority level
INT C0
request
0
X
X
INT 4 pin*
Pending bit IPC0
Mask bit
IMC0
SPIS
TEC1
SPI Interrupt
V6
V6
V6
V5 V4 1
V7
0
X
1
VECTOR
“1”
“0”
Priority level
INT C1
request
1
X
X
INT 5 pin*
Pending bit IPC1
Mask bit
IMC1
INT_SEL
RCCU
TED0
V5 V4
V7
1
1
X
0
VECTOR
Priority level
“1”
“0”
INT D0
request
0
X
X
INT 6 pin
Mask bit
IMD0
Pending bit IPD0
ID1S
WKUP
(0:15)
V7
V5 V4 1
1
X
1
VECTOR
Priority level
“1”
“0”
INT D1
request
1
X
X
Wake-up
Controller
Mask bit
IMD1
Pending bit IPD1
TED1
INT 7 pin
Not implemented.
* Only four interrupt pins are available at the same time. Refer to Table 18 for I/O pin mapping.
75/324
9
ST92F120 - INTERRUPTS
5.7 TOP LEVEL INTERRUPT
The Top Level Interrupt channel can be assigned
either to the external pin NMI or to the Timer/
Watchdog according to the status of the control bit
EIVR.TLIS (R246.2, Page 0). If this bit is high (the
reset condition) the source is the external pin NMI.
If it is low, the source is the Timer/ Watchdog End
Of Count. When the source is the NMI external
pin, the control bit EIVR.TLTEV (R246.3; Page 0)
selects between the rising (if set) or falling (if reset)
edge generating the interrupt request. When the
selected event occurs, the CICR.TLIP bit (R230.6)
is set. Depending on the mask situation, a Top
Level Interrupt request may be generated. Two
kinds of masks are available, a Maskable mask
and a Non-Maskable mask. The first mask is the
CICR.TLI bit (R230.5): it can be set or cleared to
enable or disable respectively the Top Level Inter-
rupt request. If it is enabled, the global Enable In-
terrupt bit, CICR.IEN (R230.4) must also be ena-
bled in order to allow a Top Level Request.
Caution. The interrupt machine cycle of the Top
Level Interrupt does not clear the CICR.IEN bit,
and the corresponding iret does not set it. Fur-
thermore the TLI never modifies the CPL bits and
the NICR register.
5.8 ON-CHIP PERIPHERAL INTERRUPTS
The general structure of the peripheral interrupt
unit is described here, however each on-chip pe-
ripheral has its own specific interrupt unit contain-
ing one or more interrupt channels, or DMA chan-
nels. Please refer to the specific peripheral chap-
ter for the description of its interrupt features and
control registers.
The on-chip peripheral interrupt channels provide
the following control bits:
– Interrupt Pending bit (IP). Set by hardware
when the Trigger Event occurs. Can be set/
cleared by software to generate/cancel pending
interrupts and give the status for Interrupt polling.
The second mask NICR.TLNM (R247.7) is a set-
only mask. Once set, it enables the Top Level In-
terrupt request independently of the value of
CICR.IEN and it cannot be cleared by the pro-
gram. Only the processor RESET cycle can clear
this bit. This does not prevent the user from ignor-
ing some sources due to a change in TLIS.
– Interrupt Mask bit (IM). If IM = “0”, no interrupt
request is generated. If IM =“1” an interrupt re-
quest is generated whenever IP = “1” and
CICR.IEN = “1”.
– Priority Level (PRL, 3 bits). These bits define
the current priority level, PRL=0: the highest pri-
ority, PRL=7: the lowest priority (the interrupt
cannot be acknowledged)
The Top Level Interrupt Service Routine cannot be
interrupted by any other interrupt or DMA request,
in any arbitration mode, not even by a subsequent
Top Level Interrupt request.
– Interrupt Vector Register (IVR, up to 7 bits).
The IVR points to the vector table which itself
contains the interrupt routine start address.
Figure 38. Top Level Interrupt Structure
n
WATCHDOG ENABLE
WDGEN
CORE
RESET
TLIP
WATCHDOG TIMER
END OF COUNT
PENDING
TOP LEVEL
MUX
INTERRUPT
REQUEST
MASK
OR
NMI
TLIS
TLTEV
TLNM
TLI
VA00294
IEN
n
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9
ST92F120 - INTERRUPTS
5.9 INTERRUPT RESPONSE TIME
cycles (DIVWS and MUL instructions) or 49 for
other instructions.
The interrupt arbitration protocol functions com-
pletely asynchronously from instruction flow and
requires 5 clock cycles. One more CPUCLK cycle
is required when an interrupt is acknowledged.
Requests are sampled every 5 CPUCLK cycles.
For a non-maskable Top Level interrupt, the re-
sponse time between a user event and the start of
the interrupt service routine can range from a min-
imum of 22 clock cycles to a maximum of 51 clock
cycles (DIV instruction), 49 clock cycles (DIVWS
and MUL instructions) or 45 for other instructions.
If the interrupt request comes from an external pin,
the trigger event must occur a minimum of one
INTCLK cycle before the sampling time.
In order to guarantee edge detection, input signals
must be kept low/high for a minimum of one
INTCLK cycle.
When an arbitration results in an interrupt request
being generated, the interrupt logic checks if the
current instruction (which could be at any stage of
execution) can be safely aborted; if this is the
case, instruction execution is terminated immedi-
ately and the interrupt request is serviced; if not,
the CPU waits until the current instruction is termi-
nated and then services the request. Instruction
execution can normally be aborted provided no
write operation has been performed.
An interrupt machine cycle requires a basic 18 in-
ternal clock cycles (CPUCLK), to which must be
added a further 2 clock cycles if the stack is in the
Register File. 2 more clock cycles must further be
added if the CSR is pushed (ENCSR =1).
The interrupt machine cycle duration forms part of
the two examples of interrupt response time previ-
ously quoted; it includes the time required to push
values on the stack, as well as interrupt vector
handling.
For an interrupt deriving from an external interrupt
channel, the response time between a user event
and the start of the interrupt service routine can
range from a minimum of 26 clock cycles to a max-
imum of 55 clock cycles (DIV instruction), 53 clock
In Wait for Interrupt mode, a further cycle is re-
quired as wake-up delay.
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ST92F120 - INTERRUPTS
5.10 INTERRUPT REGISTERS
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
R230 - Read/Write
Register Group: System
Reset value: 1000 0111 (87h)
the IEN bit when interrupts are disabled or when
no peripheral can generate interrupts. For exam-
ple, if the state of IEN is not known in advance,
and its value must be restored from a previous
push of CICR on the stack, use the sequence DI;
POP CICRto make sure that no interrupts are be-
ing arbitrated when CICR is modified.
7
0
GCEN TLIP TLI
IEN IAM CPL2 CPL1 CPL0
Bit 3 = IAM: Interrupt Arbitration Mode.
This bit is set and cleared by software.
0: Concurrent Mode
Bit 7 = GCEN: Global Counter Enable.
This bit enables the 16-bit Multifunction Timer pe-
ripheral.
1: Nested Mode
0: MFT disabled
1: MFT enabled
Bits 2:0 = CPL[2:0]: Current Priority Level.
These bits define the Current Priority Level.
CPL=0 is the highest priority. CPL=7 is the lowest
priority. These bits may be modified directly by the
interrupt hardware when Nested Interrupt Mode is
used.
Bit 6 = TLIP: Top Level Interrupt Pending.
This bit is set by hardware when Top Level Inter-
rupt (TLI) trigger event occurs. It is cleared by
hardware when a TLI is acknowledged. It can also
be set by software to implement a software TLI.
0: No TLI pending
EXTERNAL INTERRUPT TRIGGER REGISTER
(EITR)
1: TLI pending
R242 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
Bit 5 = TLI: Top Level Interrupt.
This bit is set and cleared by software.
0: A Top Level Interrupt is generared when TLIP is
set, only if TLNM=1 in the NICR register (inde-
pendently of the value of the IEN bit).
1: A Top Level Interrupt request is generated when
IEN=1 and the TLIP bit are set.
7
0
TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0
Bit 7 = TED1: INTD1 Trigger Event
Bit 6 = TED0: INTD0 Trigger Event
Bit 5 = TEC1: INTC1 Trigger Event
Bit 4 = TEC0: INTC0 Trigger Event
Bit 3 = TEB1: INTB1 Trigger Event
Bit 2 = TEB0: INTB0 Trigger Event
Bit 1 = TEA1: INTA1 Trigger Event
Bit 0 = TEA0: INTA0 Trigger Event
Bit 4 = IEN: Interrupt Enable.
This bit is cleared by the interrupt machine cycle
(except for a TLI).
It is set by the iretinstruction (except for a return
from TLI).
It is set by the EIinstruction.
It is cleared by the DI instruction.
0: Maskable interrupts disabled
1: Maskable Interrupts enabled
Note: The IEN bit can also be changed by soft-
ware using any instruction that operates on regis-
ter CICR, however in this case, take care to avoid
spurious interrupts, since IEN cannot be cleared in
the middle of an interrupt arbitration. Only modify
These bits are set and cleared by software.
0: Select falling edge as interrupt trigger event
1: Select rising edge as interrupt trigger event
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9
ST92F120 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT PENDING REGISTER
(EIPR)
R243 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
Bit 3 = IMB1: INTB1 Interrupt Mask
Bit 2 = IMB0: INTB0 Interrupt Mask
Bit 1 = IMA1: INTA1 Interrupt Mask
Bit 0 = IMA0: INTA0 Interrupt Mask
These bits are set and cleared by software.
0: Interrupt masked
7
0
1: Interrupt not masked (an interrupt is generated if
the IPxx and IEN bits = 1)
IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0
Bit 7 = IPD1: INTD1 Interrupt Pending bit
Bit 6 = IPD0: INTD0 Interrupt Pending bit
Bit 5 = IPC1: INTC1 Interrupt Pending bit
Bit 4 = IPC0: INTC0 Interrupt Pending bit
Bit 3 = IPB1: INTB1 Interrupt Pending bit
Bit 2 = IPB0: INTB0 Interrupt Pending bit
Bit 1 = IPA1: INTA1 Interrupt Pending bit
Bit 0 = IPA0: INTA0 Interrupt Pending bit
EXTERNAL INTERRUPT PRIORITY LEVEL
REGISTER (EIPLR)
R245 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
7
0
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
These bits are set by hardware on occurrence of a
trigger event (as specified in the EITR register)
and are cleared by hardware on interrupt acknowl-
edge. They can also be set by software to imple-
ment a software interrupt.
0: No interrupt pending
1: Interrupt pending
Bits 7:6 = PL2D, PL1D: INTD0, D1 Priority Level.
Bits 5:4 = PL2C, PL1C: INTC0, C1 Priority Level.
Bits 3:2 = PL2B, PL1B: INTB0, B1 Priority Level.
Bits 1:0 = PL2A, PL1A: INTA0, A1 Priority Level.
These bits are set and cleared by software.
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for Channels A0, B0, C0 and D0 and
at 1 for Channels A1, B1, C1 and D1.
EXTERNAL INTERRUPT MASK-BIT REGISTER
(EIMR)
R244 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
Hardware
PL2x PL1x
Priority
0 (Highest)
bit
0
1
0
0
1
1
0
1
0
1
1
7
0
0
1
2
3
IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0
0
1
4
5
Bit 7 = IMD1: INTD1 Interrupt Mask
Bit 6 = IMD0: INTD0 Interrupt Mask
Bit 5 = IMC1: INTC1 Interrupt Mask
Bit 4 = IMC0: INTC0 Interrupt Mask
0
1
6
7 (Lowest)
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9
ST92F120 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT VECTOR REGISTER
(EIVR)
0: WAITN pin disabled
1: WAITN pin enabled (to stretch the external
memory access cycle).
R246 - Read/Write
Register Page: 0
Reset value: xxxx 0110b (x6h)
Note: For more details on Wait mode refer to the
section describing the WAITN pin in the External
Memory Chapter.
7
0
V7
V6
V5
V4 TLTEV TLIS IAOS EWEN
NESTED INTERRUPT CONTROL (NICR)
R247 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
Bits 7:4 = V[7:4]: Most significant nibble of Exter-
nal Interrupt Vector.
These bits are not initialized by reset. For a repre-
sentation of how the full vector is generated from
V[7:4] and the selected external interrupt channel,
refer to Figure 37.
7
0
TLNM HL6 HL5 HL4 HL3 HL2 HL1 HL0
Bit 7 = TLNM: Top Level Not Maskable.
This bit is set by software and cleared only by a
hardware reset.
0: Top Level Interrupt Maskable. A top level re-
quest is generated if the IEN, TLI and TLIP bits
=1
Bit 3 = TLTEV: Top Level Trigger Event bit.
This bit is set and cleared by software.
0: Select falling edge as NMI trigger event
1: Select rising edge as NMI trigger event
1: Top Level Interrupt Not Maskable. A top level
request is generated if the TLIP bit =1
Bit 2 = TLIS: Top Level Input Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
(the IA0S bit must be set in this case)
1: NMI is TL interrupt source
Bits 6:0 = HL[6:0]: Hold Level x
These bits are set by hardware when, in Nested
Mode, an interrupt service routine at level x is in-
terrupted from a request with higher priority (other
than the Top Level interrupt request). They are
cleared by hardware at the iretexecution when
the routine at level x is recovered.
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source (the
TLIS bit must be set in this case)
1: External Interrupt pin is INTA0 source
Bit 0 = EWEN: External Wait Enable.
This bit is set and cleared by software.
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5.11 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)
5.11.1 Introduction
5.11.2 Main Features
■ Supports up to 16 additional external wake-up
or interrupt lines
■ Wake-Up lines can be used to wake-up the ST9
The Wake-up/Interrupt Management Unit extends
the number of external interrupt lines from 8 to 23
(depending on the number of external interrupt
lines mapped on external pins of the device). It al-
lows the source of the INTD1 external interrupt
channel to be selected between the INT7 pin
(when available) and up to 16 additional external
Wake-up/interrupt pins.
from STOP mode.
■ Programmable selection of wake-up or interrupt
■ Programmable wake-up trigger edge polarity
■ All Wake-Up Lines maskable
Note: The number of available pins is device de-
pendent. Refer to the device pinout description.
These 16 WKUP pins can be programmed as ex-
ternal interrupt lines or as wake-up lines, able to
exit the microcontroller from low power mode
(STOP mode) (see Figure 1).
Figure 39. Wake-Up Lines / Interrupt Management Unit Block Diagram
INT7
WKUP[7:0]
WKUP[15:8]
NMI
WUTRH
WUTRL
TRIGGERING LEVEL REGISTERS
PENDING REQUEST REGISTERS
MASK REGISTERS
WUPRH
WUMRH
WUPRL
WUMRL
1)
SW SETTING
1
0
WUCTRL
TO CPU
INTD1 - External Interrupt Channel
TO CPU
TO RCCU - Stop Mode Control
Note 1: The reset signal on the Stop bit is stronger than the set signal.
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.11.3 Functional Description
5.11.3.1 Interrupt Mode
able the INT7 external interrupt source and
enable the 16 wake-up lines as external inter-
rupt source lines. This is not mandatory if the
wake-up event does not require an interrupt
response.
To configure the 16 wake-up lines as interrupt
sources, use the following procedure:
1. Configure the mask bits of the 16 wake-up lines
(WUMRL, WUMRH)
7. Write the sequence 1,0,1 to the STOP bit of the
WUCTRL register with three consecutive write
operations. This is the STOP bit setting
sequence.
2. Configure the triggering edge registers of the
wake-up lines (WUTRL, WUTRH)
To detect if STOP Mode was entered or not, im-
mediately after the STOP bit setting sequence,
poll the RCCU EX_STP bit (R242.7, Page 55) and
the STOP bit itself.
3. Set bit 7 of EIMR (R244 Page 0) and EITR
(R242 Page 0) registers of the CPU: so an
interrupt coming from one of the 16 lines can be
correctly acknowledged
4. Reset the WKUP-INT bit in the WUCTRL regis-
ter to disable Wake-up Mode
5.11.3.3 STOP Mode Entry Conditions
5. Set the ID1S bit in the WUCTRL register to dis-
able the INT7 external interrupt source and
enable the 16 wake-up lines as external inter-
rupt source lines.
Assuming the ST9 is in Run mode: during the
STOP bit setting sequence the following cases
may occur:
Case 1: NMI = 0, wrong STOP bit setting se-
quence
To return to standard mode (INT7 external inter-
rupt source enabled and 16 wake-up lines disa-
bled) it is sufficient to reset the ID1S bit.
This can happen if an Interrupt/DMA request is ac-
knowledged during the STOP bit setting se-
quence. In this case polling the STOP and
EX_STP bits will give:
5.11.3.2 Wake-up Mode Selection
STOP = 0, EX_STP = 0
To configure the 16 lines as wake-up sources, use
the following procedure:
This means that the ST9 did not enter STOP mode
due to a bad STOP bit setting sequence: the user
must retry the sequence.
1. Configure the mask bits of the 16 wake-up lines
(WUMRL, WUMRH).
Case 2: NMI = 0, correct STOP bit setting se-
quence
2. Configure the triggering edge registers of the
wake-up lines (WUTRL, WUTRH).
In this case the ST9 enters STOP mode. There are
two ways to exit STOP mode:
3. Set, as for Interrupt Mode selection, bit 7 of
EIMR and EITR registers only if an interrupt
routine is to be executed after a wake-up event.
Otherwise, if the wake-up event only restarts
the execution of the code from where it was
stopped, the INTD1 interrupt channel must be
masked or the external source must be
selected by resetting the ID1S bit.
1. A wake-up interrupt (not an NMI interrupt) is
acknowledged. That implies:
STOP = 0, EX_STP = 1
This means that the ST9 entered and exited STOP
mode due to an external wake-up line event.
4. Since the RCCU can generate an interrupt
request when exiting from STOP mode, take
care to mask it even if the wake-up event is
only to restart code execution.
2. A NMI rising edge woke up the ST9. This
implies:
STOP = 1, EX_STP = 1
This means that the ST9 entered and exited STOP
mode due to an NMI (rising edge) event. The user
should clear the STOP bit via software.
5. Set the WKUP-INT bit in the WUCTRL register
to select Wake-up Mode
6. Set the ID1S bit in the WUCTRL register to dis-
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ST92F120 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
Case 3: NMI = 1 (NMI kept high during the 3rd
write instruction of the sequence), bad STOP
bit setting sequence
STOP = 0, EX_STP = 0
The application can determine why the ST9 did
not enter STOP mode by polling the pending
bits of the external lines (at least one must be at
1).
The result is the same as Case 1:
STOP = 0, EX_STP = 0
This means that the ST9 did not enter STOP mode
due to a bad STOP bit setting sequence: the user
must retry the sequence.
2. Interrupt requests to CPU are enabled: in this
case the ST9 will not enter STOP mode and the
interrupt service routine will be executed. The
status of STOP and EX_STP bits will be again:
Case 4: NMI = 1 (NMI kept high during the 3rd
write instruction of the sequence), correct
STOP bit setting sequence
STOP = 0, EX_STP = 0
The interrupt service routine can determine why
the ST9 did not enter STOP mode by polling
the pending bits of the external lines (at least
one must be at 1).
In this case:
STOP = 1, EX_STP = 0
This means that the ST9 did not enter STOP mode
due to NMI being kept high. The user should clear
the STOP bit via software.
If the MCU really exits from STOP Mode, the
RCCU EX_STP bit is still set and must be reset by
software. Otherwise, if NMI was high or an Inter-
rupt/DMA request was acknowledged during the
STOP bit setting sequence, the RCCU EX_STP bit
is reset. This means that the MCU has filtered the
STOP Mode entry request.
Note: If NMI goes to 0 before resetting the STOP
bit, the ST9 will not enter STOP mode.
Case 5: A rising edge on the NMI pin occurs
during the STOP bit setting sequence.
The NMI interrupt will be acknowledged and the
ST9 will not enter STOP mode. This implies:
The WKUP-INT bit can be used by an interrupt
routine to detect and to distinguish events coming
from Interrupt Mode or from Wake-up Mode, allow-
ing the code to execute different procedures.
STOP = 0, EX_STP = 0
This means that the ST9 did not enter STOP mode
due to an NMI interrupt serviced during the STOP
bit setting sequence. At the end of NMI routine, the
user must re-enter the sequence: if NMI is still high
at the end of the sequence, the ST9 can not enter
STOP mode (See “NMI Pin Management” on
page 4).
To exit STOP mode, it is sufficient that one of the
16 wake-up lines (not masked) generates an
event: the clock restarts after the delay needed for
the oscillator to restart.
The same effect is obtained when a rising edge is
detected on the NMI pin, which works as a 17th
wake-up line.
Case 6: A wake-up event on the external wake-
up lines occurs during the STOP bit setting se-
quence
Note: After exiting from STOP Mode, the software
can successfully reset the pending bits (edge sen-
sitive), even though the corresponding wake-up
line is still active (high or low, depending on the
Trigger Event register programming); the user
must poll the external pin status to detect and dis-
tinguish a short event from a long one (for example
keyboard input with keystrokes of varying length).
There are two possible cases:
1. Interrupt requests to the CPU are disabled: in
this case the ST9 will not enter STOP mode, no
interrupt service routine will be executed and
the program execution continues from the
instruction following the STOP bit setting
sequence. The status of STOP and EX_STP
bits will be again:
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ST92F120 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.11.3.4 NMI Pin Management
– If the ST9 is in Run mode and a rising edge oc-
curs on the NMI pin: the NMI service routine is
executed and then the ST9 restarts the execu-
tion of the main program. Now, suppose that
the user wants to enter STOP mode with NMI
still at 1. The ST9 will not enter STOP mode
and it will not execute an NMI routine be-
cause there were no transitions on the exter-
nal NMI line.
On the CPU side, if TLTEV=1 (Top Level Trigger
Event, bit 3 of register R246, page 0) then a rising
edge on the NMI pin will set the TLIP bit (Top Level
Interrupt Pending bit, R230.6). At this point an in-
terrupt request to the CPU is given either if TL-
NM=1 (Top Level Not Maskable bit, R247.7 - once
set it can only be cleared by RESET) or if TLI=1
and IEN=1 (bits R230.5, R230.4).
– If the ST9 is in run mode and a rising edge on
NMI pin occurs during the STOP bit setting se-
quence: the NMI interrupt will be acknowledged
and the ST9 will not enter STOP mode. At the
end of the NMI routine, the user must re-enter
the sequence: if NMI is still high at the end of the
sequence, the ST9 can not enter STOP mode
(see previous case).
Assuming that the application uses a non-maska-
ble Top Level Interrupt (TLNM=1): in this case,
whenever a rising edge occurs on the NMI pin, the
related service routine will be executed. To service
further Top Level Interrupt Requests, it is neces-
sary to generate a new rising edge on the external
NMI pin.
The following summarizes some typical cases:
– If the ST9 is in run mode and the NMI pin is high:
if NMI is forced low just before the third write in-
struction of the STOP bit setting sequence then
the ST9 will enter STOP mode.
– If the ST9 is in STOP mode and a rising edge on
the NMI pin occurs, the ST9 will exit STOP
mode and the NMI service routine will be exe-
cuted.
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ST92F120 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.11.4 Programming Considerations
9. Poll the wake-up pending bits to determine
which wake-up line caused the exit from STOP
mode.
The following paragraphs give some guidelines for
designing an application program.
10.Clear the wake-up pending bit that was set.
5.11.4.1 Procedure for Entering/Exiting STOP
mode
5.11.4.2 Simultaneous Setting of Pending Bits
1. Program the polarity of the trigger event of
external wake-up lines by writing registers
WUTRH and WUTRL.
It is possible that several simultaneous events set
different pending bits. In order to accept subse-
quent events on external wake-up/interrupt lines, it
is necessary to clear at least one pending bit: this
operation allows a rising edge to be generated on
the INTD1 line (if there is at least one more pend-
ing bit set and not masked) and so to set EIPR.7
bit again. A further interrupt on channel INTD1 will
be serviced depending on the status of bit EIMR.7.
Two possible situations may arise:
2. Check that at least one mask bit (registers
WUMRH, WUMRL) is equal to 1 (so at least
one external wake-up line is not masked).
3. Reset at least the unmasked pending bits: this
allows a rising edge to be generated on the
INTD1 channel when the trigger event occurs
(an interrupt on channel INTD1 is recognized
when a rising edge occurs).
1. The user chooses to reset all pending bits: no
further interrupt requests will be generated on
channel INTD1. In this case the user has to:
4. Select the interrupt source of the INTD1 chan-
nel (see description of ID1S bit in the WUCTRL
register) and set the WKUP-INT bit.
– Reset EIMR.7 bit (to avoid generating a spuri-
ous interrupt request during the next reset op-
eration on the WUPRH register)
5. To generate an interrupt on channel INTD1, bits
EITR.1 (R242.7, Page 0) and EIMR.1 (R244.7,
Page 0) must be set and bit EIPR.7 must be
reset. Bits 7 and 6 of register R245, Page 0
must be written with the desired priority level for
interrupt channel INTD1.
– Reset WUPRH register using a read-modify-
write instruction (AND, BRES, BAND)
– Clear the EIPR.7 bit
– Reset the WUPRL register using a read-mod-
ify-write instruction (AND, BRES, BAND)
6. Reset the STOP bit in register WUCTRL and
the EX_STP bit in the CLK_FLAG register
(R242.7, Page 55). Refer to the RCCU chapter.
2. The user chooses to keep at least one pending
bit active: at least one additional interrupt
request will be generated on the INTD1 chan-
nel. In this case the user has to reset the
desired pending bits with a read-modify-write
instruction (AND, BRES, BAND). This operation
will generate a rising edge on the INTD1 chan-
nel and the EIPR.7 bit will be set again. An
interrupt on the INTD1 channel will be serviced
depending on the status of EIMR.7 bit.
7. To enter STOP mode, write the sequence 1, 0,
1 to the STOP bit in the WUCTRL register with
three consecutive write operations.
8. The code to be executed just after the STOP
sequence must check the status of the STOP
and RCCU EX_STP bits to determine if the ST9
entered STOP mode or not (See “Wake-up
Mode Selection” on page 2 for details). If the
ST9 did not enter in STOP mode it is necessary
to reloop the procedure from the beginning, oth-
erwise the procedure continues from next point.
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ST92F120 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.11.5 Register Description
low, the ST9 will enter STOP mode independently
of the status of the STOP bit.
WAKE-UP CONTROL REGISTER (WUCTRL)
R249 - Read/Write
WARNINGS:
Register Page: 57
Reset Value: 0000 0000 (00h)
– Writing the sequence 1,0,1 to the STOP bit will
enter STOP mode only if no other register write
instructions are executed during the sequence. If
Interrupt or DMA requests (which always perform
register write operations) are acknowledged dur-
ing the sequence, the ST9 will not enter STOP
mode: the user must re-enter the sequence to
set the STOP bit.
7
0
-
-
-
-
-
STOP ID1S WKUP-INT
Bit 2 = STOP: Stop bit.
To enter STOP Mode, write the sequence 1,0,1 to
this bit with three consecutive write operations.
When a correct sequence is recognized, the
STOP bit is set and the RCCU puts the MCU in
STOP Mode. The software sequence succeeds
only if the following conditions are true:
– Whenever a STOP request is issued to the MCU,
a few clock cycles are needed to enter STOP
mode (see RCCU chapter for further details).
Hence the execution of the instruction following
the STOP bit setting sequence might start before
entering STOP mode: if such instruction per-
forms a register write operation, the ST9 will not
enter in STOP mode. In order to avoid to execute
register write instructions after a correct STOP
bit setting sequence and before entering the
STOP mode, it is mandatory to execute 3 NOP
instructions after the STOP bit setting sequence.
– The NMI pin is kept low,
– The WKUP-INT bit is 1,
– All unmasked pending bits are reset
– At least one mask bit is equal to 1 (at least one
external wake-up line is not masked).
Otherwise the MCU cannot enter STOP mode, the
program code continues executing and the STOP
bit remains cleared.
Bit 1 = ID1S: Interrupt Channel INTD1 Source.
This bit is set and cleared by software.
0: INT7 external interrupt source selected, exclud-
ing wake-up line interrupt requests
1: The 16 external wake-up lines enabled as inter-
rupt sources, replacing the INT7 external pin
function
The bit is reset by hardware if, while the MCU is in
STOP mode, a wake-up interrupt comes from any
of the unmasked wake-up lines. The bit is kept
high if, during STOP mode, a rising edge on NMI
pin wakes up the ST9. In this case the user should
reset it by software. The STOP bit is at 1 in the four
following cases (See “Wake-up Mode Selection”
on page 2 for details):
WARNING: To avoid spurious interrupt requests
on the INTD1 channel due to changing the inter-
rupt source, use this procedure to modify the ID1S
bit:
– After the first write instruction of the sequence (a
1 is written to the STOP bit)
1. Mask the INTD1 interrupt channel (bit 7 of reg-
ister EIMR - R244, Page 0 - reset to 0).
– At the end of a successful sequence (i.e. after
the third write instruction of the sequence)
2. Program the ID1S bit as needed.
– The ST9 entered and exited STOP mode due to
a rising edge on the NMI pin. In this case the
EX_STP bit in the CLK_FLAG is at 1 (see
RCCU chapter).
3. Clear the IPD1 interrupt pending bit (bit 7 of
register EIPR - R243, Page 0)
4. Remove the mask on INTD1 (bit EIMR.7=1).
– The ST9 did not enter STOP mode due to the
NMI pin being kept high. In this case RCCU bit
EX_STP is at 0
Bit 0 = WKUP-INT: Wakeup Interrupt.
This bit is set and cleared by software.
0: The 16 external wakeup lines can be used to
generate interrupt requests
1: The 16 external wake-up lines to work as wake-
up sources for exiting from STOP mode
Note: The STOP request generated by the
WUIMU (that allows the ST9 to enter STOP mode)
is ORed with the external STOP pin (active low).
This means that if the external STOP pin is forced
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ST92F120 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
WAKE-UP MASK REGISTER HIGH (WUMRH)
R250 - Read/Write
Register Page: 57
WAKE-UP MASK REGISTER LOW (WUMRL)
R251 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 WUM8
WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1 WUM0
Bit 7:0 = WUM[15:8]: Wake-Up Mask bits.
If WUMx is set, an interrupt on channel INTD1
and/or a wake-up event (depending on ID1S and
WKUP-INT bits) are generated if the correspond-
ing WUPx pending bit is set. More precisely, if
WUMx=1 and WUPx=1 then:
Bit 7:0 = WUM[7:0]: Wake-Up Mask bits.
If WUMx is set, an interrupt on channel INTD1
and/or a wake-up event (depending on ID1S and
WKUP-INT bits) are generated if the correspond-
ing WUPx pending bit is set. More precisely, if
WUMx=1 and WUPx=1 then:
– If ID1S=1 and WKUP-INT=1 then an interrupt on
channel INTD1 and a wake-up event are gener-
ated.
– If ID1S=1 and WKUP-INT=1 then an interrupt on
channel INTD1 and a wake-up event are gener-
ated.
– If ID1S=1 and WKUP-INT=0 only an interrupt on
channel INTD1 is generated.
– If ID1S=1 and WKUP-INT=0 only an interrupt on
channel INTD1 is generated.
– If ID1S=0 and WKUP-INT=1 only a wake-up
event is generated.
– If ID1S=0 and WKUP-INT=1 only a wake-up
event is generated.
– If ID1S=0 and WKUP-INT=0 neither interrupts
on channel INTD1 nor wake-up events are gen-
erated. Interrupt requests on channel INTD1 may
be generated only from external interrupt source
INT7.
– If ID1S=0 and WKUP-INT=0 neither interrupts
on channel INTD1 nor wake-up events are gen-
erated. Interrupt requests on channel INTD1 may
be generated only from external interrupt source
INT7.
If WUMx is reset, no wake-up events can be gen-
erated. Interrupt requests on channel INTD1 may
be generated only from external interrupt source
INT7 (resetting ID1S bit to 0).
If WUMx is reset, no wake-up events can be gen-
erated. Interrupt requests on channel INTD1 may
be generated only from external interrupt source
INT7 (resetting ID1S bit to 0).
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ST92F120 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
WAKE-UP
TRIGGER
REGISTER
HIGH
(WUTRH)
R252 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
WAKE-UP PENDING REGISTER HIGH
(WUPRH)
R254 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
7
0
7
0
WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 WUT8
WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9 WUP8
Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity
Bits
These bits are set and cleared by software.
0: The corresponding WUPx pending bit will be set
on the falling edge of the input wake-up line .
1: The corresponding WUPx pending bit will be set
on the rising edge of the input wake-up line.
Bit 7:0 = WUP[15:8]: Wake-Up Pending Bits
These bits are set by hardware on occurrence of
the trigger event on the corresponding wake-up
line. They must be cleared by software. They can
be set by software to implement a software inter-
rupt.
0: No Wake-up Trigger event occurred
1: Wake-up Trigger event occured
WAKE-UP TRIGGER REGISTER LOW (WUTRL)
R253 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
WAKE-UP PENDING REGISTER LOW (WUPRL)
R255 - Read/Write
Register Page: 57
7
0
Reset Value: 0000 0000 (00h)
WUT7 WUT6 WUT5 WUT4 WUT3 WUT2 WUT1 WUT0
7
0
WUP7 WUP6 WUP5 WUP4 WUP3 WUP2 WUP1 WUP0
Bit 7:0 = WUT[7:0]: Wake-Up Trigger Polarity Bits
These bits are set and cleared by software.
0: The corresponding WUPx pending bit will be set
on the falling edge of the input wake-up line.
1: The corresponding WUPx pending bit will be set
on the rising edge of the input wake-up line.
Bit 7:0 = WUP[7:0]: Wake-Up Pending Bits
These bits are set by hardware on occurrence of
the trigger event on the corresponding wake-up
line. They must be cleared by software. They can
be set by software to implement a software inter-
rupt.
WARNING
1. As the external wake-up lines are edge trig-
gered, no glitches must be generated on these
lines.
0: No Wake-up Trigger event occurred
1: Wake-up Trigger event occured
Note: To avoid losing a trigger event while clear-
ing the pending bits, it is recommended to use
read-modify-write instructions (AND, BRES,
BAND) to clear them.
2. If either a rising or a falling edge on the external
wake-up lines occurs while writing the
WUTRLH or WUTRL registers, the pending bit
will not be set.
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ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
6 ON-CHIP DIRECT MEMORY ACCESS (DMA)
6.1 INTRODUCTION
6.2 DMA PRIORITY LEVELS
The ST9 includes on-chip Direct Memory Access
(DMA) in order to provide high-speed data transfer
between peripherals and memory or Register File.
Multi-channel DMA is fully supported by peripher-
als having their own controller and DMA chan-
nel(s). Each DMA channel transfers data to or
from contiguous locations in the Register File, or in
Memory. The maximum number of bytes that can
be transferred per transaction by each DMA chan-
nel is 222 with the Register File, or 65536 with
Memory.
The 8 priority levels used for interrupts are also
used to prioritize the DMA requests, which are ar-
bitrated in the same arbitration phase as interrupt
requests. If the event occurrence requires a DMA
transaction, this will take place at the end of the
current instruction execution. When an interrupt
and a DMA request occur simultaneously, on the
same priority level, the DMA request is serviced
before the interrupt.
An interrupt priority request must be strictly higher
than the CPL value in order to be acknowledged,
whereas, for a DMA transaction request, it must be
equal to or higher than the CPL value in order to
be executed. Thus only DMA transaction requests
can be acknowledged when the CPL=0.
The DMA controller in the Peripheral uses an indi-
rect addressing mechanism to DMA Pointers and
Counter Registers stored in the Register File. This
is the reason why the maximum number of trans-
actions for the Register File is 222, since two Reg-
isters are allocated for the Pointer and Counter.
Register pairs are used for memory pointers and
counters in order to offer the full 65536 byte and
count capability.
DMA requests do not modify the CPL value, since
the DMA transaction is not interruptable.
Figure 40. DMA Data Transfer
REGISTER FILE
REGISTER FILE
OR
MEMORY
DF
REGISTER FILE
GROUP F
PERIPHERAL
PAGED
COUNTER
ADDRESS
PERIPHERAL
DATA
REGISTERS
0
COUNTER VALUE
TRANSFERRED
DATA
START ADDRESS
VR001834
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ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
6.3 DMA TRANSACTIONS
The purpose of an on-chip DMA channel is to
transfer a block of data between a peripheral and
the Register File, or Memory. Each DMA transfer
consists of three operations:
register, and the DMA Transaction Counter in the
next register (odd address). They are pointed to by
the DMA Transaction Counter Pointer Register
(DCPR), located in the peripheral’s paged regis-
ters. In order to select a DMA transaction with the
Register File, the control bit DCPR.RM (bit 0 of
DCPR) must be set.
– A load from/to the peripheral data register to/
from a location of Register File (or Memory) ad-
dressed through the DMA Address Register (or
Register pair)
If the transaction is made between the peripheral
and Memory, a register pair (16 bits) is required
for the DMA Address and the DMA Transaction
Counter (Figure 42). Thus, two register pairs must
be located in the Register File.
– A post-increment of the DMA Address Register
(or Register pair)
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
The DMA Transaction Counter is pointed to by the
DMA Transaction Counter Pointer Register
(DCPR), the DMA Address is pointed to by the
DMA Address Pointer Register (DAPR),both
DCPR and DAPR are located in the paged regis-
ters of the peripheral.
If the DMA transaction is carried out between the
peripheral and the Register File (Figure 41), one
register is required to hold the DMA Address, and
one to hold the DMA transaction counter. These
two registers must be located in the Register File:
the DMA Address Register in the even address
Figure 41. DMA Between Register File and Peripheral
IDCR
IVR
DAPR
FFh
END OF BLOCK
INTERRUPT
SERVICE ROUTINE
DCPR
PAGED
DATA
REGISTERS
F0h
EFh
PERIPHERAL
PAGED REGISTERS
000100h
000000h
SYSTEM
VECTOR
TABLE
ISR ADDRESS
MEMORY
REGISTERS
E0h
DFh
DMA
TABLE
DATA
ALREADY
TRANSFERRED
DMA
COUNTER
DMA
ADDRESS
REGISTER FILE
90/324
9
ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
DMA TRANSACTIONS (Cont’d)
When selecting the DMA transaction with memory,
bit DCPR.RM (bit 0 of DCPR) must be cleared.
When the Interrupt Pending (IDCR.IP) bit is set by
a hardware event (or by software), and the DMA
Mask bit (IDCR.DM) is set, a DMA request is gen-
erated. If the Priority Level of the DMA source is
higher than, or equal to, the Current Priority Level
(CPL), the DMA transfer is executed at the end of
the current instruction. DMA transfers read/write
data from/to the location pointed to by the DMA
Address Register, the DMA Address register is in-
cremented and the Transaction Counter Register
is decremented. When the contents of the Trans-
action Counter are decremented to zero, the DMA
Mask bit (DM) is cleared and an interrupt request
is generated, according to the Interrupt Mask bit
(End of Block interrupt). This End-of-Block inter-
rupt request is taken into account, depending on
the PRL value.
To selectbetween using theISR orthe DMASR reg-
ister to extend the address, (see Memory Manage-
ment Unit chapter), the control bit DAPR.PS (bit 0
of DAPR) must be cleared or set respectively.
The DMA transaction Counter must be initialized
with the number of transactions to perform and will
be decremented after each transaction. The DMA
Address must be initialized with the starting ad-
dress of the DMA table and is increased after each
transaction. These two registers must be located
between addresses 00h and DFh of the Register
File.
Once a DMA channel is initialized, a transfer can
start. The direction of the transfer is automatically
defined by the type of peripheral and programming
mode.
WARNING. DMA requests are not acknowledged
if the top level interrupt service is in progress.
Once the DMA table is completed (the transaction
counter reaches 0 value), an Interrupt request to
the CPU is generated.
Figure 42. DMA Between Memory and Peripheral
IDCR
IVR
DMA TRANSACTION
DAPR
DCPR
FFh
PAGED
DATA
REGISTERS
F0h
EFh
PERIPHERAL
PAGED REGISTERS
DMA
TABLE
SYSTEM
DATA
ALREADY
REGISTERS
TRANSFERRED
E0h
DFh
END OF BLOCK
INTERRUPT
SERVICE ROUTINE
DMA
TRANSACTION
COUNTER
000100h
000000h
DMA
VECTOR
TABLE
ADDRESS
ISR ADDRESS
MEMORY
REGISTER FILE
n
91/324
9
ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
DMA TRANSACTIONS (Cont’d)
6.4 DMA CYCLE TIME
transfer from two DMA tables alternatively. All the
DMA descriptors in the Register File are thus dou-
bled. Two DMA transaction counters and two DMA
address pointers allow the definition of two fully in-
dependent tables (they only have to belong to the
same space, Register File or Memory). The DMA
transaction is programmed to start on one of the
two tables (say table 0) and, at the end of the
block, the DMA controller automatically swaps to
the other table (table 1) by pointing to the other
DMA descriptors. In this case, the DMA mask (DM
bit) control bit is not cleared, but the End Of Block
interrupt request is generated to allow the optional
updating of the first data table (table 0).
The interrupt and DMA arbitration protocol func-
tions completely asynchronously from instruction
flow.
Requests are sampled every 5 CPUCLK cycles.
DMA transactions are executed if their priority al-
lows it.
A DMA transfer with the Register file requires 8
CPUCLK cycles.
A DMA transfer with memory requires 16 CPUCLK
cycles, plus any required wait states.
6.5 SWAP MODE
Until the swap mode is disabled, the DMA control-
ler will continue to swap between DMA Table 0
and DMA Table 1.
An extra feature which may be found on the DMA
channels of some peripherals (e.g. the MultiFunc-
tion Timer) is the Swap mode. This feature allows
n
92/324
9
ST92F120 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
6.6 DMA REGISTERS
Bit 3 = IM: End of block Interrupt Mask.
This bit is set and cleared by software.
0: No End of block interrupt request is generated
when IP is set
1: End of Block interrupt is generated when IP is
set. DMA requests depend on the DM bit value
as shown in the table below.
As each peripheral DMA channel has its own spe-
cific control registers, the following register list
should be considered as a general example. The
names and register bit allocations shown here
may be different from those found in the peripheral
chapters.
DM IM Meaning
DMA COUNTER POINTER REGISTER (DCPR)
Read/Write
Address set by Peripheral
A DMA request generated without End of Block
1
1
0
0
0
1
0
1
interrupt when IP=1
Reset value: undefined
A DMA request generated with End of Block in-
terrupt when IP=1
7
0
No End of block interrupt or DMA request is
generated when IP=1
C7
C6
C5
C4
C3
C2
C1
RM
An End of block Interrupt is generated without
associated DMA request (not used)
Bit 7:1 = C[7:1]: DMA Transaction Counter Point-
er.
Bit 2:0 = PRL[2:0]: Source Priority Level.
These bits are set and cleared by software. Refer
to Section 6.2 DMA PRIORITY LEVELS for a de-
scription of priority levels.
Software should write the pointer to the DMA
Transaction Counter in these bits.
PRL2 PRL1 PRL0 Source Priority Level
Bit 0 = RM: Register File/Memory Selector.
This bit is set and cleared by software.
0: DMA transactions are with memory (see also
DAPR.DP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 Highest
1
2
1: DMA transactions are with the Register File
3
4
GENERIC EXTERNAL PERIPHERAL INTER-
RUPT AND DMA CONTROL (IDCR)
Read/Write
5
6
7 Lowest
Address set by Peripheral
Reset value: undefined
DMA ADDRESS POINTER REGISTER (DAPR)
Read/Write
7
0
Address set by Peripheral
Reset value: undefined
IP
DM
IM PRL2 PRL1 PRL0
7
0
Bit 5 = IP: Interrupt Pending.
This bit is set by hardware when the Trigger Event
occurs. It is cleared by hardware when the request
is acknowledged. It can be set/cleared by software
in order to generate/cancel a pending request.
0: No interrupt pending
A7
A6
A5
A4
A3
A2
A1
PS
Bit 7:1 = A[7:1]: DMA Address Register(s) Pointer
Software should write the pointer to the DMA Ad-
dress Register(s) in these bits.
1: Interrupt pending
Bit 4 = DM: DMA Request Mask.
Bit 0 = PS: Memory Segment Pointer Selector:
This bit is set and cleared by software. It is only
meaningful if DCPR.RM=0.
0: The ISR register is used to extend the address
of data transferred by DMA (see MMU chapter).
1: The DMASR register is used to extend the ad-
dress of data transferred by DMA (see MMU
chapter).
This bit is set and cleared by software. It is also
cleared when the transaction counter reaches
zero (unless SWAP mode is active).
0: No DMA request is generated when IP is set.
1: DMA request is generated when IP is set
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9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
7 RESET AND CLOCK CONTROL UNIT (RCCU)
7.1 INTRODUCTION
CLOCK2, is the reference input clock to the pro-
grammable Phase Locked Loop frequency multi-
plier, which is capable of multiplying the clock fre-
quency by a factor of 6, 8, 10 or 14; the multiplied
clock is then divided by a programmable divider,
by a factor of 1 to 7. By this means, the ST9 can
operate with cheaper, medium frequency (3-5
MHz) crystals, while still providing a high frequen-
cy internal clock for maximum system perform-
ance; the range of available multiplication and divi-
sion factors allow a great number of operating
clock frequencies to be derived from a single crys-
tal frequency.
The Reset and Clock Control Unit (RCCU) com-
prises two distinct sections:
– The Clock Control Unit, which generates and
manages the internal clock signals.
– The Reset/Stop Manager, which detects and
flags Hardware, Software and Watchdog gener-
ated resets.
On ST9 devices where the external Stop pin is
available, this circuit also detects and manages
the externally triggered Stop mode, during which
all oscillators are frozen in order to achieve the
lowest possible power consumption.
For low power operation, especially in Wait for In-
terrupt mode, the Clock Multiplier unit may be
turned off, whereupon the output clock signal may
be programmed as CLOCK2 divided by 16. For
further power reduction, a low frequency external
clock connected to the CK_AF pin may be select-
ed, whereupon the crystal controlled main oscilla-
tor may be turned off.
7.2 CLOCK CONTROL UNIT
The Clock Control Unit generates the internal
clocks for the CPU core (CPUCLK) and for the on-
chip peripherals (INTCLK). The Clock Control Unit
may be driven by an external crystal circuit, con-
nected to the OSCIN and OSCOUT pins, or by an
external pulse generator, connected to OSCIN
(see Figure 49 and Figure 51). A low frequency ex-
ternal clock may be connected to the CK_AF pin,
and this clock source may be selected when low
power operation is required.
The internal system clock, INTCLK, is routed to all
on-chip peripherals, as well as to the programma-
ble Clock Prescaler Unit which generates the clock
for the CPU core (CPUCLK). (See Figure 43)
The Clock Prescaler is programmable and can
slow the CPU clock by a factor of up to 8, allowing
the programmer to reduce CPU processing speed,
and thus power consumption, while maintaining a
high speed clock to the peripherals. This is partic-
ularly useful when little actual processing is being
done by the CPU and the peripherals are doing
most of the work.
7.2.1 Clock Control Unit Overview
As shown in Figure 43 a programmable divider
can divide the CLOCK1 input clock signal by two.
In practice, the divide-by-two is virtually always
used in order to ensure a 50% duty cycle signal to
the PLL multiplier circuit. The resulting signal,
94/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 43. ST92F120 Clock Distribution Diagram
1...8
Baud Rate
Generator
1/2
Conversion time
138 * INTCLK
SCK
Master
1/N
N=2,4,16,32
A/Dx
SCK
Slave
LOGIC
(Max INTCLK/2)
SPI
Baud Rate
Generator
N=2,4,8
1/N
1/N
N=2...(216-1)
EXTCLKx
(Max INTCLK/4)
SCIx
EFTx
1...64
1...256
1/3
TxINA/TxINB
(Max INTCLK/3)
MFTx
JBLPD
1...256
N=4,6,8...258
STD
FAST
1/4
1/N
Fscl ≤100 kHz
Fscl > 100 kHz
Fscl ≤ 400 kHz
WDG
1/N
N=6,9,12...387
P6.5
I²C
1...256
1...8
1/4
CPUCLK
3-bit Prescaler
STIM
CPU
1/16
P9.6
P6.0
EMBEDDED MEMORY
1/8
CK_128
INTCLK
1/4
XT_DIV16
0
1
RAM
1/16
EPROM
FLASH
CSU_CKSEL
MX(1:0)
DIV2
0
1
EEPROM
Quartz
Oscillator
PLL
x
0
1
1/ N
1/2
CLOCK2
6/8/10/14
DX(2:0)
RCCU
95/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.3 CLOCK MANAGEMENT
The various programmable features and operating modes of the CCU are handled by four registers:
– MODER (Mode Register)
This is a System Register (R235, Group E).
– CLK_FLAG (Clock Flag Register)
This is a Paged Register (R242, Page 55).
The input clock divide-by-two and the CPU clock
prescaler factors are handled by this register.
This register contains various status flags, as
well as control bits for clock selection.
– CLKCTL (Clock Control Register)
This is a Paged Register (R240, Page 55).
– PLLCONF (PLL Configuration Register)
This is a Paged Register (R246, Page 55).
The low power modes and the interpretation of
the HALT instruction are handled by this register.
The PLL multiplication and division factors are
programmed in this register.
Figure 44. Clock Control Unit Programming
n
DIV2
(MODER)
CSU_CKSEL
(CLK_FLAG)
CKAF_SEL
(CLKCTL)
XTSTOP
(CLK_FLAG)
1/16
1/4
CLK_128
0
INTCLK
0
1
0
1
0
1
PLL
x
6/8/10/14
1
to
1/N
Quartz
Peripherals
CPU Clock Prescaler
and P6.5
CLOCK2
1/2
oscillator
CLOCK1
CK_AF
CK_AF
source
(available only if mapped on ext. pin)
MX(1:0)
DX(2:0)
XT_DIV16
CKAF_ST
(PLLCONF)
(CLK_FLAG)
Wait for Interrupt and Low Power Modes:
LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode.
WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode.
XTSTOP (CLK_FLAG) automatically stops the Xtal oscillator when the CK_AF clock is present and selected.
96/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont’d)
7.3.1 PLL Clock Multiplier Programming
The internal peripherals are not affected by the
CPUCLK prescaler and continue to operate at the
full INTCLK frequency. This is particularly useful
when little processing is being done and the pe-
ripherals are doing most of the work.
The CLOCK1 signal generated by the oscillator
drives a programmable divide-by-two circuit. If the
DIV2 control bit in MODER is set (Reset Condi-
tion), CLOCK2, is equal to CLOCK1 divided by
two; if DIV2 is reset, CLOCK2 is identical to
CLOCK1. Since the input clock to the Clock Multi-
plier circuit requires a 50% duty cycle for correct
PLL operation, the divide by two circuit should be
enabled when a crystal oscillator is used, or when
the external clock generator does not provide a
50% duty cycle. In practice, the divide-by-two is
virtually always used in order to ensure a 50% duty
cycle signal to the PLL multiplier circuit.
The prescaler divides the input clock by the value
programmed in the control bits PRS2,1,0 in the
MODER register. If the prescaler value is zero, no
prescaling takes place, thus CPUCLK has the
same period and phase as INTCLK. If the value is
different from 0, the prescaling is equal to the val-
ue plus one, ranging thus from two (PRS2,1,0 = 1)
to eight (PRS2,1,0 = 7).
The clock generated is shown in Figure 45, and it
will be noted that the prescaling of the clock does
not preserve the 50% duty cycle, since the high
level is stretched to replace the missing cycles.
When the PLL is active, it multiplies CLOCK2 by 6,
8, 10 or 14, depending on the status of the MX0 -1
bits in PLLCONF. The multiplied clock is then di-
vided by a factor in the range 1 to 7, determined by
the status of the DX0-2 bits; when these bits are
programmed to 111, the PLL is switched off.
This is analogous to the introduction of wait cycles
for access to external memory. When External
Memory Wait or Bus Request events occur, CPU-
CLK is stretched at the high level for the whole pe-
riod required by the function.
Following a RESET phase, programming bits
DX0-2 to a value different from 111 will turn the
PLL on. To select the multiplier clock, set the
CSU_CKSEL bit in the CLK_FLAG Register after
allowing a stabilisation period for the PLL.
Figure 45. CPU Clock Prescaling
n
INTCLK
Care is required, when programming the PLL mul-
tiplier and divider factors, not to exceed the maxi-
mum permissible operating frequency for INTCLK,
according to supply voltage, as reported in Electri-
cal Characteristics section.
PRS VALUE
000
001
010
011
The ST9 being a static machine, there is no lower
limit for INTCLK. However, some peripherals have
their own minimum internal clock frequency limit
below which the functionality is not guaranteed.
CPUCLK
100
7.3.2 CPU Clock Prescaling
101
110
111
The system clock, INTCLK, which may be the out-
put of the PLL clock multiplier, CLOCK2, CLOCK2/
16 or CK_AF, drives a programmable prescaler
which generates the basic time base, CPUCLK,
for the instruction executer of the ST9 CPU core.
This allows the user to slow down program execu-
tion during non processor intensive routines, thus
reducing power dissipation.
VA00260
97/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont’d)
7.3.3 Peripheral Clock
tal oscillator will be stopped automatically on en-
tering WFI if the WFI_CKSEL bit has been set. It
should be noted that selecting a non-existent
CK_AF clock source is impossible, since such a
selection requires that the auxiliary clock source
be actually present and selected. In no event can
a non-existent clock source be selected inadvert-
ently.
The system clock, INTCLK, which may be the out-
put of the PLL clock multiplier, CLOCK2, CLOCK2/
16 or CK_AF, is also routed to all ST9 on-chip pe-
ripherals and acts as the central timebase for all
timing functions.
7.3.4 Low Power Modes
The user can select an automatic slowdown of
clock frequency during Wait for Interrupt opera-
tion, thus idling in low power mode while waiting
for an interrupt. In WFI operation the clock to the
CPU core is stopped, thus suspending program
execution, while the clock to the peripherals may
be programmed as described in the following par-
agraphs. Two examples of Low Power operation in
WFI are illustrated in Figure 46 and Figure 47.
It is up to the user program to switch back to a fast-
er clock on the occurrence of an interrupt, taking
care to respect the oscillator and PLL stabilisation
delays, as appropriate.
It should be noted that any of the low power modes
may also be selected explicitly by the user pro-
gram even when not in Wait for Interrupt mode, by
setting the appropriate bits.
7.3.5 Interrupt Generation
Providing that low power operation during Wait for
Interrupt is enabled (by setting the LPOWFI bit in
the CLKCTL Register), as soon as the CPU exe-
cutes the WFI instruction, the PLL is turned off and
the system clock will be forced to CLOCK2 divided
by 16, or to the external low frequency clock,
CK_AF, if this has been selected by setting
WFI_CKSEL, and providing CKAF_ST is set, thus
indicating that the external clock is selected and
actually present on the CK_AF pin.
System clock selection modifies the CLKCTL and
CLK_FLAG registers.
The clock control unit generates an external inter-
rupt request when CK_AF and CLOCK2/16 are
selected or deselected as system clock source, as
well as when the system clock restarts after a
hardware stop (when the STOP MODE feature is
available on the specific device). This interrupt can
be masked by resetting the INT_SEL bit in the
CLKCTL register. Note that this is the only case in
the ST9 where an interrupt is generated with a
high to low transition.
If the external clock source is used, the crystal os-
cillator may be stopped by setting the XTSTOP bit,
providing that the CK_AK clock is present and se-
lected, indicated by CKAF_ST being set. The crys-
Table 20. Summary of Operating Modes using main Crystal Controlled Oscillator
MODE
INTCLK
CPUCLK DIV2 PRS0-2 CSU_CKSEL MX0-1 DX2-0 LPOWFI XT_DIV16
XTAL/2
x (14/D)
PLL x BY 14
INTCLK/N
INTCLK/N
INTCLK/N
INTCLK/N
1
1
1
1
N-1
N-1
N-1
N-1
1
1
1
1
1 0
0 0
1 1
0 1
D-1
D-1
D-1
D-1
X
X
X
X
1
1
1
1
XTAL/2
x (10/D)
PLL x BY 10
PLL x BY 8
PLL x BY 6
XTAL/2
x (8/D)
XTAL/2
x (6/D)
SLOW 1
SLOW 2
XTAL/2
INTCLK/N
INTCLK/N
1
1
N-1
N-1
X
X
X
X
111
X
X
X
1
0
XTAL/32
WAIT FOR
INTERRUPT
If LPOWFI=0, no changes occur on INTCLK ,but CPUCLK is stopped anyway.
LOW POWER
WAIT FOR
INTERRUPT
XTAL/32
XTAL/2
STOP
1
1
X
0
X
0
X
X
1
0
1
1
RESET
INTCLK
00
111
EXAMPLE
XTAL=4.4 MHz
2.2*10/2
= 11MHz
11MHz
1
0
1
00
001
X
1
98/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 46. Example of Low Power mode programming in WFI using CK_AF external clock
n
INTCLK FREQUENCY
PROGRAM FLOW
F
= 4 MHz, V = 4.5 V min
DD
Xtal
Begin
Reset State
PLL multiply factor
set to 10
MX(1:0) ← 00
DX2-0 ← 000
WAIT
Divider factor set
to 1, and PLL turned ON
2 MHz
Wait for the PLL to lock
T
*
PLK
CSU_CKSEL ←
system clock source
PLL is
1
CK_AF clock selected
in WFI state
WFI_CKSEL ← 1
XTSTOP ← 1
Preselect Xtal stopped
when CK_AF selected
Low Power Mode enabled
in WFI state
LPOWFI ← 1
20 MHz
User’s Program
Wait For Interrupt
activated
CK_AF selected and Xtal stopped
automatically
WFI instruction
WFI status
No code is executed until
an interrupt is requested
Interrupt
Interrupt serviced
while CK_AF is
Interrupt Routine
the System Clock
and the Xtal restarts
XTSTOP ← 0
F
CK_AF
Wait for the Xtal
to stabilise
WAIT
T
**
STUP
The System Clock
switches to Xtal
CKAF_SEL ← 0
Wait for the PLL to lock
WAIT
2 MHz
CSU_CKSEL ← 1
System Clock source
PLL is
User’s Program
Execution of user program
resumes at full speed
20 MHz
* T
= PLL lock-in time
PLK
** T
= Quartz oscillator start-up time
STUP
99/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 47. Example of Low Power mode programming in WFI using CLOCK2/16
n
INTCLK FREQUENCY
PROGRAM FLOW
F
= 4 MHz, V = 2.7 V min
Xtal
DD
Begin
Reset State
PLL multiply factor
set to 6
MX(1:0) ← 01
DX2-0 ← 000
Divider factor set
to 1, and PLL turned ON
2 MHz
Wait for the PLL to lock
WAIT
T
*
PLK
CSU_CKSEL ←
system clock source
PLL is
1
Low Power Mode enabled
in WFI state
LPOWFI ← 1
User’s Program
12 MHz
Wait For Interrupt
activated
CLOCK2/16 selected and PLL
automatically
WFI instruction
stopped
No code is executed until
an interrupt is requested
WFI status
Interrupt
125 kHz
Interrupt Routine
Interrupt serviced
PLL switched on
CLOCK2 selected
WAIT
Wait for the PLL to lock
T
*
2 MHz
PLK
system clock source
PLL is
CSU_CKSEL ← 1
User’s Program
Execution of user program
resumes at full speed
12 MHz
* T
= PLL lock-in time
PLK
100/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.4 CLOCK CONTROL REGISTERS
MODE REGISTER (MODER)
R235 - Read/Write
System Register
CLOCK CONTROL REGISTER (CLKCTL)
R240 - Read Write
Register Page: 55
Reset Value: 1110 0000 (E0h)
Reset Value: 0000 0000 (00h)
0
7
7
0
INT_SE
L
SRE- CKAF_S WFI_CKS LPOW-
-
-
DIV2 PRS2 PRS1 PRS0
-
-
0
0
0
SEN
EL
EL
FI
*Note: This register contains bits which relate to
other functions; these are described in the chapter
dealing with Device Architecture. Only those bits
relating to Clock functions are described here.
Bit 7 = INT_SEL: Interrupt Selection.
0: The external interrupt channel input signal is se-
lected (Reset state)
1: Select the internal RCCU interrupt as the source
of the interrupt request
Bit 5 = DIV2: OSCIN Divided by 2.
This bit controls the divide by 2 circuit which oper-
ates on the OSCIN Clock.
0: No division of the OSCIN Clock
1: OSCIN clock is internally divided by 2
Bits 4:6 = Reserved for test purposes
Must be kept reset for normal operation.
Bit 3 = SRESEN: Software Reset Enable.
0: The HALT instruction turns off the quartz, the
PLL and the CCU
Bits 4:2 = PRS[2:0]: Clock Prescaling.
These bits define the prescaler value used to pres-
cale CPUCLK from INTCLK. When these three
bits are reset, the CPUCLK is not prescaled, and is
equal to INTCLK; in all other cases, the internal
clock is prescaled by the value of these three bits
plus one.
1: A Reset is generated when HALT is executed
Bit 2 = CKAF_SEL: Alternate Function Clock Se-
lect.
0: CK_AF clock not selected
1: Select CK_AF clock
Note: To check if the selection has actually oc-
curred, check that CKAF_ST is set. If no clock is
present on the CK_AF pin, the selection will not
occur.
Bit 1 = WFI_CKSEL: WFI Clock Select.
This bit selects the clock used in Low power WFI
mode if LPOWFI = 1.
0: INTCLK during WFI is CLOCK2/16
1: INTCLK during WFI is CK_AF, providing it is
present. In effect this bit sets CKAF_SEL in WFI
mode
Caution: When the CK_AF is selected as Low
Power WFI clock but the XTAL is not turned off
(R242.4 = 0), after exiting from the WFI, CK_AF
will be still selected as system clock. In this case,
reset the R240.2 bit to switch back to the XT.
Bit 0 = LPOWFI: Low Power mode during Wait For
Interrupt.
0: Low Power mode during WFI disabled. When
WFI is executed, the CPUCLK is stopped and
INTCLK is unchanged
1: The ST9 enters Low Power mode when the WFI
instruction is executed. The clock during this
state depends on WFI_CKSEL
101/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
CLOCK FLAG REGISTER (CLK_FLAG)
R242 -Read/Write
Register Page: 55
Reset Value: 01001000 after a Watchdog Reset
Reset Value: 00101000 after a Software Reset
Reset Value: 00001000 after a Power-On Reset
Take care, as any operation such as a subsequent
AND with `1' or an OR with `0' to the XTSTOP bit
will reset it and the oscillator will not be stopped
even if CKAF_ST is subsequently set.
Bit 3 = XT_DIV16: CLOCK/16 Selection.
This bit is set and cleared by software. An interrupt
is generated when the bit is toggled.
7
0
0: CLOCK2/16 is selected and the PLL is off
1: The input is CLOCK2 (or the PLL output de-
pending on the value of CSU_CKSEL)
XT_
CSU_
EX_ STP WDGRES SOFTRES XTSTOP
CKAF_ST LOCK
DIV16
CKSEL
CAUTION: After this bit is modified from 0 to 1,
take care that the PLL lock-in time has elapsed be-
fore setting the CSU_CKSEL bit.
CAUTION: If this register is accessed with a logi-
cal instruction, such as AND or OR, some bits may
not be set as expected.
Bit 2 = CKAF_ST: (Read Only)
CAUTION: If you select the CK_AF as system
clock and turn off the oscillator (bits R240.2 and
R242.4 at 1), and then switch back to the XT clock
by resetting the R240.2 bit, you must wait for the
If set, indicates that the alternate function clock
has been selected. If no clock signal is present on
the CK_AF pin, the selection will not occur. If re-
set, the PLL clock, CLOCK2 or CLOCK2/16 is se-
lected (depending on bit 0).
oscillator to restart correctly (T
cal Characteristics section).
refer to Electri-
STUP
Bit 7 = EX_STP: External Stop flag.
This bit is set by hardware and cleared by soft-
ware.
0: No External Stop condition occurred
1: External Stop condition occurred
Bit 1= LOCK: PLL locked-in
This bit is read only.
0: The PLL is turned off or not locked and cannot
be selected as system clock source.
1: The PLL is locked
Bit 6 = WDGRES: Watchdog reset flag.
This bit is read only.
0: No Watchdog reset occurred
Bit 0 = CSU_CKSEL: CSU Clock Select.
This bit is set and cleared by software. It is also
cleared by hardware when:
1: Watchdog reset occurred
– bits DX[2:0] (PLLCONF) are set to 111;
– the quartz is stopped (by hardware or software);
– WFI is executed while the LPOWFI bit is set;
– the XT_DIV16 bit (CLK_FLAG) is forced to ’0’.
Bit 5 = SOFTRES: Software Reset Flag.
This bit is read only.
0: No software reset occurred
1: Software reset occurred (HALT instruction)
This prevents the PLL, when not yet locked, from
providing an irregular clock. Furthermore, a ‘0’
stored in this bit speeds up the PLL’s locking.
Bit 4 = XTSTOP: External Stop Enable.
0: External stop disabled
0: CLOCK2 provides the system clock
1: The PLL Multiplier provides the system clock.
1: The Xtal oscillator will be stopped as soon as
the CK_AF clock is present and selected,
whether this is done explicitly by the user pro-
gram, or as a result of WFI, if WFI_CKSEL has
previously been set to select the CK_AF clock
during WFI.
NOTE: Setting the CKAF_SEL bit overrides any
other clock selection. Resetting the XT_DIV16 bit
overrides the CSU_CKSEL selection (see Figure
44).
CAUTION: When the program writes ‘1’ to the XT-
STOP bit, it will still be read as 0 and is only set
when the CK_AF clock is running (CKAF_ST=1).
102/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
Table 21. PLL Multiplication Factors
PLL CONFIGURATION REGISTER (PLLCONF)
R246 - Read/Write
Register Page: 55
MX1
MX0
CLOCK2 x
1
0
1
0
0
0
1
1
14
10
8
Reset Value: xx00x111 (xxh)
7
0
6
-
-
MX1 MX0
-
DX2 DX1 DX0
Table 22. PLL Divider Factors
DX2
0
DX1
0
DX0
0
CK
Bits 5:4 = MX[1:0]: PLL Multiplication Factor.
Refer to Table 21 for multiplier settings.
PLL CLOCK/1
PLL CLOCK/2
PLL CLOCK/3
PLL CLOCK/4
PLL CLOCK/5
PLL CLOCK/6
PLL CLOCK/7
0
0
1
CAUTION: After these bits are modified, take care
that the PLL lock-in time has elapsed before set-
ting the CSU_CKSEL bit in the CLK_FLAG regis-
ter.
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Bits 2:0 = DX[2:0]: PLL output clock divider factor.
Refer to Table 22 for divider settings.
CLOCK2
(PLL OFF, Reset State)
1
1
1
Figure 48. RCCU General Timing
User program execution
PLL switched on by user
PLL selected by user
Boot ROM execution
Reset phase
20µs
< 4µs
RESET
Internal
Reset
CLOCK2
PLL Multiplier
Clock
Internal
Reset
INTCLK
T
PLL Lock-in Time
RSPH
Exit from RESET
VR02113B
103/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.5 OSCILLATOR CHARACTERISTICS
The on-chip oscillator circuit uses an inverting gate
circuit with tri-state output.
Table 23. R Crystal Specification
S
C =C
33pF
22pF
1
2
Freq.
5 MHz
4 MHz
3 MHz
80 ohm
130 ohm
250 ohm
130 ohm
200 ohm
-
OSCOUT must not be used to drive external cir-
cuits.
When the oscillator is stopped, OSCOUT goes
high impedance.
In Halt mode, set by means of the HALT instruc-
tion, the parallel resistor, R, is disconnected and
the oscillator is disabled, forcing the internal clock,
CLOCK1, to a high level, and OSCOUT to a high
impedance state.
Legend:
C , C : Maximum Total Capacitances on pins OSCIN and
1
2
OSCOUT (the value includes the external capacitance
tied to the pin plus the parasitic capacitance of the board
and of the device)
Note: The tables are relative to the fundamental quartz
crystal only (not ceramic resonator).
To exit the HALTcondition and restart the oscilla-
tor, an external RESET pulse is required, having a
a minimum duration of 20µs, as illustrated in Fig-
ure 54.
Figure 50. Internal Oscillator Schematic
It should be noted that, if the Watchdog function is
enabled, a HALTinstruction will not disable the os-
cillator. This to avoid stopping the Watchdog if a
HALTcode is executed in error. When this occurs,
the CPU will be reset when the Watchdog times
out or when an external reset is applied.
HALT
REF
Figure 49. Crystal Oscillator
OSCOUT
CRYSTAL CLOCK
CLOCK
OSCIN
INPUT
BUFFER
ST9
OSCOUT
OSCIN
VR02086A
Figure 51. External Clock
n
C
C
2
1
EXTERNAL CLOCK
1 MΩ *
*Recommended for oscillator stability
3.3 kΩ
VR02116A
OSCOUT
ST9
INPUT
CLOCK
OSCIN
VR02116B
104/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
CERAMIC RESONATORS
Murata Electronics CERALOCK resonators have been tested with the ST92F120 at 3, 3.68, 4 and 5 MHz.
Some resonators have built-in capacitors (see Table 24).
The test circuit is shown in Figure .
Figure 52. Test Circuit
ST92F120
V
DD
V
OSCIN
OSCOUT
SS
Rp
Rd
CERALOCK
V1
V2
C1 C2
Table 24 shows the recommended conditions at different frequencies.
Table 24. Obtained Results
Freq.
Parts Number
C1 (PF)
C2 (PF)
Rp (Ohm)
Rd (Ohm)
(MHz)
CSA3.00MG
CST3.00MGW
CSA3.68MG
30
(30)
30
30
(30)
30
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
0
0
0
0
0
0
0
0
0
0
0
3
3.68
4
CST3.68MGW
CSTCC3.68MG
CSA4.00MG
(30)
(15)
30
(30)
(15)
30
CST4.00MGW
CSTCC4.00MG
CSA5.00MG
(30)
(15)
30
(30)
(15)
30
5
CST5.00MGW
CSTCC5.00MG
(30)
(15)
(30)
(15)
Advantages of using ceramic resonators:
Test conditions:
CST and CSTCC types have built-in loading ca-
pacitors (those with values shown in parentheses
()).
The evaluation conditions are 4.5 to 5.5 V for the
supply voltage and -40° to 105° C for the tempera-
ture range.
Rp is always open in the previous table because
there is no need for a parallel resistor with a reso-
nator (it is needed only with a crystal).
Caution:
The above circuit condition is for design reference
only.
Recommended C1, C2 value depends on the cir-
cuit board used.
105/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.6 RESET/STOP MANAGER
The Reset/Stop Manager resets the MCU when
one of the three following events occurs:
TRES or the WDGRES bits respectively; a hard-
ware initiated reset will leave both these bits reset.
– A Hardware reset, initiated by a low level on the
Reset pin.
The hardware reset overrides all other conditions
and forces the ST9 to the reset state. During Re-
set, the internal registers are set to their reset val-
ues (when these reset values are defined, other-
wise the register content will remain unchanged),
and the I/O pins are set to Bidirectional Weak-Pull-
Up or High impedance input. See Section 1.3.
– A Software reset, initiated by a HALT instruction
(when enabled).
– A Watchdog end of count condition.
The event which caused the last Reset is flagged
in the CLK_FLAG register, by setting the SOF-
Reset is asynchronous: as soon as the reset pin is
driven low, a Reset cycle is initiated.
Figure 53. Oscillator Start-up Sequence and Reset Timing
V
V
MAX
MIN
DD
DD
OSCIN
T
STUP
INTCLK
RESET
PIN
VR02085A
Note: For T
value refer to Oscillator Electrical Characteristics
STUP
106/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
RESET/STOP MANAGER (Cont’d)
The on-chip Timer/Watchdog generates a reset
condition if the Watchdog mode is enabled
(WCR.WDGEN cleared, R252 page 0), and if the
programmed period elapses without the specific
code (AAh, 55h) written to the appropriate register.
The input pin RESET is not driven low by the on-
chip reset generated by the Timer/Watchdog.
50 ns on the Reset pin. The device is certain to re-
set if a negative pulse of more than 20µs is ap-
plied. When the reset pin goes high again, a delay
of up to 4µs will elapse before the RCCU detects
this rising front. From this event on, a defined
number of CLOCK1 cycles (refer to T
) is
RSPH
counted before exiting the Reset state
(±1CLOCK1 period depending on the delay be-
tween the positive edge the RCCU detects and the
first rising edge of CLOCK1)
When theResetpingoeshighagain, adeterministic
number of oscillator clock cycles (CLOCK1) is
counted (refer to T
) before exiting the Reset
RSPH
If the ST9 is a ROMLESS version, without on-chip
program memory, the memory interface ports are
set to external memory mode (i.e Alternate Func-
tion) and the memory accesses are made to exter-
nal Program memory with wait cycles insertion.
state (±1 CLOCK1 period, depending on the delay
betweentherising edgeoftheResetpinandthe first
rising edge ofCLOCK1). Subsequentlya shortBoot
routine is executed from the device internal Boot
memory, and control then passes to the user pro-
gram.
Figure 54. Recommended Signal to be Applied
on Reset Pin
The Boot routine sets the device characteristics
and loads the correct values in the Memory Man-
agement Unit’s pointer registers, so that these
point to the physical memory areas as mapped in
the specific device. The precise duration of this
short Boot routine varies from device to device,
depending on the Boot memory contents.
V
RESETN
V
DD
V
IHRS
At the end of the Boot routine the Program Coun-
ter will be set to the location specified in the Reset
Vector located in the lowest two bytes of memory.
V
ILRS
7.6.1 Reset Pin Timing
To improve the noise immunity of the device, the
Reset pin has a Schmitt trigger input circuit with
hysteresis. In addition, a filter will prevent an un-
wanted reset in case of a single glitch of less than
Figure 55. Reset Pin Input Structure
20µs
Minimum
PIN
SCHMITT TRIGGER and LOW
PASS FILTER
TO GENERATE RESET SIGNAL
E
SD PROTECTION
CIRCUITRY
107/324
9
ST92F120 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.7 STOP MODE
On ST9 devices provided with an external STOP
pin, the Reset/Stop Manager can also stop all os-
cillators without resetting the device.
Electrical Characteristics section), without losing
the status.
Note: If STOP Mode is entered, the clock is
stopped: hence, also the watchdog counter is
stopped. When the ST9 exits from STOP Mode,
the watchdog counter restarts from where it was
before STOP Mode was entered.
To enter STOP Mode, the STOP pin must be tied
low. When the STOP pin is tied high again, the
MCU resumes execution of the program after a set
number of CLOCK2 cycles (refer to T
in the
STR
108/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
8 EXTERNAL MEMORY INTERFACE (EXTMI)
8.1 INTRODUCTION
The ST9 External Memory Interface uses two reg-
isters (EMR1 and EMR2) to configure external
memory accesses. Some interface signals are
also affected by WCR - R252 Page 0.
During phase T2, two forms of behavior are possi-
ble. If the memory access is a Read cycle, Port 0
pins are released in high-impedance until the next
T1 phase and the data signals are sampled by the
ST9 on the rising edge of DS. If the memory ac-
cess is a Write cycle, on the falling edge of DS,
Port 0 outputs data to be written in the external
memory. Those data signals are valid on the rising
edge of DS and are maintained stable until the
next address is output. Note that DS is pulled low
at the beginning of phase T2 only during an exter-
nal memory access.
If the two registers EMR1 and EMR2 are set to the
proper values, the ST9+ memory access cycle is
similar to that of the original ST9, with the only ex-
ception that it is composed of just two system
clock phases, named T1 and T2.
During phase T1, the memory address is output on
the AS falling edge and is valid on the rising edge
of AS. Port0 and Port 1 maintain the address sta-
ble until the following T1 phase.
Figure 56. Page 21 Registers
n
Page 21
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
Relocation of P[3:0] and DPR[3:0] Registers
SSPL
SSPL
SSPH
USPL
USPH
MODER
PPR
RP1
RP0
FLAGR
CICR
P5
SSPH
USPL
USPH
MODER
PPR
RP1
RP0
FLAGR
CICR
P5
DMASR
ISR
DMASR
ISR
DMASR
ISR
MMU
EMR2
EMR1
CSR
EMR2
EMR1
CSR
P3
P2
P1
P4
P4
EMR2
EMR1
CSR
P3
P2
P1
P0
DPR3
DPR2
DPR1
DPR0
DPR3
DPR2
DPR1
DPR0
EXT.MEM
P0
DPR3
DPR2
DPR1
DPR0
Bit DPRREM=0
Bit DPRREM=1
MMU
109/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
8.2 EXTERNAL MEMORY SIGNALS
The access to external memory is made using the
AS, DS, DS2, RW, Port 0, Port1, and WAIT signals
described below.
under processor control by setting the HIMP bit
(MODER.0, R235). Under Reset status, DS is held
high with an internal weak pull-up.
Refer to Figure 58
The behavior of this signal is affected by the MC,
DS2EN, and BSZ bits in the EMR1 register. Refer
to the Register description.
8.2.1 AS: Address Strobe
AS (Output, Active low, Tristate) is active during
the System Clock high-level phase of each T1
memory cycle: an AS rising edge indicates that
Memory Address and Read/Write Memory control
signals are valid. AS is released in high-imped-
ance during the bus acknowledge cycle or under
the processor control by setting the HIMP bit
(MODER.0, R235). Depending on the device AS is
available as Alternate Function or as a dedicated
pin.
8.2.3 DS2: Data Strobe 2
This additional Data Strobe pin (Alternate Function
Output, Active low, Tristate) is available on some
ST9 devices only. It allows two external memories
to be connected to the ST9, the upper memory
block (A21=1 typically RAM) and the lower memo-
ry block (A21=0 typically ROM) without any exter-
nal logic. The selection between the upper and
lower memory blocks depends on the A21 address
pin value.
Under Reset, AS is held high with an internal weak
pull-up.
The behavior of this signal is affected by the MC,
ASAF, ETO, BSZ, LAS[1:0] and UAS[1:0] bits in
the EMR1 or EMR2 registers. Refer to the Regis-
ter description.
The upper memory block is controlled by the DS
pin while the lower memory block is controlled by
the DS2 pin. When the internal memory is ad-
dressed, DS2 is kept high during the whole mem-
ory cycle. DS2 is released in high-impedance dur-
ing bus acknowledge cycle or under processor
control by setting the HIMP bit (MODER.0, R235).
DS2 is enabled via software as the Alternate Func-
tion output of the associated I/O port bit (refer to
specific ST9 version to identify the specific port
and pin).
8.2.2 DS: Data Strobe
DS (Output, Active low, Tristate) is active during the
internal clock high-level phase of each T2 memory
cycle. During an external memory read cycle, the
data on Port 0 must be valid before the DS rising
edge. During an external memory write cycle, the
data on Port 0 are output on the falling edge of DS
and they are valid on the rising edge of DS. When
the internal memory is accessed DS is kept high
during the whole memory cycle. DS is released in
high-impedance during bus acknowledge cycle or
The behavior of this signal is affected by the
DS2EN, and BSZ bits in the EMR1 register. Refer
to the Register description.
110/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
Figure 57. Effects of DS2EN on the behavior of DS and DS2
n
NO WAIT CYCLE
T2
1 DS WAIT CYCLE
T2
T1
T1
SYSTEM
CLOCK
DS STRETCH
AS (MC=0)
DS2EN=0 OR (DS2EN=1 AND UPPER MEMORY ADDRESSED):
DS
(MC=0)
DS
(MC=1, READ)
DS
(MC=1, WRITE)
DS2
DS2EN=1 AND LOWER MEMORY ADDRESSED:
DS
DS2
(MC=0)
DS2
(MC=1, READ)
DS2
(MC=1, WRITE)
111/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
Figure 58. External Memory Read/Write with a Programmable Wait
n
NO WAIT CYCLE
1 DS WAIT CYCLE
1 AS WAIT CYCLE
T1
T1
T2
T2
TWA
TWD
SYSTEM
CLOCK
AS STRETCH
DS STRETCH
AS (MC=0)
TAVQV
ALE (MC=1)
P1
ADDRESS
ADDRESS
ADDRESS
ADDRESS
DS (MC=0)
P0
DATA IN
DATA IN
MULTIPLEXED
RW (MC=0)
DS (MC=1)
RW (MC=1)
P0
DATA
ADDRESS
DATA OUT
ADDRESS
MULTIPLEXED
TAVWH
RW (MC=0)
TAVWL
DS (MC=1)
RW (MC=1)
112/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
8.2.4 RW: Read/Write
The behavior of this signal is affected by the MC,
ETO and BSZ bits in the EMR1 register. Refer to
the Register description.
RW (Alternate Function Output, Active low,
Tristate) identifies the type of memory cycle:
RW=”1” identifies a memory read cycle, RW=”0”
identifies a memory write cycle. It is defined at the
beginning of each memory cycle and it remains
stable until the following memory cycle. RW is re-
leased in high-impedance during bus acknowl-
edge cycle or under processor control by setting
the HIMP bit (MODER). RW is enabled via soft-
ware as the Alternate Function output of the asso-
ciated I/O port bit (refer to specific ST9 device to
identify the port and pin). Under Reset status, the
associated bit of the port is set into bidirectional
weak pull-up mode.
8.2.5 BREQ, BACK: Bus Request, Bus
Acknowledge
Note: These pins are available only on some ST9
devices (see Pin description).
BREQ (Alternate Function Input, Active low) indi-
cates to the ST9 that a bus request has tried or is
trying to gain control of the memory bus. Once en-
abled by setting the BRQEN bit (MODER.1,
R235), BREQ is sampled with the falling edge of
the processor internal clock during phase T2.
n
n
Figure 59. External Memory Read/Write Sequence with External Wait (WAIT pin)
n
T2
T1
T2
T1
T2
T1
WAIT
SYSTEM
CLOCK
ADDRESS
ADDRESS
ADDRESS
P1
AS (MC=0)
ALE (MC=1)
DS (MC=0)
MULTIPLEXED
P0
ADD.
ADDRESS
ADD.
D.IN
D.IN
D.IN
RW (MC=0)
DS (MC=1)
RW (MC=1)
MULTIPLEXED
P0
D.OUT
ADD.
DATA OUT
ADD.
ADDRESS
D.OUT
RW (MC=0)
DS (MC=1)
RW (MC=1)
113/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
Whenever it is sampled low, the System Clock is
stretched and the external memory signals (AS,
DS, DS2, RW, P0 and P1) are released in high-im-
pedance. The external memory interface pins are
driven again by the ST9 as soon as BREQ is sam-
pled high.
as the external memory interface to provide the 8
MSB of the address A[15:8].
The behavior of the Port 0 and 1 pins is affected by
the BSZ and ETO bits in the EMR1 register. Refer
to the Register description.
BACK (Alternate Function Output, Active low) indi-
cates that the ST9 has relinquished control of the
memory bus in response to a bus request. BREQ
is driven low when the external memory interface
signals are released in high-impedance.
8.2.8 WAIT: External Memory Wait
WAIT (Alternate Function Input, Active low) indi-
cates to the ST9 that the external memory requires
more time to complete the memory access cycle. If
bit EWEN (EIVR) is set, the WAIT signal is sam-
pled with the rising edge of the processor internal
clock during phase T1 or T2 of every memory cy-
cle. If the signal was sampled active, one more in-
ternal clock cycle is added to the memory cycle.
On the rising edge of the added internal clock cy-
cle, WAIT is sampled again to continue or finish
the memory cycle stretching. Note that if WAIT is
sampled active during phase T1 then AS is
stretched, while if WAIT is sampled active during
phase T2 then DS is stretched. WAIT is enabled
via software as the Alternate Function input of the
associated I/O port bit (refer to specific ST9 ver-
sion to identify the specific port and pin). Under
Reset status, the associated bit of the port is set to
the bidirectional weak pull-up mode. Refer to Fig-
ure 59.
At MCU reset, the bus request function is disabled.
To enable it, configure the I/O port pins assigned
to BREQ and BACK as Alternate Function and set
the BRQEN bit in the MODER register.
8.2.6 PORT 0
If Port 0 (Input/Output, Push-Pull/Open-Drain/
Weak Pull-up) is used as a bit programmable par-
allel I/O port, it has the same features as a regular
port. When set as an Alternate Function, it is used
as the External Memory interface: it outputs the
multiplexed Address 8 LSB: A[7:0] /Data bus
D[7:0].
8.2.7 PORT 1
If Port 1 (Input/Output, Push-Pull/Open-Drain/
Weak Pull-up) is used as a bit programmable par-
allel I/O port, it has the same features as a regular
port. When set as an Alternate Function, it is used
Figure 60. Application Example
RAM
64 Kbytes
W
RW
DS
G
A0-A7/D0-D7
P0
Q0-Q7
ST9+
D1-D8
Q1-Q8
AS
P1
LE
A0-A15
E
OE
LATCH
A15-A8
114/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
8.3 REGISTER DESCRIPTION
EXTERNAL MEMORY REGISTER 1 (EMR1)
R245 - Read/Write
Register Page: 21
Bit 4 = ASAF: Address Strobe as Alternate Func-
tion.
Depending on the device, AS can be either a ded-
icated pin or a port Alternate Function. This bit is
used only in the second case.
Reset value: 1000 0000 (80h)
0: AS Alternate function disabled.
1: AS Alternate Function enabled.
7
0
x
MC
DS2EN ASAF
x
ETO
BSZ
X
Bit 2 = ETO: External toggle.
0: The external memory interface pins (AS, DS,
DS2, RW, Port0, Port1) toggle only if an access
to external memory is performed.
1: When the internal memory protection is dis-
abled (mask option available on some devices
only), the above pins (except DS and DS2 which
never toggle during internal memory accesses)
toggle during both internal and external memory
accesses.
Bit 7 = Reserved.
Bit 6 = MC: Mode Control.
0: AS, DS and RW pins have the standard ST9
meaning.
1: AS pin becomes ALE, Address Load Enable
(AS inverted); Thus Memory Adress, Read/
Write signals are valid whenever a falling edge
of ALE occurs.
DS becomes OEN, Output ENable: it has the
standard ST9 meaning during external read op-
erations, but is forced to “1” during external write
operations.
RW pin becomes WEN, Write ENable: it follows
the standard ST9 DS meaning during external
write operations, but is forced to “1” during ex-
ternal read operations.
Bit 1 = BSZ: Bus size.
0: All the I/O ports including the external memory
interface pins use smaller, less noisy output
buffers. This may limit the operation frequency
of the device, unless the clock is slow enough or
sufficient wait states are inserted.
1: All the I/O ports including the external memory
interface pins (AS, DS, DS2, R/W, Port 0, 1) use
larger, more noisy output buffers .
Bit 5 = DS2EN: Data Strobe 2 enable.
0: The DS2 pin is forced to “1” during the whole
memory cycle. In this case, access to upper or
lower memory is controlled by the DS pin.
1: If the lower memory block is addressed, the
DS2 pin follows the standard ST9 DS meaning
(if MC=0) or it becomes OEN (if MC=1). The DS
pin is forced to 1 during the whole memory cy-
cle.
Bit 0 = Reserved.
CAUTION: External memory must be correctly ad-
dressed before and after a write operation on the
EMR1 register. For example, if code is fetched
from external memory using the standard ST9 ex-
ternal memory interface configuration (MC=0),
setting the MC bit will cause the device to behave
unpredictably.
If the upper memory block is used, DS2 is forced
to “1” during the whole memory cycle. The DS
pin behaviour is not modified.
Refer to Figure 57
115/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d)
EXTERNAL MEMORY REGISTER 2 (EMR2)
R246 - Read/Write
Register Page: 21
the contents of ISR. In this case, iret will also re-
store CSR from the stack. This approach allows
interrupt service routines to access the entire
4Mbytes of address space; the drawback is that
the interrupt response time is slightly increased,
because of the need to also save CSR on the
stack. Full compatibility with the original ST9 is
lost in this case, because the interrupt stack
frame is different; this difference, however,
should not affect the vast majority of programs.
Reset value: 0001 1111 (1Fh)
7
0
MEM
-
ENCSR DPRREM
LAS1 LAS0 UAS1 UAS0
SEL
Bit 7 = Reserved.
Bit 5 = DPRREM: Data Page Registers remapping
0: The locations of the four MMU (Memory Man-
agement Unit) Data Page Registers (DPR0,
DPR1, DPR2 and DPR3) are in page 21.
1: The four MMU Data Page Registers are
swapped with that of the Data Registers of ports
0-3.
Bit 6 = ENCSR: Enable Code Segment Register.
This bit affects the ST9 CPU behavior whenever
an interrupt request is issued.
0: The CPU works in original ST9 compatibility
mode concerning stack frame during interrupts.
For the duration of the interrupt service routine,
ISR is used instead of CSR, and the interrupt
stack frame is identical to that of the original
ST9: only the PC and Flags are pushed. This
avoids saving the CSR on the stack in the event
of an interrupt, thus ensuring a faster interrupt
response time. The drawback is that it is not
possible for an interrupt service routine to per-
form inter-segment calls or jumps: these instruc-
tions would update the CSR, which, in this case,
is not used (ISR is used instead). The code seg-
ment size for all interrupt service routines is thus
limited to 64K bytes.
Refer to Figure 56
Bit 4 = MEMSEL: Memory Selection.
Caution: Must be kept as it is set in the TestFlash
Boot Code (Reset value is 1).
Bits 3:2 = LAS[1:0]: Lower memory address
strobe stretch.
These two bits contain the number of wait cycles
(from 0 to 3) to add to the System Clock to stretch
AS during external lower memory block accesses
(MSB of 22-bit internal address=0). The reset val-
ue is 3.
1: If ENCSR is set, ISR is only used to point to the
interrupt vector table and to initialize the CSR at
the beginning of the interrupt service routine: the
old CSR is pushed onto the stack together with
the PC and flags, and CSR is then loaded with
116/324
9
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d)
Bits 1:0 = UAS[1:0]: Upper memory address
strobe stretch.
tional wait cycles. UDS = 7 adds the maximum 7
INTCLK cycles (reset condition).
These two bits contain the number of wait cycles
(from 0 to 3) to add to the System Clock to stretch
AS during external upper memory block accesses
(MSB of 22-bit internal address=1). The reset val-
ue is 3.
Bits 2:0 = LDS[2:0]: Lower memory data strobe
stretch.
These bits contain the number of INTCLK cycles
to be added automatically to DS or DS2 (depend-
ing on the DS2EN bit of the EMR1 register) for ex-
ternal lower memory block accesses. LDS = 0
adds no additional wait cycles, LDS = 7 adds the
maximum 7 INTCLK cycles (reset condition).
CAUTION: The EMR2 register cannot be written
during an interrupt service routine.
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Note 1: The number of clock cycles added refers
to INTCLK and NOT to CPUCLK.
Note 2: The distinction between the Upper memo-
ry block and the Lower memory block allows differ-
ent wait cycles between the first 2 Mbytes and the
second 2 Mbytes, and allows 2 different data
strobe signals to be used to access 2 different
memories.
Reset Value: 0111 1111 (7Fh)
7
0
0
WDGEN UDS2 UDS1 UDS0 LDS2 LDS1 LDS0
Typically, the RAM will be located above address
0x200000 and the ROM below address
0x1FFFFF, with different access times. No extra
hardware is required as DS is used to access the
upper memory block and DS2 is used to access
the lower memory block.
Bit 7 = Reserved, forced by hardware to 0.
Bit 6 = WDGEN: Watchdog Enable.
For a description of this bit, refer to the Timer/
Watchdog chapter.
CAUTION: Clearing this bit has the effect of set-
ting the Timer/Watchdog to Watchdog mode. Un-
less this is desired, it must be set to “1”.
CAUTION: The reset value of the Wait Control
Register gives the maximum number of Wait cy-
cles for external memory. To get optimum perfor-
mance from the ST9, the user should write the
UDS[2:0] and LDS[2:0] bits to 0, if the external ad-
dressed memories are fast enough.
Bits 5:3 = UDS[2:0]: Upper memory data strobe
stretch.
These bits contain the number of INTCLK cycles
to be added automatically to DS for external upper
memory block accesses. UDS = 0 adds no addi-
117/324
9
ST92F120 - I/O PORTS
9 I/O PORTS
9.1 INTRODUCTION
9.2 SPECIFIC PORT CONFIGURATIONS
ST9 devices feature flexible individually program-
mable multifunctional input/output lines. Refer to
the Pin Description Chapter for specific pin alloca-
tions. These lines, which are logically grouped as
8-bit ports, can be individually programmed to pro-
vide digital input/output and analog input, or to
connect input/output signals to the on-chip periph-
erals as alternate pin functions. All ports can be in-
dividually configured as an input, bi-directional,
output or alternate function. In addition, pull-ups
can be turned off for open-drain operation, and
weak pull-ups can be turned on in their place, to
avoid the need for off-chip resistive pull-ups. Ports
configured as open drain must never have voltage
Refer to the Pin Description chapter for a list of the
specific port styles and reset values.
9.3 PORT CONTROL REGISTERS
Each port is associated with a Data register
(PxDR) and three Control registers (PxC0, PxC1,
PxC2). These define the port configuration and al-
low dynamic configuration changes during pro-
gram execution. Port Data and Control registers
are mapped into the Register File as shown in Fig-
ure 1. Port Data and Control registers are treated
just like any other general purpose register. There
are no special instructions for port manipulation:
any instruction that can address a register, can ad-
dress the ports. Data can be directly accessed in
the port register, without passing through other
memory or “accumulator” locations.
on the port pin exceeding V (refer to the Electri-
DD
cal Characteristics section). Depending on the
specific port, input buffers are software selectable
to be TTL or CMOS compatible, however on Sch-
mitt trigger ports, no selection is possible.
Figure 61. I/O Register Map
GROUP E
GROUP F
GROUP F
PAGE 3
GROUP F
PAGE 43
PAGE 2
Reserved
P3C2
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
P7DR
P7C2
P9DR
P9C2
P9C1
P9C0
P8DR
P8C2
P8C1
P8C0
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
P3C1
P7C1
P3C0
P7C0
Reserved
P2C2
P6DR
P6C2
System
Registers
P2C1
P6C1
P2C0
P6C0
Reserved
P1C2
Reserved
P5C2
E5h
E4h
E3h
E2h
E1h
E0h
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
R229
R228
R227
R226
R225
R224
P1C1
P5C1
Reserved
P1C0
P5C0
Reserved
P0C2
Reserved
P4C2
P0C1
P4C1
P0C0
P4C0
118/324
9
ST92F120 - I/O PORTS
PORT CONTROL REGISTERS (Cont’d)
During Reset, ports with weak pull-ups are set in
bidirectional/weak pull-up mode and the output
Data Register is set to FFh. This condition is also
held after Reset, except for Ports 0 and 1 in ROM-
less devices, and can be redefined under software
control.
Each pin of an I/O port may assume software pro-
grammable Alternate Functions (refer to the de-
vice Pin Description and to Section 1.5). To output
signals from the ST9 peripherals, the port must be
configured as AF OUT. On ST9 devices with A/D
Converter(s), configure the ports used for analog
inputs as AF IN.
Bidirectional ports without weak pull-ups are set in
high impedance during reset. To ensure proper
levels during reset, these ports must be externally
The basic structure of the bit Px.n of a general pur-
pose port Px is shown in Figure 3.
connected to either V
pull-up or pull-down resistors.
or V through external
DD
SS
Independently of the chosen configuration, when
the user addresses the port as the destination reg-
ister of an instruction, the port is written to and the
data is transferred from the internal Data Bus to
the Output Master Latches. When the port is ad-
dressed as the source register of an instruction,
the port is read and the data (stored in the Input
Latch) is transferred to the internal Data Bus.
Other reset conditions may apply in specific ST9
devices.
9.4 INPUT/OUTPUT BIT CONFIGURATION
By programming the control bits PxC0.n and
PxC1.n (see Figure 2) it is possible to configure bit
Px.n as Input, Output, Bidirectional or Alternate
Function Output, where X is the number of the I/O
port, and n the bit within the port (n = 0 to 7).
When Px.n is programmed as an Input:
(See Figure 4).
– The Output Buffer is forced tristate.
When programmed as input, it is possible to select
the input level as TTL or CMOS compatible by pro-
gramming the relevant PxC2.n control bit.
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of each instruc-
tion execution.
This option is not available on Schmitt trigger ports.
– The data stored in the Output Master Latch is
copied into the Output Slave Latch at the end of
the execution of each instruction. Thus, if bit Px.n
is reconfigured as an Output or Bidirectional, the
data stored in the Output Slave Latch will be re-
flected on the I/O pin.
The output buffer can be programmed as push-
pull or open-drain.
A weak pull-up configuration can be used to avoid
external pull-ups when programmed as bidirec-
tional (except where the weak pull-up option has
been permanently disabled in the pin hardware as-
signment).
119/324
9
ST92F120 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
Figure 62. Control Bits
Bit 7
Bit n
Bit 0
PxC2
PxC1
PxC0
PxC27
PxC17
PxC07
PxC2n
PxC1n
PxC0n
PxC20
PxC10
PxC00
n
Table 25. Port Bit Configuration Table (n = 0, 1... 7; X = port number)
General Purpose I/O Pins
A/D Pins
PXC2n
PXC1n
PXC0n
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
PXn Configuration
PXn Output Type
BID
BID
OD
OUT
PP
OUT
OD
IN
IN
AF OUT AF OUT
AF IN
(1)
WP OD
HI-Z
HI-Z
PP
OD
HI-Z
TTL
(or Schmitt
TTL
(or Schmitt
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
CMOS
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Analog
Input
PXn Input Type
Trigger)
Trigger)
Trigger)
(1)
For A/D Converter inputs.
Legend:
X
= Port
n
= Bit
AF
= Alternate Function
BID = Bidirectional
CMOS= CMOS Standard Input Levels
HI-Z = High Impedance
IN
= Input
OD = Open Drain
OUT = Output
PP
= Push-Pull
TTL = TTL Standard Input Levels
WP = Weak Pull-up
120/324
9
ST92F120 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
Figure 63. Basic Structure of an I/O Port Pin
I/O PIN
PUSH-PULL
TRISTATE
OPEN DRAIN
WEAK PULL-UP
TTL / CMOS
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
INTERRUPTS
OUTPUT SLAVE LATCH
ALTERNATE
FROM
FUNCTION
PERIPHERAL
OUTPUT
INPUT
BIDIRECTIONAL
ALTERNATE
FUNCTION
OUTPUT
INPUT
OUTPUT
BIDIRECTIONAL
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
Figure 64. Input Configuration
Figure 65. Output Configuration
I/O PIN
I/O PIN
OPEN DRAIN
PUSH-PULL
TTL / CMOS
TTL
TRISTATE
(or Schmitt Trigger)
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
OUTPUT SLAVE LATCH
INTERRUPTS
INTERRUPTS
OUTPUT MASTER LATCH
INPUT LATCH
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
INTERNAL DATA BUS
n
n
n
121/324
9
ST92F120 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
When Px.n is programmed as an Output:
(Figure 5)
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of the execution
of the instruction.
– The Output Buffer is turned on in an Open-drain
or Push-pull configuration.
– The signal from an on-chip function is allowed to
load the Output Slave Latch driving the I/O pin.
Signal timing is under control of the alternate
function. If no alternate function is connected to
Px.n, the I/O pin is driven to a high level when in
Push-Pull configuration, and to a high imped-
ance state when in open drain configuration.
– The data stored in the Output Master Latch is
copied both into the Input Latch and into the Out-
put Slave Latch, driving the I/O pin, at the end of
the execution of the instruction.
When Px.n is programmed as Bidirectional:
(Figure 6)
Figure 66. Bidirectional Configuration
– The Output Buffer is turned on in an Open-Drain
or Weak Pull-up configuration (except when dis-
abled in hardware).
I/O PIN
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of the execution
of the instruction.
WEAK PULL-UP
OPEN DRAIN
TTL
(or Schmitt Trigger)
– The data stored in the Output Master Latch is
copied into the Output Slave Latch, driving the I/
O pin, at the end of the execution of the instruc-
tion.
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
INTERRUPTS
WARNING: Due to the fact that in bidirectional
mode the external pin is read instead of the output
latch, particular care must be taken with arithme-
tic/logic and Boolean instructions performed on a
bidirectional port pin.
OUTPUT MASTER LATCH
INPUT LATCH
These instructions use a read-modify-write se-
quence, and the result written in the port register
depends on the logical level present on the exter-
nal pin.
INTERNAL DATA BUS
n
n
This may bring unwanted modifications to the port
output register content.
Figure 67. Alternate Function Configuration
For example:
I/O PIN
Port register content, 0Fh
external port value, 03h
(Bits 3 and 2 are externally forced to 0)
OPEN DRAIN
PUSH-PULL
TTL
(or Schmitt Trigger)
A bsetinstruction on bit 7 will return:
Port register content, 83h
external port value, 83h
(Bits 3 and 2 have been cleared).
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
INTERRUPTS
To avoid this situation, it is suggested that all oper-
ations on a port, using at least one bit in bidirec-
tional mode, are performed on a copy of the port
register, then transferring the result with a load in-
struction to the I/O port.
FROM
PERIPHERAL
OUTPUT
INPUT LATCH
When Px.n is programmed as a digital Alter-
nate Function Output:
INTERNAL DATA BUS
(Figure 7)
n
n
n
n
n
n
– The Output Buffer is turned on in an Open-Drain
or Push-Pull configuration.
122/324
9
ST92F120 - I/O PORTS
9.5 ALTERNATE FUNCTION ARCHITECTURE
Each I/O pin may be connected to three different
types of internal signal:
9.5.3 Pin Declared as an Alternate Function
Output
– Data bus Input/Output
– Alternate Function Input
– Alternate Function Output
9.5.1 Pin Declared as I/O
The user must select the AF OUT configuration
using the PxC2, PxC1, PxC0 bits. Several Alter-
nate Function outputs may drive a common pin. In
such case, the Alternate Function output signals
are logically ANDed before driving the common
pin. The user must therefore enable the required
Alternate Function Output by software.
A pin declared as I/O, is connected to the I/O buff-
er. This pin may be an Input, an Output, or a bidi-
rectional I/O, depending on the value stored in
(PxC2, PxC1 and PxC0).
WARNING: When a pin is connected both to an al-
ternate function output and to an alternate function
input, it should be noted that the output signal will
always be present on the alternate function input.
9.5.2 Pin Declared as an Alternate Function
Input
A single pin may be directly connected to several
Alternate Function inputs. In this case, the user
must select the required input mode (with the
PxC2, PxC1, PxC0 bits) and enable the selected
Alternate Function in the Control Register of the
peripheral. No specific port configuration is re-
quired to enable an Alternate Function input, since
the input buffer is directly connected to each alter-
nate function module on the shared pin. As more
than one module can use the same input, it is up to
the user software to enable the required module
as necessary. Parallel I/Os remain operational
even when using an Alternate Function input. The
exception to this is when an I/O port bit is perma-
nently assigned by hardware as an A/D bit. In this
case , after software programming of the bit in AF-
OD-TTL, the Alternate function output is forced to
logic level 1. The analog voltage level on the cor-
responding pin is directly input to the A/D (See Fig-
ure 8).
9.6 I/O STATUS AFTER WFI, HALT AND RESET
The status of the I/O ports during the Wait For In-
terrupt, Halt and Reset operational modes is
shown in the following table. The External Memory
Interface ports are shown separately. If only the in-
ternal memory is being used and the ports are act-
ing as I/O, the status is the same as shown for the
other I/O ports.
Ext. Mem - I/O Ports
Mode
I/O Ports
P1, P2, P6,
P9[7:2] *
P0
High Imped-
anceor next
address
(depending
on the last
memory op-
eration per-
formed on
Port)
Next
Address
Not Affected (clock
outputs running)
WFI
Figure 68. A/D Input Configuration
I/O PIN
High Imped-
ance
Next
Address
Not Affected (clock
outputs stopped)
TOWARDS
A/D CONVERTER
HALT
TRISTATE
GND
Bidirectional Weak
Pull-up (High im-
pedance when dis-
abled in
Alternate function push-
pull (ROMless device)
RESET
INPUT
hardware).
OUTPUT SLAVE LATCH
BUFFER
* Depending on device
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
123/324
9
TIMER/WATCHDOG (WDT)
10 ON-CHIP PERIPHERALS
10.1 TIMER/WATCHDOG (WDT)
Important Note: This chapter is a generic descrip-
tion of the WDT peripheral. However depending
on the ST9 device, some or all of WDT interface
signals described may not be connected to exter-
nal pins. For the list of WDT pins present on the
ST9 device, refer to the device pinout description
in the first section of the data sheet.
The main WDT registers are:
– Control register for the input, output and interrupt
logic blocks (WDTCR)
– 16-bit counter register pair (WDTHR, WDTLR)
– Prescaler register (WDTPR)
The hardware interface consists of up to five sig-
nals:
10.1.1 Introduction
The Timer/Watchdog (WDT) peripheral consists of
a programmable 16-bit timer and an 8-bit prescal-
er. It can be used, for example, to:
– WDIN External clock input
– WDOUT Square wave or PWM signal output
– INT0 External interrupt input
– Generate periodic interrupts
– NMI Non-Maskable Interrupt input
– Measure input signal pulse widths
– Request an interrupt after a set number of events
– Generate an output signal waveform
– HW0SW1 Hardware/Software Watchdog ena-
ble.
– Act as a Watchdog timer to monitor system in-
tegrity
Figure 69. Timer/Watchdog Block Diagram
INMD1 INMD2
INEN
INPUT
&
1
WDIN
WDTRH, WDTRL
WDTPR
END OF
16-BIT
CLOCK CONTROL LOGIC
MUX
8-BIT PRESCALER
COUNT
DOWNCOUNTER
WDT
CLOCK
INTCLK/4
WROUT
OUTEN
OUTMD
OUTPUT CONTROL LOGIC
1
NMI
1
INT0
1
WDOUT
1
HW0SW1
INTERRUPT
MUX
IAOS
CONTROL LOGIC
WDGEN
TLIS
RESET
TOP LEVEL INTERRUPT REQUEST
INTA0 REQUEST
1
Pin not present on some ST9 devices.
124/324
9
TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.2 Functional Description
10.1.2.1 External Signals
10.1.2.4 Single/Continuous Mode
The S_C bit allows selection of single or continu-
ous mode.This Mode bit can be written with the
Timer stopped or running. It is possible to toggle
the S_C bit and start the counter with the same in-
struction.
The HW0SW1 pin can be used to permanently en-
able Watchdog mode. Refer to section 10.1.3.1 on
page 126.
The WDIN Input pin can be used in one of four
modes:
Single Mode
On reaching the End Of Count condition, the Timer
stops, reloads the constant, and resets the Start/
Stop bit. Software can check the current status by
reading this bit. To restart the Timer, set the Start/
Stop bit.
– Event Counter Mode
– Gated External Input Mode
– Triggerable Input Mode
– Retriggerable Input Mode
Note: If the Timer constant has been modified dur-
ing the stop period, it is reloaded at start time.
The WDOUT output pin can be used to generate a
square wave or a Pulse Width Modulated signal.
Continuous Mode
An interrupt, generated when the WDT is running
as the 16-bit Timer/Counter, can be used as a Top
Level Interrupt or as an interrupt source connected
to channel A0 of the external interrupt structure
(replacing the INT0 interrupt input).
On reaching the End Of Count condition, the coun-
ter automatically reloads the constant and restarts.
It is stopped only if the Start/Stop bit is reset.
10.1.2.5 Input Section
The counter can be driven either by an external
clock, or internally by INTCLK divided by 4.
If the Timer/Counter input is enabled (INEN bit) it
can count pulses input on the WDIN pin. Other-
wise it counts the internal clock/4.
10.1.2.2 Initialisation
For instance, when INTCLK = 24MHz, the End Of
Count rate is:
The prescaler (WDTPR) and counter (WDTRL,
WDTRH) registers must be loaded with initial val-
ues before starting the Timer/Counter. If this is not
done, counting will start with reset values.
2.79 seconds for Maximum Count
(Timer Const. = FFFFh, Prescaler Const. = FFh)
10.1.2.3 Start/Stop
166 ns for Minimum Count
(Timer Const. = 0000h, Prescaler Const. = 00h)
The ST_SP bit enables downcounting. When this
bit is set, the Timer will start at the beginning of the
following instruction. Resetting this bit stops the
counter.
The Input pin can be used in one of four modes:
– Event Counter Mode
– Gated External Input Mode
If the counter is stopped and restarted, counting
will resume from the last value unless a new con-
stant has been entered in the Timer registers
(WDTRL, WDTRH).
– Triggerable Input Mode
– Retriggerable Input Mode
The mode is configurable in the WDTCR.
10.1.2.6 Event Counter Mode
A new constant can be written in the WDTRH,
WDTRL, WDTPR registers while the counter is
running. The new value of the WDTRH, WDTRL
registers will be loaded at the next End of Count
(EOC) condition while the new value of the
WDTPR register will be effective immediately.
In this mode the Timer is driven by the external
clock applied to the input pin, thus operating as an
event counter. The event is defined as a high to
low transition of the input signal. Spacing between
trailing edges should be at least 8 INTCLK periods
(or 333ns with INTCLK = 24MHz).
End of Count is when the counter is 0.
When Watchdog mode is enabled the state of the
ST_SP bit is irrelevant.
Counting starts at the next input event after the
ST_SP bit is set and stops when the ST_SP bit is
reset.
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TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.2.7 Gated Input Mode
10.1.3 Watchdog Timer Operation
This mode can be used for pulse width measure-
ment. The Timer is clocked by INTCLK/4, and is
started and stopped by means of the input pin and
the ST_SP bit. When the input pin is high, the Tim-
er counts. When it is low, counting stops. The
maximum input pin frequency is equivalent to
INTCLK/8.
This mode is used to detect the occurrence of a
software fault, usually generated by external inter-
ference or by unforeseen logical conditions, which
causes the application program to abandon its
normal sequence of operation. The Watchdog,
when enabled, resets the MCU, unless the pro-
gram executes the correct write sequence before
expiry of the programmed time period. The appli-
cation program must be designed so as to correct-
ly write to the WDTLR Watchdog register at regu-
lar intervals during all phases of normal operation.
10.1.2.8 Triggerable Input Mode
The Timer (clocked internally by INTCLK/4) is
started by the following sequence:
– setting the Start-Stop bit, followed by
– a High to Low transition on the input pin.
To stop the Timer, reset the ST_SP bit.
10.1.2.9 Retriggerable Input Mode
10.1.3.1
Watchdog
Hardware
Watchdog/Software
The HW0SW1 pin (when available) selects Hard-
ware Watchdog or Software Watchdog.
If HW0SW1 is held low:
In this mode, the Timer (clocked internally by
INTCLK/4) is started by setting the ST_SP bit. A
High to Low transition on the input pin causes
counting to restart from the initial value. When the
Timer is stopped (ST_SP bit reset), a High to Low
transition of the input pin has no effect.
– The Watchdog is enabled by hardware immedi-
ately after an external reset. (Note: Software re-
set or Watchdog reset have no effect on the
Watchdog enable status).
– The initial counter value (FFFFh) cannot be mod-
ified, however software can change the prescaler
value on the fly.
10.1.2.10 Timer/Counter Output Modes
Output modes are selected by means of the OUT-
EN (Output Enable) and OUTMD (Output Mode)
bits of the WDTCR register.
– The WDGEN bit has no effect. (Note: it is not
forced low).
If HW0SW1 is held high, or is not present:
No Output Mode
(OUTEN = “0”)
– The Watchdog can be enabled by resetting the
WDGEN bit.
The output is disabled and the corresponding pin
is set high, in order to allow other alternate func-
tions to use the I/O pin.
10.1.3.2 Starting the Watchdog
In Watchdog mode the Timer is clocked by
INTCLK/4.
Square Wave Output Mode
(OUTEN = “1”, OUTMD = “0”)
If the Watchdog is software enabled, the time base
must be written in the timer registers before enter-
ing Watchdog mode by resetting the WDGEN bit.
Once reset, this bit cannot be changed by soft-
ware.
The Timer outputs a signal with a frequency equal
to half the End of Count repetition rate on the WD-
OUT pin. With an INTCLK frequency of 20MHz,
this allows a square wave signal to be generated
whose period can range from 400ns to 6.7 sec-
onds.
If the Watchdog is hardware enabled, the time
base is fixed by the reset value of the registers.
Pulse Width Modulated Output Mode
(OUTEN = “1”, OUTMD = “1”)
Resetting WDGEN causes the counter to start, re-
gardless of the value of the Start-Stop bit.
The state of the WROUT bit is transferred to the
output pin (WDOUT) at the End of Count, and is
held until the next End of Count condition. The
user can thus generate PWM signals by modifying
the status of the WROUT pin between End of
Count events, based on software counters decre-
mented by the Timer Watchdog interrupt.
In Watchdog mode, only the Prescaler Constant
may be modified.
If the End of Count condition is reached a System
Reset is generated.
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TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.3.3 Preventing Watchdog System Reset
10.1.3.4 Non-Stop Operation
In order to prevent a system reset, the sequence
AAh, 55h must be written to WDTLR (Watchdog
Timer Low Register). Once 55h has been written,
the Timer reloads the constant and counting re-
starts from the preset value.
In Watchdog Mode, a Haltinstruction is regarded
as illegal. Execution of the Haltinstruction stops
further execution by the CPU and interrupt ac-
knowledgment, but does not stop INTCLK, CPU-
CLK or the Watchdog Timer, which will cause a
System Reset when the End of Count condition is
reached. Furthermore, ST_SP, S_C and the Input
Mode selection bits are ignored. Hence, regard-
less of their status, the counter always runs in
Continuous Mode, driven by the internal clock.
To reload the counter, the two writing operations
must be performed sequentially without inserting
other instructions that modify the value of the
WDTLR register between the writing operations.
The maximum allowed time between two reloads
of the counter depends on the Watchdog timeout
period.
The Output mode should not be enabled, since in
this context it is meaningless.
Figure 70. Watchdog Timer Mode
COUNT
VALUE
TIMER START COUNTING
RESET
WRITE WDTRH,WDTRL
SOFTWARE FAIL
G
WD EN=0
(E.G. INFINITE LOOP)
OR PERIPHERAL FAIL
WRITE AAh,55h
INTOWDTRL
PRODUCE
COUNT RELOAD
VA00220
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TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.4 WDT Interrupts
Figure 71. Interrupt Sources
The Timer/Watchdog issues an interrupt request
at every End of Count, when this feature is ena-
bled.
TIMER WATCHDOG
A pair of control bits, IA0S (EIVR.1, Interrupt A0 se-
lection bit) and TLIS (EIVR.2, Top Level Input Se-
lection bit) allow the selection of 2 interrupt sources
(Timer/Watchdog End of Count, or External Pin)
handled in two different ways, as a Top Level Non
Maskable Interrupt (Software Reset), or as a
source for channel A0 of the external interruptlogic.
RESET
WDGEN (WCR.6)
A block diagram of the interrupt logic is given in
Figure 71.
0
1
Note: Software traps can be generated by setting
the appropriate interrupt pending bit.
MUX
INTA0 REQUEST
INT0
Table 26 below, shows all the possible configura-
tions of interrupt/reset sources which relate to the
Timer/Watchdog.
IA0S (EIVR.1)
A reset caused by the watchdog will set bit 6,
WDGRES of R242 - Page 55 (Clock Flag Regis-
ter). See section CLOCK CONTROL REGIS-
TERS.
0
1
TOP LEVEL
INTERRUPT REQUEST
MUX
NMI
TLIS (EIVR.2)
VA00293
Table 26. Interrupt Configuration
Control Bits
Enabled Sources
INTA0
Operating Mode
WDGEN
IA0S
TLIS
Reset
Top Level
0
0
0
0
0
0
1
1
0
1
0
1
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
SW TRAP
SW TRAP
Ext Pin
SW TRAP
Ext Pin
SW TRAP
Ext Pin
Watchdog
Watchdog
Watchdog
Watchdog
Ext Pin
1
1
1
1
0
0
1
1
0
1
0
1
Ext Reset
Ext Reset
Ext Reset
Ext Reset
Timer
Timer
Ext Pin
Ext Pin
Timer
Ext Pin
Timer
Timer
Timer
Timer
Timer
Ext Pin
Legend:
WDG = Watchdog function
SW TRAP = Software Trap
Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0
interrupts), only the INTA0 interrupt is taken into account.
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TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.5 Register Description
TIMER/WATCHDOG PRESCALER REGISTER
(WDTPR)
R250 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
The Timer/Watchdog is associated with 4 registers
mapped into Group F, Page 0 of the Register File.
WDTHR: Timer/Watchdog High Register
WDTLR: Timer/Watchdog Low Register
WDTPR: Timer/Watchdog Prescaler Register
WDTCR: Timer/Watchdog Control Register
7
0
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Three additional control bits are mapped in the fol-
lowing registers on Page 0:
Bits 7:0 = PR[7:0] Prescaler value.
A programmable value from 1 (00h) to 256 (FFh).
Watchdog Mode Enable, (WCR.6)
Top Level Interrupt Selection, (EIVR.2)
Interrupt A0 Channel Selection, (EIVR.1)
Warning: In order to prevent incorrect operation of
the Timer/Watchdog, the prescaler (WDTPR) and
counter (WDTRL, WDTRH) registers must be ini-
tialised before starting the Timer/Watchdog. If this
is not done, counting will start with the reset (un-in-
itialised) values.
Note: The registers containing these bits also con-
tain other functions. Only the bits relevant to the
operation of the Timer/Watchdog are shown here.
Counter Register
This 16-bit register (WDTLR, WDTHR) is used to
load the 16-bit counter value. The registers can be
read or written “on the fly”.
WATCHDOG TIMER CONTROL REGISTER
(WDTCR)
R251- Read/Write
Register Page: 0
Reset value: 0001 0010 (12h)
TIMER/WATCHDOG HIGH REGISTER (WDTHR)
R248 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
7
0
ST_SP S_C INMD1 INMD2 INEN OUTMD WROUT OUTEN
7
0
R15 R14 R13 R12 R11 R10
R9
R8
Bit 7 = ST_SP: Start/Stop Bit.
This bit is set and cleared by software.
0: Stop counting
Bits 7:0 = R[15:8] Counter Most Significant Bits.
1: Start counting (see Warning above)
TIMER/WATCHDOG LOW REGISTER (WDTLR)
R249 - Read/Write
Register Page: 0
Bit 6 = S_C: Single/Continuous.
This bit is set and cleared by software.
0: Continuous Mode
Reset value: 1111 1111b (FFh)
1: Single Mode
7
0
Bits 5:4 = INMD[1:2]: Input mode selection bits.
R7
R6
R5
R4
R3
R2
R1
R0
These bits select the input mode:
INMD1
INMD2
INPUT MODE
Event Counter
Bits 7:0 = R[7:0] Counter Least Significant Bits.
0
0
1
1
0
1
0
1
Gated Input (Reset value)
Triggerable Input
Retriggerable Input
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TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
Bit 3 = INEN: Input Enable.
This bit is set and cleared by software.
0: Disable input section
by the user program. At System Reset, the Watch-
dog mode is disabled.
Note: This bit is ignored if the Hardware Watchdog
option is enabled by pin HW0SW1 (if available).
1: Enable input section
Bit 2 = OUTMD: Output Mode.
This bit is set and cleared by software.
EXTERNAL INTERRUPT VECTOR REGISTER
(EIVR)
R246 - Read/Write
0: The output is toggled at every End of Count
1: The value of the WROUT bit is transferred to the
output pin on every End Of Count if OUTEN=1.
Register Page: 0
Reset value: xxxx 0110 (x6h)
Bit 1 = WROUT: Write Out.
7
x
0
x
The status of this bit is transferred to the Output
pin when OUTMD is set; it is user definable to al-
low PWM output (on Reset WROUT is set).
x
x
x
x
TLIS IA0S
Bit 2 = TLIS: Top Level Input Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
1: NMI is TL interrupt source
Bit 0 = OUTEN: Output Enable bit.
This bit is set and cleared by software.
0: Disable output
1: Enable output
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source
1: External Interrupt pin is INTA0 source
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Warning: To avoid spurious interrupt requests,
the IA0S bit should be accessed only when the in-
terrupt logic is disabled (i.e. after the DI instruc-
tion). It is also necessary to clear any possible in-
terrupt pending requests on channel A0 before en-
abling this interrupt channel. A delay instruction
(e.g. a NOP instruction) must be inserted between
the reset of the interrupt pending bit and the IA0S
write instruction.
Reset value: 0111 1111 (7Fh)
7
x
0
x
WDGEN
x
x
x
x
x
Bit 6 = WDGEN: Watchdog Enable (active low).
Resetting this bit via software enters the Watch-
dog mode. Once reset, it cannot be set anymore
Other bits are described in the Interrupt section.
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STANDARD TIMER (STIM)
10.2 STANDARD TIMER (STIM)
Important Note: This chapter is a generic descrip-
tion of the STIM peripheral. Depending on the ST9
device, some or all of the interface signals de-
scribed may not be connected to external pins. For
the list of STIM pins present on the particular ST9
device, refer to the pinout description in the first
section of the data sheet.
– triggerable input mode,
– retriggerable input mode.
STOUT can be used to generate a Square Wave
or Pulse Width Modulated signal.
The Standard Timer is composed of a 16-bit down
counter with an 8-bit prescaler. The input clock to
the prescaler can be driven either by an internal
clock equal to INTCLK divided by 4, or by
CLOCK2 derived directly from the external oscilla-
tor, divided by device dependent prescaler value,
thus providing a stable time reference independ-
ent from the PLL programming or by an external
clock connected to the STIN pin.
10.2.1 Introduction
The Standard Timer includes a programmable 16-
bit down counter and an associated 8-bit prescaler
with Single and Continuous counting modes capa-
bility. The Standard Timer uses an input pin (STIN)
and an output (STOUT) pin. These pins, when
available, may be independent pins or connected
as Alternate Functions of an I/O port bit.
The Standard Timer End Of Count condition is
able to generate an interrupt which is connected to
one of the external interrupt channels.
STIN can be used in one of four programmable in-
put modes:
The End of Count condition is defined as the
Counter Underflow, whenever 00h is reached.
– event counter,
– gated external input mode,
Figure 72. Standard Timer Block Diagram
n
INMD1 INMD2
INEN
INPUT
&
1
STIN
STH,STL
16-BIT
DOWNCOUNTER
STP
(See Note 2)
CLOCK CONTROL LOGIC
MUX
8-BIT PRESCALER
STANDARD TIMER
CLOCK
INTCLK/4
END OF
COUNT
CLOCK2/x
OUTMD2
OUTMD1
1
STOUT
OUTPUT CONTROL LOGIC
EXTERNAL
1
INTERRUPT
INTERRUPT
INTS
CONTROL LOGIC
INTERRUPT REQUEST
Note 1: Pin not present on all ST9 devices.
Note 2: Depending on device, the source of the INPUT & CLOCK CONTROL LOGIC block
may be permanently connected either to STIN or the RCCU signal CLOCK2/x. In devices without STIN and CLOCK2, the
INEN bit must be held at 0.
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STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
10.2.2 Functional Description
10.2.2.1 Timer/Counter control
bles the input mode selected by the INMD2 and
INMD1 bits. If the input is disabled (INEN="0"), the
values of INMD2 and INMD1 are not taken into ac-
count. In this case, this unit acts as a 16-bit timer
(plus prescaler) directly driven by INTCLK/4 and
transitions on the input pin have no effect.
Start-stop Count. The ST-SP bit (STC.7) is used
in order to start and stop counting. An instruction
which sets this bit will cause the Standard Timer to
start counting at the beginning of the next instruc-
tion. Resetting this bit will stop the counter.
Event Counter Mode (INMD1 = "0", INMD2 = "0")
The Standard Timer is driven by the signal applied
to the input pin (STIN) which acts as an external
clock. The unit works therefore as an event coun-
ter. The event is a high to low transition on STIN.
Spacing between trailing edges should be at least
the period of INTCLK multiplied by 8 (i.e. the max-
imum Standard Timer input frequency is 3 MHz
with INTCLK = 24MHz).
If the counter is stopped and restarted, counting
will resume from the value held at the stop condi-
tion, unless a new constant has been entered in
the Standard Timer registers during the stop peri-
od. In this case, the new constant will be loaded as
soon as counting is restarted.
A new constant can be written in STH, STL, STP
registers while the counter is running. The new
value of the STH and STL registers will be loaded
at the next End of Count condition, while the new
value of the STP register will be loaded immedi-
ately.
Gated Input Mode (INMD1 = "0", INMD2 = “1”)
The Timer uses the internal clock (INTCLK divided
by 4) and starts and stops the Timer according to
the state of STIN pin. When the status of the STIN
is High the Standard Timer count operation pro-
ceeds, and when Low, counting is stopped.
WARNING: Inordertopreventincorrectcounting of
theStandardTimer,theprescaler(STP)andcounter
(STL, STH) registers must be initialised before the
starting of the timer. If this is not done, counting will
start with the reset values (STH=FFh, STL=FFh,
STP=FFh).
TriggerableInputMode(INMD1=“1”,INMD2=“0”)
The Standard Timer is started by:
a) setting the Start-Stop bit, AND
b) a High to Low (low trigger) transition on STIN.
Single/Continuous Mode.
The S-C bit (STC.6) selects between the Single or
Continuous mode.
In order to stop the Standard Timer in this mode, it
is only necessary to reset the Start-Stop bit.
SINGLE MODE: at the End of Count, the Standard
Timer stops, reloads the constant and resets the
Start/Stop bit (the user programmer can inspect
the timer current status by reading this bit). Setting
the Start/Stop bit will restart the counter.
Retriggerable Input Mode (INMD1 = “1”, INMD2
= “1”)
In this mode, when the Standard Timer is running
(with internal clock), a High to Low transition on
STIN causes the counting to start from the last
constant loaded into the STL/STH and STP regis-
ters. When the Standard Timer is stopped (ST-SP
bit equal to zero), a High to Low transition on STIN
has no effect.
CONTINUOUS MODE: At the End of the Count, the
counter automatically reloads the constant and re-
starts.ItisonlystoppedbyresettingtheStart/Stopbit.
The S-C bit can be written either with the timer
stopped or running. It is possible to toggle the S-C
bit and start the Standard Timer with the same in-
struction.
10.2.2.3 Time Base Generator (ST9 devices
without Standard Timer Input STIN)
For devices where STIN is replaced by a connec-
tion to CLOCK2, the condition (INMD1 = “0”,
INMD2 = “0”) will allow the Standard Timer to gen-
erate a stable time base independent from the PLL
programming.
10.2.2.2 Standard Timer Input Modes (ST9
devices with Standard Timer Input STIN)
Bits INMD2, INMD1 and INEN are used to select
the input modes. The Input Enable (INEN) bit ena-
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STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
10.2.2.4 Standard Timer Output Modes
ic is disabled (i.e. after the DI instruction). It is also
necessary to clear any possible interrupt pending
requests on the corresponding external interrupt
channel before enabling it. A delay instruction (i.e.
a NOP instruction) must be inserted between the
reset of the interrupt pending bit and the INTS
write instruction.
OUTPUT modes are selected using 2 bits of the
STC register: OUTMD1 and OUTMD2.
No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”)
The output is disabled and the corresponding pin
is set high, in order to allow other alternate func-
tions to use the I/O pin.
Square Wave Output Mode (OUTMD1 = “0”,
OUTMD2 = “1”)
10.2.4 Register Mapping
Depending on the ST9 device there may be up to 4
Standard Timers (refer to the block diagram in the
first section of the data sheet).
The Standard Timer toggles the state of the
STOUT pin on every End Of Count condition. With
INTCLK = 24MHz, this allows generation of a
square wave with a period ranging from 333ns to
5.59 seconds.
Each Standard Timer has 4 registers mapped into
Page 11 in Group F of the Register File
In the register description on the following page,
register addresses refer to STIM0 only.
PWM Output Mode (OUTMD1 = “1”)
The value of the OUTMD2 bit is transferred to the
STOUT output pin at the End Of Count. This al-
lows the user to generate PWM signals, by modi-
fying the status of OUTMD2 between End of Count
events, based on software counters decremented
on the Standard Timer interrupt.
STD Timer Register
Register Address
R240 (F0h)
STIM0
STIM1
STIM2
STIM3
STH0
STL0
STP0
STC0
STH1
STL1
STP1
STC1
STH2
STL2
STP2
STC2
STH3
STL3
STP3
STC3
R241 (F1h)
R242 (F2h)
R243 (F3h)
R244 (F4h)
R245 (F5h)
R246 (F6h)
R247 (F7h)
R248 (F8h)
R249 (F9h)
R250 (FAh)
R251 (FBh)
R252 (FCh)
R253 (FDh)
R254 (FEh)
R255 (FFh)
10.2.3 Interrupt Selection
The Standard Timer may generate an interrupt re-
quest at every End of Count.
Bit 2 of the STC register (INTS) selects the inter-
rupt source between the Standard Timer interrupt
and the external interrupt pin. Thus the Standard
Timer Interrupt uses the interrupt channel and
takes the priority and vector of the external inter-
rupt channel.
If INTS is set to “1”, the Standard Timer interrupt is
disabled; otherwise, an interrupt request is gener-
ated at every End of Count.
Note: When enabling or disabling the Standard
Timer Interrupt (writing INTS in the STC register)
an edge may be generated on the interrupt chan-
nel, causing an unwanted interrupt.
Note: The four standard timers are not implement-
ed on all ST9 devices. Refer to the block diagram
of the device for the number of timers.
To avoid this spurious interrupt request, the INTS
bit should be accessed only when the interrupt log-
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9
STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
10.2.5 Register Description
STANDARD TIMER CONTROL REGISTER
(STC)
R243 - Read/Write
Register Page: 11
Reset value: 0001 0100 (14h)
COUNTER HIGH BYTE REGISTER (STH)
R240 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
7
0
7
0
S-C INMD1 INMD2 INEN INTS OUTMD1 OUTMD2
ST-SP
ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9
ST.8
Bit 7 = ST-SP: Start-Stop Bit.
This bit is set and cleared by software.
0: Stop counting
Bits 7:0 = ST.[15:8]: Counter High-Byte.
1: Start counting
COUNTER LOW BYTE REGISTER (STL)
R241 - Read/Write
Bit 6 = S-C: Single-Continuous Mode Select.
This bit is set and cleared by software.
0: Continuous Mode
Register Page: 11
Reset value: 1111 1111 (FFh)
7
0
1: Single Mode
ST.7
ST.6
ST.5
ST.4
ST.3
ST.2
ST.1
ST.0
Bits 5:4 = INMD[1:2]: Input Mode Selection.
These bits select the Input functions as shown in
Section 0.1.2.2, when enabled by INEN.
Bits 7:0 = ST.[7:0]: Counter Low Byte.
Writing to the STH and STL registers allows the
user to enter the Standard Timer constant, while
reading it provides the counter’s current value.
Thus it is possible to read the counter on-the-fly.
INMD1 INMD2 Mode
0
0
1
1
0
1
0
1
Event Counter mode
Gated input mode
Triggerable mode
Retriggerable mode
STANDARD TIMER PRESCALER REGISTER
(STP)
R242 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
Bit 3 = INEN: Input Enable.
This bit is set and cleared by software. If neither
the STIN pin nor the CLOCK2 line are present,
INEN must be 0.
7
0
0: Input section disabled
1: Input section enabled
STP.7 STP.6 STP.5 STP.4 STP.3 STP.2 STP.1 STP.0
Bit 2 = INTS: Interrupt Selection.
0: Standard Timer interrupt enabled
1: Standard Timer interrupt is disabled and the ex-
ternal interrupt pin is enabled.
Bits 7:0 = STP.[7:0]: Prescaler.
The Prescaler value for the Standard Timer is pro-
grammed into this register. When reading the STP
register, the returned value corresponds to the
programmed data instead of the current data.
00h: No prescaler
01h: Divide by 2
FFh: Divide by 256
Bits 1:0 = OUTMD[1:2]: Output Mode Selection.
These bits select the output functions as described
in Section 0.1.2.4.
OUTMD1 OUTMD2 Mode
0
0
1
0
1
x
No output mode
Square wave output mode
PWM output mode
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EXTENDED FUNCTION TIMER (EFT)
Table 27. EFT Pin Naming Conventions
10.3 EXTENDED FUNCTION TIMER (EFT)
10.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
Function
EFT0
EFT1
Input Capture 1 - ICAP1
Input Capture 2 - ICAP2
ICAPA0
ICAPB0
ICAPA1
ICAPB1
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Output Compare 1 -
OCMP1
OCMPA0
OCMPB0
OCMPA1
OCMPB1
Output Compare 2 -
OCMP2
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the INTCLK
prescaler.
10.3.3 Functional Description
10.3.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running counter and its associated
16-bit registers:
10.3.2 Main Features
■ Programmable prescaler: INTCLK divided
by 2, 4 or 8.
Counter Registers
■ Overflow status flag and maskable
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
interrupts
■ External clock input (must be at least 4 times
slower than the INTCLK clock speed) with
the choice of active edge
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
■ Output compare functions with:
– 2 dedicated 16-bit registers
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
– 2 dedicated programmable signals
– 2 dedicated status flags
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note page 137).
– 2 dedicated active edge selection signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternate functions on I/O ports
■ Global timer interrupt (EFTI) mapped on
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 28. The
value in the counter register repeats every
131.072, 262.144 or 524.288 INTCLK cycles de-
pending on the CC1 and CC0 bits.
external interrupt channel
The Block Diagram is shown in Figure 73.
135/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 73. Timer Block Diagram
ST9 INTERNAL BUS
INTCLK
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
h
h
h
gh
w
w
w
w
EXEDG
i
o
i
o
i
o
i
lo
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
16 BIT
FREE RUNNING
COUNTER
1/2
1/4
1/8
1
1
2
2
COUNTER
ALTERNATE
REGISTER
16
16
16
CC1 CC0
TIMER INTERNAL BUS
16
16
OVERFLOW
DETECT
CIRCUIT
EXTCLK
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
ICAP2
6
EDGE DETECT
CIRCUIT2
OCMP1
OCMP2
LATCH1
LATCH2
ICF1 OCF1 TOF ICF2 OCF2
0
0
0
SR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
CR1
CR2
EFTIS
0
0
0
-
-
-
0
INTx
CR3
1
0
EFTI
136/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Clearing the overflow interrupt request is done by:
Register or the Alternate Counter Register).
1. Reading the SR register while the TOF bit is
set.
Beginning of the sequence
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.
Read MSB
At t0
LSB is buffered
Other
instructions
Returns the buffered
LSB value at t0
The timer is not affected by WAIT mode.
Read LSB
At t0 +Dt
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MSB first, then the LSB
value is buffered automatically.
10.3.3.2 External Clock
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit determines the type
of level transition on the external clock pin EXT-
CLK that will trigger the free running counter.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LSB of the count value at the time of the
read.
The counter is synchronised with the falling edge
of INTCLK.
An overflow occurs when the counter rolls over
from FFFFh to 0000h then:
At least four falling edges of the INTCLK must oc-
cur between two consecutive active edges of the
external clock; thus the external clock frequency
must be less than a quarter of the INTCLK fre-
quency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if the TOIE bit of
the CR1 register and the EFTIS bit of the CR3
register are set.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
137/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 74. Counter Timing Diagram, INTCLK divided by 2
INTCLK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 75. Counter Timing Diagram, INTCLK divided by 4
INTCLK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 76. Counter Timing Diagram, INTCLK divided by 8
INTCLK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
OVERFLOW FLAG TOF
138/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.3 Input Capture
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
In this section, the index, i, may be 1 or 2.
When an input capture occurs:
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 78).
MS Byte
LS Byte
– A timer interrupt is generated if the ICIE bit and
the EFTIS bit are set. Otherwise, the interrupt re-
mains pending until both conditions become true.
ICiR
ICiHR
ICiLR
ICi Rregister is a read-only register.
Clearing the Input Capture interrupt request is
done by:
The active transition is software programmable
through the IEDGi bit of the Control Register (CRi).
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Timing resolution is one count of the free running
counter: (INTCLK
).
/CC[1:0]
Note: After reading the ICiHR register, transfer of
input capture data is inhibited until the ICiLR regis-
ter is also read.
Procedure
To use the input capture function select the follow-
ing in the CR2 register:
The ICiR register always contains the free running
counter value which corresponds to the most re-
cent input capture.
– Select the timer clock (CC[1:0] (see Table 28).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Set the ICIE bit and the EFTIS bit to generate an
interrupt after an input capture.
139/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 77. Input Capture Block Diagram
ICAP1
(Control Register 1) CR1
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
(Status Register) SR
ICF1
ICF2
0
0
0
IC1R
IC2R
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
IEDG2
CC0
CC1
COUNTER
Figure 78. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
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9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.4 Output Compare
– A timer interrupt is generated if the OCIE bit in
the CR2 register and the EFTIS bit in the CR3
register are set.
In this section, the index, i, may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
Clearing the output compare interrupt request is
done by:
3. Reading the SR register while the OCFi bit is
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
set.
4. An access (read or write) to the OCiLR register.
– Assigns pins with a programmable value if the
OCiE bit is set
Note: After a processor write cycle to the OCiHR
register, the output compare function is inhibited
until the OCiLR register is also written.
– Sets a flag in the status register
– Generates an interrupt if enabled
If the OCiE bit is not set, the OCMPi pin is a gen-
eral I/O port and the OLVLi bit will not appear
when match is found but an interrupt could be gen-
erated if the OCIE bit is set.
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
The value in the 16-bit OCiR register and the
OLVLi bit should be changed after each success-
ful comparison in order to control an output wave-
form or establish a new elapsed timeout.
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
∆t INTCLK
(CC1.CC0)
*
∆ OCiR =
counter: (INTCLK
).
CC[1:0]
/
Procedure
Where:
To use the output compare function, select the fol-
lowing in the CR2 register:
∆t
= Desired output compare period (in
seconds)
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
function.
INTCLK = Internal clock frequency
CC1-CC0 = Timer clock prescaler
– Select the timer clock CC[1:0] (see Table 28).
And select the following in the CR1 register:
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE and EFTIS bit to generate an inter-
rupt if it is needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When match is found:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to OLVLi level).
141/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 79. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
OLVL2
OLVL1
OCMP1
OCMP2
Latch
2
16-bit
16-bit
OCF1
OCF2
0
0
0
OC2R
OC1R
(Status Register) SR
Figure 80. Output Compare Timing Diagram, Internal Clock Divided by 2
INTCLK
TIMER CLOCK
FFFC FFFD FFFD FFFE
CPU writes FFFF
0000
FFFF
FFFF
COUNTER
OUTPUT COMPARE REGISTER
COMPARE REGISTER LATCH
OCFi AND OCMPi PIN (OLVLi=1)
142/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.5 Forced Compare Mode
Load the OC1R register with the value corre-
sponding to the length of the pulse (see the formu-
la in Section 10.3.3.7).
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
One pulse mode cycle
Counter is
initialized
to FFFCh
FOLV2 FOLV1 OLVL2
OLVL1
When
event occurs
on ICAP1
When the FOLVi bit is set, the OLVLi bit is copied
to the OCMPi pin. The OLVLi bit has to be toggled
in order to toggle the OCMPi pin when it is enabled
(OCiE bit=1).
OCMP1 = OLVL2
OCMP1 = OLVL1
The OCFi bit is not set, and thus no interrupt re-
quest is generated.
When
Counter
= OC1R
10.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin. When the value of the counter
is equal to the value of the contents of the OC1R
register, the OLVL1 bit is output on the OCMP1
pin, (See Figure 81).
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
To use one pulse mode, select the following in the
the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
Note: The OCF1 bit cannot be set by hardware in
one pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is set.
And select the following in the CR2 register:
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
– Set the OC1E bit, the OCMP1 pin is then dedi-
cated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 28).
Figure 81. One Pulse Mode Timing
....
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
143/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.7 Pulse Width Modulation Mode
Where:
– t = Desired output compare period (seconds)
Pulse Width Modulation mode enables the gener-
ation of a signal with a frequency and pulse length
determined by the value of the OC1R and OC2R
registers.
– INTCLK = Internal clock frequency
– CC1-CC0 = Timer clock prescaler
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 82).
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register.
Procedure
Pulse Width Modulation cycle
To use pulse width modulation mode select the fol-
lowing in the CR1 register:
When
Counter
= OC1R
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful com-
parison with OC1R register.
OCMP1 = OLVL1
OCMP1 = OLVL2
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful com-
parison with OC2R register.
When
Counter
= OC2R
And select the following in the CR2 register:
Counter is reset
to FFFCh
– Set OC1E bit: the OCMP1 pin is then dedicated
to the output compare 1 function.
– Set the PWM bit.
Note: After a write instruction to the OCiHR regis-
ter, the output compare function is inhibited until
the OCiLR register is also written.
– Select the timer clock CC[1:0] bits (see Table
28).
Load the OC2R register with the value corre-
sponding to the period of the signal.
The OCF1 and OCF2 bits cannot be set by hard-
ware in PWM mode therefore the Output Compare
interrupt is inhibited. The Input Capture interrupts
are available.
Load the OC1R register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
If OLVL1=1 and OLVL2=0 the length of the pulse
is the difference between the OC2R and OC1R
registers.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t
INTCLK
*
- 5
OCiR Value =
CC[1:0]
Figure 82. Pulse Width Modulation Mode Timing
34E2
FFFC FFFD FFFE
2ED0 2ED1 2ED2
34E2 FFFC
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
144/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.4 Interrupt Management
rupts to avoid any spurious interrupt requests be-
ing performed when the mask bits is set
The interrupts of the Extended Function Timers
are mapped on external interrupt channels of the
microcontroller (refer to the “Interrupts” chapter).
– Set the mask bits of the interrupt channels used
to enable the MCU to acknowledge the interrupt
requests of the peripheral.
The five interrupt sources (2 input captures, 2 out-
put compares and overflow) are mapped on the
same interrupt channel.
Caution: Care should be taken when using only
one of the input capture pins, as both capture in-
terrupts are enabled by the ICIE bit in the CR1 reg-
ister. If only ICAP1 is used (for example), an inter-
rupt can still be generated by the ICAP2 pin when
this pin toggles, even if it is configured as a stand-
ard output. If this case, the interrupt capture status
bits in the SR register should handled in polling
mode.
Each External Interrupt Channel has:
– A trigger control bit in the EITR register (R242 -
Page 0)
– A pending bit in the EIPR register (R243 -
Page 0)
– A mask bit in the EIMR register (R244 - Page 0)
Program the interrupt priority level using the
EIPLR register (R245 - Page 0). For a description
of these registers refer to the “Interrupts” and
“DMA” chapters.
Caution:
1. It is mandatory to clear all EFT interrupt flags
simultaneously at least once before exiting an
EFT timer interrupt routine (the SR register
must = 00h at some point during the interrupt
routine), otherwise no interrupts can be issued
on that channel anymore.
To use the interrupt features, perform the following
sequence:
– Set the priority level of the interrupt channel used
(EIPLR register)
Refer to the following assembly code for an
interrupt sequence example.
– Select the interrupt trigger edge as rising edge
(set the corresponding bit in the EITR register)
– Set the EFTIS bit of the CR3 register to select
the peripheral interrupt sources
2. Since a loop statement is needed inside the IT
routine, the user must avoid situations where
an interrupt event period is narrower than the
duration of the interrupt treatment. Otherwise
nested interrupt mode must be used to serve
higher priority requests.
– Set the OCIE and/or ICIE and/or TOIE bit(s) of
the CR1 register to enable the peripheral to per-
form interrupt requests on the wanted events
– In the EIPR register, reset the pending bit of the
interrupt channel used by the peripheral inter-
145/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Note: A single access (read/write) to the SR regis-
ter at the beginning of the interrupt routine is the
first step needed to clear all the EFT interrupt
flags. In a second step, the lower bytes of the data
registers must be accessed if the corresponding
flag is set. It is not necessary to access the SR
register between these instructions, but it can
done.
; INTERRUPT ROUTINE EXAMPLE
push R234
spp #28
; Save current page
; Set EFT page
L6:
cp R254,#0
jxz L7
; while E0_SR is not cleared
tm R254,#128
jxz L2
; Check Input Capture 1 flag
; else go to next test
ld r1,R241
; Dummy read to clear IC1LR
; Insert your code here
L2:
L3:
tm R254,#16
jxz L3
; Check Input Capture 2 flag
; else go to next test
ld r1,R243
; Insert your code here
; Dummy read to clear IC2LR
tm R254,#64
jxz L4
; Check Input Compare 1 flag
; else go to next test
ld r1,R249
; Dummy read to clear OC1LR
; Insert your code here
L4:
L5:
tm R254,#8
jxz L5
; Check Input Compare 2 flag
; else go to next test
ld r1,R251
; Insert your code here
; Dummy read to clear OC1LR
tm R254,#32
jxz L6
; Check Input Overflow flag
; else go to next test
ld r1,R245
; Dummy read to clear Overflow flag
; Insert your code here
jx L6
L7:
pop R234
; Restore current page
iret
146/324
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EXTENDED FUNCTION TIMER (EFT)
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.5 Register Description
Each Timer is associated with three control and
one status registers, and with six pairs of data reg-
isters (16-bit values) relating to the two input cap-
tures, the two output compares, the counter and
the alternate counter.
R241 - Read Only
Register Page: 28
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
Notes:
1. In the register description on the following pag-
es, register and page numbers are given using the
example of Timer 0. On devices with more than
one timer, refer to the device register map for the
adresses and page numbers.
7
0
MSB
LSB
2. To work correctly with register pairs, it is strong-
ly recommended to use single byte instructions.
Do not use word instructions to access any of the
16-bit registers.
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
R242 - Read Only
Register Page: 28
Reset Value: Undefined
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
R240 - Read Only
Register Page: 28
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
MSB
LSB
7
0
MSB
LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
R243 - Read Only
Register Page: 28
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
147/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
COUNTER HIGH REGISTER (CHR)
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
R244 - Read Only
Register Page: 28
Reset Value: 1111 1111 (FFh)
R246 - Read Only
Register Page: 28
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
COUNTER LOW REGISTER (CLR)
R245 - Read/Write
Register Page: 28
Reset Value: 1111 1100 (FCh)
R247 - Read/Write
Register Page: 28
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
7
0
MSB
LSB
MSB
LSB
148/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
R248 - Read/Write
Register Page: 28
Reset Value: 1000 0000 (80h)
R250 - Read/Write
Register Page: 28
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
R249 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
R251 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
149/324
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
CONTROL REGISTER 1 (CR1)
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin.
R252 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
Bit 3 = FOLV1 Forced Output Compare 1.
0: No effect.
1: Forces OLVL1 to be copied to the OCMP1 pin.
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OC2E is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
Bit 4 = FOLV2 Forced Output Compare 2.
0: No effect.
150/324
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
R253 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
The value of the timer clock depends on these bits:
Bit 7 = OC1E Output Compare 1 Enable.
0: Output Compare 1 function is enabled, but the
OCMP1 pin is a general I/O.
Table 28. Clock Control Bits
1: Output Compare 1 function is enabled, the
OCMP1 pin is dedicated to the Output Compare
1 capability of the timer.
CC1
CC0
Timer Clock
INTCLK / 4
INTCLK / 2
INTCLK / 8
External Clock
0
0
1
1
0
1
0
1
Bit 6 = OC2E Output Compare 2 Enable.
0: Output Compare 2 function is enabled, but the
OCMP2 pin is a general I/O.
1: Output Compare 2 function is enabled, the
OCMP2 pin is dedicated to the Output Compare
2 capability of the timer.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
Bit 0 = EXEDG External Clock Edge.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
free running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
151/324
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
STATUS REGISTER (SR)
CONTROL REGISTER 3 (CR3)
R254 - Read Only
Register Page: 28
R255 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
0
7
0
0
0
0
0
0
0
0
0
EFTIS
ICF1 OCF1 TOF ICF2 OCF2
0
0
Bits 7:1 = Unused Read as 0.
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
Bit 0 = EFTIS Global Timer Interrupt Selection.
0: Select External interrupt.
1: Select Global Timer Interrupt
1: An input capture has occurred. To clear this bit,
first read the SR register, then read or write the
low byte of the IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 5 = TOF Timer Overflow.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred. To clear this bit,
first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 2-0 = Reserved, forced by hardware to 0.
152/324
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Table 29. Extended Function Timer Register Map
Address
(Dec.)
Register
Name
7
6
5
4
3
2
1
0
IC1HR
MSB
x
LSB
x
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
Reset Value
x
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
0
1
0
0
0
0
0
IC1LR
MSB
x
LSB
x
Reset Value
x
x
x
1
1
1
1
0
0
0
0
IC2HR
MSB
x
LSB
x
Reset Value
IC2LR
MSB
x
LSB
x
Reset Value
CHR
MSB
1
LSB
1
Reset Value
CLR
MSB
1
LSB
0
Reset Value
ACHR
MSB
1
LSB
1
Reset Value
ACLR
MSB
1
LSB
0
Reset Value
OC1HR
MSB
1
LSB
0
Reset Value
OC1LR
MSB
0
LSB
0
Reset Value
OC2HR
MSB
1
LSB
0
Reset Value
OC2LR
MSB
0
LSB
0
Reset Value
CR1
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Reset Value
CR2
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Reset Value
SR
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
Reset Value
0
0
0
0
0
CR3
EFTIS
0
Reset Value
0
0
0
0
0
153/324
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Table 30. Extended Function Timer Page Map
Timer number
EFT0
Page (hex)
1C
1D
EFT1
154/324
9
MULTIFUNCTION TIMER (MFT)
10.4 MULTIFUNCTION TIMER (MFT)
10.4.1 Introduction
– 1 input capture, 1 counter reload and 2 inde-
pendent output compares.
The Multifunction Timer (MFT) peripheral offers
powerful timing capabilities and features 12 oper-
ating modes, including automatic PWM generation
and frequency measurement.
– 2 alternate autoreloads and 2 independent out-
put compares.
– 2 alternate captures on the same external line
and 2 independent output compares at a fixed
repetition rate.
The MFT comprises a 16-bit Up/Down counter
driven by an 8-bit programmable prescaler. The in-
put clock may be INTCLK/3 or an external source.
The timer features two 16-bit Comparison Regis-
ters, and two 16-bit Capture/Load/Reload Regis-
ters. Two input pins and two alternate function out-
put pins are available.
When two MFTs are present in an ST9 device, a
combined operating mode is available.
An internal On-Chip Event signal can be used on
some devices to control other on-chip peripherals.
The two external inputs may be individually pro-
grammed to detect any of the following:
Several functional configurations are possible, for
instance:
– rising edges
– 2 input captures on separate external lines, and
2 independent output compare functions with the
counter in free-running mode, or 1 output com-
pare at a fixed repetition rate.
– falling edges
– both rising and falling edges
Figure 83. MFT Simplified Block Diagram
155/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
The configuration of each input is programmed in
the Input Control Register.
synchronise another on-chip peripheral. Five
maskable interrupt sources referring to an End Of
Count condition, 2 input captures and 2 output
compares, can generate 3 different interrupt re-
quests (with hardware fixed priority), pointing to 3
interrupt routine vectors.
Each of the two output pins can be driven from any
of three possible sources:
– Compare Register 0 logic
– Compare Register 1 logic
– Overflow/Underflow logic
Two independent DMA channels are available for
rapid data transfer operations. Each DMA request
(associated with a capture on the REG0R register,
or with a compare on the CMP0R register) has pri-
ority over an interrupt request generated by the
same source.
Each of these three sources can cause one of the
following four actions, independently, on each of
the two outputs:
– Nop, Set, Reset, Toggle
A SWAP mode is also available to allow high
speed continuous transfers (see Interrupt and
DMA chapter).
In addition, an additional On-Chip Event signal can
be generated by two of the three sources men-
tioned above, i.e. Over/Underflow event and Com-
pare 0 event. This signal can be used internally to
Figure 84. Detailed Block Diagram
156/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.2 Functional Description
which may be programmed to respond to the rising
edge, the falling edge or both, by programming
bits A0-A1 and B0-B1 in T_ICR.
The MFT operating modes are selected by pro-
gramming the Timer Control Register (TCR) and
the Timer Mode Register (TMR).
In One Shot and Triggered Mode, every trigger
event arriving before an End Of Count, is masked.
In One Shot and Retriggered Mode, every trigger
received while the counter is running, automatical-
ly reloads the counter from REG0R. Triggered/Re-
triggered Mode is set by the REN bit in TMR.
10.4.2.1 Trigger Events
A trigger event may be generated by software (by
setting either the CP0 or the CP1 bits in the
T_FLAGR register) or by an external source which
may be programmed to respond to the rising edge,
the falling edge or both by programming bits A0-
A1 and B0-B1 in the T_ICR register. This trigger
event can be used to perform a capture or a load,
depending on the Timer mode (configured using
the bits in Table 4).
The TxINA input refers to REG0R and the TxINB
input refers to REG1R.
WARNING. If the Triggered Mode is selected
when the counter is in Continuous Mode, every
trigger is disabled, it is not therefore possible to
synchronise the counting cycle by hardware or
software.
An event on the TxINA input or setting the CP0 bit
triggers a capture to, or a load from the REG0R
register (except in Bicapture mode, see Section
0.1.2.11).
10.4.2.5 Gated Mode
In this mode, counting takes place only when the
external gate input is at a logic low level. The se-
lection of TxINA or TxINB as the gate input is
made by programming the IN0-IN3 bits in T_ICR.
An event on the TxINB input or setting the CP1 bit
triggers a capture to, or a load from the REG1R
register.
In addition, in the special case of "Load from
REG0R and monitor on REG1R", it is possible to
use the TxINB input as a trigger for REG0R."
10.4.2.6 Capture Mode
The REG0R and REG1R registers may be inde-
pendently set in Capture Mode by setting RM0 or
RM1 in TMR, so that a capture of the current count
value can be performed either on REG0R or on
REG1R, initiated by software (by setting CP0 or
CP1 in the T_FLAGR register) or by an event on
the external input pins.
10.4.2.2 One Shot Mode
When the counter generates an overflow (in up-
count mode), or an underflow (in down-count
mode), that is to say when an End Of Count condi-
tion is reached, the counter stops and no counter
reload occurs. The counter may only be restarted
by an external trigger on TxINA or B or a by soft-
ware trigger on CP0 only. One Shot Mode is en-
tered by setting the CO bit in TMR.
WARNING. Care should be taken when two soft-
ware captures are to be performed on the same
register. In this case, at least one instruction must
be present between the first CP0/CP1 bit set and
the subsequent CP0/CP1 bit reset instructions.
10.4.2.3 Continuous Mode
10.4.2.7 Up/Down Mode
Whenever the counter reaches an End Of Count
condition, the counting sequence is automatically
restarted and the counter is reloaded from REG0R
(or from REG1R, when selected in Biload Mode).
Continuous Mode is entered by resetting the C0 bit
in TMR.
The counter can count up or down depending on
the state of the UDC bit (Up/Down Count) in TCR,
or on the configuration of the external input pins,
which have priority over UDC (see Input pin as-
signment in T_ICR). The UDCS bit returns the
counter up/down current status (see also the Up/
Down Autodiscrimination mode in the Input Pin
Assignment Section).
10.4.2.4 Triggered And Retriggered Modes
A triggered event may be generated by software
(by setting either the CP0 or the CP1 bit in the
T_FLAGR register), or by an external source
157/324
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.2.8 Free Running Mode
The Clear On Capture mode allows direct meas-
urement of delta time between successive cap-
tures on REG0R, while the Clear On Compare
mode allows free running with the possibility of
choosing a maximum count value before overflow
or underflow which is less than 2 (see Free Run-
ning Mode).
The timer counts continuously (in Up or Down
mode) and the counter value simply overflows or
underflows through FFFFh or zero; there is no End
Of Count condition as such, and no reloading
takes place. This mode is automatically selected
either in Bi-capture mode or by setting register
REG0R for a Capture function (Continuous mode
must also be set). In Autoclear mode, free running
operation can be selected, with the possibility of
16
10.4.2.11 Bi-value Mode
Depending on the value of the RM0 bit in TMR, the
Bi-load Mode (RM0 reset) or the Bi-capture Mode
(RM0 set) can be selected as illustrated in Figure 1
below:
16
choosing a maximum count value less than 2
before overflow or underflow (see Autoclear
mode).
Table 31. Bi-value Modes
10.4.2.9 Monitor Mode
When the RM1 bit in TMR is reset, and the timer is
not in Bi-value mode, REG1R acts as a monitor,
duplicating the current up or down counter con-
tents, thus allowing the counter to be read “on the
fly”.
TMR bits
RM1
Timer
Operating Modes
RM0
BM
0
1
X
X
1
1
Bi-Load mode
Bi-Capture Mode
10.4.2.10 Autoclear Mode
A) Biload Mode
A clear command forces the counter either to
0000h or to FFFFh, depending on whether up-
counting or downcounting is selected. The counter
reset may be obtained either directly, through the
CCL bit in TCR, or by entering the Autoclear
Mode, through the CCP0 and CCMP0 bits in TCR.
The Bi-load Mode is entered by selecting the Bi-
value Mode (BM set in TMR) and programming
REG0R as a reload register (RM0 reset in TMR).
At any End Of Count, counter reloading is per-
formed alternately from REG0R and REG1R, (a
low level for BM bit always sets REG0R as the cur-
rent register, so that, after a Low to High transition
of BM bit, the first reload is always from REG0R).
Every capture performed on REG0R (if CCP0 is
set), or every successful compare performed by
CMP0R (if CCMP0 is set), clears the counter and
reloads the prescaler.
158/324
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
Every software or external trigger event on
REG0R performs a reload from REG0R resetting
the Biload cycle. In One Shot mode (reload initiat-
ed by software or by an external trigger), reloading
is always from REG0R.
By loading the Prescaler Register of Timer 1 with
the value 00h the two timers (Timer 0 and Timer 1)
are driven by the same frequency in parallel mode.
In this mode the clock frequency may be divided
16
by a factor in the range from 1 to 2 .
B) Bicapture Mode
10.4.2.13 Autodiscriminator Mode
The Bicapture Mode is entered by selecting the Bi-
value Mode (the BM bit in TMR is set) and by pro-
gramming REG0R as a capture register (the RM0
bit in TMR is set).
The phase difference sign of two overlapping puls-
es (respectively on TxINB and TxINA) generates a
one step up/down count, so that the up/down con-
trol and the counter clock are both external. The
setting of the UDC bit in the TCR register has no
effect in this configuration.
Interrupt generation can be configured as an AND
or OR function of the two Capture events. This is
configured by the A0 bit in the T_FLAGR register.
Figure 85. Parallel Mode Description
Every capture event, software simulated (by set-
ting the CP0 flag) or coming directly from the TxI-
NA input line, captures the current counter value
alternately into REG0R and REG1R. When the
BM bit is reset, REG0R is the current register, so
that the first capture, after resetting the BM bit, is
always into REG0R.
MFT0
COUNTER
INTCLK/3
PRESCALER 0
MFT1
COUNTER
10.4.2.12 Parallel Mode
PRESCALER 1
When two MFTs are present on an ST9 device,
the parallel mode is entered when the ECK bit in
the TMR register of Timer 1 is set. The Timer 1
prescaler input is internally connected to the Timer
0 prescaler output. Timer 0 prescaler input is con-
nected to the system clock line.
Note: MFT 1 is not available on all devices. Refer to
the device block diagram and register map.
159/324
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3 Input Pin Assignment
– a trigger signal on the TxINA input pin performs
an U/D counter load if RM0 is reset, or an exter-
nal capture if RM0 is set.
The two external inputs (TxINA and TxINB) of the
timer can be individually configured to catch a par-
ticular external event (i.e. rising edge, falling edge,
or both rising and falling edges) by programming
the two relevant bits (A0, A1 and B0, B1) for each
input in the external Input Control Register
(T_ICR).
– a trigger signal on the TxINB input pin always
performs an external capture on REG1R. The
TxINB input pin is disabled when the Bivalue
Mode is set.
Note: For proper operation of the External Input
The 16 different functional modes of the two exter-
nal inputs can be selected by programming bits
IN0 - IN3 of the T_ICR, as illustrated in Figure 2
pins, the following must be observed:
– the minimum external clock/trigger pulse width
must not be less than the system clock (INTCLK)
period if the input pin is programmed as rising or
falling edge sensitive.
Table 32. Input Pin Function
I C Reg.
IN3-IN0 bits
TxINA Input
Function
TxINB Input
Function
– the minimum external clock/trigger pulse width
must not be less than the prescaler clock period
(INTCLK/3) if the input pin is programmed as ris-
ing and falling edge sensitive (valid also in Auto
discrimination mode).
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
not used
not used
Gate
Gate
not used
Trigger
not used
Trigger
not used
Trigger
– the minimum delay between two clock/trigger
pulse active edges must be greater than the
prescaler clock period (INTCLK/3), while the
minimum delay between two consecutive clock/
trigger pulses must be greater than the system
clock (INTCLK) period.
Ext. Clock
not used
Ext. Clock
Trigger
Clock Down
Ext. Clock
Trigger Down
not used
Autodiscr.
Ext. Clock
Trigger
Gate
Trigger
Clock Up
Up/Down
Trigger Up
Up/Down
Autodiscr.
Trigger
– the minimum gate pulse width must be at least
twice the prescaler clock period (INTCLK/3).
– in Autodiscrimination mode, the minimum delay
between the input pin A pulse edge and the edge
of the input pin B pulse, must be at least equal to
the system clock (INTCLK) period.
Ext. Clock
Trigger
Gate
Some choices relating to the external input pin as-
signment are defined in conjunction with the RM0
and RM1 bits in TMR.
– if a number, N, of external pulses must be count-
ed using a Compare Register in External Clock
mode, then the Compare Register must be load-
ed with the value [X +/- (N-1)], where X is the
starting counter value and the sign is chosen de-
pending on whether Up or Down count mode is
selected.
For input pin assignment codes which use the in-
put pins as Trigger Inputs (except for code 1010,
Trigger Up:Trigger Down), the following conditions
apply:
160/324
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3.1 TxINA = I/O - TxINB = I/O
ister was programmed (i.e. a reload or capture).
The prescaler clock is internally generated and the
up/down selection may be made only by software
via the UDC (Software Up/Down) bit in the TCR
register.
Input pins A and B are not used by the Timer. The
counter clock is internally generated and the up/
down selection may be made only by software via
the UDC (Software Up/Down) bit in the TCR regis-
ter.
10.4.3.2 TxINA = I/O - TxINB = Trigger
The signal applied to input pin B acts as a trigger
signal on REG1R register. The prescaler clock is
internally generated and the up/down selection
may be made only by software via the UDC (Soft-
ware Up/Down) bit in the TCR register.
10.4.3.3 TxINA = Gate - TxINB = I/O
The signal applied to input pin A acts as a gate sig-
nal for the internal clock (i.e. the counter runs only
when the gate signal is at a low level). The counter
clock is internally generated and the up/down con-
trol may be made only by software via the UDC
(Software Up/Down) bit in the TCR register.
(*) The timer is in One shot mode and REGOR in
Reload mode
10.4.3.7 TxINA = Gate - TxINB = Ext. Clock
The signal applied to input pin B, gated by the sig-
nal applied to input pin A, acts as external clock for
the prescaler. The up/down control may be made
only by software action through the UDC bit in the
TCR register.
10.4.3.4 TxINA = Gate - TxINB = Trigger
Both input pins A and B are connected to the timer,
with the resulting effect of combining the actions
relating to the previously described configurations.
10.4.3.8 TxINA = Trigger - TxINB = Trigger
10.4.3.5 TxINA = I/O - TxINB = Ext. Clock
The signal applied to input pin A (or B) acts as trig-
ger signal for REG0R (or REG1R), initiating the
action for which the register has been pro-
grammed. The counter clock is internally generat-
ed and the up/down selection may be made only
by software via the UDC (Software Up/Down) bit in
the TCR register.
The signal applied to input pin B is used as the ex-
ternal clock for the prescaler. The up/down selec-
tion may be made only by software via the UDC
(Software Up/Down) bit in the TCR register.
10.4.3.6 TxINA = Trigger - TxINB = I/O
The signal applied to input pin A acts as a trigger
for REG0R, initiating the action for which the reg-
161/324
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3.9 TxINA = Clock Up - TxINB = Clock
Down
10.4.3.11 TxINA = Trigger Up - TxINB = Trigger
Down
The edge received on input pin A (or B) performs a
one step up (or down) count, so that the counter
clock and the up/down control are external. Setting
the UDC bit in the TCR register has no effect in
this configuration, and input pin B has priority on
input pin A.
Up/down control is performed through both input
pins A and B. A edge on input pin A sets the up
count mode, while a edge on input pin B (which
has priority on input pin A) sets the down count
mode. The counter clock is internally generated,
and setting the UDC bit in the TCR register has no
effect in this configuration.
10.4.3.10 TxINA = Up/Down - TxINB = Ext Clock
10.4.3.12 TxINA = Up/Down - TxINB = I/O
An High (or Low) level applied to input pin A sets
the counter in the up (or down) count mode, while
the signal applied to input pin B is used as clock for
the prescaler. Setting the UDC bit in the TCR reg-
ister has no effect in this configuration.
An High (or Low) level of the signal applied on in-
put pin A sets the counter in the up (or down) count
mode. The counter clock is internally generated.
Setting the UDC bit in the TCR register has no ef-
fect in this configuration.
162/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3.13 Autodiscrimination Mode
ture), while the signal applied to input pin B is used
as the clock for the prescaler.
The phase between two pulses (respectively on in-
put pin B and input pin A) generates a one step up
(or down) count, so that the up/down control and
the counter clock are both external. Thus, if the ris-
ing edge of TxINB arrives when TxINA is at a low
level, the timer is incremented (no action if the ris-
ing edge of TxINB arrives when TxINA is at a high
level). If the falling edge of TxINB arrives when
TxINA is at a low level, the timer is decremented
(no action if the falling edge of TxINB arrives when
TxINA is at a high level).
Setting the UDC bit in the TCR register has no ef-
fect in this configuration.
(*) The timer is in One shot mode and REG0R in
reload mode
10.4.3.15 TxINA = Ext. Clock - TxINB = Trigger
The signal applied to input pin B acts as a trigger,
performing a capture on REG1R, while the signal
applied to input pin A is used as the clock for the
prescaler.
10.4.3.16 TxINA = Trigger - TxINB = Gate
The signal applied to input pin A acts as a trigger
signal on REG0R, initiating the action for which the
register was programmed (i.e. a reload or cap-
ture), while the signal applied to input pin B acts as
a gate signal for the internal clock (i.e. the counter
runs only when the gate signal is at a low level).
10.4.3.14 TxINA = Trigger - TxINB = Ext. Clock
The signal applied to input pin A acts as a trigger
signal on REG0R, initiating the action for which the
register was programmed (i.e. a reload or cap-
163/324
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.4 Output Pin Assignment
OACR is programmed with TxOUTA preset to “0”,
OUF sets TxOUTA, CM0 resets TxOUTA and
CM1 does not affect the output.
OBCR is programmed with TxOUTB preset to “0”,
OUF sets TxOUTB, CM1 resets TxOUTB while
CM0 does not affect the output.
Two external outputs are available when pro-
grammed as Alternate Function Outputs of the I/O
pins.
Two registers Output A Control Register (OACR)
and Output B Control Register (OBCR) define the
driver for the outputs and the actions to be per-
formed.
OACR = [101100X0]
OBCR = [111000X0]
Each of the two output pins can be driven from any
of the three possible sources:
T0OUTA
– Compare Register 0 event logic
– Compare Register 1 event logic
– Overflow/Underflow event logic.
OUF COMP0 OUF COMP0
COMP1
COMP1
Each of these three sources can cause one of the
following four actions on any of the two outputs:
T0OUTB
OUF
OUF
– Nop
– Set
For a configuration where TxOUTA is driven by the
Over/Underflow, by Compare 0 and by Compare
1; TxOUTB is driven by both Compare 0 and Com-
pare 1. OACR is programmed with TxOUTA pre-
set to “0”. OUF toggles Output 0, as do CM0 and
CM1. OBCR is programmed with TxOUTB preset
to “1”. OUF does not affect the output; CM0 resets
TxOUTB and CM1 sets it.
– Reset
– Toggle
Furthermore an On Chip Event signal can be driv-
en by two of the three sources: the Over/Under-
flow event and Compare 0 event by programming
the CEV bit of the OACR register and the OEV bit
of OBCR register respectively. This signal can be
used internally to synchronise another on-chip pe-
ripheral.
OACR = [010101X0]
Output Waveforms
OBCR = [100011X1]
COMP1 COMP1
Depending on the programming of OACR and OB-
CR, the following example waveforms can be gen-
erated on TxOUTA and TxOUTB pins.
T0OUTA
OUF
COMP0
OUF
COMP0
For a configuration where TxOUTA is driven by the
Over/Underflow (OUF) and the Compare 0 event
(CM0), and TxOUTB is driven by the Over/Under-
flow and Compare 1 event (CM1):
COMP1 COMP1
T0OUTB
COMP0
COMP0
164/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
For a configuration where TxOUTA is driven by the
Over/Underflow and by Compare 0, and TxOUTB
is driven by the Over/Underflow and by Compare
1. OACR is programmed with TxOUTA preset to
“0”. OUF sets TxOUTA while CM0 resets it, and
CM1 has no effect. OBCR is programmed with Tx-
OUTB preset to “1”. OUF toggles TxOUTB, CM1
sets it and CM0 has no effect.
Output Waveform Samples In Biload Mode
TxOUTA is programmed to monitor the two time
intervals, t1 and t2, of the Biload Mode, while Tx-
OUTB is independent of the Over/Underflow and
is driven by the different values of Compare 0 and
Compare 1. OACR is programmed with TxOUTA
preset to “0”. OUF toggles the output and CM0 and
CM1 do not affect TxOUTA. OBCR is programmed
with TxOUTB preset to “0”. OUF has no effect,
while CM1 resets TxOUTB and CM0 sets it.
Depending on the CM1/CM0 values, three differ-
ent sample waveforms have been drawn based on
the above mentioned configuration of OBCR. In
the last case, with a different programmed value of
OBCR, only Compare 0 drives TxOUTB, toggling
the output.
For a configuration where TxOUTA is driven by the
Over/Underflow and by Compare 0, and TxOUTB
is driven by Compare 0 and 1. OACR is pro-
grammed with TxOUTA preset to “0”. OUF sets
TxOUTA, CM0 resets it and CM1 has no effect.
OBCR is programmed with TxOUTB preset to “0”.
OUF has no effect, CM0 sets TxOUTB and CM1
toggles it.
OACR = [101100X0]
OBCR = [000111X0]
T0OUTA
OUFCOMP0OUF COMP0
COMP1 COMP1
T0OUTB
COMP0
COMP0
Note (*) Depending on the CMP1R/CMP0R values
165/324
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.5 Interrupt and DMA
10.4.5.1 Timer Interrupt
The two DMA End of Block interrupts are inde-
pendently enabled by the CP0I and CM0I Interrupt
mask bits in the IDMR register.
The timer has 5 different Interrupt sources, be-
longing to 3 independent groups, which are as-
signed to the following Interrupt vectors:
10.4.5.3 DMA Pointers
The 6 programmable most significant bits of the
DMA Counter Pointer Register (DCPR) and of the
DMA Address Pointer Register (DAPR) are com-
mon to both channels (Comp0 and Capt0). The
Comp0 and Capt0 Address Pointers are mapped
as a pair in the Register File, as are the Comp0
and Capt0 DMA Counter pair.
Table 33. Timer Interrupt Structure
Interrupt Source
Vector Address
COMP 0
COMP 1
xxxx x110
CAPT 0
CAPT 1
xxxx x100
xxxx x000
In order to specify either the Capt0 or the Comp0
pointers, according to the channel being serviced,
the Timer resets address bit 1 for CAPT0 and sets
it for COMP0, when the D0 bit in the DCPR regis-
ter is equal to zero (Word address in Register
File). In this case (transfers between peripheral
registers and memory), the pointers are split into
two groups of adjacent Address and Counter pairs
respectively.
Overflow/Underflow
The three least significant bits of the vector pointer
address represent the relative priority assigned to
each group, where 000 represents the highest pri-
ority level. These relative priorities are fixed by
hardware, according to the source which gener-
ates the interrupt request. The 5 most significant
bits represent the general priority and are pro-
grammed by the user in the Interrupt Vector Reg-
ister (T_IVR).
For peripheral register to register transfers (select-
ed by programming “1” into bit 0 of the DCPR reg-
ister), only one pair of pointers is required, and the
pointers are mapped into one group of adjacent
positions.
Each source can be masked by a dedicated bit in
the Interrupt/DMA Mask Register (IDMR) of each
timer, as well as by a global mask enable bit (ID-
MR.7) which masks all interrupts.
The DMA Address Pointer Register (DAPR) is not
used in this case, but must be considered re-
served.
If an interrupt request (CM0 or CP0) is present be-
fore the corresponding pending bit is reset, an
overrun condition occurs. This condition is flagged
in two dedicated overrun bits, relating to the
Comp0 and Capt0 sources, in the Timer Flag Reg-
ister (T_FLAGR).
Figure 86. Pointer Mapping for Transfers
between Registers and Memory
10.4.5.2 Timer DMA
Register File
Two Independent DMA channels, associated with
Comp0 and Capt0 respectively, allow DMA trans-
fers from Register File or Memory to the Comp0
Register, and from the Capt0 Register to Register
File or Memory). If DMA is enabled, the Capt0 and
Comp0 interrupts are generated by the corre-
sponding DMA End of Block event. Their priority is
set by hardware as follows:
YYYYYY11(l)
YYYYYY10(h)
YYYYYY01(l)
YYYYYY00(h)
Address
Pointers
Comp0 16 bit
Addr Pointer
Capt0 16 bit
Addr Pointer
XXXXXX11(l)
XXXXXX10(h)
XXXXXX01(l)
XXXXXX00(h)
DMA
Counters
Comp0 DMA
16 bit Counter
– Compare 0 Destination
– Capture 0 Source
—
Lower Priority
—
Higher Priority
Capt0 DMA
16 bit Counter
The two DMA request sources are independently
maskable by the CP0D and CM0D DMA Mask bits
in the IDMR register.
166/324
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
Figure 87. Pointer Mapping for Register to
Register Transfers
10.4.5.5 DMA Swap Mode
After a complete data table transfer, the transac-
tion counter is reset and an End Of Block (EOB)
condition occurs, the block transfer is completed.
Register File
The End Of Block Interrupt routine must at this
point reload both address and counter pointers of
the channel referred to by the End Of Block inter-
rupt source, if the application requires a continu-
ous high speed data flow. This procedure causes
speed limitations because of the time required for
the reload routine.
8 bit Counter
XXXXXX11
XXXXXX10
XXXXXX01
XXXXXX00
Compare 0
Capture 0
8 bit Addr Pointer
8 bit Counter
8 bit Addr Pointer
The SWAP feature overcomes this drawback, al-
lowing high speed continuous transfers. Bit 2 of
the DMA Counter Pointer Register (DCPR) and of
the DMA Address Pointer Register (DAPR), tog-
gles after every End Of Block condition, alternately
providing odd and even address (D2-D7) for the
pair of pointers, thus pointing to an updated pair,
after a block has been completely transferred. This
allows the User to update or read the first block
and to update the pointer values while the second
is being transferred. These two toggle bits are soft-
ware writable and readable, mapped in DCPR bit 2
for the CM0 channel, and in DAPR bit 2 for the
CP0 channel (though a DMA event on a channel,
in Swap mode, modifies a field in DAPR and
DCPR common to both channels, the DAPR/
DCPR content used in the transfer is always the bit
related to the correct channel).
10.4.5.4 DMA Transaction Priorities
Each Timer DMA transaction is a 16-bit operation,
therefore two bytes must be transferred sequen-
tially, by means of two DMA transfers. In order to
speed up each word transfer, the second byte
transfer is executed by automatically forcing the
peripheral priority to the highest level (000), re-
gardless of the previously set level. It is then re-
stored to its original value after executing the
transfer. Thus, once a request is being serviced,
its hardware priority is kept at the highest level re-
gardless of the other Timer internal sources, i.e.
once a Comp0 request is being serviced, it main-
tains a higher priority, even if a Capt0 request oc-
curs between the two byte transfers.
SWAP mode can be enabled by the SWEN bit in
the IDCR Register.
WARNING: Enabling SWAP mode affects both
channels (CM0 and CP0).
167/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.5.6 DMA End Of Block Interrupt Routine
– Return.
WARNING: The EOB bits are read/write only for
test purposes. Writing a logical “1” by software
(when the SWEN bit is set) will cause a spurious
interrupt request. These bits are normally only re-
set by software.
An interrupt request is generated after each block
transfer (EOB) and its priority is the same as that
assigned in the usual interrupt request, for the two
channels. As a consequence, they will be serviced
only when no DMA request occurs, and will be
subject to a possible OUF Interrupt request, which
has higher priority.
10.4.5.7 DMA Software Protection
A second EOB condition may occur before the first
EOB routine is completed, this would cause a not
yet updated pointer pair to be addressed, with con-
sequent overwriting of memory. To prevent these
errors, a protection mechanism is provided, such
that the attempted setting of the EOB bit before it
has been reset by software will cause the DMA
mask on that channel to be reset (DMA disabled),
thus blocking any further DMA operation. As
shown above, this mask bit should always be
checked in each EOB routine, to ensure that all
DMA transfers are properly served.
The following is a typical EOB procedure (with
swap mode enabled):
– Test Toggle bit and Jump.
– Reload Pointers (odd or even depending on tog-
gle bit status).
– Reset EOB bit: this bit must be reset only after
the old pair of pointers has been restored, so
that, if a new EOB condition occurs, the next pair
of pointers is ready for swapping.
– Verify the software protection condition (see
Section 0.1.5.7).
– Read the corresponding Overrun bit: this con-
firms that no DMA request has been lost in the
meantime.
10.4.6 Register Description
Note: In the register description on the following
pages, register and page numbers are given using
the example of Timer 0. On devices with more
than one timer, refer to the device register map for
the adresses and page numbers.
– Reset the corresponding pending bit.
– Reenable DMA with the corresponding DMA
mask bit (must always be done after resetting
the pending bit)
168/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
CAPTURE LOAD 0 HIGH REGISTER (REG0HR)
COMPARE 0 HIGH REGISTER (CMP0HR)
R240 - Read/Write
Register Page: 10
Reset value: undefined
R244 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
7
0
R15 R14 R13 R12 R11 R10
R9
R8
R15 R14 R13 R12 R11 R10
R9
R8
This register is used to capture values from the
Up/Down counter or load preset values (MSB).
This register is used to store the MSB of the 16-bit
value to be compared to the Up/Down counter
content.
CAPTURE LOAD 0 LOW REGISTER (REG0LR)
COMPARE 0 LOW REGISTER (CMP0LR)
R241 - Read/Write
Register Page: 10
R245 - Read/Write
Reset value: undefined
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
7
0
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
This register is used to capture values from the
Up/Down counter or load preset values (LSB).
This register is used to store the LSB of the 16-bit
value to be compared to the Up/Down counter
content.
CAPTURE LOAD 1 HIGH REGISTER (REG1HR)
R242 - Read/Write
Register Page: 10
Reset value: undefined
COMPARE 1 HIGH REGISTER (CMP1HR)
R246 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
R15 R14 R13 R12 R11 R10
R9
R8
7
0
R15 R14 R13 R12 R11 R10
R9
R8
This register is used to capture values from the
Up/Down counter or load preset values (MSB).
This register is used to store the MSB of the 16-bit
value to be compared to the Up/Down counter
content.
CAPTURE LOAD 1 LOW REGISTER (REG1LR)
R243 - Read/Write
Register Page: 10
Reset value: undefined
COMPARE 1 LOW REGISTER (CMP1LR)
R247 - Read/Write
Register Page: 10
7
0
Reset value: 0000 0000 (00h)
R7
R6
R5
R4
R3
R2
R1
R0
7
0
This register is used to capture values from the
Up/Down counter or load preset values (LSB).
R7
R6
R5
R4
R3
R2
R1
R0
This register is used to store the LSB of the 16-bit
value to be compared to the Up/Down counter
content.
169/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
TIMER CONTROL REGISTER (TCR)
R248 - Read/Write
Register Page: 10
Bit 3 = UDC: Up/Down software selection.
If the direction of the counter is not fixed by hard-
ware (TxINA and/or TxINB pins, see par. 10.3) it
can be controlled by software using the UDC bit.
0: Down counting
Reset value: 0000 0000 (00h)
7
0
1: Up counting
CEN CCP0 CCMP0 CCL UDC UDCS OF0 CS
Bit 2 = UDCS: Up/Down count status.
This bit is read only and indicates the direction of
the counter.
0: Down counting
1: Up counting
Bit 7 = CEN: Counter enable.
This bit is ANDed with the Global Counter Enable
bit (GCEN) in the CICR register (R230). The
GCEN bit is set after the Reset cycle.
0: Stop the counter and prescaler
1: Start the counter and prescaler (without reload).
Bit 1 = OF0: OVF/UNF state.
This bit is read only.
0: No overflow or underflow occurred
1: Overflow or underflow occurred during a Cap-
ture on Register 0
Note: Even if CEN=0, capture and loading will
take place on a trigger event.
Bit 6 = CCP0: Clear on capture.
0: No effect
1: Clear the counter and reload the prescaler on a
REG0R or REG1R capture event
Bit 0 = CS Counter Status.
This bit is read only and indicates the status of the
counter.
0: Counter halted
1: Counter running
Bit 5 = CCMP0: Clear on Compare.
0: No effect
1: Clear the counter and reload the prescaler on a
CMP0R compare event
Bit 4 = CCL: Counter clear.
This bit is reset by hardware after being set by
software (this bit always returns “0” when read).
0: No effect
1: Clear the counter without generating an inter-
rupt request
170/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
TIMER MODE REGISTER (TMR)
R249 - Read/Write
Register Page: 10
Bit 3 = RM0: REG0R mode.
This bit works together with the BM and RM1 bits
to select the timer operating mode. Refer to Table
Reset value: 0000 0000 (00h)
4.
7
0
Table 34. Timer Operating Modes
TMR Bits
OE1 OE0 BM RM1 RM0 ECK REN C0
Timer Operating Modes
BM RM1 RM0
1
1
x
0
1
Biload mode
Bit 7 = OE1: Output 1 enable.
0: Disable the Output 1 (TxOUTB pin) and force it
high.
1: Enable the Output 1 (TxOUTB pin)
The relevant I/O bit must also be set to Alternate
Function
x
Bicapture mode
Load from REG0R and Monitor on
REG1R
0
0
0
1
0
0
Load from REG0R and Capture on
REG1R
Capture on REG0R and Monitor on
REG1R
0
0
0
1
1
1
Bit 6 = OE0: Output 0 enable.
0: Disable the Output 0 (TxOUTA pin) and force it
high
Capture on REG0R and REG1R
1: Enable the Output 0 (TxOUTA pin).
The relevant I/O bit must also be set to Alternate
Function
Bit 2 = ECK Timer clock control.
0: The prescaler clock source is selected depend-
ing on the IN0 - IN3 bits in the T_ICR register
1: Enter Parallel mode (for Timer 1 and Timer 3
only, no effect for Timer 0 and 2). See Section
0.1.2.12.
Bit 5 = BM: Bivalue mode.
This bit works together with the RM1 and RM0 bits
to select the timer operating mode (see Table 4).
0: Disable bivalue mode
Bit 1 = REN: Retrigger mode.
0: Enable retriggerable mode
1: Disable retriggerable mode
1: Enable bivalue mode
Bit 4 = RM1: REG1R mode.
This bit works together with the BM and RM0 bits
to select the timer operating mode. Refer to Table
4.
Bit 0 = CO: Continous/One shot mode.
0: Continuous mode (with autoreload on End of
Count condition)
Note: This bit has no effect when the Bivalue
Mode is enabled (BM=1).
1: One shot mode
171/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
EXTERNAL INPUT CONTROL REGISTER
(T_ICR)
Bits 1:0 = B[0:1]: TxINB Pin event.
These bits are set and cleared by software.
R250 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
B0
B1
TxINB Pin Event
No operation
Falling edge sensitive
Rising edge sensitive
Rising and falling edges
0
0
1
1
0
1
0
1
7
0
IN3
IN2
IN1
IN0
A0
A1
B0
B1
Bits 7:4 = IN[3:0]: Input pin function.
These bits are set and cleared by software.
PRESCALER REGISTER (PRSR)
R251 - Read/Write
Register Page: 10
TxINA
Pin Function
TxINB Input
Pin Function
IN[3:0] bits
Reset value: 0000 0000 (00h)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
not used
not used
Gate
Gate
not used
Trigger
not used
Trigger
not used
Trigger
7
0
P7
P6
P5
P4
P3
P2
P1
P0
Ext. Clock
not used
Ext. Clock
Trigger
Clock Down
Ext. Clock
Trigger Down
not used
Autodiscr.
Ext. Clock
Trigger
This register holds the preset value for the 8-bit
prescaler. The PRSR content may be modified at
any time, but it will be loaded into the prescaler at
the following prescaler underflow, or as a conse-
quence of a counter reload (either by software or
upon external request).
Gate
Trigger
Clock Up
Up/Down
Trigger Up
Up/Down
Autodiscr.
Trigger
Following a RESET condition, the prescaler is au-
tomatically loaded with 00h, so that the prescaler
divides by 1 and the maximum counter clock is
generated (Crystal oscillator clock frequency divid-
ed by 6 when MODER.5 = DIV2 bit is set).
Ext. Clock
Trigger
Gate
The binary value programmed in the PRSR regis-
ter is equal to the divider value minus one. For ex-
ample, loading PRSR with 24 causes the prescal-
er to divide by 25.
Bits 3:2 = A[0:1]: TxINA Pin event.
These bits are set and cleared by software.
A0
A1
TxINA Pin Event
No operation
0
0
1
1
0
1
0
1
Falling edge sensitive
Rising edge sensitive
Rising and falling edges
172/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
OUTPUT A CONTROL REGISTER (OACR)
R252 - Read/Write
Table 35. Output A Action Bits
Action on TxOUTA pin when an xx
event occurs
Register Page: 10
xxE0
xxE1
Reset value: 0000 0000
0
0
1
1
0
1
0
1
Set
7
0
Toggle
Reset
NOP
C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P
Bits 7:6 = C0E[0:1]: COMP0 action bits.
Notes:
These bits are set and cleared by software. They
configure the action to be performed on the Tx-
OUTA pin when a successful compare of the
CMP0R register occurs. Refer to Table 5 for the
list of actions that can be configured.
– xx stands for C0, C1 or OU.
– Whenever more than one event occurs simulta-
neously, Action bit 0 will be the result of ANDing
Action bit 0 of all simultaneous events and Action
bit 1 will be the result of ANDing Action bit 1 of all
simultaneous events.
Bits 5:4 = C1E[0:1]: COMP1 action bits.
These bits are set and cleared by software. They
configure the action to be performed on the Tx-
OUTA pin when a successful compare of the
CMP1R register occurs. Refer to Table 5 for the
list of actions that can be configured.
Bit 1 = CEV: On-Chip event on CMP0R.
This bit is set and cleared by software.
0: No action
1: A successful compare on CMP0R activates the
on-chip event signal (a single pulse is generat-
ed)
Bits 3:2 = OUE[0:1]: OVF/UNF action bits.
These bits are set and cleared by software. They
configure the action to be performed on the Tx-
OUTA pin when an Overflow or Underflow of the
U/D counter occurs. Refer to Table 5 for the list of
actions that can be configured.
Bit 0 = OP: TxOUTA preset value.
This bit is set and cleared by software and by hard-
ware. The value of this bit is the preset value of the
TxOUTA pin. Reading this bit returns the current
state of the TxOUTA pin (useful when it is selected
in toggle mode).
173/324
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
OUTPUT B CONTROL REGISTER (OBCR)
R253 - Read/Write
Table 36. Output B Action Bits
Action on the TxOUTB pin when an
xx event occurs
Register Page: 10
xxE0
xxE1
Reset value: 0000 0000 (00h)
0
0
1
1
0
1
0
1
Set
7
0
Toggle
Reset
NOP
C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 OEV 0P
Bits 7:6 = C0E[0:1]: COMP0 Action Bits.
Notes:
These bits are set and cleared by software. They
configure the type of action to be performed on the
TxOUTB output pin when successful compare of
the CMP0R register occurs. Refer to Table 6 for
the list of actions that can be configured.
– xx stands for C0, C1 or OU.
– Whenever more than one event occurs simulta-
neously, Action Bit 0 will be the result of ANDing
Action Bit 0 of all simultaneous events and Action
Bit 1 will be the result of ANDing Action Bit 1 of
all simultaneous events.
Bits 5:4 = C0E[0:1]: COMP1 Action Bits.
These bits are set and cleared by software. They
configure the type of action to be performed on the
TxOUTB output pin when a successful compare of
the CMP1R register occurs. Refer to Table 6 for
the list of actions that can be configured.
Bit 1 = OEV: On-Chip event on OVF/UNF.
This bit is set and cleared by software.
0: No action
1: An underflow/overflow activates the on-chip
event signal (a single pulse is generated)
Bits 3:2 = OUE[0:1]: OVF/UNF Action Bits.
These bits are set and cleared by software.They
configure the type of action to be performed on the
TxOUTB output pin when an Overflow or Under-
flow on the U/D counter occurs. Refer to Table 6
for the list of actions that can be configured.
Bit 0 = OP: TxOUTB preset value.
This bit is set and cleared by software and by hard-
ware. The value of this bit is the preset value of the
TxOUTB pin. Reading this bit returns the current
state of the TxOUTB pin (useful when it is selected
in toggle mode).
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9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
FLAG REGISTER (T_FLAGR)
R254 - Read/Write
Register Page: 10
GTIEN and CM1I bits in the IDMR register are set.
The CM1 bit is cleared by software.
0: No Compare 1 event
Reset value: 0000 0000 (00h)
1: Compare 1 event occurred
7
0
Bit 3 = OUF: Overflow/Underflow.
CP0 CP1 CM0 CM1 OUF OCP0 OCM0 A0
This bit is set by hardware after a counter Over/
Underflow condition. An interrupt is generated if
GTIEN and OUI=1 in the IDMR register. The OUF
bit is cleared by software.
0: No counter overflow/underflow
1: Counter overflow/underflow
Bit 7 = CP0: Capture 0 flag.
This bit is set by hardware after a capture on
REG0R register. An interrupt is generated de-
pending on the value of the GTIEN, CP0I bits in
the IDMR register and the A0 bit in the T_FLAGR
register. The CP0 bit must be cleared by software.
Setting by software acts as a software load/cap-
ture to/from the REG0R register.
Bit 2 = OCP0: Overrun on Capture 0.
This bit is set by hardware when more than one
INT/DMA requests occur before the CP0 flag is
cleared by software or whenever a capture is sim-
ulated by setting the CP0 flag by software. The
OCP0 flag is cleared by software.
0: No Capture 0 event
1: Capture 0 event occurred
0: No capture 0 overrun
1: Capture 0 overrun
Bit 6 = CP1: Capture 1 flag.
This bit is set by hardware after a capture on
REG1R register. An interrupt is generated de-
pending on the value of the GTIEN, CP0I bits in
the IDMR register and the A0 bit in the T_FLAGR
register. The CP1 bit must be cleared by software.
Setting by software acts as a capture event on the
REG1R register, except when in Bicapture mode.
0: No Capture 1 event
Bit 1 = OCM0: Overrun on compare 0.
This bit is set by hardware when more than one
INT/DMA requests occur before the CM0 flag is
cleared by software.The OCM0 flag is cleared by
software.
0: No compare 0 overrun
1: Compare 0 overrun
1: Capture 1 event occurred
Bit 5 = CM0: Compare 0 flag.
Bit 0 = A0: Capture interrupt function.
This bit is set and cleared by software.
0: Configure the capture interrupt as an OR func-
tion of REG0R/REG1R captures
1: Configure the capture interrupt as an AND func-
tion of REG0R/REG1R captures
This bit is set by hardware after a successful com-
pare on the CMP0R register. An interrupt is gener-
ated if the GTIEN and CM0I bits in the IDMR reg-
ister are set. The CM0 bit is cleared by software.
0: No Compare 0 event
1: Compare 0 event occurred
Note: When A0 is set, both CP0I and CP1I in the
IDMR register must be set to enable both capture
interrupts.
Bit 4 = CM1: Compare 1 flag.
This bit is set after a successful compare on
CMP1R register. An interrupt is generated if the
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9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
INTERRUPT/DMA MASK REGISTER (IDMR)
R255 - Read/Write
Register Page: 10
Bit 1 = CM1I: Compare 1 Interrupt mask.
This bit is set and cleared by software.
0: Disable compare on CMP1R interrupt
1: Enable compare on CMP1R interrupt
Reset value: 0000 0000 (00h)
7
0
GTIEN CP0D CP0I CP1I CM0D CM0I CM1I OUI
Bit 0 = OUI:
Overflow/Underflow interrupt mask.
This bit is set and cleared by software.
0: Disable Overflow/Underflow interrupt
1: Enable Overflow/Underflow interrupt
Bit 7 = GTIEN: Global timer interrupt enable.
This bit is set and cleared by software.
0: Disable all Timer interrupts
1: Enable all timer Timer Interrupts from enabled
sources
DMA COUNTER POINTER REGISTER (DCPR)
R240 - Read/Write
Register Page: 9
Reset value: undefined
Bit 6 = CP0D: Capture 0 DMA mask.
This bit is set by software to enable a Capt0 DMA
transfer and cleared by hardware at the end of the
block transfer.
7
0
DMA REG/
SRCE MEM
0: Disable capture on REG0R DMA
1: Enable capture on REG0R DMA
DCP7 DCP6 DCP5 DCP4 DCP3 DCP2
Bits 7:2 = DCP[7:2]: MSBs of DMA counter regis-
ter address.
These are the most significant bits of the DMA
counter register address programmable by soft-
ware. The DCP2 bit may also be toggled by hard-
ware if the Timer DMA section for the Compare 0
channel is configured in Swap mode.
Bit 5 = CP0I: Capture 0 interrupt mask.
0: Disable capture on REG0R interrupt
1: Enable capture on REG0R interrupt (or Capt0
DMA End of Block interrupt if CP0D=1)
Bit 4 = CP1I: Capture 1 interrupt mask.
This bit is set and cleared by software.
0: Disable capture on REG1R interrupt
1: Enable capture on REG1R interrupt
Bit 1 = DMA-SRCE: DMA source selection.
This bit is set and cleared by hardware.
0: DMA source is a Capture on REG0R register
1: DMA destination is a Compare on CMP0R reg-
ister
Bit 3 = CM0D: Compare 0 DMA mask.
This bit is set by software to enable a Comp0 DMA
transfer and cleared by hardware at the end of the
block transfer.
0: Disable compare on CMP0R DMA
1: Enable compare on CMP0R DMA
Bit 0 = REG/MEM: DMA area selection.
This bit is set and cleared by software. It selects
the source and destination of the DMA area
0: DMA from/to memory
Bit 2 = CM0I: Compare 0 Interrupt mask.
This bit is set and cleared by software.
0: Disable compare on CMP0R interrupt
1: Enable compare on CMP0R interrupt (or
Comp0 DMA End of Block interrupt if CM0D=1)
1: DMA from/to Register File
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9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
DMA ADDRESS POINTER REGISTER (DAPR)
R241 - Read/Write
Register Page: 9
INTERRUPT VECTOR REGISTER (T_IVR)
R242 - Read/Write
Register Page: 9
Reset value: xxxx xxx0
Reset value: undefined
7
0
7
0
0
DMA PRG
SRCE /DAT
DAP7 DAP6 DAP5 DAP4 DAP3 DAP2
V4
V3
V2
V1
V0
W1
W0
Bits 7:2 = DAP[7:2]: MSB of DMA address regis-
ter location.
These are the most significant bits of the DMA ad-
dress register location programmable by software.
The DAP2 bit may also be toggled by hardware if
the Timer DMA section for the Compare 0 channel
is configured in Swap mode.
This register is used as a vector, pointing to the
16-bit interrupt vectors in memory which contain
the starting addresses of the three interrupt sub-
routines managed by each timer.
Only one Interrupt Vector Register is available for
each timer, and it is able to manage three interrupt
groups, because the 3 least significant bits are
fixed by hardware depending on the group which
generated the interrupt request.
Note: During a DMA transfer with the Register
File, the DAPR is not used; however, in Swap
mode, DAP2 is used to point to the correct table.
In order to determine which request generated the
interrupt within a group, the T_FLAGR register can
be used to check the relevant interrupt source.
Bit 1 = DMA-SRCE: DMA source selection.
This bit is fixed by hardware.
0: DMA source is a Capture on REG0R register
1: DMA destination is a Compare on the CMP0R
register
Bits 7:3 = V[4:0]: MSB of the vector address.
These bits are user programmable and contain the
five most significant bits of the Timer interrupt vec-
tor addresses in memory. In any case, an 8-bit ad-
dress can be used to indicate the Timer interrupt
vector locations, because they are within the first
256 memory locations (see Interrupt and DMA
chapters).
Bit 0 = PRG/DAT: DMA memory selection.
This bit is set and cleared by software. It is only
meaningful if DCPR.REG/MEM=0.
0: The ISR register is used to extend the address
of data transferred by DMA (see MMU chapter).
1: The DMASR register is used to extend the ad-
dress of data transferred by DMA (see MMU
chapter).
Bits 2:1 = W[1:0]: Vector address bits.
These bits are equivalent to bit 1 and bit 2 of the
Timer interrupt vector addresses in memory. They
are fixed by hardware, depending on the group of
sources which generated the interrupt request as
follows:.
REG/MEM PRG/DAT
DMA Source/Destination
0
0
ISR register used to address
memory
0
1
DMASR register used to address
memory
W1
W0
Interrupt Source
1
1
0
1
Register file
Register file
0
0
1
1
0
1
0
1
Overflow/Underflow even interrupt
Not available
Capture event interrupt
Compare event interrupt
Bit 0 = This bit is forced by hardware to 0.
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9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
INTERRUPT/DMA CONTROL REGISTER
(IDCR)
R243 - Read/Write
Register Page: 9
Reset value: 1100 0111 (C7h)
Bit 3 = SWEN: Swap function enable.
This bit is set and cleared by software.
0: Disable Swap mode
1: Enable Swap mode for both DMA channels.
7
0
Bits 2:0 = PL[2:0]: Interrupt/DMA priority level.
With these three bits it is possible to select the In-
terrupt and DMA priority level of each timer, as one
of eight levels (see Interrupt/DMA chapter).
CPE CME DCTS DCTD SWEN PL2 PL1 PL0
Bit 7 = CPE: Capture 0 EOB.
This bit is set by hardware when the End Of Block
condition is reached during a Capture 0 DMA op-
eration with the Swap mode enabled. When Swap
mode is disabled (SWEN bit = “0”), the CPE bit is
forced to 1 by hardware.
0: No end of block condition
1: Capture 0 End of block
I/O CONNECTION REGISTER (IOCR)
R248 - Read/Write
Register Page: 9
Reset value: 1111 1100 (FCh)
7
0
SC1 SC0
Bit 6 = CME: Compare 0 EOB.
This bit is set by hardware when the End Of Block
condition is reached during a Compare 0 DMA op-
eration with the Swap mode enabled. When the
Swap mode is disabled (SWEN bit = “0”), the CME
bit is forced to 1 by hardware.
0: No end of block condition
1: Compare 0 End of block
Bits 7:2 = not used.
Bit 1 = SC1: Select connection odd.
This bit is set and cleared by software. It selects if
the TxOUTA and TxINA pins for Timer 1 and Timer
3 are connected on-chip or not.
0: T1OUTA / T1INA and T3OUTA/ T3INA uncon-
nected
Bit 5 = DCTS: DMA capture transfer source.
This bit is set and cleared by software. It selects
the source of the DMA operation related to the
channel associated with the Capture 0.
Note: The I/O port source is available only on spe-
cific devices.
1: T1OUTA connected internally to T1INA and
T3OUTA connected internally to T3INA
Bit 0 = SC0: Select connection even.
This bit is set and cleared by software. It selects if
the TxOUTA and TxINA pins for Timer 0 and Timer
2 are connected on-chip or not.
0: T0OUTA / T0INA and T2OUTA/ T2INA uncon-
nected
0: REG0R register
1: I/O port.
Bit 4 = DCTD: DMA compare transfer destination.
This bit is set and cleared by software. It selects
the destination of the DMA operation related to the
channel associated with Compare 0.
Note: The I/O port destination is available only on
specific devices.
1: T0OUTA connected internally to T0INA and
T2OUTA connected internally to T2INA
Note: Timer 1 and 2 are available only on some
devices. Refer to the device block diagram and
register map.
0: CMP0R register
1: I/O port
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
10.5.1 Introduction
■ Programmable address indication bit (wake-up
bit) and user invisible compare logic to support
multiple microcomputer networking. Optional
character search function.
The Multiprotocol Serial Communications Inter-
face (SCI-M) offers full-duplex serial data ex-
change with a wide range of external equipment.
The SCI-M offers four operating modes: Asynchro-
nous, Asynchronous with synchronous clock, Seri-
al expansion and Synchronous.
■ Internal diagnostic capabilities:
– Local loopback for communications link fault
isolation.
– Auto-echo for communications link fault isola-
tion.
10.5.2 Main Features
■ Full duplex synchronous and asynchronous
operation.
■ Separate interrupt/DMA channels for transmit
■ Transmit, receive, line status, and device
and receive.
address interrupt generation.
■ In addition, a Synchronous mode supports:
■ Integral Baud Rate Generator capable of
– High speed communication
– Possibility of hardware synchronization (RTS/
DCD signals).
– Programmable polarity and stand-by level for
data SIN/SOUT.
– Programmable active edge and stand-by level
for clocks CLKOUT/RXCL.
– Programmable active levels of RTS/DCD sig-
nals.
– Full Loop-Back and Auto-Echo modes for DA-
TA, CLOCKs and CONTROLs.
dividing the input clock by any value from 2 to
16
2 -1 (16 bit word) and generating the internal
16X data sampling clock for asynchronous
operation or the 1X clock for synchronous
operation.
■ Fully programmable serial interface:
– 5, 6, 7, or 8 bit word length.
– Even, odd, or no parity generation and detec-
tion.
– 0, 1, 1.5, 2, 2.5, 3 stop bit generation.
– Complete status reporting capabilities.
– Line break generation and detection.
Figure 88. SCI-M Block Diagram
ST9 CORE BUS
DMA
CONTROLLER
DMA
CONTROLLER
TRANSMIT
BUFFER
REGISTER
ADDRESS
COMPARE
REGISTER
RECEIVER
BUFFER
REGISTER
RECEIVER
SHIFT
REGISTER
TRANSMIT
SHIFT
REGISTER
Frame Control
and STATUS
CLOCK and
BAUD RATE
GENERATOR
ALTERNATE
FUNCTION
VA00169A
SDS
SOUT RTS
TXCLK/CLKOUT RXCLK DCD
SIN
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.3 Functional Description
The SCI-M has four operating modes:
– Asynchronous mode
Asynchronous mode, Asynchronous mode with
synchronous clock and Serial expansion mode
output data with the same serial frame format. The
differences lie in the data sampling clock rates
(1X, 16X) and in the protocol used.
– Asynchronous mode with synchronous clock
– Serial expansion mode
– Synchronous mode
Figure 89. SCI -M Functional Schematic
INPL (*)
INTCLK
XBRG
RX buffer
register
RX shift
register
Baud rate
LBEN (*)
Sin
generator
RXclk
1
0
LBEN
Divider by 16
CD
1
OUTPL (*)
XRX
INPEN (*)
OCKPL (*)
Divider by 16
0
TX shift
Sout
register
CD
OCLK
AEN
OUTSB (*)
TX buffer
register
DCDEN (*)
AEN (*)
Enveloper
OCLK
Polarity
Polarity
OCKSB (*)
XTCLK
AEN (*)
RTSEN (*)
VR02054
TXclk / CLKout
DCD
RTS
The control signals marked with (*) are active only in synchronous mode (SMEN=1)
Note: Some pins may not be available on some devices. Refer to the device Pinout Description.
180/324
9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4 SCI-M Operating Modes
10.5.4.1 Asynchronous Mode
10.5.4.2
Synchronous Clock
Asynchronous
Mode
with
In this mode, data and clock are synchronous,
each data bit is sampled once per clock period.
In this mode, data and clock can be asynchronous
(the transmitter and receiver can use their own
clocks to sample received data), each data bit is
sampled 16 times per clock period.
For transmit operation, a general purpose I/O port
pin can be programmed to output the CLKOUT
signal from the baud rate generator. If the SCI is
provided with an external transmission clock
source, there will be a skew equivalent to two
INTCLK periods between clock and data.
The baud rate clock should be set to the ÷16 Mode
and the frequency of the input clock (from an ex-
ternal source or from the internal baud-rate gener-
ator output) is set to suit.
Data will be transmitted on the falling edge of the
transmit clock. Received data will be latched into
the SCI on the rising edge of the receive clock.
Figure 90. Sampling Times in Asynchronous Format
SDIN
rcvck
0
1
2
3
4
5
7
8
9
10
11
12
13
14
15
rxd
rxclk
VR001409
LEGEND:
Serial Data Input line
SIN:
rcvck: Internal X16 Receiver Clock
Internal Serial Data Input Line
Internal Receiver Shift Register Sampling Clock
rxd:
rxclk:
181/324
9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.3 Serial Expansion Mode
the Clock Configuration Register. Whenever the
SCI is to receive data in synchronous mode, the
clock waveform must be supplied externally via
the RXCLK pin and be synchronous with the data.
For correct receiver operation, the XRX bit of the
Clock Configuration Register must be set.
This mode is used to communicate with an exter-
nal synchronous peripheral.
The transmitter only provides the clock waveform
during the period that data is being transmitted on
the CLKOUT pin (the Data Envelope). Data is
latched on the rising edge of this clock.
Two external signals, Request-To-Send and Data-
Carrier-Detect (RTS/DCD), can be enabled to syn-
chronise the data exchange between two serial
units. The RTS output becomes active just before
the first active edge of CLKOUT and indicates to
the target device that the MCU is about to send a
synchronous frame; it returns to its stand-by state
following the last active edge of CLKOUT (MSB
transmitted).
Whenever the SCI is to receive data in serial port
expansion mode, the clock must be supplied ex-
ternally, and be synchronous with the transmitted
data. The SCI latches the incoming data on the ris-
ing edge of the received clock, which is input on
the RXCLK pin.
10.5.4.4 Synchronous Mode
The DCD input can be considered as a gate that
filters RXCLK and informs the MCU that a trans-
mitting device is transmitting a data frame. Polarity
of RTS/DCD is individually programmable, as for
clocks and data.
This mode is used to access an external synchro-
nous peripheral, dummy start/stop bits are not in-
cluded in the data frame. Polarity, stand-by level
and active edges of I/O signals are fully and sepa-
rately programmable for both inputs and outputs.
The data word is programmable from 5 to 8 bits, as
for the other modes; parity, address/9th, stop bits
and break cannot be inserted into the transmitted
frame. Programming of the related bits of the SCI
control registers is irrelevant in Synchronous
Mode: all the corresponding interrupt requests
must, in any case, be masked in order to avoid in-
correct operation during data reception.
It's necessary to set the SMEN bit of the Synchro-
nous Input Control Register (SICR) to enable this
mode and all the related extra features (otherwise
disabled).
The transmitter will provide the clock waveform
only during the period when the data is being
transmitted via the CLKOUT pin, which can be en-
abled by setting both the XTCLK and OCLK bits of
182/324
9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 91. SCI -M Operating Modes
PARITY
STOP BIT
I/O
DATA
PARITY
START BIT
16
DATA
I/O
STOP BIT
16
16
START BIT
CLOCK
CLOCK
VA00271
VA00272
Asynchronous Mode
Asynchronous Mode
with Synchronous Clock
stand-by
stand-by
stand-by
DATA
CLOCK
stand-by
stand-by
I/O
DATA
START BIT
(Dummy)
STOP BIT
(Dummy)
CLOCK
RTS/DCD
stand-by
VA0273A
VR02051
Serial Expansion Mode
Synchronous Mode
Note: In all operating modes, the Least Significant Bit is transmitted/received first.
183/324
9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.5 Serial Frame Format
Characters sent or received by the SCI can have
some or all of the features in the following format,
depending on the operating mode:
both Serial Expansion and Asynchronous modes
to indicate that the data is an address (bit set).
The ADDRESS/9TH bit is useful when several mi-
crocontrollers are exchanging data on the same
serial bus. Individual microcontrollers can stay idle
on the serial bus, waiting for a transmitted ad-
dress. When a microcontroller recognizes its own
address, it can begin Data Reception, likewise, on
the transmit side, the microcontroller can transmit
another address to begin communication with a
different microcontroller.
START: the START bit indicates the beginning of
a data frame in Asynchronous modes. The START
condition is detected as a high to low transition.
A dummy START bit is generated in Serial Expan-
sion mode. The START bit is not generated in
Synchronous mode.
DATA: the DATA word length is programmable
from 5 to 8 bits, for both Synchronous and Asyn-
chronous modes. LSB are transmitted first.
The ADDRESS/9TH bit can be used as an addi-
tional data bit or to mark control words (9th bit).
PARITY: The Parity Bit (not available in Serial Ex-
pansion mode and Synchronous mode) is option-
al, and can be used with any word length. It is used
for error checking and is set so as to make the total
number of high bits in DATA plus PARITY odd or
even, depending on the number of “1”s in the
DATA field.
STOP: Indicates the end of a data frame in Asyn-
chronous modes. A dummy STOP bit is generated
in Serial Expansion mode. The STOP bit can be
programmed to be 1, 1.5, 2, 2.5 or 3 bits long, de-
pending on the mode. It returns the SCI to the qui-
escent marking state (i.e., a constant high-state
condition) which lasts until a new start bit indicates
an incoming word. The STOP bit is not generated
in Synchronous mode.
ADDRESS/9TH: The Address/9th Bit is optional
and may be added to any word format. It is used in
Figure 92. SCI Character Formats
(2)
(1)
(3)
(2)
(2)
START
DATA
PARITY
ADDRESS
STOP
1, 1.5, 2, 2.5,
1, 2, 3
16X
1X
# bits
1
5, 6, 7, 8
0, 1
0, 1
NONE
ODD
EVEN
ON
OFF
states
(1)
LSB First
(2)
(3)
Not available in Synchronous mode
Not available in Serial Expansion mode
and Synchronous mode
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.5.1 Data transfer
Data to be transmitted by the SCI is first loaded by
the program into the Transmitter Buffer Register.
The SCI will transfer the data into the Transmitter
Shift Register when the Shift Register becomes
available (empty). The Transmitter Shift Register
converts the parallel data into serial format for
transmission via the SCI Alternate Function out-
put, Serial Data Out. On completion of the transfer,
the transmitter buffer register interrupt pending bit
will be updated. If the selected word length is less
than 8 bits, the unused most significant bits do not
need to be defined.
The character match Address Interrupt mode may
be used as a powerful character search mode,
generating an interrupt on reception of a predeter-
mined character e.g. Carriage Return or End of
Block codes (Character Match Interrupt). This is
the only Address Interrupt Mode available in Syn-
chronous mode.
The Line Break condition is fully supported for both
transmission and reception. Line Break is sent by
setting the SB bit (IDPR). This causes the trans-
mitter output to be held low (after all buffered data
has been transmitted) for a minimum of one com-
plete word length and until the SB bit is Reset.
Break cannot be inserted into the transmitted
frame for the Synchronous mode.
Incoming serial data from the Serial Data Input pin
is converted into parallel format by the Receiver
Shift Register. At the end of the input data frame,
the valid data portion of the received word is trans-
ferred from the Receiver Shift Register into the Re-
ceiver Buffer Register. All Receiver interrupt con-
ditions are updated at the time of transfer. If the
selected character format is less than 8 bits, the
unused most significant bits will be set.
Testing of the communications channel may be
performed using the built-in facilities of the SCI pe-
ripheral. Auto-Echo mode and Loop-Back mode
may be used individually or together. In Asynchro-
nous, Asynchronous with Synchronous Clock and
Serial Expansion modes they are available only on
SIN/SOUT pins through the programming of AEN/
LBEN bits in CCR. In Synchronous mode (SMEN
set) the above configurations are available on SIN/
SOUT, RXCLK/CLKOUT and DCD/RTS pins by
programming the AEN/LBEN bits and independ-
ently of the programmed polarity. In the Synchro-
nous mode case, when AEN is set, the transmitter
outputs (data, clock and control) are disconnected
from the I/O pins, which are driven directly by the
receiver input pins (Auto-Echo mode: SOUT=SIN,
CLKOUT=RXCLK and RTS=DCD, even if they act
on the internal receiver with the programmed po-
larity/edge). When LBEN is set, the receiver inputs
(data, clock and controls) are disconnected and
the transmitter outputs are looped-back into the re-
ceiver section (Loop-Back mode: SIN=SOUT, RX-
CLK=CLKOUT, DCD=RTS. The output pins are
locked to their programmed stand-by level and the
status of the INPL, XCKPL, DCDPL, OUTPL,
OCKPL and RTSPL bits in the SICR register are ir-
relevant). Refer to Figure 6, Figure 7, and Figure 8
for these different configurations.
The Frame Control and Status block creates and
checks the character configuration (Data length
and number of Stop bits), as well as the source of
the transmitter/receiver clock.
The internal Baud Rate Generator contains a pro-
grammable divide by “N” counter which can be
used to generate the clocks for the transmitter
and/or receiver. The baud rate generator can use
INTCLK or the Receiver clock input via RXCLK.
The Address bit/D9 is optional and may be added
to any word in Asynchronous and Serial Expan-
sion modes. It is commonly used in network or ma-
chine control applications. When enabled (AB set),
an address or ninth data bit can be added to a
transmitted word by setting the Set Address bit
(SA). This is then appended to the next word en-
tered into the (empty) Transmitter Buffer Register
and then cleared by hardware. On character input,
a set Address Bit can indicate that the data pre-
ceding the bit is an address which may be com-
pared in hardware with the value in the Address
Compare Register (ACR) to generate an Address
Match interrupt when equal.
Table 37. Address Interrupt Modes
(1)
The Address bit and Address Comparison Regis-
ter can also be combined to generate four different
types of Address Interrupt to suit different proto-
cols, based on the status of the Address Mode En-
able bit (AMEN) and the Address Mode bit (AM) in
the CHCR register.
If 9th Data Bit is set
If Character Match
(1)
If Character Match and 9th Data Bit is set
(1)
If Character Match Immediately Follows BREAK
(1)
Not available in Synchronous mode
185/324
9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 93. Auto Echo Configuration
DCD
TRANSMITTER
TRANSMITTER
RECEIVER
SOUT
SOUT
RTS
RXCLK
RECEIVER
SIN
SIN
CLKOUT
VR00210A
VR000210
All modes except Synchronous
Synchronous mode (SMEN=1)
Figure 94. Loop Back Configuration
DCD
stand-by
LOGICAL 1
SOUT
TRANSMITTER
RECEIVER
SOUT
TRANSMITTER
RECEIVER
stand-by
value
value
RTS
clock
data
RXCLK
SIN
SIN
stand-by
value
CLKOUT
VR00211A
VR000211
All modes except Synchronous
Synchronous mode (SMEN=1)
Figure 95. Auto Echo and Loop-Back Configuration
DCD
SOUT
TRANSMITTER
RECEIVER
TRANSMITTER
RECEIVER
SOUT
RTS
clock
data
RXCLK
SIN
SIN
CLKOUT
VR000212
VR00212A
Synchronous mode (SMEN=1)
All modes except Synchronous
186/324
9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.6 Clocks And Serial Transmission Rates
The output of the Baud Rate generator has a pre-
cise 50% duty cycle. The Baud Rate generator can
use INTCLK for the input clock source. In this
case, INTCLK (and therefore the MCU Xtal)
should be chosen to provide a suitable frequency
for division by the Baud Rate Generator to give the
required transmit and receive bit rates. Suitable
INTCLK frequencies and the respective divider
values for standard Baud rates are shown in Table
2.
The communication bit rate of the SCI transmitter
and receiver sections can be provided from the in-
ternal Baud Rate Generator or from external
sources. The bit rate clock is divided by 16 in
Asynchronous mode (CD in CCR reset), or undi-
vided in the 3 other modes (CD set).
With INTCLK running at 24MHz and no external
Clock provided, a maximum bit rate of 3MBaud
and 750KBaud is available in undivided and divide
by-16-mode respectively.
10.5.7 SCI -M Initialization Procedure
Writing to either of the two Baud Rate Generator
Registers immediately disables and resets the SCI
baud rate generator, as well as the transmitter and
receiver circuitry.
With INTCLK running at 24MHz and an external
Clock provided through the RXCLK/TXCLK lines,
a maximum bit rate of 3MBaud and 375KBaud is
available in undivided and divided by 16 mode re-
spectively (see Figure 10).
After writing to the second Baud Rate Generator
Register, the transmitter and receiver circuits are
enabled. The Baud Rate Generator will load the
new value and start counting.
External Clock Sources. The External Clock in-
put pin TXCLK may be programmed by the XTCLK
and OCLK bits in the CCR register as: the transmit
clock input, Baud Rate Generator output (allowing
an external divider circuit to provide the receive
clock for split rate transmit and receive), or as
CLKOUT output in Synchronous and Serial Ex-
pansion modes. The RXCLK Receive clock input
is enabled by the XRX bit, this input should be set
in accordance with the setting of the CD bit.
To initialize the SCI, the user should first initialize
the most significant byte of the Baud Rate Gener-
ator Register; this will reset all SCI circuitry. The
user should then initialize all other SCI registers
(SICR/SOCR included) for the desired operating
mode and then, to enable the SCI, he should ini-
tialize the least significant byte Baud Rate Gener-
ator Register.
Baud Rate Generator. The internal Baud Rate
Generator consists of a 16-bit programmable di-
vide by “N” counter which can be used to generate
the transmitter and/or receiver clocks. The mini-
mum baud rate divisor is 2 and the maximum divi-
'On-the-Fly' modifications of the control registers'
content during transmitter/receiver operations, al-
though possible, can corrupt data and produce un-
desirable spikes on the I/O lines (data, clock and
control). Furthermore, modifying the control regis-
ters' content without reinitialising the SCI circuitry
(during stand-by cycles, waiting to transmit or re-
ceive data) must be kept carefully under control by
software to avoid spurious data being transmitted
or received.
16
sor is 2 -1. After initialising the baud rate genera-
tor, the divisor value is immediately loaded into the
counter. This prevents potentially long random
counts on the initial load.
The Baud Rate generator frequency is equal to the
Input Clock frequency divided by the Divisor value.
WARNING: Programming the baud rate divider to
0 or 1 will stop the divider.
Note: For synchronous receive operation, the data
and receive clock must not exhibit significant skew
between clock and data. The received data and
clock are internally synchronized to INTCLK.
Figure 96. SCI-M Baud Rate Generator Initialization Sequence
MOST SIGNIFICANT
BYTE INITIALIZATION
SELECT SCI
WORKING MODE
LEAST SIGNIFICANT
BYTE INITIALIZATION
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Table 38. SCI-M Baud Rate Generator Divider Values Example 1
INTCLK: 19660.800 KHz
Divisor
Dec
Actual
Baud
Rate
Baud
Rate
Clock
Factor
Desired Freq
(kHz)
Actual Freq
(kHz)
Deviation
Hex
50.00
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
0.80000
1.20000
24576
16384
11170
4096
2048
1024
512
6000
4000
2BA2
1000
800
400
200
100
80
50.00
0.80000
1.20000
0.0000%
0.0000%
75.00
110.00
75.00
110.01
1.76000
1.76014 -0.00081%
300.00
4.80000
300.00
4.80000
9.60000
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
600.00
9.60000
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
19.20000
38.40000
76.80000
153.60000
307.20000
614.40000
1228.80000
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
19.20000
38.40000
76.80000
153.60000
307.20000
614.40000
1228.80000
256
128
64
40
32
20
16
10
Table 39. SCI-M Baud Rate Generator Divider Values Example 2
INTCLK: 24576 KHz
Divisor
Dec
Actual
Baud
Rate
Baud
Rate
Clock
Factor
Desired Freq
(kHz)
Actual Freq
(kHz)
Deviation
Hex
50.00
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
0.80000
1.20000
30720
20480
13963
5120
2560
1280
640
7800
5000
383B
1400
A00
500
280
140
A0
50.00
0.80000
1.20000
0.0000%
0.0000%
75.00
110.00
75.00
110.01
1.76000
1.76014 -0.00046%
300.00
4.80000
300.00
4.80000
9.60000
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
600.00
9.60000
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
19.20000
38.40000
76.80000
153.60000
307.20000
614.40000
1228.80000
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
19.20000
38.40000
76.80000
153.60000
307.20000
614.40000
1228.80000
320
160
80
50
40
28
20
14
188/324
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.8 Input Signals
SIN: Serial Data Input. This pin is the serial data
input to the SCI receiver shift register.
only the data portion of the frame and its stand-by
state is high: data is valid on the rising edge of the
clock. Even in Synchronous mode CLKOUT will
only clock the data portion of the frame, but the
stand-by level and active edge polarity are pro-
grammable by the user.
TXCLK: External Transmitter Clock Input. This
pin is the external input clock driving the SCI trans-
mitter. The TXCLK frequency must be greater than
or equal to 16 times the transmitter data rate (de-
pending whether the X16 or the X1 clock have
been selected). A 50% duty cycle is required for
this input and must have a period of at least twice
INTCLK. The use of the TXCLK pin is optional.
When Synchronous mode is disabled (SMEN in
SICR is reset), the state of the XTCLK and OCLK
bits in CCR determine the source of CLKOUT; '11'
enables the Serial Expansion Mode.
RXCLK: External Receiver Clock Input. This in-
put is the clock to the SCI receiver when using an
external clock source connected to the baud rate
generator. INTCLK is normally the clock source. A
50% duty cycle is required for this input and must
have a period of at least twice INTCLK. Use of RX-
CLK is optional.
When the Synchronous mode is enabled (SMEN
in SICR is set), the state of the XTCLK and OCLK
bits in CCR determine the source of CLKOUT; '00'
disables it for PLM applications.
RTS: Request To Send. This output Alternate
Function is only enabled in Synchronous mode; it
becomes active when the Least Significant Bit of
the data frame is sent to the Serial Output Pin
(SOUT) and indicates to the target device that the
MCU is about to send a synchronous frame; it re-
turns to its stand-by value just after the last active
edge of CLKOUT (MSB transmitted). The active
level can be programmed high or low.
DCD: Data Carrier Detect. This input is enabled
only in Synchronous mode; it works as a gate for
the RXCLK clock and informs the MCU that an
emitting device is transmitting a synchronous
frame. The active level can be programmed as 1
or 0 and must be provided at least one INTCLK pe-
riod before the first active edge of the input clock.
SDS: Synchronous Data Strobe. This output Al-
ternate function is only enabled in Synchronous
mode; it becomes active high when the Least Sig-
nificant Bit is sent to the Serial Output Pins
(SOUT) and indicates to the target device that the
MCU is about to send the first bit for each synchro-
nous frame. It is active high on the first bit and it is
low for all the rest of the frame. The active level
can not be programmed.
10.5.9 Output Signals
SOUT: Serial Data Output. This Alternate Func-
tion output signal is the serial data output for the
SCI transmitter in all operating modes.
CLKOUT: Clock Output. The alternate Function
of this pin outputs either the data clock from the
transmitter in Serial Expansion or Synchronous
modes, or the clock output from the Baud Rate
Generator. In Serial expansion mode it will clock
Figure 97. Receiver and Transmitter Clock Frequencies
Min
0
Max
Conditions
1x mode
INTCLK/8
INTCLK/4
INTCLK/8
INTCLK/2
INTCLK/8
INTCLK/4
INTCLK/8
INTCLK/2
External RXCLK
Receiver Clock Frequency
0
16x mode
1x mode
0
Internal Receiver Clock
0
16x mode
1x mode
0
External TXCLK
Transmitter Clock Frequency
0
16x mode
1x mode
0
Internal Transmitter Clock
0
16x mode
Note: The internal receiver and transmitter clocks
are the ones applied to the Tx and Rx shift regis-
ters (see Figure 1).
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.10 Interrupts and DMA
10.5.10.1 Interrupts
trigger. These bits should be reset by the program-
mer during the Interrupt Service routine.
The four major levels of interrupt are encoded in
hardware to provide two bits of the interrupt vector
register, allowing the position of the block of point-
er vectors to be resolved to an 8 byte block size.
The SCI can generate interrupts as a result of sev-
eral conditions. Receiver interrupts include data
pending, receive errors (overrun, framing and par-
ity), as well as address or break pending. Trans-
mitter interrupts are software selectable for either
Transmit Buffer Register Empty (BSN set) or for
Transmit Shift Register Empty (BSN reset) condi-
tions.
The SCI interrupts have an internal priority struc-
ture in order to resolve simultaneous events. Refer
also to Section 0.1.4 for more details relating to
Synchronous mode.
Typical usage of the Interrupts generated by the
SCI peripheral are illustrated in Figure 11.
Table 40. SCI Interrupt Internal Priority
Receive DMA Request
Transmit DMA Request
Receive Interrupt
Highest Priority
The SCI peripheral is able to generate interrupt re-
quests as a result of a number of events, several
of which share the same interrupt vector. It is
therefore necessary to poll S_ISR, the Interrupt
Status Register, in order to determine the active
Transmit Interrupt
Lowest Priority
190/324
9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Table 41. SCI-M Interrupt Vectors
Interrupt Source
Vector Address
Transmitter Buffer or Shift Register Empty
Transmit DMA end of Block
xxx x110
Received Data Pending
Receive DMA end of Block
xxxx x100
Break Detector
Address Word Match
xxxx x010
xxxx x000
Receiver Error
Figure 98. SCI-M Interrupts: Example of Typical Usage
ADDRESS AFTER BREAK CONDITION
BREAK
DATA
ADDRESS
NO MATCH
DATA
DATA
BREAK
ADDRESS
MATCH
DATA
DATA
DATA
INTERRUPT
DATA
INTERRUPT
DATA
INTERRUPT
BREAK
INTERRUPT
BREAK
INTERRUPT
ADDRESS
INTERRUPT
ADDRESS WORD MARKED BY D9=1
DATA
DATA
DATA
ADDRESS
NO MATCH
DATA
DATA
ADDRESS
MATCH
DATA
ADDRESS
INTERRUPT
INTERRUPT
DATA
DATA
INTERRUPT
INTERRUPT
CHARACTER SEARCH MODE
DATA MATCH
DATA
DATA
DATA
DATA
DATA
INTERRUPT
DATA
INTERRUPT
CHAR MATCH
INTERRUPT
DATA
INTERRUPT
DATA
INTERRUPT
DATA
INTERRUPT
D9 ACTING AS DATA CONTROL WITH SEPARATE INTERRUPT
DATA
DATA
DATA
DATA
D9=1
DATA
DATA
INTERRUPT
INTERRUPT
DATA
INTERRUPT
D9=1
INTERRUPT
VA00270
DATA
INTERRUPT
DATA
DATA
INTERRUPT
191/324
9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.10.2 DMA
The transfer of the last byte of a DMA data block
will be followed by a DMA End Of Block transmit or
receive interrupt, setting the TXEOB or RXEOB
bit.
Two DMA channels are associated with the SCI,
for transmit and for receive. These follow the reg-
ister scheme as described in the DMA chapter.
A typical Transmission End Of Block interrupt rou-
tine will perform the following actions:
DMA Reception
To perform a DMA transfer in reception mode:
1. Restore the DMA counter register (TDCPR).
2. Restore the DMA address register (TDAPR).
1. Initialize the DMA counter (RDCPR) and DMA
address (RDAPR) registers
3. Clear the Transmitter Shift Register Empty bit
TXSEM in the S_ISR register to avoid spurious
interrupts.
2. Enable DMA by setting the RXD bit in the IDPR
register.
3. DMA transfer is started when data is received
by the SCI.
4. Clear the Transmitter End Of Block (TXEOB)
pending bit in the IMR register.
5. Set the TXD bit in the IDPR register to enable
DMA.
DMA Transmission
To perform a DMA transfer in transmission mode:
6. Load the Transmitter Buffer Register (TXBR)
with the next byte to transmit.
1. Initialize the DMA counter (TDCPR) and DMA
address (TDAPR) registers.
The above procedure handles the case where a
further DMA transfer is to be performed.
2. Enable DMA by setting the TXD bit in the IDPR
register.
3. DMA transfer is started by writing a byte in the
Transmitter Buffer register (TXBR).
Error Interrupt Handling
If an error interrupt occurs while DMA is enabled in
reception mode, DMA transfer is stopped.
If this byte is the first data byte to be transmitted,
the DMA counter and address registers must be
initialized to begin DMA transmission at the sec-
ond byte. Alternatively, DMA transfer can be start-
ed by writing a dummy byte in the TXBR register.
To resume DMA transfer, the error interrupt han-
dling routine must clear the corresponding error
flag. In the case of an Overrun error, the routine
must also read the RXBR register.
DMA Interrupts
When DMA is active, the Received Data Pending
and the Transmitter Shift Register Empty interrupt
sources are replaced by the DMA End Of Block re-
ceive and transmit interrupt sources.
Character Search Mode with DMA
In Character Search Mode with DMA, when a
character match occurs, this character is not trans-
ferred. DMA continues with the next received char-
acter. To avoid an Overrun error occurring, the
Character Match interrupt service routine must
read the RXBR register.
Note: To handle DMA transfer correctly in trans-
mission, the BSN bit in the IMR register must be
cleared. This selects the Transmitter Shift Register
Empty event as the DMA interrupt source.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.11 Register Description
The SCI-M registers are located in the following
pages in the ST9:
SCI-M number 0: page 24 (18h)
SCI-M number 1: page 25 (19h) (when present)
The SCI is controlled by the following registers:
Address
Register
R240 (F0h)
R241 (F1h)
R242 (F2h)
R243 (F3h)
R244 (F4h)
R245 (F5h)
R246 (F6h)
R247 (F7h)
R248 (F8h)
R248 (F8h)
R249 (F9h)
R250 (FAh)
R251 (FBh)
R252 (FCh)
R253 (FDh)
R254 (FEh)
R255 (FFh)
Receiver DMA Transaction Counter Pointer Register
Receiver DMA Source Address Pointer Register
Transmitter DMA Transaction Counter Pointer Register
Transmitter DMA Destination Address Pointer Register
Interrupt Vector Register
Address Compare Register
Interrupt Mask Register
Interrupt Status Register
Receive Buffer Register same Address as Transmitter Buffer Register (Read Only)
Transmitter Buffer Register same Address as Receive Buffer Register (Write only)
Interrupt/DMA Priority Register
Character Configuration Register
Clock Configuration Register
Baud Rate Generator High Register
Baud Rate Generator Low Register
Synchronous Input Control Register
Synchronous Output Control Register
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
RECEIVER DMA COUNTER POINTER (RDCPR)
R240 - Read/Write
TRANSMITTER DMA COUNTER POINTER
(TDCPR)
R242 - Read/Write
Reset value: undefined
Reset value: undefined
7
0
7
0
RC7
RC6
RC5
RC4
RC3
RC2
RC1 RR/M
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TR/M
Bit 7:1 = RC[7:1]: Receiver DMA Counter Pointer.
These bits contain the address of the receiver
DMA transaction counter in the Register File.
Bit 7:1 = TC[7:1]: Transmitter DMA Counter Point-
er.
These bits contain the address of the transmitter
DMA transaction counter in the Register File.
Bit 0 = RR/M: Receiver Register File/Memory Se-
lector.
0: Select Memory space as destination.
1: Select the Register File as destination.
Bit 0 = TR/M: Transmitter Register File/Memory
Selector.
0: Select Memory space as source.
1: Select the Register File as source.
RECEIVER DMA ADDRESS POINTER (RDAPR)
R241 - Read/Write
TRANSMITTER DMA ADDRESS POINTER
(TDAPR)
Reset value: undefined
R243 - Read/Write
7
0
Reset value: undefined
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RPS
7
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TPS
Bit 7:1 = RA[7:1]: Receiver DMA Address Pointer.
These bits contain the address of the pointer (in
the Register File) of the receiver DMA data source.
Bit 7:1 = TA[7:1]: Transmitter DMA Address Point-
er.
These bits contain the address of the pointer (in
the Register File) of the transmitter DMA data
source.
Bit 0 = RPS: Receiver DMA Memory Pointer Se-
lector.
This bit is only significant if memory has been se-
lected for DMA transfers (RR/M = 0 in the RDCPR
register).
Bit 0 = TPS: Transmitter DMA Memory Pointer Se-
lector.
This bit is only significant if memory has been se-
lected for DMA transfers (TR/M = 0 in the TDCPR
register).
0: Select ISR register for receiver DMA transfers
address extension.
1: Select DMASR register for receiver DMA trans-
fers address extension.
0: Select ISR register for transmitter DMA transfers
address extension.
1: Select DMASR register for transmitter DMA
transfers address extension.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT VECTOR REGISTER (S_IVR)
R244 - Read/Write
ADDRESS/DATA COMPARE REGISTER (ACR)
R245 - Read/Write
Reset value: undefined
Reset value: undefined
7
0
0
7
0
V7
V6
V5
V4
V3
EV2
EV1
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad-
dress.
User programmable interrupt vector bits for trans-
mitter and receiver.
Bit 7:0 = AC[7:0]: Address/Compare Character.
With either 9th bit address mode, address after
break mode, or character search, the received ad-
dress will be compared to the value stored in this
register. When a valid address matches this regis-
ter content, the Receiver Address Pending bit
(RXAP in the S_ISR register) is set. After the
RXAP bit is set in an addressed mode, all received
data words will be transferred to the Receiver Buff-
er Register.
Bit 2:1 = EV[2:1]: Encoded Interrupt Source.
Both bits EV2 and EV1 are read only and set by
hardware according to the interrupt source.
EV2 EV1
Interrupt source
0
0
0
1
Receiver Error (Overrun, Framing, Parity)
Break Detect or Address Match
Received Data Pending/Receiver DMA
End of Block
1
1
0
1
Transmitter buffer or shift register empty
transmitter DMA End of Block
Bit 0 = D0: This bit is forced by hardware to 0.
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT MASK REGISTER (IMR)
R246 - Read/Write
Bit 4 = RXE: Receiver Error Mask.
0: Disable Receiver error interrupts (OE, PE, and
FE pending bits in the S_ISR register).
1: Enable Receiver error interrupts.
Reset value: 0xx00000
7
0
Bit 3 = RXA: Receiver Address Mask.
0: Disable Receiver Address interrupt (RXAP
pending bit in the S_ISR register).
BSN RXEOB TXEOB RXE
RXA
RXB RXDI TXDI
1: Enable Receiver Address interrupt.
Bit 7 = BSN: Buffer or shift register empty inter-
rupt.
This bit selects the source of the transmitter regis-
ter empty interrupt.
0: Select a Shift Register Empty as source of a
Transmitter Register Empty interrupt.
1: Select a Buffer Register Empty as source of a
Transmitter Register Empty interrupt.
Bit 2 = RXB: Receiver Break Mask.
0: Disable Receiver Break interrupt (RXBP pend-
ing bit in the S_ISR register).
1: Enable Receiver Break interrupt.
Bit 1 = RXDI: Receiver Data Interrupt Mask.
0: Disable Receiver Data Pending and Receiver
End of Block interrupts (RXDP and RXEOB
pending bits in the S_ISR register).
1: Enable Receiver Data Pending and Receiver
End of Block interrupts.
Bit 6 = RXEOB: Received End of Block.
This bit is set by hardware only and must be reset
by software. RXEOB is set after a receiver DMA
cycle to mark the end of a data block.
0: Clear the interrupt request.
1: Mark the end of a received block of data.
Note: RXDI has no effect on DMA transfers.
Bit 0 = TXDI: Transmitter Data Interrupt Mask.
0: Disable Transmitter Buffer Register Empty,
Transmitter Shift Register Empty, or Transmitter
End of Block interrupts (TXBEM, TXSEM, and
TXEOB bits in the S_ISR register).
1: Enable Transmitter Buffer Register Empty,
Transmitter Shift Register Empty, or Transmitter
End of Block interrupts.
Bit 5 = TXEOB: Transmitter End of Block.
This bit is set by hardware only and must be reset
by software. TXEOB is set after a transmitter DMA
cycle to mark the end of a data block.
0: Clear the interrupt request.
1: Mark the end of a transmitted block of data.
Note: TXDI has no effect on DMA transfers.
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT STATUS REGISTER (S_ISR)
R247 - Read/Write
Note: The source of this interrupt is given by the
couple of bits (AMEN, AM) as detailed in the IDPR
register description.
Reset value: undefined
7
0
Bit 3 = RXBP: Receiver Break Pending bit.
This bit is set by hardware if the received data in-
put is held low for the full word transmission time
(start bit, data bits, parity bit, stop bit).
0: No break received.
OE
FE
PE RXAP RXBP RXDP TXBEM TXSEM
Bit 7 = OE: Overrun Error Pending.
This bit is set by hardware if the data in the Receiv-
er Buffer Register was not read by the CPU before
the next character was transferred into the Receiv-
er Buffer Register (the previous data is lost).
0: No Overrun Error.
1: Break event occurred.
Bit 2 = RXDP: Receiver Data Pending bit.
This bit is set by hardware when data is loaded
into the Receiver Buffer Register.
1: Overrun Error occurred.
0: No data received.
1: Data received in Receiver Buffer Register.
Bit 6 = FE: Framing Error Pending bit.
This bit is set by hardware if the received data
word did not have a valid stop bit.
0: No Framing Error.
Bit 1 = TXBEM: Transmitter Buffer Register Emp-
ty.
This bit is set by hardware if the Buffer Register is
1: Framing Error occurred.
empty.
Note: In the case where a framing error occurs
when the SCI is programmed in address mode
and is monitoring an address, the interrupt is as-
serted and the corrupted data element is trans-
ferred to the Receiver Buffer Register.
0: No Buffer Register Empty event.
1: Buffer Register Empty.
Bit 0 = TXSEM: Transmitter Shift Register Empty.
This bit is set by hardware if the Shift Register has
completed the transmission of the available data.
0: No Shift Register Empty event.
Bit 5 = PE: Parity Error Pending.
This bit is set by hardware if the received word did
not have the correct even or odd parity bit.
0: No Parity Error.
1: Shift Register Empty.
1: Parity Error occurred.
Note: The Interrupt Status Register bits can be re-
set but cannot be set by the user. The interrupt
source must be cleared by resetting the related bit
when executing the interrupt service routine (natu-
rally the other pending bits should not be reset).
Bit 4 = RXAP: Receiver Address Pending.
RXAP is set by hardware after an interrupt ac-
knowledged in the address mode.
0: No interrupt in address mode.
1: Interrupt in address mode occurred.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
RECEIVER BUFFER REGISTER (RXBR)
R248 - Read only
TRANSMITTER BUFFER REGISTER (TXBR)
R248 - Write only
Reset value: undefined
Reset value: undefined
7
0
7
0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
Bit 7:0 = RD[7:0]: Received Data.
Bit 7:0 = TD[7:0]: Transmit Data.
This register stores the data portion of the re-
ceived word. The data will be transferred from the
Receiver Shift Register into the Receiver Buffer
Register at the end of the word. All receiver inter-
rupt conditions will be updated at the time of trans-
fer. If the selected character format is less than 8
bits, unused most significant bits will forced to “1”.
The ST9 core will load the data for transmission
into this register. The SCI will transfer the data
from the buffer into the Shift Register when availa-
ble. At the transfer, the Transmitter Buffer Register
interrupt is updated. If the selected word format is
less than 8 bits, the unused most significant bits
are not significant.
Note: RXBR and TXBR are two physically differ-
ent registers located at the same address.
Note: TXBR and RXBR are two physically differ-
ent registers located at the same address.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT/DMA PRIORITY REGISTER (IDPR)
R249 - Read/Write
mat. If software does not reset SB before the min-
imum break length has finished, the break condi-
tion will continue until software resets SB. The SCI
terminates the break condition with a high level on
the transmitter data output for one transmission
clock period.
Reset value: undefined
7
0
AMEN
SB SA RXD TXD
PRL2
PRL1
PRL0
Bit 5 = SA: Set Address.
If an address/9th data bit mode is selected, SA val-
ue will be loaded for transmission into the Shift
Register. This bit is cleared by hardware after its
load.
0: Indicate it is not an address word.
1: Indicate an address word.
Bit 7 = AMEN: Address Mode Enable.
This bit, together with the AM bit (in the CHCR reg-
ister), decodes the desired addressing/9th data
bit/character match operation.
In Address mode the SCI monitors the input serial
data until its address is detected
Note: Proper procedure would be, when the
Transmitter Buffer Register is empty, to load the
value of SA and then load the data into the Trans-
mitter Buffer Register.
AMEN AM
0
0
0
1
Address interrupt if 9th data bit = 1
Address interrupt if character match
Bit 4 = RXD: Receiver DMA Mask.
Address interrupt if character match
and 9th data bit =1
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
receiver End of Block interrupt can occur.
0: Disable Receiver DMA request (the RXDP bit in
the S_ISR register can request an interrupt).
1: Enable Receiver DMA request (the RXDP bit in
the S_ISR register can request a DMA transfer).
1
1
0
1
Address interrupt if character match
with word immediately following Break
Note: Upon reception of address, the RXAP bit (in
the Interrupt Status Register) is set and an inter-
rupt cycle can begin. The address character will
not be transferred into the Receiver Buffer Regis-
ter but all data following the matched SCI address
and preceding the next address word will be trans-
ferred to the Receiver Buffer Register and the
proper interrupts updated. If the address does not
match, all data following this unmatched address
will not be transferred to the Receiver Buffer Reg-
ister.
Bit 3 = TXD: Transmitter DMA Mask.
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
transmitter End Of Block interrupt can occur.
0: Disable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request an interrupt).
1: Enable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request a DMA trans-
fer).
In any of the cases the RXAP bit must be reset by
software before the next word is transferred into
the Buffer Register.
Bit 2:0 = PRL[2:0]: SCI Interrupt/DMA Priority bits.
The priority for the SCI is encoded with
(PRL2,PRL1,PRL0). Priority level 0 is the highest,
while level 7 represents no priority.
When AMEN is reset and AM is set, a useful char-
acter search function is performed. This allows the
SCI to generate an interrupt whenever a specific
character is encountered (e.g. Carriage Return).
When the user has defined a priority level for the
SCI, priorities within the SCI are hardware defined.
These SCI internal priorities are:
Bit 6 = SB: Set Break.
0: Stop the break transmission after minimum
Receiver DMA request
Transmitter DMA request
Receiver interrupt
highest priority
break length.
1: Transmit a break following the transmission of all
data in the Transmitter Shift Register and the
Buffer Register.
Transmitter interrupt
lowest priority
Note: The break will be a low level on the transmit-
ter data output for at least one complete word for-
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CHARACTER CONFIGURATION REGISTER
(CHCR)
Bit 4 = AB: Address/9th Bit.
R250 - Read/Write
0: No Address/9th bit.
1: Address/9th bit included in the character format
between the parity bit and the first stop bit. This
bit can be used to address the SCI or as a ninth
data bit.
Reset value: undefined
7
0
AM
EP
PEN
AB
SB1
SB0
WL1
WL0
Bit 3:2 = SB[1:0]: Number of Stop Bits..
Bit 7 = AM: Address Mode.
Number of stop bits
This bit, together with the AMEN bit (in the IDPR
register), decodes the desired addressing/9th data
bit/character match operation. Please refer to the
table in the IDPR register description.
SB1
SB0
in 16X mode
in 1X mode
0
0
1
1
0
1
0
1
1
1
2
2
3
1.5
2
2.5
Bit 6 = EP: Even Parity.
0: Select odd parity (when parity is enabled).
1: Select even parity (when parity is enabled).
Bit 1:0 = WL[1:0]: Number of Data Bits
Bit 5 = PEN: Parity Enable.
0: No parity bit.
1: Parity bit generated (transmit data) or checked
(received data).
WL1
WL0
Data Length
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
Note: If the address/9th bit is enabled, the parity
bit will precede the address/9th bit (the 9th bit is
never included in the parity calculation).
8 bits
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CLOCK CONFIGURATION REGISTER (CCR)
R251 - Read/Write
0: Select 16X clock mode for both receiver and
transmitter.
1: Select 1X clock mode for both receiver and
Reset value: 0000 0000 (00h)
transmitter.
7
0
Note: In 1X clock mode, the transmitter will trans-
mit data at one data bit per clock period. In 16X
mode each data bit period will be 16 clock periods
long.
XTCLK OCLK XRX XBRG CD AEN LBEN STPEN
Bit 7 = XTCLK
This bit, together with the OCLK bit, selects the
source for the transmitter clock. The following ta-
ble shows the coding of XTCLK and OCLK.
Bit 2 = AEN: Auto Echo Enable.
0: No auto echo mode.
1: Put the SCI in auto echo mode.
Note: Auto Echo mode has the following effect:
the SCI transmitter is disconnected from the data-
out pin SOUT, which is driven directly by the re-
ceiver data-in pin, SIN. The receiver remains con-
nected to SIN and is operational, unless loopback
mode is also selected.
Bit 6 = OCLK
This bit, together with the XTCLK bit, selects the
source for the transmitter clock. The following ta-
ble shows the coding of XTCLK and OCLK.
XTCLK
OCLK
Pin Function
0
0
0
1
Pin is used as a general I/O
Pin = TXCLK (used as an input)
Bit 1 = LBEN: Loopback Enable.
0: No loopback mode.
1: Put the SCI in loopback mode.
Pin = CLKOUT (outputs the Baud
Rate Generator clock)
1
0
Note: In this mode, the transmitter output is set to
a high level, the receiver input is disconnected,
and the output of the Transmitter Shift Register is
looped back into the Receiver Shift Register input.
All interrupt sources (transmitter and receiver) are
operational.
Pin = CLKOUT (outputs the Serial
expansion and synchronous
mode clock)
1
1
Bit 0 = STPEN: Stick Parity Enable.
Bit 5 = XRX: External Receiver Clock Source.
0: External receiver clock source not used.
1: Select the external receiver clock source.
0: The transmitter and the receiver will follow the
parity of even parity bit EP in the CHCR register.
1: The transmitter and the receiver will use the op-
posite parity type selected by the even parity bit
EP in the CHCR register.
Note: The external receiver clock frequency must
be 16 times the data rate, or equal to the data rate,
depending on the status of the CD bit.
Parity (Transmitter &
EP
SPEN
Receiver)
Bit 4 = XBRG: Baud Rate Generator Clock
Source.
0: Select INTCLK for the baud rate generator.
1: Select the external receiver clock for the baud
rate generator.
0 (odd)
1 (even)
0 (odd)
0
0
1
1
Odd
Even
Even
1 (even)
Odd
Bit 3 = CD: Clock Divisor.
The status of CD will determine the SCI configura-
tion (synchronous/asynchronous).
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
BAUD RATE GENERATOR HIGH REGISTER
(BRGHR)
Bit 6 = INPL: SIN Input Polarity.
0: Polarity not inverted.
1: Polarity inverted.
R252 - Read/Write
Note: INPL only affects received data. In Auto-
Echo mode SOUT = SIN even if INPL is set. In
Loop-Back mode the state of the INPL bit is irrele-
vant.
Reset value: undefined
15
8
BG15 BG14 BG13 BG12 BG11 BG10 BG9 BG8
Bit 5 = XCKPL: Receiver Clock Polarity.
0: RXCLK is active on the rising edge.
1: RXCLK is active on the falling edge.
BAUD RATE GENERATOR LOW REGISTER
(BRGLR)
Note: XCKPL only affects the receiver clock. In
Auto-Echo mode CLKOUT = RXCLK independ-
ently of the XCKPL status. In Loop-Back the state
of the XCKPL bit is irrelevant.
R253 - Read/Write
Reset value: undefined
7
0
Bit 4 = DCDEN: DCD Input Enable.
0: Disable hardware synchronization.
1: Enable hardware synchronization.
BG7
BG6
BG5
BG4
BG3
BG2
BG1
BG0
Bit 15:0 = Baud Rate Generator MSB and LSB.
Note: When DCDEN is set, RXCLK drives the re-
ceiver section only during the active level of the
DCD input (DCD works as a gate on RXCLK, in-
forming the MCU that a transmitting device is
sending a synchronous frame to it).
The Baud Rate generator is a programmable di-
vide by “N” counter which can be used to generate
the clocks for the transmitter and/or receiver. This
counter divides the clock input by the value in the
Baud Rate Generator Register. The minimum
baud rate divisor is 2 and the maximum divisor is
16
Bit 3 = DCDPL: DCD Input Polarity.
0: The DCD input is active when LOW.
1: The DCD input is active when HIGH.
2 -1. After initialization of the baud rate genera-
tor, the divisor value is immediately loaded into the
counter. This prevents potentially long random
counts on the initial load. If set to 0 or 1, the Baud
Rate Generator is stopped.
Note: DCDPL only affects the gating activity of the
receiver clock. In Auto-Echo mode RTS = DCD in-
dependently of DCDPL. In Loop-Back mode, the
state of DCDPL is irrelevant.
SYNCHRONOUS INPUT CONTROL (SICR)
R254 - Read/Write
Reset value: 0000 0011 (03h)
Bit 2 = INPEN: All Input Disable.
0: Enable SIN/RXCLK/DCD inputs.
1: Disable SIN/RXCLK/DCD inputs.
7
0
SMEN INPL XCKPL DCDEN DCDPL INPEN
X
X
Bit 1:0 = “Don't Care”
Bit 7 = SMEN: Synchronous Mode Enable.
0: Disable all features relating to Synchronous
mode (the contents of SICR and SOCR are ig-
nored).
1: Select Synchronous mode with its programmed
I/O configuration.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
SYNCHRONOUS OUTPUT CONTROL (SOCR)
R255 - Read/Write
Bit 3 = RTSEN: RTS and SDS Output Enable.
0: Disable the RTS and SDS hardware synchroni-
sation.
1: Enable the RTS and SDS hardware synchroni-
sation.
Reset value: 0000 0001 (01h)
7
0
Notes:
– When RTSEN is set, the RTS output becomes
active just before the first active edge of CLK-
OUT and indicates to target device that the MCU
is about to send a synchronous frame; it returns
to its stand-by value just after the last active edge
of CLKOUT (MSB transmitted).
OUTP OUTS OCKP OCKS RTSE RTS OUT
X
L
B
L
B
N
PL
DIS
Bit 7 = OUTPL: SOUT Output Polarity.
0: Polarity not inverted.
1: Polarity inverted.
– When RTSEN is set, the SDS output becomes
active high and indicates to the target device that
the MCU is about to send the first bit of a syn-
chronous frame on the Serial Output Pin
(SOUT); it returns to low level as soon as the
second bit is sent on the Serial Output Pin
(SOUT). In this way a positive pulse is generated
each time that the first bit of a synchronous frame
is present on the Serial Output Pin (SOUT).
Note: OUTPL only affects the data sent by the
transmitter section. In Auto-Echo mode SOUT =
SIN even if OUTPL=1. In Loop-Back mode, the
state of OUTPL is irrelevant.
Bit 6 = OUTSB: SOUT Output Stand-By Level.
0: SOUT stand-by level is HIGH.
1: SOUT stand-by level is LOW.
Bit 2 = RTSPL: RTS Output Polarity.
0: The RTS output is active when LOW.
1: The RTS output is active when HIGH.
Bit 5 = OCKPL: Transmitter Clock Polarity.
0: CLKOUT is active on the rising edge.
1: CLKOUT is active on the falling edge.
Note: RTSPL only affects the RTS activity on the
output pin. In Auto-Echo mode RTS = DCD inde-
pendently from the RTSPL value. In Loop-Back
mode RTSPL value is 'Don't Care'.
Note: OCKPL only affects the transmitter clock. In
Auto-Echo mode CLKOUT = RXCLK independ-
ently of the state of OCKPL. In Loop-Back mode
the state of OCKPL is irrelevant.
Bit 1 = OUTDIS: Disable all outputs.
This feature is available on specific devices only
(see device pin-out description).
When OUTDIS=1, all output pins (if configured in
Alternate Function mode) will be put in High Im-
pedance for networking.
Bit 4 = OCKSB: Transmitter Clock Stand-By Lev-
el.
0: The CLKOUT stand-by level is HIGH.
1: The CLKOUT stand-by level is LOW.
0: SOUT/CLKOUT/enabled
1: SOUT/CLKOUT/RTS put in high impedance
Bit 0 = “Don't Care”
203/324
9
SERIAL PERIPHERAL INTERFACE (SPI)
10.6 SERIAL PERIPHERAL INTERFACE (SPI)
10.6.1 Introduction
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
– SS: Slave select pin
To use any of these alternate functions (input or
output), the corresponding I/O port must be pro-
grammed as alternate function output.
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another Microcontroller.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 1.
Refer to the Pin Description chapter for the device-
specific pin-out.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave.
10.6.2 Main Features
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Maximum slave mode frequency = INTCLK/2.
■ Programmable prescalers for a wide range of
baud rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
■ Write collision flag protection
■ Master mode fault protection capability.
10.6.3 General Description
Various data/clock timing relationships may be
chosen (see Figure 4) but master and slave must
be programmed with the same timing mode.
The SPI is connected to external devices through
4 alternate function pins:
– MISO: Master In Slave Out pin
Figure 99. Serial Peripheral Interface Master/Slave
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
204/324
9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 100. Serial Peripheral Interface Block Diagram
Internal Bus
Read
SPDR
1
Read Buffer
IT
request
0
MOSI
Ext. INT
SPSR
MISO
8-Bit Shift Register
Write
MODF
WCOL
SPIF
-
-
-
-
-
SPI
STATE
CONTROL
SCK
SS
SPCR
MSTR
SPIS
SPR0
CPHA SPR1
SPIE SPOE
CPOL
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
SPPR
PRS0
PRS2 PRS1
DIV2
1/2
PRESCALER
/1 .. /8
0
1
ST9 PERIPHERAL
CLOCK (INTCLK)
205/324
9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4 Functional Description
In this configuration the MOSI pin is a data output
and the MISO pin is a data input.
Figure 2 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 4 dedicated registers:
– A Control Register (SPCR)
– A Prescaler Register (SPPR)
– A Status Register (SPSR)
Transmit Sequence
The transmit sequence begins when a byte is writ-
ten the SPDR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
– A Data Register (SPDR)
Refer to the SPCR, SPPR, SPSR and SPDR reg-
isters in Section 0.1.6 for the bit definitions.
When data transfer is complete:
– The SPIF bit is set by hardware
10.6.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
– An interrupt is generated if the SPIS and SPIE
bits are set.
Procedure
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPDR register is
read, the SPI peripheral returns this buffered val-
ue.
– Define the serial clock baud rate by setting/re-
setting the DIV2 bit of SPPR register, by writ-
ing a prescaler value in the SPPR register and
programming the SPR0 & SPR1 bits in the
SPCR register.
Clearing the SPIF bit is performed by the following
software sequence:
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 4).
1. An access to the SPSR register while the SPIF
bit is set
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
2. A read of the SPDR register.
Note: While the SPIF bit is set, all writes to the
SPDR register are inhibited until the SPSR regis-
ter is read.
– The MSTR and SPOE bits must be set (they
remain set only if the SS pin is connected to a
high level signal).
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9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if the SPIS and SPIE
bits are set.
The value of the SPPR register and SPR0 & SPR1
bits in the SPCR is not used for the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPDR register is
read, the SPI peripheral returns this buffered val-
ue.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
4.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPSR register while the SPIF
bit is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2. A read of the SPDR register.
– Clear the MSTR bit and set the SPOE bit to
assign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
SPDR register are inhibited until the SPSR regis-
ter is read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 0.1.4.6 ).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the SPDR register between each
data byte transfer to avoid a write collision (see
Section 0.1.4.4 ).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
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9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4.3 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA Bit is Set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 3).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA Bit is Reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the second clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
This pin must be toggled high and low between
each byte transmitted (see Figure 3).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its SPDR register and does not allow it
to be altered. Therefore the SS pin must be high to
write a new data byte in the SPDR without produc-
ing a write collision.
Figure 4 shows an SPI transfer with the four com-
binations of the CPHA and CPOL bits. The dia-
gram may be interpreted as a master or slave tim-
ing diagram where the SCK pin, the MISO pin, the
MOSI pin are directly connected between the mas-
ter and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
Figure 101. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
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9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 102. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the SPI Timing table in the Electrical Characteristics Section.
209/324
9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4.4 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the SPDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the SPDR register after
its SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the SPDR register without generating a write
collision.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the SPDR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
SPDR register and output the MSBit on to the ex-
ternal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL Bit
The WCOL bit in the SPSR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 5).
Figure 103. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPSR
st
1 Step
THEN
SPIF =0
WCOL=0
nd
2
Step
Read SPDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPSR
st
1
Step
Step
THEN
Note: Writing in SPDR register
instead of reading in it do not re-
set WCOL bit
nd
2
Read SPDR
WCOL=0
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9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4.5 Master Mode Fault
bits may be restored to their original state during or
after this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPOE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPOE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
10.6.4.6 Overrun Condition
An overrun condition occurs, when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
1. A read access to the SPSR register while the
MODF bit is set.
2. A write to the SPCR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPDR register returns this byte. All other bytes
are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPOE and MSTR
This condition is not detected by the SPI peripher-
al.
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9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its SPDR reg-
ister.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 6).
Multi-Master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the SPCR register and the MODF
bit in the SPSR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one slave device during a
transmission.
Figure 104. Single Master Configuration
SS
SS
SS
SS
SCK
SCK
Slave
MCU
SCK
Slave
SCK
Slave
MCU
Slave
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.5 Interrupt Management
Note: In the interrupt routine, reset the related
pending bit to avoid the interrupt request that was
just acknowledged being proposed again.
The interrupt of the Serial Peripheral Interface is
mapped on one of the eight External Interrupt
Channels of the microcontroller (refer to the “Inter-
rupts” chapter).
Then, after resetting the pending bit and before
the IRET instruction, check if the SPIF and MODF
interrupt flags in the SPSR register) are reset; oth-
erwise jump to the beginning of the routine. If, on
return from an interrupt routine, the pending bit is
reset while one of the interrupt flags is set, no in-
terrupt is performed on that channel until the flags
are set. A new interrupt request is performed only
when a flag is set with the other not set.
Each External Interrupt Channel has:
– A trigger control bit in the EITR register (R242 -
Page 0),
– A pending bit in the EIPR register (R243 -
Page0),
– A mask bit in the EIMR register (R244 - Page 0).
10.6.5.1 Register Map
Program the interrupt priority level using the EI-
PLR register (R245 - Page 0). For a description of
these registers refer to the “Interrupts” and “DMA”
chapters.
Depending on the device, one or two Serial Pe-
ripheral interfaces can be present. The previous
table summarizes the position of the registers of
the two peripherals in the register map of the mi-
crocontroller.
To use the interrupt feature, perform the following
sequence:
Address
Page
Name
DR0
CR0
SR0
PR0
DR1
CR1
SR1
PR1
– Set the priority level of the interrupt channel used
for the SPI (EIPRL register)
SPI0
R240 (F0h)
R241 (F1h)
R242 (F2h)
R243 (F3h)
R248 (F8h)
R249 (F9h)
R250 (FAh)
R251 (FBh)
7
7
7
7
7
7
7
7
– Select the interrupt trigger edge as rising edge
(set the corresponding bit in the EITR register)
– Set the SPIS bit of the SPCR register to select
the peripheral interrupt source
– Set the SPIE bit of the SPCR register to enable
the peripheral to perform interrupt requests
SPI1
– In the EIPR register, reset the pending bit of the
interrupt channel used by the SPI interrupt to
avoid any spurious interrupt requests being per-
formed when the mask bit is set
– Set the mask bit of the interrupt channel used to
enable the MCU to acknowledge the interrupt re-
quests of the peripheral.
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9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.6 Register Description
DATA REGISTER (SPDR)
R240 - Read/Write
Register Page: 7
Note: To use the MISO, MOSI and SCK alternate
functions (input or output), the corresponding I/O
port must be programmed as alternate function
output.
Reset Value: 0000 0000 (00h)
7
0
Bit 5 = SPIS Interrupt Selection.
This bit is set and cleared by software.
0: Interrupt source is external interrupt
1: Interrupt source is SPI
D7
D6
D5
D4
D3
D2
D1
D0
The SPDR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 0.1.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data register, the buffer is ac-
tually being read.
Warning: A write to the SPDR register places data
directly into the shift register for transmission.
Bit 3 = CPOL Clock polarity.
A read to the SPDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 2).
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
CONTROL REGISTER (SPCR)
R241 - Read/Write
Register Page: 7
Reset Value: 0000 0000 (00h)
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
7
0
SPIE SPOE SPIS MSTR CPOL CPHA SPR1 SPR0
1: The second clock transition is the first capture
edge.
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever either
SPIF or MODF are set in the SPSR register
while the other flag is 0.
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software. They
select one of four baud rates to be used as the se-
rial clock when the device is a master.
These 2 bits have no effect in slave mode.
Table 42. Serial Peripheral Baud Rate
Bit 6 = SPOE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 0.1.4.5 Master Mode Fault).
0: SPI alternate functions disabled (MISO, MOSI
and SCK can only work as input)
1: SPI alternate functions enabled (MISO, MOSI
and SCK can work as input or output depending
on the value of MSTR)
INTCLK Clock Divide
SPR1
SPR0
2
4
0
0
1
1
0
1
0
1
16
32
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9
SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SPSR)
R242 - Read Only
Register Page: 7
1: A fault in master mode has been detected
Bits 3:0 = Unused.
Reset Value: 0000 0000 (00h)
7
0
-
PRESCALER REGISTER (SPPR)
R243 - Read/Write
Register Page: 7
SPIF
WCOL
-
MODF
-
-
-
Reset Value: 0000 0000 (00h)
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPCR register. It is cleared by a soft-
ware sequence (an access to the SPSR register
followed by a read or write to the SPDR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
7
0
0
0
0
DIV2
0
PRS2 PRS1 PRS0
Bits 7:5 = Reserved, forced by hardware to 0.
Bit 4 = DIV2 Divider enable.
This bit is set and cleared by software.
0: Divider by 2 enabled.
1: Data transfer between the device and an exter-
nal device has been completed.
1: Divider by 2 disabled.
Note: While the SPIF bit is set, all writes to the
SPDR register are inhibited.
Bit 3 = Reserved. forced by hardware to 0.
Bit 6 = WCOL Write Collision status.
Bits 2:0 = PRS[2:0] Prescaler Value.
These bits are set and cleared by software. The
baud rate generator is driven by
INTCLK/(n1*n2*n3) where n1= PRS[2:0]+1, n2 is
the value defined by the SPR[1:0] bits (refer to Ta-
ble 1 and Table 2), n3 = 1 if DIV2=1 and n3= 2 if
DIV2=0. Refer to Figure 2.
This bit is set by hardware when a write to the
SPDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 5).
0: No write collision occurred
1: A write collision has been detected
These bits have no effect in slave mode.
Table 43. Prescaler Baud Rate
Prescaler
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
PRS2
PRS1 PRS0
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 0.1.4.5
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the SPCR register. This bit is
cleared by a software sequence (An access to the
SPSR register while MODF=1 followed by a write
to the SPCR register).
Division Factor
1 (no division)
0
0
0
0
0
1
2
...
8
1
1
1
0: No master mode fault detected
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9
I2C BUS INTERFACE
2
10.7 I C BUS INTERFACE
10.7.1 Introduction
Interrupt Features:
2
■ Interrupt generation on error condition, on
The I C bus Interface serves as an interface be-
2
transmission request and on data received
tween the microcontroller and the serial I C bus. It
provides both multimaster and slave functions with
■ Interrupt address vector for each interrupt
both 7-bit and 10-bit address modes; it controls all
source
2
I C bus-specific sequencing, protocol, arbitration,
■ Pending bit and mask bit for each interrupt
timing and supports both standard (100KHz) and
source
2
fast I C modes (400KHz).
■ Programmable interrupt priority respects the
Using DMA, data can be transferred with minimum
use of CPU time.
other peripherals of the microcontroller
■ Interrupt address vector programmable
The peripheral uses two external lines to perform
the protocols: SDA, SCL.
DMA Features:
■ DMA both in transmission and in reception with
10.7.2 Main Features
■ Parallel-bus/I C protocol converter
enabling bits
2
■ DMA from/toward both Register File and
■ Multi-master capability
■ 7-bit/10-bit Addressing
Memory
■ End Of Block interrupt sources with the related
2
2
■ Standard I C mode/Fast I C mode
■ Transmitter/Receiver flag
pending bits
■ Selection between DMA Suspended and DMA
■ End-of-byte transmission flag
■ Transfer problem detection
Not-Suspended mode if error condition occurs.
■ Interrupt generation on error conditions
■ Interrupt generation on transfer request and on
data received
2
I C Master Features:
■ Start bit detection flag
■ Clock generation
2
■ I C bus busy flag
■ Arbitration Lost flag
■ End of byte transmission flag
■ Transmitter/Receiver flag
■ Stop/Start generation
2
I C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
■ Detection of misplaced start or stop condition
2
■ Programmable I C Address detection (both 7-
bit and 10-bit mode)
■ General Call address programmable
■ Transfer problem detection
■ End of byte transmission flag
■ Transmitter/Receiver flag.
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
Figure 105. I C Interface Block Diagram
DATA BUS
DATA REGISTER
DATA SHIFT REGISTER
COMPARATOR
DATA
SDA
CONTROL
OWN ADDRESS REGISTER 1
OWN ADDRESS REGISTER 2
GENERAL CALL ADDRESS
CLOCK CONTROL REGISTER
CLOCK
SCL
STATUS REGISTER 1
STATUS REGISTER 2
CONTROL
CONTROL REGISTER
LOGIC AND INTERRUPT/DMA REGISTERS
INTERRUPT
DMA
CONTROL SIGNALS
VR02119A
2
10.7.3 Functional Description
The I C interface has sixteen internal registers.
Six of them are used for initialization:
– Own Address Registers I2COAR1, I2COAR2
– General Call Address Register I2CADR
– Clock Control Registers I2CCCR, I2CECCR
– Control register I2CCR
Refer to the I2CCR, I2CSR1 and I2CSR2 registers
in Section 0.1.7. for the bit definitions.
2
The I C interface works as an I/O interface
2
between the ST9 microcontroller and the I C bus
protocol. In addition to receiving and transmitting
data, the interface converts data from serial to
parallel format and vice versa using an interrupt or
polled handshake.
The following four registers are used during data
transmission/reception:
2
It operates in Multimaster/slave I C mode. The se-
– Data Register I2CDR
lection of the operating mode is made by software.
– Control Register I2CCR
– Status Register 1 I2CSR1
– Status Register 2 I2CSR2
2
2
The I C interface is connected to the I C bus by a
data pin (SDA) and a clock pin (SCL) which must
2
be configured as open drain when the I C cell is
enabled by programming the I/O port bits and the
PE bit in the I2CCR register. In this case, the value
of the external pull-up resistance used depends on
the application.
2
When the I C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
The following seven registers are used to handle
the interrupt and the DMA features:
bit is set) the General Call address (stored in
I2CADR register). It never recognizes the Start
Byte (address byte 01h) whatever its own address
is.
– Interrupt Status Register I2CISR
– Interrupt Mask Register I2CIMR
– Interrupt Vector Register I2CIVR
Data and addresses are transferred in 8 bits, MSB
first. The first byte(s) following the start condition
contain the address (one byte in 7-bit mode, two
bytes in 10-bit mode). The address is always
transmitted in master mode.
– Receiver DMA Address Pointer Register
I2CRDAP
– Receiver DMA Transaction Counter Register
I2CRDC
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter.
Acknowledge is enabled and disabled by software.
Refer to Figure 2.
– Transmitter DMA Address Pointer Register
I2CTDAP
– Transmitter DMA transaction Counter Register
I2CTDC
The interface can decode both addresses:
– Software programmable 7-bit General Call
address
2
– I C address stored by software in the I2COAR1
register in 7-bit address mode or stored in
I2COAR1 and I2COAR2 registers in 10-bit ad-
dress mode.
After a reset, the interface is disabled.
IMPORTANT:
1. To guarantee correct operation, before enabling
the peripheral (while I2CCR.PE=0), configure bit7
and bit6 of the I2COAR2 register according to the
internal clock INTCLK (for example 11xxxxxxb in
the range 14 - 30 MHz).
2. Bit7 of the I2CCR register must be cleared.
10.7.3.1 Mode Selection
2
In I C mode, the interface can operate in the four
following modes:
– Master transmitter/receiver
– Slave transmitter/receiver
By default, it operates in slave mode.
This interface automatically switches from slave to
master after a start condition is generated on the
bus and from master to slave in case of arbitration
loss or stop condition generation.
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, it is able to recognize its own ad-
dress (7 or 10-bit), as stored in the I2COAR1 and
I2COAR2 registers and (when the I2CCR.ENGC
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
Figure 106. I C BUS Protocol
SDA
SCL
ACK
9
MSB
1
2
8
START
STOP
CONDITION
CONDITION
VR02119B
2
Any transfer can be done using either the I C
registers directly or via the DMA.
The multimaster function is enabled with an auto-
matic switch from master mode to slave mode
when the interface loses the arbitration of the I C
2
If the transfer is to be done directly by accessing
the I2CDR, the interface waits (by holding the SCL
line low) for software to write in the Data Register
before transmission of a data byte, or to read the
Data Register after a data byte is received.
bus.
2
10.7.4.1 I C Slave Mode
As soon as a start condition is detected, the
address word is received from the SDA line and
sent to the shift register; then it is compared with
the address of the interface or the General Call
address (if selected by software).
If the transfer is to be done via DMA, the interface
sends a request for a DMA transfer. Then it waits
for the DMA to complete. The transfer between the
2
interface and the I C bus will begin on the next
Note: In 10-bit addressing mode, the comparison
includes the header sequence (11110xx0) and the
two most significant bits of the address.
rising edge of the SCL clock.
■ Header (10-bit mode) or Address (both 10-bit
and 7-bit modes) not matched: the state
machine is reset and waits for another Start
condition.
■ Header matched (10-bit mode only): the
interface generates an acknowledge pulse if the
ACK bit of the control register (I2CCR) is set.
The SCL frequency (F ) generated in master
scl
mode is controlled by a programmable clock divid-
2
er. The speed of the I C interface may be selected
between Standard (0-100KHz) and Fast (100-
2
400KHz) I C modes.
2
10.7.4 I C State Machine
■ Address matched: the I2CSR1.ADSL bit is set
and an acknowledge bit is sent to the master if
the I2CCR.ACK bit is set. An interrupt request
occurs if the I2CCR.ITE bit is set. Then the SCL
line is held low until the microcontroller reads
the I2CSR1 register (see Figure 3 Transfer
sequencing EV1).
2
To enable the interface in I C mode the I2CCR.PE
bit must be set twice as the first write only acti-
vates the interface (only the PE bit is set); and the
bit7 of I2CCR register must be cleared.
2
The I C interface always operates in slave mode
(the M/SL bit is cleared) except when it initiates a
transmission or a receipt sequencing (master
mode).
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Next, depending on the data direction bit (least
significant bit of the address byte), and after the
generation of an acknowledge, the slave must go
in sending or receiving mode.
– AF: Detection of a no-acknowledge bit.
The I2CSR2.AF flag is set and an interrupt is ge-
nerated if the I2CCR.ITE bit is set.
Note: In both cases, SCL line is not stretched low;
however, the SDA line, due to possible «0» bits
transmitted last, can remain low. It is then neces-
sary to release both lines by software.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1).
Other Events
– ADSL: Detection of a Start condition after an ac-
knowledge time-slot.
Slave Receiver
The state machine is reset and starts a new pro-
cess. The I2CSR1.ADSL flag bit is set and an in-
terrupt is generated if the I2CCR.ITE bit is set.
The SCL line is stretched low.
Following the address reception and after I2CSR1
register has been read, the slave receives bytes
from the SDA line into the Shift Register and sends
them to the I2CDR register. After each byte it
generates an acknowledge bit if the I2CCR.ACK
bit is set.
– STOPF: Detection of a Stop condition after an
acknowledge time-slot.
The state machine is reset. Then the
I2CSR2.STOPF flag is set and an interrupt is ge-
nerated if the I2CCR.ITE bit is set.
When the acknowledge bit is sent, the
I2CSR1.BTF flag is set and an interrupt is generat-
ed if the I2CCR.ITE bit is set (see Figure 3
Transfer sequencing EV2).
Then the interface waits for a read of the I2CSR1
register followed by a read of the I2CDR register,
or waits for the DMA to complete.
How to release the SDA / SCL lines
Check that the I2CSR1.BUSY bit is reset. Set and
subsequently clear the I2CCR.STOP bit while the
I2CSR1.BTF bit is set; then the SDA/SCL lines are
released immediately after the transfer of the cur-
rent byte.
Slave Transmitter
Following the address reception and after I2CSR1
register has been read, the slave sends bytes from
the I2CDR register to the SDA line via the internal
shift register.
This will also reset the state machine; any subse-
quent STOP bit (EV4) will not be detected.
2
10.7.4.2 I C Master Mode
When the acknowledge bit is received, the
I2CCR.BTF flag is set and an interrupt is
generated if the I2CCR.ITE bit is set (see Figure 3
Transfer sequencing EV3).
The slave waits for a read of the I2CSR1 register
followed by a write in the I2CDR register or waits
for the DMA to complete, both holding the SCL
line low (except on EV3-1).
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Setting the I2CCR.START bit while the
I2CSR1.BUSY bit is cleared causes the interface
to generate a Start condition.
Once the Start condition is generated, the periph-
eral is in master mode (I2CSR1.M/SL=1) and
I2CSR1.SB (Start bit) flag is set and an interrupt is
generated if the I2CCR.ITE bit is set (see Figure 3
Transfer sequencing EV5 event).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer.
The I2CSR2.BERR flag is set and an interrupt is
generated if I2CCR.ITE bit is set.
The interface waits for a read of the I2CSR1 regis-
ter followed by a write in the I2CDR register with
the Slave address, holding the SCL line low.
If it is a stop then the state machine is reset.
If it is a start then the state machine is reset and
it waits for the new slave address on the bus.
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Then the slave address is sent to the SDA line.
In 7-bit addressing mode, one address byte is
sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the
I2CSR1.EVF and I2CSR1.ADD10 bits to be set by
hardware with interrupt generation if the
I2CCR.ITE bit is set.
Then the master waits for a read of the I2CSR1
register followed by a write in the I2CDR register,
holding the SCL line low (see Figure 3 Transfer
sequencing EV9). Then the second address byte
is sent by the interface.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Master Receiver:
The master receives a byte from the SDA line into
the shift register and sends it to the I2CDR regis-
ter. It generates an acknowledge bit if the
I2CCR.ACK bit is set and an interrupt if the
I2CCR.ITE bit is set or a DMA is requested (see
Transfer sequencing EV7 event).
Then it waits for the microcontroller to read the
Data Register (I2CDR) or waits for the DMA to
complete both holding SCL line low.
After each address byte, an acknowledge clock
pulse is sent to the SCL line if the I2CSR1.EVF
and
– I2CSR1.ADD10 bit (if first header)
Error Cases
– I2CSR2.ADDTX bit (if address or second hea-
der)
■ BERR: Detection of a Stop or a Start condition
during a byte transfer.
The I2CSR2.BERR flag is set and an interrupt is
generated if I2CCR.ITE is set.
are set, and an interrupt is generated if the
I2CCR.ITE bit is set.
■ AF: Detection of a no acknowledge bit
The I2CSR2.AF flag is set and an interrupt is
generated if I2CCR.ITE is set.
The peripheral waits for a read of the I2CSR1 reg-
ister followed by a write into the Control Register
(I2CCR) by holding the SCL line low (see Figure 3
Transfer sequencing EV6 event).
■ ARLO: Arbitration Lost
The I2CSR2.ARLO flag is set, the I2CSR1.M/SL
flag is cleared and the process is reset. An
interrupt is generated if the I2CCR.ITE bit is set.
If there was no acknowledge (I2CSR2.AF=1), the
master must stop or restart the communication
(set the I2CCR.START or I2CCR.STOP bits).
If there was an acknowledge, the state machine
enters a sending or receiving process according to
the data direction bit (least significant bit of the ad-
dress), the I2CSR1.BTF flag is set and an interrupt
is generated if I2CCR.ITE bit is set (see Transfer
sequencing EV7, EV8 events).
Note: In all cases, to resume communications, set
the I2CCR.START or I2CCR.STOP bits.
2
Events generated by the I C interface
■ STOP condition
When the I2CCR.STOP bit is set, a Stop
condition is generated after the transfer of the
current byte, the I2CSR1.M/SL flag is cleared
and the state machine is reset. No interrupt is
generated in master mode at the detection of
the stop condition.
If the master loses the arbitration of the bus there
is no acknowledge, the I2CSR2.AF flag is set and
the master must set the START or STOP bit in the
control register (I2CCR).The I2CSR2.ARLO flag is
set, the I2CSR1.M/SL flag is cleared and the proc-
ess is reset. An interrupt is generated if I2CCR.ITE
is set.
■ START condition
When the I2CCR.START bit is set, a start
2
condition is generated as soon as the I C bus is
Master Transmitter:
free. The I2CSR1.SB flag is set and an interrupt
is generated if the I2CCR.ITE bit is set.
The master waits for the microcontroller to write in
the Data Register (I2CDR) or it waits for the DMA
to complete both holding the SCL line low (see
Transfer sequencing EV8).
Then the byte is received into the shift register and
sent to the SDA line. When the acknowledge bit is
received, the I2CSR1.BTF flag is set and an
interrupt is generated if the I2CCR.ITE bit is set or
the DMA is requested.
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Figure 107. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
Data2
Data2
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
DataN
A
P
r
....
.
EV1 EV3
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV5
EV9
EV6 EV8
EV8
EV8
A
10-bit Master receiver:
S
Header
A
Data1
A
DataN
P
r
.....
EV5
EV6
EV7
EV7
Legend:
S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA
is complete.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA
is complete.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register, BTF is cleared by releasing the
lines (STOP=1, STOP=0) or writing DR register (for example DR=FFh). Note: If lines are released by
STOP=1, STOP=0 the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
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I2C BUS INTERFACE
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, ADDTX=1, cleared by reading SR1 register followed by writing CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA
is complete.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA
is complete.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
Figure 108. Event Flags and Interrupt Generation
ADSL
SB
AF
IERRM
STOPF
ARLO
ERROR
INTERRUPT
REQUEST
BERR
ADD10
ADDTX
IERRP
ITE
DATA RECEIVED
or
END OF BLOCK
INTERRUPT
REQUEST
IRXM
BTF=1 & TRA=0
IRXP
ITE
REOBP
Receiving DMA
End Of Block
READY TO TRANSMIT
or
ITXM
BTF=1 & TRA=1
END OF BLOCK
INTERRUPT
REQUEST
ITXP
ITE
TEOBP
Transmitting DMA
End Of Block
I2CSR1.EVF
223/324
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
10.7.5 Interrupt Features
– Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
2
The I Cbus interface has three interrupt sources
– Bus error, Start or Stop condition detected
during data transfer
related to “Error Condition”, “Peripheral Ready to
Transmit” and “Data Received”.
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
The peripheral uses the ST9+ interrupt internal
protocol without requiring the use of the external
interrupt channel. Dedicated registers of the pe-
ripheral should be loaded with appropriate values
to set the interrupt vector (see the description of
the I2CIVR register), the interrupt mask bits (see
the description of the I2CIMR register) and the in-
terrupt priority and pending bits (see the descrip-
tion of the I2CISR register).
The peripheral also has a global interrupt enable
(the I2CCR.ITE bit) that must be set to enable the
interrupt features. Moreover there is a global inter-
rupt flag (I2CSR1.EVF bit) which is set when one
of the interrupt events occurs (except the End Of
Block interrupts - see the DMA Features section).
– Master has sent the header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
– Address byte successfully transmitted in
Master mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX=1)
Note: Depending on the value of I2CISR.DMAS-
TOP bit, the pending bit related to the “error condi-
tion” interrupt source is able to suspend or not sus-
pend DMA transfers.
Each interrupt source has a dedicated interrupt
address pointer vector stored in the I2CIVR regis-
ter. The five more significant bits of the vector ad-
dress are programmable by the customer, where-
as the three less significant bits are set by hard-
ware depending on the interrupt source:
The “Data Received” interrupt source occurs after
the acknowledge of a received data byte is per-
formed. It is generated when the I2CSR1.BTF flag
is set and the I2CSR1.TRA flag is zero.
If the DMA feature is enabled in receiver mode,
this interrupt is not generated and the same inter-
rupt vector is used to send a Receiving End Of
Block interrupt (See the DMA feature section).
– 010: error condition detected
– 100: data received
– 110: peripheral ready to transmit
The priority with respect to the other peripherals is
programmable by setting the PRL[2:0] bits in the
I2CISR register. The lowest interrupt priority is ob-
tained by setting all the bits (this priority level is
never acknowledged by the CPU and is equivalent
to disabling the interrupts of the peripheral); the
highest interrupt priority is programmed by reset-
ting all the bits. See the Interrupt and DMA chap-
ters for more details.
The “Peripheral Ready To Transmit” interrupt
source occurs as soon as a data byte can be
transmitted by the peripheral. It is generated when
the I2CSR1.BTF and the I2CSR1.TRA flags are
set.
If the DMA feature is enabled in transmitter mode,
this interrupt is not generated and the same inter-
rupt vector is used to send a Transmitting End Of
Block interrupt (See the DMA feature section).
The internal priority of the interrupt sources of the
peripheral is fixed by hardware with the following
order: “Error Condition” (highest priority), “Data
Received”, “Peripheral Ready to Transmit”.
Note: The DMA has the highest priority over the
interrupts; moreover the “Transmitting End Of
Block” interrupt has the same priority as the “Pe-
ripheral Ready to Transmit” interrupt and the “Re-
ceiving End Of Block” interrupt has the same prior-
ity as the “Data received” interrupt.
The “Error condition” interrupt source occurs when
one of the following condition occurs:
– Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
– Start condition generated
Each of these three interrupt sources has a pend-
ing bit (IERRP, IRXP, ITXP) in the I2CISR register
that is set by hardware when the corresponding in-
terrupt event occurs. An interrupt request is per-
formed only if the corresponding mask bit is set
(IERRM, IRXM, ITXM) in the I2CIMR register and
the peripheral has a proper priority level.
(I2CSR1.SB and I2CSR1.EVF flags = 1)
– No acknowledge received after byte transmis-
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
– Stop detected in Slave mode
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
The pending bit has to be reset by software.
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Note: Until the pending bit is reset (while the cor-
responding mask bit is set), the peripheral proc-
esses an interrupt request. So, if at the end of an
interrupt routine the pending bit is not reset, anoth-
er interrupt request is performed.
ory addressed through the DMA Address Regis-
ter (or Register pair)
– A post-increment of the DMA Address Register
(or Register pair)
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
Note: Before the end of the transmission and re-
ception interrupt routines, the I2CSR1.BTF flag bit
should be checked, to acknowledge any interrupt
requests that occurred during the interrupt routine
and to avoid masking subsequent interrupt re-
quests.
Depending on the value of the DDCISR.DMAS-
TOP bit the DMA feature can be suspended or not
(both in transmission and in reception) until the
pending bit related to the “Error event” interrupt re-
quest is set.
Note: The “Error” event interrupt pending bit
(I2CISR.IERRP) is forced high while the error
event flags are set (ADD10, ADSL and SB flags of
the I2CSR1 register; SCLF, ADDTX, AF, STOPF,
ARLO and BERR flags of the I2CSR2 register).
2
The priority level of the DMA features of the I C
interface with respect to the other peripherals and
the CPU is the same as programmed in the
I2CISR register for the interrupt sources. In the in-
ternal priority level order of the peripheral, if DD-
CISR.DMASTOP=0, DMA has a higher priority
with respect to the interrupt sources. Otherwise (if
DDCISR.DMASTOP=1), the DMA has a priority
lower than “error” event interrupt sources but
greater than reception and transmission interrupt
sources.
Note: If the I2CISR.DMASTOP bit is reset, then
the DMA has the highest priority with respect to
the interrupts; if the bit is set (as after the MCU re-
set) and the “Error event” pending bit is set
(I2CISR.IERRP), then the DMA is suspended until
the pending bit is reset by software. In the second
case, the “Error” interrupt sources have higher pri-
ority, followed by DMA, “Data received” and “Re-
ceiving End Of Block” interrupts, “Peripheral
Ready to Transmit” and “Transmitting End Of
Block”.
Moreover the Transmitting End Of Block interrupt
has the same priority as the “Peripheral Ready to
Transmit” interrupt and the Receiving End Of
Block interrupt has the same priority as the “Data
received” interrupt.
Refer to the Interrupt and DMA chapters for details
on the priority levels.
The DMA features are enabled by setting the cor-
responding enabling bits (RXDM, TXDM) in the
I2CIMR register. It is possible to select also the di-
rection of the DMA transactions.
Once the DMA transfer is completed (the transac-
tion counter reaches 0 value), an interrupt request
to the CPU is generated. This kind of interrupt is
called “End Of Block”. The peripheral sends two
different “End Of Block” interrupts depending on
the direction of the DMA (Receiving End Of Block -
Transmitting End Of Block). These interrupt
sources have dedicated interrupt pending bits in
the I2CIMR register (REOBP, TEOBP) and they
are mapped on the same interrupt vectors as re-
spectively “Data Received” and “Peripheral Ready
to Transmit” interrupt sources. The same corre-
spondence exists about the internal priority be-
tween interrupts.
10.7.6 DMA Features
The peripheral can use the ST9+ on-chip Direct
Memory Access (DMA) channels to provide high-
speed data transaction between the peripheral
and contiguous locations of Register File, and
Memory. The transactions can occur from and to-
ward the peripheral. The maximum number of
transactions that each DMA channel can perform
is 222 if the register file is selected or 65536 if
memory is selected. The control of the DMA fea-
tures is performed using registers placed in the pe-
ripheral register page (I2CISR, I2CIMR,
I2CRDAP, I2CRDC, I2CTDAP, I2CTDC).
Note: The I2CCR.ITE bit has no effect on the End
Of Block interrupts.
Moreover, the I2CSR1.EVF flag is not set by the
End Of Block interrupts.
Each DMA transfer consists of three operations:
– A load from/to the peripheral data register
(I2CDR) to/from a location of Register File/Mem-
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
10.7.6.1 DMA between Peripheral and Register
File
The Transaction Counter registers pair must be in-
itialized with the number of DMA transfers to per-
form and will be decremented after each transac-
tion. The DMA Address register pair must be ini-
tialized with the starting address of the DMA table
in the Memory Space, and it is increased after
each transaction. These two register pairs must be
located between addresses 00h and DFh of the
Register File.
If the DMA transaction is made between the pe-
ripheral and the Register File, one register is
required to hold the DMA Address and one to hold
the DMA transaction counter.
These two registers must be located in the Regis-
ter File:
– the DMA Address Register in the even ad-
dressed register,
10.7.6.3 DMA in Master Receive
To correctly manage the reception of the last byte
when the DMA in Master Receive mode is used,
the following sequence of operations must be per-
formed:
– the DMA Transaction Counter in the following
register (odd address).
They are pointed to by the DMA Transaction
Counter Pointer Register (I2CRDC register in re-
ceiving, I2CTDC register in transmitting) located in
the peripheral register page.
1. The number of data bytes to be received must
be set to the effective number of bytes minus
one byte.
In order to select the DMA transaction with the
Register File, the control bit I2CRDC.RF/MEM in
receiving mode or I2CTDC.RF/MEM in transmit-
ting mode must be set.
2. When the Receiving End Of Block condition
occurs, the I2CCR.STOP bit must be set and
the I2CCR.ACK bit must be reset.
The last byte of the reception sequence can be re-
ceived either using interrupts/polling or using
DMA. If the user wants to receive the last byte us-
ing DMA, the number of bytes to be received must
be set to 1, and the DMA in reception must be re-
enabled (IMR.RXDM bit set) to receive the last
byte. Moreover the Receiving End Of Block inter-
rupt service routine must be designed to recognize
and manage the two different End Of Block situa-
tions (after the first sequence of data bytes and af-
ter the last data byte).
The transaction Counter Register must be initial-
ized with the number of DMA transfers to perform
and will be decremented after each transaction.
The DMA Address Register must be initialized with
the starting address of the DMA table in the Regis-
ter File, and it is increased after each transaction.
These two registers must be located between ad-
dresses 00h and DFh of the Register File.
When the DMA occurs between Peripheral and
Register File, the I2CTDAP register (in transmis-
sion) and the I2CRDAP one (in reception) are not
used.
10.7.6.2 DMA between Peripheral and Memory
Space
If the DMA transaction is made between the pe-
ripheral and Memory, a register pair is required to
hold the DMA Address and another register pair to
hold the DMA Transaction counter. These two
pairs of registers must be located in the Register
File. The DMA Address pair is pointed to by the
DMA Address Pointer Register (I2CRDAP register
in reception, I2CTDAP register in transmission) lo-
cated in the peripheral register page; the DMA
Transaction Counter pair is pointed to by the DMA
Transaction Counter Pointer Register (I2CRDC
register in reception, I2CTDC register in transmis-
sion) located in the peripheral register page.
In order to select the DMA transaction with the
Memory Space, the control bit I2CRDC.RF/MEM
in receiving mode or I2CTDC.RF/MEM in transmit-
ting mode must be reset.
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
10.7.7 Register Description
1: The General Call address stored in the I2CADR
register will be acknowledged
Note: The correct value (usually 00h) must be
written in the I2CADR register before enabling the
General Call feature.
IMPORTANT:
1. To guarantee correct operation, before enabling
the peripheral (while I2CCR.PE=0), configure bit7
and bit6 of the I2COAR2 register according to the
internal clock INTCLK (for example 11xxxxxxb in
the range 14 - 30 MHz).
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0) or when the Start condition is
sent (with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation (reset value)
1: Start generation when the bus is free
2. Bit7 of the I2CCR register must be cleared.
2
I C CONTROL REGISTER (I2CCR)
R240 - Read / Write
Register Page: 20
Reset Value: 0000 0000 (00h)
7
0
Bit 2 = ACK Acknowledge enable.
0
0
PE
ENGC START ACK STOP ITE
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0).
0: No acknowledge returned (reset value)
1: Acknowledge returned after an address byte or
a data byte is received
Bit 7:6 = Reserved
Must be cleared
Bit 5 = PE Peripheral Enable.
This bit is set and cleared by software.
0: Peripheral disabled (reset value)
1: Master/Slave capability
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. It is not
cleared when the interface is disabled
(I2CCR.PE=0). In slave mode, this bit must be set
only when I2CSR1.BTF=1.
Notes:
– When I2CCR.PE=0, all the bits of the I2CCR
register and the I2CSR1-I2CSR2 registers ex-
cept the STOP bit are reset. All outputs will be re-
leased while I2CCR.PE=0
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When I2CCR.PE=1, the corresponding I/O pins
are selected by hardware as alternate functions
(open drain).
2
– To enable the I C interface, write the I2CCR reg-
ister TWICE with I2CCR.PE=1 as the first write
only activates the interface (only I2CCR.PE is
set).
– In slave mode:
0: No stop generation (reset value)
1: Release SCL and SDA lines after the current
byte transfer (I2CSR1.BTF=1). In this mode the
STOP bit has to be cleared by software.
– When PE=1, the FREQ[2:0] and EN10BIT bits in
the I2COAR2 and I2CADR registers cannot be
written. The value of these bits can be changed
only when PE=0.
Bit 4 = ENGC General Call address enable.
Setting this bit the peripheral works as a slave and
the value stored in the I2CADR register is recog-
nized as device address.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0).
0: The address stored in the I2CADR register is
ignored (reset value)
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Bit 0 = ITE Interrupt Enable.
2
I C STATUS REGISTER 1 (I2CSR1)
The ITE bit enables the generation of interrupts.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(I2CCR.PE=0).
0: Interrupts disabled (reset value)
1: Interrupts enabled after any of the following con-
ditions:
R241 - Read Only
Register Page: 20
Reset Value: 0000 0000 (00h)
7
0
EVF ADD10 TRA BUSY BTF ADSL M/SL
SB
– Byte received or to be transmitted
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
Note: Some bits of this register are reset by a read
operation of the register. Care must be taken when
using instructions that work on single bit. Some of
them perform a read of all the bits of the register
before modifying or testing the wanted bit. So oth-
er bits of the register could be affected by the op-
eration.
In the same way, the test/compare operations per-
form a read operation.
Moreover, if some interrupt events occur while the
register is read, the corresponding flags are set,
and correctly read, but if the read operation resets
the flags, no interrupt request occurs.
– Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
– Start condition generated
(I2CSR1.SB and I2CSR1.EVF flags = 1)
– No acknowledge received after byte transmis-
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
– Stop detected in Slave mode
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
– Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
– Bus error, Start or Stop condition detected
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
Bit 7 = EVF Event Flag.
This bit is set by hardware as soon as an event (
listed below or described in Figure 3) occurs. It is
cleared by software when all event conditions that
set the flag are cleared. It is also cleared by hard-
– Master has sent header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
ware
when
the
interface
is
disabled
– Address byte successfully transmitted in Mas-
ter mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX = 1)
(I2CCR.PE=0).
0: No event
1: One of the following events has occurred:
SCL is held low when the ADDTX flag of the
I2CSR2 register or the ADD10, SB, BTF or ADSL
flags of I2CSR1 register are set (See Figure 3) or
when the DMA is not complete.
The transfer is suspended in all cases except
when the BTF bit is set and the DMA is enabled. In
this case the event routine must suspend the DMA
transfer if it is required.
– Byte received or to be transmitted
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
– Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
– Start condition generated
(I2CSR1.SB and I2CSR1.EVF flags = 1)
– No acknowledge received after byte transmis-
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
– Stop detected in Slave mode
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
– Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
– Bus error, Start or Stop condition detected
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
– Master has sent header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
228/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
– Address byte successfully transmitted in Mas-
ter mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX=1)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. BTF is
cleared by reading I2CSR1 register followed by
writing the next byte in I2CDR register or when
DMA is complete.
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set when the master has sent the first
byte in 10-bit address mode. An interrupt is gener-
ated if ITE=1.
It is cleared by software reading I2CSR1 register
followed by a write in the I2CDR register of the
second address byte. It is also cleared by hard-
ware when peripheral is disabled (I2CCR.PE=0)
or when the STOPF bit is set.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading I2CSR1 reg-
ister followed by reading the byte from I2CDR
register or when DMA is complete.
The SCL line is held low while I2CSR1.BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
0: No ADD10 event occurred.
1: Master has sent first address byte (header).
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware if the received slave ad-
dress matches the I2COAR1/I2COAR2 register
content or a General Call address. An interrupt is
generated if ITE=1. It is cleared by software
reading I2CSR1 register or by hardware when the
interface is disabled (I2CCR.PE=0). The SCL line
is held low while ADSL=1.
Bit 5 = TRA Transmitter/ Receiver.
When BTF flag of this register is set and also
TRA=1, then a data byte has to be transmitted. It is
cleared automatically when BTF is cleared. It is
also cleared by hardware after the STOPF flag of
I2CSR2 register is set, loss of bus arbitration
(ARLO flag of I2CSR2 register is set) or when the
interface is disabled (I2CCR.PE=0).
0: Address mismatched or not received
1: Received address matched
0: A data byte is received (if I2CSR1.BTF=1)
1: A data byte can be transmitted (if
Bit 1 = M/SL Master/Slave.
I2CSR1.BTF=1)
This bit is set by hardware as soon as the interface
is in Master mode (Start condition generated on
the lines after the I2CCR.START bit is set). It is
cleared by hardware after detecting a Stop condi-
tion on the bus or a loss of arbitration (ARLO=1). It
is also cleared when the interface is disabled
(I2CCR.PE=0).
Bit 4 = BUSY Bus Busy.
It indicates a communication in progress on the
bus. The detection of the communications is al-
ways active (even if the peripheral is disabled).
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. This information is still updated
when the interface is disabled (I2CCR.PE=0).
0: No communication on the bus
0: Slave mode
1: Master mode
1: Communication ongoing on the bus
Bit 0 = SB Start Bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following a write of
START=1 if the bus is free). An interrupt is gener-
ated if ITE=1. It is cleared by software reading
I2CSR1 register followed by writing the address
byte in I2CDR register. It is also cleared by hard-
Bit 3 = BTF Byte Transfer Finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or before the transmission of a data
byte with interrupt generation if ITE=1. It is cleared
by software reading I2CSR1 register followed by a
read or write of I2CDR register or when DMA is
complete. It is also cleared by hardware when the
interface is disabled (I2CCR.PE=0).
ware
when
the
interface
is
disabled
(I2CCR.PE=0).
The SCL line is held low while SB=1.
0: No Start condition
1: Start condition generated
229/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 2 (I2CSR2)
Bit 3 = STOPF Stop Detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge. An
interrupt is generated if ITE=1.
R242 - Read Only
Register Page: 20
Reset Value: 0000 0000 (00h)
It is cleared by software reading I2CSR2 register
or by hardware when the interface is disabled
(I2CCR.PE=0).
7
0
0
0
ADDTX AF STOPF ARLO BERR GCAL
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected (while slave receiver)
Note: Some bits of this register are reset by a read
operation of the register. Care must be taken when
using instructions that work on single bit. Some of
them perform a read of all the bits of the register
before modifying or testing the wanted bit. So oth-
er bits of the register could be affected by the op-
eration.
In the same way, the test/compare operations per-
form a read operation.
Moreover, if some interrupt events occur while the
register is read, the corresponding flags are set,
and correctly read, but if the read operation resets
the flags, no interrupt request occurs.
Bit 2 = ARLO Arbitration Lost.
This bit is set by hardware when the interface (in
master mode) loses the arbitration of the bus to
another master. An interrupt is generated if ITE=1.
It is cleared by software reading I2CSR2 register
or by hardware when the interface is disabled
(I2CCR.PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 1 = BERR Bus Error.
Bit 5 = ADDTX Address or 2nd header transmitted
in Master mode.
This bit is set by hardware when the peripheral,
enabled in Master mode, has received the ac-
knowledge relative to:
This bit is set by hardware when the interface de-
tects a Start or Stop condition during a byte trans-
fer. An interrupt is generated if ITE=1.
It is cleared by software reading I2CSR2 register
or by hardware when the interface is disabled
(I2CCR.PE=0).
– Address byte in 7-bit mode
The SCL line is not held low while BERR=1.
Note: If a misplaced start condition is detected,
also the ARLO flag is set; moreover, if a misplaced
stop condition is placed on the acknowledge SCL
pulse, also the AF flag is set.
– Address or 2nd header byte in 10-bit mode.
0: No address or 2nd header byte transmitted
1: Address or 2nd header byte transmitted.
Bit 4 = AF Acknowledge Failure.
0: No Start or Stop condition detected during byte
transfer
1: Start or Stop condition detected during byte
transfer
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1.
It is cleared by software reading I2CSR2 register
after the falling edge of the acknowledge SCL
pulse, or by hardware when the interface is disa-
bled (I2CCR.PE=0).
Bit 0 = GCAL General Call address matched.
This bit is set by hardware after an address
matches with the value stored in the I2CADR reg-
ister while ENGC=1. In the I2CADR the General
Call address must be placed before enabling the
peripheral.
The SCL line is not held low while AF=1.
0: No acknowledge failure detected
1: A data or address byte was not acknowledged
It is cleared by hardware after the detection of a
Stop condition, or when the peripheral is disabled
(I2CCR.PE=0).
0: No match
1: General Call address matched.
230/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
2
I C CLOCK CONTROL REGISTER
I C OWN ADDRESS REGISTER 1
(I2COAR1)
(I2CCCR)
R243 - Read / Write
Register Page: 20
R244 - Read / Write
Register Page: 20
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
2
Bit 7 = FM/SM Fast/Standard I C mode.
7-bit Addressing Mode
This bit is used to select between fast and stand-
ard mode. See the description of the following bits.
It is set and cleared by software. It is not cleared
when the peripheral is disabled (I2CCR.PE=0)
Bits 7:1 = ADD[7:1] Interface address.
2
These bits define the I C bus address of the inter-
face.
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
Bits 6:0 = CC[6:0] 9-bit divider programming
Implementation of a programmable clock divider.
These bits and the CC[8:7] bits of the I2CECCR
Bit 0 = ADD0 Address direction bit.
This bit is don’t care; the interface acknowledges
either 0 or 1.
It is not cleared when the interface is disabled
(I2CCR.PE=0).
register select the speed of the bus (F
pending on the I C mode.
) de-
SCL
2
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
Note: Address 01h is always ignored.
– Standard mode (FM/SM=0): F
<= 100kHz
SCL
F
= INTCLK/(2x([CC8..CC0]+2))
10-bit Addressing Mode
SCL
– Fast mode (FM/SM=1): F
> 100kHz
Bits 7:0 = ADD[7:0] Interface address.
These are the least significant bits of the I Cbus
address of the interface.
They are not cleared when the interface is disa-
SCL
2
F
= INTCLK/(3x([CC8..CC0]+2))
SCL
Note: The programmed frequency is available
with no load on SCL and SDA pins.
bled (I2CCR.PE=0).
231/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
I C OWN ADDRESS REGISTER 2 (I2COAR2)
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(I2CCR.PE=0).
R245 - Read / Write
Register Page: 20
Reset Value: 0000 0000 (00h)
Bit 0 = Reserved.
7
0
2
FREQ1 FREQ0 EN10BIT FREQ2
0
ADD9 ADD8
0
I C DATA REGISTER (I2CDR)
R246 - Read / Write
Register Page: 20
Bits 7:6,4 = FREQ[2:0] Frequency bits.
Reset Value: 0000 0000 (00h)
IMPORTANT: To guarantee correct operation,
set these bits before enabling the interface
(while I2CCR.PE=0).
7
0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
These bits can be set only when the interface is
disabled (I2CCR.PE=0). To configure the interface
to I C specified delays, select the value corre-
sponding to the microcontroller internal frequency
INTCLK.
2
Bits 7:0 = DR[7:0] I2C Data.
– In transmitter mode:
I2CDR contains the next byte of data to be trans-
mitted. The byte transmission begins after the
microcontroller has written in I2CDR or on the
next rising edge of the clock if DMA is complete.
INTCLK
Range
(MHz)
FREQ2
FREQ1
FREQ0
2.5 - 6
6- 10
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
– In receiver mode:
I2CDR contains the last byte of data received.
The next byte receipt begins after the I2CDR
read by the microcontroller or on the next rising
edge of the clock if DMA is complete.
10- 14
14 - 30
30 - 50
GENERAL CALL ADDRESS (I2CADR)
R247 - Read / Write
Register Page: 20
Note: If an incorrect value, with respect to the
MCU internal frequency, is written in these bits,
2
Reset Value: 1010 0000 (A0h)
the timings of the peripheral will not meet the I C
bus standard requirements.
7
0
Note: The FREQ[2:0] = 101, 110, 111 configura-
tions must not be used.
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
2
2
Bit 5 = EN10BIT Enable 10-bit I Cbus mode.
Bits 7:0 = ADR[7:0] Interface address.
These bits define the I Cbus General Call address
2
When this bit is set, the 10-bit I Cbus mode is en-
abled.
of the interface. It must be written with the correct
This bit can be written only when the peripheral is
disabled (I2CCR.PE=0).
0: 7-bit mode selected
value depending on the use of the peripheral.If the
2
peripheral is used in I C bus mode, the 00h value
must be loaded as General Call address.
The customer could load the register with other
values.
1: 10-bit mode selected
The bits can be written only when the peripheral is
disabled (I2CCR.PE=0)
Bits 4:3 = Reserved.
The ADR0 bit is don’t care; the interface acknowl-
edges either 0 or 1.
Note: Address 01h is always ignored.
Bits 2:1 = ADD[9:8] Interface address.
These are the most significant bits of the I Cbus
2
232/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
INTERRUPT STATUS REGISTER (I2CISR)
R248 - Read / Write
Register Page: 20
Bit 2 = IERRP Error Condition pending bit
0: No error
1: Error event detected (if ITE=1)
Reset Value: 1xxx xxxx (xxh)
7
0
Note: Depending on the status of the
I2CISR.DMASTOP bit, this flag can suspend or
not suspend the DMA requests.
DMASTOP PRL2 PRL1 PRL0
0
IERRP IRXP ITXP
Note: The Interrupt pending bits can be reset by
writing a “0” but is not possible to write a “1”. It is
mandatory to clear the interrupt source by writing a
“0” in the pending bit when executing the interrupt
service routine. When serving an interrupt routine,
the user should reset ONLY the pending bit related
to the served interrupt routine (and not reset the
other pending bits).
Bit 7 = DMASTOP DMA suspended mode.
This bit selects between DMA suspended mode
and DMA not suspended mode.
In DMA Suspended mode, if the error interrupt
pending bit (I2CISR.IERRP) is set, no DMA re-
quest is performed. DMA requests are performed
only when IERRP=0. Moreover the “Error Condi-
tion” interrupt source has a higher priority than the
DMA.
In DMA Not-Suspended mode, the status of
IERRP bit has no effect on DMA requests. Moreo-
ver the DMA has higher priority with respect to oth-
er interrupt sources.
To detect the specific error condition that oc-
curred, the flag bits of the I2CSR1 and I2CSR2
register should be checked.
Note: The IERRP pending bit is forced high while
the error event flags are set (ADSL and SB flags in
the I2CSR1 register, SCLF, ADDTX, AF, STOPF,
ARLO and BERR flags in the I2CSR2 register). If
at least one flag is set, it is not possible to reset the
IERRP bit.
0: DMA Suspended mode
1: DMA Not-Suspended mode
Bits 6:4 = PRL[2:0] Interrupt/DMA Priority Bits.
The priority is encoded with these three bits. The
value of “0” has the highest priority, the value “7”
has no priority. After the setting of this priority lev-
el, the priorities between the different Interrupt/
DMA sources is hardware defined according with
the following scheme:
Bit 1 = IRXP Data Received pending bit
0: No data received
1: data received (if ITE=1).
Bit 0 = ITXP Peripheral Ready To Transmit pend-
ing bit
0: Peripheral not ready to transmit
1: Peripheral ready to transmit a data byte (if
ITE=1).
– Error condition Interrupt (If DMASTOP=1) (High-
est priority)
– Receiver DMA request
– Transmitter DMA request
– Error Condition Interrupt (If DMASTOP=0
– Data Received/Receiver End Of Block
– Peripheral Ready To Transmit/Transmitter End
Of Block (Lowest priority)
Bit 3 = Reserved.
Must be cleared.
233/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
INTERRUPT VECTOR REGISTER (I2CIVR)
R249 - Read / Write
Register Page: 20
(DMA between peripheral and Register file), this
register has no meaning.
See Section 0.1.6.1 for more details on the use of
Reset Value: Undefined
this register.
7
0
Bit 0 = RPS Receiver DMA Memory Pointer Selec-
tor.
If memory has been selected for DMA transfer
(DDCRDC.RF/MEM = 0) then:
V7
V6
V5
V4
V3
EV2 EV1
0
0: Select ISR register for Receiver DMA transfer
address extension.
1: Select DMASR register for Receiver DMA trans-
fer address extension.
Bits 7:3 = V[7:3] Interrupt Vector Base Address.
User programmable interrupt vector bits. These
are the five more significant bits of the interrupt
vector base address. They must be set before en-
abling the interrupt features.
RECEIVER DMA TRANSACTION COUNTER
REGISTER (I2CRDC)
R251 - Read / Write
Bits 2:1 = EV[2:1] Encoded Interrupt Source.
These Read-Only bits are set by hardware accord-
ing to the interrupt source:
Register Page: 20
Reset Value: Undefined
– 01: error condition detected
– 10: data received
7
0
– 11: peripheral ready to transmit
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RF/MEM
Bit 0 = Reserved.
Forced by hardware to 0.
Bits 7:1 = RC[7:1] Receiver DMA Counter Pointer.
I2CRDC contains the address of the pointer (in the
Register File) of the DMA receiver transaction
counter when the DMA between Peripheral and
Memory Space is selected. Otherwise (DMA be-
tween Peripheral and Register File), this register
points to a pair of registers that are used as DMA
Address register and DMA Transaction Counter.
See Section 0.1.6.1 and Section 0.1.6.2 for more
details on the use of this register.
RECEIVER DMA SOURCE ADDRESS POINTER
REGISTER (I2CRDAP)
R250 - Read / Write
Register Page: 20
Reset Value: Undefined
7
0
RA7 RA6 RA5 RA4 RA3 RA2 RA1
RPS
Bit 0 = RF/MEM Receiver Register File/ Memory
Selector.
0: DMA towards Memory
1: DMA towards Register file
Bits 7:1 = RA[7:1] Receiver DMA Address Pointer.
I2CRDAP contains the address of the pointer (in
the Register File) of the Receiver DMA data
source when the DMA is selected between the
peripheral and the Memory Space. Otherwise,
234/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
TRANSMITTER DMA SOURCE ADDRESS
POINTER REGISTER (I2CTDAP)
R252 - Read / Write
TRANSMITTER DMA TRANSACTION COUN-
TER REGISTER (I2CTDC)
R253 - Read / Write
Register Page: 20
Register Page: 20
Reset Value: Undefined
Reset Value: Undefined
7
0
7
0
TA7 TA6 TA5 TA4 TA3 TA2 TA1
TPS
TC7 TC6 TC5 TC4 TC3 TC2 TC1 RF/MEM
Bits 7:1= TA[7:1] Transmit DMA Address Pointer.
I2CTDAP contains the address of the pointer (in
the Register File) of the Transmitter DMA data
source when the DMA between the peripheral and
the Memory Space is selected. Otherwise (DMA
between the peripheral and Register file), this reg-
ister has no meaning.
Bits 7:1 = TC[7:1] Transmit DMA Counter Pointer.
I2CTDC contains the address of the pointer (in the
Register File) of the DMA transmitter transaction
counter when the DMA between Peripheral and
Memory Space is selected. Otherwise, if the DMA
between Peripheral and Register File is selected,
this register points to a pair of registers that are
used as DMA Address register and DMA Transac-
tion Counter.
See Section 0.1.6.2 for more details on the use of
this register.
See Section 0.1.6.1 and Section 0.1.6.2 for more
details on the use of this register.
Bit 0 = TPS Transmitter DMA Memory Pointer Se-
lector.
If memory has been selected for DMA transfer
(DDCTDC.RF/MEM = 0) then:
0: Select ISR register for transmitter DMA transfer
address extension.
1: Select DMASR register for transmitter DMA
transfer address extension.
Bit 0 = RF/MEM Transmitter Register File/ Memo-
ry Selector.
0: DMA from Memory
1: DMA from Register file
EXTENDED CLOCK CONTROL REGISTER
(I2CECCR)
R254 - Read / Write
Register Page: 20
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
CC8 CC7
Bits 7:2 = Reserved. Must always be cleared.
Bits 1:0 = CC[8:7] 9-bit divider programming
Implementation of a programmable clock divider.
These bits and the CC[6:0] bits of the I2CCCR reg-
ister select the speed of the bus (F
).
SCL
For a description of the use of these bits, see the
I2CCCR register.
They are not cleared when the interface is disa-
bled (I2CCCR.PE=0).
235/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
INTERRUPT MASK REGISTER (I2CIMR)
R255 - Read / Write
Register Page: 20
interrupt request.
Note: TEOBP can only be written to “0”.
0: End of block not reached
Reset Value: 00xx 0000 (x0h)
1: End of data block in DMA transmitter detected.
7
0
Bit 3 = Reserved. This bit must be cleared.
RXD TXD
IERR IRX ITX
REOBP TEOBP
0
M
M
M
M
M
Bit 2 = IERRM Error Condition interrupt mask bit.
This bit enables/ disables the Error interrupt.
0: Error interrupt disabled.
Bit 7 = RXDM Receiver DMA Mask.
0: DMA reception disable.
1: Error Interrupt enabled.
1: DMA reception enable
RXDM is reset by hardware when the transaction
counter value decrements to zero, that is when a
Receiver End Of Block interrupt is issued.
Bit 1 = IRXM Data Received interrupt mask bit.
This bit enables/ disables the Data Received and
Receive DMA End of Block interrupts.
0: Interrupts disabled
Bit 6 = TXDM Transmitter DMA Mask.
0: DMA transmission disable.
1: DMA transmission enable.
1: Interrupts enabled
Note: This bit has no effect on DMA transfer
TXDM is reset by hardware when the transaction
counter value decrements to zero, that is when a
Transmitter End Of Block interrupt is issued.
Bit 0 = ITXM Peripheral Ready To Transmit inter-
rupt mask bit.
This bit enables/ disables the Peripheral Ready To
Transmit and Transmit DMA End of Block inter-
rupts.
0: Interrupts disabled
1: Interrupts enabled
Bit 5 = REOBP Receiver DMA End Of Block Flag.
REOBP should be reset by software in order to
avoid undesired interrupt routines, especially in in-
itialization routine (after reset) and after entering
the End Of Block interrupt routine.Writing “0” in
this bit will cancel the interrupt request
Note: This bit has no effect on DMA transfer.
Note: REOBP can only be written to “0”.
0: End of block not reached.
1: End of data block in DMA receiver detected
Bit 4 = TEOBP Transmitter DMA End Of Block TE-
OBP should be reset by software in order to avoid
undesired interrupt routines, especially in initializa-
tion routine (after reset) and after entering the End
Of Block interrupt routine.Writing “0” will cancel the
236/324
9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
Table 44. I C BUS Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
I2CCR
-
-
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Reset Value
0
0
I2CSR1
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
Reset Value
I2CSR2
-
0
0
ADDTX
0
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
Reset Value
0
I2CCCR
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
Reset Value
I2COAR1
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
Reset Value
I2COAR2
FREQ1
0
FREQ0 EN10BIT FREQ2
0
0
ADD9
0
ADD8
0
0
0
Reset Value
0
0
0
I2CDR
DR7
0
DR6
0
DR5
0
DR4
0
DR3
0
DR2
0
DR1
0
DR0
0
Reset Value
I2CADR
ADR7
1
ADR6
0
ADR5
1
ADR4
0
ADR3
0
ADR2
0
ADR1
0
ADR0
0
Reset Value
I2CISR
DMASTOP
1
PRL2
X
PRL1
X
PRL0
X
IERRP
X
IRXP
X
ITXP
X
Reset Value
X
I2CIVR
V7
X
V6
X
V5
X
V4
X
V3
X
EV2
X
EV1
X
0
0
Reset Value
I2CRDAP
RA7
X
RA6
X
RA5
X
RA4
X
RA3
X
RA2
X
RA1
X
RPS
X
Reset Value
I2CRDC
RC7
X
RC6
X
RC5
X
RC4
X
RC3
X
RC2
X
RC1
X
RF/MEM
X
Reset Value
I2CTDAP
TA7
X
TA6
X
TA5
X
TA4
X
TA3
X
TA2
X
TA1
X
TPS
X
Reset Value
I2CTDC
TC7
X
TC6
X
TC5
X
TC4
X
TC3
X
TC2
X
TC1
X
RF/MEM
X
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
CC8
0
CC7
0
I2CECCR
I2CIMR
RXDM
0
TXDM
0
REOBP
X
TEOBP
X
IERRM
0
IRXM
0
ITXM
0
Reset Value
0
237/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
10.8 J1850 Byte Level Protocol Decoder (JBLPD)
10.8.1 Introduction
10.8.2 Main Features
■ SAE J1850 compatible
■ Digital filter
The JBLPD is used to exchange data between the
ST9 microcontroller and an external J1850 trans-
ceiver I.C.
■ In-Frame Responses of type 0, 1, 2, 3 supported
The JBLPD transmits a string of variable pulse
width (VPW) symbols to the transceiver. It also re-
ceives VPW encoded symbols from the transceiv-
er, decodes them and places the data in a register.
with automatic normalization bit
■ Programmable External Loop Delay
■ Diagnostic 4x time mode
■ Diagnostic Local Loopback mode
In-frame responses of type 0, 1, 2 and 3 are sup-
ported and the appropriate normalization bit is
generated automatically. The JBLPD filters out
any incoming messages which it does not care to
receive. It also includes a programmable external
loop delay.
■ Wide range of MCU internal frequencies
allowed
■ Low power consumption mode (JBLPD
suspended)
■ Very low power consumption mode (JBLPD
disabled)
The JBLPD uses two signals to communicate with
the transceiver:
■ Don’t care message filter
– VPWI (input)
■ Selectable VPWI input polarity
■ Selectable Normalization Bit symbol form
■ 6 maskable interrupts
– VPWO (output)
■ DMA transmission and reception with End Of
Block interrupts
238/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 109. JBLPD Byte Level Protocol Decoder Block Diagram
RXDATA
VPW
DIGITAL
FILTER
VPWI pin
DECODER
STATUS
ERROR
ARBITRATION
CHECKER
CONTROL
JBLPD
STATE
I.D. Filter
FREG[0:31]
MACHINE
CRC
GENERATOR
LOOPBACK
LOGIC
OPTIONS
TXOP
CLKSEL
CLOCK
PRESCALER
CRC BYTE
CRC\ BYTE
PADDR
Prescaled Clock
(Encoder/Decoder
Clock)
VPW
ENCODER
MUX
VPWO pin
TXDATA
Interrupt & DMA Logic and Registers
239/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.3 Functional Description
nate any transmissions in progress, and disable
receive transfers and RDRF flags until the VPW
decoder recognizes a valid EOF symbol from the
bus.
10.8.3.1 J1850 protocol symbols
J1850 symbols are defined as a duration (in micro-
seconds or clock cycles) and a state which can be
either an active state (logic high level on VPWO)
or a passive state (logic low level on VPWO).
An idle J1850 bus is in a passive state.
The JBLPD’s state machine handles all the Tv
l.D.s in accordance with the SAE J1850 specifica-
tion.
Any symbol begins by changing the state of the
VPW line. The line is in this state for a specific du-
ration depending on the symbol being transmitted.
Note: Depending on the value of a control bit, the
polarity of the VPWI input can be the same as the
J1850 bus or inverted with respect to it.
Durations, and hence symbols, are measured as
time between successive state transitions. Each
symbol has only one level transition of a specific
duration.
Symbols for logic zero and one data bits can be ei-
ther a high or a low level, but all other symbols are
defined at only one level.
Table 45. J1850 Symbol definitions
Symbol
Data Bit Zero
Definition
Passive for Tv1 or
Active for Tv2
Passive for Tv2 or
Active for Tv1
Each symbol is placed directly next to another.
Therefore, every level transition means that anoth-
er symbol has begun.
Data Bit One
Start of Frame (SOF)
End of Data (EOD)
End of Frame (EOF)
Active for Tv3
Passive for Tv3
Passive for Tv4
Data bits of a logic zero are either a short duration
if in a passive state or a long duration if in an active
state. Data bits of a logic one are either a long du-
ration if in a passive state or a short duration if in
an active state. This ensures that data logic zeros
predominate during bus arbitration.
Inter Frame Separation
(IFS)
Passive for Tv6
IDLE Bus Condition (IDLE) Passive for > Tv6
An eight bit data byte transmission will always
have eight transitions. For all data byte and CRC
byte transfers, the first bit is a passive state and
the last bit is an active state.
Active for Tv1 or
Normalization Bit (NB)
Tv2
Break (BRK)
Active for Tv5
For the duration of the VPW, symbols are ex-
pressed in terms of Tv’s (or VPW mode timing val-
ues). J1850 symbols and Tv values are described
in the SAE J1850 specification, in Table 1 and in
Table 2.
Table 46. J1850 VPW Mode Timing Value (Tv)
definitions (in clock cycles)
An ignored Tv I.D. occurs for level transitions
which occur in less than the minimum time re-
quired for an invalid bit detect. The VPW encoder
does not recognize these characters as they are
filtered out by the digital filter. The VPW decoder
does not resynchronize its counter with either
edge of “ignored” pulses. Therefore, the counter
which times symbols continues to time from the
last transition which occurred after a valid symbol
(including the invalid bit symbol) was recognized.
Pulse
Width or Tv
Minimum Nominal Maximum
Duration Duration Duration
I.D.
Ignored
0
N/A
N/A
64
<=7
Invalid Bit
Tv1
>7
<=34
<=96
<=163
<=239
N/A
>34
>96
>163
>239
>239
>280
Tv2
128
200
280
300
300
Tv3
A symbol recognized as an invalid bit will resyn-
chronize the VPW decoder to the invalid bit edges.
In the case of the reception of an invalid bit, the
JBLPD peripheral will set the IBD bit in the ER-
ROR register. The JBLPD peripheral shall termi-
Tv4
Tv5
N/A
Tv6
N/A
240/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.3.2 Transmitting Messages
chronize off the decoder output to time the VPWO
symbol time.
This section describes the general procedures
used by the JBLPD to successfully transmit J1850
frames of data out the VPWO pin. The first five
sub-sections describe the procedures used for
transmitting the specific transmit data types. The
last section goes into the details of the transmitted
symbol timing, synchronizing of symbols received
from the external J1850 bus, and how data bit ar-
bitration works.
A detailed description of the JBLPD opcodes can
be find in the description of the OP[2:0] bits in the
TXOP register.
Message Byte String Transmission (Type 0
IFR)
Message byte transmitting is the outputting of data
bytes on the VPWO pin that occurs subsequent to
a received bus idle condition. All message byte
strings start with a SOF symbol transmission, then
one or more data bytes are transmitted. A CRC
byte is then transmitted followed by an EOD sym-
bol (see Figure 2) to complete the transmission. If
transmission is queued while another frame is be-
ing received, then the JBLPD will time an Inter-
Frame Separation (IFS) time (Tv6) before com-
mencing with the SOF character.
The important concept to note for transmitting data
is: the activity sent over the VPWO line should be
timed with respect to the levels and transitions
seen on the filtered VPWI line.
The J1850 bus is a multiplexed bus, and the
VPWO & VPWI pins interface to this bus through a
transceiver I.C. Therefore, the propagation delay
through the transceiver I.C. and external bus filter-
ing must be taken into account when looking for
transmitted edges to appear back at the receiver.
The external propagation delay for an edge sent
out on the VPWO line, to be detected on the VPWI
The user program will decide at some point that it
wants to initiate a message byte string. The user
program writes the TXDATA register with the first
message data byte to be transmitted. Next, the
TXOP register is written with the MSG opcode if
more than one data byte is contained within the
message, or with MSG+CRC opcode if one data
byte is to be transmitted. The action of writing the
TXOP register causes the TRDY bit to be cleared
signifying that the TXDATA register is full and a
corresponding opcode has been queued. The
JBLPD must wait for an EOF nominal time period
at which time data is transferred from the TXDATA
register to the transmit shift register. The TRDY bit
is again set since the TXDATA register is empty.
line is denoted as T
and is programmable be-
p-ext
tween 0 and 31 µs nominal via the JDLY[4:0] bits
in CONTROL register.
The transmitter VPW encoder sets the proper level
to be sent out the VPWO line. It then waits for the
corresponding level transition to be reflected back
at the VPW decoder input.
Taking into account the external loop delay (T
)
p-ext
and the digital filter delay, the encoder will time its
output to remain at this level so that the received
symbol is at the correct nominal symbol time (refer
to “Transmit Opcode Queuing” section). If arbitra-
tion is lost at any time during bit 0 or bit 1 transmis-
sion, then the VPWO line goes passive. At the end
of the symbol time on VPWO, the encoder chang-
es the state of VPWO if any more information is to
be transmitted. It then times the new state change
from the receiver decoder output.
Note that depending on the symbol (especially the
SOF, NB0, NB1 symbols) the decoder output may
actually change to the desired state before the
transmit is attempted. It is important to still syn-
The JBLPD should also begin transmission if an-
other device begins transmitting early. As long as
an EOF minimum time period elapses, the JBLPD
should begin timing and asserting the SOF symbol
with the intention of arbitrating for the bus during
the transmission of the first data byte. If a transmit
is requested during an incoming SOF symbol, the
JBLPD should be able to synchronize itself to the
incoming SOF up to a time of Tv1 max. (96 µs) into
the SOF symbol before declaring that it was too
late to arbitrate for this frame.
241/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
If the J1850 bus was IDLE at the time the first data
byte and opcode are written, the transmitter will
immediately transfer data from the TXDATA regis-
ter to the transmit shift register. The TRDY bit will
once again be set signifying the readiness to ac-
cept a new data byte. The second data byte can
then be written followed by the respective opcode.
In the case of the last data byte, the TXOP register
should be written with the MSG+CRC opcode. The
transmitter will transmit the internally generated
CRC after the last bit of the data byte. Once the
TRDY bit is set signifying the acceptance of the
last data byte, the first byte of the next message
can be queued by writing the TXDATA register fol-
lowed by a TXOP register write. The block will wait
until the current data and the CRC data byte are
sent out and a new IFS has expired before trans-
mitting the new data. This is the case even if IFR
data reception takes place in the interim.
register except during DMA transfers (see Section
0.1.6.4 DMA Management in Transmission Mode).
Transmitting a Type 1 IFR
The user program will decide to transmit an IFR
type 1 byte in response to a message which is cur-
rently being received (See Figure 3). It does so by
writing the IFR1 opcode to the TXOP register.
Transmitting IFR data type 1 requires only a single
write of the TXOP register with the IFR1 opcode
set. The MLC[3:0] bits should be set to the proper
“byte-received-count-required-before-IFR’ing” val-
ue. If no error conditions (IBD, IFD, TRA, RBRK or
CRCE) exist to prevent transmission, the JBLPD
peripheral will then transmit out the contents of the
PADDR register at the next EOD nominal time pe-
riod or at a time greater than the EOD minimum
time period if a falling edge is detected on filtered
J1850 bus line signifying another transmitter is be-
ginning early. The NB1 symbol precedes the PAD-
DR register value and is followed with an EOF de-
limiter. The TRDY flag is cleared on the write of the
TXOP register. The TRDY bit is set once the NB1
begins transmitting.
Lost arbitration any time during the transfer of type
0 data will be honoured by immediately relinquish-
ing control to the higher priority message. The TLA
bit in the STATUS register is set accordingly and
an interrupt will be generated assuming the
TLA_M bit in the IMR register is set. It is responsi-
bility of the user program to re-send the message
beginning with the first byte if desired. This may be
done at any time by rewriting only the TXOP regis-
ter if the TXDATA contents have not changed.
Although the JBLPD should never lose arbitration
for data in the IFR portion of a type 1 frame, higher
priority messages are always honoured under the
rules of arbitration. If arbitration is lost then the
VPWO line is set to the passive state. The TLA bit
in the STATUS register is set accordingly and an
interrupt will be generated if enabled. The IFR1 is
not retried. It is lost if the JBLPD peripheral loses
arbitration. Also, the data that made it out on the
bus will be received in the RXDATA register if not
put into sleep mode. Note that for the transmitter to
synchronize to the incoming signals of a frame, an
IFR should be queued before an EODM is re-
ceived for the present frame.
Any transmitted data and CRC bytes during the
transmit frame will also be received and trans-
ferred to the RXDATA register if the corresponding
message filter bit is set in the FREG[0:31] regis-
ters. If the corresponding bit is not set in
FREG[0:31], then the transmitted data is also not
transferred to RXDATA. Also, the RDRF will not
get set during frame and receive events such as
RDOF & EODM.
NOTE: The correct procedure for transmitting is to
write first the TXDATA register and then the TXOP
242/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Transmitting a Type 2 IFR
is currently being received (See Figure 5). It does
so by writing the IFR3 or IFR3+CRC opcode to the
TXOP register. Transmitting IFR data type 3 is
similar to transmitting a message, in that the TX-
DATA register is written with the first data byte fol-
lowed by a TXOP register write. For a single data
byte IFR3 transmission, the TXOP register would
be written with IFR3+CRC opcode set. The
MLC[3:0] bits can also be set to a proper value to
check for message length errors before enabling
the IFR transmit.
The user program will decide to transmit an IFR
type 2 byte in response to a message which is cur-
rently being received (See Figure 4). It does so by
writing the IFR2 opcode to the TXOP register.
Transmitting IFR data type 2 requires only a single
write of the TXOP register with the IFR2 opcode
set. The MLC[3:0] bits can also be set to check for
message length errors. If no error conditions (IBD,
IFD, TRA, RBRK or CRCE) exist to prevent trans-
mission, the JBLPD will transmit out the contents
of the PADDR register at the next EOD nominal
time period or after an EOD minimum time period if
a rising edge is detected on the filtered VPWI line
signifying another transmitter beginning early. The
NB1 symbol precedes the PADDR register value
and is followed with an EOF delimiter. The TRDY
flag will be cleared on the write of the TXOP regis-
ter. The TRDY bit is set once the NB1 begins
transmitting.
If no error conditions (IBD, IFD, TRA, RBRK or
CRCE) exist to prevent transmission, the JBLPD
will wait for an EOD nominal time period on the fil-
tered VPWI line (or for at least an EOD minimum
time followed by a rising edge signifying another
transmitter beginning early) at which time data is
transferred from the TXDATA register to the trans-
mit shift register. The TRDY bit is set since the TX-
DATA register is empty. A NB0 symbol is output
on the VPWO line followed by the data byte and
possibly the CRC byte if a IFR3+CRC opcode was
set. Once the first IFR3 byte has been successfully
transmitted, successive IFR3 bytes are sent with
TXDATA/TXOP write sequences where the
MLC[3:O] bits are don’t cares. The final byte in the
IFR3 string must be transmitted with the
IFR3+CRC opcode to trigger the JBLPD to ap-
pend the CRC byte to the string. The user program
may queue up the next message opcode se-
quence once the TRDY bit has been set.
Lost arbitration for this case is a normal occur-
rence since type 2 IFR data is made up of single
bytes from multiple responders. If arbitration is lost
the VPWO line is released and the JBLPD waits
until the byte on the VPWI line is completed. Note
that the IFR that did make it out on the bus will be
received in the RXDATA register if it is not put into
sleep mode. Then, the JBLPD re-attempts to send
its physical address immediately after the end of
the last byte. The TLA bit is not set if arbitration is
lost and the user program does not need to re-
queue data or an opcode. The JBLPD will re-at-
tempt to send its PADDR register contents until it
successfully does so or the 12-byte frame maxi-
mum is reached if NFL=0. If NFL=1, then re-at-
tempts to send an lFR2 are executed until can-
celled by the CANCEL opcode or a JBLPD disa-
ble. Note that for the transmitter to synchronize to
the incoming signals of a frame, an IFR should be
queued before an EODM is received for the
present frame.
Although arbitration should never be lost for data
in the IFR portion of a type 3 frame, higher priority
messages are always honoured under the rules of
arbitration. If arbitration is lost then the block
should relinquish the bus by taking the VPWO line
to the passive state. In this case the TLA bit in the
STATUS register is set, and an interrupt will be
generated if enabled. Note also, that the IFR data
that did make it out on the bus will be received in
the RXDATA register if not in sleep mode. Note
that for the transmitter to synchronize to the in-
coming signals of a frame, an IFR should be
queued before an EODM is received for the cur-
rent frame.
Transmitting a Type 3 lFR Data String
The user program will decide to transmit an IFR
type 3 byte string in response to a message which
243/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 110. J1850 String Transmission Type 0
Frame
Message
I.D.
Byte
SOF
Data byte(s) (if any)
CRC EOF
Figure 111. J1850 String Transmission Type 1
Frame
IFR
to be sent
Message Rx’d from Another Node
I.D.
Byte
IFR
Byte
SOF
Data byte(s) (if any)
CRC EOD NB1
EOF
Figure 112. J1850 String Transmission Type 2
Frame
IFR
to be sent
Message Rx’d from Another Node
I.D.
IFR
NB1 Byte
... ...
IFR
Byte
Data byte(s) (if any)
Byte
CRC EOD
EOF
SOF
Figure 113. J1850 String Transmission Type 3
Frame
IFR
to be sent
Message Rx’d from Another Node
CRC
Byte
I.D.
SOF
Data byte(s) (if any)
Byte
CRC EOD NB0 IFR Data Byte(s)
EOF
244/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Transmit Opcode Queuing
JBLPD has a receiver pin which tells the transmit-
ter about bus activity. Due to characteristics of the
J1850 bus and the eight-clock digital filter, the sig-
nals presented to the VPW symbol decoder are
delayed a certain amount of time behind the actual
J1850 bus. Also, due to wave shaping and other
signal conditioning of the transceiver I.C. the ac-
tions of the VPWO pin on the transmitter take time
to appear on the bus itself. The total external
J1850 bus delays are defined in the SAE J1850
standard as nominally 16 µs. The nominal 16 µs
loop delay will actually vary between different
transceiver I.C’s. The JBLPD peripheral thus in-
cludes a programmability of the external loop de-
lay in the bit positions JDLY[4:0]. This assures
only nominal transmit symbols are placed on the
bus by the JBLPD.
The JBLPD has the capability of queuing opcode
transmits written to the TXOP register until J1850
bus conditions are in a correct state for the trans-
mit to occur. For example, a MSGx opcode can be
queued when the JBLPD is presently receiving a
frame (or transmitting a MSG+CRC opcode) or an
IFRx opcode can be queued when currently re-
ceiving or transmitting the message portion of a
frame.
Queuing a MSG or MSG+CRC opcode for the next
frame can occur while another frame is in
progress. A MSGx opcode is written to the TXOP
register when the present frame is past the point
where arbitration for control of the bus for this
frame can occur. The JBLPD will wait for a nomi-
nal IFS symbol (or EOFmin if another node begins
early) to appear on the VPWI line before com-
mencing to transmit this queued opcode. The
TRDY bit for the queued opcode will remain clear
until the EOFmin is detected on the VPWI line
where it will then get set. Queued MSGx transmits
for the next frame do not get cancelled for TLA,
IBD, IFD or CRCE errors that occur in the present
frame. An RBRK error will cancel a queued op-
code for the next frame.
The method of transmitting for the JBLPD includes
interaction between the transmitter and the receiv-
er. The transmitter starts a symbol by placing the
proper level (active or passive) on its VPWO pin.
The transmitter then waits for the corresponding
pin transition (inverted, of course) at the VPW de-
coder input. Note that the level may actually ap-
pear at the input before the transmitter places the
value on the VPWO pin. Timing of the remainder
of the symbol starts when the transition is detect-
ed. Refer to Figure 7, Case 1. The symbol timeout
value is defined as:
Queuing an IFRx opcode for the present frame
can occur at any time after the detection of the be-
ginning of an SOF character from the VPWI line.
The queued IFR will wait for a nominal EOD sym-
bol (or EODmin if another node begins early) be-
fore commencing to transmit the IFR. A queued
IFR transmit will be cancelled on IBD, lFD, CRCE,
RBRK errors as well as on a correct message
length check error or frame length limit violation if
these checks are enabled.
SymbolTimeout = NominalSymbolTime - ExternalLoop-
Delay - 8 µs
NominalSymbolTime = Tv Symbol time
ExternalLoopDelay = defined via JDLY[4:0]
8 µs = Digital Filter
Bit-by-bit arbitration must be used to settle the
conflicts that occur when multiple nodes attempt to
transmit frames simultaneously. Arbitration is ap-
plied to each data bit symbol transmitted starting
after the SOF or NBx symbol and continuing until
the EOD symbol. During simultaneous transmis-
sions of active and passive states on the bus, the
resultant state on the bus is the active state. If the
JBLPD detects a received symbol from the bus
that is different from the symbol being transmitted,
then the JBLPD will discontinue its transmit opera-
tion prior to the start of the next bit. Once arbitra-
tion has been lost, the VPWO pin must go passive
within one period of the prescaled clock of the pe-
ripheral. Figure 6 shows 3 nodes attempting to ar-
bitrate for the bus with Node B eventually winning
with the highest priority data.
Transmit Bus Timing, Arbitration, and Syn-
chronization
The external J1850 bus on the other side of the
transceiver I.C. is a single wire multiplex bus with
multiple nodes transmitting a number of different
types of message frames. Each node can transmit
at any time and synchronization and arbitration is
used to determine who wins control of the trans-
mit. It is the obligation of the JBLPD transmitter
section to synchronize off of symbols on the bus,
and to place only nominal symbol times onto the
bus within the accuracy of the peripheral (+/- 1 µs).
To transmit proper symbols the JBLPD must know
what is going on out on the bus. Fortunately, the
245/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 114. J1850 Arbitration Example
Transmitting
Node A
Active
Passive
0
0
0
0
0
0
0
0
1 1 0
0 0 1
0 0
SOF
SOF
SOF
SOF
Transmitting
Node B
Active
Passive
1 1 0
0
0
Transmitting
Node C
Active
Passive
1 1 0 1
1 1 0
Active
Passive
Signal
on Bus
0 0
Figure 115. J1850 Received Symbol Timing
178 µs
VPWO
Case 1 VPWI
VPW Decoder
178 µs
VPWO
TX2
Case 2
VPWI
VPW Decoder
178 µs
VPWO
TX2
Case 3
VPWI
VPW Decoder
0
14
200 214
-6
8
22
192 208 222
246/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Use of symbol and bit synchronization is an inte-
gral part of the J1850 bus scheme. Therefore, tight
coupling of the encoder and decoder functions is
required to maintain synchronization during trans-
mits. Transmitted symbols and bits are initiated by
the encoder and are timed through the decoder to
realize synchronization. Figure 7 exemplifies syn-
chronization with 3 examples for an SOF symbol
and JDLY[4:0] = 01110b.
10.8.3.3 Receiving Messages
Data is received from the external analog trans-
ceiver on the VPWI pin. VPWI data is immediately
passed through a digital filter that ignores all puls-
es that are less than 7µs. Pulses greater than or
equal to 7µs and less than 34µs are flagged as
invalid bits (IBD) in the ERROR register.
Once data passes through the filter, all delimiters
are stripped from the data stream and data bits are
shifted into the receive shift register by the decod-
er logic. The first byte received after a valid SOF
character is compared with the flags contained in
FREG[0:31]. If the compare indicates that this
message should be received, then the receive
shift register contents are moved to the receive
data register (RXDATA) for the user program to
access. The Receive Data Register Full bit
(RDRF) is set to indicate that a complete byte has
been received. For each byte that is to be received
in a frame, once an entire byte has been received,
the receive shift register contents are moved to the
receive data register (RXDATA). All data bits re-
ceived, including CRC bits, are transferred to the
RXDATA register. The Receive Data Register Full
bit (RDRF) is set to indicate that a complete byte
has been received.
Case 1 shows a single transmitter arbitrating for
the bus. The VPWO pin is asserted, and 14µs later
the bus transitions to an active state. The 14µs de-
lay is due to the nominal delay through the exter-
nal transceiver chip. The signal is echoed back to
the transceiver through the VPWI pin, and pro-
ceeds through the digital filter. The digital filter has
a loop delay of 8 clock cycles with the signal finally
presented to the decoder 22 µs after the VPWO
pin was asserted. The decoder waits 178 µs be-
fore issuing a signal to the encoder signifying the
end of the symbol. The VPWO pin is de-asserted
producing the nominal SOF bit timing (22 µs +
178µs = 200 µs).
Case 2 shows a condition where 2 transmitters at-
tempt to arbitrate for the bus at nearly the same
time with a second transmitter, TX2, beginning
slightly earlier than the VPWO pin. Since the
JBLPD always times symbols from its receiver
perspective, 178µs after the decoder sees the ris-
ing edge it issues a signal to the encoder to signify
the end of the SOF. Nominal SOF timings are
maintained and the JBLPD re-synchronizes to
TX2.
If the first byte after a valid SOF indicates non-re-
ception of this frame, then the current byte in the
receive shift register is inhibited from being trans-
ferred to the RXDATA register and the RDRF flag
remains clear (see the “Received Message Filter-
ing” section). Also, no flags associated with receiv-
ing a message (RDOF, CRCE, IFD, IBD) are set.
Case 3 again shows an example of 2 transmitters
attempting to arbitrate for the bus at nearly the
same time with the VPWO pin starting earlier than
TX2. In this case TX2 is required to re-synchronize
to VPWO.
A CRC check is kept on all bytes that are trans-
ferred to the RXDATA register during message
byte reception (succeeding an SOF symbol) and
IFR3 reception (succeeding an NB0 symbol). The
CRC is initialized on receipt of the first byte that
follows an SOF symbol or an NB0 symbol. The
CRC check concludes on receipt of an EODM
symbol. The CRC error bit (CRCE), therefore, gets
set after the EODM symbol has been recognized.
Refer to the “SAE Recommended Practice -
J1850” manual for more information on CRCs.
All 3 examples exemplify how bus timings are driv-
en from the receiver perspective. Once the receiv-
er detects an active bus, the transmitter symbol
timings are timed minus the transceiver and digital
filter delays (i.e. SOF = 200 µs - 14µs - 8µs =
178µs). This synchronization and timing off of the
VPWI pin occurs for every symbol while transmit-
ting. This ensures true arbitration during data byte
transmissions.
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Received Message Filtering
user program. All receiver flags and interrupts
function normally.
The FREG[0:31] registers can be considered an
array of 256 bits (the FREG[0].0 bit is bit 0 of the
array and the FREG[31].7 bit is bit 255). The I.D.
byte of a message frame is used as a pointer to
the array (See Figure 8).
Note that a break symbol received during a filtered
out message will still be received. Note also that
the filter comparison occurs after reception of the
first byte. So, any receive errors that occur before
the message filter comparison (i.e. IBD, IFD) will
be active at least until the filter comparison.
Upon the start of a frame, the first data byte re-
ceived after the SOF symbol determines the I.D. of
the message frame. This I.D. byte addresses the
I.D. byte flags stored in registers FREG[0:31]. This
operation is accomplished before the transfer of
the I.D. byte into the RXDATA register and before
the RDRF bit is set.
Transmitted Message Filtering
When transmitting a message, the corresponding
FREG[0:31] I.D. filter bit may be set or cleared. If
set, then the JBLPD will receive all data informa-
tion transferred during the frame, unless sleep
mode is invoked. Everything the JBLPD transmits
will be reflected in the RXDATA register.
If the corresponding bit in the message filter array,
FREG[0:31], is set to zero (0), then the I.D. byte is
not transferred to the RXDATA register and the
RDRF bit is not set. Also, the remainder of the
message frame is ignored until reception of an
EOFmin symbol. A received EOFmin symbol ter-
minates the operation of the message filter and
enables the receiver for the next message. None
of the flags related to the receiver, other than
IDLE, are set. The EODM flag does not get set
during a filtered frame. No error flags other than
RBRK can get set.
Because the JBLPD has invalid bit detect (IBD),
invalid frame detect (IFD), transmitter lost arbitra-
tion (TRA), and Cyclic Redundancy Check Error
(CRCE) it is not necessary for the transmitter to lis-
ten to the bytes that it is transmitting. The user
may wish to filter out the transmitted messages
from the receiver. This can reduce interrupt bur-
den. When a transmitted I.D. byte is filtered by the
receiver section of the block, then RDRF, RDOF,
EODM flags are inhibited and no RXDATA trans-
fers occur. The other flags associated normally
with receiving - RBRK, CRCE, IFD, and IBD - are
not inhibited, and they can be used to ascertain
the condition of the message transmit.
If the corresponding bit in the message filter array,
FREG[0:31], is set to a one (1), then the I.D. byte
is transferred to the RXDATA register and the
RDRF is set. Also, the remainder of the message
is received unless sleep mode is invoked by the
Figure 116. I.D. Byte and Message Filter Array use
Bit 0 = FREG[0].0
Bit 1 = FREG[0].1
Bit 2 = FREG[0].2
Bit 3 = FREG[0].3
Bit 4 = FREG[0].4
I.D. byte
value = n
Bit n-1
Bit n
Bit n+1
Bit 254 = FREG[31].6
Bit 255 = FREG[31].7
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.3.4 Sleep Mode
ing the TRDY, TLA, TTO, TDUF, TRA, IBD, IFD,
and CRCE bits to be set if required. This mode al-
lows the user to not have to listen while talking.
Sleep mode allows the user program to ignore the
remainder of a message. Normally, the user pro-
gram can recognise if the message is of interest
from the header bytes at the beginning of the mes-
sage. If the user program is not interested in the
message it simply writes the SLP bit in the PRLR
register. This causes all additional data on the bus
to be ignored until an EOF minimum occurs. No
additional flags (but not the EOFM flag) and, there-
fore, interrupts are generated for the remainder of
the message. The single exception to this is a re-
ceived break symbol while in sleep mode. Break
symbols always take precedence and will set the
RBRK bit in the ERROR register and generate an
interrupt if the ERR_M bit in IMR is set. Sleep
mode and the SLP bit gets cleared on reception of
an EOF or Break symbol.
10.8.3.5 Normalization Bit symbol selection
The form of the NB0/NB1 symbol changes de-
pending on the industry standard followed. A bit
(NBSYMS) in the OPTIONS register selects the
symbol timings used. Refer to Table 3.
10.8.3.6 VPWI input line management
The JBLPD is able to work with J1850 transceiver
chips that have both inverted and not inverted RX
signal. A dedicated bit (INPOL) of the OPTIONS
register must be programmed with the correct val-
ue depending on the polarity of the VPWI input
with respect to the J1850 bus line. Refer to the IN-
POL bit description for more details.
Writes to the SLP bit will be ignored if:
1) A valid EOFM symbol was the last valid symbol
detected,
10.8.3.7 Loopback mode
AND
The JBLPD is able to work in loopback mode. This
mode, enabled setting the LOOPB bit of the OP-
TIONS register, internally connects the output sig-
nal (VPWO) of the JBLPD to the input (VPWI)
without polarity inversion. The external VPWO pin
of the MCU is forced in its passive state and the
external VPWI pin is ignored (Refer to Figure 9).
2) The J1850 bus line (after the filter) is passive.
Therefore, sleep mode can only be invoked after
the SOF symbol and subsequent data has been
received, but before a valid EOF is detected. If
sleep mode is invoked within this time window,
then any queued IFR transmit is aborted. If a MSG
type is queued and sleep mode is invoked, then
the MSG type will remain queued and an attempt
to transmit will occur after the EOF period has
elapsed as usual.
Note: When the LOOPB bit is set or reset, edges
could be detected by the J1850 decoder on the in-
ternal VPWI line. These edges could be managed
by the JBLPD as J1850 protocol errors. It is sug-
gested to enable/disable LOOPB when the JBLPD
If SLP mode is invoked while the JBLPD is current-
ly transmitting, then the JBLPD effectively inhibits
the RDRF, RDT, EODM, & RDOF flags from being
set, and disallows RXDATA transfers. But, it other-
wise functions normally as a transmitter, still allow-
is
suspended
(CONTROL.JE=0,
CON-
TROL.JDIS=0) or when the JBLPD is disabled
(CONTROL.JDIS=1).
Table 47. Normalization Bit configurations
Symbol
NB0
NBSYMS=0
active Tv2 (active long)
active Tv1 (active short)
NBSYMS=1
IFR with CRC
active Tv1 (active short)
active Tv2 (active long)
IFR without CRC
NB1
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 117. Local Loopback structure
MCU
JBLPD peripheral
Passive state
MCU VPWO
pin
VPWO from the
peripheral logic
VPWI toward the
Polarity
manager
MCU VPWI
pin
J1850 decoder
OPTIONS.INPOL
OPTIONS.LOOPB
10.8.3.8 Peripheral clock management
(FREQ[5:0]) must be programmed with a value us-
ing the following formula:
To work correctly, the encoder and decoder sec-
tions of the peripheral need an internal clock at
1MHz. This clock is used to evaluate the protocol
symbols timings in transmission and in reception.
MCU Internal Freq. = 1MHz * (FREQ[5:0] + 1).
Note: If the MCU internal clock frequency is lower
than 1MHz, the JBLPD is not able to work correct-
ly. If a frequency lower than 1MHz is used, the
user program must disable the JBLPD.
The prescaled clock is obtained by dividing the
MCU internal clock frequency. The CLKSEL regis-
ter allows the selection of the right prescaling fac-
tor. The six least significant bits of the register
Note: When the MCU internal clock frequency or
the clock prescaler factor are changed, the JBLPD
could lose synchronization with the J1850 bus.
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.4 Peripheral Functional Modes
tion when the JBLPD is not used, even if the de-
coder is able to follow the bus traffic. So, at any
time the JBLPD is enabled, it is immediately syn-
chronized with the J1850 bus.
The JBLPD can be programmed in 3 modes, de-
pending on the value of the JE and JDIS bits in the
CONTROL register, as shown in Table 4.
Note: While the JBLPD is suspended, the STA-
TUS register, the ERROR register and the SLP bit
of the PRLR register are forced into their reset val-
ue.
Table 48. JBLPD functional modes
JE
0
JDIS mode
1
0
0
JBLPD Disabled
0
JBLPD Suspended
JBLPD Enabled
10.8.4.3 JBLPD Disabled (Very Low Power
Mode)
1
Setting the JDIS bit in the CONTROL register, the
JBLPD is stopped until the bit is reset by software.
Also the J1850 decoder is stopped, so the JBLPD
is no longer synchronized with the bus. When the
bit is reset, the JBLPD will wait for a new idle state
on the J1850 bus. This mode can be used to mini-
mize power consumption when the JBLPD is not
used.
Depending on the mode selected, the JBLPD is
able or unable to transmit or receive messages.
Moreover the power consumption of the peripheral
is affected.
Note: The configuration with both JE and JDIS set
is forbidden.
Note: While the JDIS bit is set, the STATUS regis-
ter, the ERROR register, the IMR register and the
SLP, TEOBP and REOBP bits of the PRLR regis-
ter are forced to their reset value.
10.8.4.1 JBLPD Enabled
When the JBLPD is enabled (CONTROL.JE=1), it
is able to transmit and receive messages. Every
feature is available and every register can be writ-
ten.
Note: In order that the JDIS bit is able to reset the
IMR register and the TEOBP and REOBP bits, the
JDIS bit must be left at 1 at least for 6 MCU clock
cycles (3 NOPs).
10.8.4.2 JBLPD Suspended (Low Power Mode)
Note: The JE bit of CONTROL register cannot be
set with the same instruction that reset the JDIS
bit. It can be set only after the JDIS bit is reset.
When the JBLPD is suspended (CONTROL.JE=0
and CONTROL.JDIS=0), all the logic of the
JBLPD is stopped except the decoder logic.
This feature allows a reduction of power consump-
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.5 Interrupt Features
the RXDATA register (see also the RDRF bit de-
scription of the STATUS register).
The JBLPD has six interrupt sources that it han-
dles using the internal interrupts protocol. Other
two interrupt sources (REOB and TEOB) are relat-
ed to the DMA feature (See Section 0.1.6 DMA
Features).
– The REOB (Receive End Of Block) interrupt is
generated when receiving using DMA and the
last byte of a sequence of data is read from the
JBLPD.
No external interrupt channel is used by the
JBLPD.
– The TRDY interrupt is generated by two condi-
tions: when the TXOP register is ready to accept
a new opcode for transmission; when the trans-
mit state machine accepts the opcode for trans-
mission (a more detailed description of this
condition is given in the TRDY bit description of
the STATUS register).
The dedicated registers of the JBLPD should be
loaded with appropriate values to set the interrupt
vector (see the description of the IVR register), the
interrupt mask bits (see the description of the IMR
register) and the interrupt pending bits (see the de-
scription of the STATUS and PRLR registers).
– The TEOB (Transmit End Of Block) interrupt is
generated when transmitting using DMA and the
last byte of a sequence of data is written to the
JBLPD.
The interrupt sources are as follows:
– The ERROR interrupt is generated when the ER-
ROR bit of the STATUS register is set. This bit is
set when the following events occur: Transmitter
Timeout, Transmitter Data Underflow, Receiver
Data Overflow, Transmit Request Aborted, Re-
ceived Break Symbol, Cyclic Redundancy Check
Error, Invalid Frame Detect, Invalid Bit Detect (a
more detailed description of these events is giv-
en in the description of the ERROR register).
10.8.5.1 Interrupt Management
To use the interrupt features the user has to follow
these steps:
– Set the correct priority level of the JBLPD
– Set the correct interrupt vector
– Reset the Pending bits
– The TLA interrupt is generated when the trans-
mitter loses the arbitration (a more detailed de-
scription of this condition is given in the TLA bit
description of the STATUS register).
– Enable the required interrupt source
Note: It is strongly recommended to reset the
pending bits before un-masking the related inter-
rupt sources to avoid spurious interrupt requests.
– The EODM interrupt is generated when the
JBLPD detects a passive level on the VPWI line
longer than the minimum time accepted by the
standard for the End Of Data symbol (a more de-
tailed description of this condition is given in the
EODM bit description of the STATUS register).
The priority with respect the other ST9 peripherals
is programmable by the user setting the three
most significant bits of the Interrupt Priority Level
register (PRLR). The lowest interrupt priority is ob-
tained by setting all the bits (this priority level is
never acknowledged by the CPU and is equivalent
to disabling the interrupts of the JBLPD); the high-
est interrupt priority is programmed resetting the
bits. See the Interrupt and DMA chapters of the
datasheet for more details.
– The EOFM interrupt is generated when the
JBLPD detects a passive level on the VPWI line
longer than the minimum time accepted by the
standard for the End Of Frame symbol (a more
detailed description of this condition is given in
the EOFM bit description of the STATUS regis-
ter).
When the JBLPD interrupt priority is set, the prior-
ity between the internal interrupt sources is fixed
by hardware as shown in Table 5.
– The RDRF interrupt is generated when a com-
plete data byte has been received and placed in
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Note: After an MCU reset, the DMA requests of
the JBLPD have a higher priority than the interrupt
requests.
If the DMASUSP bit of the OPTIONS register is
set, while the ERROR and TLA flags are set, no
DMA transfer will be performed, allowing the re-
lavent interrupt routines to manage each condition
and, if necessary, disable the DMA transfer (Refer
to Section 0.1.6 DMA Features).
Each interrupt source has a pending bit in the
STATUS register, except the DMA interrupt sourc-
es that have the interrupt pending bits located in
the PRLR register.
These bits are set by hardware when the corre-
sponding interrupt event occurs. An interrupt re-
quest is performed only if the related mask bits are
set in the IMR register and the JBLPD has priority.
The pending bits have to be reset by the user soft-
ware. Note that until the pending bits are set (while
the corresponding mask bits are set), the JBLPD
processes interrupt requests. So, if at the end of
an interrupt routine the related pending bit is not
reset, another interrupt request is performed.
To reset the pending bits, different actions have to
be done, depending on each bit: see the descrip-
tion of the STATUS and PRLR registers.
Table 49. JBLPD internal priority levels
Priority Level Interrupt Source
Higher
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
Lower
The user can program the most significant bits of
the interrupt vectors by writing the V[7:3] bits of the
IVR register. Starting from the value stored by the
user, the JBLPD sets the three least significant
bits of the IVR register to produce four interrupt
vectors that are associated with interrupt sources
as shown in Table 6.
Table 50. JBLPD interrupt vectors
Interrupt Vector
V[7:3] 000b
V[7:3] 010b
V[7:3] 100b
V[7:3] 110b
Interrupt Source
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.6 DMA Features
(odd address). They are pointed to by the DMA
Transaction Counter Pointer Register (RDCPR
register in receiving, TDCPR register in transmit-
ting) located in the JBLPD register page.
The JBLPD can use the ST9 on-chip Direct Mem-
ory Access (DMA) channels to provide high-speed
data transactions between the JBLPD and contig-
uous locations of Register File and Memory. The
transactions can occur from and toward the
JBLPD. The maximum number of transactions that
each DMA channel can perform is 222 with Regis-
ter File or 65536 with Memory. Control of the DMA
features is performed using registers located in the
JBLPD register page (IVR, PRLR, IMR, RDAPR,
RDCPR, TDAPR, TDCPR).
To select DMA transactions with the Register File,
the control bits RDCPR.RF/MEM in receiving
mode or TDCPR.RF/MEM in transmitting mode
must be set.
The transaction Counter Register must be initial-
ized with the number of DMA transfers to perform
and it will be decremented after each transaction.
The DMA Address Register must be initialized with
the starting address of the DMA table in the Regis-
ter File, and it is incremented after each transac-
tion. These two registers must be located between
addresses 00h and DFh of the Register File.
The priority level of the DMA features of the
JBLPD with respect to the other ST9 peripherals
and the CPU is the same as programmed in the
PRLR register for the interrupt sources. In the in-
ternal priority level order of the JBLPD, depending
on the value of the DMASUSP bit in the OPTIONS
register, the DMA may or may not have a higher
priority than the interrupt sources.
When the DMA occurs between JBLPD and Reg-
ister File, the TDAPR register (in transmission)
and the RDAPR register (in reception) are not
used.
Refer to the Interrupt and DMA chapters of the da-
tasheet for details on priority levels.
10.8.6.2 DMA between JBLPD and Memory
Space
The DMA features are enabled by setting the ap-
propriate enabling bits (RXD_M, TXD_M) in the
IMR register. It is also possible to select the direc-
tion of the DMA transactions.
If the DMA transaction is made between the
JBLPD and Memory, a register pair is required to
hold the DMA Address and another register pair to
hold the DMA Transaction counter. These two
pairs of registers must be located in the Register
File. The DMA Address pair is pointed to by the
DMA Address Pointer Registers (RDAPR register
in reception, TDAPR register in transmission) lo-
cated in the JBLPD register page; the DMA Trans-
action Counter pair is pointed to by the DMA
Transaction Counter Pointer Registers (RDCPR
register in reception, TDCPR register in transmis-
sion) located in the JBLPD register page.
Once the DMA table is completed (the transaction
counter reaches 0 value), an interrupt request to
the CPU is generated if the related mask bit is set
(RDRF_M bit in reception, TRDY_M bit in trans-
mission). This kind of interrupt is called “End Of
Block”. The peripheral sends two different “End Of
Block” interrupts depending on the direction of the
DMA (Receiving End Of Block (REOB) - Transmit-
ting End Of Block (TEOB)). These interrupt sourc-
es have dedicated interrupt pending bits in the
PRLR register (REOBP, TEOBP) and they are
mapped to the same interrupt vectors: “Receive
Data Register Full (RDRF)” and “Transmit Ready
(TRDY)” respectively. The same correspondence
exists for the internal priority between interrupts
and interrupt vectors.
To select DMA transactions with Memory Space,
the control bits RDCPR.RF/MEM in receiving
mode or TDCPR.RF/MEM in transmitting mode
must be reset.
The Transaction Counter register pair must be ini-
tialized with the number of DMA transfers to per-
form and it will be decremented after each transac-
tion. The DMA Address register pair must be ini-
tialized with the starting address of the DMA table
in Memory Space, and it is incremented after each
transaction. These two register pairs must be lo-
cated between addresses 00h and DFh of the
Register File.
10.8.6.1 DMA between JBLPD and Register File
If the DMA transaction is made between the
JBLPD and the Register File, one register is re-
quired to hold the DMA Address and one to hold
the DMA transaction counter. These two registers
must be located in the Register File: the DMA Ad-
dress Register in an even addressed register, the
DMA Transaction Counter in the following register
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.6.3 DMA Management in Reception Mode
through the DMA Address Register (or Register
pair);
The DMA in reception is performed when the
RDRF bit of the STATUS register is set (by hard-
ware). The RDRF bit is reset as soon as the DMA
cycle is finished.
To enable the DMA feature, the RXD_M bit of the
IMR register must be set (by software).
– A post-increment of the DMA Address Register
(or Register pair);
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
Each DMA request performs the transfer of a sin-
gle byte from the RXDATA register of the peripher-
al toward Register File or Memory Space (Figure
10).
Note: When the REOBP pending bit is set (at the
end of the last DMA transfer), the reception DMA
enable bit (RXD_M) is automatically reset by hard-
ware. However, the DMA can be disabled by soft-
ware resetting the RXD_M bit.
Each DMA transfer consists of three operations
that are performed with minimum use of CPU time:
Note: The DMA request acknowledge could de-
pend on the priority level stored in the PRLR regis-
ter.
– A load from the JBLPD data register (RXDATA)
to a location of Register File/Memory addressed
Figure 118. DMA in Reception Mode
Register File
or
Memory space
Previous data
Data received
RXDATA
Current
Address
Pointer
JBLPD peripheral
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.6.4 DMA Management in Transmission
Mode
Register pair); it is the next location in the TXDA-
TA transfer cycle;
DMA in transmission is performed when the TRDY
bit of the STATUS register is set (by hardware).
The TRDY bit is reset as soon as the DMA cycle is
finished.
To enable the DMA feature, the TXD_M bit in the
IMR register must be set (by software).
– A post-increment of the DMA Address Register
(or Register pair);
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
Note: When the TEOBP pending bit is set (at the
end of the last DMA transfer), the transmission
DMA enable bit (TXD_M) is automatically reset by
hardware. However, the DMA can be disabled by
software resetting the TXD_M bit.
Compared to reception, in transmission each DMA
request performs the transfer of either a single
byte or a couple of bytes depending on the value
of the Transmit Opcode bits (TXOP.OP[2:0]) writ-
ten during the DMA transfer.
The table of values managed by the DMA must be
a sequence of opcode bytes (that will be written in
the TXOP register by the DMA) each one followed
by a data byte (that will be written in the TXDATA
register by the DMA) if the opcode needs it (see
Figure 11).
Note: When using DMA, the TXOP byte is written
before the TXDATA register. This order is accept-
ed by the JBLPD only when the DMA in transmis-
sion is enabled.
Note: The DMA request acknowledge could de-
pend on the priority level stored in the PRLR regis-
ter. In the same way, some time can occur be-
tween the transfer of the first byte and the transfer
of the second one if another interrupt or DMA re-
quest with higher priority occurs.
Each DMA cycle consists of the following transfers
for a total of three/six operations that are per-
formed with minimum use of CPU time:
– A load to the JBLPD Transmit Opcode register
(TXOP) from a location of Register File/Memory
addressed through the DMA Address Register
(or Register pair);
10.8.6.5 DMA Suspend mode
In the JBLPD it is possible to suspend or not to
suspend the DMA transfer while some J1850 pro-
tocol events occur. The selection between the two
modes is done by programming the DMASUSP bit
of the OPTIONS register.
If the DMASUSP bit is set (DMA suspended
mode), while the ERROR or TLA flag is set, the
DMA transfers are suspended, to allow the user
program to handle the event condition.
– A post-increment of the DMA Address Register
(or Register pair);
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed;
and if the Transmit Opcode placed in TXOP re-
quires a datum:
– A load to the peripheral data register (TXDATA)
from a location of Register File/Memory ad-
dressed through the DMA Address Register (or
If the DMASUSP bit is reset (DMA not suspended
mode), the previous flags have no effect on the
DMA transfers.
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 119. DMA in Transmission Mode
Register File
or
Memory space
Previous Opcode sent
(data not required)
Previous Opcode sent
(data required)
Previous Data sent
Opcode sent
(data required)
1st byte
2nd byte
Data sent
TXOP
Opcode
(data not required)
TXDATA
Opcode
(data required)
Data
JBLPD peripheral
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.7 Register Description
The JBLPD peripheral uses 48 registers that are
mapped in a single page of the ST9 register file.
register (OPTIONS) are used to select the current
sub-page. See Section 0.1.7.2 Stacked Registers
section for a detailed description of these regis-
ters.
Twelve registers are mapped from R240 (F0h) to
R251 (FBh): these registers are usually used to
control the JBLPD. See Section 0.1.7.1 Un-
Stacked Registers for a detailed description of
these registers.
The ST9 Register File page used is 23 (17h).
NOTE: Bits marked as “Reserved” should be left at
their reset value to guarantee software compatibil-
ity with future versions of the JBLPD.
Thirty-six registers are mapped from R252 (FCh)
to R255 (FFh). This is obtained by creating 9 sub-
pages, each containing 4 registers, mapped in the
same register addresses; 4 bits (RSEL[3:0]) of a
Figure 120. JBLPD Register Map
R240 (F0h) STATUS
R241 (F1h) TXDATA
R242 (F2h) RXDATA
TXOP
R243 (F3h)
R244 (F4h) CLKSEL
R245 (F5h) CONTROL
R246 (F6h) PADDR
R247 (F7h) ERROR
R248 (F8h) IVR
FREG28
FREG24FREG29
R249 (F9h) PRLR
R250 (FAh) IMR
R251 (FBh) OPTIONS
FREG20FREG25FREG30
FREG16FREG21FREG26FREG31
FREG12FREG17FREG22FREG27
FREG8 FREG13FREG18FREG23
FREG4 FREG9 FREG14FREG19
FREG0 FREG5 FREG10FREG15
R252 (FCh) CREG0
R253 (FDh) CREG1
R254 (FEh) CREG2
R255 (FFh) CREG3
RDAPR
RDCPR
TDAPR
TDCPR
FREG1 FREG6 FREG11
FREG2 FREG7
FREG3
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.7.1 Un-Stacked Registers
frame will not be cancelled for these errors, so
TRDY would not get set.
STATUS REGISTER (STATUS)
R240 - Read/Write
Register Page: 23
– An RBRK error condition cancels all transmits for
this frame or any successive frames, so the
TRDY bit will always be immediately set on an
RBRK condition.
Reset Value: 0100 0000 (40h)
7
0
TRDY is set on reset or while CONTROL.JE is re-
set, or while the CONTROL.JDIS bit is set.
If the TRDY_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: TXOP register not ready to receive a new op-
code
ERR TRDY RDRF TLA
RDT EODM EOFM IDLE
The bits of this register indicate the status of the
JBLPD peripheral.
This register is forced to its reset value after the
MCU reset and while the CONTROL.JDIS bit is
set. While the CONTROL.JE bit is reset, all bits ex-
cept IDLE are forced to their reset values.
1: TXOP register ready to receive a new opcode
Bit 5 = RDRF Receive Data Register Full Flag.
RDRF is set when a complete data byte has been
received and transferred from the serial shift regis-
ter to the RXDATA register.
RDRF is cleared when the RXDATA register is
read (by software or by DMA). RDRF is also
cleared on reset or while CONTROL.JE is reset, or
while CONTROL.JDIS bit is set.
If the RDRF_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: RXDATA register doesn’t contain a new data
1: RXDATA register contains a new data
Bit 7 = ERR Error Flag.
The ERR bit indicates that one or more bits in the
ERROR register have been set. As long as any bit
in the ERROR register remains set, the ERR bit re-
mains set. When all the bits in the ERROR register
are cleared, then the ERR bit is reset by hardware.
The ERR bit is also cleared on reset or while the
CONTROL.JE bit is reset, or while the CON-
TROL.JDIS bit is set.
If the ERR_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: No error
Bit 4 = TLA Transmitter Lost Arbitration.
1: One or more errors have occurred
The TLA bit gets set when the transmitter loses ar-
bitration while transmitting messages or type 1
and 3 IFRs. Lost arbitration for a type 2 IFR does
not set the TLA bit. (Type 2 messages require re-
tries of the physical address if the arbitration is lost
until the frame length is reached (if NFL=0)). The
TLA bit gets set when, while transmitting a MSG,
MSG+CRC, IFR1, IFR3, or IFR3+CRC, the decod-
ed VPWI data bit symbol received does not match
the VPWO data bit symbol that the JBLPD is at-
tempting to send out. If arbitration is lost, the
VPWO line is switched to its passive state and
nothing further is transmitted until an end-of-data
(EOD) symbol is detected on the VPWI line. Also,
any queued transmit opcode scheduled for trans-
mission during this frame is cancelled (but the
TRA bit is not set).
Bit 6 = TRDY Transmit Ready Flag.
The TRDY bit indicates that the TXOP register is
ready to accept another opcode for transmission.
The TRDY bit is set when the TXOP register is
empty and it is cleared whenever the TXOP regis-
ter is written (by software or by DMA). TRDY will
be set again when the transmit state machine ac-
cepts the opcode for transmission.
When attempting to transmit a data byte without
using DMA, two writes are required: first a write to
TXDATA, then a write to the TXOP.
– If a byte is written into the TXOP which results in
TRA getting set, then the TRDY bit will immedi-
ately be set.
The TLA bit can be cleared by software writing a
logic “zero” in the TLA position. TLA is also cleared
on reset or while CONTROL.JE is reset, or while
CONTROL.JDIS bit is set.
If the TLA_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
– If a TLA occurs and the opcode for which TRDY
is low is scheduled for this frame, then TRDY will
go high, if the opcode is scheduled for the next
frame, then TRDY will stay low.
– If an IBD, IFD or CRCE error condition occurs,
then TRDY will be set and any queued transmit
opcode scheduled to transmit in the present
frame will be cancelled by the JBLPD peripheral.
A MSGx opcode scheduled to be sent in the next
0: The JBLPD doesn’t lose arbitration
1: The JBLPD loses arbitration
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 3 = RDT Receive Data Type.
The RDT bit indicates the type of data which is in
the RXDATA register: message byte or IFR byte.
Any byte received after an SOF but before an
EODM is considered a message byte type. Any
byte received after an SOF, EODM and NBx is an
IFR type.
RDT gets set or cleared at the same time that
RDRF gets set.
RDT is cleared on reset or while CONTROL.JE is
reset, or while CONTROL.JDIS bit is set.
0: Last RXDATA byte was a message type byte
1: Last RXDATA byte was a IRF type byte
Bit 0 = IDLE Idle Bus Flag
IDLE is set when the JBLPD decoded VPWI pin
recognized an IFS symbol. That is, an idle bus is
when the bus has been in a passive state for long-
er that the Tv6 symbol time. The IDLE flag will re-
main set as long as the decoded VPWI pin is pas-
sive. IDLE is cleared when the decoded VPWI pin
transitions to an active state.
Note that if the VPWI pin remains in a passive
state after JE is set, then the IDLE bit may go high
sometime before a Tv6 symbol is timed on VPWI
(since VPWI timers may be active when JE is
clear).
IDLE is cleared on reset or while the CON-
TROL.JDIS bit is set.
0: J1850 bus not in idle state
1: J1850 bus in idle state
Bit 2 = EODM End of Data Minimum Flag.
The EODM flag is set when the JBLPD decoded
VPWI pin has been in a passive state for longer
that the minimum Tv3 symbol time unless the
EODM is inhibited by a sleep, filter or CRCE, IBD,
IFD or RBRK error condition during a frame.
EODM bit does not get set when in the sleep mode
or when a message is filtered.
The EODM bit can be cleared by software writing a
logic “zero” in the EODM position. EODM is
cleared on reset, while CONTROL.JE is reset or
while CONTROL.JDIS bit is set.
JBLPD TRANSMIT DATA REGISTER (TXDATA)
R241- Read/Write
Register Page: 23
Reset Value: xxxx xxxx (xxh)
7
0
TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0
If the EODM_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: No EOD symbol detected
The TXDATA register is an eight bits read/write
register in which the data to be transmitted must
be placed. A write to TXDATA merely enters a
byte into the register. To initiate an attempt to
transmit the data, the TXOP register must also be
written. When the TXOP write occurs, the TRDY
flag is cleared. While the TRDY bit is clear, the
data is still in the TXDATA register, so writes to the
TXDATA register with TRDY clear will overwrite
existing TXDATA. When the TXDATA is trans-
ferred to the shift register, the TRDY bit is set
again.
1: EOD symbol detected
Note: The EODM bit is not an error flag. It means
that the minimum time related to the passive Tv3
symbol is passed.
Bit 1 = EOFM End of Frame Minimum Flag.
The EOFM flag is set when the JBLPD decoded
VPWI pin has been in a passive state for longer
that the minimum Tv4 symbol time. EOFM will still
get set at the end of filtered frames or frames
where sleep mode was invoked. Consequently,
multiple EOFM flags may be encountered be-
tween frames of interest.
The EOFM bit can be cleared by software writing a
logic “zero” in the EOFM position. EOFM is
cleared on reset, while CONTROL.JE is reset or
while CONTROL.JDIS bit is set.
Reads of the TXDATA register will always return
the last byte written.
TXDATA contents are undefined after a reset.
Note: The correct sequence to transmit is to write
first the TXDATA register (if datum is needed) and
then the TXOP one.
Only using the DMA, the correct sequence of writ-
ing operations is first the TXOP register and then
the TXDATA one (if needed).
If the EOFM_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: No EOF symbol detected
1: EOF symbol detected
Note: The EOFM bit is not an error flag. It means
that the minimum time related to the passive Tv4
symbol is passed.
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD RECEIVE DATA REGISTER (RXDATA)
R242- Read only
Register Page: 23
a byte. A write to the TXOP triggers the state ma-
chine to initialize an attempt to serially transmit a
byte out on the VPWO pin. An opcode which trig-
gers a message byte or IFR type 3 to be sent will
transfer the TXDATA register contents to the
transmit serial shift register. An opcode which trig-
gers a message byte or IFR type 3 to be sent with
a CRC appended will transfer the TXDATA regis-
ter contents to the transmit serial shift register and
subsequently the computed CRC byte. An opcode
which triggers an IFR type 1 or 2 to be sent will
transfer the PADDR register contents to the trans-
mit serial shift register. If a TXOP opcode is written
which is invalid for the bus conditions at the time
(e.g. 12 byte frame or IFR3ing an IFR2), then no
transmit attempt is tried and the TRA bit in the ER-
ROR register is set.
Transmission of a string of data bytes requires
multiple TXDATA/TXOP write sequences. Each
write combination should be accomplished while
the TRDY flag is set. However, writes to the TXOP
when TRDY is not set will be accepted by the state
machine, but it may override the previous data and
opcode.
Under normal message transmission conditions
the MSG opcode is written. If the last data byte of
a string is to be sent, then the MSG+CRC opcode
will be written. An IFRx opcode is written if a re-
sponse byte or bytes to a received message (i.e.
bytes received in RXDATA with RDT=0) is wanted
to transmit. The Message Length Count bits
(MLC[3:0]) may be used to require that the IFR be
enabled only if the correct number of message
bytes has been received.
Reset Value: xxxx xxxx (xxh)
7
0
RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0
The RXDATA register is an 8-bit read only register
in which the data received from VPWI is stored.
VPWI data is transferred from the input VPW de-
coder to a serial shift register unless it is inhibited
by sleep mode, filter mode or an error condition
(IBD, IFD, CRCE, RBRK) during a frame. When
the shift register is full, this data is transferred to
the RXDATA register, and the RDRF flag gets set.
All received data bytes are transferred to RXDATA
including CRC bytes. A read of the RXDATA reg-
ister will clear the RDRF flag.
Note that care must be taken when reading RXDA-
TA subsequent to an RDRF flag. Multiple reads of
RXDATA after an RDRF should only be attempted
if the user can be sure that another RDRF will not
occur by the time the read takes place.
RXDATA content is undefined after a reset.
JBLPD TRANSMIT OPCODE REGISTER
(TXOP)
R243 - Read/Write
Register Page: 23
Reset Value: 0000 0000 (00h)
7
0
NOTE: The correct sequence to transmit is to write
first the TXDATA register and then the TXOP one.
Only using the DMA, the correct sequence of writ-
ing operations is first the TXOP register and then
the TXDATA one (if needed).
MLC3 MLC2 MLC1 MLC0
-
OP2
OP1
OP0
TXOP is an 8-bit read/write register which contains
the instructions required by the JBLPD to transmit
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 7:4 = MLC[3:0] Message Length Count.
Message Length Count bits 3 to 0 are written when
the program writes one of the IFR opcodes. Upon
detection of the EOD symbol which delineates the
body of a frame from the IFR portion of the frame,
the received byte counter is compared against the
count contained in MLC[3:0]. If they match, then
the IFR will be transmitted. If they do not match,
then the TRA bit in the ERROR register is set and
no transmit attempt occurs.
MSG, Message Byte Opcode.
The Message byte opcode is set when the user
program wants to initiate or continue transmitting
the body of a message out the VPWO pin.
The body of a message is the string of data bytes
following an SOF symbol, but before the first EOD
symbol in a frame. If the J1850 bus is in an idle
condition when the opcode is written, an SOF
symbol is transmitted out the VPWO pin immedi-
ately before it transmits the data contained in TX-
DATA. If the JBLPD is not in idle and the J1850
transmitter has not been locked out by loss of arbi-
tration, then the TXDATA byte is transferred to the
serial output shift register for transmission immedi-
ately on completion of any previously transmitted
data. The final byte of a message string is not
transmitted using the MSG opcode (use the
MSG+CRC opcode).
– While NFL=0, an MCL[3:0] decimal value be-
tween 1 and 11 is considered valid. MCL[3:0] val-
ues of 12, 13, 14, 15 are considered invalid and
will set the Transmit Request Aborted (TRA) bit
in the ERROR register.
– While NFL=1, an MCL[3:0] value between 1 and
15 is considered valid.
– For NFL=1 or 0, MCL[3:0] bits are don’t care dur-
ing a MSG or MSG+CRC opcode write.
Special Conditions for MSG Transmit:
– 1) A MSG cannot be queued on top of an execut-
ing IFR3 opcode. If so, then TRA is set, and
TDUF will get set because the transmit state ma-
chine will be expecting more data, then the in-
verted CRC is appended to this frame. Also, no
message byte will be sent on the next frame.
– If writing an IFR opcode and MCL[3:0]=0000,
then the message length count check is ignored
(i.e. MLC=Count is disabled), and the IFR is en-
abled only on a correct CRC and a valid EOD
symbol assuming no other error conditions (IFD,
IBD, RBRK) appear.
– 2) If NFL = 0 and an MSG queued without CRC
on Received Byte Count for this frame=10 will
trigger the TRA to get set, and TDUF will get set
because the state machine will be expecting
more data and the transmit machine will send the
inverted CRC after the byte which is presently
transmitting. Also, no message byte will be sent
on the next frame.
Bit 3 = Reserved.
Bit 2:0 = OP[2:0] Transmit Opcode Select Bits.
The bits OP[2:0] form the code that the transmitter
uses to perform a transmit sequence. The codes
are listed in Table 7.
Caution should be taken when TRA gets set in
these cases because the TDUF error sequence
may engage before the user program has a
chance to rewrite the TXOP register with the cor-
rect opcode. If a TDUF error occurs, a subsequent
MSG write to the TXOP register will be used as the
first byte of the next frame.
Table 51. Opcode definitions
OP[2:0]
Transmit opcode
Abbreviation
No operation or
Cancel
000
CANCEL
001
010
Send Break Symbol
Message Byte
SBRK
MSG
Message Byte then
append CRC
011
100
101
110
111
MSG+CRC
IFR1
In-Frame Response
Type 1
In-Frame Response
Type 2
IFR2
In-Frame Response
Type 3
IFR3
IFR Type 3 then ap-
pend CRC
IFR3+CRC
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
MSG+CRC, Message byte then append CRC op-
code.
The ‘Message byte with CRC’ opcode is set when
the user program wants to transmit a single byte
message followed by a CRC byte, or transmit the
final byte of a message string followed by a CRC
byte.
chance to rewrite the TXOP register with the cor-
rect opcode. If a TDUF error occurs, a subsequent
MSG+CRC write to the TXOP register will be used
as the first byte of the next frame.
IFR1, In-Frame Response Type 1 opcode.
The In-frame Response Type 1 (IFR 1) opcode is
written if the user program wants to transmit a
physical address byte (contained in the PADDR
register) in response to a message that is currently
being received.
The user program decides to set up an IFR1 upon
receiving a certain portion of the data byte string of
an incoming message. No write of the TXDATA
register is required. The IFR1 gets its data byte
from the PADDR register.
A single byte message is basically an SOF symbol
followed by a single data byte retrieved from TX-
DATA register followed by the computed CRC
byte followed by an EOD symbol. If the J1850 bus
is in idle condition when the opcode is written, an
SOF symbol is immediately transmitted out the
VPWO pin. It then transmits the byte contained in
the TXDATA register, then the computed CRC
byte is transmitted. VPWO is then set to a passive
state. If the J1850 bus is not idle and the J1850
transmitter has not been locked out by loss of arbi-
tration, then the TXDATA byte is transferred to the
serial output shift register for transmission immedi-
ately on completion of any previously transmitted
data. After completion of the TXDATA byte the
computed CRC byte is transferred out the VPWO
pin and then the VPWO pin is set passive to time
an EOD symbol.
The JBLPD block will enable the transmission of
the IFR1 on these conditions:
– 1) The CRC check is valid (otherwise the CRCE
is set)
– 2) The received message length is valid if ena-
bled (otherwise the TRA is set)
– 3) A valid EOD minimum symbol is received (oth-
erwise the IFD may eventually get set due to byte
synchronization errors)
Special Conditions for MSG+CRC Transmit:
– 4) If NFL = 0 & Received Byte Count for this
frame <=11 (otherwise TRA is set)
– 1) A MSG+CRC opcode cannot be queued on
top of an executing IFR3 opcode. If so, then TRA
is set, and TDUF will get set because the trans-
mit state machine will be expecting more data,
then the inverted CRC is appended to this frame.
Also, no message byte will be sent on the next
frame.
– 5) If not presently executing an MSG, IFR3, op-
code (otherwise TRA is set, and TDUF will get
set because the transmit state machine will be
expecting more data, so the inverted CRC will be
appended to this frame)
– 6) If not presently executing an IFR1, IFR2, or
IFR3+CRC opcode otherwise TRA is set (but no
TDUF)
– 2) If NFL=0, a MSG+CRC can only be queued if
Received Byte Count for this frame <=10 other-
wise the TRA will get set, and TDUF will get set
because the state machine will be expecting
more data, so the transmit machine will send the
inverted CRC after the byte which is presently
transmitting. Also, no message byte will be sent
on the next frame.
– 7) If not presently receiving an IFR portion of a
frame, otherwise TRA is set.
The IFR1 byte is then attempted according to the
procedure described in section “Transmitting a
type 1 IFR”. Note that if an IFR1 opcode is written,
a queued MSG or MSG+CRC is overridden by the
IFR1.
Caution should be taken when TRA gets set in
these cases because the TDUF error sequence
may engage before the user program has a
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
IFR2, In-Frame Response Type 2 opcode.
The In-frame Response Type 2 (IFR2) opcode is
set if the user program wants to transmit a physical
address byte (contained in the PADDR register) in
response to a message that is currently being re-
ceived.
The user program decides to set up an IFR2 upon
receiving a certain portion of the data byte string of
an incoming message. No write of the TXDATA
register is required. The IFR gets its data byte from
the PADDR register.
ceived.
The IFR3 uses the contents of the TXDATA regis-
ter for data. The user program decides to set up an
IFR3 upon receiving a certain portion of the data
byte string of an incoming message. A previous
write of the TXDATA register should have oc-
curred.
The JBLPD block will enable the transmission of
the first byte of an IFR3 string on these conditions:
– 1) The CRC check is valid (otherwise the CRCE
is set)
The JBLPD block will enable the transmission of
the IFR2 on these conditions:
– 2) The received message length is valid if ena-
bled (otherwise the TRA is set)
– 1) The CRC check is valid (otherwise the CRCE
is set)
– 3) A valid EOD minimum symbol is received (oth-
erwise the IFD may eventually get set due to byte
synchronization errors)
– 2) The received message length is valid if ena-
bled (otherwise the TRA is set)
– 4) If NFL = 0 & Received Byte Count for this
frame <=9 (otherwise TRA is set and inverted
CRC is transmitted due to TDUF)
– 3) A valid EOD minimum symbol is received (oth-
erwise the IFD may eventually get set due to byte
synchronization errors)
– 5) If not presently executing an MSG opcode
(otherwise TRA is set, and TDUF will get set be-
cause the transmit state machine will be expect-
ing more data and the inverted CRC will be
appended to this frame)
– 4) If NFL = 0 & Received Byte Count for this
frame <=11 (otherwise TRA is set)
– 5) If not presently executing an MSG, IFR3, op-
code (otherwise TRA is set, and TDUF will get
set because the transmit state machine will be
expecting more data, so the inverted CRC will be
appended to this frame)
– 6) If not presently executing an IFR1, IFR2, or
IFR3+CRC opcode, otherwise TRA is set (but no
TDUF)
– 6) If not presently executing an IFR1, IFR2, or
IFR3+CRC opcodes, otherwise TRA is set (but
no TDUF)
– 7) If not presently receiving an IFR portion of a
frame, otherwise TRA is set.
The IFR3 byte string is then attempted according
to the procedure described in section “Transmit-
ting a type 3 IFR”. Note that if an IFR3 opcode is
written, a queued MSG or MSG+CRC is overrid-
den by the IFR3.
– 7) If not presently receiving an IFR portion of a
frame, otherwise TRA is set.
The IFR byte is then attempted according to the
procedure described in section “Transmitting a
type 2 IFR”. Note that if an IFR opcode is written, a
queued MSG or MSG+CRC is overridden by the
IFR2.
The next byte(s) in the IFR3 data string shall also
be written with the IFR3 opcode except for the last
byte in the string which shall be written with the
IFR3+CRC opcode. Each IFR3 data byte trans-
mission is accomplished with a TXDATA/TXOP
write sequence. The succeeding IFR3 transmit re-
quests will be enabled on conditions 4 and 5 listed
above.
IFR3, In-Frame Response Type 3 opcode.
The In-Frame Response Type 3 (IFR3) opcode is
set if the user program wants to initiate to transmit
or continue to transmit a string of data bytes in re-
sponse to a message that is currently being re-
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
IFR3+CRC, In-Frame Response Type 3 then ap-
pend CRC opcode.
The IFR3 byte is attempted according to the pro-
cedure described in section “Transmitting a type 3
IFR”. The CRC byte is transmitted out on comple-
tion of the transmit of the IFR3 byte.
If this opcode sets up the last byte in an IFR3 data
string, then the TXDATA register contents shall be
transmitted out immediately upon completion of
the previous IFR3 data byte followed by the trans-
mit of the CRC byte. In this case the IFR3+CRC is
enabled on conditions 4 and 5 listed above. Note
that if an IFR3+CRC opcode is written, a queued
MSG or MSG+CRC is overridden by the
IFR3+CRC.
The In-frame Response Type 3 then append CRC
opcode (IFR3+CRC) is set if the user program
wants to either initiate to transmit a single data
byte IFR3 followed by a CRC, or transmit the last
data byte of an IFR3 string followed by the CRC
byte in response to a message that is currently be-
ing received.
The IFR3+CRC opcode transmits the contents of
the TXDATA register followed by the computed
CRC byte. The user program decides to set up an
IFR3 upon receiving a certain portion of the data
byte string of an incoming message. A previous
write of the TXDATA register should have oc-
curred.
SBRK, Send Break Symbol.
The SBRK opcode is written to transmit a nominal
break (BRK) symbol out the VPWO pin. A Break
symbol can be initiated at any time. Once the
SBRK opcode is written a BRK symbol of the nom-
inal Tv5 duration will be transmitted out the VPWO
pin immediately. To terminate the transmission of
an in-progress break symbol the JE bit should be
set to a logic zero. An SBRK command is non-
maskable, it will override any present transmit op-
eration, and it does not wait for the present trans-
mit to complete. Note that in the 4X mode a SBRK
will send a break character for the nominal Tv5
time times four (4 x Tv5) so that all nodes on the
bus will recognize the break. A CANCEL opcode
does not override a SBRK command.
The J1850 block will enable the transmission of
the first byte of an IFR3 string on these conditions:
– 1) The CRC check is valid (otherwise the CRCE
is set)
– 2) The received message length is valid if ena-
bled (otherwise the TRA is set)
– 3) A valid EOD minimum symbol is received (oth-
erwise the IFD may eventually get set due to byte
synchronization errors)
– 4) If NFL = 0 & Received Byte Count for this
frame <=10 (otherwise TRA is set and inverted
CRC is transmitted)
CANCEL, No Operation or Cancel Pending Trans-
mit.
– 5) If not presently executing an MSG opcode
(otherwise TRA is set, and TDUF will get set be-
cause the transmit state machine will be expect-
ing more data and the inverted CRC will be
appended to this frame)
The Cancel opcode is used by the user program to
tell the J1850 transmitter that a previously queued
opcode should not be transmitted. The Cancel op-
code will set the TRDY bit. If the JBLPD peripheral
is presently not transmitting, the Cancel command
effectively cancels a pending MSGx or IFRx op-
code if one was queued, or it does nothing if no
opcode was queued. If the JBLPD peripheral is
presently transmitting, then a queued MSGx or
IFRx opcode is aborted and the TDUF circuit may
take affect.
– 6) If not presently executing an IFR1, IFR2 or
IFR3+CRC opcodes, otherwise TRA is set (but
no TDUF)
– 7) If not presently receiving an IFR portion of a
frame, otherwise TRA is set.
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD SYSTEM FREQUENCY SELECTION
REGISTER (CLKSEL)
rect value must be written in the register. So an in-
ternal frequency less than 1MHz is not allowed.
R244- Read/Write
Register Page: 23
Reset Value: 0000 0000 (00h)
Note: If the MCU internal clock frequency is lower
than 1MHz, the peripheral is not able to work cor-
rectly. If a frequency lower than 1MHz is used, the
user program must disable the peripheral.
7
0
Note: When the clock prescaler factor or the MCU
internal frequency is changed, the peripheral could
lose the synchronization with the J1850 bus.
4X
-
FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0
Bit 7 = 4X Diagnostic Four Times Mode.
This bit is set when the J1850 clock rate is chosen
four times faster than the standard requests, to
force the BREAK symbol (nominally 300 µs long)
and the Transmitter Timeout Time (nominally 1
ms) at their nominal durations.
JBLPD CONTROL REGISTER (CONTROL)
R245- Read/Write
Register Page: 23
Reset Value: 0100 0000 (40h)
7
0
When the user want to use a 4 times faster J1850
clock rate, the new prescaler factor should be
stored in the FREQ[5:0] bits and the 4X bit must be
set with the same instruction. In the same way, to
exit from the mode, FREQ[5:0] and 4X bits must
be placed at the previous value with the same in-
struction.
JE
JDIS
NFL JDLY4 JDLY3 JDLY2 JDLY1 JDLY0
The CONTROL register is an eight bit read/write
register which contains JBLPD control information.
Reads of this register return the last written data.
0: Diagnostic Four Times Mode disabled
1: Diagnostic Four Times Mode enabled
Bit 7 = JE JBLPD Enable.
Note: Setting this bit, the prescaler factor is not au-
tomatically divided by four. The user must adapt
the value stored in FREQ[5:0] bits by software.
The JBLPD block enable bit (JE) enables and dis-
ables the transmitter and receiver to the VPWO
and VPWI pins respectively. When the JBLPD pe-
ripheral is disabled the VPWO pin is in its passive
state and information coming in the VPWI pin is ig-
nored. When the JBLPD block is enabled, the
transmitter and receiver function normally. Note
that queued transmits are aborted when JE is
cleared. JE is cleared on reset, by software and
setting the JDIS bit.
Note: The customer should take care using this
mode when the MCU internal frequency is less
than 4MHz.
Bit 6 = Reserved.
0: The peripheral is disabled
1: The peripheral is enabled
Bit 5:0 = FREQ[5:0] Internal Frequency Selectors.
These 6 bits must be programmed depending on
the internal frequency of the device. The formula
that must be used is the following one:
Note: It is not possible to reset the JDIS bit and to
set the JE bit with the same instruction. The cor-
rect sequence is to first reset the JDIS bit and then
set the JE bit with another instruction.
MCU Int. Freq.= 1MHz * (FREQ[5:0] + 1).
Note: To obtain a correct operation of the periph-
eral, the internal frequency of the MCU (INTCLK)
must be an integer multiple of 1MHz and the cor-
266/324
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 6 = JDIS Peripheral clock frozen.
When this bit is set by software, the peripheral is
stopped and the bus is not decoded anymore. A
reset of the bit restarts the internal state machines
as after a MCU reset. The JDIS bit is set on MCU
reset.
Bit 4:0 = JDLY[4:0] JBLPD Transceiver External
Loop Delay Selector.
These five bits are used to select the nominal ex-
ternal loop time delay which normally occurs when
the peripheral is connected and transmitting in a
J1850 bus system. The external loop delay is de-
fined as the time between when the VPWO is set
to a certain level to when the VPWI recognizes the
corresponding (inverted) edge on its input. Refer
to “Transmit Opcode Queuing” section and the
SAE-J1850 standard for information on how the
external loop delay is used in timing transmitted
symbols.
0: The peripheral clock is running
1: The peripheral clock is stopped
Note: When the JDIS bit is set, the STATUS reg-
ister, the ERROR register, the IMR register and
the TEOBP and REOBP bits of the PRLR register
are forced into their reset value.
Note: It is not possible to reset the JDIS bit and to
set the JE bit with the same instruction. The cor-
rect sequence is to first reset the JDIS bit and then
set the JE bit with another instruction.
The allowed values are integer values between 0
µs and 31 µs.
JBLPD PHYSICAL ADDRESS REGISTER
(PADDR)
R246- Read/Write
Bit 5 = NFL No Frame Length Check
The NFL bit is used to enable/disable the J1850
requirement of 12 bytes maximum per frame limit.
The SAE J1850 standard states that a maximum
of 12 bytes (including CRCs and IFRs) can be on
the J1850 between a start of frame symbol (SOF)
and an end of frame symbol (EOF). If this condi-
tion is violated, then the JBLPD peripheral gets an
Invalid Frame Detect (IFD) and the sleep mode
ensues until a valid EOFM is detected. If the valid
frame check is disabled (NFL=1), then no limits
are imposed on the number of data bytes which
can be sent or received on the bus between an
SOF and an EOF. The default upon reset is for the
frame checking to be enabled.
Register Page: 23
Reset Value: xxxx xxxx (xxh)
7
0
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
The PADDR is an eight bit read/write register
which contains the physical address of the JBLPD
peripheral. During initialization the user program
will write the PADDR register with its physical ad-
dress. The Physical Address is used during in-
frame response types 1 and 2 to acknowledge the
receipt of a message. The JBLPD peripheral will
transmit the contents of the PADDR register for
type 1 or 2 IFRs as defined by the TXOP register.
This register is undefined on reset.
The NFL bit is cleared on reset
0: Twelve bytes frame length check enabled
1: Twelve bytes frame length check disabled
267/324
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD ERROR REGISTER (ERROR)
R247- Read only
Register Page: 23
is set, then the TTO will timeout at 4000 prescaled
clock cycles. When the TTO flag is set then the di-
agnostic circuit will disable the VPWO signal, and
disable the JBLPD peripheral. The user program
must then clear the JE bit to remove the TTO error.
It can then retry the block by setting the JE bit
again.
Reset Value: 0000 0000 (00h)
7
0
TTO TDUF RDOF TRA RBRK CRCE
IFD
IBD
The TTO bit can be used to determine if the exter-
nal J1850 bus is shorted low. Since the transmitter
looks for proper edges returned at the VPWI pin
for its timing, a lack of edges seen at VPWI when
trying to transmit (assuming the RBRK does not
get set) would indicate a constant low condition.
The user program can take appropriate actions to
test the J1850 bus circuit when a TTO occurs.
Note that a transmit attempt must occur to detect a
bus shorted low condition.
ERROR is an eight bit read only register indicating
error conditions that may arise on the VPWO and
VPWI pins. A read of the ERROR register clears
all bits (except for TTO and possibly the RBRK bit)
which were set at the time of the read. The register
is cleared after the MCU reset, while the CON-
TROL.JE bit is reset, or while the CONTROL.JDIS
bit is set.
The TTO bit is cleared while the CONTROL.JE bit
is reset or while the CONTROL.JDIS bit is set.
TTO is cleared on reset.
0: VPWO line at 1 for less than 1 ms
1: VPWO line at 1 for longer than 1 ms
All error conditions that can be read in the ERROR
register need to have redundant ERROR indicator
flags because:
– With JE set, the TDUF, RDOF, TRA, CRCE, IFD,
& IBD bits in the ERROR register can only be
cleared by reading the register.
Bit 6 = TDUF Transmitter Data Underflow.
The TDUF will be set to a logic one if the transmit-
ter expects more information to be transmitted, but
a TXOP write has not occurred in time (by the end
of transmission of the last bit).
– The TTO bit can only be cleared by clearing the
JE bit.
– The RBRK bit can only be cleared by reading the
ERROR register after the break condition has
disappeared.
The transmitter knows to expect more information
from the user program when transmitting messag-
es or type 3 IFRs only. If an opcode is written to
TXOP that does not include appending a CRC
byte, then the JBLPD peripheral assumes more
data is to be written. When the JBLPD peripheral
has shifted out the data byte it must have the next
data byte in time to place it directly next to it. If the
user program does not place new data in the TX-
DATA register and write the TXOP register with a
proper opcode, then the CRC byte which is being
kept tabulated by the transmitter is logically invert-
ed and transmitted out the VPWO pin. This will en-
sure that listeners will detect this message as an
error. In this case the TDUF bit is set to a logic
one.
Error condition indicator flags associated with the
error condition are cleared when the error condi-
tion ends. Since error conditions may alter the ac-
tions of the transmitter and receiver, the error con-
dition indicators must remain set throughout the
error condition. All error conditions, including the
RBRK condition, are events that get set during a
particular clock cycle of the prescaled clock of the
peripheral. The IFD, IBD, RBRK, and CRCE error
conditions are then cleared when a valid EOF
symbol is detected from the VPWI pin. The TRA
error condition is a singular event that sets the cor-
responding ERROR register bit, but this error itself
causes no other actions.
TDUF is cleared by reading the ERROR register
with TDUF set. TDUF is also cleared on reset,
while the CONTROL.JE bit is reset or while the
CONTROL.JDIS bit is set.
0: No transmitter data underflow condition oc-
curred
Bit 7 = TTO Transmitter Timeout Flag
The TTO bit is set when the VPWO pin has been in
a logic one (or active) state for longer than 1 ms.
This flag is the output of a diagnostic circuit based
on the prescaled system clock input. If the 4X bit is
not set, the TTO will trip if the VPWO is constantly
active for 1000 prescaled clock cycles. If the 4X bit
1: Transmitter data underflow condition occurred
268/324
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 5 = RDOF Receiver Data Overflow
The RDOF gets set to a logic one if the data in the
RXDATA register has not been read and new data
is ready to be transferred to the RXDATA register.
The old RXDATA information is lost since it is
overwritten with new data.
RDOF is cleared by reading the ERROR register
with RDOF set, while the CONTROL.JE bit is reset
or while the CONTROL.JDIS bit is set, or on reset.
0: No receiver data overflow condition occurred
1: Receiver data overflow condition occurred
0: No valid Break symbol received
1: Valid Break symbol received
Bit 2 = CRCE Cyclic Redundancy Check Error
The receiver section always keeps a running tab of
the CRC of all data bytes received from the VPWl
since the last EOD symbol. The CRC check is per-
formed when a valid EOD symbol is received both
after a message string (subsequent to an SOF
symbol) and after an IFR3 string (subsequent to
an NB0 symbol). If the received CRC check fails,
then the CRCE bit is set to a logic one. CRC errors
are inhibited if the JBLPD peripheral is in the
“sleep or filter and NOT presently transmitting”
mode. A CRC error occurs once for a frame. After-
wards, the receiver is disabled until an EOFM
symbol is received and queued transmits for the
present frame are cancelled (but the TRA bit is not
set). CRCE is cleared when ERROR is read. It is
also cleared while the CONTROL.JE bit is reset or
while the CONTROL.JDIS bit is set, or on reset.
0: No CRC error detected
Bit 4 = TRA Transmit Request Aborted
The TRA gets set to a logic one if a transmit op-
code is aborted by the JBLPD state machine.
Many conditions may cause a TRA. They are ex-
plained in the transmit opcode section. If the TRA
bit gets set after a TXOP write, then a transmit is
not attempted, and the TRDY bit is not cleared.
If a TRA error condition occurs, then the requested
transmit is aborted, and the JBLPD peripheral
takes appropriate measures as described under
the TXOP register section.
1: CRC error detected
TRA is cleared on reset, while the CONTROL.JE
bit is reset or while the CONTROL.JDIS bit is set.
0: No transmission request aborted
Bit 1 = IFD Invalid Frame Detect
The IFD bit gets set when the following conditions
are detected from the filtered VPWI pin:
1: Transmission request aborted
Bit 3 = RBRK Received Break Symbol Flag
The RBRK gets set to a logic one if a valid break
(BRK) symbol is detected from the filtered VPWI
pin. A Break received from the J1850 bus will can-
cel queued transmits of all types. The RBRK bit re-
mains set as long as the break character is detect-
ed from the VPWI. Reads of the ERROR register
will not clear the RBRK bit as long as a break char-
acter is being received. Once the break character
is gone, a final read of the ERROR register clears
this bit.
An RBRK error occurs once for a frame if it is re-
ceived during a frame. Afterwards, the receiver is
disabled from receiving information (other than the
break) until an EOFM symbol is received.
RBRK bit is cleared on reset, while the CON-
TROL.JE bit is reset or while the CONTROL.JDIS
bit is set.
The RBRK bit can be used to detect J1850 bus
shorted high conditions. If RBRK is read as a logic
high multiple times before an EOFM occurs, then a
possible bus shorted high condition exists. The
user program can take appropriate measures to
test the bus if this condition occurs. Note that this
bit does not necessarily clear when ERROR is
read.
– An SOF symbol is received after an EOD mini-
mum, but before an EOF minimum.
– An SOF symbol is received when expecting data
bits.
– If NFL = 0 and a message frame greater than 12
bytes (i.e. 12 bytes plus one bit) has been re-
ceived in one frame.
– An EOD minimum time has elapsed when data
bits are expected.
– A logic 0 or 1 symbol is received (active for Tv1
or Tv2) when an SOF was expected.
– The second EODM symbol received in a frame
is NOT followed directly by an EOFM symbol.
IFD errors are inhibited if the JBLPD peripheral is
in the “sleep or filter and NOT presently transmit-
ting” mode. An IFD error occurs once for a frame.
Afterwards, the receiver is disabled until an EOFM
symbol is received, and queued transmits for the
present frame are cancelled (but the TRA bit is not
set). IFD is cleared when ERROR is read. It is also
cleared while the CONTROL.JE bit is reset or
while the CONTROL.JDIS bit is set or on reset.
0: No invalid frame detected
1: Invalid frame detected
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 0 = IBD Invalid Bit Detect.
Bit 0 = Reserved.
The IBD bit gets set whenever the receiver detects
that the filtered VPWI pin was not fixed in a state
long enough to reach the minimum valid symbol
time of Tv1 (or 35 µs). Any timing event less than
35 µs (and, of course, > 7 µs since the VPWI digit-
al filter will not allow pulses less than this through
its filter) is considered as noise and sets the IBD
accordingly. At this point the JBLPD peripheral will
cease transmitting and receiving any information
until a valid EOF symbol is received.
JBLPD PRIORITY LEVEL REGISTER (PRLR)
R249- Read/Write
Register Page: 23
Reset Value: 0001 0000 (10h)
7
0
PRL2 PRL1 PRL0 SLP
-
-
REOBP TEOBP
IBD errors are inhibited if the JBLPD peripheral is
in the “sleep or filter and NOT presently transmit-
ting” mode. An IBD error occurs once for a frame.
Afterwards, the receiver is disabled until an EOFM
symbol is received, and queued transmits for the
present frame are cancelled (but the TRA bit is not
set).
IBD is cleared when ERROR is read. Note that if
an invalid bit is detected during a bus idle condi-
tion, the IBD flag gets set and a new EOFmin must
be seen after the invalid bit before commencing to
receive again. IBD is also cleared while the CON-
TROL.JE bit is reset or while the CONTROL.JDIS
bit is set and on reset.
Bit 7:5 = PRL[2:0] Priority level bits
The priority with respect to the other peripherals
and the CPU is encoded with these three bits. The
value of “0” has the highest priority, the value “7”
has no priority. After the setting of this priority lev-
el, the priorities between the different Interrupt
sources and DMA of the JBLPD peripheral is hard-
ware defined (refer to the “Status register” bits de-
scription, the “Interrupts Management” and the
section about the explanation of the meaning of
the interrupt sources).
Depending on the value of the OP-
TIONS.DMASUSP bit, the DMA transfers can or
cannot be suspended by an ERROR or TLA event.
Refer to the description of DMASUSP bit.
0: No invalid bit detected
1: Invalid bit detected
Table 53. Internal Interrupt and DMA Priorities
without DMA suspend mode
JBLPD INTERRUPT VECTOR REGISTER (IVR)
R248- Read/Write (except bits 2:1)
Register Page: 23
Reset Value: xxxx xxx0 (xxh)
Priority Level
Event Sources
TX-DMA
Higher Priority
7
0
-
RX-DMA
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
V7
V6
V5
V4
V3
EV2
EV1
Bit 7:3 = V[7:3] Interrupt Vector Base Address.
User programmable interrupt vector bits.
Lower Priority
Bit 2:1 = EV[2:1] Encoded Interrupt Source (Read
Only).
EV2 and EV1 are set by hardware according to the
interrupt source, given in Table 8 (refer to the Sta-
tus register bits description about the explanation
of the meaning of the interrupt sources)
Table 54. Internal Interrupt and DMA Priorities
with DMA suspend mode
Priority Level
Event Sources
ERROR, TLA
TX-DMA
Higher Priority
Table 52. Interrupt Sources
RX-DMA
EV2
EV1
Interrupt Sources
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
EODM, EOFM
RDRF, REOB
TRDY, TEOB
0
0
1
1
0
1
0
1
Lower Priority
270/324
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 4 = SLP Receiver Sleep Mode.
the end of a block of data. An interrupt request is
performed if the TRDY_M bit of the IMR register is
set. TEOBP should be reset by software in order to
avoid undesired interrupt routines, especially in in-
itialisation routine (after reset) and after entering
the End Of Block interrupt routine.
Writing “0” in this bit will cancel the interrupt re-
quest.
This bit is reset when the CONTROL.JDIS bit is
The SLP bit is written to one when the user pro-
gram does not want to receive any data from the
JBLPD VPWI pin until an EOFM symbol occurs.
This mode is usually set when a message is re-
ceived that the user does not require - including
messages that the JBLPD is transmitting.
If the JBLPD is not transmitting and is in Sleep
mode, no data is transferred to the RXDATA regis-
ter, the RDRF flag does not get set, and errors as-
sociated with received data (RDOF, CRCE, IFD,
IBD) do not get set. Also, the EODM flag will not
get set.
If the JBLPD peripheral is transmitting and is in
sleep mode, no data is transferred to the RXDATA
register, the RDRF flag does not get set and the
RDOF error flag is inhibited. The CRCE, IFD, and
IBD flags, however, will NOT be inhibited while
transmitting in sleep mode.
set at least for 6 MCU clock cycles (3 NOPs).
Note: When the TEOBP flag is set, the TXD_M bit
is reset by hardware.
Note: TEOBP can only be written to “0”.
JBLPD INTERRUPT MASK REGISTER (IMR)
R250 - Read/Write
Register Page: 23
Reset Value: 0000 0000 (00h)
The SLP bit cannot be written to zero by the user
program. The SLP bit is set on reset or TTO get-
ting set, and it will stay set upon JE getting set until
an EOFM symbol is received.
7
0
ERR_ TRDY_ RDRF_ TLA_ RXD_ EODM_ EOFM_ TXD_
M
M
M
M
M
M
M
M
The SLP gets cleared on reception of an EOF or a
Break symbol. SLP is set while CONTROL.JE is
reset and while CONTROL.JDIS is set.
0: The JBLPD is not in Sleep Mode
1: The JBLPD is in Sleep Mode
To enable an interrupt source to produce an inter-
rupt request, the related mask bit must be set.
When these bits are reset, the related Interrupt
Pending bit can not generate an interrupt.
Note: This register is forced to its reset value if the
CONTROL.JDIS bit is set at least for 6 clock cy-
cles (3 NOPs). If the JDIS bit is set for a shorter
time, the bits could be reset or not reset.
Bit 3:2 = Reserved.
Bit 1 = REOP Receiver DMA End Of Block Pend-
ing.
This bit is set after a receiver DMA cycle to mark
the end of a block of data. An interrupt request is
performed if the RDRF_M bit of the IMR register is
set. REOBP should be reset by software in order
to avoid undesired interrupt routines, especially in
initialisation routine (after reset) and after entering
the End Of Block interrupt routine.
Bit 7 = ERR_M Error Interrupt Mask bit.
This bit enables the “error” interrupt source to gen-
erate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Error interrupt source masked
1: Error interrupt source un-masked
Writing “0” in this bit will cancel the interrupt re-
quest.
This bit is reset when the CONTROL.JDIS bit is
set at least for 6 MCU clock cycles (3 NOPs).
Bit 6 = TRDY_M Transmit Ready Interrupt Mask
bit.
Note: When the REOBP flag is set, the RXD_M bit
is reset by hardware.
This bit enables the “transmit ready” interrupt
source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
Note: REOBP can only be written to “0”.
0: TRDY interrupt source masked
1: TRDY interrupt source un-masked
Bit 0 = TEOP Transmitter DMA End Of Block
Pending.
This bit is set after a transmitter DMA cycle to mark
271/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 5 = RDRF_M Receive Data Register Full Inter-
rupt Mask bit.
This bit enables the “receive data register full” in-
terrupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
Bit 0 = TXD_M Transmitter DMA Mask bit.
If this bit is “0” no transmitter DMA request will be
generated, and the TRDY bit, in the Status Regis-
ter (STATUS), can request an interrupt. If TXD_M
bit is set to “1” then the TRDY bit can request a
DMA transfer. TXD_M is reset by hardware when
the transaction counter value decrements to zero,
that is when a Transmitter End Of Block condition
occurs (TEOBP flag set).
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Transmitter DMA disabled
1: Transmitter DMA enabled
0: RDRF interrupt source masked
1: RDRF interrupt source un-masked
Bit 4 = TLA_M Transmitter Lost Arbitration Inter-
rupt Mask bit.
This bit enables the “transmitter lost arbitration” in-
terrupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: TLA interrupt source masked
1: TLA interrupt source un-masked
JBLPD OPTIONS AND REGISTER GROUPS
SELECTION REGISTER (OPTIONS)
R251- Read/Write
Register Page: 23
Reset Value: 0000 0000 (00h)
Bit 3 = RXD_M Receiver DMA Mask bit.
If this bit is “0” no receiver DMA request will be
generated, and the RDRF bit, in the Status Regis-
ter (STATUS), can request an interrupt. If RXD_M
bit is set to “1” then the RDRF bit can request a
DMA transfer. RXD_M is reset by hardware when
the transaction counter value decrements to zero,
that is when a Receiver End Of Block condition oc-
curs (REOBP flag set).
7
0
INPOL NBSYMS DMASUSP LOOPB RSEL3 RSEL2 RSEL1 RSEL0
Bit 7 = INPOL VPWI Input Polarity Selector.
This bit allows the selection of the polarity of the
RX signal coming from the transceivers. Depend-
ing on the specific transceiver, the RX signal is in-
verted or not inverted respect the VPWO and the
J1850 bus line.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Receiver DMA disabled
1: Receiver DMA enabled
0: VPWI input is inverted by the transceiver with
respect to the J1850 line.
1: VPWI input is not inverted by the transceiver
with respect to the J1850 line.
Bit 2 = EODM_M End of Data Minimum Interrupt
Mask bit.
This bit enables the “end of data minimum” inter-
rupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
Bit 6 = NBSYMS NB Symbol Form Selector.
This bit allows the selection of the form of the Nor-
malization Bits (NB0/NB1).
0: EODM interrupt source mask
1: EODM interrupt source un-masked
0: NB0 active long symbol (Tv2), NB1 active short
symbol (Tv1)
1: NB0 active short symbol (Tv1), NB1 active long
symbol (Tv2)
Bit 1 = EOFM_M End of Frame Minimum Interrupt
Mask bit.
This bit enables the “end of frame minimum” inter-
rupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: EOFM interrupt source masked
1: EOFM interrupt source un-masked
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 5 = DMASUSP DMA Suspended Selector.
If this bit is “0”, JBLPD DMA has higher priority
with respect to the Interrupts of the peripheral.
DMA is performed even if an interrupt request is
already scheduled or if the relative interrupt rou-
tine is in execution.
If the bit is “1”, while the ERROR or TLA flag of the
STATUS register are set, the DMA transfers are
suspended. As soon as the flags are reset, the
DMA transfers can be performed.
Note: When the LOOPB bit is set, also the INPOL
bit must be set to obtain the correct management
of the polarity.
Bit 3:0 = RSEL[3:0] Registers Group Selection
bits.
These four bits are used to select one of the 9
groups of registers, each one composed of four
registers that are stacked at the addresses from
R252 (FCh) to R255 (FFh) of this register page
(23). Unless the wanted registers group is already
selected, to address a specific registers group,
these bits must be correctly written.
This feature allows that 36 registers (4 DMA regis-
ters - RDADR, RDCPR, TDAPR, TDCPR - and 32
Message Filtering Registers - FREG[0:31]) are
mapped using only 4 registers (here called Current
Registers - CREG[3:0]).
0: DMA not suspended
1: DMA suspended
Note: This bit has effect only on the priorities of
the JBLPD peripheral.
Bit 4 = LOOPB Local Loopback Selector.
This bit allows the Local Loopback mode. When
this mode is enabled (LOOPB=1), the VPWO out-
put of the peripheral is sent to the VPWI input with-
out inversions whereas the VPWO output line of
the MCU is placed in the passive state. Moreover
the VPWI input of the MCU is ignored by the pe-
ripheral. (Refer to Figure 9).
Since
the
Message
Filtering
Registers
(FREG[0:31]) are seldom read or written, it is sug-
gested to always reset the RSEL[3:0] bits after ac-
cessing the FREG[0:31] registers. In this way the
DMA registers are the current registers.
0: Local Loopback disabled
1: Local Loopback enabled
273/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD CURRENT REGISTER 0 (CREG0)
R252- Read/Write
Register Page: 23
JBLPD CURRENT REGISTER 2 (CREG2)
R254- Read/Write
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Reset Value: xxxx xxxx (xxh)
7
0
7
0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Depending on the RSEL[3:0] value of the OP-
TIONS register, this register is one of the following
stacked registers: RDAPR, FREG0, FREG4,
FREG8, FREG12, FREG16, FREG20, FREG24,
FREG28.
Depending on the RSEL[3:0] value of the OP-
TIONS register, this register is one of the following
stacked registers: TDAPR, FREG2, FREG6,
FREG10, FREG14, FREG18, FREG22, FREG26,
FREG30.
JBLPD CURRENT REGISTER 1 (CREG1)
R253 - Read/Write
Register Page: 23
JBLPD CURRENT REGISTER 3 (CREG3)
R255- Read/Write
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Reset Value: xxxx xxxx (xxh)
7
0
7
0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Depending on the RSEL[3:0] value of the OP-
TIONS register, this register is one of the following
stacked registers: RDCPR, FREG1, FREG5,
FREG9, FREG13, FREG17, FREG21, FREG25,
FREG29.
Depending on the RSEL[3:0] value of the OP-
TIONS register, this register is one of the following
stacked registers: TDCPR, FREG3, FREG7,
FREG11, FREG15, FREG19, FREG23, FREG27,
FREG31.
Table 55. Stacked registers map
RSEL[3:0]
Current
0000b 1000b 1001b 1010b
1011b
1100b
1101b
1110b
1111b
Registers
RDAPR FREG0 FREG4
RDCPR FREG1 FREG5
FREG8
FREG9
FREG12 FREG16 FREG20 FREG24 FREG28
FREG13 FREG17 FREG21 FREG25 FREG29
CREG0
CREG1
CREG2
CREG3
TDAPR FREG2 FREG6 FREG10 FREG14 FREG18 FREG22 FREG26 FREG30
TDCPR FREG3 FREG7 FREG11 FREG15 FREG19 FREG23 FREG27 FREG31
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.8.7.2 Stacked Registers
Register File) of the DMA receiver transaction
counter when the DMA between Peripheral and
Memory Space is selected. Otherwise, if the DMA
between Peripheral and Register File is selected,
this register points to a pair of registers that are
used as DMA Address register and DMA Transac-
tion Counter.
See the description of the OPTIONS register to
obtain more information on the map of the regis-
ters of this section.
JBLPD RECEIVER DMA ADDRESS POINTER
REGISTER (RDAPR)
R252 - RSEL[3:0]=0000b
See Section 0.1.6.1 and Section 0.1.6.2 for more
details on the use of this register.
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Bit 0 = RF/MEM Receiver Register File/Memory
Selector.
7
0
If this bit is set to “1”, then the Register File will be
selected as Destination, otherwise the Memory
space will be used.
RA7
RA6
RA5
RA4
RA3
RA2
RA1
PS
0: Receiver DMA with Memory space
1: Receiver DMA with Register File
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = RA[7:1] Receiver DMA Address Pointer.
RDAPR contains the address of the pointer (in the
Register File) of the Receiver DMA data source
when the DMA between the peripheral and the
Memory Space is selected. Otherwise, when the
DMA between the peripheral and Register File is
selected, this register has no meaning.
JBLPD TRANSMITTER DMA ADDRESS POINT-
ER REGISTER (TDAPR)
R254 - RSEL[3:0]=0000b
Register Page: 23
Reset Value: xxxx xxxx (xxh)
7
0
See Section 0.1.6.2 for more details on the use of
this register.
TA7
TA6
TA5
TA4
TA3
TA2
TA1
PS
Bit 0 = PS Memory Segment Pointer Selector.
This bit is set and cleared by software. It is only
meaningful if RDCPR.RF/MEM = 1.
0: The ISR register is used to extend the address
of data received by DMA (see MMU chapter)
1: The DMASR register is used to extend the ad-
dress of data received by DMA (see MMU chap-
ter)
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = TA[7:1] Transmitter DMA Address Point-
er.
TDAPR contains the address of the pointer (in the
Register File) of the Transmitter DMA data source
when the DMA between the Memory Space and
the peripheral is selected. Otherwise, when the
DMA between Register File and the peripheral is
selected, this register has no meaning.
See Section 0.1.6.2 for more details on the use of
this register.
JBLPD RECEIVER DMA TRANSACTION
COUNTER REGISTER (RDCPR)
R253 - RSEL[3:0]=0000b
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Bit 0 = PS Memory Segment Pointer Selector.
This bit is set and cleared by software. It is only
meaningful if TDCPR.RF/MEM = 1.
0: The ISR register is used to extend the address
of data transmitted by DMA (see MMU chapter)
1: The DMASR register is used to extend the ad-
dress of data transmitted by DMA (see MMU
chapter)
7
0
RC7
RC6
RC5
RC4
RC3
RC2
RC1 RF/MEM
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = RC[7:1] Receiver DMA Counter Pointer.
RDCPR contains the address of the pointer (in the
275/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD TRANSMITTER DMA TRANSACTION
COUNTER REGISTER (TDCPR)
R255 - RSEL[3:0]=0000b
JBLPD MESSAGE FILTERING REGISTERS
(FREG[0:31])
R252/R253/R254/R255 - RSEL[3]=1
Register Page: 23
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Reset Value: xxxx xxxx (xxh)
7
0
Register
7
0
FREG0 F_07 F_06 F_05 F_04 F_03 F_02 F_01 F_00
FREG1 F_0F F_0E F_0D F_0C F_0B F_0A F_09 F_08
FREG2 F_17 F_16 F_15 F_14 F_13 F_12 F_11 F_10
FREG3 F_1F F_1E F_1D F_1C F_1B F_1A F_19 F_18
FREG4 F_27 F_26 F_25 F_24 F_23 F_22 F_21 F_20
FREG5 F_2F F_2E F_2D F_2C F_2B F_2A F_29 F_28
FREG6 F_37 F_36 F_35 F_34 F_33 F_32 F_31 F_30
FREG7 F_3F F_3E F_3D F_3C F_3B F_3A F_39 F_38
FREG8 F_47 F_46 F_45 F_44 F_43 F_42 F_41 F_40
FREG9 F_4F F_4E F_4D F_4C F_4B F_4A F_49 F_48
FREG10 F_57 F_56 F_55 F_54 F_53 F_52 F_51 F_50
FREG11 F_5F F_5E F_5D F_5C F_5B F_5A F_59 F_58
FREG12 F_67 F_66 F_65 F_64 F_63 F_62 F_61 F_60
FREG13 F_6F F_6E F_6D F_6C F_6B F_6A F_69 F_68
FREG14 F_77 F_76 F_75 F_74 F_73 F_72 F_71 F_70
FREG15 F_7F F_7E F_7D F_7C F_7B F_7A F_79 F_78
FREG16 F_87 F_86 F_85 F_84 F_83 F_82 F_81 F_80
FREG17 F_8F F_8E F_8D F_8C F_8B F_8A F_89 F_88
FREG18 F_97 F_96 F_95 F_94 F_93 F_92 F_91 F_90
FREG19 F_9F F_9E F_9D F_9C F_9B F_9A F_99 F_98
FREG20 F_A7 F_A6 F_A5 F_A4 F_A3 F_A2 F_A1 F_A0
FREG21 F_AF F_AE F_AD F_AC F_AB F_AA F_A9 F_A8
FREG22 F_B7 F_B6 F_B5 F_B4 F_B3 F_B2 F_B1 F_B0
FREG23 F_BF F_BE F_BD F_BC F_BB F_BA F_B9 F_B8
FREG24 F_C7 F_C6 F_C5 F_C4 F_C3 F_C2 F_C1 F_C0
FREG25 F_CF F_CE F_CD F_CC F_CB F_CA F_C9 F_C8
FREG26 F_D7 F_D6 F_D5 F_D4 F_D3 F_D2 F_D1 F_D0
FREG27 F_DF F_DE F_DD F_DC F_DB F_DA F_D9 F_D8
FREG28 F_E7 F_E6 F_E5 F_E4 F_E3 F_E2 F_E1 F_E0
FREG29 F_EF F_EE F_ED F_EC F_EB F_EA F_E9 F_E8
FREG30 F_F7 F_F6 F_F5 F_F4 F_F3 F_F2 F_F1 F_F0
FREG31 F_FF F_FE F_FD F_FC F_FB F_FA F_F9 F_F8
TC7
TC6
TC5
TC4
TC3
TC2
TC1 RF/MEM
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = TC[7:1] Transmitter DMA Counter Point-
er.
RDCPR contains the address of the pointer (in the
Register File) of the DMA transmitter transaction
counter when the DMA between Memory Space
and peripheral is selected. Otherwise, if the DMA
between Register File and peripheral is selected,
this register points to a pair of registers that are
used as DMA Address register and DMA Transac-
tion Counter.
See Section 0.1.6.1 and Section 0.1.6.2 for more
details on the use of this register.
Bit 0 = RF/MEM Transmitter Register File/Memory
Selector.
If this bit is set to “1”, then the Register File will be
selected as Destination, otherwise the Memory
space will be used.
0: Transmitter DMA with Memory space
1: Transmitter DMA with Register File
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
These registers are structured in eight groups of
four registers. The user can gain access to these
registers programming the RSEL[2:0] bits of the
OPTIONS register while the RSEL[3] bit of the
same register must be placed at 1. In this way the
user can select the group where the registers that
he/she wants to use are placed. See the descrip-
tion of OPTIONS register for the correspondence
between registers and the values of RSEL[2:0] bits
(See Table 11).
register and the RDRF flag is set. Also, every other
data byte received in this frame is transferred to
the RXDATA register unless the JBLPD peripheral
is put into sleep mode setting the SLP bit.
If the bit of the array correspondent to the I.D. byte
is clear, then the transfer of this byte as well as any
byte for the balance of this frame is inhibited, and
the RDRF bit remains cleared.
The bit 0 of the FREG[0] register (FREG[0].0 -
marked as F_00 in the previous table) corre-
sponds to the I.D. byte equal to 00h while the bit 7
of the FREG[31] register (FREG[31].7 - marked as
F_FF in the previous table) corresponds to the I.D.
byte equal to FFh.
From the functional point of view, the FREG[0]-
FREG[31] registers can be seen as an array of
256 bits involved in the J1850 received message
filtering system.
The first byte received in a frame (following a valid
received SOF character) is an Identifier (I.D.) byte.
It is used by the JBLPD peripheral as the address
of the 256 bits array.
Note: The FREG registers are undefined upon re-
set. Because of this, it is strongly recommended
that the contents of these registers has to be de-
fined before JE is set for the first time after reset.
Otherwise, unpredictable results may occur.
If the bit of the array correspondent to the I.D. byte
is set, then the byte is transferred to the RXDATA
277/324
9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Register
Address
F0h
7
0
STATUS
reset value
ERR
0
TRDY
1
RDRF
0
TLA
0
RDT
0
EODM
0
EOFM
0
IDLE
0
TXDATA
TXD7
x
TXD6
x
TXD5
x
TXD4
x
TXD3
x
TXD2
x
TXD1
x
TXD0
x
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
reset value
RXDATA
reset value
RXD7
x
RXD6
x
RXD5
x
RXD4
x
RXD3
x
RXD2
x
RXD1
x
RXD0
x
TXOP
reset value
MLC3
0
MLC2
0
MLC1
0
MLC0
0
-
0
OP2
0
OP1
0
OP0
0
CLKSEL
reset value
4X
0
-
0
FREQ5
0
FREQ4
0
FREQ3
0
FREQ2
0
FREQ1
0
FREQ0
0
CONTROL
reset value
JE
0
JDIS
1
NFL
0
JDLY4
0
JDLY3
0
JDLY2
0
JDLY1
0
JDLY0
0
PADDR
reset value
ADR7
x
ADR6
x
ADR5
x
ADR4
x
ADR3
x
ADR2
x
ADR1
x
ADR0
x
ERROR
reset value
TTO
0
TDUF
0
RDOF
0
TRA
0
RBRK
0
CRCE
0
IFD
0
IBD
0
IVR
reset value
V7
x
V6
x
V5
x
V4
x
V3
x
EV2
x
EV1
x
-
0
PRLR
reset value
PRL2
0
PRL1
0
PRL0
0
SLP
1
-
0
-
0
REOBP
0
TEOBP
0
IMR
reset value
ERR_M
0
TRDY_M
0
RDRF_M
0
TLA_M
0
RXD_M
0
EODM_M EOFM_M
TXD_M
0
0
0
OPTIONS
reset value
INPOL
0
NBSYMS DMASUSP LOOPB
RSEL3
0
RSEL2
0
RSEL1
0
RSEL0
0
0
0
0
CREG0
reset value
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
x
b0
x
CREG1
reset value
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
x
b0
x
CREG2
reset value
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
x
b0
x
CREG3
reset value
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
x
b0
x
278/324
9
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
10.9 EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
10.9.1 Introduction
supply noise rejection. In fact, the converted digital
value, is referred to the analog reference voltage
which determines the full scale converted value.
The 8-Channel Analog to Digital Converter (A/D)
comprises an input multiplex channel selector
feeding a successive approximation converter.
Conversion requires 138 INTCLK cycles (of which
84 are required for sampling), conversion time is
thus a function of the INTCLK frequency; for in-
stance, for a 20MHz clock rate, conversion of the
selected channel requires 6.9µs. This time in-
cludes the 4.2µs required by the built-in Sample
and Hold circuitry, which minimizes the need for
external components and allows quick sampling of
the signal to minimise warping and conversion er-
ror. Conversion resolution is 8 bits, with ±1 LSB
Naturally, Analog and Digital V MUST be com-
SS
mon. If analog supplies are not present, input ref-
erence voltages are referred to the digital ground
and supply.
Up to 8 multiplexed Analog Inputs are available,
depending on the specific device type. A group of
signals can be converted sequentially by simply
programming the starting address of the first ana-
log channel to be converted and with the AUTO-
SCAN feature.
Two Analog Watchdogs are provided, allowing
continuous hardware monitoring of two input chan-
nels. An Interrupt request is generated whenever
the converted value of either of these two analog
inputs is outside the upper or lower programmed
threshold values. The comparison result is stored
in a dedicated register.
maximum error in the input range between V
SS
and the analog V reference.
DD
The converter uses a fully differential analog input
configuration for the best noise immunity and pre-
cision performance. Two separate supply refer-
ences are provided to ensure the best possible
Figure 121. Block Diagram
n
INT. VECTOR POINTER
INT. CONTROL REGISTER
INTERRUPT UNIT
COMPARE RESULT REGISTER
7U
7L
6U
6L
THRESHOLD REGISTER
THRESHOLD REGISTER
THRESHOLD REGISTER
THRESHOLD REGISTER
COMPARE LOGIC
INTERNAL
TRIGGER
CONTROL
LOGIC
AIN 7
AIN 6
AIN 5
AIN 4
AIN 3
AIN 2
AIN 1
AIN 0
DATA REGISTER 7
DATA REGISTER 6
DATA REGISTER 5
DATA REGISTER 4
DATA REGISTER 3
DATA REGISTER 2
DATA REGISTER 1
DATA REGISTER 0
CONVERSION
EXTERNAL
TRIGGER
RESULT
ANALOG
MUX
SUCCESSIVE APPROXIMATION
A/D CONVERTER
AUTOSCAN LOGIC
CONTROL REG.
VA00223
279/324
9
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
ANALOG TO DIGITAL CONVERTER (Cont’d)
Single and continuous conversion modes are
available. Conversion may be triggered by an ex-
ternal signal or, internally, by the Multifunction
Timer.
In Continuous Mode (CONT = “1”), a continuous
conversion flow is initiated by the start event.
When conversion of channel 7 is complete, con-
version of channel 's' is initiated (where 's' is spec-
ified by the setting of the SC2, SC1 and SC0 bits);
this will continue until the ST bit is reset by soft-
ware. In all cases, an ECV interrupt is issued each
time channel 7 conversion ends.
A Power-Down programmable bit allows the A/D
to be set in low-power idle mode.
The A/D’s Interrupt Unit provides two maskable
channels (Analog Watchdog and End of Conver-
sion) with hardware fixed priority, and up to 7 pro-
grammable priority levels.
When channel 'i' is converted ('s' <'i' <7), the relat-
ed Data Register is reloaded with the new conver-
sion result and the previous value is lost. The End
of Conversion (ECV) interrupt service routine can
be used to save the current values before a new
conversion sequence (so as to create signal sam-
ple tables in the Register File or in Memory).
CAUTION: A/D INPUT PIN CONFIGURATION
The input Analog channel is selected by using the
I/O pin Alternate Function setting (PXC2, PXC1,
PXC0 = 1,1,1) as described in the I/O ports sec-
tion. The I/O pin configuration of the port connect-
ed to the A/D converter is modified in order to pre-
vent the analog voltage present on the I/O pin from
causing high power dissipation across the input
buffer. Deselected analog channels should also be
maintained in Alternate function configuration for
the same reason.
10.9.2.2 Triggering and Synchronisation
In both modes, conversion may be triggered by in-
ternal or external conditions; externally this may
be tied to EXTRG, as an Alternate Function input
on an I/O port pin, and internally, it may be tied to
INTRG, generated by a Multifunction Timer pe-
ripheral. Both external and internal events can be
separately masked by programming the EXTG/
INTG bits of the Control Logic Register (CLR). The
events are internally ORed, thus avoiding potential
hardware conflicts. However, the correct proce-
dure is to enable only one alternate synchronisa-
tion condition at any time.
10.9.2 Functional Description
10.9.2.1 Operating Modes
Two operating modes are available: Continuous
Mode and Single Mode. To enter one of these
modes it is necessary to program the CONT bit of
the Control Logic Register. Continuous Mode is
selected when CONT is set, while Single Mode is
selected when CONT is reset.
The effect either of these synchronisation modes
is to set the ST bit by hardware. This bit is reset, in
Single Mode only, at the end of each group of con-
versions. In Continuous Mode, all trigger pulses
after the first are ignored.
Both modes operate in AUTOSCAN configuration,
allowing sequential conversion of the input chan-
nels. The number of analog inputs to be converted
may be set by software, by setting the number of
the first channel to be converted into the Control
Register (SC2, SC1, SC0 bits). As each conver-
sion is completed, the channel number is automat-
ically incremented, up to channel 7. For example,
if SC2, SC1, SC0 are set to 0,1,1, conversion will
proceed from channel 3 to channel 7, whereas, if
SC2, SC1, SC0 are set to 1,1,1, only channel 7 will
be converted.
The synchronisation sources must be at a logic
low level for at least the duration of one INTCLK
cycle and, in Single Mode, the period between trig-
ger pulses must be greater than the total time re-
quired for a group of conversions. If a trigger oc-
curs when the ST bit is still set, i.e. when conver-
sion is still in progress, it will be ignored.
On devices where two A/D Converters are present
they can be triggered from the same source.
When the ST bit of the Control Logic Register is
set, either by software or by hardware (by an inter-
nal or external synchronisation trigger signal), the
analog inputs are sequentially converted (from the
first selected channel up to channel 7) and the re-
sults are stored in the relevant Data Registers.
On Chip Event
(Internal trigger)
Converter
External Trigger
EXTRG pin
A/D 0
A/D 1
MFT 0
10.9.2.3 Analog Watchdogs
In Single Mode (CONT = “0”), the ST bit is reset
by hardware following conversion of channel 7; an
End of Conversion (ECV) interrupt request is is-
sued and the A/D waits for a new start event.
Two internal Analog Watchdogs are available for
highly flexible automatic threshold monitoring of
external analog signal levels.
280/324
9
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
ANALOG TO DIGITAL CONVERTER (Cont’d)
Analog channels 6 and 7 monitor an acceptable
voltage level window for the converted analog in-
puts. The external voltages applied to inputs 6 and
7 are considered normal while they remain below
their respective Upper thresholds, and above or at
their respective Lower thresholds.
10.9.2.4 Power Down Mode
Before enabling an A/D conversion, the POW bit of
the Control Logic Register must be set; this must
be done at least 60µs before the first conversion
start, in order to correctly bias the analog section
of the converter circuitry.
When the external signal voltage level is greater
than, or equal to, the upper programmed voltage
limit, or when it is less than the lower programmed
voltage limit, a maskable interrupt request is gen-
erated and the Compare Results Register is up-
dated in order to flag the threshold (Upper or Low-
er) and channel (6 or 7) responsible for the inter-
rupt. The four threshold voltages are user pro-
grammable in dedicated registers (08h to 0Bh) of
the A/D register page. Only the 4 MSBs of the
Compare Results Register are used as flags (the 4
LSBs always return “1” if read), each of the four
MSBs being associated with a threshold condition.
When the A/D is not required, the POW bit may be
reset in order to reduce the total power consump-
tion. This is the reset configuration, and this state
is also selected automatically when the ST9 is
placed in Halt Mode (following the execution of the
haltinstruction).
Analog Voltage
Upper threshold
Normal Area
Following a hardware reset, these flags are reset.
During normal A/D operation, the CRR bits are set,
in order to flag an out of range condition and are
automatically reset by hardware after a software
reset of the Analog Watchdog Request flag in the
AD_ICR Register.
(Window Guarded)
Lower threshold
Figure 122. A/D Trigger Source
n
281/324
9
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
ANALOG TO DIGITAL CONVERTER (Cont’d)
Figure 123. Application Example: Analog Watchdog used in Motorspeed Control
n
whenever any of the two guarded analog inputs go
out of range. The Compare Result Register (CRR)
tracks the analog inputs which exceed their pro-
grammed thresholds.
10.9.3 Interrupts
The A/D provides two interrupt sources:
– End of Conversion
When two requests occur simultaneously, the An-
alog Watchdog Request has priority over the End
of Conversion request, which is held pending.
– Analog Watchdog Request
The A/D Interrupt Vector Register (AD_IVR) pro-
vides hardware generated flags which indicate the
interrupt source, thus allowing automatic selection
of the correct interrupt service routine.
The Analog Watchdog Request requires the user
to poll the Compare Result Register (CRR) to de-
termine which of the four thresholds has been ex-
ceeded. The threshold status bits are set to flag an
out of range condition, and are automatically reset
by hardware after a software reset of the Analog
Watchdog Request flag in the AD_ICR Register.
The interrupt pending flags, ECV and AWD,
should be reset by the user within the interrupt
service routine. Setting either of these two bits by
software will cause an interrupt request to be gen-
erated.
Analog
Watch-
dog Re-
quest
7
0
0
Lower
Word
Address
X
X
X
X
X
X
0
7
0
0
End of
Conv.
Request
Upper
Word
Address
10.9.3.1 Register Mapping
X
X
X
X
X
X
1
It is possible to have two independent A/D convert-
ers in the same device. In this case they are
named A/D 0 and A/D 1. If the device has one A/D
converter it uses the register addresses of A/D 0.
The register pages are the following:
The A/D Interrupt vector should be programmed
by the User to point to the first memory location in
the Interrupt Vector table containing the base ad-
dress of the four byte area of the interrupt vector
table in which the address of the A/D interrupt
service routines are stored.
A/Dn
A/D 0
A/D 1
Register Page
63
61
The Analog Watchdog Interrupt Pending bit (AWD,
AD_ICR.6), is automatically set by hardware
282/324
9
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
ANALOG TO DIGITAL CONVERTER (Cont’d)
10.9.4 Register Description
DATA REGISTERS (DiR)
7
0
D3.7 D3.6 D3.5 D3.4 D3.3 D3.2 D3.1 D3.0
The conversion results for the 8 available chan-
nels are loaded into the 8 Data registers following
conversion of the corresponding analog input.
CHANNEL 4 DATA REGISTER (D4R)
R244 - Read/Write
Register Page: 63
CHANNEL 0 DATA REGISTER (D0R)
R240 - Read/Write
Register Page: 63
Reset Value: undefined
7
0
Reset Value: undefined
7
0
D4.7 D4.6 D4.5 D4.4 D4.3 D4.2 D4.1 D4.0
D0.7 D0.6 D0.5 D0.4 D0.3 D0.2 D0.1 D0.0
Bit 7:0 = D4.[7:0]: Channel 4 Data
Bit 7:0 = D0.[7:0]: Channel 0 Data.
CHANNEL 5 DATA REGISTER (D5R)
R245 - Read/Write
Register Page: 63
CHANNEL 1 DATA REGISTER (D1R)
R241 - Read/Write
Register Page: 63
Reset Value: undefined
7
0
Reset Value: undefined
7
0
D5.7 D5.6 D5.5 D5.4 D5.3 D5.2 D5.1 D5.0
D1.7 D1.6 D1.5 D1.4 D1.3 D1.2 D1.1 D1.0
Bit 7:0 = D5.[7:0]: Channel 5 Data.
Bit 7:0 = D1.[7:0]: Channel 1 Data.
CHANNEL 6 DATA REGISTER (D6R)
R246 - Read/Write
Register Page: 63
CHANNEL 2 DATA REGISTER (D2R)
R242 - Read/Write
Register Page: 63
Reset Value: undefined
7
0
Reset Value: undefined
7
0
D6.7 D6.6 D6.5 D6.4 D6.3 D6.2 D6.1 D6.0
D2.7 D2.6 D2.5 D2.4 D2.3 D2.2 D2.1 D2.0
Bit 7:0 = D6.[7:0]: Channel 6 Data
Bit 7:0 = D2.[7:0]: Channel 2 Data.
CHANNEL 7 DATA REGISTER (D7R)
R247 - Read/Write
Register Page: 63
CHANNEL 3 DATA REGISTER (D3R)
R243 - Read/Write
Register Page: 63
Reset Value: undefined
7
0
Reset Value: undefined
D7.7 D7.6 D7.5 D7.4 D7.3 D7.2 D7.1 D7.0
Bit 7:0 = D3.[7:0]: Channel 3 Data.
283/324
9
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
ANALOG TO DIGITAL CONVERTER (Cont’d)
CHANNEL 6 LOWER THRESHOLD REGISTER
(LT6R)
R248 - Read/Write
Register Page: 63
Reset Value: undefined
CHANNEL 7 UPPER THRESHOLD REGISTER
(UT7R)
R251 - Read/Write
Register Page: 63
Reset Value: undefined
7
0
7
0
UT7. UT7. UT7. UT7. UT7. UT7. UT7. UT7.
LT6.7 LT6.6 LT6.5 LT6.4 LT6.3 LT6.2 LT6.1 LT6.0
7
6
5
4
3
2
1
0
Bit 7:0 = LT6.[7:0]: Channel 6 Lower Threshold
Bit 7:0 = UT7.[7:0]: Channel 7 Upper Threshold
value
User-defined lower threshold value for Channel 6,
to be compared with the conversion results.
User-defined upper threshold value for Channel 7,
to be compared with the conversion results.
CHANNEL 7 LOWER THRESHOLD REGISTER
(LT7R)
R249 - Read/Write
COMPARE RESULT REGISTER (CRR)
R252 - Read/Write
Register Page: 63
Reset Value: undefined
Register Page: 63
Reset Value: 0000 1111 (0Fh)
7
0
7
0
1
LT7.7 LT7.6 LT7.5 LT7.4 LT7.3 LT7.2 LT7.1 LT7.0
C7U C6U C7L C6L
1
1
1
Bit 7:0 = LT7.[7:0]: Channel 7 Lower Threshold.
User-defined lower threshold value for Channel 7,
to be compared with the conversion results.
These bits are set by hardware and cleared by
software.
Bit 7 = C7U: Compare Reg 7 Upper threshold
0: Threshold not reached
1: Channel 7 converted data is greater than or
equal to UT7R threshold register value.
CHANNEL 6 UPPER THRESHOLD REGISTER
(UT6R)
R250 - Read/Write
Register Page: 63
Reset Value: undefined
Bit 6 = C6U: Compare Reg 6Upper threshold
0: Threshold not reached
1: Channel 6 converted data is greater than or
equal to UT6R threshold register value.
7
0
UT6. UT6. UT6. UT6. UT6. UT6. UT6. UT6.
7
6
5
4
3
2
1
0
Bit 5 = C7L: Compare Reg 7 Lower threshold
0: Threshold not reached
1: Channel 7 converted data is less than the LT7R
Bit 7:0 = UT6.[7:0]: Channel 6 Upper Threshold
value.
User-defined upper threshold value for Channel 6,
threshold register value.
to be compared with the conversion results.
Bit 4 = C6L: Compare Reg 6 Lower threshold
0: Threshold not reached
1: Channel 6 converted data is less than the LT6R
threshold register value.
Bit 3:0 = Reserved, returns “1” when read.
Note: Any software reset request generated by
writing to the AD_ICR, will also cause all the com-
pare status bits to be cleared.
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9
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
ANALOG TO DIGITAL CONVERTER (Cont’d)
CONTROL LOGIC REGISTER (CLR)
however, the correct procedure is to enable only
one alternate synchronization input at a time.
The Control Logic Register (CLR) manages the
A/D converter logic. Writing to this register will
cause the current conversion to be aborted and
the autoscan logic to be re-initialized.
Note: The effect of either synchronization mode is
to set the START/STOP bit, which is reset by hard-
ware when in SINGLE mode, at the end of each
sequence of conversions.
CONTROL LOGIC REGISTER (CLR)
R253 - Read/Write
Register Page: 63
Requirements: The External Synchronisation In-
put must receive a low level pulse longer than an
INTCLK period and, for both External and On-Chip
Event synchronisation, the repetition period must
be greater than the time required for the selected
sequence of conversions.
Reset Value: 0000 0000 (00h)
7
0
EXT
G
CON
T
SC2 SC1 SC0
INTG POW
ST
Bit 2 = POW: Power Up/Power Down.
This bit is set and cleared by software.
0: Power down mode: all power-consuming logic is
disabled, thus selecting a low power idle mode.
1: Power up mode: the A/D converter logic and an-
alog circuitry is enabled.
Bit 7:5 = SC[2:0]: Start Conversion Address.
These 3 bits define the starting analog input chan-
nel (Autoscan mode). The first channel addressed
by SC[2:0] is converted, then the channel number
is incremented for the successive conversion, until
channel 7 (111) is converted. When SC2, SC1 and
SC0 are all set, only channel 7 will be converted.
Bit 1 = CONT: Continuous/Single.
0: Single Mode: a single sequence of conversions
is initiated whenever an external (or internal)
trigger occurs, or when the ST bit is set by soft-
ware.
1: Continuous Mode: the first sequence of conver-
sions is started, either by software (by setting
the ST bit), or by hardware (on an internal or ex-
ternal trigger, depending on the setting of the
INTG and EXTG bits); a continuous conversion
sequence is then initiated.
Bit 4 = EXTG: External Trigger Enable.
This bit is set and cleared by software.
0: External trigger disabled.
1: External trigger enabled. Allows a conversion
sequence to be started on the subsequent edge
of the external signal applied to the EXTRG pin
(when enabled as an Alternate Function).
Bit 3 = INTG: Internal Trigger Enable.
This bit is set and cleared by software.
0: Internal trigger disabled.
1: Internal trigger enabled. Allows a conversion se-
quence to be started, synchronized by an inter-
nal signal (On-chip Event signal) from a Multi-
function Timer peripheral.
Bit 0 = ST: Start/Stop.
0: Stop conversion. When the A/D converter is
running in Single Mode, this bit is hardware re-
set at the end of a sequence of conversions.
1: Start a sequence of conversions.
Both External and Internal Trigger inputs are inter-
nally ORed, thus avoiding Hardware conflicts;
285/324
9
EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)
ANALOG TO DIGITAL CONVERTER (Cont’d)
INTERRUPT CONTROL REGISTER (AD_ICR)
R254 - Read/Write
Register Page: 63
Bit 4 = AWDI: Analog Watchdog Interrupt Enable.
This bit masks or enables the Analog Watchdog
interrupt request.
Reset Value: 0000 1111 (0Fh)
0: Mask Analog Watchdog interrupts
1: Enable Analog Watchdog interrupts
7
0
ECV AWD ECI AWDI
X
PL2 PL1 PL0
Bit 3 = Reserved.
Bit 2:0 = PL[2:0]: A/D Interrupt Priority Level.
These three bits allow selection of the Interrupt pri-
ority level for the A/D.
Bit 7 = ECV: End of Conversion.
This bit is set by hardware after a group of conver-
sions is completed. It must be reset by the user,
before returning from the Interrupt Service Rou-
tine. Setting this bit by software will cause a soft-
ware interrupt request to be generated.
0: No End of Conversion event occurred
1: An End of Conversion event occurred
INTERRUPT VECTOR REGISTER (AD_IVR)
R255 - Read/Write
Register Page: 63
Reset Value: xxxx xx10 (x2h)
Bit 6 = AWD: Analog Watchdog.
7
0
0
This is automatically set by hardware whenever ei-
ther of the two monitored analog inputs goes out of
bounds. The threshold values are stored in regis-
ters F8h and FAh for channel 6, and in registers
F9h and FBh for channel 7 respectively. The Com-
pare Result Register (CRR) keeps track of the an-
alog inputs exceeding the thresholds.
V7
V6
V5
V4
V3
V2
W1
Bit 7:2 = V[7:2]: A/D Interrupt Vector.
This vector should be programmed by the User to
point to the first memory location in the Interrupt
Vector table containing the starting addresses of
the A/D interrupt service routines.
The AWD bit must be reset by the user, before re-
turning from the Interrupt Service Routine. Setting
this bit by software will cause a software interrupt
request to be generated.
0: No Analog Watchdog event occurred
1: An Analog Watchdog event occurred
Bit 1 = W1: Word Select.
This bit is set and cleared by hardware, according
to the A/D interrupt source.
0: Interrupt source is the Analog Watchdog, point-
ing to the lower word of the A/D interrupt service
block (defined by V[7:2]).
1:Interrupt source is the End of Conversion inter-
rupt, thus pointing to the upper word.
Bit 5 = ECI: End of Conversion Interrupt Enable.
This bit masks the End of Conversion interrupt re-
quest.
0: Mask End of Conversion interrupts
1: Enable End of Conversion interrupts
Note: When two requests occur simultaneously,
the Analog Watchdog Request has priority over
the End of Conversion request, which is held
pending.
Bit 0 = Reserved. Forced by hardware to 0.
286/324
9
ST92F120 - ELECTRICAL CHARACTERISTICS
11 ELECTRICAL CHARACTERISTICS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precautions to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations. The average chip-junc-
tion temperature, T , in Celsius can be obtained
J
from:
T =
T + P x RthJA
A D
J
Where: T =
Ambient Temperature.
A
For proper operation it is recommended that V
IN
.
RthJA = Package thermal resistance
(junction-to ambient).
and V be higher than V
and lower than V
O
SS
DD
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V
P =
P
+ P
.
DD
D
INT
PORT
or V ).
SS
P
P
=
I
x V (chip internal power).
INT
PORT
DD DD
=Port power dissipation
(determined by the user)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
Supply Voltage
A/D Converter Analog Reference
A/D Converter V
– 0.3 to 6.5
DD
AV
AV
V
– 0.3 to V + 0.3
V
DD
SS
IN
DD
DD
V
SS
SS
V
Input Voltage (standard I/O pins)
Input Voltage (open drain I/O pins)
Analog Input Voltage (A/D Converter)
Storage Temperature
– 0.3 to V + 0.3
V
V
DD
V
– 0.3 to 6.5
INOD
V
AV to AV
DD
V
AIN
STG
INJ
SS
T
I
– 55 to +150
±10
°C
mA
mA
V
Pin Injection Current - Digital and Analog Input
Maximum Accumulated Pin injection Current in the device
ESD Susceptibility
±100
ESD
2000
Note:
Stresses above those listed as “absolute maximum ratings“ may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability. All voltages are referenced to V =0.
SS
THERMAL CHARACTERISTICS
Symbol
Package
Value
Unit
RthJA
PQFP100
28
°C/W
RECOMMENDED OPERATING CONDITIONS
Value
Symbol
Parameter
Operating Temperature
Unit
Min
–40
4.5
Max
105
5.5
T
°C
V
A
V
Operating Supply Voltage
DD
AV
Analog Supply Voltage
V
- 0.3
V + 0.3
DD
V
DD
INTCLK
DD
(1)
f
Internal Clock Frequency @ 4.5V - 5.5V
0
24
MHz
Note:
(1) 1MHz when A/D or JBLPD is used, 2.6MHz when I²C is used.
287/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(V = 5V ± 10%, T = –40°C to +105°C, unless otherwise specified)
DD
A
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
Input High Level
TTL
2.0
V
V
V
V
P0[7:0]-P1[7.0]-P2[7:6]
P3.3 P4.2-P4.5-P5.3
CMOS
TTL
0.7 x V
2.0
DD
Input High Level
Pure open-drain I/O
CMOS
0.7 x V
DD
P2[3:2]
Input High Level
Standard Schmitt Trigger
0.7 x V
V
P2[5:4]-P2[1:0]-P3[7:4] P3[2:1]-
P4[4:3]-P4[1:0] P5[7:4]-P5[2:0]-
P6[3:0] P7[7:0]-P8[7:0]-P9[7:0]
DD
V
IH
Input High Level
Pure open-drain I/O
Special Schmitt Trigger
0.7 x V
0.7 x V
V
V
DD
P4[7:6]
Input High Level
High Hyst. Schmitt Trigger
DD
P6[5:4]
Input Low Level
TTL
0.8
V
V
P0[7:0]-P1[7:0]-P2[7:6] P2[3:2]-
P3.3-P4.2-P4.5-P5.3
CMOS
0.3 x V
DD
Input Low Level
Standard Schmitt Trigger
P2[5:4]-P2[1:0]-P3[7:4] P3[2:1]-
P4[4:3]-P4[1:0] P5[7:4]-P5[2:0]-
P6[3:0] P7[7:0]-P8[7:0]-P9[7:0]
0.8
V
IL
Input Low Level
Special Schmitt Trigger
P4[7:6]
V
0.3 x V
0.3 x V
6.0
DD
DD
Input Low Level
High Hyst. Schmitt Trigger
P6[5:4]
Input Voltage Range
Pure Open Drain
P2[3:2]-P4[7:6]
-0.3
-0.3
V
V
V
I
Input Voltage Range
All other pins
V
+ 0.3
DD
288/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
(2)
Input Hysteresis
Standard Schmitt Trigger
P2[5:4]-P2[1:0]-P3[7:4] P3[2:1]-
P4[4:3]-P4[1:0] P5[7:4]-P5[2:0]-
P6[3:0] P7[7:0]-P8[7:0]-P9[7:0]
600
mV
(2)
Input Hysteresis
V
HYS
Special Schmitt Trigger
800
900
mV
mV
P4[7:6]
(2)
Input Hysteresis
High Hyst. Schmitt Trigger
P6[5:4]
Push Pull, I = – 2mA
EMR1 Register - BSZ bit = 0
OH
V
V
V
V
– 0.8
V
V
V
V
V
V
V
Output High Level
P0[7:0]-P6[5:4]
AS-DS-RW
(3)
(3)
(3)
(3)
DD
DD
DD
DD
Push Pull, I = – 8mA
OH
– 0.8
– 0.8
– 0.8
EMR1 Register - BSZ bit = 1
V
OH
Push Pull, I = – 2mA
Output High Level
OH
EMR1 Register - BSZ bit = 0
P1[7:0]-P2[7:4]-P2[1:0] P3[7:1]-
P4[5:0]-P5[7:0]-P6[3:0]-P7[7:0]-
P8[7:0] P9[7:0]-VPWO
Push Pull, I = – 4mA
OH
EMR1 Register - BSZ bit = 1
Push Pull / Open Drain, I =2mA
EMR1 Register - BSZ bit = 0
OL
0.4
0.4
0.4
Output Low Level
P0[7:0]-P2[3:2]-P4[7:6] P6[5:4]-
AS-DS-RW
(3)
Push Pull / Open Drain, I =8mA,
EMR1 Register - BSZ bit = 1
OL
(3)
V
OL
Output Low Level
P1[7:0]-P2[7:4]-P2[1:0] P3[7:1]-
P4[5:0]-P5[7:0]
P6[3:0]-P7[7:0]-P8[7:0] P9[7:0]-
VPWO
Push Pull / Open Drain, I =2mA,
EMR1 Register - BSZ bit = 0
OL
(3)
Push Pull / Open Drain, I =4mA,
EMR1 Register - BSZ bit = 1
OL
0.4
V
(3)
Weak Pull-up Current
P2[7:4]-P2[1:0]-P3[7:1]
P4.5-P4[3:1]-P5.3-P6[3:0]
P7[7:0] P8[7:0]-P9[7:0]
Bidirectional Weak Pull-up
30
100
200
400
µA
V
= 0V
OL
R
WPU
Weak Pull-up Current
P6[5:4]-AS-DS
Bidirectional Weak Pull-up
= 0V
100
– 1
450
+ 1
+ 1
µA
µA
µA
V
OL
Input/Tri-State,
0V < V < V
I
I/O Pin Input Leakage
LKIO
IN
DD
Input/Tri-State,
I
I/O Pin Open Drain Input Leakage
– 1
– 1
LKIOD
0V < V < V
IN
DD
I
A/D Conv. Input Leakage
Overload Current
Slew Rate Rise
+ 1
5
µA
LKA/D
(4)
(5)
(5)
I
mA
OV
SR
SR
70
70
mA/ns
mA/ns
R
Slew Rate Fall
F
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production. Hysteresis voltage between switching levels: characterization results - not tested.
(2) Hysteresis voltage between switching levels: characterization results - not tested.
(3) For a description of the EMR1 Register - BSZ bit refer to the External Memory Interface Chapter.
(4) Not 100% tested, guaranteed by design characterisation. The absolute sum of input overload currents on all port pins may not exceed
100 mA.
(5) Indicative values extracted from Design simulation.
289/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
(V = 5V ± 10%, T = –40°C to +105°C, unless otherwise specified)
DD
Symbol
A
(1)
Parameter
INTCLK
Typ
Max
Unit
45
60
2.5
mA
mA/MHz
(2)
I
Run Mode Current
24 MHz
DDRUN
14
22
0.9
mA
mA/MHz
I
WFI Mode Current
24 MHz
DDWFI
(3)
I
Low Power WFI Mode Current
4MHz / 32
400
600
10
µA
µA
µA
DDLPWFI
I
HALT Mode Current
-
-
DDHALT
(4)
I
Input Transient I Current
500
DDTR
DD
Note:
All I/O Ports are configured in bidirectional weak pull-up mode with no DC load, external clock pin (OSCIN) is driven by square wave external
clock.
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
(2) CPU running with memory access, all peripherals switched off.
(3) FLASH/EEPROM in Power-Down Mode.
(4) Measured in HALT Mode, forcing a slow ramp voltage on one I/O pin, configured in input.
290/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
FLASH / EEPROM SPECIFICATIONS
(V = 5V ± 10%, T = –40°C to +105°C, unless otherwise specified) (1)
DD
A
Parameter
Min
Typ
10
Max
Unit
µs
s
Byte Program
1200
128 kbytes Flash Program
64 kbytes Flash Sector Erase
128 kbytes Flash Chip Erase
Erase Suspend Latency
1.3
1.5
3
MAIN FLASH
1
30
s
s
15
µs
16 bytes Page Update
(1k EEPROM)
0.16
30
70
200
ms
ms
EEPROM
EEPROM Chip Erase
Flash Endurance 25°C
Flash Endurance -40°C +105°C
EEPROM Endurance
10000
3000
cycles
RELIABILITY
(2)
100000
15
cycles / sector
Years
Data Retention
Note:
(1) The full range of characteristics will be available after final product characterisation.
(2) Relationship computation between EEPROM sector cycling and single byte cycling is provided in a dedicated STMicroelectronics Appli-
cation Note (ref. AN1152).
FLASH / EEPROM DC & AC CHARACTERISTICS
(V = 5V ± 10%, T = –40°C to +105°C, unless otherwise specified)
DD
A
Symbol
Parameter
Test Conditions
Min
3
Max
4
Unit
V
(1)
(2)
V
Write Lock Supply Voltage
Read Lock Supply Voltage
CWL
V
1.5
2.5
V
CRL
V
V
= 5.5 V, T = –40°C,
A
DD
IDD1
IDD2
Supply Current (Read)
Supply Current (Write)
60
60
mA
mA
f
= 24 MHz
INTCLK
= 5.5 V, T = –40°C,
DD
A
f
= 24 MHz
INTCLK
IDD3
IDD4
TPD
Supply Current (Stand-by)
Supply Current (Power-Down)
Recovery from Power-Down
V
= 5.5 V, T = –40°C
100
10
µA
µA
µs
DD
DD
DD
A
V
= 5.5 V, T = 105°C
A
V
= 4.5 V, T = 105°C
10
A
Note:
(1) Below the min value the FLASH / EEPROM can never be written; above the max value FLASH/EEPROM can always be written.
(2) Below the min value the FLASH / EEPROM can never be read; above the max value FLASH/EEPROM can always be read.
291/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
EXTERNAL INTERRUPT TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
N°
Symbol
Parameter
Unit
(1)
Formula
Min
Low Level Minimum Pulse Width in Rising Edge
Mode
1
2
3
4
TwINTLR
TwINTHR
TwINTHF
TwINTLF
≥Tck+10
50
ns
ns
ns
ns
High Level Minimum Pulse Width in Rising Edge
Mode
≥Tck+10
≥Tck+10
≥Tck+10
50
50
50
High Level Minimum Pulse Width in Falling Edge
Mode
Low Level Minimum Pulse Width in Falling Edge
Mode
Note:
The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period.
The value in the right hand two columns shows the timing minimum and maximum for an internal clock at 24MHz (INTCLK).
Measurement points are V for positive pulses and V for negative pulses.
IH
IL
(1) Formula guaranteed by design.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
EXTERNAL INTERRUPT TIMING
292/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
WAKE-UP MANAGEMENT TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, , unless otherwise specified)
INTCLK
DD
N°
A
Load
Value
(1)
Symbol
Parameter
Unit
Formula
Min
Low Level Minimum Pulse Width in Rising Edge
Mode
1
2
3
4
TwWKPLR
TwWKPHR
TwWKPHF
TwWKPLF
≥Tck+10
≥ 50
ns
ns
ns
ns
High Level Minimum Pulse Width in Rising Edge
Mode
≥Tck+10
≥Tck+10
≥Tck+10
≥ 50
50
High Level Minimum Pulse Width in Falling Edge
Mode
Low Level Minimum Pulse Width in Falling Edge
Mode
50
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period.
The value in the right hand two columns show the timing minimum and maximum for an internal clock at 24MHz (INTCLK).
The given data are related to Wake-up Management Unit used in External Interrupt mode.
Measurement points are V for positive pulses and V for negative pulses.
IH
IL
(1) Formula guaranteed by design.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
WAKE-UP MANAGEMENT TIMING
WKUPn
n=0–15
293/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
RCCU CHARACTERISTICS
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
Input Threshold
3.2
V
V
V
V
RESET Input High Level
RESET Input Low Level
IHRS
Input Voltage Range
Input Threshold
V
+ 0.3
DD
2.4
V
ILRS
Input Voltage Range
– 0.3
– 1
V
RESET Input Hysteresis
RESET Pin Input Leakage
800
mV
HYRS
I
0V < V < V
+ 1
µA
LKRS
IN
DD
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
RCCU TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
T
T
RESET Input Filtered Pulse
50
ns
µs
µs
µs
FRS
RESET Input Non Filtered
Pulse
20
NFR
(2)
T
RESET Phase duration
20400 x T
RSPH
osc
DIV2 = 0
DIV2 = 1
10200 x T
20400 x T
osc
osc
T
STOP Restart duration
STR
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
(2) Depending on the delay between rising edge of RESET pin and the first rising edge of CLOCK1, the value can differ from the typical value
for +/- 1 CLOCK1 cycle.
Legend: T
= OSCIN clock periods.
osc
PLL CHARACTERISTICS
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
5
F
Crystal Reference Frequency
VCO Operating Frequency
Lock-in Time
2
6
MHz
MHz
µs
XTL
F
24
VCO
T
350 x Tosc 1000 x Tosc
PLK
(2)
PLL Jitter
0
1200
ps
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
(2) Measured at 24MHz (INTCLK). Guaranteed by Design Characterisation (not tested).
Legend: Tosc = OSCIN clock periods.
294/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
OSCILLATOR CHARACTERISTICS
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
5
Fundamental mode
crystal only
F
Crystal Frequency
2
MHz
OSC
g
Oscillator
1.77
1.2
2.0
3.8
mA/V
m
V
Clock Input High Level
Clock Input Low Level
External Clock
External Clock
V
+ 0.3
V
V
IHCK
DD
V
0.4
0.5
+ 1
5
ILCK
OSCIN/OSCOUT Pins Input
Leakage
0V < V < V
IN DD
(HALT/STOP)
I
– 1
µA
LKOS
T
Oscillator Start-up Time
ms
STUP
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
295/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
EXTERNAL BUS TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value (Note)
N°
Symbol
TsA (AS)
Parameter
Unit
Formula
Min Max
1
2
3
4
5
6
7
8
9
Address Set-up Time before AS ↑
Address Hold Time after AS ↑
AS ↑ to Data Available (read)
AS Low Pulse Width
Tck x Wa+TckH-9
TckL-4
12
17
45
16
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ThAS (A)
TdAS (DR)
TwAS
Tck x (Wd+1)+3
Tck x Wa+TckH-5
0
TdAz (DS)
TwDS
Address Float to DS ↓
DS Low Pulse Width
Tck x Wd+TckH-5
Tck x Wd+TckH+4
7
16
25
7
TdDSR (DR)
ThDR (DS)
TdDS (A)
DS ↓ to Data Valid Delay (read)
Data to DS ↑ Hold Time (read)
DS ↑ to Address Active Delay
DS ↑ to AS ↓ Delay
TckL+11
32
17
4
10 TdDS (AS)
11 TsR/W (AS)
12 TdDSR (R/W)
13 TdDW (DSW)
14 TsD(DSW)
15 ThDS (DW)
16 TdA (DR)
TckL-4
RW Set-up Time before AS ↑
DS ↑ to RW and Address Not Valid Delay
Write Data Valid to DS ↓ Delay
Write Data Set-up before DS ↑
Data Hold Time after DS ↑ (write)
Address Valid to Data Valid Delay (read)
AS ↑ to DS ↓ Delay
Tck x Wa+TckH-17
TckL-1
20
-16
5
-16
Tck x Wd+TckH-16
TckL-3
18
55
15
Tck x (Wa+Wd+1)+TckH-7
TckL-6
17 TdAs (DS)
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
prescaler value and number of wait cycles inserted.
The values in the right hand two columns show the timing minimum and maximum for an external clock at 24MHz, prescaler value of zero
and zero wait states.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width)
TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width)
P = clock prescaling value (=PRS; division factor = 1+P)
Wa = wait cycles on AS; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT)
Wd = wait cycles on DS; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT)
296/324
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ST92F120 - ELECTRICAL CHARACTERISTICS
EXTERNAL BUS TIMING
297/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
WATCHDOG TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
unless otherwise specified)
= 50pF, f = 24MHz, Push-pull output configuration,
DD
A
Load
INTCLK
Value
N°
Symbol
Parameter
Unit
(1)
Formula
Min
Max
167
ns
s
4 x (Psc+1) x (Cnt+1) x Tck
(Psc+1) x (Cnt+1) x T
2.8
1
TwWDOL
WDOUT Low Pulse Width
WDIN
333
167
ns
with T
≥ 8 x Tck
WDIN
ns
s
4 x (Psc+1) x (Cnt+1) x Tck
(Psc+1) x (Cnt+1) x T
2.8
2
TwWDOH
WDOUT High Pulse Width
WDIN
333
ns
with T
≥ 8 x Tck
WDIN
3
4
TwWDIL
TwWDIH
WDIN High Pulse Width
WDIN Low Pulse Width
≥ 4 x Tck
≥ 4 x Tck
167
167
ns
ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
watchdog prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and
maximum prescaler value and minimum and maximum counter value.
Measurement points are V
or V for positive pulses and V or V for negative pulses.
IH OL IL
OH
(1) Formula guaranteed by design.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
Psc = Watchdog Prescaler Register content (WDTPR): from 0 to 255
Cnt = Watchdog Couter Registers content (WDTRH,WDTRL): from 0 to 65535
T
= Watchdog Input signal period (WDIN)
WDIN
WATCHDOG TIMING
298/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
STANDARD TIMER TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
unless otherwise specified)
= 50pF, f = 24MHz, Push-pull output configuration,
INTCLK
DD
A
Load
Value
N°
Symbol
Parameter
Unit
(1)
Formula
Min
Max
167
ns
s
4 x (Psc+1) x (Cnt+1) x Tck
(Psc+1) x (Cnt+1) x T
2.8
(2)
1
TwSTOL
STOUT Low Pulse Width
STIN
(2)
ns
with T
≥ 8 x Tck
STIN
167
ns
s
4 x (Psc+1) x (Cnt+1) x Tck
(Psc+1) x (Cnt+1) x T
2.8
(2)
2
TwSTOH
STOUT High Pulse Width
STIN
(2)
ns
with T
≥ 8 x Tck
STIN
3
4
TwSTIL
TwSTIH
STIN High Pulse Width
STIN Low Pulse Width
≥ 4 x Tck
≥ 4 x Tck
(2)
(2)
(2)
(2)
ns
ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
standard timer prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and
maximum prescaler value and minimum and maximum counter value.
Measurement points are V
or V for positive pulses and V or V for negative pulses.
IH OL IL
OH
(1) Formula guaranteed by design.
(2) Onthis product STIN isnot availableas Alternate Functionbut itis internallyconnectedtoa preciseclocksourcedirectly derivedfromOSCIN.
Refer to RCCU chapter for details about clock distribution.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
Psc = Standard Timer Prescaler Register content (STP): from 0 to 255
Cnt = Standard Timer Couter Registers content (STH,STL): from 0 to 65535
T
= Standard Timer Input signal period (STIN).
STIN
STANDARD TIMER TIMING
299/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
EXTENDED FUNCTION TIMER EXTERNAL TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
(1)
N° Symbol
Parameter
Unit
Formula
Min
1
2
3
4
5
6
Tw
Tw
External Clock low pulse width (EXTCLK)
External Clock high pulse width (EXTCLK)
Input Capture low pulse width (ICAPx)
Input Capture high pulse width (ICAPx)
-
2 x Tck + 10
2 x Tck + 10
2 x Tck + 10
2 x Tck + 10
177
ns
ns
ns
ns
ns
ns
PEWL
-
PEWH
Tw
Tw
-
PIWL
PIWH
ECKD
-
Tw
Tw
Distance between two active edges on EXTCLK
Distance between two active edges on ICAPx
≥ 4 x Tck + 10
2 x Tck x Prsc +10
177
EICD
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
standard timer prescaler and counter programmed values.•
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, and minimum
prescaler factor (=2).
Measurement points are V for positive pulses and V for negative pulses.
IH
IL
(1) Formula guaranteed by design.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
Prsc = Precsaler factor defined by Extended Function Timer Clock Control bits (CC1,CC0) on control register CR2 (values: 2,4,8).
EXTENDED FUNCTION TIMER EXTERNAL TIMING
1
2
EXTCLK
5
3
4
ICAPA
ICAPB
6
300/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
MULTIFUNCTION TIMER EXTERNAL TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
N° Symbol
Parameter
Unit Note
Formula
Min
n x 42
n x 42
125
Max
(1)
(1)
1
2
3
4
Tw
External clock/trigger pulse width
External clock/trigger pulse distance
Distance between two active edges
Gate pulse width
n x Tck
n x Tck
3 x Tck
6 x Tck
-
-
-
-
ns
ns
ns
ns
CTW
Tw
Tw
CTD
AED
Tw
250
GW
LBA
Distance between TINB pulse edge and the fol-
lowing TINA pulse edge
(2)
5
6
Tw
Tck
42
0
-
-
ns
ns
Distance between TINA pulse edge and the fol-
lowing TINB pulse edge
(2)
(2)
Tw
LAB
7
8
Tw
Distance between two TxINA pulses
Minimum output pulse width/distance
0
-
-
ns
ns
AD
Tw
3 x Tck
125
OWD
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
standard timer prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz.
(1) n = 1 if the input is rising OR falling edge sensitive
n = 3 if the input is rising AND falling edge sensitive
(2) In Autodiscrimination mode
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
MULTIFUNCTION TIMER EXTERNAL TIMING
301/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
SCI TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f
= 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
N° Symbol
Parameter
Condition
Unit
Min
Max
1x mode
16x mode
1x mode
16x mode
1x mode
16x mode
1x mode
16x mode
f
f
/ 8
/ 4
MHz
MHz
s
INTCLK
INTCLK
F
Frequency of RxCKIN
RxCKIN shortest pulse
Frequency of TxCKIN
TxCKIN shortest pulse
RxCKIN
4 x Tck
2 x Tck
Tw
RxCKIN
s
f
f
/ 8
/ 4
MHz
MHz
s
INTCLK
F
TxCKIN
INTCLK
4 x Tck
2 x Tck
Tw
TxCKIN
s
DS (Data Stable) before
rising edge of RxCKIN
1
2
3
Ts
1x mode reception with RxCKIN
Tck / 2
ns
ns
ns
DS
TxCKIN to Data out
delay Time
1x mode transmission with external
Td
2.5 x Tck
D1
D2
clock C
< 50pF
Load
CLKOUT to Data out
delay Time
Td
1x mode transmission with CLKOUT
350
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
SCI TIMING
302/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
SPI TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
(1)
Value
N° Symbol
Parameter
Condition
Unit
Min
/ 128
Max
Master
Slave
f
f
f
/ 4
/ 2
INTCLK
INTCLK
INTCLK
f
t
SPI frequency
MHz
ns
SPI
0
Master
Slave
4 x Tck
2 x Tck
1
SPI clock period
SPI
2
3
t
Enable lead time
Enable lag time
Slave
Slave
40
40
ns
ns
Lead
t
Lag
Master
Slave
80
90
4
5
t
Clock (SCK) high time
Clock (SCK) low time
Data set-up time
ns
ns
ns
ns
ns
ns
SPI_H
Master
Slave
80
90
t
SPI_L
Master
Slave
40
40
6
t
SU
Master
Slave
40
40
7
t
Data hold time (inputs)
H
Access time (time to data active
from high impedance state)
8
t
0
120
240
A
Slave
Disable time (hold time to high im-
pedance state)
9
t
Dis
Master (before capture edge)
Slave (after enable edge)
Tck / 4
ns
ns
10
11
12
13
t
Data valid
V
120
Master (before capture edge)
Slave (after enable edge)
Tck / 4
0
ns
ns
t
Data hold time (outputs)
Rise time
Hold
Outputs: SCK,MOSI,MISO
(20% V to 70% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
t
Rise
DD
DD
L
Fall time
Outputs: SCK,MOSI,MISO
(70% V to 20% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
t
Fall
DD
DD
L
Note:
Measurement points are V , V , V and V in the SPI Timing Diagram.
OL
OH
IL
IH
(1) Values guaranteed by design.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
303/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
SPI Master Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
1
13
12
12
13
12
SCK
(OUTPUT)
4
5
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D6-OUT
D0-OUT
D7-OUT
11
10
VR000109
VR000110
VR000107
VR000108
SPI Master Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
1
13
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
SPI Master Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
1
13
SCK
(OUTPUT)
4
5
MISO
(INPUT)
D7-OUT
D6-OUT
D6-IN
D0-OUT
6
7
MOSI
(OUTPUT)
D0-IN
D7-IN
11
10
SPI Master Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
1
12
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
304/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
SPI Slave Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
2
1
12
3
13
11
SCK
(INPUT)
4
5
MISO HIGH-Z
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
8
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000113
SPI Slave Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
2
1
13
12
11
3
SCK
(INPUT)
4
5
MISO
HIGH-Z
8
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000114
SPI Slave Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
2
1
13
12
3
SCK
(INPUT)
4
5
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
10
11
9
MOSI
(INPUT)
D7-IN
D0-IN
7
6
VR000111
SPI Slave Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
2
1
13
12
3
SCK
(INPUT)
5
4
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
10
11
9
MOSI
(INPUT)
D7-IN
D0-IN
6
7
VR000112
305/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
I²C/DDC-BUS TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Protocol Specifications
Symbol
Parameter
Formula
Standard I²C
Fast I²C
Min Max
Unit
Min
2.5
0
Max
f
f
Internal Frequency (Slave Mode)
SCL clock frequency
2.5
0
MHz
INTCLK
100
400 kHz
SCL
Bus free time between a STOP
and START condition
T
T
4.7
1.3
0.6
µs
µs
BUF
SCL clock high period
4.0
HIGH
Standard Mode
Fast Mode
T
– 3 x Tck
HIGH
4.7
T
SCL clock low period
µs
LOW
2 x (T
– 3 x Tck)
1.3
0.6
HIGH
Hold time START condition. After this peri-
od, the first clock pulse is generated
T
T
T
+ Tck
4.0
4.7
µs
µs
HD:STA
SU:STA
LOW
Set-up time for a repeated START condi-
tion
T
+ T
–
LOW
HIGH
0.6
T
HD:STA
FREQ[2:0] = 000
FREQ[2:0] = 001
FREQ[2:0] = 010
FREQ[2:0] = 011
3 x Tck
4 x Tck
4 x Tck
10 x Tck
(1;2)
(1;2)
(1;3)
T
T
Data hold time
0
0
0.9
ns
ns
HD:DAT
SU:DAT
Data set-up time
(Without SCL stretching)
T
– T
HD:DAT
LOW
FREQ[2:0] = 000
7 x Tck
15 x Tck
15 x Tck
31 x Tck
(1)
(1)
250
100
Data set-up time
(With SCL stretching)
FREQ[2:0] = 001
FREQ[2:0] = 010
FREQ[2:0] = 011
(1)
(1)
(1)
T
T
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
1000
300
20+0.1Cb
20+0.1Cb
ns
ns
R
F
(1)
T
+ T
–
LOW
T
HIGH
T
Set-up time for STOP condition
Capacitive load for each bus line
4.0
0.6
ns
SU:STO
HD:STA
Cb
400
400
pF
Note:
(1) Value guaranteed by design
(2) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL
(3) The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
Cb = total capacitance of one bus line in pF
FREQ[2:0] = Frequency bits value of I²C Own Address Register 2 (I2COAR2)
306/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
I²C TIMING
SDA
t
t
t
t
SP
t
t
LOW
BUF
R
F
HD:STA
SCL
t
t
SU:STO
HD:STA
t
t
t
t
SU:STA
HD:DAT
HIGH
SU:DAT
P
S
Sr
P
307/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
J1850 BYTE LEVEL PROTOCOL DECODER TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Value
Symbol
Parameter
Receive Mode
Transmission Mode
Unit
Note
Min
0
Max
≤ 7
Nominal
-
(1)(2)
T
Symbols Filtered
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
F
(1)(2)
T
T
T
T
T
T
T
T
T
T
T
T
Invalid Bit Detected
Passive Data Bit “0”
Active Data Bit “0”
Passive Data Bit “1”
Active Data Bit “1”
Short Normalization Bit
Long Normalization Bit
Start Of Frame Symbol
End Of Data Symbol
End Of Frame Symbol
Break Symbol
> 7
≤ 34
≤ 96
≤ 163
≤ 163
≤ 96
≤ 96
≤ 163
≤ 239
≤ 239
-
-
IB
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
> 34
> 96
> 96
> 34
> 34
> 96
> 163
> 163
> 239
> 239
> 280
64
P0
128
128
64
A0
P1
A1
64
NBS
NBL
SOF
EOD
EOF
BRK
IDLE
128
200
200
280
300
300
-
Idle Symbol
-
Note:
(1) Values obtained with internal frequency at 24 MHz (INTCLK), with CLKSEL Register set to 23.
(2) In Transmission Mode, symbol durations are compliant to nominal values defined by the J1850 Protocol Specifications.
(3) All values are reported with a precision of ±1 µs.
J1850 PROTOCOL TIMING
T IDLE
T SOF
T P0 T A0
T P1 T A1
T EOD
T NBS
T EOF
VPWO
T IDLE
T EOF
T SOF
T P0 T A0
T P1 T A1
T EOD
T NBL
VPWO
308/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
A/D EXTERNAL TRIGGER TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Value (Note)
N° Symbol
Parameter
Unit
Formula
1.5 x Tck
1.5 x Tck
Min.
62.5
Max.
1
2
3
Tw
External trigger pulse width
-
-
-
ns
ns
µs
LOW
Tw
Tw
External trigger pulse distance
62.5
HIGH
External trigger active edges distance
138 x n x Tck
n x 5.75
EXT
STR
0.5 x Tck
1.5 x Tck
4
Td
EXTRG falling edge and first conversion start
20.8
62.5
ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
standard timer prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2*OSCIN period when OSCIN is divided by 2;
OSCIN period / PLL factor when the PLL is enabled.
n = number of autoscanned channels (1 ≤ n ≤ 8)
A/D EXTERNAL TRIGGER TIMING
309/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
A/D CHANNEL ENABLE TIMING TABLE
(V = 5V ± 10%, T = –40°C to +105°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value (Note)
N° Symbol
Parameter
Unit
Formula
138 x n x Tck
Min.
Max.
1
Tw
CEn Pulse width
n x 5.75
-
µs
EXT
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
standard timer prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2*OSCIN period when OSCIN is divided by 2;
OSCIN period / PLL factor when the PLL is enabled.
n = number of autoscanned channels (1 ≤ n ≤ 8)
A/D CHANNEL ENABLE TIMING
310/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
A/D ANALOG SPECIFICATIONS
(V = 5V ± 10%, T = –40°C to +105°C, f
= 24MHz, unless otherwise specified)
DD
A
INTCLK
Typical
Parameter
Minimum
Maximum
Units (1)
INTCLK
INTCLK
µs
Notes
(2)(6)
Conversion time
Sample time
138
85
60
8
(6)
(6)
Power-up time
Resolution
8
bits
Monotonicity
GUARANTEED
No missing codes
Zero input reading
Full scale reading
Offset error
GUARANTEED
(6)
(6)
00
Hex
Hex
LSBs
LSBs
LSBs
LSBs
LSBs
kΩ
FF
0.5
0.6
0.6
1.0
(1)(4)(6)
(4)(6)
(4)(6)
(4)(6)
(4)(6)
(3)(5)(6)
(5)(6)
(6)
0.3
Gain error
DLE (Diff. Non Linearity error)
ILE (Int. Non Linearity error)
TUE (Absolute Accuracy)
Input Resistance
–1.0
1.0
2.7
1.3
1.4
0.8
Hold Capacitance
pF
Input Leakage
±1
µA
Note:
(1) “1LSBideal” has a value of AV /256
DD
(2) Including sample time
(3) This is the internal series resistance before the sampling capacitor
(4) This is a typical expected value, but not a tested production parameter.
If V(i) is the value of the i-th transition level (0 ≤ i ≤ 254), the performance of the A/D converter has been evaluated as follows:
OFFSET ERROR= deviation between the actual V(0) and the ideal V(0) (=1/2 LSB)
GAIN ERROR= deviation between the actual V(254) and the ideal V(254) - V(0) (ideal V(254)=AV -3/2 LSB)
DD
DNL ERROR= max {[V(i) - V(i-1)]/LSB - 1}
INL ERROR= max {[V(i) - V(0)]/LSB - i}
ABS. ACCURACY= overall max conversion error
(5) Simulated value, to be confirmed by characterisation.
(6) The specified values are guaranteed only if an overload condition occurs on a maximum of 2 non-selected analog input pins and the
absolute sum of input overload currents on all analog input pins does not exceed ±10 mA.
311/324
1
ST92F120 - ELECTRICAL CHARACTERISTICS
Figure 124. A/D Conversion Characteristics
Offset Error OSE
Gain Error GE
255
254
253
252
251
250
(2)
code
out
7
(1)
6
5
(5)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
4
3
(4)
)
(3
1 LSB (ideal)
2
1
0
1
2
3
4
5
6
7
250 251 252 253 254 255 256
Vin(A) (LSBideal
)
Offset Error OSE
VR02133A
312/324
1
ST92F120 - PACKAGE MECHANICAL DATA
12 PACKAGE MECHANICAL DATA
Figure 125. 100-Pin Plastic Quad Flat Package
mm
inches
D
A
Dim.
Min Typ Max Min Typ Max
D1
D2
A2
A1
A
3.40
0.134
0.020
A1 0.25
0.50 0.010
A2 2.50 2.70 2.90 0.098 0.106 0.114
b
b
c
0.22
0.11
0.40 0.009
0.23 0.004
0.016
0.009
D
23.20
20.00
18.85
17.20
14.00
12.35
0.65
0.913
0.787
0.742
0.677
0.551
0.486
0.026
e
D1
D2
E
E
E2 E1
E1
E2
e
L
c
L
0.73 0.88 1.03 0.029 0.035 0.041
1.60 mm
0×- 7×
Number of Pins
N
100
313/324
1
ST92F120 - DEVICE ORDERING INFORMATION
13 DEVICE ORDERING INFORMATION
Figure 126. Device Types
ST92 F 120 J V 1 Q 6
Temperature Code:
6: -40° C to 85° C
7: -40° C to 105° C
Package Type:
Q: PQFP
Memory Size:
1: 128K
9: 60K
Pin Count:
V: 100 pins
R: 64 pins
Feature 1: JBLPD
No Character: None
J: J1850
ST Sub-family
Version:
F: Flash
ST Family
314/324
1
ST92F120 - SUMMARY OF CHANGES
14 SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
1.2
Added History pages.
Page
1.1
Updated ARC, STIM, WUIMU, SPI7, DDC, FEE.SCI replaced ZAD by ADC8
Changed order of on-chip peripheral chapters.
In phrase "66 (80 ...) I/O bits"; replaced "bits" with "pins".
In phrase "8-bit Analog to Digital..." replaced with "Two 8-bit Analog to Digital..."
1
4
Second col. In phrase "In addition, there is an 8 channel..." replaced with "In addi-
tion, there are two 8 channel..."
At the end of the sentence, added: "On QFP80 version, only 10 input channels are
available."
End of second col.
In phrase "Low power Run, Wait for interrupt, and STOP modes are also av." re-
placed with: "Low power Run (SLOW), Wait for Interrupt, low power Wait for inter-
rupt, HALT and STOP modes are also available."
1.2
12/01/97
In picture:
. Added in RCCU output signals the new: CLOCK2/8
. Removed from A/D conv. blocks the labels "zad_0" and "zad_1"
. Added in A/D CONV. 1 signals the EXTRG item
replaced INT3:0 by INT 6:0
5
Same as Page 5.
. Added RWN in the CPU signals (bold/no italic) leaving the italic one
Changed the picture as follow:
6
7
. Added in RCCU output signals the new: CLOCK2/8
. Removed from A/D conv. block the labels "zad"
. Duplicated A/D block like at page 5 (same input signals)
replaced INT3:0 by INT 6:0
315/324
1
ST92F120 - SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
- Changed the picture as follows:
. Added in RCCU output signals the new: CLOCK2/8
. Removed from A/D conv. block the labels "zad"
. Duplicated A/D block like at page 6 (same input signals)
. Added RWN in the CPU signals (bold/no italic) leaving the italic one
replaced INT3:0 by INT 6:0
- For consistency with block diagram:
ASN instead of AS+overbar
Page
8
DSN instead of DS+overbar
RWN instead of R/W+overbar on W
RESETN instead of RESET+overbar
HW0SW1 instead of HW0_SW1
ST92E120 twice replaced with ST92E120/F120
Inside ASN item (at the end) removed the last sentence "Under program.."
Inside DSN item (at the end) removed the last sentence "It can be..."
Inside RWN item (at the end) removed the last sentence "It can be..."
Added: "On QFP100 version, RWN is also available as true pin."
VDD item: Added "Two internally connected pins are available"
VSS item: Added description "Two internally connected pins are available"
Added a new item for VPP:
9
VPP. High voltage Power Supply for Eprom memory (only on ST92E120; on
ST92F120 the pin is not connected).
P2.0...P9.7 item: highlighted that on QFP80, only
P8.0-P8.1 is available and P9 is not available at all
316/324
1
ST92F120 - SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
Added alternate functions to pin labels. Swapped OSCIN OSCOUT
Put a note saying:" NC = Not Connected (no physical bonding wire)"
Same as Page 10. Shifted labelling on pins 1-8, 100 and 73-81.
10
Two extra tables inserted before the AF table. The first table is the list of Power
Supply pins with reference to the package.
11
12
The second is the dedicated pins table (ASN/DSN/RWN/RESET/OSCIN/OSCOUT
/HW0SW1...).
In AF table: WPU in the header substituted with "Weak Pull-up".
AF table duplicated: the first for ST92E120 and the second
for ST92F120. The same done for Power Supply and dedicated pins tables.
P21: TIMPB0: replaced with TINPB0
P23:"Output A": replaced with "Output B"
P25: TIMPB1: replaced with TINPB1
P46: Cleared the cells where "SDAI" and "DDC - I2C Input Data"
Replaced "SDAO" with "SDAI/SDAO
Replaced "O" with "I/O"
Replaced "DDC - I2C Data Output" with "DDC - I2C Data"
P64: Replaced "SCHMITT TRIGGER" with "HIGH HYST. S.T."
In the table of F120 only:
P22: Replaced YES with NO
P23: Replaced YES with NO
In AF table, added new column giving the conf. after reset.
For E120 table, filled up all cells (one for each Pxy item), with BID-WPU.
For F120 table, filled up P8.2-P8.7 and P9 cells with BID-WPU; all the others are
INPUT.
P6.0: added CLOCK2/8
P6.1: replaced INT1 by INT6
P7.-P7.7 and P8.0-P8.7 Removed names in brackets and added ADC0 and ADC1
to descriptions
4.5 Added A/D0 and A/D 1 ext trigger
Removed Note about Port0 and Port1
23
- "Internal Weak Pull-up" section.
Removed the first sentence: "The internal ... 57 kohm."
"TTL/CMOS Input" section.
16
17
Added a cross ref to the current paragraph 9.4 (INPUT/OUTPUT BIT CONFI-
GURATION) at the end of the paragraph:
317/324
1
ST92F120 - SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
24
Replaced ST92E120 with ST92E120/F120
18
In WAIT FOR INTERRUPT MODE item, removed the sentence:
"Under this mode,... (LP WFI)."
Created a new item: "LOW POWER WAIT FOR INTERRUPT" with the fol-
lowing
description:
"Combining SLOW Mode and Wait For Interrupt mode it is possible to
reduce the power consumption by more than 80%."
Second column: "Watchdog counter ..." sentence rewritten.
At the end of STOP MODE item, added:
"The counter is active only when the oscillation has already taken
place: this means that 1-2 ms must be added to take into account of
the first phase of the oscillator restarting."
26
27
20
21
- Fig. 10: PAGE REGISTERS: replaced with PAGED REGISTERS
- Second col.
Last sentence "A table of available...": removed.
End of first col."...into four16 Kbytes pages.". Removed space.
End of second col.Chapter 3: cross ref updated
35
44
29
38
Replaced the Chapter 3 new doc specs Added a register and Section on protection
strategy).
59
60
50
51
Moved para. on register map to page 63
- A note in the picture added: "RAM addresses are repeated each 4 Kbytes inside
the segment 20h"
62
53
- FLASH OTP - 128 bytes: the starting address 210000h
Replaced the address with 211F80h
Same as Page 51
63
64
54
55
ZAD0 and ZAD1 removed and replaced with "Res."
Added registers for AD0 and AD1:
. AD0 - Page 63(3F) All registers from R240 to R255
. AD1 - Page 61(3D) All registers from R240 to R255
Note removed.
65
73
Added detailed register map (7 pages)
Changed table
57
63
79
Changed 2 tables
80
64
Changed figure
86
65
WUIMU section revised (edited text throughout)
103
104
112
248
249
86
Changed figure: added 16 divider to CK128 input to STIM and P6.0 output with 8
div.
87
95
Changed figure: like previous page
226
227
Changed values in two tables
Added rows in second table. Changed RESET overbar to RESETN.
Changed P2.2 and P2.3 to Pure OD output, no WPU
1.3
18
12/16/97
In Column 2: “I/O pins are set to Bidirectional Weak-Pull-Up or High impedance in-
put. See Table of I/O port alternate functions.
112
318/324
1
ST92F120 - SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
1.4
10
Replaced ST9_DDC by ST9 I2C macrocell. Updated ST9_FEE, ST9_DMA,
ST9MFT, ST9_WUIMU macrocells to new rev levels. Removed references to DDC
throughout document
02/06/98
10
11
15
Removed WKU3, ICAPB1, ICAPA0
Removed ICAPA0
Added footnote **ST92F120 only. Removed P6.6, 4.1 and 3.1. Added WKUP”**,
ICAPB1** and ICAPA0**. Inserted VDD VSS on pins 11,12 and 54,55 Swapped
VDD/VSS on pins 76,75
16
Added footnote **ST92F120 only. Removed P6.6, 4.1 and 3.1. Added *to WKUP3/
P6.7, ICAPB1/P4.1 . Added WKUP”**, ICAPB1** and ICAPA0** Inserted 2x VDD
VSS Swapped VDD/VSS on pins 93,92
17
19
20
22
24
25
66
70
5,7
6,8
9
Added 2x VDD/VSS to table 1
Removed P3.0
Removed P6.6. Moved WKUP3 from P6.7 to P7.4
Added 2x VDD/VSS to table 3
Added ICAPA0 to P3.2. Removed P3.0. Moved ICAPB1 from P4.1 to P4.3
Moved WKUP 3 from P6.7 to 7.4. Removed P6.6
Changed DDC to I2C
Changed DDC to I2C. Changed I2C register names
Removed P3.0, P4.1, P6.7, P6.6
1.5
2/18/98
Removed P3.0, P6.6
Updated list of I/O lines
19
Changed P3.2 to Input
Changed P3.7 to YES Weak Pull-up
Changed P4.4 to NO Weak Pull-up
Changed P4.5 to YES Weak Pull-up
Changed P5.2 to NO Weak Pull-up
Changed P5.3 to YES Weak Pull-up
Changed P5.7 to NO Weak Pull-up
Table format problem corrected
20
21-22
247
In VOL item, replaced IOH by IOL.
Changed total I/O pins to 62 and 78. Changed 30MHz to 25MHz
Added paragraph on EMC features
Removed comment "ST92F120 only"
1.6
1,4
9
10
11
Removed comment "ST92F120 only" and removed ICAPB1 from P4.1 and WKUP3
from P6.7
14
15
Added ICAPA0 to P3.2 and ICAPB1 to P4.3 removed ICAPB1 from P4.1
Change P6.4 removed hi hys note from Schmitt Trigger. Removed WKUP3 from
P6.7
16
19
Added WKUP3 To P7.4
SDAI/SDAO renamed SDA, SCLI/SCLO renamed SCL. Added note 1 to Schmitt
Trigger
20
Added note 2 to Schmitt Trigger P6.4
65,67
Changed Wakeup register mapping to page 59
319/324
1
ST92F120 - SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
1.7 Page Page Removed ST92E120 information. Added JBLPD, updated RCCU, INT, FEE, WDG,
STIM, EFT, I2C, Ext Mem I/F, and Electrical characteristics
1.6
1.7
1
1
Changed 25 MHz to 24 MHz, added J1850 feature. Removed EPROM version. Add-
ed device summary.
2-3
4
2-6
7
Added 1 level to table of contents
Changed 25 MHz to 24 MHz, added J1850 feature.
Removed E120 diagrams
5-6
8
-
9
Add JBLPD, removed P6.7 added CLOCK2
9
10-15 Expanded Pin description detail. Added VPWO
10
11
-
Removed E120 diagrams
16
Removed note on E120, duplicate SCK removed on P3.7 and WKUP1 corrected to
WKUP5 on P5.0
12-17
17
-
Removed E120 table.
18
Added VWO to table 2 and section 1.3.5 using I/O AF. Added P0 and P1 to gen pur-
pose I/O para at bottom of first col.
20
22
61
21
22
-
Added VPWI to P6.5
Added CLOCK2 to P9.6
Removed E120 memory map
62-64 61-63 Changed Flash reg from 3 to 4 bytes, and Testflash sector from 21 to 23. Added
Flash sector labels.
65
64
Changed WU reg. page from 59 to 57, added JBLPD to page 23
66-73 65-72 Added page ref in right column. Changed WU reg. page from 59 to 57, added
JBLPD to page 23
renamed MFT registers FLAGR, ICR and IVR to T_FLAGR, T_ICR, T_IVR
renamed SCI registers IVR, ISR to S_IVR, S_ISR
renamed ADC registers ICR, IVR to AD_ICR, AD_IVR
MEMSEL bit, bit 4 of EMR2, change to 1 (Reset value=1Fh).
126
1.8 Page Page
1.7 1.8
121
04/30/99
Updated description of DMA in MFT and SCI chapters
1-11 Removed PFQ80
Added TQFP64
Overbar format applied to active low pin names
16-23 CTS changed to RTS
I/O table format changed.
112 Stop mode description changed. Removed table of register reset values.
287-289 Electrical characteristics added for IINJ RTHJA, VIH/VIL VHYS for Schmitt trigger
320/324
1
ST92F120 - SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
1.9 Page Page
06/04/99
1.8
1
1.9
1
Changed V to R on TQFP64 devices in device summary;
8
8
Changed figure caption ”JR instead of V9T”. Added extra memory sizes and option-
al J1850 block
9
9
Same changes as page 8 plus added note to SCI1 “on some versions only”
16
16
Added TXCAN0 and RXCAN0 with note. Changed note to VPP and VPWO. Added
VPWI to P6.5. Added VREG to pin 28
17
17
18
Added TXCAN0, RXCAN0, TXCAN1 and RXCAN1 with note. Added note to VPP.
Added VREG to pin 31 and 43
18
109
-
Added figure for Vreg. Added Vreg in table 1. Removed “not used” from VPP
109 Removed Notes on Ceramic Resonator from line three
110 Added 1 new page on Ceramic resonators
288 Added ESD susceptibility 2000V
287
289
290 Added note to describe typical values. Changed TBD to 10 mA in note for IOV. Add-
ed values to RWPU.
290
292
291 Changed typ and max values. Added max values per Mhz. Added note about run
mode.
293 Replaced x by 10 in formula. Added ≥ sign. Added min values. Added note “formula
guaranteed by design” Added note “measurement points are ....”
293
294
297
294 Same changes as previous table
295 Added TNFR . Changed value of TPLK typ. and PLL jitter.
299 Added note “formula guaranteed by design” Added note “measurement points are
....”
298
299
300 Added note “formula guaranteed by design” Added note “measurement points are
....”
301 Added note “formula guaranteed by design” Added note “measurement points are
....” Removed TEXTCLK Added 10 in formula to TWECKD and TWEICD. Changed
min values for these parameters.
302
305
306
310
304 Added note “values guaranteed by design”
307 Removed VIL and VIH. Replaced TBD by specified values.
308 Added max values for TR and TF
312 Changed values of offset error Moved values for DLE ILE and TUE from typ to max.
321/324
1
ST92F120 - SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
2.0 Page Page
09/08/99
1.9
2.0
Updated ST9_SCI and ST9_MFT macrocells
1
1
Changed minimum instruction time (83 ns)
63
66
63
66
Table 16; R248/Page 9: changed “Reserved” to “MFT0 and MFT1”
Table 17: Changed Register Names for R244, R245, R246, R247 (MFT1 block) and
R240, R241, R242 and R243 (MFT0 block)
Changed reset values for TCR1, T_ICR1, OACR1, OBCR1, TCR0, T_ICR0,
OACR0, OBCR0
67
68
67
68
I2C block: Changed R254 to R255 for I2CIMR and added I2CECCR register (R254)
Changed reset value for PRLR (JBLPD block)
107
121
151
158
180
289
107 Added description of bit 1
121 Changed reset value and comment on Bit 4 of EMR2
151 10.3.5 chapter (Register description): added note
158 Removed EFT2 and EFT3
180 Changed R254 to R255 for IDMR
290 Added “Input Threshold” typical values and removed TBD for V and V
IH
IL
For V
: Removed min and max values. Changed TBD to typical values
HYS
290
291
295
291 In note 4: 100mA instead of 10mA
292 For I
: Removed TBD (max value) and added typical value
296 “RCCU characteristics” table: added “input threshold” typical values for V
DDTR
and
IHRS
V
; Removed TBD for min and max values. Changed TBD to 800 for V
typ-
ILRS
HYRS
ical value
296
300
301
303
307
297 Changed TBD to values. Changed -0.3 to 0.4 for V
301 (2) instead of (1) for note 2
302 Removed max values; Changed TBD to 2Tck + 10
304 Changed TBD to 350
Min value
ILCK
308 Changed TBD to values
2.1 Page Page
2.0
2.1
Changed document status (“preliminary data” instead of “product preview”)
Added V
description
Figure 9, added pin numbers
10
17
24
10
17
24
REG
Changed Halt mode description
01/31/00
119
273
290
119 8.2.7 section, removed Warning
276 EOFM_M instead of EOF_M
293 Removed min values (0.7 x V ) for V ; Removed max values (0.8) for V
DD
IH
IL
Changed 900 to 600 for V
(Standard Schmitt Trigger)
HYS
293
296 Flash/EEPROM Specifications Table: Added one row (flash endurance -40°C
+105°C)
2.2
Removal of TQFP64 package and 36K Flash Memory
8
1.1
3.2
4.3
5.2
8.3
11
TQFP64 Version deleted
45
Modification of Flash Memory Structure
Location of Reset Vector
59
4 Sept 00
72
Ext. Watchdog/Reset Vectors
120
296
Bit 5: Upper/lower Memory Access
Max. EEPROM Parameter values modified
322/324
1
ST92F120 - SUMMARY OF CHANGES
Rev. Page Section
Main changes
Date
2.3
Addition of TQFP100 Package
V
V
changed to V
PP
33
TEST
changed to V
REG
8 Dec 00
“On future versions” added for V
REG
Removed “ST9OLD” references (in EMR1 register description on page 115)
1.1.3 Addition of “Flash and E3PROM Memories” section
1.3
Updated Figure 3, Figure 4 and Figure 5.
3.7.1 Replaced Section 3.7.1 on page 56 by “Code Update Routine” on page 52
7.6
Added Figure 55
10.4 Added Note on Bi Capture mode on using A0 bit in MFT Section 10.4.2.11
7
2.4
11
56
111
163
295
292
318
319
06 Mar 01
11
11
12
13
Reference to AN1102 changed to AN1152 on page 295.
Added V min and V max values
IH
IL
Updated package mechanical data
Updated Figure 126 (temperature code).
2.5
Deletion of TQFP100 Package.
Added WDIN on P5.3
Changed EEPROM size for 60K devices.
Changed section 3 on page 39.
Added one note in section 3.7.1 on page 52.
Changed section 10.3 on page 135: removed references to the 3 separate interrupt
channels (ICI, OCI and TOI), not present on the ST92F120.
In section 10.7.4.1 on page 219:
changed “address matched” section,
changed “slave revceiver” section: removed “both holding the SCL line low)
changed “slave transmitter” section: added “except on EV3-1)
changed “how to release the SDA/SCL lines” section: added one sentence (“check
that...”)
02 Aug 01
Changed note in section 10.7.5 on page 224: “The error event interrupt pending
bit...while the error event flags are set” instead of “... until the error event flags are
set”.
Swapped 0 and 1 for I2CSR.DMASTOP bit.
Changed V
in Absolute Maximum Ratings table on page 287.
INOD
Changed Thermal Characteristics value on page 287.
Changed AV min value in recommended operating conditions table on page 287.
DD
Changed V in DC electrical characteristics value
IH
2.6
Changed status of the document: “datasheet” instead of “preliminary data”
Replaced Bootrom by TestFlash in descriptions
3.2.1 Changed Table 7 and Table 8
39
40
3
51
3.6.1 Added note on NVWPR register description
55
56
57
4.2
4.2
4.2
Changed Figure 27
Changed Figure 28
Changed Figure 29
12 Sept 02
204
10.6 SPI section: changed register names: SPCR instead of CR, etc
206 10.6.4.1 Changed SPIF clearing sequence description
210 10.6.4.4 Changed Figure 103
211 10.6.4.5 Changed MODF clearing sequence description
288
306
11
11
Changed DC electrical characteristics table (V , V , V )
Changed I²C/DDC-bus Timing Table
IH IL I
323/324
1
ST92F120 - SUMMARY OF CHANGES
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
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324/324
1
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