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ST92F250CV2Q3 [STMICROELECTRONICS]

16-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, PLASTIC, QFP-100;
ST92F250CV2Q3
型号： ST92F250CV2Q3
厂家： ST    ST
描述：

16-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
文件： 总12页 (文件大小：97K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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ST92F124/ST92F150/ST92F250  
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,  
3 TM  
E
(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD  
DATA BRIEFING  
■ Memories  
– Internal Memory: Single Voltage FLASH up to 256  
3 TM  
Kbytes, RAM up to 8Kbytes, 1K byte E  
ed EEPROM)  
(Emulat-  
– In-Application Programming (IAP)  
– 224 general purpose registers (register file) availa-  
ble as RAM, accumulators or index pointers  
TQFP64  
14x14  
PQFP100  
14x20  
■ Clock, Reset and Supply Management  
– Register-oriented 8/16 bit CORE with RUN, WFI,  
SLOW, HALT and STOP modes  
TQFP100  
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range  
– PLL Clock Generator (3-5 MHz crystal)  
– Minimum instruction time: 80 ns (25 MHz int. clock)  
■ Interrupt Management  
14x14  
– One or two full I C multiple Master/Slave Interfaces  
supporting Access Bus  
– One or two CAN 2.0B (150 version only) Active inter-  
faces with:  
– 80, 77 or 48 I/O pins (depending on device)  
– 4 external fast interrupts + 1 NMI  
– Up to 16 pins programmable as wake-up oraddition-  
al external interrupt with multi-level interrupt handler  
– Up to 1 MBit/s communication speed  
– 3 Transmit Mailboxes with priority configuration  
by software  
■ Timers  
– 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-  
er (activated by software or by hardware)  
– 16-bit Standard Timer that can be used to generate  
a time base independent of PLL Clock Generator  
– Two 16-bit independent Extended Function Timers  
(EFTs) with Prescaler, 2 Input Captures and two  
Output Compares (100-pin devices only)  
– Two 16-bit Multifunction Timers, with Prescaler, 2 In-  
put Captures and two Output Compares  
– Enhanced Filtering mechanism  
– 2 prioritized FIFO receive schemes  
– Time-Triggered Communication support  
■ DMA controller for reduced processor overhead  
■ 10-bit Analog to Digital Converter allowing up to 16  
input channels on 100-pin devices or 8 input channels  
on 64-pin devices  
■ Instruction Set  
– Rich Instruction Set with 14 Addressing Modes  
■ Communication Interfaces  
– Division-by-zero trap generation  
■ Development Tools  
– Serial Peripheral Interface (SPI) with Selectable  
Master/Slave mode  
– Versatile Development Tools, including Assembler,  
Linker, C-Compiler, Source Level Debugger, Real  
Time Operating System (OSEK OS, CMX) and CAN  
drivers  
– One Multiprotocol Serial Communications Interface  
with asynchronous and synchronous capabilities  
– One asynchronous Serial Communications Interface  
(on 100-pin versions only)  
– J1850 Byte Level Protocol Decoder (JBLPD)  
(on F150J versions only)  
– Hardware Emulator, Flash Programming Boards  
DEVICE SUMMARY  
Features  
ST92F124R9  
ST92F150C(R/V)1  
ST92F150JV1 ST92F150JDV1 ST92F250CV2  
FLASH - bytes  
60K  
2K  
128K  
256K  
8K  
RAM - bytes  
4K  
6K  
3 TM  
E
- bytes  
1K  
2 MFT, 0/2 EFT,  
STIM, WD  
Timers  
2 MFT, STIM, WD  
2 MFT, 2 EFT, STIM, WD  
Serial Interface  
ADC  
Network Interface  
Temp. Range  
Packages  
SCI, SPI, I C  
8 x 10 bits  
-
1/2 SCI, SPI, I C  
8/16 x 10 bits  
2 SCI, SPI, 2 I C  
16 x 10 bits  
2 CAN, J1850  
CAN  
J1850  
o
CAN  
o
o
o
-40 C to 85 C or -40 C to 125 C  
TQFP64  
P/TQFP100 and TQFP64 PQFP100  
P/TQFP100  
Rev. 1.1  
April 2002  
1/12  
This is preliminary information on a new product nowin development. Details are subject to change without notice.  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
1 GENERAL DESCRIPTION  
1.1 INTRODUCTION  
which includes the control and status registers of  
the on-chip peripherals.  
The ST92F124/F150/F250 microcontroller is de-  
veloped and manufactured by STMicroelectronics  
using a proprietary n-well HCMOS process. Its  
performance derives from the use of a flexible  
256-register programming model for ultra-fast con-  
text switching and real-time event response. The  
intelligent on-chip peripherals offload the ST9 core  
from I/O and data management processing tasks  
allowing critical application tasks to get the maxi-  
mum use of core resources. The new-generation  
ST9 MCU devices now also support low power  
consumption and low voltage operation for power-  
efficient and low-cost embedded systems.  
1.1.2 External Memory Interface  
100-pin devices have a 22-bit external address  
bus allowing them to address up to 4M bytes of ex-  
ternal memory. 64-pin devices have an 11-bit ex-  
ternal address bus for addressing up to 2K bytes.  
1.1.3 On-chip Peripherals  
Two 16-bit Multifunction Timers, each with an 8 bit  
Prescaler and 12 operating modes allow simple  
use for complex waveform generation and meas-  
urement, PWM functions and many other system  
timing functions by the usage of the two associat-  
ed DMA channels for each timer.  
1.1.1 ST9+ Core  
On 100-pin devices, two Extended Function Tim-  
ers provide further timing and signal generation  
capabilities.  
The advanced Core consists of the Central  
Processing Unit (CPU), the RegisterFile, the Inter-  
rupt and DMA controller, and the Memory Man-  
agement Unit. The MMU allows a single linear ad-  
dress space of up to 4 Mbytes.  
A Standard Timer can be used to generate a sta-  
ble time base independent from the PLL.  
2
2
An I C interface (two in the ST92F250) provides  
Four independent buses are controlled by the  
Core: a 22-bit memory bus, an 8-bit register data  
bus, an 8-bit register address bus and a 6-bit inter-  
rupt/DMA bus which connects the interrupt and  
DMA controllers in the on-chip peripherals with the  
core.  
fast I C and Access Bus support.  
The SPI is a synchronous serial interface for Mas-  
ter and Slave device communication. It supports  
single master and multimaster systems.  
A J1850 Byte Level Protocol Decoder is available  
(on some devices only) for communicating with a  
J1850 network.  
This multiple bus architecture makes the ST9 fam-  
ily devices highly efficient for accessing on and off-  
chip memory and fast exchange of data with the  
on-chip peripherals.  
The bxCAN (basic extended) interface supports  
2.0B Active protocol. It has 3 transmit mailboxes, 2  
independent receive FIFOs and 8 filters.  
The general-purpose registers can be used as ac-  
cumulators, index registers, or address pointers.  
Adjacent register pairs make up 16-bit registers for  
addressing or 16-bitprocessing. Although the ST9  
has an 8-bit ALU, the chip handles 16-bit opera-  
tions, including arithmetic, loads/stores, and mem-  
ory/register and memory/memory exchanges.  
In addition, there is an 16 channel Analog to Digital  
Converter with integral sample and hold, fast con-  
version time and 10-bit resolution. In the 64-pin  
version only 8 input channels are available.  
There is one Multiprotocol Serial Communications  
Interface with an integral generator, asynchronous  
and synchronous capability (fully programmable  
format) and associated address/wake-up option,  
plus two DMA channels.  
The powerful I/O capabilities demanded by micro-  
controller applications are fulfilled by the  
ST92F150/F124 with 48 (64-pin devices) or 77  
(100-pin devices) I/O lines dedicated to digital In-  
put/Output and with 80 I/O lines by the ST92F250.  
These lines are grouped into up to ten 8-bit I/O  
Ports and can be configured on a bit basis under  
software control to provide timing, status signals,  
an address/data bus for interfacing to the external  
memory, timer inputs and outputs, analog inputs,  
external interrupts and serial or parallel I/O. Two  
memory spaces are available to support this wide  
range of configurations: a combined Program/  
Data Memory Space and the internal Register File,  
On some devices, there is an additional asynchro-  
nous Serial Communications interface.  
Finally, a programmable PLL Clock Generator al-  
lows the usage of standard 3 to 5 MHz crystals to  
obtain a large range of internal frequencies up to  
25MHz. Low power Run (SLOW), Wait For Inter-  
rupt, low power Wait For Interrupt, STOP and  
HALT modes are also available.  
2/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 1. ST92F124R9: Architectural Block Diagram  
FLASH  
60 Kbytes  
Ext. MEM.  
ADDRESS  
DATA  
A[7:0]  
D[7:0]  
Port0  
3 TM  
E
1 Kbyte  
Ext. MEM.  
ADDRESS  
Port1  
A[10:8]  
RAM  
2 Kbytes  
AS  
DS  
RW  
WAIT  
NMI  
DS2  
P0[7:0]  
P1[2:0]  
P2[7:0]  
P3[7:4]  
P4[7:4]  
P5[7:0]  
P6[5:2,0]  
P7[7:0]  
256 bytes  
Register File  
Fully  
Prog.  
I/Os  
8/16 bits  
CPU  
Interrupt  
Management  
INT[5:0]  
WKUP[13:0]  
ST9 CORE  
RCCU  
OSCIN  
OSCOUT  
RESET  
CLOCK2/8  
INTCLK  
SDA  
SCL  
2
I C BUS  
CK_AF  
WDOUT  
HW0SW1  
WATCHDOG  
SPI  
ST. TIMER  
STOUT  
MISO  
MOSI  
SCK  
SS  
TINPA0  
TOUTA0  
TINPB0  
MF TIMER 0  
MF TIMER 1  
TOUTB0  
AV  
AV  
DD  
SS  
ADC  
TINPA1  
TOUTA1  
TINPB1  
AIN[15:8]  
EXTRG  
TOUTB1  
TXCLK  
RXCLK  
SIN  
SCI M  
DCD  
SOUT  
CLKOUT  
RTS  
VOLTAGE  
REGULATOR  
V
REG  
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6  
and Port7.  
3/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 2. ST92F150C: Architectural Block Diagram  
FLASH  
128 Kbytes  
Ext. MEM.  
ADDRESS  
DATA  
A[7:0]  
D[7:0]  
Port0  
3 TM  
E
1 Kbyte  
Ext. MEM.  
ADDRESS  
Ports  
A[10:8]  
A[21:11]*  
RAM  
4 Kbytes  
1,9*  
P0[7:0]  
P1[7:3]*  
P1[2:0]  
P2[7:0]  
P3[7:4]  
P3[3:1]*  
P4[7:4]  
P4[3:0]*  
P5[7:0]  
P6[5:2,0]  
P6.1*  
AS  
DS  
RW  
Fully  
Prog.  
I/Os  
256 bytes  
WAIT  
Register File  
NMI  
DS2  
8/16 bits  
RW*  
CPU  
INT[5:0]  
Interrupt  
INT6*  
WKUP[13:0]  
Management  
P7[7:0]  
P8[7:0]*  
P9[7:0]*  
WKUP[15:14]*  
ST9 CORE  
RCCU  
OSCIN  
OSCOUT  
RESET  
CLOCK2/8  
INTCLK  
SDA  
SCL  
2
I C BUS  
CK_AF  
WDOUT  
HW0SW1  
ST. TIMER  
STOUT  
WATCHDOG  
SPI  
ICAPA0  
OCMPA0  
ICAPB0  
OCMPB0  
EXTCLK0  
MISO  
MOSI  
SCK  
SS  
EF TIMER 0 *  
AV  
AV  
AIN[15:8]  
AIN[7:0]*  
EXTRG  
DD  
SS  
ICAPA1  
OCMPA1  
ICAPB1  
OCMPB1  
EXTCLK1  
ADC  
EF TIMER 1 *  
TXCLK  
RXCLK  
SIN  
TINPA0  
TOUTA0  
TINPB0  
MF TIMER 0  
MF TIMER 1  
DCD  
SCI M  
TOUTB0  
SOUT  
CLKOUT  
RTS  
TINPA1  
TOUTA1  
TINPB1  
TOUTB1  
RDI  
TDO  
SCI A  
VOLTAGE  
REGULATOR  
V
REG  
RX0  
TX0  
CAN_0  
* Not available on 64-pin version.  
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,  
Port8* and Port9*.  
4/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 3. ST92F150J: Architectural Block Diagram  
Ext. MEM.  
ADDRESS  
DATA  
FLASH  
128 Kbytes  
A[7:0]  
D[7:0]  
Port0  
FLASH  
128 Kbytes  
3 TM  
E
Ext. MEM.  
ADDRESS  
Ports 1,9  
1K byte  
A[21:8]  
P0[7:0]  
P1[7:0]  
P2[7:0]  
P3[7:1]  
P4[7:0]  
P5[7:0]  
P6[5:0]  
P7[7:0]  
P8[7:0]  
P9[7:0]  
RAM  
4/6 Kbytes  
AS  
DS  
RW  
Fully Prog.  
I/Os  
256 bytes  
Register File  
WAIT  
NMI  
DS2  
RW  
8/16 bit  
CPU  
J1850  
JBLPD  
VPWI  
VPWO  
Interrupt  
Management  
INT[6:0]  
WKUP[15:0]  
ST9 CORE  
RCCU  
2
SDA  
SCL  
I C BUS  
OSCIN  
OSCOUT  
RESET  
CLOCK2/8  
CLOCK2  
INTCLK  
WDOUT  
HW0SW1  
WATCHDOG  
MISO  
MOSI  
SCK  
SS  
CK_AF  
STOUT  
ST. TIMER  
EF TIMER 0  
SPI  
ICAPA0  
OCMPA0  
ICAPB0  
OCMPB0  
EXTCLK0  
AV  
AV  
DD  
SS  
ADC  
AIN[15:0]  
EXTRG  
TXCLK  
RXCLK  
SIN  
ICAPA1  
OCMPA1  
ICAPB1  
OCMPB1  
EXTCLK1  
EF TIMER 1  
DCD  
SCI M  
SCI A  
SOUT  
CLKOUT  
RTS  
TINPA0  
TOUTA0  
TINPB0  
TOUTB0  
MF TIMER 0  
MF TIMER 1  
RDI  
TDO  
TINPA1  
TOUTA1  
TINPB1  
TOUTB1  
RX0  
TX0  
CAN_0 *  
CAN_1 *  
VOLTAGE  
REGULATOR  
V
RX1  
TX1  
REG  
* Available on ST92F150JDV1 only  
The alternate functions (Italic characters) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7,  
Port8 and Port9.  
5/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 4. ST92F250CV2: Architectural Block Diagram  
Ext. MEM.  
ADDRESS  
DATA  
FLASH  
256 Kbytes  
A[7:0]  
D[7:0]  
Port0  
3 TM  
E
Ext. MEM.  
ADDRESS  
Ports 1,9  
1K byte  
A[21:8]  
P0[7:0]  
P1[7:0]  
P2[7:0]  
P3[7:0]  
P4[7:0]  
P5[7:0]  
P6[7:0]  
P7[7:0]  
P8[7:0]  
P9[7:0]  
RAM  
8 Kbytes  
AS  
DS  
RW  
WAIT  
NMI  
DS2  
RW  
Fully Prog.  
I/Os  
256 bytes  
Register File  
8/16 bit  
CPU  
Interrupt  
Management  
INT[6:0]  
WKUP[15:0]  
2
SDA0  
SCL0  
I C BUS _0  
ST9 CORE  
OSCIN  
OSCOUT  
RESET  
CLOCK2/8  
CLOCK2  
INTCLK  
2
SDA1  
SCL1  
I C BUS _1  
RCCU  
WDOUT  
HW0SW1  
WATCHDOG  
SPI  
CK_AF  
STOUT  
ST. TIMER  
EF TIMER 0  
MISO  
MOSI  
SCK  
SS  
ICAPA0  
OCMPA0  
ICAPB0  
OCMPB0  
EXTCLK0  
AV  
DD  
AV  
SS  
ADC  
AIN[15:0]  
EXTRG  
ICAPA1  
OCMPA1  
ICAPB1  
OCMPB1  
EXTCLK1  
TXCLK  
RXCLK  
SIN  
EF TIMER 1  
DCD  
SCI M  
SOUT  
CLKOUT  
RTS  
TINPA0  
TOUTA0  
TINPB0  
TOUTB0  
MF TIMER 0  
MF TIMER 1  
RDI  
TDO  
SCI A  
TINPA1  
TOUTA1  
TINPB1  
TOUTB1  
RX0  
TX0  
CAN_0  
VOLTAGE  
REGULATOR  
V
REG  
The alternate functions (Italic characters) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7,  
Port8 and Port9.  
6/12  
1
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 5. ST92F124/ST92F150: Pin Configuration (Top-view TQFP64)  
64 63626160 59 585756 55545352 515049  
N.C  
1
TX0*/WAIT/WKUP5/P5.0  
RX0*/WKUP6/WDOUT/P5.1  
SIN/WKUP2/P5.2  
WDIN/SOUT/P5.3  
TXCLK/CLKOUT/P5.4  
RXCL0/WKUP7/P5.5  
DCD/WKUP8/P5.6  
WKUP9/RTS/P5.7  
WKUP4/P4.4  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
P6.5/WKUP10/INTCLK  
P6.4/NMI  
2
3
4
5
6
7
8
9
P6.3/INT3/INT5  
P6.2/INT2/INT4/DS2  
P6.0/INT0/INT1/CLOCK2/8  
P0.7/A7/D7  
P0.6/A6/D6  
P0.5/A5/D5  
P0.4/A4/D4  
P0.3/A3/D3  
P0.2/A2/D2  
P0.1/A1/D1  
P0.0/A0/D0  
AS  
ST92F124 /  
ST92F150  
10  
11  
12  
13  
14  
15  
16  
EXTRG/STOUT/P4.5  
SDA/P4.6  
WKUP1/SCL/P4.7  
SS/P3.4  
MISO/P3.5  
MOSI/P3.6  
SCK/WKUP0/P3.7  
DS  
1718192021222324 25262728 29303132  
* Not available on ST92F124 version  
7/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 6. ST92F150: Pin Configuration (Top-view PQFP100)  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
A17/P9.3  
A18/P9.4  
A19/P9.5  
A20/P9.6  
A21/P9.7  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
P8.6/AIN6  
P8.5/AIN5  
P8.4/AIN4  
P8.3/AIN3  
1
2
3
4
5
P8.2/AIN2  
6
TX0/WAIT/WKUP5/P5.0  
RX0/WKUP6/WDOUT/P5.1  
SIN/WKUP2/P5.2  
WDIN/SOUT/P5.3  
TXCLK/CLKOUT/P5.4  
RXCLK/WKUP7/P5.5  
DCD/WKUP8/P5.6  
WKUP9/RTS/P5.7  
ICAPA1/P4.0  
P8.1/AIN1/WKUP15  
P8.0/AIN0/WKUP14  
VPWO*  
P6.5/WKUP10/INTCLK/VPWI  
P6.4/NMI  
P6.3/INT3/INT5  
P6.2/INT2/INT4/DS2  
P6.1/INT6/RW  
P6.0/INT0/INT1/CLOCK2/8  
P0.7/A7/D7  
7
8
9
10  
11  
12  
13  
14  
15  
CLOCK2/P4.1  
OCMPA1/P4.2 16  
V
ST92F150  
DD  
V
V
17  
18  
19  
20  
21  
SS  
V
SS  
P0.6/A6/D6  
P0.5/A5/D5  
P0.4/A4/D4  
P0.3/A3/D3  
P0.2/A2/D2  
P0.1/A1/D1  
P0.0/A0/D0  
AS  
DD  
ICAPB1/OCMPB1/P4.3  
EXTCLK1/WKUP4/P4.4  
EXTRG/STOUT/P4.5  
SDA/P4.6 22  
WKUP1/SCL/P4.7 23  
24  
25  
26  
27  
28  
ICAPB0/P3.1  
ICAPA0/OCMPA0/P3.2  
OCMPB0/P3.3  
DS  
EXTCLK0/SS/P3.4  
MISO/P3.5  
P1.7/A15  
P1.6/A14  
P1.5/A13  
P1.4/A12  
MOSI/P3.6 29  
30  
52  
51  
SCK/WKUP0/P3.7  
3132 33 34 35 36 3738 39 40 41 42 43 44 45 46 47 48 49 50  
*On devices without JPBLD peripheral, this pin must not be connected.  
**On devices without CAN1 peripheral, these pins must not be connected.  
8/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 7. ST92F150: Pin Configuration (Top-view TQFP100)  
10099 98 9796 95 949392 91 908988 878685 84 83 82 8180 79787776  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
1
2
3
4
5
6
7
8
A20/P9.6  
A21/P9.7  
P8.4/AIN4  
P8.3/AIN3  
P8.2/AIN2  
TX0/WAIT/WKUP 5/P5.0  
RX0/WKUP6/WDOUT/P5.1  
SIN/WKUP2/P5.2  
WDIN/SOUT/P5.3  
TXCLK/CLKOUT/P5.4  
RXCLK/WKUP7/P5.5  
DCD/WKUP8/P5.6  
WKUP9/RTS/P5.7  
ICAPA1/P4.0  
P8.1/AIN1/WKUP15  
P8.0/AIN0/WKUP14  
VPWO  
P6.5/WKUP10/INTCLK/VPWI  
P6.4/NMI  
P6.3/INT3/INT5  
P6.2/INT2/INT4/DS2  
P6.1/INT6/RW  
P6.0/INT0/INT1/CLOCK2/8  
P0.7/A7/D7  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
CLOCK2/P4.1  
OCMPA1/P4.2  
ST92F150  
V
V
SS  
DD  
V
V
DD  
SS  
ICAPB1/OCMPB1/P4.3  
EXTCLK1/WKUP4/P4.4  
EXTRG/STOUT/P4.5  
SDA/P4.6  
WKUP1/SCL/P4.7  
ICAPB0/P3.1  
ICAPA0/OCMPA0/P3.2  
OCMPB0/P3.3  
P0.6/A6/D6  
P0.5/A5/D5  
P0.4/A4/D4  
P0.3/A3/D3  
P0.2/A2/D2  
P0.1/A1/D1  
P0.0/A0/D0  
AS  
EXTCLK0/SS/P3.4  
MISO/P3.5  
DS  
P1.7/A15  
262728 2930 31 32 333435 3637 38 39 40 41424344 4546 474849 50  
* V  
must be kept low in standard operating mode.  
TEST  
**On devices without CAN1 peripheral, these pins must not be connected.  
9/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 8. ST92F250: Pin Configuration (Top-view PQFP100)  
100 99 98 97 96 95  
93 92 91 90 89 88 87 86 85 84 83 82 81  
94  
SDA1/A17/P9.3  
SCL1/A18/P9.4  
80  
P8.6/AIN6  
P8.5/AIN5  
P8.4/AIN4  
P8.3/AIN3  
1
2
3
79  
78  
77  
76  
75  
74  
73  
72  
A19/P9.5  
A20/P9.6  
A21/P9.7  
4
5
P8.2/AIN2  
6
TX0/WAIT/WKUP5/P5.0  
RX0/WKUP6/WDOUT/P5.1  
SIN/WKUP2/P5.2  
WDIN/SOUT/P5.3  
TXCLK/CLKOUT/P5.4  
RXCLK/WKUP7/P5.5  
DCD/WKUP8/P5.6  
P8.1/AIN1/WKUP15  
P8.0/AIN0/WKUP14  
P3.0  
P6.5/WKUP10/INTCLK  
P6.4/NMI  
P6.3/INT3/INT5  
P6.2/INT2/INT4/DS2  
P6.1/INT6/RW  
P6.0/INT0/INT1/CLOCK2/8  
P0.7/A7/D7  
7
8
9
10  
11  
12  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
WKUP9/RTS/P5.7 13  
14  
15  
16  
17  
18  
19  
20  
ICAPA1/P4.0  
CLOCK2/P4.1  
OCMPA1/P4.2  
V
ST92F250  
DD  
V
V
SS  
SS  
V
P0.6/A6/D6  
P0.5/A5/D5  
P0.4/A4/D4  
P0.3/A3/D3  
P0.2/A2/D2  
P0.1/A1/D1  
P0.0/A0/D0  
AS  
DD  
ICAPB1/OCMPB1/P4.3  
EXTCLK1/WKUP4/P4.4  
EXTRG/STOUT/P4.5 21  
SDA0/P4.6  
WKUP1/SCL0/P4.7  
ICAPB0/P3.1  
22  
23  
24  
ICAPA0/OCMPA0/P3.2 25  
26  
OCMPB0/P3.3  
DS  
EXTCLK0/SS/P3.4 27  
P1.7/A15  
P1.6/A14  
P1.5/A13  
P1.4/A12  
28  
29  
30  
MISO/P3.5  
MOSI/P3.6  
SCK/WKUP0/P3.7  
52  
51  
3132 33 34 35 36 3738 39 40 41 42 43 44 45 46 47 48 49 50  
* V  
must be kept low in standard operating mode.  
TEST  
10/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Figure 9. ST92F250: Pin Configuration (Top-view TQFP100)  
10099 98 979695 9493 92 91 90 89 88 87 868584 8382 818079 787776  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
1
2
3
4
5
6
7
8
A20/P9.6  
A21/P9.7  
P8.4/AIN4  
P8.3/AIN3  
P8.2/AIN2  
TX/WAIT/WKUP5/P5.0  
RX/WKUP6/WDOUT/P5.1  
SIN/WKUP2/P5.2  
WDIN/SOUT/P5.3  
TXCLK/CLKOUT/P5.4  
RXCLK/WKUP7/P5.5  
DCD/WKUP8/P5.6  
WKUP9/RTS/P5.7  
ICAPA1/P4.0  
P8.1/AIN1/WKUP15  
P8.0/AIN0/WKUP14  
P3.0  
P6.5/WKUP10/INTCLK  
P6.4/NMI  
P6.3/INT3/INT5  
P6.2/INT2/INT4/DS2  
P6.1/INT6/RW  
P6.0/INT0/INT1/CLOCK2/8  
P0.7/A7/D7  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
CLOCK2/P4.1  
OCMPA1/P4.2  
ST92F250  
V
V
SS  
DD  
V
V
DD  
SS  
ICAPB1/OCMPB1/P4.3  
EXTCLK1/WKUP4/P4.4  
EXTRG/STOUT/P4.5  
SDA0/P4.6  
WKUP1/SCL0/P4.7  
ICAPB0/P3.1  
ICAPA0/OCMPA0/P3.2  
OCMPB0/P3.3  
P0.6/A6/D6  
P0.5/A5/D5  
P0.4/A4/D4  
P0.3/A3/D3  
P0.2/A2/D2  
P0.1/A1/D1  
P0.0/A0/D0  
AS  
EXTCLK0/SS/P3.4  
MISO/P3.5  
DS  
P1.7/A15  
2627 2829 3031 323334 3536 3738 39 404142 4344 45 46 47 48 49 50  
* V  
must be kept low in standard operating mode.  
TEST  
11/12  
9
ST92F124/F150/F250 - GENERAL DESCRIPTION  
Notes:  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
2002 STMicroelectronics - All Rights Reserved.  
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an  
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.  
STMicroelectronics Group of Companies  
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan  
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.  
http://www.st.com  
12/12  
1

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