ST92F250R2QC [STMICROELECTRONICS]
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD; 8月16日- BIT单电压闪存单片机系列内存， E3 TMEMULATED EEPROM ， CAN 2.0B和J1850 BLPD
| 型号： | ST92F250R2QC |
| 厂家： | 
ST |
| 描述： | 8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD |
| 文件： | 总426页 (文件大小：3830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST92F124/ST92F150/ST92F250
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,
E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
■ Memories
– Internal Memory: Single Voltage FLASH up to 256
3 TM
Kbytes, RAM up to 8Kbytes, 1K byte E
ed EEPROM)
(Emulat-
– In-Application Programming (IAP)
– 224 general purpose registers (register file) availa-
ble as RAM, accumulators or index pointers
TQFP64
14x14
PQFP100
14x20
■ Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN, WFI,
SLOW, HALT and STOP modes
TQFP100
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
– PLL Clock Generator (3-5 MHz crystal)
– Minimum instruction time: 83 ns (24 MHz int. clock)
■ Up to 80 I/O pins
14x14
■ Communication Interfaces
– Serial Peripheral Interface (SPI) with Selectable
Master/Slave mode
– One Multiprotocol Serial Communications Interface
with asynchronous and synchronous capabilities
– One asynchronous Serial Communications Interface
with 13-bit LIN Synch Break generation capability
– J1850 Byte Level Protocol Decoder (JBLPD)
– Up to two full I²C multiple Master/Slave Interfaces
supporting Access Bus
■ Interrupt Management
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or addition-
al external interrupt with multi-level interrupt handler
■ DMA controller for reduced processor
overhead
■ Timers
– Up to two CAN 2.0B Active interfaces
– 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-
■ Analog peripheral (low current coupling)
er (activated by software or by hardware)
– 10-bit A/D Converter witvalh up to 16 robust input
channels
■ Development Tools
– 16-bit Standard Timer that can be used to generate
a time base independent of PLL Clock Generator
– Two 16-bit independent Extended Function Timers
(EFTs) with Prescaler, up to two Input Captures and
up to two Output Compares
– Two 16-bit Multifunction Timers, with Prescaler, up
to two Input Captures and up to two Output Com-
pares
– Free High performance Development environment
(IDE) based on Visual Debugger, Assembler, Linker,
and C-Compiler; Real Time Operating System (OS-
EK OS, CMX) and CAN drivers
– Hardware Emulator and Flash Programming Board
for development and ISP Flasher for production
DEVICE SUMMARY 2)
Features
ST92F124R9 ST92F124V1 ST92F150CR9/1 ST92F150CV9/1 ST92F150JDV1 ST92F250CV2
FLASH - bytes
64K
2K
1K
128K
4K
1K
64K/128K
2K/4K
1K
64K/128K
2K/4K
1K
128K
6K
1K
256K
8K
1K
RAM - bytes
3 TM
E
- bytes
Timers and
Serial
Interface
2 MFT, 2 EFT, 2 MFT, 2 EFT, 2 MFT, 2 EFT,
STIM, WD, STIM, WD, STIM, WD,
SCI, SPI, I²C 2 SCI, SPI, I²C SCI, SPI, I²C
2 MFT, 2 EFT, 2 MFT, 2 EFT, 2 MFT, 2 EFT,
STIM, WD,
STIM, WD,
STIM, WD, 2 SCI,
1)
2 SCI, SPI, I²C 2 SCI, SPI, I²C
SPI, 2 I²C
ADC
Network Inter-
face
16 x 10 bits
16 x 10 bits
LIN Master
P/TQFP100
16 x 10 bits
16 x 10 bits
CAN, LIN Master
P/TQFP100
16 x 10 bits
2 CAN,J1850,
LIN Master
16 x 10 bits
-
CAN
CAN, LIN Master
Packages
TQFP64
TQFP64
P/TQFP100
1) see Section 12.4 on page 406 for important information
2) see Table 71 on page 403 for the list of supported part numbers
Rev. 4.0
1/426
November 2004
9
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 VOLTAGE REGULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 ALTERNATE FUNCTIONS FOR I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3 SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4 WRITE OPERATION EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.5 PROTECTION STRATEGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.6 FLASH IN-SYSTEM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3 ST92F124/F150/F250 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.7 STANDARD INTERRUPTS (CAN AND SCI-A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.8 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.9 DEDICATED ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.10 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.11 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . 112
6 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.2 DMA PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3 DMA TRANSACTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
426
6.4 DMA CYCLE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.5 SWAP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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Table of Contents
6.6 DMA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.2 CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.3 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.5 CRYSTAL OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.6 RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
8 EXTERNAL MEMORY INTERFACE (EXTMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
8.2 EXTERNAL MEMORY SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
9.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
9.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
10.3 EXTENDED FUNCTION TIMER (EFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10.4 MULTIFUNCTION TIMER (MFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) . . . . . . . . . . . 211
10.6 ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) . . . . . . . . . . . 236
10.7 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
10.8 I2C BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
10.9 J1850 BYTE LEVEL PROTOCOL DECODER (JBLPD) . . . . . . . . . . . . . . . . . . . . . . . . 283
10.10 CONTROLLER AREA NETWORK (BXCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.11 10-BIT ANALOG TO DIGITAL CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
12 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.2 VERSION-SPECIFIC SALES CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.3 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
12.4 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
13 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
13.1 ST92F124/F150/F250 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
13.2 ST92F150-EMU2 EMULATION CHIP KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . 418
14 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
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ST92F124/F150/F250 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
which includes the control and status registers of
the on-chip peripherals.
The ST92F124/F150/F250 microcontroller is de-
veloped and manufactured by STMicroelectronics
using a proprietary n-well HCMOS process. Its
performance derives from the use of a flexible
256-register programming model for ultra-fast con-
text switching and real-time event response. The
intelligent on-chip peripherals offload the ST9 core
from I/O and data management processing tasks
allowing critical application tasks to get the maxi-
mum use of core resources. The new-generation
ST9 MCU devices now also support low power
consumption and low voltage operation for power-
efficient and low-cost embedded systems.
1.1.2 External Memory Interface
100-pin devices have a 22-bit external address
bus allowing them to address up to 4M bytes of ex-
ternal memory.
1.1.3 On-chip Peripherals
Two 16-bit Multifunction Timers, each with an 8 bit
Prescaler and 12 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other system
timing functions by the usage of the two associat-
ed DMA channels for each timer.
Two Extended Function Timers provide further
timing and signal generation capabilities.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File, the Inter-
rupt and DMA controller, and the Memory Man-
agement Unit. The MMU allows a single linear ad-
dress space of up to 4 Mbytes.
A Standard Timer can be used to generate a sta-
ble time base independent from the PLL.
2
An I C interface (two in the ST92F250 device) pro-
2
vides fast I C and Access Bus support.
Four independent buses are controlled by the
Core: a 22-bit memory bus, an 8-bit register data
bus, an 8-bit register address bus and a 6-bit inter-
rupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
core.
The SPI is a synchronous serial interface for Mas-
ter and Slave device communication. It supports
single master and multimaster systems.
A J1850 Byte Level Protocol Decoder is available
(ST92F150JDV1 device only) for communicating
with a J1850 network.
This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.
The bxCAN (basic extended) interface (two in the
ST92F150JDV1 device) supports 2.0B Active pro-
tocol. It has 3 transmit mailboxes, 2 independent
receive FIFOs and 8 filters.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
In addition, there is an 16 channel Analog to Digital
Converter with integral sample and hold, fast con-
version time and 10-bit resolution.
There is one Multiprotocol Serial Communications
Interface with an integral generator, asynchronous
and synchronous capability (fully programmable
format) and associated address/wake-up option,
plus two DMA channels.
The powerful I/O capabilities demanded by micro-
controller applications are fulfilled by the
ST92F150/F124 with 48 (64-pin devices) or 77
(100-pin devices) I/O lines dedicated to digital In-
put/Output and with 80 I/O lines by the ST92F250.
These lines are grouped into up to ten 8-bit I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
an address/data bus for interfacing to the external
memory, timer inputs and outputs, analog inputs,
external interrupts and serial or parallel I/O. Two
memory spaces are available to support this wide
range of configurations: a combined Program/
Data Memory Space and the internal Register File,
On 100-pin devices, there is an additional asyn-
chronous Serial Communications interface with
13-bit LIN Synch Break generation capability.
Finally, a programmable PLL Clock Generator al-
lows the usage of standard 3 to 5 MHz crystals to
obtain a large range of internal frequencies up to
24 MHz. Low power Run (SLOW), Wait For Inter-
rupt, low power Wait For Interrupt, STOP and
HALT modes are also available.
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ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 1. ST92F124R9: Architectural Block Diagram
FLASH
64 Kbytes
3 TM
E
P0[7:0]
P1[2:0]
P2[7:0]
P3[7:4]
P4[7:4]
P5[7:0]
P6[5:2,0]
P7[7:0]
1 Kbyte
Fully
Prog.
I/Os
RAM
2 Kbytes
NMI
256 bytes
Register File
8/16 bits
CPU
SDA
SCL
2
Interrupt
Management
I C BUS
INT[5:0]
WKUP[13:0]
ST9 CORE
RCCU
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
WDOUT
HW0SW1
WATCHDOG
MISO
MOSI
SCK
SS
CK_AF
ST. TIMER
STOUT
SPI
ICAPA0
OCMPA0
ICAPB0
EF TIMER 0
EF TIMER 1
AV
AV
AIN[15:8]
EXTRG
DD
SS
ADC
ICAPA1
OCMPA1
ICAPB1
TXCLK
RXCLK
SIN
TINPA0
TOUTA0
TINPB0
TOUTB0
SCI M
DCD
MF TIMER 0
MF TIMER 1
SOUT
CLKOUT
RTS
TINPA1
TOUTA1
TINPB1
TOUTB1
VOLTAGE
REGULATOR
V
REG
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6
and Port7.
5/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 2. ST92F124V1: Architectural Block Diagram
FLASH
128 Kbytes
Ext. MEM.
ADDRESS
DATA
A[7:0]
D[7:0]
Port0
3 TM
E
1 Kbyte
Ext. MEM.
ADDRESS
Ports
A[10:8]
RAM
A[21:11]
4 Kbytes
1,9
P0[7:0]
P1[7:3]
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]
P4[7:4]
P4[3:0]
P5[7:0]
P6[5:2,0]
P6.1
AS
DS
RW
Fully
Prog.
I/Os
256 bytes
WAIT
Register File
NMI
DS2
RW
8/16 bits
CPU
Interrupt
Management
INT[6:0]
WKUP[15:0]
P7[7:0]
P8[7:0]
P9[7:0]
ST9 CORE
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
SDA
SCL
RCCU
2
I C BUS
CK_AF
WDOUT
HW0SW1
ST. TIMER
EF TIMER 0
STOUT
WATCHDOG
SPI
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
MISO
MOSI
SCK
SS
AV
AV
AIN[15:8]
AIN[7:0]
EXTRG
DD
SS
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
ADC
EF TIMER 1
TXCLK
RXCLK
SIN
TINPA0
TOUTA0
TINPB0
MF TIMER 0
MF TIMER 1
DCD
SCI M
SCI A
TOUTB0
SOUT
CLKOUT
RTS
TINPA1
TOUTA1
TINPB1
TOUTB1
RDI
TDO
VOLTAGE
REGULATOR
V
REG
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8 and Port9.
6/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 3. ST92F150C(R/V)1/9: Architectural Block Diagram
FLASH
128/64 Kbytes
Ext. MEM.
ADDRESS
DATA
A[7:0]
D[7:0]
Port0
3 TM
E
1 Kbyte
Ext. MEM.
ADDRESS
Ports
A[10:8]
RAM
A[21:11]*
2/4 Kbytes
1,9*
P0[7:0]
P1[7:3]*
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]*
P4[7:4]
P4[3:0]*
P5[7:0]
P6[5:2,0]
P6.1*
AS
DS
RW
WAIT
NMI
DS2
RW*
Fully
Prog.
I/Os
256 bytes
Register File
8/16 bits
CPU
INT[5:0]
Interrupt
Management
INT6*
WKUP[13:0]
WKUP[15:14]*
P7[7:0]
P8[7:0]*
P9[7:0]*
ST9 CORE
RCCU
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
SDA
SCL
2
I C BUS
CK_AF
WDOUT
HW0SW1
ST. TIMER
STOUT
WATCHDOG
SPI
ICAPA0
OCMPA0
ICAPB0
OCMPB0*
EXTCLK0*
MISO
MOSI
SCK
SS
EF TIMER 0
AV
AV
AIN[15:8]
AIN[7:0]
EXTRG
DD
SS
ICAPA1
OCMPA1
ICAPB1
OCMPB1*
EXTCLK1*
ADC
EF TIMER 1
TXCLK
RXCLK
SIN
TINPA0
TOUTA0
TINPB0
MF TIMER 0
MF TIMER 1
DCD
SCI M
TOUTB0
SOUT
CLKOUT
RTS
TINPA1
TOUTA1
TINPB1
TOUTB1
RDI
TDO
SCI A*
CAN_0
VOLTAGE
REGULATOR
V
REG
RX0
TX0
* Not available on 64-pin version.
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8* and Port9*.
7/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 4. ST92F150JDV1: Architectural Block Diagram
Ext. MEM.
ADDRESS
DATA
FLASH
128 Kbytes
A[7:0]
D[7:0]
Port0
3 TM
E
Ext. MEM.
ADDRESS
Ports 1,9
1K byte
A[21:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:1]
P4[7:0]
P5[7:0]
P6[5:0]
P7[7:0]
P8[7:0]
P9[7:0]
RAM
6 Kbytes
AS
DS
RW
WAIT
NMI
DS2
RW
Fully Prog.
I/Os
256 bytes
Register File
8/16 bit
CPU
J1850
JBLPD
VPWI
VPWO
Interrupt
Management
INT[6:0]
WKUP[15:0]
ST9 CORE
2
SDA
SCL
I C BUS
OSCIN
OSCOUT
RESET
CLOCK2/8
CLOCK2
INTCLK
RCCU
WDOUT
HW0SW1
WATCHDOG
MISO
MOSI
SCK
SS
CK_AF
STOUT
ST. TIMER
SPI
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
AV
AV
AIN[15:0]
EXTRG
DD
SS
ADC
EF TIMER 0
TXCLK
RXCLK
SIN
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
EF TIMER 1
DCD
SCI M
SCI A
SOUT
CLKOUT
RTS
TINPA0
TOUTA0
TINPB0
TOUTB0
MF TIMER 0
MF TIMER 1
RDI
TDO
TINPA1
TOUTA1
TINPB1
TOUTB1
RX0
TX0
CAN_0
CAN_1
VOLTAGE
REGULATOR
V
RX1
TX1
REG
The alternate functions (Italic characters) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8 and Port9.
8/426
1
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 5. ST92F250CV2: Architectural Block Diagram
Ext. MEM.
ADDRESS
DATA
FLASH
256 Kbytes
A[7:0]
D[7:0]
Port0
3 TM
E
Ext. MEM.
ADDRESS
Ports 1,9
1K byte
A[21:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
P4[7:0]
P5[7:0]
P6[7:0]
P7[7:0]
P8[7:0]
P9[7:0]
RAM
8 Kbytes
AS
DS
RW
WAIT
NMI
DS2
RW
Fully Prog.
I/Os
256 bytes
Register File
8/16 bit
CPU
Interrupt
Management
INT[6:0]
WKUP[15:0]
2
SDA0
SCL0
I C BUS _0
ST9 CORE
RCCU
OSCIN
OSCOUT
RESET
CLOCK2/8
CLOCK2
INTCLK
2
SDA1
SCL1
I C BUS _1
WDOUT
HW0SW1
WATCHDOG
SPI
CK_AF
STOUT
ST. TIMER
MISO
MOSI
SCK
SS
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
AV
EF TIMER 0
DD
AV
SS
ADC
AIN[15:0]
EXTRG
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TXCLK
RXCLK
SIN
EF TIMER 1
DCD
SCI M
SOUT
CLKOUT
RTS
TINPA0
TOUTA0
TINPB0
TOUTB0
MF TIMER 0
MF TIMER 1
RDI
TDO
SCI A
TINPA1
TOUTA1
TINPB1
TOUTB1
RX0
TX0
CAN_0
VOLTAGE
REGULATOR
V
REG
The alternate functions (Italic characters) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8 and Port9.
9/426
1
ST92F124/F150/F250 - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the begin-
ning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (RW), and
Data signals are valid for memory transfers.
P0[7:0], P1[7:0] or P9[7:2] (Input/Output, TTL or
CMOS compatible). 11 lines (64-pin devices) or 22
lines (100-pin devices) providing the external
memory interface for addressing 2K or 4M bytes of
external memory.
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a
write cycle, data out is valid at the leading edge of
DS. During a read cycle, Data In must be valid pri-
or to the trailing edge of DS. When the ST9 ac-
cesses on-chip memory, DS is held high during
the whole memory cycle.
P0[7:0], P1[2:0], P2[7:0], P3[7:4], P4.[7:4],
P5[7:0], P6[5:2,0], P7[7:0] I/O Port Lines (Input/
Output, TTL or CMOS compatible). I/O lines
grouped into I/O ports of 8 bits, bit programmable
under software control as general purpose I/O or
as alternate functions.
P1[7:3], P3[3:1], P4[3:0], P6.1, P8[7:0], P9[7:0]
Additional I/O Port Lines available on 100-pin ver-
sions only.
RESET. Reset (input, active low). The ST9 is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
P3.0, P6[7:6] Additional I/O Port Lines available
on ST92F250 version only.
AV . Analog V
of the Analog to Digital Con-
DD
DD
verter (common for ADC 0 and ADC 1).
AVDD can be switched off when the ADC is not in
use.
RW. Read/Write (output, 3-state). Read/Write de-
termines the direction of data transfer for external
memory transactions. RW is low when writing to
external memory, and high for all other transac-
tions.
AV . Analog V of the Analog to Digital Con-
SS
SS
verter (common for ADC 0 and ADC 1).
V
. Main Power Supply Voltage. Four pins are
DD
available on 100-pin versions, two on 64-pin ver-
sions. The pins are internally connected.
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal, or
an external source to the on-chip clock oscillator
and buffer. OSCIN is the input of the oscillator in-
verter; OSCOUT is the output of the oscillator in-
verter.
V
. Digital Circuit Ground. Four pins are availa-
SS
ble on 100-pin versions, two on 64-pin versions.
The pins are internally connected.
V
Power Supply Voltage for Flash test pur-
TEST
HW0SW1. When connected to V through a 1K
poses. This pin must be kept to 0 in user mode.
DD
pull-up resistor, the software watchdog option is
V
. Stabilization capacitors for the internal volt-
REG
selected. When connected to V
through a 1K
SS
age regulator. The user must connect external sta-
bilization capacitors to these pins. Refer to Figure
16.
pull-down resistor, the hardware watchdog option
is selected.
VPWO. This pin is the output line of the J1850 pe-
ripheral (JBLPD). It is available only on some de-
vices.
1.2.1 I/O Port Alternate Functions
Each pin of the I/O ports of the ST92F124/F150/
F250 may assume software programmable Alter-
nate Functions as shown in Section 1.4.
RX1/WKUP6. Receive Data input of CAN1 and
Wake-up line 6. Available only on some devices.
When the CAN1 peripheral is disabled, a pull-up
resistor is connected internally to this pin.
1.2.2 Termination of Unused Pins
For unused pins, input mode is not recommended.
These pins must be kept at a fixed voltage using
the output push pull mode of the I/O or an external
pull-up or pull-down resistor.
TX1. Transmit Data output of CAN1. Available on
some devices.
10/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 6. ST92F124R9: Pin Configuration (Top-view TQFP64)
64636261605958575655545352515049
N.C
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WAIT/WKUP5/P5.0
WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCL0/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
WKUP4/P4.4
P6.5/WKUP10/INTCLK
P6.4/NMI
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P6.3/INT3/INT5
P6.2/INT2/INT4
P6.0/INT0/INT1/CLOCK2/8
P0.7(/AIN7***)
P0.6(/AIN6***)
P0.5(/AIN5***)
P0.4(/AIN4***)
P0.3(/AIN3***)
P0.2(/AIN2***)
P0.1(/AIN1***)
P0.0(/AIN0***)
Reserved*
ST92F124R9
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
Reserved*
17181920212223242526272829303132
* Reserved for ST tests, must be left unconnected
** V must be kept low in standard operating mode
TEST
*** The ST92F150-EMU2 emulator does not emulate ADC channels from AIN0 to AIN7 and extended function tim-
ers because they are not implemented on the emulator chip. See also Section 13.2 on page 418
11/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 7. ST92F124V1: Pin Configuration (Top-view PQFP100)
100 99 98 97 96 95 93 92 91 90 89 88 87 86 85 84 83 82 81
94
A17/P9.3
A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
80
79
78
77
76
75
74
73
72
P8.6/AIN6
P8.5/AIN5
P8.4/AIN4
P8.3/AIN3
1
2
3
4
5
P8.2/AIN2
6
WAIT/WKUP5/P5.0
WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
NC
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
7
8
9
10
11
12
13
14
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
CLOCK2/P4.1 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OCMPA1/P4.2
V
ST92F124
DD
V
V
SS
SS
V
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
DS
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
P1.7/A15
P1.6/A14
P1.5/A13
P1.4/A12
52
51
31 32 33 34 35 36 3738 39 40 41 42 43 44 45 46 47 48 49 50
* V
must be kept low in standard operating mode.
TEST
12/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 8. ST92F124V1: Pin Configuration (Top-view TQFP100)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
A20/P9.6
A21/P9.7
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
WAIT/WKUP5/P5.0
WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
NC
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CLOCK2/P4.1
OCMPA1/P4.2
ST92F124V1
V
V
SS
DD
V
V
DD
SS
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
EXTCLK0/SS/P3.4
MISO/P3.5
DS
P1.7/A15
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
* V
must be kept low in standard operating mode.
TEST
13/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 9. ST92F150: Pin Configuration (Top-view TQFP64)
64636261605958575655545352515049
N.C
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCL0/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
WKUP4/P4.4
P6.5/WKUP10/INTCLK
P6.4/NMI
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P6.3/INT3/INT5
P6.2/INT2/INT4
P6.0/INT0/INT1/CLOCK2/8
P0.7(/AIN7***)
P0.6(/AIN6***)
P0.5(/AIN5***)
P0.4(/AIN4***)
P0.3(/AIN3***)
P0.2(/AIN2***)
P0.1(/AIN1***)
P0.0(/AIN0***)
Reserved*
ST92F150
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
Reserved*
17181920212223242526272829303132
* Reserved for ST tests, must be left unconnected
** V must be kept low in standard operating mode.
TEST
Section 13.2 on page 418
*** Not emulated. Refer to
14/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 10. ST92F150C: Pin Configuration (Top-view PQFP100)
100 99 98 97 96 95 93 92 91 90 89 88 87 86 85 84 83 82 81
94
A17/P9.3
A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
80
79
78
77
76
75
74
73
72
P8.6/AIN6
P8.5/AIN5
P8.4/AIN4
P8.3/AIN3
1
2
3
4
5
P8.2/AIN2
6
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
NC
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
7
8
9
10
11
12
13
14
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
CLOCK2/P4.1 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OCMPA1/P4.2
V
ST92F150C
DD
V
V
SS
SS
V
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
DS
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
P1.7/A15
P1.6/A14
P1.5/A13
P1.4/A12
52
51
31 32 33 34 35 36 3738 39 40 41 42 43 44 45 46 47 48 49 50
* V
must be kept low in standard operating mode.
TEST
15/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 11. ST92F150JD: Pin Configuration (Top-view PQFP100)
100 99 98 97 96 95 93 92 91 90 89 88 87 86 85 84 83 82 81
94
A17/P9.3
A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
80
79
78
77
76
75
74
73
72
P8.6/AIN6
P8.5/AIN5
P8.4/AIN4
P8.3/AIN3
1
2
3
4
5
P8.2/AIN2
6
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
VPWO
P6.5/WKUP10/INTCLK/VPW
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
7
8
9
10
11
12
13
14
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
CLOCK2/P4.1 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OCMPA1/P4.2
V
ST92F150JD
DD
V
V
SS
SS
V
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
DS
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
P1.7/A15
P1.6/A14
P1.5/A13
P1.4/A12
52
51
31 32 33 34 35 36 3738 39 40 41 42 43 44 45 46 47 48 49 50
* V
must be kept low in standard operating mode.
TEST
16/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 12. ST92F150C: Pin Configuration (Top-view TQFP100)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
A20/P9.6
A21/P9.7
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
NC
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CLOCK2/P4.1
OCMPA1/P4.2
ST92F150C
V
V
SS
DD
V
V
DD
SS
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
EXTCLK0/SS/P3.4
MISO/P3.5
DS
P1.7/A15
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
* V
must be kept low in standard operating mode.
TEST
17/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 13. ST92F150JD: Pin Configuration (Top-view TQFP100)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
A20/P9.6
A21/P9.7
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
VPWO
P6.5/WKUP10/INTCLK/VPW
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CLOCK2/P4.1
OCMPA1/P4.2
ST92F150JD
V
V
SS
DD
V
V
DD
SS
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
EXTCLK0/SS/P3.4
MISO/P3.5
DS
P1.7/A15
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
* V
must be kept low in standard operating mode.
TEST
18/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 14. ST92F250: Pin Configuration (Top-view PQFP100)
100 99 98 97 96 95 93 92 91 90 89 88 87 86 85 84 83 82 81
94
SDA1/A17/P9.3
SCL1/A18/P9.4
80
79
78
77
76
75
74
73
72
P8.6/AIN6
P8.5/AIN5
P8.4/AIN4
P8.3/AIN3
1
2
3
A19/P9.5
A20/P9.6
A21/P9.7
4
5
P8.2/AIN2
6
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
P3.0
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
7
8
9
10
11
12
13
14
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
CLOCK2/P4.1 15
16
17
18
19
20
21
OCMPA1/P4.2
V
ST92F250
DD
V
V
SS
SS
V
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA0/P4.6 22
WKUP1/SCL0/P4.7
23
24
25
26
27
28
29
30
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
DS
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
P1.7/A15
P1.6/A14
P1.5/A13
P1.4/A12
52
51
31 32 33 34 35 36 3738 39 40 41 42 43 44 45 46 47 48 49 50
* V
must be kept low in standard operating mode.
TEST
19/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 15. ST92F250: Pin Configuration (Top-view TQFP100)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
A20/P9.6
A21/P9.7
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
TX/WAIT/WKUP5/P5.0
RX/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
P3.0
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CLOCK2/P4.1
OCMPA1/P4.2
ST92F250
V
V
SS
DD
V
V
DD
SS
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA0/P4.6
WKUP1/SCL0/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
EXTCLK0/SS/P3.4
MISO/P3.5
DS
P1.7/A15
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
* V
must be kept low in standard operating mode.
TEST
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9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Table 1. ST92F124/F150/F250 Power Supply Pins
Name
Function
TQFP64 PQFP100 TQFP100
-
18
42
65
93
17
41
64
92
82
15
39
62
90
14
38
61
89
79
Main Power Supply Voltage
(Pins internally connected)
27
-
V
DD
60
-
Digital Circuit Ground
26
-
V
SS
(Pins internally connected)
59
49
AV
AV
V
Analog Circuit Supply Voltage
Analog Circuit Ground
DD
50
29
83
44
80
41
SS
Must be kept low in standard operating mode
TEST
REG
V
31
43
28
40
Stabilization capacitor(s) for internal voltage regulator
28
Table 2. ST92F124/F150/F250 Primary Function Pins
Name
AS
Function
Address Strobe
TQFP64 PQFP100 TQFP100
-
-
56
55
32
94
95
96
97
73
49
50
53
52
29
91
92
93
94
70
46
47
DS
Data Strobe
RW
Read/Write
-
OSCIN
OSCOUT
RESET
HW0SW1
Crystal Oscillator Input
Crystal Oscillator Output
Reset to initialize the Microcontroller
Watchdog HW/SW enabling selection
J1850 JBLPD Output
61
62
63
64
-
1)
VPWO
1)
RX1/WKUP6
CAN1 Receive Data / Wake-up Line 6
CAN1 Transmit Data.
-
1)
TX1
-
Note 1: ST92F150JDV1 only.
21/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
1.3 VOLTAGE REGULATOR
The internal Voltage Regulator (VR) is used to
power the microcontroller starting from the exter-
nal power supply. The VR comprises a Main volt-
age regulator and a Low-power regulator.
non-stabilized and non-thermally-compensated
voltage sufficient for maintaining the data in
RAM and the Register File.
For both the Main VR and the Low-Power VR, sta-
bilization is achieved by an external capacitor,
– The Main voltage regulator generates sufficient
current for the microcontroller to operate in any
mode. It has a static power consumption (300
µA typ.).
connected to one of the V
pins. The minimum
REG
recommended value is 300 nF, and care must be
taken to minimize distance between the chip and
the capacitor. Care should also be taken to limit
the serial inductance to less than 60nH.
– The separate Low-Power regulator consumes
less power is used only when the microcontrol-
ler is in Low Power mode. It has a different de-
sign from the main VR and generates a lower,
Figure 16. Recommended Connections for V
REG
PQFP100
TQFP100
QFP64
Pin 28
Pin 43
Pin 31
Pin 28
Pin 40
C
C
C
L
L
L
C = 300 to 600nF
L = Ferrite bead for EMI protection.
Suggested type: Murata BLM18BE601FH1: (Imp. 600 Ω at 100 MHz).
IMPORTANT: The V pin cannot be used to drive external devices.
REG
Figure 17. Minimum Required Connections for V
REG
PQFP100
TQFP100
QFP64
Pin 31
Pin 43
Pin 28
Pin 40
Pin 28
C
C
C
C = 300 to 600nF
Note: Pin 31 of PQFP100 or pin 28 of TQFP100 can be left unconnnected. A secondary stabilization net-
work can also be connected to these pins.
22/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
1.4 I/O PORTS
Port 0, Port 1 and Port 9[7:2] provide the external
memory interface. All the ports of the device can
be programmed as Input/Output or in Input mode,
compatible with TTL or CMOS levels (except
where Schmitt Trigger is present). Each bit can be
programmed individually (Refer to the I/O ports
chapter).
ble 3), while the High Hysteresis Schmitt Trigger is
present on ports P4[7:6] and P6[5:4].
All inputs which can be used for detecting interrupt
events have been configured with a “Standard”
Schmitt Trigger, apart from the NMI pin which im-
plements the “High Hysteresis” version. In this
way, all interrupt lines are guaranteed as “edge
sensitive”.
Internal Weak Pull-up
As shown in Table 3, not all input sections imple-
ment a Weak Pull-up. This means that the pull-up
must be connected externally when the pin is not
used or programmed as bidirectional.
Push-Pull/OD Output
The output buffer can be programmed as push-
pull or open-drain: attention must be paid to the
fact that the open-drain option corresponds only to
a disabling of P-channel MOS transistor of the
buffer itself: it is still present and physically con-
nected to the pin. Consequently it is not possible to
increase the output voltage on the pin over
TTL/CMOS Input
For all those port bits where no input schmitt trig-
ger is implemented, it is always possible to pro-
gram the input level as TTL or CMOS compatible
by programming the relevant PxC2.n control bit.
Refer I/O Ports Chapter to the section titled “Input/
Output Bit Configuration”.
V
+0.3 Volt, to avoid direct junction biasing.
DD
Pure Open-Drain Output
The user can increase the voltage on an I/O pin
Schmitt Trigger Input
over V +0.3 Volt where the P-channel MOS tran-
DD
sistor is physically absent: this is allowed on all
“Pure Open Drain” pins. In this case, the push-pull
option is not available and any weak pull-up must
be implemented externally.
Two different kinds of Schmitt Trigger circuitries
are implemented: Standard and High Hysteresis.
Standard Schmitt Trigger is widely used (see Ta-
Table 3. I/O Port Characteristics
Input
Output
Push-Pull/OD
Push-Pull/OD
Weak Pull-Up
No
No
Reset State
Bidirectional
Bidirectional
Port 0[7:0]
Port 1[7:0]
TTL/CMOS
TTL/CMOS
Port 2[1:0]
Port 2[3:2]
Port 2[5:4]
Port 2[7:6]
Schmitt trigger
TTL/CMOS
Schmitt trigger
TTL/CMOS
Push-Pull/OD
Pure OD
Push-Pull/OD
Push-Pull/OD
Yes
No
Yes
Yes
Input
Input CMOS
Input
Input CMOS
1)
Port 3[2:0]
Port 3.3
Port 3[7:4]
Schmitt trigger
TTL/CMOS
Schmitt trigger
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Yes
Yes
Yes
Input
Input CMOS
Input
Port 4.0, Port 4.4
Port 4.1
Port 4.2, Port 4.5
Port 4.3
Schmitt trigger
Schmitt trigger
TTL/CMOS
Schmitt trigger
High hysteresis Schmitt trigger Pure OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
No
Input
Yes
Yes
Yes
No
Bidirectional WPU
Input CMOS
Input
Port 4[7:6]
Input
Port 5[2:0], Port 5[7:4] Schmitt trigger
Push-Pull/OD
Push-Pull/OD
No
Yes
Input
Input CMOS
Port 5.3
TTL/CMOS
Port 6[3:0]
Port 6[5:4]
Port 6[7:6]
Schmitt trigger
High hysteresis Schmitt trigger Push-Pull/OD
Schmitt trigger
Push-Pull/OD
Yes
Yes
Yes
Input
Input
Input
1)
Push-Pull/OD
Port 7[7:0]
Schmitt trigger
Push-Pull/OD
Yes
Input
Port 8[1:0]
Port 8[7:2]
Schmitt trigger
Schmitt trigger
Push-Pull/OD
Push-Pull/OD
Yes
Yes
Input
Bidirectional WPU
Port 9[7:0]
Schmitt trigger
Push-Pull/OD
Yes
Bidirectional WPU
Legend:
WPU = Weak Pull-Up, OD = Open Drain.
Note 1: Port 3.0 and Port6 [7:6] present on ST92F250 version only.
23/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
How to Configure the I/O Ports
To configure the I/O ports, use the information in
Table 3, Table 4 and the Port Bit Configuration Ta-
ble in the I/O Ports Chapter (See page 152).
Example 1: SCI-M input
AF: SIN, Port: P5.2. Schmitt Trigger input.
Write the port configuration bits:
P5C2.2=1
P5C1.2=0
P5C0.2 =1
Input Note = the hardware characteristics fixed for
each port line in Table 3.
– If Input note = TTL/CMOS, either TTL or CMOS
input level can be selected by software.
Enable the SCI peripheral by software as de-
scribed in the SCI chapter.
– If Input note = Schmitt trigger, selecting CMOS
or TTL input by software has no effect, the input
will always be Schmitt Trigger.
Example 2: SCI-M output
AF: SOUT, Port: P5.3, Push-Pull/OD output.
Write the port configuration bits (for AF OUT PP):
Alternate Functions (AF) = More than one AF
cannot be assigned to an I/O pin at the same time:
P5C2.3=0
P5C1.3=1
P5C0.3 =1
An alternate function can be selected as follows.
AF Inputs:
Example 3: External Memory I/O
– AF is selected implicitly by enabling the corre-
sponding peripheral. Exception to this are ADC
inputs which must be explicitly selected as AF in-
put by software.
AF: A0/D0, Port : P0.0, Input Note: TTL/CMOS in-
put.
Write the port configuration bits:
AF Outputs or Bidirectional Lines:
P0C2.0=1
P0C1.0=1
P0C0.0 =1
– In the case of Outputs or I/Os, AF is selected ex-
plicitly by software.
Example 4: Analog input
AF: AIN8, Port : 7.0, Analog input.
Write the port configuration bits:
P7C2.0=1
P7C1.0=1
P7C0.0 =1
24/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
1.5 Alternate Functions for I/O Ports
All the ports in the following table are useable for general purpose I/O (input, output or bidirectional).
Table 4. I/O Port Alternate Functions
Pin No.
Port
Name
Alternate Functions
TQFP64 PQFP100 TQFP100
-
35
-
57
-
54
-
A0/D0
I/O Address/Data bit 0
Analog Data Input 0
I/O Address/Data bit 1
Analog Data Input 1
I/O Address/Data bit 2
Analog Data Input 2
I/O Address/Data bit 3
Analog Data Input 3
I/O Address/Data bit 4
Analog Data Input 4
I/O Address/Data bit 5
Analog Data Input 5
I/O Address/Data bit 6
Analog Data Input 6
I/O Address/Data bit 7
Analog Data Input 7
I/O Address bit 8
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
1)
AIN0
I
58
-
55
-
A1/D1
1)
36
-
AIN1
I
59
-
56
-
A2/D2
1)
37
-
AIN2
I
60
-
57
-
A3/D3
1)
38
-
AIN3
I
61
-
58
-
A4/D4
1)
39
-
AIN4
I
62
-
59
-
A5/D5
1)
40
-
AIN5
I
63
-
60
-
A6/D6
1)
41
-
AIN6
I
66
-
63
-
A7/D7
1)
42
-
AIN7
I
45
42
A8
1)
P1.0
P1.1
P1.2
ICAPA0
I
Ext. Timer 0 - Input Capture A
Ext. Timer 0 - Output Compare A
30
-
-
46
-
-
43
-
1)
OCMPA0
A9
O
I/O Address bit 9
1)
ICAPA1
I
Ext. Timer 1- Input Capture A
Ext. Timer 1- Output Compare A
31
-
1)
OCMPA1
A10
O
47
-
44
-
I/O Address bit 10
1)
ICAPB1
I
I
Ext. Timer 1- Input Capture B
Ext. Timer 0- Input Capture B
32
1)
ICAPB0
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
-
-
48
51
52
53
54
33
34
35
36
37
45
48
49
50
51
30
31
32
33
34
A11
I/O Address bit 11
I/O Address bit 12
I/O Address bit 13
I/O Address bit 14
I/O Address bit 15
A12
-
A13
-
A14
-
A15
18
19
20
21
22
TINPA0
TINPB0
TOUTA0
TOUTB0
TINPA1
I
I
Multifunction Timer 0 - Input A
Multifunction Timer 0 - Input B
Multifunction Timer 0 - Output A
Multifunction Timer 0 - Output B
Multifunction Timer 1 - Input A
O
O
I
25/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Pin No.
Port
Name
Alternate Functions
TQFP64 PQFP100 TQFP100
P2.5
P2.6
P2.7
23
24
25
-
38
39
40
73
24
35
36
37
70
21
TINPB1
TOUTA1
TOUTB1
I
Multifunction Timer 1 - Input B
Multifunction Timer 1 - Output A
Multifunction Timer 1 - Output B
O
O
2)
P3.0
P3.1
P3.2
P3.3
P3.4
-
ICAPB0
ICAPA0
OCMPA0
OCMPB0
EXTCLK0
SS
I
I
Ext. Timer 0 - Input Capture B
Ext. Timer 0 - Input Capture A
Ext. Timer 0 - Output Compare A
Ext. Timer 0 - Output Compare B
Ext. Timer 0 - Input Clock
-
-
-
25
26
27
22
23
24
O
O
I
I
SPI - Slave Select
P3.5
P3.6
14
15
28
29
25
26
MISO
I/O SPI - Master Input/Slave Output Data
I/O SPI - Master Output/Slave Input Data
MOSI
SCK
I
I
SPI - Serial Input Clock
Wake-up Line 0
P3.7
16
30
27
WKUP0
SCK
O
I
SPI - Serial Output Clock
Ext. Timer 1 - Input Capture A
CLOCK2 internal signal
Ext. Timer 1 - Output Compare A
Ext. Timer 1 - Input Capture B
Ext. Timer 1 - Output Compare B
Ext. Timer 1 - Input Clock
Wake-up Line 4
P4.0
P4.1
P4.2
-
-
-
14
15
16
11
ICAPA1
CLOCK2
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
WKUP4
EXTRG
STOUT
SDA0
12
13
O
O
I
P4.3
P4.4
-
-
19
20
16
17
O
I
I
I
ADC Ext. Trigger
P4.5
P4.6
P4.7
10
11
12
21
22
23
18
19
20
O
Standard Timer Output
2
I/O I C 0 Data
WKUP1
SCL0
I
Wake-up Line 1
2
I/O I C 0 Clock
WAIT
I
I
External Wait Request
P5.0
P5.1
1
2
6
7
3
4
WKUP5
Wake-up Line 5
2)
TX0
O
I
CAN 0 output
WKUP6
Wake-up Line 6
2)
RX0
I
CAN 0 input
WDOUT
SIN0
O
I
Watchdog Timer Output
SCI-M - Serial Data Input
Wake-up Line 2
P5.2
P5.3
3
4
8
9
5
6
WKUP2
WDIN
I
I
Watchdog Timer Input
SCI-M - Serial Data Output
SOUT
O
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9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Pin No.
Port
Name
Alternate Functions
TQFP64 PQFP100 TQFP100
TXCLK
CLKOUT
RXCLK
WKUP7
DCD
I
O
I
SCI-M - Transmit Clock Input
SCI-M - Clock Output
SCI-M - Receive Clock Input
Wake-up Line 7
P5.4
P5.5
P5.6
P5.7
5
6
7
8
10
11
12
13
7
8
I
I
SCI-M - Data Carrier Detect
Wake-up Line 8
9
WKUP8
WKUP9
RTS
I
I
Wake-up Line 9
10
O
I
SCI-M - Request To Send
External Interrupt 0
External Interrupt 1
CLOCK2 divided by 8
External Interrupt 6
Read/Write
INT0
P6.0
P6.1
P6.2
43
-
67
68
69
64
65
66
INT1
I
CLOCK2/8
INT6
O
I
RW
O
I
INT2
External Interrupt 2
External Interrupt 4
Data Strobe 2
44
INT4
I
DS2
O
I
INT3
External Interrupt 3
External Interrupt 5
Non Maskable Interrupt
Wake-up Line 10
P6.3
P6.4
45
46
70
71
67
68
INT5
I
NMI
I
WKUP10
I
2)
P6.5
47
72
69
VPWI
I
JBLPD input
INTCLK
O
Internal Main Clock
2)
-
-
49
50
46
47
P6.6
2)
P6.7
AIN8
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Data Input 8
Clock Alternative Source
Analog Data Input 9
Analog Data Input 10
Analog Data Input 11
Wake-up Line 3
P7.0
51
84
81
CK_AF
AIN9
P7.1
P7.2
P7.3
52
53
54
85
86
87
82
83
84
AIN10
AIN11
WKUP3
AIN12
P7.4
P7.5
P7.6
P7.7
55
56
57
58
88
89
90
91
85
86
87
88
Analog Data Input 12
Analog Data Input 13
Wake-up Line 11
AIN13
WKUP11
AIN14
Analog Data Input14
Wake-up Line 12
WKUP12
AIN15
Analog Data Input 15
Wake-up Line 13
WKUP13
27/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
Pin No.
Port
Name
Alternate Functions
Analog Data Input 0
TQFP64 PQFP100 TQFP100
AIN0
I
I
P8.0
P8.1
-
-
74
75
71
72
WKUP14
AIN1
Wake-up Line 14
I
Analog Data Input 1
Wake-up Line 15
WKUP15
AIN2
I
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
P9.2
-
-
-
-
-
-
-
-
-
76
77
78
79
80
81
98
99
100
73
74
75
76
77
78
95
96
97
I
Analog Data Input 2
Analog Data Input 3
Analog Data Input 4
Analog Data Input 5
Analog Data Input 6
Analog Data Input 7
SCI-A Receive Data Input
SCI-A Transmit Data Output
Address bit 16
AIN3
I
AIN4
I
AIN5
I
AIN6
I
AIN7
I
2)
RDI
I
2)
TDO
O
O
O
A16
3)
A17
Address bit 17
P9.3
P9.4
-
-
1
2
98
99
2)
SDA1
I/O I²C 1 Data
3)
A18
O
Address bit 18
2)
SCL1
I/O I²C 1 Clock
P9.5
P9.6
P9.7
-
-
-
3
4
5
100
1
A19
A20
A21
O
O
O
Address bit 19
Address bit 20
Address bit 21
2
Note1: The ST92F150-EMU2 emulator does not
emulate ADC channels from AIN0 to AIN7 and ex-
tended function timers because they are not imple-
mented on the emulator chip. See also Section
13.2 on page 418.
Note 2: Available on some devices only.
Note 3: For the ST92F250 device, since A[18:17]
share the same pins as SDA1 and SCL1 of I²C_1,
these address bits are not available when the
I²C_1 is in use (when I2CCR.PE bit is set).
28/426
9
ST92F124/F150/F250 - GENERAL DESCRIPTION
1.6 OPERATING MODES
To optimize the performance versus the power
consumption of the device, the ST92F124/F150/
F250 supports different operating modes that can
be dynamically selected depending on the per-
formance and functionality requirements of the ap-
plication at a given moment.
agement Unit paragraphs in the following for the
details. The difference with the HALT mode con-
sists in the way the CPU exits this state: when the
STOP is executed, the status of the registers is re-
corded, and when the system exits from the STOP
mode the CPU continues the execution with the
same status, without a system reset.
RUN MODE: This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
When the MCU enters STOP mode the Watchdog
stops counting. After the MCU exits from STOP
mode, the Watchdog resumes counting from
where it left off.
SLOW MODE: Power consumption can be signifi-
cantly reduced by running the CPU and the pe-
ripherals at reduced clock speed using the CPU
Prescaler and CCU Clock Divider.
When the MCU exits from STOP mode, the oscil-
lator, which was sleeping too, requires about 5 ms
to restart working properly (at a 4 MHz oscillator
frequency). An internal counter is present to guar-
antee that all operations after exiting STOP Mode,
take place with the clock stabilised.
WAIT FOR INTERRUPT MODE: The Wait For In-
terrupt (WFI) instruction suspends program exe-
cution until an interrupt request is acknowledged.
During WFI, the CPU clock is halted while the pe-
ripheral and interrupt controller keep running at a
frequency depending on the CCU programming.
The counter is active only when the oscillation has
already taken place. This means that 1-2 ms must
be added to take into account the first phase of the
oscillator restart.
LOW POWER WAIT FOR INTERRUPT MODE:
Combining SLOW mode and Wait For Interrupt
mode it is possible to reduce the power consump-
tion by more than 80%.
In STOP mode, the oscillator is stopped. There-
fore, if the PLL is used to provide the CPU clock
before entering STOP mode, it will have to be se-
lected again when the MCU exits STOP mode.
STOP MODE: When the STOP is requested by
executing the STOP bit writing sequence (see
dedicated section on Wake-up Management Unit
paragraph), and if NMI is kept low, the CPU and
the peripherals stop operating. Operations resume
after a wake-up line is activated (16 wake-up lines
plus NMI pin). See the RCCU and Wake-up Man-
HALT MODE: When executing the HALT instruc-
tion, and if the Watchdog is not enabled, the CPU
and its peripherals stop operating and the status of
the machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
29/426
9
ST92F124/F150/F250 - DEVICE ARCHITECTURE
2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE
The ST9 Core or Central Processing Unit (CPU)
features a highly optimised instruction set, capable
of handling bit, byte (8-bit) and word (16-bit) data,
as well as BCD and Boolean formats; 14 address-
ing modes are available.
which hold data and control bits for the on-chip
peripherals and I/Os.
– A single linear memory space accommodating
both program and data. All of the physically sep-
arate memory areas, including the internal ROM,
internal RAM and external memory are mapped
in this common address space. The total ad-
dressable memory space of 4 Mbytes (limited by
the size of on-chip memory and the number of
external address pins) is arranged as 64 seg-
ments of 64 Kbytes. Each segment is further
subdivided into four pages of 16 Kbytes, as illus-
trated in Figure 18. A Memory Management Unit
uses a set of pointer registers to address a 22-bit
memory field using 16-bit address-based instruc-
tions.
Four independent buses are controlled by the
Core: a 16-bit Memory bus, an 8-bit Register data
bus, an 8-bit Register address bus and a 6-bit In-
terrupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
Core.
This multiple bus architecture affords a high de-
gree of pipelining and parallel operation, thus mak-
ing the ST9 family devices highly efficient, both for
numerical calculation, data handling and with re-
gard to communication with on-chip peripheral re-
sources.
2.2.1 Register File
The Register File consists of (see Figure 19):
2.2 MEMORY SPACES
– 224 general purpose registers (Group 0 to D,
registers R0 to R223)
There are two separate memory spaces:
– The Register File, which comprises 240 8-bit
registers, arranged as 15 groups (Group 0 to E),
each containing sixteen 8-bit registers plus up to
64 pages of 16 registers mapped in Group F,
– 6 system registers in the System Group (Group
E, registers R224 to R239)
– Up to 64 pages, depending on device configura-
tion, each containing up to 16 registers, mapped
to Group F (R240 to R255), see Figure 20.
Figure 18. Single Program and Data Memory Address Space
Data
Code
Address
16K Pages 64K Segments
255
254
3FFFFFh
63
253
3F0000h
3EFFFFh
252
251
250
249
248
247
62
3E0000h
up to 4 Mbytes
135
134
133
132
21FFFFh
Reserved
33
210000h
20FFFFh
11
10
9
02FFFFh
2
020000h
01FFFFh
8
7
6
1
5
010000h
00FFFFh
4
3
2
0
1
0
000000h
30/426
9
ST92F124/F150/F250 - DEVICE ARCHITECTURE
MEMORY SPACES (Cont’d)
Figure 19. Register Groups
Figure 20. Page Pointer for Group F mapping
PAGE 63
UP TO
255
240
239
64 PAGES
F PAGED REGISTERS
E SYSTEM REGISTERS
224
PAGE 5
223
D
R255
PAGE 0
C
B
A
9
8
7
6
5
4
3
2
1
R240
R234
R224
PAGE POINTER
224
GENERAL
PURPOSE
REGISTERS
15
0
0
0
VA00432
R0
VA00433
Figure 21. Addressing the Register File
REGISTER FILE
255
F PAGED REGISTERS
240
239
E SYSTEM REGISTERS
224
223
D
GROUP D
C
B
A
9
8
7
6
5
4
3
R195
R207
(R0C3h)
(1100)(0011)
GROUP C
R195
R192
GROUP B
2
1
15
0
0
0
VR000118
31/426
9
ST92F124/F150/F250 - DEVICE ARCHITECTURE
MEMORY SPACES (Cont’d)
2.2.2 Register Addressing
Therefore if the Page Pointer, R234, is set to 5, the
instructions:
Register File registers, including Group F paged
registers (but excluding Group D), may be ad-
dressed explicitly by means of a decimal, hexa-
decimal or binary address; thus R231, RE7hand
R11100111b represent the same register (see
Figure 21). Group D registers can only be ad-
dressed in Working Register mode.
spp #5
ld R242, r4
will load the contents of working register r4 into the
third register of page 5 (R242).
These paged registers hold data and control infor-
mation relating to the on-chip peripherals, each
peripheral always being associated with the same
pages and registers to ensure code compatibility
between ST9 devices. The number of these regis-
ters therefore depends on the peripherals which
are present in the specific ST9 family device. In
other words, pages only exist if the relevant pe-
ripheral is present.
Note that an upper case “R” is used to denote this
direct addressing mode.
Working Registers
Certain types of instruction require that registers
be specified in the form “rx”, where x is in the
range 0 to 15: these are known as Working Regis-
ters.
Note that a lower case “r” is used to denote this in-
direct addressing mode.
Table 5. Register File Organization
Two addressing schemes are available: a single
group of 16 working registers, or two separately
mapped groups, each consisting of 8 working reg-
isters. These groups may be mapped starting at
any 8 or 16 byte boundary in the register file by
means of dedicated pointer registers. This tech-
nique is described in more detail in Section 2.3.3
Register Pointing Techniques, and illustrated in
Figure 22 and in Figure 23.
Hex.
Address
Decimal
Address
Register
File Group
Function
Paged
Registers
F0-FF
E0-EF
240-255
224-239
Group F
Group E
System
Registers
D0-DF
C0-CF
B0-BF
A0-AF
90-9F
80-8F
70-7F
60-6F
50-5F
40-4F
30-3F
20-2F
10-1F
00-0F
208-223
192-207
176-191
160-175
144-159
128-143
112-127
96-111
80-95
Group D
Group C
Group B
Group A
Group 9
Group 8
Group 7
Group 6
Group 5
Group 4
Group 3
Group 2
Group 1
Group 0
System Registers
The 16 registers in Group E (R224 to R239) are
System registers and may be addressed using any
of the register addressing modes. These registers
are described in greater detail in Section 2.3 SYS-
TEM REGISTERS.
General
Purpose
Registers
Paged Registers
Up to 64 pages, each containing 16 registers, may
be mapped to Group F. These are addressed us-
ing any register addressing mode, in conjunction
with the Page Pointer register, R234, which is one
of the System registers. This register selects the
page to be mapped to Group F and, once set,
does not need to be changed if two or more regis-
ters on the same page are to be addressed in suc-
cession.
64-79
48-63
32-47
16-31
00-15
32/426
9
ST92F124/F150/F250 - DEVICE ARCHITECTURE
2.3 SYSTEM REGISTERS
The System registers are listed in Table 6. They
are used to perform all the important system set-
tings. Their purpose is described in the following
pages. Refer to the chapter dealing with I/O for a
description of the PORT[5:0] Data registers.
Note: If an MFT is not included in the ST9 device,
then this bit has no effect.
Bit 6 = TLIP: Top Level Interrupt Pending.
This bit is set by hardware when a Top Level Inter-
rupt Request is recognized. This bit can also be
set by software to simulate a Top Level Interrupt
Request.
0: No Top Level Interrupt pending
1: Top Level Interrupt pending
Table 6. System Registers (Group E)
R239 (EFh)
R238 (EEh)
R237 (EDh)
R236 (ECh)
R235 (EBh)
R234 (EAh)
R233 (E9h)
R232 (E8h)
R231 (E7h)
R230 (E6h)
R229 (E5h)
R228 (E4h)
R227 (E3h)
R226 (E2h)
R225 (E1h)
R224 (E0h)
SSPLR
SSPHR
USPLR
USPHR
Bit 5 = TLI: Top Level Interrupt bit.
0: Top Level Interrupt is acknowledged depending
on the TLNM bit in the NICR Register.
1: Top Level Interrupt is acknowledged depending
on the IEN and TLNM bits in the NICR Register
(described in the Interrupt chapter).
MODE REGISTER
PAGE POINTER REGISTER
REGISTER POINTER 1
REGISTER POINTER 0
FLAG REGISTER
CENTRAL INT. CNTL REG
PORT5 DATA REG.
PORT4 DATA REG.
PORT3 DATA REG.
PORT2 DATA REG.
PORT1 DATA REG.
PORT0 DATA REG.
Bit 4 = IEN: Interrupt Enable .
This bit is cleared by interrupt acknowledgement,
and set by interrupt return (iret). IEN is modified
implicitly by iret, eiand diinstructions or by an
interrupt acknowledge cycle. It can also be explic-
itly written by the user, but only when no interrupt
is pending. Therefore, the user should execute a
di instruction (or guarantee by other means that
no interrupt request can arrive) before any write
operation to the CICR register.
0: Disable all interrupts except Top Level Interrupt.
1: Enable Interrupts
2.3.1 Central Interrupt Control Register
Please refer to the ”INTERRUPT” chapter for a de-
tailed description of the ST9 interrupt philosophy.
Bit 3 = IAM: Interrupt Arbitration Mode.
This bit is set and cleared by software to select the
arbitration mode.
0: Concurrent Mode
1: Nested Mode.
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
R230 - Read/Write
Register Group: E (System)
Reset Value: 1000 0111 (87h)
7
0
Bits 2:0 = CPL[2:0]: Current Priority Level.
GCE
N
These three bits record the priority level of the rou-
tine currently running (i.e. the Current Priority Lev-
el, CPL). The highest priority level is represented
by 000, and the lowest by 111. The CPL bits can
be set by hardware or software and provide the
reference according to which subsequent inter-
rupts are either left pending or are allowed to inter-
rupt the current interrupt service routine. When the
current interrupt is replaced by one of a higher pri-
ority, the current priority value is automatically
stored until required in the NICR register.
TLIP TLI IEN
IAM CPL2 CPL1 CPL0
Bit 7 = GCEN: Global Counter Enable.
This bit is the Global Counter Enable of the Multi-
function Timers. The GCEN bit is ANDed with the
CE bit in the TCR Register (only in devices featur-
ing the MFT Multifunction Timer) in order to enable
the Timers when both bits are set. This bit is set af-
ter the Reset cycle.
33/426
9
ST92F124/F150/F250 - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
2.3.2 Flag Register
decw),
Test (tm, tmw, tcm, tcmw, btset).
The Flag Register contains 8 flags which indicate
the CPU status. During an interrupt, the flag regis-
ter is automatically stored in the system stack area
and recalled at the end of the interrupt service rou-
tine, thus returning the CPU to its original status.
Inmostcases,theZeroflagissetwhenthecontents
of the register being used as an accumulator be-
come zero, following one of the above operations.
This occurs for all interrupts and, when operating
in nested mode, up to seven versions of the flag
register may be stored.
Bit 5 = S: Sign Flag.
The Sign flag is affected by the same instructions
as the Zero flag.
FLAG REGISTER (FLAGR)
R231- Read/Write
Register Group: E (System)
Reset value: 0000 0000 (00h)
The Sign flag is set when bit 7 (for a byte opera-
tion) or bit 15 (for a word operation) of the register
used as an accumulator is one.
7
0
Bit 4 = V: Overflow Flag.
The Overflow flag is affected by the same instruc-
tions as the Zero and Sign flags.
C
Z
S
V
DA
H
-
DP
When set, the Overflow flag indicates that a two's-
complement number, in a result register, is in er-
ror, since it has exceeded the largest (or is less
than the smallest), number that can be represent-
ed in two’s-complement notation.
Bit 7 = C: Carry Flag.
The carry flag is affected by:
Addition (add, addw, adc, adcw),
Subtraction (sub, subw, sbc, sbcw),
Compare (cp, cpw),
Shift Right Arithmetic (sra, sraw),
Shift Left Arithmetic (sla, slaw),
Swap Nibbles (swap),
Rotate (rrc, rrcw, rlc, rlcw, ror,
rol),
Decimal Adjust (da),
Multiply and Divide (mul, div, divws).
Bit 3 = DA: Decimal Adjust Flag.
The DA flag is used for BCD arithmetic. Since the
algorithm for correcting BCD operations is differ-
ent for addition and subtraction, this flag is used to
specify which type of instruction was executed
last, so that the subsequent Decimal Adjust (da)
operation can perform its function correctly. The
DA flag cannot normally be used as a test condi-
tion by the programmer.
When set, it generally indicates a carry out of the
most significant bit position of the register being
used as an accumulator (bit 7 for byte operations
and bit 15 for word operations).
Bit 2 = H: Half Carry Flag.
The carry flag can be set by the Set Carry Flag
(scf) instruction, cleared by the Reset Carry Flag
(rcf) instruction, and complemented by the Com-
plement Carry Flag (ccf) instruction.
The H flag indicates a carry out of (or a borrow in-
to) bit 3, as the result of adding or subtracting two
8-bit bytes, each representing two BCD digits. The
H flag is used by the Decimal Adjust (da) instruc-
tion to convert the binary result of a previous addi-
tion or subtraction into the correct BCD result. Like
the DA flag, this flag is not normally accessed by
the user.
Bit 6 = Z: Zero Flag. The Zero flag is affected by:
Addition (add, addw, adc, adcw),
Subtraction (sub, subw, sbc, sbcw),
Compare (cp, cpw),
Shift Right Arithmetic (sra, sraw),
Shift Left Arithmetic (sla, slaw),
Swap Nibbles (swap),
Bit 1 = Reserved bit (must be 0).
Rotate (rrc, rrcw, rlc, rlcw, ror,
rol),
Bit 0 = DP: Data/Program Memory Flag.
This bit indicates the memory area addressed. Its
value is affected by the Set Data Memory (sdm)
and Set Program Memory (spm) instructions. Re-
fer to the Memory Management Unit for further de-
tails.
Decimal Adjust (da),
Multiply and Divide (mul, div, divws),
Logical (and, andw, or, orw, xor,
xorw, cpl),
Increment and Decrement (inc, incw, dec,
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SYSTEM REGISTERS (Cont’d)
If the bit is set, data is accessed using the Data
Pointers (DPRs registers), otherwise it is pointed
to by the Code Pointer (CSR register); therefore,
the user initialization routine must include a Sdm
instruction. Note that code is always pointed to by
the Code Pointer (CSR).
specifies the location of the lower 8-register block,
while the srp0and srp1instructions automatical-
ly select the twin 8-register group mode and spec-
ify the locations of each 8-register block.
There is no limitation on the order or position of
these register groups, other than that they must
start on an 8-register boundary in twin 8-register
mode, or on a 16-register boundary in single 16-
register mode.
Note: In the current ST9 devices, the DP flag is
only for compatibility with software developed for
the first generation of ST9 devices. With the single
memory addressing space, its use is now redun-
dant. It must be kept to 1 with a Sdminstruction at
the beginning of the program to ensure a normal
use of the different memory pointers.
The block number should always be an even
number in single 16-register mode. The 16-regis-
ter group will always start at the block whose
number is the nearest even number equal to or
lower than the block number specified in the srp
instruction. Avoid using odd block numbers, since
this can be confusing if twin mode is subsequently
selected.
2.3.3 Register Pointing Techniques
Two registers within the System register group,
are used as pointers to the working registers. Reg-
ister Pointer 0 (R232) may be used on its own as a
single pointer to a 16-register working space, or in
conjunction with Register Pointer 1 (R233), to
point to two separate 8-register spaces.
Thus:
srp #3will be interpreted as srp #2 and will al-
low using R16 ..R31 as r0 .. r15.
For the purpose of register pointing, the 16 register
groups of the register file are subdivided into 32 8-
register blocks. The values specified with the Set
Register Pointer instructions refer to the blocks to
be pointed to in twin 8-register mode, or to the low-
er 8-register block location in single 16-register
mode.
In single 16-register mode, the working registers
are referred to as r0 to r15. In twin 8-register
mode, registers r0to r7are in the block pointed
to by RP0 (by means of the srp0 instruction),
while registers r8to r15are in the block pointed
to by RP1 (by means of the srp1instruction).
The Set Register Pointer instructions srp, srp0
and srp1 automatically inform the CPU whether
the Register File is to operate in single 16-register
mode or in twin 8-register mode. The srpinstruc-
tion selects the single 16-register group mode and
Caution: Group D registers can only be accessed
as working registers using the Register Pointers,
or by means of the Stack Pointers. They cannot be
addressed explicitly in the form “Rxxx”.
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SYSTEM REGISTERS (Cont’d)
POINTER 0 REGISTER (RP0)
R232 - Read/Write
Register Group: E (System)
Reset Value: xxxx xx00 (xxh)
POINTER 1 REGISTER (RP1)
R233 - Read/Write
Register Group: E (System)
Reset Value: xxxx xx00 (xxh)
7
0
0
7
0
0
RG4 RG3 RG2 RG1 RG0 RPS
0
RG4 RG3 RG2 RG1 RG0 RPS
0
Bits 7:3 = RG[4:0]: Register Group number.
This register is only used in the twin register point-
ing mode. When using the single register pointing
mode, or when using only one of the twin register
groups, the RP1 register must be considered as
RESERVED and may NOT be used as a general
purpose register.
These bits contain the number (in the range 0 to
31) of the register block specified in the srp0 or
srp instructions. In single 16-register mode the
number indicates the lower of the two 8-register
blocks to which the 16 working registers are to be
mapped, while in twin 8-register mode it indicates
the 8-register block to which r0 to r7 are to be
mapped.
Bits 7:3 = RG[4:0]: Register Group number.
These bits contain the number (in the range 0 to
31) of the 8-register block specified in the srp1in-
struction, to which r8to r15are to be mapped.
Bit 2 = RPS: Register Pointer Selector.
This bit is set by the instructions srp0and srp1to
indicate that the twin register pointing mode is se-
lected. The bit is reset by the srpinstruction to in-
dicate that the single register pointing mode is se-
lected.
Bit 2 = RPS: Register Pointer Selector.
This bit is set by the srp0and srp1instructions to
indicate that the twin register pointing mode is se-
lected. The bit is reset by the srpinstruction to in-
dicate that the single register pointing mode is se-
lected.
0: Single register pointing mode
1: Twin register pointing mode
0: Single register pointing mode
1: Twin register pointing mode
Bits 1:0: Reserved. Forced by hardware to zero.
Bits 1:0: Reserved. Forced by hardware to zero.
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SYSTEM REGISTERS (Cont’d)
Figure 22. Pointing to a single group of 16
registers
Figure 23. Pointing to two groups of 8 registers
REGISTER
GROUP
BLOCK
NUMBER
REGISTER
GROUP
BLOCK
NUMBER
REGISTER
FILE
REGISTER
FILE
31
30
29
28
27
26
25
REGISTER
POINTER 0
&
REGISTER
POINTER 1
F
E
D
31
30
29
28
27
26
25
REGISTER
POINTER 0
set by:
F
E
D
srp #2
set by:
instruction
srp0 #2
&
srp1 #7
points to:
instructions
point to:
addressed by
BLOCK 7
9
8
7
6
5
4
3
2
1
0
4
9
8
7
6
5
4
3
2
1
0
4
r15
r8
GROUP 3
3
2
1
0
3
2
1
0
r15
r0
r7
r0
GROUP 1
addressed by
BLOCK 2
GROUP 1
addressed by
BLOCK 2
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SYSTEM REGISTERS (Cont’d)
2.3.4 Paged Registers
– Management of the clock frequency,
Up to 64 pages, each containing 16 registers, may
be mapped to Group F. These paged registers
hold data and control information relating to the
on-chip peripherals, each peripheral always being
associated with the same pages and registers to
ensure code compatibility between ST9 devices.
The number of these registers depends on the pe-
ripherals present in the specific ST9 device. In oth-
er words, pages only exist if the relevant peripher-
al is present.
– Enabling of Bus request and Wait signals when
interfacing to external memory.
MODE REGISTER (MODER)
R235 - Read/Write
Register Group: E (System)
Reset value: 1110 0000 (E0h)
7
0
SSP
USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP
The paged registers are addressed using the nor-
mal register addressing modes, in conjunction with
the Page Pointer register, R234, which is one of
the System registers. This register selects the
page to be mapped to Group F and, once set,
does not need to be changed if two or more regis-
ters on the same page are to be addressed in suc-
cession.
Bit 7 = SSP: System Stack Pointer.
This bit selects an internal or external System
Stack area.
0: External system stack area, in memory space.
1: Internal system stack area, in the Register File
(reset state).
Thus the instructions:
Bit 6 = USP: User Stack Pointer.
This bit selects an internal or external User Stack
area.
0: External user stack area, in memory space.
1: Internal user stack area, in the Register File (re-
set state).
spp #5
ld R242, r4
will load the contents of working register r4 into the
third register of page 5 (R242).
Warning: During an interrupt, the PPR register is
not saved automatically in the stack. If needed, it
should be saved/restored by the user within the in-
terrupt routine.
Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2.
This bit controls the divide-by-2 circuit operating
on the crystal oscillator clock (CLOCK1).
0: Clock divided by 1
PAGE POINTER REGISTER (PPR)
R234 - Read/Write
1: Clock divided by 2
Register Group: E (System)
Reset value: xxxx xx00 (xxh)
Bits 4:2 = PRS[2:0]: CPUCLK Prescaler.
These bits load the prescaler division factor for the
internal clock (INTCLK). The prescaler factor se-
lects the internal clock frequency, which can be di-
vided by a factor from 1 to 8. Refer to the Reset
and Clock Control chapter for further information.
7
0
0
PP5 PP4 PP3 PP2 PP1 PP0
0
Bits 7:2 = PP[5:0]: Page Pointer.
Bit 1 = BRQEN: Bus Request Enable.
0: External Memory Bus Request disabled
1: External Memory Bus Request enabled on
BREQ pin (where available).
These bits contain the number (in the range 0 to
63) of the page specified in the spp instruction.
Once the page pointer has been set, there is no
need to refresh it unless a different page is re-
quired.
Note: Disregard this bit if BREQ pin is not availa-
ble.
Bits 1:0: Reserved. Forced by hardware to 0.
Bit 0 = HIMP: High Impedance Enable.
When a port is programmed as Address and Data
lines to interface external Memory, these lines and
the Memory interface control lines (AS, DS, R/W)
can be forced into the High Impedance state.
0: External memory interface lines in normal state
1: High Impedance state.
2.3.5 Mode Register
The Mode Register allows control of the following
operating parameters:
– Selection of internal or external System and User
Stack areas,
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Note: Setting the HIMP bit is recommended for
– Subroutine Calls
noise reduction when only internal Memory is
used.
When a callinstruction is executed, only the PC
is pushed onto stack, whereas when a calls in-
struction (call segment) is executed, both the PC
and the Code Segment Register are pushed onto
the System Stack.
If the memory access ports are declared as an ad-
dress AND as an I/O port (for example: P10... P14
= Address, and P15... P17 = I/O), the HIMP bit has
no effect on the I/O lines.
– Link Instruction
The link or linku instructions create a C lan-
guage stack frame of user-defined length in the
System or User Stack.
2.3.6 Stack Pointers
Two separate, double-register stack pointers are
available: the System Stack Pointer and the User
Stack Pointer, both of which can address registers
or memory.
All of the above conditions are associated with
their counterparts, such as return instructions,
which pop the stored data items off the stack.
The stack pointers point to the “bottom” of the
stacks which are filled using the push commands
and emptied using the pop commands. The stack
pointer is automatically pre-decremented when
data is “pushed” in and post-incremented when
data is “popped” out.
User Stack
The User Stack provides a totally user-controlled
stacking area.
The User Stack Pointer consists of two registers,
R236 and R237, which are both used for address-
ing a stack in memory. When stacking in the Reg-
ister File, the User Stack Pointer High Register,
R236, becomes redundant but must be consid-
ered as reserved.
The push and pop commands used to manage the
System Stack may be addressed to the User
Stack by adding the suffix “u”. To use a stack in-
struction for a word, the suffix “w”is added. These
suffixes may be combined.
Stack Pointers
Both System and User stacks are pointed to by
double-byte stack pointers. Stacks may be set up
in RAM or in the Register File. Only the lower byte
will be required if the stack is in the Register File.
The upper byte must then be considered as re-
served and must not be used as a general purpose
register.
When bytes (or words) are “popped” out from a
stack, the contents of the stack locations are un-
changed until fresh data is loaded. Thus, when
data is “popped” from a stack area, the stack con-
tents remain unchanged.
Note: Instructions such as: pushuw RR236 or
pushw RR238, as well as the corresponding
pop instructions (where R236 & R237, and R238
& R239 are themselves the user and system stack
pointers respectively), must not be used, since the
pointer values are themselves automatically
changed by the pushor popinstruction, thus cor-
rupting their value.
The stack pointer registers are located in the Sys-
tem Group of the Register File, this is illustrated in
Table 6.
Stack Location
Care is necessary when managing stacks as there
is no limit to stack sizes apart from the bottom of
any address space in which the stack is placed.
Consequently programmers are advised to use a
stack pointer value as high as possible, particular-
ly when using the Register File as a stacking area.
System Stack
The System Stack is used for the temporary stor-
age of system and/or control data, such as the
Flag register and the Program counter.
Group D is a good location for a stack in the Reg-
ister File, since it is the highest available area. The
stacks may be located anywhere in the first 14
groups of the Register File (internal stacks) or in
RAM (external stacks).
The following automatically push data onto the
System Stack:
– Interrupts
When entering an interrupt, the PC and the Flag
Register are pushed onto the System Stack. If the
ENCSR bit in the EMR2 register is set, then the
Code Segment Register is also pushed onto the
System Stack.
Note. Stacks must not be located in the Paged
Register Group or in the System Register Group.
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SYSTEM REGISTERS (Cont’d)
USER STACK POINTER HIGH REGISTER
(USPHR)
SYSTEM STACK POINTER HIGH REGISTER
(SSPHR)
R236 - Read/Write
R238 - Read/Write
Register Group: E (System)
Reset value: undefined
Register Group: E (System)
Reset value: undefined
7
0
7
0
USP15 USP14 USP13 USP12 USP11 USP10 USP9 USP8
SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8
USER STACK POINTER LOW REGISTER
(USPLR)
R237 - Read/Write
SYSTEM STACK POINTER LOW REGISTER
(SSPLR)
R239 - Read/Write
Register Group: E (System)
Reset value: undefined
Register Group: E (System)
Reset value: undefined
7
0
7
0
USP7 USP6 USP5 USP4 USP3 USP2 USP1 USP0
SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Figure 24. Internal Stack Mode
Figure 25. External Stack Mode
REGISTER
FILE
REGISTER
FILE
STACK POINTER (LOW)
STACK POINTER (LOW)
&
points to:
F
F
STACK POINTER (HIGH)
point to:
MEMORY
E
E
STACK
D
D
STACK
4
3
2
1
0
4
3
2
1
0
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2.4 MEMORY ORGANIZATION
Code and data are accessed within the same line-
ar address space. All of the physically separate
memory areas, including the internal ROM, inter-
nal RAM and external memory are mapped in a
common address space.
The mapping of the various memory areas (inter-
nal RAM or ROM, external memory) differs from
device to device. Each 64-Kbyte physical memory
segment is mapped either internally or externally;
if the memory is internal and smaller than 64
Kbytes, the remaining locations in the 64-Kbyte
segment are not used (reserved).
The ST9 provides a total addressable memory
space of 4 Mbytes. This address space is ar-
ranged as 64 segments of 64 Kbytes; each seg-
ment is again subdivided into four 16 Kbyte pages.
Refer to the Register and Memory Map Chapter
for more details on the memory map.
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2.5 MEMORY MANAGEMENT UNIT
The CPU Core includes a Memory Management
Unit (MMU) which must be programmed to per-
form memory accesses (even if external memory
is not used).
sub-divided into 2 main groups: a first group of four
8-bit registers (DPR[3:0]), and a second group of
three 6-bit registers (CSR, ISR, and DMASR). The
first group is used to extend the address during
Data Memory access (DPR[3:0]). The second is
used to manage Program and Data Memory ac-
cesses during Code execution (CSR), Interrupts
Service Routines (ISR or CSR), and DMA trans-
fers (DMASR or ISR).
The MMU is controlled by 7 registers and 2 bits
(ENCSR and DPRREM) present in EMR2, which
may be written and read by the user program.
These registers are mapped within group F, Page
21 of the Register File. The 7 registers may be
Figure 26. Page 21 Registers
Page 21
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
Relocation of P[3:0] and DPR[3:0] Registers
SSPLR
SSPLR
SSPHR
USPLR
USPHR
MODER
PPR
SSPHR
USPLR
USPHR
MODER
PPR
DMASR
ISR
RP1
RP0
FLAGR
CICR
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
RP1
DMASR
ISR
DMASR
ISR
MMU
RP0
FLAGR
CICR
P5DR
P4DR
DPR3
DPR2
DPR1
DPR0
EMR2
EMR1
CSR
DPR3
DPR2
DPR1
DPR0
EMR2
EMR1
CSR
P3DR
P2DR
P1DR
P0DR
EMR2
EMR1
CSR
EM
MMU
DPR3
DPR2
DPR1
DPR0
MMU
Bit DPRREM=0
(default setting)
Bit DPRREM=1
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2.6 ADDRESS SPACE EXTENSION
To manage 4 Mbytes of addressing space, it is
necessary to have 22 address bits. The MMU
adds 6 bits to the usual 16-bit address, thus trans-
lating a 16-bit virtual address into a 22-bit physical
address. There are 2 different ways to do this de-
pending on the memory involved and on the oper-
ation being performed.
are involved in the following virtual address rang-
es:
DPR0: from 0000h to 3FFFh;
DPR1: from 4000h to 7FFFh;
DPR2: from 8000h to BFFFh;
DPR3: from C000h to FFFFh.
2.6.1 Addressing 16-Kbyte Pages
The contents of the selected DPR register specify
one of the 256 possible data memory pages. This
8-bit data page number, in addition to the remain-
ing 14-bit page offset address forms the physical
22-bit address (see Figure 27).
This extension mode is implicitly used to address
Data memory space if no DMA is being performed.
The Data memory space is divided into 4 pages of
16 Kbytes. Each one of the four 8-bit registers
(DPR[3:0], Data Page Registers) selects a differ-
ent 16-Kbyte page. The DPR registers allow ac-
cess to the entire memory space which contains
256 pages of 16 Kbytes.
A DPR register cannot be modified via an address-
ing mode that uses the same DPR register. For in-
stance, the instruction “POPW DPR0” is legal only
if the stack is kept either in the register file or in a
memory location above 8000h, where DPR2 and
DPR3 are used. Otherwise, since DPR0 and
DPR1 are modified by the instruction, unpredicta-
ble behaviour could result.
Data paging is performed by extending the 14 LSB
of the 16-bit address with the contents of a DPR
register. The two MSBs of the 16-bit address are
interpreted as the identification number of the DPR
register to be used. Therefore, the DPR registers
Figure 27. Addressing via DPR[3:0]
16-bit virtual address
MMU registers
DPR0
00
DPR1
01
DPR2
10
DPR3
11
8 bits
14 LSB
22-bit physical address
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ADDRESS SPACE EXTENSION (Cont’d)
2.6.2 Addressing 64-Kbyte Segments
Most of these registers do not have a default value
after reset.
This extension mode is used to address Data
memory space during a DMA and Program mem-
ory space during any code execution (normal code
and interrupt routines).
2.7.1 DPR[3:0]: Data Page Registers
The DPR[3:0] registers allow access to the entire 4
Mbyte memory space composed of 256 pages of
16 Kbytes.
Three registers are used: CSR, ISR, and DMASR.
The 6-bit contents of one of the registers CSR,
ISR, or DMASR define one out of 64 Memory seg-
ments of 64 Kbytes within the 4 Mbytes address
space. The register contents represent the 6
MSBs of the memory address, whereas the 16
LSBs of the address (intra-segment address) are
given by the virtual 16-bit address (see Figure 28).
2.7.1.1 Data Page Register Relocation
If these registers are to be used frequently, they
may be relocated in register group E, by program-
ming bit 5 of the EMR2-R246 register in page 21. If
this bit is set, the DPR[3:0] registers are located at
R224-227 in place of the Port 0-3 Data Registers,
which are re-mapped to the default DPR's loca-
tions: R240-243 page 21.
2.7 MMU REGISTERS
The MMU uses 7 registers mapped into Group F,
Page 21 of the Register File and 2 bits of the
EMR2 register.
Data Page Register relocation is illustrated in Fig-
ure 26.
Figure 28. Addressing via CSR, ISR, and DMASR
16-bit virtual address
MMU registers
ISR
DMASR
CSR
1
2
3
1
2
Fetching program
instruction
Data Memory
accessed in DMA
6 bits
Fetching interrupt
instruction or DMA
3
access to Program
Memory
22-bit physical address
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MMU REGISTERS (Cont’d)
DATA PAGE REGISTER 0 (DPR0)
R240 - Read/Write
DATA PAGE REGISTER 2 (DPR2)
R242 - Read/Write
Register Page: 21
Register Page: 21
Reset value: undefined
Reset value: undefined
This register is relocated to R224 if EMR2.5 is set.
This register is relocated to R226 if EMR2.5 is set.
7
0
7
0
DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0
_7 _6 _5 _4 _3 _2 _1 _0
DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2
_7 _6 _5 _4 _3 _2 _1 _0
Bits 7:0 = DPR0_[7:0]: These bits define the 16-
Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to ex-
tend the address during a Data Memory access.
The DPR0 register is used when addressing the
virtual address range 0000h-3FFFh.
Bits 7:0 = DPR2_[7:0]: These bits define the 16-
Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR2 register is involved when the virtual address
is in the range 8000h-BFFFh.
DATA PAGE REGISTER 1 (DPR1)
R241 - Read/Write
DATA PAGE REGISTER 3 (DPR3)
R243 - Read/Write
Register Page: 21
Register Page: 21
Reset value: undefined
Reset value: undefined
This register is relocated to R225 if EMR2.5 is set.
This register is relocated to R227 if EMR2.5 is set.
7
0
7
0
DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1
_7 _6 _5 _4 _3 _2 _1 _0
DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3
_7 _6 _5 _4 _3 _2 _1 _0
Bits 7:0 = DPR1_[7:0]: These bits define the 16-
Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to ex-
tend the address during a Data Memory access.
The DPR1 register is used when addressing the
virtual address range 4000h-7FFFh.
Bits 7:0 = DPR3_[7:0]: These bits define the 16-
Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR3 register is involved when the virtual address
is in the range C000h-FFFFh.
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MMU REGISTERS (Cont’d)
2.7.2 CSR: Code Segment Register
ISR and ENCSR bit (EMR2 register) are also de-
scribed in the chapter relating to Interrupts, please
refer to this description for further details.
This register selects the 64-Kbyte code segment
being used at run-time to access instructions. It
can also be used to access data if the spminstruc-
tion has been executed (or ldpp, ldpd, lddp).
Only the 6 LSBs of the CSR register are imple-
mented, and bits 6 and 7 are reserved. The CSR
register allows access to the entire memory space,
divided into 64 segments of 64 Kbytes.
Bits 7:6 = Reserved, keep in reset state.
Bits 5:0 = ISR_[5:0]: These bits define the 64-
Kbyte memory segment (among 64) which con-
tains the interrupt vector table and the code for in-
terrupt service routines and DMA transfers (when
the PS bit of the DAPR register is reset). These
bits are used as the most significant address bits
(A21-16). The ISR is used to extend the address
space in two cases:
To generate the 22-bit Program memory address,
the contents of the CSR register is directly used as
the 6 MSBs, and the 16-bit virtual address as the
16 LSBs.
Note: The CSR register should only be read and
not written for data operations (there are some ex-
ceptions which are documented in the following
paragraph). It is, however, modified either directly
by means of the jps and calls instructions, or
indirectly via the stack, by means of the retsin-
struction.
– Whenever an interrupt occurs: ISR points to the
64-Kbyte memory segment containing the inter-
rupt vector table and the interrupt service routine
code. See also the Interrupts chapter.
– During DMA transactions between the peripheral
and memory when the PS bit of the DAPR regis-
ter is reset : ISR points to the 64 K-byte Memory
segment that will be involved in the DMA trans-
action.
CODE SEGMENT REGISTER (CSR)
R244 - Read/Write
Register Page: 21
Reset value: 0000 0000 (00h)
7
0
0
2.7.4 DMASR: DMA Segment Register
DMA SEGMENT REGISTER (DMASR)
R249 - Read/Write
Register Page: 21
Reset value: undefined
0
CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 CSR_0
Bits 7:6 = Reserved, keep in reset state.
7
0
0
Bits 5:0 = CSR_[5:0]: These bits define the 64-
Kbyte memory segment (among 64) which con-
tains the code being executed. These bits are
used as the most significant address bits (A21-16).
DMA
DMA
DMA
DMA
DMA
DMA
0
SR_5 SR_4 SR_3 SR_2 SR_1 SR_0
Bits 7:6 = Reserved, keep in reset state.
2.7.3 ISR: Interrupt Segment Register
INTERRUPT SEGMENT REGISTER (ISR)
R248 - Read/Write
Bits 5:0 = DMASR_[5:0]: These bits define the 64-
Kbyte Memory segment (among 64) used when a
DMA transaction is performed between the periph-
eral's data register and Memory, with the PS bit of
the DAPR register set. These bits are used as the
most significant address bits (A21-16). If the PS bit
is reset, the ISR register is used to extend the ad-
dress.
Register Page: 21
Reset value: undefined
7
0
0
0
ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
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ST92F124/F150/F250 - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
Figure 29. Memory Addressing Scheme (example)
4M bytes
3FFFFFh
294000h
16K
DPR3
DPR2
DPR1
DPR0
240000h
23FFFFh
20C000h
16K
16K
200000h
1FFFFFh
040000h
03FFFFh
64K
64K
030000h
DMASR
020000h
ISR
010000h
00C000h
16K
64K
CSR
000000h
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ST92F124/F150/F250 - DEVICE ARCHITECTURE
2.8 MMU USAGE
2.8.1 Normal Program Execution
Program memory is organized as a set of 64-
Kbyte segments. The program can span as many
segments as needed, but a procedure cannot
stretch across segment boundaries. jps, calls
and retsinstructions, which automatically modify
the CSR, must be used to jump across segment
boundaries. Writing to the CSR is forbidden during
normal program execution because it is not syn-
chronized with the opcode fetch. This could result
in fetching the first byte of an instruction from one
memory segment and the second byte from anoth-
er. Writing to the CSR is allowed when it is not be-
ing used, i.e during an interrupt service routine if
ENCSR is reset.
used instead of the CSR, and the interrupt stack
frame is kept exactly as in the original ST9 (only
the PC and flags are pushed). This avoids the
need to save the CSR on the stack in the case of
an interrupt, ensuring a fast interrupt response
time. The drawback is that it is not possible for an
interrupt service routine to perform segment
calls/jps: these instructions would update the
CSR, which, in this case, is not used (ISR is used
instead). The code size of all interrupt service rou-
tines is thus limited to 64 Kbytes.
If, instead, bit 6 of the EMR2 register is set, the
ISR is used only to point to the interrupt vector ta-
ble and to initialize the CSR at the beginning of the
interrupt service routine: the old CSR is pushed
onto the stack together with the PC and the flags,
and then the CSR is loaded with the ISR. In this
case, an iret will also restore the CSR from the
stack. This approach lets interrupt service routines
access the whole 4-Mbyte address space. The
drawback is that the interrupt response time is
slightly increased, because of the need to also
save the CSR on the stack. Compatibility with the
original ST9 is also lost in this case, because the
interrupt stack frame is different; this difference,
however, would not be noticeable for a vast major-
ity of programs.
Note that a routine must always be called in the
same way, i.e. either always with callor always
with calls, depending on whether the routine
ends with ret or rets. This means that if the rou-
tine is written without prior knowledge of the loca-
tion of other routines which call it, and all the pro-
gram code does not fit into a single 64-Kbyte seg-
ment, then calls/retsshould be used.
In typical microcontroller applications, less than 64
Kbytes of RAM are used, so the four Data space
pages are normally sufficient, and no change of
DPR[3:0] is needed during Program execution. It
may be useful however to map part of the ROM
into the data space if it contains strings, tables, bit
maps, etc.
Data memory mapping is independent of the value
of bit 6 of the EMR2 register, and remains the
same as for normal code execution: the stack is
the same as that used by the main program, as in
the ST9. If the interrupt service routine needs to
access additional Data memory, it must save one
(or more) of the DPRs, load it with the needed
memory page and restore it before completion.
If there is to be frequent use of paging, the user
can set bit 5 (DPRREM) in register R246 (EMR2)
of Page 21. This swaps the location of registers
DPR[3:0] with that of the data registers of Ports 0-
3. In this way, DPR registers can be accessed
without the need to save/set/restore the Page
Pointer Register. Port registers are therefore
moved to page 21. Applications that require a lot of
paging typically use more than 64 Kbytes of exter-
nal memory, and as ports 0, 1 and 9 are required
to address it, their data registers are unused.
2.8.3 DMA
Depending on the PS bit in the DAPR register (see
DMA chapter) DMA uses either the ISR or the
DMASR for memory accesses: this guarantees
that a DMA will always find its memory seg-
ment(s), no matter what segment changes the ap-
plication has performed. Unlike interrupts, DMA
transactions cannot save/restore paging registers,
so a dedicated segment register (DMASR) has
been created. Having only one register of this kind
means that all DMA accesses should be pro-
grammed in one of the two following segments:
the one pointed to by the ISR (when the PS bit of
the DAPR register is reset), and the one refer-
enced by the DMASR (when the PS bit is set).
2.8.2 Interrupts
The ISR register has been created so that the in-
terrupt routines may be found by means of the
same vector table even after a segment jump/call.
When an interrupt occurs, the CPU behaves in
one of 2 ways, depending on the value of the ENC-
SR bit in the EMR2 register (R246 on Page 21).
If this bit is reset (default condition), the CPU
works in original ST9 compatibility mode. For the
duration of the interrupt service routine, the ISR is
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
3 SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
3.1 INTRODUCTION
The Flash circuitry contains one array divided in
two main parts that can each be read independ-
ently. The first part contains the main Flash array
for code storage, a reserved array (TestFlash) for
system routines and a 128-byte area available as
one time programmable memory (OTP). The sec-
ond part contains the two dedicated Flash sectors
used for EEPROM Hardware Emulation.
The write operations of the two parts are managed
by an embedded Program/Erase Controller.
Through a dedicated RAM buffer the Flash and the
E
3 TM can be written in blocks of 16 bytes.
Figure 30. Flash Memory Structure (Example for 64K Flash device)
sense amplifiers
Address
Data
230000h
231F80h
TestFlash
8 Kbytes
User OTP and Protection registers
Register
Interface
000000h
RAM buffer
16 bytes
Sector F0
8 Kbytes
Sector F1
8 Kbytes
002000h
004000h
Program / Erase
Controller
Sector F2
48 Kbytes
010000h
22CFFFh
228000h
Hardware emulated EEPROM sectors
8 Kbytes (Reserved)
2203FFh
220000h
Emulated EEPROM
1 Kbyte
sense amplifiers
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
Figure 31. Flash Memory Structure (Example for 128K Flash device)
sense amplifiers
Address
Data
230000h
231F80h
TestFlash
8 Kbytes
User OTP and Protection registers
Register
Interface
000000h
002000h
004000h
RAM buffer
16 bytes
Sector F0
8 Kbytes
Sector F1
8 Kbytes
Sector F2
48 Kbytes
Program / Erase
Controller
010000h
Sector F3
64 Kbytes
22CFFFh
228000h
Hardware emulated EEPROM sectors
8 Kbytes (Reserved)
2203FFh
220000h
Emulated EEPROM
1 Kbyte
sense amplifiers
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
3.2 FUNCTIONAL DESCRIPTION
3.2.1 Structure
3.2.2 EEPROM Emulation
The memory is composed of three parts:
A hardware EEPROM emulation is implemented
using special flash sectors to emulate an EEP-
– a sector wih the system routines (TestFlash) and
the user OTP area
3 TM
ROM memory. This E
is directly addressed
from 220000h to 2203FFh.
– 4 main sectors for code
– an emulated EEPROM
(For more details on hardware EEPROM emula-
tion, see application note AN1152)
124 bytes are available to the user as an OTP ar-
ea. The user can program these bytes, but cannot
erase them.
Table 7. Memory Structure for 64K Flash device
Sector
Addresses
Max Size
TestFlash (TF) (Reserved)
230000h to 231F7Fh
8064 bytes
OTP Area
Protection Registers (reserved)
231F80h to 231FFBh
231FFCh to 231FFFh
124 bytes
4 bytes
Flash 0 (F0)
Flash 1 (F1)
Flash 2 (F2)
000000h to 001FFFh
002000h to 003FFFh
004000h to 00FFFFh
8 Kbytes
8 Kbytes
48 Kbytes
Hardware Emulated EEPROM sectors
(reserved)
228000h to 22CFFFh
220000h to 2203FFh
8 Kbytes
1 Kbyte
Emulated EEPROM
Table 8. Memory Structure for 128K Flash device
Sector
Addresses
Max Size
TestFlash (TF) (Reserved)
230000h to 231F7Fh
8064 bytes
OTP Area
Protection Registers (reserved)
231F80h to 231FFBh
231FFCh to 231FFFh
124 bytes
4 bytes
Flash 0 (F0)
Flash 1 (F1)
Flash 2 (F2)
Flash 3 (F3)
000000h to 001FFFh
002000h to 003FFFh
004000h to 00FFFFh
010000h to 01FFFFh
8 Kbytes
8 Kbytes
48 Kbytes
64 Kbytes
Hardware Emulated EEPROM sectors
(reserved)
228000h to 22CFFFh
220000h to 2203FFh
8 Kbytes
1 Kbyte
Emulated EEPROM
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
FUNCTIONAL DESCRIPTION (Cont’d)
Table 9. Memory Structure for 256K Flash device
Sector
Addresses
Max Size
TestFlash (TF) (Reserved)
230000h to 231F7Fh
8064 bytes
OTP Area
Protection Registers (reserved)
231F80h to 231FFBh
231FFCh to 231FFFh
124 bytes
4 bytes
Flash 0 (F0)
Flash 1 (F1)
Flash 2 (F2)
Flash 3 (F3)
Flash 4 (F4)
Flash 5 (F5)
000000h to 001FFFh
002000h to 003FFFh
004000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
8 Kbytes
8 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
Hardware Emulated EEPROM sectors
(reserved)
228000h to 22CFFFh
220000h to 2203FFh
8 Kbytes
1 Kbyte
Emulated EEPROM
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
FUNCTIONAL DESCRIPTION (Cont’d)
3.2.3 Operation
The memory has a register interface mapped in
memory space (segment 22h). All operations are
enabled through the FCR (Flash Control Register),
ECR (E3 TM Control Register).
If the RESET pin is activated during a write opera-
tion, the write operation is interrupted. In this case
the user must repeat this last write operation fol-
lowing power on or reset. If the internal supply volt-
age drops below the V threshold, a reset se-
IT-
All operations on the Flash must be executed from
quence is generated automatically by hardware.
another memory (internal RAM, E3 TM, external
memory).
3 TM
Flash (including TestFlash) and E
are inde-
3.2.4 E3 TM Update Operation
pendent, this means that one can be read while
the other is written. However simultaneous Flash
and E3 TM write operations are forbidden.
3 TM
The update of the E
content can be made by
pages of 16 consecutive bytes. The Page Update
operation allows up to 16 bytes to be loaded into
the RAM buffer that replace the ones already con-
tained in the specified address.
An interrupt can be generated at the end of a
3 TM
Flash or an E
write operation: this interrupt is
multiplexed with an external interrupt EXTINTx
(device dependent) to generate an interrupt INTx.
Each time a Page Update operation is executed in
the E3 TM, the RAM buffer content is programmed
in the next free block relative to the specified page
(the RAM buffer is previously automatically filled
with old data for all the page addresses not select-
ed for updating). If all the 4 blocks of the specified
page in the current E3 TM sector are full, the page
content is copied to the complementary sector,
that becomes the new current one.
The status of a write operation inside the Flash
and the E3 TM memories can be monitored through
the FESR[1:0] registers.
Control and Status registers are mapped in mem-
ory (segment 22h), as shown in the following fig-
ure.
Figure 32. Control and Status Register Map.
Register Interface
After that the specified page has been copied to
the next free block, one erase phase is executed
on the complementary sector, if the 4 erase phas-
es have not yet been executed. When the selected
page is copied to the complementary sector, the
remaining 63 pages are also copied to the first
block of the new sector; then the first erase phase
is executed on the previous full sector. All this is
executed in a hidden manner, and the End Page
Update Interrupt is generated only after the end of
the complete operation.
/
FCR
ECR
FESR0
FESR1
221000h
221001h
221002h
221003h
224000h
224001h /
/
224002h
224003h
/
In order to use the same data pointer register
3
TM
At Reset the two status pages are read in order to
detect which is the sector that is currently mapping
(DPR) to point both to the E
(220000h-
2203FFh) and to these control and status regis-
3
the E TM, and in which block each page is
3 TM
ters, the Flash and E
control registers are
mapped. A system defined routine written in Test-
Flash is executed at reset, so that any previously
aborted write operation is restarted and complet-
ed.
mapped not only at page 0x89 (224000h-
224003h) but also on page 0x88 (221000h-
221003h).
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
Figure 33. Hardware Emulation Flow
Emulation Flow
Reset
Program selected
Page from RAM buffer
in next free block
Read Status Pages
new
Yes
Yes
3 TM
Map E
sector ?
in current sector
No
Copy all other Pages
into RAM buffer;
then program them
in next free block
Write operation
to complete ?
Yes
No
Complete
Write operation
Update
Complementary
sector erased ?
Status page
No
1/4 erase of
Wait for
complementary sector
Update commands
Page
Update
Update
Status Page
Command
End Page
Update
Interrupt
(to Core)
3.2.5 Important note on Flash Erase Suspend
Refer to Section 13.1.1 on page 407;
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
3.3 REGISTER DESCRIPTION
3.3.1 Control Registers
code: sectors F0-F3 (or F0-F5 for the ST92F250),
3 TM
TestFlash and E
excluded. The execution
FLASH CONTROL REGISTER (FCR)
Address: 224000h / 221000h- Read/Write
Reset value: 0000 0000 (00h)
starts by setting the FWMS bit. It is not necessary
to pre-program the sectors to 00h, because this is
done automatically.
0: Deselect chip erase
1: Select chip erase
7
6
5
4
3
2
1
0
FWMS FPAGE FCHIP FBYTE FSECT FSUSP PROT FBUSY
Bit 4 = FBYTE: Flash byte program (Read/Write).
This bit must be set to select the Byte Program op-
eration in Flash memory. This bit is automatically
reset at the end of the Byte Program operation.
The Flash Control Register is used to enable all
the operations for the Flash and the TestFlash
memories.
The Byte Program operation allows “0”s to be pro-
grammed in place of “1”s. Data to be programmed
and an address in which to program must be pro-
vided (through an LD instruction, for example) be-
fore starting execution by setting bit FWMS.
0: Deselect byte program
Bit 7 = FWMS: Flash Write Mode Start (Read/
Write).
This bit must be set to start each write/erase oper-
ation in Flash memory. At the end of the write/
erase operation or during a Sector Erase Suspend
this bit is automatically reset. To resume a sus-
pended Sector Erase operation, this bit must be
set again. Resetting this bit by software does not
stop the current write operation.
1: Select byte program
Bit 3 = FSECT: Flash sector erase (Read/Write).
This bit must be set to select the Sector Erase op-
eration in Flash memory. This bit is automatically
reset at the end of the Sector Erase operation.
0: No effect
1: Start Flash write
The Sector Erase operation erases all the Flash
locations to FFh. From 1 to 6 sectors (F0-F5) can
be simultaneously erased. These sectors can be
entered before starting the execution by setting
the FWMS bit. An address located in the sector to
erase must be provided (through an LD instruc-
tion, for example), while the data to be provided is
don’t care. It is not necessary to pre-program the
sectors to 00h, because this is done automatically.
0: Deselect sector erase
Bit 6 = FPAGE: Flash Page program (Read/Write).
This bit must be set to select the Page Program
operation in Flash memory. This bit is automatical-
ly reset at the end of the Page Program operation.
The Page Program operation allows to program
“0”s in place of “1”s. From 1 to 16 bytes can be en-
tered (in any order, no need for an ordered ad-
dress sequence) before starting the execution by
setting the FWMS bit. All the addresses must be-
long to the same page (only the 4 LSBs of address
can change). Data to be programmed and ad-
dresses in which to program must be provided
(through an LD instruction, for example). Data
contained in page addresses that are not entered
are left unchanged.
1: Select sector erase
Bit 2 = FSUSP: Flash sector erase suspend
(Read/Write).
This bit must be set to suspend the current Sector
Erase operation in Flash memory in order to read
data to or from program data to a sector not being
erased. The FSUSP bit must be reset (and FWMS
must be set again) to resume a suspended Sector
Erase operation.
0: Deselect page program
1: Select page program
Bit 5 = FCHIP: Flash CHIP erase (Read/Write).
This bit must be set to select the Chip Erase oper-
ation in Flash memory. This bit is automatically re-
set at the end of the Chip Erase operation.
The Erase Suspend operation resets the Flash
memory to normal read mode (automatically reset-
ting bit FBUSY) in a maximum time of 15µs.
The Chip Erase operation erases all the Flash lo-
cations to FFh. The operation is limited to Flash
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
REGISTER DESCRIPTION (Cont’d)
When in Erase Suspend the memory accepts only
the following operations: Read, Erase Resume
and Byte Program. Updating the E3 TM memory is
not possible during a Flash Erase Suspend.
0: Resume sector erase when FWMS is set again.
1: Suspend Sector erase
E
3 TM CONTROL REGISTER (ECR)
Address: 224001h /221001h- Read/Write
Reset value: 000x x000 (xxh)
7
6
5
4
3
2
1
0
EWMS EPAGE ECHIP
WFIS FEIEN EBUSY
Bit 1 = PROT: Set Protection (Read/Write).
This bit must be set to select the Set Protection op-
eration. This bit is automatically reset at the end of
the Set Protection operation.
The E3 TM Control Register is used to enable all the
operations for the E3 TM memory.
The ECR also contains two bits (WFIS and FEIEN)
that are related to both Flash and E3 TM memories.
The Set Protection operation allows “0”s in place
of “1”s to be programmed in the four Non Volatile
Protection registers. From 1 to 4 bytes can be en-
tered (in any order, no need for an ordered ad-
dress sequence) before starting the execution by
setting the FWMS bit. Data to be programmed and
addresses in which to program must be provided
(through an LD instruction, for example). Protec-
tion contained in addresses that are not entered
are left unchanged.
Bit 7 = EWMS: E3 TM Write Mode Start.
This bit must be set to start every write/erase oper-
ation in the E3 TM memory. At the end of the write/
erase operation this bit is automatically reset. Re-
setting by software this bit does not stop the cur-
rent write operation.
0: No effect
1: Start E3 TM write
0: Deselect protection
1: Select protection
Bit 6 = EPAGE: E3 TM page update.
This bit must be set to select the Page Update op-
eration in E3 TM memory. The Page Update opera-
tion allows to write a new content: both “0”s in
place of “1”s and “1”s in place of “0”s. From 1 to 16
bytes can be entered (in any order, no need for an
ordered address sequence) before starting the ex-
ecution by setting bit EWMS. All the addresses
must belong to the same page (only the 4 LSBs of
address can change). Data to be programmed and
addresses in which to program must be provided
(through an LD instruction, for example). Data
contained in page addresses that are not entered
are left unchanged. This bit is automatically reset
at the end of the Page Update operation.
Bit 0 = FBUSY: Flash Busy (Read Only).
This bit is automatically set during Page Program,
Byte Program, Sector Erase or Set Protection op-
erations when the first address to be modified is
latched in Flash memory, or during Chip Erase op-
eration when bit FWMS is set. When this bit is set
every read access to the Flash memory will output
invalid data (FFh equivalent to a NOP instruction),
while every write access to the Flash memory will
be ignored. At the end of the write operations or
during a Sector Erase Suspend this bit is automat-
ically reset and the memory returns to read mode.
After an Erase Resume this bit is automatically set
again. The FBUSY bit remains high for a maxi-
mum of 10µs after Power-Up and when exiting
Power-Down mode, meaning that the Flash mem-
ory is not yet ready to be accessed.
0: Deselect page update
1: Select page update
Bit 5 = ECHIP: E3 TM chip erase.
This bit must be set to select the Chip Erase oper-
ation in the E3 TM memory. The Chip Erase opera-
tion allows to erase all the E3 TM locations to FFh.
The execution starts by setting bit EWMS. This bit
is automatically reset at the end of the Chip Erase
operation.
0: Flash not busy
1: Flash busy
0: Deselect chip erase
1: Select chip erase
Bit 4:3 = Reserved.
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
REGISTER DESCRIPTION (Cont’d)
Bit 2 = WFIS: Wait For Interrupt Status.
0: E3 TM not busy
1: E3 TM busy
If this bit is reset, the WFI instruction puts the
Flash macrocell in Stand-by mode (immediate
read possible, but higher consumption: 100 µA); if
it is set, the WFI instruction puts the Flash macro-
cell in Power-Down mode (recovery time of 10µs
needed before reading, but lower consumption:
10µA). The Stand-by mode or the Power-Down
mode will be entered only at the end of any current
Flash or E3 TM write operation.
3.3.2 Status Registers
Two Status Registers (FESR[1:0] are available to
check the status of the current write operation in
Flash and E3 TM memories.
During a Flash or an E3 TM write operation any at-
tempt to read the memory under modification will
output invalid data (FFh equivalent to a NOP in-
struction). This means that the Flash memory is
not fetchable when a write operation is active: the
write operation commands must be given from an-
other memory (E3 TM, internal RAM, or external
memory).
In the same way following an HALT or a STOP in-
struction, the Memory enters Power-Down mode
only after the completion of any current write oper-
ation.
0: Flash in Stand-by mode on WFI
1: Flash in Power-Down mode on WFI
FLASH & E3 TM STATUS REGISTER 0 (FESR0)
Address: 224002h /221002h -Read/Write
Reset value: 0000 0000 (00h)
Note: HALT or STOP mode can be exited without
problems, but the user should take care when ex-
iting WFI Power Down mode. If WFIS is set, the
user code must reset the XT_DIV16 bit in the
R242 register (page 55) before executing the WFI
instruction. When exiting WFI mode, this gives the
Flash enough time to wake up before the interrupt
vector fetch.
7
6
5
4
3
2
1
0
FEERR FESS6 FESS5 FESS4 FESS3 FESS2 FESS1 FESS0
Bit 7 = FEERR: Flash or E3 TM write ERRor (Read/
Write).
Bit 1 = FEIEN: Flash & E3 TM Interrupt enable.
This bit selects the source of interrupt channel
INTx between the external interrupt pin and the
Flash/E3 TM End of Write interrupt. Refer to the In-
terrupt chapter for the channel number.
0: External interrupt enabled
This bit is set by hardware when an error occurs
during a Flash or an E3 TM write operation. It must
be cleared by software.
0: Write OK
1: Flash or E3 TM write error
1: Flash & E3 TM Interrupt enabled
Bit 0 = EBUSY: E3 TM Busy (Read Only).
Bit 6:0 = FESS[6:0]. Flash and E3 TM Sectors Sta-
tus Bits (Read Only).
This bit is automatically set during a Page Update
operation when the first address to be modified is
latched in the E3 TM memory, or during Chip Erase
operation when bit EWMS is set. At the end of the
write operation or during a Sector Erase Suspend
this bit is automatically reset and the memory re-
turns to read mode. When this bit is set every read
access to the E3 TM memory will output invalid data
These bits are set by hardware and give the status
of the 7 Flash and E3 TM sectors.
– FESS6 = TestFlash and OTP
– FESS5:4 = E3 TM sectors
For 128K and 64K Flash devices:
– FESS3:0 = Flash sectors (F3:0)
For the ST92F250 (256K):
(FFh equivalent to a NOP instruction), while every
3 TM
write access to the E
memory will be ignored.
At the end of the write operation this bit is automat-
ically reset and the memory returns to read mode.
Bit EBUSY remains high for a maximum of 10ms
– FESS3 gives the status of F5, F4 and F3 sectors:
the status of all these three sectors are ORed on
this bit
after Power-Up and when exiting Power-Down
3 TM
mode, meaning that the E
ready to be accessed.
memory is not yet
– FESS2:0 = Flash sectors (F2:0)
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
REGISTER DESCRIPTION (Cont’d)
The meaning of the FESSx bit for sector x is given
in Table 10.
Bit 5 = SWER. Swap or 1 over 0 Error (Read On-
ly).
Table 10. Sector Status Bits
FBUSY
This bit has two different meanings, depending on
whether the current write operation is to Flash or
E
3 TM memory.
FESSx=1
meaning
FEERR
FSUSP
EBUSY
In Flash memory this bit is automatically set when
trying to program at 1 bits previously set at 0 (this
does not happen when programming the Protec-
tion bits). This error is not due to a failure of the
Flash cell, but only flags that the desired data has
not been written.
Write Error in
Sector x
1
-
-
Write operation
on-going in sec-
tor x
0
1
-
3 TM
In the E
memory this bit is automatically set
when a Program error occurs during the swapping
of the unselected pages to the new sector when
the old sector is full (see AN1152 for more details).
Sector Erase
Suspended in
sector x
0
0
0
0
1
0
This error is due to a real failure of a Flash cell,
that can no longer be programmed. When this er-
ror is detected, the embedded algorithm automati-
cally exits the Page Update operation at the end of
the Swap phase, without performing the Erase
Phase 0 on the full sector. In this way the old data
are kept, and through predefined routines in Test-
Flash (Find Wrong Pages = 230029h and Find
Wrong Bytes = 23002Ch), the user can compare
the old and the new data to find where the error oc-
curred.
Don’t care
FLASH & E3 TM STATUS REGISTER 1 (FESR1)
Address: 224003h /221003h-Read Only
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
ERER PGER SWER
Once the error has been discovered the user must
take to end the stopped Erase Phase 0 on the old
sector (through another predefined routine in Test-
Flash: Complete Swap = 23002Fh). The byte
where the error occurred must be reprogrammed
to FFh and then discarded, to avoid the error oc-
curring again when that byte is internally moved.
Bit 7 = ERER. Erase error (Read Only).
This bit is set by hardware when an Erase error oc-
3 TM
curs during a Flash or an E
write operation.
This error is due to a real failure of a Flash cell,
that can no longer be erased. This kind of error is
fatal and the sector where it occurred must be dis-
carded. This bit is automatically cleared when bit
FEERR of the FESR0 register is cleared by soft-
ware.
This bit is automatically cleared when bit FEERR
of the FESR0 register is cleared by software.
Bit 4:0 = Reserved.
0: Erase OK
1: Erase error
Bit 6 = PGER. Program error (Read Only).
This bit is automatically set when a Program error
occurs during a Flash or an E3 TM write operation.
This error is due to a real failure of a Flash cell,
that can no longer be programmed. The byte
where this error occurred must be discarded (if it
was in the E3 TM memory, the byte must be repro-
grammed to FFh and then discarded, to avoid the
error occurring again when that byte is internally
moved). This bit is automatically cleared when bit
FEERR of the FESR0 register is cleared by soft-
ware.
0: Program OK
1: Flash or E3 TM Programming error
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
3.4 WRITE OPERATION EXAMPLE
Each operation (both Flash and E3 TM) is activated
by a sequence of instructions like the following:
The load instructions are used to set the address-
es (in the Flash or in the E3 TM memory space) and
the data to be modified.
The last instruction is used to start the write oper-
ation, by setting the start bit (FWMS for Flash op-
erations, EWMS for E3 TM operation) in the Control
register.
OR
LD
LD
..
LD
FCR, #OPMASK ;Operation selection
ADD1, #DATA1 ;1st Add and Data
ADD2, #DATA2 ;2nd Add and Data
...., ......
Once selected, but not yet started, one operation
can be cancelled by resetting the operation selec-
tion bit. Any latched address and data will be reset.
ADDn, #DATAn ;nth Add and Data
;n range = (1 to 16)
OR
FCR, #80h
;Operation start
3
Warning: during the Flash Page Program or the E
TM Page Update operation it is forbidden to change
the page address: only the last page address is ef-
fectively kept and all programming will effect only
that page.
The first instruction is used to select the desired
operation by setting its corresponding selection bit
in the Control Register (FCR for Flash operations,
ECR for E3 TM operations).
3 TM
A summary of the available Flash and E
operations are shown in the following tables:
write
Table 11. Flash Write Operations
Operation
Byte Program
Page Program
Sector Erase
Selection bit
FBYTE
Addresses and Data
1 byte
Start bit
FWMS
FWMS
FWMS
None
Typical Duration
10 µs
160 µs (16 bytes)
1.5 s (1 sector)
15 µs
FPAGE
FSECT
FSUSP
FCHIP
From 1 to 16 bytes
From 1 to 4 sectors
None
Sector Erase Suspend
Chip Erase
None
FWMS
FWMS
3 s
Set Protection
PROT
From 1 to 4 bytes
40 µs (4 bytes)
Table 12. E3 TM Write Operations
Operation
Page Update
Chip Erase
Selection bit
Addresses and Data
From 1 to 16 bytes
None
Start bit
EWMS
EWMS
Typical Duration
EPAGE
ECHIP
30 ms
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
3.5 PROTECTION STRATEGY
The protection bits are stored in the 4 locations
from 231FFCh to 231FFFh (see Figure 34).
NON VOLATILE ACCESS PROTECTION REG-
ISTER (NVAPR)
All the available protections are forced active dur-
ing reset, then in the initialisation phase they are
read from the TestFlash.
Address: 231FFCh - Read/Write
Delivery value: 1111 1111 (FFh)
7
1
6
5
4
3
2
1
0
The protections are stored in 2 Non Volatile Regis-
ters. Other 2 Non Volatile Registers can be used
as a password to re-enable test modes once they
have been disabled.
APRO APBR APEE APEX PWT2 PWT1 PWT0
Bit 7 = Reserved.
The protections can be programmed using the Set
Protection operation (see Control Registers para-
graph), that can be executed from all the internal
or external memories except the Flash or Test-
Flash itself.
Bit 6 = APRO: FLASH access protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the Flash
address space (E3 TM excluded), unless the current
instruction is fetched from the TestFlash or from
the Flash itself.
The TestFlash area (230000h to 231F7Fh) is al-
ways protected against write access.
0: ROM protection on
1: ROM protection off
Figure 34. Protection Register Map
Bit 5 = APBR: TestFlash access protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the Test-
Flash, the OTP and the protection registers, un-
less the current instruction is fetched from the
TestFlash or the OTP area.
231FFCh
231FFDh
231FFEh
231FFFh
NVAPR
NVWPR
NVPWD0
NVPWD1
0: TestFlash protection on
1: TestFlash protection off
3.5.1 Non Volatile Registers
The 4 Non Volatile Registers used to store the pro-
tection bits for the different protection features are
one time programmable by the user.
Bit 4 = APEE: E3 TM access protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the E
3 TM
Access to these registers is controlled by the pro-
tections related to the TestFlash. Since the code to
program the Protection Registers cannot be
fetched by the Flash or the TestFlash memories,
this means that, once the APRO or APBR bits in
the NVAPR register are programmed, it is no long-
er possible to modify any of the protection bits. For
this reason the NV Password, if needed, must be
set with the same Set Protection operation used to
program these bits. For the same reason it is
strongly advised to never program the WPBR bit in
the NVWPR register, as this will prevent any fur-
ther write access to the TestFlash, and conse-
quently to the Protection Registers.
address space, unless the current instruction is
fetched from the TestFlash or from the Flash, or
from the E3 TM itself.
0: E3 TM protection on
1: E3 TM protection off
Bit 3 = APEX: Access Protection from External
memory.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the ad-
dress space of one of the internal memories (Test-
Flash, Flash, E3 TM, RAM), if the current instruction
is fetched from an external memory.
0: Protection from external memory on
1: Protection from external memory off
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
PROTECTION STRATEGY (Cont’d)
Bit 2:0 = PWT[2:0]: Password Attempt 2-0.
Bit 5 = WPBR: TestFlash Write Protection.
This bit, if programmed at 0, disables any write ac-
cess to the TestFlash, the OTP and the protection
registers. This protection cannot be temporarily
disabled.
If the TMDIS bit in the NVWPR register (231FFDh)
is programmed to 0, every time a Set Protection
operation is executed with Program Addresses
equal to NVPWD1-0 (231FFE-Fh), the two provid-
ed Program Data are compared with the
NVPWD1-0 content; if there is not a match one of
PWT2-0 bits is automatically programmed to 0:
when these three bits are all programmed to 0 the
test modes are disabled forever. In order to inten-
tionally disable test modes forever, it is sufficient to
set a random Password and then to make 3 wrong
attempts to enter it.
0: TestFlash write protection on
1: TestFlash write protection off
Note: it is strongly advised to never program the
WPBR bit in the NVWPR register, as this will pre-
vent any further write access to the protection reg-
isters.
Bit 4 = WPEE: E3 TM Write Protection.
This bit, if programmed to 0, disables any write ac-
3 TM
NON VOLATILE WRITE PROTECTION REGIS-
TER (NVWPR)
cess to the E
address space. This protection
can be temporary disabled by executing the Set
Protection operation and writing 1 into this bit. To
restore the protection, reset the micro or execute
another Set Protection operation on this bit.
0: E3 TM write protection on
Address: 231FFDh - Read/Write
Delivery value: 1111 1111 (FFh)
1: E3 TM write protection off
7
6
5
4
3
2
1
0
Note: a read access to the NVWPR register re-
stores any protection previously enabled.
TMDIS PWOK WPBR WPEE WPRS3 WPRS2 WPRS1 WPRS0
Bit 3 = WPRS3: FLASH Sectors 5-3 Write Protec-
Bit 7 = TMDIS: Test mode disable (Read Only).
This bit, if set to 1, allows to bypass all the protec-
tions in test and EPB modes. If programmed to 0,
on the contrary, all the protections remain active
also in test mode. The only way to enable the test
modes if this bit is programmed to 0, is to execute
the Set Protection operation with Program Ad-
dresses equal to NVPWD1-0 (231FFF-Eh) and
Program Data matching with the content of
NVPWD1-0. This bit is read only: it is automatically
programmed to 0 when NVPWD1-0 are written for
the first time.
tion.
This bit, if programmed to 0, disables any write ac-
cess to the Flash sector 3 (and sectors 4 and 5
when available) address space(s). This protection
can be temporary disabled by executing the Set
Protection operation and writing 1 into this bit. To
restore the protection, reset the micro or execute
another Set Protection operation on this bit.
0: FLASH Sectors 5-3 write protection on
1: FLASH Sectors 5-3 write protection off
Note: a read access to the NVWPR register re-
stores any protection previously enabled.
0: Test mode disabled
1: Test mode enabled
Bit 2:0 = WPRS[2:0]: FLASH Sectors 2-0 Write
Bit 6 = PWOK: Password OK (Read Only).
If the TMDIS bit is programmed to 0, when the Set
Protection operation is executed with Program Ad-
dresses equal to NVPWD[1:0] and Program Data
matching with NVPWD[1:0] content, the PWOK bit
is automatically programmed to 0. When this bit is
programmed to 0 TMDIS protection is bypassed
and the test and EPB modes are enabled.
0: Password OK
Protection.
These bits, if programmed to 0, disable any write
access to the 3 Flash sectors address spaces.
These protections can be temporary disabled by
executing the Set Protection operation and writing
1 into these bits. To restore the protection, reset
the micro or execute another Set Protection oper-
ation on this bit.
1: Password not OK
0: FLASH Sectors 2-0 write protection on
1: FLASH Sectors 2-0 write protection off
Note: a read access to the NVWPR register re-
stores any protection previously enabled.
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
PROTECTION STRATEGY (Cont’d)
Bit APEX can be temporarily disabled by execut-
ing the Set Protection operation and writing 1 into
NON VOLATILE PASSWORD (NVPWD1-0)
this bit, but only if this write instruction is executed
Address: 231FFF-231FFEh - Write Only
Delivery value: 1111 1111 (FFh)
from an internal memory (Flash and Test Flash ex-
cluded).
Bit APEE can be temporarily disabled by execut-
ing the Set Protection operation and writing 1 into
this bit, but only if this write instruction is executed
from the memory itself to unprotect (E3 TM).
7
6
5
4
3
2
1
0
PWD7 PWD6 PWD5 PWD4 PWD3 PWD2 PWD1 PWD0
Bits APRO and APBR can be temporarily disabled
through a direct write at NVAPR location, by over-
writing at 1 these bits, but only if this write instruc-
tion is executed from the memory itself to unpro-
tect.
Bit 7:0 = PWD[7:0]: Password bits 7:0 (Write On-
ly).
These bits must be programmed with the Non Vol-
atile Password that must be provided with the Set
Protection operation to disable (first write access)
or to reenable (second write access) the test and
EPB modes. The first write access fixes the pass-
word value and resets the TMDIS bit of NVWPR
(231FFDh). The second write access, with Pro-
gram Data matching with NVPWD[1:0] content, re-
sets the PWOK bit of NVWPR.
To restore the access protections, reset the micro
or execute another Set Protection operation by
writing 0 to the desired bits.
Note: To restore all the protections previously en-
abled in the NVAPR or NVWPR register, read the
corresponding register.
When an internal memory (Flash, TestFlash or
These two registers can be accessed only in write
mode (a read access returns FFh).
E
3 TM) is protected in access, also the data access
through a DMA of a peripheral is forbidden (it re-
turns FFh). To read data in DMA mode from a pro-
tected memory, first it is necessary to temporarily
unprotect that memory.
3.5.2 Temporary Unprotection
On user request the memory can be configured so
as to allow the temporary unprotection also of all
access protections bits of NVAPR (write protection
bits of NVWPR are always temporarily unprotecta-
ble).
The temporary unprotection allows also to update
a protected code.
Refer to the following figures to manage the Test/
EPB, Access and Write protection modes.
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
Figure 35. Test /EPB Mode Protection
Test/EPB Mode
Unprotected
Good
Password
2nd
Bad Password
Good
Test/EPB Mode
Protected
PassWord
1st
Bad Password
3rd Bad Password
Test/EPB Mode
Protected
Test/EPB Mode
Unprotected
Good
Good
Password
Password
Bad Password
Bad Password
Figure 36. Access Mode Protection
Access Mode
Unprotected
Reset the Access Protection bit
by a Set Protection Operationexecuted from RAM
Access Mode
Protected
Reset the
SW/HW
Reset
Access Protection bit
by a Set Protection
Operation
Set the
NVAPR
Read
Access
Access Protection Bit
by an OR operation executed
from the Memory
Executed from RAM
Access Mode
to unprotect
Temporarily
Unprotected
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
Figure 37. WRITE Mode Protection
Write Mode
Unprotected
Reset the Write Protection Bit
by a Set Protection Operation
executed from RAM
Write Mode
Protected
Reset the Write
Protection Bit by a
Set the
SW/HW
Reset
Set Protection
Operation exectued
from RAM
Write Protection Bit
by a Set Protection Operation
executed from RAM
NVWPR
Read
Access
Write Mode
Temporarily
Unprotected
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
3.6 FLASH IN-SYSTEM PROGRAMMING
The first 4 words should be the interrupt vectors
of the 4 possible SCI interrupts, to be used by
the in-system programming routine;
The Flash memory can be programmed in-system
through a serial interface (SCI0).
■ Transmits a last datum (21h) as a request for
Exiting from reset, the ST9 executes the initializa-
tion from the TestFlash code (written in Test-
Flash), where it checks the value of the SOUT0
pin. If it is at 0, this means that the user wishes to
update the Flash code, otherwise normal execu-
tion continues. In this second case, the TestFlash
code reads the Reset vector.
end of communications;
■ Receives
the
end
of
communication
confirmation datum (any byte other than 25h);
■ Resets all the unused RAM locations to FFh;
■ Calls address 200018h in internal RAM;
■ After completion of the in-system programming
routine, an HALT instruction is executed and an
Hardware Reset is needed.
If the Flash is virgin (read content is always FFh),
the reset vector contains FFFFh. This will repre-
sent the last location of segment 0h, and it is inter-
preted by the TestFlash code as a flag indicating
that the Flash memory is virgin and needs to be
programmed. If the value 1 is detected on the
SOUT0 pin and the Flash is virgin, a HALT instruc-
tion is executed, waiting for a hardware Reset.
The Code Update routine initializes the SCI0 pe-
ripheral as shown in the following table:
Table 13. SCI0 Registers (page 24) initialization
Register
IVR - R244
Value
10h
Notes
Vector Table in 0010h
Address Match is 23h
SCI interrupt priority is 0
8 Data Bits
3.6.1 Code Update Routine
ACR - R245
IDPR - R249
CHCR - R250
23h
The TestFlash Code Update routine is called auto-
matically if the SOUT0 pin is held low during pow-
er-on.
00h
83h
rec. clock: ext RXCLK0
trx clock: int CLKOUT0
The Code Update routine performs the following
operations:
CCR - R251
E8h
BRGHR - R252
BRGLR - R253
SICR - R254
00h
04h
83h
01h
■ Enables the SCI0 peripheral in synchronous
Baud Rate Divider is 4
Synchronous Mode
mode
■ Transmits a synchronization datum (25h);
■ Waits for an address match (23h) with a timeout
SOCR - R255
of 10ms (@ f
■ If the match is not received before the timeout,
4 MHz);
OSC
In addition, the Code Update routine remaps the
interrupts in the TestFlash (ISR = 23h), and config-
ures I/O Ports P5.3 (SOUT0) and and P5.4
(CLKOUT0) as Alternate Functions.
the execution returns to the Power-On routine;
■ If the match is received, the SCI0 transmits a
new datum (21h) to tell the external device that
it is ready to receive the data to be loaded in
RAM (that represents the code of the in-system
programming routine);
Note: Four interrupt routines are used by the code
update routine: SCI Receiver Error Interrupt rou-
tine (vector in 0010h), SCI address Match Interrupt
routine (vector in 0012h), SCI Receiver Data
Ready Interrupt routine (vector in 0014h) and SCI
Transmitter Buffer Empty Interrupt routine (vector
in 0016h).
■ Receives two data representing the number of
bytes to be loaded (max. 4 Kbytes);
■ Receives the specified number of bytes (each
one preceded by the transmission of a Ready to
Receive character: (21h) and writes them in
internal RAM starting from address 200010h.
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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
Figure 38. Flash in-system Programming.
Internal RAM (User Code Example)
TestFlash Code
Start
In-system
prog routine
Initialisation
Address
Match
Interrupt
(from SCI)
No
Flash
virgin ?
Yes
No
Yes
SOUT0
= 0 ?
Erase sectors
Jump to Flash
Enable Serial
Interface
Main
User
Code
Load 1st table
of data in RAM
through S.I.
Test
Flash
WFI
Code Update
Routine
Prog 1st table
of data from
RAM in Flash
Load 2nd table
of data in RAM
through SCI
Enable DMA
Load in-system
prog routine
in internal RAM
through SCI.
Inc. Address
No
Last
Call in-system
prog routine
Address ?
Yes
RET
HALT
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ST92F124/F150/F250 - REGISTER AND MEMORY MAP
4 REGISTER AND MEMORY MAP
4.1 INTRODUCTION
The ST92F124/F150/F250 register map, memory
map and peripheral options are documented in
this section. Use this reference information to sup-
plement the functional descriptions given else-
where in this document.
ment where the routine is located has to be written
in 000009h (one byte).
This routine is called at least once every time that
3 TM
the TestFlash executes an E
write operation. If
the write operation has a long duration, the user
routine is called with a rate fixed by location
000008h with an internal clock frequency of 2
MHz, location 000008h fixes the number of milli-
seconds to wait between two calls of the user rou-
tine.
4.2 MEMORY CONFIGURATION
The Program memory space of the ST92F124/
F150/F250 up to 256K bytes of directly addressa-
ble on-chip memory, is fully available to the user.
Table 14. User Routine Parameters
4.2.1 Reset Vector Location
The user power on reset vector must be stored in
the first two physical bytes of memory, 000000h
and 000001h.
Location
000006h to
000007h
Size
Description
2 bytes
User routine address
4.2.2 Location of Vector for External Watchdog
Refresh
000008h
000009h
1 byte
1 byte
ms rate at 2 MHz.
User routine segment
If an external watchdog is used, it must be re-
freshed during TestFlash execution by a user writ-
ten routine. This routine has to be located in Flash
memory, the address where the routine starts has
to be written in 000006h (one word) while the seg-
If location 000006h to 000007h is virgin (FFFFh),
the user routine is not called.
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ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Figure 39. ST92F150/F250 External Memory Map
3FFFFFh
External
Memory
Upper Memory(1.8 Mbytes)
(usually external RAM starting
in Segment 24h)
250000h
24FFFFh
PAGE 93h - 16 Kbytes
PAGE 92h - 16 Kbytes
PAGE 91h - 16 Kbytes
PAGE 90h - 16 Kbytes
24C000h
24BFFFh
SEGMENT 24h
64 Kbytes
248000h
247FFFh
244000h
243FFFh
240000h
Segments 20h to 23h
(Reserved for
internal
memory)
(256Kbytes)
1FFFFFh
External
Memory
Lower Memory
(usually external ROM/FLASH
starting in Segment 4h)
(1.8 Mbytes)
050000h
04FFFFh
PAGE 13h - 16 Kbytes
PAGE 12h - 16 Kbytes
PAGE 11h - 16 Kbytes
PAGE 10h - 16 Kbytes
04C000h
04BFFFh
SEGMENT 4h
64 Kbytes
048000h
047FFFh
044000h
043FFFh
040000h
Segments 0h to 3h
(Reserved for
internal
memory)
(256Kbytes)
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ST92F124/F150/F250 - REGISTER AND MEMORY MAP
3 TM
Figure 40. ST92F124/F150/F250 TESTFLASH and E
Memory Map
23FFFFh
PAGE 8Fh - 16 Kbytes
23C000h
23BFFFh
PAGE 8Eh - 16 Kbytes
PAGE 8Dh - 16 Kbytes
PAGE 8Ch - 16 Kbytes
SEGMENT 23h
64 Kbytes
238000h
237FFFh
234000h
233FFFh
230000h
231FFFh
8 Kbytes
230000h
TESTFLASH - 8 Kbytes
FLASH OTP - 128 bytes
231FFFh
231F80h
128 bytes
4 bytes
231FFFh
231FFCh
FLASH OTP Protection Registers - 4 bytes
22FFFFh
PAGE 8Bh - 16 Kbytes
PAGE 8Ah - 16 Kbytes
PAGE 89h- 16 Kbytes
PAGE 88h - 16 Kbytes
22C000h
22BFFFh
SEGMENT 22h
64 Kbytes
228000h
227FFFh
224003h/221000h
224000h/221003h
3 TM
224000h
223FFFh
220000h
2203FFh
FLASH and E
Control Registers - 4 bytes
mapped in both locations
1 Kbyte
220000h
Emulated EEPROM - 1 Kbyte
Not Available
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ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Figure 41. ST92F124/F150 Internal Memory Map (64K versions)
20FFFFh
PAGE 83h - 16 Kbytes
PAGE 82h - 16 Kbytes
PAGE 81h - 16 Kbytes
PAGE 80h - 16 Kbytes
20C000h
20BFFFh
SEGMENT 20h
64 Kbytes
208000h
207FFFh
204000h
203FFFh
200000h
2017FFh
200FFFh
2007FFh
6 Kbytes
4 Kbytes
2 Kbytes
200000h
RAM
03FFFFh
PAGE Fh - 16 Kbytes
PAGE Eh - 16 Kbytes
PAGE Dh- 16 Kbytes
PAGE Ch - 16 Kbytes
PAGE Bh - 16 Kbytes
PAGE Ah - 16 Kbytes
PAGE 9h - 16 Kbytes
PAGE 8h- 16 Kbytes
PAGE 7h - 16 Kbytes
PAGE 6h - 16 Kbytes
PAGE 5h - 16 Kbytes
PAGE 4h - 16 Kbytes
PAGE 3h - 16 Kbytes
PAGE 2h - 16 Kbytes
PAGE 1h - 16 Kbytes
PAGE 0h - 16 Kbytes
03C000h
03BFFFh
SEGMENT 3h
64 Kbytes
038000h
037FFFh
034000h
033FFFh
030000h
02FFFFh
02C000h
02BFFFh
SEGMENT 2h
64 Kbytes
028000h
027FFFh
Reserved Area -192 Kbytes
024000h
023FFFh
020000h
01FFFFh
01C000h
01BFFFh
SEGMENT 1h
64 Kbytes
018000h
017FFFh
014000h
013FFFh
010000h
00FFFFh
SECTOR F2
48 Kbytes
00C000h
00BFFFh
SEGMENT 0h
64 Kbytes
008000h
007FFFh
SECTOR F1
8 Kbytes
004000h
003FFFh
000000h
SECTOR F0
8 Kbytes
FLASH - 64 Kbytes
Not Available
70/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Figure 42. ST92F124/F150 Internal Memory Map (128K versions)
20FFFFh
PAGE 83h - 16 Kbytes
PAGE 82h - 16 Kbytes
PAGE 81h - 16 Kbytes
PAGE 80h - 16 Kbytes
20C000h
20BFFFh
SEGMENT 20h
64 Kbytes
208000h
207FFFh
204000h
203FFFh
200000h
2017FFh
200FFFh
2007FFh
6 Kbytes
4 Kbytes
2 Kbytes
200000h
RAM
03FFFFh
PAGE Fh - 16 Kbytes
PAGE Eh - 16 Kbytes
PAGE Dh- 16 Kbytes
PAGE Ch - 16 Kbytes
PAGE Bh - 16 Kbytes
PAGE Ah - 16 Kbytes
PAGE 9h - 16 Kbytes
PAGE 8h- 16 Kbytes
PAGE 7h - 16 Kbytes
PAGE 6h - 16 Kbytes
PAGE 5h - 16 Kbytes
PAGE 4h - 16 Kbytes
PAGE 3h - 16 Kbytes
PAGE 2h - 16 Kbytes
PAGE 1h - 16 Kbytes
PAGE 0h - 16 Kbytes
03C000h
03BFFFh
SEGMENT 3h
64 Kbytes
038000h
037FFFh
034000h
033FFFh
030000h
02FFFFh
Reserved Area- 128 Kbytes
02C000h
02BFFFh
SEGMENT 2h
64 Kbytes
028000h
027FFFh
024000h
023FFFh
020000h
01FFFFh
01C000h
01BFFFh
SECTOR F3 *
64 Kbytes
SEGMENT 1h
64 Kbytes
018000h
017FFFh
014000h
013FFFh
010000h
00FFFFh
SECTOR F2
48 Kbytes
00C000h
00BFFFh
SEGMENT 0h
64 Kbytes
008000h
007FFFh
SECTOR F1
8 Kbytes
004000h
003FFFh
000000h
SECTOR F0
8 Kbytes
FLASH - 128 Kbytes
* Available on ST92F150 versions only. Reserved area on ST92F124 version.
Not Available
71/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Figure 43. ST92F250 Internal Memory Map (256K version)
20FFFFh
PAGE 83h - 16 Kbytes
PAGE 82h - 16 Kbytes
PAGE 81h - 16 Kbytes
PAGE 80h - 16 Kbytes
20C000h
20BFFFh
SEGMENT 20h
64 Kbytes
208000h
207FFFh
204000h
203FFFh
200000h
201FFFh
8Kbytes
RAM
200000h
03FFFFh
PAGE Fh - 16 Kbytes
PAGE Eh - 16 Kbytes
PAGE Dh- 16 Kbytes
PAGE Ch - 16 Kbytes
PAGE Bh - 16 Kbytes
PAGE Ah - 16 Kbytes
PAGE 9h - 16 Kbytes
PAGE 8h- 16 Kbytes
PAGE 7h - 16 Kbytes
PAGE 6h - 16 Kbytes
PAGE 5h - 16 Kbytes
PAGE 4h - 16 Kbytes
PAGE 3h - 16 Kbytes
PAGE 2h - 16 Kbytes
PAGE 1h - 16 Kbytes
PAGE 0h - 16 Kbytes
03C000h
03BFFFh
SECTOR F5
SEGMENT 3h
64 Kbytes
038000h
037FFFh
64 Kbytes
034000h
033FFFh
030000h
02FFFFh
02C000h
02BFFFh
SECTOR F4
64 Kbytes
SEGMENT 2h
64 Kbytes
028000h
027FFFh
024000h
023FFFh
020000h
01FFFFh
01C000h
01BFFFh
SECTOR F3
64 Kbytes
SEGMENT 1h
64 Kbytes
018000h
017FFFh
014000h
013FFFh
010000h
00FFFFh
SECTOR F2
48 Kbytes
00C000h
00BFFFh
SEGMENT 0h
64 Kbytes
008000h
007FFFh
SECTOR F1
8 Kbytes
004000h
003FFFh
000000h
SECTOR F0
8 Kbytes
FLASH - 256Kbytes
Not Available
72/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
4.3 ST92F124/F150/F250 REGISTER MAP
– Registers common to other functions.
– In particular, double-check that any registers
with “undefined” reset values have been correct-
ly initialized.
Table 16 contains the map of the group F periph-
eral pages.
The common registers used by each peripheral
are listed in Table 15.
Warning: Note that in the EIVR and each IVR reg-
ister, all bits are significant. Take care when defin-
ing base vector addresses that entries in the Inter-
rupt Vector table do not overlap.
Be very careful to correctly program both:
– The set of registers dedicated to a particular
function or peripheral.
Table 15. Common Registers
Function or Peripheral
Common Registers
SCI, MFT
ADC
CICR + NICR + DMA REGISTERS + I/O PORT REGISTERS
CICR + NICR + I/O PORT REGISTERS
CICR + NICR + EXTERNAL INTERRUPT REGISTERS +
I/O PORT REGISTERS
SPI, WDT, STIM
I/O PORTS
EXTERNAL INTERRUPT
RCCU
I/O PORT REGISTERS + MODER
INTERRUPT REGISTERS + I/O PORT REGISTERS
INTERRUPT REGISTERS + MODER
73/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Table 16. Group F Pages Register Map
Resources available on the ST92F124/F150/F250 devices:
Reg.
Page
0
2
3
7
8
9
10
11
20
21
22
23
24
26
28
29
36
37
38
39
40
R255
Res
R254 Res.
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
Res.
Res
Res.
Res.
Res. Res.
Res. Res.
R241
Res.
R240
74/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
:
Reg.
Page
41
42
43
48
49
50
51
52
53
54
55
57
60
61
62
63
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
Res.
Res.
Res.
Res
* Available on some devices only
75/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Table 17. Detailed Register Map
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R224
R225
R226
R227
R228
R229
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R240
R241
R242
R244
R245
R246
R248
R249
R250
R252
R253
R254
CICR
FLAGR
RP0
Central Interrupt Control Register
Flag Register
87
33
34
36
36
38
38
40
40
40
40
00
Pointer 0 Register
xx
RP1
Pointer 1 Register
xx
PPR
Page Pointer Register
xx
Core
MODER
USPHR
USPLR
SSPHR
SSPLR
P0DR
P1DR
P2DR
P3DR
P4DR
P5DR
EITR
Mode Register
E0
User Stack Pointer High Register
User Stack Pointer Low Register
System Stack Pointer High Reg.
System Stack Pointer Low Reg.
Port 0 Data Register
xx
xx
N/A
xx
xx
FF
Port 1 Data Register
FF
I/O
Port
0:5
Port 2 Data Register
FF
150
Port 3 Data Register
1111 111x
Port 4 Data Register
FF
Port 5 Data Register
FF
External Interrupt Trigger Register
External Interrupt Pending Reg.
External Interrupt Mask-bit Reg.
External Interrupt Priority Level Reg.
External Interrupt Vector Register
Nested Interrupt Control
00
105
106
106
106
162
107
161
161
161
161
162
EIPR
00
EIMR
00
INT
EIPLR
EIVR
FF
x6
0
NICR
00
WDTHR
WDTLR
WDTPR
WDTCR
WCR
Watchdog Timer High Register
Watchdog Timer Low Register
Watchdog Timer Prescaler Reg.
Watchdog Timer Control Register
Wait Control Register
FF
FF
WDT
FF
12
7F
P0C0
Port 0 Configuration Register 0
Port 0 Configuration Register 1
Port 0 Configuration Register 2
Port 1 Configuration Register 0
Port 1 Configuration Register 1
Port 1 Configuration Register 2
Port 2 Configuration Register 0
Port 2 Configuration Register 1
Port 2 Configuration Register 2
Port 3 Configuration Register 0
Port 3 Configuration Register 1
Port 3 Configuration Register 2
00
I/O
Port
0
P0C1
00
P0C2
00
P1C0
00
00
I/O
Port
1
P1C1
P1C2
00
2
150
P2C0
FF
I/O
Port
2
P2C1
00
P2C2
00
P3C0
1111 111x
0000 000x
0000 000x
I/O
Port
3
P3C1
P3C2
76/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R244
R245
R246
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
P4C0
P4C1
P4C2
P5C0
P5C1
P5C2
P6C0
P6C1
P6C2
P6DR
P7C0
P7C1
P7C2
P7DR
SPDR0
SPCR0
SPSR0
SPPR0
Port 4 Configuration Register 0
Port 4 Configuration Register 1
Port 4 Configuration Register 2
Port 5 Configuration Register 0
Port 5 Configuration Register 1
Port 5 Configuration Register 2
Port 6 Configuration Register 0
Port 6 Configuration Register 1
Port 6 Configuration Register 2
Port 6 Data Register
FD
I/O
Port
4
00
00
FF
I/O
Port
5
00
00
xx11 1111
3
150
I/O
Port
6
xx00 0000
xx00 0000
xx11 1111
Port 7 Configuration Register 0
Port 7 Configuration Register 1
Port 7 Configuration Register 2
Port 7 Data Register
FF
00
00
FF
00
00
00
00
I/O
Port
7
SPI Data Register
259
259
260
260
SPI Control Register
7
SPI
SPI Status Register
SPI Prescaler Register
77/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240 REG0HR1
R241 REG0LR1
R242 REG1HR1
R243 REG1LR1
Capture Load Register 0 High
Capture Load Register 0 Low
Capture Load Register 1 High
Capture Load Register 1 Low
Compare 0 Register High
Compare 0 Register Low
Compare 1 Register High
Compare 1 Register Low
Timer Control Register
xx
xx
xx
xx
00
00
00
00
00
00
00
00
00
00
00
00
xx
xx
xx
C7
FC
xx
xx
xx
C7
xx
xx
xx
xx
00
00
00
00
00
00
00
00
00
00
00
00
201
201
201
201
201
201
201
201
202
203
204
204
205
206
206
208
201
201
201
201
210
208
209
209
210
201
201
201
201
201
201
201
201
202
203
204
204
205
206
206
208
R244 CMP0HR1
R245 CMP0LR1
R246 CMP1HR1
R247 CMP1LR1
8
R248
R249
R250
R251
R252
R253
TCR1
TMR1
Timer Mode Register
MFT1
MFT0,1
MFT0
T_ICR1
PRSR1
OACR1
OBCR1
External Input Control Register
Prescaler Register
Output A Control Register
Output B Control Register
Flags Register
R254 T_FLAGR1
R255
R244
R245
R246
R247
R248
R240
R241
R242
R243
IDMR1
DCPR1
DAPR1
T_IVR1
IDCR1
IOCR
Interrupt/DMA Mask Register
DMA Counter Pointer Register
DMA Address Pointer Register
Interrupt Vector Register
Interrupt/DMA Control Register
I/O Connection Register
DMA Counter Pointer Register
DMA Address Pointer Register
Interrupt Vector Register
Interrupt/DMA Control Register
Capture Load Register 0 High
Capture Load Register 0 Low
Capture Load Register 1 High
Capture Load Register 1 Low
Compare 0 Register High
Compare 0 Register Low
Compare 1 Register High
Compare 1 Register Low
Timer Control Register
9
DCPR0
DAPR0
T_IVR0
IDCR0
R240 REG0HR0
R241 REG0LR0
R242 REG1HR0
R243 REG1LR0
R244 CMP0HR0
R245 CMP0LR0
R246 CMP1HR0
R247 CMP1LR0
10
R248
R249
R250
R251
R252
R253
TCR0
TMR0
Timer Mode Register
T_ICR0
PRSR0
OACR0
OBCR0
External Input Control Register
Prescaler Register
Output A Control Register
Output B Control Register
Flags Register
R254 T_FLAGR0
R255 IDMR0
Interrupt/DMA Mask Register
78/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R243
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R248
R249
R245
R246
STH
STL
Counter High Byte Register
Counter Low Byte Register
FF
FF
FF
14
00
00
00
00
00
00
00
A0
xx
xx
xx
xx
xx
xx
00
x0
xx
xx
xx
xx
00
xx
xx
80
1F
165
165
165
165
272
273
275
276
276
277
277
277
278
279
279
279
280
280
280
281
45
11
STIM
STP
Standard Timer Prescaler Register
Standard Timer Control Register
STC
2
I2DCCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I2CADR
I2CISR
I2CIVR
I2CRDAP
I2CRDC
I2CTDAP
I2CTDC
I2CECCR
I2CIMR
DPR0
I C Control Register
2
I C Status Register 1
2
I C Status Register 2
2
I C Clock Control Register
2
I C Own Address Register 1
2
I C Own Address Register 2
2
I C Data Register
2
I C General Call Address
20
I2C_0
2
I C Interrupt Status Register
2
I C Interrupt Vector Register
Receiver DMA Source Addr. Pointer
Receiver DMA Transaction Counter
Transmitter DMA Source Addr. Pointer
Transmitter DMA Transaction Counter
Extended Clock Control Register
2
I C Interrupt Mask Register
Data Page Register 0
Data Page Register 1
DPR1
45
DPR2
Data Page Register 2
45
MMU
DPR3
Data Page Register 3
45
21
CSR
Code Segment Register
Interrupt Segment Register
DMA Segment Register
External Memory Register 1
External Memory Register 2
46
ISR
46
DMASR
EMR1
46
147
148
EXTMI
EMR2
79/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
2
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
I2DCCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I C Control Register
00
00
00
00
00
00
00
A0
xx
xx
xx
xx
xx
xx
00
x0
40
xx
xx
00
00
40
xx
00
xx
10
00
00
xx
xx
xx
xx
272
273
275
276
276
277
277
277
278
279
279
279
280
280
280
281
304
305
306
306
311
311
312
313
315
315
315
317
319
319
319
319
2
I C Status Register 1
2
I C Status Register 2
2
I C Clock Control Register
2
I C Own Address Register 1
2
I C Own Address Register 2
2
I C Data Register
2
I2CADR
I2CISR
I C General Call Address
22
I2C_1*
2
I C Interrupt Status Register
2
I2CIVR
I C Interrupt Vector Register
I2CRDAP
I2CRDC
I2CTDAP
I2CTDC
I2CECCR
I2CIMR
Receiver DMA Source Addr. Pointer
Receiver DMA Transaction Counter
Transmitter DMA Source Addr. Pointer
Transmitter DMA Transaction Counter
Extended Clock Control Register
2
I C Interrupt Mask Register
STATUS
TXDATA
RXDATA
TXOP
Status Register
Transmit Data Register
Receive Data Register
Transmit Opcode Register
System Frequency Selection Register
Control Register
CLKSEL
R245 CONTROL
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
PADDR
ERROR
IVR
Physical Address Register
Error Register
23
JBLPD*
Interrupt Vector Register
Priority Level Register
Interrupt Mask Register
Options and Register Group Selection
Current Register 0
PRLR
IMR
OPTIONS
CREG0
CREG1
CREG2
CREG3
Current Register 1
Current Register 2
Current Register 4
80/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R243
R244
R245
R246
R247
R248
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
RDCPR0
RDAPR0
Receiver DMA Transaction Counter Pointer
Receiver DMA Source Address Pointer
xx
xx
xx
xx
xx
xx
x0
xx
xx
xx
xx
xx
00
xx
xx
03
01
C0
xx
xx
xx
00
00
00
00
xx
xx
xx
xx
FF
FC
FF
FC
80
00
80
00
00
00
00
00
226
226
226
226
228
228
228
228
230
230
231
232
233
234
234
234
235
244
247
247
245
246
248
248
246
180
180
180
180
181
181
181
181
182
182
182
182
184
184
184
184
TDCPR0 Transmitter DMA Transaction Counter Pointer
TDAPR0
S_IVR0
ACR0
Transmitter DMA Destination Address Pointer
Interrupt Vector Register
Address/Data Compare Register
Interrupt Mask Register
IMR0
S_ISR0
RXBR0
TXBR0
IDPR0
Interrupt Status Register
24
SCI-M
Receive Buffer Register
Transmitter Buffer Register
Interrupt/DMA Priority Register
Character Configuration Register
Clock Configuration Register
Baud Rate Generator High Reg.
Baud Rate Generator Low Register
Synchronous Input Control
Synchronous Output Control
SCI Status Register
CHCR0
CCR0
BRGHR0
BRGLR0
SICR0
SOCR0
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
SCICR3
IC1HR0
IC1LR0
IC2HR0
IC2LR0
CHR0
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
26
SCI-A*
SCI Control Register 2
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
SCI Control Register 3
Input Capture 1 High Register
Input Capture 1 Low Register
Input Capture 2 High Register
Input Capture 2 Low Register
Counter High Register
CLR0
Counter Low Register
ACHR0
ACLR0
OC1HR0
OC1LR0
OC2HR0
OC2LR0
CR1_0
CR2_0
SR0
Alternate Counter High Register
Alternate Counter Low Register
Output Compare 1 High Register
Output Compare 1 Low Register
Output Compare 2 High Register
Output Compare 2 Low Register
Control Register 1
28
EFT0*
Control Register 2
Status Register
CR3_0
Control Register 3
81/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R255
IC1HR1
IC1LR1
IC2HR1
IC2LR1
CHR1
Input Capture 1 High Register
Input Capture 1 Low Register
Input Capture 2 High Register
Input Capture 2 Low Register
Counter High Register
xx
xx
180
180
180
180
181
181
181
181
182
182
182
182
184
184
184
184
342
343
343
344
345
345
345
346
346
347
347
347
348
348
348
xx
xx
FF
FC
FF
FC
80
00
80
00
00
00
00
00
02
02
00
00
00
00
00
00
00
00
00
00
00
23
00
CLR1
Counter Low Register
ACHR1
ACLR1
OC1HR1
OC1LR1
OC2HR1
OC2LR1
CR1_1
CR2_1
SR1
Alternate Counter High Register
Alternate Counter Low Register
Output Compare 1 High Register
Output Compare 1 Low Register
Output Compare 2 High Register
Output Compare 2 Low Register
Control Register 1
29
EFT1*
Control Register 2
Status Register
CR3_1
CMCR
CMSR
CTSR
Control Register 3
CAN Master Control Register
CAN Master Status Register
CAN Transmit Control Register
CAN Transmit Priority Register
CAN Receive FIFO Register 0
CAN Receive FIFO Register 1
CAN Interrupt Enable Register
CAN Error Status Register
CAN Error Interrupt Enable Register
Transmit Error Counter Register
Receive Error Counter Register
CAN Diagnosis Register
CTPR
CRFR0
CRFR1
CIER
CAN1*
36
CESR
Control/
Status
CEIER
TECR
RECR
CDGR
CBTR0
CBTR1
CFPSR
CAN Bit Timing Register 0
CAN Bit Timing Register 1
Filter page Select Register
82/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
MFMI
MDLC
Mailbox Filter Match Index
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
350
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
350
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
MFMI
CAN1*
Mailbox Data Register 1
37
Receive
FIFO 0
Mailbox Data Register 2
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
Mailbox Filter Match Index
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
MDLC
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
CAN1*
Mailbox Data Register 1
38
Receive
FIFO 1
Mailbox Data Register 2
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
83/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
MCSR
MDLC
Mailbox Control Status Register
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
349
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
349
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
MCSR
CAN1 *
Tx
Mailbox Data Register 1
39
Mailbox Data Register 2
Mailbox 0
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
Mailbox Control Status Register
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
MDLC
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
CAN1 *
Tx
Mailbox Data Register 1
40
Mailbox Data Register 2
Mailbox 1
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
84/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
MCSR
MDLC
Mailbox Control Status Register
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
00
x0
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
349
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
CAN1 *
Tx
Mailbox Data Register 1
41
Mailbox Data Register 2
Mailbox 2
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
Filter Configuration
See “Page Mapping
for CAN 0 / CAN 1”
on page 356
CAN1 *
Filters
42
43
Acceptance Filters 7:0
(5 register pages)
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R255
P8C0
P8C1
Port 8 Configuration Register 0
Port 8 Configuration Register 1
Port 8 Configuration Register 2
Port 8 Data Register
03
00
00
FF
00
00
00
FF
02
02
00
00
00
00
00
00
00
00
00
00
00
23
00
I/O
Port
8 *
P8C2
P8DR
P9C0
150
Port 9 Configuration Register 0
Port 9 Configuration Register 1
Port 9 Configuration Register 2
Port 9 Data Register
I/O
Port
9 *
P9C1
P9C2
P9DR
CMCR
CMSR
CTSR
CTPR
CRFR0
CRFR1
CIER
CAN Master Control Register
CAN Master Status Register
CAN Transmit Control Register
CAN Transmit Priority Register
CAN Receive FIFO Register 0
CAN Receive FIFO Register 1
CAN Interrupt Enable Register
CAN Error Status Register
CAN Error Interrupt Enable Register
Transmit Error Counter Register
Receive Error Counter Register
CAN Diagnosis Register
342
343
343
344
345
345
345
346
346
347
347
347
348
348
348
CAN0*
48
CESR
CEIER
TECR
RECR
CDGR
CBTR0
CBTR1
CFPSR
Control/
Status
CAN Bit Timing Register 0
CAN Bit Timing Register 1
Filter page Select Register
85/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
MFMI
MDLC
Mailbox Filter Match Index
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
350
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
350
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
MFMI
CAN0*
Mailbox Data Register 1
49
Receive
FIFO 0
Mailbox Data Register 2
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
Mailbox Filter Match Index
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
MDLC
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
CAN0*
Mailbox Data Register 1
50
Receive
FIFO 1
Mailbox Data Register 2
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
86/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
MCSR
MDLC
Mailbox Control Status Register
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
349
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
349
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
MCSR
CAN0*
Tx
Mailbox Data Register 1
51
Mailbox Data Register 2
Mailbox 0
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
Mailbox Control Status Register
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
MDLC
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
CAN0*
Tx
Mailbox Data Register 1
52
Mailbox Data Register 2
Mailbox 1
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
87/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
MCSR
MDLC
Mailbox Control Status Register
Mailbox Data Length Control Register
Mailbox Identifier Register 0
Mailbox Identifier Register 1
Mailbox Identifier Register 2
Mailbox Identifier Register 3
Mailbox Data Register 0
00
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
349
351
350
350
350
350
351
351
351
351
351
351
351
351
351
351
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSLR
MTSHR
CAN0*
Tx
Mailbox Data Register 1
53
Mailbox Data Register 2
Mailbox 2
Mailbox Data Register 3
Mailbox Data Register 4
Mailbox Data Register 5
Mailbox Data Register 6
Mailbox Data Register 7
Mailbox Time Stamp Low Register
Mailbox Time Stamp High Register
Filter Configuration
“Page Mapping for
CAN 0 / CAN 1” on
page 356
CAN0*
Filters
54
55
Acceptance Filters 7:0
(5 register pages)
R240
R241
CLKCTL
VRCTR
Clock Control Register
00
0x
133
133
Voltage Regulator Control Register
RCCU
64,48, 28
or 08
R242 CLK_FLAG
Clock Flag Register
134
R246 PLLCONF
PLL Configuration Register
Wake-Up Control Register
xx
00
00
00
00
00
00
00
00
00
00
00
00
00
xE
FF
FF
00
00
134
117
118
118
119
119
119
119
108
108
108
108
108
108
109
109
109
110
110
R249
R250
R251
R252
R253
R254
R255
R245
R246
R247
R248
R249
R250
R251
R252
R253
WUCTRL
WUMRH
WUMRL
WUTRH
WUTRL
WUPRH
WUPRL
SIMRH
SIMRL
Wake-Up Mask Register High
Wake-Up Mask Register Low
57
WUIMU
Wake-Up Trigger Register High
Wake-Up Trigger Register Low
Wake-Up Pending Register High
Wake-Up Pending Register Low
Interrupt Mask Register High (Ch. I to L)
Interrupt Mask Register Low (Ch. E to H)
Interrupt Trigger Register High (Ch. I to L)
Interrupt Trigger Register Low (Ch. E to H)
Interrupt Pending Register High (Ch. I to L)
Interrupt Pending Register Low (Ch. E to H)
Interrupt Vector Register (Ch. E to L)
Interrupt Priority Register High (Ch. I to L)
Interrupt Priority Register Low (Ch. E to H)
Interrupt Flag Register High (Ch. I to L)
Interrupt Flag Register Low (Ch. E to H)
SITRH
SITRL
SIPRH
STD
INT
60
SIPRL
SIVR
SIPLRH
SIPLRL
R254 SFLAGRH
R255 SIFLAGRL
88/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Doc.
Page
(Dec)
Reg.
No.
Register
Name
Block
Description
Value
Hex.
Page
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
D0HR
D0LR
Channel 0 Data High Register
Channel 0 Data Low Register
Channel 1 Data High Register
Channel 1 Data Low Register
Channel 2 Data High Register
Channel 2 Data Low Register
Channel 3 Data High Register
Channel 3 Data Low Register
Channel 4 Data High Register
Channel 4 Data Low Register
Channel 5 Data High Register
Channel 5 Data Low Register
Channel 6 Data High Register
Channel 6 Data Low Register
Channel 7 Data High Register
Channel 7 Data Low Register
Channel 8 Data High Register
Channel 8 Data Low Register
Channel 9 Data High Register
Channel 9 Data Low Register
Channel 10 Data High Register
Channel 10 Data Low Register
Channel 11 Data High Register
Channel 11 Data Low Register
Channel 12 Data High Register
Channel 12 Data Low Register
Channel 13 Data High Register
Channel 13 Data Low Register
Channel 14 Data High Register
Channel 14 Data Low Register
Channel 15 Data High Register
Channel 15 Data Low Register
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
xx
x0
365
365
365
365
365
365
365
365
366
366
366
366
366
366
366
366
367
367
367
367
367
367
367
367
368
368
368
368
368
368
368
368
D1HR
D1LR
D2HR
D2LR
D3HR
D3LR
61
D4HR
D4LR
D5HR
D5LR
D6HR
D6LR
D7HR
D7LR
ADC
D8HR
D8LR
D9HR
D9LR
D10HR
D10LR
D11HR
D11LR
D12HR
D12LR
D13HR
D13LR
D14HR
D14LR
D15HR
D15LR
62
89/426
9
ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Reset
Value
Hex.
Page
(Dec)
Reg.
No.
Register
Name
Doc.
Page
Block
Description
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
CRR
LTAHR
LTALR
LTBHR
LTBLR
UTAHR
UTALR
UTBHR
UTBLR
CLR1
Compare Result Register
Channel A Lower Threshold High Register
Channel A Lower Threshold Low Register
Channel B Lower Threshold High Register
Channel B Lower Threshold Low Register
Channel A Upper Threshold High Register
Channel A Upper Threshold Low Register
Channel B Upper Threshold High Register
Channel B Upper Threshold Low Register
Control Logic Register 1
0x
xx
x0
xx
x0
xx
x0
xx
x0
0F
A0
0F
x2
369
369
369
369
370
370
370
370
370
371
371
372
373
63
ADC
CLR2
Control Logic Register 2
AD_ICR
AD_IVR
Interrupt Control Register
Interrupt Vector Register
Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register
description for details.
* Available on some devices only
90/426
9
ST92F124/F150/F250 - INTERRUPTS
5.1.1.4 Top Level Interrupt (TLI)
5 INTERRUPTS
5.1 INTRODUCTION
In addition, a dedicated interrupt channel, set to
the Top-level priority, can be devoted either to the
external NMI pin (where available) to provide a
Non-Maskable Interrupt, or to the Timer/Watch-
dog. Interrupt service routines are addressed
through a vector table mapped in Memory.
The ST9 responds to peripheral and external
events through its interrupt channels. Current pro-
gram execution can be suspended to allow the
ST9 to execute a specific response routine when
such an event occurs, providing that interrupts
have been enabled, and according to a priority
mechanism. If an event generates a valid interrupt
request, the current program status is saved and
control passes to the appropriate Interrupt Service
Routine.
Figure 44. Interrupt Response
n
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
The ST9 CPU can receive requests from the fol-
lowing sources:
– On-chip peripherals
– External pins
– Top-Level Pseudo-non-maskable interrupt
5.1.1 On-Chip Peripheral Interrupt Sources
5.1.1.1 Dedicated Channels
CLEAR
PENDING BIT
INTERRUPT
The following on-chip peripherals have dedicated
interrupt channels with interrupt control registers
located in their peripheral register page.
IRET
INSTRUCTION
– A/D Converter
2
– I C
VR001833
– JPBLD
– MFT
5.2 INTERRUPT VECTORING
– SCI-M
5.1.1.2 Standard Channels
The ST9 implements an interrupt vectoring struc-
ture which allows the on-chip peripheral to identify
the location of the first instruction of the Interrupt
Service Routine automatically.
Other on-chip peripherals have their interrupts
mapped to the INTxx interrupt channel group.
These channels have control registers located in
Pages 0 and 60. These peripherals are:
When an interrupt request is acknowledged, the
peripheral interrupt module provides, through its
Interrupt Vector Register (IVR), a vector to point
into the vector table of locations containing the
start addresses of the Interrupt Service Routines
(defined by the programmer).
– CAN
3 TM
– E
/FLASH
– EFT Timer
– RCCU
Each peripheral has a specific IVR mapped within
its Register File pages (or in register page 0 or 60
if it is mapped to one of the INTxx channels).
– SCI-A
– SPI
– STIM timer
– WDT Timer
– WUIMU
The Interrupt Vector table, containing the address-
es of the Interrupt Service Routines, is located in
the first 256 locations of Memory pointed to by the
ISR register, thus allowing 8-bit vector addressing.
For a description of the ISR register refer to the
chapter describing the MMU.
5.1.1.3 External Interrupts
Up to eight external interrupts, with programmable
input trigger edge, are available and are mapped
to the INTxx interrupt channel group in page 0.
The user Power on Reset vector is stored in the
first two physical bytes in memory, 000000h and
000001h.
91/426
9
ST92F124/F150/F250 - INTERRUPTS
The Top Level Interrupt vector is located at ad-
dresses 0004h and 0005h in the segment pointed
to by the Interrupt Segment Register (ISR).
If ENCSR is reset, the CPU works in original ST9
compatibility mode. For the duration of the inter-
rupt service routine, ISR is used instead of CSR,
and the interrupt stack frame is identical to that of
the original ST9: only the PC and Flags are
pushed.
If an external watchdog is used, refer to the Regis-
ter and Memory Map section for details on using
vector locations 0006h to 0009h. Otherwise loc-
tions 0006h to 0007h must contain FFFFh.
This avoids saving the CSR on the stack in the
event of an interrupt, thus ensuring a faster inter-
rupt response time.
With one Interrupt Vector register, it is possible to
address several interrupt service routines; in fact,
peripherals can share the same interrupt vector
register among several interrupt channels. The
most significant bits of the vector are user pro-
grammable to define the base vector address with-
in the vector table, the least significant bits are
controlled by the interrupt module, in hardware, to
select the appropriate vector.
It is not possible for an interrupt service routine to
perform inter-segment calls or jumps: these in-
structions would update the CSR, which, in this
case, is not used (ISR is used instead). The code
segment size for all interrupt service routines is
thus limited to 64K bytes.
ST9+ mode (ENCSR = 1)
Note: The first 256 locations of the memory seg-
ment pointed to by ISR can contain program code.
If ENCSR is set, ISR is only used to point to the in-
terrupt vector table and to initialize the CSR at the
beginning of the interrupt service routine: the old
CSR is pushed onto the stack together with the PC
and flags, and CSR is then loaded with the con-
tents of ISR.
5.2.1 Divide by Zero trap
The Divide by Zero trap vector is located at ad-
dresses 0002h and 0003h of each code segment;
it should be noted that for each code segment a
Divide by Zero service routine is required.
In this case, iretwill also restore CSR from the
stack. This approach allows interrupt service rou-
tines to access the entire 4 Mbytes of address
space. The drawback is that the interrupt response
time is slightly increased, because of the need to
also save CSR on the stack.
Warning. Although the Divide by Zero Trap oper-
ates as an interrupt, the FLAG Register is not
pushed onto the system Stack automatically. As a
result it must be regarded as a subroutine, and the
service routine must end with the RET instruction
(not IRET ).
Full compatibility with the original ST9 is lost in this
case, because the interrupt stack frame is differ-
ent.
5.2.2 Segment Paging During Interrupt
Routines
ENCSR Bit
Mode
0
1
ST9 Compatible
ST9+
The ENCSR bit in the EMR2 register can be used
to select between original ST9 backward compati-
bility mode and ST9+ interrupt management
mode.
Pushed/Popped
Registers
Max. Code Size
for interrupt
PC, FLAGR,
CSR
PC, FLAGR
64KB
No limit
ST9 backward compatibility mode (ENCSR = 0)
Within 1 segment Across segments
service routine
92/426
9
ST92F124/F150/F250 - INTERRUPTS
5.3 INTERRUPT PRIORITY LEVELS
guarantees a maximum number of 8 nested levels
including the Top Level Interrupt request.
The ST9 supports a fully programmable interrupt
priority structure. Nine priority levels are available
to define the channel priority relationships:
5.4.3 Simultaneous Interrupts
If two or more requests occur at the same time and
at the same priority level, an on-chip daisy chain,
specific to every ST9 version, selects the channel
with the highest position in the chain, as shown in
Table 18
– The on-chip peripheral channels and the eight
external interrupt sources can be programmed
within eight priority levels. Each channel has a 3-
bit field, PRL (Priority Level), that defines its pri-
ority level in the range from 0 (highest priority) to
7 (lowest priority).
Table 18. Daisy Chain Priority
Highest Position INTA0 / Watchdog Timer
INTA1 / Standard Timer
– The 9th level (Top Level Priority) is reserved for
the Timer/Watchdog or the External Pseudo
Non-Maskable Interrupt. An Interrupt service
routine at this level cannot be interrupted in any
arbitration mode. Its mask can be both maskable
(TLI) or non-maskable (TLNM).
INTB0 / Extended Function Timer 0 *
INTB1 / Extended Function Timer 1 *
3 TM
INTC0 / E
/Flash
INTC1 / SPI
INTD0 / RCCU
5.4 PRIORITY LEVEL ARBITRATION
INTD1 / WKUP MGT
Multifunction Timer 0
INTE0/CAN0_RX0
INTE1/CAN0_RX1
INTF0/CAN0_TX
INTF1/CAN0_SCE
INTG0/CAN1_RX0 *
INTG1/CAN1_RX1 *
INTH0/CAN1_TX *
INTH1/CAN1_SCE *
INTI0/SCI-A *
The 3 bits of CPL (Current Priority Level) in the
Central Interrupt Control Register contain the pri-
ority of the currently running program (CPU priori-
ty). CPL is set to 7 (lowest priority) upon reset and
can be modified during program execution either
by software or automatically by hardware accord-
ing to the selected Arbitration Mode.
During every instruction, an arbitration phase
takes place, during which, for every channel capa-
ble of generating an Interrupt, each priority level is
compared to all the other requests (interrupts or
DMA).
JBLPD *
2
If the highest priority request is an interrupt, its
PRL value must be strictly lower (that is, higher pri-
ority) than the CPL value stored in the CICR regis-
ter (R230) in order to be acknowledged. The Top
Level Interrupt overrides every other priority.
I C bus Interface 0
2
I C bus Interface 1 *
A/D Converter
Lowest Position Multifunction Timer 1
SCI-M
5.4.1 Priority Level 7 (Lowest)
* available on some devices only
Interrupt requests at PRL level 7 cannot be ac-
knowledged, as this PRL value (the lowest possi-
ble priority) cannot be strictly lower than the CPL
value. This can be of use in a fully polled interrupt
environment.
5.4.4 Dynamic Priority Level Modification
The main program and routines can be specifically
prioritized. Since the CPL is represented by 3 bits
in a read/write register, it is possible to dynamically
modify the current priority value during program
execution. This means that a critical section can
have a higher priority with respect to other inter-
rupt requests. Furthermore it is possible to priori-
tize even the Main Program execution by modify-
ing the CPL during its execution. See Figure 45.
5.4.2 Maximum Depth of Nesting
No more than 8 routines can be nested. If an inter-
rupt routine at level N is being serviced, no other
Interrupts located at level N can interrupt it. This
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ST92F124/F150/F250 - INTERRUPTS
Figure 45. Example of Dynamic Priority
Level Modification in Nested Mode
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
INTERRUPT 6 HAS PRIORITY LEVEL 6
Priority Level
– If ENCSR is set, CSR is pushed onto system
stack.
CPL is set to 7
by MAIN program
4
– The Flag register is pushed onto system stack.
ei
INT6
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
5
6
7
MAIN
CPL is set to 5
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwise ISR is used in place of CSR until
iretinstruction.
CPL6 > CPL5:
INT6 pending
INT 6
CPL=6
End of Interrupt Routine
The Interrupt Service Routine must be ended with
the iret instruction. The iret instruction exe-
cutes the following operations:
MAIN
CPL=7
– The Flag register is popped from system stack.
5.5 ARBITRATION MODES
– If ENCSR is set, CSR is popped from system
stack.
The ST9 provides two interrupt arbitration modes:
Concurrent mode and Nested mode. Concurrent
mode is the standard interrupt arbitration mode.
Nested mode improves the effective interrupt re-
sponse time when service routine nesting is re-
quired, depending on the request priority levels.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
The IAM control bit in the CICR Register selects
Concurrent Arbitration mode or Nested Arbitration
Mode.
– If ENCSR is reset, CSR is used instead of ISR.
Normal program execution thus resumes at the in-
terrupted instruction. All pending interrupts remain
pending until the next ei instruction (even if it is
executed during the interrupt service routine).
5.5.1 Concurrent Mode
This mode is selected when the IAM bit is cleared
(reset condition). The arbitration phase, performed
during every instruction, selects the request with
the highest priority level. The CPL value is not
modified in this mode.
Note: In Concurrent mode, the source priority level
is only useful during the arbitration phase, where it
is compared with all other priority levels and with
the CPL. No trace is kept of its value during the
ISR. If other requests are issued during the inter-
rupt service routine, once the global CICR.IEN is
re-enabled, they will be acknowledged regardless
of the interrupt service routine’s priority. This may
cause undesirable interrupt response sequences.
Start of Interrupt Routine
The interrupt cycle performs the following steps:
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
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ST92F124/F150/F250 - INTERRUPTS
ARBITRATION MODES (Cont’d)
Examples
Example 1
In the following two examples, three interrupt re-
quests with different priority levels (2, 3 & 4) occur
simultaneously during the interrupt 5 service rou-
tine.
In the first example, (simplest case, Figure 46) the
eiinstruction is not used within the interrupt serv-
ice routines. This means that no new interrupt can
be serviced in the middle of the current one. The
interrupt routines will thus be serviced one after
another, in the order of their priority, until the main
program eventually resumes.
Figure 46. Simple Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected and
- IEN unchanged by the interrupt routines
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
0
1
2
3
4
5
6
7
Priority Level of
Interrupt Request
INT 2
CPL = 7
INT 3
CPL = 7
INT 2
INT 3
INT 4
INT 4
CPL = 7
INT 5
CPL = 7
ei
INT 5
MAIN
MAIN
CPL = 7
CPL is set to 7
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ST92F124/F150/F250 - INTERRUPTS
ARBITRATION MODES (Cont’d)
Example 2
In the second example, (more complex, Figure
47), each interrupt service routine sets Interrupt
Enable with the eiinstruction at the beginning of
the routine. Placed here, it minimizes response
time for requests with a higher priority than the one
being serviced.
ice routines being executed in the opposite order
of their priority.
It is therefore recommended to avoid inserting
the ei instruction in the interrupt service rou-
tine in Concurrent mode. Use the ei instruc-
tion only in Nested mode.
The level 2 interrupt routine (with the highest prior-
ity) will be acknowledged first, then, when the ei
instruction is executed, it will be interrupted by the
level 3 interrupt routine, which itself will be inter-
rupted by the level 4 interrupt routine. When the
level 4 interrupt routine is completed, the level 3 in-
terrupt routine resumes and finally the level 2 inter-
rupt routine. This results in the three interrupt serv-
WARNING: If, in Concurrent Mode, interrupts are
nested (by executing ei in an interrupt service
routine), make sure that either ENCSR is set or
CSR=ISR, otherwise the iretof the innermost in-
terrupt will make the CPU use CSR instead of ISR
before the outermost interrupt service routine is
terminated, thus making the outermost routine fail.
Figure 47. Complex Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected
- IEN set to 1 during interrupt service routine execution
0
Priority Level of
INTERRUPT 2 HAS PRIORITY LEVEL 2
Interrupt Request
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
1
2
3
4
5
6
7
INT 2
INT 2
CPL = 7
CPL = 7
INT 3
CPL = 7
INT 3
CPL = 7
ei
INT 2
INT 3
INT 4
ei
ei
INT 4
CPL = 7
INT 5
INT 5
CPL = 7
CPL = 7
ei
ei
INT 5
MAIN
MAIN
CPL is set to 7
CPL = 7
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ST92F124/F150/F250 - INTERRUPTS
ARBITRATION MODES (Cont’d)
5.5.2 Nested Mode
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
The difference between Nested mode and Con-
current mode, lies in the modification of the Cur-
rent Priority Level (CPL) during interrupt process-
ing.
– CPL is saved in the special NICR stack to hold
the priority level of the suspended routine.
– Priority level of the acknowledged routine is
stored in CPL, so that the next request priority
will be compared with the one of the routine cur-
rently being serviced.
The arbitration phase is basically identical to Con-
current mode, however, once the request is ac-
knowledged, the CPL is saved in the Nested Inter-
rupt Control Register (NICR) by setting the NICR
bit corresponding to the CPL value (i.e. if the CPL
is 3, the bit 3 will be set).
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
stack.
The CPL is then loaded with the priority of the re-
quest just acknowledged; the next arbitration cycle
is thus performed with reference to the priority of
the interrupt service routine currently being exe-
cuted.
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
Start of Interrupt Routine
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwise ISR is used in place of CSR until
iretinstruction.
The interrupt cycle performs the following steps:
Figure 48. Simple Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN unchanged by the interrupt routines
Priority Level of
Interrupt Request
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
INT 0
CPL=0
0
1
2
3
4
CPL6 > CPL3:
INT6 pending
INT0
INT 2
CPL=2
INT 2
CPL=2
INT6
INT 3
INT2
CPL=3
INT2
INT3
INT4
INT 4
CPL=4
CPL2 < CPL4:
Serviced next
5
INT 5
CPL=5
ei
6
INT 6
CPL=6
INT5
7
MAIN
CPL is set to 7
MAIN
CPL=7
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ST92F124/F150/F250 - INTERRUPTS
ARBITRATION MODES (Cont’d)
End of Interrupt Routine
– If ENCSR is reset, CSR is used instead of ISR,
unless the program returns to another nested
routine.
The iret Interrupt Return instruction executes
the following steps:
The suspended routine thus resumes at the inter-
rupted instruction.
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
Figure 48 contains a simple example, showing that
if the ei instruction is not used in the interrupt
service routines, nested and concurrent modes
are equivalent.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
Figure 49 contains a more complex example
showing how nested mode allows nested interrupt
processing (enabled inside the interrupt service
routinesi using the ei instruction) according to
their priority level.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
– The priority level of the interrupted routine is
popped from the special register (NICR) and
copied into CPL.
Figure 49. Complex Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN set to 1 during the interrupt routine execution
Priority Level of
Interrupt Request
0
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
INT 0
CPL=0
CPL6 > CPL3:
INT6 pending
1
2
3
INT0
INT 2
INT 2
INT 2
CPL=2
INT6
CPL=2
CPL=2
INT 3
ei
INT2
CPL=3
ei
INT2
INT3
INT4
4
5
6
7
INT 4
CPL=4
INT 4
CPL=4
CPL2 < CPL4:
Serviced just after ei
ei
INT 5
CPL=5
INT 5
CPL=5
ei
INT 6
CPL=6
ei
INT5
MAIN
CPL is set to 7
MAIN
CPL=7
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ST92F124/F150/F250 - INTERRUPTS
5.6 EXTERNAL INTERRUPTS
The ST9 core contains 8 external interrupt sources
grouped into four pairs.
Figure 51 and Table 20 give an overview of the ex-
ternal interrupts and vectors.
Table 19. External Interrupt Channel Grouping
External
Table 20. Multiplexed Interrupt Sources
External
Channel
Internal Interrupt Source
Channel
I/O Port Pin
Interrupt
Interrupt
INTA0
INTA1
INTB0
INTB1
INTC0
INTC1
INTD0
INTD1
Timer/Watchdog
Standard Timer
INT0
P8[1:0] P7[7:5]
P6[7,5] P5[7:5, 2:0] P4[7,4]
WKUP[0:15]
INTD1
INT1
INT6
INT5
INT4
INT3
INT2
INT1
INT0
INTD0
INTC1
INTC0
INTB1
INTB0
INTA1
INTA0
P6.1
P6.3
P6.2
P6.3
P6.2
P6.0
P6.0
Extended Function Timer 0
INT2
Extended Function Timer 1
INT3
3 TM
E
/Flash
INT4
SPI Interrupt
RCCU
INT5
INT6
Wake-up Management Unit
Each source has a trigger control bit TEA0,..TED1
(R242,EITR.0,..,7 Page 0) to select triggering on
the rising or falling edge of the external pin. If the
Trigger control bit is set to “1”, the corresponding
pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page
0) is set on the input pin rising edge, if it is cleared,
the pending bit is set on the falling edge of the in-
put pin. Each source can be individually masked
– The source of INTA0 can be selected between
the external pin INT0 or the Timer/Watchdog pe-
ripheral using the IA0S bit in the EIVR register
(R246 Page 0).
– The source of INTA1 can be selected between
the external pin INT1 or the Standard Timer us-
ing the INTS bit in the STC register (R232 Page
11).
through
the
corresponding
control
bit
IMA0,..,IMD1 (EIMR.7,..,0). See Figure 51.
– The source of INTB0 can be selected between
the external pin INT2 or the on-chip Extended
Function Timer 0 using the EFTIS bit in the CR3
register (R255 Page 28).
Figure 50. Priority Level Examples
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
– The source of INTB1 can be selected between
external pin INT3 or the on-chip Extended Func-
tion Timer 1 using the EFTIS bit in the CR3 reg-
ister (R255 Page 29).
1
0
0
0
1
0
0
1
EIPLR
SOURCE PRIORITY
SOURCE PRIORITY
INT.D0: 100=4
INT.D1: 101=5
INT.A0: 010=2
INT.A1: 011=3
– The source of INTC0 can be selected between
external pin INT4 or the On-chip E3 TM/Flash
Memory using bit FEIEN in the ECR register (Ad-
dress 224001h).
INT.C0: 000=0
INT.C1: 001=1
INT.B0: 100=4
INT.B1: 101=5
– The source of INTC1 can be selected between
external pin INT5 or the on-chip SPI using the
SPIS bit in the SPCR0 register (R241 Page 7).
The priority level of the external interrupt sources
can be programmed among the eight priority lev-
els with the control register EIPLR (R245). The pri-
ority level of each pair is software defined using
the bits PRL2,PRL1. For each pair, the even chan-
nel (A0,B0,C0,D0) of the group has the even prior-
ity level and the odd channel (A1,B1,C1,D1) has
the odd (lower) priority level.
– The source of INTD0 can be selected between
external pin INT6 or the Reset and Clock Unit
RCCU using the INT_SEL bit in the CLKCTL reg-
ister (R240 Page 55).
– The source of INTD1 can be selected between
the NMI pin and the WUIMU Wakeup/Interrupt
Lines using the ID1S bit in the WUCRTL register
(R248 Page 9).
Figure 50 shows an example of priority levels.
Warning: When using external interrupt channels
shared by both external interrupts and peripherals,
special care must be taken to configure control
registers both for peripheral and interrupts.
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ST92F124/F150/F250 - INTERRUPTS
EXTERNAL INTERRUPTS (Cont’d)
Figure 51. External Interrupt Control Bits and Vectors
Watchdog/Timer
End of count
IA0S
TEA0
V6
V7
V5 V4 0
0
X
0
VECTOR
Priority level
“0”
INT A0
request
0
X
X
Mask bit
Pending bit IPA0
IMA0
“1”
INT 0 pin*
INT 1 pin*
INTS
TEA1
STIM Timer
V6
V6
V7
V5 V4 0
0
X
1
VECTOR
“0”
Priority level
INT A1
request
1
X
X
Mask bit
Pending bit IPA1
IMA1
“1”
EFTIS
TEB0
TEB1
TEC0
EFT0 Timer
V7
V5 V4 0
1
X
0
VECTOR
Priority level
“1”
INT B0
request
0
X
X
INT 2 pin*
INT 3 pin*
Mask bit
Pending bit IPB0
IMB0
“0”
EFTIS
EFT1 Timer
V6
V6
V7
V5 V4 0
1
X
1
VECTOR
Priority level
“1”
INT B1
request
1
X
X
“0”
Mask bit
IMB1
Pending bit IPB1
FEIEN
3 TM
E
/Flash
“1”
“0”
V7
V5 V4 1
0
X
0
VECTOR
Priority level
INT C0
request
0
X
X
INT 4 pin*
INT 5 pin*
Pending bit IPC0
Mask bit
IMC0
SPIS
TEC1
SPI
V6
V6
V6
V7
V5 V4 1
0
X
1
VECTOR
“1”
“0”
INT C1
request
Priority level
1
X
X
Pending bit IPC1
Mask bit
IMC1
INT_SEL
RCCU
TED0
V7
V5 V4 1
1
X
0
VECTOR
Priority level
“1”
“0”
INT D0
request
0
X
X
INT 6 pin
NMI
Mask bit
IMD0
Pending bit IPD0
ID1S
V7
V5 V4 1
1
X
1
VECTOR
Priority level
“1”
“0”
INT D1
request
1
X
X
Wake-up
Controller
Mask bit
IMD1
Pending bit IPD1
WKUP
(0:15)
* Only four interrupt pins are available. Refer to Table 19 for I/O pin mapping.
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ST92F124/F150/F250 - INTERRUPTS
5.7 STANDARD INTERRUPTS (CAN AND SCI-A)
The two on-chip CAN peripherals generate 4 inter-
rupt sources each. The SCI-A interrupts are
mapped on a single interrupt channel. The map-
ping is shown in the following table.
The priority level of the interrupt channels can be
programmed to one of eight priority levels using
the SIPLRL and SIPLRH control registers.
The two MSBs of the priority level are user pro-
grammable. For each interrupt group, the even
channels (E0, F0, G0, H0, I0) have an even priority
level (LSB of priority level is zero) and the odd
channels (E1, F1, G1, H1) have an odd priority lev-
el (the LSB of priority level is one). See Figure 52.
Table 21. Interrupt Channel Assignment
Interrupt Pairs
INTE0
Interrupt Source
CAN0_RX0
CAN0_RX1
CAN0_TX
INTE1
.
INTF0
Figure 52. Priority Level Examples
INTF1
CAN0_SCE
CAN1_RX0
CAN1_RX1
CAN1_TX
INTG0
INTG1
INTH0
INTH1
INTI0
PL2H PL1H PL2GPL1G PL2F PL1F PL2E PL1E
1
0
0
0
1
0
0
1
IPLRL
SOURCE PRIORITY
SOURCE PRIORITY
CAN1_SCE
SCI-A
INT.G0: 100=4
INT.G1:101=5
INT.E0: 010=2
INT.E1: 011=3
INTI1
Reserved
INT.H0: 000=0
INT.H1: 001=1
INT.F0: 100=4
INT.F1: 101=5
5.7.1 Functional Description
The SIPRL and SIPRH registers contain the inter-
rupt pending bits of the interrupt sources. The
pending bits are set by hardware on occurrence of
a rising edge event. The pending bits are reset by
hardware when the interrupt is acknowledged.
All interrupt channels share a single interrupt vec-
tor register (SIVR). Bits 1 to 4 of the SIVR register
change according to the interrupt channel which
has the highest priority pending interrupt request.
If more than one interrupt channel has pending in-
terrupt requests with the same priority, then an in-
ternal daisy chain decides the interrupt channel
that will be served. INTE0 is first in the internal dai-
sy chain and INTI0 is last.
The SIMRL and SIMRH registers are used to
mask the interrupt requests coming from the inter-
rupt sources. Resetting the bits of these registers
prevents the interrupt requests being sent to the
ST9 core.
The SITRL and SITRH registers are used to select
the edge sensitivity of the interrupt channel (rising
or falling edge). As the SCI-A and CAN interrupt
events are rising edge events, all bits in the SITRL
register and ITEI0 bit in SITRH register must be
set to 1.
An overrun flag is associated with each interrupt
channel. If a new interrupt request comes before
the earlier interrupt request is acknowledged then
the corresponding overrun flag is set.
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ST92F124/F150/F250 - INTERRUPTS
Figure 53. Standard Interrupt (Channels E to I) Control Bits and Vectors
ITEE0
0
X
V6
V7
V5
X
0
0
0
X
0
VECTOR
Priority level
INT E0
request
Mask bit
Pending bit IPE0
IME0
ITEE1
ITEF0
V6
V6
0
X
V7
V5
X
0
0
1
X
1
VECTOR
Priority level
INT E1
request
Mask bit
Pending bit IPE1
IME1
ITRX0
ITRX1
ITTX
0
X
V7
V5
X
0
1
0
X
0
VECTOR
Priority level
ITSCE
INT F0
request
Mask bit
Pending bit IPF0
IMF0
CAN_0 *
ITEF1
ITEG0
0
0
1
V6
V6
V7
V5
X
X
1
VECTOR
Priority level
INT F1
request
1
X
Mask bit
IMF1
Pending bit IPF1
0
1
0
V7
V5
X
X
0
VECTOR
Priority level
INT G0
request
0
X
Pending bit IPG0
Mask bit
IMG0
ITEG1
ITEH0
0
X
V6
V6
V7
V5
X
1
0
1
X
1
VECTOR
Priority level
INT G1
request
Pending bit IPG1
Mask bit
IMG1
ITRX0
ITRX1
ITTX
0
X
V7
V5
X
1
1
0
X
0
VECTOR
Priority level
ITSCE
INT H0
request
Mask bit
IMH0
Pending bit IPH0
CAN_1 *
ITEH1
ITEI0
V6
V6
0
X
V7
V5
X
1
1
1
X
1
VECTOR
Priority level
INT H1
request
Mask bit
IMH1
Pending bit IPH1
1
X
V7
V5
X
0
0
0
X
0
VECTOR
Priority level
INT I0
request
SCI-A *
Mask bit
IMI0
Pending bit IPI0
* On some devices only
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5.7.2 IMPORTANT NOTE ON STANDARD
INTERRUPTS
Refer to Section 13.1.4 on page 412.
5.8 TOP LEVEL INTERRUPT
The Top Level Interrupt channel can be assigned
either to the external pin NMI or to the Timer/
Watchdog according to the status of the control bit
EIVR.TLIS (R246.2, Page 0). If this bit is high (the
reset condition) the source is the external pin NMI.
If it is low, the source is the Timer/ Watchdog End
Of Count. When the source is the NMI external
pin, the control bit EIVR.TLTEV (R246.3; Page 0)
selects between the rising (if set) or falling (if reset)
edge generating the interrupt request. When the
selected event occurs, the CICR.TLIP bit (R230.6)
is set. Depending on the mask situation, a Top
Level Interrupt request may be generated. Two
kinds of masks are available, a Maskable mask
and a Non-Maskable mask. The first mask is the
CICR.TLI bit (R230.5): it can be set or cleared to
enable or disable respectively the Top Level Inter-
rupt request. If it is enabled, the global Enable In-
terrupt bit, CICR.IEN (R230.4) must also be ena-
bled in order to allow a Top Level Request.
Warning. The interrupt machine cycle of the Top
Level Interrupt does not clear the CICR.IEN bit,
and the corresponding iretdoes not set it. Fur-
thermore the TLI never modifies the CPL bits and
the NICR register.
5.9 DEDICATED ON-CHIP PERIPHERAL
INTERRUPTS
Some of the on-chip peripherals have their own
specific interrupt unit containing one or more inter-
rupt channels, or DMA channels. Please refer to
the specific peripheral chapter for the description
of its interrupt features and control registers.
The on-chip peripheral interrupts are controlled by
the following bits:
– Interrupt Pending bit (IP). Set by hardware
when the Trigger Event occurs. Can be set/
cleared by software to generate/cancel pending
interrupts and give the status for Interrupt polling.
The second mask NICR.TLNM (R247.7) is a set-
only mask. Once set, it enables the Top Level In-
terrupt request independently of the value of
CICR.IEN and it cannot be cleared by the pro-
gram. Only the processor RESET cycle can clear
this bit. This does not prevent the user from ignor-
ing some sources due to a change in TLIS.
– Interrupt Mask bit (IM). If IM = “0”, no interrupt
request is generated. If IM =“1” an interrupt re-
quest is generated whenever IP = “1” and
CICR.IEN = “1”.
– Priority Level (PRL, 3 bits). These bits define
the current priority level, PRL=0: the highest pri-
ority, PRL=7: the lowest priority (the interrupt
cannot be acknowledged)
The Top Level Interrupt Service Routine cannot be
interrupted by any other interrupt or DMA request,
in any arbitration mode, not even by a subsequent
Top Level Interrupt request.
– Interrupt Vector Register (IVR, up to 7 bits).
The IVR points to the vector table which itself
contains the interrupt routine start address.
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ST92F124/F150/F250 - INTERRUPTS
Figure 54. Top Level Interrupt Structure
n
WATCHDOG ENABLE
WDGEN
CORE
RESET
TLIP
WATCHDOG TIMER
END OF COUNT
PENDING
MASK
TOP LEVEL
INTERRUPT
REQUEST
MUX
TLIS
OR
NMI
TLTEV
TLNM
TLI
VA00294
IEN
n
5.10 INTERRUPT RESPONSE TIME
cycles (DIVWS and MUL instructions) or 49 for
other instructions.
The interrupt arbitration protocol functions com-
pletely asynchronously from instruction flow and
requires 5 clock cycles. One more CPUCLK cycle
is required when an interrupt is acknowledged.
Requests are sampled every 5 CPUCLK cycles.
For a non-maskable Top Level interrupt, the re-
sponse time between a user event and the start of
the interrupt service routine can range from a min-
imum of 22 clock cycles to a maximum of 51 clock
cycles (DIV instruction), 49 clock cycles (DIVWS
and MUL instructions) or 45 for other instructions.
If the interrupt request comes from an external pin,
the trigger event must occur a minimum of one
INTCLK cycle before the sampling time.
In order to guarantee edge detection, input signals
must be kept low/high for a minimum of one
INTCLK cycle.
When an arbitration results in an interrupt request
being generated, the interrupt logic checks if the
current instruction (which could be at any stage of
execution) can be safely aborted; if this is the
case, instruction execution is terminated immedi-
ately and the interrupt request is serviced; if not,
the CPU waits until the current instruction is termi-
nated and then services the request. Instruction
execution can normally be aborted provided no
write operation has been performed.
An interrupt machine cycle requires a basic 18 in-
ternal clock cycles (CPUCLK), to which must be
added a further 2 clock cycles if the stack is in the
Register File. 2 more clock cycles must further be
added if the CSR is pushed (ENCSR =1).
The interrupt machine cycle duration forms part of
the two examples of interrupt response time previ-
ously quoted; it includes the time required to push
values on the stack, as well as interrupt vector
handling.
For an interrupt deriving from an external interrupt
channel, the response time between a user event
and the start of the interrupt service routine can
range from a minimum of 26 clock cycles to a max-
imum of 55 clock cycles (DIV instruction), 53 clock
In Wait for Interrupt mode, a further cycle is re-
quired as wake-up delay.
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5.11 INTERRUPT REGISTERS
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
the IEN bit when interrupts are disabled or when
no peripheral can generate interrupts. For exam-
ple, if the state of IEN is not known in advance,
and its value must be restored from a previous
push of CICR on the stack, use the sequence DI;
POP CICRto make sure that no interrupts are be-
ing arbitrated when CICR is modified.
R230 - Read/Write
Register Group: System
Reset value: 1000 0111 (87h)
7
0
GCEN TLIP TLI
IEN IAM CPL2 CPL1 CPL0
Bit 3 = IAM: Interrupt Arbitration Mode.
This bit is set and cleared by software.
0: Concurrent Mode
Bit 7 = GCEN: Global Counter Enable.
This bit enables the 16-bit Multifunction Timer pe-
ripheral.
1: Nested Mode
0: MFT disabled
Bits 2:0 = CPL[2:0]: Current Priority Level.
These bits define the Current Priority Level.
CPL=0 is the highest priority. CPL=7 is the lowest
priority. These bits may be modified directly by the
interrupt hardware when Nested Interrupt Mode is
used.
1: MFT enabled
Bit 6 = TLIP: Top Level Interrupt Pending.
This bit is set by hardware when Top Level Inter-
rupt (TLI) trigger event occurs. It is cleared by
hardware when a TLI is acknowledged. It can also
be set by software to implement a software TLI.
0: No TLI pending
EXTERNAL INTERRUPT TRIGGER REGISTER
(EITR)
R242 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
1: TLI pending
Bit 5 = TLI: Top Level Interrupt.
This bit is set and cleared by software.
0: A Top Level Interrupt is generared when TLIP is
set, only if TLNM=1 in the NICR register (inde-
pendently of the value of the IEN bit).
1: A Top Level Interrupt request is generated when
IEN=1 and the TLIP bit are set.
7
0
TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0
Bit 7 = TED1: INTD1 Trigger Event
Bit 6 = TED0: INTD0 Trigger Event
Bit 5 = TEC1: INTC1 Trigger Event
Bit 4 = TEC0: INTC0 Trigger Event
Bit 3 = TEB1: INTB1 Trigger Event
Bit 2 = TEB0: INTB0 Trigger Event
Bit 1 = TEA1: INTA1 Trigger Event
Bit 0 = TEA0: INTA0 Trigger Event
Bit 4 = IEN: Interrupt Enable.
This bit is cleared by the interrupt machine cycle
(except for a TLI).
It is set by the iretinstruction (except for a return
from TLI).
It is set by the EIinstruction.
It is cleared by the DI instruction.
0: Maskable interrupts disabled
1: Maskable Interrupts enabled
Note: The IEN bit can also be changed by soft-
ware using any instruction that operates on regis-
ter CICR, however in this case, take care to avoid
spurious interrupts, since IEN cannot be cleared in
the middle of an interrupt arbitration. Only modify
These bits are set and cleared by software.
0: Select falling edge as interrupt trigger event
1: Select rising edge as interrupt trigger event
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ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT PENDING REGISTER
(EIPR)
Bit 3 = IMB1: INTB1 Interrupt Mask
Bit 2 = IMB0: INTB0 Interrupt Mask
Bit 1 = IMA1: INTA1 Interrupt Mask
Bit 0 = IMA0: INTA0 Interrupt Mask
R243 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
These bits are set and cleared by software.
0: Interrupt masked
7
0
1: Interrupt not masked (an interrupt is generated if
the IPxx and IEN bits = 1)
IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0
Bit 7 = IPD1: INTD1 Interrupt Pending bit
Bit 6 = IPD0: INTD0 Interrupt Pending bit
Bit 5 = IPC1: INTC1 Interrupt Pending bit
Bit 4 = IPC0: INTC0 Interrupt Pending bit
Bit 3 = IPB1: INTB1 Interrupt Pending bit
Bit 2 = IPB0: INTB0 Interrupt Pending bit
Bit 1 = IPA1: INTA1 Interrupt Pending bit
Bit 0 = IPA0: INTA0 Interrupt Pending bit
EXTERNAL INTERRUPT PRIORITY LEVEL
REGISTER (EIPLR)
R245 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
7
0
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
These bits are set by hardware on occurrence of a
trigger event (as specified in the EITR register)
and are cleared by hardware on interrupt acknowl-
edge. They can also be set by software to imple-
ment a software interrupt.
Bits 7:6 = PL2D, PL1D: INTD0, D1 Priority Level.
Bis 5:4 = PL2C, PL1C: INTC0, C1 Priority Level.
Bits 3:2 = PL2B, PL1B: INTB0, B1 Priority Level.
Bits 1:0 = PL2A, PL1A: INTA0, A1 Priority Level.
These bits are set and cleared by software.
0: No interrupt pending
1: Interrupt pending
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for Channels A0, B0, C0 and D0 and
at 1 for Channels A1, B1, C1 and D1.
EXTERNAL INTERRUPT MASK-BIT REGISTER
(EIMR)
Hardware
R244 - Read/Write
PL2x PL1x
Priority
0 (Highest)
bit
Register Page: 0
Reset value: 0000 0000 (00h)
0
1
0
0
1
1
0
1
0
1
1
7
0
0
1
2
3
IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0
0
1
4
5
Bit 7 = IMD1: INTD1 Interrupt Mask
Bit 6 = IMD0: INTD0 Interrupt Mask
Bit 5 = IMC1: INTC1 Interrupt Mask
Bit 4 = IMC0: INTC0 Interrupt Mask
0
1
6
7 (Lowest)
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ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT VECTOR REGISTER
(EIVR)
0: WAITN pin disabled
1: WAITN pin enabled (to stretch the external
memory access cycle).
R246 - Read/Write
Register Page: 0
Reset value: xxxx 0110 (x6h)
Note: For more details on Wait mode refer to the
section describing the WAITN pin in the External
Memory Chapter.
7
0
V7
V6
V5
V4 TLTEV TLIS IAOS EWEN
NESTED INTERRUPT CONTROL (NICR)
R247 - Read/Write
Register Page: 0
Bits 7:4 = V[7:4]: Most significant nibble of Exter-
nal Interrupt Vector.
These bits are not initialized by reset. For a repre-
sentation of how the full vector is generated from
V[7:4] and the selected external interrupt channel,
refer to Figure 51.
Reset value: 0000 0000 (00h)
7
0
TLNM HL6 HL5 HL4 HL3 HL2 HL1 HL0
Bit 7 = TLNM: Top Level Not Maskable.
This bit is set by software and cleared only by a
hardware reset.
0: Top Level Interrupt Maskable. A top level re-
quest is generated if the IEN, TLI and TLIP bits
=1
Bit 3 = TLTEV: Top Level Trigger Event bit.
This bit is set and cleared by software.
0: Select falling edge as NMI trigger event
1: Select rising edge as NMI trigger event
1: Top Level Interrupt Not Maskable. A top level
request is generated if the TLIP bit =1
Bit 2 = TLIS: Top Level Input Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
(the IA0S bit must be set in this case)
1: NMI is TL interrupt source
Bits 6:0 = HL[6:0]: Hold Level x
These bits are set by hardware when, in Nested
Mode, an interrupt service routine at level x is in-
terrupted from a request with higher priority (other
than the Top Level interrupt request). They are
cleared by hardware at the iretexecution when
the routine at level x is recovered.
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source (the
TLIS bit must be set in this case)
1: External Interrupt pin is INTA0 source
Bit 0 = EWEN: External Wait Enable.
This bit is set and cleared by software.
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ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
INTERRUPT MASK REGISTER HIGH (SIMRH)
1: The I0 pending bit will be set on the rising edge
of the interrupt line
R245 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Note: The ITEI0 bit must be set to enable the SCI-
A interrupt as the SCI-A interrupt event is a rising
edge event.
7
-
0
-
-
-
-
-
-
IMI0
INTERRUPT TRIGGER EVENT REGISTER LOW
(SITRL)
R248 - Read/Write
Bits 7:1 = Reserved.
Bit 0 = IMI0 Channel I Mask bit
Register Page: 60
Reset value: 0000 0000 (00h)
The IMI0 bit is set and cleared by software to ena-
ble or disable interrupts on channel I0 .
0: Interrupt masked
1: An interrupt is generated if the IPI0 bit is set in
the SIPRH register.
7
0
ITEH1 ITEH0 ITEG1 ITEG0 ITEF1 ITEF0 ITEE1 ITEE0
Bits 7:0 = ITExx Channel E to H Trigger Event
The ITExx bits are set and cleared by software to
define the polarity of the channel xx trigger event
0: The corresponding pending bit will be set on the
falling edge of the interrupt line
1: The corresponding pending bit will be set on the
rising edge of the interrupt line
INTERRUPT MASK REGISTER LOW (SIMRL)
R246 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
7
0
Note: The ITExx bits must be set to enable the
CAN interrupts as the CAN interrupt events are ris-
ing edge events.
IMH1 IMH0 IMG1 IMG0 IMF1
IMF0 IME1
IME0
Bits 7:0 = IMxx Channel E to H Mask bits
Note: If either a rising or a falling edge occurs on
the interrupt lines during a write access to the
ITER register, the pending bit will not be set.
The IMxx bits are set and cleared by software to
enable or disable on channel xx interrupts.
0: Interrupt masked
1: An interrupt is generated if the corresponding
IPxx bit is set in the SIPRL register.
INTERRUPT PENDING REGISTER HIGH
(SIPRH)
R249 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
INTERRUPT TRIGGER EVENT REGISTER
HIGH (SITRH)
R247 - Read/Write
7
-
0
Register Page: 60
Reset value: 0000 0000 (00h)
-
-
-
-
-
-
IPI0
7
-
0
Bits 7:1 = Reserved.
Bit 0 = IPI0 Channel I0 Pending bit
-
-
-
-
-
-
ITEI0
The IPI0 bit is set by hardware on occurrence of
the trigger event. (as specified in the ITR register)
and is cleared by hardware on interrupt acknowl-
edge.
Bits 7:1 = Reserved.
Bit 0 = ITEI0 Channel I0 Trigger Event
This bit is set and cleared by software to define the
polarity of the channel I0 trigger event
0: The I0 pending bit will be set on the falling edge
of the interrupt line
0 : No interrupt pending
1 : Interrupt pending
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ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
INTERRUPT PENDING REGISTER LOW
(SIPRL)
Bits 4:1 = W[3:0] Arbitration Winner Bits
These bits are set and cleared by hardware de-
pending upon the channel which emerges as a
winner as shown in the following table.
R250 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Interrupt Channel pair
INTE0
W[3:0]
0000
7
0
INTE1
0001
0010
0011
0100
0101
0110
0111
1000
IPH1 IPH0 IPG1 IPG0
IPF1
IPF0
IPE1
IPE0
INTF0
INTF1
Bits 7:0 = IPxx Channel E-H Pending bits
INTG0
The IPxx bits are set by hardware on occurrence
of the trigger event. (as specified in the ITR regis-
ter) and are cleared by hardware on interrupt ac-
knowledge.
INTG1
INTH0
INTH1
INTI0
0 : No interrupt pending
1 : Interrupt pending
At the start of interrupt/DMA arbitration (IC0 = 0)
the W[3:0] bits are latched. They remain stable
through the entire arbitration cycle. Even if a inter-
rupt of higher priority comes after the start of int/
DMA arbitration, the SIVR register is not updated.
This new request will be taken into account in the
next arbitration cycle.
Note: IPR bits may be set by the user to imple-
ment a software interrupt.
STANDARD INTERRUPT VECTOR REGISTER
(SIVR)
R251 - Read/Write
Register Page: 60
Reset value: xxx1 1110 (xE)
Bit 0 = Reserved, fixed by hardware to 0.
7
0
0
INTERRUPT PRIORITY LEVEL REGISTER
HIGH (SIPLRH)
V7
V6
V5
W3
W2
W1
W0
R252 - Read/Write
Register Page: Page 60
Reset Value : 1111 1111
Bits 7:5 = V[7:5] MSBs of Channnel E to L inter-
rupt vector address
These bits are not initialized by reset. For a repre-
sentation of how the full vector is generated from
V[7:5], refer to Figure 53.
7
-
0
-
-
-
-
-
PL2I
PL1I
Bits 1:0 = PL2I, PL1I: INTI0, I1 Priority Level.
These bits are set and cleared by software.
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for even channels and at 1 for odd
channels
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ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
INTERRUPT PRIORITY LEVEL REGISTER LOW
(SIPLRL)
Interrupt Channel
Pair
Priority Level
R253 - Read/Write
INTE0
INTE1
INTF0
INTF1
INTG0
INTG1
INTH0
INTH1
PL2E
PL2E
PL2F
PL2F
PL2G
PL2G
PL2H
PL2H
PL1E
PL1E
PL1F
PL1F
PL1G
PL1G
PL1H
PL1H
0
1
0
1
0
1
0
1
Register Page: Page 60
Reset Value : 1111 1111
7
0
PL2H PL1H PL2G PL1G PL2F PL1F PL2E PL1E
Bits 7:6 = PL2H, PL1H: INTH0,H1 Priority Level.
Bits 5:4 = PL2G, PL1G: INTG0, G1 Priority Level.
Bits 3:2 = PL2F, PL1F: INTF0, F1 Priority Level.
Bits 1:0 = PL2E, PL1E: INTE0, E1 Priority Level.
These bits are set and cleared by software.
INTERRUPT FLAG REGISTER HIGH
(SFLAGRH)
R254 - Read Only
Register Page: 60
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for even channels and at 1 for odd
channels
Reset Value : 0000 0000
7
0
Table 22. PL Bit Assignment
-
-
-
-
-
-
-
OUFI0
Interrupt Channel
3-bit Priority Level
Pair
Bit 0 = OUFI0 : Overrun flag for INTI0
INTH0
INTH1
INTG0
INTG1
INTF0
INTF1
INTE0
INTE1
PL2H
PL2H
PL2G
PL2G
PL2F
PL2F
PL2E
PL2E
PL1H
PL1H
PL1G
PL1G
PL1F
PL1F
PL1E
PL1E
0
1
0
1
0
1
0
1
This bit is set and cleared by hardware. It indicates
if more than one interrupt event occured on INTI0
before the IPI0 bit in the SIPRH register has been
cleared.
0 : No overrun
1 : Overrun has occurred on INTI0
INTERRUPT FLAG REGISTER LOW
(SFLAGRL)
R255 - Read Only
Register Page: 60
Reset Value : 0000 0000
Table 23. PL bit Meaning
PL2x
PL1x
Hardware bit
Priority
7
0
0
1
0 (Highest)
1
0
0
OUFH1 OUFH0 OUFG1 OUFG0 OUFF1 OUFF0 OUFE1 OUFE0
0
1
2
3
0
1
1
1
0
1
Bits 7:0 = OUFxx : Overrun flag for channel xx
These bits are set and cleared by hardware. They
indicate if more than one interrupt event occurs on
the associated channel before the pending bit in
the SIPRL register has been cleared.
0
1
4
5
0
1
6
7 (Lowest)
0 : No overrun
1 : Overrun has occurred on channel xx
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ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
Table 25. Standard Interrupt Channel Register map (Page 60)
Register
Address
7
6
5
4
3
2
1
0
Name
SIMRH
IMI0
R245
0
0
0
0
0
0
0
Reset value
SIMRL
0
IMH1
0
IMH0
0
IMG1
0
IMG0
0
IMF1
0
IMF0
0
IME1
0
IME0
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
Reset value
SITRH
0
ITEI0
0
0
0
0
0
0
0
Reset value
SITRL
0
ITEH1
0
ITEH0
0
ITEG1
0
ITEG0
0
ITEF1
0
ITEF0
0
ITEE1
0
ITEE0
Reset value
SIPRH
0
IPI0
0
0
0
0
0
0
0
Reset value
SIPRL
0
IPH1
0
IPH0
0
IPG1
0
IPG0
0
IPF1
0
IPF0
0
IPE1
0
IPE0
Reset value
SIVR
0
V2
x
V1
x
V0
x
W3
1
W2
1
W1
1
W0
1
0
0
Reset value
SIPLRH
PL2I
1
PL1I
1
0
0
0
0
0
0
Reset value
SIPLRL
PL2H
1
PL1H
1
PL2G
1
PL1G
1
PL2F
1
PL1F
1
PL2E
1
PL1E
1
Reset value
SFLAGRH
Reset value
SFLAGRL
Reset value
OUF0
0
0
0
0
0
0
0
0
OUF7
0
OUF6
0
OUF5
0
OUF4
0
OUF3
0
OUF2
0
OUF1
0
OUF0
0
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5.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)
5.12.1 Introduction
5.12.2 Main Features
■ Supports up to 16 additional external wake-up
The Wake-up/Interrupt Management Unit extends
the number of external interrupt lines from 8 to 23
(depending on the number of external interrupt
lines mapped on external pins of the device).
or interrupt lines
■ Wake-Up lines can be used to wake-up the ST9
from STOP mode.
The 16 additional external Wake-up/interrupt pins
can be programmed as external interrupt lines or
as wake-up lines, able to exit the microcontroller
from low power mode (STOP mode) (see Figure
55).
■ Programmable selection of wake-up or interrupt
■ Programmable wake-up trigger edge polarity
■ All Wake-Up Lines maskable
Note: The number of available pins is device de-
pendent. Refer to the device pinout description.
Figure 55. Wake-Up Lines / Interrupt Management Unit Block Diagram
WKUP[7:0]
WKUP[15:8]
NMI
WUTRH
WUTRL
TRIGGERING LEVEL REGISTERS
PENDING REQUEST REGISTERS
MASK REGISTERS
WUPRH
WUMRH
WUPRL
WUMRL
Not Connected
1)
SW SETTING
1
0
WUCTRL
TO CPU
INTD1 - External Interrupt Channel
TO CPU
TO RCCU - Stop Mode Control
Note 1: The reset signal on the Stop bit is stronger than the set signal.
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ST92F124/F150/F250 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.12.3 Functional Description
5.12.3.1 Interrupt Mode
wake-up event does not require an interrupt
response.
7. Write the sequence 1,0,1 to the STOP bit of the
WUCTRL register with three consecutive write
operations. This is the STOP bit setting
sequence.
To configure the 16 wake-up lines as interrupt
sources, use the following procedure:
1. Configure the mask bits of the 16 wake-up lines
(WUMRL, WUMRH)
To detect if STOP Mode was entered or not, im-
mediately after the STOP bit setting sequence,
poll the RCCU EX_STP bit (R242.7, Page 55) and
the STOP bit itself.
2. Configure the triggering edge registers of the
wake-up lines (WUTRL, WUTRH)
3. Set bit 7 of EIMR (R244 Page 0) and EITR
(R242 Page 0) registers of the CPU: so an
interrupt coming from one of the 16 lines can be
correctly acknowledged
5.12.3.3 STOP Mode Entry Conditions
Assuming the ST9 is in Run mode: during the
STOP bit setting sequence the following cases
may occur:
4. Reset the WKUP-INT bit in the WUCTRL regis-
ter to disable Wake-up Mode
5. Set the ID1S bit in the WUCTRL register to
enable the 16 wake-up lines as external inter-
rupt source lines.
Case 1: NMI = 0, wrong STOP bit setting se-
quence
This can happen if an Interrupt/DMA request is ac-
knowledged during the STOP bit setting se-
quence. In this case polling the STOP and
EX_STP bits will give:
5.12.3.2 Wake-up Mode Selection
To configure the 16 lines as wake-up sources, use
the following procedure:
STOP = 0, EX_STP = 0
1. Configure the mask bits of the 16 wake-up lines
(WUMRL, WUMRH).
This means that the ST9 did not enter STOP mode
due to a bad STOP bit setting sequence: the user
must retry the sequence.
2. Configure the triggering edge registers of the
wake-up lines (WUTRL, WUTRH).
Case 2: NMI = 0, correct STOP bit setting se-
quence
3. Set, as for Interrupt Mode selection, bit 7 of
EIMR and EITR registers only if an interrupt
routine is to be executed after a wake-up event.
Otherwise, if the wake-up event only restarts
the execution of the code from where it was
stopped, the INTD1 interrupt channel must be
masked.
In this case the ST9 enters STOP mode. There are
two ways to exit STOP mode:
1. A wake-up interrupt (not an NMI interrupt) is
acknowledged. That implies:
STOP = 0, EX_STP = 1
4. Since the RCCU can generate an interrupt
request when exiting from STOP mode, take
care to mask it even if the wake-up event is
only to restart code execution.
This means that the ST9 entered and exited STOP
mode due to an external wake-up line event.
2. A NMI rising edge woke up the ST9. This
implies:
5. Set the WKUP-INT bit in the WUCTRL register
to select Wake-up Mode
STOP = 1, EX_STP = 1
This means that the ST9 entered and exited STOP
mode due to an NMI (rising edge) event. The user
should clear the STOP bit via software.
6. Set the ID1S bit in the WUCTRL register to
enable the 16 wake-up lines as external inter-
rupt source lines. This is not mandatory if the
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
Case 3: NMI = 1 (NMI kept high during the 3rd
write instruction of the sequence), bad STOP
bit setting sequence
STOP = 0, EX_STP = 0
The application can determine why the ST9 did
not enter STOP mode by polling the pending
bits of the external lines (at least one must be at
1).
The result is the same as Case 1:
STOP = 0, EX_STP = 0
This means that the ST9 did not enter STOP mode
due to a bad STOP bit setting sequence: the user
must retry the sequence.
2. Interrupt requests to CPU are enabled: in this
case the ST9 will not enter STOP mode and the
interrupt service routine will be executed. The
status of STOP and EX_STP bits will be again:
Case 4: NMI = 1 (NMI kept high during the 3rd
write instruction of the sequence), correct
STOP bit setting sequence
STOP = 0, EX_STP = 0
The interrupt service routine can determine why
the ST9 did not enter STOP mode by polling
the pending bits of the external lines (at least
one must be at 1).
In this case:
STOP = 1, EX_STP = 0
This means that the ST9 did not enter STOP mode
due to NMI being kept high. The user should clear
the STOP bit via software.
If the MCU really exits from STOP Mode, the
RCCU EX_STP bit is still set and must be reset by
software. Otherwise, if NMI was high or an Inter-
rupt/DMA request was acknowledged during the
STOP bit setting sequence, the RCCU EX_STP bit
is reset. This means that the MCU has filtered the
STOP Mode entry request.
Note: If NMI goes to 0 before resetting the STOP
bit, the ST9 will not enter STOP mode.
Case 5: A rising edge on the NMI pin occurs
during the STOP bit setting sequence.
The NMI interrupt will be acknowledged and the
ST9 will not enter STOP mode. This implies:
The WKUP-INT bit can be used by an interrupt
routine to detect and to distinguish events coming
from Interrupt Mode or from Wake-up Mode, allow-
ing the code to execute different procedures.
STOP = 0, EX_STP = 0
This means that the ST9 did not enter STOP mode
due to an NMI interrupt serviced during the STOP
bit setting sequence. At the end of NMI routine, the
user must re-enter the sequence: if NMI is still high
at the end of the sequence, the ST9 can not enter
STOP mode (See “NMI Pin Management” on
page 115.).
To exit STOP mode, it is sufficient that one of the
16 wake-up lines (not masked) generates an
event: the clock restarts after the delay needed for
the oscillator to restart.
The same effect is obtained when a rising edge is
detected on the NMI pin, which works as a 17th
wake-up line.
Case 6: A wake-up event on the external wake-
up lines occurs during the STOP bit setting se-
quence
Note: After exiting from STOP Mode, the software
can successfully reset the pending bits (edge sen-
sitive), even though the corresponding wake-up
line is still active (high or low, depending on the
Trigger Event register programming); the user
must poll the external pin status to detect and dis-
tinguish a short event from a long one (for example
keyboard input with keystrokes of varying length).
There are two possible cases:
1. Interrupt requests to the CPU are disabled: in
this case the ST9 will not enter STOP mode, no
interrupt service routine will be executed and
the program execution continues from the
instruction following the STOP bit setting
sequence. The status of STOP and EX_STP
bits will be again:
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.12.3.4 NMI Pin Management
– If the ST9 is in Run mode and a rising edge oc-
curs on the NMI pin: the NMI service routine is
executed and then the ST9 restarts the execu-
tion of the main program. Now, suppose that
the user wants to enter STOP mode with NMI
still at 1. The ST9 will not enter STOP mode
and it will not execute an NMI routine be-
cause there were no transitions on the exter-
nal NMI line.
On the CPU side, if TLTEV=1 (Top Level Trigger
Event, bit 3 of register R246, page 0) then a rising
edge on the NMI pin will set the TLIP bit (Top Level
Interrupt Pending bit, R230.6). At this point an in-
terrupt request to the CPU is given either if TL-
NM=1 (Top Level Not Maskable bit, R247.7 - once
set it can only be cleared by RESET) or if TLI=1
and IEN=1 (bits R230.5, R230.4).
– If the ST9 is in run mode and a rising edge on
NMI pin occurs during the STOP bit setting se-
quence: the NMI interrupt will be acknowledged
and the ST9 will not enter STOP mode. At the
end of the NMI routine, the user must re-enter
the sequence: if NMI is still high at the end of the
sequence, the ST9 can not enter STOP mode
(see previous case).
Assuming that the application uses a non-maska-
ble Top Level Interrupt (TLNM=1): in this case,
whenever a rising edge occurs on the NMI pin, the
related service routine will be executed. To service
further Top Level Interrupt Requests, it is neces-
sary to generate a new rising edge on the external
NMI pin.
The following summarizes some typical cases:
– If the ST9 is in run mode and the NMI pin is high:
if NMI is forced low just before the third write in-
struction of the STOP bit setting sequence then
the ST9 will enter STOP mode.
– If the ST9 is in STOP mode and a rising edge on
the NMI pin occurs, the ST9 will exit STOP
mode and the NMI service routine will be exe-
cuted.
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.12.4 Programming Considerations
9. Poll the wake-up pending bits to determine
which wake-up line caused the exit from STOP
mode.
The following paragraphs give some guidelines for
designing an application program.
10.Clear the wake-up pending bit that was set.
5.12.4.1 Procedure for Entering/Exiting STOP
mode
5.12.4.2 Simultaneous Setting of Pending Bits
1. Program the polarity of the trigger event of
external wake-up lines by writing registers
WUTRH and WUTRL.
It is possible that several simultaneous events set
different pending bits. In order to accept subse-
quent events on external wake-up/interrupt lines, it
is necessary to clear at least one pending bit: this
operation allows a rising edge to be generated on
the INTD1 line (if there is at least one more pend-
ing bit set and not masked) and so to set EIPR.7
bit again. A further interrupt on channel INTD1 will
be serviced depending on the status of bit EIMR.7.
Two possible situations may arise:
2. Check that at least one mask bit (registers
WUMRH, WUMRL) is equal to 1 (so at least
one external wake-up line is not masked).
3. Reset at least the unmasked pending bits: this
allows a rising edge to be generated on the
INTD1 channel when the trigger event occurs
(an interrupt on channel INTD1 is recognized
when a rising edge occurs).
1. The user chooses to reset all pending bits: no
further interrupt requests will be generated on
channel INTD1. In this case the user has to:
4. Set the ID1S bit in the WUCTRL register and
set the WKUP-INT bit.
– Reset EIMR.7 bit (to avoid generating a spuri-
ous interrupt request during the next reset op-
eration on the WUPRH register)
5. To generate an interrupt on channel INTD1, bits
EITR.1 (R242.7, Page 0) and EIMR.1 (R244.7,
Page 0) must be set and bit EIPR.7 must be
reset. Bits 7 and 6 of register R245, Page 0
must be written with the desired priority level for
interrupt channel INTD1.
– Reset WUPRH register using a read-modify-
write instruction (AND, BRES, BAND)
– Clear the EIPR.7 bit
– Reset the WUPRL register using a read-mod-
ify-write instruction (AND, BRES, BAND)
6. Reset the STOP bit in register WUCTRL and
the EX_STP bit in the CLK_FLAG register
(R242.7, Page 55). Refer to the RCCU chapter.
2. The user chooses to keep at least one pending
bit active: at least one additional interrupt
request will be generated on the INTD1 chan-
nel. In this case the user has to reset the
desired pending bits with a read-modify-write
instruction (AND, BRES, BAND). This operation
will generate a rising edge on the INTD1 chan-
nel and the EIPR.7 bit will be set again. An
interrupt on the INTD1 channel will be serviced
depending on the status of EIMR.7 bit.
7. To enter STOP mode, write the sequence 1, 0,
1 to the STOP bit in the WUCTRL register with
three consecutive write operations.
8. The code to be executed just after the STOP
sequence must check the status of the STOP
and RCCU EX_STP bits to determine if the ST9
entered STOP mode or not (See “Wake-up
Mode Selection” on page 113. for details). If the
ST9 did not enter in STOP mode it is necessary
to reloop the procedure from the beginning, oth-
erwise the procedure continues from next point.
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5.12.5 Register Description
low, the ST9 will enter STOP mode independently
of the status of the STOP bit.
WAKE-UP CONTROL REGISTER (WUCTRL)
R249 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
WARNINGS:
– Writing the sequence 1,0,1 to the STOP bit will
enter STOP mode only if no other register write
instructions are executed during the sequence. If
Interrupt or DMA requests (which always perform
register write operations) are acknowledged dur-
ing the sequence, the ST9 will not enter STOP
mode: the user must re-enter the sequence to
set the STOP bit.
7
0
-
-
-
-
-
STOP ID1S WKUP-INT
Bit 2 = STOP: Stop bit.
To enter STOP Mode, write the sequence 1,0,1 to
this bit with three consecutive write operations.
When a correct sequence is recognized, the
STOP bit is set and the RCCU puts the MCU in
STOP Mode. The software sequence succeeds
only if the following conditions are true:
– Whenever a STOP request is issued to the MCU,
a few clock cycles are needed to enter STOP
mode (see RCCU chapter for further details).
Hence the execution of the instruction following
the STOP bit setting sequence might start before
entering STOP mode: if such instruction per-
forms a register write operation, the ST9 will not
enter in STOP mode. In order to avoid to execute
register write instructions after a correct STOP
bit setting sequence and before entering the
STOP mode, it is mandatory to execute 3 NOP
instructions after the STOP bit setting sequence.
Refer to Section 13.1.2 on page 408.
– The NMI pin is kept low,
– The WKUP-INT bit is 1,
– All unmasked pending bits are reset
– At least one mask bit is equal to 1 (at least one
external wake-up line is not masked).
Otherwise the MCU cannot enter STOP mode, the
program code continues executing and the STOP
bit remains cleared.
Bit 1 = ID1S: Interrupt Channel INTD1 Source.
This bit is set and cleared by software.
It enables the 16 wake-up lines as external inter-
rupt sources. This bit must be set to 1 to enable
the wake-up lines.
The bit is reset by hardware if, while the MCU is in
STOP mode, a wake-up interrupt comes from any
of the unmasked wake-up lines. The bit is kept
high if, during STOP mode, a rising edge on NMI
pin wakes up the ST9. In this case the user should
reset it by software. The STOP bit is at 1 in the four
following cases (See “Wake-up Mode Selection”
on page 113. for details):
WARNING: To avoid spurious interrupt requests
on the INTD1 channel due to changing the inter-
rupt source, use this procedure to modify the ID1S
bit:
– After the first write instruction of the sequence (a
1 is written to the STOP bit)
1. Mask the INTD1 interrupt channel (bit 7 of reg-
ister EIMR - R244, Page 0 - reset to 0).
– At the end of a successful sequence (i.e. after
the third write instruction of the sequence)
2. Set the ID1S bit.
3. Clear the IPD1 interrupt pending bit (bit 7 of
register EIPR - R243, Page 0)
– The ST9 entered and exited STOP mode due to
a rising edge on the NMI pin. In this case the
EX_STP bit in the CLK_FLAG is at 1 (see
RCCU chapter).
4. Remove the mask on INTD1 (bit EIMR.7=1).
– The ST9 did not enter STOP mode due to the
NMI pin being kept high. In this case RCCU bit
EX_STP is at 0
Bit 0 = WKUP-INT: Wakeup Interrupt.
This bit is set and cleared by software.
0: The 16 external wakeup lines can be used to
generate interrupt requests
1: The 16 external wake-up lines to work as wake-
up sources for exiting from STOP mode
Note: The STOP request generated by the
WUIMU (that allows the ST9 to enter STOP mode)
is ORed with the external STOP pin (active low).
This means that if the external STOP pin is forced
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
WAKE-UP MASK REGISTER HIGH (WUMRH)
R250 - Read/Write
WAKE-UP MASK REGISTER LOW (WUMRL)
R251 - Read/Write
Register Page: 57
Register Page: 57
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 WUM8
WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1 WUM0
Bit 7:0 = WUM[15:8]: Wake-Up Mask bits.
If WUMx is set, an interrupt on channel INTD1
and/or a wake-up event (depending on ID1S and
WKUP-INT bits) are generated if the correspond-
ing WUPx pending bit is set. More precisely, if
WUMx=1 and WUPx=1 then:
Bit 7:0 = WUM[7:0]: Wake-Up Mask bits.
If WUMx is set, an interrupt on channel INTD1
and/or a wake-up event (depending on ID1S and
WKUP-INT bits) are generated if the correspond-
ing WUPx pending bit is set. More precisely, if
WUMx=1 and WUPx=1 then:
– If ID1S=1 and WKUP-INT=1 then an interrupt on
channel INTD1 and a wake-up event are gener-
ated.
– If ID1S=1 and WKUP-INT=1 then an interrupt on
channel INTD1 and a wake-up event are gener-
ated.
– If ID1S=1 and WKUP-INT=0 only an interrupt on
channel INTD1 is generated.
– If ID1S=1 and WKUP-INT=0 only an interrupt on
channel INTD1 is generated.
If WUMx is reset, no wake-up events can be gen-
erated.
If WUMx is reset, no wake-up events can be gen-
erated.
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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
WAKE-UP
TRIGGER
REGISTER
HIGH
WAKE-UP PENDING REGISTER HIGH
(WUPRH)
(WUTRH)
R252 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
R254 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
7
0
7
0
WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 WUT8
WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9 WUP8
Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity
Bits
These bits are set and cleared by software.
0: The corresponding WUPx pending bit will be set
on the falling edge of the input wake-up line .
1: The corresponding WUPx pending bit will be set
on the rising edge of the input wake-up line.
Bit 7:0 = WUP[15:8]: Wake-Up Pending Bits
These bits are set by hardware on occurrence of
the trigger event on the corresponding wake-up
line. They must be cleared by software. They can
be set by software to implement a software inter-
rupt.
0: No Wake-up Trigger event occurred
1: Wake-up Trigger event occured
WAKE-UP TRIGGER REGISTER LOW (WUTRL)
R253 - Read/Write
WAKE-UP PENDING REGISTER LOW (WUPRL)
R255 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
Register Page: 57
7
0
Reset Value: 0000 0000 (00h)
7
0
WUT7 WUT6 WUT5 WUT4 WUT3 WUT2 WUT1 WUT0
WUP7 WUP6 WUP5 WUP4 WUP3 WUP2 WUP1 WUP0
Bit 7:0 = WUT[7:0]: Wake-Up Trigger Polarity Bits
These bits are set and cleared by software.
0: The corresponding WUPx pending bit will be set
on the falling edge of the input wake-up line.
1: The corresponding WUPx pending bit will be set
on the rising edge of the input wake-up line.
Bit 7:0 = WUP[7:0]: Wake-Up Pending Bits
These bits are set by hardware on occurrence of
the trigger event on the corresponding wake-up
line. They must be cleared by software. They can
be set by software to implement a software inter-
rupt.
WARNING
0: No Wake-up Trigger event occurred
1: Wake-up Trigger event occured
1. As the external wake-up lines are edge trig-
gered, no glitches must be generated on these
lines.
Note: To avoid losing a trigger event while clear-
ing the pending bits, it is recommended to use
read-modify-write instructions (AND, BRES,
BAND) to clear them.
2. If either a rising or a falling edge on the external
wake-up lines occurs while writing the
WUTRLH or WUTRL registers, the pending bit
will not be set.
5.12.6 Important Note On WUIMU
Refer to Section 13.1.2 on page 408.
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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
6 ON-CHIP DIRECT MEMORY ACCESS (DMA)
6.1 INTRODUCTION
6.2 DMA PRIORITY LEVELS
The ST9 includes on-chip Direct Memory Access
(DMA) in order to provide high-speed data transfer
between peripherals and memory or Register File.
Multi-channel DMA is fully supported by peripher-
als having their own controller and DMA chan-
nel(s). Each DMA channel transfers data to or
from contiguous locations in the Register File, or in
Memory. The maximum number of bytes that can
be transferred per transaction by each DMA chan-
nel is 222 with the Register File, or 65536 with
Memory.
The 8 priority levels used for interrupts are also
used to prioritize the DMA requests, which are ar-
bitrated in the same arbitration phase as interrupt
requests. If the event occurrence requires a DMA
transaction, this will take place at the end of the
current instruction execution. When an interrupt
and a DMA request occur simultaneously, on the
same priority level, the DMA request is serviced
before the interrupt.
An interrupt priority request must be strictly higher
than the CPL value in order to be acknowledged,
whereas, for a DMA transaction request, it must be
equal to or higher than the CPL value in order to
be executed. Thus only DMA transaction requests
can be acknowledged when the CPL=0.
The DMA controller in the Peripheral uses an indi-
rect addressing mechanism to DMA Pointers and
Counter Registers stored in the Register File. This
is the reason why the maximum number of trans-
actions for the Register File is 222, since two Reg-
isters are allocated for the Pointer and Counter.
Register pairs are used for memory pointers and
counters in order to offer the full 65536 byte and
count capability.
DMA requests do not modify the CPL value, since
the DMA transaction is not interruptable.
Figure 56. DMA Data Transfer
REGISTER FILE
REGISTER FILE
OR
MEMORY
DF
REGISTER FILE
GROUP F
PERIPHERAL
PAGED
COUNTER
ADDRESS
PERIPHERAL
DATA
REGISTERS
0
COUNTER VALUE
TRANSFERRED
DATA
START ADDRESS
VR001834
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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
6.3 DMA TRANSACTIONS
The purpose of an on-chip DMA channel is to
transfer a block of data between a peripheral and
the Register File, or Memory. Each DMA transfer
consists of three operations:
register, and the DMA Transaction Counter in the
next register (odd address). They are pointed to by
the DMA Transaction Counter Pointer Register
(DCPR), located in the peripheral’s paged regis-
ters. In order to select a DMA transaction with the
Register File, the control bit DCPR.RM (bit 0 of
DCPR) must be set.
– A load from/to the peripheral data register to/
from a location of Register File (or Memory) ad-
dressed through the DMA Address Register (or
Register pair)
If the transaction is made between the peripheral
and Memory, a register pair (16 bits) is required
for the DMA Address and the DMA Transaction
Counter (Figure 58). Thus, two register pairs must
be located in the Register File.
– A post-increment of the DMA Address Register
(or Register pair)
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
The DMA Transaction Counter is pointed to by the
DMA Transaction Counter Pointer Register
(DCPR), the DMA Address is pointed to by the
DMA Address Pointer Register (DAPR),both
DCPR and DAPR are located in the paged regis-
ters of the peripheral.
If the DMA transaction is carried out between the
peripheral and the Register File (Figure 57), one
register is required to hold the DMA Address, and
one to hold the DMA transaction counter. These
two registers must be located in the Register File:
the DMA Address Register in the even address
Figure 57. DMA Between Register File and Peripheral
IDCR
IVR
DAPR
FFh
END OF BLOCK
INTERRUPT
SERVICE ROUTINE
DCPR
PAGED
DATA
REGISTERS
F0h
EFh
PERIPHERAL
PAGED REGISTERS
000100h
000000h
SYSTEM
VECTOR
TABLE
ISR ADDRESS
MEMORY
REGISTERS
E0h
DFh
DMA
TABLE
DATA
ALREADY
TRANSFERRED
DMA
COUNTER
DMA
ADDRESS
REGISTER FILE
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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
DMA TRANSACTIONS (Cont’d)
When selecting the DMA transaction with memory,
bit DCPR.RM (bit 0 of DCPR) must be cleared.
When the Interrupt Pending (IDCR.IP) bit is set by
a hardware event (or by software), and the DMA
Mask bit (IDCR.DM) is set, a DMA request is gen-
erated. If the Priority Level of the DMA source is
higher than, or equal to, the Current Priority Level
(CPL), the DMA transfer is executed at the end of
the current instruction. DMA transfers read/write
data from/to the location pointed to by the DMA
Address Register, the DMA Address register is in-
cremented and the Transaction Counter Register
is decremented. When the contents of the Trans-
action Counter are decremented to zero, the DMA
Mask bit (DM) is cleared and an interrupt request
is generated, according to the Interrupt Mask bit
(End of Block interrupt). This End-of-Block inter-
rupt request is taken into account, depending on
the PRL value.
ToselectbetweenusingtheISRortheDMASRreg-
ister to extend the address, (see Memory Manage-
ment Unit chapter), the control bit DAPR.PS (bit 0
of DAPR) must be cleared or set respectively.
The DMA transaction Counter must be initialized
with the number of transactions to perform and will
be decremented after each transaction. The DMA
Address must be initialized with the starting ad-
dress of the DMA table and is increased after each
transaction. These two registers must be located
between addresses 00h and DFh of the Register
File.
Once a DMA channel is initialized, a transfer can
start. The direction of the transfer is automatically
defined by the type of peripheral and programming
mode.
WARNING. DMA requests are not acknowledged
if the top level interrupt service is in progress.
Once the DMA table is completed (the transaction
counter reaches 0 value), an Interrupt request to
the CPU is generated.
Figure 58. DMA Between Memory and Peripheral
IDCR
IVR
DMA TRANSACTION
DAPR
FFh
DCPR
PAGED
DATA
REGISTERS
F0h
EFh
PERIPHERAL
PAGED REGISTERS
DMA
TABLE
SYSTEM
DATA
ALREADY
REGISTERS
TRANSFERRED
E0h
DFh
END OF BLOCK
INTERRUPT
SERVICE ROUTINE
DMA
TRANSACTION
COUNTER
000100h
000000h
DMA
VECTOR
TABLE
ADDRESS
ISR ADDRESS
MEMORY
REGISTER FILE
n
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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
DMA TRANSACTIONS (Cont’d)
6.4 DMA CYCLE TIME
transfer from two DMA tables alternatively. All the
DMA descriptors in the Register File are thus dou-
bled. Two DMA transaction counters and two DMA
address pointers allow the definition of two fully in-
dependent tables (they only have to belong to the
same space, Register File or Memory). The DMA
transaction is programmed to start on one of the
two tables (say table 0) and, at the end of the
block, the DMA controller automatically swaps to
the other table (table 1) by pointing to the other
DMA descriptors. In this case, the DMA mask (DM
bit) control bit is not cleared, but the End Of Block
interrupt request is generated to allow the optional
updating of the first data table (table 0).
The interrupt and DMA arbitration protocol func-
tions completely asynchronously from instruction
flow.
Requests are sampled every 5 CPUCLK cycles.
DMA transactions are executed if their priority al-
lows it.
A DMA transfer with the Register file requires 8
CPUCLK cycles.
A DMA transfer with memory requires 16 CPUCLK
cycles, plus any required wait states.
6.5 SWAP MODE
Until the swap mode is disabled, the DMA control-
ler will continue to swap between DMA Table 0
and DMA Table 1.
An extra feature which may be found on the DMA
channels of some peripherals (e.g. the MultiFunc-
tion Timer) is the Swap mode. This feature allows
n
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9
ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
6.6 DMA REGISTERS
Bit 3 = IM: End of block Interrupt Mask.
This bit is set and cleared by software.
0: No End of block interrupt request is generated
when IP is set
As each peripheral DMA channel has its own spe-
cific control registers, the following register list
should be considered as a general example. The
names and register bit allocations shown here
may be different from those found in the peripheral
chapters.
1: End of Block interrupt is generated when IP is
set. DMA requests depend on the DM bit value
as shown in the table below.
DM IM Meaning
DMA COUNTER POINTER REGISTER (DCPR)
Read/Write
Address set by Peripheral
Reset value: undefined
A DMA request generated without End of Block
interrupt when IP=1
1
1
0
0
0
1
0
1
A DMA request generated with End of Block in-
terrupt when IP=1
7
0
No End of block interrupt or DMA request is
generated when IP=1
C7
C6
C5
C4
C3
C2
C1
RM
An End of block Interrupt is generated without
associated DMA request (not used)
Bit 7:1 = C[7:1]: DMA Transaction Counter Point-
er.
Bit 2:0 = PRL[2:0]: Source Priority Level.
These bits are set and cleared by software. Refer
to Section 6.2 DMA PRIORITY LEVELS for a de-
scription of priority levels.
Software should write the pointer to the DMA
Transaction Counter in these bits.
PRL2 PRL1 PRL0 Source Priority Level
Bit 0 = RM: Register File/Memory Selector.
This bit is set and cleared by software.
0: DMA transactions are with memory (see also
DAPR.DP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 Highest
1
2
1: DMA transactions are with the Register File
3
4
GENERIC EXTERNAL PERIPHERAL INTER-
RUPT AND DMA CONTROL (IDCR)
Read/Write
Address set by Peripheral
Reset value: undefined
5
6
7 Lowest
DMA ADDRESS POINTER REGISTER (DAPR)
Read/Write
7
0
Address set by Peripheral
Reset value: undefined
IP
DM
IM PRL2 PRL1 PRL0
7
0
Bit 5 = IP: Interrupt Pending.
This bit is set by hardware when the Trigger Event
occurs. It is cleared by hardware when the request
is acknowledged. It can be set/cleared by software
in order to generate/cancel a pending request.
0: No interrupt pending
A7
A6
A5
A4
A3
A2
A1
PS
Bit 7:1 = A[7:1]: DMA Address Register(s) Pointer
Software should write the pointer to the DMA Ad-
dress Register(s) in these bits.
1: Interrupt pending
Bit 4 = DM: DMA Request Mask.
Bit 0 = PS: Memory Segment Pointer Selector:
This bit is set and cleared by software. It is only
meaningful if DCPR.RM=0.
0: The ISR register is used to extend the address
of data transferred by DMA (see MMU chapter).
1: The DMASR register is used to extend the ad-
dress of data transferred by DMA (see MMU
chapter).
This bit is set and cleared by software. It is also
cleared when the transaction counter reaches
zero (unless SWAP mode is active).
0: No DMA request is generated when IP is set.
1: DMA request is generated when IP is set
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9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
7 RESET AND CLOCK CONTROL UNIT (RCCU)
7.1 INTRODUCTION
the PLL multiplier circuit. The resulting signal,
CLOCK2, is the reference input clock to the pro-
grammable Phase Locked Loop frequency multi-
plier, which is capable of multiplying the clock fre-
quency by a factor of 6, 8, 10 or 14; the multiplied
clock is then divided by a programmable divider,
by a factor of 1 to 7. By these means, the ST9 can
operate with cheaper, medium frequency (3-5
MHz) crystals, while still providing a high frequen-
cy internal clock for maximum system perform-
ance; the range of available multiplication and divi-
sion factors allow a great number of operating
clock frequencies to be derived from a single crys-
tal frequency.
The Reset and Clock Control Unit (RCCU) com-
prises two distinct sections:
– the Clock Control Unit, which generates and
manages the internal clock signals.
– the Reset/Stop Manager, which detects and
flags Hardware, Software and Watchdog gener-
ated resets.
On ST9 devices where the external Stop pin and/
or the Wake-Up Interrupt Manager Unit are availa-
ble, this circuit also detects and manages the Stop
mode during which all oscillators are frozen in or-
der to achieve the lowest possible power con-
sumption (refer to the Reset/Stop mode and
Wake-Up Interrupt Manager Unit description).
For low power operation, especially in Wait for In-
terrupt mode, the Clock Multiplier unit may be
turned off, whereupon the output clock signal may
be programmed as CLOCK2 divided by 16. For
further power reduction, a low frequency external
clock connected to the CK_AF pin may be select-
ed, whereupon the crystal controlled main oscilla-
tor may be turned off.
7.2 CLOCK CONTROL UNIT
The Clock Control Unit generates the internal
clocks for the CPU core (CPUCLK) and for the on-
chip peripherals (INTCLK). The Clock Control Unit
may be driven by the on-chip oscillator (provided
an external crystal circuit is connected to the OS-
CIN and OSCOUT pins), or by an external pulse
generator, connected to OSCOUT (see Figure 66
and Figure 68). When significant power reduction
is required, a low frequency external clock may be
selected. To do this, this clock source must be
connected to the CK_AF pin.
The internal system clock, INTCLK, is routed to all
on-chip peripherals, as well as to the programma-
ble Clock Prescaler Unit which generates the clock
for the CPU core (CPUCLK). (See Figure 59)
The Clock Prescaler is programmable and can
slow the CPU clock by a factor of up to 8, allowing
the programmer to reduce CPU processing speed,
and thus power consumption, while maintaining a
high speed clock to the peripherals. This is partic-
ularly useful when little actual processing is being
done by the CPU and the peripherals are doing
most of the work.
7.2.1 Clock Control Unit Overview
As shown in Figure 59 a programmable divider
can divide the CLOCK1 input clock signal by two.
In practice, the divide-by-two is virtually always
used in order to ensure a 50% duty cycle signal to
Figure 59. Clock Control Unit Simplified Block Diagram
1/16
CPUCLK
to
CPU Core
CPU Clock
Prescaler
PLL
Clock Multiplier
Crystal
oscillator
/Divider Unit
1/2
CLOCK2
CLOCK1
CK_AF
INTCLK
to
CK_AF
source
Peripherals
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9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 60. ST92F124/F150/F250 Clock Distribution Diagram
1...64
1...8
Baud Rate
Prescaler
Baud Rate
Generator
1/2
SCK
Master
CAN
ADC
1/N
1...8
3-bit Prescaler
N=2,4,16,32
1/2
SCK
Slave
(Max INTCLK/2)
LOGIC
SPI
1...128
1...256
N=2,4,8
1/N
1,3,4,13
EXTCLKx
(Max INTCLK/4)
EFTx
SCI-A
SCI-M
1...256
Baud Rate
Generator
1/N
1/3
N = 2...(216-1)
TxINA/TxINB
(Max INTCLK/3)
1...64
MFTx
WDG
1...256
1/4
JBLPD
WDIN
N=4,6,8...258
P6.5
STD
1/N
Fscl ≤100 kHz
1...256
FAST
Fscl > 100 kHz
Fscl ≤ 400 kHz
1/N
N=6,9,12...387
1/4
2
I C
1...8
3-bit Prescaler
STIM
CPUCLK
1/16
P4.1
P6.0
CPU
CLOCK2/8
1/8
CK_128
INTCLK
EMBEDDED MEMORY
CKAF_SEL
XT_DIV16
0
1
1/4
0
1
1/16
CSU_CKSEL
RAM
MX(1:0)
DIV2
EPROM
FLASH
0
1
PLL
x
0
1
CLOCK1
1/ N
3 TM
1/2
CLOCK2
E
6/8/10/14
DX(2:0)
CK_AF
P7.0
RCCU
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9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.3 CLOCK MANAGEMENT
The various programmable features and operating modes of the CCU are handled by four registers:
– MODER (Mode Register)
This is a System Register (R235, Group E).
– CLK_FLAG (Clock Flag Register)
This is a Paged Register (R242, Page 55).
The input clock divide-by-two and the CPU clock
prescaler factors are handled by this register.
This register contains various status flags, as
well as control bits for clock selection.
– CLKCTL (Clock Control Register)
This is a Paged Register (R240, Page 55).
– PLLCONF (PLL Configuration Register)
This is a Paged Register (R246, Page 55).
The low power modes, the RCCU interrupts and
the interpretation of the HALT instruction are
handled by this register.
PLL management is programmed in this register.
Figure 61. Clock Control Unit Programming
DIV2
(MODER)
CSU_CKSEL
(CLK_FLAG)
CKAF_SEL
(CLKCTL)
XTSTOP
(CLK_FLAG)
CK_128
1/16
1/4
0
1
INTCLK
0
1
0
1
0
PLL
x
6/8/10/14
to
Peripherals
and
1/N
Crystal
oscillator
1
CLOCK2
1/2
CLOCK1
CK_AF
CPU Clock Prescaler
CK_AF
source
MX[1:0]
DX[2:0]
XT_DIV16
CKAF_ST
(PLLCONF)
(CLK_FLAG)
Wait for Interrupt and Low Power Modes:
LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode.
WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode.
XTSTOP (CLK_FLAG) automatically stops the crystal oscillator when the CK_AF clock is present and selected.
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9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont’d)
7.3.1 PLL Clock Multiplier Programming
The ST9 being a static machine, there is no lower
limit for INTCLK. However, some peripherals have
their own minimum internal clock frequency limit
below which the functionality is not guaranteed.
The CLOCK1 signal generated by the oscillator
drives a programmable divide-by-two circuit. If the
DIV2 control bit in MODER is set (Reset Condi-
tion), CLOCK2, is equal to CLOCK1 divided by
two; if DIV2 is reset, CLOCK2 is identical to
CLOCK1. Since the input clock to the Clock Multi-
plier circuit requires a 50% duty cycle for correct
PLL operation, the divide by two circuit should be
enabled when a crystal oscillator is used, or when
the external clock generator does not provide a
50% duty cycle. In practice, the divide-by-two is
virtually always used in order to ensure a 50% duty
cycle signal to the PLL multiplier circuit.
7.3.2 PLL Free Running Mode
The PLL is able to provide a 50-kHz clock, usable
to slow program execution. This mode is
controlled by the FREEN and DX[2:0] bits in the
PLLCONF register: when the PLL is off and the
FREEN bit is set to 1 (i.e. when the FREEN and
DX[2:0] bits are set to 1), the PLL provides this
clock. The selection of this clock is also managed
by the CSU_CKSEL bit but is not conditioned by
the LOCK bit. To avoid unpredictable behaviour of
the PLL clock, Free Running mode must be set
and reset by the user only when the PLL clock is
not the system clock, i.e. when the CSU_CKSEL
bit is reset.
When the PLL is active, it multiplies CLOCK2 by 6,
8, 10 or 14, depending on the status of the MX[0:1]
bits in PLLCONF. The multiplied clock is then di-
vided by a factor in the range 1 to 7, determined by
the status of the DX[0:2] bits; when these bits are
programmed to 111, the PLL is switched off.
In addition, when the PLL provides the internal
clock, if the clock signal disappears (for instance
due to a broken or disconnected resonator...), a
safety clock signal is automatically provided, al-
lowing the ST9 to perform some rescue opera-
tions.
Following a RESET phase, programming bits
DX0-2 to a value different from 111 will turn the
PLL on. After allowing a stabilization period for the
PLL, setting the CSU_CKSEL bit in the
CLK_FLAG Register selects the multiplier clock.
The RCCU contains a frequency comparator be-
tween CLOCK2 and the PLL clock output that ver-
ifies if the PLL reaches the programmed frequency
and has stabilized (locked status). When this con-
dition occurs, the LOCK bit in the CLK_FLAG reg-
ister is set to 1 by hardware and this value is main-
tained as long as the PLL is locked. The LOCK bit
is set back to 0 if for some reason (change of MX
bit value, stop and restart of PLL or CLOCK2,
etc.), the PLL loses the programmed frequency in
which it was locked.
Typ. Safety clock frequency = 800 kHz / Div,
where Div depends on the DX[0..2] bits of the PLL-
CONF register (R246, page55).
Table 26. Free Running Clock Frequency
DX2
0
DX1
0
DX0
0
DIV
2
CK (Typ.)
400 kHz
200 kHz
133 kHz
100 kHz
80 kHz
0
0
1
4
0
1
0
6
0
1
1
8
The PLL selection as system clock is further con-
ditioned by the status of the Voltage Regulator:
when it is not providing a stabilized supply voltage,
the PLL cannot be selected.
1
0
0
10
12
14
1
0
1
67 kHz
1
1
0
57 kHz
50 kHz
1
1
1
1
1
1
16
-
(CSU_CKSEL=0;
FREEN=1)
The maximum frequency allowed for INTCLK is
24 MHz. Care is required, when programming the
PLL multiplier and divider factors, not to exceed
the maximum permissible operating frequency for
INTCLK, according to supply voltage, as reported
in Electrical Characteristics section.
CLOCK2
(CSU_CKSEL=0;
FREEN=0)
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9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont’d)
7.3.3 CPU Clock Prescaling
7.3.4 Peripheral Clock
The system clock, INTCLK, which may be the out-
put of the PLL clock multiplier, CLOCK2, CLOCK2/
16 or CK_AF, drives a programmable prescaler
which generates the basic time base, CPUCLK,
for the instruction executer of the ST9 CPU core.
This allows the user to slow down program execu-
tion during non processor intensive routines, thus
reducing power dissipation.
The system clock, INTCLK, which may be the out-
put of the PLL clock multiplier, CLOCK2, CLOCK2/
16 or CK_AF, is also routed to all ST9 on-chip pe-
ripherals and acts as the central timebase for all
timing functions.
7.3.5 Low Power Modes
The user can select an automatic slowdown of
clock frequency during Wait for Interrupt opera-
tion, thus idling in low power mode while waiting
for an interrupt. In WFI operation the clock to the
CPU core is stopped, thus suspending program
execution, while the clock to the peripherals may
be programmed as described in the following par-
agraphs. Two examples of Low Power operation in
WFI are illustrated in Figure 63 and Figure 64.
The internal peripherals are not affected by the
CPUCLK prescaler and continue to operate at the
full INTCLK frequency. This is particularly useful
when little processing is being done and the pe-
ripherals are doing most of the work.
The prescaler divides the input clock by the value
programmed in the control bits PRS2,1,0 in the
MODER register. If the prescaler value is zero, no
prescaling takes place, thus CPUCLK has the
same period and phase as INTCLK. If the value is
different from 0, the prescaling is equal to the val-
ue plus one, ranging thus from two (PRS[2:0] = 1)
to eight (PRS[2:0] = 7).
Providing that low power operation during Wait for
Interrupt is enabled (by setting the LPOWFI bit in
the CLKCTL Register), as soon as the CPU exe-
cutes the WFI instruction, the PLL is turned off and
the system clock will be forced to CLOCK2 divided
by 16, or to the external low frequency clock,
CK_AF, if this has been selected by setting
WFI_CKSEL, and providing CKAF_ST is set, thus
indicating that the external clock is selected and
actually present on the CK_AF pin.
The clock generated is shown in Figure 62, and it
will be noted that the prescaling of the clock does
not preserve the 50% duty cycle, since the high
level is stretched to replace the missing cycles.
This is analogous to the introduction of wait cycles
for access to external memory. When External
Memory Wait or Bus Request events occur, CPU-
CLK is stretched at the high level for the whole pe-
riod required by the function
If the external clock source is used, the crystal os-
cillator may be stopped by setting the XTSTOP bit,
providing that the CK_AF clock is present and se-
lected, indicated by CKAF_ST being set. In this
case, the crystal oscillator will be stopped auto-
matically on entering WFI if the WFI_CKSEL bit
has been set.
Figure 62. CPU Clock Prescaling
n
It should be noted that selecting a non-existent
CK_AF clock source is impossible, since such a
selection requires that the auxiliary clock source
be actually present and selected. In no event can
a non-existent clock source be selected inadvert-
ently.
INTCLK
PRS VALUE
000
001
010
011
It is up to the user program to switch back to a fast-
er clock on the occurrence of an interrupt, taking
care to respect the oscillator and PLL stabilization
delays, as appropriate.
CPUCLK
100
It should be noted that any of the low power modes
may also be selected explicitly by the user pro-
gram even when not in Wait for Interrupt mode, by
setting the appropriate bits.
101
110
111
If the FREEN bit is set, the PLL is not stopped dur-
ing Low Power WFI, increasing power consump-
tion.
VA00260
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9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont’d)
7.3.6 Interrupt Generation
– when the system clock restarts after a hardware
stop (when the STOP MODE feature is availa-
ble on the specific device).
System clock selection modifies the CLKCTL and
CLK_FLAG registers.
– when the PLL loses the programmed frequency
in which it was locked, and when it re-locks
The clock control unit generates an external inter-
rupt request (INTD0) in the following conditions:
This interrupt can be masked by resetting the
INT_SEL bit in the CLKCTL register. Note that this
is the only case in the ST9 where an interrupt is
generated with a high to low transition.
– when CK_AF and CLOCK2/16 are selected or
deselected as system clock source,
Table 27. Summary of Operating Modes using main Crystal Controlled Oscillator
WFI_CK
SEL
MODE
PLL x BY 14
PLL x BY 10
PLL x BY 8
PLL x BY 6
SLOW 1
INTCLK CPUCLK DIV2 PRS0-2 CSU_CKSEL MX0-1 DX2-0 LPOWFI
XT_DIV16
XTAL/2
x (14/D)
INTCLK/
N
1
1
1
1
1
N-1
N-1
N-1
N-1
N-1
1
1
1
1
X
1 0
0 0
1 1
0 1
X
D-1
D-1
D-1
D-1
111
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
XTAL/2
x (10/D)
INTCLK/
N
XTAL/2
x (8/D)
INTCLK/
N
XTAL/2
x (6/D)
INTCLK/
N
INTCLK/
N
XTAL/2
INTCLK/
N
SLOW 2
XTAL/32
1
N-1
N-1
X
X
X
X
X
X
X
X
X
X
0
SLOW3
WFI
CK_AF CK_AF/N
X
X
If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.
LOW POW-
ER WFI 1
XTAL/32
STOP
1
X
X
X
X
1
0
X
LOW POW-
ER WFI 2
CK_AF
XTAL/2
STOP
1
1
X
0
X
0
X
X
1
0
1
0
X
1
RESET
INTCLK
00
111
EXAMPLE
XTAL=4.4
MHz
2.2*10/2
= 11MHz
11MHz
1
0
1
00
001
X
1
130/426
9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 63. Example of Low Power mode programming in WFI using CK_AF external clock
INTCLK FREQUENCY
PROGRAM FLOW
F
= 4 MHz
Xtal
Begin
Reset State
PLL multiply factor
set to 10
MX[1:0] ← 00
DX[2:0] ← 000
WAIT
Divider factor set
to 1, and PLL turned ON
2 MHz
Wait for the PLL to lock
T *
1
CSU_CKSEL ←
system clock source
PLL is
1
CK_AF clock selected
in WFI state
WFI_CKSEL ← 1
XTSTOP ← 1
Preselect Xtal stopped
when CK_AF selected
Low Power Mode enabled
in WFI state
LPOWFI ← 1
20 MHz
User’s Program
Wait For Interrupt
activated
CK_AF selected and Xtal stopped
WFI instruction
WFI status
automatically
No code is executed until
an interrupt is requested
Interrupt
Interrupt serviced
while CK_AF is
the System Clock
and the Xtal restarts
Interrupt Routine
XTSTOP ← 0
F
CK_AF
Wait for the Xtal to stabilise
WAIT
T **
2
The System Clock
switches to Xtal
CKAF_SEL ← 0
Wait for the PLL to lock
WAIT
2 MHz
CSU_CKSEL ← 1
PLL is
System Clock source
User’s Program
Execution of user program
resumes at full speed
20 MHz
* T = PLL lock-in time
1
** T = Quartz oscillator start-up time
2
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9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 64. Example of Low Power mode programming in WFI using CLOCK2/16
INTCLK FREQUENCY
Xtal
PROGRAM FLOW
F
= 4 MHz
Begin
Reset State
PLL multiply factor
set to 6
MX[1:0] ← 01
DX[2:0] ← 000
Divider factor set
to 1, and PLL turned ON
2 MHz
Wait for the PLL to lock
WAIT
T *
1
CSU_CKSEL ←
system clock source
PLL is
1
Low Power Mode enabled
in WFI state
LPOWFI ← 1
User’s Program
12 MHz
Wait For Interrupt
activated
CLOCK2/16 selected and PLL
automatically
WFI instruction
stopped
No code is executed until
an interrupt is requested
WFI status
Interrupt
125 KHz
Interrupt Routine
Interrupt serviced
PLL switched on
CLOCK2 selected
WAIT
Wait for the PLL to lock
2 MHz
T *
1
system clock source
PLL is
CSU_CKSEL ← 1
User’s Program
Execution of user program
resumes at full speed
12 MHz
* T = PLL lock-in time
1
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9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.4 CLOCK CONTROL REGISTERS
MODE REGISTER (MODER)
R235 - Read/Write
Bit 2 = CKAF_SEL: Alternate Function Clock Se-
lect.
0: CK_AF clock not selected
1: Select CK_AF clock
System Register
Reset Value: 1110 0000 (E0h)
7
0
-
Note: To check if the selection has actually oc-
curred, check that CKAF_ST is set. If no clock is
present on the CK_AF pin, the selection will not
occur.
-
-
DIV2 PRS2 PRS1 PRS0
-
*Note: This register contains bits which relate to
other functions; these are described in the chapter
dealing with Device Architecture. Only those bits
relating to Clock functions are described here.
Bit 1 = WFI_CKSEL: WFI Clock Select.
This bit selects the clock used in Low power WFI
mode if LPOWFI = 1.
0: INTCLK during WFI is CLOCK2/16
1: INTCLK during WFI is CK_AF, providing it is
present. In effect this bit sets CKAF_SEL in WFI
mode
Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2.
This bit controls the divide by 2 circuit which oper-
ates on CLOCK1.
0: No division of CLOCK1
1: CLOCK1 is internally divided by 2
WARNING: When the CK_AF is selected as Low
Power WFI clock but the crystal is not turned off
(R242.4 = 0), after exiting from the WFI, CK_AF
will be still selected as system clock. In this case,
reset the R240.2 bit to switch back to the crystal
oscillator clock.
Bits 4:2 = PRS[2:0]: Clock Prescaling.
These bits define the prescaler value used to pres-
cale CPUCLK from INTCLK. When these three
bits are reset, the CPUCLK is not prescaled, and is
equal to INTCLK; in all other cases, the internal
clock is prescaled by the value of these three bits
plus one.
Bit 0 = LPOWFI: Low Power mode during Wait For
Interrupt.
0: Low Power mode during WFI disabled. When
WFI is executed, the CPUCLK is stopped and
INTCLK is unchanged
1: The ST9 enters Low Power mode when the WFI
instruction is executed. The clock during this
state depends on WFI_CKSEL
CLOCK CONTROL REGISTER (CLKCTL)
R240 - Read/Write
Register Page: 55
Reset Value: 0000 0000 (00h)
7
0
VOLTAGE REGULATOR CONTROL REGISTER
(VRCTR)
INT_S
EL
SRE- CKAF_S WFI_CKS LPOW
-
-
-
R241 - Read/Write
SEN
EL
EL
FI
Register Page: 55
Bit 7 = INT_SEL: Interrupt Selection.
0: The external interrupt channel input signal is se-
lected (Reset state)
1: Select the internal RCCU interrupt as the source
of the interrupt request
Reset Value: 0000 0x00 (0xh)
7
0
0
VROFF
_REG
0
0
0
0
-
0
Bit 7-4 = Reserved, must be kept at 0.
Bits 6:4 = Reserved for test purposes
Must be kept reset for normal operation.
Bit 3 = VROFF_REG: Voltage Regulator OFF
state. This bit is set and cleared by software.
0: Main Voltage Regulator (VR) on
1: Main VR off. In this state the Main Regulator has
zero power consumption, and the PLL is auto-
matically deselected.
Bit 3 = SRESEN: Software Reset Enable.
0: The HALT instruction turns off the quartz, the
PLL and the CCU
This bit must be set for the RTC mode.
1: A Reset is generated when HALT is executed
Bit 2 = Reserved.
Bit 1-0 = Reserved, must be kept at 0.
133/426
9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
CLOCK FLAG REGISTER (CLK_FLAG)
R242 -Read/Write
Register Page: 55
gram, or as a result of WFI, if WFI_CKSEL has
previously been set to select the CK_AF clock
during WFI.
Reset Value: 0110 1000 after a Flash LVD Reset
Reset Value: 0100 1000 after a Watchdog Reset
Reset Value: 0010 1000 after a Software Reset
Reset Value: 0000 1000 after an External Reset
Note: When the program writes ‘1’ to the XTSTOP
bit, it will still be read as 0 as long as the CKAF_ST
bit is reset (CKAF_ST=0). In this case, take care of
this behaviour, because a subsequent AND with
‘1’ or a OR with ‘0’ to the XSTOP bit before setting
the CKAF_ST bit will prevent the oscillator from
being stopped.
7
0
CSU_
CK-
SEL
EX_
STP
WDG
RES
SOFT
RES
XT-
XT_ CKAF_ LO
ST CK
STOP DIV16
WARNING: If you select the CK_AF as system
clock and turn off the oscillator (bits R240.2 and
R242.4 at 1), in order to switch back to the crystal
clock by resetting the R240.2 bit, you must first
wait for the oscillator to restart correctly.
Bit 3 = XT_DIV16: CLOCK/16 Selection.
This bit is set and cleared by software. An interrupt
is generated when the bit is toggled.
0: CLOCK2/16 is selected and the PLL is off
1: The input is CLOCK2 (or the PLL output de-
pending on the value of CSU_CKSEL)
Bit 7 = EX_STP: External Stop flag.
This bit is set by hardware/software and cleared by
software.
Bit 2 = CKAF_ST: (Read Only)
0: No External Stop condition occurred
1: External Stop condition occurred
If set, indicates that the alternate function clock
has been selected. If no clock signal is present on
the CK_AF pin, the selection will not occur. If re-
set, the PLL clock, CLOCK2 or CLOCK2/16 is se-
lected (depending on bit 0).
Note: This bit is set after the end of the instruction
being executed when the microcontroller enters
stop mode. So, if this instruction is a reading of the
CLK_FLAG register, this bit will still be read as 0.
Next reading will give 1 as result.
Bit 1= LOCK: PLL locked-in
This bit is read only.
0: The PLL is turned off or not locked and cannot
be selected as system clock source.
1: The PLL is locked
Bit 6 = WDGRES: Watchdog reset flag.
This bit is read only.
0: No Watchdog reset occurred
1: Watchdog reset occurred
Bit 0 = CSU_CKSEL: CSU Clock Select.
This bit is set and cleared by software. It is also
cleared by hardware when:
– bits DX[2:0] (PLLCONF) are set to 111;
– the quartz is stopped (by hardware or software);
– WFI is executed while the LPOWFI bit is set;
– the XT_DIV16 bit (CLK_FLAG) is forced to ’0’;
– STOP mode is entered.
Bit 5 = SOFTRES: Software Reset Flag.
This bit is read only.
0: No software reset occurred
1: Software reset occurred (HALT instruction)
If both SOFTRES and WDGRES are set to 1, the
last reset event generator was a Flash LVD reset.
Table 28. Reset Flags
This prevents the PLL, when not yet locked, from
providing an irregular clock. Furthermore, a ‘0’
stored in this bit speeds up the PLL’s locking.
WDGRES
SOFTRES
0
0
1
1
0
1
0
1
External Reset
Software Reset
Watchdog Reset
LVD Reset
0: CLOCK2 provides the system clock
1: The PLL Multiplier provides the system clock if
the LOCK bit is set to 1
If the FREEN bit is set, this bit selects this clock in-
dependently by the LOCK bit.
Bit 4 = XTSTOP: External Stop Enable.
0: External stop disabled
1: The Xtal oscillator will be stopped as soon as
the CK_AF clock is present and selected,
whether this is done explicitly by the user pro-
NOTE: Setting the CKAF_SEL bit overrides any
other clock selection. Resetting the XT_DIV16 bit
overrides the CSU_CKSEL selection (see Figure
61).
134/426
9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
Table 29. PLL Multiplication Factors
MX1
MX0
CLOCK2 x
PLL CONFIGURATION REGISTER (PLLCONF)
R246 - Read/Write
1
0
1
0
0
0
1
1
14
10
8
Register Page: 55
Reset Value: 0x00 x111
7
0
6
FREEN
0
MX1
MX0
0
DX2 DX1 DX0
Table 30. PLL Divider Factors
Bit 7 = FREEN: PLL Free Running Mode Enable
0: PLL Free Running Mode disabled
DX2
0
DX1
0
DX0
0
CK
PLL CLOCK/1
PLL CLOCK/2
PLL CLOCK/3
PLL CLOCK/4
PLL CLOCK/5
PLL CLOCK/6
PLL CLOCK/7
1: PLL Free Running Mode enabled
0
0
1
0
1
0
When this bit is set, even if the DX[2:0] bits are all
set to 1, the PLL is not stopped but provides a slow
frequency back-up clock, selectable by the
CSU_CKSEL bit of the CLK_FLAG register (with-
out needing to have the LOCK bit equal to ‘1’).
0
1
1
1
0
0
1
0
1
1
1
0
CLOCK2
(PLL OFF, Reset State)
1
1
1
Bits 5:4 = MX[1:0]: PLL Multiplication Factor.
Refer to Table 29 for multiplier settings.
WARNING: After these bits are modified, take
care that the PLL lock-in time has elapsed before
setting the CSU_CKSEL bit in the CLK_FLAG reg-
ister.
Bits 2:0 = DX[2:0]: PLL output clock divider factor.
Refer to Table 30 for divider settings.
135/426
9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 65. RCCU General Timing
User program execution
PLL switched on by user
Boot ROM execution
PLL selected by user
20µs
< 4µs
Reset phase
External
Reset
Filtered
External
Reset
CLOCK2
PLL Multiplier
clock
Internal
Reset
INTCLK
t
BRE
20479 x CLOCK1
PLL Lock-in
time
Exit from RESET
VR02113B
136/426
9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.5 CRYSTAL OSCILLATOR
The on-chip components for the crystal oscillator
are an inverting circuit, polarised at the trip point.
The inverter is built around an n-channel transis-
tor, loaded with a current source and polarised
through a feedback resistor.
Table 31. Maximum R values
S
C =C
33pF
22pF
1
2
Freq.
5 MHz
4 MHz
3 MHz
80
130
200
370
120
220
The current source is tailored to obtain a pseudo
sinusoidal signal at OSCOUT and OSCIN, reduc-
ing the electromagnetic emission. The inverter
stage is followed by a matching inverter, which is
followed in turn by a schmitt-triggered buffer.
Legend:
C , C : Maximum Total Capacitances on pins OSCIN and
1
2
OSCOUT (the value includes the external capacitance
tied to the pin plus the parasitic capacitance of the board
and of the device)
In HALT mode, set by means of the HALTinstruc-
tion, in STOP mode, and under control of the XT-
STOP bit, the oscillator is disabled. The current
sources are switched off, reducing the power dis-
sipation. The internal clock, CLOCK1, is forced to
a high level.
Note: The tables are relative to the fundamental quartz
crystal only (not ceramic resonator).
Figure 67. Internal Oscillator Schematic
To exit the HALTcondition and restart the oscilla-
tor, an external RESET pulse is required, having a
V
DD
a minimum duration of T
(see Figure 70 and
STUP
Section 11 ELECTRICAL CHARACTERISTICS).
I
LOAD
It should be noted that, if the Watchdog function is
enabled, a HALTinstruction will not disable the os-
cillator. This to avoid stopping the Watchdog if a
HALTcode is executed in error. When this occurs,
the CPU will be reset when the Watchdog times
out or when an external reset is applied.
CLOCK1
R
POL
OSCIN
Figure 66. Crystal Oscillator
OSCOUT
CRYSTAL CLOCK
ST9
Figure 68. External Clock
OSCOUT
OSCIN
EXTERNAL CLOCK
*
Rd
OSCIN
C
C
1
2
ST9
INPUT
CLOCK
OSCOUT
*Rd can be inserted to reduce the drive level,
when using low drive crystals.
VR02116B
137/426
9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
CERAMIC RESONATORS
Murata Electronics CERALOCK resonators have been tested with the ST92F150 at 3, 3.68, 4 and 5 MHz.
These recommended resonators have built-in capacitors (see Table 32).
The test circuit is shown in Figure 69.
Figure 69. Test Circuit
ST92F150
V
DD
V
OSCIN
OSCOUT
SS
Rd
CERALOCK
C1 C2
Table 32 shows the recommended conditions at different frequencies.
Table 32. Obtained Results
Freq.
Parts Number
C1 (pF)
C2 (pF)
Rd (Ohm)
(MHz)
CSTCR5M00G55A-R0
CSTCC5M00G56A-R0
CSTCR4M00G55A-R0
CSTCC4M00G56A-R0
CSTCC3M00G56A-R0
CSTCC3M68G56A-R0
39
47
39
47
47
47
39
47
39
47
47
47
0
0
0
0
0
0
5
4
3
3.68
Advantages of using ceramic resonators:
For tight frequency tolerance applications, please
contact the nearest Murata office for more de-
tailled PCB evaluation regarding layout.
CSTCR and CSTCC types have built-in loading
capacitors.
Smallest loading capacitor resonators are recom-
mended for standard applications.
Note 1:
Attention must be paid to leakage currents around
Highest loading capacitor resonators are recom-
mended for automotive applications with CAN and
tight frequency tolerance.
the OSCIN pin. Leakage paths from V could al-
DD
ter the DC polarization of the inverter stage and in-
troduce a mismatch with the second stage, and
possibly stop the clock signal. It is recommended
to surround the oscillator components by a ground
ring on the printed circuit board and if necessary to
apply a coating film to avoid humidity problems.
Test conditions:
The evaluation conditions are 4.5 to 5.5 V for the
supply voltage and -40° to 105° C for the tempera-
ture range.
Caution:
Note 2:
These circuit conditions are for design reference
Attention must be paid to the capacitive loading of
OSCOUT. OSCOUT must not be used to drive ex-
ternal circuits.
only.
Recommended C1, C2 value depends on the cir-
cuit board used.
138/426
9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
7.6 RESET/STOP MANAGER
The Reset/Stop Manager resets the MCU when
one of the three following events occurs:
SOFTRES or the WDGRES bit or both; a hard-
ware initiated reset will leave both these bits reset.
– A Hardware reset, initiated by a low level on the
Reset pin.
The hardware reset overrides all other conditions
and forces the ST9 to the reset state. During Re-
set, the internal registers are set to their reset val-
ues (when these reset values are defined, other-
wise the register content will remain unchanged),
and the I/O pins are set to Bidirectional Weak-Pull-
Up or High impedance input. See Section 7.3.
– A Software reset, initiated by a HALT instruction
(when enabled with the SRESEN bit of the
CLKCTL register).
– A Watchdog end of count condition.
The event which caused the last Reset is flagged
in the CLK_FLAG register, by setting either the
Reset is asynchronous: as soon as the reset pin is
driven low, a Reset cycle is initiated.
Figure 70. Oscillator Start-up Sequence and Reset Timing
V
V
MAX
MIN
DD
DD
OSCIN
OSCOUT
T
STUP
INTCLK
RESET
PIN
VR02085A
139/426
9
ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
RESET/STOP MANAGER (Cont’d)
The on-chip Timer/Watchdog generates a reset
condition if the Watchdog mode is enabled
(WCR.WDGEN cleared, R252 page 0), and if the
programmed period elapses without the specific
code (AAh, 55h) written to the appropriate register.
The input pin RESET is not driven low by the on-
chip reset generated by the Timer/Watchdog.
of up to 4µs will elapse before the RCCU detects
this rising front. From this event on, a defined
number of CLOCK1 cycles (refer to t ) is
counted before exiting the Reset state (+ one pos-
sible CLOCK1 period depending on the delay be-
tween the positive edge the RCCU detects and the
first rising edge of CLOCK1).
If the ST9 is a ROMLESS version, without on-chip
program memory, the memory interface ports are
set to external memory mode (i.e Alternate Func-
tion) and the memory accesses are made to exter-
nal Program memory with wait cycles insertion.
If the Voltage Regulator is present in the device,
please ensure the reset pin is released only when
the internal voltage supply is stabilized at 3.3V.
RSPH
When the Reset pin goes high again, 20479 oscil-
lator clock cycles (CLOCK1) are counted before ex-
iting the Reset state (+ one possible CLOCK1 pe-
riod, depending on the delay between the rising
edge of the Reset pin and the first rising edge of
CLOCK1). Subsequently a short Boot routine is ex-
ecuted from the device internal Boot memory, and
control then passes to the user program.
The Boot routine sets the device characteristics
and loads the correct values in the Memory Man-
agement Unit’s pointer registers, so that these
point to the physical memory areas as mapped in
the specific device. The precise duration of this
short Boot routine varies from device to device,
depending on the Boot memory contents.
Figure 71. Recommended Signal to be Applied
on Reset Pin
V
RESETN
V
DD
At the end of the Boot routine the Program Coun-
ter will be set to the location specified in the Reset
Vector located in the lowest two bytes of memory.
V
IHRS
V
ILRS
7.6.1 Reset Pin Timing
To improve the noise immunity of the device, the
Reset pin has a Schmitt trigger input circuit with
hysteresis. In addition, a filter will prevent an un-
wanted reset in case of a single glitch of less than
50 ns on the Reset pin. The device is certain to re-
set if a negative pulse of more than 20µs is ap-
plied. When the reset pin goes high again, a delay
20µs
Minimum
Figure 72. Reset Pin Input Structure
PIN
SCHMITT TRIGGER and LOW
PASS FILTER
TO GENERATE RESET SIGNAL
E
SD PROTECTION
CIRCUITRY
140/426
9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
8 EXTERNAL MEMORY INTERFACE (EXTMI)
8.1 INTRODUCTION
The ST9 External Memory Interface uses two reg-
isters (EMR1 and EMR2) to configure external
memory accesses. Some interface signals are
also affected by WCR - R252 Page 0.
During phase T2, two forms of behavior are possi-
ble. If the memory access is a Read cycle, Port 0
pins are released in high-impedance until the next
T1 phase and the data signals are sampled by the
ST9 on the rising edge of DS. If the memory ac-
cess is a Write cycle, on the falling edge of DS,
Port 0 outputs data to be written in the external
memory. Those data signals are valid on the rising
edge of DS and are maintained stable until the
next address is output.
If the two registers EMR1 and EMR2 are set to the
proper values, the ST9+ memory access cycle is
similar to that of the original ST9, with the only ex-
ception that it is composed of just two system
clock phases, named T1 and T2.
During phase T1, the memory address is output on
the AS falling edge and is valid on the rising edge
of AS. Port1 and Port 9 maintain the address sta-
ble until the following T1 phase.
Note that DS is pulled low at the beginning of
phase T2 only during an external memory access.
Figure 73. Page 21 Registers
Page 21
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
Relocation of P0-3 and DPR0-3 Registers
SSPL
SSPL
SSPH
USPL
USPH
MODER
PPR
SSPH
USPL
USPH
MODER
PPR
RP1
RP0
FLAGR
CICR
P5
DMASR
ISR
RP1
DMASR
ISR
DMASR
ISR
MMU
RP0
FLAGR
CICR
P5
EMR2
EMR1
CSR
DPR3
DPR2
DPR1
DPR0
EMR2
EMR1
CSR
P3
P2
P1
P0
P4
P3
P2
P1
P0
P4
EMR2
EMR1
CSR
DPR3
DPR2
DPR1
DPR0
EXT.MEM
DPR3
DPR2
DPR1
DPR0
Bit DPRREM=0
Bit DPRREM=1
MMU
141/426
9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
8.2 EXTERNAL MEMORY SIGNALS
The access to external memory is made using the
AS, DS, RW, Port 0, Port1, Port9, DS2 and WAIT
signals described below.
EMR1 or WCR register. Refer to the Register de-
scription.
8.2.3 RW: Read/Write
Refer to Figure 76.
RW (Output, Active low, Tristate) identifies the
type of memory cycle: RW=”1” identifies a memory
read cycle, RW=”0” identifies a memory write cy-
cle. It is defined at the beginning of each memory
cycle and it remains stable until the following
memory cycle.
8.2.1 AS: Address Strobe
AS (Output, Active low, Tristate) is active during
the System Clock high-level phase of each T1
memory cycle: an AS rising edge indicates that
Memory Address and Read/Write Memory control
signals are valid.
RW is released in high-impedance during bus ac-
knowledge cycle or under processor control by
setting the HIMP bit (MODER).
AS is released in high-impedance during the bus
acknowledge cycle or under the processor control
by setting the HIMP bit (MODER.0, R235).
Under Reset status, RW is held high with an inter-
nal weak pull-up.
Under Reset, AS is held high with an internal weak
pull-up.
The behavior of this signal is affected by the MC
and ETO bits in the EMR1 register. Refer to the
Register description.
The behavior of this signal is also affected by the
MC, ASAF, ETO, LAS[1:0] and UAS[1:0] bits in the
EMR1 or EMR2 registers. Refer to the Register
description.
8.2.4 DS2: Data Strobe 2
This additional Data Strobe pin (Alternate Function
Output, Active low, Tristate) allows two different
external memories to be connected to the ST9, the
upper memory block (A21=1 typically RAM) and
the lower memory block (A21=0 typically ROM)
without any external logic. The selection between
the upper and lower memory blocks depends on
the A21 address pin value.
8.2.2 DS: Data Strobe
DS (Output, Active low, Tristate) is active during the
internal clock high-level phase of each T2 memory
cycle. During an external memory read cycle, the
data on Port 0 must be valid before the DS rising
edge. During an external memory write cycle, the
data on Port 0 are output on the falling edge of DS
and they are valid on the rising edge of DS. When
the internal memory is accessed DS is kept high
during the whole memory cycle.
The upper memory block is controlled by the DS
pin while the lower memory block is controlled by
the DS2 pin. When the internal memory is ad-
dressed, DS2 is kept high during the whole mem-
ory cycle. DS2 is enabled via software as the Alter-
nate Function output of the associated I/O port bit.
DS is released in high-impedance during bus ac-
knowledge cycle or under processor control by set-
ting the HIMP bit (MODER.0, R235).
DS2 is released in high-impedance during bus ac-
knowledge cycle or under processor control by
setting the HIMP bit (MODER.0, r235).
Under Reset status, DS is held high with an internal
weak pull-up.
The behavior of this signal is also affected by the
LDS[2:0], UDS[2:0], DS2EN and MC bits in the
The behavior of this signal is also affected by the
DS2EN bit in the EMR1 register. Refer to the Reg-
ister description.
142/426
9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
8.2.5 PORT 0
8.2.7 PORT 9 [7:2]
If Port 0 is used as a bit programmable parallel I/O
port, it has the same features as a regular port.
When set as an Alternate Function, it is used as
the External Memory interface: it outputs the mul-
tiplexed Address (8 LSB: A[7:0]) / Data bus D[7:0].
If Port 9 is available and used as a bit programma-
ble I/O port, it has the same features as a regular
port. If the MMU is available on the device and
Port 9 is set as an Alternate Function, Port 9[7:2] is
used as the external memory interface to provide
the 6 MSB of the address (A[21:16]).
8.2.6 PORT 1
Note: For the ST92F250 device, since A[18:17]
share the same pins as SDA1 and SCL1 of I²C_1,
these address bits are not available when the
I²C_1 is in use (when I2CCR.PE bit is set).
If Port 1 is used as a bit programmable parallel I/O
port, it has the same features as a regular port.
When set as an Alternate Function, it is used as
the external memory interface to provide the ad-
dress bits A[15:8].
Figure 74. Application Example (MC=0)
RAM
2 Mbytes
RW
DS
W
G
D[7:0]
P0
Q[7:0]
A[7:0]
ST9
D[7:0]
A[20:0]
E
Q[7:0]
AS
LE
OE
LATCH
ROM
2 Mbytes
A[20:8]
A21
DS
Q[7:0]
P9[6:2], P1
P9.7
A[20:0]
E
Figure 75. Application Example (MC=1)
RAM
2 Mbytes
WEN
OEN
W
G
D[7:0]
P0
Q[7:0]
A[7:0]
ST9
D[7:0]
A[20:0]
E
Q[7:0]
ALE
LE
OE
LATCH
ROM
2 Mbytes
A[20:8]
DS
Q[7:0]
P9[6:2], P1
P9.7
A21
A[20:0]
E
143/426
9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
Figure 76. External memory Read/Write with a programmable wait
NO WAIT CYCLE
1 DS WAIT CYCLE
T2
1 AS WAIT CYCLE
T1
T1
T2
TWA
TWD
SYSTEM
CLOCK
AS STRETCH
DS STRETCH
AS (MC=0)
TAVQV
ALE (MC=1)
(AS pin)
P1, P9
ADDRESS
ADDRESS
DS (MC=0)
DATA IN
ADDRESS
DATA IN
ADDRESS
P0
RW (MC=0)
OEN (MC=1)
(DS pin)
WEN (MC=1)
(RW pin)
DATA
P0
ADDRESS
DATA OUT
ADDRESS
TAVWH
RW (MC=0)
TAVWL
OEN (MC=1)
(DS pin)
WEN (MC=1)
(RW pin)
144/426
9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
Figure 77. Effects of DS2EN on the behavior of DS and DS2
n
NO WAIT CYCLE
1 DS WAIT CYCLE
T2
T1
T2
T1
SYSTEM
CLOCK
DS STRETCH
AS (MC=0)
ALE (MC=1)
DS2EN=0 OR (DS2EN=1 AND UPPER MEMORY ADDRESSED):
DS
(MC=0)
DS2
(MC=0)
OEN
(MC=1, READ)
OEN
(MC=1, WRITE)
OEN2
(MC=1)
DS2EN=1 AND LOWER MEMORY ADDRESSED:
DS
(MC=0)
DS2
(MC=0)
OEN
(MC=1)
OEN2
(MC=1, READ)
OEN2
(MC=1, WRITE)
145/426
9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
8.2.8 WAIT: External Memory Wait
cle, WAIT is sampled again to continue or finish
the memory cycle stretching. Note that if WAIT is
sampled active during phase T1 then AS is
stretched, while if WAIT is sampled active during
phase T2 then DS is stretched. WAIT is enabled
via software as the Alternate Function input of the
associated I/O port bit (refer to specific ST9 ver-
sion to identify the specific port and pin). Refer to
Figure 78.
WAIT (Alternate Function Input, Active low) indi-
cates to the ST9 that the external memory requires
more time to complete the memory access cycle. If
bit EWEN (EIVR) is set, the WAIT signal is sam-
pled with the rising edge of the processor internal
clock during phase T1 or T2 of every memory cy-
cle. If the signal was sampled active, one more in-
ternal clock cycle is added to the memory cycle.
On the rising edge of the added internal clock cy-
Figure 78. External memory Read/Write sequence with external wait request (WAIT pin)
T2
T1
T2
T1
T2
T1
WAIT
SYSTEM
CLOCK
ADDRESS
ADDRESS
ADDRESS
P1, P9
AS (MC=0)
ALE (MC=1)
DS (MC=0)
ADD.
ADDRESS
ADD.
D.IN
D.IN
P0
D.IN
RW (MC=0)
OEN (MC=1)
WEN (MC=1)
D.OUT
ADD.
DATA OUT
ADD.
ADDRESS
P0
D.OUT
RW (MC=0)
OEN (MC=1)
WEN (MC=1)
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9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
8.3 REGISTER DESCRIPTION
EXTERNAL MEMORY REGISTER 1 (EMR1)
R245 - Read/Write
If the upper memory block is addressed, DS2 is
forced to “1” during the whole memory cycle.
Refer to Figure 77
Register Page: 21
Reset value: 1000 0000 (80h)
Bit 4 = ASAF: Address Strobe as Alternate Func-
tion.
7
0
Depending on the device, AS can be either a ded-
icated pin or a port Alternate Function. This bit is
used only in the second case.
X
MC
DS2EN
ASAF
0
ETO
BSZ
X
0: AS Alternate function disabled.
1: AS Alternate Function enabled.
Bit 7 = Reserved.
Bit 6 = MC: Mode Control.
Bit 3 = Reserved, must be kept cleared.
0: AS, DS and RW pins have the standard ST9 for-
mat.
Bit 2 = ETO: External toggle.
1: AS pin becomes ALE, Address Load Enable.
This signal indicates to the external address
latch that a valid address is put on AD[7:0].
When ALE is high, the multiplexed address/data
bus AD[7:0] carries the LSBs of the memory ad-
dress, which must be latched on the falling edge
of this signal.
DS becomes OEN, Output ENable: When this
signal is low, the external memory should put
the data on the multiplexed address/data bus
AD[7:0]. The data is sampled by the microcon-
troller on the rising edge of the OEN signal.
RW pin becomes WEN, Write ENable: when this
signal is low, the multiplexed address/data bus
AD[7:0] carries the data to be written in the ex-
ternal memory. The external memory should
sample the data on the rising edge of the WEN
signal.
0: The external memory interface pins (AS, DS,
DS2, RW, Port0, Port1, Port9) toggle only if an
access to external memory is performed.
1: When the internal memory protection is dis-
abled, the above pins (except DS which never
toggles during internal memory accesses) tog-
gle during both internal and external memory
accesses.
Bit 1 = BSZ: Bus size.
0: All outputs use the standard low-noise output
buffers.
1: P4[7:6], P6[5:4] use high-drive output buffers
Bit 0 = Reserved.
Caution: External memory must be correctly ad-
dressed before and after a write operation on the
EMR1 register. For example, if code is fetched
from external memory using the standard ST9 ex-
ternal memory interface configuration (MC=0),
setting the MC bit will cause the device to behave
unpredictably.
Bit 5 = DS2EN: Data Strobe 2 enable.
0: The DS pin is active for any external memory
access (lower and upper memory block).
The DS2 pin remains high.
1: If the lower memory block is addressed, the
DS2 pin outputs the standard DS signal, while
the DS pin stays high during the whole memory
cycle.
147/426
9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d)
EXTERNAL MEMORY REGISTER 2 (EMR2)
R246 - Read/Write
the contents of ISR. In this case, iret will also re-
store CSR from the stack. This approach allows
interrupt service routines to access the entire
4Mbytes of address space; the drawback is that
the interrupt response time is slightly increased,
because of the need to also save CSR on the
stack. Full compatibility with the original ST9 is
lost in this case, because the interrupt stack
frame is different; this difference, however,
should not affect the vast majority of programs.
Register Page: 21
Reset value: 0001 1111 (1Fh)
7
0
-
ENCSR DPRREM MEMSEL LAS1 LAS0 UAS1 UAS0
Bit 7 = Reserved.
Bit 5 = DPRREM: Data Page Registers remapping
0: The locations of the four MMU (Memory Man-
agement Unit) Data Page Registers (DPR0,
DPR1, DPR2 and DPR3) are in page 21.
1: The four MMU Data Page Registers are
swapped with that of the Data Registers of ports
0-3.
Bit 6 = ENCSR: Enable Code Segment Register.
This bit affects the ST9 CPU behavior whenever
an interrupt request is issued.
0: The CPU works in original ST9 compatibility
mode concerning stack frame during interrupts.
For the duration of the interrupt service routine,
ISR is used instead of CSR, and the interrupt
stack frame is identical to that of the original
ST9: only the PC and Flags are pushed. This
avoids saving the CSR on the stack in the event
of an interrupt, thus ensuring a faster interrupt
response time. The drawback is that it is not
possible for an interrupt service routine to per-
form inter-segment calls or jumps: these instruc-
tions would update the CSR, which, in this case,
is not used (ISR is used instead). The code seg-
ment size for all interrupt service routines is thus
limited to 64K bytes.
Refer to Figure 73
Bit 4 = MEMSEL: Memory Selection.
Warning: Must be kept at 1.
Bit 3:2 = LAS[1:0]: Lower memory address strobe
stretch.
These two bits contain the number of wait cycles
(from 0 to 3) to add to the System Clock to stretch
AS during external lower memory block accesses
(A21=”0”). The reset value is 3.
1: If ENCSR is set, ISR is only used to point to the
interrupt vector table and to initialize the CSR at
the beginning of the interrupt service routine: the
old CSR is pushed onto the stack together with
the PC and flags, and CSR is then loaded with
148/426
9
ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d)
Bit 1:0 = UAS[1:0]: Upper memory address strobe
stretch.
These two bits contain the number of wait cycles
(from 0 to 3) to add to the System Clock to stretch
AS during external upper memory block accesses
(A21=1). The reset value is 3.
memory block accesses. UDS = 0 adds no addi-
tional wait cycles. UDS = 7 adds the maximum 7
INTCLK cycles (reset condition).
Bit 2:0 = LDS[2:0]: Lower memory data strobe
stretch.
These bits contain the number of INTCLK cycles
to be added automatically to DS for external lower
memory block accesses. LDS = 0 adds no addi-
tional wait cycles, LDS = 7 adds the maximum 7
INTCLK cycles (reset condition).
Caution: The EMR2 register cannot be written
during an interrupt service routine.
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Note 1: The number of clock cycles added refers
Register Page: 0
to INTCLK and NOT to CPUCLK.
Reset Value: 0111 1111 (7Fh)
Note 2: The distinction between the Upper memo-
ry block and the Lower memory block allows differ-
ent wait cycles between the first 2 Mbytes and the
second 2 Mbytes, and allows 2 different data
strobe signals to be used to access 2 different
memories.
7
0
0
WDGEN UDS2 UDS1 UDS0 LDS2 LDS1 LDS0
Bit 7 = Reserved, forced by hardware to 0.
Typically, the RAM will be located above address
0x200000 and the ROM below address
0x1FFFFF, with different access times (see Figure
74).
Bit 6 = WDGEN: Watchdog Enable.
For a description of this bit, refer to the Timer/
Watchdog chapter.
Caution: The reset value of the Wait Control Reg-
ister gives the maximum number of Wait cycles for
external memory. To get optimum performance
from the ST9, the user should write the UDS[2:0]
and LDS[2:0] bits to 0, if the external addressed
memories are fast enough.
Caution: Clearing this bit has the effect of setting
the Timer/Watchdog to Watchdog mode. Unless
this is desired, it must be set to “1”.
Bit 5:3 = UDS[2:0]: Upper memory data strobe
stretch.
These bits contain the number of INTCLK cycles
to be added automatically to DS for external upper
149/426
9
ST92F124/F150/F250 - I/O PORTS
9 I/O PORTS
9.1 INTRODUCTION
9.2 SPECIFIC PORT CONFIGURATIONS
ST9 devices feature flexible individually program-
mable multifunctional input/output lines. Refer to
the Pin Description Chapter for specific pin alloca-
tions. These lines, which are logically grouped as
8-bit ports, can be individually programmed to pro-
vide digital input/output and analog input, or to
connect input/output signals to the on-chip periph-
erals as alternate pin functions. All ports can be in-
dividually configured as an input, bi-directional,
output or alternate function. In addition, pull-ups
can be turned off for open-drain operation, and
weak pull-ups can be turned on in their place, to
avoid the need for off-chip resistive pull-ups. Ports
configured as open drain must never have voltage
Refer to the Pin Description chapter for a list of the
specific port styles and reset values.
9.3 PORT CONTROL REGISTERS
Each port is associated with a Data register
(PxDR) and three Control registers (PxC0, PxC1,
PxC2). These define the port configuration and al-
low dynamic configuration changes during pro-
gram execution. Port Data and Control registers
are mapped into the Register File as shown in Fig-
ure 79. Port Data and Control registers are treated
just like any other general purpose register. There
are no special instructions for port manipulation:
any instruction that can address a register, can ad-
dress the ports. Data can be directly accessed in
the port register, without passing through other
memory or “accumulator” locations.
on the port pin exceeding V (refer to the Electri-
DD
cal Characteristics section). Depending on the
specific port, input buffers are software selectable
to be TTL or CMOS compatible, however on Sch-
mitt trigger ports, no selection is possible.
Figure 79. I/O Register Map
GROUP E
GROUP F
GROUP F
PAGE 3
GROUP F
PAGE 43
PAGE 2
Reserved
P3C2
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
P7DR
P7C2
P9DR
P9C2
P9C1
P9C0
P8DR
P8C2
P8C1
P8C0
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
P3C1
P7C1
P3C0
P7C0
Reserved
P2C2
P6DR
P6C2
System
Registers
P2C1
P6C1
P2C0
P6C0
Reserved
P1C2
Reserved
P5C2
E5h
E4h
E3h
E2h
E1h
E0h
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
R229
R228
R227
R226
R225
R224
P1C1
P5C1
Reserved
P1C0
P5C0
Reserved
P0C2
Reserved
P4C2
P0C1
P4C1
P0C0
P4C0
150/426
9
ST92F124/F150/F250 - I/O PORTS
PORT CONTROL REGISTERS (Cont’d)
During Reset, ports with weak pull-ups are set in
bidirectional/weak pull-up mode and the output
Data Register is set to FFh. This condition is also
held after Reset, except for Ports 0 and 1 in ROM-
less devices, and can be redefined under software
control.
Each pin of an I/O port may assume software pro-
grammable Alternate Functions (refer to the de-
vice Pin Description and to Section 9.5 ALTER-
NATE FUNCTION ARCHITECTURE). To output
signals from the ST9 peripherals, the port must be
configured as AF OUT. On ST9 devices with A/D
Converter(s), configure the ports used for analog
inputs as AF IN.
Bidirectional ports without weak pull-ups are set in
high impedance during reset. To ensure proper
levels during reset, these ports must be externally
The basic structure of the bit Px.n of a general pur-
pose port Px is shown in Figure 81.
connected to either V
or V through external
DD
SS
pull-up or pull-down resistors.
Independently of the chosen configuration, when
the user addresses the port as the destination reg-
ister of an instruction, the port is written to and the
data is transferred from the internal Data Bus to
the Output Master Latches. When the port is ad-
dressed as the source register of an instruction,
the port is read and the data (stored in the Input
Latch) is transferred to the internal Data Bus.
Other reset conditions may apply in specific ST9
devices.
9.4 INPUT/OUTPUT BIT CONFIGURATION
By programming the control bits PxC0.n and
PxC1.n (see Figure 80) it is possible to configure
bit Px.n as Input, Output, Bidirectional or Alternate
Function Output, where X is the number of the I/O
port, and n the bit within the port (n = 0 to 7).
When Px.n is programmed as an Input:
(See Figure 82).
When programmed as input, it is possible to select
the input level as TTL or CMOS compatible by pro-
gramming the relevant PxC2.n control bit.
– The Output Buffer is forced tristate.
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of each instruc-
tion execution.
This option is not available on Schmitt trigger ports.
The output buffer can be programmed as push-
pull or open-drain.
– The data stored in the Output Master Latch is
copied into the Output Slave Latch at the end of
the execution of each instruction. Thus, if bit Px.n
is reconfigured as an Output or Bidirectional, the
data stored in the Output Slave Latch will be re-
flected on the I/O pin.
A weak pull-up configuration can be used to avoid
external pull-ups when programmed as bidirec-
tional (except where the weak pull-up option has
been permanently disabled in the pin hardware as-
signment).
151/426
9
ST92F124/F150/F250 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
Figure 80. Control Bits
Bit 7
Bit n
Bit 0
PxC2
PxC1
PxC0
PxC27
PxC17
PxC07
PxC2n
PxC1n
PxC0n
PxC20
PxC10
PxC00
n
Table 33. Port Bit Configuration Table (n = 0, 1... 7; X = port number)
General Purpose I/O Pins
A/D Pins
PXC2n
PXC1n
PXC0n
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
PXn Configuration
PXn Output Type
BID
BID
OD
OUT
PP
OUT
OD
IN
IN
AF OUT AF OUT
AF IN
(1)
WP OD
HI-Z
HI-Z
PP
OD
HI-Z
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
CMOS
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
TTL
(or Schmitt
Trigger)
Analog
Input
PXn Input Type
(1)
For A/D Converter inputs.
Legend:
X
= Port
n
= Bit
AF
= Alternate Function
BID = Bidirectional
CMOS= CMOS Standard Input Levels
HI-Z = High Impedance
IN
= Input
OD = Open Drain
OUT = Output
PP
= Push-Pull
TTL = TTL Standard Input Levels
WP = Weak Pull-up
152/426
9
ST92F124/F150/F250 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
Figure 81. Basic Structure of an I/O Port Pin
I/O PIN
PUSH-PULL
TRISTATE
OPEN DRAIN
WEAK PULL-UP
TTL / CMOS
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
INTERRUPTS
OUTPUT SLAVE LATCH
ALTERNATE
FROM
FUNCTION
PERIPHERAL
OUTPUT
INPUT
BIDIRECTIONAL
ALTERNATE
FUNCTION
OUTPUT
INPUT
OUTPUT
BIDIRECTIONAL
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
Figure 82. Input Configuration
Figure 83. Output Configuration
I/O PIN
I/O PIN
OPEN DRAIN
PUSH-PULL
TTL / CMOS
TTL
TRISTATE
(or Schmitt Trigger)
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
OUTPUT SLAVE LATCH
INTERRUPTS
INTERRUPTS
OUTPUT MASTER LATCH
INPUT LATCH
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
INTERNAL DATA BUS
n
n
n
153/426
9
ST92F124/F150/F250 - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
When Px.n is programmed as an Output:
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of the execution
of the instruction.
(Figure 83)
– The Output Buffer is turned on in an Open-drain
or Push-pull configuration.
– The signal from an on-chip function is allowed to
load the Output Slave Latch driving the I/O pin.
Signal timing is under control of the alternate
function. If no alternate function is connected to
Px.n, the I/O pin is driven to a high level when in
Push-Pull configuration, and to a high imped-
ance state when in open drain configuration.
– The data stored in the Output Master Latch is
copied both into the Input Latch and into the Out-
put Slave Latch, driving the I/O pin, at the end of
the execution of the instruction.
When Px.n is programmed as Bidirectional:
(Figure 84)
Figure 84. Bidirectional Configuration
– The Output Buffer is turned on in an Open-Drain
or Weak Pull-up configuration (except when dis-
abled in hardware).
I/O PIN
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of the execution
of the instruction.
WEAK PULL-UP
OPEN DRAIN
TTL
(or Schmitt Trigger)
– The data stored in the Output Master Latch is
copied into the Output Slave Latch, driving the I/
O pin, at the end of the execution of the instruc-
tion.
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
INTERRUPTS
WARNING: Due to the fact that in bidirectional
mode the external pin is read instead of the output
latch, particular care must be taken with arithme-
tic/logic and Boolean instructions performed on a
bidirectional port pin.
OUTPUT MASTER LATCH
INPUT LATCH
These instructions use a read-modify-write se-
quence, and the result written in the port register
depends on the logical level present on the exter-
nal pin.
INTERNAL DATA BUS
n
n
This may bring unwanted modifications to the port
output register content.
Figure 85. Alternate Function Configuration
For example:
I/O PIN
Port register content, 0Fh
external port value, 03h
(Bits 3 and 2 are externally forced to 0)
OPEN DRAIN
PUSH-PULL
TTL
(or Schmitt Trigger)
A bsetinstruction on bit 7 will return:
Port register content, 83h
external port value, 83h
(Bits 3 and 2 have been cleared).
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
INTERRUPTS
To avoid this situation, it is suggested that all oper-
ations on a port, using at least one bit in bidirec-
tional mode, are performed on a copy of the port
register, then transferring the result with a load in-
struction to the I/O port.
FROM
PERIPHERAL
OUTPUT
INPUT LATCH
When Px.n is programmed as a digital Alter-
nate Function Output:
INTERNAL DATA BUS
(Figure 85)
n
n
n
n
n
n
– The Output Buffer is turned on in an Open-Drain
or Push-Pull configuration.
154/426
9
ST92F124/F150/F250 - I/O PORTS
9.5 ALTERNATE FUNCTION ARCHITECTURE
Each I/O pin may be connected to three different
types of internal signal:
9.5.3 Pin Declared as an Alternate Function
Output
– Data bus Input/Output
– Alternate Function Input
– Alternate Function Output
9.5.1 Pin Declared as I/O
The user must select the AF OUT configuration
using the PxC2, PxC1, PxC0 bits. Several Alter-
nate Function outputs may drive a common pin. In
such case, the Alternate Function output signals
are logically ANDed before driving the common
pin. The user must therefore enable the required
Alternate Function Output by software.
A pin declared as I/O, is connected to the I/O buff-
er. This pin may be an Input, an Output, or a bidi-
rectional I/O, depending on the value stored in
(PxC2, PxC1 and PxC0).
WARNING: When a pin is connected both to an al-
ternate function output and to an alternate function
input, it should be noted that the output signal will
always be present on the alternate function input.
9.5.2 Pin Declared as an Alternate Function
Input
A single pin may be directly connected to several
Alternate Function inputs. In this case, the user
must select the required input mode (with the
PxC2, PxC1, PxC0 bits) and enable the selected
Alternate Function in the Control Register of the
peripheral. No specific port configuration is re-
quired to enable an Alternate Function input, since
the input buffer is directly connected to each alter-
nate function module on the shared pin. As more
than one module can use the same input, it is up to
the user software to enable the required module
as necessary. Parallel I/Os remain operational
even when using an Alternate Function input. The
exception to this is when an I/O port bit is perma-
nently assigned by hardware as an A/D bit. In this
case , after software programming of the bit in AF-
OD-TTL, the Alternate function output is forced to
logic level 1. The analog voltage level on the cor-
responding pin is directly input to the A/D (See Fig-
ure 86).
9.6 I/O STATUS AFTER WFI, HALT AND RESET
The status of the I/O ports during the Wait For In-
terrupt, Halt and Reset operational modes is
shown in the following table. The External Memory
Interface ports are shown separately. If only the in-
ternal memory is being used and the ports are act-
ing as I/O, the status is the same as shown for the
other I/O ports.
Ext. Mem - I/O Ports
Mode
I/O Ports
P1, P2, P6,
P9[7:2] *
P0
High Imped-
anceornext
address
(depending
on the last
memory op-
eration per-
formed on
Port)
Next
Address
Not Affected (clock
outputs running)
WFI
Figure 86. A/D Input Configuration
I/O PIN
High Imped-
ance
Next
Address
Not Affected (clock
outputs stopped)
TOWARDS
ADC CONVERTER
HALT
TRISTATE
GND
Bidirectional Weak
Pull-up (High im-
pedance when dis-
abled in
Alternate function push-
pull (ROMless device)
RESET
INPUT
hardware).
OUTPUT SLAVE LATCH
BUFFER
* Depending on device
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
155/426
9
TIMER/WATCHDOG (WDT)
10 ON-CHIP PERIPHERALS
10.1 TIMER/WATCHDOG (WDT)
Important Note: This chapter is a generic descrip-
tion of the WDT peripheral. However depending
on the ST9 device, some or all of WDT interface
signals described may not be connected to exter-
nal pins. For the list of WDT pins present on the
ST9 device, refer to the device pinout description
in the first section of the data sheet.
The main WDT registers are:
– Control register for the input, output and interrupt
logic blocks (WDTCR)
– 16-bit counter register pair (WDTHR, WDTLR)
– Prescaler register (WDTPR)
The hardware interface consists of up to five sig-
nals:
10.1.1 Introduction
The Timer/Watchdog (WDT) peripheral consists of
a programmable 16-bit timer and an 8-bit prescal-
er. It can be used, for example, to:
– WDIN External clock input
– WDOUT Square wave or PWM signal output
– INT0 External interrupt input
– Generate periodic interrupts
– NMI Non-Maskable Interrupt input
– Measure input signal pulse widths
– Request an interrupt after a set number of events
– Generate an output signal waveform
– HW0SW1 Hardware/Software Watchdog ena-
ble.
– Act as a Watchdog timer to monitor system in-
tegrity
Figure 87. Timer/Watchdog Block Diagram
INMD1 INMD2
INEN
INPUT
&
WDIN
WDTRH, WDTRL
WDTPR
END OF
16-BIT
CLOCK CONTROL LOGIC
MUX
8-BIT PRESCALER
COUNT
DOWNCOUNTER
WDT
CLOCK
INTCLK/4
WROUT
OUTEN
OUTMD
OUTPUT CONTROL LOGIC
NMI
INT0
WDOUT
HW0SW1
INTERRUPT
MUX
IAOS
CONTROL LOGIC
WDGEN
TLIS
RESET
TOP LEVEL INTERRUPT REQUEST
INTA0 REQUEST
156/426
9
TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.2 Functional Description
10.1.2.1 External Signals
10.1.2.4 Single/Continuous Mode
The S_C bit allows selection of single or continu-
ous mode.This Mode bit can be written with the
Timer stopped or running. It is possible to toggle
the S_C bit and start the counter with the same in-
struction.
The HW0SW1 pin can be used to permanently en-
able Watchdog mode. Refer to Section 10.1.3.1 on
page 158.
The WDIN Input pin can be used in one of four
modes:
Single Mode
On reaching the End Of Count condition, the Timer
stops, reloads the constant, and resets the Start/
Stop bit. Software can check the current status by
reading this bit. To restart the Timer, set the Start/
Stop bit.
– Event Counter Mode
– Gated External Input Mode
– Triggerable Input Mode
– Retriggerable Input Mode
Note: If the Timer constant has been modified dur-
ing the stop period, it is reloaded at start time.
The WDOUT output pin can be used to generate a
square wave or a Pulse Width Modulated signal.
Continuous Mode
An interrupt, generated when the WDT is running
as the 16-bit Timer/Counter, can be used as a Top
Level Interrupt or as an interrupt source connected
to channel A0 of the external interrupt structure
(replacing the INT0 interrupt input).
On reaching the End Of Count condition, the coun-
ter automatically reloads the constant and restarts.
It is stopped only if the Start/Stop bit is reset.
10.1.2.5 Input Section
The counter can be driven either by an external
clock, or internally by INTCLK divided by 4.
If the Timer/Counter input is enabled (INEN bit) it
can count pulses input on the WDIN pin. Other-
wise it counts the internal clock/4.
10.1.2.2 Initialisation
For instance, when INTCLK = 24MHz, the End Of
Count rate is:
The prescaler (WDTPR) and counter (WDTRL,
WDTRH) registers must be loaded with initial val-
ues before starting the Timer/Counter. If this is not
done, counting will start with reset values.
2.79 seconds for Maximum Count
(Timer Const. = FFFFh, Prescaler Const. = FFh)
10.1.2.3 Start/Stop
166 ns for Minimum Count
(Timer Const. = 0000h, Prescaler Const. = 00h)
The ST_SP bit enables downcounting. When this
bit is set, the Timer will start at the beginning of the
following instruction. Resetting this bit stops the
counter.
The Input pin can be used in one of four modes:
– Event Counter Mode
– Gated External Input Mode
If the counter is stopped and restarted, counting
will resume from the last value unless a new con-
stant has been entered in the Timer registers
(WDTRL, WDTRH).
– Triggerable Input Mode
– Retriggerable Input Mode
The mode is configurable in the WDTCR.
10.1.2.6 Event Counter Mode
A new constant can be written in the WDTRH,
WDTRL, WDTPR registers while the counter is
running. The new value of the WDTRH, WDTRL
registers will be loaded at the next End of Count
(EOC) condition while the new value of the
WDTPR register will be effective immediately.
In this mode the Timer is driven by the external
clock applied to the input pin, thus operating as an
event counter. The event is defined as a high to
low transition of the input signal. Spacing between
trailing edges should be at least 8 INTCLK periods
(or 333ns with INTCLK = 24MHz).
End of Count is when the counter is 0.
When Watchdog mode is enabled the state of the
ST_SP bit is irrelevant.
Counting starts at the next input event after the
ST_SP bit is set and stops when the ST_SP bit is
reset.
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9
TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.2.7 Gated Input Mode
10.1.3 Watchdog Timer Operation
This mode can be used for pulse width measure-
ment. The Timer is clocked by INTCLK/4, and is
started and stopped by means of the input pin and
the ST_SP bit. When the input pin is high, the Tim-
er counts. When it is low, counting stops. The
maximum input pin frequency is equivalent to
INTCLK/8.
This mode is used to detect the occurrence of a
software fault, usually generated by external inter-
ference or by unforeseen logical conditions, which
causes the application program to abandon its
normal sequence of operation. The Watchdog,
when enabled, resets the MCU, unless the pro-
gram executes the correct write sequence before
expiry of the programmed time period. The appli-
cation program must be designed so as to correct-
ly write to the WDTLR Watchdog register at regu-
lar intervals during all phases of normal operation.
10.1.2.8 Triggerable Input Mode
The Timer (clocked internally by INTCLK/4) is
started by the following sequence:
– setting the Start-Stop bit, followed by
– a High to Low transition on the input pin.
To stop the Timer, reset the ST_SP bit.
10.1.2.9 Retriggerable Input Mode
10.1.3.1
Hardware
Watchdog/Software
Watchdog
The HW0SW1 pin (when available) selects Hard-
ware Watchdog or Software Watchdog.
If HW0SW1 is held low:
In this mode, the Timer (clocked internally by
INTCLK/4) is started by setting the ST_SP bit. A
High to Low transition on the input pin causes
counting to restart from the initial value. When the
Timer is stopped (ST_SP bit reset), a High to Low
transition of the input pin has no effect.
– The Watchdog is enabled by hardware immedi-
ately after an external reset. (Note: Software re-
set or Watchdog reset have no effect on the
Watchdog enable status).
– The initial counter value (FFFFh) cannot be mod-
ified, however software can change the prescaler
value on the fly.
10.1.2.10 Timer/Counter Output Modes
Output modes are selected by means of the OUT-
EN (Output Enable) and OUTMD (Output Mode)
bits of the WDTCR register.
– The WDGEN bit has no effect. (Note: it is not
forced low).
If HW0SW1 is held high, or is not present:
No Output Mode
(OUTEN = “0”)
– The Watchdog can be enabled by resetting the
WDGEN bit.
The output is disabled and the corresponding pin
is set high, in order to allow other alternate func-
tions to use the I/O pin.
10.1.3.2 Starting the Watchdog
In Watchdog mode the Timer is clocked by
INTCLK/4.
Square Wave Output Mode
(OUTEN = “1”, OUTMD = “0”)
If the Watchdog is software enabled, the time base
must be written in the timer registers before enter-
ing Watchdog mode by resetting the WDGEN bit.
Once reset, this bit cannot be changed by soft-
ware.
The Timer outputs a signal with a frequency equal
to half the End of Count repetition rate on the WD-
OUT pin. With an INTCLK frequency of 20MHz,
this allows a square wave signal to be generated
whose period can range from 400ns to 6.7 sec-
onds.
If the Watchdog is hardware enabled, the time
base is fixed by the reset value of the registers.
Pulse Width Modulated Output Mode
(OUTEN = “1”, OUTMD = “1”)
Resetting WDGEN causes the counter to start, re-
gardless of the value of the Start-Stop bit.
The state of the WROUT bit is transferred to the
output pin (WDOUT) at the End of Count, and is
held until the next End of Count condition. The
user can thus generate PWM signals by modifying
the status of the WROUT pin between End of
Count events, based on software counters decre-
mented by the Timer Watchdog interrupt.
In Watchdog mode, only the Prescaler Constant
may be modified.
If the End of Count condition is reached a System
Reset is generated.
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TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.3.3 Preventing Watchdog System Reset
10.1.3.4 Non-Stop Operation
In order to prevent a system reset, the sequence
AAh, 55h must be written to WDTLR (Watchdog
Timer Low Register). Once 55h has been written,
the Timer reloads the constant and counting re-
starts from the preset value.
In Watchdog Mode, a Haltinstruction is regarded
as illegal. Execution of the Haltinstruction stops
further execution by the CPU and interrupt ac-
knowledgment, but does not stop INTCLK, CPU-
CLK or the Watchdog Timer, which will cause a
System Reset when the End of Count condition is
reached. Furthermore, ST_SP, S_C and the Input
Mode selection bits are ignored. Hence, regard-
less of their status, the counter always runs in
Continuous Mode, driven by the internal clock.
To reload the counter, the two writing operations
must be performed sequentially without inserting
other instructions that modify the value of the
WDTLR register between the writing operations.
The maximum allowed time between two reloads
of the counter depends on the Watchdog timeout
period.
The Output mode should not be enabled, since in
this context it is meaningless.
Figure 88. Watchdog Timer Mode
COUNT
VALUE
TIMER START COUNTING
RESET
WRITE WDTRH,WDTRL
WDGEN=0
SOFTWARE FAIL
(E.G. INFINITE LOOP)
OR PERIPHERAL FAIL
WRITE AAh,55h
INTO WDTRL
PRODUCE
COUNT RELOAD
VA00220
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9
TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.4 WDT Interrupts
Figure 89. Interrupt Sources
The Timer/Watchdog issues an interrupt request
at every End of Count, when this feature is ena-
bled.
TIMER WATCHDOG
A pair of control bits, IA0S (EIVR.1, Interrupt A0 se-
lection bit) and TLIS (EIVR.2, Top Level Input Se-
lection bit) allow the selection of 2 interrupt sources
(Timer/Watchdog End of Count, or External Pin)
handled in two different ways, as a Top Level Non
Maskable Interrupt (Software Reset), or as a
source for channel A0 of the external interrupt logic.
RESET
WDGEN (WCR.6)
A block diagram of the interrupt logic is given in
Figure 89.
0
1
Note: Software traps can be generated by setting
the appropriate interrupt pending bit.
MUX
INTA0 REQUEST
INT0
Table 34 below, shows all the possible configura-
tions of interrupt/reset sources which relate to the
Timer/Watchdog.
IA0S (EIVR.1)
A reset caused by the watchdog will set bit 6,
WDGRES of R242 - Page 55 (Clock Flag Regis-
ter). See section CLOCK CONTROL REGIS-
TERS.
0
1
TOP LEVEL
INTERRUPT REQUEST
MUX
NMI
TLIS (EIVR.2)
VA00293
Table 34. Interrupt Configuration
Control Bits
Enabled Sources
INTA0
Operating Mode
WDGEN
IA0S
TLIS
Reset
Top Level
0
0
0
0
0
0
1
1
0
1
0
1
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
SW TRAP
SW TRAP
Ext Pin
SW TRAP
Ext Pin
SW TRAP
Ext Pin
Watchdog
Watchdog
Watchdog
Watchdog
Ext Pin
1
1
1
1
0
0
1
1
0
1
0
1
Ext Reset
Ext Reset
Ext Reset
Ext Reset
Timer
Timer
Ext Pin
Ext Pin
Timer
Ext Pin
Timer
Timer
Timer
Timer
Timer
Ext Pin
Legend:
WDG = Watchdog function
SW TRAP = Software Trap
Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0
interrupts), only the INTA0 interrupt is taken into account.
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9
TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.5 Register Description
TIMER/WATCHDOG PRESCALER REGISTER
(WDTPR)
The Timer/Watchdog is associated with 4 registers
mapped into Group F, Page 0 of the Register File.
R250 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
WDTHR: Timer/Watchdog High Register
WDTLR: Timer/Watchdog Low Register
WDTPR: Timer/Watchdog Prescaler Register
WDTCR: Timer/Watchdog Control Register
7
0
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Three additional control bits are mapped in the fol-
lowing registers on Page 0:
Bits 7:0 = PR[7:0] Prescaler value.
A programmable value from 1 (00h) to 256 (FFh).
Watchdog Mode Enable, (WCR.6)
Top Level Interrupt Selection, (EIVR.2)
Interrupt A0 Channel Selection, (EIVR.1)
Warning: In order to prevent incorrect operation of
the Timer/Watchdog, the prescaler (WDTPR) and
counter (WDTRL, WDTRH) registers must be ini-
tialised before starting the Timer/Watchdog. If this
is not done, counting will start with the reset (un-in-
itialised) values.
Note: The registers containing these bits also con-
tain other functions. Only the bits relevant to the
operation of the Timer/Watchdog are shown here.
Counter Register
This 16-bit register (WDTLR, WDTHR) is used to
load the 16-bit counter value. The registers can be
read or written “on the fly”.
WATCHDOG TIMER CONTROL REGISTER
(WDTCR)
R251- Read/Write
Register Page: 0
Reset value: 0001 0010 (12h)
TIMER/WATCHDOG HIGH REGISTER (WDTHR)
R248 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
7
0
ST_SP S_C INMD1 INMD2 INEN OUTMD WROUT OUTEN
7
0
R15 R14 R13 R12 R11 R10
R9
R8
Bit 7 = ST_SP: Start/Stop Bit.
This bit is set and cleared by software.
0: Stop counting
Bits 7:0 = R[15:8] Counter Most Significant Bits.
1: Start counting (see Warning above)
TIMER/WATCHDOG LOW REGISTER (WDTLR)
R249 - Read/Write
Bit 6 = S_C: Single/Continuous.
This bit is set and cleared by software.
0: Continuous Mode
Register Page: 0
Reset value: 1111 1111b (FFh)
1: Single Mode
7
0
Bits 5:4 = INMD[1:2]: Input mode selection bits.
R7
R6
R5
R4
R3
R2
R1
R0
These bits select the input mode:
INMD1
INMD2
INPUT MODE
Event Counter
Bits 7:0 = R[7:0] Counter Least Significant Bits.
0
0
1
1
0
1
0
1
Gated Input (Reset value)
Triggerable Input
Retriggerable Input
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9
TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
Bit 3 = INEN: Input Enable.
This bit is set and cleared by software.
0: Disable input section
by the user program. At System Reset, the Watch-
dog mode is disabled.
Note: This bit is ignored if the Hardware Watchdog
option is enabled by pin HW0SW1 (if available).
1: Enable input section
Bit 2 = OUTMD: Output Mode.
This bit is set and cleared by software.
0: The output is toggled at every End of Count
1: The value of the WROUT bit is transferred to the
output pin on every End Of Count if OUTEN=1.
EXTERNAL INTERRUPT VECTOR REGISTER
(EIVR)
R246 - Read/Write
Register Page: 0
Reset value: xxxx 0110 (x6h)
Bit 1 = WROUT: Write Out.
7
x
0
x
The status of this bit is transferred to the Output
pin when OUTMD is set; it is user definable to al-
low PWM output (on Reset WROUT is set).
x
x
x
x
TLIS IA0S
Bit 2 = TLIS: Top Level Input Selection.
Bit 0 = OUTEN: Output Enable bit.
This bit is set and cleared by software.
0: Disable output
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
1: NMI is TL interrupt source
1: Enable output
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source
1: External Interrupt pin is INTA0 source
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Warning: To avoid spurious interrupt requests,
the IA0S bit should be accessed only when the in-
terrupt logic is disabled (i.e. after the DI instruc-
tion). It is also necessary to clear any possible in-
terrupt pending requests on channel A0 before en-
abling this interrupt channel. A delay instruction
(e.g. a NOP instruction) must be inserted between
the reset of the interrupt pending bit and the IA0S
write instruction.
Reset value: 0111 1111 (7Fh)
7
x
0
x
WDGEN
x
x
x
x
x
Bit 6 = WDGEN: Watchdog Enable (active low).
Resetting this bit via software enters the Watch-
dog mode. Once reset, it cannot be set any more
Other bits are described in the Interrupt section.
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9
STANDARD TIMER (STIM)
10.2 STANDARD TIMER (STIM)
10.2.1 Introduction
the prescaler can be driven either by an internal
clock equal to INTCLK divided by 4, or by
CLOCK2/1024 derived directly from the external
oscillator, thus providing a stable time reference
independent from the PLL programming (refer to
Figure 90).
The Standard Timer includes a programmable 16-
bit down counter and an associated 8-bit prescaler
with Single and Continuous counting modes capa-
bility. The Standard Timer uses an output
(STOUT) pin. This pin may be independent pin or
connected as Alternate Function of an I/O port bit.
The Standard Timer End Of Count condition is
able to generate an interrupt which is connected to
one of the external interrupt channels.
STOUT can be used to generate a Square Wave
or Pulse Width Modulated signal.
The End of Count condition is defined as the
Counter Underflow, whenever 00h is reached.
The Standard Timer is composed of a 16-bit down
counter with an 8-bit prescaler. The input clock to
Figure 90. Standard Timer Block Diagram
n
INMD1 INMD2
INEN
INPUT
&
STH,STL
16-BIT
DOWNCOUNTER
STP
CLOCK CONTROL LOGIC
MUX
8-BIT PRESCALER
STANDARD TIMER
CLOCK
INTCLK/4
END OF
COUNT
CLOCK2/1024
STOUT
OUTMD2
OUTMD1
OUTPUT CONTROL LOGIC
EXTERNAL
INTERRUPT
INTERRUPT
INTS
CONTROL LOGIC
INTERRUPT REQUEST
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9
STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
10.2.2 Functional Description
10.2.2.1 Timer/Counter control
10.2.2.3 Standard Timer Output Modes
Start-stop Count. The ST-SP bit (STC.7) is used
in order to start and stop counting. An instruction
which sets this bit will cause the Standard Timer to
start counting at the beginning of the next instruc-
tion. Resetting this bit will stop the counter.
OUTPUT modes are selected using 2 bits of the
STC register: OUTMD1 and OUTMD2.
No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”)
The output is disabled and the corresponding pin
is set high, in order to allow other alternate func-
tions to use the I/O pin.
If the counter is stopped and restarted, counting
will resume from the value held at the stop condi-
tion, unless a new constant has been entered in
the Standard Timer registers during the stop peri-
od. In this case, the new constant will be loaded as
soon as counting is restarted.
Square Wave Output Mode (OUTMD1 = “0”,
OUTMD2 = “1”)
The Standard Timer toggles the state of the
STOUT pin on every End Of Count condition. With
INTCLK = 24MHz, this allows generation of a
square wave with a period ranging from 333ns
(STP = STH = STL = 00h) to 5.59 seconds (STP =
STH = STL = FFh).
A new constant can be written in STH, STL, STP
registers while the counter is running. The new
value of the STH and STL registers will be loaded
at the next End of Count condition, while the new
value of the STP register will be loaded immedi-
ately.
PWM Output Mode (OUTMD1 = “1”)
The value of the OUTMD2 bit is transferred to the
STOUT output pin at the End Of Count. This al-
lows the user to generate PWM signals, by modi-
fying the status of OUTMD2 between End of Count
events, based on software counters decremented
on the Standard Timer interrupt.
WARNING:Inordertopreventincorrectcountingof
theStandardTimer,theprescaler(STP)andcounter
(STL, STH) registers must be initialised before the
starting of the timer. If this is not done, counting will
start with the reset values (STH=FFh, STL=FFh,
STP=FFh).
10.2.3 Interrupt Selection
Single/Continuous Mode.
The S-C bit (STC.6) selects between the Single or
Continuous mode.
The Standard Timer may generate an interrupt re-
quest at every End of Count.
Bit 2 of the STC register (INTS) selects the inter-
rupt source between the Standard Timer interrupt
and the external interrupt pin. Thus the Standard
Timer Interrupt uses the interrupt channel and
takes the priority and vector of the external inter-
rupt channel.
SINGLE MODE: at the End of Count, the Standard
Timer stops, reloads the constant and resets the
Start/Stop bit (the user programmer can inspect
the timer current status by reading this bit). Setting
the Start/Stop bit will restart the counter.
CONTINUOUS MODE: At the End of the Count, the
counter automatically reloads the constant and re-
starts.ItisonlystoppedbyresettingtheStart/Stopbit.
If INTS is set to “1”, the Standard Timer interrupt is
disabled; otherwise, an interrupt request is gener-
ated at every End of Count.
The S-C bit can be written either with the timer
stopped or running. It is possible to toggle the S-C
bit and start the Standard Timer with the same in-
struction.
Note: When enabling or disabling the Standard
Timer Interrupt (writing INTS in the STC register)
an edge may be generated on the interrupt chan-
nel, causing an unwanted interrupt.
10.2.2.2 Time Base Generator
To avoid this spurious interrupt request, the INTS
bit should be accessed only when the interrupt log-
ic is disabled (i.e. after the DI instruction). It is also
necessary to clear any possible interrupt pending
requests on the corresponding external interrupt
channel before enabling it. A delay instruction (i.e.
a NOP instruction) must be inserted between the
reset of the interrupt pending bit and the INTS
write instruction.
The INEN bit in the STC register selects the clock
source (refer to RCCU section).
When the INEN bit is reset, INTCLK/4 is selected
as clock input.
When the INEN bit is set, CLOCK2/1024 is select-
ed as clock input. In this case, INMD1 and INMD2
bits in the STC register must always be kept at 0 to
select the event counter mode. This mode allows
the Standard Timer to generate a stable time base
independent from PLL programming.
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9
STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
10.2.4 Register Description
COUNTER HIGH BYTE REGISTER (STH)
R240 - Read/Write
STANDARD TIMER CONTROL REGISTER
(STC)
Register Page: 11
R243 - Read/Write
Reset value: 1111 1111 (FFh)
Register Page: 11
Reset value: 0001 0100 (14h)
7
0
7
0
ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9
ST.8
S-C INMD1 INMD2 INEN INTS OUTMD1 OUTMD2
ST-SP
Bits 7:0 = ST.[15:8]: Counter High-Byte.
Bit 7 = ST-SP: Start-Stop Bit.
This bit is set and cleared by software.
0: Stop counting
COUNTER LOW BYTE REGISTER (STL)
R241 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
1: Start counting
Bit 6 = S-C: Single-Continuous Mode Select.
This bit is set and cleared by software.
0: Continuous Mode
7
0
1: Single Mode
ST.7
ST.6
ST.5
ST.4
ST.3
ST.2
ST.1
ST.0
Bits 7:0 = ST.[7:0]: Counter Low Byte.
Bits 5:4 = INMD[1:2]
Bit 3 = INEN
Writing to the STH and STL registers allows the
user to enter the standard timer constant from 1
(0000h) to 65536 (FFFFh). Reading these regis-
ters provides the counter's current value. Thus it is
possible to read the counter on-the-fly.
These 3 bits select the clock source.
INMD1 INMD2 INEN Clock input
0
X
0
X
1
0
CLOCK2/1024
INTCLK/4
STANDARD TIMER PRESCALER REGISTER
(STP)
Bit 2 = INTS: Interrupt Selection.
0: Standard Timer interrupt enabled
1: Standard Timer interrupt is disabled and the ex-
ternal interrupt pin is enabled.
R242 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
7
0
Bits 1:0 = OUTMD[1:2]: Output Mode Selection.
These bits select the output functions as described
in Section 10.2.2.3.
STP.7 STP.6 STP.5 STP.4 STP.3 STP.2 STP.1 STP.0
OUTMD1 OUTMD2 Mode
Bits 7:0 = STP.[7:0]: Prescaler.
0
0
1
0
1
x
No output mode
The Prescaler value for the Standard Timer is pro-
grammed into this register. When reading the STP
register, the returned value corresponds to the
programmed data instead of the current data.
00h: No prescaler
Square wave output mode
PWM output mode
01h: Divide by 2
FFh: Divide by 256
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EXTENDED FUNCTION TIMER (EFT)
10.3 EXTENDED FUNCTION TIMER (EFT)
10.3.1 Introduction
Table 35. EFT Pin Naming conventions
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
Function
Input Capture 1 - ICAP1
Input Capture 2 - ICAP2
EFT0
ICAPA0
ICAPB0
EFT1
ICAPA1
ICAPB1
OCMPA1
OCMPB1
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Output Compare 1 - OCMP1 OCMPA0
Output Compare 2 - OCMP2 OCMPB0
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the INTCLK
prescaler.
10.3.3 Functional Description
10.3.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running counter and its associated
16-bit registers:
10.3.2 Main Features
■ Programmable prescaler: INTCLK divided by 2,
4 or 8.
Counter Registers
■ Overflow status flag and maskable interrupts
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
■ External clock input (must be at least 4 times
slower than the INTCLK clock speed) with the
choice of active edge
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
■ Output compare functions with
– 2 dedicated 16-bit registers
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
– 2 dedicated programmable signals
– 2 dedicated status flags
– Maskable interrupt generation
■ Input capture functions with
– 2 dedicated 16-bit registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note page 168).
– 2 dedicated active edge selection signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
– Maskable interrupt generation
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternate functions on I/O ports
■ Global Timer interrupt (EFTI).
The Block Diagram is shown in Figure 91.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 36. The
value in the counter register repeats every
131.072, 262.144 or 524.288 INTCLK cycles de-
pending on the CC[1:0] bits.
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9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 91. Timer Block Diagram
ST9 INTERNAL BUS
INTCLK
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
16 BIT
FREE RUNNING
1/2
1/4
1/8
COUNTER
1
1
2
2
COUNTER
ALTERNATE
REGISTER
16
16
16
CC1 CC0
TIMER INTERNAL BUS
16
16
OVERFLOW
DETECT
CIRCUIT
EXTCLK
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
ICAP2
6
EDGE DETECT
CIRCUIT2
OCMP1
OCMP2
LATCH1
LATCH2
ICF1 OCF1 TOF ICF2 OCF2
0
0
0
SR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
CR1
CR2
OCF2
OCF1
1
0
EFTIS
IC1IE
IC2IE OC2IE
-
-
-
OC1IE
CR3
ICF1
1
0
ICF2
0
1
INTx External interrupt pin
EFTI Interrupt
Request
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Clearing the overflow interrupt request is done by:
Register or the Alternate Counter Register).
1. Reading the SR register while the TOF bit is
set.
Beginning of the sequence
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.
Read MSB
At t0
LSB is buffered
Other
instructions
Returns the buffered
LSB value at t0
The timer is not affected by WAIT mode.
Read LSB
At t0 +Dt
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MSB first, then the LSB
value is buffered automatically.
10.3.3.2 External Clock
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit determines the type
of level transition on the external clock pin EXT-
CLK that will trigger the free running counter.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LSB of the count value at the time of the
read.
The counter is synchronised with the falling edge
of INTCLK.
An overflow occurs when the counter rolls over
from FFFFh to 0000h then:
At least four falling edges of the INTCLK must oc-
cur between two consecutive active edges of the
external clock; thus the external clock frequency
must be less than a quarter of the INTCLK fre-
quency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set
– EFTIS bit of the CR3 register is set.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 92. Counter Timing Diagram, INTCLK divided by 2
INTCLK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 93. Counter Timing Diagram, INTCLK divided by 4
INTCLK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 94. Counter Timing Diagram, INTCLK divided by 8
INTCLK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
OVERFLOW FLAG TOF
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.3 Input Capture
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit if ICAP1 is active.
In this section, the index, i, may be 1 or 2.
When an input capture occurs:
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 96).
MS Byte
LS Byte
– A timer interrupt is generated under the following
two conditions :
ICiR
ICiHR
ICiLR
1. If the ICIE bit (for both ICAP1 & ICAP2) and
the EFTIS bit are set.
ICi Rregister is a read-only register.
Note: If the ICIE bit is set, the status of the
IC1IE/IC2IE bits in the CR3 register is not sig-
nificant.
The active transition is software programmable
through the IEDGi bit of the Control Register (CRi).
2. If the ICIE bit is reset and the IC1IE and /or
IC2IE bits are set and the EFTIS bit is set.
Timing resolution is one count of the free running
counter: (INTCLK
).
/CC[1:0]
Otherwise, the interrupt remains pending until
the related enable bits are set.
Procedure
To use the input capture function select the follow-
ing in the CR2 register:
Clearing the Input Capture interrupt request is
done by:
– Select the timer clock (CC[1:0] (see Table 36).
1. An access (read or write) to the SR register
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit, if ICAP2 is active.
while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
And select the following in the CR1/CR3 register:
– To enable both ICAP1 & ICAP2 interrupts, set
the ICIE bit in the CR1 register (in this case, the
IC1IE & IC2IE enable bits are not significant).
To enable only one ICAP interrupt, reset the ICIE
bit and set the IC1IE (or IC2IE) bit.
Note: If ICIE is reset and both IC1IE & IC2IE are
set, both interrupts are enabled.
Note: After reading the ICiHR register, transfer of
input capture data is inhibited until the ICiLR regis-
ter is also read.
The ICiR register always contains the free running
counter value which corresponds to the most re-
cent input capture.
In all cases, set the EFTIS bit to enable timer in-
terrupts globally
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 95. Input Capture Block Diagram
ICAP1
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
(Status Register) SR
ICF1
ICF2
0
0
0
IC1R
IC2R
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 96. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.4 Output Compare
– A timer interrupt is generated under the following
two conditions :
1. If the OCIE bit (for both OCMP1 & OCMP2)
and the EFTIS bit are set.
In this section, the index, i, may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
Note: If the OCIE bit is set, the status of the
OC1IE/OC2IE bits in the CR3 register is not
significant.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
2. If the OCIE bit is reset and the OC1IE and /or
OC2IE bits are set and the EFTIS bit is set.
– Assigns pins with a programmable value if the
Otherwise, the interrupt remains pending until
the related enable bits are set.
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Clearing the output compare interrupt request is
done by:
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
– An access (read or write) to the SR register while
the OCFi bit is set.
– An access (read or write) to the OCiLR register.
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
Note: After a write access to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
If the OCiE bit is not set, the OCMPi pin is a gen-
eral I/O port and the OLVLi bit will not appear
when match is found but an interrupt could be gen-
erated if the OCIE bit is set.
Timing resolution is one count of the free running
counter: (INTCLK
).
CC[1:0]
/
Procedure
The value in the 16-bit OCiR register and the
OLVLi bit should be changed after each success-
ful comparison in order to control an output wave-
form or establish a new elapsed timeout.
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OCiE bit if an output is needed, the OC-
MPi pin is then dedicated to the output compare
function.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
– Select the timer clock (CC[1:0] see Table 36).
Select the following in the CR1/CR3 register:
∆t INTCLK
(CC1.CC0)
*
∆ OCiR =
– Select the OLVLi bit to be applied to the OCMP
pins after the match occurs.
Where:
– To enable both OCMP1 & OCMP2 interrupts, set
the OCIE bit in the CR1 register (in this case, the
OC1IE & OC2IE enable bits are not significant).
To enable only one OCMP interrupt, reset the
OCIE bit and set the OC1IE (or OC2IE) bit.
Note: If OCIE is reset and both OC1IE & OC2IE
are set, both interrupts are enabled.
∆t
= Desired output compare period (in
seconds)
INTCLK = Internal clock frequency
CC[1:0] = Timer clock prescaler
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
In all cases, set the EFTIS bit to enable timer in-
terrupts globally.
When a match is found:
– Write to the OCiHR register (further compares
are inhibited).
– The OCFi bit is set.
– Read the SR register (first step of the clearance
– The OCMPi pin takes the OLVLi bit value (the
OCMPi pin latch is forced low during reset and
stays low until a valid compare changes it to the
OLVLi level).
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 97. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
(Control Register 1) CR1
16-bit
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
OLVL2
OLVL1
OCMP1
OCMP2
Latch
2
16-bit
16-bit
OCF1
OCF2
0
0
0
OC2R
OC1R
(Status Register) SR
Figure 98. Output Compare Timing Diagram, Internal Clock Divided by 2
INTCLK
TIMER CLOCK
FFFC FFFD FFFD FFFE
CPU writes FFFF
0000
FFFF
FFFF
COUNTER
OUTPUT COMPARE REGISTER
COMPARE REGISTER LATCH
OCFi AND OCMPi PIN (OLVLi=1)
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.5 Forced Compare Mode
Load the OC1R register with the value corre-
sponding to the length of the pulse (see the formu-
la in Section 10.3.3.7).
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
One pulse mode cycle
Counter is
initialized
to FFFCh
FOLV2 FOLV1 OLVL2
OLVL1
When
event occurs
on ICAP1
When the FOLV1 bit is set, the OLVL1 bit is copied
to the OCMP1 pin if PWM and OPM are both
cleared.
OCMP1 = OLVL2
OCMP1 = OLVL1
When the FOLV2 bit is set, the OLVL2 bit is copied
to the OCMP2 pin.
When
The OLVLi bit has to be toggled in order to toggle
the OCMPi pin when it is enabled (OCiE bit=1).
Counter
= OC1R
Notes:
– The OCFi bit is not set when FOLVi is set, and
thus no interrupt request is generated.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin. When the value of the counter
is equal to the value of the contents of the OC1R
register, the OLVL1 bit is output on the OCMP1
pin, (See Figure 99).
– The OCFi bit can be set if OCiR = Counter and
an interrupt can be generated if enabled. This
can be avoided by writing in the OCiHR register.
The output compare function is inhibited till
OCiLR is also written.
– The Input Capture function works in Forced com-
pare mode. To disable it, read the ICiHR register.
Input capture will be inhibited till ICiLR is read.
Notes:
– The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
10.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
– The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is set
or ICIE is reset and IC1IE is set. The IC1R regis-
ter will have the value FFFCh.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
– When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
To use one pulse mode, select the following in the
the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
– When One Pulse Mode (OPM) and Forced Com-
pare 1 mode (FOLV1) bits are set then OPM is
the active mode
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
– Forced Compare 2 mode works in OPM
– Input Capture 2 function works in OPM
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
– When OC1R = FFFCh in OPM, then a pulse of
width FFFCh is generated
And select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedi-
cated to the Output Compare 1 function.
– If IC1HR register is read in OPM before an active
edge of ICAP1, then OPM is inhibited till IC1LR
is also read.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 36).
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
– If an event occurs on ICAP1 again before the
Counter reaches the OC1R value, then the
Counter will be reset again and the pulse gener-
ated might be longer than expected as in Figure
99.
– If a write operation is performed on CLR or ACLR
register before the Counter reaches the OC1R
value, then the Counter will be reset again and
the pulse generated might be longer than expect-
ed.
Figure 99. One Pulse Mode Timing
....
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
....
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
0010 FFFC
FFFC FFFD FFFE
COUNTER
ICAP1
OLVL2
OLVL2
OLVL1
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.3.7 Pulse Width Modulation Mode
Pulse Width Modulation mode enables the gener-
ation of a signal with a frequency and pulse length
determined by the value of the OC1R and OC2R
registers.
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register.
OCMP1 = OLVL2
Procedure
When
Counter
= OC2R
To use pulse width modulation mode select the fol-
lowing in the CR1 register:
Counter is reset
to FFFCh
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful com-
parison with OC1R register.
Notes:
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful com-
parison with OC2R register.
– After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
And select the following in the CR2 register:
– The OCF1 bit cannot be set by hardware in PWM
mode, but the OCF2 bit is set every time the
counter matches the OC2R register.
– Set OC1E bit: the OCMP1 pin is then dedicated
to the output compare 1 function.
– Set the PWM bit.
– The Input Capture function is available in PWM
mode.
– Select the timer clock CC[1:0] bits (see Table
36).
– When Counter = OC2R, then the OCF2 bit will be
set. This can generate an interrupt if OCIE is set
or OCIE is reset and OC2IE is set. This interrupt
is useful in applications where the pulse-width or
period needs to be changed interactively.
Load the OC2R register with the value corre-
sponding to the period of the signal.
Load the OC1R register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
– When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active mode.
If OLVL1=1 and OLVL2=0 the length of the pulse
is the difference between the OC2R and OC1R
registers.
– The value loaded in register OC2R must always
be greater than the value in register OC1R in or-
der to produce meaningful waveforms. Note that
0000h is considerred to be greater than FFFCh
or FFFDh or FFFEh or FFFFh.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t
INTCLK
*
- 5
OCiR Value =
– When OC1R >OC2R, no waveform will be gen-
erated.
CC[1:0]
Where:
– When OC2R = OC1R, a square waveform will
be generated as in Figure 100
– t = Desired output compare period (seconds)
– INTCLK = Internal clock frequency
– When OC2R is loaded with FFFC (the counter
reset value) then no waveform will be generated
& the counter will remain stuck at FFFC.
– CC1-CC0 = Timer clock prescaler
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 100).
– When OC1R is loaded with FFFC (the counter
reset value) then the waveform will be generated
as in Figure 100
– When FOLV1 bit is set and PWM bit is set, then
PWM mode is the active one. But if FOLV2 bit is
set then the OLVL2 bit will appear on OCMP2
(when OC2E bit = 1).
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
– When a write is performed on the CLR or ACLR
register in PWM mode, then the Counter will be
reset and the pulse-width/period of the waveform
generated may not be be as desired
Figure 100. Pulse Width Modulation Mode Timing
34E2 FFFC FFFD FFFE
COUNTER
2ED0 2ED1 2ED2
34E2 FFFC
OLVL2
OLVL1
OLVL2
OCMP1
compare2
compare1
compare2
OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
0010 FFFC
000F 0010 FFFC
0010 FFFC
OLVL1
COUNTER
OCMP1
OLVL2
OLVL1
OC1R = OC2R = 0010h, OLVL1 = 1, OLVL2 = 0
0003 0004 FFFC
0003 0004 FFFC
COUNTER
OCMP1
OLVL1
OLVL2
OLVL1
OLVL2
OC1R = FFFCh, OC2R = 0004h, OLVL1 = 1, OLVL2 = 0
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.4 Interrupt Management
– Set the OCIE (or OC1IE/OC2IE bits) and/or ICIE
(or IC1IE/IC2IE bits and/or TOIE bit(s) in the CR1
register to enable interrupts
The interrupts of the Extended Function Timer are
mapped on one of the eight External Interrupt
Channels of the microcontroller (refer to the “Inter-
rupts” chapter).
The three interrupt sources are mapped on the
same interrupt channel. To use them, the EFTIS
bit must be set)
– In the EIPR register, reset the pending bit of the
interrupt channel used by the peripheral inter-
rupts to avoid any spurious interrupt requests be-
ing performed when the mask bit is set
– Set the mask bits of the interrupt channels used
to enable the MCU to acknowledge the interrupt
requests of the peripheral.
Each External Interrupt Channel has:
– A trigger control bit in the EITR register (R242 -
Page 0),
– Clear all EFT interrupt flags by reading the Sta-
tus, Input Capture Low, Output Compare Low
and Counter Low Registers.
– A pending bit in the EIPR register (R243 - Page
0),
Caution:
– A mask bit in the EIMR register (R244 - Page 0).
1. It is mandatory to clear all EFT interrupt flags
simultaneously at least once before exiting an
EFT timer interrupt routine (the SR register
must = 00h at some point during the interrupt
routine), otherwise no interrupts can be issued
on that channel anymore.
Program the interrupt priority level using the EI-
PLR register (R245 - Page 0). For a description of
these registers refer to the “Interrupts” and “DMA”
chapters.
Refer to the following assembly code for an
interrupt sequence example.
Using the external interrupt channel for all EFT
interrupts
To use the interrupt features, perform the following
sequence:
2. Since a loop statement is needed inside the IT
routine, the user must avoid situations where
an interrupt event period is narrower than the
duration of the interrupt treatment. Otherwise
nested interrupt mode must be used to serve
higher priority requests.
– Set the priority level of the interrupt channel used
(EIPLR register)
– Select the interrupt trigger edge as rising edge
(set the corresponding bit in the EITR register)
– Set the EFTIS bit of the CR3 register to select
the peripheral interrupt sources
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Note: A single access (read/write) to the SR regis-
ter at the beginning of the interrupt routine is the
first step needed to clear all the EFT interrupt
flags. In a second step, the lower bytes of the data
registers must be accessed if the corresponding
flag is set. It is not necessary to access the SR
register between these instructions, but it can
done.
; INTERRUPT ROUTINE EXAMPLE
push R234
spp #28
; Save current page
; Set EFT page
L6:
cp R254,#0
jxz L7
; while E0_SR is not cleared
tm R254,#128
jxz L2
; Check Input Capture 1 flag
; else go to next test
ld r1,R241
; Dummy read to clear IC1LR
; Insert your code here
L2:
L3:
tm R254,#16
jxz L3
; Check Input Capture 2 flag
; else go to next test
ld r1,R243
; Insert your code here
; Dummy read to clear IC2LR
tm R254,#64
jxz L4
; Check Input Compare 1 flag
; else go to next test
ld r1,R249
; Dummy read to clear OC1LR
; Insert your code here
L4:
L5:
tm R254,#8
jxz L5
; Check Input Compare 2 flag
; else go to next test
ld r1,R251
; Dummy read to clear OC1LR
; Insert your code here
tm R254,#32
jxz L6
; Check Input Overflow flag
; else go to next test
ld r1,R245
; Dummy read to clear Overflow flag
; Insert your code here
jx L6
L7:
pop R234
; Restore current page
iret
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
10.3.5 Register Description
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
R241 - Read Only
Register Page: 28
Each Timer is associated with three control and
one status registers, and with six pairs of data reg-
isters (16-bit values) relating to the two input cap-
tures, the two output compares, the counter and
the alternate counter.
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
Notes:
7
0
1. In the register description on the following pag-
es, register and page numbers are given using the
example of Timer 0. On devices with more than
one timer, refer to the device register map for the
adresses and page numbers.
MSB
LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
2. To work correctly with register pairs, it is strong-
ly recommended to use single byte instructions.
Do not use word instructions to access any of the
16-bit registers.
R242 - Read Only
Register Page: 28
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
R240 - Read Only
Register Page: 28
7
0
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
MSB
LSB
7
0
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
MSB
LSB
R243 - Read Only
Register Page: 28
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
COUNTER HIGH REGISTER (CHR)
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
R244 - Read Only
Register Page: 28
Reset Value: 1111 1111 (FFh)
R246 - Read Only
Register Page: 28
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
COUNTER LOW REGISTER (CLR)
R245 - Read/Write
Register Page: 28
Reset Value: 1111 1100 (FCh)
R247 - Read/Write
Register Page: 28
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in the SR
register.
7
0
7
0
MSB
LSB
MSB
LSB
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EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
R248 - Read/Write
Register Page: 28
Reset Value: 1000 0000 (80h)
R250 - Read/Write
Register Page: 28
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
R249 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
R251 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
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9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
CONTROL REGISTER 1 (CR1)
Bit 4 = FOLV2 Forced Output Compare 2.
0: No effect.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin.
R252 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
7
0
Bit 3 = FOLV1 Forced Output Compare 1.
0: No effect.
1: Forces OLVL1 to be copied to the OCMP1 pin.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt enabling depends on the IC1IE and
IC2IE bits in the CR3 register.
1: An interrupt is generated whenever the ICF1 or
ICF2 bit in the SR register is set. The IC1IE and
IC2IE bits in the CR3 register do not have any
effect in this case.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OC2E is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt generation depends on the OC1IE and
OC2IE bits in the CR3 register.
1: An interrupt is generated whenever the OCF1 or
OCF2 bit in the SR register is set. The OC1IE
and OC2IE bits in the CR3 rgister do not have
any effect in this case.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
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9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
R253 - Read/Write
Register Page: 28
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bits 3:2 = CC[1:0] Clock Control.
The value of the timer clock depends on these bits:
Bit 7 = OC1E Output Compare 1 Enable.
0: Output Compare 1 function is enabled, but the
OCMP1 pin is a general I/O.
Table 36. Clock Control Bits
1: Output Compare 1 function is enabled, the
OCMP1 pin is dedicated to the Output Compare
1 capability of the timer.
CC1
CC0
Timer Clock
INTCLK / 4
INTCLK / 2
INTCLK / 8
External Clock
0
0
1
1
0
1
0
1
Bit 6 = OC2E Output Compare 2 Enable.
0: Output Compare 2 function is enabled, but the
OCMP2 pin is a general I/O.
1: Output Compare 2 function is enabled, the
OCMP2 pin is dedicated to the Output Compare
2 capability of the timer.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: A rising edge triggers the capture.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
free running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
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9
EXTENDED FUNCTION TIMER (EFT)
CONTROL REGISTER 3 (CR3)
EXTENDED FUNCTION TIMER (Cont’d)
STATUS REGISTER (SR)
R254 - Read Only
R255 - Read/Write
Register Page: 28
Register Page: 28
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
7
0
0
0
IC1IE OC1IE IC2IE OC2IE
0
0
0
EFTIS
ICF1 OCF1 TOF ICF2 OCF2
0
0
Bit 7 = IC1IE Input Capture1 interrupt enable
Bit 7 = ICF1 Input Capture Flag 1.
This bit is not significant if the ICIE bit in the CR1
register is set.
0: ICAP1 interrupt disabled
1: ICAP1 interrupt enabled
0: No input capture (reset value).
1: An input capture has occurred. To clear this bit,
first read the SR register, then read or write the
low byte of the IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 6 = OC1IE output compare 1 interrupt enable
This bit is not significant if the OCIE bit in the CR1
register is set.
0: OCMP1 interrupt disabled
1: OCMP1 interrupt enabled
Bit 5 = IC2IE input capture 2 interrupt enable
This bit is not significant if the ICIE bit in the CR1
register is set.
0: ICAP2 interrupt disabled
1: ICAP2 interrupt enabled
Bit 5 = TOF Timer Overflow.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Bit 4= OC2IE output compare 2 interrupt enable
Note: Reading or writing the ACLR register does
not clear TOF.
This bit is not significant if the OCIE bit in the CR1
register is set.
0: OCMP2 interrupt disabled
1: OCMP2 interrupt enabled
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred. To clear this bit,
first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register.
Bits 3:1 = Reserved, must be kept cleared.
Bit 0 = EFTIS Global Timer Interrupt Selection.
0: Select External interrupt.
1: Select Global Timer Interrupt.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 2:0 = Reserved, forced by hardware to 0.
185/426
9
EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Table 37. Extended Function Timer Register Map
Address
(Dec.)
Register
Name
7
6
5
4
3
2
1
0
IC1HR
MSB
x
LSB
x
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
Reset Value
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
1
0
1
0
0
0
0
0
IC1LR
MSB
x
LSB
x
Reset Value
IC2HR
MSB
x
LSB
x
Reset Value
IC2LR
MSB
x
LSB
x
Reset Value
CHR
MSB
1
LSB
1
Reset Value
CLR
MSB
1
LSB
0
Reset Value
ACHR
MSB
1
LSB
1
Reset Value
ACLR
MSB
1
LSB
0
Reset Value
OC1HR
MSB
1
LSB
0
Reset Value
OC1LR
MSB
0
LSB
0
Reset Value
OC2HR
MSB
1
LSB
0
Reset Value
OC2LR
MSB
0
LSB
0
Reset Value
CR1
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Reset Value
CR2
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Reset Value
SR
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
-
-
-
Reset Value
0
0
0
CR3
IC1IE
0
OC1IE
0
IC2IE
0
OC2IE
0
-
-
-
EFTIS
0
Reset Value
0
0
0
186/426
9
MULTIFUNCTION TIMER (MFT)
10.4 MULTIFUNCTION TIMER (MFT)
10.4.1 Introduction
– 1 input capture, 1 counter reload and 2 inde-
pendent output compares.
The Multifunction Timer (MFT) peripheral offers
powerful timing capabilities and features 12 oper-
ating modes, including automatic PWM generation
and frequency measurement.
– 2 alternate autoreloads and 2 independent out-
put compares.
– 2 alternate captures on the same external line
and 2 independent output compares at a fixed
repetition rate.
The MFT comprises a 16-bit Up/Down counter
driven by an 8-bit programmable prescaler. The in-
put clock may be INTCLK/3 or an external source.
The timer features two 16-bit Comparison Regis-
ters, and two 16-bit Capture/Load/Reload Regis-
ters. Two input pins and two alternate function out-
put pins are available.
When two MFTs are present in an ST9 device, a
combined operating mode is available.
An internal On-Chip Event signal can be used on
some devices to control other on-chip peripherals.
The two external inputs may be individually pro-
grammed to detect any of the following:
Several functional configurations are possible, for
instance:
– rising edges
– 2 input captures on separate external lines, and
2 independent output compare functions with the
counter in free-running mode, or 1 output com-
pare at a fixed repetition rate.
– falling edges
– both rising and falling edges
Figure 101. MFT Simplified Block Diagram
187/426
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
The configuration of each input is programmed in
the Input Control Register.
synchronise another on-chip peripheral. Five
maskable interrupt sources referring to an End Of
Count condition, 2 input captures and 2 output
compares, can generate 3 different interrupt re-
quests (with hardware fixed priority), pointing to 3
interrupt routine vectors.
Each of the two output pins can be driven from any
of three possible sources:
– Compare Register 0 logic
– Compare Register 1 logic
– Overflow/Underflow logic
Two independent DMA channels are available for
rapid data transfer operations. Each DMA request
(associated with a capture on the REG0R register,
or with a compare on the CMP0R register) has pri-
ority over an interrupt request generated by the
same source.
Each of these three sources can cause one of the
following four actions, independently, on each of
the two outputs:
– Nop, Set, Reset, Toggle
A SWAP mode is also available to allow high
speed continuous transfers (see Interrupt and
DMA chapter).
In addition, an additional On-Chip Event signal can
be generated by two of the three sources men-
tioned above, i.e. Over/Underflow event and Com-
pare 0 event. This signal can be used internally to
Figure 102. Detailed Block Diagram
188/426
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.2 Functional Description
which may be programmed to respond to the rising
edge, the falling edge or both, by programming
bits A0-A1 and B0-B1 in T_ICR.
The MFT operating modes are selected by pro-
gramming the Timer Control Register (TCR) and
the Timer Mode Register (TMR).
In One Shot and Triggered Mode, every trigger
event arriving before an End Of Count, is masked.
In One Shot and Retriggered Mode, every trigger
received while the counter is running, automatical-
ly reloads the counter from REG0R. Triggered/Re-
triggered Mode is set by the REN bit in TMR.
10.4.2.1 Trigger Events
A trigger event may be generated by software (by
setting either the CP0 or the CP1 bits in the
T_FLAGR register) or by an external source which
may be programmed to respond to the rising edge,
the falling edge or both by programming bits A0-
A1 and B0-B1 in the T_ICR register. This trigger
event can be used to perform a capture or a load,
depending on the Timer mode (configured using
the bits in Table 41).
The TxINA input refers to REG0R and the TxINB
input refers to REG1R.
WARNING. If the Triggered Mode is selected
when the counter is in Continuous Mode, every
trigger is disabled, it is not therefore possible to
synchronise the counting cycle by hardware or
software.
An event on the TxINA input or setting the CP0 bit
triggers a capture to, or a load from the REG0R
register (except in Bicapture mode, see Section
10.4.2.11).
10.4.2.5 Gated Mode
In this mode, counting takes place only when the
external gate input is at a logic low level. The se-
lection of TxINA or TxINB as the gate input is
made by programming the IN0-IN3 bits in T_ICR.
An event on the TxINB input or setting the CP1 bit
triggers a capture to, or a load from the REG1R
register.
In addition, in the special case of "Load from
REG0R and monitor on REG1R", it is possible to
use the TxINB input as a trigger for REG0R."
10.4.2.6 Capture Mode
The REG0R and REG1R registers may be inde-
pendently set in Capture Mode by setting RM0 or
RM1 in TMR, so that a capture of the current count
value can be performed either on REG0R or on
REG1R, initiated by software (by setting CP0 or
CP1 in the T_FLAGR register) or by an event on
the external input pins.
10.4.2.2 One Shot Mode
When the counter generates an overflow (in up-
count mode), or an underflow (in down-count
mode), that is to say when an End Of Count condi-
tion is reached, the counter stops and no counter
reload occurs. The counter may only be restarted
by an external trigger on TxINA or B or a by soft-
ware trigger on CP0 only. One Shot Mode is en-
tered by setting the CO bit in TMR.
WARNING. Care should be taken when two soft-
ware captures are to be performed on the same
register. In this case, at least one instruction must
be present between the first CP0/CP1 bit set and
the subsequent CP0/CP1 bit reset instructions.
10.4.2.3 Continuous Mode
10.4.2.7 Up/Down Mode
Whenever the counter reaches an End Of Count
condition, the counting sequence is automatically
restarted and the counter is reloaded from REG0R
(or from REG1R, when selected in Biload Mode).
Continuous Mode is entered by resetting the C0 bit
in TMR.
The counter can count up or down depending on
the state of the UDC bit (Up/Down Count) in TCR,
or on the configuration of the external input pins,
which have priority over UDC (see Input pin as-
signment in T_ICR). The UDCS bit returns the
counter up/down current status (see also the Up/
Down Autodiscrimination mode in the Input Pin
Assignment Section).
10.4.2.4 Triggered And Retriggered Modes
A triggered event may be generated by software
(by setting either the CP0 or the CP1 bit in the
T_FLAGR register), or by an external source
189/426
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.2.8 Free Running Mode
The Clear On Capture mode allows direct meas-
urement of delta time between successive cap-
tures on REG0R, while the Clear On Compare
mode allows free running with the possibility of
choosing a maximum count value before overflow
The timer counts continuously (in Up or Down
mode) and the counter value simply overflows or
underflows through FFFFh or zero; there is no End
Of Count condition as such, and no reloading
takes place. This mode is automatically selected
either in Bi-capture mode or by setting register
REG0R for a Capture function (Continuous mode
must also be set). In Autoclear mode, free running
operation can be selected, with the possibility of
16
or underflow which is less than 2 (see Free Run-
ning Mode).
10.4.2.11 Bi-value Mode
Depending on the value of the RM0 bit in TMR, the
Bi-load Mode (RM0 reset) or the Bi-capture Mode
(RM0 set) can be selected as illustrated in Figure
38 below:
16
choosing a maximum count value less than 2
before overflow or underflow (see Autoclear
mode).
Table 38. Bi-value Modes
10.4.2.9 Monitor Mode
When the RM1 bit in TMR is reset, and the timer is
not in Bi-value mode, REG1R acts as a monitor,
duplicating the current up or down counter con-
tents, thus allowing the counter to be read “on the
fly”.
TMR bits
RM1
Timer
Operating Modes
RM0
0
1
BM
1
1
X
X
Bi-Load mode
Bi-Capture Mode
10.4.2.10 Autoclear Mode
A) Biload Mode
A clear command forces the counter either to
0000h or to FFFFh, depending on whether up-
counting or downcounting is selected. The counter
reset may be obtained either directly, through the
CCL bit in TCR, or by entering the Autoclear
Mode, through the CCP0 and CCMP0 bits in TCR.
The Bi-load Mode is entered by selecting the Bi-
value Mode (BM set in TMR) and programming
REG0R as a reload register (RM0 reset in TMR).
At any End Of Count, counter reloading is per-
formed alternately from REG0R and REG1R, (a
low level for BM bit always sets REG0R as the cur-
rent register, so that, after a Low to High transition
of BM bit, the first reload is always from REG0R).
Every capture performed on REG0R (if CCP0 is
set), or every successful compare performed by
CMP0R (if CCMP0 is set), clears the counter and
reloads the prescaler.
190/426
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
Every software or external trigger event on
REG0R performs a reload from REG0R resetting
the Biload cycle. In One Shot mode (reload initiat-
ed by software or by an external trigger), reloading
is always from REG0R.
By loading the Prescaler Register of Timer 1 with
the value 00h the two timers (Timer 0 and Timer 1)
are driven by the same frequency in parallel mode.
In this mode the clock frequency may be divided
16
by a factor in the range from 1 to 2 .
B) Bicapture Mode
10.4.2.13 Autodiscriminator Mode
The Bicapture Mode is entered by selecting the Bi-
value Mode (the BM bit in TMR is set) and by pro-
gramming REG0R as a capture register (the RM0
bit in TMR is set).
The phase difference sign of two overlapping puls-
es (respectively on TxINB and TxINA) generates a
one step up/down count, so that the up/down con-
trol and the counter clock are both external. The
setting of the UDC bit in the TCR register has no
effect in this configuration.
Interrupt generation can be configured as an AND
or OR function of the two Capture events. This is
configured by the A0 bit in the T_FLAGR register.
Figure 103. Parallel Mode Description
Every capture event, software simulated (by set-
ting the CP0 flag) or coming directly from the TxI-
NA input line, captures the current counter value
alternately into REG0R and REG1R. When the
BM bit is reset, REG0R is the current register, so
that the first capture, after resetting the BM bit, is
always into REG0R.
MFT0
COUNTER
INTCLK/3
PRESCALER 0
MFT1
COUNTER
10.4.2.12 Parallel Mode
PRESCALER 1
When two MFTs are present on an ST9 device,
the parallel mode is entered when the ECK bit in
the TMR register of Timer 1 is set. The Timer 1
prescaler input is internally connected to the Timer
0 prescaler output. Timer 0 prescaler input is con-
nected to the system clock line.
Note: MFT 1 is not available on all devices. Refer to
the device block diagram and register map.
191/426
9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3 Input Pin Assignment
– a trigger signal on the TxINA input pin performs
an U/D counter load if RM0 is reset, or an exter-
nal capture if RM0 is set.
The two external inputs (TxINA and TxINB) of the
timer can be individually configured to catch a par-
ticular external event (i.e. rising edge, falling edge,
or both rising and falling edges) by programming
the two relevant bits (A0, A1 and B0, B1) for each
input in the external Input Control Register
(T_ICR).
– a trigger signal on the TxINB input pin always
performs an external capture on REG1R. The
TxINB input pin is disabled when the Bivalue
Mode is set.
Note: For proper operation of the External Input
pins, the following must be observed:
The 16 different functional modes of the two exter-
nal inputs can be selected by programming bits
IN0 - IN3 of the T_ICR, as illustrated in Figure 39
– the minimum external clock/trigger pulse width
must not be less than the system clock (INTCLK)
period if the input pin is programmed as rising or
falling edge sensitive.
Table 39. Input Pin Function
I C Reg.
IN3-IN0 bits
TxINA Input
Function
TxINB Input
Function
not used
Trigger
not used
Trigger
Ext. Clock
not used
Ext. Clock
Trigger
Clock Down
Ext. Clock
Trigger Down
not used
Autodiscr.
Ext. Clock
Trigger
– the minimum external clock/trigger pulse width
must not be less than the prescaler clock period
(INTCLK/3) if the input pin is programmed as ris-
ing and falling edge sensitive (valid also in Auto
discrimination mode).
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
not used
not used
Gate
Gate
not used
Trigger
– the minimum delay between two clock/trigger
pulse active edges must be greater than the
prescaler clock period (INTCLK/3), while the
minimum delay between two consecutive clock/
trigger pulses must be greater than the system
clock (INTCLK) period.
Gate
Trigger
Clock Up
Up/Down
Trigger Up
Up/Down
Autodiscr.
Trigger
– the minimum gate pulse width must be at least
twice the prescaler clock period (INTCLK/3).
– in Autodiscrimination mode, the minimum delay
between the input pin A pulse edge and the edge
of the input pin B pulse, must be at least equal to
the system clock (INTCLK) period.
Ext. Clock
Trigger
Gate
Some choices relating to the external input pin as-
signment are defined in conjunction with the RM0
and RM1 bits in TMR.
– if a number, N, of external pulses must be count-
ed using a Compare Register in External Clock
mode, then the Compare Register must be load-
ed with the value [X +/- (N-1)], where X is the
starting counter value and the sign is chosen de-
pending on whether Up or Down count mode is
selected.
For input pin assignment codes which use the in-
put pins as Trigger Inputs (except for code 1010,
Trigger Up:Trigger Down), the following conditions
apply:
192/426
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3.1 TxINA = I/O - TxINB = I/O
ister was programmed (i.e. a reload or capture).
The prescaler clock is internally generated and the
up/down selection may be made only by software
via the UDC (Software Up/Down) bit in the TCR
register.
Input pins A and B are not used by the Timer. The
counter clock is internally generated and the up/
down selection may be made only by software via
the UDC (Software Up/Down) bit in the TCR regis-
ter.
10.4.3.2 TxINA = I/O - TxINB = Trigger
The signal applied to input pin B acts as a trigger
signal on REG1R register. The prescaler clock is
internally generated and the up/down selection
may be made only by software via the UDC (Soft-
ware Up/Down) bit in the TCR register.
10.4.3.3 TxINA = Gate - TxINB = I/O
The signal applied to input pin A acts as a gate sig-
nal for the internal clock (i.e. the counter runs only
when the gate signal is at a low level). The counter
clock is internally generated and the up/down con-
trol may be made only by software via the UDC
(Software Up/Down) bit in the TCR register.
(*) The timer is in One shot mode and REGOR in
Reload mode
10.4.3.7 TxINA = Gate - TxINB = Ext. Clock
The signal applied to input pin B, gated by the sig-
nal applied to input pin A, acts as external clock for
the prescaler. The up/down control may be made
only by software action through the UDC bit in the
TCR register.
10.4.3.4 TxINA = Gate - TxINB = Trigger
Both input pins A and B are connected to the timer,
with the resulting effect of combining the actions
relating to the previously described configurations.
10.4.3.8 TxINA = Trigger - TxINB = Trigger
10.4.3.5 TxINA = I/O - TxINB = Ext. Clock
The signal applied to input pin A (or B) acts as trig-
ger signal for REG0R (or REG1R), initiating the
action for which the register has been pro-
grammed. The counter clock is internally generat-
ed and the up/down selection may be made only
by software via the UDC (Software Up/Down) bit in
the TCR register.
The signal applied to input pin B is used as the ex-
ternal clock for the prescaler. The up/down selec-
tion may be made only by software via the UDC
(Software Up/Down) bit in the TCR register.
10.4.3.6 TxINA = Trigger - TxINB = I/O
The signal applied to input pin A acts as a trigger
for REG0R, initiating the action for which the reg-
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3.9 TxINA = Clock Up - TxINB = Clock
Down
10.4.3.11 TxINA = Trigger Up - TxINB = Trigger
Down
The edge received on input pin A (or B) performs a
one step up (or down) count, so that the counter
clock and the up/down control are external. Setting
the UDC bit in the TCR register has no effect in
this configuration, and input pin B has priority on
input pin A.
Up/down control is performed through both input
pins A and B. A edge on input pin A sets the up
count mode, while a edge on input pin B (which
has priority on input pin A) sets the down count
mode. The counter clock is internally generated,
and setting the UDC bit in the TCR register has no
effect in this configuration.
10.4.3.10 TxINA = Up/Down - TxINB = Ext Clock
10.4.3.12 TxINA = Up/Down - TxINB = I/O
An High (or Low) level applied to input pin A sets
the counter in the up (or down) count mode, while
the signal applied to input pin B is used as clock for
the prescaler. Setting the UDC bit in the TCR reg-
ister has no effect in this configuration.
An High (or Low) level of the signal applied on in-
put pin A sets the counter in the up (or down) count
mode. The counter clock is internally generated.
Setting the UDC bit in the TCR register has no ef-
fect in this configuration.
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.3.13 Autodiscrimination Mode
ture), while the signal applied to input pin B is used
as the clock for the prescaler.
The phase between two pulses (respectively on in-
put pin B and input pin A) generates a one step up
(or down) count, so that the up/down control and
the counter clock are both external. Thus, if the ris-
ing edge of TxINB arrives when TxINA is at a low
level, the timer is incremented (no action if the ris-
ing edge of TxINB arrives when TxINA is at a high
level). If the falling edge of TxINB arrives when
TxINA is at a low level, the timer is decremented
(no action if the falling edge of TxINB arrives when
TxINA is at a high level).
Setting the UDC bit in the TCR register has no ef-
fect in this configuration.
(*) The timer is in One shot mode and REG0R in
reload mode
10.4.3.15 TxINA = Ext. Clock - TxINB = Trigger
The signal applied to input pin B acts as a trigger,
performing a capture on REG1R, while the signal
applied to input pin A is used as the clock for the
prescaler.
10.4.3.16 TxINA = Trigger - TxINB = Gate
The signal applied to input pin A acts as a trigger
signal on REG0R, initiating the action for which the
register was programmed (i.e. a reload or cap-
ture), while the signal applied to input pin B acts as
a gate signal for the internal clock (i.e. the counter
runs only when the gate signal is at a low level).
10.4.3.14 TxINA = Trigger - TxINB = Ext. Clock
The signal applied to input pin A acts as a trigger
signal on REG0R, initiating the action for which the
register was programmed (i.e. a reload or cap-
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.4 Output Pin Assignment
OACR is programmed with TxOUTA preset to “0”,
OUF sets TxOUTA, CM0 resets TxOUTA and
CM1 does not affect the output.
OBCR is programmed with TxOUTB preset to “0”,
OUF sets TxOUTB, CM1 resets TxOUTB while
CM0 does not affect the output.
Two external outputs are available when pro-
grammed as Alternate Function Outputs of the I/O
pins.
Two registers Output A Control Register (OACR)
and Output B Control Register (OBCR) define the
driver for the outputs and the actions to be per-
formed.
OACR = [101100X0]
OBCR = [111000X0]
Each of the two output pins can be driven from any
of the three possible sources:
T0OUTA
– Compare Register 0 event logic
– Compare Register 1 event logic
– Overflow/Underflow event logic.
OUF COMP0 OUF COMP0
COMP1
COMP1
Each of these three sources can cause one of the
following four actions on any of the two outputs:
T0OUTB
OUF
OUF
– Nop
– Set
For a configuration where TxOUTA is driven by the
Over/Underflow, by Compare 0 and by Compare
1; TxOUTB is driven by both Compare 0 and Com-
pare 1. OACR is programmed with TxOUTA pre-
set to “0”. OUF toggles Output 0, as do CM0 and
CM1. OBCR is programmed with TxOUTB preset
to “1”. OUF does not affect the output; CM0 resets
TxOUTB and CM1 sets it.
– Reset
– Toggle
Furthermore an On Chip Event signal can be driv-
en by two of the three sources: the Over/Under-
flow event and Compare 0 event by programming
the CEV bit of the OACR register and the OEV bit
of OBCR register respectively. This signal can be
used internally to synchronise another on-chip pe-
ripheral.
OACR = [010101X0]
Output Waveforms
OBCR = [100011X1]
COMP1 COMP1
Depending on the programming of OACR and OB-
CR, the following example waveforms can be gen-
erated on TxOUTA and TxOUTB pins.
T0OUTA
OUF
COMP0
OUF
COMP0
For a configuration where TxOUTA is driven by the
Over/Underflow (OUF) and the Compare 0 event
(CM0), and TxOUTB is driven by the Over/Under-
flow and Compare 1 event (CM1):
COMP1 COMP1
T0OUTB
COMP0
COMP0
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
For a configuration where TxOUTA is driven by the
Over/Underflow and by Compare 0, and TxOUTB
is driven by the Over/Underflow and by Compare
1. OACR is programmed with TxOUTA preset to
“0”. OUF sets TxOUTA while CM0 resets it, and
CM1 has no effect. OBCR is programmed with Tx-
OUTB preset to “1”. OUF toggles TxOUTB, CM1
sets it and CM0 has no effect.
Output Waveform Samples In Biload Mode
TxOUTA is programmed to monitor the two time
intervals, t1 and t2, of the Biload Mode, while Tx-
OUTB is independent of the Over/Underflow and
is driven by the different values of Compare 0 and
Compare 1. OACR is programmed with TxOUTA
preset to “0”. OUF toggles the output and CM0 and
CM1 do not affect TxOUTA. OBCR is programmed
with TxOUTB preset to “0”. OUF has no effect,
while CM1 resets TxOUTB and CM0 sets it.
Depending on the CM1/CM0 values, three differ-
ent sample waveforms have been drawn based on
the above mentioned configuration of OBCR. In
the last case, with a different programmed value of
OBCR, only Compare 0 drives TxOUTB, toggling
the output.
For a configuration where TxOUTA is driven by the
Over/Underflow and by Compare 0, and TxOUTB
is driven by Compare 0 and 1. OACR is pro-
grammed with TxOUTA preset to “0”. OUF sets
TxOUTA, CM0 resets it and CM1 has no effect.
OBCR is programmed with TxOUTB preset to “0”.
OUF has no effect, CM0 sets TxOUTB and CM1
toggles it.
OACR = [101100X0]
OBCR = [000111X0]
T0OUTA
OUFCOMP0OUFCOMP0
COMP1 COMP1
T0OUTB
COMP0
COMP0
Note (*) Depending on the CMP1R/CMP0R values
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.5 Interrupt and DMA
10.4.5.1 Timer Interrupt
The two DMA End of Block interrupts are inde-
pendently enabled by the CP0I and CM0I Interrupt
mask bits in the IDMR register.
The timer has 5 different Interrupt sources, be-
longing to 3 independent groups, which are as-
signed to the following Interrupt vectors:
10.4.5.3 DMA Pointers
The 6 programmable most significant bits of the
DMA Counter Pointer Register (DCPR) and of the
DMA Address Pointer Register (DAPR) are com-
mon to both channels (Comp0 and Capt0). The
Comp0 and Capt0 Address Pointers are mapped
as a pair in the Register File, as are the Comp0
and Capt0 DMA Counter pair.
Table 40. Timer Interrupt Structure
Interrupt Source
Vector Address
COMP 0
COMP 1
xxxx x110
CAPT 0
CAPT 1
xxxx x100
xxxx x000
In order to specify either the Capt0 or the Comp0
pointers, according to the channel being serviced,
the Timer resets address bit 1 for CAPT0 and sets
it for COMP0, when the D0 bit in the DCPR regis-
ter is equal to zero (Word address in Register
File). In this case (transfers between peripheral
registers and memory), the pointers are split into
two groups of adjacent Address and Counter pairs
respectively.
Overflow/Underflow
The three least significant bits of the vector pointer
address represent the relative priority assigned to
each group, where 000 represents the highest pri-
ority level. These relative priorities are fixed by
hardware, according to the source which gener-
ates the interrupt request. The 5 most significant
bits represent the general priority and are pro-
grammed by the user in the Interrupt Vector Reg-
ister (T_IVR).
For peripheral register to register transfers (select-
ed by programming “1” into bit 0 of the DCPR reg-
ister), only one pair of pointers is required, and the
pointers are mapped into one group of adjacent
positions.
Each source can be masked by a dedicated bit in
the Interrupt/DMA Mask Register (IDMR) of each
timer, as well as by a global mask enable bit (ID-
MR.7) which masks all interrupts.
The DMA Address Pointer Register (DAPR) is not
used in this case, but must be considered re-
served.
If an interrupt request (CM0 or CP0) is present be-
fore the corresponding pending bit is reset, an
overrun condition occurs. This condition is flagged
in two dedicated overrun bits, relating to the
Comp0 and Capt0 sources, in the Timer Flag Reg-
ister (T_FLAGR).
Figure 104. Pointer Mapping for Transfers
between Registers and Memory
10.4.5.2 Timer DMA
Register File
Two Independent DMA channels, associated with
Comp0 and Capt0 respectively, allow DMA trans-
fers from Register File or Memory to the Comp0
Register, and from the Capt0 Register to Register
File or Memory). If DMA is enabled, the Capt0 and
Comp0 interrupts are generated by the corre-
sponding DMA End of Block event. Their priority is
set by hardware as follows:
YYYYYY11(l)
YYYYYY10(h)
YYYYYY01(l)
YYYYYY00(h)
Address
Pointers
Comp0 16 bit
Addr Pointer
Capt0 16 bit
Addr Pointer
XXXXXX11(l)
XXXXXX10(h)
XXXXXX01(l)
XXXXXX00(h)
DMA
Counters
Comp0 DMA
16 bit Counter
– Compare 0 Destination
– Capture 0 Source
—
Lower Priority
—
Higher Priority
Capt0 DMA
16 bit Counter
The two DMA request sources are independently
maskable by the CP0D and CM0D DMA Mask bits
in the IDMR register.
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
Figure 105. Pointer Mapping for Register to
Register Transfers
10.4.5.5 DMA Swap Mode
After a complete data table transfer, the transac-
tion counter is reset and an End Of Block (EOB)
condition occurs, the block transfer is completed.
Register File
The End Of Block Interrupt routine must at this
point reload both address and counter pointers of
the channel referred to by the End Of Block inter-
rupt source, if the application requires a continu-
ous high speed data flow. This procedure causes
speed limitations because of the time required for
the reload routine.
8 bit Counter
XXXXXX11
XXXXXX10
XXXXXX01
XXXXXX00
Compare 0
Capture 0
8 bit Addr Pointer
8 bit Counter
8 bit Addr Pointer
The SWAP feature overcomes this drawback, al-
lowing high speed continuous transfers. Bit 2 of
the DMA Counter Pointer Register (DCPR) and of
the DMA Address Pointer Register (DAPR), tog-
gles after every End Of Block condition, alternately
providing odd and even address (D2-D7) for the
pair of pointers, thus pointing to an updated pair,
after a block has been completely transferred. This
allows the User to update or read the first block
and to update the pointer values while the second
is being transferred. These two toggle bits are soft-
ware writable and readable, mapped in DCPR bit 2
for the CM0 channel, and in DAPR bit 2 for the
CP0 channel (though a DMA event on a channel,
in Swap mode, modifies a field in DAPR and
DCPR common to both channels, the DAPR/
DCPR content used in the transfer is always the bit
related to the correct channel).
10.4.5.4 DMA Transaction Priorities
Each Timer DMA transaction is a 16-bit operation,
therefore two bytes must be transferred sequen-
tially, by means of two DMA transfers. In order to
speed up each word transfer, the second byte
transfer is executed by automatically forcing the
peripheral priority to the highest level (000), re-
gardless of the previously set level. It is then re-
stored to its original value after executing the
transfer. Thus, once a request is being serviced,
its hardware priority is kept at the highest level re-
gardless of the other Timer internal sources, i.e.
once a Comp0 request is being serviced, it main-
tains a higher priority, even if a Capt0 request oc-
curs between the two byte transfers.
SWAP mode can be enabled by the SWEN bit in
the IDCR Register.
WARNING: Enabling SWAP mode affects both
channels (CM0 and CP0).
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.5.6 DMA End Of Block Interrupt Routine
– Return.
WARNING: The EOB bits are read/write only for
test purposes. Writing a logical “1” by software
(when the SWEN bit is set) will cause a spurious
interrupt request. These bits are normally only re-
set by software.
An interrupt request is generated after each block
transfer (EOB) and its priority is the same as that
assigned in the usual interrupt request, for the two
channels. As a consequence, they will be serviced
only when no DMA request occurs, and will be
subject to a possible OUF Interrupt request, which
has higher priority.
10.4.5.7 DMA Software Protection
A second EOB condition may occur before the first
EOB routine is completed, this would cause a not
yet updated pointer pair to be addressed, with con-
sequent overwriting of memory. To prevent these
errors, a protection mechanism is provided, such
that the attempted setting of the EOB bit before it
has been reset by software will cause the DMA
mask on that channel to be reset (DMA disabled),
thus blocking any further DMA operation. As
shown above, this mask bit should always be
checked in each EOB routine, to ensure that all
DMA transfers are properly served.
The following is a typical EOB procedure (with
swap mode enabled):
– Test Toggle bit and Jump.
– Reload Pointers (odd or even depending on tog-
gle bit status).
– Reset EOB bit: this bit must be reset only after
the old pair of pointers has been restored, so
that, if a new EOB condition occurs, the next pair
of pointers is ready for swapping.
– Verify the software protection condition (see
Section 10.4.5.7).
10.4.6 Register Description
– Read the corresponding Overrun bit: this con-
firms that no DMA request has been lost in the
meantime.
Note: In the register description on the following
pages, register and page numbers are given using
the example of Timer 0. On devices with more
than one timer, refer to the device register map for
the adresses and page numbers.
– Reset the corresponding pending bit.
– Reenable DMA with the corresponding DMA
mask bit (must always be done after resetting
the pending bit)
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
CAPTURE LOAD 0 HIGH REGISTER (REG0HR)
COMPARE 0 HIGH REGISTER (CMP0HR)
R240 - Read/Write
Register Page: 10
Reset value: undefined
R244 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
7
0
R15 R14 R13 R12 R11 R10
R9
R8
R15 R14 R13 R12 R11 R10
R9
R8
This register is used to capture values from the
Up/Down counter or load preset values (MSB).
This register is used to store the MSB of the 16-bit
value to be compared to the Up/Down counter
content.
CAPTURE LOAD 0 LOW REGISTER (REG0LR)
COMPARE 0 LOW REGISTER (CMP0LR)
R241 - Read/Write
Register Page: 10
Reset value: undefined
R245 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
7
0
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
This register is used to capture values from the
Up/Down counter or load preset values (LSB).
This register is used to store the LSB of the 16-bit
value to be compared to the Up/Down counter
content.
CAPTURE LOAD 1 HIGH REGISTER (REG1HR)
R242 - Read/Write
Register Page: 10
COMPARE 1 HIGH REGISTER (CMP1HR)
Reset value: undefined
R246 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
R15 R14 R13 R12 R11 R10
R9
R8
7
0
R15 R14 R13 R12 R11 R10
R9
R8
This register is used to capture values from the
Up/Down counter or load preset values (MSB).
This register is used to store the MSB of the 16-bit
value to be compared to the Up/Down counter
content.
CAPTURE LOAD 1 LOW REGISTER (REG1LR)
R243 - Read/Write
Register Page: 10
COMPARE 1 LOW REGISTER (CMP1LR)
Reset value: undefined
R247 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
R7
R6
R5
R4
R3
R2
R1
R0
7
0
This register is used to capture values from the
Up/Down counter or load preset values (LSB).
R7
R6
R5
R4
R3
R2
R1
R0
This register is used to store the LSB of the 16-bit
value to be compared to the Up/Down counter
content.
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
TIMER CONTROL REGISTER (TCR)
R248 - Read/Write
Bit 3 = UDC: Up/Down software selection.
If the direction of the counter is not fixed by hard-
ware (TxINA and/or TxINB pins, see par. 10.3) it
can be controlled by software using the UDC bit.
0: Down counting
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
1: Up counting
CEN CCP0 CCMP0 CCL UDC UDCS OF0 CS
Bit 2 = UDCS: Up/Down count status.
This bit is read only and indicates the direction of
the counter.
Bit 7 = CEN: Counter enable.
This bit is ANDed with the Global Counter Enable
bit (GCEN) in the CICR register (R230). The
GCEN bit is set after the Reset cycle.
0: Down counting
1: Up counting
0: Stop the counter and prescaler
1: Start the counter and prescaler (without reload).
Bit 1 = OF0: OVF/UNF state.
This bit is read only.
0: No overflow or underflow occurred
1: Overflow or underflow occurred during a Cap-
ture on Register 0
Note: Even if CEN=0, capture and loading will
take place on a trigger event.
Bit 6 = CCP0: Clear on capture.
0: No effect
1: Clear the counter and reload the prescaler on a
REG0R or REG1R capture event
Bit 0 = CS Counter Status.
This bit is read only and indicates the status of the
counter.
Bit 5 = CCMP0: Clear on Compare.
0: No effect
1: Clear the counter and reload the prescaler on a
CMP0R compare event
0: Counter halted
1: Counter running
Bit 4 = CCL: Counter clear.
This bit is reset by hardware after being set by
software (this bit always returns “0” when read).
0: No effect
1: Clear the counter without generating an inter-
rupt request
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
TIMER MODE REGISTER (TMR)
R249 - Read/Write
Bit 3 = RM0: REG0R mode.
This bit works together with the BM and RM1 bits
to select the timer operating mode. Refer to Table
41.
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
Table 41. Timer Operating Modes
TMR Bits
OE1 OE0 BM RM1 RM0 ECK REN C0
Timer Operating Modes
BM RM1 RM0
1
1
x
0
1
Biload mode
Bit 7 = OE1: Output 1 enable.
0: Disable the Output 1 (TxOUTB pin) and force it
high.
1: Enable the Output 1 (TxOUTB pin)
The relevant I/O bit must also be set to Alternate
Function
x
Bicapture mode
Load from REG0R and Monitor on
REG1R
0
0
0
1
0
0
Load from REG0R and Capture on
REG1R
Capture on REG0R and Monitor on
REG1R
0
0
0
1
1
1
Bit 6 = OE0: Output 0 enable.
0: Disable the Output 0 (TxOUTA pin) and force it
high
Capture on REG0R and REG1R
1: Enable the Output 0 (TxOUTA pin).
The relevant I/O bit must also be set to Alternate
Function
Bit 2 = ECK Timer clock control.
0: The prescaler clock source is selected depend-
ing on the IN0 - IN3 bits in the T_ICR register
1: Enter Parallel mode (for Timer 1 and Timer 3
only, no effect for Timer 0 and 2). See Section
10.4.2.12.
Bit 5 = BM: Bivalue mode.
This bit works together with the RM1 and RM0 bits
to select the timer operating mode (see Table 41).
0: Disable bivalue mode
Bit 1 = REN: Retrigger mode.
0: Enable retriggerable mode
1: Disable retriggerable mode
1: Enable bivalue mode
Bit 4 = RM1: REG1R mode.
This bit works together with the BM and RM0 bits
to select the timer operating mode. Refer to Table
41.
Bit 0 = CO: Continous/One shot mode.
0: Continuous mode (with autoreload on End of
Count condition)
Note: This bit has no effect when the Bivalue
Mode is enabled (BM=1).
1: One shot mode
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
EXTERNAL INPUT CONTROL REGISTER
(T_ICR)
Bits 1:0 = B[0:1]: TxINB Pin event.
These bits are set and cleared by software.
R250 - Read/Write
B0
B1
TxINB Pin Event
No operation
Register Page: 10
Reset value: 0000 0000 (00h)
0
0
1
1
0
1
0
1
Falling edge sensitive
Rising edge sensitive
Rising and falling edges
7
0
IN3
IN2
IN1
IN0
A0
A1
B0
B1
Bits 7:4 = IN[3:0]: Input pin function.
These bits are set and cleared by software.
PRESCALER REGISTER (PRSR)
R251 - Read/Write
TxINA
Pin Function
TxINB Input
Pin Function
IN[3:0] bits
Register Page: 10
Reset value: 0000 0000 (00h)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
not used
not used
Gate
Gate
not used
Trigger
not used
Trigger
not used
Trigger
7
0
P7
P6
P5
P4
P3
P2
P1
P0
Ext. Clock
not used
Ext. Clock
Trigger
Clock Down
Ext. Clock
Trigger Down
not used
Autodiscr.
Ext. Clock
Trigger
This register holds the preset value for the 8-bit
prescaler. The PRSR content may be modified at
any time, but it will be loaded into the prescaler at
the following prescaler underflow, or as a conse-
quence of a counter reload (either by software or
upon external request).
Gate
Trigger
Clock Up
Up/Down
Trigger Up
Up/Down
Autodiscr.
Trigger
Following a RESET condition, the prescaler is au-
tomatically loaded with 00h, so that the prescaler
divides by 1 and the maximum counter clock is
generated (Crystal oscillator clock frequency divid-
ed by 6 when MODER.5 = DIV2 bit is set).
Ext. Clock
Trigger
Gate
The binary value programmed in the PRSR regis-
ter is equal to the divider value minus one. For ex-
ample, loading PRSR with 24 causes the prescal-
er to divide by 25.
Bits 3:2 = A[0:1]: TxINA Pin event.
These bits are set and cleared by software.
A0
A1
TxINA Pin Event
No operation
0
0
1
1
0
1
0
1
Falling edge sensitive
Rising edge sensitive
Rising and falling edges
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
OUTPUT A CONTROL REGISTER (OACR)
R252 - Read/Write
Table 42. Output A Action Bits
Action on TxOUTA pin when an xx
event occurs
Register Page: 10
xxE0
xxE1
Reset value: 0000 0000
0
0
1
1
0
1
0
1
Set
7
0
Toggle
Reset
NOP
C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P
Bits 7:6 = C0E[0:1]: COMP0 action bits.
Notes:
These bits are set and cleared by software. They
configure the action to be performed on the Tx-
OUTA pin when a successful compare of the
CMP0R register occurs. Refer to Table 42 for the
list of actions that can be configured.
– xx stands for C0, C1 or OU.
– Whenever more than one event occurs simulta-
neously, Action bit 0 will be the result of ANDing
Action bit 0 of all simultaneous events and Action
bit 1 will be the result of ANDing Action bit 1 of all
simultaneous events.
Bits 5:4 = C1E[0:1]: COMP1 action bits.
These bits are set and cleared by software. They
configure the action to be performed on the Tx-
OUTA pin when a successful compare of the
CMP1R register occurs. Refer to Table 42 for the
list of actions that can be configured.
Bit 1 = CEV: On-Chip event on CMP0R.
This bit is set and cleared by software.
0: No action
1: A successful compare on CMP0R activates the
on-chip event signal (a single pulse is generat-
ed)
Bits 3:2 = OUE[0:1]: OVF/UNF action bits.
These bits are set and cleared by software. They
configure the action to be performed on the Tx-
OUTA pin when an Overflow or Underflow of the
U/D counter occurs. Refer to Table 42 for the list of
actions that can be configured.
Bit 0 = OP: TxOUTA preset value.
This bit is set and cleared by software and by hard-
ware. The value of this bit is the preset value of the
TxOUTA pin. Reading this bit returns the current
state of the TxOUTA pin (useful when it is selected
in toggle mode).
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
OUTPUT B CONTROL REGISTER (OBCR)
R253 - Read/Write
Table 43. Output B Action Bits
Action on the TxOUTB pin when an
xx event occurs
Register Page: 10
xxE0
xxE1
Reset value: 0000 0000 (00h)
0
0
1
1
0
1
0
1
Set
7
0
Toggle
Reset
NOP
C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 OEV 0P
Bits 7:6 = C0E[0:1]: COMP0 Action Bits.
Notes:
These bits are set and cleared by software. They
configure the type of action to be performed on the
TxOUTB output pin when successful compare of
the CMP0R register occurs. Refer to Table 43 for
the list of actions that can be configured.
– xx stands for C0, C1 or OU.
– Whenever more than one event occurs simulta-
neously, Action Bit 0 will be the result of ANDing
Action Bit 0 of all simultaneous events and Action
Bit 1 will be the result of ANDing Action Bit 1 of
all simultaneous events.
Bits 5:4 = C0E[0:1]: COMP1 Action Bits.
These bits are set and cleared by software. They
configure the type of action to be performed on the
TxOUTB output pin when a successful compare of
the CMP1R register occurs. Refer to Table 43 for
the list of actions that can be configured.
Bit 1 = OEV: On-Chip event on OVF/UNF.
This bit is set and cleared by software.
0: No action
1: An underflow/overflow activates the on-chip
event signal (a single pulse is generated)
Bits 3:2 = OUE[0:1]: OVF/UNF Action Bits.
These bits are set and cleared by software.They
configure the type of action to be performed on the
TxOUTB output pin when an Overflow or Under-
flow on the U/D counter occurs. Refer to Table 43
for the list of actions that can be configured.
Bit 0 = OP: TxOUTB preset value.
This bit is set and cleared by software and by hard-
ware. The value of this bit is the preset value of the
TxOUTB pin. Reading this bit returns the current
state of the TxOUTB pin (useful when it is selected
in toggle mode).
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
FLAG REGISTER (T_FLAGR)
R254 - Read/Write
GTIEN and CM1I bits in the IDMR register are set.
The CM1 bit is cleared by software.
0: No Compare 1 event
Register Page: 10
Reset value: 0000 0000 (00h)
1: Compare 1 event occurred
7
0
Bit 3 = OUF: Overflow/Underflow.
CP0 CP1 CM0 CM1 OUF OCP0 OCM0 A0
This bit is set by hardware after a counter Over/
Underflow condition. An interrupt is generated if
GTIEN and OUI=1 in the IDMR register. The OUF
bit is cleared by software.
Bit 7 = CP0: Capture 0 flag.
This bit is set by hardware after a capture on
REG0R register. An interrupt is generated de-
pending on the value of the GTIEN, CP0I bits in
the IDMR register and the A0 bit in the T_FLAGR
register. The CP0 bit must be cleared by software.
Setting by software acts as a software load/cap-
ture to/from the REG0R register.
0: No counter overflow/underflow
1: Counter overflow/underflow
Bit 2 = OCP0: Overrun on Capture 0.
This bit is set by hardware when more than one
INT/DMA requests occur before the CP0 flag is
cleared by software or whenever a capture is sim-
ulated by setting the CP0 flag by software. The
OCP0 flag is cleared by software.
0: No Capture 0 event
1: Capture 0 event occurred
0: No capture 0 overrun
1: Capture 0 overrun
Bit 6 = CP1: Capture 1 flag.
This bit is set by hardware after a capture on
REG1R register. An interrupt is generated de-
pending on the value of the GTIEN, CP0I bits in
the IDMR register and the A0 bit in the T_FLAGR
register. The CP1 bit must be cleared by software.
Setting by software acts as a capture event on the
REG1R register, except when in Bicapture mode.
0: No Capture 1 event
Bit 1 = OCM0: Overrun on compare 0.
This bit is set by hardware when more than one
INT/DMA requests occur before the CM0 flag is
cleared by software.The OCM0 flag is cleared by
software.
0: No compare 0 overrun
1: Capture 1 event occurred
1: Compare 0 overrun
Bit 5 = CM0: Compare 0 flag.
Bit 0 = A0: Capture interrupt function.
This bit is set and cleared by software.
0: Configure the capture interrupt as an OR func-
tion of REG0R/REG1R captures
1: Configure the capture interrupt as an AND func-
tion of REG0R/REG1R captures
This bit is set by hardware after a successful com-
pare on the CMP0R register. An interrupt is gener-
ated if the GTIEN and CM0I bits in the IDMR reg-
ister are set. The CM0 bit is cleared by software.
0: No Compare 0 event
1: Compare 0 event occurred
Note: When A0 is set, both CP0I and CP1I in the
IDMR register must be set to enable both capture
interrupts.
Bit 4 = CM1: Compare 1 flag.
This bit is set after a successful compare on
CMP1R register. An interrupt is generated if the
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
INTERRUPT/DMA MASK REGISTER (IDMR)
R255 - Read/Write
Bit 1 = CM1I: Compare 1 Interrupt mask.
This bit is set and cleared by software.
0: Disable compare on CMP1R interrupt
1: Enable compare on CMP1R interrupt
Register Page: 10
Reset value: 0000 0000 (00h)
7
0
GTIEN CP0D CP0I CP1I CM0D CM0I CM1I OUI
Bit 0 = OUI:
Overflow/Underflow interrupt mask.
This bit is set and cleared by software.
0: Disable Overflow/Underflow interrupt
1: Enable Overflow/Underflow interrupt
Bit 7 = GTIEN: Global timer interrupt enable.
This bit is set and cleared by software.
0: Disable all Timer interrupts
1: Enable all timer Timer Interrupts from enabled
sources
DMA COUNTER POINTER REGISTER (DCPR)
R240 - Read/Write
Register Page: 9
Reset value: undefined
Bit 6 = CP0D: Capture 0 DMA mask.
This bit is set by software to enable a Capt0 DMA
transfer and cleared by hardware at the end of the
block transfer.
0: Disable capture on REG0R DMA
1: Enable capture on REG0R DMA
7
0
DMA REG/
SRCE MEM
DCP7 DCP6 DCP5 DCP4 DCP3 DCP2
Bits 7:2 = DCP[7:2]: MSBs of DMA counter regis-
ter address.
These are the most significant bits of the DMA
counter register address programmable by soft-
ware. The DCP2 bit may also be toggled by hard-
ware if the Timer DMA section for the Compare 0
channel is configured in Swap mode.
Bit 5 = CP0I: Capture 0 interrupt mask.
0: Disable capture on REG0R interrupt
1: Enable capture on REG0R interrupt (or Capt0
DMA End of Block interrupt if CP0D=1)
Bit 4 = CP1I: Capture 1 interrupt mask.
This bit is set and cleared by software.
0: Disable capture on REG1R interrupt
1: Enable capture on REG1R interrupt
Bit 1 = DMA-SRCE: DMA source selection.
This bit is set and cleared by hardware.
0: DMA source is a Capture on REG0R register
1: DMA destination is a Compare on CMP0R reg-
ister
Bit 3 = CM0D: Compare 0 DMA mask.
This bit is set by software to enable a Comp0 DMA
transfer and cleared by hardware at the end of the
block transfer.
0: Disable compare on CMP0R DMA
1: Enable compare on CMP0R DMA
Bit 0 = REG/MEM: DMA area selection.
This bit is set and cleared by software. It selects
the source and destination of the DMA area
0: DMA from/to memory
Bit 2 = CM0I: Compare 0 Interrupt mask.
This bit is set and cleared by software.
0: Disable compare on CMP0R interrupt
1: Enable compare on CMP0R interrupt (or
Comp0 DMA End of Block interrupt if CM0D=1)
1: DMA from/to Register File
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9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
DMA ADDRESS POINTER REGISTER (DAPR)
R241 - Read/Write
INTERRUPT VECTOR REGISTER (T_IVR)
R242 - Read/Write
Register Page: 9
Reset value: xxxx xxx0
Register Page: 9
Reset value: undefined
7
0
7
0
0
DMA PRG
SRCE /DAT
DAP7 DAP6 DAP5 DAP4 DAP3 DAP2
V4
V3
V2
V1
V0
W1
W0
Bits 7:2 = DAP[7:2]: MSB of DMA address regis-
ter location.
These are the most significant bits of the DMA ad-
dress register location programmable by software.
The DAP2 bit may also be toggled by hardware if
the Timer DMA section for the Compare 0 channel
is configured in Swap mode.
This register is used as a vector, pointing to the
16-bit interrupt vectors in memory which contain
the starting addresses of the three interrupt sub-
routines managed by each timer.
Only one Interrupt Vector Register is available for
each timer, and it is able to manage three interrupt
groups, because the 3 least significant bits are
fixed by hardware depending on the group which
generated the interrupt request.
Note: During a DMA transfer with the Register
File, the DAPR is not used; however, in Swap
mode, DAP2 is used to point to the correct table.
In order to determine which request generated the
interrupt within a group, the T_FLAGR register can
be used to check the relevant interrupt source.
Bit 1 = DMA-SRCE: DMA source selection.
This bit is fixed by hardware.
0: DMA source is a Capture on REG0R register
1: DMA destination is a Compare on the CMP0R
register
Bits 7:3 = V[4:0]: MSB of the vector address.
These bits are user programmable and contain the
five most significant bits of the Timer interrupt vec-
tor addresses in memory. In any case, an 8-bit ad-
dress can be used to indicate the Timer interrupt
vector locations, because they are within the first
256 memory locations (see Interrupt and DMA
chapters).
Bit 0 = PRG/DAT: DMA memory selection.
This bit is set and cleared by software. It is only
meaningful if DCPR.REG/MEM=0.
0: The ISR register is used to extend the address
of data transferred by DMA (see MMU chapter).
1: The DMASR register is used to extend the ad-
dress of data transferred by DMA (see MMU
chapter).
Bits 2:1 = W[1:0]: Vector address bits.
These bits are equivalent to bit 1 and bit 2 of the
Timer interrupt vector addresses in memory. They
are fixed by hardware, depending on the group of
sources which generated the interrupt request as
follows:.
REG/MEM PRG/DAT
DMA Source/Destination
0
0
ISR register used to address
memory
0
1
DMASR register used to address
memory
W1
W0
Interrupt Source
1
1
0
1
Register file
Register file
0
0
1
1
0
1
0
1
Overflow/Underflow even interrupt
Not available
Capture event interrupt
Compare event interrupt
Bit 0 = This bit is forced by hardware to 0.
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9
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
INTERRUPT/DMA CONTROL REGISTER
(IDCR)
Bit 3 = SWEN: Swap function enable.
This bit is set and cleared by software.
0: Disable Swap mode
R243 - Read/Write
Register Page: 9
Reset value: 1100 0111 (C7h)
1: Enable Swap mode for both DMA channels.
7
0
Bits 2:0 = PL[2:0]: Interrupt/DMA priority level.
With these three bits it is possible to select the In-
terrupt and DMA priority level of each timer, as one
of eight levels (see Interrupt/DMA chapter).
CPE CME DCTS DCTD SWEN PL2 PL1 PL0
Bit 7 = CPE: Capture 0 EOB.
This bit is set by hardware when the End Of Block
condition is reached during a Capture 0 DMA op-
eration with the Swap mode enabled. When Swap
mode is disabled (SWEN bit = “0”), the CPE bit is
forced to 1 by hardware.
I/O CONNECTION REGISTER (IOCR)
R248 - Read/Write
Register Page: 9
Reset value: 1111 1100 (FCh)
0: No end of block condition
1: Capture 0 End of block
7
0
Bit 6 = CME: Compare 0 EOB.
SC1 SC0
This bit is set by hardware when the End Of Block
condition is reached during a Compare 0 DMA op-
eration with the Swap mode enabled. When the
Swap mode is disabled (SWEN bit = “0”), the CME
bit is forced to 1 by hardware.
Bits 7:2 = not used.
Bit 1 = SC1: Select connection odd.
This bit is set and cleared by software. It selects if
the TxOUTA and TxINA pins for Timer 1 and Timer
3 are connected on-chip or not.
0: No end of block condition
1: Compare 0 End of block
0: T1OUTA / T1INA and T3OUTA/ T3INA uncon-
nected
Bit 5 = DCTS: DMA capture transfer source.
This bit is set and cleared by software. It selects
the source of the DMA operation related to the
channel associated with the Capture 0.
Note: The I/O port source is available only on spe-
cific devices.
1: T1OUTA connected internally to T1INA and
T3OUTA connected internally to T3INA
Bit 0 = SC0: Select connection even.
This bit is set and cleared by software. It selects if
the TxOUTA and TxINA pins for Timer 0 and Timer
2 are connected on-chip or not.
0: T0OUTA / T0INA and T2OUTA/ T2INA uncon-
nected
0: REG0R register
1: I/O port.
Bit 4 = DCTD: DMA compare transfer destination.
This bit is set and cleared by software. It selects
the destination of the DMA operation related to the
channel associated with Compare 0.
Note: The I/O port destination is available only on
specific devices.
1: T0OUTA connected internally to T0INA and
T2OUTA connected internally to T2INA
Note: Timer 1 and 2 are available only on some
devices. Refer to the device block diagram and
register map.
0: CMP0R register
1: I/O port
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
10.5.1 Introduction
■ Programmable address indication bit (wake-up
bit) and user invisible compare logic to support
multiple microcomputer networking. Optional
character search function.
The Multiprotocol Serial Communications Inter-
face (SCI-M) offers full-duplex serial data ex-
change with a wide range of external equipment.
The SCI-M offers four operating modes: Asynchro-
nous, Asynchronous with synchronous clock, Seri-
al expansion and Synchronous.
■ Internal diagnostic capabilities:
– Local loopback for communications link fault
isolation.
– Auto-echo for communications link fault isola-
tion.
10.5.2 Main Features
■ Full duplex synchronous and asynchronous
operation.
■ Separate interrupt/DMA channels for transmit
and receive.
■ Transmit, receive, line status, and device
address interrupt generation.
■ In addition, a Synchronous mode supports:
■ Integral Baud Rate Generator capable of
– High speed communication
– Possibility of hardware synchronization (RTS/
DCD signals).
– Programmable polarity and stand-by level for
data SIN/SOUT.
– Programmable active edge and stand-by level
for clocks CLKOUT/RXCL.
– Programmable active levels of RTS/DCD sig-
nals.
– Full Loop-Back and Auto-Echo modes for DA-
TA, CLOCKs and CONTROLs.
dividing the input clock by any value from 2 to
16
2 -1 (16 bit word) and generating the internal
16X data sampling clock for asynchronous
operation or the 1X clock for synchronous
operation.
■ Fully programmable serial interface:
– 5, 6, 7, or 8 bit word length.
– Even, odd, or no parity generation and detec-
tion.
– 0, 1, 1.5, 2, 2.5, 3 stop bit generation.
– Complete status reporting capabilities.
– Line break generation and detection.
Figure 106. SCI-M Block Diagram
ST9 CORE BUS
DMA
CONTROLLER
DMA
CONTROLLER
TRANSMIT
BUFFER
REGISTER
ADDRESS
COMPARE
REGISTER
RECEIVER
BUFFER
REGISTER
RECEIVER
SHIFT
REGISTER
TRANSMIT
SHIFT
REGISTER
Frame Control
and STATUS
CLOCK and
BAUD RATE
GENERATOR
ALTERNATE
FUNCTION
VA00169A
SDS
SOUT RTS
TXCLK/CLKOUT RXCLK DCD
SIN
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.3 Functional Description
The SCI-M has four operating modes:
– Asynchronous mode
Asynchronous mode, Asynchronous mode with
synchronous clock and Serial expansion mode
output data with the same serial frame format. The
differences lie in the data sampling clock rates
(1X, 16X) and in the protocol used.
– Asynchronous mode with synchronous clock
– Serial expansion mode
– Synchronous mode
Figure 107. SCI -M Functional Schematic
INPL (*)
INTCLK
XBRG
RX buffer
register
RX shift
register
Baud rate
generator
Sin
LBEN (*)
RXclk
1
LBEN
Divider by 16
0
CD
1
OUTPL (*)
XRX
INPEN (*)
OCKPL (*)
Divider by 16
0
TX shift
register
Sout
CD
OCLK
AEN
OUTSB (*)
TXbuffer
register
DCDEN (*)
Polarity
AEN (*)
Enveloper
OCLK
Polarity
OCKSB (*)
XTCLK
AEN (*)
RTSEN (*)
VR02054
TXclk / CLKout
DCD
RTS
The control signals marked with (*) are active only in synchronous mode (SMEN=1)
Note: Some pins may not be available on some devices. Refer to the device Pinout Description.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4 SCI-M Operating Modes
10.5.4.1 Asynchronous Mode
10.5.4.2
Asynchronous
Mode
with
Synchronous Clock
In this mode, data and clock are synchronous,
each data bit is sampled once per clock period.
In this mode, data and clock can be asynchronous
(the transmitter and receiver can use their own
clocks to sample received data), each data bit is
sampled 16 times per clock period.
For transmit operation, a general purpose I/O port
pin can be programmed to output the CLKOUT
signal from the baud rate generator. If the SCI is
provided with an external transmission clock
source, there will be a skew equivalent to two
INTCLK periods between clock and data.
The baud rate clock should be set to the ÷16 Mode
and the frequency of the input clock (from an ex-
ternal source or from the internal baud-rate gener-
ator output) is set to suit.
Data will be transmitted on the falling edge of the
transmit clock. Received data will be latched into
the SCI on the rising edge of the receive clock.
Figure 108. Sampling Times in Asynchronous Format
SDIN
rcvck
0
1
2
3
4
5
7
8
9
10
11 12
13
14
15
rxd
rxclk
VR001409
LEGEND:
Serial Data Input line
rcvck: Internal X16 Receiver Clock
SIN:
Internal Serial Data Input Line
Internal Receiver Shift Register Sampling Clock
rxd:
rxclk:
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.3 Serial Expansion Mode
the Clock Configuration Register. Whenever the
SCI is to receive data in synchronous mode, the
clock waveform must be supplied externally via
the RXCLK pin and be synchronous with the data.
For correct receiver operation, the XRX bit of the
Clock Configuration Register must be set.
This mode is used to communicate with an exter-
nal synchronous peripheral.
The transmitter only provides the clock waveform
during the period that data is being transmitted on
the CLKOUT pin (the Data Envelope). Data is
latched on the rising edge of this clock.
Two external signals, Request-To-Send and Data-
Carrier-Detect (RTS/DCD), can be enabled to syn-
chronise the data exchange between two serial
units. The RTS output becomes active just before
the first active edge of CLKOUT and indicates to
the target device that the MCU is about to send a
synchronous frame; it returns to its stand-by state
following the last active edge of CLKOUT (MSB
transmitted).
Whenever the SCI is to receive data in serial port
expansion mode, the clock must be supplied ex-
ternally, and be synchronous with the transmitted
data. The SCI latches the incoming data on the ris-
ing edge of the received clock, which is input on
the RXCLK pin.
10.5.4.4 Synchronous Mode
The DCD input can be considered as a gate that
filters RXCLK and informs the MCU that a trans-
mitting device is transmitting a data frame. Polarity
of RTS/DCD is individually programmable, as for
clocks and data.
This mode is used to access an external synchro-
nous peripheral, dummy start/stop bits are not in-
cluded in the data frame. Polarity, stand-by level
and active edges of I/O signals are fully and sepa-
rately programmable for both inputs and outputs.
The data word is programmable from 5 to 8 bits, as
for the other modes; parity, address/9th, stop bits
and break cannot be inserted into the transmitted
frame. Programming of the related bits of the SCI
control registers is irrelevant in Synchronous
Mode: all the corresponding interrupt requests
must, in any case, be masked in order to avoid in-
correct operation during data reception.
It's necessary to set the SMEN bit of the Synchro-
nous Input Control Register (SICR) to enable this
mode and all the related extra features (otherwise
disabled).
The transmitter will provide the clock waveform
only during the period when the data is being
transmitted via the CLKOUT pin, which can be en-
abled by setting both the XTCLK and OCLK bits of
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 109. SCI -M Operating Modes
PARITY
STOP BIT
I/O
DATA
PARITY
START BIT
16
DATA
I/O
STOP BIT
16
16
START BIT
CLOCK
CLOCK
VA00271
VA00272
Asynchronous Mode
Asynchronous Mode
with Synchronous Clock
stand-by
stand-by
stand-by
DATA
CLOCK
stand-by
stand-by
I/O
DATA
START BIT
(Dummy)
STOP BIT
(Dummy)
CLOCK
RTS/DCD
stand-by
VA0273A
VR02051
Serial Expansion Mode
Synchronous Mode
Note: In all operating modes, the Least Significant Bit is transmitted/received first.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.5 Serial Frame Format
Characters sent or received by the SCI can have
some or all of the features in the following format,
depending on the operating mode:
both Serial Expansion and Asynchronous modes
to indicate that the data is an address (bit set).
The ADDRESS/9TH bit is useful when several mi-
crocontrollers are exchanging data on the same
serial bus. Individual microcontrollers can stay idle
on the serial bus, waiting for a transmitted ad-
dress. When a microcontroller recognizes its own
address, it can begin Data Reception, likewise, on
the transmit side, the microcontroller can transmit
another address to begin communication with a
different microcontroller.
START: the START bit indicates the beginning of
a data frame in Asynchronous modes. The START
condition is detected as a high to low transition.
A dummy START bit is generated in Serial Expan-
sion mode. The START bit is not generated in
Synchronous mode.
DATA: the DATA word length is programmable
from 5 to 8 bits, for both Synchronous and Asyn-
chronous modes. LSB are transmitted first.
The ADDRESS/9TH bit can be used as an addi-
tional data bit or to mark control words (9th bit).
PARITY: The Parity Bit (not available in Serial Ex-
pansion mode and Synchronous mode) is option-
al, and can be used with any word length. It is used
for error checking and is set so as to make the total
number of high bits in DATA plus PARITY odd or
even, depending on the number of “1”s in the
DATA field.
STOP: Indicates the end of a data frame in Asyn-
chronous modes. A dummy STOP bit is generated
in Serial Expansion mode. The STOP bit can be
programmed to be 1, 1.5, 2, 2.5 or 3 bits long, de-
pending on the mode. It returns the SCI to the qui-
escent marking state (i.e., a constant high-state
condition) which lasts until a new start bit indicates
an incoming word. The STOP bit is not generated
in Synchronous mode.
ADDRESS/9TH: The Address/9th Bit is optional
and may be added to any word format. It is used in
Figure 110. SCI Character Formats
(2)
(1)
(3)
(2)
(2)
START
DATA
PARITY
ADDRESS
STOP
1, 1.5, 2, 2.5,
1, 2, 3
16X
1X
# bits
1
5, 6, 7, 8
0, 1
0, 1
NONE
ODD
EVEN
ON
OFF
states
(1)
LSB First
(2)
(3)
Not available in Synchronous mode
Not available in Serial Expansion mode
and Synchronous mode
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.5.1 Data transfer
Data to be transmitted by the SCI is first loaded by
the program into the Transmitter Buffer Register.
The SCI will transfer the data into the Transmitter
Shift Register when the Shift Register becomes
available (empty). The Transmitter Shift Register
converts the parallel data into serial format for
transmission via the SCI Alternate Function out-
put, Serial Data Out. On completion of the transfer,
the transmitter buffer register interrupt pending bit
will be updated. If the selected word length is less
than 8 bits, the unused most significant bits do not
need to be defined.
The character match Address Interrupt mode may
be used as a powerful character search mode,
generating an interrupt on reception of a predeter-
mined character e.g. Carriage Return or End of
Block codes (Character Match Interrupt). This is
the only Address Interrupt Mode available in Syn-
chronous mode.
The Line Break condition is fully supported for both
transmission and reception. Line Break is sent by
setting the SB bit (IDPR). This causes the trans-
mitter output to be held low (after all buffered data
has been transmitted) for a minimum of one com-
plete word length and until the SB bit is Reset.
Break cannot be inserted into the transmitted
frame for the Synchronous mode.
Incoming serial data from the Serial Data Input pin
is converted into parallel format by the Receiver
Shift Register. At the end of the input data frame,
the valid data portion of the received word is trans-
ferred from the Receiver Shift Register into the Re-
ceiver Buffer Register. All Receiver interrupt con-
ditions are updated at the time of transfer. If the
selected character format is less than 8 bits, the
unused most significant bits will be set.
Testing of the communications channel may be
performed using the built-in facilities of the SCI pe-
ripheral. Auto-Echo mode and Loop-Back mode
may be used individually or together. In Asynchro-
nous, Asynchronous with Synchronous Clock and
Serial Expansion modes they are available only on
SIN/SOUT pins through the programming of AEN/
LBEN bits in CCR. In Synchronous mode (SMEN
set) the above configurations are available on SIN/
SOUT, RXCLK/CLKOUT and DCD/RTS pins by
programming the AEN/LBEN bits and independ-
ently of the programmed polarity. In the Synchro-
nous mode case, when AEN is set, the transmitter
outputs (data, clock and control) are disconnected
from the I/O pins, which are driven directly by the
receiver input pins (Auto-Echo mode: SOUT=SIN,
CLKOUT=RXCLK and RTS=DCD, even if they act
on the internal receiver with the programmed po-
larity/edge). When LBEN is set, the receiver inputs
(data, clock and controls) are disconnected and
the transmitter outputs are looped-back into the re-
ceiver section (Loop-Back mode: SIN=SOUT, RX-
CLK=CLKOUT, DCD=RTS. The output pins are
locked to their programmed stand-by level and the
status of the INPL, XCKPL, DCDPL, OUTPL,
OCKPL and RTSPL bits in the SICR register are ir-
relevant). Refer to Figure 111, Figure 112, and
Figure 113 for these different configurations.
The Frame Control and Status block creates and
checks the character configuration (Data length
and number of Stop bits), as well as the source of
the transmitter/receiver clock.
The internal Baud Rate Generator contains a pro-
grammable divide by “N” counter which can be
used to generate the clocks for the transmitter
and/or receiver. The baud rate generator can use
INTCLK or the Receiver clock input via RXCLK.
The Address bit/D9 is optional and may be added
to any word in Asynchronous and Serial Expan-
sion modes. It is commonly used in network or ma-
chine control applications. When enabled (AB set),
an address or ninth data bit can be added to a
transmitted word by setting the Set Address bit
(SA). This is then appended to the next word en-
tered into the (empty) Transmitter Buffer Register
and then cleared by hardware. On character input,
a set Address Bit can indicate that the data pre-
ceding the bit is an address which may be com-
pared in hardware with the value in the Address
Compare Register (ACR) to generate an Address
Match interrupt when equal.
Table 44. Address Interrupt Modes
(1)
The Address bit and Address Comparison Regis-
ter can also be combined to generate four different
types of Address Interrupt to suit different proto-
cols, based on the status of the Address Mode En-
able bit (AMEN) and the Address Mode bit (AM) in
the CHCR register.
If 9th Data Bit is set
If Character Match
(1)
If Character Match and 9th Data Bit is set
(1)
If Character Match Immediately Follows BREAK
(1)
Not available in Synchronous mode
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 111. Auto Echo Configuration
DCD
TRANSMITTER
RECEIVER
TRANSMITTER
RECEIVER
SOUT
SOUT
RTS
RXCLK
SIN
SIN
CLKOUT
VR00210A
VR000210
All modes except Synchronous
Synchronous mode (SMEN=1)
Figure 112. Loop Back Configuration
DCD
stand-by
value
LOGICAL 1
TRANSMITTER
RECEIVER
SOUT
SOUT
SIN
TRANSMITTER
RECEIVER
stand-by
value
RTS
clock
data
RXCLK
SIN
stand-by
value
CLKOUT
VR00211A
VR000211
All modes except Synchronous
Synchronous mode (SMEN=1)
Figure 113. Auto Echo and Loop-Back Configuration
DCD
SOUT
TRANSMITTER
RECEIVER
TRANSMITTER
RECEIVER
SOUT
RTS
clock
data
RXCLK
SIN
SIN
CLKOUT
VR000212
VR00212A
Synchronous mode (SMEN=1)
All modes except Synchronous
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.6 Clocks And Serial Transmission Rates
The output of the Baud Rate generator has a pre-
cise 50% duty cycle. The Baud Rate generator can
use INTCLK for the input clock source. In this
case, INTCLK (and therefore the MCU Xtal)
should be chosen to provide a suitable frequency
for division by the Baud Rate Generator to give the
required transmit and receive bit rates. Suitable
INTCLK frequencies and the respective divider
values for standard Baud rates are shown in Table
45.
The communication bit rate of the SCI transmitter
and receiver sections can be provided from the in-
ternal Baud Rate Generator or from external
sources. The bit rate clock is divided by 16 in
Asynchronous mode (CD in CCR reset), or undi-
vided in the 3 other modes (CD set).
With INTCLK running at 24MHz and no external
Clock provided, a maximum bit rate of 3MBaud
and 750KBaud is available in undivided and divide
by-16-mode respectively.
10.5.7 SCI -M Initialization Procedure
Writing to either of the two Baud Rate Generator
Registers immediately disables and resets the SCI
baud rate generator, as well as the transmitter and
receiver circuitry.
With INTCLK running at 24MHz and an external
Clock provided through the RXCLK/TXCLK lines,
a maximum bit rate of 3MBaud and 375KBaud is
available in undivided and divided by 16 mode re-
spectively (see Figure 115).
After writing to the second Baud Rate Generator
Register, the transmitter and receiver circuits are
enabled. The Baud Rate Generator will load the
new value and start counting.
External Clock Sources. The External Clock in-
put pin TXCLK may be programmed by the XTCLK
and OCLK bits in the CCR register as: the transmit
clock input, Baud Rate Generator output (allowing
an external divider circuit to provide the receive
clock for split rate transmit and receive), or as
CLKOUT output in Synchronous and Serial Ex-
pansion modes. The RXCLK Receive clock input
is enabled by the XRX bit, this input should be set
in accordance with the setting of the CD bit.
To initialize the SCI, the user should first initialize
the most significant byte of the Baud Rate Gener-
ator Register; this will reset all SCI circuitry. The
user should then initialize all other SCI registers
(SICR/SOCR included) for the desired operating
mode and then, to enable the SCI, he should ini-
tialize the least significant byte Baud Rate Gener-
ator Register.
Baud Rate Generator. The internal Baud Rate
Generator consists of a 16-bit programmable di-
vide by “N” counter which can be used to generate
the transmitter and/or receiver clocks. The mini-
mum baud rate divisor is 2 and the maximum divi-
'On-the-Fly' modifications of the control registers'
content during transmitter/receiver operations, al-
though possible, can corrupt data and produce un-
desirable spikes on the I/O lines (data, clock and
control). Furthermore, modifying the control regis-
ters' content without reinitialising the SCI circuitry
(during stand-by cycles, waiting to transmit or re-
ceive data) must be kept carefully under control by
software to avoid spurious data being transmitted
or received.
16
sor is 2 -1. After initialising the baud rate genera-
tor, the divisor value is immediately loaded into the
counter. This prevents potentially long random
counts on the initial load.
The Baud Rate generator frequency is equal to the
Input Clock frequency divided by the Divisor value.
WARNING: Programming the baud rate divider to
0 or 1 will stop the divider.
Note: For synchronous receive operation, the data
and receive clock must not exhibit significant skew
between clock and data. The received data and
clock are internally synchronized to INTCLK.
Figure 114. SCI-M Baud Rate Generator Initialization Sequence
MOST SIGNIFICANT
BYTE INITIALIZATION
SELECT SCI
WORKING MODE
LEAST SIGNIFICANT
BYTE INITIALIZATION
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Table 45. SCI-M Baud Rate Generator Divider Values Example 1
INTCLK: 19660.800 KHz
Divisor
Dec
Actual
Baud
Rate
Baud
Rate
Clock
Factor
Desired Freq
(kHz)
Actual Freq
(kHz)
Deviation
Hex
50.00
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
0.80000
1.20000
24576
16384
11170
4096
2048
1024
512
6000
4000
2BA2
1000
800
400
200
100
80
50.00
0.80000
1.20000
0.0000%
0.0000%
75.00
110.00
75.00
110.01
1.76000
1.76014 -0.00081%
300.00
4.80000
300.00
4.80000
9.60000
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
600.00
9.60000
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
19.20000
38.40000
76.80000
153.60000
307.20000
614.40000
1228.80000
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
19.20000
38.40000
76.80000
153.60000
307.20000
614.40000
1228.80000
256
128
64
40
32
20
16
10
Table 46. SCI-M Baud Rate Generator Divider Values Example 2
INTCLK: 24576 KHz
Divisor
Dec
Actual
Baud
Rate
Baud
Rate
Clock
Factor
Desired Freq
(kHz)
Actual Freq
(kHz)
Deviation
Hex
50.00
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
16 X
0.80000
1.20000
30720
20480
13963
5120
2560
1280
640
7800
5000
383B
1400
A00
500
280
140
A0
50.00
0.80000
1.20000
0.0000%
0.0000%
75.00
110.00
75.00
110.01
1.76000
1.76014 -0.00046%
300.00
4.80000
300.00
4.80000
9.60000
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
0.0000%
600.00
9.60000
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
19.20000
38.40000
76.80000
153.60000
307.20000
614.40000
1228.80000
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
19.20000
38.40000
76.80000
153.60000
307.20000
614.40000
1228.80000
320
160
80
50
40
28
20
14
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.8 Input Signals
SIN: Serial Data Input. This pin is the serial data
only the data portion of the frame and its stand-by
state is high: data is valid on the rising edge of the
clock. Even in Synchronous mode CLKOUT will
only clock the data portion of the frame, but the
stand-by level and active edge polarity are pro-
grammable by the user.
input to the SCI receiver shift register.
TXCLK: External Transmitter Clock Input. This
pin is the external input clock driving the SCI trans-
mitter. The TXCLK frequency must be greater than
or equal to 16 times the transmitter data rate (de-
pending whether the X16 or the X1 clock have
been selected). A 50% duty cycle is required for
this input and must have a period of at least twice
INTCLK. The use of the TXCLK pin is optional.
When Synchronous mode is disabled (SMEN in
SICR is reset), the state of the XTCLK and OCLK
bits in CCR determine the source of CLKOUT; '11'
enables the Serial Expansion Mode.
RXCLK: External Receiver Clock Input. This in-
put is the clock to the SCI receiver when using an
external clock source connected to the baud rate
generator. INTCLK is normally the clock source. A
50% duty cycle is required for this input and must
have a period of at least twice INTCLK. Use of RX-
CLK is optional.
When the Synchronous mode is enabled (SMEN
in SICR is set), the state of the XTCLK and OCLK
bits in CCR determine the source of CLKOUT; '00'
disables it for PLM applications.
RTS: Request To Send. This output Alternate
Function is only enabled in Synchronous mode; it
becomes active when the Least Significant Bit of
the data frame is sent to the Serial Output Pin
(SOUT) and indicates to the target device that the
MCU is about to send a synchronous frame; it re-
turns to its stand-by value just after the last active
edge of CLKOUT (MSB transmitted). The active
level can be programmed high or low.
DCD: Data Carrier Detect. This input is enabled
only in Synchronous mode; it works as a gate for
the RXCLK clock and informs the MCU that an
emitting device is transmitting a synchronous
frame. The active level can be programmed as 1
or 0 and must be provided at least one INTCLK pe-
riod before the first active edge of the input clock.
SDS: Synchronous Data Strobe. This output Al-
ternate function is only enabled in Synchronous
mode; it becomes active high when the Least Sig-
nificant Bit is sent to the Serial Output Pins
(SOUT) and indicates to the target device that the
MCU is about to send the first bit for each synchro-
nous frame. It is active high on the first bit and it is
low for all the rest of the frame. The active level
can not be programmed.
10.5.9 Output Signals
SOUT: Serial Data Output. This Alternate Func-
tion output signal is the serial data output for the
SCI transmitter in all operating modes.
CLKOUT: Clock Output. The alternate Function
of this pin outputs either the data clock from the
transmitter in Serial Expansion or Synchronous
modes, or the clock output from the Baud Rate
Generator. In Serial expansion mode it will clock
Figure 115. Receiver and Transmitter Clock Frequencies
Min
0
Max
Conditions
1x mode
INTCLK/8
INTCLK/4
INTCLK/8
INTCLK/2
INTCLK/8
INTCLK/4
INTCLK/8
INTCLK/2
External RXCLK
Receiver Clock Frequency
0
16x mode
1x mode
0
Internal Receiver Clock
0
16x mode
1x mode
0
External TXCLK
Transmitter Clock Frequency
0
16x mode
1x mode
0
Internal Transmitter Clock
0
16x mode
Note: The internal receiver and transmitter clocks
are the ones applied to the Tx and Rx shift regis-
ters (see Figure 106).
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.10 Interrupts and DMA
10.5.10.1 Interrupts
trigger. These bits should be reset by the program-
mer during the Interrupt Service routine.
The four major levels of interrupt are encoded in
hardware to provide two bits of the interrupt vector
register, allowing the position of the block of point-
er vectors to be resolved to an 8 byte block size.
The SCI can generate interrupts as a result of sev-
eral conditions. Receiver interrupts include data
pending, receive errors (overrun, framing and par-
ity), as well as address or break pending. Trans-
mitter interrupts are software selectable for either
Transmit Buffer Register Empty (BSN set) or for
Transmit Shift Register Empty (BSN reset) condi-
tions.
The SCI interrupts have an internal priority struc-
ture in order to resolve simultaneous events. Refer
also to Section 10.5.4 SCI-M Operating Modes for
more details relating to Synchronous mode.
Typical usage of the Interrupts generated by the
SCI peripheral are illustrated in Figure 116.
Table 47. SCI Interrupt Internal Priority
Receive DMA Request
Transmit DMA Request
Receive Interrupt
Highest Priority
The SCI peripheral is able to generate interrupt re-
quests as a result of a number of events, several
of which share the same interrupt vector. It is
therefore necessary to poll S_ISR, the Interrupt
Status Register, in order to determine the active
Transmit Interrupt
Lowest Priority
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Table 48. SCI-M Interrupt Vectors
Interrupt Source
Vector Address
Transmitter Buffer or Shift Register Empty
Transmit DMA end of Block
xxx x110
Received Data Pending
Receive DMA end of Block
xxxx x100
Break Detector
Address Word Match
xxxx x010
xxxx x000
Receiver Error
Figure 116. SCI-M Interrupts: Example of Typical Usage
ADDRESS AFTER BREAK CONDITION
BREAK
DATA
DATA
ADDRESS
NO MATCH
DATA
BREAK
ADDRESS
MATCH
DATA
DATA
DATA
INTERRUPT
DATA
INTERRUPT
BREAK
INTERRUPT
BREAK
INTERRUPT
DATA
INTERRUPT
ADDRESS
INTERRUPT
ADDRESS WORD MARKED BY D9=1
DATA
DATA
ADDRESS
NO MATCH
DATA
DATA
DATA
ADDRESS
MATCH
DATA
ADDRESS
INTERRUPT
INTERRUPT
DATA
DATA
INTERRUPT
INTERRUPT
CHARACTER SEARCH MODE
DATA MATCH
DATA
DATA
DATA
DATA
DATA
INTERRUPT
DATA
INTERRUPT
CHAR MATCH
INTERRUPT
DATA
INTERRUPT
DATA
INTERRUPT
DATA
INTERRUPT
D9 ACTING AS DATA CONTROL WITH SEPARATE INTERRUPT
DATA
DATA
DATA
DATA
D9=1
DATA
DATA
INTERRUPT
INTERRUPT
D9=1
INTERRUPT
DATA
INTERRUPT
VA00270
DATA
INTERRUPT
DATA
DATA
INTERRUPT
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.10.2 DMA
The transfer of the last byte of a DMA data block
will be followed by a DMA End Of Block transmit or
receive interrupt, setting the TXEOB or RXEOB
bit.
Two DMA channels are associated with the SCI,
for transmit and for receive. These follow the reg-
ister scheme as described in the DMA chapter.
A typical Transmission End Of Block interrupt rou-
tine will perform the following actions:
DMA Reception
To perform a DMA transfer in reception mode:
1. Restore the DMA counter register (TDCPR).
2. Restore the DMA address register (TDAPR).
1. Initialize the DMA counter (RDCPR) and DMA
address (RDAPR) registers
3. Clear the Transmitter Shift Register Empty bit
TXSEM in the S_ISR register to avoid spurious
interrupts.
2. Enable DMA by setting the RXD bit in the IDPR
register.
3. DMA transfer is started when data is received
by the SCI.
4. Clear the Transmitter End Of Block (TXEOB)
pending bit in the IMR register.
5. Set the TXD bit in the IDPR register to enable
DMA.
DMA Transmission
To perform a DMA transfer in transmission mode:
6. Load the Transmitter Buffer Register (TXBR)
with the next byte to transmit.
1. Initialize the DMA counter (TDCPR) and DMA
address (TDAPR) registers.
The above procedure handles the case where a
further DMA transfer is to be performed.
2. Enable DMA by setting the TXD bit in the IDPR
register.
3. DMA transfer is started by writing a byte in the
Transmitter Buffer register (TXBR).
Error Interrupt Handling
If an error interrupt occurs while DMA is enabled in
reception mode, DMA transfer is stopped.
If this byte is the first data byte to be transmitted,
the DMA counter and address registers must be
initialized to begin DMA transmission at the sec-
ond byte. Alternatively, DMA transfer can be start-
ed by writing a dummy byte in the TXBR register.
To resume DMA transfer, the error interrupt han-
dling routine must clear the corresponding error
flag. In the case of an Overrun error, the routine
must also read the RXBR register.
DMA Interrupts
When DMA is active, the Received Data Pending
and the Transmitter Shift Register Empty interrupt
sources are replaced by the DMA End Of Block re-
ceive and transmit interrupt sources.
Character Search Mode with DMA
In Character Search Mode with DMA, when a
character match occurs, this character is not trans-
ferred. DMA continues with the next received char-
acter. To avoid an Overrun error occurring, the
Character Match interrupt service routine must
read the RXBR register.
Note: To handle DMA transfer correctly in trans-
mission, the BSN bit in the IMR register must be
cleared. This selects the Transmitter Shift Register
Empty event as the DMA interrupt source.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.11 Register Description
The SCI-M registers are located in the following
pages in the ST9:
SCI-M number 0: page 24 (18h)
SCI-M number 1: page 25 (19h) (when present)
The SCI is controlled by the following registers:
Address
Register
R240 (F0h)
R241 (F1h)
R242 (F2h)
R243 (F3h)
R244 (F4h)
R245 (F5h)
R246 (F6h)
R247 (F7h)
R248 (F8h)
R248 (F8h)
R249 (F9h)
R250 (FAh)
R251 (FBh)
R252 (FCh)
R253 (FDh)
R254 (FEh)
R255 (FFh)
Receiver DMA Transaction Counter Pointer Register
Receiver DMA Source Address Pointer Register
Transmitter DMA Transaction Counter Pointer Register
Transmitter DMA Destination Address Pointer Register
Interrupt Vector Register
Address Compare Register
Interrupt Mask Register
Interrupt Status Register
Receive Buffer Register same Address as Transmitter Buffer Register (Read Only)
Transmitter Buffer Register same Address as Receive Buffer Register (Write only)
Interrupt/DMA Priority Register
Character Configuration Register
Clock Configuration Register
Baud Rate Generator High Register
Baud Rate Generator Low Register
Synchronous Input Control Register
Synchronous Output Control Register
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9
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
RECEIVER DMA COUNTER POINTER (RDCPR)
R240 - Read/Write
TRANSMITTER DMA COUNTER POINTER
(TDCPR)
R242 - Read/Write
Reset value: undefined
Reset value: undefined
7
0
7
0
RC7
RC6
RC5
RC4
RC3
RC2
RC1 RR/M
TC7
TC6
TC5
TC4
TC3
TC2
TC1 TR/M
Bit 7:1 = RC[7:1]: Receiver DMA Counter Pointer.
These bits contain the address of the receiver
DMA transaction counter in the Register File.
Bit 7:1 = TC[7:1]: Transmitter DMA Counter Point-
er.
These bits contain the address of the transmitter
DMA transaction counter in the Register File.
Bit 0 = RR/M: Receiver Register File/Memory Se-
lector.
0: Select Memory space as destination.
1: Select the Register File as destination.
Bit 0 = TR/M: Transmitter Register File/Memory
Selector.
0: Select Memory space as source.
1: Select the Register File as source.
RECEIVER DMA ADDRESS POINTER (RDAPR)
R241 - Read/Write
TRANSMITTER DMA ADDRESS POINTER
(TDAPR)
Reset value: undefined
R243 - Read/Write
7
0
Reset value: undefined
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RPS
7
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TPS
Bit 7:1 = RA[7:1]: Receiver DMA Address Pointer.
These bits contain the address of the pointer (in
the Register File) of the receiver DMA data source.
Bit 7:1 = TA[7:1]: Transmitter DMA Address Point-
er.
These bits contain the address of the pointer (in
the Register File) of the transmitter DMA data
source.
Bit 0 = RPS: Receiver DMA Memory Pointer Se-
lector.
This bit is only significant if memory has been se-
lected for DMA transfers (RR/M = 0 in the RDCPR
register).
0: Select ISR register for receiver DMA transfers
address extension.
1: Select DMASR register for receiver DMA trans-
fers address extension.
Bit 0 = TPS: Transmitter DMA Memory Pointer Se-
lector.
This bit is only significant if memory has been se-
lected for DMA transfers (TR/M = 0 in the TDCPR
register).
0: Select ISR register for transmitter DMA transfers
address extension.
1: Select DMASR register for transmitter DMA
transfers address extension.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT VECTOR REGISTER (S_IVR)
R244 - Read/Write
ADDRESS/DATA COMPARE REGISTER (ACR)
R245 - Read/Write
Reset value: undefined
Reset value: undefined
7
0
0
7
0
V7
V6
V5
V4
V3
EV2
EV1
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad-
dress.
User programmable interrupt vector bits for trans-
mitter and receiver.
Bit 7:0 = AC[7:0]: Address/Compare Character.
With either 9th bit address mode, address after
break mode, or character search, the received ad-
dress will be compared to the value stored in this
register. When a valid address matches this regis-
ter content, the Receiver Address Pending bit
(RXAP in the S_ISR register) is set. After the
RXAP bit is set in an addressed mode, all received
data words will be transferred to the Receiver Buff-
er Register.
Bit 2:1 = EV[2:1]: Encoded Interrupt Source.
Both bits EV2 and EV1 are read only and set by
hardware according to the interrupt source.
EV2 EV1
Interrupt source
0
0
0
1
Receiver Error (Overrun, Framing, Parity)
Break Detect or Address Match
Received Data Pending/Receiver DMA
End of Block
1
1
0
1
Transmitter buffer or shift register empty
transmitter DMA End of Block
Bit 0 = D0: This bit is forced by hardware to 0.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT MASK REGISTER (IMR)
R246 - Read/Write
Bit 4 = RXE: Receiver Error Mask.
0: Disable Receiver error interrupts (OE, PE, and
FE pending bits in the S_ISR register).
1: Enable Receiver error interrupts.
Reset value: 0xx00000
7
0
Bit 3 = RXA: Receiver Address Mask.
0: Disable Receiver Address interrupt (RXAP
pending bit in the S_ISR register).
BSN RXEOB TXEOB RXE
RXA
RXB RXDI TXDI
1: Enable Receiver Address interrupt.
Bit 7 = BSN: Buffer or shift register empty inter-
rupt.
This bit selects the source of the transmitter regis-
ter empty interrupt.
0: Select a Shift Register Empty as source of a
Transmitter Register Empty interrupt.
1: Select a Buffer Register Empty as source of a
Transmitter Register Empty interrupt.
Bit 2 = RXB: Receiver Break Mask.
0: Disable Receiver Break interrupt (RXBP pend-
ing bit in the S_ISR register).
1: Enable Receiver Break interrupt.
Bit 1 = RXDI: Receiver Data Interrupt Mask.
0: Disable Receiver Data Pending and Receiver
End of Block interrupts (RXDP and RXEOB
pending bits in the S_ISR register).
1: Enable Receiver Data Pending and Receiver
End of Block interrupts.
Bit 6 = RXEOB: Received End of Block.
This bit is set by hardware only and must be reset
by software. RXEOB is set after a receiver DMA
cycle to mark the end of a data block.
0: Clear the interrupt request.
1: Mark the end of a received block of data.
Note: RXDI has no effect on DMA transfers.
Bit 0 = TXDI: Transmitter Data Interrupt Mask.
0: Disable Transmitter Buffer Register Empty,
Transmitter Shift Register Empty, or Transmitter
End of Block interrupts (TXBEM, TXSEM, and
TXEOB bits in the S_ISR register).
1: Enable Transmitter Buffer Register Empty,
Transmitter Shift Register Empty, or Transmitter
End of Block interrupts.
Bit 5 = TXEOB: Transmitter End of Block.
This bit is set by hardware only and must be reset
by software. TXEOB is set after a transmitter DMA
cycle to mark the end of a data block.
0: Clear the interrupt request.
1: Mark the end of a transmitted block of data.
Note: TXDI has no effect on DMA transfers.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT STATUS REGISTER (S_ISR)
R247 - Read/Write
Note: The source of this interrupt is given by the
couple of bits (AMEN, AM) as detailed in the IDPR
register description.
Reset value: undefined
7
0
Bit 3 = RXBP: Receiver Break Pending bit.
This bit is set by hardware if the received data in-
put is held low for the full word transmission time
(start bit, data bits, parity bit, stop bit).
0: No break received.
OE
FE
PE RXAP RXBP RXDP TXBEM TXSEM
Bit 7 = OE: Overrun Error Pending.
This bit is set by hardware if the data in the Receiv-
er Buffer Register was not read by the CPU before
the next character was transferred into the Receiv-
er Buffer Register (the previous data is lost).
0: No Overrun Error.
1: Break event occurred.
Bit 2 = RXDP: Receiver Data Pending bit.
This bit is set by hardware when data is loaded
into the Receiver Buffer Register.
0: No data received.
1: Data received in Receiver Buffer Register.
1: Overrun Error occurred.
Bit 6 = FE: Framing Error Pending bit.
This bit is set by hardware if the received data
word did not have a valid stop bit.
0: No Framing Error.
Bit 1 = TXBEM: Transmitter Buffer Register Emp-
ty.
This bit is set by hardware if the Buffer Register is
empty.
0: No Buffer Register Empty event.
1: Buffer Register Empty.
1: Framing Error occurred.
Note: In the case where a framing error occurs
when the SCI is programmed in address mode
and is monitoring an address, the interrupt is as-
serted and the corrupted data element is trans-
ferred to the Receiver Buffer Register.
Bit 0 = TXSEM: Transmitter Shift Register Empty.
This bit is set by hardware if the Shift Register has
completed the transmission of the available data.
0: No Shift Register Empty event.
Bit 5 = PE: Parity Error Pending.
This bit is set by hardware if the received word did
not have the correct even or odd parity bit.
0: No Parity Error.
1: Shift Register Empty.
1: Parity Error occurred.
Note: The Interrupt Status Register bits can be re-
set but cannot be set by the user. The interrupt
source must be cleared by resetting the related bit
when executing the interrupt service routine (natu-
rally the other pending bits should not be reset).
Bit 4 = RXAP: Receiver Address Pending.
RXAP is set by hardware after an interrupt ac-
knowledged in the address mode.
0: No interrupt in address mode.
1: Interrupt in address mode occurred.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
RECEIVER BUFFER REGISTER (RXBR)
R248 - Read only
TRANSMITTER BUFFER REGISTER (TXBR)
R248 - Write only
Reset value: undefined
Reset value: undefined
7
0
7
0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
Bit 7:0 = RD[7:0]: Received Data.
Bit 7:0 = TD[7:0]: Transmit Data.
This register stores the data portion of the re-
ceived word. The data will be transferred from the
Receiver Shift Register into the Receiver Buffer
Register at the end of the word. All receiver inter-
rupt conditions will be updated at the time of trans-
fer. If the selected character format is less than 8
bits, unused most significant bits will forced to “1”.
The ST9 core will load the data for transmission
into this register. The SCI will transfer the data
from the buffer into the Shift Register when availa-
ble. At the transfer, the Transmitter Buffer Register
interrupt is updated. If the selected word format is
less than 8 bits, the unused most significant bits
are not significant.
Note: RXBR and TXBR are two physically differ-
ent registers located at the same address.
Note: TXBR and RXBR are two physically differ-
ent registers located at the same address.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
INTERRUPT/DMA PRIORITY REGISTER (IDPR)
R249 - Read/Write
mat. If software does not reset SB before the min-
imum break length has finished, the break condi-
tion will continue until software resets SB. The SCI
terminates the break condition with a high level on
the transmitter data output for one transmission
clock period.
Reset value: undefined
7
0
AMEN
SB SA RXD TXD
PRL2
PRL1
PRL0
Bit 5 = SA: Set Address.
If an address/9th data bit mode is selected, SA val-
ue will be loaded for transmission into the Shift
Register. This bit is cleared by hardware after its
load.
0: Indicate it is not an address word.
1: Indicate an address word.
Bit 7 = AMEN: Address Mode Enable.
This bit, together with the AM bit (in the CHCR reg-
ister), decodes the desired addressing/9th data
bit/character match operation.
In Address mode the SCI monitors the input serial
data until its address is detected
Note: Proper procedure would be, when the
Transmitter Buffer Register is empty, to load the
value of SA and then load the data into the Trans-
mitter Buffer Register.
AMEN AM
0
0
0
1
Address interrupt if 9th data bit = 1
Address interrupt if character match
Bit 4 = RXD: Receiver DMA Mask.
Address interrupt if character match
and 9th data bit =1
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
receiver End of Block interrupt can occur.
1
1
0
1
Address interrupt if character match
with word immediately following Break
0: Disable Receiver DMA request (the RXDP bit in
the S_ISR register can request an interrupt).
1: Enable Receiver DMA request (the RXDP bit in
the S_ISR register can request a DMA transfer).
Note: Upon reception of address, the RXAP bit (in
the Interrupt Status Register) is set and an inter-
rupt cycle can begin. The address character will
not be transferred into the Receiver Buffer Regis-
ter but all data following the matched SCI address
and preceding the next address word will be trans-
ferred to the Receiver Buffer Register and the
proper interrupts updated. If the address does not
match, all data following this unmatched address
will not be transferred to the Receiver Buffer Reg-
ister.
Bit 3 = TXD: Transmitter DMA Mask.
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
transmitter End Of Block interrupt can occur.
0: Disable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request an interrupt).
1: Enable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request a DMA trans-
fer).
In any of the cases the RXAP bit must be reset by
software before the next word is transferred into
the Buffer Register.
Bit 2:0 = PRL[2:0]: SCI Interrupt/DMA Priority bits.
The priority for the SCI is encoded with
(PRL2,PRL1,PRL0). Priority level 0 is the highest,
while level 7 represents no priority.
When AMEN is reset and AM is set, a useful char-
acter search function is performed. This allows the
SCI to generate an interrupt whenever a specific
character is encountered (e.g. Carriage Return).
When the user has defined a priority level for the
SCI, priorities within the SCI are hardware defined.
These SCI internal priorities are:
Bit 6 = SB: Set Break.
0: Stop the break transmission after minimum
break length.
1: Transmit a break following the transmission of all
data in the Transmitter Shift Register and the
Buffer Register.
Receiver DMA request
Transmitter DMA request
Receiver interrupt
highest priority
Transmitter interrupt
lowest priority
Note: The break will be a low level on the transmit-
ter data output for at least one complete word for-
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CHARACTER CONFIGURATION REGISTER
(CHCR)
Bit 4 = AB: Address/9th Bit.
0: No Address/9th bit.
R250 - Read/Write
1: Address/9th bit included in the character format
between the parity bit and the first stop bit. This
bit can be used to address the SCI or as a ninth
data bit.
Reset value: undefined
7
0
AM
EP
PEN
AB
SB1
SB0
WL1
WL0
Bit 3:2 = SB[1:0]: Number of Stop Bits..
Bit 7 = AM: Address Mode.
Number of stop bits
This bit, together with the AMEN bit (in the IDPR
register), decodes the desired addressing/9th data
bit/character match operation. Please refer to the
table in the IDPR register description.
SB1
SB0
in 16X mode
in 1X mode
0
0
1
1
0
1
0
1
1
1
2
2
3
1.5
2
2.5
Bit 6 = EP: Even Parity.
0: Select odd parity (when parity is enabled).
1: Select even parity (when parity is enabled).
Bit 1:0 = WL[1:0]: Number of Data Bits
Bit 5 = PEN: Parity Enable.
0: No parity bit.
1: Parity bit generated (transmit data) or checked
(received data).
WL1
WL0
Data Length
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
Note: If the address/9th bit is enabled, the parity
bit will precede the address/9th bit (the 9th bit is
never included in the parity calculation).
8 bits
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CLOCK CONFIGURATION REGISTER (CCR)
R251 - Read/Write
0: Select 16X clock mode for both receiver and
transmitter.
1: Select 1X clock mode for both receiver and
transmitter.
Reset value: 0000 0000 (00h)
7
0
Note: In 1X clock mode, the transmitter will trans-
mit data at one data bit per clock period. In 16X
mode each data bit period will be 16 clock periods
long.
XTCLK OCLK XRX XBRG CD AEN LBEN STPEN
Bit 7 = XTCLK
This bit, together with the OCLK bit, selects the
source for the transmitter clock. The following ta-
ble shows the coding of XTCLK and OCLK.
Bit 2 = AEN: Auto Echo Enable.
0: No auto echo mode.
1: Put the SCI in auto echo mode.
Note: Auto Echo mode has the following effect:
the SCI transmitter is disconnected from the data-
out pin SOUT, which is driven directly by the re-
ceiver data-in pin, SIN. The receiver remains con-
nected to SIN and is operational, unless loopback
mode is also selected.
Bit 6 = OCLK
This bit, together with the XTCLK bit, selects the
source for the transmitter clock. The following ta-
ble shows the coding of XTCLK and OCLK.
XTCLK
OCLK
Pin Function
0
0
0
1
Pin is used as a general I/O
Pin = TXCLK (used as an input)
Bit 1 = LBEN: Loopback Enable.
0: No loopback mode.
1: Put the SCI in loopback mode.
Pin = CLKOUT (outputs the Baud
Rate Generator clock)
1
0
Note: In this mode, the transmitter output is set to
a high level, the receiver input is disconnected,
and the output of the Transmitter Shift Register is
looped back into the Receiver Shift Register input.
All interrupt sources (transmitter and receiver) are
operational.
Pin = CLKOUT (outputs the Serial
expansion and synchronous
mode clock)
1
1
Bit 0 = STPEN: Stick Parity Enable.
Bit 5 = XRX: External Receiver Clock Source.
0: External receiver clock source not used.
1: Select the external receiver clock source.
0: The transmitter and the receiver will follow the
parity of even parity bit EP in the CHCR register.
1: The transmitter and the receiver will use the op-
posite parity type selected by the even parity bit
EP in the CHCR register.
Note: The external receiver clock frequency must
be 16 times the data rate, or equal to the data rate,
depending on the status of the CD bit.
Parity (Transmitter &
EP
SPEN
Receiver)
Bit 4 = XBRG: Baud Rate Generator Clock
Source.
0: Select INTCLK for the baud rate generator.
1: Select the external receiver clock for the baud
rate generator.
0 (odd)
1 (even)
0 (odd)
0
0
1
1
Odd
Even
Even
1 (even)
Odd
Bit 3 = CD: Clock Divisor.
The status of CD will determine the SCI configura-
tion (synchronous/asynchronous).
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
BAUD RATE GENERATOR HIGH REGISTER
(BRGHR)
Bit 6 = INPL: SIN Input Polarity.
0: Polarity not inverted.
1: Polarity inverted.
R252 - Read/Write
Note: INPL only affects received data. In Auto-
Echo mode SOUT = SIN even if INPL is set. In
Loop-Back mode the state of the INPL bit is irrele-
vant.
Reset value: undefined
15
8
BG15 BG14 BG13 BG12 BG11 BG10 BG9 BG8
Bit 5 = XCKPL: Receiver Clock Polarity.
0: RXCLK is active on the rising edge.
1: RXCLK is active on the falling edge.
BAUD RATE GENERATOR LOW REGISTER
(BRGLR)
Note: XCKPL only affects the receiver clock. In
Auto-Echo mode CLKOUT = RXCLK independ-
ently of the XCKPL status. In Loop-Back the state
of the XCKPL bit is irrelevant.
R253 - Read/Write
Reset value: undefined
7
0
Bit 4 = DCDEN: DCD Input Enable.
0: Disable hardware synchronization.
1: Enable hardware synchronization.
BG7
BG6
BG5
BG4
BG3
BG2
BG1
BG0
Bit 15:0 = Baud Rate Generator MSB and LSB.
Note: When DCDEN is set, RXCLK drives the re-
ceiver section only during the active level of the
DCD input (DCD works as a gate on RXCLK, in-
forming the MCU that a transmitting device is
sending a synchronous frame to it).
The Baud Rate generator is a programmable di-
vide by “N” counter which can be used to generate
the clocks for the transmitter and/or receiver. This
counter divides the clock input by the value in the
Baud Rate Generator Register. The minimum
baud rate divisor is 2 and the maximum divisor is
16
Bit 3 = DCDPL: DCD Input Polarity.
0: The DCD input is active when LOW.
1: The DCD input is active when HIGH.
2 -1. After initialization of the baud rate genera-
tor, the divisor value is immediately loaded into the
counter. This prevents potentially long random
counts on the initial load. If set to 0 or 1, the Baud
Rate Generator is stopped.
Note: DCDPL only affects the gating activity of the
receiver clock. In Auto-Echo mode RTS = DCD in-
dependently of DCDPL. In Loop-Back mode, the
state of DCDPL is irrelevant.
SYNCHRONOUS INPUT CONTROL (SICR)
R254 - Read/Write
Reset value: 0000 0011 (03h)
Bit 2 = INPEN: All Input Disable.
0: Enable SIN/RXCLK/DCD inputs.
1: Disable SIN/RXCLK/DCD inputs.
7
0
SMEN INPL XCKPL DCDEN DCDPL INPEN
X
X
Bit 1:0 = “Don't Care”
Bit 7 = SMEN: Synchronous Mode Enable.
0: Disable all features relating to Synchronous
mode (the contents of SICR and SOCR are ig-
nored).
1: Select Synchronous mode with its programmed
I/O configuration.
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
SYNCHRONOUS OUTPUT CONTROL (SOCR)
R255 - Read/Write
Bit 3 = RTSEN: RTS and SDS Output Enable.
0: Disable the RTS and SDS hardware synchroni-
sation.
1: Enable the RTS and SDS hardware synchroni-
sation.
Reset value: 0000 0001 (01h)
7
0
Notes:
– When RTSEN is set, the RTS output becomes
active just before the first active edge of CLK-
OUT and indicates to target device that the MCU
is about to send a synchronous frame; it returns
to its stand-by value just after the last active edge
of CLKOUT (MSB transmitted).
OUTP OUTS OCKP OCKS RTSE RTS OUT
X
L
B
L
B
N
PL
DIS
Bit 7 = OUTPL: SOUT Output Polarity.
0: Polarity not inverted.
1: Polarity inverted.
– When RTSEN is set, the SDS output becomes
active high and indicates to the target device that
the MCU is about to send the first bit of a syn-
chronous frame on the Serial Output Pin
(SOUT); it returns to low level as soon as the
second bit is sent on the Serial Output Pin
(SOUT). In this way a positive pulse is generated
each time that the first bit of a synchronous frame
is present on the Serial Output Pin (SOUT).
Note: OUTPL only affects the data sent by the
transmitter section. In Auto-Echo mode SOUT =
SIN even if OUTPL=1. In Loop-Back mode, the
state of OUTPL is irrelevant.
Bit 6 = OUTSB: SOUT Output Stand-By Level.
0: SOUT stand-by level is HIGH.
1: SOUT stand-by level is LOW.
Bit 2 = RTSPL: RTS Output Polarity.
0: The RTS output is active when LOW.
1: The RTS output is active when HIGH.
Bit 5 = OCKPL: Transmitter Clock Polarity.
0: CLKOUT is active on the rising edge.
1: CLKOUT is active on the falling edge.
Note: RTSPL only affects the RTS activity on the
output pin. In Auto-Echo mode RTS = DCD inde-
pendently from the RTSPL value. In Loop-Back
mode RTSPL value is 'Don't Care'.
Note: OCKPL only affects the transmitter clock. In
Auto-Echo mode CLKOUT = RXCLK independ-
ently of the state of OCKPL. In Loop-Back mode
the state of OCKPL is irrelevant.
Bit 1 = OUTDIS: Disable all outputs.
This feature is available on specific devices only
(see device pin-out description).
When OUTDIS=1, all output pins (if configured in
Alternate Function mode) will be put in High Im-
pedance for networking.
Bit 4 = OCKSB: Transmitter Clock Stand-By Lev-
el.
0: The CLKOUT stand-by level is HIGH.
1: The CLKOUT stand-by level is LOW.
0: SOUT/CLKOUT/enabled
1: SOUT/CLKOUT/RTS put in high impedance
Bit 0 = “Don't Care”
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
10.6 ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
10.6.1 Introduction
The Asynchronous Serial Communications Inter-
face (SCI-A) offers a flexible means of full-duplex
data exchange with external equipment requiring
an industry standard NRZ asynchronous serial
data format. The SCI-A offers a very wide range of
baud rates using two baud rate generator sys-
tems.
10.6.3 General Description
The interface is externally connected to another
device by two pins (see Figure 118):
– TDO: Transmit Data Output. When the trans-
mitter is disabled, the output pin is in high im-
pedance. When the transmitter is enabled and
nothing is to be transmitted, the TDO pin is at
high level.
10.6.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
– RDI: Receive Data Input is the serial data in-
put. Oversampling techniques are used for
data recovery by discriminating between valid
incoming data and noise.
■ Independently programmable transmit and
Through these pins, serial data is transmitted and
received as frames comprising:
receive baud rates up to 700K baud.
■ Programmable data word length (8 or 9 bits)
– An Idle Line prior to transmission or reception
– A start bit
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
– A data word (8 or 9 bits) least significant bit
first
– A Stop bit indicating that the frame is com-
plete.
■ Muting
function
for
multiprocessor
This interface uses two types of baud rate genera-
tors:
configurations
■ Separate enable bits for Transmitter and
Receiver
■ Three error detection flags:
– Overrun error
– A conventional type for commonly-used baud
rates,
– An extended type with a prescaler offering a
very wide range of baud rates even with non-
standard oscillator frequencies.
– Noise error
– Frame error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
■ LIN Master: 13-bit LIN Synch Break generation
capability
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9
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 117. SCI-A Block Diagram
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
RDI
Transmit Shift Register
SCICR1
PIE
PS
R8
SCID
T8
M
WAKE PCE
WAKE
UP
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
UNIT
SCISR
SCICR2
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE
RDRF
IDLE OR NF FE
TC
PE
SCI
INTERRUPT
Extended Prescaler
Block Diagram
(cf.Figure 119)
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
SCICR3
RECEIVER RATE
CONTROL
LINE
-
-
-
-
-
-
-
CONVENTIONAL BAUD RATE GENERATOR
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9
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4 Functional Description
10.6.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 117. It contains 6 dedicated
registers:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 117).
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (SCIER-
PR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– An extended prescaler transmitter register (SCI-
ETPR)
Refer to the register descriptions in Section 10.6.5
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 118. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0 Bit1
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit0
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.2 Transmitter
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the IMI0 bit is set in the SIMRH register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 117).
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Procedure
– Select the M bit to define the word length.
LIN Transmission
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
The same procedure has to be applied with the fol-
lowing differences:
– Set the TE bit to send an idle frame as first trans-
mission.
– Clear the M bit to configure 8-bit word length
– Set the LINE bit to enter LIN Master mode. In this
case, setting the SBK bit will send 13 low bits.
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 118).
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
As long as the SBK bit is set, the SCI sends break
frames to the TDO pin. After clearing this bit by
software, the SCI inserts a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
Idle Characters
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
This flag generates an interrupt if the TIE bit is set
in the SCICR2 register and the IMI0 bit is set in the
SIMRH register.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, i.e. before writing the next byte in the
SCIDR.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
Character Reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 117).
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the IMI0 bit is set in the SIMRH register.
Procedure
– Select the M bit to define the word length.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the IMI0 bit is set in the SIMRH register.
– Data is transferred from the Shift register to the
SCIDR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing the RDRF bit is performed by the following
software sequence done by:
The NF bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
1. An access to the SCISR register
2. A read to the SCIDR register.
Framing Error
A framing error is detected when:
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SCI han-
dles it as a framing error.
When the framing error is detected:
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
SCIDR register.
When a idle frame is detected, there is the same
procedure as a data received character plus an
iterrupt if the ILIE bit is set and the IMI0 bit is set in
the SIMRH register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 119. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.4 Conventional Baud Rate Generation
10.6.4.6 Receiver Muting and Wake-up Feature
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
f
f
CPU
CPU
Rx =
Tx =
The non addressed devices may be placed in
sleep mode by means of the muting function.
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
Setting the RWU bit by software puts the SCI in
sleep mode:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
All the reception status bits can not be set.
All the receive interrupt are inhibited.
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
A muted receiver may be awakened by one of the
following two ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
All this bits are in the SCIBRR register.
Example: If f
is 24 MHz and if PR=13 and
TR=RR=2, the transmit and receive baud rates are
57700 baud.
CPU
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
10.6.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
The extended Baud Rate Generator block diagram
is described in the Figure 119.
M Bit
PCE Bit
SCI Frame
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
Note: The extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
SB : Start Bit
STB : Stop Bit
PB : Parity Bit
f
f
CPU
CPU
Rx =
16 ERPR*(PR*TR)
Tx =
16 ETPR*(PR*TR)
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
*
*
with:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.7 Parity definition
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Even parity: The parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PCIE is set in the SCICR1 register.
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain
an odd number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.5 Register Description
STATUS REGISTER (SCISR)
the SCISR register followed by a read to the
SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
R240 - Read Only
Register Page: 26
Reset Value: 1100 0000 (C0h)
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.
7
0
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by hardware when RE=0 by a
software sequence (an access to the SCISR regis-
ter followed by a read to the SCIDR register).
0: No Overrun error
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
1: Overrun error is detected
Note: data will not be transferred to the shift regis-
ter as long as the TDRE bit is not reset.
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
Bit 2 = NF Noise flag.
Bit 6 = TC Transmission complete.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SCISR register followed by a read to the
SCIDR register).
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
0: No noise is detected
1: Noise is detected
0: Transmission is not complete
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
1: Transmission is complete
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred into the SCIDR
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by hardware when
RE=0 or by a software sequence (an access to the
SCISR register followed by a read to the SCIDR
register).
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SCISR regis-
ter followed by a read to the SCIDR register).
0: No Framing error is detected
0: Data is not received
1: Received data is ready to be read
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by hardware
when RE=0 by a software sequence (an access to
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Bit 0 = PE Parity error.
Note: The M bit must not be modified during a data
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
transfer (both transmission and reception).
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
1: Parity error
1: Address Mark
CONTROL REGISTER 1 (SCICR1)
Bit 2 = PCE Parity control enable.
R243 - Read/Write
Register Page: 26
Reset Value: x000 0000 (x0h)
This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on receive data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
7
0
R8
T8
SCID
M
WAKE PCE
PS
PIE
0: Parity control disabled
1: Parity control enabled
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
1: Odd parity
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The ITEI0 bit in the SITRH register (See In-
terrupts Chapter) must be set to enable the SCI-A
interrupt as the SCI-A interrupt is a rising edge
event.
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
R244 - Read/Write
Register Page: 26
Reset Value: 0000 0000 (00h)
0: Receiver in active mode
1: Receiver in mute mode
7
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SCISR register
Notes:
– If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SCISR register
– The ITEI0 bit in the SITRH register (See Inter-
rupts Chapter) must be set to enable the SCI-A
interrupt as the SCI-A interrupt is a rising edge
event.
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register
CONTROL REGISTER 3 (SCICR3)
R255 - Read/Write
Register Page: 26
Reset Value: 0000 0000 (00h)
7
0
-
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
-
LINE
-
-
-
-
-
1: An SCI interrupt is generated whenever IDLE=1
in the SCISR register.
Bit 7 = Reserved
Bit 6 = LINE LIN mode Enable.
This bit is set and cleared by software.
0: LIN master mode disabled
1: LIN master mode enabled
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is in high
impedance
LIN master mode enables the capability to send
LIN Synch Breaks (13 low bits) using the SBK bit
in the SCICR2 register. In transmission, the LIN
Synch Break low phase duration is shown as be-
low:
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Number of low bits sent
LINE
M
during a LIN Synch Break
0
0
1
1
0
1
0
1
10
11
13
14
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SCISR register
1: Receiver is enabled and begins searching for a
start bit
Bits 5:0 = Reserved
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
R241 - Read/Write
Register Page: 26
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR Dividing Factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
16
32
64
128
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 117).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 117).
Note: This TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the (TR*ETPR) dividing factor.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
BAUD RATE REGISTER (SCIBRR)
R242 - Read/Write
Register Page: 26
Reset Value: 00xx xxxx (xxh)
RR Dividing Factor
SCR2
SCR1
SCR0
7
0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
4
8
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
16
32
64
128
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
Note: This RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the (RR*ERPR) dividing factor.
4
13
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ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
R245 - Read/Write
R246 - Read/Write
Register Page: 26
Register Page: 26
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0
ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0
Bits 7:1 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:1 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 119) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 119) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended Baud Rate Generator is not used af-
ter a reset.
The extended Baud Rate Generator is not used af-
ter a reset.
10.6.6 Important Notes on SCI-A
Refer to Section 13.1.4 on page 412 and Section
13.1.5 on page 412.
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SERIAL PERIPHERAL INTERFACE (SPI)
10.7 SERIAL PERIPHERAL INTERFACE (SPI)
10.7.1 Introduction
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
– SS: Slave select pin
To use any of these alternate functions (input or
output), the corresponding I/O port must be pro-
grammed as alternate function output.
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another Microcontroller.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 120.
Refer to the Pin Description chapter for the device-
specific pin-out.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave.
10.7.2 Main Features
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Maximum slave mode frequency = INTCLK/2.
■ Programmable prescalers for a wide range of
baud rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision flag protection
■ Master mode fault protection capability.
10.7.3 General Description
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Various data/clock timing relationships may be
chosen (see Figure 123) but master and slave
must be programmed with the same timing mode.
The SPI is connected to external devices through
4 alternate function pins:
– MISO: Master In Slave Out pin
Figure 120. Serial Peripheral Interface Master/Slave
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 121. Serial Peripheral Interface Block Diagram
Internal Bus
Read
SPDR
1
0
Read Buffer
IT
request
MOSI
Ext. INT
SPSR
MISO
8-Bit Shift Register
Write
MODF
WCOL
SPIF
-
-
-
-
-
SPI
STATE
CONTROL
SCK
SS
SPCR
MSTR
SPIS
SPR0
CPOL CPHA SPR1
SPIE SPOE
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
SPPR
PRS2 PRS1 PRS0
DIV2
1/2
PRESCALER
/1 .. /8
0
1
ST9 PERIPHERAL
CLOCK (INTCLK)
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4 Functional Description
In this configuration the MOSI pin is a data output
and the MISO pin is a data input.
Figure 121 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 4 dedicated registers:
– A Control Register (SPCR)
– A Prescaler Register (SPPR)
– A Status Register (SPSR)
Transmit Sequence
The transmit sequence begins when a byte is writ-
ten the SPDR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
– A Data Register (SPDR)
Refer to the SPCR, SPPR, SPSR and SPDR reg-
isters in Section 10.7.6for the bit definitions.
When data transfer is complete:
– The SPIF bit is set by hardware
10.7.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
– An interrupt is generated if the SPIS and SPIE
bits are set.
Procedure
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPDR register is
read, the SPI peripheral returns this buffered val-
ue.
– Define the serial clock baud rate by setting/re-
setting the DIV2 bit of SPPR register, by writ-
ing a prescaler value in the SPPR register and
programming the SPR0 & SPR1 bits in the
SPCR register.
Clearing the SPIF bit is performed by the following
software sequence:
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 123).
1. An access to the SPSR register while the SPIF
bit is set
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
2. A read of the SPDR register.
Note: While the SPIF bit is set, all writes to the
SPDR register are inhibited until the SPSR regis-
ter is read.
– The MSTR and SPOE bits must be set (they
remain set only if the SS pin is connected to a
high level signal).
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if the SPIS and SPIE
bits are set.
The value of the SPPR register and SPR0 & SPR1
bits in the SPCR is not used for the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPDR register is
read, the SPI peripheral returns this buffered val-
ue.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
123.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPSR register while the SPIF
bit is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2. A read of the SPDR register.
– Clear the MSTR bit and set the SPOE bit to
assign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
SPDR register are inhibited until the SPSR regis-
ter is read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 10.7.4.6).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the SPDR register between each
data byte transfer to avoid a write collision (see
Section 10.7.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4.3 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA Bit is Set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 122).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA Bit is Reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the second clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
This pin must be toggled high and low between
each byte transmitted (see Figure 122).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its SPDR register and does not allow it
to be altered. Therefore the SS pin must be high to
write a new data byte in the SPDR without produc-
ing a write collision.
Figure 123 shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
Figure 122. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 123. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the SPI Timing table in the Electrical Characteristics Section.
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4.4 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the SPDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the SPDR register after
its SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the SPDR register without generating a write
collision.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the SPDR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
SPDR register and output the MSBit on to the ex-
ternal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL Bit
The WCOL bit in the SPSR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 124).
Figure 124. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPSR
st
1 Step
THEN
SPIF =0
WCOL=0
nd
2
Step
Read SPDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPSR
st
1 Step
THEN
Note: Writing in SPDR register
instead of reading in it do not re-
set WCOL bit
nd
2
Step
Read SPDR
WCOL=0
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4.5 Master Mode Fault
bits may be restored to their original state during or
after this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPOE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPOE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
10.7.4.6 Overrun Condition
An overrun condition occurs, when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
1. A read access to the SPSR register while the
MODF bit is set.
2. A write to the SPCR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPDR register returns this byte. All other bytes
are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPOE and MSTR
This condition is not detected by the SPI peripher-
al.
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its SPDR reg-
ister.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 125).
Multi-Master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the SPCR register and the MODF
bit in the SPSR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one slave device during a
transmission.
Figure 125. Single Master Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
Slave
MCU
MCU
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.5 Interrupt Management
Note: In the interrupt routine, reset the related
pending bit to avoid the interrupt request that was
just acknowledged being proposed again.
The interrupt of the Serial Peripheral Interface is
mapped on one of the eight External Interrupt
Channels of the microcontroller (refer to the “Inter-
rupts” chapter).
Then, after resetting the pending bit and before
the IRET instruction, check if the SPIF and MODF
interrupt flags in the SPSR register) are reset; oth-
erwise jump to the beginning of the routine. If, on
return from an interrupt routine, the pending bit is
reset while one of the interrupt flags is set, no in-
terrupt is performed on that channel until the flags
are set. A new interrupt request is performed only
when a flag is set with the other not set.
Each External Interrupt Channel has:
– A trigger control bit in the EITR register (R242 -
Page 0),
– A pending bit in the EIPR register (R243 -
Page0),
– A mask bit in the EIMR register (R244 - Page 0).
10.7.5.1 Register Map
Program the interrupt priority level using the EI-
PLR register (R245 - Page 0). For a description of
these registers refer to the “Interrupts” and “DMA”
chapters.
Depending on the device, one or two Serial Pe-
ripheral interfaces can be present. The previous
table summarizes the position of the registers of
the two peripherals in the register map of the mi-
crocontroller.
To use the interrupt feature, perform the following
sequence:
Address
Page
Name
DR0
CR0
SR0
PR0
DR1
CR1
SR1
PR1
– Set the priority level of the interrupt channel used
for the SPI (EIPRL register)
SPI0
R240 (F0h)
R241 (F1h)
R242 (F2h)
R243 (F3h)
R248 (F8h)
R249 (F9h)
R250 (FAh)
R251 (FBh)
7
7
7
7
7
7
7
7
– Select the interrupt trigger edge as rising edge
(set the corresponding bit in the EITR register)
– Set the SPIS bit of the SPCR register to select
the peripheral interrupt source
– Set the SPIE bit of the SPCR register to enable
the peripheral to perform interrupt requests
SPI1
– In the EIPR register, reset the pending bit of the
interrupt channel used by the SPI interrupt to
avoid any spurious interrupt requests being per-
formed when the mask bit is set
– Set the mask bit of the interrupt channel used to
enable the MCU to acknowledge the interrupt re-
quests of the peripheral.
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.6 Register Description
DATA REGISTER (SPDR)
R240 - Read/Write
Note: To use the MISO, MOSI and SCK alternate
functions (input or output), the corresponding I/O
port must be programmed as alternate function
output.
Register Page: 7
Reset Value: 0000 0000 (00h)
7
0
Bit 5 = SPIS Interrupt Selection.
This bit is set and cleared by software.
0: Interrupt source is external interrupt
1: Interrupt source is SPI
D7
D6
D5
D4
D3
D2
D1
D0
The SPDR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.7.4.5 Master Mode Fault).
0: Slave mode is selected
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data register, the buffer is ac-
tually being read.
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
Warning: A write to the SPDR register places data
directly into the shift register for transmission.
Bit 3 = CPOL Clock polarity.
A read to the SPDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 121).
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
CONTROL REGISTER (SPCR)
R241 - Read/Write
Register Page: 7
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
Reset Value: 0000 0000 (00h)
7
0
SPIE SPOE SPIS MSTR CPOL CPHA SPR1 SPR0
1: The second clock transition is the first capture
edge.
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever either
SPIF or MODF are set in the SPSR register
while the other flag is 0.
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software. They
select one of four baud rates to be used as the se-
rial clock when the device is a master.
These 2 bits have no effect in slave mode.
Table 49. Serial Peripheral Baud Rate
Bit 6 = SPOE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.7.4.5 Master Mode Fault).
0: SPI alternate functions disabled (MISO, MOSI
and SCK can only work as input)
1: SPI alternate functions enabled (MISO, MOSI
and SCK can work as input or output depending
on the value of MSTR)
INTCLK Clock Divide
SPR1
SPR0
2
4
16
32
0
0
1
1
0
1
0
1
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SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SPSR)
R242 - Read Only
1: A fault in master mode has been detected
Bits 3:0 = Unused.
Register Page: 7
Reset Value: 0000 0000 (00h)
7
0
-
PRESCALER REGISTER (SPPR)
R243 - Read/Write
Register Page: 7
Reset Value: 0000 0000 (00h)
SPIF
WCOL
-
MODF
-
-
-
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPCR register. It is cleared by a soft-
ware sequence (an access to the SPSR register
followed by a read or write to the SPDR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
7
0
0
0
0
DIV2
0
PRS2 PRS1 PRS0
Bits 7:5 = Reserved, forced by hardware to 0.
Bit 4 = DIV2 Divider enable.
This bit is set and cleared by software.
0: Divider by 2 enabled.
1: Data transfer between the device and an exter-
nal device has been completed.
1: Divider by 2 disabled.
Note: While the SPIF bit is set, all writes to the
SPDR register are inhibited.
Bit 3 = Reserved. forced by hardware to 0.
Bit 6 = WCOL Write Collision status.
Bits 2:0 = PRS[2:0] Prescaler Value.
This bit is set by hardware when a write to the
SPDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 124).
0: No write collision occurred
1: A write collision has been detected
These bits are set and cleared by software. The
baud rate generator is driven by
INTCLK/(n1*n2*n3) where n1= PRS[2:0]+1, n2 is
the value defined by the SPR[1:0] bits (refer to Ta-
ble 49 and Table 50), n3 = 1 if DIV2=1 and n3= 2 if
DIV2=0. Refer to Figure 121.
These bits have no effect in slave mode.
Table 50. Prescaler Baud Rate
Prescaler
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
PRS2
PRS1 PRS0
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.7.4.5
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the SPCR register. This bit is
cleared by a software sequence (An access to the
SPSR register while MODF=1 followed by a write
to the SPCR register).
Division Factor
1 (no division)
0
0
0
0
0
1
2
...
8
1
1
1
0: No master mode fault detected
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I2C BUS INTERFACE
2
10.8 I C BUS INTERFACE
10.8.1 Introduction
2
The I C bus Interface serves as an interface be-
Interrupt Features:
2
tween the microcontroller and the serial I C bus. It
■ Interrupt generation on error condition, on
provides both multimaster and slave functions with
both 7-bit and 10-bit address modes; it controls all
transmission request and on data received
■ Interrupt address vector for each interrupt
2
I C bus-specific sequencing, protocol, arbitration,
source
timing and supports both standard (100KHz) and
2
■ Pending bit and mask bit for each interrupt
fast I C modes (400KHz).
source
Using DMA, data can be transferred with minimum
use of CPU time.
■ Programmable interrupt priority respects the
other peripherals of the microcontroller
The peripheral uses two external lines to perform
the protocols: SDA, SCL.
■ Interrupt address vector programmable
DMA Features:
10.8.2 Main Features
■ Parallel-bus/I C protocol converter
2
■ DMA both in transmission and in reception with
enabling bits
■ Multi-master capability
■ 7-bit/10-bit Addressing
■ DMA from/toward both Register File and
Memory
2
2
■ Standard I C mode/Fast I C mode
■ Transmitter/Receiver flag
■ End Of Block interrupt sources with the related
pending bits
■ End-of-byte transmission flag
■ Transfer problem detection
■ Interrupt generation on error conditions
■ Interrupt generation on transfer request and on
data received
2
I C Master Features:
■ Start bit detection flag
■ Clock generation
2
■ I C bus busy flag
■ Arbitration Lost flag
■ End of byte transmission flag
■ Transmitter/Receiver flag
■ Stop/Start generation
2
I C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
■ Detection of misplaced start or stop condition
2
■ Programmable I C Address detection (both 7-
bit and 10-bit mode)
■ General Call address programmable
■ Transfer problem detection
■ End of byte transmission flag
■ Transmitter/Receiver flag.
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
Figure 126. I C Interface Block Diagram
DATA BUS
DATA REGISTER
DATA SHIFT REGISTER
COMPARATOR
DATA
SDA
CONTROL
OWN ADDRESS REGISTER 1
OWN ADDRESS REGISTER 2
GENERAL CALL ADDRESS
CLOCK CONTROL REGISTER
CLOCK
SCL
STATUS REGISTER 1
STATUS REGISTER 2
CONTROL
CONTROL REGISTER
LOGIC AND INTERRUPT/DMA REGISTERS
INTERRUPT
DMA
CONTROL SIGNALS
VR02119A
2
10.8.3 Functional Description
The I C interface has sixteen internal registers.
Six of them are used for initialization:
– Own Address Registers I2COAR1, I2COAR2
– General Call Address Register I2CADR
– Clock Control Registers I2CCCR, I2CECCR
– Control register I2CCR
Refer to the I2CCR, I2CSR1 and I2CSR2 registers
in Section 10.8.7. for the bit definitions.
2
The I C interface works as an I/O interface
2
between the ST9 microcontroller and the I C bus
protocol. In addition to receiving and transmitting
data, the interface converts data from serial to
parallel format and vice versa using an interrupt or
polled handshake.
The following four registers are used during data
transmission/reception:
2
It operates in Multimaster/slave I C mode. The se-
– Data Register I2CDR
lection of the operating mode is made by software.
– Control Register I2CCR
– Status Register 1 I2CSR1
– Status Register 2 I2CSR2
2
2
The I C interface is connected to the I C bus by a
data pin (SDA) and a clock pin (SCL) which must
2
be configured as open drain when the I C cell is
enabled by programming the I/O port bits and the
PE bit in the I2CCR register. In this case, the value
of the external pull-up resistance used depends on
the application.
2
When the I C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
The following seven registers are used to handle
the interrupt and the DMA features:
bit is set) the General Call address (stored in
I2CADR register). It never recognizes the Start
Byte (address byte 01h) whatever its own address
is.
– Interrupt Status Register I2CISR
– Interrupt Mask Register I2CIMR
– Interrupt Vector Register I2CIVR
Data and addresses are transferred in 8 bits, MSB
first. The first byte(s) following the start condition
contain the address (one byte in 7-bit mode, two
bytes in 10-bit mode). The address is always
transmitted in master mode.
– Receiver DMA Address Pointer Register
I2CRDAP
– Receiver DMA Transaction Counter Register
I2CRDC
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter.
Acknowledge is enabled and disabled by software.
Refer to Figure 127.
– Transmitter DMA Address Pointer Register
I2CTDAP
– Transmitter DMA transaction Counter Register
I2CTDC
The interface can decode both addresses:
– Software programmable 7-bit General Call
address
2
– I C address stored by software in the I2COAR1
register in 7-bit address mode or stored in
I2COAR1 and I2COAR2 registers in 10-bit ad-
dress mode.
After a reset, the interface is disabled.
IMPORTANT:
1. To guarantee correct operation, before enabling
the peripheral (while I2CCR.PE=0), configure bit7
and bit6 of the I2COAR2 register according to the
internal clock INTCLK (for example 11xxxxxxb in
the range 14 - 30 MHz).
2. Bit7 of the I2CCR register must be cleared.
10.8.3.1 Mode Selection
2
In I C mode, the interface can operate in the four
following modes:
– Master transmitter/receiver
– Slave transmitter/receiver
By default, it operates in slave mode.
This interface automatically switches from slave to
master after a start condition is generated on the
bus and from master to slave in case of arbitration
loss or stop condition generation.
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, it is able to recognize its own ad-
dress (7 or 10-bit), as stored in the I2COAR1 and
I2COAR2 registers and (when the I2CCR.ENGC
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
Figure 127. I C BUS Protocol
SDA
SCL
ACK
9
MSB
1
2
8
START
STOP
CONDITION
CONDITION
VR02119B
2
Any transfer can be done using either the I C
registers directly or via the DMA.
The multimaster function is enabled with an auto-
matic switch from master mode to slave mode
2
when the interface loses the arbitration of the I C
If the transfer is to be done directly by accessing
the I2CDR, the interface waits (by holding the SCL
line low) for software to write in the Data Register
before transmission of a data byte, or to read the
Data Register after a data byte is received.
bus.
2
10.8.4.1 I C Slave Mode
As soon as a start condition is detected, the
address word is received from the SDA line and
sent to the shift register; then it is compared with
the address of the interface or the General Call
address (if selected by software).
If the transfer is to be done via DMA, the interface
sends a request for a DMA transfer. Then it waits
for the DMA to complete. The transfer between the
2
interface and the I C bus will begin on the next
Note: In 10-bit addressing mode, the comparison
includes the header sequence (11110xx0) and the
two most significant bits of the address.
rising edge of the SCL clock.
■ Header (10-bit mode) or Address (both 10-bit
and 7-bit modes) not matched: the state
machine is reset and waits for another Start
condition.
■ Header matched (10-bit mode only): the
interface generates an acknowledge pulse if the
ACK bit of the control register (I2CCR) is set.
■ Address matched: the I2CSR1.ADSL bit is set
and an acknowledge bit is sent to the master if
the I2CCR.ACK bit is set. An interrupt request
occurs if the I2CCR.ITE bit is set. Then the SCL
line is held low until the microcontroller reads
the I2CSR1 register (see Figure 128 Transfer
sequencing EV1).
The SCL frequency (F ) generated in master
scl
mode is controlled by a programmable clock divid-
2
er. The speed of the I C interface may be selected
between Standard (0-100KHz) and Fast (100-
2
400KHz) I C modes.
2
10.8.4 I C State Machine
2
To enable the interface in I C mode the I2CCR.PE
bit must be set twice as the first write only acti-
vates the interface (only the PE bit is set); and the
bit7 of I2CCR register must be cleared.
2
The I C interface always operates in slave mode
(the M/SL bit is cleared) except when it initiates a
transmission or a receipt sequencing (master
mode).
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Next, depending on the data direction bit (least
significant bit of the address byte), and after the
generation of an acknowledge, the slave must go
in sending or receiving mode.
– AF: Detection of a no-acknowledge bit.
The I2CSR2.AF flag is set and an interrupt is
generated if the I2CCR.ITE bit is set.
Note: In both cases, SCL line is not stretched low;
however, the SDA line, due to possible «0» bits
transmitted last, can remain low. It is then neces-
sary to release both lines by software.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1).
Other Events
– ADSL: Detection of a Start condition after an ac-
knowledge time-slot.
The state machine is reset and starts a new proc-
ess. The I2CSR1.ADSL flag bit is set and an in-
terrupt is generated if the I2CCR.ITE bit is set.
The SCL line is stretched low.
Slave Receiver
Following the address reception and after I2CSR1
register has been read, the slave receives bytes
from the SDA line into the Shift Register and sends
them to the I2CDR register. After each byte it
generates an acknowledge bit if the I2CCR.ACK
bit is set.
– STOPF: Detection of a Stop condition after an
acknowledge time-slot.
The state machine is reset. Then the
I2CSR2.STOPF flag is set and an interrupt is
generated if the I2CCR.ITE bit is set.
When the acknowledge bit is sent, the
I2CSR1.BTF flag is set and an interrupt is generat-
ed if the I2CCR.ITE bit is set (see Figure 128
Transfer sequencing EV2).
Then the interface waits for a read of the I2CSR1
register followed by a read of the I2CDR register,
or waits for the DMA to complete.
How to release the SDA / SCL lines
Check that the I2CSR1.BUSY bit is reset. Set and
subsequently clear the I2CCR.STOP bit while the
I2CSR1.BTF bit is set; then the SDA/SCL lines are
released immediately after the transfer of the cur-
rent byte.
Slave Transmitter
Following the address reception and after I2CSR1
register has been read, the slave sends bytes from
the I2CDR register to the SDA line via the internal
shift register.
This will also reset the state machine; any subse-
quent STOP bit (EV4) will not be detected.
2
10.8.4.2 I C Master Mode
When the acknowledge bit is received, the
I2CCR.BTF flag is set and an interrupt is
generated if the I2CCR.ITE bit is set (see Figure
128 Transfer sequencing EV3).
The slave waits for a read of the I2CSR1 register
followed by a write in the I2CDR register or waits
for the DMA to complete, both holding the SCL
line low (except on EV3-1).
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Setting the I2CCR.START bit while the
I2CSR1.BUSY bit is cleared causes the interface
to generate a Start condition.
Once the Start condition is generated, the periph-
eral is in master mode (I2CSR1.M/SL=1) and
I2CSR1.SB (Start bit) flag is set and an interrupt is
generated if the I2CCR.ITE bit is set (see Figure
128 Transfer sequencing EV5 event).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer.
The I2CSR2.BERR flag is set and an interrupt is
generated if I2CCR.ITE bit is set.
The interface waits for a read of the I2CSR1 regis-
ter followed by a write in the I2CDR register with
the Slave address, holding the SCL line low.
If it is a stop then the state machine is reset.
If it is a start then the state machine is reset and
it waits for the new slave address on the bus.
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Then the slave address is sent to the SDA line.
In 7-bit addressing mode, one address byte is
sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the
I2CSR1.EVF and I2CSR1.ADD10 bits to be set by
hardware with interrupt generation if the
I2CCR.ITE bit is set.
Then the master waits for a read of the I2CSR1
register followed by a write in the I2CDR register,
holding the SCL line low (see Figure 128 Trans-
fer sequencing EV9). Then the second address
byte is sent by the interface.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Master Receiver:
The master receives a byte from the SDA line into
the shift register and sends it to the I2CDR regis-
ter. It generates an acknowledge bit if the
I2CCR.ACK bit is set and an interrupt if the
I2CCR.ITE bit is set or a DMA is requested (see
Transfer sequencing EV7 event).
Then it waits for the microcontroller to read the
Data Register (I2CDR) or waits for the DMA to
complete both holding SCL line low.
After each address byte, an acknowledge clock
pulse is sent to the SCL line if the I2CSR1.EVF
and
– I2CSR1.ADD10 bit (if first header)
Error Cases
■ BERR: Detection of a Stop or a Start condition
during a byte transfer.
– I2CSR2.ADDTX bit (if address or second head-
er)
The I2CSR2.BERR flag is set and an interrupt is
generated if I2CCR.ITE is set.
are set, and an interrupt is generated if the
I2CCR.ITE bit is set.
■ AF: Detection of a no acknowledge bit
The I2CSR2.AF flag is set and an interrupt is
generated if I2CCR.ITE is set.
The peripheral waits for a read of the I2CSR1 reg-
ister followed by a write into the Control Register
(I2CCR) by holding the SCL line low (see Figure
128 Transfer sequencing EV6 event).
■ ARLO: Arbitration Lost
The I2CSR2.ARLO flag is set, the I2CSR1.M/SL
flag is cleared and the process is reset. An
interrupt is generated if the I2CCR.ITE bit is set.
If there was no acknowledge (I2CSR2.AF=1), the
master must stop or restart the communication
(set the I2CCR.START or I2CCR.STOP bits).
If there was an acknowledge, the state machine
enters a sending or receiving process according to
the data direction bit (least significant bit of the ad-
dress), the I2CSR1.BTF flag is set and an interrupt
is generated if I2CCR.ITE bit is set (see Transfer
sequencing EV7, EV8 events).
Note: In all cases, to resume communications, set
the I2CCR.START or I2CCR.STOP bits.
2
Events generated by the I C interface
■ STOP condition
When the I2CCR.STOP bit is set, a Stop
condition is generated after the transfer of the
current byte, the I2CSR1.M/SL flag is cleared
and the state machine is reset. No interrupt is
generated in master mode at the detection of
the stop condition.
If the master loses the arbitration of the bus there
is no acknowledge, the I2CSR2.AF flag is set and
the master must set the START or STOP bit in the
control register (I2CCR).The I2CSR2.ARLO flag is
set, the I2CSR1.M/SL flag is cleared and the proc-
ess is reset. An interrupt is generated if I2CCR.ITE
is set.
■ START condition
When the I2CCR.START bit is set, a start
2
condition is generated as soon as the I C bus is
Master Transmitter:
free. The I2CSR1.SB flag is set and an interrupt
is generated if the I2CCR.ITE bit is set.
The master waits for the microcontroller to write in
the Data Register (I2CDR) or it waits for the DMA
to complete both holding the SCL line low (see
Transfer sequencing EV8).
Then the byte is received into the shift register and
sent to the SDA line. When the acknowledge bit is
received, the I2CSR1.BTF flag is set and an
interrupt is generated if the I2CCR.ITE bit is set or
the DMA is requested.
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
Figure 128. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
Data2
Data2
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
A
DataN NA
DataN
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
DataN
....
A
P
r
.
EV1 EV3
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV5
EV9
EV6 EV8
EV8
EV8
A
10-bit Master receiver:
Legend:
S
Header
A
Data1
A
DataN
P
r
.....
EV5
EV6
EV7
EV7
S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA
is complete.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA
is complete.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register, BTF is cleared by releasing the
lines (STOP=1, STOP=0) or writing DR register (for example DR=FFh). Note: If lines are released by
STOP=1, STOP=0 the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
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I2C BUS INTERFACE
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, ADDTX=1, cleared by reading SR1 register followed by writing CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA
is complete.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA
is complete.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
Figure 129. Event Flags and Interrupt Generation
ADSL
SB
AF
IERRM
STOPF
ARLO
ERROR
INTERRUPT
REQUEST
BERR
ADD10
ADDTX
IERRP
ITE
DATA RECEIVED
or
END OF BLOCK
INTERRUPT
REQUEST
IRXM
BTF=1 & TRA=0
IRXP
ITE
REOBP
Receiving DMA
End Of Block
READY TO TRANSMIT
or
ITXM
BTF=1 & TRA=1
END OF BLOCK
INTERRUPT
REQUEST
ITXP
ITE
TEOBP
Transmitting DMA
End Of Block
I2CSR1.EVF
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
10.8.5 Interrupt Features
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
2
The I Cbus interface has three interrupt sources
related to “Error Condition”, “Peripheral Ready to
Transmit” and “Data Received”.
– Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
– Bus error, Start or Stop condition detected
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
The peripheral uses the ST9+ interrupt internal
protocol without requiring the use of the external
interrupt channel. Dedicated registers of the pe-
ripheral should be loaded with appropriate values
to set the interrupt vector (see the description of
the I2CIVR register), the interrupt mask bits (see
the description of the I2CIMR register) and the in-
terrupt priority and pending bits (see the descrip-
tion of the I2CISR register).
The peripheral also has a global interrupt enable
(the I2CCR.ITE bit) that must be set to enable the
interrupt features. Moreover there is a global inter-
rupt flag (I2CSR1.EVF bit) which is set when one
of the interrupt events occurs (except the End Of
Block interrupts - see the DMA Features section).
– Master has sent the header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
– Address byte successfully transmitted in
Master mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX=1)
Each interrupt source has a dedicated interrupt
address pointer vector stored in the I2CIVR regis-
ter. The five more significant bits of the vector ad-
dress are programmable by the customer, where-
as the three less significant bits are set by hard-
ware depending on the interrupt source:
– 010: error condition detected
– 100: data received
The “Data Received” interrupt source occurs after
the acknowledge of a received data byte is per-
formed. It is generated when the I2CSR1.BTF flag
is set and the I2CSR1.TRA flag is zero.
If the DMA feature is enabled in receiver mode,
this interrupt is not generated and the same inter-
rupt vector is used to send a Receiving End Of
Block interrupt (See the DMA feature section).
– 110: peripheral ready to transmit
The priority with respect to the other peripherals is
programmable by setting the PRL[2:0] bits in the
I2CISR register. The lowest interrupt priority is ob-
tained by setting all the bits (this priority level is
never acknowledged by the CPU and is equivalent
to disabling the interrupts of the peripheral); the
highest interrupt priority is programmed by reset-
ting all the bits. See the Interrupt and DMA chap-
ters for more details.
The “Peripheral Ready To Transmit” interrupt
source occurs as soon as a data byte can be
transmitted by the peripheral. It is generated when
the I2CSR1.BTF and the I2CSR1.TRA flags are
set.
If the DMA feature is enabled in transmitter mode,
this interrupt is not generated and the same inter-
rupt vector is used to send a Transmitting End Of
Block interrupt (See the DMA feature section).
The internal priority of the interrupt sources of the
peripheral is fixed by hardware with the following
order: “Error Condition” (highest priority), “Data
Received”, “Peripheral Ready to Transmit”.
Note: The DMA has the highest priority over the
interrupts; moreover the “Transmitting End Of
Block” interrupt has the same priority as the “Pe-
ripheral Ready to Transmit” interrupt and the “Re-
ceiving End Of Block” interrupt has the same prior-
ity as the “Data received” interrupt.
The “Error condition” interrupt source occurs when
one of the following condition occurs:
– Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
Each of these three interrupt sources has a pend-
ing bit (IERRP, IRXP, ITXP) in the I2CISR register
that is set by hardware when the corresponding in-
terrupt event occurs. An interrupt request is per-
formed only if the corresponding mask bit is set
(IERRM, IRXM, ITXM) in the I2CIMR register and
the peripheral has a proper priority level.
– Start condition generated
(I2CSR1.SB and I2CSR1.EVF flags = 1)
– No acknowledge received after byte transmis-
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
The pending bit has to be reset by software.
– Stop detected in Slave mode
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I C BUS INTERFACE (Cont’d)
Note: Until the pending bit is reset (while the cor-
responding mask bit is set), the peripheral proc-
esses an interrupt request. So, if at the end of an
interrupt routine the pending bit is not reset, anoth-
er interrupt request is performed.
ory addressed through the DMA Address Regis-
ter (or Register pair)
– A post-increment of the DMA Address Register
(or Register pair)
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
Note: Before the end of the transmission and re-
ception interrupt routines, the I2CSR1.BTF flag bit
should be checked, to acknowledge any interrupt
requests that occurred during the interrupt routine
and to avoid masking subsequent interrupt re-
quests.
2
The priority level of the DMA features of the I C
interface with respect to the other peripherals and
the CPU is the same as programmed in the
I2CISR register for the interrupt sources. In the in-
ternal priority level order of the peripheral, the “Er-
ror” interrupt sources have higher priority, followed
by DMA, “Data received” and “Receiving End Of
Block” interrupts, “Peripheral Ready to Transmit”
and “Transmitting End Of Block”.
Note: The “Error” event interrupt pending bit
(I2CISR.IERRP) is forced high when the error
event flags are set (ADD10, ADSL and SB flags of
the I2CSR1 register; SCLF, ADDTX, AF, STOPF,
ARLO and BERR flags of the I2CSR2 register).
Refer to the Interrupt and DMA chapters for details
on the priority levels.
Moreover the Transmitting End Of Block interrupt
has the same priority as the “Peripheral Ready to
Transmit” interrupt and the Receiving End Of
Block interrupt has the same priority as the “Data
received” interrupt.
The DMA features are enabled by setting the cor-
responding enabling bits (RXDM, TXDM) in the
I2CIMR register. It is possible to select also the di-
rection of the DMA transactions.
Once the DMA transfer is completed (the transac-
tion counter reaches 0 value), an interrupt request
to the CPU is generated. This kind of interrupt is
called “End Of Block”. The peripheral sends two
different “End Of Block” interrupts depending on
the direction of the DMA (Receiving End Of Block -
Transmitting End Of Block). These interrupt
sources have dedicated interrupt pending bits in
the I2CIMR register (REOBP, TEOBP) and they
are mapped on the same interrupt vectors as re-
spectively “Data Received” and “Peripheral Ready
to Transmit” interrupt sources. The same corre-
spondence exists about the internal priority be-
tween interrupts.
10.8.6 DMA Features
The peripheral can use the ST9+ on-chip Direct
Memory Access (DMA) channels to provide high-
speed data transaction between the peripheral
and contiguous locations of Register File, and
Memory. The transactions can occur from and to-
ward the peripheral. The maximum number of
transactions that each DMA channel can perform
is 222 if the register file is selected or 65536 if
memory is selected. The control of the DMA fea-
tures is performed using registers placed in the pe-
ripheral register page (I2CISR, I2CIMR,
I2CRDAP, I2CRDC, I2CTDAP, I2CTDC).
Note: The I2CCR.ITE bit has no effect on the End
Of Block interrupts.
Moreover, the I2CSR1.EVF flag is not set by the
End Of Block interrupts.
Each DMA transfer consists of three operations:
– A load from/to the peripheral data register
(I2CDR) to/from a location of Register File/Mem-
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2
I C BUS INTERFACE (Cont’d)
10.8.6.1 DMA between Peripheral and Register
File
The Transaction Counter registers pair must be in-
itialized with the number of DMA transfers to per-
form and will be decremented after each transac-
tion. The DMA Address register pair must be ini-
tialized with the starting address of the DMA table
in the Memory Space, and it is increased after
each transaction. These two register pairs must be
located between addresses 00h and DFh of the
Register File.
If the DMA transaction is made between the pe-
ripheral and the Register File, one register is
required to hold the DMA Address and one to hold
the DMA transaction counter.
These two registers must be located in the Regis-
ter File:
– the DMA Address Register in the even ad-
dressed register,
10.8.6.3 DMA in Master Receive
To correctly manage the reception of the last byte
when the DMA in Master Receive mode is used,
the following sequence of operations must be per-
formed:
– the DMA Transaction Counter in the following
register (odd address).
They are pointed to by the DMA Transaction
Counter Pointer Register (I2CRDC register in re-
ceiving, I2CTDC register in transmitting) located in
the peripheral register page.
1. The number of data bytes to be received must
be set to the effective number of bytes minus
one byte.
In order to select the DMA transaction with the
Register File, the control bit I2CRDC.RF/MEM in
receiving mode or I2CTDC.RF/MEM in transmit-
ting mode must be set.
2. When the Receiving End Of Block condition
occurs, the I2CCR.STOP bit must be set and
the I2CCR.ACK bit must be reset.
The last byte of the reception sequence can be re-
ceived either using interrupts/polling or using
DMA. If the user wants to receive the last byte us-
ing DMA, the number of bytes to be received must
be set to 1, and the DMA in reception must be re-
enabled (IMR.RXDM bit set) to receive the last
byte. Moreover the Receiving End Of Block inter-
rupt service routine must be designed to recognize
and manage the two different End Of Block situa-
tions (after the first sequence of data bytes and af-
ter the last data byte).
The transaction Counter Register must be initial-
ized with the number of DMA transfers to perform
and will be decremented after each transaction.
The DMA Address Register must be initialized with
the starting address of the DMA table in the Regis-
ter File, and it is increased after each transaction.
These two registers must be located between ad-
dresses 00h and DFh of the Register File.
When the DMA occurs between Peripheral and
Register File, the I2CTDAP register (in transmis-
sion) and the I2CRDAP one (in reception) are not
used.
10.8.6.2 DMA between Peripheral and Memory
Space
If the DMA transaction is made between the pe-
ripheral and Memory, a register pair is required to
hold the DMA Address and another register pair to
hold the DMA Transaction counter. These two
pairs of registers must be located in the Register
File. The DMA Address pair is pointed to by the
DMA Address Pointer Register (I2CRDAP register
in reception, I2CTDAP register in transmission) lo-
cated in the peripheral register page; the DMA
Transaction Counter pair is pointed to by the DMA
Transaction Counter Pointer Register (I2CRDC
register in reception, I2CTDC register in transmis-
sion) located in the peripheral register page.
In order to select the DMA transaction with the
Memory Space, the control bit I2CRDC.RF/MEM
in receiving mode or I2CTDC.RF/MEM in transmit-
ting mode must be reset.
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
10.8.7 Register Description
1: The General Call address stored in the I2CADR
register will be acknowledged
Note: The correct value (usually 00h) must be
written in the I2CADR register before enabling the
General Call feature.
IMPORTANT:
1. To guarantee correct operation, before enabling
the peripheral (while I2CCR.PE=0), configure bit7
and bit6 of the I2COAR2 register according to the
internal clock INTCLK (for example 11xxxxxxb in
the range 14 - 30 MHz).
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0) or when the Start condition is
sent (with interrupt generation if ITE=1).
– In master mode:
2. Bit7 of the I2CCR register must be cleared.
2
I C CONTROL REGISTER (I2CCR)
0: No start generation
R240 - Read / Write
1: Repeated start generation
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
– In slave mode:
0: No start generation (reset value)
1: Start generation when the bus is free
7
0
Bit 2 = ACK Acknowledge enable.
0
0
PE
ENGC START ACK STOP ITE
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0).
Bit 7:6 = Reserved
Must be cleared
0: No acknowledge returned (reset value)
1: Acknowledge returned after an address byte or
a data byte is received
Bit 5 = PE Peripheral Enable.
This bit is set and cleared by software.
0: Peripheral disabled (reset value)
1: Master/Slave capability
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. It is not
cleared when the interface is disabled
(I2CCR.PE=0). In slave mode, this bit must be set
only when I2CSR1.BTF=1.
Notes:
– When I2CCR.PE=0, all the bits of the I2CCR
register and the I2CSR1-I2CSR2 registers ex-
cept the STOP bit are reset. All outputs will be re-
leased while I2CCR.PE=0
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When I2CCR.PE=1, the corresponding I/O pins
are selected by hardware as alternate functions
(open drain).
2
– To enable the I C interface, write the I2CCR reg-
ister TWICE with I2CCR.PE=1 as the first write
only activates the interface (only I2CCR.PE is
set).
– In slave mode:
0: No stop generation (reset value)
1: Release SCL and SDA lines after the current
byte transfer (I2CSR1.BTF=1). In this mode the
STOP bit has to be cleared by software.
– When PE=1, the FREQ[2:0] and EN10BIT bits in
the I2COAR2 and I2CADR registers cannot be
written. The value of these bits can be changed
only when PE=0.
Bit 4 = ENGC General Call address enable.
Setting this bit the peripheral works as a slave and
the value stored in the I2CADR register is recog-
nized as device address.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0).
0: The address stored in the I2CADR register is
ignored (reset value)
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
Bit 0 = ITE Interrupt Enable.
I C STATUS REGISTER 1 (I2CSR1)
R241 - Read Only
The ITE bit enables the generation of interrupts.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(I2CCR.PE=0).
0: Interrupts disabled (reset value)
1: Interrupts enabled after any of the following con-
ditions:
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
7
0
EVF ADD10 TRA
BUSY BTF ADSL M/SL
SB
– Byte received or to be transmitted
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
Note: Some bits of this register are reset by a read
operation of the register. Care must be taken when
using instructions that work on single bit. Some of
them perform a read of all the bits of the register
before modifying or testing the wanted bit. So oth-
er bits of the register could be affected by the op-
eration.
In the same way, the test/compare operations per-
form a read operation.
Moreover, if some interrupt events occur while the
register is read, the corresponding flags are set,
and correctly read, but if the read operation resets
the flags, no interrupt request occurs.
– Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
– Start condition generated
(I2CSR1.SB and I2CSR1.EVF flags = 1)
– No acknowledge received after byte transmis-
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
– Stop detected in Slave mode
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
– Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
– Bus error, Start or Stop condition detected
during data transfer
Bit 7 = EVF Event Flag.
This bit is set by hardware as soon as an event (
listed below or described in Figure 128) occurs. It
is cleared by software when all event conditions
that set the flag are cleared. It is also cleared by
hardware when the interface is disabled
(I2CCR.PE=0).
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
– Master has sent header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
– Address byte successfully transmitted in Mas-
ter mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX = 1)
0: No event
1: One of the following events has occurred:
SCL is held low when the ADDTX flag of the
I2CSR2 register or the ADD10, SB, BTF or ADSL
flags of I2CSR1 register are set (See Figure 128)
or when the DMA is not complete.
The transfer is suspended in all cases except
when the BTF bit is set and the DMA is enabled. In
this case the event routine must suspend the DMA
transfer if it is required.
– Byte received or to be transmitted
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
– Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
– Start condition generated
(I2CSR1.SB and I2CSR1.EVF flags = 1)
– No acknowledge received after byte transmis-
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
– Stop detected in Slave mode
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
– Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
– Bus error, Start or Stop condition detected
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
– Master has sent header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
– Address byte successfully transmitted in Mas-
ter mode.
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. BTF is
cleared by reading I2CSR1 register followed by
writing the next byte in I2CDR register or when
DMA is complete.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX=1)
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set when the master has sent the first
byte in 10-bit address mode. An interrupt is gener-
ated if ITE=1.
It is cleared by software reading I2CSR1 register
followed by a write in the I2CDR register of the
second address byte. It is also cleared by hard-
ware when peripheral is disabled (I2CCR.PE=0)
or when the STOPF bit is set.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading I2CSR1 reg-
ister followed by reading the byte from I2CDR
register or when DMA is complete.
The SCL line is held low while I2CSR1.BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
0: No ADD10 event occurred.
1: Master has sent first address byte (header).
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware if the received slave ad-
dress matches the I2COAR1/I2COAR2 register
content or a General Call address. An interrupt is
generated if ITE=1. It is cleared by software
reading I2CSR1 register or by hardware when the
interface is disabled (I2CCR.PE=0). The SCL line
is held low while ADSL=1.
Bit 5 = TRA Transmitter/ Receiver.
When BTF flag of this register is set and also
TRA=1, then a data byte has to be transmitted. It is
cleared automatically when BTF is cleared. It is
also cleared by hardware after the STOPF flag of
I2CSR2 register is set, loss of bus arbitration
(ARLO flag of I2CSR2 register is set) or when the
interface is disabled (I2CCR.PE=0).
0: Address mismatched or not received
1: Received address matched
0: A data byte is received (if I2CSR1.BTF=1)
1: A data byte can be transmitted (if
I2CSR1.BTF=1)
Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface
is in Master mode (Start condition generated on
the lines after the I2CCR.START bit is set). It is
cleared by hardware after detecting a Stop condi-
tion on the bus or a loss of arbitration (ARLO=1). It
is also cleared when the interface is disabled
(I2CCR.PE=0).
Bit 4 = BUSY Bus Busy.
It indicates a communication in progress on the
bus. The detection of the communications is al-
ways active (even if the peripheral is disabled).
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. This information is still updated
when the interface is disabled (I2CCR.PE=0).
0: No communication on the bus
0: Slave mode
1: Master mode
1: Communication ongoing on the bus
Bit 0 = SB Start Bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following a write of
START=1 if the bus is free). An interrupt is gener-
ated if ITE=1. It is cleared by software reading
I2CSR1 register followed by writing the address
byte in I2CDR register. It is also cleared by hard-
Bit 3 = BTF Byte Transfer Finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or before the transmission of a data
byte with interrupt generation if ITE=1. It is cleared
by software reading I2CSR1 register followed by a
read or write of I2CDR register or when DMA is
complete. It is also cleared by hardware when the
interface is disabled (I2CCR.PE=0).
ware
when
the
interface
is
disabled
(I2CCR.PE=0).
The SCL line is held low while SB=1.
0: No Start condition
1: Start condition generated
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 2 (I2CSR2)
Bit 3 = STOPF Stop Detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge. An
interrupt is generated if ITE=1.
R242 - Read Only
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
It is cleared by software reading I2CSR2 register
or by hardware when the interface is disabled
(I2CCR.PE=0).
7
0
0
0
ADDTX AF STOPF ARLO BERR GCAL
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
Note: Some bits of this register are reset by a read
operation of the register. Care must be taken when
using instructions that work on single bit. Some of
them perform a read of all the bits of the register
before modifying or testing the wanted bit. So oth-
er bits of the register could be affected by the op-
eration.
In the same way, the test/compare operations per-
form a read operation.
Moreover, if some interrupt events occur while the
register is read, the corresponding flags are set,
and correctly read, but if the read operation resets
the flags, no interrupt request occurs.
1: Stop condition detected (while slave receiver)
Bit 2 = ARLO Arbitration Lost.
This bit is set by hardware when the interface (in
master mode) loses the arbitration of the bus to
another master. An interrupt is generated if ITE=1.
It is cleared by software reading I2CSR2 register
or by hardware when the interface is disabled
(I2CCR.PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 1 = BERR Bus Error.
Bit 5 = ADDTX Address or 2nd header transmitted
in Master mode.
This bit is set by hardware when the peripheral,
enabled in Master mode, has received the ac-
knowledge relative to:
This bit is set by hardware when the interface de-
tects a Start or Stop condition during a byte trans-
fer. An interrupt is generated if ITE=1.
It is cleared by software reading I2CSR2 register
or by hardware when the interface is disabled
(I2CCR.PE=0).
– Address byte in 7-bit mode
The SCL line is not held low while BERR=1.
Note: If a misplaced start condition is detected,
also the ARLO flag is set; moreover, if a misplaced
stop condition is placed on the acknowledge SCL
pulse, also the AF flag is set.
– Address or 2nd header byte in 10-bit mode.
0: No address or 2nd header byte transmitted
1: Address or 2nd header byte transmitted.
Bit 4 = AF Acknowledge Failure.
0: No Start or Stop condition detected during byte
transfer
1: Start or Stop condition detected during byte
transfer
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1.
It is cleared by software reading I2CSR2 register
after the falling edge of the acknowledge SCL
pulse, or by hardware when the interface is disa-
bled (I2CCR.PE=0).
Bit 0 = GCAL General Call address matched.
This bit is set by hardware after an address
matches with the value stored in the I2CADR reg-
ister while ENGC=1. In the I2CADR the General
Call address must be placed before enabling the
peripheral.
The SCL line is not held low while AF=1.
0: No acknowledge failure detected
1: A data or address byte was not acknowledged
It is cleared by hardware after the detection of a
Stop condition, or when the peripheral is disabled
(I2CCR.PE=0).
0: No match
1: General Call address matched.
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
2
I C CLOCK CONTROL REGISTER
(I2CCCR)
I C OWN ADDRESS REGISTER 1
(I2COAR1)
R243 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
R244 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
2
Bit 7 = FM/SM Fast/Standard I C mode.
7-bit Addressing Mode
This bit is used to select between fast and stand-
ard mode. See the description of the following bits.
It is set and cleared by software. It is not cleared
when the peripheral is disabled (I2CCR.PE=0)
Bits 7:1 = ADD[7:1] Interface address.
2
These bits define the I C bus address of the inter-
face.
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
Bits 6:0 = CC[6:0] 9-bit divider programming
Implementation of a programmable clock divider.
These bits and the CC[8:7] bits of the I2CECCR
Bit 0 = ADD0 Address direction bit.
This bit is don’t care; the interface acknowledges
either 0 or 1.
It is not cleared when the interface is disabled
(I2CCR.PE=0).
register select the speed of the bus (F
) de-
SCL
2
pending on the I C mode.
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
Note: Address 01h is always ignored.
Refer to the Electrical Characteristics section for
the table of values (Table 70 on page 398).
10-bit Addressing Mode
Note: The programmed frequency is available
with no load on SCL and SDA pins.
Bits 7:0 = ADD[7:0] Interface address.
2
These are the least significant bits of the I Cbus
address of the interface.
They are not cleared when the interface is disa-
bled (I2CCR.PE=0).
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
I C OWN ADDRESS REGISTER 2 (I2COAR2)
are not cleared when the interface is disabled
(I2CCR.PE=0).
R245 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
Bit 0 = Reserved.
7
0
2
I C DATA REGISTER (I2CDR)
FREQ1 FREQ0 EN10BIT FREQ2
0
ADD9 ADD8
0
R246 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
Bits 7:6,4 = FREQ[2:0] Frequency bits.
IMPORTANT: To guarantee correct operation,
set these bits before enabling the interface
(while I2CCR.PE=0).
7
0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
These bits can be set only when the interface is
disabled (I2CCR.PE=0). To configure the interface
Bits 7:0 = DR[7:0] I2C Data.
2
to I C specified delays, select the value corre-
– In transmitter mode:
sponding to the microcontroller internal frequency
INTCLK.
I2CDR contains the next byte of data to be trans-
mitted. The byte transmission begins after the
microcontroller has written in I2CDR or on the
next rising edge of the clock if DMA is complete.
INTCLK
Range
(MHz)
FREQ2
FREQ1
FREQ0
– In receiver mode:
2.5 - 6
6- 10
0
0
0
0
0
0
1
1
0
1
0
1
I2CDR contains the last byte of data received.
The next byte receipt begins after the I2CDR
read by the microcontroller or on the next rising
edge of the clock if DMA is complete.
10- 14
14 - 24
GENERAL CALL ADDRESS (I2CADR)
R247 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 1010 0000 (A0h)
Note: If an incorrect value, with respect to the
MCU internal frequency, is written in these bits,
2
the timings of the peripheral will not meet the I C
bus standard requirements.
7
0
Note: The FREQ[2:0] = 100, 101, 110, 111 config-
urations must not be used.
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
2
2
Bit 5 = EN10BIT Enable 10-bit I Cbus mode.
Bits 7:0 = ADR[7:0] Interface address.
2
When this bit is set, the 10-bit I Cbus mode is en-
These bits define the I Cbus General Call address
abled.
of the interface. It must be written with the correct
value depending on the use of the peripheral.If the
This bit can be written only when the peripheral is
disabled (I2CCR.PE=0).
0: 7-bit mode selected
2
peripheral is used in I C bus mode, the 00h value
must be loaded as General Call address.
The customer could load the register with other
values.
1: 10-bit mode selected
The bits can be written only when the peripheral is
disabled (I2CCR.PE=0)
Bits 4:3 = Reserved.
The ADR0 bit is don’t care; the interface acknowl-
edges either 0 or 1.
Note: Address 01h is always ignored.
Bits 2:1 = ADD[9:8] Interface address.
2
These are the most significant bits of the I Cbus
address of the interface (10-bit mode only). They
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
INTERRUPT STATUS REGISTER (I2CISR)
R248 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 1xxx xxxx (xxh)
Note: The Interrupt pending bits can be reset by
writing a “0” but is not possible to write a “1”. It is
mandatory to clear the interrupt source by writing a
“0” in the pending bit when executing the interrupt
service routine. When serving an interrupt routine,
the user should reset ONLY the pending bit related
to the served interrupt routine (and not reset the
other pending bits).
7
0
1
PRL2 PRL1 PRL0
0
IERRP IRXP ITXP
To detect the specific error condition that oc-
curred, the flag bits of the I2CSR1 and I2CSR2
register should be checked.
Bit 7 = Reserved.
Must be kept at 1
Note: The IERRP pending bit is forced high when-
the error event flags are set (ADSL and SB flags in
the I2CSR1 register, SCLF, ADDTX, AF, STOPF,
ARLO and BERR flags in the I2CSR2 register). If
at least one flag is set, the application code should
not reset the IERRP bit.
Bits 6:4 = PRL[2:0] Interrupt/DMA Priority Bits.
The priority is encoded with these three bits. The
value of “0” has the highest priority, the value “7”
has no priority. After the setting of this priority lev-
el, the priorities between the different Interrupt/
DMA sources is hardware defined according with
the following scheme:
Bit 1 = IRXP Data Received pending bit
0: No data received
1: data received (if ITE=1).
– Error condition Interrupt (If DMASTOP=1) (High-
est priority)
– Receiver DMA request
Bit 0 = ITXP Peripheral Ready To Transmit pend-
– Transmitter DMA request
ing bit
– Error Condition Interrupt (If DMASTOP=0
– Data Received/Receiver End Of Block
0: Peripheral not ready to transmit
1: Peripheral ready to transmit a data byte (if
ITE=1).
– Peripheral Ready To Transmit/Transmitter End
Of Block (Lowest priority)
Bit 3 = Reserved.
Must be cleared.
Bit 2 = IERRP Error Condition pending bit
0: No error
1: Error event detected (if ITE=1)
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I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
INTERRUPT VECTOR REGISTER (I2CIVR)
R249 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: Undefined
(DMA between peripheral and Register file), this
register has no meaning.
See Section 10.8.6.1 for more details on the use
of this register.
7
0
Bit 0 = RPS Receiver DMA Memory Pointer Selec-
tor.
If memory has been selected for DMA transfer
(I2CRDC.RF/MEM = 0) then:
V7
V6
V5
V4
V3 EV2 EV1
0
0: Select ISR register for Receiver DMA transfer
address extension.
1: Select DMASR register for Receiver DMA trans-
fer address extension.
Bits 7:3 = V[7:3] Interrupt Vector Base Address.
User programmable interrupt vector bits. These
are the five more significant bits of the interrupt
vector base address. They must be set before en-
abling the interrupt features.
RECEIVER DMA TRANSACTION COUNTER
REGISTER (I2CRDC)
Bits 2:1 = EV[2:1] Encoded Interrupt Source.
These Read-Only bits are set by hardware accord-
ing to the interrupt source:
R251 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: Undefined
– 01: error condition detected
– 10: data received
7
0
– 11: peripheral ready to transmit
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RF/MEM
Bit 0 = Reserved.
Bits 7:1 = RC[7:1] Receiver DMA Counter Pointer.
I2CRDC contains the address of the pointer (in the
Register File) of the DMA receiver transaction
counter when the DMA between Peripheral and
Memory Space is selected. Otherwise (DMA be-
tween Peripheral and Register File), this register
points to a pair of registers that are used as DMA
Address register and DMA Transaction Counter.
See Section 10.8.6.1 and Section 10.8.6.2 for
more details on the use of this register.
Forced by hardware to 0.
RECEIVER DMA SOURCE ADDRESS POINTER
REGISTER (I2CRDAP)
R250 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: Undefined
7
0
RA7 RA6 RA5 RA4 RA3 RA2 RA1
RPS
Bit 0 = RF/MEM Receiver Register File/ Memory
Selector.
0: DMA towards Memory
Bits 7:1 = RA[7:1] Receiver DMA Address Pointer.
I2CRDAP contains the address of the pointer (in
the Register File) of the Receiver DMA data
source when the DMA is selected between the
peripheral and the Memory Space. Otherwise,
1: DMA towards Register file
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
TRANSMITTER DMA SOURCE ADDRESS
POINTER REGISTER (I2CTDAP)
R252 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: Undefined
TRANSMITTER DMA TRANSACTION COUN-
TER REGISTER (I2CTDC)
R253 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: Undefined
7
0
7
0
TA7 TA6 TA5 TA4 TA3 TA2 TA1
TPS
TC7 TC6 TC5 TC4 TC3 TC2 TC1 RF/MEM
Bits 7:1= TA[7:1] Transmit DMA Address Pointer.
I2CTDAP contains the address of the pointer (in
the Register File) of the Transmitter DMA data
source when the DMA between the peripheral and
the Memory Space is selected. Otherwise (DMA
between the peripheral and Register file), this reg-
ister has no meaning.
Bits 7:1 = TC[7:1] Transmit DMA Counter Pointer.
I2CTDC contains the address of the pointer (in the
Register File) of the DMA transmitter transaction
counter when the DMA between Peripheral and
Memory Space is selected. Otherwise, if the DMA
between Peripheral and Register File is selected,
this register points to a pair of registers that are
used as DMA Address register and DMA Transac-
tion Counter.
See Section 10.8.6.2 for more details on the use
of this register.
See Section 10.8.6.1 and Section 10.8.6.2 for
more details on the use of this register.
Bit 0 = TPS Transmitter DMA Memory Pointer Se-
lector.
If memory has been selected for DMA transfer
(I2CTDC.RF/MEM = 0) then:
0: Select ISR register for transmitter DMA transfer
address extension.
1: Select DMASR register for transmitter DMA
transfer address extension.
Bit 0 = RF/MEM Transmitter Register File/ Memo-
ry Selector.
0: DMA from Memory
1: DMA from Register file
EXTENDED CLOCK CONTROL REGISTER
(I2CECCR)
R254 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
CC8 CC7
Bits 7:2 = Reserved. Must always be cleared.
Bits 1:0 = CC[8:7] 9-bit divider programming
Implementation of a programmable clock divider.
These bits and the CC[6:0] bits of the I2CCCR reg-
ister select the speed of the bus (F
).
SCL
For a description of the use of these bits, see the
I2CCCR register.
They are not cleared when the interface is disa-
bled (I2CCCR.PE=0).
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
INTERRUPT MASK REGISTER (I2CIMR)
R255 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 00xx 0000 (x0h)
interrupt request.
Note: TEOBP can only be written to “0”.
0: End of block not reached
1: End of data block in DMA transmitter detected.
7
0
Bit 3 = Reserved. This bit must be cleared.
RXDM TXDM REOBP TEOBP
0
IERRM IRXM ITXM
Bit 2 = IERRM Error Condition interrupt mask bit.
This bit enables/ disables the Error interrupt.
0: Error interrupt disabled.
Bit 7 = RXDM Receiver DMA Mask.
0: DMA reception disable.
1: DMA reception enable
1: Error Interrupt enabled.
RXDM is reset by hardware when the transaction
counter value decrements to zero, that is when a
Receiver End Of Block interrupt is issued.
Bit 1 = IRXM Data Received interrupt mask bit.
This bit enables/ disables the Data Received and
Receive DMA End of Block interrupts.
0: Interrupts disabled
Bit 6 = TXDM Transmitter DMA Mask.
0: DMA transmission disable.
1: DMA transmission enable.
TXDM is reset by hardware when the transaction
counter value decrements to zero, that is when a
Transmitter End Of Block interrupt is issued.
1: Interrupts enabled
Note: This bit has no effect on DMA transfer
Bit 0 = ITXM Peripheral Ready To Transmit inter-
rupt mask bit.
This bit enables/ disables the Peripheral Ready To
Transmit and Transmit DMA End of Block inter-
rupts.
Bit 5 = REOBP Receiver DMA End Of Block Flag.
REOBP should be reset by software in order to
avoid undesired interrupt routines, especially in in-
itialization routine (after reset) and after entering
the End Of Block interrupt routine.Writing “0” in
this bit will cancel the interrupt request
0: Interrupts disabled
1: Interrupts enabled
Note: This bit has no effect on DMA transfer.
Note: REOBP can only be written to “0”.
0: End of block not reached.
1: End of data block in DMA receiver detected
Bit 4 = TEOBP Transmitter DMA End Of Block TE-
OBP should be reset by software in order to avoid
undesired interrupt routines, especially in initializa-
tion routine (after reset) and after entering the End
Of Block interrupt routine.Writing “0” will cancel the
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9
I2C BUS INTERFACE
2
I C BUS INTERFACE (Cont’d)
2
Table 51. I C BUS Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
I2CCR
-
-
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Reset Value
0
0
I2CSR1
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
Reset Value
I2CSR2
-
0
0
ADDTX
0
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
Reset Value
0
I2CCCR
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
Reset Value
I2COAR1
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
Reset Value
I2COAR2
FREQ1
0
FREQ0 EN10BIT FREQ2
0
0
ADD9
0
ADD8
0
0
0
Reset Value
0
0
0
I2CDR
DR7
0
DR6
0
DR5
0
DR4
0
DR3
0
DR2
0
DR1
0
DR0
0
Reset Value
I2CADR
ADR7
1
ADR6
0
ADR5
1
ADR4
0
ADR3
0
ADR2
0
ADR1
0
ADR0
0
Reset Value
I2CISR
DMASTOP
1
PRL2
X
PRL1
X
PRL0
X
IERRP
X
IRXP
X
ITXP
X
Reset Value
X
I2CIVR
V7
X
V6
X
V5
X
V4
X
V3
X
EV2
X
EV1
X
0
0
Reset Value
I2CRDAP
RA7
X
RA6
X
RA5
X
RA4
X
RA3
X
RA2
X
RA1
X
RPS
X
Reset Value
I2CRDC
RC7
X
RC6
X
RC5
X
RC4
X
RC3
X
RC2
X
RC1
X
RF/MEM
X
Reset Value
I2CTDAP
TA7
X
TA6
X
TA5
X
TA4
X
TA3
X
TA2
X
TA1
X
TPS
X
Reset Value
I2CTDC
TC7
X
TC6
X
TC5
X
TC4
X
TC3
X
TC2
X
TC1
X
RF/MEM
X
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
CC8
0
CC7
0
I2CECCR
I2CIMR
RXDM
0
TXDM
0
REOBP
X
TEOBP
X
IERRM
0
IRXM
0
ITXM
0
Reset Value
0
10.8.8 IMPORTANT NOTES ON I2C
Please refer to Section 13.1.3 on page 410
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9
J1850 Byte Level Protocol Decoder (JBLPD)
10.9 J1850 Byte Level Protocol Decoder (JBLPD)
10.9.1 Introduction
10.9.2 Main Features
■ SAE J1850 compatible
■ Digital filter
The JBLPD is used to exchange data between the
ST9 microcontroller and an external J1850 trans-
ceiver I.C.
■ In-Frame Responses of type 0, 1, 2, 3 supported
The JBLPD transmits a string of variable pulse
width (VPW) symbols to the transceiver. It also re-
ceives VPW encoded symbols from the transceiv-
er, decodes them and places the data in a register.
with automatic normalization bit
■ Programmable External Loop Delay
■ Diagnostic 4x time mode
■ Diagnostic Local Loopback mode
In-frame responses of type 0, 1, 2 and 3 are sup-
ported and the appropriate normalization bit is
generated automatically. The JBLPD filters out
any incoming messages which it does not care to
receive. It also includes a programmable external
loop delay.
■ Wide range of MCU internal frequencies
allowed
■ Low power consumption mode (JBLPD
suspended)
■ Very low power consumption mode (JBLPD
disabled)
■ Don’t care message filter
The JBLPD uses two signals to communicate with
the transceiver:
– VPWI (input)
■ Selectable VPWI input polarity
■ Selectable Normalization Bit symbol form
■ 6 maskable interrupts
– VPWO (output)
■ DMA transmission and reception with End Of
Block interrupts
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 130. JBLPD Byte Level Protocol Decoder Block Diagram
RXDATA
VPW
DIGITAL
FILTER
VPWI pin
DECODER
STATUS
ERROR
ARBITRATION
CHECKER
CONTROL
JBLPD
STATE
I.D. Filter
FREG[0:31]
MACHINE
CRC
GENERATOR
LOOPBACK
LOGIC
OPTIONS
TXOP
CLKSEL
CLOCK
PRESCALER
CRC BYTE
CRC\ BYTE
PADDR
Prescaled Clock
(Encoder/Decoder
Clock)
VPW
ENCODER
MUX
VPWO pin
TXDATA
Interrupt & DMA Logic and Registers
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.3 Functional Description
In the case of the reception of an invalid bit, the
JBLPD peripheral will set the IBD bit in the ER-
ROR register. The JBLPD peripheral shall termi-
nate any transmissions in progress, and disable
receive transfers and RDRF flags until the VPW
decoder recognizes a valid EOF symbol from the
bus.
10.9.3.1 J1850 protocol symbols
J1850 symbols are defined as a duration (in micro-
seconds or clock cycles) and a state which can be
either an active state (logic high level on VPWO)
or a passive state (logic low level on VPWO).
An idle J1850 bus is in a passive state.
Any symbol begins by changing the state of the
VPW line. The line is in this state for a specific du-
ration depending on the symbol being transmitted.
The JBLPD’s state machine handles all the Tv
l.D.s in accordance with the SAE J1850 specifica-
tion.
Note: Depending on the value of a control bit, the
polarity of the VPWI input can be the same as the
J1850 bus or inverted with respect to it.
Durations, and hence symbols, are measured as
time between successive state transitions. Each
symbol has only one level transition of a specific
duration.
Symbols for logic zero and one data bits can be ei-
ther a high or a low level, but all other symbols are
defined at only one level.
Table 52. J1850 Symbol definitions
Symbol
Data Bit Zero
Definition
Each symbol is placed directly next to another.
Therefore, every level transition means that anoth-
er symbol has begun.
Passive for Tv1 or Ac-
tive for Tv2
Passive for Tv2 or Ac-
tive for Tv1
Data Bit One
Data bits of a logic zero are either a short duration
if in a passive state or a long duration if in an active
state. Data bits of a logic one are either a long du-
ration if in a passive state or a short duration if in
an active state. This ensures that data logic zeros
predominate during bus arbitration.
Start of Frame (SOF)
End of Data (EOD)
Active for Tv3
Passive for Tv3
Passive for Tv4
Passive for Tv6
Passive for > Tv6
Active for Tv1 or Tv2
Active for Tv5
End of Frame (EOF)
Inter Frame Separation (IFS)
IDLE Bus Condition (IDLE)
Normalization Bit (NB)
Break (BRK)
An eight bit data byte transmission will always
have eight transitions. For all data byte and CRC
byte transfers, the first bit is a passive state and
the last bit is an active state.
For the duration of the VPW, symbols are ex-
pressed in terms of Tv’s (or VPW mode timing val-
ues). J1850 symbols and Tv values are described
in the SAE J1850 specification, in Table 52 and in
Table 53.
Table 53. J1850 VPW Mode Timing Value (Tv)
definitions (in clock cycles)
Pulse Width
or Tv I.D.
Minimum
Duration
Nominal
Duration
Maximum
Duration
An ignored Tv I.D. occurs for level transitions
which occur in less than the minimum time re-
quired for an invalid bit detect. The VPW encoder
does not recognize these characters as they are
filtered out by the digital filter. The VPW decoder
does not resynchronize its counter with either
edge of “ignored” pulses. Therefore, the counter
which times symbols continues to time from the
last transition which occurred after a valid symbol
(including the invalid bit symbol) was recognized.
Ignored
Invalid Bit
Tv1
0
N/A
<=7
>7
N/A
64
<=34
<=96
<=163
<=239
N/A
>34
Tv2
>96
128
200
280
300
300
Tv3
>163
>239
>239
>280
Tv4
Tv5
N/A
A symbol recognized as an invalid bit will resyn-
chronize the VPW decoder to the invalid bit edges.
Tv6
N/A
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.3.2 Transmitting Messages
chronize off the decoder output to time the VPWO
symbol time.
This section describes the general procedures
used by the JBLPD to successfully transmit J1850
frames of data out the VPWO pin. The first five
sub-sections describe the procedures used for
transmitting the specific transmit data types. The
last section goes into the details of the transmitted
symbol timing, synchronizing of symbols received
from the external J1850 bus, and how data bit ar-
bitration works.
A detailed description of the JBLPD opcodes can
be find in the description of the OP[2:0] bits in the
TXOP register.
Message Byte String Transmission (Type 0
IFR)
Message byte transmitting is the outputting of data
bytes on the VPWO pin that occurs subsequent to
a received bus idle condition. All message byte
strings start with a SOF symbol transmission, then
one or more data bytes are transmitted. A CRC
byte is then transmitted followed by an EOD sym-
bol (see Figure 131) to complete the transmission.
If transmission is queued while another frame is
being received, then the JBLPD will time an Inter-
Frame Separation (IFS) time (Tv6) before com-
mencing with the SOF character.
The important concept to note for transmitting data
is: the activity sent over the VPWO line should be
timed with respect to the levels and transitions
seen on the filtered VPWI line.
The J1850 bus is a multiplexed bus, and the
VPWO & VPWI pins interface to this bus through a
transceiver I.C. Therefore, the propagation delay
through the transceiver I.C. and external bus filter-
ing must be taken into account when looking for
transmitted edges to appear back at the receiver.
The external propagation delay for an edge sent
out on the VPWO line, to be detected on the VPWI
The user program will decide at some point that it
wants to initiate a message byte string. The user
program writes the TXDATA register with the first
message data byte to be transmitted. Next, the
TXOP register is written with the MSG opcode if
more than one data byte is contained within the
message, or with MSG+CRC opcode if one data
byte is to be transmitted. The action of writing the
TXOP register causes the TRDY bit to be cleared
signifying that the TXDATA register is full and a
corresponding opcode has been queued. The
JBLPD must wait for an EOF nominal time period
at which time data is transferred from the TXDATA
register to the transmit shift register. The TRDY bit
is again set since the TXDATA register is empty.
line is denoted as T
tween 0 and 31 µs nominal via the JDLY[4:0] bits
in CONTROL register.
and is programmable be-
p-ext
The transmitter VPW encoder sets the proper level
to be sent out the VPWO line. It then waits for the
corresponding level transition to be reflected back
at the VPW decoder input.
Taking into account the external loop delay (T
)
p-ext
and the digital filter delay, the encoder will time its
output to remain at this level so that the received
symbol is at the correct nominal symbol time (refer
to “Transmit Opcode Queuing” section). If arbitra-
tion is lost at any time during bit 0 or bit 1 transmis-
sion, then the VPWO line goes passive. At the end
of the symbol time on VPWO, the encoder chang-
es the state of VPWO if any more information is to
be transmitted. It then times the new state change
from the receiver decoder output.
The JBLPD should also begin transmission if an-
other device begins transmitting early. As long as
an EOF minimum time period elapses, the JBLPD
should begin timing and asserting the SOF symbol
with the intention of arbitrating for the bus during
the transmission of the first data byte. If a transmit
is requested during an incoming SOF symbol, the
JBLPD should be able to synchronize itself to the
incoming SOF up to a time of Tv1 max. (96 µs) into
the SOF symbol before declaring that it was too
late to arbitrate for this frame.
Note that depending on the symbol (especially the
SOF, NB0, NB1 symbols) the decoder output may
actually change to the desired state before the
transmit is attempted. It is important to still syn-
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
If the J1850 bus was IDLE at the time the first data
byte and opcode are written, the transmitter will
immediately transfer data from the TXDATA regis-
ter to the transmit shift register. The TRDY bit will
once again be set signifying the readiness to ac-
cept a new data byte. The second data byte can
then be written followed by the respective opcode.
In the case of the last data byte, the TXOP register
should be written with the MSG+CRC opcode. The
transmitter will transmit the internally generated
CRC after the last bit of the data byte. Once the
TRDY bit is set signifying the acceptance of the
last data byte, the first byte of the next message
can be queued by writing the TXDATA register fol-
lowed by a TXOP register write. The block will wait
until the current data and the CRC data byte are
sent out and a new IFS has expired before trans-
mitting the new data. This is the case even if IFR
data reception takes place in the interim.
register except during DMA transfers (see Section
10.9.6.4 DMA Management in Transmission
Mode).
Transmitting a Type 1 IFR
The user program will decide to transmit an IFR
type 1 byte in response to a message which is cur-
rently being received (See Figure 132). It does so
by writing the IFR1 opcode to the TXOP register.
Transmitting IFR data type 1 requires only a single
write of the TXOP register with the IFR1 opcode
set. The MLC[3:0] bits should be set to the proper
“byte-received-count-required-before-IFR’ing” val-
ue. If no error conditions (IBD, IFD, TRA, RBRK or
CRCE) exist to prevent transmission, the JBLPD
peripheral will then transmit out the contents of the
PADDR register at the next EOD nominal time pe-
riod or at a time greater than the EOD minimum
time period if a falling edge is detected on filtered
J1850 bus line signifying another transmitter is be-
ginning early. The NB1 symbol precedes the PAD-
DR register value and is followed with an EOF de-
limiter. The TRDY flag is cleared on the write of the
TXOP register. The TRDY bit is set once the NB1
begins transmitting.
Lost arbitration any time during the transfer of type
0 data will be honoured by immediately relinquish-
ing control to the higher priority message. The TLA
bit in the STATUS register is set accordingly and
an interrupt will be generated assuming the
TLA_M bit in the IMR register is set. It is responsi-
bility of the user program to re-send the message
beginning with the first byte if desired. This may be
done at any time by rewriting only the TXOP regis-
ter if the TXDATA contents have not changed.
Although the JBLPD should never lose arbitration
for data in the IFR portion of a type 1 frame, higher
priority messages are always honoured under the
rules of arbitration. If arbitration is lost then the
VPWO line is set to the passive state. The TLA bit
in the STATUS register is set accordingly and an
interrupt will be generated if enabled. The IFR1 is
not retried. It is lost if the JBLPD peripheral loses
arbitration. Also, the data that made it out on the
bus will be received in the RXDATA register if not
put into sleep mode. Note that for the transmitter to
synchronize to the incoming signals of a frame, an
IFR should be queued before an EODM is re-
ceived for the present frame.
Any transmitted data and CRC bytes during the
transmit frame will also be received and trans-
ferred to the RXDATA register if the corresponding
message filter bit is set in the FREG[0:31] regis-
ters. If the corresponding bit is not set in
FREG[0:31], then the transmitted data is also not
transferred to RXDATA. Also, the RDRF will not
get set during frame and receive events such as
RDOF & EODM.
NOTE: The correct procedure for transmitting is to
write first the TXDATA register and then the TXOP
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Transmitting a Type 2 IFR
is currently being received (See Figure 134). It
does so by writing the IFR3 or IFR3+CRC opcode
to the TXOP register. Transmitting IFR data type 3
is similar to transmitting a message, in that the TX-
DATA register is written with the first data byte fol-
lowed by a TXOP register write. For a single data
byte IFR3 transmission, the TXOP register would
be written with IFR3+CRC opcode set. The
MLC[3:0] bits can also be set to a proper value to
check for message length errors before enabling
the IFR transmit.
The user program will decide to transmit an IFR
type 2 byte in response to a message which is cur-
rently being received (See Figure 133). It does so
by writing the IFR2 opcode to the TXOP register.
Transmitting IFR data type 2 requires only a single
write of the TXOP register with the IFR2 opcode
set. The MLC[3:0] bits can also be set to check for
message length errors. If no error conditions (IBD,
IFD, TRA, RBRK or CRCE) exist to prevent trans-
mission, the JBLPD will transmit out the contents
of the PADDR register at the next EOD nominal
time period or after an EOD minimum time period if
a rising edge is detected on the filtered VPWI line
signifying another transmitter beginning early. The
NB1 symbol precedes the PADDR register value
and is followed with an EOF delimiter. The TRDY
flag will be cleared on the write of the TXOP regis-
ter. The TRDY bit is set once the NB1 begins
transmitting.
If no error conditions (IBD, IFD, TRA, RBRK or
CRCE) exist to prevent transmission, the JBLPD
will wait for an EOD nominal time period on the fil-
tered VPWI line (or for at least an EOD minimum
time followed by a rising edge signifying another
transmitter beginning early) at which time data is
transferred from the TXDATA register to the trans-
mit shift register. The TRDY bit is set since the TX-
DATA register is empty. A NB0 symbol is output
on the VPWO line followed by the data byte and
possibly the CRC byte if a IFR3+CRC opcode was
set. Once the first IFR3 byte has been successfully
transmitted, successive IFR3 bytes are sent with
TXDATA/TXOP write sequences where the
MLC[3:O] bits are don’t cares. The final byte in the
IFR3 string must be transmitted with the
IFR3+CRC opcode to trigger the JBLPD to ap-
pend the CRC byte to the string. The user program
may queue up the next message opcode se-
quence once the TRDY bit has been set.
Lost arbitration for this case is a normal occur-
rence since type 2 IFR data is made up of single
bytes from multiple responders. If arbitration is lost
the VPWO line is released and the JBLPD waits
until the byte on the VPWI line is completed. Note
that the IFR that did make it out on the bus will be
received in the RXDATA register if it is not put into
sleep mode. Then, the JBLPD re-attempts to send
its physical address immediately after the end of
the last byte. The TLA bit is not set if arbitration is
lost and the user program does not need to re-
queue data or an opcode. The JBLPD will re-at-
tempt to send its PADDR register contents until it
successfully does so or the 12-byte frame maxi-
mum is reached if NFL=0. If NFL=1, then re-at-
tempts to send an lFR2 are executed until can-
celled by the CANCEL opcode or a JBLPD disa-
ble. Note that for the transmitter to synchronize to
the incoming signals of a frame, an IFR should be
queued before an EODM is received for the
present frame.
Although arbitration should never be lost for data
in the IFR portion of a type 3 frame, higher priority
messages are always honoured under the rules of
arbitration. If arbitration is lost then the block
should relinquish the bus by taking the VPWO line
to the passive state. In this case the TLA bit in the
STATUS register is set, and an interrupt will be
generated if enabled. Note also, that the IFR data
that did make it out on the bus will be received in
the RXDATA register if not in sleep mode. Note
that for the transmitter to synchronize to the in-
coming signals of a frame, an IFR should be
queued before an EODM is received for the cur-
rent frame.
Transmitting a Type 3 lFR Data String
The user program will decide to transmit an IFR
type 3 byte string in response to a message which
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 131. J1850 String Transmission Type 0
Frame
Message
I.D.
Byte
SOF
Data byte(s) (if any)
CRC EOF
Figure 132. J1850 String Transmission Type 1
Frame
IFR
to be sent
Message Rx’d from Another Node
I.D.
Byte
IFR
Byte
SOF
Data byte(s) (if any)
CRC EOD NB1
EOF
Figure 133. J1850 String Transmission Type 2
Frame
IFR
to be sent
Message Rx’d from Another Node
I.D.
IFR
NB1 Byte
... ...
IFR
Byte
Data byte(s) (if any)
Byte
CRC EOD
EOF
SOF
Figure 134. J1850 String Transmission Type 3
Frame
IFR
to be sent
Message Rx’d from Another Node
CRC
Byte
I.D.
SOF
Data byte(s) (if any)
Byte
CRC EOD NB0 IFR Data Byte(s)
EOF
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Transmit Opcode Queuing
JBLPD has a receiver pin which tells the transmit-
ter about bus activity. Due to characteristics of the
J1850 bus and the eight-clock digital filter, the sig-
nals presented to the VPW symbol decoder are
delayed a certain amount of time behind the actual
J1850 bus. Also, due to wave shaping and other
signal conditioning of the transceiver I.C. the ac-
tions of the VPWO pin on the transmitter take time
to appear on the bus itself. The total external
J1850 bus delays are defined in the SAE J1850
standard as nominally 16 µs. The nominal 16 µs
loop delay will actually vary between different
transceiver I.C’s. The JBLPD peripheral thus in-
cludes a programmability of the external loop de-
lay in the bit positions JDLY[4:0]. This assures
only nominal transmit symbols are placed on the
bus by the JBLPD.
The JBLPD has the capability of queuing opcode
transmits written to the TXOP register until J1850
bus conditions are in a correct state for the trans-
mit to occur. For example, a MSGx opcode can be
queued when the JBLPD is presently receiving a
frame (or transmitting a MSG+CRC opcode) or an
IFRx opcode can be queued when currently re-
ceiving or transmitting the message portion of a
frame.
Queuing a MSG or MSG+CRC opcode for the next
frame can occur while another frame is in
progress. A MSGx opcode is written to the TXOP
register when the present frame is past the point
where arbitration for control of the bus for this
frame can occur. The JBLPD will wait for a nomi-
nal IFS symbol (or EOFmin if another node begins
early) to appear on the VPWI line before com-
mencing to transmit this queued opcode. The
TRDY bit for the queued opcode will remain clear
until the EOFmin is detected on the VPWI line
where it will then get set. Queued MSGx transmits
for the next frame do not get cancelled for TLA,
IBD, IFD or CRCE errors that occur in the present
frame. An RBRK error will cancel a queued op-
code for the next frame.
The method of transmitting for the JBLPD includes
interaction between the transmitter and the receiv-
er. The transmitter starts a symbol by placing the
proper level (active or passive) on its VPWO pin.
The transmitter then waits for the corresponding
pin transition (inverted, of course) at the VPW de-
coder input. Note that the level may actually ap-
pear at the input before the transmitter places the
value on the VPWO pin. Timing of the remainder
of the symbol starts when the transition is detect-
ed. Refer to Figure 136, Case 1. The symbol time-
out value is defined as:
Queuing an IFRx opcode for the present frame
can occur at any time after the detection of the be-
ginning of an SOF character from the VPWI line.
The queued IFR will wait for a nominal EOD sym-
bol (or EODmin if another node begins early) be-
fore commencing to transmit the IFR. A queued
IFR transmit will be cancelled on IBD, lFD, CRCE,
RBRK errors as well as on a correct message
length check error or frame length limit violation if
these checks are enabled.
SymbolTimeout = NominalSymbolTime - ExternalLoop-
Delay - 8 µs
NominalSymbolTime = Tv Symbol time
ExternalLoopDelay = defined via JDLY[4:0]
8 µs = Digital Filter
Bit-by-bit arbitration must be used to settle the
conflicts that occur when multiple nodes attempt to
transmit frames simultaneously. Arbitration is ap-
plied to each data bit symbol transmitted starting
after the SOF or NBx symbol and continuing until
the EOD symbol. During simultaneous transmis-
sions of active and passive states on the bus, the
resultant state on the bus is the active state. If the
JBLPD detects a received symbol from the bus
that is different from the symbol being transmitted,
then the JBLPD will discontinue its transmit opera-
tion prior to the start of the next bit. Once arbitra-
tion has been lost, the VPWO pin must go passive
within one period of the prescaled clock of the pe-
ripheral. Figure 135 shows 3 nodes attempting to
arbitrate for the bus with Node B eventually win-
ning with the highest priority data.
Transmit Bus Timing, Arbitration, and Syn-
chronization
The external J1850 bus on the other side of the
transceiver I.C. is a single wire multiplex bus with
multiple nodes transmitting a number of different
types of message frames. Each node can transmit
at any time and synchronization and arbitration is
used to determine who wins control of the trans-
mit. It is the obligation of the JBLPD transmitter
section to synchronize off of symbols on the bus,
and to place only nominal symbol times onto the
bus within the accuracy of the peripheral (+/- 1 µs).
To transmit proper symbols the JBLPD must know
what is going on out on the bus. Fortunately, the
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 135. J1850 Arbitration Example
Transmitting
Node A
Active
Passive
0
0
0
0
0
0
0
0
1 1 0
0 0 1
0 0
SOF
SOF
SOF
SOF
Transmitting
Node B
Active
Passive
1 1 0
0
0
Transmitting
Node C
Active
Passive
1 1 0 1
1 1 0
Active
Passive
Signal
on Bus
0 0
Figure 136. J1850 Received Symbol Timing
178 µs
VPWO
Case 1 VPWI
VPW Decoder
178 µs
VPWO
TX2
Case 2
VPWI
VPW Decoder
178 µs
VPWO
TX2
Case 3
VPWI
VPW Decoder
0
14
200 214
-6
8
22
192 208 222
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Use of symbol and bit synchronization is an inte-
gral part of the J1850 bus scheme. Therefore, tight
coupling of the encoder and decoder functions is
required to maintain synchronization during trans-
mits. Transmitted symbols and bits are initiated by
the encoder and are timed through the decoder to
realize synchronization. Figure 136 exemplifies
synchronization with 3 examples for an SOF sym-
bol and JDLY[4:0] = 01110b.
10.9.3.3 Receiving Messages
Data is received from the external analog trans-
ceiver on the VPWI pin. VPWI data is immediately
passed through a digital filter that ignores all puls-
es that are less than 7µs. Pulses greater than or
equal to 7µs and less than 34µs are flagged as
invalid bits (IBD) in the ERROR register.
Once data passes through the filter, all delimiters
are stripped from the data stream and data bits are
shifted into the receive shift register by the decod-
er logic. The first byte received after a valid SOF
character is compared with the flags contained in
FREG[0:31]. If the compare indicates that this
message should be received, then the receive
shift register contents are moved to the receive
data register (RXDATA) for the user program to
access. The Receive Data Register Full bit
(RDRF) is set to indicate that a complete byte has
been received. For each byte that is to be received
in a frame, once an entire byte has been received,
the receive shift register contents are moved to the
receive data register (RXDATA). All data bits re-
ceived, including CRC bits, are transferred to the
RXDATA register. The Receive Data Register Full
bit (RDRF) is set to indicate that a complete byte
has been received.
Case 1 shows a single transmitter arbitrating for
the bus. The VPWO pin is asserted, and 14µs later
the bus transitions to an active state. The 14µs de-
lay is due to the nominal delay through the exter-
nal transceiver chip. The signal is echoed back to
the transceiver through the VPWI pin, and pro-
ceeds through the digital filter. The digital filter has
a loop delay of 8 clock cycles with the signal finally
presented to the decoder 22 µs after the VPWO
pin was asserted. The decoder waits 178 µs be-
fore issuing a signal to the encoder signifying the
end of the symbol. The VPWO pin is de-asserted
producing the nominal SOF bit timing (22 µs +
178µs = 200 µs).
Case 2 shows a condition where 2 transmitters at-
tempt to arbitrate for the bus at nearly the same
time with a second transmitter, TX2, beginning
slightly earlier than the VPWO pin. Since the
JBLPD always times symbols from its receiver
perspective, 178µs after the decoder sees the ris-
ing edge it issues a signal to the encoder to signify
the end of the SOF. Nominal SOF timings are
maintained and the JBLPD re-synchronizes to
TX2.
If the first byte after a valid SOF indicates non-re-
ception of this frame, then the current byte in the
receive shift register is inhibited from being trans-
ferred to the RXDATA register and the RDRF flag
remains clear (see the “Received Message Filter-
ing” section). Also, no flags associated with receiv-
ing a message (RDOF, CRCE, IFD, IBD) are set.
Case 3 again shows an example of 2 transmitters
attempting to arbitrate for the bus at nearly the
same time with the VPWO pin starting earlier than
TX2. In this case TX2 is required to re-synchronize
to VPWO.
A CRC check is kept on all bytes that are trans-
ferred to the RXDATA register during message
byte reception (succeeding an SOF symbol) and
IFR3 reception (succeeding an NB0 symbol). The
CRC is initialized on receipt of the first byte that
follows an SOF symbol or an NB0 symbol. The
CRC check concludes on receipt of an EODM
symbol. The CRC error bit (CRCE), therefore, gets
set after the EODM symbol has been recognized.
Refer to the “SAE Recommended Practice -
J1850” manual for more information on CRCs.
All 3 examples exemplify how bus timings are driv-
en from the receiver perspective. Once the receiv-
er detects an active bus, the transmitter symbol
timings are timed minus the transceiver and digital
filter delays (i.e. SOF = 200 µs - 14µs - 8µs =
178µs). This synchronization and timing off of the
VPWI pin occurs for every symbol while transmit-
ting. This ensures true arbitration during data byte
transmissions.
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Received Message Filtering
user program. All receiver flags and interrupts
function normally.
The FREG[0:31] registers can be considered an
array of 256 bits (the FREG[0].0 bit is bit 0 of the
array and the FREG[31].7 bit is bit 255). The I.D.
byte of a message frame is used as a pointer to
the array (See Figure 137).
Note that a break symbol received during a filtered
out message will still be received. Note also that
the filter comparison occurs after reception of the
first byte. So, any receive errors that occur before
the message filter comparison (i.e. IBD, IFD) will
be active at least until the filter comparison.
Upon the start of a frame, the first data byte re-
ceived after the SOF symbol determines the I.D. of
the message frame. This I.D. byte addresses the
I.D. byte flags stored in registers FREG[0:31]. This
operation is accomplished before the transfer of
the I.D. byte into the RXDATA register and before
the RDRF bit is set.
Transmitted Message Filtering
When transmitting a message, the corresponding
FREG[0:31] I.D. filter bit may be set or cleared. If
set, then the JBLPD will receive all data informa-
tion transferred during the frame, unless sleep
mode is invoked. Everything the JBLPD transmits
will be reflected in the RXDATA register.
If the corresponding bit in the message filter array,
FREG[0:31], is set to zero (0), then the I.D. byte is
not transferred to the RXDATA register and the
RDRF bit is not set. Also, the remainder of the
message frame is ignored until reception of an
EOFmin symbol. A received EOFmin symbol ter-
minates the operation of the message filter and
enables the receiver for the next message. None
of the flags related to the receiver, other than
IDLE, are set. The EODM flag does not get set
during a filtered frame. No error flags other than
RBRK can get set.
Because the JBLPD has invalid bit detect (IBD),
invalid frame detect (IFD), transmitter lost arbitra-
tion (TRA), and Cyclic Redundancy Check Error
(CRCE) it is not necessary for the transmitter to lis-
ten to the bytes that it is transmitting. The user
may wish to filter out the transmitted messages
from the receiver. This can reduce interrupt bur-
den. When a transmitted I.D. byte is filtered by the
receiver section of the block, then RDRF, RDOF,
EODM flags are inhibited and no RXDATA trans-
fers occur. The other flags associated normally
with receiving - RBRK, CRCE, IFD, and IBD - are
not inhibited, and they can be used to ascertain
the condition of the message transmit.
If the corresponding bit in the message filter array,
FREG[0:31], is set to a one (1), then the I.D. byte
is transferred to the RXDATA register and the
RDRF is set. Also, the remainder of the message
is received unless sleep mode is invoked by the
Figure 137. I.D. Byte and Message Filter Array use
Bit 0 = FREG[0].0
Bit 1 = FREG[0].1
Bit 2 = FREG[0].2
Bit 3 = FREG[0].3
Bit 4 = FREG[0].4
I.D. byte
value = n
Bit n-1
Bit n
Bit n+1
Bit 254 = FREG[31].6
Bit 255 = FREG[31].7
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.3.4 Sleep Mode
ing the TRDY, TLA, TTO, TDUF, TRA, IBD, IFD,
and CRCE bits to be set if required. This mode al-
lows the user to not have to listen while talking.
Sleep mode allows the user program to ignore the
remainder of a message. Normally, the user pro-
gram can recognise if the message is of interest
from the header bytes at the beginning of the mes-
sage. If the user program is not interested in the
message it simply writes the SLP bit in the PRLR
register. This causes all additional data on the bus
to be ignored until an EOF minimum occurs. No
additional flags (but not the EOFM flag) and, there-
fore, interrupts are generated for the remainder of
the message. The single exception to this is a re-
ceived break symbol while in sleep mode. Break
symbols always take precedence and will set the
RBRK bit in the ERROR register and generate an
interrupt if the ERR_M bit in IMR is set. Sleep
mode and the SLP bit gets cleared on reception of
an EOF or Break symbol.
10.9.3.5 Normalization Bit symbol selection
The form of the NB0/NB1 symbol changes de-
pending on the industry standard followed. A bit
(NBSYMS) in the OPTIONS register selects the
symbol timings used. Refer to Table 54.
10.9.3.6 VPWI input line management
The JBLPD is able to work with J1850 transceiver
chips that have both inverted and not inverted RX
signal. A dedicated bit (INPOL) of the OPTIONS
register must be programmed with the correct val-
ue depending on the polarity of the VPWI input
with respect to the J1850 bus line. Refer to the IN-
POL bit description for more details.
Writes to the SLP bit will be ignored if:
1) A valid EOFM symbol was the last valid symbol
detected,
10.9.3.7 Loopback mode
AND
The JBLPD is able to work in loopback mode. This
mode, enabled setting the LOOPB bit of the OP-
TIONS register, internally connects the output sig-
nal (VPWO) of the JBLPD to the input (VPWI)
without polarity inversion. The external VPWO pin
of the MCU is forced in its passive state and the
external VPWI pin is ignored (Refer to Figure 138).
2) The J1850 bus line (after the filter) is passive.
Therefore, sleep mode can only be invoked after
the SOF symbol and subsequent data has been
received, but before a valid EOF is detected. If
sleep mode is invoked within this time window,
then any queued IFR transmit is aborted. If a MSG
type is queued and sleep mode is invoked, then
the MSG type will remain queued and an attempt
to transmit will occur after the EOF period has
elapsed as usual.
Note: When the LOOPB bit is set or reset, edges
could be detected by the J1850 decoder on the in-
ternal VPWI line. These edges could be managed
by the JBLPD as J1850 protocol errors. It is sug-
gested to enable/disable LOOPB when the JBLPD
If SLP mode is invoked while the JBLPD is current-
ly transmitting, then the JBLPD effectively inhibits
the RDRF, RDT, EODM, & RDOF flags from being
set, and disallows RXDATA transfers. But, it other-
wise functions normally as a transmitter, still allow-
is
suspended
(CONTROL.JE=0,
CON-
TROL.JDIS=0) or when the JBLPD is disabled
(CONTROL.JDIS=1).
Table 54. Normalization Bit configurations
Symbol
NB0
NBSYMS=0
active Tv2 (active long)
active Tv1 (active short)
NBSYMS=1
IFR with CRC
active Tv1 (active short)
active Tv2 (active long)
IFR without CRC
NB1
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 138. Local Loopback structure
MCU
JBLPD peripheral
Passive state
MCU VPWO
pin
VPWO from the
peripheral logic
VPWI toward the
J1850 decoder
Polarity
manager
MCU VPWI
pin
OPTIONS.INPOL
OPTIONS.LOOPB
10.9.3.8 Peripheral clock management
(FREQ[5:0]) must be programmed with a value us-
ing the following formula:
To work correctly, the encoder and decoder sec-
tions of the peripheral need an internal clock at
1MHz. This clock is used to evaluate the protocol
symbols timings in transmission and in reception.
MCU Internal Freq. = 1MHz * (FREQ[5:0] + 1).
Note: If the MCU internal clock frequency is lower
than 1MHz, the JBLPD is not able to work correct-
ly. If a frequency lower than 1MHz is used, the
user program must disable the JBLPD.
The prescaled clock is obtained by dividing the
MCU internal clock frequency. The CLKSEL regis-
ter allows the selection of the right prescaling fac-
tor. The six least significant bits of the register
Note: When the MCU internal clock frequency or
the clock prescaler factor are changed, the JBLPD
could lose synchronization with the J1850 bus.
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.4 Peripheral Functional Modes
tion when the JBLPD is not used, even if the de-
coder is able to follow the bus traffic. So, at any
time the JBLPD is enabled, it is immediately syn-
chronized with the J1850 bus.
The JBLPD can be programmed in 3 modes, de-
pending on the value of the JE and JDIS bits in the
CONTROL register, as shown in Table 55.
Note: While the JBLPD is suspended, the STA-
TUS register, the ERROR register and the SLP bit
of the PRLR register are forced into their reset val-
ue.
Table 55. JBLPD functional modes
JE
0
JDIS mode
1
0
0
JBLPD Disabled
0
JBLPD Suspended
JBLPD Enabled
10.9.4.3 JBLPD Disabled (Very Low Power
Mode)
1
Setting the JDIS bit in the CONTROL register, the
JBLPD is stopped until the bit is reset by software.
Also the J1850 decoder is stopped, so the JBLPD
is no longer synchronized with the bus. When the
bit is reset, the JBLPD will wait for a new idle state
on the J1850 bus. This mode can be used to mini-
mize power consumption when the JBLPD is not
used.
Depending on the mode selected, the JBLPD is
able or unable to transmit or receive messages.
Moreover the power consumption of the peripheral
is affected.
Note: The configuration with both JE and JDIS set
is forbidden.
Note: While the JDIS bit is set, the STATUS regis-
ter, the ERROR register, the IMR register and the
SLP, TEOBP and REOBP bits of the PRLR regis-
ter are forced to their reset value.
10.9.4.1 JBLPD Enabled
When the JBLPD is enabled (CONTROL.JE=1), it
is able to transmit and receive messages. Every
feature is available and every register can be writ-
ten.
Note: In order that the JDIS bit is able to reset the
IMR register and the TEOBP and REOBP bits, the
JDIS bit must be left at 1 at least for 6 MCU clock
cycles (3 NOPs).
10.9.4.2 JBLPD Suspended (Low Power Mode)
Note: The JE bit of CONTROL register cannot be
set with the same instruction that reset the JDIS
bit. It can be set only after the JDIS bit is reset.
When the JBLPD is suspended (CONTROL.JE=0
and CONTROL.JDIS=0), all the logic of the
JBLPD is stopped except the decoder logic.
This feature allows a reduction of power consump-
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.5 Interrupt Features
– The RDRF interrupt is generated when a com-
plete data byte has been received and placed in
the RXDATA register (see also the RDRF bit
description of the STATUS register).
The JBLPD has six interrupt sources that it han-
dles using the internal interrupts protocol. Other
two interrupt sources (REOB and TEOB) are relat-
ed to the DMA feature (See Section 10.9.6 DMA
Features).
No external interrupt channel is used by the
JBLPD.
– The REOB (Receive End Of Block) interrupt is
generated when receiving using DMA and the
last byte of a sequence of data is read from the
JBLPD.
The dedicated registers of the JBLPD should be
loaded with appropriate values to set the interrupt
vector (see the description of the IVR register), the
interrupt mask bits (see the description of the IMR
register) and the interrupt pending bits (see the de-
scription of the STATUS and PRLR registers).
– The TRDY interrupt is generated by two condi-
tions: when the TXOP register is ready to ac-
cept a new opcode for transmission; when the
transmit state machine accepts the opcode for
transmission (a more detailed description of this
condition is given in the TRDY bit description of
the STATUS register).
The interrupt sources are as follows:
– The TEOB (Transmit End Of Block) interrupt is
generated when transmitting using DMA and
the last byte of a sequence of data is written to
the JBLPD.
– The ERROR interrupt is generated when the ER-
ROR bit of the STATUS register is set. This bit
is set when the following events occur: Trans-
mitter Timeout, Transmitter Data Underflow,
Receiver Data Overflow, Transmit Request
Aborted, Received Break Symbol, Cyclic Re-
dundancy Check Error, Invalid Frame Detect,
Invalid Bit Detect (a more detailed description of
these events is given in the description of the
ERROR register).
10.9.5.1 Interrupt Management
To use the interrupt features the user has to follow
these steps:
– Set the correct priority level of the JBLPD
– Set the correct interrupt vector
– Reset the Pending bits
– The TLA interrupt is generated when the trans-
mitter loses the arbitration (a more detailed de-
scription of this condition is given in the TLA bit
description of the STATUS register).
– Enable the required interrupt source
Note: It is strongly recommended to reset the
pending bits before un-masking the related inter-
rupt sources to avoid spurious interrupt requests.
– The EODM interrupt is generated when the
JBLPD detects a passive level on the VPWI line
longer than the minimum time accepted by the
standard for the End Of Data symbol (a more
detailed description of this condition is given in
the EODM bit description of the STATUS regis-
ter).
The priority with respect the other ST9 peripherals
is programmable by the user setting the three
most significant bits of the Interrupt Priority Level
register (PRLR). The lowest interrupt priority is ob-
tained by setting all the bits (this priority level is
never acknowledged by the CPU and is equivalent
to disabling the interrupts of the JBLPD); the high-
est interrupt priority is programmed resetting the
bits. See the Interrupt and DMA chapters of the
datasheet for more details.
– The EOFM interrupt is generated when the
JBLPD detects a passive level on the VPWI line
longer than the minimum time accepted by the
standard for the End Of Frame symbol (a more
detailed description of this condition is given in
the EOFM bit description of the STATUS regis-
ter).
When the JBLPD interrupt priority is set, the prior-
ity between the internal interrupt sources is fixed
by hardware as shown in Table 56.
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Note: After an MCU reset, the DMA requests of
the JBLPD have a higher priority than the interrupt
requests.
If the DMASUSP bit of the OPTIONS register is
set, while the ERROR and TLA flags are set, no
DMA transfer will be performed, allowing the re-
lavent interrupt routines to manage each condition
and, if necessary, disable the DMA transfer (Refer
to Section 10.9.6 DMA Features).
Each interrupt source has a pending bit in the
STATUS register, except the DMA interrupt sourc-
es that have the interrupt pending bits located in
the PRLR register.
These bits are set by hardware when the corre-
sponding interrupt event occurs. An interrupt re-
quest is performed only if the related mask bits are
set in the IMR register and the JBLPD has priority.
The pending bits have to be reset by the user soft-
ware. Note that until the pending bits are set (while
the corresponding mask bits are set), the JBLPD
processes interrupt requests. So, if at the end of
an interrupt routine the related pending bit is not
reset, another interrupt request is performed.
To reset the pending bits, different actions have to
be done, depending on each bit: see the descrip-
tion of the STATUS and PRLR registers.
Table 56. JBLPD internal priority levels
Priority Level
Interrupt Source
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
Higher
Lower
The user can program the most significant bits of
the interrupt vectors by writing the V[7:3] bits of the
IVR register. Starting from the value stored by the
user, the JBLPD sets the three least significant
bits of the IVR register to produce four interrupt
vectors that are associated with interrupt sources
as shown in Table 57.
Table 57. JBLPD interrupt vectors
Interrupt Vector
V[7:3] 000b
V[7:3] 010b
V[7:3] 100b
V[7:3] 110b
Interrupt Source
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.6 DMA Features
(odd address). They are pointed to by the DMA
Transaction Counter Pointer Register (RDCPR
register in receiving, TDCPR register in transmit-
ting) located in the JBLPD register page.
The JBLPD can use the ST9 on-chip Direct Mem-
ory Access (DMA) channels to provide high-speed
data transactions between the JBLPD and contig-
uous locations of Register File and Memory. The
transactions can occur from and toward the
JBLPD. The maximum number of transactions that
each DMA channel can perform is 222 with Regis-
ter File or 65536 with Memory. Control of the DMA
features is performed using registers located in the
JBLPD register page (IVR, PRLR, IMR, RDAPR,
RDCPR, TDAPR, TDCPR).
To select DMA transactions with the Register File,
the control bits RDCPR.RF/MEM in receiving
mode or TDCPR.RF/MEM in transmitting mode
must be set.
The transaction Counter Register must be initial-
ized with the number of DMA transfers to perform
and it will be decremented after each transaction.
The DMA Address Register must be initialized with
the starting address of the DMA table in the Regis-
ter File, and it is incremented after each transac-
tion. These two registers must be located between
addresses 00h and DFh of the Register File.
The priority level of the DMA features of the
JBLPD with respect to the other ST9 peripherals
and the CPU is the same as programmed in the
PRLR register for the interrupt sources. In the in-
ternal priority level order of the JBLPD, depending
on the value of the DMASUSP bit in the OPTIONS
register, the DMA may or may not have a higher
priority than the interrupt sources.
When the DMA occurs between JBLPD and Reg-
ister File, the TDAPR register (in transmission)
and the RDAPR register (in reception) are not
used.
Refer to the Interrupt and DMA chapters of the da-
tasheet for details on priority levels.
10.9.6.2 DMA between JBLPD and Memory
Space
The DMA features are enabled by setting the ap-
propriate enabling bits (RXD_M, TXD_M) in the
IMR register. It is also possible to select the direc-
tion of the DMA transactions.
If the DMA transaction is made between the
JBLPD and Memory, a register pair is required to
hold the DMA Address and another register pair to
hold the DMA Transaction counter. These two
pairs of registers must be located in the Register
File. The DMA Address pair is pointed to by the
DMA Address Pointer Registers (RDAPR register
in reception, TDAPR register in transmission) lo-
cated in the JBLPD register page; the DMA Trans-
action Counter pair is pointed to by the DMA
Transaction Counter Pointer Registers (RDCPR
register in reception, TDCPR register in transmis-
sion) located in the JBLPD register page.
Once the DMA table is completed (the transaction
counter reaches 0 value), an interrupt request to
the CPU is generated if the related mask bit is set
(RDRF_M bit in reception, TRDY_M bit in trans-
mission). This kind of interrupt is called “End Of
Block”. The peripheral sends two different “End Of
Block” interrupts depending on the direction of the
DMA (Receiving End Of Block (REOB) - Transmit-
ting End Of Block (TEOB)). These interrupt sourc-
es have dedicated interrupt pending bits in the
PRLR register (REOBP, TEOBP) and they are
mapped to the same interrupt vectors: “Receive
Data Register Full (RDRF)” and “Transmit Ready
(TRDY)” respectively. The same correspondence
exists for the internal priority between interrupts
and interrupt vectors.
To select DMA transactions with Memory Space,
the control bits RDCPR.RF/MEM in receiving
mode or TDCPR.RF/MEM in transmitting mode
must be reset.
The Transaction Counter register pair must be ini-
tialized with the number of DMA transfers to per-
form and it will be decremented after each transac-
tion. The DMA Address register pair must be ini-
tialized with the starting address of the DMA table
in Memory Space, and it is incremented after each
transaction. These two register pairs must be lo-
cated between addresses 00h and DFh of the
Register File.
10.9.6.1 DMA between JBLPD and Register File
If the DMA transaction is made between the
JBLPD and the Register File, one register is re-
quired to hold the DMA Address and one to hold
the DMA transaction counter. These two registers
must be located in the Register File: the DMA Ad-
dress Register in an even addressed register, the
DMA Transaction Counter in the following register
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.6.3 DMA Management in Reception Mode
through the DMA Address Register (or Register
pair);
The DMA in reception is performed when the
RDRF bit of the STATUS register is set (by hard-
ware). The RDRF bit is reset as soon as the DMA
cycle is finished.
To enable the DMA feature, the RXD_M bit of the
IMR register must be set (by software).
– A post-increment of the DMA Address Register
(or Register pair);
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
Each DMA request performs the transfer of a sin-
gle byte from the RXDATA register of the peripher-
al toward Register File or Memory Space (Figure
139).
Note: When the REOBP pending bit is set (at the
end of the last DMA transfer), the reception DMA
enable bit (RXD_M) is automatically reset by hard-
ware. However, the DMA can be disabled by soft-
ware resetting the RXD_M bit.
Each DMA transfer consists of three operations
that are performed with minimum use of CPU time:
Note: The DMA request acknowledge could de-
pend on the priority level stored in the PRLR regis-
ter.
– A load from the JBLPD data register (RXDATA)
to a location of Register File/Memory addressed
Figure 139. DMA in Reception Mode
Register File
or
Memory space
Previous data
Data received
RXDATA
Current
Address
Pointer
JBLPD peripheral
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.6.4 DMA Management in Transmission
Mode
Register pair); it is the next location in the TX-
DATA transfer cycle;
DMA in transmission is performed when the TRDY
bit of the STATUS register is set (by hardware).
The TRDY bit is reset as soon as the DMA cycle is
finished.
To enable the DMA feature, the TXD_M bit in the
IMR register must be set (by software).
– A post-increment of the DMA Address Register
(or Register pair);
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
Note: When the TEOBP pending bit is set (at the
end of the last DMA transfer), the transmission
DMA enable bit (TXD_M) is automatically reset by
hardware. However, the DMA can be disabled by
software resetting the TXD_M bit.
Compared to reception, in transmission each DMA
request performs the transfer of either a single
byte or a couple of bytes depending on the value
of the Transmit Opcode bits (TXOP.OP[2:0]) writ-
ten during the DMA transfer.
The table of values managed by the DMA must be
a sequence of opcode bytes (that will be written in
the TXOP register by the DMA) each one followed
by a data byte (that will be written in the TXDATA
register by the DMA) if the opcode needs it (see
Figure 140).
Note: When using DMA, the TXOP byte is written
before the TXDATA register. This order is accept-
ed by the JBLPD only when the DMA in transmis-
sion is enabled.
Note: The DMA request acknowledge could de-
pend on the priority level stored in the PRLR regis-
ter. In the same way, some time can occur be-
tween the transfer of the first byte and the transfer
of the second one if another interrupt or DMA re-
quest with higher priority occurs.
Each DMA cycle consists of the following transfers
for a total of three/six operations that are per-
formed with minimum use of CPU time:
– A load to the JBLPD Transmit Opcode register
(TXOP) from a location of Register File/Memory
addressed through the DMA Address Register
(or Register pair);
10.9.6.5 DMA Suspend mode
In the JBLPD it is possible to suspend or not to
suspend the DMA transfer while some J1850 pro-
tocol events occur. The selection between the two
modes is done by programming the DMASUSP bit
of the OPTIONS register.
If the DMASUSP bit is set (DMA suspended
mode), while the ERROR or TLA flag is set, the
DMA transfers are suspended, to allow the user
program to handle the event condition.
– A post-increment of the DMA Address Register
(or Register pair);
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed;
and if the Transmit Opcode placed in TXOP re-
quires a datum:
– A load to the peripheral data register (TXDATA)
from a location of Register File/Memory ad-
dressed through the DMA Address Register (or
If the DMASUSP bit is reset (DMA not suspended
mode), the previous flags have no effect on the
DMA transfers.
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 140. DMA in Transmission Mode
Register File
or
Memory space
Previous Opcode sent
(data not required)
Previous Opcode sent
(data required)
Previous Data sent
Opcode sent
(data required)
1st byte
2nd byte
Data sent
TXOP
Opcode
(data not required)
TXDATA
Opcode
(data required)
Data
JBLPD peripheral
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.7 Register Description
The JBLPD peripheral uses 48 registers that are
mapped in a single page of the ST9 register file.
register (OPTIONS) are used to select the current
sub-page. See Section 10.9.7.2 Stacked Regis-
ters section for a detailed description of these reg-
isters.
Twelve registers are mapped from R240 (F0h) to
R251 (FBh): these registers are usually used to
control the JBLPD. See Section 10.9.7.1 Un-
Stacked Registers for a detailed description of
these registers.
The ST9 Register File page used is 23 (17h).
NOTE: Bits marked as “Reserved” should be left at
their reset value to guarantee software compatibil-
ity with future versions of the JBLPD.
Thirty-six registers are mapped from R252 (FCh)
to R255 (FFh). This is obtained by creating 9 sub-
pages, each containing 4 registers, mapped in the
same register addresses; 4 bits (RSEL[3:0]) of a
Figure 141. JBLPD Register Map
R240 (F0h) STATUS
R241 (F1h) TXDATA
R242 (F2h) RXDATA
TXOP
R243 (F3h)
R244 (F4h) CLKSEL
R245 (F5h) CONTROL
R246 (F6h) PADDR
R247 (F7h) ERROR
R248 (F8h) IVR
FREG28
FREG24FREG29
R249 (F9h) PRLR
R250 (FAh) IMR
R251 (FBh) OPTIONS
FREG20FREG25FREG30
FREG16FREG21FREG26FREG31
FREG12FREG17FREG22FREG27
FREG8 FREG13FREG18FREG23
FREG4 FREG9 FREG14FREG19
FREG0 FREG5 FREG10FREG15
FREG1 FREG6 FREG11
R252 (FCh) CREG0
R253 (FDh) CREG1
R254 (FEh) CREG2
R255 (FFh) CREG3
RDAPR
RDCPR
TDAPR
TDCPR
FREG2 FREG7
FREG3
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.7.1 Un-Stacked Registers
next frame will not be cancelled for these errors,
so TRDY would not get set.
STATUS REGISTER (STATUS)
R240 - Read/Write
Register Page: 23
Reset Value: 0100 0000 (40h)
– An RBRK error condition cancels all transmits for
this frame or any successive frames, so the
TRDY bit will always be immediately set on an
RBRK condition.
7
0
TRDY is set on reset or while CONTROL.JE is re-
set, or while the CONTROL.JDIS bit is set.
If the TRDY_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: TXOP register not ready to receive a new op-
code
ERR TRDY RDRF TLA
RDT EODM EOFM IDLE
The bits of this register indicate the status of the
JBLPD peripheral.
This register is forced to its reset value after the
MCU reset and while the CONTROL.JDIS bit is
set. While the CONTROL.JE bit is reset, all bits ex-
cept IDLE are forced to their reset values.
1: TXOP register ready to receive a new opcode
Bit 5 = RDRF Receive Data Register Full Flag.
RDRF is set when a complete data byte has been
received and transferred from the serial shift regis-
ter to the RXDATA register.
RDRF is cleared when the RXDATA register is
read (by software or by DMA). RDRF is also
cleared on reset or while CONTROL.JE is reset, or
while CONTROL.JDIS bit is set.
If the RDRF_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: RXDATA register doesn’t contain a new data
1: RXDATA register contains a new data
Bit 7 = ERR Error Flag.
The ERR bit indicates that one or more bits in the
ERROR register have been set. As long as any bit
in the ERROR register remains set, the ERR bit re-
mains set. When all the bits in the ERROR register
are cleared, then the ERR bit is reset by hardware.
The ERR bit is also cleared on reset or while the
CONTROL.JE bit is reset, or while the CON-
TROL.JDIS bit is set.
If the ERR_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: No error
Bit 4 = TLA Transmitter Lost Arbitration.
1: One or more errors have occurred
The TLA bit gets set when the transmitter loses ar-
bitration while transmitting messages or type 1
and 3 IFRs. Lost arbitration for a type 2 IFR does
not set the TLA bit. (Type 2 messages require re-
tries of the physical address if the arbitration is lost
until the frame length is reached (if NFL=0)). The
TLA bit gets set when, while transmitting a MSG,
MSG+CRC, IFR1, IFR3, or IFR3+CRC, the decod-
ed VPWI data bit symbol received does not match
the VPWO data bit symbol that the JBLPD is at-
tempting to send out. If arbitration is lost, the
VPWO line is switched to its passive state and
nothing further is transmitted until an end-of-data
(EOD) symbol is detected on the VPWI line. Also,
any queued transmit opcode scheduled for trans-
mission during this frame is cancelled (but the
TRA bit is not set).
Bit 6 = TRDY Transmit Ready Flag.
The TRDY bit indicates that the TXOP register is
ready to accept another opcode for transmission.
The TRDY bit is set when the TXOP register is
empty and it is cleared whenever the TXOP regis-
ter is written (by software or by DMA). TRDY will
be set again when the transmit state machine ac-
cepts the opcode for transmission.
When attempting to transmit a data byte without
using DMA, two writes are required: first a write to
TXDATA, then a write to the TXOP.
– If a byte is written into the TXOP which results in
TRA getting set, then the TRDY bit will immedi-
ately be set.
The TLA bit can be cleared by software writing a
logic “zero” in the TLA position. TLA is also cleared
on reset or while CONTROL.JE is reset, or while
CONTROL.JDIS bit is set.
If the TLA_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
– If a TLA occurs and the opcode for which TRDY
is low is scheduled for this frame, then TRDY
will go high, if the opcode is scheduled for the
next frame, then TRDY will stay low.
– If an IBD, IFD or CRCE error condition occurs,
then TRDY will be set and any queued transmit
opcode scheduled to transmit in the present
frame will be cancelled by the JBLPD peripher-
al. A MSGx opcode scheduled to be sent in the
0: The JBLPD doesn’t lose arbitration
1: The JBLPD loses arbitration
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 3 = RDT Receive Data Type.
The RDT bit indicates the type of data which is in
the RXDATA register: message byte or IFR byte.
Any byte received after an SOF but before an
EODM is considered a message byte type. Any
byte received after an SOF, EODM and NBx is an
IFR type.
RDT gets set or cleared at the same time that
RDRF gets set.
RDT is cleared on reset or while CONTROL.JE is
reset, or while CONTROL.JDIS bit is set.
0: Last RXDATA byte was a message type byte
1: Last RXDATA byte was a IRF type byte
Bit 0 = IDLE Idle Bus Flag
IDLE is set when the JBLPD decoded VPWI pin
recognized an IFS symbol. That is, an idle bus is
when the bus has been in a passive state for long-
er that the Tv6 symbol time. The IDLE flag will re-
main set as long as the decoded VPWI pin is pas-
sive. IDLE is cleared when the decoded VPWI pin
transitions to an active state.
Note that if the VPWI pin remains in a passive
state after JE is set, then the IDLE bit may go high
sometime before a Tv6 symbol is timed on VPWI
(since VPWI timers may be active when JE is
clear).
IDLE is cleared on reset or while the CON-
TROL.JDIS bit is set.
Bit 2 = EODM End of Data Minimum Flag.
The EODM flag is set when the JBLPD decoded
VPWI pin has been in a passive state for longer
that the minimum Tv3 symbol time unless the
EODM is inhibited by a sleep, filter or CRCE, IBD,
IFD or RBRK error condition during a frame.
EODM bit does not get set when in the sleep mode
or when a message is filtered.
The EODM bit can be cleared by software writing a
logic “zero” in the EODM position. EODM is
cleared on reset, while CONTROL.JE is reset or
while CONTROL.JDIS bit is set.
0: J1850 bus not in idle state
1: J1850 bus in idle state
JBLPD TRANSMIT DATA REGISTER (TXDATA)
R241- Read/Write
Register Page: 23
Reset Value: xxxx xxxx (xxh)
7
0
TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0
If the EODM_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: No EOD symbol detected
The TXDATA register is an eight bits read/write
register in which the data to be transmitted must
be placed. A write to TXDATA merely enters a
byte into the register. To initiate an attempt to
transmit the data, the TXOP register must also be
written. When the TXOP write occurs, the TRDY
flag is cleared. While the TRDY bit is clear, the
data is still in the TXDATA register, so writes to the
TXDATA register with TRDY clear will overwrite
existing TXDATA. When the TXDATA is trans-
ferred to the shift register, the TRDY bit is set
again.
1: EOD symbol detected
Note: The EODM bit is not an error flag. It means
that the minimum time related to the passive Tv3
symbol is passed.
Bit 1 = EOFM End of Frame Minimum Flag.
The EOFM flag is set when the JBLPD decoded
VPWI pin has been in a passive state for longer
that the minimum Tv4 symbol time. EOFM will still
get set at the end of filtered frames or frames
where sleep mode was invoked. Consequently,
multiple EOFM flags may be encountered be-
tween frames of interest.
The EOFM bit can be cleared by software writing a
logic “zero” in the EOFM position. EOFM is
cleared on reset, while CONTROL.JE is reset or
while CONTROL.JDIS bit is set.
Reads of the TXDATA register will always return
the last byte written.
TXDATA contents are undefined after a reset.
Note: The correct sequence to transmit is to write
first the TXDATA register (if datum is needed) and
then the TXOP one.
Only using the DMA, the correct sequence of writ-
ing operations is first the TXOP register and then
the TXDATA one (if needed).
If the EOFM_M bit of the IMR register is set, when
this bit is set an interrupt request occurs.
0: No EOF symbol detected
1: EOF symbol detected
Note: The EOFM bit is not an error flag. It means
that the minimum time related to the passive Tv4
symbol is passed.
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD RECEIVE DATA REGISTER (RXDATA)
R242- Read only
a byte. A write to the TXOP triggers the state ma-
chine to initialize an attempt to serially transmit a
byte out on the VPWO pin. An opcode which trig-
gers a message byte or IFR type 3 to be sent will
transfer the TXDATA register contents to the
transmit serial shift register. An opcode which trig-
gers a message byte or IFR type 3 to be sent with
a CRC appended will transfer the TXDATA regis-
ter contents to the transmit serial shift register and
subsequently the computed CRC byte. An opcode
which triggers an IFR type 1 or 2 to be sent will
transfer the PADDR register contents to the trans-
mit serial shift register. If a TXOP opcode is written
which is invalid for the bus conditions at the time
(e.g. 12 byte frame or IFR3ing an IFR2), then no
transmit attempt is tried and the TRA bit in the ER-
ROR register is set.
Transmission of a string of data bytes requires
multiple TXDATA/TXOP write sequences. Each
write combination should be accomplished while
the TRDY flag is set. However, writes to the TXOP
when TRDY is not set will be accepted by the state
machine, but it may override the previous data and
opcode.
Under normal message transmission conditions
the MSG opcode is written. If the last data byte of
a string is to be sent, then the MSG+CRC opcode
will be written. An IFRx opcode is written if a re-
sponse byte or bytes to a received message (i.e.
bytes received in RXDATA with RDT=0) is wanted
to transmit. The Message Length Count bits
(MLC[3:0]) may be used to require that the IFR be
enabled only if the correct number of message
bytes has been received.
Register Page: 23
Reset Value: xxxx xxxx (xxh)
7
0
RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0
The RXDATA register is an 8-bit read only register
in which the data received from VPWI is stored.
VPWI data is transferred from the input VPW de-
coder to a serial shift register unless it is inhibited
by sleep mode, filter mode or an error condition
(IBD, IFD, CRCE, RBRK) during a frame. When
the shift register is full, this data is transferred to
the RXDATA register, and the RDRF flag gets set.
All received data bytes are transferred to RXDATA
including CRC bytes. A read of the RXDATA reg-
ister will clear the RDRF flag.
Note that care must be taken when reading RXDA-
TA subsequent to an RDRF flag. Multiple reads of
RXDATA after an RDRF should only be attempted
if the user can be sure that another RDRF will not
occur by the time the read takes place.
RXDATA content is undefined after a reset.
JBLPD TRANSMIT OPCODE REGISTER
(TXOP)
R243 - Read/Write
Register Page: 23
Reset Value: 0000 0000 (00h)
7
0
NOTE: The correct sequence to transmit is to write
first the TXDATA register and then the TXOP one.
Only using the DMA, the correct sequence of writ-
ing operations is first the TXOP register and then
the TXDATA one (if needed).
MLC3 MLC2 MLC1 MLC0
-
OP2
OP1
OP0
TXOP is an 8-bit read/write register which contains
the instructions required by the JBLPD to transmit
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 7:4 = MLC[3:0] Message Length Count.
Message Length Count bits 3 to 0 are written when
the program writes one of the IFR opcodes. Upon
detection of the EOD symbol which delineates the
body of a frame from the IFR portion of the frame,
the received byte counter is compared against the
count contained in MLC[3:0]. If they match, then
the IFR will be transmitted. If they do not match,
then the TRA bit in the ERROR register is set and
no transmit attempt occurs.
MSG, Message Byte Opcode.
The Message byte opcode is set when the user
program wants to initiate or continue transmitting
the body of a message out the VPWO pin.
The body of a message is the string of data bytes
following an SOF symbol, but before the first EOD
symbol in a frame. If the J1850 bus is in an idle
condition when the opcode is written, an SOF
symbol is transmitted out the VPWO pin immedi-
ately before it transmits the data contained in TX-
DATA. If the JBLPD is not in idle and the J1850
transmitter has not been locked out by loss of arbi-
tration, then the TXDATA byte is transferred to the
serial output shift register for transmission immedi-
ately on completion of any previously transmitted
data. The final byte of a message string is not
transmitted using the MSG opcode (use the
MSG+CRC opcode).
– While NFL=0, an MCL[3:0] decimal value be-
tween 1 and 11 is considered valid. MCL[3:0]
values of 12, 13, 14, 15 are considered invalid
and will set the Transmit Request Aborted
(TRA) bit in the ERROR register.
– While NFL=1, an MCL[3:0] value between 1 and
15 is considered valid.
– For NFL=1 or 0, MCL[3:0] bits are don’t care dur-
ing a MSG or MSG+CRC opcode write.
Special Conditions for MSG Transmit:
– 1) A MSG cannot be queued on top of an execut-
ing IFR3 opcode. If so, then TRA is set, and
TDUF will get set because the transmit state
machine will be expecting more data, then the
inverted CRC is appended to this frame. Also,
no message byte will be sent on the next frame.
– If writing an IFR opcode and MCL[3:0]=0000,
then the message length count check is ignored
(i.e. MLC=Count is disabled), and the IFR is en-
abled only on a correct CRC and a valid EOD
symbol assuming no other error conditions
(IFD, IBD, RBRK) appear.
– 2) If NFL = 0 and an MSG queued without CRC
on Received Byte Count for this frame=10 will
trigger the TRA to get set, and TDUF will get set
because the state machine will be expecting
more data and the transmit machine will send
the inverted CRC after the byte which is pres-
ently transmitting. Also, no message byte will be
sent on the next frame.
Bit 3 = Reserved.
Bit 2:0 = OP[2:0] Transmit Opcode Select Bits.
The bits OP[2:0] form the code that the transmitter
uses to perform a transmit sequence. The codes
are listed in Table 58.
Caution should be taken when TRA gets set in
these cases because the TDUF error sequence
may engage before the user program has a
chance to rewrite the TXOP register with the cor-
rect opcode. If a TDUF error occurs, a subsequent
MSG write to the TXOP register will be used as the
first byte of the next frame.
Table 58. Opcode definitions
OP[2:0]
Transmit opcode
Abbreviation
No operation or
Cancel
000
CANCEL
001
010
Send Break Symbol
Message Byte
SBRK
MSG
Message Byte then ap-
pend CRC
011
100
101
110
111
MSG+CRC
IFR1
In-Frame Response Type
1
In-Frame Response Type
2
IFR2
In-Frame Response Type
3
IFR3
IFR Type 3 then append
CRC
IFR3+CRC
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
MSG+CRC, Message byte then append CRC op-
code.
The ‘Message byte with CRC’ opcode is set when
the user program wants to transmit a single byte
message followed by a CRC byte, or transmit the
final byte of a message string followed by a CRC
byte.
chance to rewrite the TXOP register with the cor-
rect opcode. If a TDUF error occurs, a subsequent
MSG+CRC write to the TXOP register will be used
as the first byte of the next frame.
IFR1, In-Frame Response Type 1 opcode.
The In-frame Response Type 1 (IFR 1) opcode is
written if the user program wants to transmit a
physical address byte (contained in the PADDR
register) in response to a message that is currently
being received.
The user program decides to set up an IFR1 upon
receiving a certain portion of the data byte string of
an incoming message. No write of the TXDATA
register is required. The IFR1 gets its data byte
from the PADDR register.
A single byte message is basically an SOF symbol
followed by a single data byte retrieved from TX-
DATA register followed by the computed CRC
byte followed by an EOD symbol. If the J1850 bus
is in idle condition when the opcode is written, an
SOF symbol is immediately transmitted out the
VPWO pin. It then transmits the byte contained in
the TXDATA register, then the computed CRC
byte is transmitted. VPWO is then set to a passive
state. If the J1850 bus is not idle and the J1850
transmitter has not been locked out by loss of arbi-
tration, then the TXDATA byte is transferred to the
serial output shift register for transmission immedi-
ately on completion of any previously transmitted
data. After completion of the TXDATA byte the
computed CRC byte is transferred out the VPWO
pin and then the VPWO pin is set passive to time
an EOD symbol.
The JBLPD block will enable the transmission of
the IFR1 on these conditions:
– 1) The CRC check is valid (otherwise the CRCE
is set)
– 2) The received message length is valid if ena-
bled (otherwise the TRA is set)
– 3) A valid EOD minimum symbol is received (oth-
erwise the IFD may eventually get set due to
byte synchronization errors)
Special Conditions for MSG+CRC Transmit:
– 4) If NFL = 0 & Received Byte Count for this
frame <=11 (otherwise TRA is set)
– 1) A MSG+CRC opcode cannot be queued on
top of an executing IFR3 opcode. If so, then
TRA is set, and TDUF will get set because the
transmit state machine will be expecting more
data, then the inverted CRC is appended to this
frame. Also, no message byte will be sent on
the next frame.
– 5) If not presently executing an MSG, IFR3, op-
code (otherwise TRA is set, and TDUF will get
set because the transmit state machine will be
expecting more data, so the inverted CRC will
be appended to this frame)
– 6) If not presently executing an IFR1, IFR2, or
IFR3+CRC opcode otherwise TRA is set (but no
TDUF)
– 2) If NFL=0, a MSG+CRC can only be queued if
Received Byte Count for this frame <=10 other-
wise the TRA will get set, and TDUF will get set
because the state machine will be expecting
more data, so the transmit machine will send
the inverted CRC after the byte which is pres-
ently transmitting. Also, no message byte will be
sent on the next frame.
– 7) If not presently receiving an IFR portion of a
frame, otherwise TRA is set.
The IFR1 byte is then attempted according to the
procedure described in section “Transmitting a
type 1 IFR”. Note that if an IFR1 opcode is written,
a queued MSG or MSG+CRC is overridden by the
IFR1.
Caution should be taken when TRA gets set in
these cases because the TDUF error sequence
may engage before the user program has a
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
IFR2, In-Frame Response Type 2 opcode.
The In-frame Response Type 2 (IFR2) opcode is
set if the user program wants to transmit a physical
address byte (contained in the PADDR register) in
response to a message that is currently being re-
ceived.
The user program decides to set up an IFR2 upon
receiving a certain portion of the data byte string of
an incoming message. No write of the TXDATA
register is required. The IFR gets its data byte from
the PADDR register.
ceived.
The IFR3 uses the contents of the TXDATA regis-
ter for data. The user program decides to set up an
IFR3 upon receiving a certain portion of the data
byte string of an incoming message. A previous
write of the TXDATA register should have oc-
curred.
The JBLPD block will enable the transmission of
the first byte of an IFR3 string on these conditions:
– 1) The CRC check is valid (otherwise the CRCE
is set)
The JBLPD block will enable the transmission of
the IFR2 on these conditions:
– 2) The received message length is valid if ena-
bled (otherwise the TRA is set)
– 1) The CRC check is valid (otherwise the CRCE
is set)
– 3) A valid EOD minimum symbol is received (oth-
erwise the IFD may eventually get set due to
byte synchronization errors)
– 2) The received message length is valid if ena-
bled (otherwise the TRA is set)
– 4) If NFL = 0 & Received Byte Count for this
frame <=9 (otherwise TRA is set and inverted
CRC is transmitted due to TDUF)
– 3) A valid EOD minimum symbol is received (oth-
erwise the IFD may eventually get set due to
byte synchronization errors)
– 5) If not presently executing an MSG opcode
(otherwise TRA is set, and TDUF will get set be-
cause the transmit state machine will be expect-
ing more data and the inverted CRC will be
appended to this frame)
– 4) If NFL = 0 & Received Byte Count for this
frame <=11 (otherwise TRA is set)
– 5) If not presently executing an MSG, IFR3, op-
code (otherwise TRA is set, and TDUF will get
set because the transmit state machine will be
expecting more data, so the inverted CRC will
be appended to this frame)
– 6) If not presently executing an IFR1, IFR2, or
IFR3+CRC opcode, otherwise TRA is set (but
no TDUF)
– 6) If not presently executing an IFR1, IFR2, or
IFR3+CRC opcodes, otherwise TRA is set (but
no TDUF)
– 7) If not presently receiving an IFR portion of a
frame, otherwise TRA is set.
The IFR3 byte string is then attempted according
to the procedure described in section “Transmit-
ting a type 3 IFR”. Note that if an IFR3 opcode is
written, a queued MSG or MSG+CRC is overrid-
den by the IFR3.
– 7) If not presently receiving an IFR portion of a
frame, otherwise TRA is set.
The IFR byte is then attempted according to the
procedure described in section “Transmitting a
type 2 IFR”. Note that if an IFR opcode is written, a
queued MSG or MSG+CRC is overridden by the
IFR2.
The next byte(s) in the IFR3 data string shall also
be written with the IFR3 opcode except for the last
byte in the string which shall be written with the
IFR3+CRC opcode. Each IFR3 data byte trans-
mission is accomplished with a TXDATA/TXOP
write sequence. The succeeding IFR3 transmit re-
quests will be enabled on conditions 4 and 5 listed
above.
IFR3, In-Frame Response Type 3 opcode.
The In-Frame Response Type 3 (IFR3) opcode is
set if the user program wants to initiate to transmit
or continue to transmit a string of data bytes in re-
sponse to a message that is currently being re-
309/426
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
IFR3+CRC, In-Frame Response Type 3 then ap-
pend CRC opcode.
The IFR3 byte is attempted according to the pro-
cedure described in section “Transmitting a type 3
IFR”. The CRC byte is transmitted out on comple-
tion of the transmit of the IFR3 byte.
If this opcode sets up the last byte in an IFR3 data
string, then the TXDATA register contents shall be
transmitted out immediately upon completion of
the previous IFR3 data byte followed by the trans-
mit of the CRC byte. In this case the IFR3+CRC is
enabled on conditions 4 and 5 listed above. Note
that if an IFR3+CRC opcode is written, a queued
MSG or MSG+CRC is overridden by the
IFR3+CRC.
The In-frame Response Type 3 then append CRC
opcode (IFR3+CRC) is set if the user program
wants to either initiate to transmit a single data
byte IFR3 followed by a CRC, or transmit the last
data byte of an IFR3 string followed by the CRC
byte in response to a message that is currently be-
ing received.
The IFR3+CRC opcode transmits the contents of
the TXDATA register followed by the computed
CRC byte. The user program decides to set up an
IFR3 upon receiving a certain portion of the data
byte string of an incoming message. A previous
write of the TXDATA register should have oc-
curred.
SBRK, Send Break Symbol.
The SBRK opcode is written to transmit a nominal
break (BRK) symbol out the VPWO pin. A Break
symbol can be initiated at any time. Once the
SBRK opcode is written a BRK symbol of the nom-
inal Tv5 duration will be transmitted out the VPWO
pin immediately. To terminate the transmission of
an in-progress break symbol the JE bit should be
set to a logic zero. An SBRK command is non-
maskable, it will override any present transmit op-
eration, and it does not wait for the present trans-
mit to complete. Note that in the 4X mode a SBRK
will send a break character for the nominal Tv5
time times four (4 x Tv5) so that all nodes on the
bus will recognize the break. A CANCEL opcode
does not override a SBRK command.
The J1850 block will enable the transmission of
the first byte of an IFR3 string on these conditions:
– 1) The CRC check is valid (otherwise the CRCE
is set)
– 2) The received message length is valid if ena-
bled (otherwise the TRA is set)
– 3) A valid EOD minimum symbol is received (oth-
erwise the IFD may eventually get set due to
byte synchronization errors)
– 4) If NFL = 0 & Received Byte Count for this
frame <=10 (otherwise TRA is set and inverted
CRC is transmitted)
CANCEL, No Operation or Cancel Pending Trans-
mit.
– 5) If not presently executing an MSG opcode
(otherwise TRA is set, and TDUF will get set be-
cause the transmit state machine will be expect-
ing more data and the inverted CRC will be
appended to this frame)
The Cancel opcode is used by the user program to
tell the J1850 transmitter that a previously queued
opcode should not be transmitted. The Cancel op-
code will set the TRDY bit. If the JBLPD peripheral
is presently not transmitting, the Cancel command
effectively cancels a pending MSGx or IFRx op-
code if one was queued, or it does nothing if no
opcode was queued. If the JBLPD peripheral is
presently transmitting, then a queued MSGx or
IFRx opcode is aborted and the TDUF circuit may
take affect.
– 6) If not presently executing an IFR1, IFR2 or
IFR3+CRC opcodes, otherwise TRA is set (but
no TDUF)
– 7) If not presently receiving an IFR portion of a
frame, otherwise TRA is set.
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD SYSTEM FREQUENCY SELECTION
REGISTER (CLKSEL)
rect value must be written in the register. So an in-
ternal frequency less than 1MHz is not allowed.
R244- Read/Write
Note: If the MCU internal clock frequency is lower
than 1MHz, the peripheral is not able to work cor-
rectly. If a frequency lower than 1MHz is used, the
user program must disable the peripheral.
Register Page: 23
Reset Value: 0000 0000 (00h)
7
0
Note: When the clock prescaler factor or the MCU
internal frequency is changed, the peripheral could
lose the synchronization with the J1850 bus.
4X
-
FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0
Bit 7 = 4X Diagnostic Four Times Mode.
This bit is set when the J1850 clock rate is chosen
four times faster than the standard requests, to
force the BREAK symbol (nominally 300 µs long)
and the Transmitter Timeout Time (nominally 1
ms) at their nominal durations.
JBLPD CONTROL REGISTER (CONTROL)
R245- Read/Write
Register Page: 23
Reset Value: 0100 0000 (40h)
7
0
When the user want to use a 4 times faster J1850
clock rate, the new prescaler factor should be
stored in the FREQ[5:0] bits and the 4X bit must be
set with the same instruction. In the same way, to
exit from the mode, FREQ[5:0] and 4X bits must
be placed at the previous value with the same in-
struction.
JE
JDIS
NFL JDLY4 JDLY3 JDLY2 JDLY1 JDLY0
The CONTROL register is an eight bit read/write
register which contains JBLPD control information.
Reads of this register return the last written data.
0: Diagnostic Four Times Mode disabled
1: Diagnostic Four Times Mode enabled
Bit 7 = JE JBLPD Enable.
Note: Setting this bit, the prescaler factor is not au-
tomatically divided by four. The user must adapt
the value stored in FREQ[5:0] bits by software.
The JBLPD block enable bit (JE) enables and dis-
ables the transmitter and receiver to the VPWO
and VPWI pins respectively. When the JBLPD pe-
ripheral is disabled the VPWO pin is in its passive
state and information coming in the VPWI pin is ig-
nored. When the JBLPD block is enabled, the
transmitter and receiver function normally. Note
that queued transmits are aborted when JE is
cleared. JE is cleared on reset, by software and
setting the JDIS bit.
Note: The customer should take care using this
mode when the MCU internal frequency is less
than 4MHz.
Bit 6 = Reserved.
0: The peripheral is disabled
1: The peripheral is enabled
Bit 5:0 = FREQ[5:0] Internal Frequency Selectors.
These 6 bits must be programmed depending on
the internal frequency of the device. The formula
that must be used is the following one:
Note: It is not possible to reset the JDIS bit and to
set the JE bit with the same instruction. The cor-
rect sequence is to first reset the JDIS bit and then
set the JE bit with another instruction.
MCU Int. Freq.= 1MHz * (FREQ[5:0] + 1).
Note: To obtain a correct operation of the periph-
eral, the internal frequency of the MCU (INTCLK)
must be an integer multiple of 1MHz and the cor-
311/426
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 6 = JDIS Peripheral clock frozen.
When this bit is set by software, the peripheral is
stopped and the bus is not decoded anymore. A
reset of the bit restarts the internal state machines
as after a MCU reset. The JDIS bit is set on MCU
reset.
Bit 4:0 = JDLY[4:0] JBLPD Transceiver External
Loop Delay Selector.
These five bits are used to select the nominal ex-
ternal loop time delay which normally occurs when
the peripheral is connected and transmitting in a
J1850 bus system. The external loop delay is de-
fined as the time between when the VPWO is set
to a certain level to when the VPWI recognizes the
corresponding (inverted) edge on its input. Refer
to “Transmit Opcode Queuing” section and the
SAE-J1850 standard for information on how the
external loop delay is used in timing transmitted
symbols.
0: The peripheral clock is running
1: The peripheral clock is stopped
Note: When the JDIS bit is set, the STATUS reg-
ister, the ERROR register, the IMR register and
the TEOBP and REOBP bits of the PRLR register
are forced into their reset value.
Note: It is not possible to reset the JDIS bit and to
set the JE bit with the same instruction. The cor-
rect sequence is to first reset the JDIS bit and then
set the JE bit with another instruction.
The allowed values are integer values between 0
µs and 31 µs.
JBLPD PHYSICAL ADDRESS REGISTER
(PADDR)
Bit 5 = NFL No Frame Length Check
R246- Read/Write
The NFL bit is used to enable/disable the J1850
requirement of 12 bytes maximum per frame limit.
The SAE J1850 standard states that a maximum
of 12 bytes (including CRCs and IFRs) can be on
the J1850 between a start of frame symbol (SOF)
and an end of frame symbol (EOF). If this condi-
tion is violated, then the JBLPD peripheral gets an
Invalid Frame Detect (IFD) and the sleep mode
ensues until a valid EOFM is detected. If the valid
frame check is disabled (NFL=1), then no limits
are imposed on the number of data bytes which
can be sent or received on the bus between an
SOF and an EOF. The default upon reset is for the
frame checking to be enabled.
Register Page: 23
Reset Value: xxxx xxxx (xxh)
7
0
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
The PADDR is an eight bit read/write register
which contains the physical address of the JBLPD
peripheral. During initialization the user program
will write the PADDR register with its physical ad-
dress. The Physical Address is used during in-
frame response types 1 and 2 to acknowledge the
receipt of a message. The JBLPD peripheral will
transmit the contents of the PADDR register for
type 1 or 2 IFRs as defined by the TXOP register.
This register is undefined on reset.
The NFL bit is cleared on reset
0: Twelve bytes frame length check enabled
1: Twelve bytes frame length check disabled
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD ERROR REGISTER (ERROR)
R247- Read only
is set, then the TTO will timeout at 4000 prescaled
clock cycles. When the TTO flag is set then the di-
agnostic circuit will disable the VPWO signal, and
disable the JBLPD peripheral. The user program
must then clear the JE bit to remove the TTO error.
It can then retry the block by setting the JE bit
again.
Register Page: 23
Reset Value: 0000 0000 (00h)
7
0
TTO TDUF RDOF TRA RBRK CRCE IFD
IBD
The TTO bit can be used to determine if the exter-
nal J1850 bus is shorted low. Since the transmitter
looks for proper edges returned at the VPWI pin
for its timing, a lack of edges seen at VPWI when
trying to transmit (assuming the RBRK does not
get set) would indicate a constant low condition.
The user program can take appropriate actions to
test the J1850 bus circuit when a TTO occurs.
Note that a transmit attempt must occur to detect a
bus shorted low condition.
The TTO bit is cleared while the CONTROL.JE bit
is reset or while the CONTROL.JDIS bit is set.
TTO is cleared on reset.
0: VPWO line at 1 for less than 1 ms
1: VPWO line at 1 for longer than 1 ms
ERROR is an eight bit read only register indicating
error conditions that may arise on the VPWO and
VPWI pins. A read of the ERROR register clears
all bits (except for TTO and possibly the RBRK bit)
which were set at the time of the read. The register
is cleared after the MCU reset, while the CON-
TROL.JE bit is reset, or while the CONTROL.JDIS
bit is set.
All error conditions that can be read in the ERROR
register need to have redundant ERROR indicator
flags because:
– With JE set, the TDUF, RDOF, TRA, CRCE, IFD,
& IBD bits in the ERROR register can only be
cleared by reading the register.
Bit 6 = TDUF Transmitter Data Underflow.
The TDUF will be set to a logic one if the transmit-
ter expects more information to be transmitted, but
a TXOP write has not occurred in time (by the end
of transmission of the last bit).
– The TTO bit can only be cleared by clearing the
JE bit.
– The RBRK bit can only be cleared by reading the
ERROR register after the break condition has
disappeared.
The transmitter knows to expect more information
from the user program when transmitting messag-
es or type 3 IFRs only. If an opcode is written to
TXOP that does not include appending a CRC
byte, then the JBLPD peripheral assumes more
data is to be written. When the JBLPD peripheral
has shifted out the data byte it must have the next
data byte in time to place it directly next to it. If the
user program does not place new data in the TX-
DATA register and write the TXOP register with a
proper opcode, then the CRC byte which is being
kept tabulated by the transmitter is logically invert-
ed and transmitted out the VPWO pin. This will en-
sure that listeners will detect this message as an
error. In this case the TDUF bit is set to a logic
one.
Error condition indicator flags associated with the
error condition are cleared when the error condi-
tion ends. Since error conditions may alter the ac-
tions of the transmitter and receiver, the error con-
dition indicators must remain set throughout the
error condition. All error conditions, including the
RBRK condition, are events that get set during a
particular clock cycle of the prescaled clock of the
peripheral. The IFD, IBD, RBRK, and CRCE error
conditions are then cleared when a valid EOF
symbol is detected from the VPWI pin. The TRA
error condition is a singular event that sets the cor-
responding ERROR register bit, but this error itself
causes no other actions.
TDUF is cleared by reading the ERROR register
with TDUF set. TDUF is also cleared on reset,
while the CONTROL.JE bit is reset or while the
CONTROL.JDIS bit is set.
0: No transmitter data underflow condition oc-
curred
1: Transmitter data underflow condition occurred
Bit 7 = TTO Transmitter Timeout Flag
The TTO bit is set when the VPWO pin has been in
a logic one (or active) state for longer than 1 ms.
This flag is the output of a diagnostic circuit based
on the prescaled system clock input. If the 4X bit is
not set, the TTO will trip if the VPWO is constantly
active for 1000 prescaled clock cycles. If the 4X bit
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 5 = RDOF Receiver Data Overflow
The RDOF gets set to a logic one if the data in the
RXDATA register has not been read and new data
is ready to be transferred to the RXDATA register.
The old RXDATA information is lost since it is
overwritten with new data.
0: No valid Break symbol received
1: Valid Break symbol received
Bit 2 = CRCE Cyclic Redundancy Check Error
The receiver section always keeps a running tab of
the CRC of all data bytes received from the VPWl
since the last EOD symbol. The CRC check is per-
formed when a valid EOD symbol is received both
after a message string (subsequent to an SOF
symbol) and after an IFR3 string (subsequent to
an NB0 symbol). If the received CRC check fails,
then the CRCE bit is set to a logic one. CRC errors
are inhibited if the JBLPD peripheral is in the
“sleep or filter and NOT presently transmitting”
mode. A CRC error occurs once for a frame. After-
wards, the receiver is disabled until an EOFM
symbol is received and queued transmits for the
present frame are cancelled (but the TRA bit is not
set). CRCE is cleared when ERROR is read. It is
also cleared while the CONTROL.JE bit is reset or
while the CONTROL.JDIS bit is set, or on reset.
0: No CRC error detected
RDOF is cleared by reading the ERROR register
with RDOF set, while the CONTROL.JE bit is reset
or while the CONTROL.JDIS bit is set, or on reset.
0: No receiver data overflow condition occurred
1: Receiver data overflow condition occurred
Bit 4 = TRA Transmit Request Aborted
The TRA gets set to a logic one if a transmit op-
code is aborted by the JBLPD state machine.
Many conditions may cause a TRA. They are ex-
plained in the transmit opcode section. If the TRA
bit gets set after a TXOP write, then a transmit is
not attempted, and the TRDY bit is not cleared.
If a TRA error condition occurs, then the requested
transmit is aborted, and the JBLPD peripheral
takes appropriate measures as described under
the TXOP register section.
1: CRC error detected
TRA is cleared on reset, while the CONTROL.JE
bit is reset or while the CONTROL.JDIS bit is set.
0: No transmission request aborted
Bit 1 = IFD Invalid Frame Detect
The IFD bit gets set when the following conditions
are detected from the filtered VPWI pin:
1: Transmission request aborted
Bit 3 = RBRK Received Break Symbol Flag
The RBRK gets set to a logic one if a valid break
(BRK) symbol is detected from the filtered VPWI
pin. A Break received from the J1850 bus will can-
cel queued transmits of all types. The RBRK bit re-
mains set as long as the break character is detect-
ed from the VPWI. Reads of the ERROR register
will not clear the RBRK bit as long as a break char-
acter is being received. Once the break character
is gone, a final read of the ERROR register clears
this bit.
An RBRK error occurs once for a frame if it is re-
ceived during a frame. Afterwards, the receiver is
disabled from receiving information (other than the
break) until an EOFM symbol is received.
RBRK bit is cleared on reset, while the CON-
TROL.JE bit is reset or while the CONTROL.JDIS
bit is set.
The RBRK bit can be used to detect J1850 bus
shorted high conditions. If RBRK is read as a logic
high multiple times before an EOFM occurs, then a
possible bus shorted high condition exists. The
user program can take appropriate measures to
test the bus if this condition occurs. Note that this
bit does not necessarily clear when ERROR is
read.
– An SOF symbol is received after an EOD mini-
mum, but before an EOF minimum.
– An SOF symbol is received when expecting data
bits.
– If NFL = 0 and a message frame greater than 12
bytes (i.e. 12 bytes plus one bit) has been re-
ceived in one frame.
– An EOD minimum time has elapsed when data
bits are expected.
– A logic 0 or 1 symbol is received (active for Tv1
or Tv2) when an SOF was expected.
– The second EODM symbol received in a frame
is NOT followed directly by an EOFM symbol.
IFD errors are inhibited if the JBLPD peripheral is
in the “sleep or filter and NOT presently transmit-
ting” mode. An IFD error occurs once for a frame.
Afterwards, the receiver is disabled until an EOFM
symbol is received, and queued transmits for the
present frame are cancelled (but the TRA bit is not
set). IFD is cleared when ERROR is read. It is also
cleared while the CONTROL.JE bit is reset or
while the CONTROL.JDIS bit is set or on reset.
0: No invalid frame detected
1: Invalid frame detected
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 0 = IBD Invalid Bit Detect.
Bit 0 = Reserved.
The IBD bit gets set whenever the receiver detects
that the filtered VPWI pin was not fixed in a state
long enough to reach the minimum valid symbol
time of Tv1 (or 35 µs). Any timing event less than
35 µs (and, of course, > 7 µs since the VPWI digit-
al filter will not allow pulses less than this through
its filter) is considered as noise and sets the IBD
accordingly. At this point the JBLPD peripheral will
cease transmitting and receiving any information
until a valid EOF symbol is received.
JBLPD PRIORITY LEVEL REGISTER (PRLR)
R249- Read/Write
Register Page: 23
Reset Value: 0001 0000 (10h)
7
0
PRL2 PRL1 PRL0 SLP
-
-
REOBP TEOBP
IBD errors are inhibited if the JBLPD peripheral is
in the “sleep or filter and NOT presently transmit-
ting” mode. An IBD error occurs once for a frame.
Afterwards, the receiver is disabled until an EOFM
symbol is received, and queued transmits for the
present frame are cancelled (but the TRA bit is not
set).
IBD is cleared when ERROR is read. Note that if
an invalid bit is detected during a bus idle condi-
tion, the IBD flag gets set and a new EOFmin must
be seen after the invalid bit before commencing to
receive again. IBD is also cleared while the CON-
TROL.JE bit is reset or while the CONTROL.JDIS
bit is set and on reset.
Bit 7:5 = PRL[2:0] Priority level bits
The priority with respect to the other peripherals
and the CPU is encoded with these three bits. The
value of “0” has the highest priority, the value “7”
has no priority. After the setting of this priority lev-
el, the priorities between the different Interrupt
sources and DMA of the JBLPD peripheral is hard-
ware defined (refer to the “Status register” bits de-
scription, the “Interrupts Management” and the
section about the explanation of the meaning of
the interrupt sources).
Depending on the value of the OP-
TIONS.DMASUSP bit, the DMA transfers can or
cannot be suspended by an ERROR or TLA event.
Refer to the description of DMASUSP bit.
0: No invalid bit detected
1: Invalid bit detected
Table 60. Internal Interrupt and DMA Priorities
without DMA suspend mode
JBLPD INTERRUPT VECTOR REGISTER (IVR)
R248- Read/Write (except bits 2:1)
Register Page: 23
Priority Level
Event Sources
TX-DMA
Higher Priority
Reset Value: xxxx xxx0 (xxh)
RX-DMA
7
0
-
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
V7
V6
V5
V4
V3
EV2
EV1
Bit 7:3 = V[7:3] Interrupt Vector Base Address.
User programmable interrupt vector bits.
Lower Priority
Bit 2:1 = EV[2:1] Encoded Interrupt Source (Read
Only).
EV2 and EV1 are set by hardware according to the
interrupt source, given in Table 59 (refer to the
Status register bits description about the explana-
tion of the meaning of the interrupt sources)
Table 61. Internal Interrupt and DMA Priorities
with DMA suspend mode
Priority Level
Event Sources
ERROR, TLA
TX-DMA
Higher Priority
Table 59. Interrupt Sources
RX-DMA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
EV2
EV1
Interrupt Sources
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
0
0
1
1
0
1
0
1
Lower Priority
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 4 = SLP Receiver Sleep Mode.
the end of a block of data. An interrupt request is
performed if the TRDY_M bit of the IMR register is
set. TEOBP should be reset by software in order to
avoid undesired interrupt routines, especially in in-
itialisation routine (after reset) and after entering
the End Of Block interrupt routine.
Writing “0” in this bit will cancel the interrupt re-
quest.
This bit is reset when the CONTROL.JDIS bit is
set at least for 6 MCU clock cycles (3 NOPs).
The SLP bit is written to one when the user pro-
gram does not want to receive any data from the
JBLPD VPWI pin until an EOFM symbol occurs.
This mode is usually set when a message is re-
ceived that the user does not require - including
messages that the JBLPD is transmitting.
If the JBLPD is not transmitting and is in Sleep
mode, no data is transferred to the RXDATA regis-
ter, the RDRF flag does not get set, and errors as-
sociated with received data (RDOF, CRCE, IFD,
IBD) do not get set. Also, the EODM flag will not
get set.
Note: When the TEOBP flag is set, the TXD_M bit
is reset by hardware.
Note: TEOBP can only be written to “0”.
If the JBLPD peripheral is transmitting and is in
sleep mode, no data is transferred to the RXDATA
register, the RDRF flag does not get set and the
RDOF error flag is inhibited. The CRCE, IFD, and
IBD flags, however, will NOT be inhibited while
transmitting in sleep mode.
The SLP bit cannot be written to zero by the user
program. The SLP bit is set on reset or TTO get-
ting set, and it will stay set upon JE getting set until
an EOFM symbol is received.
JBLPD INTERRUPT MASK REGISTER (IMR)
R250 - Read/Write
Register Page: 23
Reset Value: 0000 0000 (00h)
7
0
ERR_ TRDY_ RDRF_ TLA_ RXD_ EODM_ EOFM_ TXD_
M
M
M
M
M
M
M
M
The SLP gets cleared on reception of an EOF or a
Break symbol. SLP is set while CONTROL.JE is
reset and while CONTROL.JDIS is set.
To enable an interrupt source to produce an inter-
rupt request, the related mask bit must be set.
When these bits are reset, the related Interrupt
Pending bit can not generate an interrupt.
0: The JBLPD is not in Sleep Mode
1: The JBLPD is in Sleep Mode
Note: This register is forced to its reset value if the
CONTROL.JDIS bit is set at least for 6 clock cy-
cles (3 NOPs). If the JDIS bit is set for a shorter
time, the bits could be reset or not reset.
Bit 3:2 = Reserved.
Bit 1 = REOP Receiver DMA End Of Block Pend-
ing.
This bit is set after a receiver DMA cycle to mark
the end of a block of data. An interrupt request is
performed if the RDRF_M bit of the IMR register is
set. REOBP should be reset by software in order
to avoid undesired interrupt routines, especially in
initialisation routine (after reset) and after entering
the End Of Block interrupt routine.
Bit 7 = ERR_M Error Interrupt Mask bit.
This bit enables the “error” interrupt source to gen-
erate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Error interrupt source masked
1: Error interrupt source un-masked
Writing “0” in this bit will cancel the interrupt re-
quest.
This bit is reset when the CONTROL.JDIS bit is
set at least for 6 MCU clock cycles (3 NOPs).
Bit 6 = TRDY_M Transmit Ready Interrupt Mask
bit.
This bit enables the “transmit ready” interrupt
source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
Note: When the REOBP flag is set, the RXD_M bit
is reset by hardware.
Note: REOBP can only be written to “0”.
0: TRDY interrupt source masked
1: TRDY interrupt source un-masked
Bit 0 = TEOP Transmitter DMA End Of Block
Pending.
This bit is set after a transmitter DMA cycle to mark
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 5 = RDRF_M Receive Data Register Full Inter-
rupt Mask bit.
This bit enables the “receive data register full” in-
terrupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
Bit 0 = TXD_M Transmitter DMA Mask bit.
If this bit is “0” no transmitter DMA request will be
generated, and the TRDY bit, in the Status Regis-
ter (STATUS), can request an interrupt. If TXD_M
bit is set to “1” then the TRDY bit can request a
DMA transfer. TXD_M is reset by hardware when
the transaction counter value decrements to zero,
that is when a Transmitter End Of Block condition
occurs (TEOBP flag set).
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Transmitter DMA disabled
1: Transmitter DMA enabled
0: RDRF interrupt source masked
1: RDRF interrupt source un-masked
Bit 4 = TLA_M Transmitter Lost Arbitration Inter-
rupt Mask bit.
This bit enables the “transmitter lost arbitration” in-
terrupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: TLA interrupt source masked
1: TLA interrupt source un-masked
JBLPD OPTIONS AND REGISTER GROUPS
SELECTION REGISTER (OPTIONS)
R251- Read/Write
Bit 3 = RXD_M Receiver DMA Mask bit.
If this bit is “0” no receiver DMA request will be
generated, and the RDRF bit, in the Status Regis-
ter (STATUS), can request an interrupt. If RXD_M
bit is set to “1” then the RDRF bit can request a
DMA transfer. RXD_M is reset by hardware when
the transaction counter value decrements to zero,
that is when a Receiver End Of Block condition oc-
curs (REOBP flag set).
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Receiver DMA disabled
1: Receiver DMA enabled
Register Page: 23
Reset Value: 0000 0000 (00h)
7
0
INPOL NBSYMS DMASUSP LOOPB RSEL3 RSEL2 RSEL1 RSEL0
Bit 7 = INPOL VPWI Input Polarity Selector.
This bit allows the selection of the polarity of the
RX signal coming from the transceivers. Depend-
ing on the specific transceiver, the RX signal is in-
verted or not inverted respect the VPWO and the
J1850 bus line.
0: VPWI input is inverted by the transceiver with
respect to the J1850 line.
1: VPWI input is not inverted by the transceiver
with respect to the J1850 line.
Bit 2 = EODM_M End of Data Minimum Interrupt
Mask bit.
This bit enables the “end of data minimum” inter-
rupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
Bit 6 = NBSYMS NB Symbol Form Selector.
This bit allows the selection of the form of the Nor-
malization Bits (NB0/NB1).
0: NB0 active long symbol (Tv2), NB1 active short
symbol (Tv1)
1: NB0 active short symbol (Tv1), NB1 active long
symbol (Tv2)
0: EODM interrupt source mask
1: EODM interrupt source un-masked
Bit 1 = EOFM_M End of Frame Minimum Interrupt
Mask bit.
This bit enables the “end of frame minimum” inter-
rupt source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: EOFM interrupt source masked
1: EOFM interrupt source un-masked
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 5 = DMASUSP DMA Suspended Selector.
If this bit is “0”, JBLPD DMA has higher priority
with respect to the Interrupts of the peripheral.
DMA is performed even if an interrupt request is
already scheduled or if the relative interrupt rou-
tine is in execution.
If the bit is “1”, while the ERROR or TLA flag of the
STATUS register are set, the DMA transfers are
suspended. As soon as the flags are reset, the
DMA transfers can be performed.
Note: When the LOOPB bit is set, also the INPOL
bit must be set to obtain the correct management
of the polarity.
Bit 3:0 = RSEL[3:0] Registers Group Selection
bits.
These four bits are used to select one of the 9
groups of registers, each one composed of four
registers that are stacked at the addresses from
R252 (FCh) to R255 (FFh) of this register page
(23). Unless the wanted registers group is already
selected, to address a specific registers group,
these bits must be correctly written.
This feature allows that 36 registers (4 DMA regis-
ters - RDADR, RDCPR, TDAPR, TDCPR - and 32
Message Filtering Registers - FREG[0:31]) are
mapped using only 4 registers (here called Current
Registers - CREG[3:0]).
0: DMA not suspended
1: DMA suspended
Note: This bit has effect only on the priorities of
the JBLPD peripheral.
Bit 4 = LOOPB Local Loopback Selector.
This bit allows the Local Loopback mode. When
this mode is enabled (LOOPB=1), the VPWO out-
put of the peripheral is sent to the VPWI input with-
out inversions whereas the VPWO output line of
the MCU is placed in the passive state. Moreover
the VPWI input of the MCU is ignored by the pe-
ripheral. (Refer to Figure 138).
Since
the
Message
Filtering
Registers
(FREG[0:31]) are seldom read or written, it is sug-
gested to always reset the RSEL[3:0] bits after ac-
cessing the FREG[0:31] registers. In this way the
DMA registers are the current registers.
0: Local Loopback disabled
1: Local Loopback enabled
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD CURRENT REGISTER 0 (CREG0)
R252- Read/Write
JBLPD CURRENT REGISTER 2 (CREG2)
R254- Read/Write
Register Page: 23
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Reset Value: xxxx xxxx (xxh)
7
0
7
0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Depending on the RSEL[3:0] value of the OP-
TIONS register, this register is one of the following
stacked registers: RDAPR, FREG0, FREG4,
FREG8, FREG12, FREG16, FREG20, FREG24,
FREG28.
Depending on the RSEL[3:0] value of the OP-
TIONS register, this register is one of the following
stacked registers: TDAPR, FREG2, FREG6,
FREG10, FREG14, FREG18, FREG22, FREG26,
FREG30.
JBLPD CURRENT REGISTER 1 (CREG1)
R253 - Read/Write
JBLPD CURRENT REGISTER 3 (CREG3)
R255- Read/Write
Register Page: 23
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Reset Value: xxxx xxxx (xxh)
7
0
7
0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Depending on the RSEL[3:0] value of the OP-
TIONS register, this register is one of the following
stacked registers: RDCPR, FREG1, FREG5,
FREG9, FREG13, FREG17, FREG21, FREG25,
FREG29.
Depending on the RSEL[3:0] value of the OP-
TIONS register, this register is one of the following
stacked registers: TDCPR, FREG3, FREG7,
FREG11, FREG15, FREG19, FREG23, FREG27,
FREG31.
Table 62. Stacked registers map
RSEL[3:0]
Current
0000b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Registers
CREG0
CREG1
CREG2
CREG3
RDAPR FREG0 FREG4
RDCPR FREG1 FREG5
FREG8
FREG9
FREG12 FREG16 FREG20 FREG24 FREG28
FREG13 FREG17 FREG21 FREG25 FREG29
TDAPR FREG2 FREG6 FREG10 FREG14 FREG18 FREG22 FREG26 FREG30
TDCPR FREG3 FREG7 FREG11 FREG15 FREG19 FREG23 FREG27 FREG31
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.7.2 Stacked Registers
Register File) of the DMA receiver transaction
counter when the DMA between Peripheral and
Memory Space is selected. Otherwise, if the DMA
between Peripheral and Register File is selected,
this register points to a pair of registers that are
used as DMA Address register and DMA Transac-
tion Counter.
See the description of the OPTIONS register to
obtain more information on the map of the regis-
ters of this section.
JBLPD RECEIVER DMA ADDRESS POINTER
REGISTER (RDAPR)
See Section 10.9.6.1and Section 10.9.6.2 for
more details on the use of this register.
R252 - RSEL[3:0]=0000b
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Bit 0 = RF/MEM Receiver Register File/Memory
Selector.
7
0
If this bit is set to “1”, then the Register File will be
selected as Destination, otherwise the Memory
space will be used.
RA7
RA6
RA5
RA4
RA3
RA2
RA1
PS
0: Receiver DMA with Memory space
1: Receiver DMA with Register File
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = RA[7:1] Receiver DMA Address Pointer.
RDAPR contains the address of the pointer (in the
Register File) of the Receiver DMA data source
when the DMA between the peripheral and the
Memory Space is selected. Otherwise, when the
DMA between the peripheral and Register File is
selected, this register has no meaning.
JBLPD TRANSMITTER DMA ADDRESS POINT-
ER REGISTER (TDAPR)
R254 - RSEL[3:0]=0000b
Register Page: 23
Reset Value: xxxx xxxx (xxh)
7
0
See Section 10.9.6.2 for more details on the use of
this register.
TA7
TA6
TA5
TA4
TA3
TA2
TA1
PS
Bit 0 = PS Memory Segment Pointer Selector.
This bit is set and cleared by software. It is only
meaningful if RDCPR.RF/MEM = 1.
0: The ISR register is used to extend the address
of data received by DMA (see MMU chapter)
1: The DMASR register is used to extend the ad-
dress of data received by DMA (see MMU chap-
ter)
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = TA[7:1] Transmitter DMA Address Point-
er.
TDAPR contains the address of the pointer (in the
Register File) of the Transmitter DMA data source
when the DMA between the Memory Space and
the peripheral is selected. Otherwise, when the
DMA between Register File and the peripheral is
selected, this register has no meaning.
See Section 10.9.6.2 for more details on the use of
this register.
JBLPD RECEIVER DMA TRANSACTION
COUNTER REGISTER (RDCPR)
R253 - RSEL[3:0]=0000b
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Bit 0 = PS Memory Segment Pointer Selector.
This bit is set and cleared by software. It is only
meaningful if TDCPR.RF/MEM = 1.
0: The ISR register is used to extend the address
of data transmitted by DMA (see MMU chapter)
1: The DMASR register is used to extend the ad-
dress of data transmitted by DMA (see MMU
chapter)
7
0
RC7
RC6
RC5
RC4
RC3
RC2
RC1 RF/MEM
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = RC[7:1] Receiver DMA Counter Pointer.
RDCPR contains the address of the pointer (in the
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
JBLPD TRANSMITTER DMA TRANSACTION
COUNTER REGISTER (TDCPR)
R255 - RSEL[3:0]=0000b
JBLPD MESSAGE FILTERING REGISTERS
(FREG[0:31])
R252/R253/R254/R255 - RSEL[3]=1
Register Page: 23
Register Page: 23
Reset Value: xxxx xxxx (xxh)
Reset Value: xxxx xxxx (xxh)
7
0
Register
7
0
FREG0 F_07 F_06 F_05 F_04 F_03 F_02 F_01 F_00
FREG1 F_0F F_0E F_0D F_0C F_0B F_0A F_09 F_08
FREG2 F_17 F_16 F_15 F_14 F_13 F_12 F_11 F_10
FREG3 F_1F F_1E F_1D F_1C F_1B F_1A F_19 F_18
FREG4 F_27 F_26 F_25 F_24 F_23 F_22 F_21 F_20
FREG5 F_2F F_2E F_2D F_2C F_2B F_2A F_29 F_28
FREG6 F_37 F_36 F_35 F_34 F_33 F_32 F_31 F_30
FREG7 F_3F F_3E F_3D F_3C F_3B F_3A F_39 F_38
FREG8 F_47 F_46 F_45 F_44 F_43 F_42 F_41 F_40
FREG9 F_4F F_4E F_4D F_4C F_4B F_4A F_49 F_48
FREG10 F_57 F_56 F_55 F_54 F_53 F_52 F_51 F_50
FREG11 F_5F F_5E F_5D F_5C F_5B F_5A F_59 F_58
FREG12 F_67 F_66 F_65 F_64 F_63 F_62 F_61 F_60
FREG13 F_6F F_6E F_6D F_6C F_6B F_6A F_69 F_68
FREG14 F_77 F_76 F_75 F_74 F_73 F_72 F_71 F_70
FREG15 F_7F F_7E F_7D F_7C F_7B F_7A F_79 F_78
FREG16 F_87 F_86 F_85 F_84 F_83 F_82 F_81 F_80
FREG17 F_8F F_8E F_8D F_8C F_8B F_8A F_89 F_88
FREG18 F_97 F_96 F_95 F_94 F_93 F_92 F_91 F_90
FREG19 F_9F F_9E F_9D F_9C F_9B F_9A F_99 F_98
FREG20 F_A7 F_A6 F_A5 F_A4 F_A3 F_A2 F_A1 F_A0
FREG21 F_AF F_AE F_AD F_AC F_AB F_AA F_A9 F_A8
FREG22 F_B7 F_B6 F_B5 F_B4 F_B3 F_B2 F_B1 F_B0
FREG23 F_BF F_BE F_BD F_BC F_BB F_BA F_B9 F_B8
FREG24 F_C7 F_C6 F_C5 F_C4 F_C3 F_C2 F_C1 F_C0
FREG25 F_CF F_CE F_CD F_CC F_CB F_CA F_C9 F_C8
FREG26 F_D7 F_D6 F_D5 F_D4 F_D3 F_D2 F_D1 F_D0
FREG27 F_DF F_DE F_DD F_DC F_DB F_DA F_D9 F_D8
FREG28 F_E7 F_E6 F_E5 F_E4 F_E3 F_E2 F_E1 F_E0
FREG29 F_EF F_EE F_ED F_EC F_EB F_EA F_E9 F_E8
FREG30 F_F7 F_F6 F_F5 F_F4 F_F3 F_F2 F_F1 F_F0
FREG31 F_FF F_FE F_FD F_FC F_FB F_FA F_F9 F_F8
TC7
TC6
TC5
TC4
TC3
TC2
TC1 RF/MEM
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = TC[7:1] Transmitter DMA Counter Point-
er.
RDCPR contains the address of the pointer (in the
Register File) of the DMA transmitter transaction
counter when the DMA between Memory Space
and peripheral is selected. Otherwise, if the DMA
between Register File and peripheral is selected,
this register points to a pair of registers that are
used as DMA Address register and DMA Transac-
tion Counter.
See Section 10.9.6.1and Section 10.9.6.2 for
more details on the use of this register.
Bit 0 = RF/MEM Transmitter Register File/Memory
Selector.
If this bit is set to “1”, then the Register File will be
selected as Destination, otherwise the Memory
space will be used.
0: Transmitter DMA with Memory space
1: Transmitter DMA with Register File
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9
J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
These registers are structured in eight groups of
four registers. The user can gain access to these
registers programming the RSEL[2:0] bits of the
OPTIONS register while the RSEL[3] bit of the
same register must be placed at 1. In this way the
user can select the group where the registers that
he/she wants to use are placed. See the descrip-
tion of OPTIONS register for the correspondence
between registers and the values of RSEL[2:0] bits
(See Table 62).
register and the RDRF flag is set. Also, every other
data byte received in this frame is transferred to
the RXDATA register unless the JBLPD peripheral
is put into sleep mode setting the SLP bit.
If the bit of the array correspondent to the I.D. byte
is clear, then the transfer of this byte as well as any
byte for the balance of this frame is inhibited, and
the RDRF bit remains cleared.
The bit 0 of the FREG[0] register (FREG[0].0 -
marked as F_00 in the previous table) corre-
sponds to the I.D. byte equal to 00h while the bit 7
of the FREG[31] register (FREG[31].7 - marked as
F_FF in the previous table) corresponds to the I.D.
byte equal to FFh.
From the functional point of view, the FREG[0]-
FREG[31] registers can be seen as an array of
256 bits involved in the J1850 received message
filtering system.
The first byte received in a frame (following a valid
received SOF character) is an Identifier (I.D.) byte.
It is used by the JBLPD peripheral as the address
of the 256 bits array.
Note: The FREG registers are undefined upon re-
set. Because of this, it is strongly recommended
that the contents of these registers has to be de-
fined before JE is set for the first time after reset.
Otherwise, unpredictable results may occur.
If the bit of the array correspondent to the I.D. byte
is set, then the byte is transferred to the RXDATA
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Register
Address
F0h
7
0
STATUS
reset value
ERR
0
TRDY
1
RDRF
0
TLA
0
RDT
0
EODM
0
EOFM
0
IDLE
0
TXDATA
TXD7
x
TXD6
x
TXD5
x
TXD4
x
TXD3
x
TXD2
x
TXD1
x
TXD0
x
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
reset value
RXDATA
reset value
RXD7
x
RXD6
x
RXD5
x
RXD4
x
RXD3
x
RXD2
x
RXD1
x
RXD0
x
TXOP
reset value
MLC3
0
MLC2
0
MLC1
0
MLC0
0
-
0
OP2
0
OP1
0
OP0
0
CLKSEL
reset value
4X
0
-
0
FREQ5
0
FREQ4
0
FREQ3
0
FREQ2
0
FREQ1
0
FREQ0
0
CONTROL
reset value
JE
0
JDIS
1
NFL
0
JDLY4
0
JDLY3
0
JDLY2
0
JDLY1
0
JDLY0
0
PADDR
reset value
ADR7
x
ADR6
x
ADR5
x
ADR4
x
ADR3
x
ADR2
x
ADR1
x
ADR0
x
ERROR
reset value
TTO
0
TDUF
0
RDOF
0
TRA
0
RBRK
0
CRCE
0
IFD
0
IBD
0
IVR
reset value
V7
x
V6
x
V5
x
V4
x
V3
x
EV2
x
EV1
x
-
0
PRLR
reset value
PRL2
0
PRL1
0
PRL0
0
SLP
1
-
0
-
0
REOBP
0
TEOBP
0
IMR
reset value
ERR_M
0
TRDY_M
0
RDRF_M
0
TLA_M
0
RXD_M
0
EODM_M EOFM_M
TXD_M
0
0
0
OPTIONS
reset value
INPOL
0
NBSYMS DMASUSP LOOPB
RSEL3
0
RSEL2
0
RSEL1
0
RSEL0
0
0
0
0
CREG0
reset value
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
x
b0
x
CREG1
reset value
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
x
b0
x
CREG2
reset value
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
x
b0
x
CREG3
reset value
b7
x
b6
x
b5
x
b4
x
b3
x
b2
x
b1
x
b0
x
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9
CONTROLLER AREA NETWORK (bxCAN)
10.10 CONTROLLER AREA NETWORK (bxCAN)
10.10.1 Introduction
■ 16-bit free running timer
■ Configurable timer resolution
■ Time Stamp sent in last two data bytes
Management
This peripheral Basic Extended CAN, named bx-
CAN, interfaces the CAN network. It supports the
CAN protocol version 2.0A and B. It has been de-
signed to manage a high number of incoming mes-
sages efficiently with a minimum CPU load. It also
meets the priority requirements for transmit mes-
sages.
■ Maskable interrupts
■ Software-efficient mailbox mapping at a unique
address space
For safety-critical applications, the CAN controller
provides all hardware functions for supporting the
CAN Time Triggered Communication option.
10.10.3 General Description
In today’s CAN applications, the number of nodes
in a network is increasing and often several net-
works are linked together via gateways. Typically
the number of messages in the system (and thus
to be handled by each node) has significantly in-
creased. In addition to the application messages,
Network Management and Diagnostic messages
have been introduced.
10.10.2 Main Features
■ Supports CAN protocol version 2.0 A, B Active
■ Bit rates up to 1Mbit/s
■ Supports the Time Triggered Communication
option
Transmission
– An enhanced filtering mechanism is required to
handle each type of message.
■ Three transmit mailboxes
■ Configurable transmit priority
■ Time Stamp on SOF transmission
Reception
■ Two receive FIFOs with three stages
■ Eight scalable filter banks
■ Identifier list feature
■ Configurable FIFO overrun
■ Time Stamp on SOF reception
Time Triggered Communication Option
■ Disable automatic retransmission mode
Furthermore, application tasks require more CPU
time, therefore real-time constraints caused by
message reception have to be reduced.
– A receive FIFO scheme allows the CPU to be
dedicated to application tasks for a long time pe-
riod without losing messages.
The standard HLP (Higher Layer Protocol) based
on standard CAN drivers requires an efficient in-
terface to the CAN controller.
– All mailboxes and registers are organized in 16-
byte pages mapped at the same address and se-
lected via a page select register.
Figure 142. CAN Network Topology
ST9 MCU
Application
CAN
Controller
CAN
Rx
CAN
Tx
CAN
Transceiver
CAN
High
CAN
Low
CAN Bus
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CONTROLLER AREA NETWORK (bxCAN)
Tx Mailboxes
CONTROLLER AREA NETWORK (Cont’d)
CAN 2.0B Active Core
The bxCAN module handles the transmission and
the reception of CAN messages fully autonomous-
ly. Standard identifiers (11-bit) and extended iden-
tifiers (29-bit) are fully supported by hardware.
Three transmit mailboxes are provided to the soft-
ware for setting up messages. The transmission
Scheduler decides which mailbox has to be trans-
mitted first.
Control, Status and Configuration Registers
The application uses these registers to:
– Configure CAN parameters, e.g.baud rate
– Request transmissions
Acceptance Filters
The bxCAN provides eight scalable/configurable
identifier filter banks for selecting the incoming
messages the software needs and discarding the
others.
– Handle receptions
Receive FIFO
– Manage interrupts
Two receive FIFOs are used by hardware to store
the incoming messages. Three complete messag-
es can be stored in each FIFO. The FIFOs are
managed completely by hardware.
– Get diagnostic information
Figure 143. CAN Block Diagram
Tx Mailboxes
Receive FIFO 0
Receive FIFO 1
Master Control
Mailbox 2
2
2
1
1
Master Status
Mailbox 0
Mailbox 0
Transmit Control
Mailbox 1
Transmit Status
Transmit Priority
Receive FIFO
Mailbox 0
Interrupt Enable
Page Select
Acceptance Filters
Error Status
7
6
5
4
Error Int. Enable
3
2
1
Transmission
0
Filter
Tx Error Counter
Scheduler
Rx Error Counter
Diagnostic
Bit Timing
CAN 2.0B Active Core
Filter Mode
Filter Config.
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CONTROLLER AREA NETWORK (Cont’d)
Figure 144. bxCAN Operating Modes
RESET
SLEEP
SLAK= 1
INAK = 0
SYNC
SLAK= X
INAK = X
NORMAL
INITIALIZATION
SLAK= 0
INAK = 1
SLAK= 0
INAK = 0
INRQ
10.10.4 Operating Modes
tus of the CAN bus output CANTX is recessive
(high).
bxCAN has three main operating modes: initiali-
zation, normal and sleep. After a hardware reset,
bxCAN is in sleep mode to reduce power con-
sumption and an internal pull-up is active on RX1.
The software requests bxCAN to enter initializa-
tion or sleep mode by setting the INRQ or SLEEP
bits in the CMCR register. Once the mode has
been entered, bxCAN confirms it by setting the
INAK or SLAK bits in the CMSR register and the
internal pull-up is disabled. When neither INAK nor
SLAK are set, bxCAN is in normal mode. Before
entering normal mode bxCAN always has to syn-
chronize on the CAN bus. To synchronize, bx-
CAN waits until the CAN bus is idle, this means 11
consecutive recessive bits have been monitored
on CANRX.
Entering Initialization Mode does not change any
of the configuration registers.
To initialize the CAN Controller, software has to
set up the Bit Timing registers and the filters. If a
filter bank is not used, it is recommended to leave
it non active (leave the corresponding FACT bit
cleared).
10.10.4.2 Normal Mode
Once the initialization has been done, the software
must request the hardware to enter Normal mode,
to synchronize on the CAN bus and start reception
and transmission. Entering Normal mode is done
by clearing the INRQ bit in the CMCR register and
waiting until the hardware has confirmed the re-
quest by clearing the INAK bit in the CMSR regis-
ter. Afterwards, the bxCAN synchronizes with the
data transfer on the CAN bus by waiting for the oc-
currence of a sequence of 11 consecutive reces-
sive bits (≡ Bus Idle) before it can take part in bus
activities and start message transfer.
10.10.4.1 Initialization Mode
The software initialization can be done while the
hardware is in Initialization mode. To enter this
mode the software sets the INRQ bit in the CMCR
register and waits until the hardware has con-
firmed the request by setting the INAK bit in the
CMSR register.
The initialization of the filter values is independent
from Initialization Mode but must be done while the
filter is not active (corresponding FACTx bit
cleared). The filter scale and mode configuration
must be configured before entering Normal Mode.
To leave Initialization mode, the software clears
the INQR bit. bxCAN has left Initialization mode
once the INAK bit has been cleared by hardware.
While in Initialization Mode, all message transfers
to and from the CAN bus are stopped and the sta-
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CONTROLLER AREA NETWORK (Cont’d)
10.10.4.3 Low Power Mode (Sleep)
without affecting it by the transmission of dominant
bits (Acknowledge Bits, Error Frames).
To reduce power consumption, bxCAN has a low
power mode called sleep mode. This mode is en-
tered on software request by setting the SLEEP bit
in the CMCR register. In this mode, the bxCAN
clock is stopped. Consequently, software can still
access the bxCAN registers and mailboxes but the
bxCAN will not update the status bits.
Figure 145. bxCAN in Silent Mode
bxCAN
Tx
Rx
Example: If software requests entry to initializa-
tion mode by setting the INRQ bit while bxCAN is
in sleep mode, it will not be acknowledged by the
hardware, INAK stays cleared.
=1
bxCAN can be woken up (exit sleep mode) either
by software clearing the SLEEP bit or on detection
of CAN bus activity.
CANTX CANRX
10.10.4.6 Loop Back Mode
On CAN bus activity detection, hardware automat-
ically performs the wake-up sequence by clearing
the SLEEP bit if the AWUM bit in the CMCR regis-
ter is set. If the AWUM bit is cleared, software has
to clear the SLEEP bit when a wake-up interrupt
occurs, in order to exit from sleep mode.
The bxCAN can be set in Loop Back Mode by set-
ting the LBKM bit in the CDGR register. In Loop
Back Mode, the bxCAN treats its own transmitted
messages as received messages and stores them
(if they pass acceptance filtering) in a Receive
mailbox. bxCAN in Loop Back Mode
Note: If the wake-up interrupt is enabled (WKUIE
bit set in CIER register) a wake-up interrupt will be
generated on detection of CAN bus activity, even if
the bxCAN automatically performs the wake-up
sequence.
bxCAN
After the SLEEP bit has been cleared, sleep mode
is exited once bxCAN has synchronized with the
CAN bus, refer to Figure 144.bxCAN Operating
Modes. The sleep mode is exited once the SLAK
bit has been cleared by hardware.
Tx
Rx
10.10.4.4 Test Mode
Test mode can be selected by the SILM and LBKM
bits in the CDGR register. These bits must be con-
figured while bxCAN is in Initialization mode. Once
test mode has been selected, the INRQ bit in the
CMCR register must be reset to enter Normal
mode.
CANTX CANRX
10.10.4.5 Silent Mode
This mode is provided for self-test functions. To be
independent of external events, the CAN Core ig-
nores acknowledge errors (no dominant bit sam-
pled in the acknowledge slot of a data / remote
frame) in Loop Back Mode. In this mode, the bx-
CAN performs an internal feedback from its Tx
output to its Rx input. The actual value of the CAN-
RX input pin is disregarded by the bxCAN. The
transmitted messages can be monitored on the
CANTX pin.
The bxCAN can be put in Silent mode by setting
the SILM bit in the CDGR register.
In Silent mode, the bxCAN is able to receive valid
data frames and valid remote frames, but it sends
only recessive bits on the CAN bus and it cannot
start a transmission. If the bxCAN has to send a
dominant bit (ACK bit, overload flag, active error
flag), the bit is rerouted internally so that the CAN
Core monitors this dominant bit, although the CAN
bus may remain in recessive state. Silent mode
can be used to analyze the traffic on a CAN bus
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CONTROLLER AREA NETWORK (Cont’d)
10.10.4.7 Loop Back combined with Silent
Mode
bitration Lost, and/or the TERR bit, in case of
transmission error detection.
It is also possible to combine Loop Back mode and
Silent mode by setting the LBKM and SILM bits in
the CDGR register. This mode can be used for a
“Hot Selftest”, meaning the bxCAN can be tested
like in Loop Back mode but without affecting a run-
ning CAN system connected to the CANTX and
CANRX pins. In this mode, the CANRX pin is dis-
connected from the bxCAN and the CANTX pin is
held recessive.
Transmit Priority
By Identifier:
When more than one transmit mailbox is pending,
the transmission order is given by the identifier of
the message stored in the mailbox. The message
with the lowest identifier value has the highest pri-
ority according to the arbitration of the CAN proto-
col. If the identifier values are equal, the lower
mailbox number will be scheduled first.
Figure 146. bxCAN in Combined Mode
By Transmit Request Order:
The transmit mailboxes can be configured as a
transmit FIFO by setting the TXFP bit in the CMCR
register. In this mode the priority order is given by
the transmit request order.
bxCAN
Tx
Rx
This mode is very useful for segmented transmis-
sion.
Abort
=1
A transmission request can be aborted by the user
setting the ABRQ bit in the MCSR register. In
pending or scheduled state, the mailbox is abort-
ed immediately. An abort request while the mail-
box is in transmit state can have two results. If the
mailbox is transmitted successfully the mailbox
becomes empty with the TXOK bit set in the
MCSR and CTSR registers. If the transmission
fails, the mailbox becomes scheduled, the trans-
mission is aborted and becomes empty with
TXOK cleared. In all cases the mailbox will be-
come empty again at least at the end of the cur-
rent transmission.
CANTX CANRX
10.10.5 Functional Description
10.10.5.1 Transmission Handling
In order to transmit a message, the application
must select one empty transmit mailbox, set up
the identifier, the data length code (DLC) and the
data before requesting the transmission by setting
the corresponding TXRQ bit in the MCSR register.
Once the mailbox has left empty state, the soft-
ware no longer has write access to the mailbox
registers. Immediately after the TXRQ bit has
been set, the mailbox enters pending state and
waits to become the highest priority mailbox, see
Transmit Priority. As soon as the mailbox has the
highest priority it will be scheduled for transmis-
sion. The transmission of the message of the
scheduled mailbox will start (enter transmit state)
when the CAN bus becomes idle. Once the mail-
box has been successfully transmitted, it will be-
come empty again. The hardware indicates a suc-
cessful transmission by setting the RQCP and
TXOK bits in the MCSR and CTSR registers.
Non-Automatic Retransmission Mode
This mode has been implemented in order to fulfil
the requirement of the Time Triggered Communi-
cation option of the CAN standard. To configure
the hardware in this mode the NART bit in the
CMCR register must be set.
In this mode, each transmission is started only
once. If the first attempt fails, due to an arbitration
loss or an error, the hardware will not automatical-
ly restart the message transmission.
At the end of the first transmission attempt, the
hardware considers the request as completed and
sets the RQCP bit in the MCSR register. The result
of the transmission is indicated in the MCSR regis-
ter by the TXOK, ALST and TERR bits.
If the transmission fails, the cause is indicated by
the ALST bit in the MCSR register in case of an Ar-
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Figure 147. Transmit Mailbox States
EMPTY
RQCP=X
TXOK=X
TXRQ=1
TME = 1
PENDING
RQCP=0
TXOK=0
TME = 0
Mailbox has
highest priority
ABRQ=1
EMPTY
Mailbox does not
have highest priority
SCHEDULED
RQCP=0
TXOK=0
RQCP=1
TXOK=0
TME = 1
ABRQ=1
TME = 0
CAN Bus = IDLE
TRANSMIT
Transmit failed * NART
Transmit failed * NART
RQCP=0
TXOK=0
TME = 0
EMPTY
Transmit succeeded
RQCP=1
TXOK=1
TME = 1
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10.10.5.2 Time Triggered Communication
Mode
completely by hardware. The application accesses
the messages stored in the FIFO through the FIFO
output mailbox.
In this mode, the internal counter of the CAN hard-
ware is activated and used to generate the Time
Stamp value stored in the MTSRH and MTSRL
registers. The internal counter is captured on the
sample point of the Start Of Frame bit in both re-
ception and transmission.
Valid Message
A received message is considered as valid when it
has been received correctly according to the CAN
protocol (no error until the last but one bit of the
EOF field) and It passed through the identifier fil-
tering successfully, see Section 10.10.5.4 Identifi-
er Filtering.
10.10.5.3 Reception Handling
For the reception of CAN messages, three
mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and
guarantee data consistency, the FIFO is managed
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CONTROLLER AREA NETWORK (bxCAN)
Figure 148. Receive FIFO states
EMPTY
Valid Message
Received
FMP=0x00
FOVR=0
PENDING_1
FMP=0x01
FOVR=0
Release
Mailbox
Valid Message
Received
Release
Mailbox
RFOM=1
PENDING_2
FMP=0x10
FOVR=0
Valid Message
Received
Release
Mailbox
RFOM=1
PENDING_3
FMP=0x11
FOVR=0
Valid Message
Received
OVERRUN
FMP=0x11
FOVR=1
Release
Mailbox
RFOM=1
Valid Message
Received
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CONTROLLER AREA NETWORK (Cont’d)
FIFO Management
On overrun condition, the FOVR bit is set and an
interrupt is generated if the FOVIE bit in the CIER
register is set.
Starting from the empty state, the first valid mes-
sage received is stored in the FIFO which be-
comes pending_1. The hardware signals the
event setting the FMP[1:0] bits in the CRFR regis-
ter to the value 01b. The message is available in
the FIFO output mailbox. The software reads out
the mailbox content and releases it by setting the
RFOM bit in the CRFR register. The FIFO be-
comes empty again. If a new valid message has
been received in the meantime, the FIFO stays in
pending_1 state and the new message is availa-
ble in the output mailbox.
10.10.5.4 Identifier Filtering
In the CAN protocol the identifier of a message is
not associated with the address of a node but re-
lated to the content of the message. Consequently
a transmitter broadcasts its message to all receiv-
ers. On message reception a receiver node de-
cides - depending on the identifier value - whether
the software needs the message or not. If the mes-
sage is needed, it is copied into the RAM. If not,
the message must be discarded without interven-
tion by the software.
If the application does not release the mailbox, the
next valid message will be stored in the FIFO
which enters pending_2 state (FMP[1:0] = 10b).
The storage process is repeated for the next valid
message putting the FIFO into pending_3 state
(FMP[1:0] = 11b). At this point, the software must
release the output mailbox by setting the RFOM
bit, so that a mailbox is free to store the next valid
message. Otherwise the next valid message re-
ceived will cause a loss of message.
To fulfil this requirement, the bxCAN Controller
provides eight configurable and scalable filter-
banks (0-7) to the application, in order to receive
only the messages the software needs. This hard-
ware filtering saves CPU resources which would
be otherwise needed to perform filtering by soft-
ware. Each filter bank consists of eight 8-bit regis-
ters, CFxR[0:7].
Scalable Width
Refer also to Section 10.10.5.5 Message Storage
To optimize and adapt the filters to the application
needs, each filter bank can be scaled independ-
ently. Depending on the filter scale a filter bank
provides:
Overrun
Once the FIFO is in pending_3 state (i.e. the three
mailboxes are full) the next valid message recep-
tion will lead to an overrun and a message will be
lost. The hardware signals the overrun condition
by setting the FOVR bit in the CRFR register.
Which message is lost depends on the configura-
tion of the FIFO:
– One 32-bit filter for the STDID[10:0], IDE, EX-
TID[17:0] and RTR bits.
– Two 16-bit filters for the STDID[10:0], RTR and
IDE bits.
– Four 8-bit filters for the STDID[10:3] bits. The
other bits are considered as don’t care.
– If the FIFO lock function is disabled (RFLM bit in
the CMCR register cleared) the last message
stored in the FIFO will be overwritten by the new
incoming message. In this case the latest mes-
sages will be always available to the application.
– One 16-bit filter and two 8-bit filters for filtering
the same set of bits as the 16 and 8-bit filters de-
scribed above.
– If the FIFO lock function is enabled (RFLM bit in
the CMCR register set) the most recent message
will be discarded and the software will have the
three oldest messages in the FIFO available.
Refer to Figure 149.
Furthermore, the filters can be configured in mask
mode or in identifier list mode.
Mask mode
Reception Related Interrupts
In mask mode the identifier registers are associat-
ed with mask registers specifying which bits of the
identifier are handled as “must match” or as “don’t
care”.
Once a message has been stored in the FIFO, the
FMP[1:0] bits are updated and an interrupt request
is generated if the FMPIE bit in the CIER register is
set.
Identifier List mode
When the FIFO becomes full (i.e. a third message
is stored) the FULL bit in the CRFR register is set
and an interrupt is generated if the FFIE bit in the
CIER register is set.
In identifier list mode, the mask registers are
used as identifier registers. Thus instead of defin-
ing an identifier and a mask, two identifiers are
specified, doubling the number of single identifi-
ers. All bits of the incoming identifier must match
the bits specified in the filter registers.
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Figure 149. Filter Bank Scale Configuration - Register Organisation
1
Filter Bank Scale Configuration
Filter Bank Scale Config. Bits
One 32-Bit Filter
FSCx = 3
CFxR2
Identifier
Mask/Ident.
CFxR0
CFxR4
CFxR1
CFxR5
CFxR3
CFxR7
CFxR6
STID10:3
STID2:0 RTR IDE EXID17:15
EXID14:7
EXID6:0
Bit Mapping
Two 16-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR2
CFxR1
CFxR3
FSCx = 2
Identifier
Mask/Ident.
CFxR4
CFxR6
CFxR5
CFxR7
Bit Mapping
STID10:3
STID2:0 RTR IDE EXID17:15
One 16-Bit / Two 8-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR2
CFxR1
CFxR3
Identifier
Mask/Ident.
CFxR4
CFxR5
FSCx = 1
Identifier
Mask/Ident.
CFxR6
CFxR7
Four 8-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR1
Identifier
Mask/Ident.
CFxR2
CFxR3
FSCx = 0
Identifier
Mask/Ident.
CFxR4
CFxR5
Identifier
Mask/Ident.
CFxR6
CFxR7
x = filter bank number
1
These bits are located in the CFCR register
Bit Mapping
STID10:3
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Filter Bank Scale and Mode Configuration
The filter banks are configured by means of the
corresponding CFCRx register. To configure a fil-
ter bank it must be deactivated by clearing the
FACT bit in the CFCR register. The filter scale is
configured by means of the FSC[1:0] bits in the
corresponding CFCR register, refer to Figure 149.
The identifier list or identifier mask mode for the
corresponding Mask/Identifier registers is config-
ured by means of the FMCLx and FMCHx bits in
the CFMR register. The FMCLx bit defines the
mode for the two least significant bytes, and the
FMCHx bit the mode for the two most significant
bytes of filter bank x. Examples:
data to the right location the application has to
identify the data by means of the identifier. To
avoid this and to ease the access to the RAM loca-
tions, the CAN controller provides a Filter Match
Index.
This index is stored in the mailbox together with
the message according to the filter priority rules.
Thus each received message has its associated
filter match index.
The Filter Match index can be used in two ways:
– Compare the Filter Match index with a list of ex-
pected values.
– If filter bank 1 is configured as two 16-bit filters,
then the FMCL1 bit defines the mode of the
CF1R2 and CF1R3 registers and the FMCH1 bit
defines the mode of the CF1R6 and CF1R7 reg-
isters.
– Use the Filter Match Index as an index on an ar-
ray to access the data destination location.
For non-masked filters, the software no longer has
to compare the identifier.
If the filter is masked the software reduces the
comparison to the masked bits only.
– If filter bank 2 is configured as four 8-bit filters,
then the FMCL2 bit defines the mode of the
CF2R1 and CF2R3 registers and the FMCH2 bit
defines the mode of the CF2R5 and CF2R7 reg-
isters.
Filter Priority Rules
Depending on the filter combination it may occur
that an identifier passes successfully through sev-
eral filters. In this case the filter match value stored
in the receive mailbox is chosen according to the
following rules:
Note: In 32-bit configuration, the FMCLx and FM-
CHx bits must have the same value to ensure that
the four Mask/Identifier registers are in the same
mode.
– A filter in identifier list mode prevails on an filter
in mask mode.
To filter a group of identifiers, configure the Mask/
Identifier registers in mask mode.
– A filter with full identifier coverage prevails over
filters covering part of the identifier, e.g. 16-bit fil-
ters prevail over 8-bit filters.
To select single identifiers, configure the Mask/
Identifier registers in identifier list mode.
– Filters configured in the same mode and with
identical coverage are prioritized by filter number
and register number. The lower the number the
higher the priority.
Filters not used by the application should be left
deactivated.
Filter Match Index
Once a message has been received in the FIFO it
is available to the application. Typically application
data are copied into RAM locations. To copy the
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CONTROLLER AREA NETWORK (Cont’d)
Figure 150. Filtering Mechanism - example
Message Received
Data
Identifier
Ctrl
Receive FIFO
Identifier
Identifier
Identifier
0
1
2
Message
Stored
Identifier #2 Match
Identifier
n
Identifier
Mask
n+1
n+m
Identifier
Mask
No Match
Found
n: number of single identifiers to receive
m: number of identifier groups to receive
n and m values depend on the configuration of the filters
Message Discarded
The example above shows the filtering principle of
the bxCAN. On reception of a message, the iden-
tifier is compared first with the filters configured in
identifier list mode. If there is a match, the mes-
sage is stored in the associated FIFO and the in-
dex of the matching filter is stored in the Filter
Match Index. As shown in the example, the identi-
fier matches with Identifier #2 thus the message
content and MFMI 2 is stored in the FIFO.
If there is no match, the incoming identifier is then
compared with the filters configured in mask
mode.
If the identifier does not match any of the identifi-
ers configured in the filters, the message is dis-
carded by hardware without disturbing the soft-
ware.
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CONTROLLER AREA NETWORK (Cont’d)
10.10.5.5 Message Storage
Receive Mailbox
The interface between the software and the hard-
ware for the CAN messages is implemented by
means of mailboxes. A mailbox contains all infor-
mation related to a message; identifier, data, con-
trol, status and time stamp information.
When a message has been received, it is available
to the software in the FIFO output mailbox. Once
the software has handled the message (e.g. read
it) the software must release the FIFO output mail-
box by means of the RFOM bit in the CRFR regis-
ter to make the next incoming message available.
The filter match index is stored in the MFMI regis-
ter. The 16-bit time stamp value is stored in the
MTSR[0:1] registers.
Transmit Mailbox
The software sets up the message to be transmit-
ted in an empty transmit mailbox. The status of the
transmission is indicated by hardware in the
MCSR register.
Receive Mailbox Mapping
Offset to Receive
Transmit Mailbox Mapping
Mailbox base ad-
dress (bytes)
Register Name
Offset to Transmit
Mailbox base ad-
dress (bytes)
Register Name
0
1
MFMI
MDLC
0
1
MCSR
2
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSR0
MTSR1
MDLC
3
2
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSR0
MTSR1
4
3
5
4
6
5
7
6
8
7
9
8
10
11
12
13
14
15
9
10
11
12
13
14
15
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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
Figure 151. . CAN Error State Diagram
When TEC or REC > 127
ERROR ACTIVE
ERROR PASSIVE
When TEC and REC < 128,
When 128 * 11 recessive bits occur:
When TEC > 255
BUS OFF
10.10.5.6 Error Management
Bus-Off Recovery
The error management as described in the CAN
protocol is handled entirely by hardware using a
Transmit Error Counter (TECR register) and a Re-
ceive Error Counter (RECR register), which get in-
cremented or decremented according to the error
condition. For detailed information about TEC and
REC management, please refer to the CAN stand-
ard.
The Bus-Off state is reached when TECR is great-
er then 255, this state is indicated by BOFF bit in
CESR register. In Bus-Off state, the bxCAN is no
longer able to transmit and receive messages.
Depending on the ABOM bit in the CMCR register
bxCAN will recover from Bus-Off (become error
active again) either automatically or on software
request. But in both cases the bxCAN has to wait
at least for the recovery sequence specified in the
CAN standard (128 x 11 consecutive recessive
bits monitored on CANRX).
Both of them may be read by software to deter-
mine the stability of the network. Furthermore, the
CAN hardware provides detailed information on
the current error status in CESR register. By
means of CEIER register and ERRIE bit in CIER
register, the software can configure the interrupt
generation on error detection in a very flexible
way.
If ABOM is set, the bxCAN will start the recovering
sequence automatically after it has entered Bus-
Off state.
If ABOM is cleared, the software must initiate the
recovering sequence by requesting bxCAN to en-
ter and to leave initialization mode.
Note: In initialization mode, bxCAN does not mon-
itor the CANRX signal, therefore it cannot com-
plete the recovery sequence. To recover, bxCAN
must be in normal mode.
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CONTROLLER AREA NETWORK (Cont’d)
10.10.5.7 Bit Timing
The resynchronization jump width (RJW) defines
an upper bound to the amount of lengthening or
shortening of the bit segments. It is programmable
between 1 and 4 time quanta.
The bit timing logic monitors the serial bus-line and
performs sampling and adjustment of the sample
point by synchronizing on the start-bit edge and re-
synchronizing on the following edges.
A valid edge is defined as the first transition in a bit
time from dominant to recessive bus level provid-
ed the controller itself does not send a recessive
bit.
Its operation may be explained simply by splitting
nominal bit time into three segments as follows:
– Synchronization segment (SYNC_SEG): a bit
change is expected to occur within this time seg-
ment. It has a fixed length of one time quantum
If a valid edge is detected in BS1 instead of
SYNC_SEG, BS1 is extended by up to RJW so
that the sample point is delayed.
(1 x t
).
CAN
Conversely, if a valid edge is detected in BS2 in-
stead of SYNC_SEG, BS2 is shortened by up to
RJW so that the transmit point is moved earlier.
– Bit segment 1 (BS1): defines the location of the
sample point. It includes the PROP_SEG and
PHASE_SEG1 of the CAN standard. Its duration
is programmable between 1 and 16 time quanta
but may be automatically lengthened to compen-
sate for positive phase drifts due to differences in
the frequency of the various nodes of the net-
work.
As a safeguard against programming errors, the
configuration of the Bit Timing Register (BTR) is
only possible while the device is in STANDBY
mode.
Note: for a detailed description of the CAN bit tim-
ing and resynchronization mechanism, please re-
fer to the ISO 11898 standard.
– Bit segment 2 (BS2): defines the location of the
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programma-
ble between 1 and 8 time quanta but may also be
automatically shortened to compensate for neg-
ative phase drifts.
Figure 152. Bit Timing
NOMINAL BIT TIME
BIT SEGMENT 1 (BS1)
SYNC_SEG
BIT SEGMENT 2 (BS2)
1 x t
t
t
BS2
CAN
BS1
SAMPLE POINT
TRANSMIT POINT
1
BaudRate = -------------------------------------------------
NominalBitTime
NominalBitTime = 1 × tCAN + tBS1 + tBS2
with:
t
t
t
= t
= t
x (TS1[3:0] + 1) ,
x (TS2[2:0] + 1),
x BRP,
BS1
BS2
CAN
CAN
= t
CAN
CPU
CPU
t
= time period of the CPU clock,
BRP = BRP[5:0] + 1 = Baud Rate Prescaler
BRP[5:0] is defined in the CBTR0 Register,
TS1[3:0] and TS2[2:0] are defined in the CBTR1 Register.
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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
Figure 153. CAN Frames
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Data Frame (Standard identifier)
44 + 8 * N
Ack Field
2
Control Field Data Field
CRC Field
16
Arbitration Field
12
ID
6
8 * N
7
CRC
EOF
DLC
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Data Frame (Extended Identifier)
64 + 8 * N
Std Arbitr. Field
12
Ext Arbitr. Field
20
Ack Field
2
Ctrl Field Data Field CRC Field
6
8 * N
16
7
ID
CRC
EOF
DLC
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Remote Frame
44
Ack Field End Of Frame
Control Field
CRC Field
Arbitration Field
12
2
6
16
7
ID
CRC
DLC
Data Frame or
Remote Frame
Inter-Frame Space
or Overload Frame
Notes:
Error Frame
Flag Echo Error Delimiter
• 0 <= N <= 8
Error Flag
• SOF = Start Of Frame
• ID = Identifier
≤ 6
8
6
• RTR = Remote Transmission Request
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
Data Frame or
Remote Frame
Any Frame
Intermission
Inter-Frame Space
Suspend
• DLC = Data Length Code
• CRC = Cyclic Redundancy Code
• Error flag: 6 dominant bits if node is error
active else 6 recessive bits.
• Suspend transmission: applies to error
passive nodes only.
Bus Idle
Transmission
8
3
End Of Frame or
Error Delimiter or
Overload Delimiter
Inter-Frame Space
or Error Frame
Overload Frame
• EOF = End of Frame
Overload Flag Overload Delimiter
• ACK = Acknowledge bit
6
8
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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
10.10.6 Interrupts
bled or disabled by means of the CAN Interrupt
Enable Register (CIER) and CAN Error Interrupt
Enable register (CEIER).
Four interrupt vectors are dedicated to bxCAN.
Each interrupt source can be independently ena-
Figure 154. Event flags and Interrupt Generation
CIER
TRANSMIT
INTERRUPT
TMEIE
RQCP
RQCP
RQCP
TXMB 0
TXMB 1
TXMB 2
&
+
FMPIE
FFIE
&
&
&
FIFO 0
FMP
FULL
FOVR
INTERRUPT
+
+
FOVIE
FMPIE
FFIE
&
&
&
FIFO 1
FMP
FULL
FOVR
INTERRUPT
FOVIE
EWGIE
EPVIE
BOFIE
LECIE
&
EWGF
EPVF
&
&
&
ERRIE
&
+
BOFF
STATUS CHANGE
ERROR
INTERRUPT
LECIEF
+
WKUIE
&
WKUI
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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
– The transmit interrupt can be generated by the
following events:
– The error and status change interrupt can be
generated by the following events:
– Transmit mailbox 0 becomes empty, RQCP0
bit in the CTSR register set.
– Error condition, for more details on error con-
ditions please refer to the CAN Error Status
register (CESR).
– Transmit mailbox 1 becomes empty, RQCP1
bit in the CTSR register set.
– Wake-up condition, SOF monitored on the
CAN Rx signal.
– Transmit mailbox 2 becomes empty, RQCP2
bit in the CTSR register set.
– The FIFO 0 interrupt can be generated by the
10.10.7 Register Access Protection
following events:
Erroneous access to certain configuration regis-
ters can cause the hardware to temporarily disturb
the whole CAN network. Therefore the following
registers can be modified by software only while
the hardware is in initialization mode:
– Reception of a new message, FMP bits in the
CRFR0 register incremented.
– FIFO0 full condition, FULL bit in the CRFR0
register set.
CBTR0, CBTR1, CFCR0, CFCR1, CFMR and
CDGR registers.
– FIFO0 overrun condition, FOVR bit in the
CRFR0 register set.
Although the transmission of incorrect data will not
cause problems at the CAN network level, it can
severely disturb the application. A transmit mail-
box can be only modified by software while it is in
empty state, refer to Figure 147.Transmit Mailbox
States
– The FIFO 1 interrupt can be generated by the
following events:
– Reception of a new message, FMP bits in the
CRFR1 register incremented.
– FIFO1 full condition, FULL bit in the CRFR1
register set.
The filters must be deactivated before their value
can be modified by software. The modification of
the filter configuration (scale or mode) can be
done by software only in initialization mode.
– FIFO1 overrun condition, FOVR bit in the
CRFR1 register set.
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CONTROLLER AREA NETWORK (Cont’d)
10.10.8 Register Description
1: A message will be transmitted only once, inde-
pendently of the transmission result (successful,
error or arbitration lost).
10.10.8.1 Control and Status Registers
CAN MASTER CONTROL REGISTER (CMCR)
Reset Value: 0000 0010 (02h)
Bit 3 = RFLM Receive FIFO Locked Mode
- Read/Set/Clear
0: Receive FIFO not locked on overrun. Once a re-
ceive FIFO is full the next incoming message
will overwrite the previous one.
7
0
TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ
1: Receive FIFO locked against overrun. Once a
receive FIFO is full the next incoming message
will be discarded.
Bit 7 = TTCM Time Triggered Communication
Mode
- Read/Set/Clear
0: Time Triggered Communication mode disabled.
1: Time Triggered Communication mode enabled
Bit 2 = TXFP Transmit FIFO Priority
- Read/Set/Clear
This bit controls the transmission order when sev-
eral mailboxes are pending at the same time.
0: Priority driven by the identifier of the message
1: Priority driven by the request order (chronologi-
cally)
Note: For more information on Time Triggered
Communication mode, please refer to Section
10.10.5.2 Time Triggered Communication Mode.
Bit 6 = ABOM Automatic Bus-Off Management
- Read/Set/Clear
This bit controls the behaviour of the CAN hard-
ware on leaving the Bus-Off state.
0: The Bus-Off state is left on software request,
once 128 x 11 recessive bits have been moni-
tored and the software has first set and cleared
the INRQ bit of the CMCR register.
1: The Bus-Off state is left automatically by hard-
ware once 128 x 11 recessive bits have been
monitored.
Bit 1 = SLEEP Sleep Mode Request
- Read/Set/Clear
This bit is set by software to request the CAN hard-
ware to enter the sleep mode. Sleep mode will be
entered as soon as the current CAN activity (trans-
mission or reception of a CAN frame) has been
completed.
This bit is cleared by software to exit sleep mode.
This bit is cleared by hardware when the AWUM
bit is set and a SOF bit is detected on the CAN Rx
signal.
For detailed information on the Bus-Off state
please refer to Section 10.10.5.6 Error Manage-
ment.
Bit 0 = INRQ Initialization Request
Bit 5 = AWUM Automatic Wake-Up Mode
- Read/Set/Clear
- Read/Set/Clear
The software clears this bit to switch the hardware
into normal mode. Once 11 consecutive recessive
bits have been monitored on the Rx signal the
CAN hardware is synchronized and ready for
transmission and reception. Hardware signals this
event by clearing the INAK bit if the CMSR regis-
ter.
This bit controls the behaviour of the CAN hard-
ware on message reception during sleep mode.
0: The sleep mode is left on software request by
clearing the SLEEP bit of the CMCR register.
1: The sleep mode is left automatically by hard-
ware on CAN message detection. The SLEEP
bit of the CMCR register and the SLAK bit of the
CMSR register are cleared by hardware.
Software sets this bit to request the CAN hardware
to enter initialization mode. Once software has set
the INRQ bit, the CAN hardware waits until the
current CAN activity (transmission or reception) is
completed before entering the initialization mode.
Hardware signals this event by setting the INAK bit
in the CMSR register.
Bit 4 = NART No Automatic Retransmission
- Read/Set/Clear
0: The CAN hardware will automatically retransmit
the message until it has been successfully
transmitted according to the CAN standard.
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CONTROLLER AREA NETWORK (Cont’d)
CAN MASTER STATUS REGISTER (CMSR)
Reset Value: 0000 0010 (02h)
cleared. Please refer to the AWUM bit of the
CMCR register description for detailed information
for clearing SLEEP bit.
7
0
Bit 0 = INAK Initialization Acknowledge
- Read
0
0
REC TRAN WKUI ERRI SLAK INAK
This bit is set by hardware and indicates to the
software that the CAN hardware is now in initiali-
zation mode. This bit acknowledges the initializa-
tion request from the software (set INRQ bit in
CMCR register).
Note: To clear a bit of this register the software
must write this bit with a one.
This bit is cleared by hardware when the CAN
hardware has left the initialization mode and is
now synchronized on the CAN bus. To be syn-
chronized the hardware has to monitor a se-
quence of 11 consecutive recessive bits on the
CAN RX signal.
Bit 7:4 = Reserved. Forced to 0 by hardware.
Bit 5 = REC Receive
- Read
The CAN hardware is currently receiver.
CAN TRANSMIT STATUS REGISTER (CTSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 4 = TRAN Transmit
- Read
The CAN hardware is currently transmitter.
7
0
0
Bit 3 = WKUI Wake-Up Interrupt
- Read/Clear
TXOK2 TXOK1 TXOK0
0
RQCP2 RQCP1 RQCP0
This bit is set by hardware to signal that a SOF bit
has been detected while the CAN hardware was in
sleep mode. Setting this bit generates a status
change interrupt if the WKUIE bit in the CIER reg-
ister is set.
Note: To clear a bit of this register the software
must write this bit with a one.
Bit 7 = Reserved. Forced to 0 by hardware.
This bit is cleared by software.
Bit 2 = ERRI Error Interrupt
Bit 6 = TXOK2 Transmission OK for mailbox 2
- Read
This bit is set by hardware when the transmission
request on mailbox 2 has been completed suc-
cessfully. Please refer to Figure 147.
- Read/Clear
This bit is set by hardware when a bit of the CESR
has been set on error detection and the corre-
sponding interrupt in the CEIER is enabled. Set-
ting this bit generates a status change interrupt if
the ERRIE bit in the CIER register is set.
This bit is cleared by hardware when mailbox 2 is
requested for transmission or when the software
clears the RQCP2 bit.
This bit is cleared by software.
Bit 1 = SLAK Sleep Acknowledge
- Read
This bit is set by hardware and indicates to the
software that the CAN hardware is now in sleep
mode. This bit acknowledges the sleep mode re-
quest from the software (set SLEEP bit in CMCR
register).
Bit 5 = TXOK1 Transmission OK for mailbox 1
- Read
This bit is set by hardware when the transmission
request on mailbox 1 has been completed suc-
cessfully. Please refer to Figure 147.
This bit is cleared by hardware when mailbox 1 is
requested for transmission or when the software
clears the RQCP1 bit.
This bit is cleared by hardware when the CAN
hardware has left sleep mode. Sleep mode is left
when the SLEEP bit in the CMCR register is
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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
Bit 4 = TXOK0 Transmission OK for mailbox 0
- Read
This bit is set by hardware when the transmission
request on mailbox 0 has been completed suc-
cessfully. Please refer to Figure 147.
Bit 6 = LOW1 Lowest Priority Flag for Mailbox 1
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
1 has the lowest priority.
This bit is cleared by hardware when mailbox 0 is
requested for transmission or when the software
clears the RQCP0 bit.
Bit 5 = LOW0 Lowest Priority Flag for Mailbox 0
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
0 has the lowest priority.
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2 = RQCP2 Request Completed for Mailbox 2
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 2 has been completed. The re-
quest could be a transmit or an abort request.
Note: These bits are set to zero when only one
mailbox is pending.
Bit 4 = TME2 Transmit Mailbox 2 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 2.
This bit is cleared by software.
Bit 1 = RQCP1 Request Completed for Mailbox 1
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 1 has been completed. The re-
quest could be a transmit or an abort request.
Bit 3 = TME1 Transmit Mailbox 1 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 1.
This bit is cleared by software.
Bit 2 = TME0 Transmit Mailbox 0 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 0.
Bit 0 = RQCP0 Request Completed for Mailbox 0
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 0 has been completed. The re-
quest could be a transmit or an abort request.
Bit 1:0 = CODE[1:0] Mailbox Code
- Read
This bit is cleared by software.
In case at least one transmit mailbox is free, the
code value is equal to the number of the next
transmit mailbox free.
CAN TRANSMIT PRIORITY REGISTER (CTPR)
All bits of this register are read only.
In case all transmit mailboxes are pending, the
code value is equal to the number of the transmit
mailbox with the lowest priority.
Reset Value: 0000 0000 (00h)
7
0
LOW2
LOW1
LOW0
TME2
TME1
TME0 CODE1 CODE0
Bit 7 = LOW2 Lowest Priority Flag for Mailbox 2
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
2 has the lowest priority.
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CONTROLLER AREA NETWORK (bxCAN)
CAN INTERRUPT ENABLE REGISTER (CIER)
CONTROLLER AREA NETWORK (Cont’d)
CAN RECEIVE FIFO REGISTERS (CRFRx)
Read / Write
Reset Value: 0000 0000 (00h)
All bits of this register are set and cleared by soft-
ware.
7
0
Read / Write
Reset Value: 0000 0000 (00h)
0
0
RFOM FOVR FULL
0
FMP1 FMP0
7
0
Note: To clear a bit in this register, software must
write a “1” to the bit.
WKUIE FOVIE1 FFIE1 FMPIE1 FOVIE0 FFIE0 FMPIE0 TMEIE
Bit 7 = WKUIE Wake-Up Interrupt Enable
0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = RFOM Release FIFO Output Mailbox
- Read/Set
Bit 6 = FOVIE1 FIFO Overrun Interrupt Enable
0: No interrupt when FOVR is set.
Set by software to release the output mailbox of
the FIFO. The output mailbox can only be released
when at least one message is pending in the FIFO.
Setting this bit when the FIFO is empty has no ef-
fect. If at least two messages are pending in the
FIFO, the software has to release the output mail-
box to access the next message.
1: Interrupt generation when FOVR is set.
Bit 5 = FFIE1 FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Cleared by hardware when the output mailbox has
been released.
Bit 4 = FMPIE1 FIFO Message Pending Interrupt
Enable
0: No interrupt on FMP[1:0] bits transition from 00b
to 01b.
Bit 4 = FOVR FIFO Overrun
- Read/Clear
This bit is set by hardware when a new message
has been received and passed the filter while the
FIFO was full.
1: Interrupt generated on FMP[1:0] bits transition
from 00b to 01b.
This bit is cleared by software.
Bit 3 = FOVIE0 FIFO Overrun Interrupt Enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
Bit 3 = FULL FIFO Full
- Read/Clear
Set by hardware when three messages are stored
in the FIFO.
This bit is cleared by software.
Bit 2 = FFIE0 FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 1 = FMPIE0 FIFO Message Pending Interrupt
Enable
Bit 1:0 = FMP[1:0] FIFO Message Pending
- Read
These bits indicate how many messages are
pending in the receive FIFO.
0: No interrupt on FMP[1:0] bits transition from 00b
to 01b.
1: Interrupt generated on FMP[1:0] bits transition
from 00b to 01b.
FMP is increased each time the hardware stores a
new message in to the FIFO. FMP is decreased
each time the software releases the output mail-
box by setting the RFOM bit.
Bit 0 = TMEIE Transmit Mailbox Empty Interrupt
Enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
Note: refer to Standard Interrupts Section.
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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
CAN ERROR STATUS REGISTER (CESR)
Bit 1 = EWGF Error Warning Flag
- Read
This bit is set by hardware when the warning limit
has been reached. Receive Error Counter or
Transmit Error Counter greater than 96.
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
LEC2 LEC1 LEC0
0
BOFF EPVF EWGF
CAN ERROR INTERRUPT ENABLE REGISTER
(CEIER)
Bit 7 = Reserved. Forced to 0 by hardware.
All bits of this register are set and clear by soft-
ware.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 6:4 = LEC[2:0] Last Error Code
- Read/Set/Clear
This field holds a code which indicates the type of
the last error detected on the CAN bus. If a mes-
sage has been transferred (reception or transmis-
sion) without error, this field will be cleared to ‘0’.
The code 7 is unused and may be written by the
CPU to check for update
7
0
ERRIE
0
0
LECIE
0
BOFIE EPVIE EWGIE
Bit 7 = ERRIE Error Interrupt Enable
0: No interrupt will be generated when an error
condition is pending in the CESR.
Table 63. LEC Error Types
1: An interrupt will be generated when an error
condition is pending in the CESR.
Code
Error Type
0
1
2
3
4
5
6
7
No Error
Stuff Error
Form Error
Bit 6:5 = Reserved. Forced to 0 by hardware.
Acknowledgment Error
Bit recessive Error
Bit dominant Error
CRC Error
Bit 4 = LECIE Last Error Code Interrupt Enable
0: ERRI bit will not be set when the error code in
LEC[2:0] is set by hardware on error detection.
1: ERRI bit will be set when the error code in
LEC[2:0] is set by hardware on error detection.
Set by software
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2 = BOFF Bus-Off Flag
- Read
Bit 2 = BOFIE Bus-Off Interrupt Enable
This bit is set by hardware when it enters the bus-
off state. The bus-off state is entered on TECR
overrun, TEC greater than 255, refer to Section
10.10.5.6 on page 337.
0: ERRI bit will not be set when BOFF is set.
1: ERRI bit will be set when BOFF is set.
Bit 1 = EPVIE Error Passive Interrupt Enable
0: ERRI bit will not be set when EPVF is set.
1: ERRI bit will be set when EPVF is set.
Bit 1 = EPVF Error Passive Flag
- Read
This bit is set by hardware when the Error Passive
limit has been reached (Receive Error Counter or
Transmit Error Counter greater than 127).
Bit 0 = EWGIE Error Warning Interrupt Enable
0: ERRI bit will not be set when EWGF is set.
1: ERRI bit will be set when EWGF is set.
Note: refer to Standard Interrupts Section.
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CONTROLLER AREA NETWORK (bxCAN)
CAN DIAGNOSIS REGISTER (CDGR)
CONTROLLER AREA NETWORK (Cont’d)
TRANSMIT ERROR COUNTER REG. (TECR)
Read Only
All bits of this register are set and clear by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Reset Value: 00h
7
0
7
0
0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
0
0
0
RX
SAMP SILM LBKM
TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
fault confinement mechanism of the CAN protocol.
Bit 3 = RX CAN Rx Signal
- Read
Monitors the actual value of the CAN_RX Pin.
RECEIVE ERROR COUNTER REG. (RECR)
Page: 00h — Read Only
Bit 2 = SAMP Last Sample Point
- Read
The value of the last sample point.
Reset Value: 00h
7
0
Bit 1 = SILM Silent Mode
- Read/Set/Clear
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
0: Normal operation
1: Silent Mode
REC[7:0] is the Receive Error Counter implement-
ing part of the fault confinement mechanism of the
CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on the error condition as defined by the CAN stand-
ard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.
Bit 0 = LBKM Loop Back Mode
- Read/Set/Clear
0: Loop Back Mode disabled
1: Loop Back Mode enabled
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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
CAN BIT TIMING REGISTER 0 (CBTR0)
CAN FILTER PAGE SELECT REGISTER
(CFPSR)
This register can only be accessed by the software
when the CAN hardware is in configuration mode.
Read / Write
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
0
0
0
0
FPS2 FPS1 FPS0
Bit 7:6 SJW[1:0] Resynchronization Jump Width
These bits define the maximum number of time
quanta the CAN hardware is allowed to lengthen
or shorten a bit to perform the resynchronization.
Bit 7:3 = Reserved. Forced to 0 by hardware.
Bit 2:0 = FPS[2:0] Filter Page Select
- Read/Write
This register contains the filter page number avail-
able in page 54.
Bit 5:0 BRP[5:0] Baud Rate Prescaler
These bits define the length of a time quantum.
tq = (BRP+1)/fsys
Table 64. Filter Page Selection
For more information on bit timing, please refer to
Section 10.10.5.7 Bit Timing.
FPS[2:0]
Filter Page Selected in Page 54
Acceptance Filter 0:1
Acceptance Filter 2:3
Acceptance Filter 4:5
Acceptance Filter 6:7
Filter Configuration
0
1
2
3
4
5
6
7
CAN BIT TIMING REGISTER 1 (CBTR1)
Read / Write
Reset Value: 0001 0011 (23h)
7
0
0
Filter Configuration
TS22 TS21 TS20 TS13 TS12 TS11 TS10
Filter Configuration
Filter Configuration
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6:4 TS2[2:0] Time Segment 2
These bits define the number of time quanta in
Time Segment 2.
t
= t
x (TS2[2:0] + 1),
BS2
CAN
Bit 3:0 TS1[3:0] Time Segment 1
These bits define the number of time quanta in
Time Segment 1
t
= t
x (TS1[3:0] + 1)
BS1
CAN
.For more information on bit timing, please refer to
Section 10.10.5.7 Bit Timing.
348/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
10.10.8.2 Mailbox Registers
Bit 3 = TXOK Transmission OK
- Read/Clear
The hardware updates this bit after each transmis-
sion attempt.
This chapter describes the registers of the transmit
and receive mailboxes. Refer to Section 10.10.5.5
Message Storage for detailed register mapping.
0: The previous transmission failed
1: The previous transmission was successful
Transmit and receive mailboxes have the same
registers except:
Note: This bit has the same value as the corre-
sponding TXOKx bit in the CTSR register.
– MCSR register in a transmit mailbox is replaced
by MFMI register in a receive mailbox.
– A receive mailbox is always write protected.
Bit 2 = RQCP Request Completed
- Read/Clear
Set by hardware when the last request (transmit or
abort) has been performed.
– A transmit mailbox is write enable only while
empty, corresponding TME bit in the CTPR reg-
ister set.
Cleared by software writing a “1” or by hardware
on transmission request.
MAILBOX CONTROL STATUS REGISTER
(MCSR)
Note: This bit has the same value as the corre-
sponding RQCPx bit of the CTSR register.
Read / Write
Reset Value: 0000 0000 (00h)
Clearing this bit clears all the status bits (TX-
OK, ALST and TERR) in the MCSR register and
the RQCP and TXOK bits in the CTSR register.
7
0
0
0
TERR ALST TXOK RQCP ABRQ TXRQ
Bit 1 = ABRQ Abort Request for Mailbox
- Read/Set
Set by software to abort the transmission request
for the corresponding mailbox.
Bit 7:6 = Reserved. Forced to 0 by hardware.
Cleared by hardware when the mailbox becomes
empty.
Bit 5 = TERR Transmission Error
- Read/Clear
This bit is updated by hardware after each trans-
mission attempt.
Setting this bit has no effect when the mailbox is
not pending for transmission.
0: The previous transmission was successful
1: The previous transmission failed due to an error
Bit 0 = TXRQ Transmit Mailbox Request
- Read/Set
Set by software to request the transmission for the
corresponding mailbox.
Bit 4 = ALST Arbitration Lost
- Read/Clear
This bit is updated by hardware after each trans-
mission attempt.
Cleared by hardware when the mailbox becomes
empty.
0: The previous transmission was successful
1: The previous transmission failed due to an arbi-
tration lost
Note: This register is implemented only in transmit
mailboxes. In receive mailboxes, the MFMI regis-
ter is mapped at this location.
349/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
MAILBOX FILTER MATCH INDEX (MFMI)
This register is read only.
MIDR1
Reset Value: 0000 0000 (00h)
7
0
7
0
STID5
STID4
STID3
STID2
STID1
STID0 EXID17 EXID16
FMI7
FMI6
FMI5
FMI4
FMI3
FMI2
FMI1
FMI0
Bit 7:0 = FMI[7:0] Filter Match Index
Bit 7:2 = STID[5:0] Standard Identifier
6 least significant bits of the standard part of the
identifier.
This register contains the index of the filter the
message stored in the mailbox passed through.
For more details on identifier filtering please refer
to Section 10.10.5.4 - Filter Match Index para-
graph.
Bit 1:0 = EXID[17:16] Extended Identifier
2 most significant bits of the extended part of the
identifier.
Note: This register is implemented only in receive
mailboxes. In transmit mailboxes, the MCSR reg-
ister is mapped at this location.
MIDR2
7
0
MAILBOX IDENTIFIER REGISTERS
(MIDR[3:0])
EXID15 EXID14 EXID13 EXID12 EXID11 EXID10 EXID9
EXID8
Read / Write
Reset Value: xxxx xxxx (xxh)
MIDR0
Bit 7:0 = EXID[15:8] Extended Identifier
7
0
Bit 15 to 8 of the extended part of the identifier.
0
IDE
RTR
STID10 STID9
STID8
STID7
STID6
MIDR3
7
0
Bit 7 = Reserved. Forced to 0 by hardware.
EXID7
EXID6
EXID5
EXID4
EXID3
EXID2
EXID1
EXID0
Bit 6 = IDE Extended Identifier
This bit defines the identifier type of message in
the mailbox.
Bit 7:1 = EXID[6:0] Extended Identifier
6 least significant bits of the extended part of the
identifier.
0: Standard identifier.
1: Extended identifier.
Bit 5 = RTR Remote Transmission Request
0: Data frame
1: Remote frame
Bit 4:0 = STID[10:6] Standard Identifier
5 most significant bits of the standard part of the
identifier.
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9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
MAILBOX DATA LENGTH CONTROL REGIS-
TER (MDLC)
MAILBOX TIME STAMP LOW REGISTER
(MTSLR)
All bits of this register is write protected when the
mailbox is not in empty state.
Read / Write
Reset Value: xxxx xxxx (xxh)
Read / Write
Reset Value: xxxx xxxx (xxh)
7
0
TIME7 TIME6 TIME5 TIME4 TIME3 TIME2 TIME1 TIME0
7
0
TGT
0
0
0
DLC3
DLC2
DLC1
DLC0
Bit 7:0 = TIME[7:0] Message Time Stamp Low
This fields contains the low byte of the 16-bit timer
value captured at the SOF detection.
Bit 7 = TGT Transmit Global Time
This bit is active only when the hardware is in the
Time Trigger Communication mode, TTCM bit of
the CCR register is set.
0: MTSRH and MTSRL registers are not sent.
1: MTSRH and MTSRL registers are sent in the
last two data bytes of the message.
MAILBOX TIME STAMP HIGH REGISTER
(MTSHR)
Read / Write
Reset Value: xxxx xxxx (xxh)
7
0
6:4 = Reserved. Forced to 0 by hardware.
TIME15 TIME14 TIME13 TIME12 TIME11 TIME10 TIME9 TIME8
Bit 3:0 = DLC[3:0] Data Length Code
This field defines the number of data bytes a data
frame contains or a remote frame request.
Bit 7:0 = TIME[15:8] Message Time Stamp High
This field contains the high byte of the 16-bit timer
value captured at the SOF detection.
MAILBOX DATA REGISTERS (MDAR[7:0])
All bits of this register are write protected when the
mailbox is not in empty state.
Read / Write
Reset Value: xxxx xxxx (xxh)
7
0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Bit 7:0 = DATA[7:0] Data
A data byte of the message. A message can con-
tain from 0 to 8 data bytes.
351/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
10.10.8.3 CAN Filter Registers
CAN FILTER CONFIGURATION REG.1 (CFCR1)
CAN FILTER CONFIGURATION REG.0 (CFCR0)
All bits of this register are set and cleared by soft-
ware.
All bits of this register are set and cleared by soft-
Read / Write
Reset Value: 0000 0000 (00h)
ware.
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FFA3 FSC31 FSC30 FACT3 FFA2 FSC21 FSC20 FACT2
FFA1 FSC11 FSC10 FACT1 FFA0 FSC01 FSC00 FACT0
Bit 7 = FFA3 Filter FIFO Assignment for Filter 3
The message passing through this filter will be
stored in the specified FIFO.
Note: To modify the FFAx and FSCx bits, the bx-
CAN must be in INIT mode.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 7 = FFA1 Filter FIFO Assignment for Filter 1
The message passing through this filter will be
stored in the specified FIFO.
Bit 6:5 = FSC3[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
3.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 4 = FACT3 Filter Active
Bit 6:5 = FSC1[1:0] Filter Scale Configuration
The software sets this bit to activate filter 3. To
modify the Filter 3 registers (CF3R[0:7]) the
FACT3 bit must be cleared.
These bits define the scale configuration of Filter
1.
0: Filter 3 is not active
1: Filter 3 is active
Bit 4 = FACT1 Filter Active
The software sets this bit to activate Filter 1. To
modify the Filter 1 registers (CF1R[7:0]), the
FACT1 bit must be cleared.
Bit 3 = FFA2 Filter FIFO Assignment for Filter 2
The message passing through this filter will be
stored in the specified FIFO.
0: Filter 1 is not active
1: Filter 1 is active
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 3 = FFA0 Filter FIFO Assignment for Filter 0
The message passing through this filter will be
stored in the specified FIFO.
Bit 2:1 = FSC2[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
2.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 0 = FACT2 Filter Active
Bit 2:1 = FSC0[1:0] Filter Scale Configuration
The software sets this bit to activate Filter 2. To
modify the Filter 2 registers (CF2R[0:7]), the
FACT2 bit must be cleared.
These bits define the scale configuration of Filter
0.
0: Filter 2 is not active
1: Filter 2 is active
Bit 0 = FACT0 Filter Active
The software sets this bit to activate Filter 0. To
modify the Filter 0 registers (CF0R[0:7]), the
FACT0 bit must be cleared.
0: Filter 0 is not active
1: Filter 0 is active
352/426
9
CONTROLLER AREA NETWORK (bxCAN)
CAN FILTER CONFIGURATION REG.3 (CFCR3)
CONTROLLER AREA NETWORK (Cont’d)
CAN FILTER CONFIGURATION REG.2 (CFCR2)
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FFA5 FSC51 FSC50 FACT5 FFA4 FSC41 FSC40 FACT4
FFA7 FSC71 FSC70 FACT7 FFA6 FSC61 FSC60 FACT6
Note: To modify FFAx and FSCx bits bxCAN must
be in INIT mode.
Bit 7 = FFA7 Filter FIFO Assignment for Filter 7
The message passing through this filter will be
stored in the specified FIFO.
Bit 7 = FFA5 Filter FIFO Assignment for Filter 5
The message passing through this filter will be
stored in the specified FIFO.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
Bit 6:5 = FSC7[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
7.
Bit 6:5 = FSC5[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
5.
Bit 4 = FACT7 Filter Active
The software sets this bit to activate Filter 7. To
modify the Filter 7 registers (CF7R[7:0]), the
FACT7 bit must be cleared.
Bit 4 = FACT5 Filter Active
The software sets this bit to activate Filter 5. To
modify the filter 5 registers (CF5R[7:0]), the
FACT5 bit must be cleared.
0: Filter 5 is not active
1: Filter 5 is active
0: Filter 7 is not active.
1: Filter 7 is active.
Bit 3 = FFA6 Filter FIFO Assignment for Filter 6
This bit allows the software to define whether the
message passing through this filter will be as-
signed to the receive FIFO0 or FIFO1.
0: Filter assigned to FIFO 0
Bit 3 = FFA4 Filter FIFO Assignment for Filter 4
The message passing through this filter will be
stored in the specified FIFO.
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1
1: Filter assigned to FIFO 1
Bit 2:1 = FSC6[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
6.
Bit 2:1 = FSC4[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
4.
Bit 0 = FACT6 Filter Active
The software sets this bit to activate Filter 6. To
modify the Filter 6 registers (CF6R[7:0]), the
FACT6 bit must be cleared.
Bit 0 = FACT4 Filter Active
The software sets this bit to activate filter 4. To
modify the Filter 4 registers (CF4R[7:0]), the
FACT4 bit must be cleared).
0: Filter 6 is not active
1: Filter 6 is active
0: Filter 4 is not active
1: Filter 4 is active
353/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
CAN FILTER MODE REG.1 (CFMR1)
Bit 1 = FMH4 Filter Mode High
Mode of the high registers of filter 4.
0: High registers are in mask mode.
1: High registers are in identifier list mode.
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Bit 0 = FML4 Filter Mode Low
7
0
Mode of the low registers of filter 4.
0: Low registers are in mask mode.
1: Low registers are in identifier list mode.
FMH7 FML7 FMH6 FML6 FMH5 FML5 FMH4 FML4
Note: Please refer to Figure 149.Filter Bank Scale
Configuration - Register Organisation
CAN FILTER MODE REG.0 (CFMR0)
All bits of this register are set and cleared by soft-
ware.
Bit 7 = FMH7 Filter Mode High
Read / Write
Mode of the high registers of Filter 7.
0: High registers are in mask mode.
1: High registers are in identifier list mode.
Reset Value: 0000 0000 (00h)
7
0
FMH3 FML3 FMH2 FML2 FMH1 FML1 FMH0 FML0
Bit 6 = FML7 Filter Mode Low
Mode of the low registers of Filter 7.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 7 = FMH3 Filter Mode High
Mode of the high registers of Filter 3.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 5 = FMH6 Filter Mode High
Mode of the high registers of Filter 6.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 6 = FML3 Filter Mode Low
Mode of the low registers of Filter 3.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 4 = FML6 Filter Mode Low
Mode of the low registers of Filter 6.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 5 = FMH2 Filter Mode High
Mode of the high registers of Filter 2.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 3 = FMH5 Filter Mode High
Mode of the high registers of filter 5.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 4 = FML2 Filter Mode Low
Mode of the low registers of Filter 2.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 2 = FML5 Filter Mode Low
Mode of the low registers of Filter 5.
0: Low registers are in mask mode
1: Low registers are in identifier list mode.
Bit 3 = FMH1 Filter Mode High
Mode of the high registers of Filter 1.
0: High registers are in mask mode
1: High registers are in identifier list mode
354/426
9
CONTROLLER AREA NETWORK (bxCAN)
FILTER x REGISTER[7:0] (CFxR[7:0])
CONTROLLER AREA NETWORK (Cont’d)
Bit 2 = FML1 Filter Mode Low
Mode of the low registers of filter 1.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Read / Write
Reset Value: xxxx xxxx (xxh)
7
0
Bit 1 = FMH0 Filter Mode High
FB7
FB6
FB5
FB4
FB3
FB2
FB1
FB0
Mode of the high registers of filter 0.
0: High registers are in mask mode
1: High registers are in identifier list mode
In all configurations:
Bit 7:0 = FB[7:0] Filter Bits
Identifier
Bit 0 = FML0 Filter Mode Low
Each bit of the register specifies the level of the
corresponding bit of the expected identifier.
0: Dominant bit is expected
Mode of the low registers of filter 0.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
1: Recessive bit is expected
Mask
Each bit of the register specifies whether the bit of
the associated identifier register must match with
the corresponding bit of the expected identifier or
not.
0: Don’t care, the bit is not used for the comparison
1: Must match, the bit of the incoming identifier
must have the same level has specified in the
corresponding identifier register of the filter.
Note: Each filter x is composed of 8 registers,
CFxR[7:0]. Depending on the scale and mode
configuration of the filter the function of each reg-
ister can differ. For the filter mapping, functions
description and mask registers association, refer
to Section 10.10.5.4Identifier Filtering.
A Mask/Identifier register in mask mode has the
same bit mapping as in identifier list mode.
Note: To modify these registers, the correspond-
ing FACT bit in the CFCR register must be
cleared.
355/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
10.10.8.4 Page Mapping for CAN 0 / CAN 1
PAGE 48 / 36
CMCR
PAGE 49 / 37
MFMI
PAGE 50 / 38
MFMI
PAGE 51 / 39
MCSR
PAGE 52 / 40
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
MCSR
MDLC
MIDR0
MIDR1
CMSR
MDLC
MDLC
MDLC
CTSR
MIDR0
MIDR0
MIDR0
CTPR
MIDR1
MIDR1
MIDR1
CRFR0
CRFR1
CIER
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
CESR
CEIER
TEC
REC
MDAR3
MDAR4
MDAR5
MDAR3
MDAR4
MDAR5
MDAR3
MDAR4
MDAR5
MDAR3
MDAR4
MDAR5
CDGR
CBTR0
CBTR1
MDAR6
MDAR7
MDAR6
MDAR7
MDAR6
MDAR7
MDAR6
MDAR7
Reserved
CFPSR
MTSLR
MTSLR
MTSHR
MTSLR
MTSHR
MTSLR
MTSHR
MTSHR
Control/Status
PAGE 53 / 41
Receive FIFO 0
PAGE 54/4 42/4
Receive FIFO 1
PAGE 54/0 42/0
Tx Mailbox 0
Tx Mailbox 1
PAGE 54/2 42/2
PAGE 54/1 42/1
CF4R0
CF4R1
CF4R2
CF4R3
CF2R0
CF2R1
CF2R2
CF2R3
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
MCSR
MDLC
MIDR0
MIDR1
CF0R0
CF0R1
CF0R2
CF0R3
CFMR0
CFMR1
CFCR0
CFCR1
CF4R4
CF4R5
CF4R6
CF4R7
CF2R4
CF2R5
CF2R6
CF2R7
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
CF0R4
CF0R5
CF0R6
CF0R7
CF1R0
CF1R1
CF1R2
CF1R3
CFCR2
CFCR3
Reserved
Reserved
Reserved
CF5R0
CF5R1
CF5R2
CF5R3
CF3R0
CF3R1
CF3R2
CF3R3
MDAR3
MDAR4
MDAR5
Reserved
Reserved
Reserved
MDAR6
MDAR7
Reserved
Reserved
CF5R4
CF5R5
CF3R4
CF3R5
CF1R4
CF1R5
CF1R6
CF5R6
MTSLR
MTSHR
Reserved
Reserved
CF3R6
CF5R7
CF3R7
CF1R7
Tx Mailbox 2
Acceptance Filter 4:5
Filter Configuration
Acceptance Filter 0:1
Acceptance Filter 2:3
356/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
Page Mapping for CAN0 /CAN1 (Cont’d)
PAGE 54/3 42/3
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
CF6R0
CF6R1
CF6R2
CF6R3
CF6R4
CF6R5
CF6R6
CF6R7
CF7R0
CF7R1
CF7R2
CF7R3
CF7R4
CF7R5
CF7R6
CF7R7
Acceptance Filter 6:7
357/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
Table 65. bxCAN Control & Status Page - Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
CMCR
TTCM
0
ABOM
0
AWUM
0
NART
0
RFLM
0
TXFP
0
SLEEP
1
INRQ
0
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Reset Value
CMSR
REC
0
TRAN
0
WKUI
0
ERRI
0
SLAK
0
INAK
0
Reset Value
0
0
CTSR
TXOK2
0
TXOK1
0
TXOK0
0
RQCP2
0
RQCP1
0
RQCP0
0
Reset Value
0
0
CTPR
LOW2
0
LOW1
0
LOW0
0
TME2
1
TME1
1
TME0
1
CODE1
0
CODE0
0
Reset Value
CRFR0
RFOM
0
FOVR
0
FULL
0
FMP1
0
FMP0
0
Reset Value
0
0
0
CRFR1
RFOM
0
FOVR
0
FULL
0
FMP1
0
FMP0
0
Reset Value
0
0
0
CIER
WKUIE
0
FOVIE1
0
FFIE1
0
FMPIE1
0
FOVIE0
0
FFIE0
0
FMPIE0
0
TMEIE
0
Reset Value
CESR
LEC2
0
LEC1
0
LEC0
0
BOFF
0
EPVF
0
EWGF
0
Reset Value
0
0
CEIER
LECIE
0
BOFIE
0
EPVIE
0
EWGIE
0
ERRIE
0
Reset Value
0
0
0
TECR
TEC7
0
TEC6
0
TEC5
0
TEC4
0
TEC3
0
TEC2
0
TEC1
0
TEC0
0
Reset Value
RECR
REC7
0
REC6
0
REC5
0
REC4
0
REC3
0
REC2
0
REC1
0
REC0
0
Reset Value
CDGR
RX
0
SAMP
0
SILM
0
LBKM
0
Reset Value
0
0
0
0
CBTR0
SJW1
0
SJW0
0
BRP5
0
BRP4
0
BRP3
0
BRP2
0
BRP1
0
BRP0
0
Reset Value
CBTR1
TS22
0
TS21
1
TS20
0
TS13
0
TS12
0
TS11
1
TS10
1
Reset Value
0
X
0
Reserved
X
0
X
0
X
0
X
0
X
X
X
CFPSR
FPS2
0
FPS1
0
FPS0
0
Reset Value
358/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
Table 66. bxCAN Mailbox Pages - Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
F0h
MFMI
FMI7
0
FMI6
0
FMI5
0
FMI4
0
FMI3
0
FMI2
0
FMI1
0
FMI0
0
Receive Reset Value
F0h MCSR
TERR
0
ALST
0
TXOK
0
RQCP
0
ABRQ
1
TXRQ
0
Transmit Reset Value
0
0
MDLC
F1h
TGT
x
DLC3
x
DLC2
x
DLC1
x
DLC0
x
Reset Value
x
x
x
MIDR0
F2h
IDE
x
RTR
x
STID10
x
STID9
x
STID8
x
STID7
x
STID6
x
Reset Value
x
MIDR1
F3h
STID5
x
STID4
x
STID3
x
STID2
x
STID1
x
STID0
x
EXID17
x
EXID16
x
Reset Value
MIDR2
F4h
EXID15
x
EXID14
x
EXID13
x
EXID12
x
EXID11
x
EXID10
x
EXID9
x
EXID8
x
Reset Value
MIDR3
F5h
EXID7
x
EXID6
x
EXID5
x
EXID4
x
EXID3
x
EXID2
x
EXID1
x
EXID0
x
Reset Value
MDAR[0:7] MDAR7
MDAR6
x
MDAR5
x
MDAR4
x
MDAR3
x
MDAR2
x
MDAR1
x
MDAR0
x
F6h:FDh
FEh
Reset Value
x
MTSLR
TIME7
x
TIME6
x
TIME5
x
TIME4
x
TIME3
x
TIME2
x
TIME1
x
TIME0
x
Reset Value
MTSHR
TIME15
x
TIME14
x
TIME13
x
TIME12
x
TIME11
x
TIME10
x
TIME9
x
TIME8
x
FFh
Reset Value
Table 67. bxCAN Filter Configuration Page - Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
CFMR0
FMH3
0
FML3
0
FMH2
0
FML2
0
FMH1
0
FML1
0
FMH0
0
FML0
0
F0h
F1h
F2h
F3h
F4h
F5h
Reset Value
CFMR1
FMH7
0
FML7
0
FMH6
0
FML6
0
FMH5
0
FML5
0
FMH4
0
FML4
0
Reset Value
CFCR0
FFA1
0
FSC11
0
FSC10
0
FACT1
0
FFA0
0
FSC01
0
FSC00
0
FACT0
0
Reset Value
CFCR1
FFA3
0
FSC31
0
FSC30
0
FACT3
0
FFA2
0
FSC21
0
FSC20
0
FACT2
0
Reset Value
CFCR2
FFA5
0
FSC51
0
FSC50
0
FACT5
0
FFA4
0
FSC41
0
FSC40
0
FACT4
0
Reset Value
CFCR3
FFA7
0
FSC71
0
FSC70
0
FACT7
0
FFA6
0
FSC61
0
FSC60
0
FACT6
0
Reset Value
359/426
9
CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
10.10.9 IMPORTANT NOTES ON CAN
Refer to Section 13.1.4 on page 412 and Section
13.1.6 on page 413.
360/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
10.11 10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
10.11.1 Main Characteristics
■ 10-bit Resolution
The conversion time depends on the INTCLK fre-
quency and the prescaler factor stored in the
PR[2:0] bits of the CLR2 register (R253-page 63)).
■ Monotonicity: Guaranteed
■ No missing codes: Guaranteed
■ 3-bit INTCLK/2 Frequency Prescaler
■ Internal/External Trigger availability
■ Continuous/Single Modes
■ Autoscan Mode
AV
and AV are the high and low level refer-
SS
DD
ence voltage pins. Up to 16 multiplexed Analog In-
puts are available depending on the specific de-
vice type. With the AUTOSCAN feature, a group of
signals can be converted sequentially by simply
programming the starting address of the first ana-
log channel to be converted.
■ Power Down Mode
■ 16 10-bit data registers (two per channel)
There are two Analog Watchdogs used for the
continuous hardware monitoring of two consecu-
tive input channels selectable by means of the
CC[3:0] bits in the CLR1 register (R252-page 63).
An Interrupt request is generated whenever the
converted value of either of these two analog in-
puts exceeds the upper or lower programmed
threshold values.
■ Two analog watchdogs selectable on adjacent
channels
10.11.2 Introduction
The Analog to Digital Converter (ADC) consists of
an input multiplex channel selector feeding a suc-
cessive approximation converter.
Figure 155. ADC Block Diagram
INT. VECTOR POINTER
INT. CONTROL REGISTER
INTERRUPT UNIT
COMPARE RESULT REGISTER
THRESHOLD H/L REGISTER BU
THRESHOLD H/L REGISTER BL
THRESHOLD H/L REGISTER AH
THRESHOLD H/L REGISTER AL
COMPARE LOGIC
INTERNAL
TRIGGER
(from MFT0)
AIN 15
AIN 14
AIN 13
AIN 12
AIN 11
DATA REGISTER H/L15
DATA REGISTER H/L14
DATA REGISTER H/L13
DATA REGISTER H/L12
DATA REGISTER H/L11
DATA REGISTER H/L10
DATA REGISTER H/L 9
DATA REGISTER H/L 8
DATA REGISTER H/L 7
DATA REGISTER H/L 6
DATA REGISTER H/L 5
DATA REGISTER H/L 4
DATA REGISTER H/L 3
DATA REGISTER H/L 2
DATA REGISTER H/L 1
DATA REGISTER H/L 0
CONVERSION
RESULT
EXTERNAL
TRIGGER
(EXTRG)
AIN 10
AIN 9
AIN 8
CONTROL
LOGIC
SUCCESSIVE
ANALOG
MUX
APPROXIMATION
ANALOG TO DIGITAL
CONVERTER
AIN 7
AIN 6
AIN 5
AIN 4
AIN 3
10 bit
AIN 2
AIN 1
AIN 0
CKAD
CK PRESCALER
ANALOG
SECTION
CONTROL REG.2
(CLR2)
DIVIDER by 2
AUTOSCAN LOGIC
CONTROL REG.1
(CLR1)
INTCLK
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9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
ANALOG TO DIGITAL CONVERTER (Cont’d)
Single and continuous conversion modes are
available. These two modes may be triggered by
an external signal or, internally, by the Multifunc-
tion Timer MFT0.
Both modes operate in AUTOSCAN configuration,
allowing sequential conversion of the input chan-
nels. The number of analog inputs to be converted
may be set by software, by setting the number of
the first channel to be converted into Control Reg-
ister 1 (SC[3:0] bits). As each conversion is com-
pleted, the channel number is automatically incre-
mented, up to channel 15. For example, if SC[3:0]
are set to 0011, the conversion will proceed from
channel 3 to channel 15, whereas, if SC[3:0] are
set to 1111, only channel 15 will be converted.
A Power-Down programmable bit allows the ADC
to be set in low-power idle mode.
The reference voltage AV
can be switched off
DD
when the ADC is in power down mode.
The ADC Interrupt Unit provides two maskable
channels (Analog Watchdog and End of Conver-
sion) with hardware fixed priority, and up to 7 pro-
grammable priority levels.
When the ST bit of Control Logic Register 2 is set,
either by software or by hardware (by an internal
or external synchronisation trigger signal), the an-
alog inputs are sequentially converted (from the
first selected channel up to channel 15) and the re-
sults are stored in the relevant pair of Data Regis-
ters.
Conversion Time
The maximum CKAD frequency allowable for the
analog part is 4 MHz. This is provided by a pro-
grammable prescaler that divides the ST9 system
clock (INTCLK) and a divider by 2. The user must
program the PR[2:0] bits in Control Logic Register
2 (CLR2, R253 - Page 63) to select the right pres-
caler dividing factor to obtain the correct clock fre-
quency for the analog part. Table 69 shows the
possible prescaling values and the related sam-
pling and conversion times. Generally, the formu-
las for the sampling and conversion times are:
In Single Mode (CONT = “0”), the ST bit is reset
by hardware following conversion of channel 15;
an End of Conversion (ECV) interrupt request is is-
sued and the ADC waits for a new start event.
In Continuous Mode (CONT = “1”), a continuous
conversion flow is initiated by the start event.
When conversion of channel 15 is complete,
conversion of channel 's' is initiated (where 's' is
specified by the setting of the SC[3:0] bits); this will
continue until the ST bit is reset by software. In all
cases, an ECV interrupt is issued each time
channel 15 conversion ends.
T
T
= (T
x 2) x (PR[2:0] x 8)
INTCLK
Sample
= (T
x 2) x (PR[2:0] x 28)
INTCLK
Conv
The user may need to increase the conversion
time if a resistor is added to the input pin, for in-
stance, as an overvoltage protection. In this case,
the ADC needs a longer sampling time to work
correctly.
When channel 'i' is converted ('s' <'i' <15), the re-
lated pair of Data Registers is reloaded with the
new conversion result and the previous value is
lost. The End of Conversion (ECV) interrupt serv-
ice routine can be used to save the current values
before a new conversion sequence (so as to cre-
ate signal sample tables in the Register File or in
Memory).
CAUTION: ADC INPUT PIN CONFIGURATION
The input Analog channel is selected by using the
I/O pin Alternate Function setting (PxC2, PxC1,
PxC0 = 1,1,1) as described in the I/O ports sec-
tion. The I/O configuration of the port connected to
the ADC converter is modified in order to prevent
the analog voltage present on the I/O pin from
causing high power dissipation across the input
buffer. Analog channels should be maintained in
Alternate Function configuration for this reason.
10.11.3.2 Triggering and Synchronisation
In both modes, conversion may be triggered by in-
ternal or external conditions; externally this may
be tied to EXTRG, as an Alternate Function input
on an I/O port pin, and internally, it may be tied to
INTRG, generated by a Multifunction Timer pe-
ripheral. Both external and internal events can be
separately masked by programming the EXTG/
INTG bits of the Control Logic Register (CLR). The
events are internally ORed, thus avoiding potential
hardware conflicts. However, the correct proce-
dure is to enable only one alternate synchronisa-
tion condition at any time.
10.11.3 Functional Description
10.11.3.1 Operating Modes
Two operating modes are available: Continuous
Mode and Single Mode. To enter one of these
modes it is necessary to program the CONT bit of
the Control Logic Register2 (CLR2, R253-
page63). The Continuous Mode is selected when
CONT is set, while Single Mode is selected when
CONT is reset.
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9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
ANALOG TO DIGITAL CONVERTER (Cont’d)
The effect of either of these synchronisation
modes is to set the ST bit by hardware. This bit is
reset, in Single Mode only, at the end of each
group of conversions. In Continuous Mode, all trig-
ger pulses after the first are ignored.
rupt. The four threshold voltages are user pro-
grammable in dedicated registers pairs (R244 to
R251, page 63). Only the 4 MSBs of the Compare
Results Register are used as flags, each of the
four MSBs being associated with a threshold con-
dition.
The synchronisation sources must be at a logic
low level for at least the duration of two INTCLK
cycles and, in Single Mode, the period between
trigger pulses must be greater than the total time
required for a group of conversions. If a trigger oc-
curs when the ST bit is still set, i.e. when a conver-
sion is still in progress, it will be ignored.
Following a reset, these flags are reset. During
normal ADC operation, the CRR bits are set, in or-
der to flag an out of range condition and are auto-
matically reset by hardware after a software reset
of the Analog Watchdog Request flag in the ICR
Register.
Note: The external trigger will set the CLR2.ST bit
10.11.3.4 Power Down Mode
even if the CLR2.POW is reset.
Before enabling an ADC conversion, the POW bit
of the Control Logic Register must be set; this
must be done at least 10 µs before the first conver-
sion start, in order to correctly bias the analog sec-
tion of the converter circuitry.
10.11.3.3 Analog Watchdog
Two internal Analog Watchdogs are available for
highly flexible automatic threshold monitoring of
external analog signal levels. Depending on the
value of the CC[3:0] bits in Control Logic Register1
these two watchdog are mapped onto 2 of the 16
available adjacent channels, allowing the user to
set the channel to be monitored. Refer to Table 68
to see the possible choices for this feature.
When the ADC is not required, the POW bit may
be reset in order to reduce the total power con-
sumption. This is the reset configuration, and this
state is also selected automatically when the ST9
is placed in Halt Mode (following the execution of
the haltinstruction).
Analog watchdog channels (named as A and B)
monitor an acceptable voltage level window for the
converted analog inputs. The external voltages
applied to inputs A and B are considered normal
while they remain below their respective Upper
thresholds, and above or at their respective Lower
thresholds.
Figure 156. Analog Watchdog Function
Analog Voltage
Upper Threshold
Normal Area
When the external signal voltage level is greater
than, or equal to, the upper programmed voltage
limit, or when it is less than the lower programmed
voltage limit, a maskable interrupt request is gen-
erated and the Compare Results Register is up-
dated in order to flag the threshold (Upper or Low-
er) and channel (A or B) responsible for the inter-
Figure 157. ADC Trigger Source
(Window Guarded)
Lower Threshold
Ext. Trigger Enable
ADC Trigger
EXTRG
Int. Trigger Enable
Start group of conversions
Continuous or Single mode
On-Chip Event
MFT0
Software Trigger
363/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
ANALOG TO DIGITAL CONVERTER (Cont’d)
Figure 158. Application Example: Analog Watchdog used in Motor Speed Control
the Interrupt Vector table containing the base ad-
dress of the four byte area of the interrupt vector
table in which the address of the ADC interrupt
service routines are stored.
10.11.4 Interrupts
The ADC provides two interrupt sources:
– End of Conversion
The Analog Watchdog Interrupt Pending bit (AWD,
ICR.6) is automatically set by hardware whenever
any of the two guarded analog inputs go out of
range. The Compare Result Register (CRR) tracks
the analog inputs which exceed their programmed
thresholds.
– Analog Watchdog Request
The ADC Interrupt Vector Register (IVR, R255
Page 63) provides hardware generated flags
which indicate the interrupt source, thus allowing
the automatic selection of the correct interrupt
service routine.
When two requests occur simultaneously, the An-
alog Watchdog Request has priority over the End
of Conversion request, which is held pending.
Analog
Watch-
dog Re-
quest
7
0
0
The Analog Watchdog Request requires the user
to poll the Compare Result Register (CRR) to de-
termine which of the four thresholds has been ex-
ceeded. The threshold status bits are set to flag an
out of range condition, and are automatically reset
by hardware after a software reset of the Analog
Watchdog Request flag in the ICR Register. The
interrupt pending flags, ECV and AWD, should be
reset by the user within the interrupt service rou-
tine. Setting either of these two bits by software
will cause an interrupt request to be generated.
Lower
Word
Address
X
X
X
X
X
X
0
7
0
0
End of
Conv.
Request
Upper
Word
Address
X
X
X
X
X
X
1
The ADC Interrupt vector should be programmed
by the user to point to the first memory location in
364/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
10.11.5 Register Description
DATA REGISTERS (DiHR/DiLR)
CHANNEL 2 DATA HIGH REGISTER (D2HR)
R244 - Read/Write
The conversion results for the 16 available chan-
nels are loaded into the 32 Data Registers (two for
each channel) following conversion of the corre-
sponding analog input.
Register Page: 61
Reset Value: undefined
7
0
CHANNEL 0 DATA HIGH REGISTER (D0HR)
R240 - Read/Write
D2.9 D2.8 D2.7 D2.6 D2.5 D2.4 D2.3 D2.2
Register Page: 61
Reset Value: undefined
Bits 7:0 = D2.[9:2]: Channel 2 9:2 bit Data
7
0
CHANNEL 2 DATA LOW REGISTER (D2LR)
R245 - Read/Write
D0.9 D0.8 D0.7 D0.6 D0.5 D0.4 D0.3 D0.2
Register Page: 61
Reset Value: xx00 0000
Bits 7:0 = D0.[9:2]: Channel 0 9:2 bit Data
7
0
0
CHANNEL 0 DATA LOW REGISTER (D0LR)
R241 - Read/Write
D2.1 D2.0
0
0
0
0
0
Register Page: 61
Reset Value: xx00 0000
Bits 7:0 = D2.[1:0]: Channel 2 1:0 bit Data
7
0
0
Bits 5:0 = Reserved, forced by hardware to 0.
D0.1 D0.0
0
0
0
0
0
CHANNEL 3 DATA HIGH REGISTER (D3HR)
R246 - Read/Write
Bits 7:6 = D0.[1:0]: Channel 0 1:0 bit Data
Register Page: 61
Reset Value: undefined
Bits 5:0 = Reserved, forced by hardware to 0.
7
0
CHANNEL 1 DATA HIGH REGISTER (D1HR)
R242 - Read/Write
D3.9 D3.8 D3.7 D3.6 D3.5 D3.4 D3.3 D3.2
Register Page: 61
Reset Value: undefined
Bits 7:0 = D3.[9:2]: Channel 3 9:2 bit Data
7
0
CHANNEL 3 DATA LOW REGISTER (D3LR)
R247 - Read/Write
D1.9 D1.8 D1.7 D1.6 D1.5 D1.4 D1.3 D1.2
Register Page: 61
Reset Value: xx00 0000
Bits 7:0 = D1.[9:2]: Channel 1 9:2 bit Data
7
0
0
CHANNEL 1 DATA LOW REGISTER (D1LR)
R243 - Read/Write
D3.1 D3.0
0
0
0
0
0
Register Page: 61
Reset Value: xx00 0000
Bits 7:0 = D3.[1:0]: Channel 3 1:0 bit Data
7
0
0
Bits 5:0 = Reserved, forced by hardware to 0.
D1.1 D1.0
0
0
0
0
0
Bits 7:0 = D1.[1:0]: Channel 1 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
365/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
CHANNEL 4 DATA HIGH REGISTER (D4HR)
R248 - Read/Write
CHANNEL 6 DATA HIGH REGISTER (D6HR)
R252 - Read/Write
Register Page: 61
Register Page: 61
Reset Value: undefined
Reset Value: undefined
7
0
7
0
D4.9 D4.8 D4.7 D4.6 D4.5 D4.4 D4.3 D4.2
D6.9 D6.8 D6.7 D6.6 D6.5 D6.4 D6.3 D6.2
Bits 7:0 = D4.[9:2]: Channel 4 9:2 bit Data
Bits 7:0 = D6.[9:2]: Channel 6 9:2 bit Data
CHANNEL 4 DATA LOW REGISTER (D4LR)
R249 - Read/Write
CHANNEL 6 DATA LOW REGISTER (D6LR)
R253 - Read/Write
Register Page: 61
Register Page: 61
Reset Value: xx00 0000
Reset Value: xx00 0000
7
0
0
7
0
0
D4.1 D4.0
0
0
0
0
0
D6.1 D6.0
0
0
0
0
0
Bits 7:6 = D4.[1:0]: Channel 4 1:0 bit Data
Bits 7:0 = D6.[1:0]: Channel 6 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
Bits 5:0 = Reserved, forced by hardware to 0.
CHANNEL 5 DATA HIGH REGISTER (D5HR)
R250 - Read/Write
CHANNEL 7 DATA HIGH REGISTER (D7HR)
R254 - Read/Write
Register Page: 61
Register Page: 61
Reset Value: undefined
Reset Value: undefined
7
0
7
0
D5.9 D5.8 D5.7 D5.6 D5.5 D5.4 D5.3 D5.2
D7.9 D7.8 D7.7 D7.6 D7.5 D7.4 D7.3 D7.2
Bits 7:0 = D5.[9:2]: Channel 5 9:2 bit Data
Bits 7:0 = D7.[9:2]: Channel 7 9:2 bit Data
CHANNEL 5 DATA LOW REGISTER (D5LR)
R251 - Read/Write
CHANNEL 7 DATA LOW REGISTER (D7LR)
R255- Read/Write
Register Page: 61
Register Page: 61
Reset Value: xx00 0000
Reset Value: xx00 0000
7
0
0
7
0
0
D5.1 D5.0
0
0
0
0
0
D7.1 D7.0
0
0
0
0
0
Bits 7:0 = D1.[1:0]: Channel 5 1:0 bit Data
Bits 7:0 = D7.[1:0]: Channel 7 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
Bits 5:0 = Reserved, forced by hardware to 0.
366/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
CHANNEL 8 DATA HIGH REGISTER (D8HR)
R240 - Read/Write
CHANNEL 10 DATA HIGH REGISTER (D10HR)
R244 - Read/Write
Register Page: 62
Register Page: 62
Reset Value: undefined
Reset Value: undefined
7
0
7
0
D8.9 D8.8 D8.7 D8.6 D8.5 D8.4 D8.3 D8.2
D10.9 D10.8 D10.7 D10.6 D10.5 D10.4 D10.3 D10.2
Bits 7:0 = D8.[9:2]: Channel 8 9:2 bit Data
Bits 7:0 = D10.[9:2]: Channel 10 9:2 bit Data
CHANNEL 8 DATA LOW REGISTER (D8LR)
R241 - Read/Write
CHANNEL 10 DATA LOW REGISTER (D10LR)
R245 - Read/Write
Register Page: 62
Register Page: 62
Reset Value: xx00 0000
Reset Value: xx00 0000
7
0
0
7
0
0
D8.1 D8.0
0
0
0
0
0
D10.1 D10.0
0
0
0
0
0
Bits 7:6 = D8.[1:0]: Channel 8 1:0 bit Data
Bits 7:0 = D10.[1:0]: Channel 10 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
Bits 5:0 = Reserved, forced by hardware to 0.
CHANNEL 9 DATA HIGH REGISTER (D9HR)
R242 - Read/Write
CHANNEL 11 DATA HIGH REGISTER (D11HR)
R246 - Read/Write
Register Page: 62
Register Page: 62
Reset Value: undefined
Reset Value: undefined
7
0
7
0
D9.9 D9.8 D9.7 D9.6 D9.5 D9.4 D9.3 D9.2
D11.9 D11.8 D11.7 D11.6 D11.5 D11.4 D11.3 D11.2
Bits 7:0 = D9.[9:2]: Channel 9 9:2 bit Data
Bits 7:0 = D11.[9:2]: Channel 11 9:2 bit Data
CHANNEL 9 DATA LOW REGISTER (D9LR)
R243 - Read/Write
CHANNEL 11 DATA LOW REGISTER (D11LR)
R247 - Read/Write
Register Page: 62
Register Page: 62
Reset Value: xx00 0000
Reset Value: xx00 0000
7
0
0
7
0
0
D9.1 D9.0
0
0
0
0
0
D11.1 D11.0
0
0
0
0
0
Bits 7:0 = D9.[1:0]: Channel 9 1:0 bit Data
Bits 7:0 = D11.[1:0]: Channel 11 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
Bits 5:0 = Reserved, forced by hardware to 0.
367/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
CHANNEL 12 DATA HIGH REGISTER (D12HR)
R248 - Read/Write
CHANNEL 14 DATA HIGH REGISTER (D14HR)
R252 - Read/Write
Register Page: 62
Register Page: 62
Reset Value: undefined
Reset Value: undefined
7
0
7
0
D12.9 D12.8 D12.7 D12.6 D12.5 D12.4 D12.3 D12.2
D14.9 D14.8 D14.7 D14.6 D14.5 D14.4 D14.3 D14.2
Bits 7:0 = D12.[9:2]: Channel 12 9:2 bit Data
Bits 7:0 = D14.[9:2]: Channel 14 9:2 bit Data
CHANNEL 12 DATA LOW REGISTER (D12LR)
R249 - Read/Write
CHANNEL 14 DATA LOW REGISTER (D14LR)
R253 - Read/Write
Register Page: 62
Register Page: 62
Reset Value: xx00 0000
Reset Value: xx00 0000
7
0
0
7
0
0
D12.1 D12.0
0
0
0
0
0
D14.1 D14.0
0
0
0
0
0
Bits 7:6 = D12.[1:0]: Channel 12 1:0 bit Data
Bits 7:0 = D14.[1:0]: Channel 14 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
Bits 5:0 = Reserved, forced by hardware to 0.
CHANNEL 13 DATA HIGH REGISTER (D13HR)
R250 - Read/Write
CHANNEL 15 DATA HIGH REGISTER (D15HR)
R254 - Read/Write
Register Page: 62
Register Page: 62
Reset Value: undefined
Reset Value: undefined
7
0
7
0
D13.9 D13.8 D13.7 D13.6 D13.5 D13.4 D13.3 D13.2
D15.9 D15.8 D15.7 D15.6 D15.5 D15.4 D15.3 D15.2
Bits 7:0 = D13.[9:2]: Channel 13 9:2 bit Data
Bits 7:0 = D15.[9:2]: Channel 15 9:2 bit Data
CHANNEL 13 DATA LOW REGISTER (D13LR)
R251 - Read/Write
CHANNEL 15 DATA LOW REGISTER (D15LR)
R255- Read/Write
Register Page: 62
Register Page: 62
Reset Value: xx00 0000
Reset Value: xx00 0000
7
0
0
7
0
0
D13.1 D13.0
0
0
0
0
0
D15.1 D15.0
0
0
0
0
0
Bits 7:0 = D13.[1:0]: Channel 13 1:0 bit Data
Bits 7:0 = D15.[1:0]: Channel 15 1:0 bit Data
Bits 5:0 = Reserved, forced by hardware to 0.
Bits 5:0 = Reserved, forced by hardware to 0.
Note: If only 8-bit accuracy is required, each Data
High Register can be used to get the conversion
result, ignoring the corresponding DxLR register
content.
368/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
COMPARE RESULT REGISTER (CRR)
R243 - Read/Write
CHANNEL A LOWER THRESHOLD HIGH
REGISTER (LTAHR)
Register Page: 63
R244 - Read
Reset Value: 0000 xxxx (0xh)
Register Page: 63
Reset Value: undefined
Two adjacent channels (identified as A and B) can
be selected through CLR1 register programming
(bits CC[3:0]); a level window for the converted an-
alog input can be defined on these channels.
7
0
LTA.9 LTA.8 LTA.7 LTA.6 LTA.5 LTA.4 LTA.3 LTA.2
7
0
Bits 7:0 = LTA.[9:2]: Channel A [9:2] bit Lower
Threshold
CBU CAU CBL CAL
x
x
x
x
Bits 7 = CBU: Compare Register Ch. B Upper
Threshold
Set when converted data on channel B is greater
than the threshold value set in UTBHR/UTBLR
registers.
CHANNEL A LOWER THRESHOLD LOW
REGISTER (LTALR)
R245 - Read/Write
Register Page: 63
Reset Value: xx00 0000
7
0
0
Bits 6 = CAU: Compare Register Ch. A Upper
Threshold
Set when converted data on channel A is greater
than the threshold value set in UTAHR/UTALR
registers.
LTA.1 LTA.0
0
0
0
0
0
Bits 7:6 = LTA.[1:0]: Channel A [1:0] bit Lower
Threshold
Bits 5 = CBL: Compare Register Ch. B Lower
Threshold
Bits 5:0 = Reserved, forced by hardware to 0.
Set when converted data on channel B is less than
the threshold value set in LTBHR/LTBLR regis-
ters.
CHANNEL B LOWER THRESHOLD HIGH REG-
ISTER (LTBHR)
R246 - Read/Write
Register Page: 63
Reset Value: undefined
Bits 4 = CAL: Compare Register Ch. A Lower
Threshold
Set when converted data on channel A is less than
the threshold value set in LTAHR/LTALR regis-
ters.
7
0
LTB.7 LTB.7 LTB.5 LTB.4 LTB.3 LTB.2 LTB.1 LTB.0
Bits 3:0 = Don’t care
Bits 7:0 = LTB.[9:2]: Channel B [9:2] bit Lower
Threshold
LOWER THRESHOLD REGISTERS (LTiHR/
LTiLR)
The two pairs of Lower Threshold High/Low regis-
ters are used to store the user programmable low-
er threshold 10-bit values, to be compared with the
current conversion results, thus setting the lower
window limit.
369/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
CHANNEL B LOWER THRESHOLD LOW
REGISTER (LTBLR)
CHANNEL A UPPER THRESHOLD LOW
REGISTER (UTALR)
R249 - Read/Write
Register Page: 63
R247 - Read/Write
Register Page: 63
Reset Value: xx00 0000
Reset Value: xx00 0000
7
0
0
7
0
0
LTB.1 LTB.0
0
0
0
0
0
UTA.1 UTA.0
0
0
0
0
0
Bits 7:6 = LTB.[1:0]: Channel B [1:0] bit Lower
Threshold
Bits 7:6 = UTA.[1:0]: Channel A [1:0] bit Upper
Threshold
Bits 5:0 = Reserved, forced by hardware to 0.
Bits 5:0 = Reserved, forced by hardware to 0.
UPPER THRESHOLD REGISTERS (UTiHR/
UTiLR)
CHANNEL B UPPER THRESHOLD HIGH REG-
ISTER (UTBHR)
R250 - Read/Write
The two pairs of Upper Threshold High/Low Reg-
isters are used to store the user programmable up-
per threshold 10-bit values, to be compared with
the current conversion results, thus setting the up-
per window limit.
Register Page: 63
Reset Value: undefined
7
0
UTB.9 UTB.8 UTB.7 UTB.6 UTB.5 UTB.4 UTB.3 UTB.2
CHANNEL A UPPER THRESHOLD HIGH REG-
ISTER (UTAR)
Bits 7:0 = UTB.[9:2]: Channel B [9:2] bit Upper
Threshold
R248 - Read/Write
Register Page: 63
Reset Value: undefined
CHANNEL B UPPER THRESHOLD LOW
REGISTER (UTBLR)
7
0
R251 - Read/Write
UTA.9 UTA.8 UTA.7 UTA.6 UTA.5 UTA.4 UTA.3 UTA.2
Register Page: 63
Reset Value: xx00 0000
Bits 7:0 = UTA.[9:2]: Channel 6 [9:2] bit Upper
Threshold value
7
0
0
UTB.1 UTB.0
0
0
0
0
0
Bits 7:6 = UTB.[1:0]: Channel B [1:0] bit Lower
Threshold
Bits 5:0 = Reserved, forced by hardware to 0.
370/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
Table 68. Compare Channels definition
REGISTER DESCRIPTION (Cont’d)
CONTROL LOGIC REGISTER 1 (CLR1)
R252 - Read/Write
Register Page: 63
Reset Value: 0000 1111 (0Fh)
CC[3:0]
Channel A
Channel B
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
3
4
5
6
7
4
5
6
7
8
7
0
SC3 SC2 SC1 SC0 CC3 CC2 CC1 CC0
Bits 7:4 = SC[3:0]: Start Conversion Channel
These four bits define the starting analog input
channel (Autoscan Mode). The first channel ad-
dressed by SC[3:0] is converted, then the channel
number is incremented for the successive conver-
sion, until channel 15 (1111) is converted. When
SC3, SC2, SC1 and SC0 are all set, only channel
15 will be converted.
8
9
9
10
11
12
13
14
15
10
11
12
13
14
Bits 3:0 = CC[3:0]: Compare Channels
The programmed value corresponds to the first of
the two adjacent channels (A) on which it is possi-
ble to define a level window for the converted ana-
log input (see Table 68).
CONTROL LOGIC REGISTER 2 (CLR2)
R253 - Read/Write
Register Page: 63
Reset Value: 1010 0000 (A0h)
Note: If a write access to this register occurs, the
conversion is re-started from the SC[3:0] channel.
7
0
PR2 PR1 PR0 EXTG INTG POW CONT ST
Table 68. Compare Channels definition
CC[3:0]
Channel A
Channel B
Bits 7:5 = PR[2:0]: INTCLK Frequency Prescaler
These bits determine the ratio between the ADC
clock and the system clock (INTCLK) according to
Table 69.
0000
0001
0010
0011
15
0
1
0
1
2
3
2
Table 69. Prescaler programming
T
f
T
f
T
T
f
T
T
Conv
ADC
Sample
ADC
Sample
Conv
ADC
Sample Conv
T
/
A/D clock
(µs)
(MHz)
(µs)
(MHz)
(µs)
(µs)
(MHz)
(µs)
(µs)
PR[2:0]
T
INTCLK
@T
= 8MHz
@T
= 20MHz
@T
=24MHz
INTCLK
INTCLK
INTCLK
000
001
010
011
100
101
110
111
2
4
6
4.00
2.00
1.33
1.00
0.80
0.66
0.57
0.50
2
4
6
8
7
10.00
5.00
3.33
2.50
2.00
1.66
1.43
1.25
Not Allowed
Not Allowed
12.00
6.00
4.00
3.00
2.40
2.00
1.71
1.50
Not Allowed
Not Allowed
14
21
28
2.4
3.2
4
8.4
11.2
14
2
7
8
2.66
9.33
10
12
14
16
Not Allowed
Not Allowed
Not Allowed
Not Allowed
3.33 11.66
14
4.8
5.6
6.4
16.8
19.6
22.4
4
4.66 16.33
5.33 18.66
371/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
Bit 4 = EXTG: External Trigger Enable.
This bit is set and cleared by software.
0: External trigger disabled.
1: External trigger enabled. Allows a conversion
sequence to be started on the subsequent edge
of the external signal applied to the EXTRG pin
(when enabled as an Alternate Function).
Bit 0 = ST: Start/Stop.
0: Stop conversion. When the ADC converter is
running in Single Mode, this bit is hardware re-
set at the end of a sequence of conversions.
1: Start a sequence of conversions.
Note: If a write access to this register occurs, the
conversion is re-started from the SC[3:0] channel.
Bit 3 = INTG: Internal Trigger Enable.
This bit is set and cleared by software.
0: Internal trigger disabled.
INTERRUPT CONTROL REGISTER (AD_ICR)
1: Internal trigger enabled. Allows a conversion se-
quence to be started, synchronized by an inter-
nal signal (On-chip Event signal) from a Multi-
function Timer peripheral.
The Interrupt Control Register contains the three
priority level bits, the two source flags, and their bit
mask:
INTERRUPT CONTROL REGISTER (AD_ICR)
R254 - Read/Write
Register Page: 63
Reset Value: 0000 0111 (07h)
Both External and Internal Trigger inputs are inter-
nally ORed, thus avoiding Hardware conflicts;
however, the correct procedure is to enable only
one alternate synchronization input at a time.
7
0
Note: The effect of either synchronization mode is
to set the START/STOP bit, which is reset by hard-
ware when in SINGLE mode, at the end of each
sequence of conversions.
ECV AWD ECI AWDI
X
PL2 PL1 PL0
Requirements: The External Synchronisation In-
put must receive a low level pulse wider than an
INTCLK period and, for both External and On-Chip
Event synchronisation, the repetition period must
be greater than the time required for the selected
sequence of conversions.
Bit 7 = ECV: End of Conversion.
This bit is automatically set by hardware after a
group of conversions is completed. It must be re-
set by the user, before returning from the Interrupt
Service Routine. Setting this bit by software will
cause a software interrupt request to be generat-
ed.
0: No End of Conversion event occurred
1: An End of Conversion event occurred
Bit 2 = POW: Power Up/Power Down.
This bit is set and cleared by software.
0: Power down mode: all power-consuming logic is
disabled, thus selecting a low power idle mode.
1: Power up mode: the ADC converter logic and
analog circuitry is enabled.
Bit 6 = AWD: Analog Watchdog.
This is automatically set by hardware whenever ei-
ther of the two monitored analog inputs exceeds a
threshold. The threshold values are stored in reg-
isters R244/R245 and R248/R249 for channel A,
and in registers R246/R247 and R250/R251 for
channel B respectively. The Compare Result Reg-
ister (CRR) keeps track of the analog inputs ex-
ceeding the thresholds.
Bit 1 = CONT: Continuous/Single.
0: Single Mode: a single sequence of conversions
is initiated whenever an external (or internal)
trigger occurs, or when the ST bit is set by soft-
ware.
The AWD bit must be reset by the user, before re-
turning from the Interrupt Service Routine. Setting
this bit by software will cause a software interrupt
request to be generated.
0: No Analog Watchdog event occurred
1: An Analog Watchdog event occurred
1: Continuous Mode: the first sequence of conver-
sions is started, either by software (by setting
the ST bit), or by hardware (on an internal or ex-
ternal trigger, depending on the setting of the
INTG and EXTG bits); a continuous conversion
sequence is then initiated.
372/426
9
10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
Bit 5 = ECI: End of Conversion Interrupt Enable.
This bit masks the End of Conversion interrupt re-
quest.
0: Mask End of Conversion interrupts
1: Enable End of Conversion interrupts
INTERRUPT VECTOR REGISTER (AD_IVR)
R255 - Read/Write
Register Page: 63
Reset Value: xxxx xx10 (x2h)
7
0
0
V7
V6
V5
V4
V3
V2
W1
Bit 4 = AWDI: Analog Watchdog Interrupt Enable.
This bit masks or enables the Analog Watchdog
interrupt request.
0: Mask Analog Watchdog interrupts
1: Enable Analog Watchdog interrupts
Bits 7:2 = V[7:2]: ADC Interrupt Vector.
This vector should be programmed by the user to
point to the first memory location in the Interrupt
Vector table containing the starting addresses of
the ADC interrupt service routines.
Bit 3 = Reserved.
Bits 2:0 = PL[2:0]: ADC Interrupt Priority Level.
These three bits are used to select the Interrupt
priority level for the ADC.
Bit 1 = W1: Word Select.
This bit is set and cleared by hardware, according
to the ADC interrupt source.
0: Interrupt source is the Analog Watchdog, point-
ing to the lower word of the ADC interrupt serv-
ice block (defined by V[7:2]).
1:Interrupt source is the End of Conversion inter-
rupt, thus pointing to the upper word.
Note: When two requests occur simultaneously,
the Analog Watchdog Request has priority over
the End of Conversion request, which is held
pending.
Bit 0 = Reserved, forced by hardware to 0.
373/426
9
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
11 ELECTRICAL CHARACTERISTICS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precautions to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations. The average chip-junc-
tion temperature, T , in Celsius can be obtained
J
from:
T =
T + P x RthJA
A D
J
Where: T =
Ambient Temperature.
A
For proper operation it is recommended that V
IN
RthJA = Package thermal resistance
(junction-to ambient).
and V be higher than V and lower than V .
DD
O
SS
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V
P =
P
+ P
.
PORT
DD
D
INT
or V ).
SS
P
P
=
I
x V (chip internal power).
INT
PORT
DD DD
=Port power dissipation
(determined by the user)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
Supply Voltage
– 0.3 to 6.5
DD
AV
AV
ADC Reference Voltage
ADC Ground
V
to V + 0.3
V
DD
SS
IN
SS
DD
V
SS
V
Input Voltage (all pins except pure open drain I/O pins)
Input Voltage (pure open drain I/O pins)
Analog Input Voltage (ADC inputs)
Storage Temperature
– 0.3 to V + 0.3
V
V
DD
V
– 0.3 to 6.5
INOD
V
-0.3 to AV + 0.3
V
AIN
DD
T
– 55 to +150
°C
mA
mA
mA
STG
(2)
⎥I
⎥
Load Current
10
IO
(1)
(2)
⎥I
⎥
Pin Injection Current - Digital and Analog Inputs
10
INJ
(2)
⎥I
⎥
Absolute sum of all Pin Injection Current in the device
100
TINJ
Notes:
Stresses above those listed as “absolute maximum ratings“ may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability. All voltages are referenced to V = 0 V.
SS
Note 1: Pin injection current occurs when the voltage on any pin exceeds the specified range.
Note 2: Value guaranteed by design.
THERMAL CHARACTERISTICS
Symbol
Package
Value
Unit
TQFP64
PQFP100
TQFP100
47
28
44
RthJA
°C/W
374/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
-40
-40
4.5
0
Max
105
125
5.5
Unit
B Suffix Version
C Suffix Version
T
Ambient temperature range
°C
A
V
Operating Supply Voltage
ADC Reference Voltage
V
V
DD
AV
V
+ 0.2
DD
DD
(1)
f
Internal Clock Frequency
Stabilization capacitor between V
0
24
MHz
nF
INTCLK
C33
and V
300
REG
SS
Note: (1) > 1MHz when ADC or JBLPD is used, 2.6MHz when I²C is used
375/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(V = 5 V ± 10%, T = –40° C to +125° C, unless otherwise specified)
DD
A
Value
Symbol
Parameter
Comment
Unit
Typ
Min
Max
(1)
(2)
Input High Level
TTL
2.0
V
V
P0[7:0]-P1[7:0]-P2[7:6]-P2[3:2]-
P3.3-P4.2-P4.5-P5.3
(2)
(2)
CMOS
0.7 x V
DD
Input High Level
Standard Schmitt Trigger
V
0.6 x V
V
P2[5:4]-P2[1:0]-P3[7:4]-P3[2:0]-P4[4:3]-
P4[1:0]-P5[7:4]-P5[2:0]-P6[3:0]-P6[7:6]-
P7[7:0]-P8[7:0]-P9[7:0]
IH
DD
Input High Level
High Hyst. Schmitt Trigger
(2)
0.7 x V
V
DD
P4[7:6]-P6[5:4]
Input Low Level
(2)
TTL
0.8
V
V
P0[7:0]-P1[7:0]-P2[7:6]-P2[3:2]-P3.3-
P4.2-P4.5-P5.3
(2)
(2)
CMOS
0.3 x V
DD
Input Low Level
Standard Schmitt Trigger
V
0.2 x V
V
V
P2[5:4]-P2[1:0]-P3[7:4] P3[2:0]-P4[4:3]-
P4[1:0]-P5[7:4]-P5[2:0]-P6[3:0]-P6[7:6]-
P7[7:0]-P8[7:0]-P9[7:0]
IL
DD
Input Low Level
High Hyst.Schmitt Trigger
(2)
0.25 x V
6.0
DD
P4[7:6]-P6[5:4]
Input Voltage Range
-0.3
-0.3
V
V
Pure Open Drain
P2[3:2]-P4[7:6]
V
I
Input Voltage Range
All other pins
V
+ 0.3
DD
Input Hysteresis
Standard Schmitt Trigger
250
1
mV
P2[5:4]-P2[1:0]-P3[7:4]-P3[2:0]-P4[4:3]-
P4[1:0]-P5[7:4]-P5[2:0]-P6[3:0]-P6[7:6]-
P7[7:0]-P8[7:0]-P9[7:0]
V
HYS
Input Hysteresis
High Hyst. Schmitt Trigger
V
V
P4[7:6]-P6[5:4]
Output High Level
P6[5:4]
Push Pull mode
= – 8mA
EMR1.BSZ bit = 1
I
V
V
– 0.8
OH
DD
DD
(3)
Output High Level
V
OH
P0[7:0]-P2[7:4]-P2[1:0]-P3[7:0]-P4[5:0]-
P5[7:0]-P6[3:0]-
P6[7:6]-P7[7:0]-P8[7:0]-P9[7:0]-VPWO-
AS-DS-RW
Push Pull mode
– 0.8
V
I
= – 2mA
OH
376/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
Value
Symbol
Parameter
Comment
Unit
Typ
Min
Max
(1)
Push Pull or
Open Drain mode,
I =8mA,
OL
Output Low Level
P4[7:6]-P6[5:4]
0.4
V
V
(3)
EMR1.BSZ bit = 1
V
OL
Push Pull or
Open Drain mode,
Output Low Level
All pins except OSCOUT
0.4
300
450
I
=2mA
OL
Weak Pull-up Current
Bidirectional
Weak Pull-up mode
= 0V
P2[7:4]-P2[1:0]-P3[7:0]
P4[7:5]-P4[3:1]-P5.3-P6[7:6]-P6[3:0]-
P7[7:0]-P8[7:0]-P9[7:0]
50
100
220
µA
µA
V
IN
I
WPU
Bidirectional
Weak Pull-up mode
Weak Pull-up Current
P6[5:4]-AS-DS-RW
100
V
= 0V
IN
Input or Tri-State mode,
0V < V < V
I
I/O Pin Input Leakage
– 1
– 1
1
1
µA
µA
LKIO
IN
DD
Input or Tri-State mode,
0V < V < V
I
I/O Pin Open Drain Input Leakage
LKIOD
IN
DD
V <V | I |< 400µA
ADC Conv.Input leakage current on ro-
bust pins
|
IN
SS, IN
6
1
µA
µA
on robust analog pin
|I
LKADC
ADC Conv.Input leakage current
V
SS≤V ≤V
IN
DD
P4[7:6]-P6[5:4]
EMR1.BSZ bit = 1
(4)
8
(3)
(3)
P4[7:6]-P6[5:4]
EMR1.BSZ bit = 0
(4)
I
Load current
2
mA
IO
All other pins except
OSCOUT
(4)
2
(5)
(4)
⎥I
⎥
Overload Current
Slew Rate Rise
Slew Rate Fall
5
mA
ns
OV
(6)
(6)
SR
20
20
30
30
R
SR
ns
F
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
(2) Value guaranteed by characterisation.
(3) For a description of the EMR1 Register - BSZ bit refer to the External Memory Interface Chapter.
(4) Value guaranteed by Design.
(5) Not tested in production, guaranteed by product characterisation. An overload condition occurs when the input voltage on any pin ex-
ceeds the specified voltage range.
(6) Indicative values extracted from design simulation, 20% to 80% on 50pF load, EMR1.BSZ bit =0.
377/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
(V
= 5 V ± 10%, T = –40° C to +125° C for Max values and 25°C for Typ values, unless otherwise
A
DD
specified)
(1)
Symbol
Parameter
Conditions
INTCLK
Typ
Max
Unit
CPU running with code execution
from RAM memory, all peripherals
in reset state, clock input (OSCIN)
driven by external square wave.
24 MHz
45
60
mA
I
Run Mode Current
2.5 +
DDRUN
any
frequency
mA
1.8xf
/MHz
INTCLK
f
in [MHz].
INTCLK
3 TM
FLASH/E
∆I
∆I
Supply Current
(Read)
-
-
2
mA
mA
DD1
DD2
(2)
3 TM
FLASH/E
Supply Current
12
(2)
(Write/Erase)
CPU running with code execution
from FLASH memory, all peripher-
als running in a typical configura-
tion, clock input (OSCIN) driven by
a 4-MHz crystal =
Typical application
Run Mode Current
24 MHz
24 MHz
50
14
mA
I
+ ∆I
+ I
DDRUN
DD1 DD Peripherals
(Timers, CAN, etc)
22
mA
mA
I
WFI Mode Current
DDWFI
any
frequency
(3)
f
in [MHz].
0.9xf
/MHz
INTCLK
INTCLK
3 TM
FLASH/E
∆I
Supply Current
(Stand-by)
-
-
20
µA
µA
µA
DD3
(4)
Main Voltage Regu-
lator Power
Consumption
I
300
200
DDLPR
Crystal Oscillator
Power Consump-
tion
I
DDOSC
3 TM
FLASH/E
in Stand-by Mode,
Low Power WFI
Mode Current
Main Voltage Regulator ON, I
DDL-
I
4MHz / 32
550
1000
µA
µA
DDLPWFI
+ I
+ I
DD (Standard Timer in
PR
DDOSC
real time clock mode)
3 TM
FLASH/E
in Power-Down
Mode, Main Voltage Regulator
OFF, Standard Timer in Real Time
Clock mode
I
RTC Mode Current
HALT Mode Cur-
4MHz / 32
-
250
5
DDRTC
I
25
µA
µA
µA
(5)
DDHALT
rent
All I/O ports are configured in out-
put push-pull mode with no DC
load
STOP Mode Cur-
(3)
I
see Figure 159
300
(3)
DDSTOP
rent
Input Transient I
DD
I
-
(6)
DDTR
Current
Note:
All I/O Ports are configured in bidirectional weak pull-up mode with no DC load, unless otherwise specified, external clock is driven by a
square wave.
(1) Unless otherwise stated, typical data are based on V = 5V. They are only reported for design guide lines not tested in production.
DD
(2) Current consumption to be added to IDD
when the FLASH memory is accessed.
RUN
(3) Value guaranteed by product characterization. Not tested in production.
(4) Current consumption to be added to IDD when the FLASH memory is in stand-by mode.
LPWFI
(5) Value guaranteed by product characterization.
(6) The I/Os draw a transient current from V when an input takes a voltage level in between V and V . This current is 0 for V <0.3V
DD
SS
DD
IN
or V >V -0.3V, it typically reaches its maximum value when V is approximatively at V /2.
IN
DD
IN
DD
378/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
Figure 159. Stop Mode Current
120
100
80
60
40
20
0
-45
0
25
45
85
125
Temperature (°C)
379/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
3 TM
FLASH / E
SPECIFICATIONS
(V = 5V ± 10%, T = –40°C to +125°C, unless otherwise specified
DD
A
Parameter
Byte Program
Min
Typ
10
Max
250
4
Unit
µs
s
128 kbytes Flash Program
64 kbytes Flash Sector Erase
128 kbytes Flash Chip Erase
Erase Suspend Latency
1.3
1.5
3
30
s
MAIN FLASH
30
s
15
µs
µs
Recovery from Power-Down
10
16 bytes Page Update
3 TM
(1)
E
30
200
ms
3 TM
(1k E
) -40°C +105°C
Flash Endurance 25°C
10000
3000
cycles
Flash Endurance
RELIABILITY
3 TM
(2)
E
Endurance
800000
15
page updates
years
Data Retention
Note:
(1) The maximum value depends on the number of E3 cycles/sector as shown in Figure 160. This maximum value corresponds to the worst
3 TM
3 TM
case E
page update, 1 of 4 consecutive write operations at the same E
address (refer to AN1152). In any case, the page update
operation starts with the write operation of the data (160 µs max). Then, one of the 4 erase operations of the unused sector may be per-
formed, leading to the worst case.
3 TM
(2) Relational calculation between E
Note (ref. AN1152).
page updates and single byte cycling is provided in a dedicated STMicroelectronics Application
Figure 160. Evolution of Worst Case E3 Page Update Time
Page Update Max
300
T =125°C
A
200
100
T =105°C
A
T =25°C
A
80
400
800
k page updates
380/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
highly dependent on the user application and the
software in particular.
Functional EMS (Electro Magnetic Susceptibil-
ity)
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Based on a simple application running on the
product, the product is stressed by two electro
magnetic events until a failure occurs.
Software recommendations:
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
■ FTB: A Burst of Fast Transient voltage (positive
– Critical Data corruption (control registers...)
Prequalification trials:
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A device reset allows normal operations to be re-
sumed.
Designing hardened software to avoid noise
problems
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be improved to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Level
Unit
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
=4MHz
OSC
DD
A
V
>1.5
kV
FESD
Fast transient voltage burst limits to be applied
V
=5V, T =+25°C, f =8MHz
DD
A
OSC
V
through 100pF on V and V pins to induce a func-
>1.5
kV
FFTB
DD
DD
conforms to IEC 1000-4-4
tional disturbance
Electro Magnetic Interference (EMI)
Based on a simple application running on the
product, the product is monitored in terms of emis-
sion. This emission test is in line with the norm
SAE J 1752/3 which specifies the board and the
loading of each pin.
Max vs.
[f /f ]
OSC CPU
Unit
Monitored
Frequency Band
Symbol
Parameter
Conditions
4/10MHz
13
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
V
=5V, T =+25°C,
A
PQFP100 14x20 package
conforming to SAE J 1752/3
DD
25
dBµV
S
Peak level
EMI
24
3.5
-
Notes:
1. Data based on characterization results, not tested in production.
381/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
EMC CHARACTERISTICS (Cont’d)
Absolute Maximum Ratings (Electrical Sensi-
tivity)
Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
200
A
ESD(MM)
Notes:
1. Data based on characterization results, not tested in production.
Static and Dynamic Latch-Up
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
Electrical Sensitivities
1)
Symbol
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
A
LU
T =+85°C
A
T =+125°C
A
V
=5.5V, f
=4MHz, T =+25°C
OSC A
DLU
A
DD
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
382/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
EXTERNAL INTERRUPT TIMING TABLE
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
N°
A
Load
Value
Unit
Symbol
Parameter
Formula
≥Tck+10
≥Tck+10
≥Tck+10
≥Tck+10
Min
50
1
2
3
4
TwINTLR
TwINTHR
TwINTHF
TwINTLF
Low Level Minimum Pulse Width in Rising Edge Mode
High Level Minimum Pulse Width in Rising Edge Mode
High Level Minimum Pulse Width in Falling Edge Mode
Low Level Minimum Pulse Width in Falling Edge Mode
ns
ns
ns
ns
50
50
50
Note:
The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period.
The value in the right hand two columns shows the timing minimum and maximum for an internal clock at 24MHz (INTCLK).
Measurement points are V for positive pulses and V for negative pulses.
IH
IL
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 7is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
EXTERNAL INTERRUPT TIMING
Rising Edge Detection
INTn
Falling Edge Detection
n = 0-7
WAKE-UP MANAGEMENT TIMING TABLE
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Value
Unit
N°
Symbol
Parameter
Formula
≥Tck+10
≥Tck+10
≥Tck+10
≥Tck+10
Min
50
1
2
3
4
TwWKPLR
TwWKPHR
TwWKPHF
TwWKPLF
Low Level Minimum Pulse Width in Rising Edge Mode
High Level Minimum Pulse Width in Rising Edge Mode
High Level Minimum Pulse Width in Falling Edge Mode
Low Level Minimum Pulse Width in Falling Edge Mode
ns
ns
ns
ns
50
50
50
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period.
The value in the right hand two columns show the timing minimum and maximum for an internal clock at 24MHz (INTCLK).
The given data are related to Wake-up Management Unit used in External Interrupt mode.
Measurement points are V for positive pulses and V for negative pulses.
IH
IL
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
WAKE-UP MANAGEMENT TIMING
Rising Edge Detection
Falling Edge Detection
WKUPn
n = 0-15
383/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
RCCU CHARACTERISTICS
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
V
RESET Input High Level
RESET Input Low Level
Input Voltage Range
Input Threshold
Input Threshold
0.75 x V
– 0.3
– 1
V
V
IHRS
DD
V
0.25 x V
ILRS
DD
V
V
+ 0.3
DD
V
IRS
(2)
V
RESET Input Hysteresis
RESET Pin Input Leakage
1
V
HYRS
LKRS
I
0V < V < V
1
µA
IN
DD
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
(2) Value guaranteed by design.
RCCU TIMING TABLE
(V = 5V ± 10%, T = –40°C to +125°C, f
= 24 MHz, unless otherwise specified)
DD
A
INTCLK
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
(2)
t
t
RESET Input Filtered Pulse
RESET Input Non Filtered
Pulse
50
ns
FRS
20
µs
(2)
NFR
(3)
t
RESET Phase duration
20400
T
T
RSPH
osc
osc
DIV2 = 0
DIV2 = 1
10200
20400
t
STOP Restart duration
STR
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
production.
A
DD
(2) To be valid, a RESET pulse must exceed t
. All reset glitches with a duration shorter than t
will be filtered
NFR
FRS
(3) Depending on the delay between rising edge of RESET pin and the first rising edge of CLOCK1, the value can differ from the typical value
for +/- 1 CLOCK1 cycle.
Legend: T
= Crystal Oscilllator Clock (CLOCK1) period.
osc
BOOTROM TIMING TABLE
(1)
Symbol
Parameter
Conditions
= 4MHz
Typ Value
Unit
BOOTROM Execution Duration
(see Figure 65 on page 136)
t
f
33
ms
(2)
BRE
OSC
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production
(2) Refer to AN1528 for more details on BOOTROM code.
384/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
PLL CHARACTERISTICS
(V = 5 V ± 10%, T = –40° C to +125° C, f = 24 MHz, unless otherwise specified)
DD
A
INTCLK
Value
Symbol
Parameter
Unit
(1)
Min
3
Typ
Max
5
F
Crystal Reference Frequency
VCO Operating Frequency
Lock-in Time
MHz
MHz
XTL
F
6
24
VCO
(2)
(2)
T
350
1000
1200
T
osc
PLK
(2)
(2)
PLL Jitter
0
ps
PLL Jitter Impact on applicative
500kHz signal (CAN, SCI, TIMERS)
0.2
%
(2)
(2)
F
PLL free running mode Frequency
10
50
250
kHz
PLLFREE
Note:
(1) Unless otherwise stated, typical data are based on T = 25°C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
(2) Value guaranteed by design.
Legend: Tosc = Crystal Oscilllator Clock (CLOCK1) period.
385/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
OSCILLATOR CHARACTERISTICS
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
Symbol
Parameter
Comment
Unit
(1)
Min
Typ
Max
Fundamental mode crystal or ex-
ternal clock applied to OSCOUT
f
Crystal Frequency
3
5
MHz
OSC
(2)
(2)
g
Oscillator Transconductance
Clock Input High Level
Clock Input Low Level
Oscillator Start-up Time
1.2
1.5
mA/V
V
m
(2)
V
External Clock
External Clock
2
V
+ 0.3
DD
IHCK
(2)
V
-0.3
0.4
V
ILCK
STUP
LOAD
(2)
T
5
ms
µA
kΩ
mV
I
100
128
R
90
180
POL
OSC
(2)
V
Oscillation Level
600
Note:
(1) Unless otherwise stated, typical data are based on T = 25° C and V = 5V. They are only reported for design guide lines not tested in
A
DD
production.
(2) Value guaranteed by design.
386/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
EXTERNAL BUS TIMING TABLE (MC=1)
(V = 5V ± 10%, T = –40°C to +125°C, C
= 0 to 50pF
DD
N°
A
Load
Value (see note)
Symbol
Parameter
Unit
Formula
Min
160
10
Max
1
2
3
4
5
6
7
8
9
TsA (ALE)
ThALE (A)
TwALE
Address Set-up Time before ALE ↓
Address Hold Time after ALE ↓
ALE High Pulse Width
Tck*Wa+TckH - 48
TckL - 31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tck*Wa+TckH - 58
0
150
0
TdAz (OEN)
TdOEN(Az)
TwOEN
Address Float (P0) to OEN ↓
P0 driven after OEN ↑
TckL - 13
29
OEN Low Pulse Width
Tck*Wd+TckH - 36
Tck*Wd+TckH - 36
Tck*Wd+TckH - 44
0
172
172
TwWEN
WEN Low Pulse Width
TdOEN (DR)
ThDR (OEN)
OEN ↓ to Data Valid Delay
Data hold time after OEN ↑
Address (A21:A8) hold time after OEN ↑
Address (A21:A8) hold time after WEN ↑
Address (A21:A0) valid to OEN ↑
Address (A21:A0) valid to WEN ↑
Data Set-up time before WEN ↑
Data Hold Time after WEN ↑
ALE ↑ to WEN ↑ Delay
164
0
0
10 ThOEN(A)
11 ThWEN(A)
12 TvA(OEN)
0
0
0
Tck (Wd+Wa+1.5) - 76
Tck (Wd+Wa+1.5) - 44
Tck*Wd+TckH - 158
TckL - 37
382
414
50
5
13 TvA(WEN)
14 TsD (WEN)
15 ThWEN(DW)
16 TdALE (WEN)
17 TdALE (OEN)
Tck (Wd+Wa+1.5) - 54
Tck (Wd+Wa+1.5) - 50
404
408
ALE ↑ to OEN ↑ Delay
Notes:
The expressions in the “Formula” column show how to calculate the typical parameter value depending on the CPU clock
period and the number of inserted wait cycles. The values in the Min column give the parameter values for a CPU clock
at 12MHz and two wait states for T1 and T2.
For certain versions of the ST92F150, the external bus has high-drive capabilities.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
= 2*OSCIN period when OSCIN is divided by 2;
= OSCIN period / PLL factor when the PLL is enabled
TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse
width)
TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse
width)
P = clock prescaling value (=PRS; division factor = 1+P)
Wa = wait cycles on ALE; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT)
Wd = wait cycles on OEN and WEN ; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT)
387/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
EXTERNAL BUS TIMING
CPUCLK
PORT9/1
A21 - A8
12
PORT0
(READ)
D7-D0 IN
A7-A0
1
2
9
16
8
ALE
3
4
17
OEN
(READ)
6
7
5
13
10
11
WEN
(WRITE)
14
15
PORT0
(WRITE)
A7-A0
D7-D0 OUT
Note : OEN stays high for the whole write cycle and WEN stays high for the whole read cycle.
388/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
WATCHDOG TIMING TABLE
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, Push-pull output configuration,
INTCLK
DD
A
Load
unless otherwise specified)
Value
N°
Symbol
Parameter
Unit
Formula
4 x (Psc+1) x (Cnt+1) x Tck
(Psc+1) x (Cnt+1) x T
Min
Max
167
ns
s
2.8
1
TwWDOL
WDOUT Low Pulse Width
333
167
ns
ns
s
WDIN
4 x (Psc+1) x (Cnt+1) x Tck
2.8
2
TwWDOH
WDOUT High Pulse Width
(Psc+1) x (Cnt+1) x T
≥ 4 x Tck
333
167
167
ns
ns
ns
WDIN
3
4
TwWDIL
TwWDIH
WDIN High Pulse Width
WDIN Low Pulse Width
≥ 4 x Tck
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
watchdog prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and
maximum prescaler value and minimum and maximum counter value.
Measurement points are V or V for positive pulses and V or V for negative pulses.
OH
IH
OL
IL
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
Psc = Watchdog Prescaler Register content (WDTPR): from 0 to 255
Cnt = Watchdog Couter Registers content (WDTRH,WDTRL): from 0 to 65535
T
= Watchdog Input signal period (WDIN), TWDIN ≥ 8 x Tck
WDIN
WATCHDOG TIMING
389/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
STANDARD TIMER TIMING TABLE
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, Push-pull output configuration,
DD
A
Load
INTCLK
unless otherwise specified)
Value
N°
Symbol
Parameter
Unit
Formula
4 x (Psc+1) x (Cnt+1) x Tck
(Psc+1) x (Cnt+1) x T
Min
Max
167
ns
s
2.8
(1)
1
TwSTOL
STOUT Low Pulse Width
(1)
ns
ns
s
STIN
167
4 x (Psc+1) x (Cnt+1) x Tck
2.8
2
TwSTOH
STOUT High Pulse Width
(1)
(1)
(1)
(1)
(Psc+1) x (Cnt+1) x T
≥ 4 x Tck
ns
ns
ns
STIN
(1)
(1)
3
4
TwSTIL
TwSTIH
STIN High Pulse Width
STIN Low Pulse Width
≥ 4 x Tck
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
standard timer prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and
maximum prescaler value and minimum and maximum counter value.
Measurement points are V or V for positive pulses and V or V for negative pulses.
OH
IH
OL
IL
(1) On this product STIN is not available as Alternate Function but it is internally connected to a precise clock source directly derived from the
crystal oscillator. Refer to RCCU chapter for details about clock distribution.
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
Psc = Standard Timer Prescaler Register content (STP): from 0 to 255
Cnt = Standard Timer Counter Registers content (STH,STL): from 0 to 65535
T
= Standard Timer Input signal period (STIN) , TSTIN ≥ 8 x Tck
STIN
STANDARD TIMER TIMING
390/426
1
ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
EXTENDED FUNCTION TIMER EXTERNAL TIMING TABLE
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
Unit
N° Symbol
Parameter
Formula
≥ 2 x Tck + 10
≥ 2 x Tck + 10
≥ 2 x Tck + 10
≥ 2 x Tck + 10
≥ 4 x Tck + 10
≥ 2 x Tck x Prsc +10
Min
52
1
2
3
4
5
6
Tw
Tw
External Clock low pulse width (EXTCLK)
External Clock high pulse width (EXTCLK)
Input Capture low pulse width (ICAPx)
Input Capture high pulse width (ICAPx)
ns
ns
ns
ns
ns
ns
PEWL
52
PEWH
Tw
Tw
52
PIWL
PIWH
ECKD
52
Tw
Tw
Distance between two active edges on EXTCLK
Distance between two active edges on ICAPx
177
177
EICD
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
standard timer prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, and minimum
prescaler factor (=2).
Measurement points are V for positive pulses and V for negative pulses.
IH
IL
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
Prsc = Precsaler factor defined by Extended Function Timer Clock Control bits (CC1,CC0) on control register CR2 (values: 2,4,8).
EXTENDED FUNCTION TIMER EXTERNAL TIMING
1
2
EXTCLK
5
3
4
ICAPA
ICAPB
6
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
MULTIFUNCTION TIMER EXTERNAL TIMING TABLE
(V = 5V 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
Value
N° Symbol
Parameter
Unit Note
Formula
Min
n x 42
n x 42
125
Max
(1)
(1)
1
2
3
4
Tw
External clock/trigger pulse width
External clock/trigger pulse distance
Distance between two active edges
Gate pulse width
n x Tck
n x Tck
3 x Tck
6 x Tck
-
-
-
-
ns
ns
ns
ns
CTW
Tw
Tw
CTD
AED
Tw
250
GW
LBA
Distance between TINB pulse edge and the fol-
lowing TINA pulse edge
(2)
5
6
Tw
Tck
42
0
-
-
ns
ns
Distance between TINA pulse edge and the fol-
lowing TINB pulse edge
(2)
(2)
Tw
LAB
7
8
Tw
Distance between two TxINA pulses
Minimum output pulse width/distance
0
-
-
ns
ns
AD
Tw
3 x Tck
125
OWD
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
standard timer prescaler and counter programmed values.
The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz.
(1) n = 1 if the input is rising OR falling edge sensitive
n = 3 if the input is rising AND falling edge sensitive
(2) In Autodiscrimination mode
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
MULTIFUNCTION TIMER EXTERNAL TIMING
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
SCI-M TIMING TABLE
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f
= 24MHz, unless otherwise specified)
DD
A
Load
INTCLK
(1)
Value
N° Symbol
Parameter
Condition
Unit
Min
Max
1x mode
16x mode
1x mode
16x mode
1x mode
16x mode
1x mode
16x mode
f
f
/ 8
/ 4
MHz
MHz
s
INTCLK
INTCLK
F
Frequency of RxCKIN
RxCKIN shortest pulse
Frequency of TxCKIN
TxCKIN shortest pulse
RxCKIN
4 x Tck
2 x Tck
Tw
RxCKIN
s
f
f
/ 8
/ 4
MHz
MHz
s
INTCLK
INTCLK
F
TxCKIN
4 x Tck
2 x Tck
Tw
TxCKIN
s
DS (Data Stable) before
rising edge of RxCKIN
1
2
3
Ts
1x mode reception with RxCKIN
Tck / 2
ns
ns
ns
DS
TxCKIN to Data out
delay Time
1x mode transmission with external
Td
Td
2.5 x Tck
D1
clock C
< 50pF
Load
CLKOUT to Data out
delay Time
1x mode transmission with CLKOUT
350
D2
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
Note 1: Values guaranteed by product characterization, not tested in production.
SCI TIMING
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
SPI TIMING TABLE
(V = 5V ± 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
(1)
Value
N° Symbol
Parameter
Condition
Unit
Min
/ 128
Max
Master
Slave
f
f
f
/ 4
/ 2
INTCLK
INTCLK
INTCLK
f
t
SPI frequency
MHz
ns
SPI
0
Master
Slave
4 x Tck
2 x Tck
1
SPI clock period
SPI
2
3
t
Enable lead time
Enable lag time
Slave
Slave
40
40
ns
ns
Lead
t
Lag
Master
Slave
80
90
4
5
t
Clock (SCK) high time
Clock (SCK) low time
Data set-up time
ns
ns
ns
ns
ns
ns
SPI_H
Master
Slave
80
90
t
SPI_L
Master
Slave
40
40
6
t
SU
Master
Slave
40
40
7
t
Data hold time (inputs)
H
Access time (time to data active
from high impedance state)
8
t
0
120
240
A
Slave
Disable time (hold time to high im-
pedance state)
9
t
Dis
Master (before capture edge)
Slave (after enable edge)
Tck / 4
ns
ns
10
11
12
13
t
Data valid
V
120
Master (before capture edge)
Slave (after enable edge)
Tck / 4
0
ns
ns
t
Data hold time (outputs)
Rise time
Hold
Outputs: SCK,MOSI,MISO
(20% V to 70% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
t
Rise
DD
DD
L
Fall time
Outputs: SCK,MOSI,MISO
(70% V to 20% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
t
Fall
DD
DD
L
Note:
Measurement points are V , V , V and V in the SPI Timing Diagram.
OL
OH
IL
IH
(1) Values guaranteed by design.
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
SPI Master Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
1
13
12
12
13
12
SCK
(OUTPUT)
4
5
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000109
VR000110
VR000107
VR000108
SPI Master Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
1
13
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
SPI Master Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
1
13
SCK
(OUTPUT)
4
5
MISO
(INPUT)
D7-OUT
D6-OUT
D6-IN
D0-OUT
6
7
MOSI
(OUTPUT)
D7-IN
11
D0-IN
10
SPI Master Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
1
12
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
SPI Slave Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
2
1
12
3
13
11
SCK
(INPUT)
4
5
HIGH-Z
8
MISO
(OUTPUT)
D7-OUT
D6-OUT
D0-OUT
D0-IN
10
9
MOSI
(INPUT)
D7-IN
7
D6-IN
6
VR000113
SPI Slave Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
2
1
13
12
11
3
SCK
(INPUT)
4
5
MISO
(OUTPUT)
HIGH-Z
8
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000114
SPI Slave Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
2
1
13
12
3
SCK
(INPUT)
4
5
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
10
11
9
MOSI
(INPUT)
D7-IN
7
6
VR000111
SPI Slave Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
2
1
13
12
3
SCK
(INPUT)
5
4
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
10
11
9
MOSI
(INPUT)
D7-IN
D0-IN
6
7
VR000112
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
2
I C/DDC-BUS TIMING TABLE
(V = 5V 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Protocol Specifications
2
2
Symbol
Parameter
Formula
Standard I C
Fast I C
Min
2.5
0
Unit
Min
2.5
0
Max
Max
f
f
Internal Frequency (Slave Mode)
SCL clock frequency
MHz
kHz
INTCLK
100
400
SCL
Bus free time between a STOP and
START condition
T
T
4.7
1.3
0.6
µs
µs
BUF
SCL clock high period
4.0
4.7
HIGH
Standard Mode
SCL clock low period
T
µs
LOW
1.3
0.6
Fast Mode
Hold time START condition. After this
period, the first clock pulse is generated
T
T
T
+ Tck
LOW
4.0
4.7
µs
µs
HD:STA
SU:STA
Set-up time for a repeated START condi-
tion
T
+ T
LOW
HIGH
HD:STA
0.6
– T
FREQ[2:0] = 000
FREQ[2:0] = 001
FREQ[2:0] = 010
FREQ[2:0] = 011
3 x Tck
4 x Tck
4 x Tck
10 x Tck
(1;2)
(1;2)
(1;3)
T
T
Data hold time
0
0
0.9
µs
HD:DAT
SU:DAT
Data set-up time
(Without SCL stretching)
T
– T
HD:DAT
LOW
(1)
100
FREQ[2:0] = 000
Data set-up time
7 x Tck
15 x Tck
15 x Tck
31 x Tck
(1)
250
ns
FREQ[2:0] = 001
(With SCL stretch-
FREQ[2:0] = 010
ing)
FREQ[2:0] = 011
(1)
(1)
(1)
T
T
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
1000
300
20+0.1Cb
20+0.1Cb
ns
ns
R
F
(1)
(1)
4.0
T
+ T
(1)
LOW
HIGH
T
Set-up time for STOP condition
Capacitive load for each bus line
0.6
ns
SU:STO
– T
HD:STA
Cb
400
400
pF
Note:
(1) Value guaranteed by design.
(2) The ST9 device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the fall-
ing edge of SCL
(3) The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal
Legend:
Tck = INTCLK period = Crystal Oscillator Clock period when CLOCK1 is not divided by 2;
2 x Crystal Oscillator Clock period when CLOCK1 is divided by 2;
Crystal Oscillator Clock period x PLL factor when the PLL is enabled.
Cb = total capacitance of one bus line in pF
2
FREQ[2:0] = Frequency bits value of I C Own Address Register 2 (I2COAR2)
2
I C TIMING
SDA
t R
t F
t HD:STA
t SP
t BUF
t LOW
SCL
t HD:STA
t SU:STO
t HD:DAT
t HIGH
t SU:DAT
t SU:STA
P
S
Sr
P
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
2
I C/DDC-BUS TIMING TABLE (Cont’d)
The following table gives the values to be written in
the I2CCCR and I2CECCR registers to obtain the
2
required I C SCL line frequency.
Table 70. SCL Frequency Table
I2CCCR Value
f
=12 MHz
f
=24 MHz.
CPU
CPU
f
SCL
V
= 5 V
DD
(kHz)
R =3.3kΩ
R =4.7kΩ
R =3.3kΩ
R =4.7kΩ
P
P
P
P
I2CECCR I2CCCR I2CECCR I2CCCR I2CECCR I2CCCR I2CECCR I2CCCR
400
300
200
100
50
0
0
0
0
0
86h
89h
90h
36h
72h
0
0
0
0
0
85h
89h
8Fh
36h
72h
0
0
0
0
0
8Fh
95h
A2h
71h
64h
0
0
0
0
1
8Eh
94h
A2h
70h
64h
Legend:
R = External pull-up resistance
P
2
f
= I C speed
SCL
NA = Not achievable
Note:
– For speeds around 200 kHz, achieved speed can have ±5% tolerance
– For other speed ranges, achieved speed can have ±2% tolerance
The above variations depend on the accuracy of the external components used.
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
J1850 BYTE LEVEL PROTOCOL DECODER TIMING TABLE
(V = 5V 10%, T = –40°C to +125°C, C
= 50pF, f = 24MHz, unless otherwise specified)
INTCLK
DD
A
Load
Value
Symbol
Parameter
Receive Mode
Transmission Mode
Unit
Note
Min
0
Max
≤ 7
Nominal
-
(1)(2)
T
Symbols Filtered
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
F
(1)(2)
T
T
T
T
T
T
T
T
T
T
T
T
Invalid Bit Detected
Passive Data Bit “0”
Active Data Bit “0”
Passive Data Bit “1”
Active Data Bit “1”
Short Normalization Bit
Long Normalization Bit
Start Of Frame Symbol
End Of Data Symbol
End Of Frame Symbol
Break Symbol
> 7
≤ 34
≤ 96
≤ 163
≤ 163
≤ 96
≤ 96
≤ 163
≤ 239
≤ 239
-
-
IB
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
(1)(2)(3)
> 34
> 96
> 96
> 34
> 34
> 96
> 163
> 163
> 239
> 239
> 280
64
P0
128
128
64
A0
P1
A1
64
NBS
NBL
SOF
EOD
EOF
BRK
IDLE
128
200
200
280
300
300
-
Idle Symbol
-
Note:
(1) Values obtained with internal frequency at 24 MHz (INTCLK), with CLKSEL Register set to 23.
(2) In Transmission Mode, symbol durations are compliant to nominal values defined by the J1850 Protocol Specifications.
(3) All values are reported with a precision of ±1 µs.
J1850 PROTOCOL TIMING
T IDLE
T SOF
T P0 T A0
T P1 T A1
T EOD
T NBS
T EOF
VPWO
T IDLE
T EOF
T SOF
T P0 T A0
T P1 T A1
T EOD
T NBL
VPWO
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T , unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion range voltage
Analog Input Voltage
Conditions
Min
Typ
Max
Unit
MHz
V
f
1
4
ADC
(2)
V
AV
AV
DD
AIN
SS
V
-0.2
AV +0.2
AINx
DD
(3)
R
External source impedance
10
kΩ
pF
kΩ
AIN
ADC
ADC
STAB
(3,4)
C
R
Internal sample and hold capacitor
Analog input pin impedance
6
1.7
10
t
Stabilization time after ADC enable
Conversion time (Sample+Hold)
µs
f
= 4 MHz
7
ADC
t
- Sample capacitor loading time
- Hold conversion time
8
20
ADC
1/f
ADC
(4)
I
VDDA input current
1
mA
VDDA
Figure 161. Typical Application with ADC
V
DD
R
AIN
AINx
V
AIN
ADC
C
I
LKADC
IO
~2pF
1µA
V
DD
AV
AV
DD
0.1µF
SS
Notes:
1. Unless otherwise specified, typical data is based on T =25°C and V -V =5V. These values are given only as design
A
DD SS
guidelines and are not tested.
2. V may exceed A or A . However the conversion result in these cases will be 0000h or FFC0h respectively.
VDD
AIN
VSS
3. Any external serial impedance will downgrade the ADC accuracy (especially for resistance greater than 10 kΩ). Data
based on characterization results, not tested in production.
4. Value guaranteed by design.
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS
10-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy (V =5V+/-10%, T =-40°C to +125°C)
DD
A
1)
Symbol
Parameter
Conditions
Guaranteed
Guaranteed
Typ
Max
Unit
2)
2)
Monotonicity
No missing codes
Total unadjusted error
3)
|Et|
1.5
1
6
3)
|Eo|
|Eg|
|Ed|
|El|
Offset error
5.5
6
3)
Gain Error
f
= 4MHz
1.5
0.5
0.5
LSB
ADC
3)
Differential linearity error
1.5
1.5
3)
Integral linearity error
1. Typical data is based on T =25°C, Vdd=5V
A
2. Monotonicity and No Missing Codes are guaranteed by design.
3. Refer to Figure 162. for the definition of these parameters.
Figure 162. ADC Accuracy Characteristics
Digital Result DiHR/DiLR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
1023
1022
1021
(3) End point correlation line
AVDD – AVSS
1LSB
= -----------------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
AV
AV
SS
DD
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ST92F124/F150/F250 - GENERAL INFORMATION
12 GENERAL INFORMATION
12.1 ORDERING INFORMATION
Figure 163. Device Types
ST92 F 150 J D V 1 Q C
Temperature Code:
B: Automotive -40°C to 105°C
C: Automotive -40° C to 125° C
6: Standard -40° C to 85° C
Package Type:
Q: PQFP
T: TQFP
Memory Size:
2: 256K
1: 128K
9: 64K
Pin Count:
V: 100 pins
R: 64 pins
Feature 2:
C: 1 CAN
D: Dual (2) CAN
No Character: No CAN
Feature 1:
No Character: No J1850
J: J1850
ST Sub-family
Version:
F: Flash
No Character: ROM
ST Family
12.2 VERSION-SPECIFIC SALES CONDITIONS
To satisfy the different customer requirements and to ensure that ST Standard Microcontrollers will con-
sistently meet or exceed the expectations of each Market Segment, the Codification System for Standard
Microcontrollers clearly distinguishes products intended for use in automotive environments, from prod-
ucts intended for use in non-automotive environments. It is the responsibility of the Customer to select the
appropriate product for his application.
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ST92F124/F150/F250 - GENERAL INFORMATION
ORDERING INFORMATION (Cont’d)
Table 71. Supported part numbers
Program
Memory
(Bytes)
RAM
(Bytes)
Part Number
ST92F124R9TB
Package
Temperature
TQFP64
TQFP64
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C
-40°C to 105°C
ST92F150CR9TB
ST92F150CV9TB
ST92F124V1QB
ST92F124V1TB
ST92F124V1T6
64K FLASH
2K
TQFP100
PQFP100
TQFP100
TQFP100
TQFP64
4K
ST92F150CR1TB
ST92F150CV1QB
ST92F150CV1TB
ST92F150JDV1QC
ST92F150JDV1TC
ST92F250CV2TC
ST92F250CV2T6
ST92F250CV2QB
ST92F250CV2TB
128K FLASH
PQFP100
TQFP100
PQFP100
TQFP100
TQFP100
TQFP100
PQFP100
TQFP100
6K
8K
-40°C to 125°C
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C
256K FLASH
Contact ST sales office for product availability
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ST92F124/F150/F250 - GENERAL INFORMATION
12.3 PACKAGE MECHANICAL DATA
Figure 164. 64-Pin Thin Quad Flat Package
A
mm
inches
D
Dim.
A2
Min Typ Max Min Typ Max
D1
A
1.60
0.063
0.006
A1
b
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
D
16.00
14.00
16.00
14.00
0.80
0.630
0.551
0.630
0.551
0.031
3.5°
e
D1
E
E
E1
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
L
L1
L1
c
N
h
Figure 165. 100-Pin Thin Quad Flat Package
mm
inches
A
D
Dim.
Min Typ Max Min Typ Max
D1
A2
A
1.60
0.063
0.006
A1
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
e
D
16.00
14.00
16.00
14.00
0.50
0.630
0.551
0.630
0.551
0.020
3.5°
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
100
c
L1
L
1
L
h
N
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ST92F124/F150/F250 - GENERAL INFORMATION
Figure 166. 100-Pin Plastic Quad Flat Package
mm
inches
D
A
Dim.
Min Typ Max Min Typ Max
D1
D2
A2
A1
A
3.40
0.134
0.020
A1 0.25
0.50 0.010
A2 2.50 2.70 2.90 0.098 0.106 0.114
b
b
c
0.22
0.11
0.40 0.009
0.23 0.004
0.016
0.009
D
23.20
20.00
18.85
17.20
14.00
12.35
0.65
0.913
0.787
0.742
0.677
0.551
0.486
0.026
e
D1
D2
E
E
E2 E1
E1
E2
e
L
c
L
0.73 0.88 1.03 0.029 0.035 0.041
1.60 mm
0×- 7×
Number of Pins
N
100
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ST92F124/F150/F250 - GENERAL INFORMATION
12.4 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for the ST9 micro-
controller family. Full details of tools available for
the ST9 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
Tools from these manufacturers include realtime
kernel software and gang programmers.
Table 72. STMicroelectronics Development Tools
Supported Products
Emulator
Programming Board
ST92F124 (TQFP64, TQFP100)
ST92F150-EPB/EU
ST92F150-EPB/US
ST92F150-EPB/UK
ST92F150 (TQFP64, TQFP100,
PQFP100
ST92F150-EMU2
(1)
ST92F250 (TQFP100, PQFP100)
Note 1: The I²C 1 and the general purpose I/Os P3.0, P6.6 and P6.7 cannot be emulated by this emulator.
Since the upper 128Kbytes of Flash memory are emulated with a RAM memory, the programming oper-
ations on the F4 and F5 Flash sectors are not emulated.
12.4.1 Socket and Emulator Adapter Information
For information on the type of socket that is sup-
plied with ST92F150-EMU2, refer to the suggest-
ed list of sockets in Table 73.
Note: Before designing the board layout, it is rec-
ommended to check the overall dimensions of the
socket as they may be greater than the dimen-
sions of the device.
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet (available from www.ya-
maichi.de for TQFP100 and PQFP100 and from
www.cabgmbh.com for TQFP64).
Table 73. Suggested List of Socket Types
Device
Socket (supplied with ST92F150-
Emulator Adapter (supplied with
ST92F150-EMU2)
EMU2)
TQFP64 14 x14
TQFP100 14 x14
PQFP100 14 x 20
CAB 3303262
CAB 3303351
YAMAICHI IC149-100-*25-*5
YAMAICHI IC149-100-*14-*5
YAMAICHI ICP-100-5
YAMAICHI ICP-100-4-4
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ST92F124/F150/F250 - KNOWN LIMITATIONS
13 KNOWN LIMITATIONS
Limitations described in this section apply to all sil-
icon revisions. Additional limitations exist on spe-
cific silicon revisions identified by the following
trace codes:
Please contact your nearest sales office for further
information.
– Gxxxxxxxx1 (ST92F124)
– AxxxxxxxxZ (ST92F150)
– AxxxxxxxxY (ST92F150)
– AxxxxxxxxA (ST92F250)
13.1 ST92F124/F150/F250 KNOWN LIMITATIONS
13.1.1 FLASH ERASE SUSPEND LIMITATIONS
13.1.1.1 Description
6 in the FESR1 register) is set although no pro-
gram error occurred.
13.1.1.2 Workaround
In normal operation, the FSUSP bit (bit 2 in the
FCR register) must be set to suspend the current
Sector Erase operation in Flash memory in order
to access a sector not being erased. The Flash
sector erase operation is done in 3 different steps:
After a Sector Erase suspend operation, the soft-
ware must check the status register to detect if an
erase error occurred (the corresponding sector
must be discarded). Then the software must reset
the FEERR bit. This automatically resets the flash
status register.
1. Program all addresses to 0 on selected sectors
2. Erase and erase verify
Whatever the state of the PGER bit at the end of
the erase operation, it will not impact the applica-
tion and an erase error is still detected.
3. Reprogramming
If the erase suspend is performed during Steps 1
and 2, the flash works correctly. If the erase sus-
pend is performed during Step 3, the PGER bit (bit
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KNOWN LIMITATIONS (Cont’d)
13.1.2 FLASH CORRUPTION WHEN EXITING
STOP MODE
Workaround
Description
Description
Under very specific conditions, the first read per-
formed in flash memory by the core when exiting
stop mode may be corrupted.
In ST92F124/F150/F250 datasheet, there is a
warning in the WUCTRL register description:
“In order to avoid to execute register write instruc-
tions after a correct STOP bit setting sequence
and before entering the STOP mode, it is manda-
tory to execute 3 NOP instructions after the STOP
bit setting sequence.”
Impact on application
As this first read is an opcode, this corruption may
lead to an unpredictable behavior of the applica-
tion.
The workaround is to replace these 3 NOPs by the
following assembly code:
nop
ldw RRx,0
In a C language software, implement the following
code.
RRx is an unused register in the register file.
Declare a dummy variable in the register file (for
example in RR0 16-bit register)
Implementation
#pragma register_file Dummy_16bit_data
volatile unsigned int Dummy_16bit_data;
0
And replace the actual STOP bit setting sequence
(specified in datasheet):
spp(WU_PG);
WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop;
WU_CTLR = WUm_wuit | WUm_id1s;
WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop;
asm("nop");
asm("nop");
asm("nop");
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KNOWN LIMITATIONS (Cont’d)
By:
spp(WU_PG);
WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop;
WU_CTLR = WUm_wuit | WUm_id1s;
WU_CTLR = WUm_wuit | WUm_id1s | WUm_stop;
asm(“nop”);
Dummy_16bit_data = 0;
Compiled code (with –O2 optimization option) and hexa is:
C language
Assembly
Hexa
Comment
WU_CTLR = WUm_wuit |
WUm_id1s | WUm_stop;
ld @WU_CTLR, #7
F5 F9 07
WU_CTLR = WUm_wuit |
WUm_id1s;
ld @WU_CTLR, #3
F5 F9 03
The CORE executes the
following NOP and
prefetch the 2 following
bytes (BF and 00)
WU_CTLR = WUm_wuit |
WUm_id1s | WUm_stop;
ld @WU_CTLR, #7
nop
F5 F9 07
FF
NOP
The two first bytes fetch
in flash after wake up are
00 00
Dummy_16bit_data = 0;
ldw RR0,#0
BF 00 00 00
RR0 is always filled with
00 RR0 is not used in the
software
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13.1.3 I2C LIMITATIONS
Limitations
Description
Start condition ignored
Missing bus error
Mode
Mustimaster mode
Section 13.1.3.1
Section 13.1.3.2
Section 13.1.3.3
Section 13.1.3.4
Section 13.1.3.5
Section 13.1.3.6
Master transmitter mode
Transmitter mode (Master and Slave)
Mustimaster mode
Multimaster mode
AF bit (acknowledge failure flag)
BUSY bit
ARLO (arbitration lost)
BUSY flag
All
will not be set and transfer will continue however
the BUSY flag will be reset.
13.1.3.1 Start condition ignored in multimaster
mode
Description
Multimaster Mode:
Normally the BERR bit would be set whenever un-
authorized transmission takes place while transfer
is already in progress. However, an issue will arise
if an external master generates an unauthorized
Start or Stop while the I2C master is on the first or
second pulse of a 9-bit transaction.
In multimaster configurations, if the ST9 I2C re-
ceives a START condition from another I2C
master after the START bit is set in the I2CCR reg-
ister and before the START condition is generated
by the ST9 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST9
master will receive a NACK from the other device.
Workaround
Workaround
Single Master Mode:
On reception of the NACK, ST9 can send a re-start
and Slave address to re-initiate communication.
Slave devices should issue a NACK when they re-
ceive a misplaced Start or Stop. The reception of a
NACK or BUSY by the master in the middle of
communication gives the possibility to reinitiate
transmission.
13.1.3.2 Missing BUS error in master
transmitter mode
Description
Multimaster Mode:
BERR will not be set if an error is detected during
the first or second pulse of each 9-bit transaction.
It is possible to work around the problem by polling
the BUSY bit during I2C master mode transmis-
sion. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag
being set.
Single Master Mode:
If a Start or Stop is issued during the first or
second pulse of a 9-bit transaction, the BERR flag
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KNOWN LIMITATIONS (Cont’d)
13.1.3.3 AF bit (acknowledge failure flag) in
transmitter mode (slave and master)
13.1.3.5 ARLO (arbitration lost) flag in
multimaster mode
Description
Description
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of the
transmission, the AF flag will be set again, thus
possibly generating a new interrupt.
In a Multimaster environment, when the interface
is configured in Master Receive mode it does not
perform arbitration during the reception of the Ac-
knowledge Bit. Mishandling of the ARLO bit from
the I2CSR2 register may occur when a second
master simultaneously requests the same data
from the same slave and the I2C master does not
acknowledge the data. The ARLO bit is then left at
0 instead of being set.
Workaround
Software must ensure either that the SCL line is
back at 0 before reading the SR2 register, or be
able to correctly handle a second interrupt during
the 9th pulse of a transmitted byte.
Workaround
None
13.1.3.6 BUSY flag gets cleared when BUS
error occurs
13.1.3.4 BUSY flag in multimaster mode
Description
Description
BUSY bit gets cleared when the BUS error occurs
but the bus is actually BUSY (SCL line shows CLK
pulses). Contradictory, M/SL bit is unaffected on
BUS error
The BUSY flag is NOT updated when the interface
is disabled (PE=0). This can have consequences
when operating in Multimaster mode; i.e. a second
active I2C master commencing a transfer with an
unset BUSY bit can cause a conflict resulting in
lost data.
Workaround
If a Bus Error occurs, a Stop or a repeated Start
condition should be generated by the Master to re-
synchronize communication, get the transmission
acknowledged and the bus released for further
communication
Workaround
Check that the I2C is not busy before enabling the
I2C Multimaster cell.
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KNOWN LIMITATIONS (Cont’d)
13.1.4 SCI-A AND CAN INTERRUPTS
Description
A received data is indicated by the RDRF (Read
Data Ready Flag) bit in the SCISR register (R240,
page 26). This status bit is evaluated at the end of
the stop bit. If the RWU bit is in the set state at the
end of the stop bit, the data is not loaded in the
data register and the RDRF bit is not set.
SCI-A interrupt (I0 channel) and CAN interrupts
(channels E0, E1, F0, F1, G0, G1, H0, H1) do not
respond when the CPUCLK is prescaled (MODER
register).
On the contrary, if the RWU bit is in the reset state
at the end of the stop bit the data is loaded in the
data register and the RDRF bit is set.
Workaround
13.1.5.2 Limitation Description
Avoid using CPU prescaler when SCI-A and/or
CAN interrupts are used in the application.
The SCICR2 also contains the following configura-
tion bits: Interrupt Enable, Transmitter Enable, Re-
ceiver Enable and Send Break.
13.1.5 SCI-A MUTE MODE
13.1.5.1 Mute Mode Description
When the value of one of these bits is modified by
software, the SCICR2 register is read, its value is
modified and reloaded in the SCICR2 register. If
the SCI-A is in Mute mode during the read opera-
tion (RWU=1) and if an address mark event occurs
(resetting the RWU bit) before the write operation,
the RWU bit is set before the end of the stop bit. In
this case, the RDRF bit is not set, the data is not
received and no flag indicates the lost of the data.
The SCI can be put in Mute mode waiting for an
Idle line detection or an Address Mark detection,
and discarding all other byte transmissions. This is
done by setting the RWU (Receiver wake-up) bit in
the SCICR2 register (R244, page 26). This bit can
be reset either by software, to leave the Mute
mode, or by hardware when a wake up condition
has been reached.
Figure 1. Mute Mode Mechanism on address mark
Data Line
data
Data Line
data
RWU
RWU
RDRF
RDRF
int
ld r0,SCICR2
and r0,0x80
ld SCICR2, r0
Mute mode mechanism
Corrupted Mute mode mechanism
under an SCICR2 access
Consequence
13.1.5.3 Workaround
If you need to disable the SCI-A interrupt while it is
in Mute mode, use the global interrupt mask in the
dedicated interrupt controller, refer to Section 5.7
“Standard Interrupts” in the datasheet. Do not
change the TE, RE and SBK bits in the SCICR2
register while the SCI-A is in Mute mode.
The address byte is lost and the SCI-A is again in
Mute mode.
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KNOWN LIMITATIONS (Cont’d)
13.1.6 CAN FIFO CORRUPTION WHEN 2 FIFO
MESSAGES ARE PENDING
WHILE the bxCAN requests the transfer of a new
receive message into the FIFO (this lasts one CPU
cycle)
Description
Under certain conditions, FIFO corruption can
occur in the following cases:
THEN the internal FIFO pointer is not updated
BUT the FMP bits are updated correctly
Impact on Application:
WHEN a bxCAN RX FIFO already holds 2 mes-
sages (i.e. FMP==2)
As the FIFO pointer is not updated correctly, this
causes the last message received to be over-
written by any incoming message. This means one
message is lost as shown in the example in Figure
2 The bxCAN will not recover normal operation
until a device reset occurs.
AND the application releases the same FIFO
(with the instruction CANx_CTRL_CRFRy |=
CRF_rfom;
x=0 for the CAN_0 cell
x=1 for the CAN_1 cell
y=0 for the Receive FIFO 0
y=1 for the Receive FIFO 1 )
Figure 2. FIFO Corruption
FIFO
FMP
*
v
When the FIFO is empty, v and * point to the same location
* does not move because FIFO is full (normal operation)
Initial State
0
1
- - -
v
*
Receive Message A
Receive Message B
Receive Message C
Release Message A
A - -
v
*
A B -
2
3
v
*
A B C
v
*
2
2
A B C
v
*
D B C
Normal operation
Release Message B
and Receive Message D
v
*
D B C
* Does not move, pointer curruption
v
*
3
2
Receive Message E
Release Message C
E B C D is overwritten by E
v
*
C released
E B C
v
*
1
0
Release Message E
Release Message B
E released instead of B
E B C
v
*
* and v are not pointing to the same message
the FIFO is empty
E B C
* pointer to next receive location
v pointer to next message to be released
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KNOWN LIMITATIONS (Cont’d)
Workaround 1
:
The workaround is to replace any occurrence of
spp (CANx_CTRL_PG);
CANx_CTRL_CRFRy |= CRFR_rfom;
by:
spp(CANx_CTRL_PG);
if ((CANx_CTRL_CRFRy & 0x03) == 0x02)
while (( CANx_CTRL_CMSRy & 0x20) && (CANx_CTRL_CDGRy & 0x08));
CANx_CTRL_CRFRy |= CRFR_rfom;
x=0 for the CAN_0 cell
x=1 for the CAN_1 cell
time when the received message is loaded into the
FIFO.
y=0 for the Receive FIFO 0
y=1 for the Receive FIFO 1
We could simply wait for the end of the reception,
but this could take a long time (200µs for a 100-bit
frame at 500kHz), so we also monitor the Rx pin of
the microcontroller to minimize the time the appli-
cation may wait in the while loop.
Explanation of Workaround 1
First, we need to make sure no interrupt can occur
between the test and the release of the FIFO to
avoid any added delay.
We know the critical window is located at the end
of the frame, 6+ CAN bit times after the acknowl-
edge bit (exactly six full bit times plus the time from
the beginning of the bit to the sample point). Those
bits represent the acknowledge delimiter + the end
of frame slot.
The workaround checks if the first 2 FIFO levels
are already full (FMP = 2) as the problem happens
only in this case.
If FMP≠2 we release the FIFO immediately, if
FMP=2, we monitor the reception status of the
cell.
We know also that those 6+ bits are in recessive
state on the bus, therefore if the CAN Rx pin of the
device is at ‘0’, (reflecting a CAN dominant state
on the bus), this is early enough to be sure we can
release the FIFO before the critical time slot.
The reception status is available in the CMSR reg-
ister bit 5 (REC bit).
Note: The REC bit was called RX in olders ver-
sions of the datasheet.
Therefore, if the device hardware pin Rx is at 0
and there is a reception on going, its message will
be transferred to the FIFO only 6+ CAN bit times
later at the earliest (if the dominant bit is the ac-
knowledge) or later if the dominant bit is part of the
message.
If the cell is not receiving, then REC bit in CMSR is
at 0, the software can release the FIFO immedi-
ately: there is no risk.
If the cell is receiving, it is important to make sure
the release of the mailbox will not happen at the
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ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Figure 3. Workaround 1 in Assembler
asm (“
/*
Bytes/cycles
2/4
*/
*/
spp#48
ld
/* setCAN0_CTRLpage
/* Usespp#36forCAN1
/* ForFIFO0
/* NB:ReplaceR244withR245forFIFO1
/*
/*
/* (JRNEinstruction)
/* ifFMPisnot2thenFIFO
/* releasecanbedone
r0,R244
2/4
*/
*/
*/
*/
*/
*/
*/
and
cp
jxnz
r0,#3
r0,#2
_release
3/6
3/6
2/6
pushw RR232
srp #31
/* pushworkinggroup
/* setgroupFasworkinggroup
2/8or10
2/4
3/6or10ifjmp
3/6or10ifjmp
*/
*/
*/
*/
_whileloop:btjfr1.5,_release/* RECbitofCMSRregister
btjf r12.3,_whileloop/* RXbitofCDGRregister
_release:
popw
orR244,#32
RR232
/* setRFOMbitofCRFRregister
/* NB:ReplaceR244withR245forFIFO1
/* restorepreviousworkinggroup 2/10
3/6
*/
*/
*/
“);
We can assume a time quantum number between
8 and 25. The worst case is when the baud rate
prescaler is 0 (BRP=0) and the time quantum is 8,
ie. TS1+TS2=5. This means a CPU frequency of
8MHz and 1 Mbits/sec for the CAN communica-
tion. In this case the minimum time between the
end of the acknowledge and the critical period is
52 CPU cycles (48 for the 6 bit times + 4 for the
At low speed, this time could represent a long
delay for the application, therefore it makes sense
to evaluate how frequently this delay occurs.
In order to reach the critical FMP=2, the CAN node
needs to receive 2 messages without servicing
them. Then in order to reach the critical window,
the cell has to receive a third one and the applica-
tion has to release the mailbox at the same time, at
the end of the reception.
(PROP SEG + T
). According to the previous
Seg 1
code timing, we need less than 22 cycles from the
time we see the dominant state to the time we per-
form the FIFO release (one full loop + the actual
release) therefore the application will never re-
lease the FIFO at the critical time when this work-
around is implemented.
In the application, messages are not processed
only if either the interrupt are disabled or higher
level interrupts are being serviced.
Therefore if:
T
+ T
+ T
< 2 x T
IT CAN CAN
IT higher level
frame
IT disable
Timing analysis
the application will never wait in the workaround
: This the sum of the duration of all the
interrupts with a level strictly higher than the CAN
interrupt level
- Time spent in the workaround
T
IT higher level
Inside a CAN frame, the longest period that the Rx
pin stays in recessive state is 5 bits. At the end of
the frame, the time between the acknowledge
dominant bit and the end of reception (signaled by
T
: This is the longest time the application
IT disable
disables the CAN interrupt (or all interrupts)
REC bit status) is 8T
, therefore the max-
CANbit
imum time spent in the workaround is:
T
: This is the maximum duration between
IT CAN
8T
8T
+T
+68T
+T
.
+T
in this case or
release
the beginning of the CAN interrupt and the actual
location of the workaround
CANbit
loop
test
CANbit
CPU
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ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
T
: This is minimum CAN frame duration
CAN frame
Figure 4. Critical Window Timing Diagram
Critical window: the received
message is placed in the FIFO
CAN Frame
Acknowledge: last
dominant bit in the frame
A release is not
allowed at this time
Time to test RX pin and to
release the FIFO 4.5 µs@4MHz
Time between the end of the
acknowledge and the critical windows
- 6 full CAN bit times+ time to the sample point
approx. 13µs @ 500kBd
Figure 5. Reception of a Sequence of Frames
FMP
0
1
2
2
BUS
T
1
T
2
T
3
CAN frame
CAN frame
CAN frame
T
T
IT higher level
T
CPU
IT disable
IT CAN
If this happens, we will continue waiting in the
while loop instead of releasing the FIFO immedi-
ately. The workaround is still valid because we will
not release the FIFO during the critical period. But
the application may lose additional time waiting in
the while loop as we are no longer able to guar-
antee a maximum of 6 CAN bit times spent in the
workaround.
Side-effect of Workround 1
Because the while loop lasts 16 CPU cycles, if
≤16MHz at high baud rate, it is possible to
miss a dominant state on the bus if it lasts just one
CAN bit time and the bus speed is high enough
(see Table 74)
f
CPU
Table 74. While Loop Timing
In this particular case the time the application can
spend in the workaround may increase up to a full
CAN frame, depending of the frame contents. This
case is very rare but happens when a specific se-
quence is present on in the CAN frame.
Baud rate for possible
f
CPU
missed dominant bit
No dominant bit missed
1 MBaud
24 MHz
16 MHz
8 MHz
4 MHz
> 500 kHz
> 250 kHz
The example in Figure 6 shows reception if TCAN
f
> f
/ 16
CPU
is 12/f
and the sampling time is 16/f
.
CPU
CPU
CPU
If the application is using the maximum baud rate
and the possible delay caused by the workaround
is not acceptable, there is another workaround
which reduces the Rx pin sampling time.
Note: As can be seen from the above table, no
side effect occurs in cases when f is 16MHz or
higher and if the CAN baud rate is below 1MBaud.
CPU
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ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Workaround 2
after the acknowledge and the critical slot. If a
dominant bit is read on the bus, we can release the
FIFO immediately. This workaround has to be
written in assembly language to avoid the compiler
optimizing the test sequence.
Workaround 2 (see Figure 7) first tests that
FMP=2 and the CAN cell is receiving, if not the
FIFO can be released immediately. If yes, the pro-
gram goes through a sequence of test instructions
on the RX pin that last longer than the time be-
tween the acknowledge dominant bit and the crit-
ical time slot. If the Rx pin is in recessive state for
more than 8 CAN bit times, it means we are now
The implementation shown here is for the CAN
bus maximum speed (1MBd @ 8MHz CPU clock).
Figure 6. Reception with TCAN=12/f
and sampling time is 16/f
CPU
CPU
CAN Bus signal
R R R
D R R R D R R R D R R R D R R R D
Sampling of Rx pin
Figure 7. Workaround 2 in Assembler
asm (“
/*
Bytes/cycles
2/4
*/
spp#48
ld
/* setCAN0_CTRLpage
/* Usespp#36forCAN1
/* ForFIFO0
*/
r0,R244
2/4
*/
*/
*/
*/
*/
*/
*/
/* NB:ReplaceR244withR245forFIFO1
/*
/*
/* (JRNEinstruction)
/* ifFMPisnot2thenFIFO
/* releasecanbedone
and
cp
jxnz
r0,#3
r0,#2
_release
3/6
3/6
2/6
pushw RR232
/* pushworkinggroup
/* setgroupFasworkinggroup
/* RECbitofCMSRregister
2/8or10
2/4
3/6or10ifjmp
*/
*/
*/
srp
#31
btjf
r1.5,_release
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
r12.3,_release
r12.3,_release
r12.3,_release
r12.3,_release
r12.3,_release
r12.3,_release
r12.3,_release
r12.3,_release
r12.3,_release
r12.3,_release
r12.3,_release
/* sampleRXbitfor8bittime
/* ie.11btjfinstructions
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
3/6or10ifjmp
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
/*
/*
/*
/*
/*
/*
/*
/*
/*
_release:
orR244,#32
RR232
/* setRFOMbitofCRFR0register 3/6
/* NB:ReplaceR244withR245forFIFO1
/* restorepreviousworkinggroup 2/10
*/
*/
*/
popw
“);
417/426
1
ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
13.2 ST92F150-EMU2 EMULATION CHIP KNOWN LIMITATIONS
Additional limitations exist on Emulation chips (EMU2 emulator). These limitations correspond to those
present in AxxxxxxxxY trace codes (ST92F150). They are listed in the following table.
Section
Section 13.2.1
Section 13.2.2
Section 13.2.3
Section 13.2.4
Section 13.2.5
Section 13.2.6
Section 13.2.7
Section 13.2.8
Section 13.2.9
Section 13.2.10
Section 13.2.11
Section 13.2.12
Limitation (AxxxxxxxxY trace code)
P1 I/O PORT CHARACTERISTICS
RESET BEHAVIOUR FOR BI-DIRECTIONAL, WEAK PULL-UP PORTS
HIGH DRIVE I/Os WHEN BSZ=1
ADC PARASITIC DIODE
ADC ACCURACY VS. NEGATIVE INJECTION CURRENT
I2CECCR REGISTER LIMITATION
I2C BEHAVIOUR DISTURBED DURING DMA TRANSACTIONS
MFT DMA MASK BIT RESET
DMA DATA CORRUPTED BY MFT INPUT CAPTURE
SCI-A WRONG BREAK DURATION
LIN MASTER MODE NOT AVAILABLE ON SCI-A
LIMITATIONS ON TQFP64 PACKAGES
13.2.1 P1 I/O PORT CHARACTERISTICS
These I/Os behave in the same way following an
external, watchdog or software reset.
During reset, 5 I/Os of Port P1 are in High Imped-
ance state (Hi-Z), which corresponds to the da-
tasheet specification, however, contrary to the da-
tasheet specification, they get a Weak Pull Up
13.2.2
RESET
BEHAVIOUR
FOR
BI-
DIRECTIONAL, WEAK PULL-UP PORTS
This section applies to ports P4[1], P8[7:2] and
P9[7:0].
after the delay of 20400 clock periods (t
) fol-
RSPH
lowing a reset (external reset signal low). Refer to
Table 75.
Table 75. Reset Behaviour Table
Rev Z Behaviour
Port Behaviour
Control Register Value
Datasheet
Condition
Port
During next
20K Clock
Cycles
Hi-Z
After these
20K Clock
While RESET
is low
PxC0
PxC1
PxC2
Cycles
P1[7:3]
P4.1
Bi-Dir
Bi-Dir + WPU
P8[7:2] Bi-Dir + WPU
P9[7:0] Bi-Dir + WPU
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Bi-Dir + WPU
Bi-Dir + WPU
Bi-Dir + WPU
Bi-Dir + WPU
0
0
0
0
0
0
0
0
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
Shaded areas represent erroneous operations.
have weak pull-ups. These ports then enter Weak
Pull-up state until the user overwrites the reset
values of I/O Port Control Registers PxC0, PxC1
and PxC2.
During the reset phase (external reset signal low)
and the delay of 20400 clock periods (t
lowing a reset, these ports are in High Impedance
state, while according to the datasheet they should
) fol-
RSPH
418/426
1
ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
During reset, the risk of power consumption in the
input stage due to floating inputs is avoided by a
design feature.
The Input Port affected by this diode is the one
pointed to by the analog multiplexer of the ADC, if
the port is set up as AF analog input. When the
ADC is stopped, the multiplexer points to the first
input to be converted in a scan (i.e. the channel
pointed to by the SC[3:0] bits).
However, if the application requires pull-ups
during reset (for instance, in order to send known
logic values to external devices), external pull-ups
must be provided. When the I/O port outputs a
zero, there will be some additional power con-
sumption as these external pull-ups are not
switched off.
Workaround
In order to avoid this problem, the I/O connected to
the ADC has to be set up in any mode except AF
analog input (i.e. any combination of PxC2.. PxC0
except 111).
These ports behave in the same way following an
external, watchdog or software reset.
1. Deprogram analog input mode from the I/O port
which is pointed to by the SC[3:0] bits (start
conversion channel, b7..b4 of CLR1).
13.2.3 HIGH DRIVE I/OS WHEN BSZ=1
Description
If the BSZ bit in the EMR1 register (bit 1 of R245,
page 21) is set so as to use high-drive output
buffers for P4[7:6] and P6[5:4], all I/O ports as well
as AS, DS and RW will also use high-drive output
buffers.
For example the I/O can be reprogrammed as
an open drain output, with the data at 1. The
high impedance of the output stage then
avoids a conflict with the external voltage
source. In order to avoid potential power con-
sumption in the input buffer of this I/O,
depending on the external voltage applied to
the pin, it is wise to set the 'start conversion
channel' to a channel which carries levels
Impact On Application
P0[7:0], AS, DS and RW have the same V pa-
OH
rameter value as P6[5:4].
below 800 mV or above (V - 800 mV).
DD
P0[7:0]-P2[3:2], AS, DS and RW have the same
V
and I parameter values as the P4[7:6] and
IO
OL
Another possibility is to modify the SC[3:0]
bits so that they point to an I/O Port which is
not used as an analog input.
P6[5:4].
These I/Os using high-drive output buffers will
generate more noise than those using the
standard low-noise output buffers.
2. Next, switch off the A/D Converter.
The current in AV
will be zero, whatever the
DD
13.2.4 ADC PARASITIC DIODE
Description
logic levels on the analog inputs, and whatever the
voltage level applied to AV (between 0 and
DD
V
).
DD
A parasitic diode is present between an ADC input
and AV
.
13.2.5 ADC ACCURACY VS. NEGATIVE
INJECTION CURRENT
DD
As described in the datasheet, the user has the
possibility to switch off AV when he switches off
Description
DD
If a negative current is injected to an input pin (i.e.
input signal voltage below -0.3V), a part of this cur-
rent will be drawn from the adjacent I/Os. The fol-
lowing curve quantifies this current:
the ADC to save power consumption. However, if
AV
is connected to ground and a voltage is
DD
present on the Input Port, an increase in power
consumption can occur.
419/426
1
ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Figure 8. Impact of negative current injection on adjacent pin
350
300
Current drawn
250
from adjacent
200
pin (uA,
absolute
value)
150
100
50
0
0
5
10
15
20
25
30
Current injection (mA)
Impact on application
mode, additional bytes can be seen in the I2CDR
register.
If the adjacent I/O is used as an analog input (Port
7 and 8 only), the current drawn through the ex-
ternal resistor generates a difference in potential,
resulting in a conversion error.
Workaround
Avoid using DMA transfer while I2C peripheral is
running.
13.2.6 I2CECCR REGISTER LIMITATION
It is not possible to write to the CC7 and CC8 bits
in the I2CECCR register. These bits remain at
their reset value (0).
13.2.8 MFT DMA MASK BIT RESET
Introduction
The MultiFunction Timer is a 16-bit timer with Input
Capture and Output Compare modes. In Input
Capture mode, the timer value is saved when an
external event occurs. In Output Compare mode,
the timer changes an I/O pin level when it reaches
the Compare Register value.
Impact on application
The baudrate prescaler cannot be higher than 258
(CC8:7=0 and CC6:0=1). As a consequence, the
baudrate cannot be lower than f
=INTCLK/258
SCL
Workaround
In these two modes the event (Input Capture or
Output Compare) may generate an interrupt or re-
quest a Direct Memory Access.
None.
13.2.7 I2C BEHAVIOUR DISTURBED DURING
DMA TRANSACTIONS
– In interrupt Input Capture mode (or Output Com-
pare mode), the interrupt routine saves the coun-
ter in the RAM or the Register File (or updates
the compare register from a location in RAM or
in the Register File).
Description
If a DMA transfer occurs on SCI-M, MFT or J1850
during I2C transmission or reception, I2C periph-
eral may be disturbed.
– In DMA mode these transfers are done automat-
ically.
In transmission mode, additional bytes can be ob-
served on I2C lines (SDA and SCL). In reception
420/426
1
ST92F124/F150/F250 - KNOWN LIMITATIONS
Limitation Description
KNOWN LIMITATIONS (Cont’d)
The choice between Interrupt or DMA modes is
defined by the CP0D and CM0D bits (bit 6 and bit
3 in the IDMR register, R255 page 10/8).
If a MFT DMA request (for instance MFT1) occurs
when another peripheral DMA request is being
serviced (for instance MFT0), and if the MFT0
DMA corresponds to an End-of-Block, the MFT1
resets its DMA Mask bit even if the End-of-Block
signal is dedicated to the MFT0.
CP0D : Capture 0 DMA Mask. Capture on REG0R
DMA is enabled when CP0D = 1.
CM0D: Compare 0 DMA Mask. Compare on
CMP0R DMA is enabled when CM0D = 1.
This limitation is due to wrong End-of-Block event
management by the MFT, it does not impact the
SCI and the I2C but they can be involved in the
limitation if:
In DMA mode a DMA counter register and a DMA
address register define the location and the size of
the memory block (RAM or Reg. File) involved in
these transfers.
– First peripheral requests a DMA transfer with
End-of-Block event,
Each DMA transfer decreases the counter value.
When the counter reaches 0, an EndOfBlock
event occurs on the DMA controller. This event is
detected by the MFT which resets the CP0D or the
CM0D bit.
– Other peripherals request a DMA transfer with a
higher priority level between the same two DMA
arbitrations. As a consequence, the MFT1 DMA
request is not serviced and a DMA transfer is
lost. This is also true for a Top Level Interrupt
(higher priority than DMA).
Arbitra-
tion
End-Of
-Block
Output
Com-
pare
DMA
Request Transfer
DMA
End-of-Block
Interrupt
Routine
MFT0
CM0D
reset
Interrupt
Request
DMA
Request
Output
Compare
DMA
Transfer
The next Output Compare
event generates an interrupt
and not a DMA request.
MFT1
CM0D
reset
(1)
(1) The MFT1 CM0D bit should not be reset by the End-of-
Block signal unless its DMA request is being serviced.
421/426
1
ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Impact On Apllication
4. The MFT1 does not win the next DMA Arbi-
tration, the DMA request is not serviced. The
MFT1 will not request the DMA again as its
DMA Mask bit is reset.
1. The MFT1 wins the next DMA Arbitration, the
DMA request is serviced.
The MFT0 interrupt routine is executed before
the next Input Capture or Output Compare
event. It detects that a wrong Mask Bit Reset
has occurred on the MFT1 and re-enables the
DMA Mask.
=> A DMA transfer is lost.
The MFT0 interrupt routine is not executed
before the next MFT1 Input Capture or Output
Compare event. This new event generates an
Interrupt. The interrupt routine must check
that the DMA counter is equal to 0. If it is not
equal to 0, the DMA counter and address
must not be changed, but the DMA Mask
must be set.
=> There is no application impact.
2. The MFT1 does not win the next DMA Arbitra-
tion, the DMA request is not serviced. The
MFT1 will not request the DMA again as its
DMA Mask bit is reset.
=> An Input Capture value or a Comparison
value must be handled by the interrupt rou-
tine.
=> A DMA transfer is lost.
The MFT0 interrupt routine is executed be-
fore the next Input Capture or Output Com-
pare event. It detects that a wrong Mask Bit
Reset has occurred on the MFT1 and re-ena-
bles the DMA Mask.
If this failure recovery management can be
executed fast enough within the interrupt rou-
tine, only one transfer is lost. Otherwise the
counter will reach the new compare value
before it has been loaded in the Compare
Register or a new input capture event will
occur before the previous value has been
saved.
=> An Input Capture value is lost or a Com-
pare value is used twice.
3. The MFT1 wins the next DMA Arbitration, the
DMA request is serviced.
Workaround
The MFT0 interrupt routine is not executed
before the next MFT1 Input Capture or Output
Compare event. This new event generates an
Interrupt. The interrupt routine must check
that the DMA counter is equal to 0. If it is not
equal to 0, the DMA counter and address
must not be changed, but the DMA Mask
must be set.
If it is not possible to limit the DMA to one MFT
only (no DMA with another MFT, SCI-M or I2C),
the following failure recovery management must
be included in the MFT, SCI-M, I2C Interrupt rou-
tines (if the DMA is used).
1. Following an End-of-Block event (DMA coun-
ter equal to 0):
=> An Input Capture value or a Comparison
value must be handled by the interrupt rou-
tine.
Check the other MFT DMA counter (both
MFTs if this is the SCI-M or the I2C interrupt
routine). If the counter does not equal 0 and
the DMA mask is reset, reset the interrupt flag
bit, set the DMA Mask bit.
If this failure recovery management can be
executed fast enough within the interrupt rou-
tine, there is no impact on the application.
Otherwise the counter will reach the new
compare value before it has been loaded in
the Compare Register or a new input capture
event will occur before the previous value has
been saved.
2. Following an Input Capture or an Output
Compare event (DMA counter does not equal
0):
Execute the transfer by software, modify the
DMA counter and address, reset the interrupt
flag bit, set the DMA Mask bit.
422/426
1
ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Here is an example of a patch for the MFT1 using
DMA in ouput compare mode, inserted at the be-
ginning of the MFT0 interrupt routine:
13.2.10 SCI-A WRONG BREAK DURATION
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a
longer duration than expected:
spp #8 ;Set to page 8 (mft1)
tm T_IDMR,#0x08 ;test mft0 OCMP dma
mask bit
jxnz MFT0_it_routine
- 20 bits instead of 10 bits if M=0
cpw DMA_CNT1,#0 ;If the DMA count is
not at zero the block did not complete
jxeq MFT0_it_routine
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than ex-
pected.
and T_FLAGR,#11011111b ;Clear dma
compare interrupt request
or T_IDMR,#0x08 ;Re-enable the com-
pare 0 dma
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit fre-
MFT0_it_routine: ;MFT0 interrupt rou-
tine code
quency of 19200 baud (f
=8MHz and
CPU
SCIBRR=0xC9), the wrong break duration occur-
rence is around 1%.
In addition, the peripheral DMA priorities must be
organized so that the MFT DMA priorities are the
highest. This way the impact is limited: DMA re-
quests with the wrong Mask Bit Reset are serv-
iced.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
Workaround Limitation
If the counter event period is too short, the failure
recovery in the interrupt routines will not work.
13.2.9 DMA DATA CORRUPTED BY MFT INPUT
CAPTURE
Description
If the MFT requests a DMA transfer following an
input capture event and while a DMA transfer is
currently ongoing to or from another peripheral
(SCI-M, I2C, or second MFT), the DMA data is cor-
rupted (overwritten by the captured data).
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
Workaround
13.2.11 LIN MASTER MODE NOT AVAILABLE
ON SCI-A
LIN Synch Breaks (13 low bits) generation is not
possible on SCI-A. LINE bit has no effect on break
length.
Avoid using the MFT Input Capture function in
DMA mode while another peripheral is in DMA
mode.
423/426
1
ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
13.2.12 LIMITATIONS ON TQFP64 DEVICES
13.2.12.2 EFT0 AND EFT1 NOT AVAILABLE ON
TQFP64 DEVICES
13.2.12.1 AIN[7:0] NOT AVAILABLE ON
TQFP64 DEVICES
Extended Function Timers are not present on
TQFP64 devices.
ADC Channels from AIN0 to AIN7 are not present
on TQFP64 devices.
424/426
1
ST92F124/F150/F250 - REVISION HISTORY
14 REVISION HISTORY
Date
Revision
Main Changes
Revision number incremented from 1.5 to 3.0 due to Internal Document Man-
agement System change
Changed document status: Datasheet instead of Preliminary Data
Added 2EFT for TQFP64 devices
Changed description in Section 1.2.2 on page 10
Replaced 1 by DPR1 in Page 21 column (Figure 26 on page 42)
Removed references to sector 2 (mirrored) in Figure 30 on page 49, Table 7
on page 51. and Figure 41 on page 70
Removed formula in the description of I2CCCR on page 276 and added Ta-
ble 70 on page 398.
Removed “mask option” in the description of ETO bit on page 147
Changed “INTCLK range” table (FREQ[2:0] bits) on page 277
Replaced RX by REC and TX by TRAN in CMSR register on page 343
Changed Section 10.11 on page 361 (added divider/2) and Table 69 on
page 371.
29-oct-2004
3.0
Changed “FLASH / E3 TM SPECIFICATIONS” on page 380
Changed I values in “DC ELECTRICAL CHARACTERISTICS” on page 376
IO
Changed note for I
page 378 (note 5)
in “AC ELECTRICAL CHARACTERISTICS” on
DDHALT
Added Table , “BOOTROM TIMING TABLE,” on page 384
Changed ACD Accuracy table on page 401
Changed Table 73 on page 406.
Added Section 13 on page 407
19-nov-2004
4.0
Changed Table 69 on page 371.
425/426
1
ST92F124/F150/F250 - REVISION HISTORY
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
426/426
1
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