ST93C06B1 [STMICROELECTRONICS]
Microwire Serial EEPROM ; Microwire串行EEPROM\n
| 型号： | ST93C06B1 |
| 厂家： | 
ST |
| 描述： | Microwire Serial EEPROM
|
| 文件： | 总15页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST93C06
ST93C06C
256 bit (16 x 16 or 32 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATARETENTION
DUAL ORGANIZATION: 16 x 16 or 32 x 8
BYTE/WORDand ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
8
8
READY/BUSY SIGNAL DURING
PROGRAMMING
1
1
SINGLE 5V ±10% SUPPLY VOLTAGE
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
PSDIP8 (B)
0.4mm Frame
SO8 (M)
150mil Width
ENHANCED ESD/LATCH UP
PERFORMANCES for ”C” VERSION
ST93C06 and ST93C06C are replaced by
the M93C06
Figure 1. Logic Diagram
DESCRIPTION
The ST93C06 and ST93C06C are 256 bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricatedwith SGS-THOMSON’s High Endurance
SinglePolysilicon CMOS technology.Inthetext the
two products are referred to as ST93C06.
The memory is divided into either 32 x 8 bit bytes
or 16 x 16 bit words. The organization may be
selected by a signal applied on the ORG input.
V
CC
The memory is accessed througha serial input (D)
and by a set of instructions which includes Read a
byte/word, Write a byte/word, Erase a byte/word,
EraseAlland WriteAll. ARead instruction loadsthe
address of the first byte/word to be read into an
internal address pointer.
D
Q
C
S
ST93C06
ST93C06C
ORG
Table 1. Signal Names
S
Chip Select Input
Serial Data Input
Serial Data Output
Serial Clock
V
SS
D
AI00816B
Q
C
ORG
VCC
VSS
Organisation Select
Supply Voltage
Ground
June 1997
1/15
This is information on a product still in production but not recommended for new designs.
ST93C06, ST93C06C
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST93C06
ST93C06C
ST93C06
ST93C06C
S
C
D
Q
1
2
3
4
8
V
CC
DU
S
C
D
Q
1
2
3
4
8
V
CC
DU
7
7
6
5
ORG
6
5
ORG
V
V
SS
SS
AI00817B
AI00818C
Warning: DU = Don’t Use
Warning: DU = Don’t Use
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
°C
Ambient Operating Temperature
Storage Temperature
–40 to 125
–65 to 150
TSTG
°C
TLEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
°C
VIO
Input or Output Voltages (Q = VOH or Hi-Z)
Supply Voltage
–0.3 to VCC +0.5
–0.3 to 6.5
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
ST93C06
2000
4000
V
V
ST93C06C
VESD
Electrostatic Discharge Voltage (Machine model) (3)
ST93C06
ST93C06C
500
500
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d)
signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not requirean erasecycle priorto the Writeinstruc-
tion. The Write instruction writes 8or 16 bits at one
time into one of the 32 bytes or 16 words. After the
startoftheprogrammingcycle aBusy/Readysignal
is available on the Data output (Q) when Chip
Select (S) is driven High.
The design of the ST93C06 and the High Endur-
anceCMOStechnologyusedfor itsfabricationgive
an Erase/Write cycle Endurance of 1,000,000 cy-
cles and a data retention of 40 years.
The data containedat this address is then clocked
out serially. The address pointer is automatically
incrementedafterthe data is outputand, if the Chip
Select input (S) is held High, the ST93C06 can
output a sequentialstream of data bytes/words. In
this way, the memory can be read as a datastream
from 8 to 256 bits long, or continuously as the
address counter automatically rolls over to ’00’
when the highest address is reached. Program-
ming is internally self-timed (the external clock
2/15
ST93C06, ST93C06C
Figure 3. AC Testing Input Output Waveforms
2.4V
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
≤ 20ns
Input Pulse Voltages
0.4V to 2.4V
1V to 2.0V
0.8V to 2.0V
Input Timing Reference Voltages
Output Timing Reference Voltages
2V
2.0V
1V
0.8V
0.4V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
INPUT
OUTPUT
AI00815
Table 3. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
5
Unit
pF
COUT
VOUT = 0V
5
pF
Note: 1. Sampled only, not 100% tested.
Table 4. DC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 5V ± 10%)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±2.5
µA
0V ≤ VOUT ≤ VCC
,
ILO
Output Leakage Current
±2.5
µA
Q in Hi-Z
Supply Current (TTL Inputs)
S = VIH, f = 1 MHz
S = VIH, f = 1 MHz
3
2
mA
mA
ICC
Supply Current (CMOS Inputs)
S = VSS, C = VSS
,
ICC1
Supply Current (Standby)
50
µA
ORG = VSS or VCC
VIL
VIH
Input Low Voltage (D, C, S)
Input High Voltage (D, C, S)
–0.3
2
0.8
VCC + 1
0.4
V
V
V
V
V
V
I
OL = 2.1mA
VOL
Output Low Voltage
Output High Voltage
IOL = 10 µA
0.2
I
OH = –400µA
2.4
VOH
IOH = –10µA
VCC – 0.2
3/15
ST93C06, ST93C06C
Table 5. AC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 5V ± 10%)
Symbol
tSHCH
Alt
tCSS
tSKS
tDIS
Parameter
Test Condition
Min
50
Max
Unit
ns
Chip Select High to Clock High
Clock Low to Chip Select High
Input Valid to Clock High
tCLSH
100
100
100
ns
tDVCH
ns
Temp. Range: grade 1
ns
tCHDX
tDIH
Clock High to Input Transition
Temp. Range:
grades 3, 6
200
ns
tCHQL
tCHQV
tCLSL
tSLCH
tSLSH
tSHQV
tPD0
tPD1
tCSH
Clock High to Output Low
500
500
ns
ns
Clock High to Output Valid
Clock Low to Chip Select Low
Chip Select Low to Clock High
Chip Select Low to Chip Select High
Chip Select High to Output Valid
0
ns
250
250
ns
tCS
tSV
Note 1
ns
500
300
200
ns
ST93C06
ST93C06C
Note 2
ns
tSLQZ
tDF
Chip Select Low to Output Hi-Z
ns
tCHCL
tCLCH
tW
tSKH
tSKL
tWP
fSK
Clock High to Clock Low
Clock Low to Clock High
Erase/Write Cycle time
Clock Frequency
250
250
ns
Note 2
ns
10
1
ms
MHz
fC
0
Notes: 1. Chip Select must bebrought low for a minimum of 250 ns(tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
tCLCH
tCLSH
C
S
D
tSHCH
tCHCL
tCHDX
tDVCH
START
OP CODE
OP CODE
OP CODE
OP CODE
START
OP CODE INPUT
AI00819C
4/15
ST93C06, ST93C06C
Figure 5. Synchronous Timing, Read or Write
C
S
tCLSL
tSLSH
tDVCH
tCHDX
tCHQV
A0
D
Q
An
tSLQZ
Q0
tCHQL
Hi-Z
Q15/Q7
ADDRESS INPUT
DATA OUTPUT
AI00820C
tSLCH
C
S
D
Q
tCLSL
tDVCH
tCHDX
A0/D0
tSLSH
An
tSHQV
BUSY
tW
WRITE CYCLE
tSLQZ
Hi-Z
READY
ADDRESS/DATA INPUT
AI01429
DESCRIPTION (cont’d)
MEMORY ORGANIZATION
The ST93C06 is organized as 32 bytes x 8 bits or
16 words x 16 bits. If the ORG input is left uncon-
nected (or connected to VCC) the x16 organization
is selected, when ORG is connected to Ground
(VSS) the x8 organization is selected. When the
ST93C06 is in standby mode, the ORG input
should be unconnectedor set to either VSS or VCC
in order to achieve the minimum power consump-
tion. Any voltage between VSS and VCC applied to
ORG may increase the standby current value.
TheDU(Don’t Use) pindoesnot affectthe function
of the memory and it is reserved for use by SGS-
THOMSONduringtest sequences.The pinmay be
left unconnected or may be connected to VCC or
VSS. Direct connection of DU to VSS is recom-
mended for the lowest standby power consump-
tion.
5/15
ST93C06, ST93C06C
POWER-ON DATA PROTECTION
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
intoan outputshiftregister.Adummy’0’bit isoutput
firstfollowed by the 8bitbyte orthe 16 bit word with
the MSB first. Output data changes are triggered
by the Low to High transitionof the Clock (C). The
ST93C06 will automatically increment the address
and will clock out the next byte/word aslong as the
Chip Select input (S) is held High. In this case the
dummy ’0’ bit is NOT output between bytes/words
and a continuousstream of data can be read.
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset(POR)circuit resetsall internalprogramming
circuitry and sets the device in the Write Disable
mode. When VCC reaches its functional value, the
device is properlyreset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction. A stable VCC must be applied before
any logic signal.
INSTRUCTIONS
The ST93C06 has seven instructions, as shown in
Table 6. The op-codes ofthe instructionsare made
up of4 bits: some instructionsuse only the first two
bits, others use all four bits to define the op-code.
The op-code is followed by an address for the
byte/wordwhich is fourbits long for thex16 organi-
zation or five bits long for the x8 organization.
Erase/Write Enable and Disable
The Erase/Write Enable instruction (EWEN)
authorizesthe following Erase/Write instructionsto
be executed, the Erase/Write Disable instruction
(EWDS) disables the execution of the following
Erase/Write instructions. When power is first ap-
plied, the ST93C06 enters the Disable mode.
When the Erase/Write Enable instruction (EWEN)
is executed, Write instructionsremainenabled until
an Erase/Write Disable instruction (EWDS) is exe-
cuted or if the Power-on reset circuit becomes
activeduetoareducedVCC. Toprotectthe memory
contentsfrom accidental corruption, it is advisable
to issue the EWDS instruction after every write
cycle. The READ instruction is not affected by the
EWEN or EWDS instructions.
Each instruction is preceded by the rising edge of
the signal applied on the S input (assuming that
clock C and data input D are low), followed by a
first clock pulse which is ignored by the ST93C06
(optional clock pulse for the ST93C06C). The data
input D is then sampled upon the following rising
edges of the clock C untill a ’1’ is sampled and
decoded by the ST93C06 as a Start bit. Even
though the first clock pulse is ignored, it recom-
mended to pull low the data input D during this first
clock pulse in order to keep the timing upwardly
compatible with other ST93Cxx devices.
Erase
The Erase instruction (ERASE) programs the ad-
dressed memory byte or word bits to ’1’. Once the
addressiscorrectlydecoded,thefallingedgeofthe
Chip Select input (S) triggers a self-timed erase
cycle.
The ST93C06 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
input signals) up to themaximum ratings(specified
in Table 5).
Table 6. Instruction Set
x8 Org
Address
(ORG = 0)
x16 Org
Address
(ORG = 1)
Instruction
Description
Op-Code
Data
Data
READ
WRITE
EWEN
EWDS
ERASE
ERAL
Read Data from Memory
Write Data to Memory
Erase/Write Enable
Erase/Write Disable
Erase Byte or Word
Erase All Memory
10XX
01XX
0011
0000
11XX
0010
A4-A0
A4-A0
Q7-Q0
D7-D0
A3-A0
A3-A0
XXXX
XXXX
A3-A0
XXXX
Q15-Q0
D15-D0
XXXXX
XXXXX
A4-A0
XXXXX
Write All Memory
with same Data
WRAL
0001
XXXXX
D7-D0
XXXX
D15-D0
Note: X = don’t care bit.
6/15
ST93C06, ST93C06C
Figure 6. READ, WRITE, EWEN, EWDS Sequences
READ
S
D
Q
1 1 0 X X An A0
Qn
Q0
OP
CODE
DATA OUT
ADDR
WRITE
S
D
Q
CHECK
STATUS
1 0 1 XX An A0 Dn
D0
OP
CODE
DATA IN
BUSY
READY
ADDR
ERASE
WRITE
ENABLE
S
D
ERASE
WRITE
DISABLE
S
1 0 0 1 1 Xn X0
D
1 0 0 0 0 Xn X0
OP
OP
CODE
CODE
AI00822D
Notes: 1. An: n = 3 for x16 org. and 4 for x8 org.
2. Xn: n = 3 for x16 org. and 4 for x8 org.
If the ST93C06 is still performing the erase cycle,
the Busysignal (Q= 0)will be returned if S is driven
high, and the ST93C06 will ignore any data on the
bus.When the erasecycle is completed, theReady
signal (Q = 1) will indicate (if S is driven high) that
the ST93C06is ready to receivea new instruction.
self-timed programming cycle. If the ST93C06 is
still performing the write cycle, the Busy signal (Q
= 0) will be returned if S is driven high, and the
ST93C06will ignoreany dataon the bus. Whenthe
write cycle is completed, the Ready signal (Q = 1)
will indicate (if S is driven high) that the ST93C06
is ready to receivea new instruction. Programming
is internallyself-timed (the external clock signal on
C input may be disconnected or left running after
the start of a programming cycle) and does not
require an Erase instruction prior to the Write in-
struction (The Write instruction includes an auto-
matic erase cycle before programing data).
Write
The Write instruction (WRITE) is followed by the
addressand the 8or16 data bits tobe written.Data
input is sampled on the Low to High transition of
the clock. After the last data bit has been sampled,
Chip Select (S) must be brought Low before the
next rising edgeof the clock (C) in order to start the
7/15
ST93C06, ST93C06C
Figure 7. ERASE, ERAL Sequences
ERASE
S
D
Q
CHECK
STATUS
1 1 1 X X An A0
OP
CODE
BUSY
READY
ADDR
ERASE
ALL
S
D
Q
CHECK
STATUS
1 0 0 1 0 Xn X0
OP
CODE
BUSY
READY
ADDR
DUMMY
AI00823B
Notes: 1. An:n = 3 for x16 org. and 4 for x8 org.
2. Xn:n = 3 for x16 org. and 4 for x8 org.
Figure 8. WRAL Sequence
WRITE
ALL
S
D
Q
CHECK
STATUS
1 0 0 0 1 Xn X0 Dn
D0
OP
DATA IN
BUSY
READY
CODE ADDR
DUMMY
AI00824B
Note: 1 Xn: n = 3 for x16 org. and 4 for x8 org.
8/15
ST93C06, ST93C06C
Erase All
memory when the Chip Select (S) is driven High.
Once the ST93C06 is Ready, the Ready/Busy
status is available on the Data Output (Q) until a
new start bit is decoded or the Chip Select (S) is
brought Low.
The Erase All instruction (ERAL) erases the whole
memory (all memory bits are set to ’1’). A dummy
address is input duringthe instruction transfer and
the erase is made in the same way as the ERASE
instruction. If the ST93C06 is still performing the
erasecycle, the Busysignal (Q =0) willbe returned
if S is driven high, and the ST93C06will ignore any
data on the bus. When the erase cycle is com-
pleted, the Ready signal (Q = 1) will indicate (if S
is driven high)that theST93C06 is ready to receive
a new instruction.
COMMON I/O OPERATION
The DataOutput (Q)andData Input(D) signalscan
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memory with this connection,mostly toprevent
a short circuit between the last entered address bit
(A0) and the first data bit output by Q. The reader
may also refer to the SGS-THOMSON application
note ”MICROWIRE EEPROMCommon I/OOpera-
tion”.
Write All
For correct operation, an ERAL instruction should
be executed before the WRAL instruction: the
WRAL instructionDOES NOTperform an automat-
ic erase before writing. The Write All instruction
(WRAL) writes the Data Inputbyte or word to all the
addresses of the memory. If the ST93C06 is still
performingthe write cycle, the Busy signal (Q = 0)
will bereturnedifS isdrivenhigh,andtheST93C06
will ignore any data on the bus. When the write
cycle is completed, the Ready signal (Q = 1) will
indicate (if S is driven high) that the ST93C06 is
ready to receive a new instruction.
DIFFERENCES BETWEEN ST93C06 AND
ST93C06C
Each instruction of the ST93C06 requires an Addi-
tional Dummy clock pulse after the rising edge of
the Chip Select input(S)and before the STARTbit,
see Figure 9. When replacing the ST93C06 with
the ST93C06C in an application, it must be
checked that this Dummy Clock cycle DOES NOT
HAPPEN when D = 1: if it is so, this clock pulsewill
latch an information which is decoded by the
ST93C06Cas a STARTbit (see Figure 10) and the
following bits will be decodedwitha shift of one bit.
READY/BUSY Status
During every programming cycle (after a WRITE,
ERASE, WRAL or ERAL instruction) the Data Out-
put (Q) indicates the Ready/Busy status of the
Figure 9. ST93C06 Timing
S
D
C
0
1
Dummy Clock pulse
START Bit
AI01334
9/15
ST93C06, ST93C06C
Figure 10. Comparative Timings
WRONG
TIMING
S
D
C
1
1
For ST93C06:
Dummy Clock pulse
START Bit
START Bit
Bit = 1
For ST93C06C:
GOOD
TIMING
S
D
C
0
1
For ST93C06:
Dummy Clock pulse
START Bit
For ST93C06C:
Nothing happens
(waits for D = 1)
Bit = 1
AI01335
10/15
ST93C06, ST93C06C
Figure 11. WRITE Swquence with One Clock Glitch
S
C
D
An
An-1
Glitch
An-2
START
”0”
”1”
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
WRITE
AI01395
DIFFERENCES BETWEEN ST93C06 AND
The ST93C46C has an on-board counter which
counts the clock pulses from the Start bit until the
falling edge of the Chip Select signal. For the
WRITE instructions, the number of clock pulses
incoming to the counter must be exactly 18 (with
the Organisation by 8) from the Start bit to the
falling edge ofChip Select signal (1 Startbit +2 bits
of Op-code + 7 bits of Address + 8 bits of Data =
18): if so, the ST93C06C executes the WRITE
instruction; if the number of clock pulses is not
equal to 18, the instruction will not be executed
(and data will not be corrupted).
ST93C06C (cont’d)
The ST93C06C is an enhanced version of the
ST93C06Aand offers the following extra features:
– EnhancedESD voltage
– Functional security filtering glitches on the
clock input (C).
Refer to Table 2 (Absolute Maximum Ratings) for
more about ESD limits. The following description
will detail the Clock pulses counter (available only
on the ST93C06C).
In the same way, when the Organisation by 16 is
selected, the number of clock pulses incoming to
the counter must be exactly 25 (1 Start bit + 2 bits
of Op-code+ 6 bits of Address + 16 bits of Data =
25) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C06C executes the
WRITE instruction; if the number of clock pulses is
not equal to 25, the instruction will not be executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in-
structions (WRITE, ERASE, ERAL, WRALL).
In anormal environment,theST93C06is expected
to receive the exact amount of data on the D input,
that is the exact amount of clock pulses on the C
input.
In a noisy environment, the amount of pulses re-
ceived (on the clock input C) may be greater than
the clockpulsesdeliveredbythe Master(Microcon-
troller) driving the ST93C06C. In such a case, a
part of the instruction is delayed by one bit (see
Figure11), and it may inducean erroneous write of
data at a wrong address.
11/15
ST93C06, ST93C06C
ORDERING INFORMATION SCHEME
Example:
ST93C06C
M
1
013TR
Revision
Package
Temperature Range
Option
blank CMOS F3
Tech.
B (1) PSDIP8
1
0 to 70 °C
013TR Tape & Reel
Packing
0.4mm Frame
6
–40 to 85 °C
C
CMOS F4
Tech.
M
SO8
150mil Width
3 (2) –40 to 125 °C
Notes: 1. ST93C06CB1 is available with 0.25mm lead Frame only.
2. Temperature range on special request only.
Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh for x16, FFh for x8).
For a list ofavailableoptions (Package, etc...) or for further information on any aspect of this device, please
contact the SGS-THOMSON Sales Office nearest to you.
12/15
ST93C06, ST93C06C
PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame
mm
Min
inches
Min
Symb
Typ
Max
4.80
–
Typ
Max
0.189
–
A
A1
A2
B
0.70
3.10
0.38
1.15
0.38
9.20
–
0.028
0.122
0.015
0.045
0.015
0.362
–
3.60
0.58
1.65
0.52
9.90
–
0.142
0.023
0.065
0.020
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.30
–
7.10
–
0.248
–
0.280
–
8.40
–
0.331
–
9.20
3.80
0.362
0.150
3.00
8
0.118
8
N
PSDIP8
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not to scale
13/15
ST93C06, ST93C06C
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
H
h
1.27
0.050
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
SO8
h x 45°
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Drawing is not to scale
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ST93C06, ST93C06C
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