ST93C47B6 [STMICROELECTRONICS]
128X8 MICROWIRE BUS SERIAL EEPROM, 500ns, PDIP8, 0.40 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8;
| 型号： | ST93C47B6 |
| 厂家： | 
ST |
| 描述： | 128X8 MICROWIRE BUS SERIAL EEPROM, 500ns, PDIP8, 0.40 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST93C46A,46C,46T
ST93C47C,47T
1K (64 x 16 or 128 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATARETENTION
DUAL ORGANIZATION: 64 x 16 or 128 x 8
BYTE/WORDand ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
8
8
READY/BUSY SIGNAL DURING
PROGRAMMING
1
1
SINGLE SUPPLY VOLTAGE:
PSDIP8 (B)
0.4mm Frame
SO8 (M)
150mil Width
– 4.5V to 5.5V for ST93C46 version
– 3V to 5.5V for ST93C47 version
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ENHANCED ESD/LATCH UP
PERFORMANCE for ”C” VERSION
Figure 1. Logic Diagram
ST93C46A, ST93C46C, ST93C46T,
ST93C47C, ST93C47T are replaced by the
M93C46
DESCRIPTION
This specification covers a range of 1K bit serial
EEPROM products, the ST93C46A,46C,46T
specified at 5V±10% and the ST93C47C,47T
specifiedat 3V to 5.5V.
V
CC
In the text, products are referred to as ST93C46.
The ST93C46 is a 1K bit Electrically Erasable
ProgrammableMemory(EEPROM)fabricatedwith
SGS-THOMSON’s High EnduranceSingle Polysili-
con CMOS technology. The memory is accessed
through a serial input (D) and output (Q).
D
C
Q
ST93C46
ST93C47
S
Table 1. Signal Names
ORG
S
Chip Select Input
Serial Data Input
Serial Data Output
Serial Clock
D
V
SS
AI00871C
Q
C
ORG
VCC
VSS
Organisation Select
Supply Voltage
Ground
June 1997
1/13
This is information on a product still in production but not recommended for new designs.
ST93C46A/46C/46T, ST93C47C/47T
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
°C
Ambient Operating Temperature
Storage Temperature
–40 to 125
–65 to 150
TSTG
°C
TLEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
°C
VIO
Input or Output Voltages (Q = VOH or Hi-Z)
Supply Voltage
–0.3 to VCC +0.5
–0.3 to 6.5
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
ST93C46A,T
ST93C46C
2000
4000
V
VESD
Electrostatic Discharge Voltage (Machine model) (3)
ST93C46
500
V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST93C46
ST93C47
ST93C46
ST93C47
S
C
D
Q
1
2
3
4
8
V
CC
DU
S
C
D
Q
1
2
3
4
8
V
CC
DU
7
7
6
5
ORG
6
5
ORG
V
V
SS
SS
AI00872C
AI00874C
Warning: DU = Don’t Use
Warning: DU = Don’t Use
Figure 2C. SO, 90° Turn, Pin Connections
DESCRIPTION (cont’d)
The 1K bit memory is divided into either 128 x 8 bit
bytes or 64 x 16 bit words. The organizationmay
be selected by a signal on the ORG input. The
memory is accessed by a set of instructions which
includes Read a byte/word, Write a byte/word,
Erase a byte/word, Erase All and Write All.
ST93C46T
ST93C47T
DU
1
2
3
4
8
ORG
A Read instruction loads the address of the first
byte/word to be read into an internal address
pointer. The data is then clocked out serially.
V
7
V
CC
S
SS
6
5
Q
C
D
The address pointer is automatically incremented
after the data is output and, if the Chip Select input
(S)isheldHigh, the ST93C46can outputasequen-
tial stream of data bytes/words. In this way, the
memory can be read as a data stream from 8 to
1024 bits long, or continuously as the address
AI00982B
Warning: DU = Don’t Use
2/13
ST93C46A/46C/46T, ST93C47C/47T
AC MEASUREMENT CONDITIONS
Figure 3. AC Testing Input Output Waveforms
Input Rise and Fall Times
≤ 20ns
Input Pulse Voltages
0.4V to 2.4V
1V to 2.0V
0.8V to 2.0V
2.4V
2V
1V
2.0V
0.8V
Input Timing Reference Voltages
Output Timing Reference Voltages
0.4V
INPUT
OUTPUT
AI00815
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Table 3. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
Unit
pF
5
5
COUT
VOUT = 0V
pF
Note: 1. Sampled only, not 100% tested.
Table 4. DC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±2.5
µA
0V ≤ VOUT ≤ VCC
,
ILO
Output Leakage Current
±2.5
µA
Q in Hi-Z
Supply Current (TTL Inputs)
S = VIH, f = 1 MHz
S = VIH, f = 1 MHz
3
2
mA
mA
ICC
Supply Current (CMOS Inputs)
S = VSS, C = VSS
ORG = VSS or VCC
,
ICC1
Supply Current (Standby)
Input Low Voltage (D, C, S)
50
µA
V
CC = 5V ± 10%
3V ≤ VCC ≤ 4.5V
CC = 5V ± 10%
3V ≤ VCC ≤ 4.5V
OL = 2.1mA
IOL = 10 µA
–0.3
–0.3
2
0.8
0.2 VCC
VCC + 1
VCC + 1
0.4
V
V
V
V
V
V
V
V
VIL
V
VIH
VOL
VOH
Input High Voltage (D, C, S)
Output Low Voltage
0.8 VCC
I
0.2
IOH = –400µA
2.4
Output High Voltage
IOH = –10µA
VCC – 0.2
3/13
ST93C46A/46C/46T, ST93C47C/47T
Table 5. AC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
Symbol
tSHCH
Alt
tCSS
tSKS
tDIS
Parameter
Test Condition
Min
50
Max
Unit
ns
Chip Select High to Clock High
Clock Low to Chip Select High
Input Valid to Clock High
tCLSH
100
100
100
ns
tDVCH
ns
Temp. Range: grade 1
ns
tCHDX
tDIH
Clock High to Input Transition
Temp. Range:
grades 3, 6
200
ns
tCHQL
tCHQV
tCLSL
tSLCH
tSLSH
tSHQV
tPD0
tPD1
tCSH
Clock High to Output Low
500
500
ns
ns
Clock High to Output Valid
Clock Low to Chip Select Low
Chip Select Low to Clock High
Chip Select Low to Chip Select High
Chip Select High to Output Valid
0
ns
250
250
ns
tCS
tSV
Note 1
ns
500
300
200
ns
ST93C46A
ST93C46C, 47C
Note 2
ns
tSLQZ
tDF
Chip Select Low to Output Hi-Z
ns
tCHCL
tCLCH
tW
tSKH
tSKL
tWP
fSK
Clock High to Clock Low
Clock Low to Clock High
Erase/Write Cycle time
Clock Frequency
250
250
ns
Note 2
ns
10
1
ms
MHz
fC
0
Notes: 1. Chip Select must bebrought low for a minimum of 250 ns(tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
tCLSH
tCHCL
C
S
D
tSHCH
tCLCH
tDVCH
START
tCHDX
OP CODE
OP CODE
START
OP CODE INPUT
AI01428
4/13
ST93C46A/46C/46T, ST93C47C/47T
Figure 5. Synchronous Timing, Read or Write
C
S
tCLSL
tDVCH
tCHDX
tCHQV
tSLSH
A0
D
Q
An
tSLQZ
tCHQL
Hi-Z
Q15/Q7
Q0
ADDRESS INPUT
DATA OUTPUT
AI00820C
tSLCH
C
S
D
Q
tCLSL
tDVCH
tCHDX
A0/D0
tSLSH
An
tSHQV
BUSY
tSLQZ
READY
Hi-Z
tW
ADDRESS/DATA INPUT
WRITE CYCLE
AI01429
An internal feature of the ST93C46 provides
Power-on Data Protection by inhibiting any opera-
tion when the Supply is too low. The design of the
ST93C46and theHigh EnduranceCMOS technol-
ogy used for its fabrication give an Erase/Write
cycle Endurance of 1,000,000 cycles and a data
retention of 40 years.
The DU(Don’t Use) pin doesnotaffectthe function
of the memory and it is reserved for use by SGS-
THOMSON duringtest sequences.The pinmay be
left unconnected or may be connected to VCC or
VSS. Direct connection of DU to VSS is recom-
mended for the lowest standby power consump-
tion.
DESCRIPTION (cont’d)
counter automatically rolls over to ’00’ when the
highest addressis reached.
Programming is internally self-timed (the external
clock signal on C input may be disconnectedor left
running after the start of a Write cycle) and does
not require an erase cycle prior to theWrite instruc-
tion. The Write instruction writes 8 or 16 bits at one
time into one of the 128 bytes or 64 words. After
the start of the programming cycle a Busy/Ready
signal is available on the Data output (Q) when
Chip Select (S) is High.
5/13
ST93C46A/46C/46T, ST93C47C/47T
MEMORY ORGANIZATION
The ST93C46 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
input signals)up to the maximumratings (specified
in Table 5).
The ST93C46 is organised as 128 bytes x 8 bits or
64 words x 16 bits. If the ORG input is left uncon-
nected (or connected to VCC) the x16 organization
is selected, when ORG is connected to Ground
(VSS) the x8 organization is selected. When the
ST93C46 is in standby mode, the ORG input
should be unconnectedor set to either VSS or VCC
in order to get minimum power consumption. Any
voltage betweenVSS andVCC appliedto ORG may
increase the standby current value.
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
intoan outputshiftregister.Adummy’0’bit isoutput
firstfollowed by the 8bitbyte orthe 16 bit word with
the MSB first. Output data changes are triggered
by the Low to High transitionof the Clock (C). The
ST93C46 will automatically increment the address
and will clock out the next byte/word aslong as the
Chip Select input (S) is held High. In this case the
dummy ’0’ bit is NOT output between bytes/words
and a continuousstream of data can be read.
POWER-ON DATA PROTECTION
During power-up, A Power On Reset sequence is
run in order to reset all internal programming cir-
cuitry and the device is set in the Write Disable
mode. When VCC reaches its functional value, the
device is properlyreset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction.
Erase/Write Enable and Disable
The Erase/Write Enable instruction (EWEN)
authorizesthe following Erase/Write instructionsto
be executed, the Erase/Write Disable instruction
(EWDS) freezes the execution of the following
Erase/Write instructions. When power is first ap-
plied to the ST93C46, Erase/Write is inhibited.
When the EWEN instruction is executed, Write
instructions remain enabled until an Erase/Write
Disable instruction (EWDS)is executedorVCC falls
below the power-on reset threshold.To protect the
memory contents from accidental corruption, it is
advisableto issuethe EWDS instructionafterevery
write cycle.
INSTRUCTIONS
The ST93C46 has seven instructions, as shown in
Table 6. Each instruction is preceded by the rising
edgeof the signalapplied onthe S input(assuming
that the clock C is low), followed by a ’1’ read on D
input during the rising edge of the clock C. The
op-codes of the instructions are made up of the 2
followingbits. Someinstructionsuseonly thesefirst
two bits, others use also the first two bits of the
address to define the op-code. The op-code is
followed by an address for the byte/wordwhich is
made up of six bits for the x16 organization or
seven bits for the x8 organization.
The READ instruction is not affected by the EWEN
or EWDS instructions.
Table 6. Instruction Set
x8 Org
Address
(ORG = 0)
x16 Org
Address
(ORG = 1)
Instruction
Description
Op-Code
Data
Data
READ
WRITE
EWEN
EWDS
ERASE
ERAL
Read Data from Memory
Write Data to Memory
Erase/Write Enable
10
01
00
00
11
00
00
A6-A0
A6-A0
Q7-Q0
D7-D0
A5-A0
A5-A0
Q15-Q0
D15-D0
11XXXXX
00XXXXX
A6-A0
11XXXX
00XXXX
A5-A0
Erase/Write Disable
Erase Byte or Word
Erase All Memory
10XXXXX
01XXXXX
10XXXX
01XXXX
WRAL
Write All Memory with same Data
D7-D0
D15-D0
Note: X = don’t care bit.
6/13
ST93C46A/46C/46T, ST93C47C/47T
Erase
signal (Q = 1) will indicate (if S is driven high) that
the ST93C46is ready to receive a new instruction.
Write
The Write instruction (WRITE) is followed by the
address andthe 8 or16 databits to bewritten. Data
input is sampled on the Low to High transition of
the clock. After the last data bit has been sampled,
Chip Select (S) must be brought Low before the
next rising edge of the clock (C), in order to start
the self-timed programming cycle. If the ST93C46
is still performing the write cycle, the Busy signal
The Erase instruction (ERASE) programs the ad-
dressed memory byte or word bits to ’1’. Once the
addressiscorrectlydecoded,the fallingedge ofthe
Chip Select input (S) starts a self-timed program-
ming cycle.
If the ST93C46 is still performing the write cycle,
the Busysignal (Q= 0)will be returned if S is driven
high, and the ST93C46 will ignore any data on the
bus. When the write cycle iscompleted, the Ready
Figure 6. READ, WRITE, EWEN, EWDS Sequences
READ
S
D
Q
1 1 0 An
A0
Qn
Q0
ADDR
DATA OUT
OP
CODE
WRITE
S
D
Q
CHECK
STATUS
1 0 1 An
A0 Dn
D0
ADDR
DATA IN
BUSY
READY
OP
CODE
ERASE
WRITE
ENABLE
S
D
ERASE
WRITE
DISABLE
S
D
1 0 0 1 1 Xn X0
1 0 0 0 0 Xn X0
OP
OP
CODE
CODE
AI00878C
Notes: 1. An: n = 5 for x16 org. and 6 for x8 org.
2. Xn: n = 3 for x16 org. and 4 for x8 org.
7/13
ST93C46A/46C/46T, ST93C47C/47T
INSTRUCTIONS (cont’d)
ignore any data on the bus. When the write cycle
is completed,the Ready signal (Q = 1) will indicate
(if S is driven high) that the ST93C46 is ready to
receive a new instruction.
(Q = 0) will be returned if S is driven high, and the
ST93C46will ignoreany dataon thebus. When the
write cycle is completed, the Ready signal (Q = 1)
will indicate (if S is driven high) that the ST93C46
is ready to receive a new instruction.
Write All
For correct operation,an ERAL instruction should
be executedbefore the WRAL instruction.
The Write instruction includes an automaticErase
cycle before writing the data, it is thereforeunnec-
essary to execute an Erase instruction before a
Write instruction execution.
The Write All instruction (WRAL) writes the Data
Input byte or word to all the addresses of the
memory. In the WRAL instruction, NO automatic
erase is made so all bytes/words must be erased
before theWRAL instruction. If the ST93C46 is still
performing the write cycle, the Busy signal (Q = 0)
will bereturnedif Sis drivenhigh,and theST93C46
will ignore any data on the bus. When the write
cycle is completed, the Ready signal (Q = 1) will
indicate (if S is driven high) that the ST93C46 is
ready to receive a new instruction.
Erase All
The Erase All instruction (ERAL) erases the whole
memory (all memory bits are set to ”1”). A dummy
address is input duringthe instruction transfer and
the erase is made in the same way as the ERASE
instructionabove. If theST93C46 is still performing
the write cycle, the Busy signal (Q = 0) will be
returned if S is driven high, and the ST93C46 will
Figure 7. ERASE, ERAL Sequences
ERASE
S
D
Q
CHECK
STATUS
1 1 1 An
A0
ADDR
BUSY
READY
OP
CODE
ERASE
ALL
S
D
Q
CHECK
STATUS
1 0 0 1 0 Xn X0
ADDR
OP
BUSY
READY
CODE
AI00879B
Notes: 1. An: n = 5 for x16 org. and 6 for x8 org.
2. Xn: n = 3 for x16 org. and 4 for x8 org.
8/13
ST93C46A/46C/46T, ST93C47C/47T
Figure 8. WRAL Sequence
WRITE
ALL
S
D
Q
CHECK
STATUS
D0
1 0 0 0 1 Xn X0 Dn
ADDR
OP
DATA IN
BUSY
READY
CODE
AI00880C
Note: 1. Xn: n = 3 for x16 org. and 4 for x8 org.
READY/BUSY Status
In a normalenvironment,theST93C46is expected
to receive the exact amount of data on the D input,
that is the exact amount of clock pulses on the C
input.
In a noisy environment, the amount of pulses re-
ceived (on the clock input C) may be greater than
the clockpulsesdeliveredby the Master(Microcon-
troller) driving the ST93C46C. In such a case, a
part of the instruction is delayed by one bit (see
Figure 9), and it may induce an erroneouswrite of
data at a wrongaddress.
During every programming cycle (after a WRITE,
ERASE, WRAL or ERAL instruction) the Data Out-
put (Q) indicates the Ready/Busy status of the
memory whenthe Chip Selectis driven High. Once
the ST93C46 is Ready, the Data Outputis set to ’1’
until a new start bit is decoded or the Chip Select
is brought Low.
COMMON I/O OPERATION
The ST93C46C has an on-board counter which
counts the clock pulses from the Start bit until the
falling edge of the Chip Select signal. For the
WRITE instructions, the number of clock pulses
incoming to the counter must be exactly 18 (with
the Organisation by 8) from the Start bit to the
falling edge ofChip Select signal (1 Startbit +2 bits
of Op-code + 7 bits of Address + 8 bits of Data =
18): if so, the ST93C46C executes the WRITE
instruction; if the number of clock pulses is not
equal to 18, the instruction will not be executed
(and data will not be corrupted).
In the same way, when the Organisation by 16 is
selected, the number of clock pulses incoming to
the counter must be exactly 25 (1 Start bit + 2 bits
of Op-code+ 6 bits of Address + 16 bits of Data =
25) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C46C executes the
WRITE instruction; if the number of clock pulses is
not equal to 25, the instruction will not be executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in-
structions (WRITE, ERASE, ERAL, WRALL).
TheData Output(Q)andData Input(D)signals can
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memory with this connection,mostly to prevent
a shortcircuit betweenthe last entered address bit
(A0) and the first data bit output by Q. The reader
should refer to the SGS-THOMSON application
note”MICROWIRE EEPROMCommonI/OOpera-
tion”.
DIFFERENCES BETWEEN ST93C46A AND
ST93C46C
The ST93C46C is an enhanced version of the
ST93C46Aand offers the following extra features:
– EnhancedESD voltage
– Functional security filtering glitches on the
clock input (C).
Refer to Table 2 (Absolute Maximum Ratings) for
more about ESD limits. The following description
will detail the Clock pulses counter (available only
on the ST93C46C).
9/13
ST93C46A/46C/46T, ST93C47C/47T
Figure 9. WRITE Sequence with One Clock Glitch
S
C
D
An
An-1
An-2
START
”0”
”1”
Glitch
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
WRITE
AI01395
ORDERING INFORMATION SCHEME
Example: ST93C46A
M
1
013TR
Operating Voltage
Revision
Package
Temperature Range
Option
46 4.5V to 5.5V
47 3V to 5.5V
A (1) CMOS F3
B (2) PSDIP8
1
0 to 70 °C
013TR Tape & Reel
Packing
0.4 mm Frame
C
T
CMOS F4
6
–40 to 85 °C
(A, T ver.)
M
SO8
150mil Width
CMOS F3
90° Turn pin out
3 (3) –40 to 125 °C
TR Tape & Reel
Packing
(C version)
Notes: 1. Revision ”A” is not available for the ST93C47 product.
2. ST93C46CB1 is available in 0.25mm lead Frame only.
3. Temperature range on special request only.
Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh for x16, FFh for x8).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the SGS-THOMSON Sales Office nearest to you.
10/13
ST93C46A/46C/46T, ST93C47C/47T
PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame
mm
Min
inches
Min
Symb
Typ
Max
4.80
–
Typ
Max
0.189
–
A
A1
A2
B
0.70
3.10
0.38
1.15
0.38
9.20
–
0.028
0.122
0.015
0.045
0.015
0.362
–
3.60
0.58
1.65
0.52
9.90
–
0.142
0.023
0.065
0.020
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.30
–
7.10
–
0.248
–
0.280
–
8.40
–
0.331
–
9.20
3.80
0.362
0.150
3.00
8
0.118
8
N
CP
0.10
0.004
PSDIP8
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not to scale
11/13
ST93C46A/46C/46T, ST93C47C/47T
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
SO8
h x 45°
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Drawing is not to scale
12/13
ST93C46A/46C/46T, ST93C47C/47T
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
MICROWIRE isa registered trademark of National Semiconductor Corp.
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13/13
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