ST93C57CM6TR [STMICROELECTRONICS]
2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM; 2K 128 ×16或256 ×8串行EEPROM MICROWIRE
| 型号： | ST93C57CM6TR |
| 厂家： | 
ST |
| 描述： | 2K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM |
| 文件： | 总13页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST93C56, 56C
ST93C57C
2K (128 x 16 or 256 x 8) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATARETENTION
DUAL ORGANIZATION: 128 x 16 or 256 x 8
BYTE/WORDand ENTIRE MEMORY
PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
8
8
READY/BUSY SIGNAL DURING
PROGRAMMING
1
1
SINGLE SUPPLY VOLTAGE:
PSDIP8 (B)
0.4mm Frame
SO8 (M)
150mil Width
– 4.5V to 5.5V for ST93C56 version
– 3V to 5.5V for ST93C57 version
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ST93C56, ST93C56C, ST93C57C are
replaced by the M93C56
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 2K bit serial
EEPROM products, the ST93C56, 56C specified
at 5V ± 10% and the ST93C57C specified at 3V to
5.5V. In the text, products are referred to as
ST93C56.
V
CC
The ST93C56 is a 2K bit Electrically Erasable
ProgrammableMemory(EEPROM)fabricatedwith
SGS-THOMSON’s High EnduranceSingle Polysili-
con CMOS technology. The memory is accessed
through a serial input (D) and output (Q). The 2K
bit memory is divided into either 256 x 8 bit bytes
or 128 x 16 bit words. The organization may be
selected by a signal applied on the ORG input.
D
C
Q
ST93C56
ST93C57
S
ORG
Table 1. Signal Names
S
Chip Select Input
Serial Data Input
Serial Data Output
Serial Clock
V
SS
D
AI00881C
Q
C
ORG
VCC
VSS
Organisation Select
Supply Voltage
Ground
June 1997
1/13
This is information on a product still in production but not recommended for new designs.
ST93C56/56C, ST93C57C
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST93C56
ST93C57
ST93C56
ST93C57
S
C
D
Q
1
2
3
4
8
V
S
C
D
Q
1
2
3
4
8
V
CC
DU
CC
7
DU
7
6
5
ORG
6
5
ORG
V
V
SS
SS
AI00882C
AI00883D
Warning: DU = Don’t Use
Warning: DU = Don’t Use
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
°C
Ambient Operating Temperature
Storage Temperature
–40 to 125
–65 to 150
TSTG
°C
TLEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
°C
VIO
Input or Output Voltages (Q = VOH or Hi-Z)
Supply Voltage
–0.3 to VCC +0.5
–0.3 to 6.5
4000
V
V
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
VESD
500
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d)
nected orleft runningafter the start ofaWrite cycle)
and does not require an erase cycle prior to the
Write instruction. The Write instruction writes 8 or
16 bits at one time into one of the 256 bytes or 128
words. After the start of the programming cycle, a
Busy/Ready signal is available on the Data output
(Q) when Chip Select (S) is driven High.
The memory is accessed by a set of instructions
which includes Read a byte/word, Write a
byte/word, Erase a byte/word,Erase All and Write
All. ARead instruction loads the addressof the first
byte/word to be read into an internal address
pointer. The datacontained at this address is then
clocked out serially. The address pointer is auto-
matically incremented after the data is output and,
if the Chip Select input (S) is held High, the
ST93C56 can output a sequential stream of data
bytes/words. In this way, the memory can be read
as a data stream from 8 to 2048 bits long, or
continuouslyas the address counterautomatically
rolls over to ’00’ when the highest address is
reached. Programming is internally self-timed (the
external clock signal on C input may be discon-
The design of the ST93C56 and the High Endur-
anceCMOStechnologyusedfor itsfabricationgive
an Erase/Write cycle Endurance of 1,000,000 cy-
cles and a data retention of 40 years.
TheDU (Don’tUse) pindoes notaffectthe function
of the memory and it is reserved for use by SGS-
THOMSON duringtest sequences.Thepinmay be
left unconnected or may be connected to VCC or
VSS. Direct connection of DU to VSS is recom-
mended for the lowest standby power consump-
tion.
2/13
ST93C56/56C, ST93C57C
Figure 3. AC Testing Input Output Waveforms
2.4V
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
≤ 20ns
Input Pulse Voltages
0.4V to 2.4V
1V to 2.0V
0.8V to 2.0V
Input Timing Reference Voltages
Output Timing Reference Voltages
2V
2.0V
1V
0.8V
0.4V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
INPUT
OUTPUT
AI00815
Table 3. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
Unit
pF
5
5
COUT
VOUT = 0V
pF
Note: 1. Sampled only, not 100% tested.
Table 4. DC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±2.5
µA
0V ≤ VOUT ≤ VCC
,
ILO
Output Leakage Current
±2.5
µA
Q in Hi-Z
Supply Current (TTL Inputs)
S = VIH, f = 1 MHz
S = VIH, f = 1 MHz
3
2
mA
mA
ICC
Supply Current (CMOS Inputs)
S = VSS, C = VSS
ORG = VSS or VCC
,
ICC1
Supply Current (Standby)
Input Low Voltage (D, C, S)
50
µA
V
CC = 5V ± 10%
3V ≤ VCC ≤ 4.5V
CC = 5V ± 10%
–0.3
–0.3
2
0.8
0.2 VCC
VCC + 1
VCC + 1
0.4
V
V
V
V
V
V
V
V
VIL
V
VIH
VOL
VOH
Input High Voltage (D, C, S)
Output Low Voltage
3V ≤ VCC ≤ 4.5V
0.8 VCC
IOL = 2.1mA
I
OL = 10 µA
0.2
IOH = –400µA
IOH = –10µA
2.4
Output High Voltage
VCC – 0.2
3/13
ST93C56/56C, ST93C57C
Table 5. AC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
Symbol
tSHCH
Alt
tCSS
tSKS
tDIS
Parameter
Test Condition
Min
50
Max
Unit
ns
Chip Select High to Clock High
Clock Low to Chip Select High
Input Valid to Clock High
tCLSH
100
100
100
ns
tDVCH
ns
Temp. Range: grade 1
ns
tCHDX
tDIH
Clock High to Input Transition
Temp. Range:
grades 3, 6
200
ns
tCHQL
tCHQV
tCLSL
tSLCH
tSLSH
tSHQV
tPD0
tPD1
tCSH
Clock High to Output Low
500
500
ns
ns
Clock High to Output Valid
Clock Low to Chip Select Low
Chip Select Low to Clock High
Chip Select Low to Chip Select High
Chip Select High to Output Valid
0
ns
250
250
ns
tCS
tSV
Note 1
ns
500
300
200
ns
ST93C56
ST93C56C, 57C
Note 2
ns
tSLQZ
tDF
Chip Select Low to Output Hi-Z
ns
tCHCL
tCLCH
tW
tSKH
tSKL
tWP
fSK
Clock High to Clock Low
Clock Low to Clock High
Erase/Write Cycle time
Clock Frequency
250
250
ns
Note 2
ns
10
1
ms
MHz
fC
0
Notes: 1. Chip Select must bebrought low for a minimum of 250 ns(tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
tCLSH
tCHCL
C
S
D
tSHCH
tCLCH
tDVCH
START
tCHDX
OP CODE
OP CODE
START
OP CODE INPUT
AI01428
4/13
ST93C56/56C, ST93C57C
Figure 5. Synchronous Timing, Read or Write
C
S
tCLSL
tSLSH
tDVCH
tCHDX
tCHQV
A0
D
Q
An
tSLQZ
Q0
tCHQL
Hi-Z
Q15/Q7
ADDRESS INPUT
DATA OUTPUT
AI00820C
tSLCH
C
S
D
Q
tCLSL
tDVCH
tCHDX
A0/D0
tSLSH
An
tSHQV
BUSY
tW
WRITE CYCLE
tSLQZ
Hi-Z
READY
ADDRESS/DATA INPUT
AI01429
MEMORY ORGANIZATION
POWER-ON DATA PROTECTION
The ST93C56 is organized as 256 bytes x 8 bits or
128 words x 16 bits. If the ORG input is left uncon-
nected (or connected to VCC) the x16 organization
is selected, when ORG is connected to Ground
(VSS) the x8 organization is selected. When the
ST93C56 is in standby mode, the ORG input
should be unconnectedor set to either VSS or VCC
in order to achieve the minimum power consump-
tion. Any voltage between VSS and VCC applied to
ORG may increase the standby current value.
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset(POR) circuitresetsall internalprogramming
circuitry and sets the device in the Write Disable
mode. When VCC reachesits functional value, the
device is properlyreset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction. A stable VCC must be applied, before
applying any logic signal.
5/13
ST93C56/56C, ST93C57C
INSTRUCTIONS
be executed, the Erase/Write Disable instruction
(EWDS) disables the execution of the following
Erase/Write instructions. When power is first ap-
plied, the ST93C56 enters the Disable mode.
When the EWEN instruction is executed, Write
instructions remain enabled until an Erase/Write
Disableinstruction(EWDS) is executedorVCC falls
below the power-onreset threshold. To protect the
memory contents from accidental corruption, it is
advisableto issuethe EWDSinstruction afterevery
write cycle.
The ST93C56 has seven instructions, as shown in
Table 6. The op-codes ofthe instructionsare made
up of2 bits. The op-code is followed by an address
for the byte/wordwhich is eight bits long for the x16
organization or nine bits long for the x8 organiza-
tion.Eachinstructionis precededbythe rising edge
of the signal applied on the Chip Select (S) input
(assuming that the clock C is low). The data input
D is then sampled upon the following rising edges
of the clock C untill a ’1’ is sampled and decoded
by the ST93C56 as a Start bit.
The READ instruction is not affected by the EWEN
or EWDS instructions.
The ST93C56 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
input signals) up to themaximum ratings(specified
in Table 5).
Erase
The Erase instruction (ERASE) programs the ad-
dressed memory byte or word bits to ’1’. Once the
addressiscorrectlydecoded,the fallingedgeof the
Chip Select input (S) triggers a self-timed erase
cycle.
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from the memory is transferred
into anoutputshiftregister.Adummy’0’bitis output
first, followed by the 8 bit byte or the 16 bit word
with the MSB first. Output data changes are trig-
geredby the Low toHightransition ofthe Clock (C).
The ST93C56 will automaticallyincrement the ad-
dress and will clock out the next byte/wordas long
as the Chip Select input (S) is held High. In this
case the dummy ’0’ bit is NOT output between
bytes/words and a continuous stream of data can
be read.
If the ST93C56 is still performing the erase cycle,
the Busysignal (Q =0) will bereturned if S is driven
high, and the ST93C56 will ignore any data on the
bus. Whenthe erase cycle is completed,theReady
signal (Q = 1) will indicate (if S is driven high) that
the ST93C56is ready to receive a new instruction.
Write
The Write instruction (WRITE) is followed by the
address andthe 8 or16 databits to bewritten. Data
input is sampled on the Low to High transition of
the clock. After the last data bit has been sampled,
Chip Select (S) must be brought Low before the
next rising edge of the clock (C) in order to start
the self-timed programming cycle. If the ST93C56
is still performing the write cycle, the Busy signal
Erase/Write Enable and Disable
The Erase/Write Enable instruction (EWEN)
authorizesthe following Erase/Writeinstructions to
Table 6. Instruction Set
x8 Org
Address
x16 Org
Address
Instruction
Description
Op-Code
Data
Data
(ORG = 0) (1, 2)
(ORG = 1) (1, 3)
READ
WRITE
EWEN
EWDS
ERASE
ERAL
Read Data from Memory
Write Data to Memory
Erase/Write Enable
Erase/Write Disable
Erase Byte or Word
Erase All Memory
10
01
00
00
11
00
A8-A0
A8-A0
Q7-Q0
D7-D0
A7-A0
A7-A0
Q15-Q0
D15-D0
11XXX XXXX
00XXX XXXX
A8-A0
11XX XXXX
00XX XXXX
A7-A0
10XXX XXXX
10XX XXXX
Write All Memory
with same Data
WRAL
00
01XXX XXXX
D7-D0
01XX XXXX
D15-D0
Notes: 1. X = don’t care bit.
2. Address bit A8 is not decoded by the ST93C56, ST93C56C.
3. Address bit A7 is not decoded by the ST93C56, ST93C56C.
6/13
ST93C56/56C, ST93C57C
Figure 6. READ, WRITE, EWEN, EWDS Sequences
READ
S
D
Q
1 1 0 An
A0
Qn
Q0
ADDR
DATA OUT
OP
CODE
WRITE
S
D
Q
CHECK
STATUS
1 0 1 An
A0 Dn
D0
ADDR
DATA IN
BUSY
READY
OP
CODE
ERASE
WRITE
ENABLE
S
D
ERASE
WRITE
DISABLE
S
1 0 0 1 1 Xn X0
D
1 0 0 0 0 Xn X0
OP
OP
CODE
CODE
AI00878C
Notes: 1. An: n = 7 for x16 org. and 8 for x8 org.
2. Xn: n = 5 for x16 org. and 6 for x8 org.
(Q = 0) will be returned if S is driven high, and the
ST93C56will ignoreany dataon thebus. When the
write cycle is completed, the Ready signal (Q = 1)
will indicate (if S is driven high) that the ST93C56
is ready to receivea new instruction. Programming
is internallyself-timed (the external clock signal on
C input may be disconnected or left running after
the start of a programming cycle) and does not
require an Erase instruction prior to the Write in-
struction (The Write instruction includes an auto-
matic erase cycle before programing data).
7/13
ST93C56/56C, ST93C57C
Figure 7. ERASE, ERAL Sequences
ERASE
S
D
Q
CHECK
STATUS
1 1 1 An
A0
ADDR
BUSY
READY
OP
CODE
ERASE
ALL
S
D
Q
CHECK
STATUS
1 0 0 1 0 Xn X0
ADDR
OP
BUSY
READY
CODE
AI00879B
Notes: 1. An:n = 7 for x16 org. and 8 for x8 org.
2. Xn:n = 5 for x16 org. and 6 for x8 org.
Figure 8. WRAL Sequence
WRITE
ALL
S
D
Q
CHECK
STATUS
1 0 0 0 1 Xn X0 Dn
D0
ADDR
DATA IN
BUSY
READY
OP
CODE
AI00880C
Note: 1. Xn: n = 5 for x16 org. and 6 for x8 org.
8/13
ST93C56/56C, ST93C57C
Erase All
DIFFERENCES BETWEEN ST93C56 AND
ST93C56C
The ST93C56C is an enhanced version of the
ST93C56 and offers a functional security filtering
glitches on the clock input (C).
The followingdescription will detail the Clock pulse
counter (available only on the ST93C56C).
In a normal environment, the ST93C56expects to
receive the exact amount of data on the D input,
that is, the exact amount of clock pulses on the C
input.
The Erase All instruction (ERAL) erases the whole
memory (all memory bits are set to ’1’). A dummy
address is input duringthe instruction transfer and
the erase is made in the same way as the ERASE
instruction. If the ST93C56 is still performing the
erasecycle, the Busysignal (Q =0) willbe returned
if S is driven high, and the ST93C56will ignore any
data on the bus. When the erase cycle is com-
pleted, the Ready signal (Q = 1) will indicate (if S
is driven high)that theST93C56 is ready to receive
a new instruction.
In a noisy environment, the number of pulses re-
ceived (on the clock input C) may be greater than
the clockpulsesdeliveredby the Master(Microcon-
troller) driving the ST93C56C. In such a case, a
part of the instruction is delayed by one bit (see
Figure 9), and it may induce an erroneouswrite of
data at a wrongaddress.
The ST93C56C has an on-chip counter which
counts the clock pulses from the Start bit until the
falling edge of the Chip Select signal. For the
WRITE instructions, the number of clock pulses
incoming to the counter must be exactly 20 (with
the Organisation by 8) from the Start bit to the
falling edge ofChip Select signal (1 Startbit +2 bits
of Op-code + 9 bits of Address + 8 bits of Data =
20): if so, the ST93C56C executes the WRITE
instruction; if the number of clock pulses is not
equal to 20, the instruction will not be executed
(and data will not be corrupted).
In the same way, when the Organisation by 16 is
selected, the number of clock pulses incoming to
the counter must be exactly 27 (1 Start bit + 2 bits
of Op-code+ 8 bits of Address + 16 bits of Data =
27) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C56C executes the
WRITE instruction; if the number of clock pulses is
not equal to 27, the instruction will not be executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in-
structions (WRITE, ERASE, ERAL, WRALL).
Write All
The Write All instruction (WRAL) writes the Data
Input byte or word to all the addresses of the
memory. Ifthe ST93C56 is stillperformingthe write
cycle, the Busy signal (Q = 0) will be returned if S
is driven high, and the ST93C56 will ignore any
dataon the bus. Whenthe write cycle is completed,
the Ready signal (Q = 1) will indicate (if S is driven
high) that the ST93C56 is ready to receive a new
instruction.
READY/BUSY Status
During every programming cycle (after a WRITE,
ERASE, WRAL or ERAL instruction) the Data Out-
put (Q) indicates the Ready/Busy status of the
memory when the Chip Select (S) is driven High.
Once the ST93C56 is Ready, the Ready/Busy
status is available on the Data Output (Q) until a
new start bit is decoded or the Chip Select (S) is
broughtLow.
COMMON I/O OPERATION
TheData Output(Q)andData Input(D)signals can
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memory with this connection,mostly to prevent
a shortcircuit betweenthe last entered address bit
(A0) and the first data bit output by Q. The reader
may also refer to the SGS-THOMSON application
note”MICROWIRE EEPROMCommonI/OOpera-
tion”.
9/13
ST93C56/56C, ST93C57C
Figure 9. WRITE Sequence with One Clock Glitch
S
C
D
An
An-1
An-2
START
”0”
”1”
Glitch
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
WRITE
AI01395
ORDERING INFORMATION SCHEME
Example:
ST93C56C
M
1
013TR
Operating Voltage
Revision
Package
Temperature Range
Option
56 4.5V to 5.5V
57 3V to 5.5V
blank CMOS F3
B
PSDIP8
0.4 mm Frame
1
6
0 to 70 °C
013TR Tape & Reel
Packing
C
CMOS F4
–40 to 85 °C
(A, T ver.)
M
SO8
150mil Width
3 (1) –40 to 125 °C
TR Tape & Reel
Packing
(C version)
Note: 1. Temperature range on special request only.
Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh for x16, FFh for x8).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the SGS-THOMSON Sales Office nearest to you.
10/13
ST93C56/56C, ST93C57C
PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame
mm
Min
inches
Min
Symb
Typ
Max
4.80
–
Typ
Max
0.189
–
A
A1
A2
B
0.70
3.10
0.38
1.15
0.38
9.20
–
0.028
0.122
0.015
0.045
0.015
0.362
–
3.60
0.58
1.65
0.52
9.90
–
0.142
0.023
0.065
0.020
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.30
–
7.10
–
0.248
–
0.280
–
8.40
–
0.331
–
9.20
3.80
0.362
0.150
3.00
8
0.118
8
N
CP
0.10
0.004
PSDIP8
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not to scale
11/13
ST93C56/56C, ST93C57C
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
H
h
1.27
0.050
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
SO8
h x 45°
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Drawing is not to scale
12/13
ST93C56/56C, ST93C57C
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
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