ST93CS56B6013TR [STMICROELECTRONICS]
2K 128 x 16 SERIAL MICROWIRE EEPROM; 2K 128 ×16串行EEPROM MICROWIRE
| 型号： | ST93CS56B6013TR |
| 厂家： | 
ST |
| 描述： | 2K 128 x 16 SERIAL MICROWIRE EEPROM |
| 文件： | 总16页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST93CS56
ST93CS57
2K (128 x 16) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATARETENTION
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE
8
8
– 3V to 5.5V for the ST93CS56
– 2.5V to 5.5V for the ST93CS57
USER DEFINED WRITE PROTECTED AREA
PAGE WRITE MODE (4 WORDS)
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
1
1
PSDIP8 (B)
0.4mm Frame
SO8 (M)
150mil Width
ST93CS56 and ST93CS57 are replaced by
the M93S56
Figure 1. Logic Diagram
DESCRIPTION
The ST93CS56 and ST93CS57 are 2K bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricatedwith SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed through a serial input D and output Q.
V
CC
The 2K bit memory is organized as 128 x 16 bit
words.Thememory is accessedby a set of instruc-
tions which include Read, Write, Page Write, Write
All and instructions used to set the memory protec-
tion. A Read instruction loads the address of the
first word to be read into an internal address
pointer.
D
C
Q
ST93CS56
ST93CS57
S
PRE
W
Table 1. Signal Names
S
Chip Select Input
Serial Data Input
Serial Data Output
Serial Clock
D
Q
V
SS
C
AI00896B
PRE
W
Protect Enable
Write Enable
VCC
VSS
Supply Voltage
Ground
June 1997
1/16
This is information on a product still in production but not recommended for new designs.
ST93CS56, ST93CS57
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST93CS56
ST93CS57
ST93CS56
ST93CS57
S
C
D
Q
1
2
3
4
8
V
CC
PRE
S
C
D
Q
1
2
3
4
8
V
CC
PRE
7
7
6
5
W
6
5
W
V
SS
V
SS
AI00897B
AI00898C
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
°C
Ambient Operating Temperature
Storage Temperature
–40 to 85
TSTG
–65 to 150
°C
TLEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
°C
VIO
Input or Output Voltages (Q = VOH or Hi-Z)
Supply Voltage
–0.3 to VCC +0.5
–0.3 to 6.5
3000
V
V
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
VESD
500
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d)
Protect Register, located outside of the memory
array. As a final protection step, data may be per-
manently protected by programming a One Time
Programing bit (OTP bit) which locks the Protect
Register content.
The data is then clocked out serially. The address
pointer is automaticallyincremented after the data
is output and, if the Chip Select input (S) is held
High, the ST93CS56/57 can output a sequential
stream of data words. In this way, the memory can
be read as a data stream of 16 to 2048 bits, or
continuouslyas the address counterautomatically
rolls over to 00 when the highest address is
reached. Within the time required by a program-
ming cycle (tW), up to 4 words may be written with
the help of the Page Write instruction; the whole
memory may also be erased, or set to a predeter-
mined pattern, by using the Write All instruction.
Programming is internally self-timed (the external
clock signal on C input may be disconnectedor left
running after the start of a Write cycle) and does
not requirean erasecycle priorto the Writeinstruc-
tion. The Writeinstruction writes 16bits at onetime
into one of the 128 words, the Page Write instruc-
tion writes up to 4 words of 16 bits to sequential
locations, assuming in both cases that all ad-
dresses are outside the Write Protected area.
After the start of the programming cycle, a
Ready/Busysignal is available on the Data output
(Q) when the Chip Select (S) input pin is driven
High.
Within the memory, an user defined area may be
protected against further Write instructions. The
size of this area is defined by the content of a
2/16
ST93CS56, ST93CS57
AC MEASUREMENT CONDITIONS
Figure 3. AC Testing Input Output Waveforms
Input Rise and Fall Times
Input Pulse Voltages
≤ 20ns
0.8V
CC
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
0.7V
CC
Input and Output Timing
Reference Voltages
0.3V
CC
0.2V
CC
AI00825
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Table 3. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
Unit
pF
5
5
COUT
VOUT = 0V
pF
Note: 1. Sampled only, not 100% tested.
Table 4. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS56 and
VCC = 2.5V to 5.5V for ST93CS57)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±2.5
µA
0V ≤ VOUT ≤ VCC
,
ILO
ICC
Output Leakage Current
±2.5
µA
Q in Hi-Z
Supply Current (TTL Inputs)
S = VIH, f = 1 MHz
S = VIH, f = 1 MHz
S = VSS, C = VSS
4.5V ≤ VCC ≤ 5.5V
3V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
3V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
IOL = 2.1mA
3
2
mA
mA
µA
V
Supply Current (CMOS Inputs)
Supply Current (Standby)
ICC1
50
Input Low Voltage (ST93CS56,57)
Input Low Voltage (ST93CS56)
Input Low Voltage (ST93CS57)
Input High Voltage (ST93CS56,57)
Input High Voltage (ST93CS56)
Input High Voltage (ST93CS57)
–0.1
–0.1
0.8
VIL
0.2 VCC
0.2 VCC
VCC + 1
VCC + 1
VCC + 1
0.4
V
–0.1
V
2
V
VIH
0.8 VCC
0.8 VCC
V
V
V
VOL
Output Low Voltage
Output High Voltage
I
OL = 10 µA
0.2
V
IOH = –400µA
IOH = –10µA
2.4
V
VOH
VCC – 0.2
V
3/16
ST93CS56, ST93CS57
Table 5. AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS56 and
VCC = 2.5V to 5.5V for ST93CS57)
Symbol
tPRVCH
tWVCH
tSHCH
tDVCH
tCHDX
tCHQL
tCHQV
tCLPRX
tSLWX
tCLSL
tSLSH
tSHQV
tSLQZ
tCHCL
tCLCH
tW
Alt
tPRES
tPES
tCSS
tDIS
tDIH
tPD0
tPD1
tPREH
tPEH
tCSH
tCS
Parameter
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Chip Select High to Clock High
Input Valid to Clock High
Test Condition
Min
50
Max
Unit
ns
50
ns
50
ns
100
100
ns
Clock High to Input Transition
Clock High to Output Low
ns
500
500
ns
Clock High to Output Valid
ns
Clock Low to Protect Enable Transition
Chip Select Low to Write Enable Transition
Clock Low to Chip Select Transition
Chip Select Low to Chip Select High
Chip Select High to Output Valid
Chip Select Low to Output Hi-Z
Clock High to Clock Low
0
ns
250
0
ns
ns
Note 1
250
ns
tSV
500
300
ns
tDF
ns
tSKH
tSKL
tWP
Note 2
Note 2
250
250
ns
Clock Low to Clock High
ns
Erase/Write Cycle time
10
1
ms
MHz
fC
fSK
Clock Frequency
0
Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clockperiod of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
PRE
tPRVCH
W
tWVCH
tSHCH
tCHCL
C
S
D
tCLCH
tDVCH
START
tCHDX
OP CODE
OP CODE
OP CODE INPUT
START
AI00887
4/16
ST93CS56, ST93CS57
Figure 5. Synchronous Timing, Read or Write
C
S
tCLSL
tSLSH
tDVCH
tCHDX
tCHQV
A0
D
Q
An
tSLQZ
Q0
tCHQL
Hi-Z
Q15/Q7
ADDRESS INPUT
DATA OUTPUT
AI00820C
PRE
W
tCLPRX
tSLWX
C
tCLSL
S
tSLSH
tDVCH
tCHDX
A0/D0
An
D
Q
tSHQV
BUSY
tW
tSLQZ
Hi-Z
READY
ADDRESS/DATA INPUT
WRITE CYCLE
AI00888B
5/16
ST93CS56, ST93CS57
POWER-ON DATA PROTECTION
appliedon the Chip Select(S) input (assumingthat
the Clock C is low). The data input D is then
sampled upon the following rising edges of the
clock C until a ’1’ is sampled and decoded by the
ST93CS56/57 as a Start bit.
The ST93CS56/57 is fabricated in CMOS technol-
ogy and is thereforeable to runfrom zero Hz (static
input signals) upto the maximum ratings (specified
in Table5).
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset(POR)circuit resetsall internalprogramming
circuitry and sets the device in the Write Disable
mode. When VCC reaches its functional value, the
device is properlyreset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction. A stable VCC must be applied before
any logic signal.
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are de-
coded and the data from thememory is transferred
into anoutputshift register. Adummy’0’bitis output
first followedby the 16 bit word with the MSB first.
INSTRUCTIONS
The ST93CS56/57 has eleven instructions, as
shown in Table 6. Each instruction is composedof
a 2 bit op-code and an 8bit address. Each instruc-
tion is preceded by the rising edge of the signal
Table 6. Instruction Set
W
PRE
pin
Op
Code
Additional
Information
Instruction
Description
Address (1, 2)
Data
pin (1)
Read Data from
Memory
READ
X
’0’
10
01
A7-A0
Q15-Q0
Write is executed if
the address is not
inside the Protected
area
WRITE
Write Data to Memory
’1’
’0’
A7-A0
D15-D0
D15-D0
Write is executed if
all the addresses
are not inside the
Protected area
PAWRITE
WRALL
Page Write to Memory
Write All Memory
’1’
’1’
’0’
’0’
11
00
A7-A0
Write all data if the
01XX XXXX
D15-D0 Protect Register is
cleared
WEN
WDS
Write Enable
Write Disable
’1’
X
’0’
’0’
00
00
11XX XXXX
00XX XXXX
Data Output =
Protect Register
content + Protect
Flag bit
PRREAD
Protect Register Read
X
’1’
10
XXXX XXXX
Q8-Q0
Data above
specified address
A7-A0 are
PRWRITE
PRCLEAR
Protect Register Write
Protect Register Clear
’1’
’1’
’1’
’1’
01
11
A7-A0
protected (2)
Protect Flag is also
cleared (cleared
Flag = 1)
1111 1111
PREN
PRDS
Protect Register Enable
Protect Register Disable
’1’
’1’
’1’
’1’
00
00
11XX XXXX
0000 0000
OTP bit is set
permanently
Notes: 1. X = don’t care bit.
2. Address bit A7 is not decoded by the ST93CS56/57.
6/16
ST93CS56, ST93CS57
Output data changes are triggered by the Low to
High transition of the Clock (C). The ST93CS56/57
will automatically increment the address and will
clock out the next word as long as the Chip Select
input (S) is held High. In this case the dummy ’0’ bit
is NOT output between words and a continuous
stream of data can be read.
After the LSB of the last data word, Chip Select (S)
must be broughtLow beforethe next risingedge of
the Clock (C). The falling edge of Chip Select (S)
initiates the internal, self-timed write cycle. The
Page Write operation will not be performed if any
of the 4 words is addressing the protected area. If
the ST93CS56/57 is still performing the program-
ming cycle, the Busy signal (Q = 0) will be returned
if the Chip Select input (S) is driven high, and the
ST93CS56/57 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the ST93CS56/57is ready toreceivea newinstruc-
tion.
Write Enable and Write Disable
TheWrite Enableinstruction (WEN)authorizesthe
following Write instructions to be executed, the
Write Disable instruction (WDS) disables the exe-
cution of the following Erase/Write instructions.
When power is first applied, the ST93CS56/57
enters the Disable mode. When the Write Enable
instruction (WEN) is executed, Write instructions
remain enabled until a Write Disable instruction
(WDS) is executed or if the Power-on reset circuit
becomes active due to a reduced VCC. To protect
the memory contentsfrom accidental corruption, it
is advisable to issue the WDS instruction after
every write cycle.
Write All
The WriteAll instruction (WRALL) is valid onlyafter
the ProtectRegisterhas beencleared byexecuting
a PRCLEAR (Protect Register Clear) instruction.
The Write All instructionsimultaneously writes the
whole memory with the same data word included
in theinstruction.TheWriteEnablesignal (W) must
be held High before and during the Write instruc-
tion. Input address and data are read on the Low
to Hightransitionofthe clock. If the ST93CS56/57
is still performing the programming cycle, the Busy
signal (Q = 0) will be returned if the Chip Select
input (S) is driven high, and the ST93CS56/57 will
ignore any data on the bus. When the write cycle
is completed,the Ready signal (Q = 1) will indicate
(if S is driven high) that the ST93CS56/57 is ready
to receivea new instruction.
The READ instruction is not affected by the WEN
or WDS instructions.
Write
The Write instruction (WRITE) is followed by the
address and the word to be written. The Write
Enable signal (W) must be held high during the
WRITE instruction. Data input D is sampled on the
Low to High transition of the clock. After the last
data bit has been sampled, Chip Select (S) must
be brought Low before the next rising edge of the
clock (C), inorder to start the self-timed program-
mingcycle, providing thattheaddressis NOTin the
protected area. If the ST93CS56/57 is still per-
forming the programming cycle, the Busy signal (Q
= 0) will be returnedif the Chip Select input (S) is
driven high, and the ST93CS56/57will ignore any
dataon the bus. Whenthe write cycle is completed,
the Ready signal (Q = 1) will indicate (if S is driven
high) that the ST93CS56/57 is ready to receive a
new instruction.
MEMORY WRITE PROTECTION AND PROTECT
REGISTER
The ST93CS56/57 offers a Protect Register con-
taining the bottom address of the memory area
which has to be protected against write instruc-
tions. In addition to this Protect Register, two flag
bits are usedtoindicatetheProtectRegisterstatus:
the Protect Flag enabling/disabling the protection
of theProtectRegister andtheOTPbit which, when
set, disables access to the Protect Register and
thus preventsany further modifications of this Pro-
tect Register value. The content of the Protect
Register is defined when using the PRWRITE in-
struction, it may be read when using the PRREAD
instruction. A specific instruction PREN (Protect
Register Enable) allows the user to execute the
protect instructions PRCLEAR, PRWRITE and
PRDS; this PREN instruction being used together
with the signals applied on the input pins PRE
(Protect Register Enable pin) and W (Write En-
able).
Page Write
APage Write instruction (PAWRITE) contains the
first address to be written followed by up to 4 data
words. The Write Enable signal (W) must be held
High duringtheWrite instruction.Inputaddressand
data are read on the Low to High transition of the
clock. After the receipt of each data word, bits
A1-A0 of the internal address register are incre-
mented, the high order bits A7-A2 remaining un-
changed. Users must take care by software to
ensurethat the lastword addresshasthe samefive
upper order address bits as the initial address
transmitted to avoid address roll-over.
7/16
ST93CS56, ST93CS57
Figure 6. READ, WRITE, WEN, WDS Sequences
READ
PRE
S
D
1 1 0 An
A0
Q
Qn
Q0
ADDR
DATA OUT
OP
CODE
WRITE
PRE
W
S
CHECK
STATUS
D
1 0 1 An
A0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
WRITE
ENABLE
PRE
W
WRITE
DISABLE
PRE
S
S
D
1 0 0 0 0 Xn X0
D
1 0 0 1 1 Xn X0
OP
CODE
OP
CODE
AI00889D
8/16
ST93CS56, ST93CS57
Figure 7. PAWRITE, WRALL Sequences
PAGE
WRITE
PRE
W
S
CHECK
STATUS
D
1 1 1 An
A0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
WRITE
ALL
PRE
W
S
CHECK
STATUS
D
1 0 0 0 1 Xn X0 Dn
D0
Q
ADDR
OP
DATA IN
BUSY
READY
CODE
AI00890C
9/16
ST93CS56, ST93CS57
MEMORY WRITE PROTECTION (cont’d)
protectedfrom writing. TheProtect Flag bit is set to
’0’, it can be read with Protect Register Read
instruction. Both the Protect Enable (PRE) and
Write Enable (W) input pins must be driven High
during the instructionexecution.
Accessing the Protect Register is done by execut-
ing the followingsequence:
– WEN: execute the Write Enable instruction,
– PREN: execute the PREN instruction,
– PRWRITE, PRCLEAR or PRDS: the protection
then may be defined, in terms of size of the
protected area (PRWRITE, PRCLEAR) and
may be set permanently(PRDS instruction).
Note: A PREN instruction must immediately pre-
cede the PRWRITE instruction, but it is not neces-
sary to execute first a PRCLEAR.
Protect Register Disable
The Protect Register Disable instruction sets the
One Time Programmable bit(OTP bit). TheProtect
RegisterDisable instruction(PRDS) isaONETIME
ONLYinstruction which latches the Protect Regis-
ter content, this content is therefore unalterable in
thefuture. BoththeProtect Enable(PRE) andWrite
Enable (W) input pins must be driven High during
the instruction execution. The OTP bit cannot be
directly read, it can be checked by reading the
content of the Protect Register (PRREAD instruc-
tion), then by writing this same value into the Pro-
tect Register (PRWRITE instruction): when the
OTP bit is set, the Ready/Busy status cannot ap-
pear on the Data output (Q); when the OTP bit is
not set, the Busy status appear on the Data output
(Q).
Protect Register Read
The Protect Register Read instruction (PRREAD)
outputs on the Data Output Q the content of the
Protect Register, followed by the Protect Flag bit.
The Protect Register Enable pin (PRE) must be
driven High beforeand duringthe instruction. As in
the Read instructiona dummy ’0’ bit is output first.
Since it is not possible to distinguish if the Protect
Register is cleared (all 1’s) or if it is written with all
1’s, user must check the Protect Flag status (and
not the Protect Register content) to ascertain the
setting of the memory protection.
Protect Register Enable
The Protect Register Enableinstruction (PREN) is
used to authorize the use of further PRCLEAR,
PRWRITE and PRDS instructions. The PREN
insruction does not modify the Protect Flag bit
value.
APREN instruction must immediately precede the
PRDS instruction.
READY/BUSY Status
Note: A Write Enable (WEN) instruction must be
executed before the Protect Enable instruction.
Both the Protect Enable (PRE) and Write Enable
(W) inputpinsmust beheld Highduringthe instruc-
tion execution.
When the ST93CS56/57 is performing the write
cycle, the Busy signal (Q = 0) is returned if S is
driven high, and the ST93CS56/57will ignore any
dataon thebus. When the write cycle is completed,
the Ready signal (Q = 1) will indicate, if S is driven
high, that the ST93CS56/57 is ready to receive a
new instruction. Once the ST93CS56/57is Ready,
the Data Output Q is set to ’1’ until a new Start bit
is decoded or the Chip Select is brought Low.
Protect Register Clear
The Protect Register Clear instruction (PRCLEAR)
clears the addressstored in the Protect Register to
all 1’s, and thus enables the execution of WRITE
and WRALL instructions. The Protect Register
Clear execution clears the Protect Flag to ’1’. Both
the Protect Enable (PRE) and Write Enable (W)
input pins must be driven High during the instruc-
tion execution.
Note: A PREN instruction must immediately pre-
cede the PRCLEAR instruction.
Protect Register Write
The Protect Register Write instruction (PRWRITE)
is used to write into the Protect Register the ad-
dress of the first word to be protected. After the
PRWRITE instruction execution, all memory loca-
tions equal to andabovethe specifiedaddress, are
COMMON I/O OPERATION
TheData Output (Q)andDataInput(D) signalscan
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memory with this connection,mostly to prevent
a short circuit between the last entered address bit
(A0) and the first data bit output by Q. The reader
should refer to the SGS-THOMSON application
note”MICROWIRE EEPROMCommon I/OOpera-
tion”.
10/16
ST93CS56, ST93CS57
Figure 8. PRREAD, PRWRITE, PREN Sequences
Protect
Register
READ
PRE
S
D
1 1 0 Xn
X0
Q
An
A0 F
ADDR
DATA
OUT
F = Protect Flag
OP
CODE
Protect
Register
WRITE
PRE
W
S
CHECK
STATUS
D
1 0 1 An
A0
Q
ADDR
BUSY
READY
OP
CODE
Protect
Register
ENABLE
PRE
W
S
D
1 0 0 1 1 Xn X0
OP
CODE
AI00891D
11/16
ST93CS56, ST93CS57
Figure 9. PRCLEAR, PRDS Sequences
Protect
Register
CLEAR
PRE
W
S
CHECK
STATUS
D
1 1 1
1 1 1
Q
ADDR
BUSY
READY
OP
CODE
Protect
Register
DISABLE
PRE
W
S
CHECK
STATUS
D
1 0 0
0 0 0
Q
ADDR
BUSY
READY
OP
CODE
AI00892C
12/16
ST93CS56, ST93CS57
ORDERING INFORMATION SCHEME
Example:
ST93CS56
M
1
013TR
Operating Voltage
56 3V to 5.5V
Package
Temp. Range
Option
B
PSDIP8
0.4 mm Frame
1
0 to 70 °C
013TR Tape & Reel
Packing
57 2.5V to 5.5V
6
–40 to 85 °C
M
SO8
150mil Width
3 (1) –40 to 125 °C
Note: 1. Temperature range on special request only.
Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the SGS-THOMSON Sales Office nearest to you.
13/16
ST93CS56, ST93CS57
PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame
mm
Min
inches
Min
Symb
Typ
Max
4.80
–
Typ
Max
0.189
–
A
A1
A2
B
0.70
3.10
0.38
1.15
0.38
9.20
–
0.028
0.122
0.015
0.045
0.015
0.362
–
3.60
0.58
1.65
0.52
9.90
–
0.142
0.023
0.065
0.020
0.390
–
B1
C
D
E
E1
e1
eA
eB
L
7.62
2.54
0.300
0.100
6.30
–
7.10
–
0.248
–
0.280
–
8.40
–
0.331
–
9.20
3.80
0.362
0.150
3.00
8
0.118
8
N
CP
0.10
0.004
PSDIP8
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not to scale
14/16
ST93CS56, ST93CS57
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
SO8
h x 45°
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Drawing is not to scale
15/16
ST93CS56, ST93CS57
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
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