ST95020 [STMICROELECTRONICS]
4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe; 4K / 2K / 1K串行SPI EEPROM，带有正时钟选通
| 型号： | ST95020 |
| 厂家： | 
ST |
| 描述： | 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe |
| 文件： | 总18页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST95040
ST95020, ST95010
4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
1 MILLIONERASE/WRITE CYCLES
40 YEARSDATARETENTION
SINGLE SUPPLYVOLTAGE
– 4.5V to 5.5V for ST950x0
– 2.5V to 5.5V for ST950x0W
SPI BUS COMPATIBLE SERIALINTERFACE
8
2 MHzCLOCK RATE MAX
8
BLOCK WRITE PROTECTION
STATUS REGISTER
1
1
16 BYTE PAGE MODE
PSDIP8 (B)
SO8 (M)
0.25mm Frame
150mil Width
WRITE PROTECT
SELF-TIMED PROGRAMMINGCYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
Figure 1. Logic Diagram
DESCRIPTION
The ST950x0 is a family of Electrically Erasable
Programmable Memories (EEPROM) fabricated
with STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology. Each memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serialdata output
(Q).
V
CC
D
C
S
Q
Table 1. Signal Names
ST950x0
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
W
D
HOLD
Q
S
V
SS
W
AI01435B
HOLD
VCC
VSS
Supply Voltage
Ground
June 1998
1/18
ST95040, ST95020, ST95010
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST950x0
ST950x0
S
Q
1
2
3
4
8
V
S
Q
1
2
3
4
8
V
CC
HOLD
CC
7
HOLD
7
W
6
5
C
D
W
6
5
C
D
V
V
SS
SS
AI01436B
AI01437B
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
Ambient Operating Temperature
Storage Temperature
–40 to 125
–65 to 150
°C
TSTG
C
°
TLEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
C
°
VO
VI
Output Voltage
–0.3 to VCC +0.6
–0.3 to 6.5
–0.3 to 6.5
4000
V
Input Voltage with respect to Ground
Supply Voltage
V
V
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
VESD
500
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500Ω)
3. EIAJ IC-121 (Condition C) (200pF, 0Ω)
DESCRIPTION
SIGNALS DESCRIPTION
(cont’d)
SerialOutput (Q). Theoutput pinis used totrans-
fer data serially out of the Memory. Data is shifted
out on the falling edge of the serial clock.
Serial Input (D). The input pin is used to transfer
dataseriallyinto thedevice.Itreceivesinstructions,
addresses, and the data to be written. Input is
latched on the rising edge of the serial clock.
The device connectedto the bus is selectedwhen
thechip selectinput(S) goeslow. Communications
with the chip can be interrupted with a hold input
(HOLD). The write operation is disabled by a write
protect input (W).
Data is clocked in during the low to high transition
of clock C, data is clocked out during the high to
low transitionof clock C.
2/18
ST95040, ST95020, ST95010
Figure 3. Data and Clock Timing
CPOL
0
CPHA
0
C
1
1
C
D or Q
MSB
LSB
AI01438
Figure 4. Microcontroller and SPI Interface Set-up
MICROCONTROLLER
(ST6, ST7, ST9, ST10, OTHERS)
SCK
C
SPI Interface with
(CPOL, CPHA) =
(’0’, ’0’) or (’1’, ’1’)
ST95xx0
SDI
Q
D
SDO
AI01439B
Serial Clock (C).
The serial clock provides the
power-on, a high to low transition on S is required
prior to the start of any operation.
timing of the serial interface. Instructions, ad-
dresses,ordatapresentat theinputpinare latched
on the rising edge of the clock input, while data on
theQ pinchangesafterthe fallingedgeof the clock
input.
Write Protect (W).
This pin is for hardware write
protection. When W is low, writes to the Memory
aredisabledbutanyotheroperationsstayenabled.
When Wis high,all writes operationsare available.
W going low at any time before the last bit D0 of
thedata streamwill resetthewrite enablelatchand
prevent programming. No action on W or on the
write enable latch can interrupt a write cycle which
has commenced.
Chip Select (S).
When S is high, the Memory is
deselected and the Q output pin is at high imped-
ance and, unless an internal write operation is
underwaythe Memorywill be in the standby power
mode. S low enables the Memory, placing it in the
active power mode. It should be noted that after
3/18
ST95040, ST95020, ST95010
Hold (HOLD).
The HOLD pin is used to pause
operation. If an invalid instruction is sent (one not
contained in Table 3), the chip is automatically
deselected. For operations that read or write data
in the memory array, bit 3 of the instruction is the
MSB of the address, otherwise, it is a don’t care.
serial communications with the Memory without
resetting the serial sequence. To take the Hold
condition into account, the product must be se-
lected (S = 0). Then the Hold state is validated by
a high tolow transitionon HOLDwhen C islow. To
resumethecommunications,HOLDis broughthigh
while C is low. During the Hold conditionD, Q, and
C are at a high impedance state.
Write Enable (WREN) and Write Disable (WRDI)
The Memory contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation. The WREN instructionwill set the latch
and the WRDI instruction will reset the latch. The
latch is reset under the following conditions:
When the Memoryis underthe Hold condition,it is
possibletodeselectthedevice.However,the serial
communications will remain paused after a rese-
lect, and the chip will be reset.
– W pin is low
– Power on
TheMemorycan bedrivenbyamicrocontrollerwith
its SPI peripheral running in either of the two fol-
lowingmodes:(CPOL, CPHA) = (’0’, ’0’)or (CPOL,
CPHA) = (’1’, ’1’).
– WRDI instruction executed
– WRSR instruction executed
– WRITEinstruction executed
Forthesetwo modes,inputdatais latchedinby the
low to high transitionof clockC, and output data is
available from the high to low transition of Clock
(C).
As soon as the WREN or WRDI instruction is
received by the memory, the circuit executes the
instruction and enters a wait mode until it is dese-
lected.
Thedifferencebetween(CPOL, CPHA)= (0,0)and
(CPOL, CPHA) = (1, 1) is the stand-by polarity: C
remains at ’0’ for (CPOL, CPHA) = (0, 0) and C
remainsat ’1’for(CPOL,CPHA)=(1,1)whenthere
is no data transfer.
Read Status Register (RDSR)
TheRDSRinstructionprovidesaccesstothestatus
register. The status register may be read at any
time, even during a writeto the memory operation.
If a Read Status register reaches the 8th bit of the
Status register, an additional 9th clock pulse will
wrap around to read the 1st bit of the Status Reg-
ister
OPERATIONS
All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
thechip select (S) goes low. Prior to any operation,
a one-byte instruction code must be enteredin the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C). To enter an instructioncode, the productmust
have been previously selected (S = low). Table 3
shows the instruction set and format for device
The status register format is as follows:
b7
1
b0
1
1
1
BP1 BP0 WEL WIP
BP1, BP0: Read and write bits
WEL, WIP: Read only bits.
b7 to b4: Read only bits.
Table 3. Instruction Set
Instruction
WREN
WRDI
Description
Set Write Enable Latch
Instruction Format
0000 0110
Reset Write Enable Latch
Read Status Register
0000 0100
RDSR
0000 0101
WRSR
READ
Write Status Register
0000 0001
Read Data from Memory Array
Write Data to Memory Array
0000 A8011
0000 A8010
WRITE
Notes: A8 = 1, Upper page selected on ST95040.
A8 = 0, Lower page selected on ST95040.
4/18
ST95040, ST95020, ST95010
Figure 5. Block Diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Block
Protect
16 Bytes
X Decoder
AI01272
During a write to the memory operation to the
memory array, all bits BP1, BP0, WEL, WIP are
valid and can be read. During a write to the status
register, only the bits WEL and WIP are valid and
can be read. The values of BP1 and BP0 read at
thattimecorrespondto thepreviouscontentsof the
status register.
When set to a ’1’a writeis in progress,when set to
a ’0’ no write is in progress.
The Write Enable Latch (WEL) read-only bit indi-
catesthe statusofthe writeenable latch. When set
to a ’1’ the latch is set, when set to a ’0’ the latch is
reset. The Block Protect (BP0 and BP1) bits indi-
cate the extent of the protectionemployed. These
bits are set by the user issuing the WRSR instruc-
tion. These bits are non-volatile.
TheWrite-In-Process (WIP) read-onlybit indicates
whetherthe Memory is busywith a writeoperation.
5/18
ST95040, ST95020, ST95010
Figure 6. Read Operation Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
A8
BYTE ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
D
Q
DATA OUT
HIGH IMPEDANCE
1
7
6
5
4
3
2
0
AI01440
Notes: A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only activeon ST95040.
Table 4. Write Protected Block Size
Status Register Bits
Protected Block
Array Address Protected
ST95020 ST95010
BP1
BP0
ST95040
none
0
0
1
1
0
1
0
1
none
none
none
Upper quarter
Upper half
180h - 1FFh
100h - 1FFh
000h - 1FFh
C0h - FFh
60h - 7Fh
40h - 7Fh
00h - 7Fh
80h - FFh
Whole memory
00h - FFh
Write Status Register (WRSR)
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 (seeTable 3)
of the read instruction contains address bit A8
(mostsignificantaddressbit). Thenthe datastored
inthememory attheselectedaddressis shiftedout
on the Q output pin; each bit being shifted out
during the falling edge of the clock (C). The data
stored in the memory at the next address can be
read in sequence by continuing to provide clock
pulses. The byte address is automatically incre-
mented to the next higher address after each byte
of data is shiftedout. When the highestaddress is
reached,theaddresscounterrollsover to0h allow-
ing the read cycle to be continuedindefinitely.The
read operation is terminated by deselecting the
chip.Thechipcanbe deselectedat anytime during
data output. Any read attempt during a write cycle
will be rejected and will deselect the chip.
TheWRSR instructionallowsthe usertoselect the
size of protected memory. The user may read the
blocks but will be unable to write within the pro-
tected blocks. The blocks and respective WRSR
control bits are shown in Table 4.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S.
Thisrising edge of S must appearno laterthan the
16th clock cycle of the WRSR instruction of the
Status Register content (it must not appeara 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Read Operation
Thechipis firstselectedbyputtingS low.Theserial
one byte read instruction is followedby a one byte
6/18
ST95040, ST95020, ST95010
Figure 7. Write Enable Latch Sequence
S
C
D
Q
0
1
2
3
4
5
6
7
HIGH IMPEDANCE
AI01441
Figure 8. Byte Write Operation Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
A8
BYTE ADDRESS
DATA BYTE
1
A7 A6 A5 A4 A3 A2 A1 A0
7
6
5
4
3
2
0
D
Q
HIGH IMPEDANCE
AI01442
Notes: A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only activeon ST95040.
7/18
ST95040, ST95020, ST95010
Figure 9. Page Write Operation Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
D
S
C
D
INSTRUCTION
A8
BYTE ADDRESS
DATA BYTE 1
1
A7 A6 A5 A4 A3 A2 A1 A0
7
6
5
4
3
2
0
7
24 25 26 27 28 29 30 31 8+8N
DATA BYTE 2
DATA BYTE N
DATA BYTE 16
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
AI01443
Notes: A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only activeon ST95040.
Figure 10. RDSR:Read Status Register Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
INSTRUCTION
STATUS REG. OUT
HIGH IMPEDANCE
Q
7
6
5
4
3
2
1
0
MSB
AI01444
8/18
ST95040, ST95020, ST95010
Figure 11. WRSR: Write Status Register Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
INSTRUCTION
STATUS REG.
D
Q
HIGH IMPEDANCE
AI01445
Byte Write Operation
must reside on the same page. The page write
mode is the same as the byte write mode except
that instead of deselectingthe device after the first
byteofdata, upto15additionalbytescanbeshifted
in prior to deselecting the chip. A page address
beginswith addressxxxx 0000 and ends with xxxx
1111.If the addresscounterreaches xxxx 1111and
the clock continues, the counter will roll over to the
firstaddress of the page(xxxx0000) and overwrite
any previously written data. The programming cy-
cle will only start if the S transition occurs just after
the eighth bit of data of a word is received.
Prior to any write attempt, the write enable latch
must be set by issuing the WREN instruction. First
the device is selected(S = low)and a serial WREN
instruction byte is issued. Then the product is de-
selectedby taking S high. After the WREN instruc-
tion byte is sent, the Memory will set the write
enable latch and then remain in standby until it is
deselected. Then the write state is entered by
selecting the chip, issuing two bytes of instruction
and address, and one byte of data.
Chip Select (S) must remain low for the entire
duration of the operation. The product must be
deselectedjust afterthe eighthbitof datahasbeen
latchedin. If not,the write process is cancelled.As
soon as the product is deselected, the self-timed
writecycleisinitiated. Whilethewrite isin progress,
thestatusregistermay be readto checkBP1,BP0,
WEL and WIP. WIP is high during the self-timed
write cycle. When the cycle is completed,the write
enable latch is reset.
POWER ON STATE
After a Power up the Memory is in the following
state:
– The device is in the low power standby state.
– The chip is deselected.
– The chip is not in hold condition.
– The write enable latch is reset.
Page Write Operation
– BP1 and BP0 are unchanged (non-volatile
bits).
A maximum of 16 bytes of data may be written
during one non-volatile write cycle. All 16 bytes
9/18
ST95040, ST95020, ST95010
Figure 12. EEPROM and SPI Bus
D
Q
C
MASTER
C
Q
D
C
Q
D
C Q D
ST95xxx
ST95xxx
ST95xxx
CS3 CS2 CS1
S
S
S
AI01446
DATA PROTECTION AND PROTOCOL SAFETY
– All inputs are protectedagainstnoise, see Table
6.
– Afterany of theoperationsWREN,WRDI,RDSR
is completed, the chip enters a wait state and
waits for a deselect.
– The write enable latch is reset upon power-up.
– Thewriteenablelatchis resetwhenWis brought
low.
– Non valid S and HOLD transitionsare not taken
into account.
– S must come high at the proper clock count in
order to start a non-volatile write cycle (in the
memory array or in the status register), that is
theChipSelectSmustriseduringtheclockpulse
following the introduction of a multiple of 8 bits.
– Access to the memory array during non-volatile
programmingcycleis ignored;however,the pro-
gramming cycle continues.
INITIAL DELIVERY STATE
Thedevice is delivered with the memory array in a
fully erased state (all data set at all ”1’s” or FFh).
The block protect bits are initialized to 00.
10/18
ST95040, ST95020, ST95010
Table 5. AC Measurement Conditions
Figure 13. AC Testing Input Output Wavef.
Input Rise and Fall Times
Input Pulse Voltages
50ns
≤
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
CL = 100pF
0.8V
CC
0.7V
CC
Input and Output Timing
Reference Voltages
0.3V
CC
0.2V
CC
Output Load
AI00825
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 6. Input Parameters (1) (TA = 25 °C, f = 2 MHz )
Symbol
CIN
Parameter
Input Capacitance (D)
Min
Max
8
Unit
pF
CIN
Input Capacitance (other pins)
6
pF
tLPF
Input Signal Pulse Width Filtered Out
10
ns
Note: 1. Sampled only, not 100% tested.
Table 7. DC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 4.5V to 5.5V or 2.5Vto 5.5V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
Unit
µA
±2
ILO
2
±
A
µ
C = 0.1 VCC/0.9 VCC
@ 2 MHz, Q = Open
,
2
mA
mA
Supply Current
C = 0.1 VCC/0.9 VCC
@ 2 MHz, Q = Open, Note 2
,
2
ICC
C = 0.1 VCC/0.9 VCC
@ 1 MHz, VCC = 2.5V,
Q = Open
,
Supply Current (W series)
Standby Current
1.5
mA
S = VCC, VIN = VSS or VCC
50
50
µA
µA
S = VCC, VIN = VSS or VCC
Note 2
,
ICC1
S = VCC, VIN = VSS or VCC
,
Standby Current (W series)
25
µA
V
CC = 2.5V
VIL
VIH
Input Low Voltage
Input High Voltage
– 0.3
0.3 VCC
VCC + 1
0.4
V
V
V
V
V
V
V
V
0.7 VCC
IOL = 2mA
Output Low Voltage
(1)
VOL
I
OL = 2mA, Note 2
0.4
Output Low Voltage (W series)
Output High Voltage
I
OL = 1.5mA, VCC = 2.5V
0.4
I
OH = –2mA
IOH = –2mA, Note 2
IOH = –0.4mA, VCC = 2.5V
VCC –0.6
VCC –0.6
VCC –0.3
(1)
VOH
Output High Voltage (W series)
Notes: 1. The device meets output requirements for both TTL and CMOS standards.
2. Test performed at –40 to 125°C temperature range, grade 3.
11/18
ST95040, ST95020, ST95010
Table 8. AC Characteristics
ST95040 / 020 / 010
VCC = 4.5V to 5.5V,
VCC = 4.5V to 5.5V,
TA = 0 to 70 C,
V
CC = 2.5V to 5.5V,
TA = 0 to 70 C,
Symbol
Alt
Parameter
Unit
°
°
TA = –40 to 125 C
°
TA = –40 to 85 C
TA = –40 to 85 C
°
°
Min
D.C.
100
Max
Min
D.C.
100
Max
Min
D.C.
200
Max
fC
fC
Clock Frequency
2
2
1
MHz
ns
tSLCH
tCSS
S Active Setup Time
S Not Active Hold
Time
tCHSL
100
100
200
ns
(1)
tCH
tCLH
tCLL
tRC
tFC
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
190
200
200
200
400
400
ns
ns
(1)
tCL
tCLCH
tCHCL
tDVCH
tCHDX
tDLDH
tDHDL
tHHCH
tHLCH
tCLHL
1
1
1
1
1
1
s
µ
µs
ns
ns
tDSU
tDH
tRI
Data In Setup Time
Data In Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
Clock Low Hold Time
HOLD Hold Time
50
50
50
50
100
100
1
1
1
1
1
1
s
s
µ
µ
tFI
tHSU
100
90
100
90
200
200
200
ns
ns
ns
tHH
80
80
Clock Low Set-up
Time
tCLHH
tCHSH
tSHCH
100
200
100
200
100
200
100
200
200
200
200
200
ns
ns
ns
S Active Hold Time
S Not Active Setup
Time
tSHSL
tSHQZ
tCSH
tDIS
S Deselect Time
ns
ns
Output Disable Time
150
240
150
300
200
400
Clock Low to Output
Valid
tCLQV
tV
ns
tCLQX
tHO
tRO
tFO
Output Hold Time
Output Rise Time
Output Fall Time
0
0
0
ns
ns
ns
(2)
tQLQH
100
100
100
100
200
200
(2)
tQHQL
HOLD High to Output
Low-Z
tHHQX
tLZ
100
100
200
ns
HOLD Low to Output
High-Z
tHLQZ
tW
tHZ
130
10
130
10
200
10
ns
tWP
Write Cycle Time
ms
Notes:
≥
1. tCH + tCL 1/fc
2. Value guaranteed by characterization, not 100% tested in production.
12/18
ST95040, ST95020, ST95010
Figure 14. Serial Input Timing
tSHSL
tSHCH
tCHCL
S
tCHSL
tSLCH
tCHSH
C
tDVCH
tCHDX
tCLCH
LSB IN
MSB IN
D
Q
tDLDH
tDHDL
HIGH IMPEDANCE
AI01447
Figure 15. Hold Timing
S
C
tHLCH
tCLHL
tHHCH
tCLHH
tHHQX
tHLQZ
Q
D
HOLD
AI01448
13/18
ST95040, ST95020, ST95010
Figure 16. Output Timing
S
C
tCH
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
ADDR.LSB IN
D
AI01449B
14/18
ST95040, ST95020, ST95010
ORDERING INFORMATION SCHEME
Example:
ST95xx0
W
M
6
TR
Density
Option
04 4K (512 x 8)
02 2K (256 x 8)
01 1K (128 x 8)
TR Tape & Reel
Packing
Data Strobe
Operating Voltage
Package
Temperature Range
0
Note 1
blank 4.5V to 5.5V
B
PSDIP8
0.25 mm Frame
1
6
0 to 70 C
°
W
2.5V to 5.5V
–40 to 85 °C
M
SO8
150mils Width
3 (2) –40 to 125 °C
Notes: 1. Data In is strobed on rising edge of the clock (C) and Data Out is synchronized from the falling edge of the clock.
2. Temperature range on request only, 5V ± 10% only.
Devices are shipped from the factorywith the memory content set at all ”1’s” (FFh).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.
15/18
ST95040, ST95020, ST95010
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
Min
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
inches
Min
Symb
Typ
Max
5.90
–
Typ
Max
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
E1
e1
eA
eB
L
7.62
2.54
0.300
0.100
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
CP
0.10
0.004
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not to scale
16/18
ST95040, ST95020, ST95010
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
6.20
0.50
0.90
0.228
0.010
0.016
0.244
0.020
0.035
L
0
°
8
°
0
°
8
°
α
N
CP
8
8
0.10
0.004
h x 45°
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Drawing is not to scale
17/18
ST95040, ST95020, ST95010
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such informationnor for any infringementof patents or other rights of third parties which may result from its use. No licenseis granted
by implication or otherwise under any patentor patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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18/18
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