STA027_技术文档

STA027

SBC CODEC

PRODUCT PREVIEW

Features

■ Fully Integrated SBC Encoder And Decoder

■ Operating Modes:

– SBC encoder mode (PCM In/Serial Output)

–

PCM input: 16, 32, 44.1, 48kHz

Channel Mode: Mono, Dual,

Stereo

Subbands: 4 OR 8

Allocation Methods:

Loudness/SNR

TQFP64

■ Wireless Audio Dongle

■ PC Wireless Speakers

■ Generic Compressed Audio LinkS

■ Wireless Headphone/Headsets

– SBC Decoder Mode

–

Serial Input

PCM Output: 16, 32, 44.1, 48kHz

■ Digital Volume

Description

■ Bass & Treble Control

STA027 is a fully integrated SBC codec targeting

wireless audio transmission such as DVD rear

channels wireless speakers, USB dongle, PC

wireless speakers. The device is fully controllable

■ Serial Bitstream Input/output Interface up to

2Mbit/s

■ Easy Programmable ADC Input Interface

2

through a standard I C bus.

2

■ Serial PCM Output Interface (I S and other

Formats)

Compression Engine

■ PLL for Internal Clock and for Output PCM

Clock Generation

SBC

2

■ I C Control Bus

The SBC Subband Coding engine can be used

when high quality audio is required in wireless

applications (such as Bluetooth). SBC is an audio

coding system specially designed for Bluetooth

AV applications to obtain high quality audio at

medium bit rates, and having a low computational

complexity. SBC uses 4 or 8 subbands, adaptive

bit allocation algorithm, and simple adaptive block

PCM quantizers..

■ Low Power 2.4V CMOS Technology with 3.3V

Tolerant and Capable I/O

Applications

■ bluetooth AV Applications

■ DVD Wirless Speaker Options

Order codes

Part number

Package

TQFP64

Packing

STA027

Tube

Rev 1

1/44

September 2005

CD00066274

www.st.com

44

STA027

Contents

1

Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Typical bluetooth wireless audio application . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

3

Pins description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

3.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4

5

Host register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1

5.2

Version registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.1 VERSION : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.2 IDENT : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.3 SOFT_VERSION : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PLL_AUDIO_CONFIGURATION registers description . . . . . . . . . . . . . . . . . 16

5.2.1 PLL_AUDIO_PEL_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2.2 PLL_AUDIO_PEH_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2.3 PLL_AUDIO_NDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2.4 PLL_AUDIO_XDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2.5 PLL_AUDIO_MDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2.6 PLL_AUDIO_PEL_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.7 PLL_AUDIO_PEH_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.8 PLL_AUDIO_NDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.9 PLL_AUDIO_XDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.10 PLL_AUDIO_MDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3

PLL_SYSTEM_CONFIGURATION registers description . . . . . . . . . . . . . . . 19

5.3.1 PLL_SYSTEM_PEL_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3.2 PLL_SYSTEM_PEH_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3.3 PLL_SYSTEM_NDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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STA027

5.3.4 PLL_SYSTEM_XDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.3.5 PLL_SYSTEM_MDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.3.6 PLL_SYSTEM_PEL_42_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.3.7 PLL_SYSTEM_PEH_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3.8 PLL_SYSTEM_NDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3.9 PLL_SYSTEM_XDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3.10 PLL_SYSTEM_MDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4

I2Sout_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . 23

5.4.1 OUTPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4.2 PCM_DIV : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4.3 PCM_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4.4 PCM_CROSS : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.5

5.6

GPSO_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . 25

5.5.1 OUTPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.5.2 GPSO_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

I2Sin_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . . 27

5.6.1 INPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.6.2

I_AUDIO_CONFIG_1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.6.3 I_AUDIO_CONFIG_2 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.6.4 I_AUDIO_CONFIG_3 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.7

5.8

SDI_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . . . 29

5.7.1 POL_REQ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.7.2 INPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.7.3

I_AUDIO_CONFIG_1 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

COMMAND registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.8.1 SOFT_RESET : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.8.2 CK_CMD : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.8.3 DEC_SEL : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.8.4 RUN : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.8.5 CRC_IGNORE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.8.6 MUTE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.8.7 SKIP : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.8.8 PAUSE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.9

STATUS registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.9.1 STATUS_MODE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.9.2 STATUS_CHANS_NB : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

CD00066274

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STA027

5.9.3 STATUS_SF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.9.4 STATUS_FE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.9.5 HEADER _n: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.10 MIX_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . . . 34

5.10.1 MIX_MODE: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.10.2 MIX_DLA: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.10.3 MIX_DLB: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.10.4 MIX_DRA: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.10.5 MIX_DRB: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.11 TONE_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . 36

5.11.1 TONE_ON: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.11.2 TONE_FCUTH : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.11.3 TONE_FCUTL : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.11.4 TONE_GAINH : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.11.5 TONE_GAINL : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.11.6 TONE_GAIN_ATTEN : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6

7

TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.1

Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

I/O CELL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1

7.2

TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew Rate Control . . 41

TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control

41

7.3

7.4

7.5

TTL Schmitt Trigger Inpud Pad Buffer, 3V capable . . . . . . . . . . . . . . . . . . . . 41

TTL Inpud Pad Buffer, 3V capable with Pull-Up . . . . . . . . . . . . . . . . . . . . . . 41

TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control /

3V capable 42

7.6

TTL Input Pad Buffer, 3V capable, with pull down . . . . . . . . . . . . . . . . . . . . . 42

8

9

Package Informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4/44

CD00066274

STA027

1 Typical application circuit and block diagram

1

Typical application circuit and block diagram

1.1

Block diagram

Figure 1. Block diagram

BSO_LRCK

BSO_DATA

BSO_BCK

SDO

I/F

BSI_BCK

SDI

INPUT BUFFER

GPSO_CK

I/F

BSI_DATA

GPSO_SDO

GPSO_REQ

GPSO

I/F

DREQ

BCKI

SDI

MMDSP

CORE

BCKO

SDO

2

I S IN

I/F

2

PCM OUTPUT

BUFFER

I S OUT

I/F

LRCKI

SBC CODEC

LRCKO

RQST

AUDIO

PLL

SCL

SDA

2

I C

SYSTEM

PLL

2

I C

I/F

OSC

REG BANK

D05AU1615

OSCK

XTI

XTO

1.2

Typical bluetooth wireless audio application

Figure 2. Transmitter block diagram

ENCODER

L

I²S IN

I/F

SDO

I/F

BT

MODULE

ADC

R

STA027

D05AU1616

Figure 3. Receiver block diagram

DECODER

L

I²S OUT

I/F

BT

MODULE

SDI

I/F

DAC

R

STA027

D05AU1617

Note:

for Bluetooth chipset please refer to following device: SLTLC2416, STLC2150, STLC2500. For

ADC and DAC solutions please refer to following devices: STW5094, STW5095, TDA7535.

CD00066274

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2 Pins description and connection diagram

STA027

2

Pins description and connection diagram

2.1

Pin description

Table 1.

pin description

Pin Name

Type

Description

Source/Dest

SDO interface

1

2

3

BSO_LRCK

BSO_BCK

BSO_DATA

I

DSP Interface left/right Clock

DSP interface serial data

DSP interface bit clock

From DSP

SDI interface

4

7

8

9

DREQ

O

I

Bitstream data request

To MCU

BSI_LRCK

BSI_BCK

BSI_DATA

Bitstream interface left/right Clock

Bitstream interface clock

From MCU

I

Bitstream interface serial data

PCM IN interface

12

13

14

LRCKI

I

ADC left/right Clock

ADC bit clock

From ADC

BCKI

SDI

ADC serial data

PCM OUT interface

19

20

21

22

OSCK

O

DAC oversampling clock

DAC Interface left/right Clock

DAC bit clock

To DAC/ADC

To DAC

LRCKO

BCKO

SDO

To DAC

DAC serial data

To DAC

GPSO interface

54

55

56

GPSO_SDO

O

I

GPSO serial data

GPSO bit clock

To MCU

GPSO_CK

From MCU

To MCU

GPSO_REQ

O

GPSO request signal

GPIO interface

26

27

28

31

32

33

IODATA0

I/O

GPIODATA0

GPIODATA1

GPIODATA2

GPIODATA3

GPIODATA4

GPIODATA5

IODATA1

IODATA2

IODATA3

IODATA4

IODATA5

6/44

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STA027

2 Pins description and connection diagram

Table 1.

pin description

Pin Name

Type

Description

Source/Dest

34

35

44

45

46

47

48

49

50

51

IODATA6

IODATA7

IODATA8

IODATA9

IODATA10

IODATA11

IODATA12

IODATA13

IODATA14

IODATA15

I/O

GPIODATA6

GPIODATA7

GPIODATA8

GPIODATA9

GPIODATA10

GPIODATA11

GPIODATA12

GPIODATA13

GPIODATA14

GPIODATA15

HANDSHAKE SIGNALS

I²C data signal

Strobe signal

59

60

RQST

STB

O

I

To MCU

From MCU

I²C LINK

I²C clock signal

I²C data signal

63

64

SCL

SDA

I

From MCU

To MCU

I/O

MISCELLANEOUS

15

16

17

18

25

38

40

-RESET

I

Reset

-TESTEN

XTI

Reserved for test purpose

Oscillator input

I

XTO

O

Oscillator output

CLKOUT

FILT1

Buffered output clock

PLL external filter

FILT0

I

POWER SUPPLY

5

VDD_1

Digital supply (2.5V Power Supply)

Ground

6

VSS_1

VDD_2

VSS_2

VCC_1

VSS_3

VDD_3

VSS_4

10

11

23

24

29

30

Digital supply (2.5V Power Supply)

Ground

Digital supply (3.3V Power Supply)

Ground

Digital supply (2.5V Power Supply)

Ground

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2 Pins description and connection diagram

STA027

Table 1.

pin description

Pin Name

Type

Description

Source/Dest

36

37

39

41

42

43

52

53

57

58

61

62

VDD_4

VSS_5

Digital supply (2.5V Power Supply)

Ground

PLL_VCC

PLL_GND

VCC_2

VSS_6

Digital supply (2.5V Power Supply)

Ground

Digital supply (3.3V Power Supply)

Ground

VSS_7

Ground

VDD_5

VSS_8

Digital supply (2.5V Power Supply)

Ground

VCC_3

VSS_9

Digital supply (3.3V Power Supply)

Ground

VDD_6

Digital supply (2.5V Power Supply)

Figure 4.

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

3

4

5

6

7

8

9

BSO_LRCK

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

IODATA12

IODATA11

IODATA10

IODATA9

IODATA8

VSS_6

BSO_BCK

BSO_DATA

DREQ

VDD_1

VSS_1

BSI_LRCK

BSI_BCK

BSI_DATA

VDD_2

VCC_2

PLL_GND

FILT0

PLL_VCC

FILT1

10

11

12

13

14

VSS_2

LRCK1

VSS_5

BCKI

VDD_4

SDI

IODATA7

IODATA6

IODATA5

RESET

TESTEN

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

D00AU1227

Table 2.

Symbol

Thermal Data

Parameter

Value

85

Unit

R_{th j-amb}

Thermal resistance Junction to Ambient

°C/W

8/44

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STA027

3 Electrical Specification

3

Electrical Specification

3.1

Absolute maximum ratings

Table 3.

Symbol

Absolute Maximum Ratings

Parameter

Value

Unit

V

V_DD

V_CC

Digital Power Supply at 2.5V (nominal)

Digital Power Supply at 3.3V (nominal)

Analog Supply Voltage at 2.5V (nominal)

Voltage on input pins (3.3V pads)

Storage Temperature

-0.5 to 3.3

-0.5 to 4

V

P_LL-V_CC

V_IH/V_IL

T_stg

-0.5 to 3.3

V

-0.5 to V_CC+0.5

V

-40 to +150

-40 to +85(*)

-40 to 125

°C

T_op

Operative ambient temp

T_j

Operating Junction Temperature

3.2

Electrical characteristics

(T

= 25°C; R = 50Ω unless otherwise specified)

g

amb

Table 4.

Symbol

DC Operating Conditions

Parameter

Value

Unit

V

V_DD

V_CC

Power Supply Voltage

2.5 0.25

3.3 0.3

2.5 0.25

V

PLL_V_CC

V

Table 5.

Symbol

General Interface Electrical Characteristics

Parameter

Test Condition

Min. Typ. Max. Unit Note

Low Level Input CurrentWithout pull-

up device

I_IL

V_i= 0V

-10

10

µA

1

High Level Input CurrentWithout pull-

up device

I_IH

V_i= V_DD

-10

µA

1

2

V_esd

Electrostatic Protection

Leakage < 1µA

2000

V

Note: 1 The leakage currents are generally very small, < 1nA. The value given here is a maximum that

can occur after an electrostatic stress on the pin.

2 Human Body Model.

CD00066274

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3 Electrical Specification

STA027

Table 6.

Symbol

DC electrical characteristics

Parameter

Test Condition

Min.

Typ.

Max.

Unit Note

V_IL

V_IH

V_ol

0.2*V_CC

Low Level Input Voltage

High Level Input Voltage

Low Level Output Voltage

High Level Output Voltage

V

0.8*V_CC

0.85*V_CC

0.4V

V

1, 2

I_ol= Xma

V_oh

Note: 1 Takes into account 200mV voltage drop in both supply lines.

2 X is the source/sink current under worst case conditions and is reflected in the name of the I/O

cell according to the drive capability.

Table 7.

Symbol

Parameter

Pull-up current

Test Condition

Min.

Typ.

Max.

Unit

Note

I_pu

-25

-66

-125

µA

1

V_i= 0V; pin numbers 7, 24

and 26

Equivalent Pull-up

Resistance

R_pu

50

kΩ

Note: 1 Min. condition: V = 2.7V, 125°C Min process Max. condition: V = 3.6V, -20°C Max.

DD

Table 8.

Symbol

Power Dissipation

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Note

Sampling_freq ≤24 kHz

Sampling_freq ≤32 kHz

Sampling_freq ≤48 kHz

165

170

185

mW

Power Dissipation@ V_DD

2.4V

=

P_D

Note:

power measurements refer to encoder mode.

10/44

CD00066274

STA027

4 Host register

4

Host register

The following table gives a description of STA027 register list.

2

The STA027 device includes 256 I C registers. In this document, only the user-oriented registers are

described. The undocumented registers are reserved or unused. These registers must never be

accessed (in Read or in Write mode). The Read-Only registers must never be written

We can split the data flux in different time periods (see following diagram) meanwhile host registers can

be read or written :

●

DWT : During Whole Time (at any time during process).

DEC : During External Config (period between RUN=2 and RUN=1).

DBO : During Boot (period between RUN=0 and RUN=2).

ABO : After BOot (period after RUN=1).

AEC : After External Config (period after RUN=2).

EDF : Every Decoded Frame (each time a frame has been decoded).

EDB : Every Decoded Block (each time a block has been decoded).

Figure 5.

SOFT_RESET = 1

CK_CMD = 0

block1

frame1

block2

frame1

block1

frame2

HR

RUN==0 RUN==2 RUN==1

time

DWT

DBO

DEC

ABO

AEC

D01AU1260

EDB

EDF

EDB

CD00066274

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4 Host register

STA027

4.1

Register map

Table 9.

register map by function

Register function Hex

Dec

Name

Type

When

0x00

0x01

0xD3

0xDC

0xDD

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

0xEF

0x66

0x67

0x68

0x69

0x66

0x6A

0x5A

0x5B

0x5C

0x5D

0

VERSION

IDENT

RO

RW

DWT

DEC

VERSION

1

211

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

102

103

104

105

102

106

90

SOFT_VERSION

PLL_AUDIO_PEL_192

PLL_AUDIO_PEH_192

PLL_AUDIO_NDIV_192

PLL_AUDIO_XDIV_192

PLL_AUDIO_MDIV_192

PLL_AUDIO_PEL_176

PLL_AUDIO_PEH_176

PLL_AUDIO_NDIV_176

PLL_AUDIO_XDIV_176

PLL_AUDIO_MDIV_176

PLL_SYSTEM_PEL_50

PLL_SYSTEM_PEH_50

PLL_SYSTEM_NDIV_50

PLL_SYSTEM_XDIV_50

PLL_SYSTEM_MDIV_50

PLL_SYSTEM_PEL_42_5

PLL_SYSTEM_PEH_42_5

PLL_SYSTEM_NDIV_42_5

PLL_SYSTEM_XDIV_42_5

PLL_SYSTEM_MDIV_42_5

OUTPUT_CONF

PLL_AUDIO_CONFIGURATION

PLL_SYSTEM_CONFIGURATION

I²Sout_CONFIGURATION

PCM_DIV

PCM_CONF

PCM_CROSS

OUTPUT_CONF

GPSO_CONFIGURATION

I²Sin_CONFIGURATION

GPSO_CONF

INPUT_CONF

91

I_AUDIO_CONFIG_1

I_AUDIO_CONFIG_2

I_AUDIO_CONFIG_3

92

93

12/44

CD00066274

STA027

Table 9.

4 Host register

register map by function

Register function

Hex

Dec

Name

Type

When

0x59

0x5A

0x5B

0x10

0x3A

0x55

0x56

0x52

0x53

0x57

0x58

0xCC

0xCD

0xCE

0x6F

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0x7b

0x7c

0x7d

0x7e

0x7f

89

90

POL_REQ

RW

WO

RW

RO

RW

DEC

DWT

DBO

DEC

ABO

EDF

ABO

SDI_CONFIGURATION

INPUT_CONF

I_AUDIO_CONFIG_1

SOFT_RESET

CK_CMD

91

16

58

85

DEC_SEL

86

RUN

COMMAND

82

CRC_IGNORE

MUTE

83

87

SKIP

88

PAUSE

204

205

206

111

212

213

214

215

216

217

123

124

125

126

127

117

118

119

120

121

122

STATUS_MODE

STATUS_CHAN_NB

STATUS_SF

STATUS_FE

HEADER_1

HEADER_2

HEADER_3

HEADER_4

HEADER_5

HEADER_6

MIX_MODE

MIX_DLA

STATUS

MIX_CONFIGURATION

MIX_DLB

MIX_DRA

MIX_DRB

0x75

0x76

0x77

0x78

0x79

0x7A

TONE_ON

TONE_FCUTH

TONE_FCUTL

TONE_GAINH

TONE_GAINL

TONE_GAIN_ATTEN

TONE_CONFIGURATION

CD00066274

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5 Register description

STA027

5

Register description

5.1

Version registers description

5.1.1 VERSION :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x00 (0)

Type : RO - DWT

Software Reset : 0x10

Hardware Reset : 0x10

Description :

The VERSION register is Read-only and it is used to identify the IC on the application board.

5.1.2 IDENT :

b7

b6

b5

b4

b3

b2

b1

b0

1

0

1

0

1

0

Address : 0x01 (1)

Type : RO - DWT

Software Reset : 0xAC

Hardware Reset : 0xAC

Description :

IDENT is a read-only register and it is used to identify the IC on an application board. IDENT

always has the value 0xAC.

5.1.3 SOFT_VERSION :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xD3 (211)

Type : RO - DWT

Software Reset : X

Description :

The SOFT_VERSION register is Read-only and it is used to identify the software running on

the IC.

14/44

CD00066274

STA027

5 Register description

5.2

PLL_AUDIO_CONFIGURATION registers description

5.2.1 PLL_AUDIO_PEL_192 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xDC (220)

Type : RW - DEC

Software Reset : 58

Description :

This register must contain a PEL value that enables the audio PLL to generate a frequency of

ofact*192 kHz for the PCMCK.See table 1, 2 & 3.

ofact is the oversampling factor needed by the DAC (ofac==246 or ofac==384).

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.2.2 PLL_AUDIO_PEH_192 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xDD (221)

Type : RW - DEC

Software Reset : 187

Description :

This register must contain a PEH value that enables the audio PLL to generate a frequency of

ofact*192 kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.2.3 PLL_AUDIO_NDIV_192 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xDE (222)

Type : RW - DEC

Software Reset : 0

CD00066274

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5 Register description

Description :

STA027

This register must contain a NDIV value that enables the audio PLL to generate a frequency of

ofact*192 kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.2.4 PLL_AUDIO_XDIV_192 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xDF (223)

Type : RW - DEC

Software Reset : 3

Description :

This register must contain a XDIV value that enables the audio PLL to generate a frequency of

ofact*192 kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.2.5 PLL_AUDIO_MDIV_192 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE0 (224)

Type : RW - DEC

Software Reset : 12

Description :

This register must contain a MDIV value that enables the audio PLL to generate a frequency of

ofact*192 kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

16/44

CD00066274

STA027

5 Register description

5.2.6 PLL_AUDIO_PEL_176 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE1 (225)

Type : RW - DEC

Software Reset : 54

Description :

This register must contain a PEL value that enables the audio PLL to generate a frequency of

ofact*176 kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–

fact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.2.7 PLL_AUDIO_PEH_176 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE2 (226)

Type : RW - DEC

Software Reset : 118

Description :

This register must contain a PEH value that enables the audio PLL to generate a frequency of

ofact*176 kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.2.8 PLL_AUDIO_NDIV_176 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE3 (227)

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a NDIV value that enables the audio PLL to generate a frequency of

ofact*176 kHz for the PCMCK.See table 1, 2 & 3.

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5 Register description

STA027

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.2.9 PLL_AUDIO_XDIV_176 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE4 (228)

Type : RW - DEC

Software Reset : 2

Description :

This register must contain a XDIV value that enables the audio PLL to generate a frequency of

ofact*176 kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.2.10 PLL_AUDIO_MDIV_176 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE5 (229)

Type : RW - DEC

Software Reset : 8

Description :

This register must contain a MDIV value that enables the audio PLL to generate a frequency of

ofact*176 kHz for the PCMCK.See table 1,2 & 3.

Default value at soft reset assume :

–

ofact == 256

external crystal provide a CRYCK running at 14.31818 MHz

5.3

PLL_SYSTEM_CONFIGURATION registers description

5.3.1 PLL_SYSTEM_PEL_50 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE6 (230)

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CD00066274

STA027

5 Register description

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a PEL value that enables the system PLL to generate a frequency of

50 MHz for the SYSCK. See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

5.3.2 PLL_SYSTEM_PEH_50 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE7 (231)

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a PEH value that enables the system PLL to generate a frequency of

50 MHz for the SYSCK. See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

5.3.3 PLL_SYSTEM_NDIV_50 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE8 (232)

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a NDIV value that enables the system PLL to generate a frequency

of 50 MHz for the SYSCK. See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

CD00066274

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5 Register description

STA027

5.3.4 PLL_SYSTEM_XDIV_50 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE9 (233)

Type : RW - DEC

Software Reset : 1

Description :

This register must contain a XDIV value that enables the system PLL to generate a frequency

of 50 MHZ for the SYSCK. See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

5.3.5 PLL_SYSTEM_MDIV_50 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xEA (234)

Type : RW - DEC

Software Reset : 13

Description :

This register must contain a MDIV value that enables the system PLL to generate a frequency

of 50 MHz for the SYSCK. See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

5.3.6 PLL_SYSTEM_PEL_42_5

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE6 (230)

Type : RW - DEC

Software Reset : 126

Description :

This register must contain a PEL value that enables the system PLL to generate a frequency of

42.5 MHz for the SYSCK.See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

20/44

CD00066274

STA027

5 Register description

5.3.7 PLL_SYSTEM_PEH_42_5 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE7 (231)

Type : RW - DEC

Software Reset : 223

Description :

This register must contain a PEH value that enables the system PLL to generate a frequency of

42.5 MHz for the SYSCK.See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

5.3.8 PLL_SYSTEM_NDIV_42_5 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE8 (232)

Type : RW - DEC

Software Reset : 0

Description :

This register must contain a NDIV value that enables the system PLL to generate a frequency

of 42.5 MHz for the SYSCK.See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

5.3.9 PLL_SYSTEM_XDIV_42_5 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xE9 (233)

Type : RW - DEC

Software Reset : 1

Description :

This register must contain a XDIV value that enables the system PLL to generate a frequency

of 42.5 MHz for the SYSCK.See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

CD00066274

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5 Register description

STA027

5.3.10 PLL_SYSTEM_MDIV_42_5 :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xEA (234)

Type : RW - DEC

Software Reset : 10

Description :

This register must contain a MDIV value that enables the system PLL to generate a frequency

of 42.5 MHz for the SYSCK.See table 4.

Default value at soft reset assume :

–

external crystal provide a CRYCK running at 14.31818 MHz

5.4

I²Sout_CONFIGURATION registers description

5.4.1 OUTPUT_CONF :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x66 (102)

Type : RW - DEC

Software Reset : 0

Description :

If set to 1 enable the configurability of the PCM-BLOCK Output thanks to following registers,

else disable this configurability and take embedded default configuration for PCM-BLOCK

registers.

Note that this embedded default configuration can be retrieved by user thanks to following

setting :

–

PCM_DIV = 3;

PCM_CONF = 0;

PCM_CROSS = 0;

5.4.2 PCM_DIV :

b7

b6

b5

b4

b3

b2

b1

b0

0

DV5

DV4

DV3

DV2

DV1

DV0

Address : 0x67 (103)

Type : RW - DEC

22/44

CD00066274

STA027

5 Register description

Software Reset : 0

Description :

2

If OUTPUT_CONF == 1, configure the divider to generate the bit clock of the I Sout interface,

called BCK0, from PCMCK. according the following relation : BCKO = PCMCK / 2 *

(PCM_DIV+1)

5.4.3 PCM_CONF :

b7

b6

CO6

b5

b4

b3

b2

b1

b0

0

CO5

CO4

CO3

CO2

CO1

CO0

Address : 0x68 (104)

Type : RW - DEC

Software Reset : 0

Description :

2

If OUTPUT_CONF == 1, configure the I Sout interface according following table

Table 10.

.

Bit fields

Comment

0 : 16 bits mode (16 slots transmitted).

1 : 18 bits mode (18 slots transmitted).

2 : 20 bits mode (20 slots transmitted).

3 : 24 bits mode (24 slots transmitted).

CO[1:0]

Polarity of BCKO :

CO2

CO3

CO4

0 : data are sent on the falling edge & stable on the rising).

1 : (data are sent on the rising edge & stable on the falling).

0 : I2S format is selected

1 : other format is selected

Polarity of LRCKO :

0 : low->right, high->left).

1 : low->left, high->right so compliant to I2S format ).

0 : data are in the last BCKO cycles of LRCKO (right aligned data).

1 : data are in the first BCKO cycles of LRCKO (left aligned data).

CO5

CO6

0 : the transmission is LS bit first.

1 : the transmission is MS bit first.

CD00066274

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5 Register description

STA027

5.4.4 PCM_CROSS :

b7

b6

b5

b4

b3

b2

b1

b0

0

CR1

CR0

Address : 0x69 (105)

Type : RW - DEC

Software Reset : 0

Description :

If OUTPUT_CONF == 1, CR[1:0] is used to configure the output crossbar according following

table

Table 11.

CR1

.

CR0

Comment

Left channel is mapped on the left output.

0

Right channel is mapped on the right output.

Left channel is duplicated on both output channels.

Right channel is duplicated on both output channels.

Right and left channels are toggled.

0

1

0

1

5.5

GPSO_CONFIGURATION registers description

5.5.1 OUTPUT_CONF :

b7

b6

b5

b4

b3

b2

b1

b0

X

0C2

OC1

OC0

Address : 0x66 (102)

Type : RW - DEC

Software Reset : 0

Description

Table 12.

Bit fields

Comment

Configuration of gpso :

0 : take embedded default configuration.

1 : configure gpso from register GPSO_CONF.

OC0

24/44

CD00066274

STA027

5 Register description

Table 12.

Bit fields

Comment

Use of block PCM to generate clocks (PCMCK, LRCK & BCK):

OC1

OC2

0 : no use.

1 : use it.

Configuration of PCM block:

0 : take embedded default configuration.

1 : configure PCM block from PCM_DIV & PCM_CONF registers.

Note:

that embedded default configuration for GPSO can be retrieved by user thanks to following

setting :

–

GPSO_CONF = b00000011;

that embedded default configuration for PCM block is described at previous chapter.

5.5.2 GPSO_CONF :

b7

b6

b5

b4

b3

b2

b1

b0

CF7

CF6

CF5

CF4

CF3

CF2

CF1

CF0

Address : 0x6A (106)

Type : RW - DEC

Software Reset : 0

Description :

If OUTPUT_CONF == 1, this register configure the GPSO interface

Table 13.

.

Bit fields

Comment

Polarity of GPSO_CK :

CF0

0 : data provided on rising edge & stable on falling edge

1 : data provided on falling edge & stable on rising edge

Polarity of GPSO_REQ :

CF1

0 : data are valid when GPSO_REQ is high

1 : data are valid when GPSO_REQ is low

CF[7:2]

Reserved : to be set to 0.

CD00066274

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5 Register description

STA027

5.6

I²Sin_CONFIGURATION registers description

5.6.1 INPUT_CONF :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x5A (90)

Type : RW - DEC

Software Reset : 0

Description :

2

If set to 1 enable the configurability of the I Sin Input thanks to following registers, else disable

this configurability and take embedded default configuration for I2Sin registers.

Note that this embedded default configuration can be retrieved by user thanks to following

setting :

–

I_AUDIO_CONFIG_1 = b00000110;

I_AUDIO_CONFIG_2 = b11100000;

I_AUDIO_CONFIG_3 = b00000001;

5.6.2

I_AUDIO_CONFIG_1:

b7

b6

b5

b4

b3

b2

b1

b0

CF7

CF6

CF5

CF4

CF3

CF2

CF1

CF0

Address : 0x5B (91)

Type : RW - DEC

Software Reset : 0

Description :

2

If INPUT_CONF == 1, this register configure the I Sin interface.

Table 14.

Bit fields

Comment

Relative synchro :

CF0

0 : synchro with first data bit

1 : synchro one bit before first data bit

Data reception configuration :

0 : LSB first

CF1

CF2

1 : MSB first

Polarity of bit clock BCK :

0 : data provided on falling edge & stable on rising edge.

1 : data provided on rising edge & stable on falling edge

26/44

CD00066274

STA027

5 Register description

Table 14.

Bit fields

Comment

Polarity of LR clock LRCK :

0 : negative

CF3

1 : positive

Start value of LRCK : combined with CF3, this bit enable user to determine left/right

couple according to the following table.

CF4

CF[7:5]

Reserved : to be set to 0.

Table 15.

CF3

CF4

Left/Right couples

(data1/data2), (data3/data4),...

0

1

0

1

0

1

(data0/data1), (data2/data3),...

(data1/data2), (data3/data4),...

5.6.3 I_AUDIO_CONFIG_2 :

b7

b6

b5

b4

b3

b2

b1

b0

LR7

LR6

LR5

LR4

LR3

LR2

LR1

LR0

Address : 0x5C (92)

Type : RW - DEC

Software Reset : 0

Description :

See I_AUDIO_CONFIG_3 register description..

5.6.4 I_AUDIO_CONFIG_3 :

b7

b6

b5

b4

b3

b2

b1

b0

0

LR9

LR8

Address : 0x5D (93)

Type : RW - DEC

Software Reset : 0

Description :

2

If INPUT_CONF == 1, this register is used to configure the phase of the LRCK of the I Sin.

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5 Register description

STA027

Table 16.

Bit fields

Comment

Position of the data within the LRCK phase :

- if CF1 = 0 (LSB), value must be set to[31 - SL[9:5] - bit position of the first bit

of data within the LRCK phase].

LR[4:0]

- if CF1 = 1 (MSB), value must be set to bit position of the first bit of data within

the LRCK phase.

Note:

that range of value for this bit position is [0:31].

Length-1 of the data.

LR[9:5]

Max value is 31.

LR[15:10]

Reserved : to be set to 0

5.7

SDI_CONFIGURATION registers description

5.7.1 POL_REQ :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x59 (89)

Type : WO - DEC

Software Reset : 0

Description :

This register manage the polarity of the data REQ signal DREQ of the BS input interface.

If set to 0, data are requested when REQ = 0.

If set to 1, data are requested when REQ = 1.

5.7.2 INPUT_CONF :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x5A (90)

Type : RW - DEC

Software Reset : 0

Description :

If set to 1 enable the configurability of the BSB input interfaces in burst mode thanks to following

register, else disable this configurability and take embedded default configuration.

Note that this embedded default configuration can be retrieved by user thanks to following

setting :

–

I_AUDIO_CONFIG1 = b00000000;// polarity choice

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5.7.3

5 Register description

I_AUDIO_CONFIG_1 :

b7

b6

b5

b4

b3

b2

b1

b0

0

CF0

Address : 0x5B (91)

Type : RW - DEC

Software Reset : 0

Description :

If INPUT_CONF == 1, this register is used to configure BSB bit clock

Table 17.

Bit

.

Comment

Polarity of bit clock BS_BCK :

CF0

0 : data provided on falling edge & stable on rising edge.

1 : data provided on rising edge & stable on falling edge.

5.8

COMMAND registers description

5.8.1 SOFT_RESET :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x10 (16)

Type : WO - DWT

Software Reset : 0

Description :

When user write 1 in this register, a soft reset occurs. The core command register and the

interrupt register are cleared. The decoder goes into idle mode.

5.8.2 CK_CMD :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x3A (58)

Type : WO - DBO

Software Reset : 1

Hardware Reset : 1

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5 Register description

Description :

STA027

After a soft reset, user must write 0 in CK_CMD to run the core clock of the chip. This will begin

the boot of the chip, and so get it out of its idle state.

5.8.3 DEC_SEL :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x55 (85)

Type : RW - DEC

Software Reset : 0

Description :

This register select the encoder/decoder data flux according the mode written in following table

Table 18.

.

Bit(7:0)

Mode

10

18

19

21

22

SINE (test mode chip alive)

SBC decoder

ADC/GPSO SBC encoder

SDI/GPSO SBC encoder

ADC/SDO SBC encoder

Note:

available modes depends on patch code used

5.8.4 RUN :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x56 (86)

Type : RW - DEC

Software Reset : 0

Description :

–

When a software reset occurs, register RUN is reset (value 0) by the dsp (see I).

When boot routines are finished, the dsp write inside RUN register the value 2 : this is

the start of the external configuration period (start of DEC : see I).

–

When the external device wants to end the external configuration period, it must write

the value 1 inside the register RUN: this is the run command that starts the decoding

process (see I).

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5 Register description

5.8.5 CRC_IGNORE :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x52 (82)

Type : RW - ABO

Software Reset : 0

Description :

For decoders having CRC abilities (see each decoder configuration), if set to 0 enable the

check of CRC, if set to 1 disable the check of the CRC.

5.8.6 MUTE :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x53 (83)

Type : RW - ABO

Software Reset : 0

Description :

For decoders having MUTE abilities (see each decoder configuration), if set to 0 disable the

mute of the decoder, if set to 1 enable the mute of the decoder. Note that during a MUTE the

input stream keeps on entering.

5.8.7 SKIP :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x57 (87)

Type : RW - ABO

Software Reset : 0

Description :

For data flux using USSB Input, if SKIP == n>2, decoder skip (n-1) out of n frames. Note that

maximum value for n is 8, and if n==0 or n==1, no frames is skipped.

5.8.8 PAUSE :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x58 (88)

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5 Register description

STA027

Type : RW - ABO

Software Reset : 0

Description :

For decoders having PAUSE abilities (see each decoder configuration), if set to 0 disable the

pause of the decoder, if set to 1 enable the pause of the decoder. Note that during a PAUSE the

input stream is stopped.

5.9

STATUS registers description

5.9.1 STATUS_MODE :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xCC (204)

Type : RO - EDF

Software Reset : 0

Description :

This register give the type of the currently decoded bitstream.

5.9.2 STATUS_CHANS_NB :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xCD (205)

Type : RO - EDF

Software Reset : 0

Description :

This register gives the number of channel currently decoded.

5.9.3 STATUS_SF :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xCE (206)

Type : RO - EDF

Software Reset : 0

Description :

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CD00066274

STA027

5 Register description

This register gives the index of the sampling frequency of the stream currently decoded. Note

that sampling frequency indexes are given by table 5

5.9.4 STATUS_FE :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x6F (111)

Type : RO - AEC

Software Reset : 0

Description :

This register give the status of the synchronization process according following table.

Table 19.

Value

Level

0

1

2

3

Syncrho not started

Syncword found

Syncword search

Syncword hard to find

5.9.5 HEADER _n:

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0xD4 (212) to 0xD9 (217)

Type : RO - EDF

Software Reset : 0

Description :

This register give the nth byte of the header of the frame currently decoded

5.10 MIX_CONFIGURATION registers description

5.10.1 MIX_MODE:

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x7B (123)

Type : RW - ABO

Software Reset : 2

CD00066274

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5 Register description

Description :

STA027

This register selectes the mode of mix/volume control

Table 20.

:

Value

Mode

0

1

2

3

diseable mix/volume control

volume control

mono to stereo (up-mix)

stereo to mono (down-mix)

5.10.2 MIX_DLA:

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x7C (124)

Type : RW - ABO

Software Reset : 0

Description :

This register specifies the direct left attenuation (in dB).

5.10.3 MIX_DLB:

b7

b6

b5

b4

b3

b2

Address : 0x7D (125)

Type : RW - ABO

Software Reset : 0

Description :

This register specifies the left attenuation (in dB) on rigth channel.

5.10.4 MIX_DRA:

b7

b6

b5

b4

b3

b2

Address : 0x7E (126)

Type : RW - ABO

Software Reset : 0

Description :

This register specifies the direct right attenuation (in dB).

34/44

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5 Register description

5.10.5 MIX_DRB:

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x7F (127)

Type : RW - ABO

Software Reset : 0

Description :

This register specifies the rigth attenuation (in dB) on left channel.

5.11 TONE_CONFIGURATION registers description

5.11.1 TONE_ON:

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x75 (117)

Type : RW - ABO

Software Reset : 0

Description :

This register enables/diseables (1/0) the tone control.

5.11.2 TONE_FCUTH :

b7

b6

b5

b4

b3

b2

b1

Address : 0x76 (118)

Type : RW - ABO

Software Reset : 20

Description :

This register specifies the high cut frequency: fcut(in Hz)=(TONE_FCUTH+1)*50.

5.11.3 TONE_FCUTL :

b7

b6

b5

b4

b3

b2

b1

Address : 0x77 (119)

Type : RW - ABO

Software Reset : 10

CD00066274

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5 Register description

Description :

STA027

This register specifies the low cut frequency: fcut(in Hz) = (TONE_FCUTL+1)*10

5.11.4 TONE_GAINH :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x78 (120)

Type : RW - ABO

Software Reset : 12

Description :

This register specifies the gain on high frequencies: gain(in Db)=(TONE_GAINH-12)*1.5

5.11.5 TONE_GAINL :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x79 (121)

Type : RW - ABO

Software Reset : 12

Description :

This register specifies the gain on high frequencies: gain (in Db)=(TONE_GAINL-12)*1.5. Value

of register from 0 to 24.

5.11.6 TONE_GAIN_ATTEN :

b7

b6

b5

b4

b3

b2

b1

b0

Address : 0x7A (122)

Type : RW - ABO

Software Reset : 0

Description :

This register specifies the attenuation on global spectrum: gain (in dB)=-

TONE_GAIN_ATTEN*1.5. Value of register from 0 to 12.

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6 TABLES

6

TABLES

Table 21. values to configure audio PLL for ofact==256.

This table give values to configure the audio PLL according CRYCK so that to generate a

PCMCK == 256*SF.

CRYCK in MHz

10

CRYCK in MHz

14.31818

CRYCK in MHz

14.7456

Register

PLL_AUDIO_PEL_192

PLL_AUDIO_PEH_192

PLL_AUDIO_NDIV_192

PLL_AUDIO_XDIV_192

PLL_AUDIO_MDIV_192

PLL_AUDIO_PEL_176

PLL_AUDIO_PEH_176

PLL_AUDIO_NDIV_176

PLL_AUDIO_XDIV_176

PLL_AUDIO_MDIV_176

42

169

0

58

187

0

85

0

3

0

18

56

16

0

12

54

118

0

2

0

64

0

3

2

3

17

8

11

Table 22. values to configure audio PLL for ofact==384

This table give values to configure the audio PLL according CRYCK so that to generate a

PCMCK == 384*SF.

CRYCK in MHz

10

CRYCK in MHz

14.31818

CRYCK in MHz

14.7456

Register

PLL_AUDIO_PEL_192

PLL_AUDIO_PEH_192

PLL_AUDIO_NDIV_192

PLL_AUDIO_XDIV_192

PLL_AUDIO_MDIV_192

PLL_AUDIO_PEL_176

PLL_AUDIO_PEH_176

PLL_AUDIO_NDIV_176

PLL_AUDIO_XDIV_176

PLL_AUDIO_MDIV_176

224

190

0

108

76

0

1

13

42

140

0

9

54

118

0

48

0

1

12

8

CD00066274

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6 TABLES

STA027

Table 23. values to configure audio PLL for ofact==512.

This table give values to configure the audio PLL according CRYCK so that to generate a

PCMCK == 512*SF.

CRYCK in MHz

10

CRYCK in MHz

14.31818

CRYCK in MHz

14.7456

Register

PLL_AUDIO_PEL_192

PLL_AUDIO_PEH_192

PLL_AUDIO_NDIV_192

PLL_AUDIO_XDIV_192

PLL_AUDIO_MDIV_192

PLL_AUDIO_PEL_176

PLL_AUDIO_PEH_176

PLL_AUDIO_NDIV_176

PLL_AUDIO_XDIV_176

PLL_AUDIO_MDIV_176

42

169

0

58

187

0

85

0

1

0

1

18

56

16

0

5

12

0

157

0

64

0

1

17

11

Table 24. values to configure system PLL for SYSCK.

This table give values to configure the system PLL according CRYCK so that to generate a

SYSCK == 50MHz. or SYSCK == 42.5MHz.

CRYCK in MHz

14.31818

CRYCK in MHz

14.7456

Register

CRYCK in MHz 10

PLL_SYSTEM_PEL_50

PLL_SYSTEM_PEH_50

PLL_SYSTEM_NDIV_50

PLL_SYSTEM_XDIV_50

PLL_SYSTEM_MDIV_50

PLL_SYSTEM_PEL_42_5

PLL_SYSTEM_PEH_42_5

PLL_SYSTEM_NDIV_42_5

PLL_SYSTEM_XDIV_42_5

PLL_SYSTEM_MDIV_42_5

162

11

0

28

152

0

1

19

0

13

126

223

0

12

100

135

0

1

16

10

Table 25. index of the Sampling Frequency

Index

Frequency

0

1

2

4

5

48 kHz

44.1 kHz

32 kHz

96 kHz

88.2 kHz

38/44

CD00066274

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6 TABLES

Table 25. index of the Sampling Frequency

Index

Frequency

6

64 kHz

24 kHz

8

9

22.05 kHz

16 kHz

10

12

12 kHz

13

11.025 kHz

8 kHz

14

16

192 kHz

17

18

176.4 kHz

128 kHz

3, 7, 11, 15 or 19

illegal frequency

6.1

Notations

ABO : After BOot (see I).

AEC : After External Config (see I).

BCK: Bit ClocK

BSA: BitStream input interface in Audio mode.

BSB: BitStream input interface in Burst mode.

BS: BitStream input interface.

BYPASSA : decoder BYPASS an Audio stream.

CD : input interface for CD.

CK : ClocK.

CRYCK: CRYstal ClocK provided to the chip by an external crystal.

DBO : During BOot (see I).

DEC : During External Config (see I).

DWT : During Whole Time (see I).

EDB : Every Decoded Block (see I).

EDF : Every Decoded Frame (see I).

LRCK: Left Right ClocK for an I2S interface.

ofact: oversampling factor for PCMCK (PCMCK == ofact * SF).

PCMCK: PCM ClocK (can be generated by the audio PLL).

SF: Sampling Frequency.

SYSCK: SYStem ClocK (clock of the core, can be generated by the system PLL).

X : don’t care.

CD00066274

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7 I/O CELL DESCRIPTION

STA027

7

I/O CELL DESCRIPTION

7.1

TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew

Rate Control

Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56, 59

EN

A

INPUT PIN

MAX LOAD

Z

100pF

D98AU904

7.2

TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with

Slew Rate Control

Pin numbers: 1, 2, 3, 7, 8, 9, 19

EN

OUTPUT

MAX

LOAD

INPUT PIN CAPACITANCE

IO TBD

IO

A

IO

100pF

ZI

D98AU905

7.3

7.4

TTL Schmitt Trigger Inpud Pad Buffer, 3V capable

Pin numbers:17, 60, 63

EN

INPUT PIN

CAPACITANCE

IO

A

TBD

A

ZI

D98AU905

TTL Inpud Pad Buffer, 3V capable with Pull-Up

Pin numbers:15, 16

INPUT PIN

CAPACITANCE

A

Z

A

TBD

D98AU907

40/44

CD00066274

STA027

7.5

TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with

slew rate control / 3V capable

Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51, 64

EN

OUTPUT

MAX

LOAD

INPUT PIN CAPACITANCE

IO TBD

IO

A

IO

100pF

ZI

D00AU1150

7.6

TTL Input Pad Buffer, 3V capable, with pull down

Pin numbers: 12, 13, 14, 55

A

Z

INPUT PIN

CAPACITANCE

A

TBD

D00AU1222

CD00066274

41/44

8 Package Informations

STA027

8

Package Informations

Figure 6. TQFP64 (10x10x1.4mm) Mechanical Data & Package Dimensions

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN.

TYP. MAX.

0.063

A

A1

A2

B

1.60

0.05

1.35

0.17

0.09

0.15 0.002

0.006

1.40

0.22

1.45 0.053 0.055 0.057

0.27 0.0066 0.0086 0.0106

0.0035

C

D

11.80 12.00 12.20 0.464 0.472 0.480

9.80 10.00 10.20 0.386 0.394 0.401

D1

D3

e

7.50

0.50

0.295

0.0197

E

11.80 12.00 12.20 0.464 0.472 0.480

9.80 10.00 10.20 0.386 0.394 0.401

E1

E3

L

7.50

0.60

1.00

0.295

0.75 0.0177 0.0236 0.0295

0.0393

0.45

L1

K

TQFP64 (10 x 10 x 1.4mm)

0˚ (min.), 3.5˚ (min.), 7˚(max.)

0.080

ccc

0.0031

D

D1

D3

A

A2

A1

48

33

32

49

0.08mm ccc

Seating Plane

17

16

64

1

C

e

K

TQFP64

0051434 E

42/44

CD00066274

STA027

9 Revision history

9

Revision history

Date

Revision

Changes

1-sept-2005

1

Initial release.

CD00066274

43/44

STA027

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

44/44

CD00066274


型号：	STA027
厂家：	ST
描述：	SBC CODEC SBC编解码器解码器编解码器
文件：	总44页 (文件大小：202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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