STA306 [STMICROELECTRONICS]
MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX; 使用DDX多声道数字音频处理器
| 型号： | STA306 |
| 厂家： | 
ST |
| 描述： | MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX |
| 文件： | 总33页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA306
MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX™
PRODUCT PREVIEW
■ 6 DDXTM Channels Capability (24 bit)
■ From 32kHz to 192kHz Input Sample Rates
Supported
■ Volume Control from 0 to -127 dB (0.5 dB steps)
■ Variable Digital Gain from 0 to 24dB (0.5dB
TQFP64
steps) with Digital Limiter Functionality and
Variable Attack and Release Time
ORDERING NUMBER: STA306
■ I2S Inputs and Outputs
■ Individual Channel and Master Gain/
Attenuation
■ Individual Channel Mute and Zero Input Detect
DESCRIPTION
Auto-Mute
The STA306 is a single chip solution for digital audio
processing and control in multi-channel applications.
It provides output capabilities for DDXTM (Direct Digi-
tal Amplification). In conjunction with a DDXTM power
device, it provides high-quality, high-efficiency, all
digital amplification. The device is extremely versatile
allowing for input of most digital formats including
192kHz, 24-bit DVD-Audio.
■ Selectable Serial Audio Data Interface
■ Bass/Treble Controls
■ Channel Mapping of any Input to any
Processing/DDXTM Channel
■ Active Crossover Capability
■ DC Blocking Selectable High-Pass Filter
■ Selectable Bass Management on Channel 6
■ Selectable Adjacent Channel Mixing Capability
■ Selectable Clock Input Ratio
The internal 24-bit DSP allows for high resolution
processing at all standard input sample frequencies.
Processing includes volume control, filtering, bass
management, gain compression/limiting and PCM
and DDXTM outputs. Filtering includes five user-pro-
grammable 28-bit biquads for EQ per channel, as
well as bass, treble and DC blocking. External clock-
ing can be provided at 4 different ratios of the input
sample frequency. All sample frequencies are up-
sampled for processing. Each internal processing
channel can receive any input channel, allowing flex-
ibility and the ability to perform active digital cross-
over for powered loudspeaker systems.
■ Selectable De-emphasis
■ Selectable DDXTM Ternary, or Binary PWM
output
■ AM Interference Reduction Mode
■ I2C Control
The serial audio data interface accepts many differ-
ent formats, including the popular I2S format. STx-
channels of DDX processing are performed.
October 2003
1/33
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
STA306
BLOCK DIAGRAM
SCL
MVO
SA
SDA
LRCKI
BICKI
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
I2C
SERIAL
DATA
IN
OVERSAMPLING
SDI12
SDI34
SDI56
DDX
SYSTEM
CONTROL
OUT6A/B
VARIABLE
OVER-
SAMPLING
TREBLE,
BASS, EQ
(BIQUADS)
VOLUME
LIMITING
CHANNEL
MAPPING
LRCKO
SERIAL
DATA
OUT
BICKO
SDO12
SYSTEM TIMING
VARIABLE
DOWN-
SAMPLING
SDO34
SDO56
PLLB
PLL
POWER
DOWN
XTI
CKOUT
EAPD
PWDN
Figure 1. Signal Flow Diagram
Channels 1-6
1st Stage
Interpolation
Output
Bass Management
Scale
& Mix
Interp_Rate
6 Inputs
From I2S
BME
Channel
Mapping
1x,2x,4x
Interp
Biquads
B/T
Volume
Limiter
2x
Interp
DDX
Output
Noise & Distortion Reduction
PWM
2/33
STA306
IN CONNECTION (Top view)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
MVO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT2_A
OUT2_B
VDD
TEST_MODE
VDD3
GND
GND
VDD
VDD3
N.C.
OUT3_A
OUT3_B
OUT4_A
OUT4_B
OUT5_A
OUT5_B
VDD
SDI_56
SDI_34
SDI_12
LRCKI
BICKI
10
11
12
13
14
VDD3
GND
GND
VDD
VDD3
RESET
PLLB
OUT6_A
OUT6_B
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D02AU1522
PIN FUNCTION
PIN
1
NAME
TYPE
DESCRIPTION
Master Volume Override
PAD TYPE
CMOS Input Buffer with
Pull-Down
3.3V Digital Power
Supply Voltage (pad ring)
Digital Ground
MVO
VDD3
GND
VDD
I
3, 12, 24, 28,
35, 44, 52, 59
2, 4, 13, 27,
36, 45, 53, 60
5, 14, 26, 37,
46, 54, 61
3.3V Digital Supply
Digital Ground
2.5V Digital Supply
2.5V Digital Power
Supply Voltage (core +
ring)
7
8
9
10
11
15
SDI_56
SDI_34
SDI_12
LRCKI
BICKI
I
I
I
I
I
I
Input I2S Serial Data Channels 5 & 6
Input I2S Serial Data Channels 3 & 4
Input I2S Serial Data Channels 1 & 2
Inputs I2C Left/Right Clock
Inputs I2C Serial Clock
5V Tolerant TTL Input Buffer
5V Tolerant TTL Input Buffer
5V Tolerant TTL Input Buffer
5V Tolerant TTL Input Buffer
5V Tolerant TTL Input Buffer
5V Tolerant TTL Schmitt
Trigger Input Buffer
CMOS Input Buffer with
Pull-Down
CMOS Input Buffer with
Pull-Down
Bidirectional Buffer:
5V Tolerant TTL Schmitt
Trigger Input;
RESET
Global Reset
16
17
18
PLLB
SA
I
I
PLL Bypass
Select Address (I2C)
I2C Serial Data
SDA
I/O
3.3V Capable 2 mA
Slew-rate control Output;
5V Tolerant TTL Schmitt
Trigger Input Buffer
19
SCL
I
I2C Serial Clock
3/33
STA306
PIN FUNCTION (continued)
PIN
NAME
TYPE
DESCRIPTION
PAD TYPE
20
XTI
I
Crystal Oscillator Input (Clock Input)
3.3V Tolerant TTL Schmitt
Trigger Input Buffe
r
21
22
FILTER_PLL
VDDA
PLL Filter
PLL 2.5V Supply
Analog Pad
2.5V Analog Power
Supply Voltage
23
25
GNDA
CKOUT
PLL Ground
Clock Output
Analog Ground
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
3.3V Capable TTL Tristate
4mA Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
33
34
38
39
40
41
42
43
47
48
49
50
51
55
56
57
58
62
63
64
OUT6_B
OUT6_A
OUT5_B
OUT5_A
OUT4_B
OUT4_A
OUT3_B
OUT3_A
OUT2_B
OUT2_A
OUT1_B
OUT1_A
EAPD
PWM Channel 6 Output B
PWM Channel 6 Output A
PWM Channel 5 Output B
PWM Channel 5 Output A
PWM Channel 4 Output B
PWM Channel 4 Output A
PWM Channel 3 Output B
PWM Channel 3 Output A
PWM Channel 2 Output B
PWM Channel 2 Output A
PWM Channel 1 Output B
PWM Channel 1 Output A
External Amplifier Power Down
Output I2S Serial Clock
BICKO
LRCKO
SDO_12
SDO_34
SDO_56
SDO_78
PWDN
Output I2S Left/Right Clock
Output I2S Serial Data Channels 1 & 2
Output I2S Serial Data Channels 3 & 4
Output I2S Serial Data Channels 5 & 6
Output I2S Serial Data Channels 7 & 8
Device Powerdown
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
3.3V Capable TTL 2mA
Output Buffer
5V Tolerant TTL Schmitt
Trigger Input Buffer
4/33
STA306
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
-0.5 to 4
Unit
V
V
3.3V I/O Power Supply
2.5V Logic Power Supply
Voltage on input pins
Voltage on output pins
Storage Temperature
DD_3.3
DD_2.5
V
-0.5 to 3.3
V
V
i
-0.5 to (VDD+0.5)
-0.5 to (VDD+0.3)
-40 to +150
-20 to +85
V
V
o
V
T
°C
°C
stg
T
amb
Ambient Operating Temperature
THERMAL DATA
Symbol
Parameter
Value
Unit
R
thj-amb
Thermal resistance Junction to Ambient
85
°C/W
RECOMMENDED DC OPERATING CONDITIONS
Symbol Parameter
Value
Unit
V
V
I/O Power Supply
3.0 to 3.6
2.3 to 2.7
-20 to +125
DD_3.3
DD_2.5
V
Logic Power Supply
V
T
Operating Junction Temperature
°C
j
5/33
STA306
ELECTRICAL CHARACTERISTCS (V
= 3.3V ± 0.3V; V = 2.5V ± 0.2V; T
= 0 to 70 °C; unless other-
amb
DD3
DD
wise specified)
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
V = 0V
Min.
Typ.
Max.
Unit
µA
Note
I
il
Low Level Input no pull-up
High Level Input no pull-down
1
2
2
1
1
1
i
I
V = V
µA
ih
i
DD3
I
Tristate output leakage without
pullup/down
V = V
µA
OZ
i
DD3
V
esd
Electrostatic Protection
Leakage < 1µA
2000
V
2
Note 1: The leakage currents are generally very small, < 1na. The values given here are maximum after an electrostatic stress on the pin.
Note 2: Human Body Model
DC ELECTRICAL CHARACTERISTICS: 3.3V BUFFERS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
V
Low Level Input Voltage
High Level Input Voltage
Low Level Threshold
High Level Threshold
Schmitt Trigger Hysteresis
Low Level Output
0.8
IL
V
IH
2.0
0.8
1.3
0.3
V
V
Input Falling
Input Rising
1.35
2.0
0.8
0.2
V
ILhyst
IHhyst
V
V
V
hyst
V
V
ol
IoI = 100uA
V
V
oh
High Level Output
Ioh = -100uA
Ioh = -2mA
VDD3-0.2
2.4
V
V
DC ELECTRICAL CHARACTERISTICS: 2.5V BUFFERS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
V
Low Level Input Voltage
High Level Input Voltage
Low Level Threshold
Schmitt input
0.26*VDD
ILst
V
Schmitt input
0.7*VDD
V
IHst
V
non Schmitt, Input
Falling
0.5*VDD
0.5*VDD
V
ILhyst
V
IHhyst
High Level Threshold
non Schmitt, Input
Rising
1.3
2.0
V
V
Schmitt Trigger Hysteresis
Low Level Output
0.23*VDD
V
V
V
hyst
V
Note 1
Note 1
0.15*VDD
OL
V
High Level Output
0.85*VDD
OH
Notes: 1. Source/Sink current under worst-case conditions.
6/33
STA306
1.0 PIN DESCRIPTION
1.1 MVO: Master Volume Override
This pin enables the user to bypass the Volume Control on all channels. When MVO is pulled High, the Master
Volume Register is set to 00h, which corresponds to its Full Scale setting. The Master Volume Register Setting
offsets the individual Channel Volume Settings, which default to 0dB.
1.2 SDI_12 through 56: Serial Data In
Audio information enters the device here. Six format choices are available including I2S, left- or right-justified,
LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
1.3 RESET
Driving this pin (low) turns off the outputs and returns all settings to their defaults.
1.4 I2C
The SA, SDA and SCL pins operate per the Philips I2C specification. See Section 2.
1.5 PLL: Phase Locked Loop
The phase locked loop section provides the System Timing Signals and CKOUT.
1.6 CKOUT: Clock Out
System synchronization and master clocks are provided by the CKOUT.
1.7 OUT1 through OUT6: PWM Outputs
The PWM outputs provide the input signal for the power devices.
1.8 EAPD: External Amplifier Power-Down
This signal can be used to control the power-down of DDX power devices.
1.9 SDO_12 through 56: Serial Data Out
Audio information exits the device here. Six different format choices are available including I2S, left- or right-
justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
1.10 PWDN: Device Power-Down
This puts the STA306 into a low-power state via appropriate power-down sequence. Pulling PWDN low begins
power-down sequence, and EAPD goes low ~30ms later.
2.0 II2C BUS SPECIFICATION
The STA306 supports the I2C protocol. This protocol defines any device that sends data on to the bus as a
transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known
as the master and the other as the slave. The master always starts the transfer and provides the serial clock
for synchronization. The STA306 is always a slave device in all of its communications.
7/33
STA306
2.1 COMMUNICATION PROTOCOL
2.1.1 Data Transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is
high is used to identify a START or STOP condition.
2.1.2 Start Condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A START condition must precede any command for data transfer.
2.1.3 Stop Condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the
high state. A STOP condition terminates communication between STA306 and the bus master.
2.1.4 Data Input
During the data input the STA306 samples the SDA signal on the rising edge of clock SCL. For correct device
operation the SDA signal must be stable during the rising edge of the clock and the data can change only when
the SCL line is low.
2.2 DEVICE ADDRESSING
To start communication between the master and the STA306, the master must initiate with a start condition.
Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address
and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the
STA306 the I2C interface has two device addresses depending on the SA pin configuration, 0x30 or 0011000x
when SA = 0, and 0x32 or 0011001x when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode.
After a START condition the STA306 identifies on the bus the device address and if a match is found, it acknowl-
edges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is
the internal space address.
2.3 WRITE OPERATION
Following the START condition the master sends a device select code with the RW bit set to 0. The STA306
acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the
STA306 again responds with an acknowledgement.
2.3.1 Byte Write
In the byte write mode the master sends one data byte, this is acknowledged by the STA306. The master then
terminates the transfer by generating a STOP condition.
2.3.2 Multi-byte Write
The multi-byte write modes can start from any internal address. The master generating a STOP condition ter-
minates the transfer.
8/33
STA306
Write Mode Sequence
ACK
ACK
ACK
ACK
ACK
BYTE
DEV-ADDR
SUB-ADDR
SUB-ADDR
DATA IN
DATA IN
WRITE
START
RW
STOP
ACK
ACK
MULTIBYTE
WRITE
DEV-ADDR
DATA IN
START
RW
STOP
Read Mode Sequence
ACK
NO ACK
CURRENT
ADDRESS
READ
DEV-ADDR
DEV-ADDR
DEV-ADDR
DEV-ADDR
DATA
START
START
START
START
RW
RW
STOP
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
NO ACK
RANDOM
ADDRESS
READ
SUB-ADDR
DEV-ADDR
DATA
START
RW
STOP
STOP
RW=
HIGH
NO ACK
SEQUENTIAL
CURRENT
READ
DATA
DATA
DATA
DATA
ACK
ACK
NO ACK
SEQUENTIAL
RANDOM
READ
SUB-ADDR
DEV-ADDR
DATA
DATA
RW
START
RW
STOP
Table 1. Register summary
Address
00h
Name
ConfA
ConfB
ConfC
ConfD
ConfE
ConfF
Mmute
Mvol
D7
MPC
DRC
HPB
BQL
RES
EAPD
D6
D5
D4
IR1
D3
D2
D1
D0
HPE
ZCE
BME
SAIFB
RES
IR0
SAI1
MCS2
SAI0
RES
MCS1
ZDE
MCS0
DSPB
OM0
01h
SAI2
RES
COS0
SAO1
02h
RES
RES
OM1
03h
PSL
COS1
SAO2
C78BO
SAO0
AME
C56BO
DEMP
COD
C34BO
VOLEN
I2SD
C12BO
MIXE
PWMD
MMute
MV0
04h
SAOFB
05h
06h
07h
MV7
C8M
MV6
C7M
MV5
C6M
MV4
C5M
MV3
C4M
MV2
C3M
MV1
C2M
08h
Cmute
C1Vol
C2Vol
C3Vol
C4Vol
C5Vol
C6Vol
C7Vol
C1M
09h
C1V7
C2V7
C3V7
C4V7
C5V7
C6V7
C7V7
C1V6
C2V6
C3V6
C4V6
C5V6
C6V6
C7V6
C1V5
C2V5
C3V5
C4V5
C5V5
C6V5
C7V5
C1V4
C2V4
C3V4
C4V4
C5V4
C6V4
C7V4
C1V3
C2V3
C3V3
C4V3
C5V3
C6V3
C7V3
C1V2
C2V2
C3V2
C4V2
C5V2
C6V2
C7V2
C1V1
C2V1
C3V1
C4V1
C5V1
C6V1
C7V1
C1V0
C2V0
C3V0
C4V0
C5V0
C6V0
C7V0
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
9/33
STA306
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
C8Vol
C12im
C34im
C56im
C78im
C1234ls
C5678ls
L1ar
C8V7
C8V6
C2IM2
C4IM2
C6IM2
C8IM2
C4LS0
C8LS0
L1R2
C8V5
C2IM1
C4IM1
C6IM1
C8IM1
C3LS1
C7LS1
L1R1
C8V4
C2IM0
C4IM0
C6IM0
C8IM0
C3LS0
C7LS0
L1R0
C8V3
C8V2
C1IM2
C3IM2
C5IM2
C7IM2
C2LS0
C6LS0
L1A2
C8V1
C1IM1
C3IM1
C5IM1
C7IM1
C1LS1
C5LS1
L1A1
C8V0
C1IM0
C3IM0
C5IM0
C7IM0
C1LS0
C5LS0
L1A0
C4LS1
C8LS1
L1R3
C2LS1
C6LS1
L1A3
L1atrt
L2ar
L1AT3
L2R3
L1AT2
L2R2
L1AT1
L2R1
L1AT0
L2R0
L1RT3
L2A3
L1RT2
L2A2
L1RT1
L2A1
L1RT0
L2A0
L2atrt
Tone
L2AT3
TTC3
L2AT2
TTC2
L2AT1
TTC1
L2AT0
TTC0
L2RT3
BTC3
L2RT2
BTC2
L2RT1
BTC1
CFA1
C1B17
C1B9
C1B1
C2B17
C2B9
C2B1
C3B17
C3B9
C3B1
C4B17
C4B9
C4B1
C5B17
C5B9
C5B1
WA
L2RT0
BTC0
CFA0
C1B16
C1B8
C1B0
C2B16
C2B8
C2B0
C3B16
C3B8
C3B0
C4B16
C4B8
C4B0
C5B16
C5B8
C5B0
W1
Cfaddr
B2cf1
B2cf2
B2cf3
B0cf1
B0cf2
B0cf3
A2cf1
A2cf2
A2cf3
A1cf1
A1cf2
A1cf3
B1cf1
B1cf2
B1cf3
Cfud
CFA7
CFA6
CFA5
CFA4
CFA3
CFA2
C1B23
C1B15
C1B7
C1B22
C1B14
C1B6
C1B21
C1B13
C1B5
C1B20
C1B12
C1B4
C1B19
C1B11
C1B3
C1B18
C1B10
C1B2
C2B23
C2B15
C2B7
C2B22
C2B14
C2B6
C2B21
C2B13
C2B5
C2B20
C2B12
C2B4
C2B19
C2B11
C2B3
C2B18
C2B10
C2B2
C3B23
C3B15
C3B7
C3B22
C3B14
C3B6
C3B21
C3B13
C3B5
C3B20
C3B12
C3B4
C3B19
C3B11
C3B3
C3B18
C3B10
C3B2
C4B23
C4B15
C4B7
C4B22
C4B14
C4B6
C4B21
C4B13
C4B5
C4B20
C4B12
C4B4
C4B19
C4B11
C4B3
C4B18
C4B10
C4B2
C5B23
C5B15
C5B7
C5B22
C5B14
C5B6
C5B21
C5B13
C5B5
C5B20
C5B12
C5B4
C5B19
C5B11
C5B3
C5B18
C5B10
C5B2
DC1
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
DC2
RES
RES
BIST1
BIST2
RES
RES
RES
RES
10/33
STA306
3.0 CONFIGURATION REGISTER A (ADDRESS 00H)
BIT
NAME
RST
D7
MPC
1
D6
HPE
0
D5
BME
0
D4
IR1
0
D3
IR0
0
D2
MCS2
0
D1
MCS1
1
D0
MCS0
1
3.0.1 Master Clock Select
BIT
0
R/W
R/W
R/W
R/W
RST
NAME
DESCRIPTION
2
1
1
0
MCS0
MCS1
MCS2
Master Clock Select : Selects the ratio between the input I S
sample frequency and the input clock.
1
2
The STA306 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz.
Therefore the internal clock will be:
– 65.536Mhz for 32kHz
– 90.3168Mhz for 44.1khz, 88.2kHz, and 176.4kHz
– 98.304Mhz for 48kHz, 96kHz, and 192kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The
relationship between the input clock and the input sample rate is determined by both the MCSx and the IRx (In-
put Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IRx bits
determine the oversampling ratio used internally.
Input Sample Rate
IR
MCS(2..0)
fs (kHz)
1xx
128fs
64fs
64fs
011
010
001
000
32, 44.1, 48
88.2, 96
00
01
10
256fs
128fs
128fs
384fs
192fs
192fs
512fs
256fs
256fs
768fs
384fs
384fs
176.4, 192
3.0.2 Interpolation Ratio Select
BIT
3
R/W
R/W
R/W
RST
NAME
IR0
DESCRIPTION
2
0
0
Interpolation Ratio Select : Selects internal interpolation ratio based on input I S
sample frequency
4
IR1
The STA306 has variable interpolation (oversampling) settings such that internal processing and DDX output
rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-
through). The IR bits determine the oversampling ratio of this interpolation.
Table 2. IR bit settings as a function of Input Sample Rate.
st
Input Sample Rate Fs
IR(1,0)
1
Stage Interpolation Ratio
4 times oversampling
4 times oversampling
4 times oversampling
2 times oversampling
2 times oversampling
Pass-Through
32kHz
44.1kHz
48kHz
00
00
00
01
01
10
10
88.2kHz
96kHz
176.4kHz
192kHz
Pass-Through
11/33
STA306
3.0.3 Bass Management Enable
BIT
R/W
RST
NAME
DESCRIPTION
5
R/W
0
BME
Bass Management Enable : 0 – No Bass Management
1 – Bass Management operation on channel 6, scale and add inputs
Channel 6 of the STA306 features a bass management mode that enables redirection of information in all other
channels to this channel and which can then be filtered appropriately using the EQ(Biquad) section. Setting the
BME bit selects the output of the scale and mix block for channel 6 instead of the output of the channel mapping
block. The settings for the scale and mix block are provided by the CxBMS registers
3.0.4 Max Power Correction
BIT
R/W
RST
NAME
DESCRIPTION
7
R/W
1
MPC
Max Power Correction : Setting of 1 enables DDX correction for THD reduction
near maximum power output.
Setting the MPC bit turns on special processing that corrects the DDX power device at high power. This mode
should lower the THD+N of a full DDX system at maximum power output and slightly below. This mode will only
be operational in OM= 00 or 10.
3.1 Configuration Register B (address 01h)
BIT
NAME
RST
D7
DRC
0
D6
ZCE
1
D5
SAIFB
0
D4
SAI2
0
D3
SAI1
0
D2
SAI0
0
D1
ZDE
1
D0
DSPB
0
3.1.1 DSP Bypass
BIT
R/W
RST
NAME
DSPB
DESCRIPTION
0
R/W
0
DSP Bypass Bit : 0 – Normal Operation
1 – Bypass of Biquad and Bass/Treble Functionality
Setting the DSPB bit bypasses the biquad and bass/treble functionality of the STA306.
3.1.2 Zero-Detect Mute Enable
BIT
R/W
RST
NAME
DESCRIPTION
1
R/W
1
ZDE
Zero-Detect Mute Enable : Setting of 1 enables the
automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute.
The zero-detect circuit looks at the input data to each processing channel after the channel mapping block. If
any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is
muted if this function is enabled.
12/33
STA306
Serial Audio Input Interface Format
BIT
R/W
R/W
R/W
R/W
RST
NAME
SAI0
SAI1
SAI2
DESCRIPTION
2
0
0
0
Serial Audio Input Interface Format : Determines the
interface format of the input serial digital audio interface.
3
4
The STA306 features a configurable digital serial audio interface. The settings of the SAIx bits determine how
the input to this interface is interpreted. Six formats are accepted.
Table 3. Interface format as a function of SAI bits.
SAI(2..0)
Interface Format
2
000
I S
001
010
011
100
101
Left-Justified Data
Right-Justified 16-bit Data
Right-Justified 18-bit Data
Right-Justified 20-bit Data
Right-Justified 24-bit Data
Figure 2. Serial Audio Signals
SAI=000 I2S
Left
Right
LRCLK
SCLK
MSB
LSB
MSB
LSB
MSB
SDATA
SAI=001 Left Justified
Left
Right
LRCLK
SCLK
SDATA
MSB
LSB
MSB
LSB
MSB
SAI=010 to 101 Right Justified
Left
Right
LRCLK
SCLK
SDATA
MSB
LSB
MSB
LSB
MSB
13/33
STA306
3.1.3 Serial Audio Input Interface First Bit
BIT
R/W
RST
NAME
DESCRIPTION
5
R/W
0
SAIFB
Determines MSB or LSB first for all SAI formats
0 – MSB First, 1 – LSB First
3.1.4 Zero-Crossing Volume Enable
BIT
R/W
RST
NAME
DESCRIPTION
Zero-Crossing Volume Enable :
6
R/W
1
ZCE
1 – Volume adjustments will only occur at digital zero-crossings
0 – Volume adjustments will occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings,
"zipper noise" is eliminated
3.1.5 Dynamic Range Compression/Anti-Clipping Bit
BIT
R/W
RST
NAME
DESCRIPTION
7
R/W
0
DRC
Dynamic Range Compression/Anti-Clipping
0 – Limiters act in Anti-Clipping Mode
1- Limiters act in Dynamic Range Compression Mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-
clipping mode the limiter threshold values are constant and dependent on the gain/attenuation settings applied
to the input signal. In dynamic range compression mode the limiter threshold values vary with the volume set-
tings allowing for limiting to occur independently of the gain/attenuation but dependent on the input signal
3.2 Configuration Register C (address 02h)
BIT
NAME
RST
D7
HPB
0
D6
RES
1
D5
RES
1
D4
RES
1
D3
RES
1
D2
RES
1
D1
OM1
0
D0
OM0
0
3.2.1 DDX Power Output Mode
BIT
0
R/W
R/W
R/W
RST
NAME
OM0
DESCRIPTION
DDX Power Output Mode : Selects configuration of DDX output.
0
0
1
OM1
The DDX Power Output Mode selects how the DDX output timing is configured. Different power devices use
different output modes. The DDX recommended use is OM = 00. The variable mode uses the OMVx bits for
adjustment
OM(1,0)
00
Output Stage - Mode
Fixed Compensation
RESERVED
01
10
Full Power Mode recommended for STA500 and STA505
RESERVED
11
14/33
STA306
3.2.2 High-Pass Filter Bypass
BIT
R/W
RST
NAME
DESCRIPTION
7
R/W
0
HPB
High-Pass Filter Bypass Bit. Setting of one bypasses internal AC
coupling digital high-pass filter
The STA306 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter
is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage
3.3 Configuration Register D (address 03h)
BIT
NAME
RST
D7
BQL
0
D6
PSL
0
D5
COS1
1
D4
COS0
0
D3
C78BO
0
D2
C56BO
0
D1
C34BO
0
D0
C12BO
0
3.3.1 Binary Output Enable Registers
BIT
0
R/W
R/W
R/W
R/W
R/W
RST
NAME
C12BO
C34BO
C56BO
C78BO
DESCRIPTION
0
0
0
0
Channels 1&2, 3&4, 5&6 Binary Output Mode Enable Bits. A
setting of 0 indicates ordinary DDX tri-state output. A setting
of 1 indicates binary output mode.
1
2
3
Each two-channel pair of outputs can be set to output a binary PWM stream. In this mode, output A
of a channel will be considered the positive output and output B is negative inverse. For example, setting C34BO
= 1 sets channels 3&4 to Binary Output (PWM) Mode.
3.3.2 Clock Output Select
BIT
4
R/W
R/W
R/W
RST
NAME
COS0
COS1
DESCRIPTION
Clock Output Select
Clock Output Select
0
1
5
The Clock Output Select register selects the frequency of the clock output pin relative to the PLL clock output.
The PLL clock runs at 2048fs for 32, 44.1, and 48kHz, at 1024fs for 88.2kHz and 96 kHz, and at 512fs for
176.4kHz and 192kHz.
COS(1,0)
CKOUT Frequency
PLL Output/4
01
10
11
PLL Output/8
PLL Output/16
3.3.3 Post-Scale Link
BIT
R/W
RST
NAME
PSL
DESCRIPTION
6
R/W
0
Post-Scale Link :0 – Each Channel uses individual Post-Scale value
1 - Each Channel uses Channel 1 Post-Scale value
For multi-channel applications, the post-scale values can be linked to the value of channel 1 for ease of use and
update the values faster.
15/33
STA306
3.3.4 Biquad Coefficient Link
BIT
R/W
RST
NAME
DESCRIPTION
7
R/W
0
BQL
Biquad Link :
0 – Each Channel uses coefficient values
1- Each Channel uses Channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space
by setting the BQL bit to 1. Then any EQ updates would only have to be performed once.
3.4 Configuration Register E (address 04h)
BIT
NAME
RST
D7
RES
0
D6
SAOFB
0
D5
SAO2
0
D4
SAO1
0
D3
SAO0
0
D2
DEMP
0
D1
VOLEN
1
D0
MIXE
0
BIT
R/W
RST
NAME
DESCRIPTION
0
R/W
0
MIXE
Mix Enable: 0 – Normal Operation
1 - Adjacent Channel Mix Mode
The scale and mix functionality can be used to mix adjacent channels instead of for bass management. By set-
ting this bit(BME must be set to 0) odd channels will be mixed with their adjacent even channel and output in
the place of the even channel. The odd channel wills pass-through unscaled. The values used for this function
are the same as for bass management. Since this function occurs post channel mapping a large number of
possibilities are present for two channel mixing. Up to four mixed channels can be obtained.
BIT
R/W
RST
NAME
DESCRIPTION
1
R/W
1
VOLEN Volume Enable: 0 – Volume Operation Bypassed
1 - Volume Operation Normal
When VOLEN set to 1, volume operation is normal. When set to 0, volume operation is bypassed and the vol-
ume stages are all set to pass-through. This also eliminates the digital volume offset of ~-0.6dB that is used to
map full-scale digital input to full DDX modulation output.
BIT
R/W
RST
NAME
DESCRIPTION
2
R/W
0
DEMP
Deemphasis : 0 – No Deemphasis, 1- Deemphasis
By setting this bit to one deemphasis will implemented on all channels. When this is used it takes the place of
biquad #1 in each channel and any coefficients using biquad #1 will be ignored. DSPB(DSP Bypass) bit must
be set to 0 for Deemphasis to function.
BIT
3
R/W
R/W
R/W
R/W
RST
NAME
SAO0
SAO1
SAO2
DESCRIPTION
0
0
0
Serial Audio Output Interface Format : Determines the interface
format of the output serial digital audio interface.
4
5
The STA306 features a configurable digital serial audio interface. The settings of the SAIx bits determine how
the output to this interface is interpreted. Six formats are accepted.
16/33
STA306
Table 4. Interface format as a function of SAO bits.
SAO(2..0)
Interface Format
2
000
I S
001
010
011
100
101
Left-Justified Data
Right-Justified 16-bit Data
Right-Justified 18-bit Data
Right-Justified 20-bit Data
Right-Justified 24-bit Data
BIT
R/W
RST
NAME
DESCRIPTION
6
R/W
0
SAOFB
Determines MSB or LSB first for all SAO formats;
0 – MSB First
1 – LSB First
3.5 Configuration Register F (address 05h)
BIT
NAME
RST
D7
EAPD
0
D6
D5
D4
D3
AME
0
D2
COD
0
D1
SID
0
D0
PWMD
0
BIT
R/W
RST
NAME
DESCRIPTION
0
R/W
0
PWMD PWM Output Disable: 0 – PWM Output Normal
1- No PWM Output
2
2
1
R/W
0
SID
Serial Interface(I S Out) Disable: 0 – I S Output Normal
2
1- No I S Output
2
3
R/W
R/W
0
0
COD
AME
Clock Output Disable: 0 – Clock Output Normal
1- No Clock Output
AM Mode Enable : 0 – Normal DDX operation.
1 – AM reduction mode DDX operation.
The STA306 features a DDX processing mode that minimizes the amount of noise generated in frequency range
of AM radio. This mode is intended to be used when DDX is operating in a device with an AM tuner active. The
SNR of the DDX processing is reduced to ~83dB in this mode, which is still greater than the SNR of AM radio.
BIT R/W RST NAME
DESCRIPTION
7
R/W EAPD External Amplifier Power Down:
0
0 – External Power Stage Power Down Active
1 - Normal Operation
This output bit, on pin 51 of the device, is used to mute the DDX Power Devices for Power-Down.
3.6 Master Mute Register (address 06h)
BIT
NAME
RST
D7
D6
D5
D4
D3
D2
D1
D0
MMUTE
0
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STA306
3.7 Master Volume Register (address 07h)
BIT
NAME
RST
D7
MV7
1
D6
MV6
1
D5
MV5
1
D4
MV4
1
D3
MV3
1
D2
MV2
1
D1
MV1
1
D0
MV0
1
3.8 Channels 1,2,3,4,5,6 Mute (address 08h)
BIT
NAME
RST
D7
C8M
0
D6
C7M
0
D5
C6M
0
D4
C5M
0
D3
C4M
0
D2
C3M
0
D1
C2M
0
D0
C1M
0
3.9 Channel 1 Volume (address 09h)
BIT
NAME
RST
D7
C1V7
0
D6
C1V6
0
D5
C1V5
1
D4
C1V4
1
D3
C1V3
0
D2
C1V2
0
D1
C1V1
0
D0
C1V0
0
3.10 Channel 2 Volume (address 0Ah)
BIT
NAME
RST
D7
C2V7
0
D6
C2V6
0
D5
C2V5
1
D4
C2V4
1
D3
C2V3
0
D2
C2V2
0
D1
C2V1
0
D0
C2V0
0
3.11 Channel 3 Volume (address 0Bh)
BIT
NAME
RST
D7
C3V7
D6
C3V6
0
D5
C3V5
D4
D3
D2
D1
D0
C3V4
C3V3
C3V2
C3V1
C3V0
0
1
1
0
0
0
0
3.12 Channel 4 Volume (address 0Ch)
BIT
NAME
RST
D7
C4V7
0
D6
C4V6
0
D5
C4V5
1
D4
C4V4
1
D3
C4V3
0
D2
C4V2
0
D1
C4V1
0
D0
C4V0
0
3.13 Channel 5 Volume (address 0Dh)
BIT
NAME
RST
D7
C5V7
0
D6
C5V6
0
D5
C5V5
1
D4
C5V4
1
D3
C5V3
0
D2
C5V2
0
D1
C5V1
0
D0
C5V0
0
18/33
STA306
3.14 Channel 6 Volume (address 0Eh)
BIT
NAME
RST
D7
C6V7
0
D6
C6V6
0
D5
C6V5
1
D4
C6V4
1
D3
C6V3
0
D2
C6V2
0
D1
C6V1
0
D0
C6V0
0
The Volume structure of the STA306 consists of individual volume registers for each channel and a master vol-
ume register that provides an offset to each channels volume setting. The individual channel volumes are ad-
justable in 0.5dB steps from +24dB to -103dB. As an example if C5V = 0Bh or +18.5dB and MV = 21h or -
16.5dB, then the total gain for channel 5 = +2dB. The Master Mute when set to 1 will mute all channels at once,
whereas the individual channel mutes(CxM) will mute only that channel. Both the Master Mute and the Channel
Mutes provide a "soft mute" with the volume ramping down to mute in 8192 samples from the maximum volume
setting at the internal processing rate(~192kHz). A "hard mute" can be obtained by commanding a value of all
1's(255) to any channel volume register or the master volume register. When volume offsets are provided via
the master volume register any channel that whose total volume is less than -103dB will be muted. All changes
in volume take place at zero-crossings when ZCE = 1(configuration register B) on a per channel basis as this
creates the smoothest possible volume transitions. When ZCE=0, volume updates will occur immediately.
19/33
STA306
Table 5. Master Volume Offset as a function of MV(7..0).
MV(7..0)
00000000(00h)
00000001(01h)
00000010(02h)
…
Volume Offset from Channel Value
0dB
-0.5dB
-1dB
…
-38dB
01001100(4Ch)
…
…
11111110(FEh)
11111111(FFh)
-127dB
Hard Master Mute
Channel Volume as a function of CxV(7..0)
CxV(7..0)
00000000(00h)
00000001(01h)
00000010(02h)
…
Volume
+24dB
+23.5dB
+23dB
…
00101111(2Fh)
00110000(30h)
00110001(31h)
…
+0.5dB
0dB
-0.5dB
…
11111110(FEh)
11111111(FFh)
-103dB
Hard Channel Mute
3.15 Channel Input Mapping Channels 1 & 2 (address 11h)
BIT
NAME
RST
D7
D6
C2IM2
0
D5
C2IM1
0
D4
C2IM0
1
D3
D3
D3
D2
C1IM2
0
D1
C1IM1
0
D0
C1IM0
0
3.16 Channel Input Mapping Channels 3 & 4 (address 12h)
BIT
NAME
RST
D7
D6
C4IM2
0
D5
C4IM1
1
D4
C4IM0
1
D2
C3IM2
0
D1
C3IM1
1
D0
C3IM0
0
3.17 Channel Input Mapping Channels 5 & 6 (address 13h)
BIT
NAME
RST
D7
D6
C6IM2
1
D5
C6IM1
0
D4
C6IM0
1
D2
C5IM2
1
D1
C5IM1
0
D0
C5IM0
0
20/33
STA306
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Map-
ping registers. This allows for flexibility in processing, simplifies output stage designs, and enables the ability
to perform crossovers. The default settings of these registers map each I2S input channel to its corresponding
processing channel.
For example, to map input 2 to Channel 5, set Address 11h, bits D6, D5 and D4 to 100. Now, inputs 2 and 5 go
to Channel 5.
Table 6. Channel Mapping as a function of CxIM bits
2
CxIM(2..0)
I S Input Mapped to:
Channel 1
000
001
010
011
100
101
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
6:1
Channel 2
Mux
Channel X
Channel 3
Channel 4
3
CxIM(2..0)
Channel 5
Channel 6
STA306 Output Phasing
CH1
CH2
CH3
CH4
CH5
CH6
1/384kHz or 2.874us
21/33
STA306
3.18 Channel Limiter Select Channels 1,2,3,4 (address 15h)
BIT
NAME
RST
D7
C4LS1
0
D6
C4LS0
0
D5
C3LS1
0
D4
C3LS0
0
D3
C2LS1
0
D2
C2LS0
0
D1
C1LS1
0
D0
C1LS0
0
3.19 Channel Limiter Select Channels 5,6 (address 16h)
BIT
NAME
RST
D7
C8LS1
0
D6
C8LS0
0
D5
C7LS1
0
D4
C7LS0
0
D3
C6LS1
0
D2
C6LS0
0
D1
C5LS1
0
D0
C5LS0
0
3.20 Limiter 1 Attack/Release Rate (address 17h)
BIT
NAME
RST
D7
L1R3
1
D6
L1R2
0
D5
L1R1
1
D4
L1R0
0
D3
L1A3
0
D2
L1A2
1
D1
L1A1
1
D0
L1A0
0
3.21 Limiter 1 Attack/Release Threshold (address 18h)
BIT
NAME
RST
D7
L1AT3
0
D6
L1AT2
1
D5
L1AT1
1
D4
L1AT0
0
D3
L1RT3
0
D2
L1RT2
1
D1
L1RT1
1
D0
L1RT0
1
3.22 Limiter 2 Attack/Release Rate (address 19h)
BIT
NAME
RST
D7
L2R3
1
D6
L2R2
0
D5
L2R1
1
D4
L2R0
0
D3
L2A3
0
D2
L2A2
1
D1
L2A1
1
D0
L2A0
0
3.23 Limiter 2 Attack/Release Threshold (address 1Ah)
BIT
NAME
RST
D7
L2AT3
0
D6
L2AT2
1
D5
L2AT1
1
D4
L2AT0
0
D3
L2RT3
0
D2
L2RT2
1
D1
L2RT1
1
D0
L2RT0
1
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STA306
Basic Limiter and Volume Flow Diagram
.
Limiter
RMS
Gain/Volume
Input
Gain
Output
Attenuation
Saturation
A limiter is basically a variable gain device, where the amount of gain applied depends on the input signal level.
As the name implies, compression limits the dynamic range of the signal.
The STA306 includes 2 independent limiter blocks.
The purpose of the limiters is to automatically reduce the dynamic range of the input signal to prevent the out-
puts from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environ-
ment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the
DRC bit in Configuration Register B; address 0x02, bit 7.
Each channel can be mapped to either limiter or not mapped. Non-mapped channels will clip when 0dBFS is
exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum
absolute value of all these channels, perform the limiting algorithm on that value, and then, if needed, adjust the
gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers. It is recommended in anti-clipping mode to
set this to 0dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain
can be added digitally within the STA306 it is possible to exceed 0dBFS or any other LxAT setting. When this
occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced
when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The
gain reduction occurs on a peak-detect algorithm.
The release of limiter (uncompression), when the gain is again increased, is dependent on a RMS-detect algo-
rithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared
to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below
the release threshold, the gain is again increased (uncompressed) at a rate dependent upon the Release Rate
register. The gain can never be increased past its set value and therefore the release will only occur if the limiter
has already reduced the gain.
The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as
over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". In
AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is
set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is
set relative to the maximum volume setting plus the attack threshold.
Table 7. Channel Limiter Mapping as a function of CxLS bits.
CxLS(1,0)
Channel Limiter Mapping
Channel has limiting disabled
00
01
10
Channel is mapped to limiter #1
Channel is mapped to limiter #2
23/33
STA306
Table 8. Limiter Attack Rate as a function of LxA bits.
LxA(3..0)
Attack Rate dB/ms
0001
0010
0011
LxA(3..0)
1.3536
0.9024
0.4512
0.2256
0.1504
0.1123
0.0902
0.0752
0.0645
0.0564
0.0501
0.0451
0000
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
note: Shaded areas are Default Settings
Table 9. Limiter Release Rate and Uncompression Threshold as a function of LxR bits
LxR(3..0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Release Rate dB/ms
0.5116
0.1370
0.0744
0.0499
0.0360
0.0299
0.0264
0.0208
0.0198
0.0172
0.0147
0.0137
0.0134
0.0117
0.0110
0.0104
24/33
STA306
Table 10. Limiter Attack Threshold as a function of LxAT bits.
LxAT(3..0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AC(dB relative to FS)
DRC(db relative to Volume)
-12
-10
-8
-22
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
+2
+3
+4
+5
+6
+7
+8
+9
+10
-7
-6
-5
-4
-3
-2
-1
0
Table 11. Limiter Release Threshold as a function of LxRT bits
LxRT(3..0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AC(dB relative to FS)
•
DRC(db relative to Volume + LxAT)
•
-23dB
-33dB
-16.9dB
-13.4dB
-10.9dB
-9.0dB
-26.9dB
-23.4dB
-20.9dB
-19.0dB
-17.4dB
-16.0dB
-14.9dB
-13.8dB
-12.9dB
-12.1dB
-11.3dB
-10.65dB
-10dB
-7.4dB
-6.0dB
-4.9dB
-3.8dB
-2.9dB
-2.1dB
-1.3dB
-0.65dB
0dB
+0.6dB
-9.4dBdB
25/33
STA306
3.24 Bass and Treble Tone Control(address 1Bh)
BIT
NAME
RST
D7
TTC3
0
D6
TTC2
1
D5
TTC1
1
D4
TTC0
1
D3
BTC3
0
D2
BTC2
1
D1
BTC1
1
D0
BTC0
1
The STA306 contains bass and treble tone control adjustments. These are selectable from +12dB to -12dB of
boost or cut. These are 1st order shelving filters with a corner frequency of 150Hz for bass and 3kHz for treble.
Any gain introduced in the tone controls will carry through to the volume and limiting block without saturation.
Table 12. Tone Control Boost/Cut as a function of BTC and TTC bits
BTC(3..0)/TTC(3..0)
Boost/Cut
-12dB
-12dB
…
0000
0001
…
0111
0110
0111
1000
1001
…
-4dB
-2dB
0dB
+2dB
+4dB
…
1101
1110
1111
+12dB
+12dB
+12dB
3.25 Coefficient Address Register (address 1Ch)
BIT
NAME
RST
D7
CFA7
0
D6
CFA6
0
D5
CFA5
0
D4
CFA4
0
D3
CFA3
0
D2
CFA2
0
D1
CFA1
0
D0
CFA0
0
3.26 Coefficient b2 Data Register Bits 23..16 (address 1Dh)
BIT
NAME
RST
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
D2
C1B18
0
D1
C1B17
0
D0
C1B16
0
3.27 Coefficient b2 Data Register Bits 15..8 (address 1Eh)
BIT
NAME
RST
D7
C1B15
0
D6
C1B14
0
D5
C1B13
0
D4
C1B12
0
D3
C1B11
0
D2
C1B10
0
D1
C1B9
0
D0
C1B8
0
26/33
STA306
3.28 Coefficient b2 Data Register Bits 7..0 (address 1Fh)
BIT
NAME
RST
D7
C1B7
0
D6
C1B6
0
D5
C1B5
0
D4
C1B4
0
D3
C1B3
0
D2
C1B2
0
D1
C1B1
0
D0
C1B0
0
3.29 Coefficient b0 Data Register Bits 23..16 (address 20h)
BIT
NAME
RST
D7
C2B23
0
D6
C2B22
0
D5
C2B21
0
D4
C2B20
0
D3
C2B19
0
D2
C2B18
0
D1
C2B17
0
D0
C2B16
0
3.30 Coefficient b0 Data Register Bits 15..8 (address 21h)
BIT
NAME
RST
D7
C2B15
0
D6
C2B14
0
D5
C2B13
0
D4
C2B12
0
D3
C2B11
0
D2
C2B10
0
D1
C2B9
0
D0
C2B8
0
3.31 Coefficient b0 Data Register Bits 7..0 (address 22h)
BIT
NAME
RST
D7
C2B7
0
D6
C2B6
0
D5
C2B5
0
D4
C2B4
0
D3
C2B3
0
D2
C2B2
0
D1
C2B1
0
D0
C2B0
0
3.32 Coefficient a2 Data Register Bits 23..16 (address 23h)
BIT
NAME
RST
D7
C3B23
0
D6
C3B22
0
D5
C3B21
0
D4
C3B20
0
D3
C3B19
0
D2
C3B18
0
D1
C3B17
0
D0
C3B16
0
3.33 Coefficient a2 Data Register Bits 15..8 (address 24h)
BIT
NAME
RST
D7
C3B15
0
D6
C3B14
0
D5
C3B13
0
D4
C3B12
0
D3
C3B11
0
D2
C3B10
0
D1
C3B9
0
D0
C3B8
0
3.34 Coefficient a2 Data Register Bits 7..0 (address 25h)
BIT
NAME
RST
D7
C3B7
0
D6
C3B6
0
D5
C3B5
0
D4
C3B4
0
D3
C3B3
0
D2
C3B2
0
D1
C3B1
0
D0
C3B0
0
3.35 Coefficient a1 Data Register Bits 23..16 (address 26h)
BIT
NAME
RST
D7
C4B23
0
D6
C4B22
0
D5
C4B21
0
D4
C4B20
0
D3
C4B19
0
D2
C4B18
0
D1
C4B17
0
D0
C4B16
0
27/33
STA306
3.36 Coefficient a1 Data Register Bits 15..8 (address 27h)
BIT
NAME
RST
D7
C4B15
0
D6
C4B14
0
D5
C4B13
0
D4
C4B12
0
D3
C4B11
0
D2
C4B10
0
D1
C4B9
0
D0
C4B8
0
3.37 Coefficient a1 Data Register Bits 7..0 (address 28h)
BIT
NAME
RST
D7
C4B7
0
D6
C4B6
0
D5
C4B5
0
D4
C4B4
0
D3
C4B3
0
D2
C4B2
0
D1
C4B1
0
D0
C4B0
0
3.38 Coefficient b1 Data Register Bits 23..16 (address 29h)
BIT
NAME
RST
D7
C5B23
0
D6
C5B22
0
D5
C5B21
0
D4
C5B20
0
D3
C5B19
0
D2
C5B18
0
D1
C5B17
0
D0
C5B16
0
3.39 Coefficient b1 Data Register Bits 15..8 (address 2Ah)
BIT
NAME
RST
D7
C5B15
0
D6
C5B14
0
D5
C5B13
0
D4
C5B12
0
D3
C5B11
0
D2
C5B10
0
D1
C5B9
0
D0
C5B8
0
3.40 Coefficient b1 Data Register Bits 7..0 (address 2Bh)
BIT
NAME
RST
D7
C5B7
0
D6
C5B6
0
D5
C5B5
0
D4
C5B4
0
D3
C5B3
0
D2
C5B2
0
D1
C5B1
0
D0
C5B0
0
3.41 Coefficient Write Control Register (address 2Ch)
BIT
NAME
RST
D7
D6
D5
D4
D3
D2
D1
D0
WA
W1
Coefficients for EQ and Bass Management are handled internally in the STA306 via RAM. Access to this RAM
is available to the user via an I2C register interface. A collection of I2C registers is dedicated to this function.
One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written
or that were read, and one contains bits used to control the writing of the coefficient(s) to RAM. The following
are step instructions for reading and writing coefficients.
Reading a coefficient from RAM
– write 8-bit address to I2C register 1Ch
– ead top 8-bits of coefficient in I2C address 1Dh
– ead middle 8-bits of coefficient in I2C address 1Eh
– ead bottom 8-bits of coefficient in I2C address 1Fh
28/33
STA306
Writing a single coefficient to RAM
– write 8-bit address to I2C register 1Ch
– write top 8-bits of coefficient in I2C address 1Dh
– write middle 8-bits of coefficient in I2C address 1Eh
– write bottom 8-bits of coefficient in I2C address 1Fh
– write 1 to W1 bit in I2C address 2Bh
Writing a set of coefficients to RAM
– write 8-bit starting address to I2C register 1Ch
– write top 8-bits of coefficient b2 in I2C address 1Dh
– write middle 8-bits of coefficient b2 in I2C address 1Eh
– write bottom 8-bits of coefficient b2 in I2C address 1Fh
– write top 8-bits of coefficient b0 in I2C address 20h
– write middle 8-bits of coefficient b0 in I2C address 21h
– write bottom 8-bits of coefficient b0 in I2C address 22h
– write top 8-bits of coefficient a2 in I2C address 23h
– write middle 8-bits of coefficient a2 in I2C address 24h
– write bottom 8-bits of coefficient a2 in I2C address 25h
– write top 8-bits of coefficient a1 in I2C address 26h
– write middle 8-bits of coefficient a1 in I2C address 27h
– write bottom 8-bits of coefficient a1 in I2C address 28h
– write top 8-bits of coefficient b1 in I2C address 29h
– write middle 8-bits of coefficient b1 in I2C address 2Ah
– write bottom 8-bits of coefficient b1 in I2C address 2Bh
– write 1 to WA bit in I2C address 2Ch
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients cor-
responding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side effects. When
using this technique, the 8-bit address would specify the address of the biquad b2 coefficient (e.g. 0, 5, 10, 15,
…, 50, … 195 decimal), and the STA306 will generate the RAM addresses as offsets from this base value to
write the complete set of coefficient data.
Equalization:
Figure 3. Data Flow for single channel Biquad / Bass / Treble block.:
From
To
1st Interpolation
Stage
Volume/
Limiter
Bass/
Treble
PreScale
Biquad1
Biquad2
Biquad3
Biquad4
Biquad5
Five user-programmable 28-bit biquads are available per channel in the STA306. These biquads run at 192kHz
for 48kHz, 96kHz, or 192kHz input and at 176.4kHz for 44.1kHz, 88.2kHz, and 176.4kHz input. The PreScale
block is used for attenuation when filters are to be designed that boost frequencies above 0dBFS. This is a
29/33
STA306
single 28-bit signed multiply, with 800000h = -1 and 7FFFFFh = 0.9999998808. These values are labeled
CxPS, with x representing the channel. The biquads use this equation:
Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2]
= b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2]
Y[n] represents the output and X[n] represents the input. Coefficients are defined in the following manner:
CxHx0 = b2
CxHx1 = b0/2
CxHx2 = -a2
CxHx3 = -a1/2
CxHx4 = b1/2
The first x represents the channel and the second the biquad number. For example C3H41 is the b0/2 coeffi-
cient in the fourth series biquad in channel 3. The biquad link bit allows all channels to use the coefficients of
channel 1.
Bass Management
Channel 6 provides the ability to scale and mix all channels before the biquad block. This allows for information
from any channel to be redirected to this channel and then filtered appropriately for a subwoofer application.
When the BME bit is set (bit D5 of Configuration Register A, at address 00h) the input to the biquad section is
routed from the scale and mix block instead of the normal channel 6 1st stage interpolation output.
Eight scaling coefficients are provided to perform this function. They are labeled CxBMS with x representing the
channel that is being scaled. Each input channel is multiplied by its corresponding scale factor and summed.
The output of the summation is the output of the scale and mix block.
Post-Scale
The STA306 provides one additional multiplication after the last interpolation stage and before the distortion
compensation on each channel. This is a 24-bit signed fractional multiply. The scale factor for this multiply is
loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. All chan-
nels can use the channel 1 by setting the post-scale link bit.
RAM Block for Biquads and Bass Management:
Index
(Decimal)
Index
(Hex)
Coefficient
Default
000000h
0
00h
01h
02h
03h
04h
05h
…
Channel 1 - Biquad 1
C1H10(b
2)
C1H11(b0/2)
C1H12(a2)
C1H13(a1/2)
C1H14(b1/2)
C1H20
1
3FFFFFh
000000h
000000h
000000h
000000h
…
2
3
4
5
Channel 1 - Biquad 2
…
…
…
30/33
STA306
24
18h
19h
1Ah
…
Channel 1 - Biquad 5
Channel 2 - Biquad 1
C1H54
C2H10
C2H11
…
000000h
25
000000h
3FFFFFh
…
26
…
…
45
2Dh
…
Distortion Compensation
DCC 23…0
…
000000h
…
…
…
49
31h
32h
…
Channel 2 - Biquad 5
C2H54
C3H10
…
000000h
000000h
…
50
Channel 3 - Biquad 1
…
…
200
201
202
…
C8h
C9h
CAh
…
Channel 1 - Pre-Scale
C1PS
C2PS
C3PS
…
800000h
800000h
800000h
…
Channel 2 – Pre-Scale
Channel 3 – Pre-Scale
…
208
209
…
D0h
D1h
…
Channel 1 – BassM Scale
C1BMS
C2BMS
…
000000h
000000h
…
Channel 2 – BassM Scale
…
216
217
…
D8h
D9h
…
Channel 1 – Post-Scale
C1PS
C2PS
…
800000h
800000h
…
Channel 2 – Post-Scale
…
224
…
F0h
…
Not Used
…
…
…
255
FFh
Not Used
31/33
STA306
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.063
A
1.60
A1
A2
B
0.05
0.15 0.002
0.006
1.35
0.17
0.09
1.40
0.22
1.45 0.053 0.055 0.057
0.27 0.0066 0.0086 0.0086
0.0035
C
D
11.80 12.00 12.20 0.464 0.472 0.480
9.80 10.00 10.20 0.386 0.394 0.401
D1
D3
e
7.50
0.50
0.295
0.0197
E
11.80 12.00 12.20 0.464 0.472 0.480
9.80 10.00 10.20 0.386 0.394 0.401
E1
E3
L
7.50
0.60
1.00
0.295
0.75 0.0177 0.0236 0.0295
0.0393
0.45
L1
K
TQFP64 (10 x 10 x 1.4mm)
0˚ (min.), 3.5˚ (min.), 7˚(max.)
0.080
ccc
0.0031
D
D1
D3
A
A2
A1
48
33
32
49
0.08mm
ccc
Seating Plane
17
16
64
1
C
e
K
TQFP64
0051434 E
32/33
STA306
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
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33/33
相关型号：
STA30813TR
1 CHANNEL(S), TONE CONTROL CIRCUIT, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64
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