STA50613TR [STMICROELECTRONICS]
6A 4 CHANNEL, HALF BRIDGE BASED PRPHL DRVR, PDSO36, SOP-36;
| 型号： | STA50613TR |
| 厂家： | 
ST |
| 描述： | 6A 4 CHANNEL, HALF BRIDGE BASED PRPHL DRVR, PDSO36, SOP-36 驱动 CD 光电二极管 接口集成电路 |
| 文件： | 总14页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA506
40V 4A QUAD POWER HALF BRIDGE
1 FEATURES
Figure 1. Package
■ MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
■ 200mΩ RdsON COMPLEMENTARY DMOS
PowerSO36
OUTPUT STAGE
■ CMOS COMPATIBLE LOGIC INPUTS
■ THERMAL PROTECTION
Table 1. Order Codes
Part Number
STA506
Pacge
PerSO36
Tape & Reel
■ THERMAL WARNING OUTPUT
■ UNDER VOLTAGE PROTECTION
■ SHORT CIRCUIT PROTECTION
STA50613TR
The device is particularly designed to make the out-
put stage of stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver 60 + 60W @
2 DESCRIPTION
STA506 is a monolithic quad half bridge stage in Mul-
tipower BCD Technology.
THD 10% at V 32V output power on 8
Ω
load and
cc
80W @ THD = 10% at V 36V on 8
Ω load in single
CC
The device can be used as dual bridge or reconfig-
ured, by connecting CONFIG pin to Vdd pin, as single
bridge with double current capability, and as half
bridge (Binary mode) with half current capability.
BTL configuration. In single BTL configuration is also
capable to deliver a peak of 120W @THD = 10% at
V
= 32V on 4
Ω
L
load. The input pins have threshold
CC
proportional to V pin voltage.
Figure 2. Application Circuit (Dual TL)
+VCC
V
CC1A
15
17
16
C30
1µF
C55
1000µF
IN1A
29
M3
M2
M5
M4
IN1A
L18 22µH
C20
V
L
23
24
+3.3V
OUT1A
CONFIG
PWRDN
FAULT
100nF
OUT1A
GND1A
C52
330pF
PWRDN
25
C99
100nF
14
12
R98
6
PROTECTIONS
R57
10K
R59
10K
27
26
&
C23
470nF
8Ω
LOGIC
VCC1B
R63 R100
C101
100nF
TRI-STATE
20
6
C58
100nF
C31
1µF
11
10
C21
100nF
TH_WAR
IN1B
28
30
OUT1B
OUT1B
GND1B
TH_WAR
L19 22µH
IN1B
VDD
VDD
VSS
VSS
21
22
33
34
13
7
REGULATORS
V
CC2A
C32
1µF
M17
M15
M16
M14
C58
100nF
C53
100nF
L113 22µH
VCCSIGN
8
9
35
OUT2A
C60
100nF
C110
100nF
V
CCSIGN
36
31
20
19
OUT2A
GND2A
C109
330pF
C107
100nF
6
4
R103
6
IN2A
IN2B
IN2A
C108
470nF
8Ω
GND-Reg
V
CC2B
R104
20
R102
6
C106
100nF
GND-Clean
C33
1µF
3
2
C111
100nF
OUT2B
OUT2B
GND2B
IN2B
32
1
L112 22µH
GNDSUB
5
D00AU1148B
Rev. 6
1/14
February 2006
STA506
Table 2. Pin Function
Pin n.
1
Pin Name
GND-SUB
OUT2B
Description
Substrate Ground
Output Half Bridge 2B
Positive Supply
2 ; 3
4
V
CC 2B
5
GND2B
GND2A
Negative Supply
Negative Supply
Positive Supply
6
7
VCC 2A
8 ; 9
10 ; 11
12
OUT2A
OUT1B
VCC1B
GND1B
GND1A
Output Half Bridge 2A
Output Half Bridge 1B
Positive Supply
13
Negative Supply
Negative Supply
Positive Supply
14
15
VCC1A
16 ; 17
18
OUT1A
NC
Output Half Bridge 1A
Not Connected
19
GND-clean Logical Ground
20
GND-Reg
Vdd
Ground for Regulator Vdd
21 ; 22
23
5V Regulator Referred to Ground
Logic ReferenVoltage
Confuration pin
VL
24
CONFIG
PWRDN
25
Stand-by pin
26
TRI-STAE High-Z pin
27
FLT
TH-WAR
IN1A
Fault pin advisor
Thermal warning advisor
Input of Half Bridge 1A
Input of Half Bridge 1B
Input of Half Bridge 2A
Input of Half Bridge 2B
5V Regulator Referred to +VCC
Signal Positive Supply
29
30
IN1B
31
IN2A
32
IN2B
33 ; 34
35 ; 36
VSS
VCC Sign
2/14
STA506
Table 3. Functional Pin Status
Pin name
Pin n.
27
Logical value
IC -STATUS
FAULT
0
1
Fault detected (Short circuit, or Thermal ..)
Normal Operation
FAULT (*)
TRI-STATE
TRI-STATE
PWRDN
27
26
26
25
25
28
28
0
1
0
1
0
1
All powers in Hi-Z state
Normal operation
Low absorpion
PWRDN
Normal operation
THWAR
Temperature of the IC =130°C
Normal operation
THWAR(*)
CONFIG
24
24
0
1
Normal Operation
CONFIG(**)
OUT1A = OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
(*) :
(**):
The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) to implement single BT(mono mode) operation for
high current.
Figure 3. Pin Connection
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
V
CCSign
GND-SUB
OUT2B
OUT2B
VCC2B
VCCSign
VSS
3
4
VSS
5
IN2B
GND2B
GND2A
6
IN2A
7
INB
VCC2A
8
IN1A
OUT2A
OUT2A
OUT1B
OUT1B
9
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
10
11
12
13
14
15
16
17
18
VCC1B
GND1B
GND1A
VCC1A
OUT1A
OUT1A
N.C.
V
L
V
V
DD
DD
GND-Reg
GND-Clean
D01AU1273
3/14
STA506
Table 4. Absolute Maximum Ratings
Symbol
VCC
Parameter
Value
40
Unit
V
DC Supply Voltage (Pin 4,7,12,15)
Maximum Voltage on pins 23 to 32 (logic reference)
Power Dissipation (Tcase = 70°C)
Vmax
Ptot
5.5
V
50
W
Top
Operating Temperature Range
-40 to 90
-40 to 150
°C
°C
T
stg, Tj
Storage and Junction Temperature
Table 5. (*) Recommended Operating Conditions
Symbol
VCC
Parameter
Min.
10
Typ.
Max.
36.0
5.0
Unit
V
DC Supply Voltage
VL
Input Logic Reference
Ambient Temperature
2.7
0
3.3
v
Tamb
7
°C
(*) performances not guaranteed beyond recommended operating conditions
Table 6. Thermal Data
Symbol
Parameter
Min.
Typ.
Max.
Unit
°C/W
°C
Tj-case Thermal Resistance Junction to Case (thermal pad)
1.5
TjSD
Twarn
thSD
Thermal shut-down junction temperature
Thermal warning temperature
150
130
25
°C
Thermal shut-down hysteresis
°C
Table 7. Electrical Characteristcs: refer to circuit in Fig.1 (VL = 3.3V; VCC = 32V; RL = 8Ω;
fsw = 384KHz; Tamb = 25°C unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
RdsON Power Pchannel/Nchannel
MOSFET RdsON
Id=1A
200
270
mΩ
Idss
Power Pchannl/Nchannel
leakage Idss
VCC =35V
50
µA
gN
gP
PowPchannel RdsON Matching Id=1A
95
95
%
%
Power Nchannel RdsON
Matching
Id=1A
Dt_s
Dt_d
Low current Dead Time (static)
see test circuit no.1; see fig. 3
10
20
50
ns
ns
High current Dead Time (dinamic) L=22µH; C = 470nF; RL = 8 Ω
Id=3.5A; see fig. 5
td ON
td OFF
tr
Turn-on delay time
Turn-off delay time
Rise time
Resistive load
100
100
25
ns
ns
ns
ns
V
Resistive load
Resistive load; as fig.3
Resistive load; as fig. 3
tf
Fall time
25
VCC
VIN-H
Supply voltage operating voltage
High level input voltage
10
36
VL/2
V
+300mV
4/14
STA506
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VIN-L
Low level input voltage
VL/2
-
V
300mV
IIN-H
IIN-L
High level Input current
Low level input current
Pin Voltage = VL
1
1
µA
µA
µA
Pin Voltage = 0.3V
VL = 3.3V
I
High level PWRDN pin input
current
35
PWRDN-H
VLOW
Low logical state voltage VLow
(pin PWRDN, TRISTATE) (note 1)
VL = 3.3V
VL = 3.3V
PWRDN = 0
0.8
V
V
VHIGH
High logical state voltage VHigh
(pin PWRDN, TRISTATE) (note 1)
1.7
3
IVCC-
PWRDN
Supply CURRENT from Vcc in
Power Down
mA
IFAULT
Output Current pins
FAULT -TH-WARN when
FAULT CONDITIONS
Vpin = 3.3V
1
mA
mA
mA
IVCC-hiz Supply Current from Vcc in Tri-
state
VCC = 30V; Tri-state = 0
22
50
IVCC
Supply Current from Vcc in
operation
both channel switching)
VCC =30V;
Input Pulse width = 50% Duty;
Switching Frequency = 384KH
No LC filters;
IVCC-q
VUV
Isc (short circuit current limit)
(note 2)
4
6
7
8
A
Undervoltage protection threshold
V
tpw-min Output minimum pulse width
Notes: 1. The following table explains the V
No Load
70
150
ns
, V
LOW
variation with V
HIGH
L
Table 8.
VL
2.7
3.3
5
VLOW min
0.7
VHIGH max
1.5
Unit
V
0.8
1.7
V
0.85
1.85
V
Note e relevant Application Note AN1994
Table 9. Logic Truth Table (see fig. 4)
OUTPUT
MODE
TRI-STATE
INxA
INxB
Q1
Q2
Q3
Q4
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
Hi-Z
DUMP
ON
OFF
ON
NEGATIVE
POSITIVE
Not used
OFF
ON
OFF
OFF
ON
OFF
5/14
STA506
Figure 4. Test Circuit.
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
DTf
Duty cycle = 50%
INxY
M58
M57
OUTxY
R 8Ω
+
-
V67 =
vdc = Vcc/
gnd
D03AU1458
Figure 5.
+VCC
Q1
Q2
OUTxA
OUTxB
INxA
INxB
Q3
Q4
GND
D00AU1134
Figure 6.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
M57
M64
M63
Q1
OUTA
Iout=4.5A
Q2
OUTB
Iout=4.5A
DTin(A)
DTout(B)
L68 22µ
DTin(B)
INB
Rload=8Ω
INA
L67 22µ
Q3
C69
470nF
C70
470nF
Q4
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
D03AU1517
6/14
STA506
3 TECHNICAL INFO:
The STA506 is a dual channel H-Bridge that is able to deliver more than 60W per channel (@ THD=10%) of
audio output power in high efficiency.
The STA506 converts both DDX and binary-controlled PWM signals into audio power at the load. It includes a
logic interface , integrated bridge drivers, high efficiency MOSFET outputs and thermal and short circuit protec-
tion circuitry.
In DDX mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect
the speaker load to the input supply or to ground in a Bridge configuration, according to the damped ternary
Modulation operation.
In Binary Mode operation , both Full Bridge and Half Bridge Modes are supported. The STA506 includes over-
current and thermal protection as well as an under-voltage
Lockout with automatic recovery. A thermal warning status is also provided.
Figure 7. STA506 Block Diagram Full-Bridge DDX® or Binary Modes
INL[1:2]
INR[1:2]
VL
OUTPL
Left
H-Bridge
Logic I/F
and Decode
PWRDN
OUTNL
TRI-STATE
Protection
Circuitry
FAULT
OR
OUTNR
TWARN
Right
H-Bridge
Regulators
Figure 8. STA506 Block Diagram Binary Half-Bridge Mode
INL[1:2]
LeftA
‰-Bridge
OUTPL
OUTNL
INR[1:2]
Logic I/F
and Decode
V
LeftB
‰-Bridge
PWRDN
TRI-STATE
Protection
Circuitry
FAULT
RightA
‰-Bridge
OUTPR
OUTNR
TWARN
RightB
‰-Bridge
Regulators
3.1 Logic Interface and Decode:
The STA506 power outputs are controlled using one or two logic level timing signals. In order to provide a proper
logic interface, the Vbias input must operate at the dame voltage as the DDX control logic supply.
3.2 Protection Circuitry:
The STA506 includes protection circuitry for over-current and thermal overload conditions. A thermal warning
pin (pin.28) is activated low (open drain MOSFET) when the IC temperature exceeds 130C, in advance of the
thermal shutdown protection. When a fault condition is detected , an internal fault signal acts to immediately
disable the output power MOSFETs, placing both H-Bridges in high impedance state. At the same time an open-
drain MOSFET connected to the fault pin (pin.27) is switched on.
There are two possible modes subsequent to activating a fault:
7/14
STA506
– 1) SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent, an activated
fault will disable the device, signaling low at the FAULT output.
The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from
High to Low to High using an external logic signal.
– 2) AUTOMATIC recovery mode: This is shown in the Application Circuit of fig.1.
The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit com-
prising R59 and C58.
An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume fol-
lowing a delay determined by the time constant of the circuit.
If the fault condition is still present , the circuit operation will continue repeating until the fault condition
is removed .
An increase in the time constant of the circuit will produce a longer recovery interval. Care must be
taken in the overall system design as not to exceed the protection thesholds under normal operation.
3.3 Power Outputs:
The STA506 power and output pins are duplicated to provide a low impedance path the device's bridged
outputs .
All duplicate power, ground and output pins must be connected for proper operation.
The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state during power-up until the
logic power supply, V , is settled.
L
3.4 Parallel Output / High Current Operation:
When using DDX Mode output , the STA506 outputs can be connected in parallel in order to increase the output
current capability to a load.
In this configuration the STA506 can provide 80W into 8 ohm or up to 120W into 4ohm.
This mode of operation is enabled with the CONFIG pin (pin.24) connected to VREG1 and the inputs combined
INLA=INLB, INRA=INRB and the outpcombined OUTLA=OTLB, OUTRA=OUTRB.
3.5 Additional Informatios:
Output Filter: A passive 2nd-order passive filter is used on the STA506 power outputs to reconstruct an analog
Audio Signal .
System performce can be significantly affected by the output filter design and choice of passive components.
A filter design for 6ohm/8ohm loads is shown in the Typical Application circuit of fig.1. Figure 9 shows a filter
desisuable for 4ohm loads.
Figure 10 shows a filter for ½ bridge mode , 4 ohm loads.
Power Dissipation & Heat Sink requirements: The power dissipated within the device will depend primarily
on the supply voltage, load impedance and output modulation level.
The PowerSO36 package of the STA506 includes an exposed thermal slug on the top of the device to provide
a direct thermal path from the IC to the heatsink.
Careful consideration must be given to the overall thermal design . See figure 8 for power derating
versus Slug temperature using different heatsinks and considering the Rth-jc =1.5°C/W.
8/14
STA506
Figure 9. STA506 Power Derating Curve
60
50
40
30
20
10
0
Pdiss(W)
1 –Infinite
2- 1.5C/W
3- 3 C/W
4- 4 C/W
1
2
3
4
0
20
40
60
80 100 120 140 160
Slug temperature C°
Figure 10. Typical Single BTL Configurationto Obtain 120W @ THD 10%, RL= 4, VCC = 32V (note 1))
VL
+3.3V
23
18
N.C.
10µH
100nF
GND-Clean
GND-Reg
17
16
O1A
19
20
100nF
FILM
11
10
100nF
X7R
10K
100nF
X7R
470nF
FILM
100nF
OUT1B
OUT1B
OUT2A
OUT2A
22Ω
6.2
1/2W
VDD
VDD
1/2W
21
22
24
4Ω
6.2
1/2W
CONFIG
9
8
330pF
X7R
32V
32V
TH_WAR
PWRDN
FAULT
TH_WAR
OUT2B
OUT2B
28
25
100nF
FILM
3
2
nPWRDN
10µH
10K
VCC1A
27
26
15
TRI-STATE
IN1A
1µF
2200µF
63V
100nF
X7R
VCC1B
VCC2A
29
30
31
32
12
7
IN1B
IN1A
IN1B
IN2A
IN2B
1µF
X7R
VSS
VSS
VCC2B
33
34
4
14
13
GND1A
GND1B
100nF
X7R
VCCSIGN
35
100nF
X7R
VCCSIGN
GNDSUB
GND2A
GND2B
36
1
6
5
Add.
D03AU1514
Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board". Peak Pow-
er for t ≤1sec
9/14
STA506
Figure 11. Typical Quad Half Bridge Configuration
+VCC
VCC1P
15
17
16
C21
2200µF
IN1A
29
M3
M2
M5
M4
R61
5K
IN1A
C31 820µF
L11 22µH
V
23
24
L
+3.3V
OUTPL
C71
100nF
CONFIG
PWRDN
FAULT
R41
20
C91
1µF
4Ω
OUTPL
PWRDN
25
C81
100nF
14
12
PGND1P
R51
6
R62
5K
C41
330pF
PROTECTIONS
R57
10K
R59
10K
27
26
&
LOGIC
VCC1N
TRI-STATE
C58
100nF
C51
1µF
C61
100nF
11
10
R63
5K
TH_WAR
IN1B
28
30
OUTNL
OUTNL
PGND1N
C32 820µF
L12 22µH
TH_WAR
C72
100nF
R42
20
IN1B
C92
1µF
4Ω
VDD
VDD
VSS
VSS
21
22
33
34
13
7
C82
100nF
R52
6
R64
5K
C42
330pF
REGULATORS
VCC2P
M17
M15
M16
M14
R65
5K
C58
100nF
C53
100nF
C33 820µF
L13 22µH
VCCSIGN
VCCSIGN
8
9
35
OUTPR
C60
100nF
C73
100nF
R43
20
C9
1µF
4Ω
36
31
20
19
OUTPR
C83
100nF
6
4
PGND2P
R53
6
R66
5K
IN2A
IN2B
C43
330pF
IN2A
GND-Reg
V
CC2N
GND-Clean
C52
1µF
C62
100nF
3
2
R67
5K
OUTNR
OUTNR
PGND2N
C34 820µF
L14 22µH
IN2B
32
1
C74
100nF
R44
20
GNDSUB
C94
1µF
4Ω
5
C84
100nF
R54
6
R68
5K
330pF
D03AU1474
For more information refer to the application notes AN1456 and AN1661
10/14
STA506
Figure 12. THD+N vs Frequency
Figure 15. THD+N vs Output Power
1
THD(%)
10
5
T
0.5
Vcc=32V
Vcc=36V
Rl=8ohm
F=1KHz
Rl=8ohm
2
1
0.2
0.5
0.1
%
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
20
50
100
200
500
Hz
1k
2k
5k
10k
20k
100m 200m
500m
1
2
5
10
20
50 80
Pout(W)
Figure 16. THD+N vs Output PoerRevision
Figure 13. Output Power vs Vsupply
10
5
THD(%)
80
70
60
Po(W)
Rl=8ohm
F=1KHz
Vcc=32V
Rl=8oh
F=1KHz
2
1
THD=10%
50
40
30
20
0.2
0.1
THD=1%
+24
0.05
10
0.02
0.01
+14
+16
+18
+20
+22
+26
+28
+30
+32
+34 +36
100m 200m
500m
1
2
5
10
20
50 80
Vsuppl
Pout(W)
Figure 14. THD+N vs Output Power
THD(%)
10
5
Vcc=34V
Rl=8ohm
1
F=1KHz
0.5
0.2
0.1
0.05
0.02
0.01
100m 200m
500m
1
2
5
10
20
50 80
Pout(W)
11/14
STA506
Figure 17. PowerSO36 (Slug Up) Mechanical Data & Package Dimensions
mm
inch
TYP. MAX.
0.135
0.126
0.039
0.008
-0.0015
0.015
0.012
0.630
0.38
DIM.
MIN.
3.25
3.1
TYP. MAX. MIN.
3.43 0.128
OUTLINE AND
MECHANICAL DATA
A
A2
A4
A5
a1
b
3.2
1
0.122
0.031
0.8
0.2
0.030
0.22
0.23
15.8
9.4
-0.040 0.0011
0.38 0.008
0.32 0.009
c
D
16
0.622
0.37
D1
D2
E
9.8
1
0.039
0.57
13.9
10.9
14.5 0.547
11.1 0.429
2.9
E1
E2
E3
E4
e
0.437
0.114
0.244
1.259
0.026
0.435
0.003
0.625
0.043
0.043
10˚
5.8
2.9
6.2
3.2
0.228
0.114
0.65
e3
G
11.05
0
0.075
15.9
1.1
0
H
15.5
0.61
h
L
0.8
1.1
0.031
N
10˚
s
8 ˚
8˚
owerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
7183931 D
12/14
STA506
Table 10. Revision History
Date
Revision
Description of Changes
December 2003
April 2004
1
2
3
4
5
6
First Issue
Inserted Technical Info and Graphics
Small changes in pag 4 and 5
April 2004
June 2004
Note 2: See relevant Application Note AN1994
Changed Vcc from 9 min to 10 min
Changed Top value on Table 4.
November 2004
February 2006
13/14
STA506
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectcs NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN STTERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO HE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR FRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED,
AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS,
NOR IN PRODUCOR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
Resale ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
14/14
相关型号：
©2020 ICPDF网 联系我们和版权申明