STA529_12 [STMICROELECTRONICS]
FFX⢠audio codec with analog and digital inputs and 2 x 1.2 W (or 2 x 100 mW HP) class-D amplifier; FFXâ ?? ¢为模拟和数字输入和2× 1.2 W（或2×100 MW高压） D类放大器的音频编解码器
| 型号： | STA529_12 |
| 厂家： | 
ST |
| 描述： | FFX⢠audio codec with analog and digital inputs and 2 x 1.2 W (or 2 x 100 mW HP) class-D amplifier |
| 文件： | 总57页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA529
FFX™ audio codec with analog and digital inputs
and 2 x 1.2 W (or 2 x 100 mW HP) class-D amplifier
Datasheet − production data
Features
■ Up to 96 dB dynamic range
TFBGA48
■ Sample rates from 8 kHz to 192 kHz
™
■ FFX class-D driver
■ 1.55 V to 1.95 V digital power supply
■ 1.80 V to 3.60 V analog and I/O power supply
™
■ 18-bit audio processing and class-D FFX
modulator
■ >90-dB SNR analog-to-digital converter
■ Digital volume control:
VFQFPN52
– +36 dB to -105 dB in 0.5-dB steps
– Software volume update
■ 16-bit ADC
■ Individual channel and master gain/attenuation
■ Automatic invalid input detect mute
2
■ 2-channel I S input/output data interface
■ Digitally controlled pop-free operation
■ 90% efficiency
■ Output power for stereo headphones or stereo
Applications
speakers applications (at THD = 10% and
■ Portable devices
– Laptops
V
= 3.3 V):
CC
– 45 mW with 32-Ω headphones
– 85 mW with 16-Ω headphones
– 720 mW with 8-Ω speakers
– 1.1 W with 4-Ω speakers
– Digital cameras
– Microless applications
Table 1.
Order code
STA529Q
Device summary
Operating temp. range
Package
Packaging
-40 to 85 °C
-40 to 85 °C
VFQFPN52
TFBGA48
Tray
Tray
STA529
March 2012
Doc ID 13095 Rev 3
1/57
This is information on a product in full production.
www.st.com
57
Contents
STA529
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection diagrams and pin descriptions . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
TFBGA48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VFQFPN52 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Electrical and thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
5
Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
SELCLK33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
5.2
5.3
Signal processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2C interface disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Volume control and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
7
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1
6.2
6.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Set fractional PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
7.2
ADC performance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2.1
7.2.2
7.2.3
Digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Programmable gain amplifier (PGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.3
Applications scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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7.4
Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
9
Driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1
I2S bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1
9.2
9.3
Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.3.1
9.3.2
9.3.3
9.3.4
DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2
I S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PCM/IF (non-delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PCM/IF (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
10
I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1 Data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.6 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.6.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.6.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
12
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.2 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.1 Package TFBGA48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.2 Package VFQFPN52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Doc ID 13095 Rev 3
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Contents
STA529
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection diagram for TFBGA48 (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Connection diagram for VFQFPN52 (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Circuit for crystal drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Diagram of input coupling and supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Right justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Left justified. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2
Figure 13. I S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14. PCM/IF (non delayed mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15. PCM/IF (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
Figure 16. I C write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2
Figure 17. I C read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. Package outline (TFBGA48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19. Package outline (VFQFPN52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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List of tables
STA529
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description for TFBGA48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin description for VFQFPN52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Load power at 1% distortion in headphone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Load power at 10% distortion in headphone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Load power at 1% distortion in speaker mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Load power at 10% distortion in speaker mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PLL lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Master volume offset as a function of register MVOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Channel volume as a function of registers LVOL and RVOL . . . . . . . . . . . . . . . . . . . . . . . 19
Oversampling table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Programmable gain performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin functions in driver-configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Package dimensions (TFBGA48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Package dimensions (VFQFPN52). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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Description
1
Description
The STA529 is a digital stereo class-D audio amplifier. It includes an audio DSP, an ST
proprietary high-efficiency class-D driver and CMOS power output stage. It is intended for
high-efficiency digital-to-power-audio conversion for portable applications. The STA529 also
™
provides output capabilities for FFX . In conjunction with a power device, the STA529
provides high-quality digital amplification.
The STA529 contains an on-chip volume/gain control.
The PWM amplifier achieves greater than 90% efficiency for longer battery life for portable
systems.
The innovative class-D modulation, allows the STA529 to work without external LC filters
and without a heatsink.
2
The STA529 I2CDIS pin disables the audio DSP functions and the I C interface provides a
direct conversion of the input signal into output power. This conversion is done without the
microcontroller.
The STA529 is designed for low-power operation with extremely low-current consumption in
standby mode. It is available in packages TFBGA48 and VFQFPN52. These are very thin
packages (1.2 mm thick) ideal for small portable applications.
Figure 1.
Block diagram
Serial digital
audio interface
OUT1A
OUT1B
Power
driver
FFX
Digital
VBIAS
modulator
volume
INL
VHI
OUT2A
OUT2B
Power
driver
ADC
VCM
VLO
PWM out I/F
PLL Divider
PGA
INR
ADC
Control
interface
OSC
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Connection diagrams and pin descriptions
STA529
2
Connection diagrams and pin descriptions
This section includes connection diagrams and pin descriptions for the following packages:
●
TFBGA48
●
VFQFPN52
2.1
TFBGA48 package
Figure 2.
Connection diagram for TFBGA48 (bottom view)
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
Table 2.
Pin
Pin description for TFBGA48
Name Type
VCC2 Supply
Description
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
Channel 2 power supply
Channel 2 power ground
Channel 2 half-bridge A output
Channel 2 half-bridge B output
Channel 1 half-bridge B output
Channel 1 half-bridge A output
Channel 1 power ground
Channel 1 power supply
I/O ring ground
GND2
Ground
OUT2A
OUT2B
OUT1B
OUT1A
GND1
Analog output
Analog output
Analog output
Analog output
Ground
VCC1
Supply
GNDIO
GND33
OUT2A
OUT2B
Ground
Ground
Pre-driver ground
Analog output
Analog output
Channel 2 half-bridge A output
Channel 2 half-bridge B output
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Connection diagrams and pin descriptions
Pin description for TFBGA48 (continued)
Table 2.
Pin
Name
OUT1B
Type
Description
B5
B6
B7
B8
C1
C2
Analog output
Analog output
Digital input
Ground
Channel 1 half-bridge B output
Channel 1 half-bridge A output
Mute (active high)
OUT1A
MUTE
GND
Digital ground
VDDIO
VCC33
Supply
I/O ring supply
Supply
Pre-driver supply
CLKOUT /
PWM2B
C7
C8
D1
Digital output
Supply
Buffered clock output / PWM2B FFX
Digital supply
VDD
XTI
Digital input
1.8V
Crystal input or master clock input
Digital output
1.8V
D2
XTO
Crystal output
D7
D8
E1
E2
E7
E8
F1
RST_N
VCM
Digital input
Analog I/O
Digital input
Digital input
Analog input
Ground
Reset (active low)
ADC common mode voltage
Master clock input 3.3-V capable
Input serial audio interface data
ADC low reference voltage
ADC analog ground
MCLK33
SDATAI
VLO
AGND
SCL
Digital input
I2C serial clock
POWERFAULT /
EAPD
Power fault signal (active high) /
external audio power-down signal
F2
Digital output
F7
F8
G1
G2
VHI
Analog input
Supply
ADC high reference voltage
ADC analog supply
AVDD
SDA
Digital I/O
Digital input
I2C serial data
I2CDIS
I2C disable pin (active high)
Master clock input selector:
G3
SELCLK33
Digital input
0: XTI selected
1: MCLK33 selected
SDATAO /
PWM2A
G4
G5
G6
Digital output
Digital I/O
Output serial audio interface data / PWM2A FFX
LRCLKO /
PWM1B
Output serial audio interface L/R-clock
(volume increases when I2CDIS = 1) / PWM1B FFX
BICLKO /
PWM1A
Output serial audio interface bit-clock
(volume decreases when I2CDIS = 1) / PWM1A FFX
Digital I/O
G7
G8
H1
VBIAS
STBY
FILT
Analog I/O
Digital input
Analog I/O
ADC microphone bias voltage
Standby (active high)
PLL loop filter terminal
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Connection diagrams and pin descriptions
STA529
Table 2.
Pin
Pin description for TFBGA48 (continued)
Name
Type
Description
Test mode (active high)
H2
H3
H4
H5
H6
H7
H8
TM
Digital input
Ground
GNDPLL
VDDPLL
LRCLKI
BICLKI
INL
PLL analog ground
Supply
PLL analog supply
Digital I/O
Digital I/O
Analog input
Analog I/O
Input serial audio interface L/R-clock
Input serial audio interface bit-clock
ADC left channel line input or microphone input
ADC right channel line input
INR
2.2
VFQFPN52 package
Figure 3.
Connection diagram for VFQFPN52 (bottom view)
27
39
40
26
52
14
13
1
Table 3.
Pin
Pin description for VFQFPN52
Name
STBY
Type
Description
Standby (active high)
1
2
3
4
5
6
7
Digital input
Analog input
Analog I/O
Analog I/O
Supply
INL
ADC left channel line input or microphone input
ADC right channel line input
ADC microphone bias voltage
ADC analog supply
INR
VBIAS
AVDD
VHI
Analog input
Analog input
ADC high reference voltage
ADC low reference voltage
VLO
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Doc ID 13095 Rev 3
STA529
Connection diagrams and pin descriptions
Table 3.
Pin
Pin description for VFQFPN52 (continued)
Name Type
AGND Ground
Description
8
ADC analog ground
9
VCM
Analog I/O
ADC Common mode voltage
Reset (active low)
10
RST_N
Digital input
CLKOUT /
PWM2B
11
Digital output
Buffered clock output / PWM2B FFX
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND1
Ground
Digital ground
VDD1
Supply
Digital supply
MUTE
Digital input
Supply
Mute (active high)
VCC1A
OUT1A
GND1A
GND1B
OUT1B
VCC1B
VCC2B
OUT2B
GND2B
GND2A
OUT2A
VCC2A
GND33
GNDIO1
VDDIO1
VCC33
Channel 1 half-bridge A power supply
Channel 1 half-bridge A output
Channel 1 half-bridge A power ground
Channel 1 half-bridge B power ground
Channel 1 half-bridge B output
Channel 1 half-bridge B power supply
Channel 2 half-bridge B power supply
Channel 2 half-bridge B output
Channel 2 half-bridge B power ground
Channel 2 half-bridge A power ground
Channel 2 half-bridge A output
Channel 2 half-bridge A power supply
Pre-driver ground
Analog output
Ground
Ground
Analog output
Supply
Supply
Analog output
Ground
Ground
Analog output
Supply
Ground
Ground
I/O ring ground
Supply
I/O ring supply
Supply
Pre-driver supply
POWERFAULT /
EAPD
Power fault signal (active high) / external audio power
down signal
31
Digital output
32
33
34
35
TM
Digital input
Digital input
Digital input
Digital I/O
Test mode (active high)
I2C disable pin (active high)
I2C serial clock
I2CDIS
SCL
SDA
I2C serial data
Master clock input selector:
36
SELCLK33
Digital input
Digital input
0: XTI selected
1: MCLK33 selected
37
38
MCLK33
XTI
Master clock input 3.3-V capable
Crystal input or master clock input
Digital input
1.8V
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Connection diagrams and pin descriptions
STA529
Table 3.
Pin
Pin description for VFQFPN52 (continued)
Name
Type
Description
Digital output
1.8V
39
XTO
FILT
Crystal output
40
41
42
43
44
45
Analog I/O
Ground
PLL loop filter terminal
PLL analog ground
PLL analog supply
Digital ground
GNDPLL
VDDPLL
GND2
Supply
Ground
VDD2
Supply
Digital supply
SDATAI
Digital input
Input serial audio interface data
SDATAO /
PWM2A
46
47
48
Digital output
Digital I/O
Output serial audio interface data / PWM2A FFX
Input serial audio interface L/R-clock
LRCLKI
LRCLKO /
PWM1B
Output serial audio interface L/R-clock
(volume increases when I2CDIS = 1) / PWM1B FFX
Digital I/O
49
50
51
GNDIO2
VDDIO2
BICLKI
Ground
Supply
I/O ring ground
I/O ring supply
Digital I/O
Input serial audio interface bit-clock
BICLKO /
PWM1A
Output serial audio interface bit-clock
(volume decreases when I2CDIS = 1) / PWM1A FFX
52
Digital I/O
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STA529
Electrical and thermal specifications
3
Electrical and thermal specifications
3.1
Thermal data
Table 4.
Device
Thermal data
Parameter
Min
Typ
40
22
Max
Unit
TFBGA48
Thermal resistance junction to ambient
-
-
-
-
°C/W
°C/W
VFQFPN52 Thermal resistance junction to ambient
3.2
Absolute maximum ratings
Table 5.
Absolute maximum ratings
Description
Pin/symbol
Min
Max
Unit
VDD
VDD1
VDD2
Digital supply voltage
-0.5
+2.5
V
AVDD
ADC supply voltage
-0.5
-0.5
+4
V
V
VDDPLL
PLL analog supply voltage
+2.5
VCC1A
VCC1B
VCC2A
VCC2B
Power stage supply voltage
-0.5
+4
V
VCC33
VDDIO
TSTG
TJ
Pre-driver supply
-0.5
-0.5
-40
-40
+4
V
Digital I/O supply
+4
V
Storage temperature
Junction temperature
150
150
oC
oC
Note:
All grounds must be within 0.3 V of each other.
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Electrical and thermal specifications
STA529
3.3
Recommended operating conditions
Table 6.
Symbol
Recommended operating conditions
Parameter
Min
Typ
Max
Unit
VDD
VDD1
VDD2
Digital supply voltage
1.55
1.80
1.95
V
AVDD
ADC supply voltage
1.8
3.3
3.6
V
V
VDDPLL
PLL analog supply voltage
1.55
1.80
1.95
VCC1A
VCC1B
VCC2A
VCC2B
Power stage supply voltage
1.8
3.0
3.3
V
Pre-driver supply
(must be at same level as VCC1A/1B/2A/2B)
VCC33
VDDIO
1.8
1.8
3.0
3.0
3.3
3.6
V
V
Power supply for I/Os
GND1,
GND2,
GND33
Channel 1 and 2 power ground, pre-driver ground
-
0
-
V
GNDIO
VIH
Ground for I/Os
-
0
-
-
V
3.3-V supply
2.0
-
-
V
VIL
3.3-V supply
-
0.8
-
V
VHYST
TAMB
Schmitt trigger hysteresis (VDDIO)
Ambient operating temperature
0.4
-40
-
V
-
85
oC
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STA529
Electrical and thermal specifications
3.4
Electrical characteristics
The electrical specifications in Table 7 below are given for operation under the
recommended conditions listed in Table 6. Unless otherwise specified, LRCLKI frequency
(fs) = 48 kHz, input frequency = 1 kHz, and R
= 32 Ω.
LOAD
Table 7.
Symbol
Electrical characteristics
Parameter
Test conditions
Min
Typ
90
Max
Unit
Eff
Output power efficiency
-
-
-
-
-
%
Output stage N/PMOS on-
resistance
Rdson
250
1.3
0.7
15
380
mΩ
µA
Logic power supply current at
standby
IstbyL
IstbyP
IddL
-
-
-
-
-
-
-
-
-
Bridges power supply current in
standby
µA
Logic power supply current at
operating
mA
Bridges power supply current at
operating
IddP
Tds
Tdd
-
-
-
-
-
-
0.5
1
-
-
-
mA
ns
Low current dead time (static)
High current dead time
(dynamic)
2.5
ns
Tr
Tf
Rise time
Fall time
-
-
-
-
3
3
-
-
ns
ns
Dynamic range
A-weighted
DNR
SNR
Speaker mode
Speaker mode
-
-
-
-
-
-
96
-
-
-
-
-
-
dB
dB
%
Signal-to-noise ratio (A-
weighted)
92
0 dBFS input,
8 Ω speakers
0.1
0.05
0.1
0.05
-6 dBFS input,
8 Ω speakers
%
THDN
Total harmonic distortion
0 dBFS input,
32 Ω headphones
%
-6 dBFS input,
32 Ω headphones
%
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Electrical and thermal specifications
STA529
The following tables give the output power for 1% and 10% THD levels for headphones and
speakers.
Table 8.
Load power at 1% distortion in headphone mode
Load (Ω) P (mW) at 1.8 V
P (mW) at 3.3 V
P (mW) at 3.3 V
P (mW) at 3.3 V
16
32
20
10
65
32
Table 9.
Load power at 10% distortion in headphone mode
Load (Ω) P (mW) at 1.8 V
16
32
25
13
85
42
Table 10. Load power at 1% distortion in speaker mode
Load (Ω) P (mW) at 1.8 V
4
310
166
86
860
560
290
147
8
16
32
43
Table 11. Load power at 10% distortion in speaker mode
Load (Ω) P (mW) at 1.8 V
P (mW) at 3.3 V
4
400
216
112
57
1100
720
380
200
8
16
32
3.5
Lock time
Table 12 gives the typical lock time of the PLL using the suggested loop filter with 1.8 V
o
supply and 30 C junction temperature.
Table 12. PLL lock time
Parameter
Value
Lock time
200 µs
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STA529
Input clock
4
Input clock
4.1
SELCLK33
In STA529 the oversampling clock comes from MCLK33 or from pin XTI. The selection is
done by applying the appropriate voltage to pin SELCLK33. If SELCLK33 is logical 1 then
MCLK33 is selected, otherwise XTI is selected.
If an external crystal is used, SELCLK33 pin must be connected to GND and the suggested
circuit shown below should be used.
Figure 4.
Circuit for crystal drive
STA529
External
components
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Digital processing
STA529
5
Digital processing
The STA529 processor block is a digital block providing two channels of audio processing
and channel-mapping capability.
5.1
5.2
Signal processing flow
2
2
I S or stereo ADC data can be selected. The I S frequency range is 8 kHz to 192 kHz. The
ADC sampling frequency can be selected between 8 kHz and 48 kHz.
I2C interface disable
When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low
to change certain parameters of operation.
●
●
●
●
SDA = 0: FFX input comes from ADC
SDA = 1: FFX input comes from digital audio interface
SCL = 0: binary output mode (binary soft start/stop enabled)
SCL = 1: phase shift output mode
LRCLKO = 0: no volume change
LRCLKO = 1: channel volume up on both channel
BICLKO = 0: no volume change
BICLKO = 1: channel volume down on both xchannel.
At power up, the channel volume is set to -60 dB. When holding pin LRCLKO = 1 and pin
BICLKO = 1 simultaneously, the channel volume is set to 0 dB. A high pulse on pin LRCLKO
causes a channel volume change of +0.5 dB and a high pulse on pin BICLKO causes a
channel volume change of -0.5 dB.
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STA529
Digital processing
5.3
Volume control and gain
The volume control structure of the STA529 consists of individual volume registers for each
channel and a master volume register that provides an offset to each channel’s volume
setting. The individual channel volumes are adjustable in 0.5-dB steps from +36 dB
to -91.5 dB. As an example, if register LVOL = 0x00 or +36 dB and register MVOL = 0x18
or -12 dB, then the total gain for the left channel is +24 dB.
When the mute bit is set to 1, all channels are muted. The volume control provides a soft
mute with the volume ramping down to mute in 4096 samples from the maximum volume
setting at the internal processing rate (around 48 kHz).
Table 13. Master volume offset as a function of register MVOL
MVOL[7:0]
Volume offset from channel value
0x00
0x01
0x02
…
0 dB
-0.5 dB
-1dB
…
0x78
…
-60 dB
…
0xFE
0xFF
-105 dB
Hard master mute
Table 14. Channel volume as a function of registers LVOL and RVOL
LVOL/RVOL[7:0] Volume
0x00
0x01
0x02
…
+36 dB
+35.5 dB
+35 dB
…
0x47
0x48
0x49
…
+0.5 dB
0 dB
-0.5 dB
…
…
…
0xFF
-91.5 dB
Doc ID 13095 Rev 3
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PLL
STA529
6
PLL
Figure 5 shows the main components of the PLL.
Figure 5.
PLL block diagram
INFIN
LOCKP
CLKIN
IDF
Input frequency
divider
Lock detect
FBCLK
FILT
INFIN
LF
VCONT
Phase
frequency
divider
Charge
pump and
loop filter
Buffer
(PFD)
INFOUT
FBCLK
REFOUT
VCO
f
Loop frequency divider
VCO
STRB
STRB_BYPASS
FRAC_CTRL
Output
frequency
divider
PHI
Fractional controller
DITHER_DISABLE
FRAC_INPUT
NDIV
6.1
Functional description
Phase/frequency detector
The phase/frequency detector (PFD) compares the phase difference between the
corresponding rising edges of INFIN and FBCLK, (clock output from the loop frequency
divider) by generating voltage pulses with widths proportional to the input phase error.
Charge pump and loop filter
This block converts the voltage pulses from the phase/frequency detector to current pulses
which charge the loop filter and generate the control voltage for the voltage-controlled
oscillator. The loop filter is placed external to the PLL on pin FILT.
Voltage controlled oscillator
The voltage controlled oscillator (VCO) is the oscillator inside the PLL. It produces a
frequency (f
) proportional to the input control voltage.
VCO
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STA529
PLL
Input frequency divider
This frequency divider divides the PLL input clock CLKIN by a factor called the input division
factor (IDF) to generate the PFD input frequency INFIN.
Loop frequency divider
This frequency divider is present within the PLL for dividing f
by a factor called the loop
VCO
division factor (LDF). The output of this block is clock FBCLK.
Output frequency divider
The output frequency divider divides f
by the output division factor (ODF) to produce the
VCO
output clock PHI and the clock to the core. In the STA529, ODF = 2 and cannot be
reconfigured.
Lock-detect circuit
The output of this block (signal LOCKP) is asserted high when the PLL enters the state of
Coarse Lock in which the output frequency is within 10%, approximately, of the desired
frequency. LOCKP is refreshed every 32 cycles of clock INFIN. The generated value is
based on the result of comparing the number of FBCLK cycles in a window of 14 INFIN
cycles. The different cases generated after comparison are as follows.
●
●
●
If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number
of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP
stays at 0.
If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number
of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17,
otherwise LOCKP stays at 1.
If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP
stays at 1. In this case, the PLL is unlocked.
PLL filter
Figure 6 below shows the PLL filter circuit. Recommended values are R1 = 12.5 kΩ,
C1 = 250 pF and C2 = 82 pF.
Figure 6.
PLL filter circuit
Vc
R1
C1
C2
Ground
Table 12 on page 16 gives a typical lock time value for the PLL.
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PLL
STA529
6.2
Configuration examples
The STA529 PLL can be configured in two ways:
●
default startup configuration
direct PLL programming
●
The default startup configuration reads the device defaults. With this configuration, it is not
necessary to program the PLL dividers directly as preset values are used. In this mode, the
oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256.
The direct PLL programming bypasses the automatic presets allowing direct programming
of the PLL dividers.
The output PLL frequency can be determined by the following equations.
Output division factor:
ODF = 2.
Relation between input and output clock frequency:
f
= f
/ IDF.
INFIN
XTI
If register bit PLLCFG0.FRAC_CTRL = 1
16
17
f
f
= f
* (LDF + FRACT / 2 + 1 / 2 )
VCO
INFIN
= f
/ ODF.
VCO
PHI
17
When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/2 factor is not in the
multiplication. This is recommended in order to keep register bit
PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output
clock spectrum.
If register bit PLLCFG0.FRAC_CTRL = 0, then:
f
f
= f
* LDF
VCO
INFIN
= f
/ ODF.
VCO
PHI
In the above equations:
FRACT = decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0]
IDF = input division factor
LDF = loop division factor
ODF = output division factor = 2
f
f
f
f
= INFIN frequency
INFIN
= XTI frequency
XTI
= VCO frequency
VCO
= frequency of the PLL output clock.
PHI
When selecting the values for IDF, LDF and FRACT, ensure that the following limits are
maintained:
2.048 MHz < f
2.048 MHz < f
< 49.152 MHz
XTI
< 16.384 MHz
< 98.304 MHz
INFIN
65.536 MHz < f
VCO
There are also some additional constraints on IDF and LDF. IDF should be greater than 0,
LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1.
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STA529
PLL
When automatic settings are not used, the PLL must be configured to generate an internal
frequency, f , of N * fs, where fs is the frequency of pin LRCLKI. Values for N are given in
PHI
Table 15.
Table 15. Oversampling table
fs (kHz)
N
fPHI (MHz)
8
4096
4096
4096
2048
2048
2048
1024
1024
1024
512
32.768
45.1584
49.152
32.768
45.1584
49.152
32.768
45.1584
49.152
32.768
45.1584
49.152
32.768
45.1584
49.152
11.025
12
16
22.05
24
32
44.1
48
64
88.2
96
512
512
128
176.4
192
256
256
256
Example 1
f
= 13 MHz and fs = 44.1 kHz
XTI
IDF should be equal to 3 otherwise LDF becomes less than 8 (FRAC_CTRL must be 1):
LDF = floor(45.1584 / (13 / IDF)) = 10
16
FRACT = round([(45.1584 / (13 / IDF)) - floor(45.1584 / (13 / IDF))] * 2 ) = 27602.
where:
floor means rounded down and
round means rounded to nearest integer.
Using the above configuration, the system clock is 45.15841675 MHz, the approximate
static error is 16 Hz (that is, 0.5 ppm).
Example 2
f
= 19.2 MHz and fs = 48 kHz
XTI
IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1):
LDF = floor(49.152 / (19.2 / IDF)) = 10
16
FRACT = round([(49.152 / (19.2 / IDF)) - floor(49.152 / (19.2 / IDF))] * 2 ) = 15728.
Using the above configuration, the system clock is 49.151953125 MHz, the approximate
static error is 47 Hz (that is, 1 ppm).
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PLL
STA529
6.3
Set fractional PLL
The following procedure is mandatory to configure the fractional PLL:
1. Set bit D7 reg 0x18 ( PLL_BYP_UNL) to "1"
2. Write reg 0x17 (PLLCFG3)
3. Write reg 0x14 (PLLCFG0)
4. Write reg 0x15 (PLLCFG1)
5. Write reg 0x16 (PLLCFG2)
6. Set bit D7 reg 0x18 ( PLL_BYP_UNL) to "0"
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STA529
ADC
7
ADC
7.1
ADC performance values
Table 16. Programmable gain performance
Parameter
Min
Typ
92
Max
Unit
dB
Dynamic range 1 kHz, A-weighted (3.3 V supply)
Dynamic range 1 kHz, A-weighted (1.8 V supply)
SNDR 1 kHz, A-weighted (3.3 V supply)
SNDR 1 kHz, A-weighted (1.8 V supply)
THD 1 kHz (-1 dB input) (3.3 V supply)
THD 1 kHz (-1 dB input) (1.8 V supply)
Cross talk (3.3 V supply)
84
dB
dB
dB
dB
dB
dB
dB
92
84
-85
-75
-80
-60
Cross talk (1.8 V supply)
7.2
Functional description
The STA529 analog input is provided through a low-power, low-voltage, 16-bit stereo audio
analog-to-digital converter front end designed for audio applications. It includes a
programmable gain amplifier, anti-aliasing filter, low-noise microphone biasing circuit,
third-order MASH2-1 delta-sigma modulator, digital decimating filter and a first-order
DC-removal filter.
The ADC works in the microphone input (mic-in) mode and in the line-input mode. If the line
input mode is selected, the ADC is configured in stereo and all conversion channels are
active.
If the microphone input mode is selected, the ADC is configured in mono. The mono
channel is routed through the left conversion path, and the right conversion path is kept in
power-down mode to minimize power consumption. A programmable gain amplifier (PGA) is
available in mic-in mode, making it possible to amplify the signal from 0 to +42 dB in steps of
6 dB.
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ADC
STA529
7.2.1
Digital filter characteristics
Table 17. Digital filter characteristics
Parameter
Typical
Unit
Pass band
0.4535 * fs
kHz
Pass-band ripple:
Fs mode
0.08 at 44.1 kHz
0.08 at 22.05 kHz
0.08 at 11.025 kHz
dB
dB
dB
Fs_by_2 mode
Fs_by_4 mode
Stop-band attenuation:
Fs mode
45 at 44.1 kHz
45 at 22.05 kHz
45 at 11.025 kHz
dB
dB
dB
Fs_by_2 mode
Fs_by_4 mode
Group delay:
Fs mode
0.4 at 32 kHz
0.7 at 16 kHz
1.4 at 8 kHz
ms
ms
ms
Fs_by_2 mode
Fs_by_4 mode
7.2.2
High-pass filter characteristics
Table 18. High-pass filter characteristics
Parameter
Typical
Unit
Frequency response:
-3 dB
7
Hz
Hz
-0.08 dB
50
Phase deviation at 20 Hz
Passband ripple
19.35
0.08
degree
dB
7.2.3
Programmable gain amplifier (PGA)
The PGA is available in mic-in mode only. The input signal can be amplified from 0 to 42 dB
in 6-dB steps via bits PGA of register ADCCFG on page 49.
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STA529
ADC
7.3
Applications scheme
Figure 7.
Diagram of input coupling and supply decoupling
C9
AC coupled
C1, C2, C3, C4 = 10 nF
INL
(These capacitors must be
placed very close to their
respective IC pins)
DC coupled
C0
AC coupled
DC coupled
INR
C5, C6, C7 = 33 µF
(Low ESR and ESL
capacitors are
recommended)
3 V, 3 A supply
AVDD
AGND
C5
C6
C1
C2
VSSA
R1
C8 = 10 µF
C9, C0 = 1 µF
R1 = 500 Ω
VHI
VSSA
VLO
VCM
VSSA plane must be
different from other
ground plane
C7
C8
C3
C4
3 V, 3 A must be a
low-noise supply and
separate from
other supplies
VBIAS
7.4
Configuration examples
The ADC sampling frequency can be selected from three values:
●
●
●
normal (from 32 kHz to 48 kHz)
low (from 16 kHz to 24 kHz)
very-low (from 8 kHz to 12 kHz)
The setting is done through bits ADC_FS_RANGE of register MISC on page 50. For all
other settings register ADCCFG on page 49 is used.
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Driver configuration
STA529
8
Driver configuration
A driver configuration is available that allows PWM commands to be used on an external
power device. For this purpose, the output serial audio interface is disabled and the
respective pins have an alternative name and a new function, as shown in Table 19.
Table 19. Pin functions in driver-configuration mode
Pin
Alternative pin name and function
BICLKO
LRCLKO
SDATAO
CLKOUT
PWM1A (external bridge PWM command for output 1A)
PWM1B (external bridge PWM command for output 1B)
PWM2A (external bridge PWM command for output 2A)
PWM2B (external bridge PWM command for output 2B)
EADP (external audio power-down signal)
POWERFAULT
The driver configuration is selected with the two programmable registers, PWMINT1 = 0x93
and PWMINT2 = 0x81, on page 51.
8.1
I2S bypass
2
A configuration is available which allows the passing of the I S input signal straight to the
2
I S output signal.
This configuration is set using two programmable registers PWMINT1 = 0x93 and
PWMINT2 = 0x80.
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Serial audio interface
9
Serial audio interface
The serial-to-parallel interface and the parallel-to-serial interface can have different
sampling rates.
The following terms are used in this section:
●
BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change
synchronously with BITCLK active edges. The active edge can be configured as a
rising or falling edge via register programming.
●
BICLK strobe edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO should be stable near
BICLK strobe edges, the slave device is able to use strobe edges to latch serial data
internally.
9.1
Master mode
In this mode, pins BICLKI/BICLKO and pins LRCLKI/LRCLKO are configured as outputs.
Figure 8.
Master mode
BICLKI/
BICLKO
tDL
LRCLKI/
LRCLKO
tDDA
SDATAO
SDATAI
tDST
tDHT
Table 20. Master mode
Symbol
Parameter
Min
Typ
Max
10
15
Unit
ns
LRCLKI/LRCLKO propagation delay from BICLK active
edge
tDL
0
tDDA
tDST
tDHT
SDATAO propagation delay from BICLKI/O active edge 0
ns
ns
ns
SDATAI setup time to BICLKI/O strobing edge
SDATAI hold time from BICLKI/O strobing edge
10
10
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Serial audio interface
STA529
9.2
Slave mode
In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs.
Figure 9.
Slave mode
tBCH
tBCL
BICLKI/
BICLKO
tBCY
LRCLKI/
LRCLKO
tDS
tLRH
tLRSU
SDATAI
tDH
SDATAO
tDD
Table 21. Slave mode
Symbol
Parameter
Min
50
Typ
Max
Unit
tBCY
tBCH
tBCL
tLRSU
tLRH
tDS
BICLK cycle time
ns
ns
ns
ns
ns
ns
ns
ns
BICLK pulse width high
BICLK pulse width low
20
20
10
10
25
25
0
LRCLKI/LRCLKO setup time to BICLK strobing edge
LRCLKI/LRCLKO hold time to BICLK strobing edge
SDATAO setup time to BICLK strobing edge
tDH
SDATAO hold time to BICLK strobing edge
tDD
SDATAI propagation delay from BICLK active edge
10
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Serial audio interface
9.3
Serial formats
Different audio formats are supported in both master and slave modes. Clock and data
configurations can be customized to match most of the serial audio protocols available on
the market.
Data length can be customized to 8, 16, 24 or 32 bits.
Figure 10. Right justified
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
n-1
n
n
n-1
1
2 3
1 2 3
Figure 11. Left justified
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
n-1
n
n
n-1
1
2 3
1 2 3
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Serial audio interface
STA529
9.3.1
DSP
Figure 12. DSP
LRCLKI/
LRCLKO
BICLKI/
BICLKO
Left
Right
SDATAI/
SDATAO
n-1
n
1 2 3
n
1
2 3
n-1
2
9.3.2
I S
2
Figure 13. I S
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
n
n
n
1
2 3
n-1
1 2 3
-1
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Serial audio interface
9.3.3
PCM/IF (non-delayed mode)
●
●
MSB first
16-bit data
Figure 14. PCM/IF (non-delayed mode)
Any width
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
n
n
1
2 3
-1
9.3.4
PCM/IF (delayed mode)
●
●
MSB first
16-bit data
Figure 15. PCM/IF (delayed mode)
LRCLKI/
LRCLKO
BICLKI/
BICLKO
SDATAI/
SDATAO
n
n
1
2 3
-1
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2
I C interface
STA529
2
10
I C interface
10.1
Data transition and change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a start or stop condition.
10.2
10.3
10.4
10.5
Start condition
A start condition is identified by a high to low transition of the data bus SDA signal while the
clock signal SCL is stable in the high state. A start condition must precede any command for
data transfer.
Stop condition
A stop condition is identified by low to high transition of the data bus SDA signal while the
clock signal SCL is stable in the high state. A stop condition terminates communication
between the STA529 and the master bus.
Data input
During data input, the STA529 samples the SDA signal on the rising edge of clock SCL. For
correct device operation the SDA signal must be stable during the rising edge of the clock
and the data can change only when the SCL line is low.
Device addressing
To start communication between the master and the STA529, the master must initiate with a
start condition. Following this, the master sends 8 bits (MSB first) on the SDA line
corresponding to the device select address and read or write mode.
2
The 7 most significant bits are the device address identifiers, corresponding to the I C bus
2
definition. In the STA529, the I C interface has the device address 0x34.
The 8th bit (LSB) identifies the read or write operation (R/W). It is set to 1 in read mode and
0 in write mode.
After the start condition, the STA529 waits for its device address on SDA. When a match is
found, it acknowledges the identification on SDA during the 9th bit time. The byte following
the device identification byte is the internal space address.
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STA529
I C interface
10.6
Write operation
Following the start condition the master sends a device select code with the R/W bit set to 0.
The STA529 acknowledges this and then writes to the byte of the internal address. After
receiving the internal byte address, the STA529 responds with an acknowledgement.
10.6.1
10.6.2
Byte write
In the byte-write mode the master sends one data byte. This is acknowledged by the
STA529. The master then terminates the transfer by generating a stop condition.
Multi-byte write
The multi-byte write modes can start from any internal address. The master generates a
stop condition which terminates the transfer.
10.7
Read operation
10.7.1
Current address byte read
Following the start condition the master sends a device select code with bit R/W set to 1.
The STA529 acknowledges this and then responds by sending one byte of data. The master
then terminates the transfer by generating a stop condition.
10.7.2
10.7.3
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA529. The master acknowledges each data
byte read and then generates a stop condition terminating the transfer.
Random address byte read
Following the start condition the master sends a device select code with bit R/W set to 0.
The STA529 acknowledges this and then the master writes the internal address byte. After
receiving the internal byte address, the STA529 again responds with an acknowledgement.
The master then initiates another start condition and sends the device select code with bit
R/W set to 1. The STA529 acknowledges this and then responds by sending one byte of
data. The master then terminates the transfer by generating a stop condition.
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2
I C interface
STA529
10.7.4
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are
read from sequential addresses within the STA529. The master acknowledges each data
byte read and then generates a stop condition terminating the transfer.
2
Figure 16. I C write operations
ACK
ACK
ACK
ACK
ACK
Byte
Write
R/W
Sub address
Sub address
Dev address
Data in
Data in
Stop
Start
Start
ACK
ACK
Multibyte
Write
Stop
R/W
Data in
Dev address
2
Figure 17. I C read operations
ACK
No ACK
Current
address
read
Stop
ACK
Data
Dev address
R/W
ACK
Start
ACK
No ACK
Stop
Random
address
read
Start Dev address
Start Dev address
Start Dev address
R/W
Sub address
Start
Dev address
R/W
Data
Data
ACK
ACK
ACK
No ACK
Stop
Sequential
current
read
Data
R/W=High
ACK
Data
ACK
ACK
ACK
Sequential
random
read
R/W
Sub address
Start
Dev address
Data
R/W
ACK
Data
Data
No ACK
Stop
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STA529
Registers
11
Registers
This section describes the set-up register used in the device.
11.1
Summary
Table 22. Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SOFT_
VOL_ON
BIN_SOFT
START
MUTE
POW_STBY
TIM_SOFT_VOL[3:0]
0x00
FFXCFG0
FFXCFG1
MUTE_ON_
INVALID
L1_R2
PWM_MODE[1:0]
PWM_SHIFT[1:0]
Reserved
0x01
SET_VOL_MASTER[7:0]
SET_VOL_LEFT[7:0]
SET_VOL_RIGHT[7:0]
TIM_TS_FAULT[15:8]
TIM_TS_FAULT[7:0]
0x02
0x03
0x04
0x05
0x06
0x07
0x08
MVOL
LVOL
RVOL
TTF0
TTF1
TTP0
TTP1
TIM_TS_POWUP[15:8]
TIM_TS_POWUP[7:0]
BICLK_
STRB
LRCLK_
LEFT
SHARE_
BILR
MASTER_
MODE
MSB_FIRST
DATA_FORMAT[2:0]
MAP_L[1:0]
DATA_FORMAT[2:0]
MAP_L[1:0]
0x0A
0x0B
0x0C
0x0D
0x14
S2PCFG0
S2PCFG1
P2SCFG0
P2SCFG1
PLLCFG0
PDATA_LENGTH[1:0]
BICLK_OS[1:0]
MAP_R[1:0]
BICLK_
STRB
LRCLK_
LEFT
SDATAO_
ACT
MASTER_
MODE
MSB_FIRST
PDATA_LENGTH[1:0]
BICLK_OS[1:0]
DITHER_DISABLE[1:0]
FRAC_INPUT[15:8]
FRAC_INPUT[7:0]
MAP_R[1:0]
PLL_DIREC
T_PROG
FRAC_
CTRL
IDF[3:0]
0x15
0x16
PLLCFG1
PLLCFG2
STRB_
BYPASS
STRB
NDIV[5:0]
0x17
0x18
0x19
0x1E
0x1F
0x20
PLLCFG3
PLLPFE
PLLST
PLL_
BYP_ UNL
RESET_
FAULT
BICLK2PLL PLL_PWDN
PFE1A
INSEL
PFE1B
STBY
PFE2A
PFE2B
PLL_
UNLOCK
PLL_PWD_
STATE
PLL_BYP_
STATE
Reserved
BYPASS_
CALIB
PGA[2:0]
CLKENBL
Reserved
ADCCFG
CKOCFG
MISC
CLKOUT_
DIS
CLKOUT_SEL[1:0]
Reserved
P2P_IN_
ADC
CORE_
CLKENBL
OSC_DIS
P2P_FS_RANGE[2:0]
ADC_FS_RANGE[1:0]
Reserved
Reserved
0x21
0x22
PADST0
PADST1
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Registers
STA529
Table 22. Register summary (continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INVALID_
INP_FBK
MUTE_
INT_FBK
Reserved
Reserved
0x23
FFXST
Reserved
0x28
0x29
0x2A
0x2B
0x2D
0x2E
BISTRUN
BISTST0
BISTST1
BISTST2
PWMINT1
PWMINT2
Reserved
Reserved
Reserved
PWM_INT[15:8]
PWM_INT[7:0]
POWER
DOWN
POW_
TRISTATE
POW_
FAULT1A
POW_
FAULT1B
POW_
FAULT2A
POW_
FAULT2B
Reserved
0x32
POWST
All other registers not mentioned here are reserved and must not be used.
11.2
General registers
FFXCFG0
FFX configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BIN_
SOFTSTART
MUTE
POW_STBY
SOFT_VOL_ON
TIM_SOFT_VOL[3:0]
Address:
Type:
0x00
R/W
No
Buffer:
Reset:
0x75
Description:
7 MUTE:
0: standard operation (default)
1: FFX output is zero (muted condition)
6 POW_STBY:
0: FFX bridge is in power-up mode
1: FFX bridge is in standby mode (default)
5 SOFT_VOL_ON:
0: smooth transition not active
1: smooth transition when changing volume control (default)
4 BIN_SOFTSTART:
Reserved (1: default)
3:0 TIM_SOFT_VOL: volume control time step for any 0.5 dB volume change
Time is (2TIM_SOFT_VOL) * 20.83 µs
Default value: 0101. This value means 666.66 µs
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Registers
FFXCFG1
Configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RES
Bit 0
MUTE_ON_
INVALID
L1_R2
PWM_MODE[1:0]
PWM_SHIFT[1:0]
RES
Address:
Type:
0x01
R/W
No
Buffer:
Reset:
0xF8
Description:
7 L1_R2: channel mapping:
0: right channel is mapped to output channel 1 and left channel is mapped to output
channel 2
1: left channel is mapped to output channel 1 and right channel is mapped to output
channel 2 (default)
6 MUTE_ON_ INVALID: mutes PWM outputs if invalid digital data is received:
0: outputs are not muted
1: outputs are muted (default)
5:4 PWM_MODE[1:0]:
00: binary (output B is opposite of output A)
01: binary headphones (output B is 50% duty cycle)
10: reserved, do not use
11: phase shift (default)
3:2 PWM_SHIFT[1:0]:
10: default
PWM period-shift between channels 1 and 2
Value is N * 90o
Default is 180o
1:0 Reserved (00: default)
MVOL
Master volume control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SET_VOL_MASTER[7:0]
Address:
Type:
0x02
R/W
No
Buffer:
Reset:
0x00
Description:
7:0 SET_VOL_MASTER[7:0]: master volume control:
From 0 dB to -127.5 dB in 0.5-dB steps
Default value (0x00) corresponds to 0 dB
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Registers
STA529
LVOL
Left channel volume control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SET_VOL_LEFT[7:0]
Address:
Type:
0x03
R/W
No
Buffer:
Reset:
0x48
Description:
7:0 SET_VOL_LEFT[7:0]: left channel volume control:
Left channel volume control (from +36 dB to -91.5 dB in 0.5-dB steps)
Default value (0x48) corresponds to 0 dB
RVOL
Right channel volume control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SET_VOL_RIGHT[7:0]
Address:
Type:
0x04
R/W
No
Buffer:
Reset:
0x48
Description:
7:0 SET_VOL_RIGHT[7:0]: right channel volume control:
Right channel volume control (from +36 dB to -91.5 dB in 0.5-dB steps)
Default value (0x00) corresponds to 0 dB
TTF0
Tristate time after fault (MSBs)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM_TS_FAULT[15:8]
Address:
Type:
0x05
R/W
No
Buffer:
Reset:
0x00
Description:
7:0 MSBs of TIM_TS_FAULT[15:0]:
See register TTF1.
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Registers
TTF1
Tri-state time after fault (LSBs)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM_TS_FAULT[7:0]
Address:
Type:
0x06
R/W
No
Buffer:
Reset:
0x02
Description:
7:0 LSBs of TIM_TS_FAULT[15:0]: time in which power is held in tristate mode after a fault
signal:
Time is TIM_TS_FAULT * 83.33 µs.
Default value (0x0002) corresponds to 166.66 µs tristate time after fault
TTP0
Tri-state time after power-up (MSBs)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM_TS_POWUP[15:8]
Address:
Type:
0x07
R/W
No
Buffer:
Reset:
0x00
Description:
7:0 MSBs of TIM_TS_POWUP[15:0]:
See register TTP1 below.
TTP1
Tristate time after power-up (LSBs)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM_TS_POWUP[7:0]
Address:
Type:
0x08
R/W
No
Buffer:
Reset:
0x02
Description:
7:0 LSBs of TIM_TS_POWUP[15:0]: time in which power is held in tri-state mode after a
power-up signal:
Time is TIM_TS_POWUP * 83.33 µs
Default value (0x0002) corresponds to 166.66 µs tristate time after power-up
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Registers
STA529
S2PCFG0
Serial to parallel audio interface configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MASTER_
MODE
BICLK_STRB
LRCLK_LEFT
SHARE_BILR
MSB_FIRST
DATA_FORMAT[2:0]
Address:
Type:
0x0A
R/W
No
Buffer:
Reset:
0xD2
Description:
7 BICLK_STRB:
0: bit clock strobe edge is falling edge, bit clock active edge is rising edge
1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default)
6 LRCLK_LEFT:
0: left/right clock is low for left channel, high for right channel
1: left/right clock is high for left channel, low for right channel (default)
5 SHARE_BILR:
0: default
1: left/right clock and bit clock are shared between serial to parallel interface and parallel to
serial interface, BICLKI and LRCLKI are used
4 MSB_FIRST:
0: LSB first
1: MSB first (default)
3:1 DATA_FORMAT[2:0]: serial interface protocol format:
000: left Justified
001: I2S (default)
010: right justified
100: PCM no delay
101: PCM delay
111: DSP
0 MASTER_MODE:
0: SAI OUTis in slave mode (default)
1: SAI OUTis in master mode
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Registers
S2PCFG1
Serial-to-parallel audio interface configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PDATA_LENGTH[1:0]
BICLK_OS[1:0]
MAP_L[1:0]
MAP_R[1:0]
Address:
0x0B
R/W
No
Type:
Buffer:
Reset:
0x91
Description:
7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length:
Length is (N+1) * 8 bit
Default (10) is 24 bit
5:4 BICLK_OS[1:0]: bit clock oversampling:
Value is (N+1) * 32 * fs (where fs = sampling frequency)
Default (01) is 64 fs
3:2 MAP_L[1:0]: left data-mapping slot:
Value is nth slot
Default (00) is slot 0
1:0 MAP_R[1:0]: right data-mapping slot:
Value is nth slot
Default (01) is slot 1
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Registers
STA529
P2SCFG0
Parallel-to-serial audio interface configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MASTER_
MODE
BICLK_ STRB
LRCLK_LEFT
SDATAO_ACT
MSB_FIRST
DATA_FORMAT[2:0]
Address:
Type:
0x0C
R/W
No
Buffer:
Reset:
0xD3
Description:
7 BICLK_STRB: defines the bit clock edges:
0: strobe is falling edge, active edge is rising
1: strobe is rising edge, active edge is falling (default)
6 LRCLK_LEFT: defines the channel for the LR clock:
0: clock is low for left channel, high for right channel
1: clock is high for left channel, low for right channel (default)
5 SDATAO_ ACT: sets the behavior of pin SDATAO:
0: output is tristated when no data is sent (default)
1: output is never in tri-state (it is 0 when no data is sent)
4 MSB_FIRST: data alignment in the protocol for SDATAI and SDATAO:
0: LSB is the first bit
1: MSB is the first bit (default)
3:1 DATA_FORMAT[2:0]: serial interface protocol format:
000: left justified
001: I2S (default)
010: right justified
100: PCM no delay
101: PCM delay
111: DSP
0 MASTER_ MODE: selects serial interface master/slave mode:
0: slave
1: master (default)
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Registers
P2SCFG1
Parallel-to-serial audio interface configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PDATA_LENGTH[1:0]
BICLK_OS[1:0]
MAP_L[1:0]
MAP_R[1:0]
Address:
0x0D
R/W
No
Type:
Buffer:
Reset:
0x91
Description:
7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length:
Length is (PDATA_LENGTH+1) * 8 bit
Default (10) is 24 bits
5:4 BICLK_OS[1:0]: bit clock oversampling:
Value is (BICLK_OS+1) * 32 * fs
Default (01) is 64 fs
3:2 MAP_L[1:0]: left data-mapping slot:
Value is nth slot
Default (00) is slot0
1:0 MAP_R[1:0]: right channel data-mapping slot:
Value is nth slot
Default (01) is slot1
PLLCFG0
PLL configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL_DIRECT_
PROG
FRAC_CTRL
DITHER_DISABLE[1:0]
IDF[3:0]
Address:
Type:
0x14
R/W
No
Buffer:
Reset:
0x00
Description:
7 PLL_DIRECT_PROG: PLL programming:
0: default
1: PLL is programmed according to the PLLCFG register settings
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Registers
STA529
6 FRAC_CTRL:
0: default
1: PLL fractional-frequency synthesis is enabled
5:4 DITHER_DISABLE[1:0]:
00: default
1x: disables rectangular phase frequency divider dither input to fractional control
x1: disables triangular Phase Frequency Divider dither input to Fractional Control
The mentioned blocks are shown in Figure 5.
3:0 IDF[3:0]: PLL input division factor:
0000: IDF = 1 (default)
0001: IDF = 1
0010: IDF = 2
…
1111: IDF = 15
PLLCFG1
PLL configuration (MSBs)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FRAC_INPUT[15:8]
Address:
Type:
0x15
R/W
No
Buffer:
Reset:
0x00
Description:
7:0 FRAC_INPUT[15:8]: MSBs of FRAC_INPUT[15:0] used to set the fractional part of PLL
multiplication factor
PLLCFG2
PLL configuration (LSBs)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FRAC_INPUT[7:0]
Address:
Type:
0x16
R/W
No
Buffer:
Reset:
0x00
Description:
7:0 FRAC_INPUT[7:0]: LSBs of FRAC_INPUT[15:0] used to set the fractional part of PLL
multiplication factor
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Registers
PLLCFG3
PLL configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STRB
STRB_BYPASS
NDIV[5:0]
Address:
Type:
0x17
R/W
No
Buffer:
Reset:
0x00
Description:
7 STRB: asynchronous strobe input to the fractional controller:
0: default
6 STRB_BYPASS: standby bypass:
0: STRB signal is not bypassed (default)
1: STRB signal is bypassed
5:0 NDIV[5:0]: PLL multiplication factor (integral part) named as loop division factor:
0000 XX: LDF = NA
0001 00: LDF = NA
0001 01: LDF = 5
...
1101 11: LDF = 55
111X XX: LDF = NA
0000 00: default
PLLPFE
PLL/POP-free configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL_BYP_UNL
BICLK2PLL
PLL_PWDN
PFE1A
PFE1B
PFE2A
PFE2B
RESET_FAULT
Address:
Type:
0x18
R/W
No
Buffer:
Reset:
0x00
Description:
7 PLL_BYP_UNL: PLL bypass:
0: PLL is not bypassed (default)
1: PLL is bypassed when not locked
6 BICLK2PLL:
0: default
1: BICLKI is input to PLL
5 PLL_PWDN:
0: default
1: PLL is in power-down mode
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Registers
STA529
4 PFE1A:
0: default
1: POP-free resistances are connected to output 1A
3 PFE1B:
0: default
1: POP-free resistances are connected to output 1B
2 PFE2A:
0: default
1: POP-free resistances are connected to output 2A
1 PFE2B:
0: default
1: POP-free resistances are connected to output 2B
0 RESET_FAULT:
0: default
1: fault signal in the I2C register POWST is reset
PLLST
PLL status
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL_PWD_
STATE
PLL_BYP_
STATE
PLL_UNLOCK
Reserved
Address:
Type:
0x19
RO
Buffer:
No
Reset:
Undefined
Description:
7 PLL_UNLOCK: PLL unlock state:
0: PLL is not in unlock state
1: PLL is in unlock state
6 PLL_PWD_ STATE: PLL power-down state:
0: PLL is not in power-down state
1: PLL is in power-down state
5 PLL_BYP_STATE: PLL bypass state:
0: PLL is not in bypass state
1: PLL is in bypass state
4:0 Reserved
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Registers
ADCCFG
ADC configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGA[2:0]
INSEL
STBY
BYPASS_CALIB
CLKENBL
Reserved
Address:
Type:
0x1E
RO
Buffer:
No
Reset:
Undefined
Description:
7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier:
000: default
Values are from 0 to 42 dB in 6 dB steps
4 INSEL:
0: line input selected (default)
1: microphone input selected (it must be applied to INL line)
3 STBY: ADC standby mode:
0: ADC in power-up mode (default)
1: ADC in standby mode
2 BYPASS_CALIB:
0: ADC DC-removal block not bypassed (default)
1: ADC DC-removal block bypassed
1 CLKENBL: Clock enable:
0: system clock not enabled
1: system clock available at ADC input (default)
0 Reserved
CKOCFG
Output clock configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLKOUT_DIS
CLKOUT_SEL[1:]]
Reserved
Address:
Type:
0x1F
R/W
Buffer:
No
Reset:
Undefined
Description:
7 CLKOUT_DIS: CLKOUT PAD disabled
0: default
1: enabled
6:5 CLKOUT_SEL[1:0]:
00: default
The CLKOUT output frequency is the PLL output frequency divided by 2CLKOUT_SEL
4:0 Reserved
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Registers
STA529
MISC
Miscellaneous configuration
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CORE_
CLKENBL
OSC_DIS
P2P_FS_RANGE[2:0]
ADC_FS_RANGE[1:0]
P2P_IN_ADC
Address:
Type:
0x20
R/W
No
Buffer:
Reset:
0x20
Description:
7 OSC_DIS: enable/disable crystal oscillator:
0: default
1: disabled
6:4 P2P_FS_RANGE[2:0]: FFX audio frequency range:
000: very low (fs = 8 to 12 kHz)
001: low (fs = 16 to 24 kHz)
010: normal (fs = 32 to 48 kHz) (default)
011: high (fs = 64 to 96 kHz)
1X: very high (fs = 128 to 192 kHz)
3:2 ADC_FS_RANGE[2:0]: ADC audio frequency range:
00: normal (fs = 32 to 48 kHz) (default)
01: low (fs = 16 to 24 kHz)
1X: very low (fs = 8 to 12 kHz)
1 P2P_IN_ADC: FFX input:
0: FFX input is from serial-to-parallel audio interface (default)
1: FFX input is from ADC
0 CORE_CLKENBL: availability of system clock:
0: FFX system clock disabled (default)
1: FFX system clock enabled
FFXST
FFX status
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INVALID_INP_
FBK
Reserved
MUTE_INT_FBK
Reserved
Address:
Type:
0x23
RO
No
Buffer:
Reset:
Undefined
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Registers
Description:
7:3 Reserved
2 INVALID_INP_FBK: invalid input status:
1: invalid input sent to FFX
1 MUTE_INT_FBK: FFX mute status
1: FFX is in mute state
0 Reserved
PWMINT1
PWM driver configuration (MSBs)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWM_INT[15:8]
Address:
Type:
0x2D
R/W
No
Buffer:
Reset:
0x00
Description:
7:0 PWM_INT[15:8]: MSBs of PWM_INT[15:0], see Chapter 8: Driver configuration on page 28
PWMINT2
PWM driver configuration (LSBs)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWM_INT[7:0]
Address:
Type:
0x2E
R/W
No
Buffer:
Reset:
0x00
Description:
7:0 PWM_INT[7:0]: LSBs of PWM_INT[15:0], see Chapter 8: Driver configuration on page 28
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Registers
STA529
POWST
Power bridge status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POW_
POWERDOWN
POW_
TRISTATE
POW_FAULT1A POW_FAULT1B POW_FAULT2A POW_FAULT2B
Reserved
Address:
Type:
0x32
RO
Buffer:
No
Reset:
Undefined
Description:
7 POW_POWERDOWN: power-down bridge:
0: not in power-down state
1: power-down state
6 POW_TRISTATE:
1: power bridge is in tristate
5 POW_FAULT1A:
1: power bridge 1A is in fault state
4 POW_FAULT1B:
1: power bridge 1B is in fault state
3 POW_FAULT2A:
1: power bridge 2A is in fault state
2 POW_FAULT2B:
1: power bridge 2B is in fault state
1:0 Reserved
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Package mechanical data
12
Package mechanical data
This section contains packaging information for the following packages:
●
TFBGA48
●
VFQFPN52
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
12.1
Package TFBGA48
Figure 18. Package outline (TFBGA48)
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Package mechanical data
STA529
Table 23. Package dimensions (TFBGA48)
Dimensions in mm
Typ
Reference
Min
Max
A
-
-
-
1.20
A1
A2
A3
A4
b
0.15
-
-
0.785
0.20
-
-
-
-
-
0.60
0.35
5.15
-
0.25
0.30
5.00
3.50
5.00
3.50
0.50
0.75
-
D
4.85
D1
E
-
4.85
5.15
-
E1
e
-
-
-
-
-
-
-
F
-
ddd
eee
fff
0.08
0.15
0.05
-
-
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Package mechanical data
12.2
Package VFQFPN52
Figure 19. Package outline (VFQFPN52)
Table 24. Package dimensions (VFQFPN52)
Dimensions in mm
Typ
Reference
Min
Max
A
0.800
-
0.900
0.020
0.650
0.250
0.230
8.000
5.700
8.000
5.700
0.500
0.550
-
1.000
0.050
1.000
-
A1
A2
A3
b
-
-
0.180
7.875
2.750
7.875
2.750
0.450
0.350
-
0.300
8.125
6.250
8.125
6.250
0.550
0.750
0.080
D
D2
E
E2
e
L
ddd
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Revision history
STA529
13
Revision history
Table 25. Document revision history
Date
Revision
Changes
25-Jan-2007
09-Apr-2010
1
2
Initial release.
Complete update and change in presentation
Updated Features
Added Section 6.3: Set fractional PLL
Updated Section 7.2: Functional description
Minor textual updates
30-Mar-2012
3
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Doc ID 13095 Rev 3
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