STCD1020RDG6E [STMICROELECTRONICS]
Multi-channel clock distribution circuit; 多路时钟分配电路
| 型号： | STCD1020RDG6E |
| 厂家： | 
ST |
| 描述： | Multi-channel clock distribution circuit |
| 文件： | 总40页 (文件大小：1779K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STCD1020, STCD1030, STCD1040
Multi-channel clock distribution circuit
Features
■ 2, 3 or 4 outputs buffered clock distribution
■ Single-ended sine wave or square wave clock
input and output
■ Individual clock enable for each output
■ Lower fan-out on clock source
TDFN (8, 10 or 12 lead)
■ No AC coupling capacitor needed at the input
■ Ultra-low phase noise and standby current
Description
(a)
■ 2.5 V to 3.6 V supply voltage
The STCD1020, STCD1030 and STCD1040 are
2, 3 or 4 outputs unity gain clock distribution
circuits, which are used to provide a common
frequency clock to multi-mode mobile RF
applications. It can also be used for those
baseband peripheral applications in a mobile
phone such as WLAN, Bluetooth, GPS and DVB-
H as a clock reference. The STCD1020,
STCD1030 and STCD1040 isolate each device
driven by their clock outputs and minimize
interference between the devices. Each of the
clock buffers can be disabled to lower the power
consumption if the connected device does not
need the clock. The STCD1020, STCD1030 and
STCD1040 accept commonly used mobile master
clock frequencies ranging from 10 MHz to 52
MHz.
■ 10 pF typical load driving capability
■ Available in TDFN packages
– STCD1020 - 8-lead (2 mm x 2 mm)
– STCD1030 - 10-lead (2 mm x 2.5 mm)
– STCD1040 - 12-lead (2 mm x 3 mm)
■ Operational temperature : –40°C to 85°C
Applications
■ Multi-mode RF clock reference
■ Baseband peripheral devices clock reference
The STCD1020, STCD1030 and STCD1040 are
available in 2 mm x 2 mm 8-lead, 2 mm x 2.5 mm
10-lead and 2 mm x 3 mm 12-lead TDFN
packages and can be operated with a single 2.8 V
(or 1.8 V) supply. The operational temperature is
–40°C to +85°C.
a. For the 1.65 to 2.75 V version, please contact local ST
sales office
Table 1.
Device summary
Order code
Operating temperature range
Channel
Supply
Package
STCD1020RDG6E
STCD1030RDH6E
STCD1040RDM6F
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
2
3
4
2.8 V
2.8 V
2.8 V
TDFN8
TDFN10
TDFN12
May 2008
Rev 4
1/40
www.st.com
1
Contents
STCD1020, STCD1030, STCD1040
Contents
1
2
3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
3.2
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Connection of the source clock to MCLK . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
5
6
7
8
9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/40
STCD1020, STCD1030, STCD1040
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Truth table for enable signals (EN 1-4) and output clocks (CLK1-4) . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings (1.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings (2.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating and AC measurement conditions (1.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC characteristics (1.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating and AC measurement conditions (2.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC characteristics (2.8 V supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TDFN - 8-lead (2 x 2 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TDFN - 10-lead (2 x 2.5 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TDFN - 12-lead (2 x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3/40
List of figures
STCD1020, STCD1030, STCD1040
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connections diagram (STCD1020, 2-channel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connections diagram (STCD1030, 3-channel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connections diagram (STCD1040, 4-channel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical application circuit using STCD1040 for RF ends of TD-SCDMA/GSM dual mode
mobile phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical application circuit using STCD1040 for baseband peripherals in mobile phone . . 12
Direct connection of the source clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8.
Figure 9.
Figure 10. Connection of the DC-CUT capacitor and bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Quiescent current (I ) vs. supply voltage (V ) (STCD1040, 2.8 V version,
Q
CC
EN1=EN2=EN3=EN4=1, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Quiescent current (I ) vs. temperature (STCD1040, 2.8 V version,
Q
EN1=EN2=EN3=EN4=1, C
= 30 pF, no master clock input) . . . . . . . . . . . . . . . . . . . . . 18
load
Figure 13. Standy current (I ) vs. supply voltage (V ) (STCD1040, 2.8 V version,
SB
CC
EN1=EN2=EN3=EN4=0, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Active current (I ) vs. supply voltage (V ) (STCD1040, 2.8 V version,
ACT
CC
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO) . . . . . . . . . . 19
Figure 15. Active current (I ) vs. master clock input voltage level (Vpp) (STCD1040, 2.8 V version,
ACT
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input). . . . . . . . . . . . . . . . . . . . 20
Figure 16. Active current (I ) vs. input frequency (STCD1040, 2.8 V version,
ACT
EN1=EN2=EN3=EN4=1, master clock input Vpp = 1 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. STCD10x0 recovery time from standby to active (STCD1040, 2.8 V version,
EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1) . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. STCD10x0 buffer recovery time from off to on (STCD1040, 2.8 V version,
EN2=EN3=EN4=1, measure CLK1 when EN1 from 0 to 1) . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. Sine wave input clock vs. output clock (STCD1040, 2.8 V version, 26 MHz sine wave
master clock input from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 20. Rise and fall time for square wave output (STCD1040, 2.8 V, 10 MHz square wave
master clock input, C
= 20 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
load
Figure 21. Input clock phase noise (STCD1040, 2.8 V version, 26 MHz master clock input
from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 22. Output clock phase noise (STCD1040, 2.8V version, this phase noise includes the
additive phase noise from TCXO and STCD1040). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23. Clock bandwidth (STCD1040, 2.8 V version, C
= 10 pF) . . . . . . . . . . . . . . . . . . . . . . . 24
load
Figure 24. Quiescent current (I ) vs. supply voltage (V ) (STCD1040, 1.8 V version,
Q
CC
EN1=EN2=EN3=EN4=1, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 25. Quiescent current (I ) vs. temperature (STCD1040, 1.8 V version,
Q
EN1=EN2=EN3=EN4=1, C
= 30 pF, no master clock input) . . . . . . . . . . . . . . . . . . . . 25
load
Figure 26. Standby current (I ) vs. supply voltage (V ) (STCD1040, 1.8 V version,
SB
CC
EN1=EN2=EN3=EN4=0, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 27. Active current (I ) vs. supply voltage (V ) (STCD1040, 1.8 V version,
ACT
CC
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO) . . . . . . . . . . 26
Figure 28. Active current (I ) vs. master clock input voltage level (Vpp) (STCD1040, 1.8 V version,
ACT
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input). . . . . . . . . . . . . . . . . . . . 26
Figure 29. Active current (I ) vs. input frequency (STCD1040, 1.8 V version,
ACT
EN1=EN2=EN3=EN4=1, master clock input Vpp=1 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4/40
STCD1020, STCD1030, STCD1040
List of figures
Figure 30. STCD10x0 recovery time from standby to active (STCD1040, 1.8 V version,
EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1) . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 31. STCD10x0 buffer recovery time from off to on (STCD1040, 1.8 V version,
EN2 =EN3=EN4=1, measure CLK1 when EN1 from 0 to 1). . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 32. Sine wave input clock vs. output clock (STCD1040, 1.8 V version, 26 MHz sine wave
master clock input from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33. Rise and fall time for square wave output (STCD1040, 1.8 V version, 10MHz square wave
master clock input, C
= 20 pF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
load
Figure 34. Input clock phase noise (STCD1040, 1.8 V version, 26 MHz master clock input
from TCXO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 35. Output clock phase noise (STCD1040, 1.8 V version, this phase noise includes the
additive phase noise from TCXO and STCD1040). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 36. Clock bandwidth (STCD1040, 1.8 V version, C
= 10 pF) . . . . . . . . . . . . . . . . . . . . . . . 30
load
Figure 37. TDFN - 8-lead, 2 x 2 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 38. TDFN - 10-lead, 2 x 2.5 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. TDFN - 12-lead, 2 x 3 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5/40
Device overview
STCD1020, STCD1030, STCD1040
1
Device overview
Figure 1.
Logic diagram
V
CC
MCLK
EN1
EN2
EN3
EN4
CLK1
CLK2
CLK3
CLK4
STCD1040
Clock
distribution
GND
ai13948
Note:
No EN3, EN4, CLK3 nor CLK4 for STCD1020 and no EN4 nor CLK4 for STCD1030.
Figure 2. Connections diagram (STCD1020, 2-channel)
1
2
8
7
V
GND
NC
CC
STCD1020
TDFN8
MCLK
EN1
3
4
6
5
CLK1
CLK2
EN2
ai13949
6/40
STCD1020, STCD1030, STCD1040
Figure 3. Connections diagram (STCD1030, 3-channel)
Device overview
V
CC
GND
NC
1
2
10
9
MCLK
EN1
STCK1030
TDFN10
8
3
4
5
CLK1
CLK2
CLK3
EN2
7
6
EN3
ai13950
Figure 4.
Connections diagram (STCD1040, 4-channel)
V
1
CC
12
11
GND
NC
2
MCLK
STCD1040
TDFN12
3
4
CLK1
CLK2
CLK3
CLK4
10
9
EN1
EN2
EN3
EN4
5
6
8
7
ai13951
7/40
Device overview
STCD1020, STCD1030, STCD1040
Function
Table 2.
Pin names and functions
Pin
Type
Clock output channel #1, #2, #3, #4. A 0.001μ F DC
cut capacitor needed outside.
CLK1, CLK2, CLK3, CLK4
Output
Clock output channel #1, #2, #3, #4 enable, active
high
EN1, EN2, EN3, EN4
Input
Input
MCLK
VCC
Master clock input
Supply voltage. Bypass to GND with a 0.1 μ F
capacitor.
Supply
Supply
GND
NC
Supply ground
Not connected
Figure 5.
Block diagram
V
CC
EN4
STCD1040
4
CLK4
EN3
3
CLK3
MCLK
EN2
2
CLK2
EN1
1
CLK1
GND
ai13952
8/40
STCD1020, STCD1030, STCD1040
Figure 6. Hardware hookup
Device overview
V
CC
Clock enable
control
V
CC
EN4
Clock #4
output
CLK4
STCD1040
MCLK
EN3
CLK3
Master
Clock #3
output
Clock input
EN2
CLK2
Clock #2
output
EN1
CLK1
Clock #1
output
GND
ai13953
9/40
Device operation
STCD1020, STCD1030, STCD1040
2
Device operation
The STCD1020, STCD1030 and STCD1040 are 2, 3 or 4 buffered unity gain clock
distribution circuits. They accept the clock input from an external clock source and send 2, 3
or 4 buffered outputs to different devices.
Each clock output of the STCD1020, STCD1030 and STCD1040 can be enabled for the
device connected to it. If the device connected is in standby and does not require a clock,
the buffer can be disabled to save power consumption. If all the devices connected are in
standby, the STCD1020, STCD1030 and STCD1040 will also be put into standby mode for
further power consumption saving. The enable signals and output clock signals truth table
are given in Table 3.
The input DC cut capacitor is embedded in STCD1020, STCD1030 and STCD1040. A
capacitor outside is needed for each of the clock outputs. The STCD1020, STCD1030 and
STCD1040 are internally biased at 1/2 V DC voltage level at the outputs.
CC
Table 3.
EN1
Truth table for enable signals (EN 1-4) and output clocks (CLK1-4)
EN2
EN3
EN4
CLK1
CLK2
CLK3
CLK4
0
1
0
0
0
0
0
0
NO CLOCK NO CLOCK NO CLOCK NO CLOCK
CLOCK
CLOCK
...
NO CLOCK NO CLOCK NO CLOCK
1
1
0
0
CLOCK
...
NO CLOCK NO CLOCK
...
1
...
1
...
1
...
1
...
...
CLOCK
CLOCK
CLOCK
CLOCK
Note:
"0" means logic low and "1" means logic high. When NO CLOCK outputs, the CLKx pins
stay at High Impedance.
10/40
STCD1020, STCD1030, STCD1040
Application information
3
Application information
3.1
Typical applications
The STCD1020, STCD1030 and STCD1040 distribute a source clock (for example, from
VCTCXO) to 2, 3 or 4 channel outputs. The typical application circuits using STCD1040 are
shown in Figure 7 and Figure 8 below.
In Figure 7, the clock from VCTCXO is distributed to the TD-SCDMA transmitter and
receiver and GSM transceiver separately.
In Figure 8, the buffer #4 output is fed into the Bluetooth system. In order to allow minimum
power consumption, a Bluetooth system always has a clock request feature. If the Bluetooth
system does not require the clock, the clock request will disable the clock output.
The enable pins can also be connected to logic high to let the channel output always on. If
the channels of STCD1020, STCD1030 and STCD1040 are not used in the application, the
enable pins of the channels should be connected to ground on PCB.
Figure 7.
Typical application circuit using STCD1040 for RF ends of TD-
SCDMA/GSM dual mode mobile phone
V
CC
Mode
selection
V
CC
EN4
STCD1040
TD-SCDMA
transmitter
CLK4
VCTCXO
EN3
CLK3
EN2
MCLK
TD-SCDMA
receiver
CLK2
EN1
CLK1
GND
GSM
transceiver
ai13954
11/40
Application information
Figure 8.
STCD1020, STCD1030, STCD1040
Typical application circuit using STCD1040 for baseband peripherals in
mobile phone
V
BT_External_Req
CC
V
CC
Bluetooth
EN4
CLK4
STCD1040
VCTCXO
WLAN
GPS
EN3
CLK3
MCLK
EN2
CLK2
EN1
CLK1
GND
Other
device
ai13955
3.2
Connection of the source clock to MCLK
If the output of the clock source voltage level is within the supply rails of the STCD1020,
STCD1030 and STCD1040, the output of the source clock should be connected directly to
the MCLK of the clock distribution circuits. This is described in Figure 9. The direct
connection of the source clock is the common case and a DC-CUT capacitor is saved on
PCB.
Figure 9.
Direct connection of the source clock
V
CC
STCD1020
STCD1030
STCD1040
MCLK
OUT
VCTCXO
ai13956
Note:
The input clock voltage level of the STCD1020, STCD1030, and STCD1040 cannot exceed
the supply rails when it is directly connected to the source clock. If it is needed to connect a
source clock with the voltage level exceeds the supply rails of the clock distribution circuits,
the user needs to connect a DC-CUT capacitor serially as shown in Figure 10. A voltage
divider formed by a resistor string is also needed to set a proper DC bias for the clock input
12/40
STCD1020, STCD1030, STCD1040
Application information
of the STCD1020, STCD1030 and STCD1040. The proper DC voltage is around half of the
supply.
The connection of the DC-CUT capacitor and bias for the STCD1020, STCD1030 and
STCD1040 is only needed when the output of VCTCXO voltage level exceeds the supply of
the clock distribution circuit (see Figure 10).
Figure 10. Connection of the DC-CUT capacitor and bias
V
CC
R
1
0.1μF
STCD1020
STCD1030
STCD1040
MCLK
OUT
VCTCXO
DC-CUT
R
2
ai13957
13/40
Maximum rating
STCD1020, STCD1030, STCD1040
4
Maximum rating
Stressing the device above the rating listed in the "Absolute maximum ratings" table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Symbol
TSTG
Absolute maximum ratings (1.8 V supply)
Parameter
Value
Unit
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
Maximum junction temperature
Supply voltage
-55 to 150
260
°C
°C
°C
(1)
TSLD
TJ
150
VCC
VIN
-0.3 to 3.6
-0.3 to 3.6
-0.3 to 3.6
149.0
V
Input voltage level
V
VEN
Voltage on enable pins
V
TDFN8
°C/W
°C/W
°C/W
θJA
Thermal resistance (junction to ambient)
TDFN10
TDFN12
136.6
132.4
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
Table 5.
Symbol
Absolute maximum ratings (2.8 V supply)
Parameter
Value
Unit
TSTG
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
Maximum junction temperature
Supply voltage
-55 to 150
260
°C
°C
°C
(1)
TSLD
TJ
150
VCC
VIN
-0.3 to 6
-0.3 to 6
-0.3 to 6
149.0
V
Input voltage level
V
VEN
Voltage on enable pins
V
TDFN8
°C/W
°C/W
°C/W
θJA
Thermal resistance (junction to ambient)
TDFN10
TDFN12
136.6
132.4
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
14/40
STCD1020, STCD1030, STCD1040
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow are derived from tests performed under the measurement conditions summarized in
Table 6. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 6.
Operating and AC measurement conditions (1.8 V supply)
Parameter
Condition
Unit
V
CC supply
1.65 to 2.75
0 to VCC
V
V
Output clock voltage (CLK1…CLK4)
Device enable voltage (EN1…EN4)
Ambient operating temperature (TA)
0 to VCC
V
-40 to +85
°C
Table 7.
Symbol
DC and AC characteristics (1.8 V supply)
Parameter
Condition(1)
Min
Typ
Max
Unit
fMCLK Master clock (eg. from VCTCXO)
Sine wave/square wave
10
26
1.8
1
52
MHz
V
VCC
Supply voltage
1.65
0.75
-1.5
2.75
Vin
Input clock voltage level(2)
Vpp
dB
Vout Output gain level(3)
CL = 10 pF
2 buffers version
3 buffers version
4 buffers version
1 channel enabled
2 channels enabled
3 channels enabled
4 channels enabled
All buffers disabled
At DC level
-0.5
1.6
2.0
2.6
1.7
2.2
2.7
3.2
2.6
3.3
4
IQ
Quiescent current(4)
Active current(5)
mA
IACT
mA
ISB
RIN
CIN
Standby current
Input resistance
Input capacitance
1
μA
kΩ
pF
>100
3
f = 26 MHz
4
5
Vin = 1 Vpp, CL = 10 pF
Square wave input/output
tr/f
Rise/fall time(6)
2
ns
Vin = 1 Vpp, –1 dB, CL = 10 pF
Sine wave input/output
BW
Signal bandwidth(3)
52
MHz
VENH Enable voltage high(7)
VENL Enable voltage low(7)
EN1~EN4
EN1~EN4
1.2
V
V
0.6
15/40
DC and AC parameters
STCD1020, STCD1030, STCD1040
Table 7.
Symbol
DC and AC characteristics (1.8 V supply)
Parameter
Condition(1)
Min
Typ
Max
Unit
at 1 kHz offset
at 10 kHz offset
at 100 kHz offset
-135
-145
-150
dBc/
Hz
PN
Additive phase noise(3)(8)
Buffer recovery time from off to
on
tRECB
tRECC
STCD10x0 active
20
μs
μs
STCD10x0 active recovery time
from standby to active
50
10
CL
RL
Capacitive load for each channel
Resistive load for each channel
20
pF
10
kΩ
1. Valid for ambient operating temperature: TA = -40°C to 85°C; VCC = 1.65 V to 2.75 V; typical TA = 25°C; Load
capacitance = 10 pF (except where noted).
2. Clock input voltage level should not exceed supply rails.
3. Simulated and determined via design and NOT 100% tested.
4. The quiescent current is measured when the enable pins are active, but without input master clock signal (fmclk = 0 Hz).
5. The active current is dependent on the master clock input Vpp and frequency and the capacitive load condition. The
typical test condition is 26 MHz sine wave with 1 Vpp master clock input, CL = 10 pF.
6. The rise time is measured when clock edge transfers from 10% VCC to 90% VCC. The fall time is measured when clock
edge transfers from 90% VCC to 10% VCC
.
7. Other test results are under test condition VENH = 1.8 V and VENL = 0 V.
8. Guaranteed with the supply noise of 30 μ Vrms from 300 Hz to 50 kHz.
Table 8.
Operating and AC measurement conditions (2.8 V supply)
Parameter
Condition
Unit
V
CC supply
2.5 to 3.6
0 to VCC
0 to VCC
-40 to +85
V
V
Output clock voltage (CLK1…CLK4)
Device enable voltage (EN1…EN4)
Ambient operating temperature (TA)
V
°C
Table 9.
Symbol
DC and AC characteristics (2.8 V supply)
Parameter
Condition(1)
Min
Typ
Max Unit
fMCLK
VCC
Vin
Master clock (eg. from VCTCXO)
Supply voltage
Sine wave/square wave
10
2.5
26
2.8
1
52
MHz
V
3.6
Input clock voltage level(2)
Output gain level(3)
0.75
-1.5
Vpp
dB
Vout
CL = 10 pF
-0.5
1.7
2.2
2.8
2 buffers version
3 buffers version
4 buffers version
2.6
3.3
4
IQ
Quiescent current(4)
mA
16/40
STCD1020, STCD1030, STCD1040
DC and AC parameters
Table 9.
Symbol
DC and AC characteristics (2.8 V supply) (continued)
Parameter
Condition(1)
Min
Typ
Max Unit
1 channel enabled
2 channels enabled
3 channels enabled
4 channels enabled
All buffers disabled
At DC level
1.8
2.3
IACT
Active current(5)
mA
2.85
3.4
ISB
RIN
CIN
Standby current
Input resistance
Input capacitance
1
μA
kΩ
pF
>100
3
f = 26 MHz
4
5
Vin = 1Vpp, CL = 10 pF
Square wave input/output
tr/f
Rise/fall times(6)
2
ns
Vin =1 Vpp, -1dB, CL = 10 pF
Sine wave input/output
BW
Signal bandwidth(3)
52
MHz
VENH
VENL
Enable voltage high(7)
Enable voltage low(7)
EN1~EN4
EN1~EN4
1.2
V
V
0.6
at 1 kHz offset
at 10 kHz offset
at 100 kHz offset
STCD10x0 active
-135
-145
-150
20
dBc/
Hz
PN
Additive phase noise(3)(8)
tRECB
tRECC
Buffer recovery time from off to on
μs
μs
STCD10x0 active recovery time
from standby to active
50
10
CL
RL
Capacitive load for each channel
Resistive load for each channel
20
pF
10
kΩ
1. Valid for ambient operating temperature: TA = -40°C to 85°C; VCC = 2.5 V to 3.6 V; typical TA = 25°C;
Load capacitance = 10 pF (except where noted).
2. Clock input voltage level should not exceed supply rails.
3. Simulated and determined via design and NOT 100% tested.
4. The quiescent current is measured when the enable pins are active, but without input master clock signal (fMCLK = 0 Hz).
5. The active current is dependent on the master clock input Vpp and frequency and the capacitive load condition. The typical
test condition is 26 MHz sine wave with 1 Vpp master clock input, CL = 10 pF.
6. The rise time is measured when clock edge transfers from 10% VCC to 90% VCC. The fall time is measured when clock
edge transfers from 90% VCC to 10% VCC
.
7. Other test results are under test condition VENH = 1.8 V and VENL = 0 V.
8. Guaranteed with the supply noise of 30 μ Vrms from 300 Hz to 50 kHz.
17/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
6
Typical operating characteristics
Typical operating characteristics of STCD1040 are V = 2.8 V; T = 25°C;
CC
A
load capacitance = 10 pF, 26 MHz TCXO ENE3127B from NDK (except where noted).
Figure 11. Quiescent current (I ) vs. supply voltage (V ) (STCD1040, 2.8 V version,
Q
CC
EN1=EN2=EN3=EN4=1, no master clock input)
Quiescent current vs. Supply voltage
3.1
3
10pF
20pF
30pF
2.9
2.8
2.7
2.6
2.5
2.4
Supply voltage (V)
Figure 12. Quiescent current (I ) vs. temperature (STCD1040, 2.8 V version,
Q
EN1=EN2=EN3=EN4=1, C
= 30 pF, no master clock input)
load
Quiescent current vs. Temperature
3.2
3
2.8
2.6
2.4
2.2
2
-50 -30 -10
10
30
50
70
90
Temperature (ºC)
18/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 13. Standy current (I ) vs. supply voltage (V ) (STCD1040, 2.8 V version,
SB
CC
EN1=EN2=EN3=EN4=0, no master clock input)
Standby current vs. Supply voltage
1
0.5
0
-0.5
-1
2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7
Supply voltage (V)
Figure 14. Active current (I
) vs. supply voltage (V ) (STCD1040, 2.8 V version,
CC
ACT
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO)
Active current vs. Supply voltage
6
4
10pF
2
20pF
30pF
0
2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7
Supply voltage (V)
19/40
Typical operating characteristics
Figure 15. Active current (I
STCD1020, STCD1030, STCD1040
) vs. master clock input voltage level (Vpp)
ACT
(STCD1040, 2.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz sine wave
master clock input)
Active current vs. Master clock voltage level
6
5
4
3
10pF
20pF
30pF
2
1
0
Master clock voltage level Vpp(V)
Figure 16. Active current (I
) vs. input frequency (STCD1040, 2.8 V version,
ACT
EN1=EN2=EN3=EN4=1, master clock input Vpp = 1 V)
Active current vs. Input frequency
10
8
6
4
10pF
20pF
30pF
2
0
1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Frequency (MHZ)
20/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 17. STCD10x0 recovery time from standby to active (STCD1040, 2.8 V
version, EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1)
Figure 18. STCD10x0 buffer recovery time from off to on (STCD1040, 2.8 V version,
EN2=EN3=EN4=1, measure CLK1 when EN1 from 0 to 1)
21/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 19. Sine wave input clock vs. output clock (STCD1040, 2.8 V version, 26 MHz
sine wave master clock input from TCXO)
Figure 20. Rise and fall time for square wave output (STCD1040, 2.8 V, 10 MHz
square wave master clock input, C
= 20 pF)
load
22/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 21. Input clock phase noise (STCD1040, 2.8 V version, 26 MHz master clock
input from TCXO)
Figure 22. Output clock phase noise (STCD1040, 2.8V version, this phase noise
includes the additive phase noise from TCXO and STCD1040)
23/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 23. Clock bandwidth (STCD1040, 2.8 V version, C
= 10 pF)
load
Clock bandwidth
0.00
-1.00
-2.00
-3.00
-4.00
-5.00
-6.00
-7.00
-8.00
0
1
10
100
Input frequency (MHz)
Figure 24. Quiescent current (I ) vs. supply voltage (V ) (STCD1040, 1.8 V version,
Q
CC
EN1=EN2=EN3=EN4=1, no master clock input)
Quiescent current vs. Supply voltage
3
2.8
2.6
2.4
2.2
2
10pF
20pF
30pF
Supply voltage (V)
24/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 25. Quiescent current (I ) vs. temperature (STCD1040, 1.8 V version,
Q
EN1=EN2=EN3=EN4=1, C
= 30 pF, no master clock input)
load
Quiescent current vs. Temperature
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
-50
-30
-10
10
30
50
70
90
Temperature (˚C)
Figure 26. Standby current (I ) vs. supply voltage (V ) (STCD1040, 1.8 V version,
SB
CC
EN1=EN2=EN3=EN4=0, no master clock input)
Standby current vs. Supply voltage
1
0.5
0
-0.5
-1
Supply voltage (V)
25/40
Typical operating characteristics
Figure 27. Active current (I
STCD1020, STCD1030, STCD1040
) vs. supply voltage (V ) (STCD1040, 1.8 V version,
ACT
CC
EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO)
Active current vs. Supply voltage
6
4
10pF
2
20pF
30pF
0
1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
Supply voltage (V)
Figure 28. Active current (I
) vs. master clock input voltage level (Vpp)
ACT
(STCD1040, 1.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz sine wave
master clock input)
Active current vs. Master clock voltage level
6
5
4
3
10pF
2
20pF
1
30pF
0
Master clock voltage level Vpp(V)
26/40
STCD1020, STCD1030, STCD1040
Figure 29. Active current (I
Typical operating characteristics
) vs. input frequency (STCD1040, 1.8 V version,
ACT
EN1=EN2=EN3=EN4=1, master clock input Vpp=1 V)
Active current vs. Input frequency
12
10
8
6
10pF
20pF
30pF
4
2
0
1
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Frequency (MHZ)
Figure 30. STCD10x0 recovery time from standby to active (STCD1040, 1.8 V
version, EN2=EN3=EN4=0, measure CLK1 when EN1 from 0 to 1)
27/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 31. STCD10x0 buffer recovery time from off to on (STCD1040, 1.8 V version,
EN2 =EN3=EN4=1, measure CLK1 when EN1 from 0 to 1)
Figure 32. Sine wave input clock vs. output clock (STCD1040, 1.8 V version, 26 MHz
sine wave master clock input from TCXO)
28/40
STCD1020, STCD1030, STCD1040
Typical operating characteristics
Figure 33. Rise and fall time for square wave output (STCD1040, 1.8 V version,
10MHz square wave master clock input, C = 20 pF)
load
Figure 34. Input clock phase noise (STCD1040, 1.8 V version, 26 MHz master clock
input from TCXO)
29/40
Typical operating characteristics
STCD1020, STCD1030, STCD1040
Figure 35. Output clock phase noise (STCD1040, 1.8 V version, this phase noise
includes the additive phase noise from TCXO and STCD1040)
Figure 36. Clock bandwidth (STCD1040, 1.8 V version, C
= 10 pF)
load
Clock bandwidth
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
0
1
10
100
Input frequency(MHz)
30/40
STCD1020, STCD1030, STCD1040
Package mechanical data
7
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
31/40
Package mechanical data
STCD1020, STCD1030, STCD1040
Figure 37. TDFN - 8-lead, 2 x 2 mm package outline
D
B
PIN 1 INDEX AREA
0.10 C 2x
TOP VIEW
0.10
C
C
SEATING
PLANE
SIDE VIEW
e
0.08
C
b
PIN 1 INDEX AREA
0.10
C A B
1
4
Pin#1 ID
5
8
BOTTOM VIEW
TDFN-8L
32/40
STCD1020, STCD1030, STCD1040
Package mechanical data
Table 10. TDFN - 8-lead (2 x 2 mm) package mechanical data
mm
inches
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
A
A1
b
0.70
0.00
0.15
0.75
0.02
0.20
0.80
0.05
0.25
0.028
0.000
0.006
0.030
0.001
0.008
0.031
0.002
0.010
2.00
BSC
0.079
BSC
D
E
2.00
BSC
0.079
BSC
e
L
0.50
0.55
0.020
0.022
0.45
0.65
0.018
0.026
33/40
Package mechanical data
STCD1020, STCD1030, STCD1040
Figure 38. TDFN - 10-lead, 2 x 2.5 mm package outline
D
B
PIN 1 INDEX AREA
0.10 C 2x
TOP VIEW
0.10
C
SEATING
PLANE
SIDE VIEW
0.08
C
e
b
PIN 1 INDEX AREA
0.10
C A B
Pin#1 ID
BOTTOM VIEW
TDFN-10L
34/40
STCD1020, STCD1030, STCD1040
Package mechanical data
Table 11. TDFN - 10-lead (2 x 2.5 mm) package mechanical data
mm
inches
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
A
A1
b
0.70
0.00
0.15
0.75
0.02
0.20
0.80
0.05
0.25
0.028
0.000
0.006
0.030
0.001
0.008
0.031
0.002
0.010
2.50
BSC
0.098
BSC
D
E
2.00
BSC
0.079
BSC
e
L
0.50
0.55
0.020
0.022
0.45
0.65
0.018
0.026
35/40
Package mechanical data
STCD1020, STCD1030, STCD1040
Figure 39. TDFN - 12-lead, 2 x 3 mm package outline
D
B
INDEX AREA
(D/2xE/2)
0.10
C
TOP VIEW
0.10
C
C
SEATING
PLANE
SIDE VIEW
e
0.08
C
b
0.10
C A B
6
1
PIN#1 ID
INDEX AREA
(D/2xE/2)
12
7
BOTTOM VIEW
TDFN-12L
36/40
STCD1020, STCD1030, STCD1040
Package mechanical data
Table 12. TDFN - 12-lead (2 x 3 mm) package mechanical data
mm
inches
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
A
A1
b
0.70
0.00
0.15
0.75
0.02
0.20
0.80
0.05
0.25
0.028
0.000
0.006
0.030
0.001
0.008
0.031
0.002
0.010
3.00
BSC
D
E
0.118
0.079
2.00
BSC
e
L
0.50
0.55
0.020
0.022
0.45
0.65
0.018
0.026
37/40
Part numbering
STCD1020, STCD1030, STCD1040
8
Part numbering
Table 13. Ordering information scheme
Example:
STCD
1020
R
DG
6
E
Device type
STCD = clock distribution
Channels
1020 = 2-channel
1030 = 3-channel
1040 = 4-channel
Operating voltage
R = 2.5 to 3.6 V
P = 1.65 to 2.75 V(1)
Package
DG = TDFN8 (2-channel)
DH = TDFN10 (3-channel)
DM = TDFN12 (4-channel)
Temperature range
6 = –40°C to +85°C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
38/40
STCD1020, STCD1030, STCD1040
Revision history
9
Revision history
Table 14. Document revision history
Date
Revision
Changes
08-Aug-2007
1
Initial release.
Addition of footnote 4 in Table 7: DC and AC characteristics (1.8 V
supply); updated Vout in Table 7 and Table 9; minor text changes.
08-Oct-2007
03-Apr-2008
08-May-2008
2
3
4
Updated cover page, Table 2, 5, 7, 9, 13, Figure 1, 6, 11, 12, 13, 14,
15, 16, 17, 18, 19, 20, Section 2 and 6; added Figure 21, 22, 23, 24,
25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36.
Updated cover page, Table 7, 8, Figure 14, 15, 27, 28, and Section 6;
datasheet status upgraded to full datasheet.
39/40
STCD1020, STCD1030, STCD1040
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any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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40/40
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