STGIPQ3H60T-HZ [STMICROELECTRONICS]
Internal bootstrap diode;型号: | STGIPQ3H60T-HZ |
厂家: | ST |
描述: | Internal bootstrap diode |
文件: | 总26页 (文件大小:1305K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STGIPQ3H60T-HL,
STGIPQ3H60T-HZ
SLLIMM™ nano - 2nd series
IPM, 3 A, 600 V, 3-phase IGBT inverter bridge
Datasheet - production data
Applications
3-phase inverters for motor drives
Dish washers, refrigerator compressors,
heating systems, air-conditioning fans,
draining and recirculation pumps
Description
N2DIP-26L type L
This second series of SLLIMM (small low-loss
intelligent molded module) nano provides a
compact, high performance AC motor drive in a
simple, rugged design. It is composed of six
improved IGBTs with freewheeling diodes and
three half-bridge HVICs for gate driving, providing
low electromagnetic interference (EMI)
characteristics with optimized switching speed.
The package is designed to allow a better and
more easily screwed-on heatsink and is
N2DIP-26L type Z
Features
IPM 3 A, 600 V, 3-phase IGBT inverter
bridge including 3 control ICs for gate driving
and freewheeling diodes
optimized for thermal performance and
compactness in built-in motor applications or
other low power applications where assembly
space is limited. This IPM includes a completely
uncommitted operational amplifier and a
comparator that can be used to design a fast and
efficient protection circuit. SLLIMM™ is a
trademark of STMicroelectronics.
3.3 V, 5 V, 15 V TTL/CMOS input
comparators with hysteresis and pull-
down/pull-up resistors
Internal bootstrap diode
Optimized for low electromagnetic
interference
Undervoltage lockout
VCE(SAT) negative temperature coefficient
Smart shutdown function
Interlocking function
Op-amp for advanced current sensing
Comparator for fault protection against
overcurrent
NTC (UL 1434 CA 2 and 4)
Isolation ratings of 1500 Vrms/min.
Up to ±2 kV ESD protection
(HBM C = 100 pF, R = 1.5 kΩ)
UL recognition: UL 1557 file E81734
Table 1: Device summary
Marking
Order code
Package
Packing
STGIPQ3H60T-HL
STGIPQ3H60T-HZ
GIPQ3H60T-HL
GIPQ3H60T-HZ
N2DIP-26L type L
N2DIP-26L type Z
Tube
March 2017
DocID027219 Rev 5
1/26
www.st.com
This is information on a product in full production.
Contents
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Contents
1
2
Internal schematic diagram and pin configuration.......................3
Electrical ratings .............................................................................5
2.1
2.2
Absolute maximum ratings................................................................5
Thermal data.....................................................................................6
3
Electrical characteristics ................................................................7
3.1
3.2
Inverter part.......................................................................................7
Control part .......................................................................................9
3.2.1
NTC thermistor ................................................................................. 12
3.3
Waveform definitions.......................................................................14
4
5
Smart shutdown function .............................................................15
Application circuit example..........................................................17
5.1
Guidelines.......................................................................................18
6
Package information .....................................................................20
6.1
6.2
6.3
N2DIP-26L type L package information ..........................................20
N2DIP-26L type Z package information ..........................................22
N2DIP-26L packing information ......................................................24
7
Revision history ............................................................................25
2/26
DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Internal schematic diagram and pin configuration
1
Internal schematic diagram and pin configuration
Figure 1: Internal schematic diagram
N W (26)
GND (1)
NTC
T/ SD / OD (2)
Vcc W (3)
W, OUT W (25)
GND
HVG
OUT
LVG
Vboo t W (24)
VCC
HIN
HIN W (4)
SD/OD
LIN
LINW (5)
OP+ (6)
Vboot
N V (23)
OPOUT (7)
OP- (8)
GND
OP+
OPOUT
OP-
V, OUT V (22)
HVG
OUT
LVG
VCC
HIN
Vcc V (9)
HIN V (10)
LIN V (11)
SD/OD
LIN
Vboot
Vboo t V (21)
N U (20)
GND
CIN (12)
CIN
HVG
OUT
LVG
Vcc U (13)
U, OUT U (19)
VCC
HIN
HIN U (14)
SD/OD
LIN
P (18)
Vboot
T / SD / OD (15)
Vboo t U (17)
LIN U (16)
DocID027219 Rev 5
3/26
Internal schematic diagram and pin configuration
Table 2: Pin description
Description
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Pin
Symbol
1
GND
Ground
NTC thermistor terminal / shutdown logic input (active low) / open-drain
(comparator output)
T/ SD / OD
2
3
4
VCC
W
Low voltage power supply W phase
High-side logic input for W phase
Low-side logic input for W phase
Op-amp non-inverting input
Op-amp output
HIN W
LIN W
OP+
5
6
7
OPOUT
OP-
8
Op-amp inverting input
9
VCC
V
Low voltage power supply V phase
High-side logic input for V phase
Low-side logic input for V phase
Comparator input
10
11
12
13
14
HIN V
LIN V
CIN
VCC
U
Low voltage power supply for V phase
High-side logic input for V phase
HIN U
T/ SD / OD
LIN U
NTC thermistor terminal / shutdown logic input (active low) / open-drain
(comparator output)
15
16
17
18
19
20
21
22
23
24
25
26
Low-side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
VBOOT
P
U
U, OUTU
NU
U phase output
Negative DC input for U phase
Bootstrap voltage for V phase
V phase output
VBOOT
V
V, OUTV
NV
Negative DC input for V phase
Bootstrap voltage for W phase
W phase output
VBOOT
W
W, OUTW
NW
Negative DC input for W phase
4/26
DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Electrical ratings
2
Electrical ratings
2.1
Absolute maximum ratings
Table 3: Inverter part
Symbol
VCES
IC
Parameter
Value
Unit
V
Collector-emitter voltage each IGBT (VIN(1)= 0 V)
Continuous collector current each IGBT
600
3
A
(2)
ICP
Peak collector current each IGBT (less than 1 ms)
Total dissipation at TC=25 °C each IGBT
6
A
PTOT
12
W
Notes:
(1)Applied among HINx, LINx and GND for x = U, V, W.
(2)Pulse width limited by max. junction temperature.
Table 4: Control part
Parameter
Low voltage power supply
Bootstrap voltage
Symbol
VCC
Min.
- 0.3
- 0.3
Max.
21
Unit
V
Vboot
620
V
Output voltage applied among OUTU, OUTV, OUTW
GND
-
VOUT
Vboot - 21
Vboot + 0.3
V
VCIN
Vop+
Vop-
Comparator input voltage
Op-amp non-inverting input
Op-amp inverting input
- 0.3
- 0.3
- 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
V
V
V
Logic input voltage applied among HINx, LINx and
GND
VIN
- 0.3
- 0.3
15
V
푉푇/푆퐷/푂퐷
̅̅̅̅
Open-drain voltage
15
50
V
∆VOUT/dT Allowed output slew rate
V/ns
Table 5: Total system
Symbol
Parameter
Value
Unit
Isolation withstand voltage applied to each pin and
heatsink plate (AC voltage, t = 60 s)
VISO
1500
V
Tj
Power chip operating junction temperature
Module case operation temperature
-40 to 150
-40 to 125
°C
°C
TC
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5/26
Electrical ratings
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
2.2
Thermal data
Table 6: Thermal data
Parameter
Symbol
Rth(j-c)
Value
10
Unit
Thermal resistance junction-case single IGBT
Thermal resistance junction-case single diode
Thermal resistance junction-ambient
15
°C/W
Rth(j-a)
44
6/26
DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Electrical characteristics
3
Electrical characteristics
TJ = 25 °C unless otherwise specified.
3.1
Inverter part
Table 7: Static
Test conditions
VCE = 550 V,
Symbol
Parameter
Min. Typ. Max. Unit
Collector cut-off current
ICES
-
-
250
2.6
μA
(VIN(1) = 0 “logic state”)
VCC = VBoot = 15 V
VCC = Vboot = 15 V,
VIN(1) = 0 - 5 V, IC = 1 A
2.15
1.65
V
Collector-emitter
saturation voltage
VCE(sat)
VCC = Vboot = 15 V,
VIN(1)= 0 to 5 V, IC = 1 A,
TJ = 125 °C
-
-
V
V
VF
Diode forward voltage
VIN(1) = 0 “logic state”, IC = 1 A
1.8
Notes:
(1)Applied among HINx, LINx and GND for x = U, V, W.
Table 8: Inductive load switching time and energy
Parameter Test conditions Min. Typ. Max. Unit
Turn-on time
Symbol
(1)
ton
-
-
-
-
-
275
90
-
-
-
-
-
(1)
tc(on)
Crossover time (on)
Turn-off time
VDD = 300 V,
(1)
toff
890
125
50
ns
VCC = Vboot = 15 V,
VIN(2) = 0 - 5 V,
IC = 1 A
(1)
tc(off)
Crossover time (off)
Reverse recovery time
trr
Turn-on switching
energy
(see Figure 3: "Switching time
definition")
Eon
-
-
18
13
-
-
µJ
Turn-off switching
energy
Eoff
Notes:
(1)
t
and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of
ON
IGBT itself under the internally given gate driving conditions.
(2)Applied among HINx, LINx and GND for x = U, V, W.
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Electrical characteristics
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Figure 2: Switching time test circuit
Figure 3: Switching time definition
Figure 3: "Switching time definition" refers to HIN, LIN inputs (active high).
8/26
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STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Electrical characteristics
Min. Typ. Max. Unit
3.2
Control part
Table 9: Low voltage power supply
Test conditions
Symbol
Parameter
VCC UV hysteresis
VCC_hys
1.2
11.5
10
1.5
12
1.8
12.5
11
V
V
V
VCCH_th(on) VCCH UV turn-on threshold
VCCH_th(off) VCCH UV turn-off threshold
10.5
VCC = 10 V,
Undervoltage quiescent
supply current
T/ SD /OD = 5 V;
LIN =HIN =CIN = 0 V
VCC = 10 V,
Iqccu
150
1
µA
T/ SD /OD = 5 V;
LIN = HIN =CIN = 0 V
Iqcc
Quiescent current
mA
V
Internal comparator (CIN)
reference voltage
VREF
0.51 0.54 0.56
Table 10: Bootstrapped voltage
Test conditions
Symbol
Parameter
Min. Typ.
Max. Unit
VBS_hys
VBS UV hysteresis
1.2
11.1
9.8
1.5
11.5
10
1.8
V
V
V
VBS_th(on) VBS UV turn-on threshold
VBS_th(off) VBS UV turn-off threshold
12.1
10.6
VBS < 9 V,
T/ SD /OD = 5 V;
Undervoltage VBS
IQBSU
70
110
210
µA
quiescent current
LIN = 0 V and HIN = 5 V;
CIN = 0 V
VBS = 15 V,
T/ SD /OD = 5 V;
IQBS
VBS quiescent current
150
120
µA
LIN = 0 V and HIN = 5 V;
CIN = 0 V
Bootstrap driver on-
resistance
RDS(on)
LVG ON
Ω
DocID027219 Rev 5
9/26
Electrical characteristics
Symbol
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Table 11: Logic inputs
Test conditions
Parameter
Min. Typ. Max. Unit
Vil
Low logic level voltage
High logic level voltage
0.8
V
V
Vih
2.25
20
HIN logic “1” input bias
current
IHINh
IHINl
ILINl
HIN = 15 V
40
100
1
µA
µA
µA
µA
HIN logic “0” input bias
current
HIN = 0 V
LIN = 0 V
LIN = 15 V
LIN logic “0” input bias
current
1
LIN logic “1” input bias
current
ILINh
20
40
100
SD logic “0” input bias
SD = 15 V
SD = 0 V
ISDh
220
295
370
3
µA
µA
current
SD logic “1” input bias
ISDl
current
See Figure 8: "Dead time and
interlocking waveform
definitions"
Dt
Dead time
180
ns
Table 12: Op-amp characteristics
Test conditions
Symbol Parameter
Min. Typ. Max. Unit
Vio
Iio
Input offset voltage
Vic = 0 V, Vo = 7.5 V
Vic = 0 V, Vo = 7.5 V
6
mV
nA
nA
mV
V
Input offset current
Input bias current (1)
4
100
75
40
Iib
200
150
VOL
VOH
Low level output voltage
High level output voltage
RL = 10 kΩ to VCC
RL= 10 kΩ to GND
14
16
50
14.7
30
Source, Vid = + 1 V; Vo = 0 V
Sink, Vid = -1 V; Vo = VCC
mA
mA
Io
Output short-circuit current
Slew rate
80
Vi = 1 - 4 V; CL = 100 pF;
unity gain
SR
2.5
3.8
V/µs
GBWP Gain bandwidth product
Vo = 7.5 V
8
12
85
MHz
dB
Avd
Large signal voltage gain
RL = 2 kΩ
70
Supply voltage rejection
ratio
SVR
vs VCC
60
55
75
70
dB
dB
Common mode rejection
ratio
CMRR
Notes:
(1)The direction of input current is out of the IC.
10/26
DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Table 13: Sense comparator characteristics
Parameter Test conditions
Input bias current VCIN = 1 V
Electrical characteristics
Symbol
Min. Typ. Max. Unit
Iib
-
-
3.1
0.5
µA
V
Open-drain low level output
voltage
Vod
Iod = 3 mA
Iod = 3 mA
RON_OD Open-drain low level output
-
-
166
125
Ω
SD pull-down resistor (1)
RPD_SD
kΩ
T/ SD /OD pulled to 5 V
through 100 kΩ resistor
CL = 180 pF; Rpu = 5 kΩ
td_comp
Comparator delay
Slew rate
-
90
130
ns
SR
tsd
-
-
60
V/µs
Shutdown to high / low-side
driver propagation delay
VOUT = 0, Vboot = VCC
VIN = 0 to 3.3 V
,
125
ns
Comparator triggering to high / Measured applying a
tisd
low-side driver turn-off
propagation delay
voltage step from 0 V to
3.3 V to pin CIN
-
200
Notes:
(1)Equivalent values as a result of the resistances of three drivers in parallel.
Table 14: Truth table
Logic input (VI)
Conditions
Output
T/ SD /OD
LIN
HIN
LVG
HVG
Shutdown enable half-bridge tri-state
Interlocking half-bridge tri-state
L
X(1)
H
X(1)
H
L
L
L
H
L
L
L
L
L
H
H
H
H
H
0 “logic state” half-bridge tri-state
1 “logic state” low-side direct driving
1 “logic state” high-side direct driving
L
L
H
L
L
H
Notes:
(1)X: don’t care.
DocID027219 Rev 5
11/26
Electrical characteristics
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
3.2.1
NTC thermistor
Figure 4: Internal structure of SD and NTC
Vbias
R SD
LIN
Vboot
V
T/SD/OD
SD/OD
HIN
HVG
OUT
LVG
CIN
C SD
NTC
VCC
RPD_SD
GND
RPD_SD: equivalent value as result of resistances of three drivers in parallel.
Figure 5: Equivalent resistance (NTC//RPD_SD)
12/26
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STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Electrical characteristics
Figure 6: Equivalent resistance (NTC//RPD_SD) zoom
̅̅̅̅
Figure 7: Voltage of T/퐒퐃/OD pin according to NTC temperature
DocID027219 Rev 5
13/26
Electrical characteristics
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
3.3
Waveform definitions
Figure 8: Dead time and interlocking waveform definitions
14/26
DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Smart shutdown function
4
Smart shutdown function
The device integrates a comparator for fault sensing purposes. The comparator has an
internal voltage reference VREF connected to the inverting input, while the non-inverting
input on pin (CIN) can be connected to an external shunt resistor for overcurrent protection.
When the comparator triggers, the device is set to the shutdown state and both of its
outputs are set to the low level, causing the half-bridge to enter a tri-state.
In common overcurrent protection architectures, the comparator output is usually
connected to the shutdown input through an RC network so to provide a monostable circuit,
which implements a protection time following to a fault condition.
Our smart shutdown architecture immediately turns off the output gate driver in case of
overcurrent through a preferential path for the fault signal, which directly switches off the
outputs. The time delay between the fault and output shutdown no longer depends on the
RC values of the external network connected to the shutdown pin. At the same time, the
DMOS connected to the open-drain output (pin T/ SD /OD) is turned on by the internal
logic, which holds it on until the shutdown voltage is well below the minimum value of logic
input threshold (Vil).
Besides, the smart shutdown function allows the real disable time to be increased while the
constant time of the external RC network remains as it is.
An NTC thermistor for temperature monitoring is internally connected in parallel to the
SD pin. To avoid undesired shutdown, keep the voltage 푉푇/푆퐷/푂퐷 higher than the high
̅̅̅̅
level logic threshold by setting the pull-up resistor 푅 to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V
̅̅̅̅
푆퐷
MCU power supplies, respectively.
DocID027219 Rev 5
15/26
Smart shutdown function
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Figure 9: Smart shutdown timing waveforms in case of overcurrent event
comp Vref
CP+
HIN/LIN
PROTECTION
HVG/LVG
SD/OD
open-drain gate
(internal)
disable time
Fast shutdown:
the driver outputs are set to the SD state as soon as the comparator
triggers even if the SD signal hasn’t reached the lowest input threshold
An approximation of the disable time is given by:
SHUTDOWN CIRCUIT
Vbias
R SD
T/SD/ OD
VT/SD/OD
SMART SD
LOGIC
C SD
RPD_SD
RON_OD
NTC
GIPG080920140931FSR
16/26
DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Application circuit example
5
Application circuit example
Figure 10: Application circuit example
MICROCONTROLLER
GAD250720161156FSR
Application designers are free to use a different scheme according to the specifications of
the device.
DocID027219 Rev 5
17/26
Application circuit example
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
5.1
Guidelines
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-
in for each input. To avoid input signal oscillations, the wiring of each input should be
as short as possible and the use of RC filters (R1, C1) on each input signal is
suggested. The filters should be with a time constant of about 100 ns and placed as
close as possible to the IPM input pins.
The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient
circuit demand on the power supply. Also, to reduce high frequency switching noise
distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR
and low ESL) should be placed as close as possible to Vcc pin and in parallel whit the
bypass capacitor.
The use of RC filter (RSF, CSF) is recommended to avoid protection circuit malfunction .
The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as
close as possible to the CIN pin.
The SD is an input/output pin (open-drain type if it is used as output). A built-in
thermistor NTC is internally connected between the SD pin and GND. The voltage
VSD-GND decreases as the temperature increases, due to the pull-up resistor RSD. In
order to keep the voltage always higher than the high level logic threshold, the pull-up
resistor is suggested to be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply,
respectively. The CSD capacitor of the filter on SD should be fixed no higher than
3.3 nF in order to assure the SD activation time τ1 ≤ 500 ns. Moreover, the filter
should be placed as close as possible to the SD pin.
The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low
ESL), in parallel with each Cboot, filters high frequency disturbance. Both Cboot and C3
(if present) should be placed as close as possible to the U, V, W and Vboot pins.
Bootstrap negative electrodes should be connected to U, V, W terminals directly and
separated from the main output wires.
To avoid the overvoltage on Vcc pin, a Zener diode (Dz1) can be used. Similarly on the
Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot
.
The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in
parallel with the electrolytic capacitor Cvdc avoids surge destruction. Both capacitors C4
and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc).
By integrating an application-specific type HVIC inside the module, direct coupling to
the MCU terminals without an optocoupler is possible.
Low inductance shunt resistors have to be used for phase leg current sensing.
In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND
should be as short as possible.
The connection of SGN_GND to PWR_GND on one point only (close to the shunt
resistor terminal) can reduce the impact of power ground fluctuation.
These guidelines ensure the specifications of the device for application designs. For further
details, please refer to the relevant application note.
18/26
DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Application circuit example
Table 15: Recommended operating conditions
Symbol
VPN
Parameter
Supply voltage
Test conditions
Applied among P-Nu, Nv, Nw
Applied to VCC-GND
Min. Typ. Max. Unit
300
15
500
18
V
V
VCC
Control supply voltage
13.5
13
Applied to VBOOTx-OUT
for x = U, V, W
VBS
High-side bias voltage
18
V
Blanking time to prevent
arm-short
tdead
For each input signal
1.5
µs
-40 °C < Tc < 100 °C
-40 °C < Tj < 125 °C
fPWM
TC
PWM input signal
25
kHz
°C
Case operation temperature
100
DocID027219 Rev 5
19/26
Package information
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.1
N2DIP-26L type L package information
Figure 11: N2DIP-26L type L package outline
20/26
DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Table 16: N2DIP-26L type L mechanical data
Package information
mm
Dim.
Min.
4.80
0.80
4.00
1.70
1.70
8.10
1.75
0.53
0.83
0.46
32.05
2.10
1.85
30.65
12.35
1.70
2.40
14.25
0.85
3.10
Typ.
5.10
1.00
4.10
1.80
1.80
8.40
Max.
5.40
1.20
4.20
1.90
1.90
8.70
A
A1
A2
A3
A4
A5
A6
b
0.72
1.02
b2
c
0.59
D
32.15
32.25
D1
D2
D3
E
30.75
12.45
1.80
30.85
12.55
1.90
e
e1
eB1
L
2.50
2.60
14.55
1.05
14.85
1.25
Dia
3.20
3.30
DocID027219 Rev 5
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Package information
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
6.2
N2DIP-26L type Z package information
Figure 12: N2DIP-26L type Z package outline
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DocID027219 Rev 5
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Table 17: N2DIP-26L type Z mechanical data
Package information
mm
Dim.
Min.
4.80
0.80
4.00
1.70
1.70
8.10
1.75
0.53
0.83
0.46
32.05
2.10
1.85
30.65
12.35
1.70
2.40
16.10
21.18
0.85
3.10
Typ.
5.10
1.00
4.10
1.80
1.80
8.40
Max.
5.40
1.20
4.20
1.90
1.90
8.70
A
A1
A2
A3
A4
A5
A6
b
0.72
1.02
b2
c
0.59
D
32.15
32.25
D1
D2
D3
E
30.75
12.45
1.80
30.85
12.55
1.90
e
e1
eB1
eB2
L
2.50
2.60
16.40
21.48
1.05
16.70
21.78
1.25
Dia
3.20
3.30
DocID027219 Rev 5
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Package information
STGIPQ3H60T-HL, STGIPQ3H60T-HZ
6.3
N2DIP-26L packing information
Figure 13: N2DIP-26L tube (dimensions are in mm)
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STGIPQ3H60T-HL, STGIPQ3H60T-HZ
Revision history
7
Revision history
Table 18: Document revision history
Changes
Date
Revision
25-Nov-2014
1
Initial release.
Text and formatting changes throughout document On cover page: -
updated Features - added N2DIP-26L type Z silhouette - renamed
N2DIP-26L type L silhouette and package name (was N2DIP-26L) -
renamed N2DIP-26L type Z package name (was N2DIP-26L) In
Section 2: Absolute maximum ratings: - updated Table 3: Inverter
parts In Section 2.1: Thermal data: - updated Table 6: Thermal data
In Section 3: Electrical characteristics: - updated Table 7: Inverter
parts
27-May-2015
2
Updated Table 8: Low voltage power supply, Table 9: Bootstrapped
voltage, Table 10: Logic inputs and Table 12: Sense comparator
characteristics. Minor text changes.
06-Jul-2015
31-Jul-2015
3
4
Document status promoted from preliminary to production data.
Modified Figure 2: "Switching time test circuit" and Figure 4: "Internal
structure of SD and NTC".
21-Mar-2017
5
Minor text changes.
DocID027219 Rev 5
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STGIPQ3H60T-HL, STGIPQ3H60T-HZ
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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