STL15N3LLH5 [STMICROELECTRONICS]

N-channel 30 V, 0.0045 Ω, 15 A, PowerFLAT™ (3.3 x 3.3) STripFET™ V Power MOSFET; N沟道30 V , 0.0045 Ω , 15 A , PowerFLAT ™ ( 3.3× 3.3 )的STripFET ™ V功率MOSFET
STL15N3LLH5
型号: STL15N3LLH5
厂家: ST    ST
描述:

N-channel 30 V, 0.0045 Ω, 15 A, PowerFLAT™ (3.3 x 3.3) STripFET™ V Power MOSFET
N沟道30 V , 0.0045 Ω , 15 A , PowerFLAT ™ ( 3.3× 3.3 )的STripFET ™ V功率MOSFET

晶体 晶体管 功率场效应晶体管 开关 脉冲 光电二极管
文件: 总10页 (文件大小:157K)
中文:  中文翻译
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STL15N3LLH5  
N-channel 30 V, 0.0045 , 15 A, PowerFLAT™ (3.3 x 3.3)  
STripFET™ V Power MOSFET  
Preliminary Data  
Features  
Type  
VDSS  
RDS(on)  
ID  
STL15N3LLH5  
30V  
<0.005415A (1)  
1. The value is rated according Rthj-pcb  
R  
* Q industry benchmark  
DS(on)  
g
Extremely low on-resistance R  
DS(on)  
Very low switching gate charge  
High avalanche ruggedness  
Low gate drive power losses  
PowerFLAT™(3.3x3.3)  
(Chip scale package)  
Applications  
Switching applications  
Figure 1.  
Internal schematic diagram  
Description  
th  
This product utilizes the 5 generation of design  
rules of ST’s proprietary STripFET™ technology.  
The lowest available R  
*Q , in this chip scale  
DS(on)  
g
package, makes this device suitable for the most  
demanding DC-DC converter applications, where  
high power density is to be achieved.  
Table 1.  
Device summary  
Order code  
STL15N3LLH5  
Marking  
Package  
Packaging  
15N3LLH5  
PowerFLAT™ (3.3 x 3.3)  
Tape and reel  
August 2008  
Rev 1  
1/10  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
10  
Contents  
STL15N3LLH5  
Contents  
1
2
3
4
5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
2/10  
STL15N3LLH5  
Electrical ratings  
1
Electrical ratings  
Table 2.  
Absolute maximum ratings  
Symbol  
Parameter  
Value  
30  
22  
Unit  
VDS  
VGS  
Drain-source voltage (VGS = 0)  
Gate-source voltage  
V
V
(1)  
ID  
Drain current (continuous) at TC = 25 °C  
Drain current (continuous) at TC=100 °C  
Drain current (pulsed)  
15  
9.3  
60  
50  
2
A
(1)  
ID  
A
(2)  
IDM  
A
(3)  
PTOT  
Total dissipation at TC = 25 °C  
Total dissipation at TC = 25 °C  
Derating factor  
W
(1)  
PTOT  
W
0.4  
W/°C  
TJ  
Operating junction temperature  
storage temperature  
-55 to 150  
°C  
Tstg  
1. The value is rated according Rthj-pcb  
2. Pulse width limited by safe operating area.  
3. The vaule is rated according Rthj-c  
Table 3.  
Thermal resistance  
Symbol  
Parameter  
Value  
Unit  
Rthj-case  
Thermal resistance junction-case (drain)  
Thermal resistance junction-pcb  
Thermal resistance junction-pcb  
2.5  
°C/W  
°C/W  
°C/W  
(1)  
Rthj-pcb  
42.8  
63.5  
(2)  
Rthj-pcb  
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec  
2. Steady state  
3/10  
Electrical characteristics  
STL15N3LLH5  
2
Electrical characteristics  
(T  
=25°C unless otherwise specified)  
CASE  
Table 4.  
On/off states  
Symbol  
Parameter  
Test conditions  
Min.  
Typ.  
Max.  
Unit  
Drain-source breakdown  
voltage  
V(BR)DSS  
ID = 250 µA, VGS= 0  
30  
V
V
DS = Max rating,  
1
µA  
µA  
Zero gate voltage drain  
current (VGS = 0)  
IDSS  
VDS = Max rating @125 °C  
10  
Gate body leakage current  
(VDS = 0)  
IGSS  
VGS  
=
22 V  
±100  
nA  
V
VGS(th)  
RDS(on)  
VDS= VGS, ID = 250 µA  
Gate threshold voltage  
1
2.5  
VGS= 10 V, ID= 7.5 A  
VGS= 4.5 V, ID= 7.5 A  
0.0045 0.0054  
0.006 0.0075  
Static drain-source on  
resistance  
Table 5.  
Dynamic  
Symbol  
Parameter  
Test conditions  
Min. Typ.  
Max.  
Unit  
Ciss  
Coss  
Crss  
Input capacitance  
1500  
295  
39  
pF  
pF  
pF  
VDS =25 V, f=1 MHz,  
VGS=0  
Output capacitance  
Reverse transfer  
capacitance  
Qg  
Qgs  
Qgd  
VDD=15 V, ID = 15 A  
VGS =4.5 V  
Total gate charge  
Gate-source charge  
Gate-drain charge  
12  
4
nC  
nC  
nC  
4.7  
(see Figure 3)  
f=1 MHz Gate DC Bias = 0  
Test signal level = 20 mV  
Open drain  
RG  
Gate input resistance  
0.5  
1.5  
2.5  
4/10  
STL15N3LLH5  
Electrical characteristics  
Table 6.  
Switching times  
Symbol  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
td(on)  
tr  
td(off)  
tf  
Turn-on delay time  
Rise time  
9.3  
14.5  
22.7  
4.5  
ns  
ns  
ns  
ns  
VDD=15 V, ID= 7.5 A,  
RG=4.7 , VGS=4.5 V  
(see Figure 2)  
Turn-off delay time  
Fall time  
Table 7.  
Source drain diode  
Symbol  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
ISD  
Source-drain current  
15  
60  
A
A
V
(1)  
Source-drain current (pulsed)  
Forward on voltage  
ISDM  
(2)  
ISD=15 A, VGS=0  
ISD=15 A,  
1.1  
VSD  
trr  
Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
25  
17.5  
1.4  
ns  
nC  
A
di/dt = 100 A/µs,  
Qrr  
VDD=20 V, Tj=150 °C  
IRRM  
(see Figure 7)  
1. Pulse width limited by safe operating area  
2. Pulsed: pulse duration=300µs, duty cycle 1.5%  
5/10  
Test circuit  
STL15N3LLH5  
3
Test circuit  
Figure 2. Switching times test circuit for  
resistive load  
Figure 3. Gate charge test circuit  
Figure 4. Test circuit for inductive load  
switching and diode recovery times  
Figure 5. Unclamped inductive load test  
circuit  
Figure 6. Unclamped inductive waveform  
Figure 7. Switching time waveform  
6/10  
STL15N3LLH5  
Package mechanical data  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. These packages have a lead-free second level interconnect . The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering  
conditions are also marked on the inner box label. ECOPACK is an ST trademark.  
ECOPACK specifications are available at: www.st.com  
7/10  
Package mechanical data  
STL15N3LLH5  
PowerFLAT™ ( 3.3 x 3.3) mechanical data  
mm  
inch  
Typ  
Dim  
Min  
Typ  
Max  
Min  
Max  
A
A3  
b
0.950  
1.000  
0.037  
0.039  
0.200  
0.34  
0.008  
0.013  
0.123  
0.090  
0.123  
0.067  
0.025  
0.0157  
0.0196  
0.29  
3.200  
2.24  
0.39  
3.400  
2.34  
0.011  
0.126  
0.088  
0.086  
0.065  
0.015  
0.134  
0.092  
0.1338  
0.069  
D
3.300  
2.29  
D2  
E
2.20  
3.30  
3.40  
E2  
e
1.660  
1.710  
0.650  
0.40  
1.760  
L
L1  
0.45  
0.50  
0.55  
0.017  
0.021  
8/10  
STL15N3LLH5  
Revision history  
5
Revision history  
Table 8.  
Date  
25-Aug-2008  
Document revision history  
Revision  
Changes  
1
First release  
9/10  
STL15N3LLH5  
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10/10  

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