STLS2F02_技术文档

STLS2F02

Loongson 2F

high performance 64-bit superscalar MIPS^®microprocessor

Preliminary Data

Features

■ 64-bit superscalar architecture

■ 900 MHz clock frequency

■ Single/double precision floating-point units

■ New streaming multimedia instruction set

support (SIMD)

■ 64 Kbyte instruction cache, 64 Kbyte data

HFCBGA452 (27x27x2.9mm)

cache, on-chip 512 Kbyte unified L2 cache

■ On chip DDR2-667 and PCI-X controller

The memory hierarchy is composed by the first

level of 64 Kbyte 4-way set associative caches for

instructions and data, the second level of

512 Kbyte unified 4-way set associative cache

and the memory management unit with table

lookside buffer.

■ 4 W @ 900 MHz power consumption:

– Best in class for power management

– Voltage/frequency scaling

– Standby mode support

– L2 cache disable/enable option

The Loongson microprocessor family is the

outcome of a successful collaboration started in

2004 between STMicroelectronics and the

Institute of Computing Technology, part of the

Chinese Academy of Science. Loongson

microprocessors were co-developed by

STMicroelectronics and the Institute of

Computing Technology to address all the

applications requiring high level of performance

and low power dissipation.

■ Leading edge 90 nm process technology

■ 27x27 heat spreader flip-chip BGA package

■ MIPS based (compatible with MIPSIII)

instruction set

Description

The STLS2F02 is a MIPS based 64-bit

superscalar microprocessor, able to issue four

instructions per clock cycle among six functional

units: two integer, two single/double-precision

floating-point, one 64-bit SIMD and one load/store

unit.

Compared to the STLS2E02 processor, the

STLS2F02 has an enhanced architecture

providing higher performances, reduced power

consumption, integrated DDR2 memory controller

and PCI-X bus interface.

The micro architecture is organized with nine

stages of pipeline and support of dynamic branch

prediction.

Table 1.

Device summary

Order code

Package

HFCBGA452 (27x27x2.9 mm)

Packing

STLS2F02

Tray

August 2008

Rev 1

1/49

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

STLS2F02

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Interface signal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PCI bus interface signal components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DDR2 SDRAM interface signal components . . . . . . . . . . . . . . . . . . . . . . 10

Local bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Initialization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Test and control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.10 Supply and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3

IO bus interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1

3.2

3.3

3.4

PCI interface characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Host and agent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PCI bus arbitrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

System interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4.1

3.4.2

Single processor system connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Multiprocessor system connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5

3.6

Local bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4

DDR2 SDRAM controller interface description . . . . . . . . . . . . . . . . . . 21

4.1

4.2

4.3

4.4

DDR2 SDRAM controller features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DDR2 SDRAM read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DDR2 SDRAM write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DDR2 SDRAM parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4.1

4.4.2

4.4.3

Memory initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Parameter descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Parameter formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/49

STLS2F02

Contents

4.5

DDR2 SDRAM sample mode configuration . . . . . . . . . . . . . . . . . . . . . . . 36

5

6

Initialization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.1

6.2

6.3

6.4

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Recommended operation environment . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7

8

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1

7.2

Thermal resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Reflow temperature to time curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Pin arrangement and package information . . . . . . . . . . . . . . . . . . . . . 44

8.1

Pin arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10

3/49

List of tables

STLS2F02

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PCI bus signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DDR2 SDRAM controller interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Local bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Initialization interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

JTAG interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Processor internal/external frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DDR internal/external frequency division factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Supply and ground signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDR SDRAM configuration parameter register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Recommended operating temperature, voltage and frequency . . . . . . . . . . . . . . . . . . . . . 38

DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DC parameters (JTAG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Clock parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Input setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Input setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Output delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

JTAG parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Reflow temperature parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4/49

STLS2F02

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Interface signal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

STLS2F02 uniprocessor system connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

STLS2F02 multiprocessor system connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Local bus read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Local bus write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DDR2 SDRAM row/column address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DDR2 SDRAM read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DDR2 SDRAM write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. Initialization process when in main bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11. Reflow temperature to time curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12. Pin arrangement (left-hand side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 13. Pin arrangement (middle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 14. Pin arrangement (right-hand side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 15. HFCBGA452 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . 47

5/49

Introduction

STLS2F02

1

Introduction

STLS processors are based on the Loongson CPU architecture licensed by

STMicroelectronics from the Institute of Computing Technology (ICT), which is part of the

Chinese Academy of Science. The STLS family contains 64-bit high-end processors for

applications requiring high levels of performance and efficiency in terms of cost, power

consumption and area.

The Loongson CPU architecture is compatible in user mode at the MIPSIII level of the

MIPS64-bit architecture.

This microprocessor achieves a leading position in the MIPS family for its combination of

multiple features, including high clock frequency, out-of-order superscalar execution and

ability to run single-instruction-multiple data (SIMD).

STLS processors implement a superscalar, out-of-order execution pipeline with dynamic

branch prediction and non-blocking cache.

Figure 1.

Block diagram

Commit Bus

Reorder Queue

Writeback Bus

Branch Bus

BRQ

ROQ

BTB

Map Bus

D-Cache

64KB

ALU1

ALU2

AGU

Integer

Register

File

Fix

RS

BHT

ITLB

CP0

Queue

Floating

Point

FPU1

FPU2

Float

RS

TLB

Register

File

I-Cache

64KB

Refill Bus

Miss

Queue

Writeback

Queue

Cache Interface

L2 cache

DDR2 Controller

333MHz DDR

AXI Crossbar

IO Controller

AC00117

133MHz PCIX Local IO GPIO, INT

6/49

STLS2F02

Introduction

The instruction pipeline allows fetch and coding of four instructions per cycle and dynamic

issue of the decoded instructions to five fully-pipelined function components.

The STLS2F02 uses out-of-order execution and an aggressive memory hierarchy design to

maximize pipeline efficiency.

Out-of-order execution is accomplished with a combination of register renaming, dynamic

scheduling, and branch prediction techniques. The result is fewer pipeline stalls caused by

WAR (write after read) and WAW (write after write) hazards, RAW (read after write) hazards,

and control hazards. The STLS2F02 has a 64-entry physical register file for fixed- and

floating-point register renaming, a 16-entry fixed-point reservation station, and a 16-entry

floating-point reservation station that is responsible for out-of-order instruction issuing. A 64-

entry ROQ (reorder queue) ensures that out-of-order executed instructions are committed in

the program order. For precise branch prediction, a 16-entry BTB (branch target buffer), a

4K-entry BHT (branch history table), a 9-bit GHR (global history register), and a 4-entry

RAS (return address stack) are used to record branch history information.

The STLS2F02 memory hierarchy is also engineered for high performance. There is a 64

Kbyte instruction cache, a 64 Kbyte data cache, and a 512 Kbyte level-two cache, all four-

way set associative. The on-chip DDR memory allows the STLS2F02 to achieve high

memory bandwidth with low latency. The fully associative translation lookahead buffer (TLB)

has 64 entries, each mapping an odd and even page. A 24-entry memory access queue

contains a content-addressable memory for dynamic memory disambiguation and allows

the STLS2F02 to implement out-of-order memory access, non-blocking cache, load

speculation, and store forwarding.

The STLS2F02 has two fixed-point functional units, two floating-point functional units, and

one memory access unit. The floating-point units can also execute 32-bit or 64-bit fixed-

point instructions and 8-bit or 16-bit SIMD fixed-point instructions through extension of the

fmt field of the floating-point instructions. The SIMD unit extends the STLS2E02 with new

XX SSE2 type instructions.

The basic pipeline stages of the STLS2F02 include instruction fetch, pre-decode, decode,

register rename, dispatch, issue, register read, execution, and commit.

The STLS2F02 device:

●

is manufactured in ST 90 nm CMOS technology.

●

is an evolution of the STLS2E02 with enhanced I/O and memory accessing bandwidth

and a software working frequency changing scheme.

●

has a standard 32-bit PCI/PCI-X interface, a standard 64-bit DDR2 interface, an 8/16-

bit local IO interface, a 4-bit GPIO interface.

achieves a higher memory accessing bandwidth by utilizing a 64-bit DDR2 memory

controller.

Compared to its predecessor, the STLS2F02 provides better power management ability by

using a software manageable working frequency changing scheme. The operating system

can use this feature to change the processor frequency according to the workload.

The STLS2F02 integrates a video accelerate module in its write data path to the PCI/PCI-X

controller. Coupled with software drivers, the video accelerate module can transfer YUV

format video data to RGB format and zoom automatically. This greatly reduces the

processor's workload when the system utilizes a simple VGA controller.

The cores are centered on a 2x2 AXI cross bar with 128-bit width data bus. The CPU core

and PCI/PCI-X slave takes up two master ports, and the DDR2 controller one slave port. All

other modules including the PCI/PCI-X master share one slave port.

7/49

Interface description

STLS2F02

2

Interface description

2.1

Note:

Interface signal block diagram

The STLS2F02interface signals are shown in Figure 2.

The arrow indicates signal directions, for example input, output or bi-direction.

Figure 2.

Interface signal block diagram

SYSCLK

MEMCLK

PCI AD[31:0]

PCI CBEn[3:0]

C

L

O

C

K

P

C

I

CLKSEL [9:0]

TESTCLK

PCI REQ [6:1]

PCI GNT [6:1]

PCI REQ [0]

PCI CLK

I

N

T

E

R

F

A

C

E

PCI GNT [0]

PCI PAR

I

NMIn

N

T

E

R

U

P

T

INTn [3:0]

PCI PERR

PCI IRQn [3:0]

GPIO [3:0]

PCI SERR

PCI FRAMEn

PCI IRDYn

PCI TRDYn

PCI DEV SELn

PCI STOPn

PCI ID SEL

S

I

G

N

A

L

TCK

TDI

J

T

A

G

TDO

TMS

TRST

S

L

O

C

A

L

LIO AD [15:0]

LIO A [7:0]

DDR2 DQ[63:0]

DDR2 CB[7:0]

Loongson 2F

LIO C Sn

LIO ROMC Sn

LIO WRn

D

R

2

DDR2 DQ Sp[8:0]

DDR2 DQ Sn[8:0]

B

U

S

D

R

A

LIO RDn

LIO ADLOCK

LIO DIR

DDR2 A[14:0]

S

I

G

N

A

L

DDR2 DQM[8:0]

M

DDR2 CKp[5:0]

DDR2 CKn[5:0]

DDR2 CKE[3:0]

DDR2 ODT[3:0]

DDR2 SC Sn[3:0]

I

LIO DEN

N

T

E

R

F

A

C

E

S

SYSRESETn

PCI RESETn

I

N

I

T

DDR2 BA[2:0]

DDR2 RASn

PCI CONFIG [7:0]

S

I

G

N

A

L

T

E

S

T

DDR2 CASn

TEST CTRL [7:0]

PLLCLOCK0

DDR2 WEn

&

DDR2 GATEO[3:0]

C

O

N

T

S

DDR2 GATEI[3:0]

PLLCLOCK1

R

O

L

8/49

STLS2F02

Interface description

2.2

PCI bus interface signal components

The STLS2F02 PCI bus signals include:

●

32-bit address data bus

4-bit command data ID bus

14-bit bus arbitrator

7-bit interface control

2-bit error report signals

The STLS2F02 PCI bus signals are shown in Table 2.

Table 2.

Name

PCI bus signals

Input/output

Description

PCI_AD[63:0]

PCI_CBEn[7:0]

PCI_PAR

I/O

I

PCI address/data bus

PCI command/byte

Address/data parity check signal

External request

PCI_REQn[6:1]

PCI_REQn[0]

PCI_GNT[6:1]

I/O

O

External request input/request output to external arbiter

PCI bus grant to external device

PCI bus grant to external device / grant input from

external arbiter

PCI_GNT[0]

I/O

PCI_FRAMEn

PCI_IRDYn

I/O

PCI bus cycle frame

PCI initiator ready

PCI target ready

PCI stop

PCI_TRDYn

PCI_STOPn

PCI_DEVSELn

PCI device select

9/49

Interface description

STLS2F02

2.3

DDR2 SDRAM interface signal components

The STLS2F02 includes a built-in memory controller fully compatible with DDR2 SDRAM

industry standard (JESD79-2B). These signals include:

●

72-bit bidirectional data bus (ECC included)

9-bit bidirectional data strobe differential signal (ECC included)

9-bit data mask signal (ECC included)

15-bit address bus

7-bit bank and chip select signal

6-bit differential clock

4-bit clock enable

3-bit command bus

4-bit delay sample input/output signal

4-bit ODT (on die termination) signal

The STLS2F02 DDR2 SDRAM controller signals are shown in Table 3.

Table 3.

Name

DDR2 SDRAM controller interface signals

Input/output

Description

DDR2_DQ[63:0]

DDR2_CB[7:0]

DDR2_DQSp[8:0]

DDR2_DQSn[8:0]

DDR2_DQM[8:0]

DDR2_A[14:0]

IO

O

I

DDR2 SDRAM data bus

DDR2 SDRAM data ECC data bus

DDR2 SDRAM data strobe (ECC included)

DDR2 SDRAM data mask (ECC included)

DDR2 SDRAM address bus

DDR2_BA[2:0]

DDR2_WEn

DDR2 SDRAM bank address signal

DDR2 SDRAM write enable

DDR2_CASn

DDR2 SDRAM column select enable

DDR2 SDRAM row select enable

DDR2 SDRAM chip select

DDR2_RASn

DDR2_SCSn[3:0]

DDR2_CKE[3:0]

DDR2_CKp[5:0]

DDR2_CKn[5:0]

DDR2_GATEI[3:0]

DDR2_GATEO[3:0]

DDR2_ODT[3:0]

DDR2 SDRAM clock enable

DDR2 SDRAM phase clock output

DDR2 SDRAM phase inversion clock output

DDR2 SDRAM delay sample input signal

DDR2 SDRAM delay sample output signal

DDR2 SDRAM on die termination signal

O

10/49

STLS2F02

Interface description

2.4

Local bus signals

The local bus provides a simple bus interface for system boot ROM and IO device. The

interface is designed for chip-connect simplicity.

The local bus signals are shown in Table 4.

Table 4.

Name

Local bus signals

Input/output

Description

Local IO address and data bus

LIO_AD[15:0]

I/O

(when ADLOCK valid output the most significant 16-bit)

Lowest significant 8-bit address bus

Local IO chip select

LIO_A[7:0]

LIO_CSn

O

LIO_ROMCSn

LIO_WRn

Local IO ROM chip select

Local IO write enable

LIO_RDn

Local IO read enable

LIO_ADLOCK

LIO_DIR

Local IO address lock

Local IO direction

LIO_DEN

Local IO device enable

11/49

Interface description

STLS2F02

2.5

Initialization signals

Table 5 details the initialization signals.

Table 5.

Name

Initialization interface signals

Input/output

Description

System reset. Low state of the signal must be maintained

more than one SYSCLK period. It can be asynchronous

to SYSCLK

SYSRESETn

PCI_RESETn

I

I/O

PCI interface reset

PCI configuration

7

undefined

6:5

PCIX BUS speed selection

PCIX BUS mode

Master mode

4

3

2

Start from PCI

1

External PCI arbitration

16-bit starting ROM

0

PCI_CONFIG

I

Note:

6

0

1

5

0

1

0

1

4

0

1

PCIX BUS mode

PCI 33/66

PCIX 66

PCIX 100

PCIX 133

The STLS2F02 processor includes two reset signals:

●

SYSRESETn: This reset signal is the only way to reset whole STLS2F02 processor.

SYSCLK and MEMCLK must provide stable clock when SYSRESETn is valid. The

width of SYSRESETn should be more than one clock period. Internal reset-control

begins to reset the internal logic when the reset signal is invalid. The internal reset is

finished after 64K SYSCLK cycle. The reset exception vector can then be executed.

●

PCI_RESETn: This signal works as an output when the processor works as a system

main bridge. The reset of PCIX devices in the system must be controlled by this signal.

When the processor works as a PCI/PCIX device, the signal works as reset input to the

PCI interface of the processor.

Note:

Resetting the PCI interface when a process is running may cause the processor to stop

working.

PCI_CONFIG defines the working mode of the processor interface. It must be stable during

system reset, so that software can read this value from an internal register after system start

up. The PCI address of the first instruction is 0x1FC0 0000 when system start from PCI is

configured. Otherwise the first instruction is fetched from address 0 of local bus ROM.

12/49

STLS2F02

Interface description

2.6

Interrupt signals

The STLS2F02 processor supports up to 12 external interrupts and one non-maskable

interrupt (NMI). There are 4 PCI interrupt signals, 4 special interrupt signals and 4

configurable GPIO interrupt. There are also 3 internal interrupts, two PCI bus error report

signals and one DDR2 control interrupt. When an interrupt occurs, the processor handles

the exception. Table 6 details the interrupt signals.

Table 6.

Name

Interrupt interface signals

Input/output

Description

4 external interrupt signals. OR operations are performed

on these signals with interrupt register from bit 5 to bit 2

separately

INTn[3:0]

NMIn

I

NMI. An OR operation is performed on the NOT-value of

this signal and the interrupt register’s 6th bit

These interrupts should be enabled in the interrupt

controller and can be configured as different active power

level and different trigger mode. These interrupts could be

routed to interrupt register bit 0/1

GPIO[3:0]

I/O

I

These interrupts should be enabled in the interrupt

controller and low active. These interrupts could be routed

to interrupt register bit 0/1

PCI_IRQ[3:0]

PCI bus parity error, high pulse active. These interrupts

could be routed to interrupt register bit 0/1

PCI_PERR

PCI_SERR

I/O

PCI bus error, high pulse active. These interrupts could be

routed to interrupt register bit 0/1

2.7

JTAG signals

The STLS2F02 provides a JTAG-compliant boundary scan interface. The JTAG interface is

particularly suitable for testing the processor pins for connectivity. Table 7 details the JTAG

signals.

Table 7.

Name

JTAG interface signals

Input/output

Description

JTAG serial scan data input

TDI

I

TDO

O

JTAG serial scan data input

JTAG command, indicating that the input serial data is a

command.

TMS

TCK

I

JTAG serial scan clock

2.8

Test and control signals

On the STLS2F02 chip, the test signals are only used for chip physical test, for example

scan chain test. When the chip works normally, these signals are set invalid (to 1).

13/49

Interface description

STLS2F02

2.9

Clock signals

Table 8 details the STLS2F02 chip clocks. The processor has three system input clock

signals. (SYSCLK, MEMCLK and PCI_CLK). TESTCLK is only used for chip test.

The CPU core clock and DDR2 control clock are generated separately by the PLL using

SYSCLK and MEMCLK. The frequency division is controlled by CLKSEL. For further

information about the division factor, see Table 9 and Table 10. MEMCLK frequency can

also be configured through control register CR88 except pins CLKSEL [9:5]. Please refer to

register CR88 in the STLS2F02 user manual.

Table 8.

Name

Clock signals

Input/output

Description

System input clock, which drives the built-in PLL to

generate core clock. It also used as clock of system reset

circuit

SYSCLK

I

DDR2 controller input clock, which is used by the built-in

PLL to generate DDR2 control clock

MEMCLK

I

PLL frequency division control signal of core clock, see

Table 9

CLKSEL[4:0]

PLL frequency division control signal of DDR2 controller

clock, see Table 10

CLKSEL[9:5]

PCI_CLK

I

Clock for PCI and local bus interface.

Table 9.

Processor internal/external frequency configuration

Multi.

factor

Input frequency

range (MHz)

Multi.

factor

Input frequency

range (MHz)

CLKSEL[4:0]

11xxx

10000

10001

10010

10011

10100

10101

10110

10111

01000

01001

01010

01011

1

2.25

2.5

2.75

3

-

88.9~177.8

80.0~160.0

72.7~145.5

66.7~133.3

61.5~123.1

57.1~114.3

53.3~106.7

50.0~100.0

88.9~177.8

80.0~160.0

72.7~145.5

66.7~133.3

01100

01101

01110

01111

00000

00001

00010

00011

00100

00101

00110

00111

6.5

7

61.5~123.1

57.1~114.3

53.3~106.7

50.0~100.0

88.9~177.8

80.0~160.0

72.7~145.5

66.7~133.3

61.5~123.1

57.1~114.3

53.3~106.7

50.0~100.0

7.5

8

3.25

3.5

3.75

4

9

10

11

12

13

14

15

16

4.5

5

5.5

6

14/49

STLS2F02

Interface description

Table 10. DDR internal/external frequency division factor

Multi.

factor

Input frequency

range (MHz)

Multi.

factor

Input frequency

range (MHz)

CLKSEL[9:5]

11000

11001

11010

11011

11100

11101

11110

11111

10000

10001

10010

10011

-

1.125

1.25

1.375

1.5

88.9~177.8

80.0~160.0

72.7~145.5

66.7~133.3

61.5~123.1

57.1~114.3

53.3~106.7

50.0~100.0

88.9~177.8

80.0~160.0

72.7~145.5

66.7~133.3

-

10100

10101

10110

10111

01000

01001

01010

01011

01100

01101

01110

01111

00xxx

3.25

3.5

3.75

4

61.5~123.1

57.1~114.3

53.3~106.7

50.0~100.0

88.9~177.8

80.0~160.0

72.7~145.5

66.7~133.3

61.5~123.1

57.1~114.3

53.3~106.7

50.0~100.0

-

1.625

1.75

1.875

2

4.5

5

5.5

6

2.25

2.5

6.5

7

2.75

3

7.5

8

-

1

15/49

Interface description

STLS2F02

2.10

Supply and ground

See Table 11 for supply and ground signals of the STLS2F02.

Table 11. Supply and ground signals

Name

Input/output

Description

1.2 V CPU core voltage

Vdd

Gnd

PWR

GND

PWR

GND

PWR

I

1.2 V CPU core ground

Vdde1v8

1.8 V DDR2 power supply

Gnde

1.8 V DDR2 and 3.3V IO ground

3.3 V IO power supply

Vdde3v3

DDR2_VREF

Pll_vdd_1

0.9 V DDR reference voltage input

1.0 V PLL 1 digital power supply

1.0 V PLL 1 digital ground

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

I

Pll_gnd_1

Pll_vdd_0

1.0 V PLL 0 digital power supply

1.0 V PLL 0 digital ground

Pll_gnd_0

Pllio_vdde1v8

Pllio_gnde

Pllio_vdd

1.8 V PLL IO power supply

1.8 V PLL IO ground

1.2 V PLL IO power supply

1.2 V PLL IO ground

Pllio_gnd

Pll_vdde1v8_1

Pll_gnde_1

Pll_vdde1v8_0

Pll_gnde_0

Comp1v8_gnd

Comp1v8_resistor

1.8 V PLL 1 analog power supply

1.8 V PLL 1 analog ground

1.8 V PLL 0 analog power supply

1.8 V PLL 0 analog ground

Compensation reference current ground

Compensation external resistor input

16/49

STLS2F02

IO bus interface description

3

IO bus interface description

The STLS2F02 processor IO interface consists of the PCI bus and a local bus. The PCI bus

is used to for generic peripheral device interface, while the local bus a simple interface for

processor boot or debug.

3.1

3.2

PCI interface characteristic

The PCI interface features are as follows:

●

PCI 2.3 and PCIX 1.0 compatible

Support PCI 66 MHz and PCIX133 MHz

Support dual address cycle for 64-bit addressing

Support 8 outstanding master request in PCIX mode

Support 4 delay-split read request in PCIX mode

Host and agent mode

The STLS2F02 PCI interface can work in host mode or agent mode, depending on the initial

value of signal PCI_CONFIG.

When the processor works in host mode, the interface initializes the bus device according to

the value of PCI_CONFIG[6:4]. In this case, PCI_IDSEL can be connected directly to GND.

When the processor works in agent mode, the initial value of the PCI bus defines the

working-mode of the interface. In host mode, on the system main board, the value of

PCI_CONFIG[6:4] should be set according to the ability of bus device. (Refer also to the

PCIX 1.0 standard)

3.3

3.4

PCI bus arbitrator

The PCI/PCIX bus arbitrator built into the STLS2F02 supports up t o 7 external masters. The

arbitration rules are two-level round robin scheduling. The level of each request is

determined by software configuration. The bus is granted to insert a dummy cycle during

switching. Bus parking can be configured as the last master or any specified master.

The internal request/grant wire of the interface can be set to connect to the number 0

request/grant wire by PCI_CONFIG [1] so that the external bus arbitrator can be used.

System interface connection

The STLS2F02 processor can be easily implemented in uniprocessor system. Since no

multi-processor cache coherence protocol is supported in the PCI interface, the cache

coherence should be managed by software in a multiprocessor system.

17/49

IO bus interface description

STLS2F02

3.4.1

Single processor system connection

Figure 3.

STLS2F02 uniprocessor system connection

PCI Dev

PCI Bus

Loongson 2F

PCI_REQ

PCI_GNT

Boot Rom

Local Bus

3.4.2

Multiprocessor system connections

Figure 4.

STLS2F02 multiprocessor system connections

PCI_REQn

PCI_GNTn

Loongson 2F

PCI Bus

I/O

Chipset

PCI_REQn

PCI_GNTn

Loongson 2F

PCI Bus

18/49

STLS2F02

IO bus interface description

3.5

Local bus description

The local bus is a simple peripheral interface. It is mainly used to connect to boot ROM.

There are two chip select signals, and a corresponding configurable data width and access

delay. The read and writing timings are shown in Figure 5 and Figure 6. When the data

width is 16-bits, the output address can be generated by shifting the physical address right

one bit.

Figure 5.

Local bus read timing

pciclk

lioden

liodir

lioaddr

addr[7:0]

addr[7:0]+1

lioad

addr[23..8]

data

lioadlock

liocs

liord

19/49

IO bus interface description

Figure 6. Local bus write timing

STLS2F02

pciclk

lioden

liodir

lioaddr

addr[7:0]

addr[7:0]+1

lioad

addr[23:8]

data_0

data_1

lioadlock

liocs

liowr

3.6

Interrupt handling

An interrupt controller is built into the STLS2F02 processor to handle internal and external

interrupt. The 4 most significant bits of the interrupt INTn[5:0] in L2E are still used as

interrupts in the STLS2F02, while the other two bits are used for new interrupts, such as

PCI_IRQ and GPIO.

Interrupt between processors is handled as follows:

1. The interrupt initiator writes the dedicated interrupt register in the chipset.

2. Upon receiving the request for interrupt transmission, the chipset requests the target

processor for an interrupt.

3. The processor handles the request in the same way as the previous L2E.

20/49

STLS2F02

DDR2 SDRAM controller interface description

4

DDR2 SDRAM controller interface description

The STLS2F02 integrates a built-in memory controller compliant with DDR2 SDRAM

standard (JESD79-2B). The STLS2F02 provides JESD79-2B-compliant read/write memory

operations.

4.1

DDR2 SDRAM controller features

The STLS2F01 CPU supports up to 4 physical memories by using two DDR SDRAM chip

select signals, with an 18-bit address bus (15-bit row/column address and 3-bit logic bank

37

bus). The maximum address space is 128 Gbytes (2 bytes).

This device supports all the JESD79-2B-compatible memory chips. The DDR2 controller

parameters can be set to support specific memory chip type. The maximum number of chip

selection (CS_n) is 2-bit. The maximum width of row address (RAS_n) is 15-bit, and the

maximum width of column address (CAS_n) is 14-bit. And there is 3-bit logic bank bus

(BANK_n).

For example, in the 4 Gbyte address space configuration of 2-bit CS_n, 3-bit BANK_n,

12-bit RAS_n and 12-bit CAS_n, the physical memory address CPU required can be

translated into row/column address as shown in Figure 7: DDR2 SDRAM row/column

address translation.

Figure 7.

DDR2 SDRAM row/column address translation

36

32 31

30 29

18 17

15 14

3 2

0

CS_n

2

RAS_n

12

BANK_n

CAS_n

12

Byte_enable

3

5

3

The built-in memory controller IC receives only memory read/write requests from a

processor or external device. The controller IC is in slave state whenever memory are read

or written.

A dynamic page management policy is implemented on the integrated memory controller.

For one access to memory, the controller selects open page/close page strategies on a

hardware circuit, without software designers’ intervention. The memory controller features:

●

Full pipelining support to command and read/write data of interface

Increasing bandwidth by merging and sorting memory command

Modify fundamental parameters through the configuration of register read/write ports

Built-in delay compensation circuit (DCC), it is used to send/receive data reliably

1-bit and 2-bit error detection, 1-bit error correction by error correcting-code (ECC)

Frequency: 133 MHz to 333 MHz.

21/49

DDR2 SDRAM controller interface description

STLS2F02

4.2

DDR2 SDRAM read protocol

As shown in Figure 8 DDR2 SDRAM read protocol, the command (CMD) includes RAS_n,

CAS_n and WE_n. When a read request happens, RAS_n=1,CAS_n=0,and WE_n=1.

Figure 8.

DDR2 SDRAM read protocol

CAS latency = 3, read latency = 3, burst length = 8

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK/CK

CMD

READ A

NOP

≤ t_DQSCK

DQS/DQS

CL=3

RL=3

DQ

S

DOUT

A1

A2

A3

A4

A5

A6

A7

22/49

STLS2F02

DDR2 SDRAM controller interface description

4.3

DDR2 SDRAM write protocol

As shown in Figure 9 DDR2 SDRAM write protocol, the command (CMD) includes RAS_n,

CAS_n and WE_n. When a write request happens, RAS_n=1, CAS_n=0,and WE_n=0.

Unlike a read transaction, DQM is used to identify the write mask. In other words, the

number of written bytes is needed. DQM is synchronous with DQS.

Figure 9.

DDR2 SDRAM write protocol

CAS latency = 3, write latency = read latency = 2, burst length = 4

T0

T1

T2

T3

T4

T5

T6

T7

Tn

CK/CK

CMD

Bank A

Activate

WRITE A

NOP

Precharge

NOP

Completion of

the Burst Write

≤ t_DQS6

DQS/DQS

WL = RL - 1 = 2

≥ WR

≥ t

RP

DQ

S

DIN

A0

A1

A2

A3

4.4

DDR2 SDRAM parameters

Since different DDR2 SDRAMs may be used in a system, DDR2 SDRAM needs

configuration after power-on reset. The JESD79-2B standard defines the configuration

operations and procedure in detail. DDR2 is not available before the memory is initialized. In

STLS2F02-based systems, after the system motherboard is initialized, the DDR2 SDRAM

controller must configure the memory type before the memory is used. The configuration

parameters are written into the 29 64-bit registers corresponding to the physical address

0x0000 0000 0FFF FE00. In one register, single, multiple or partial parameter data can be

included. The configuration register and its parameters are shown in Table 12: DDR SDRAM

configuration parameter register format

Note:

Unused bits are reserved.

4.4.1

Memory initialization sequence

The memory initialization sequence is as follows:

1. System reset, aresetn signal is set to 0, all register content is set to its initial value

2. System reset release, aresetn signal is set to 1

3. Issue 64-bit write command to configuration register, all 29 registers are configured. If

register CTRL_03 is written in this step, the parameter of start should be set 0.

4. Issue 64-bit write command to register CTRL_03. Set the parameter of start to 1. The

memory controller then sends the initial instruction to memory automatically.

23/49

DDR2 SDRAM controller interface description

STLS2F02

4.4.2

Parameter descriptions

CONF_CTL_00 AP

The parameter determines whether the auto pre-charge function is enabled. If the function

is enabled, memory closes the page after each write/read instruction. If mass continuous

address operation happens, setting this parameter causes performance degradation.

CONF_CTL_00 CONCURRENTAP

This parameter determines whether the concurrent auto pre-charge function is enabled.

Most SDRAM vendors do not support this feature.

CONF_CTL_03 SREFRESH

This parameter sets the self refresh style. It must be set to 0 when returning from self

refresh.

CONF_CTL_07 CASLAT_LIN_GATE

This parameter controls the data sample of the memory controller when a read operation

returns. In general, It is equal to or less than half period of ACALAT_LIN. The value of

CASLAT_LIN is twice that of CAS.

CONF_CTL_15 DLL_INCREMENT

This parameter should not be set 0.

CONF_CTL_15 DLL_START_POINT

This parameter should not be set to 0 or 1 and should be less than 1.5 times the

DLL_LOCK_VALUE.

CONF_CTL_28 UB_DIMM

This parameter should be set to 1, when unbuffered DIMM(s) are used. It should be set 0

when SDRAM(s) are used.

24/49

STLS2F02

DDR2 SDRAM controller interface description

4.4.3

Parameter formats

Table 12. DDR SDRAM configuration parameter register format

Default

Parameters

Bits

Range

Description

value

CONF_CTL_00[31:0] Offset: 0x00

DDR2 667:0x00000101

Initiate auto-refresh when specified by

AUOT_REFRESH_MODE. WRITE-

ONLY

AREFRESH

24:24

0x0

0x0-0x1

Enable auto pre-charge mode of

controller

AP

16:16

8:8

0x0

0x0-0x1

Enable address collision detection for

command queue placement logic

ADDR_CMP_EN

Enable command aging in the

command queue, avoiding low priority

command hungry

ACTIVE_AGING

0:0

0x0

0x0-0x1

CONF_CTL_00[63:32] Offset: 0x00

DDR2 667:0x01000100

DDR2_SDRAM_MODE

56:56

48:48

0x0

0x0-0x1

DDRI or DDRII mode

Allow controller to issue cmds to other

banks while a bank is in auto pre-

charge. Note: most DDR2 DIMM

vendor do not support this feature

CONCURRENTAP

BANK_SPLIT_EN

0x0

0x0-0x1

Enable bank splitting for cmd queue

placement logic

40:40

32:32

0x0

0x0-0x1

Sets if auto-refresh occurs be at next

burst or next cmd boundary

AUTO_REFRESH_MODE

CONF_CTL_01[31:0] Offset: 0x10

DDR2 667:0x00010000

Disable auto-corruption of ECC when

un-correctable errors occur in R/M/W

operations.

ECC_DISBALE_W_UC_ERR

24:24

0x0

0x0-0x1

DQS_N_EN

16:16

8:8

0x0

0x0-0x1

Single-ended or differential dqs pins.

Enable the DLL bypass feature of the

controller.

DLL_BYPASS_MODE

Status of DLL lock coming out of

master delay. READ-ONLY

DLLLOCKREG

0:0

0x0

0x0-0x1

CONF_CTL_01[63:32] Offset: 0x10

DDR2 667:0x00100000

Force a write checks. Xor

FWC

56:56

48:48

0x0

0x0-0x1

XOR_CHECK_BITS with ecc code and

write to memory. WRITE_ONLY

Sets when write cmds are issued to

DRAM device.

FAST_WRITE

0x0

0x0-0x1

Allows user to interrupt memory

initialization to enter self-refresh mode.

ENABLE_QUICK_SREFRESH

EIGHT_BANK_MODE

40:40

32:32

0x0

0x0-0x1

Number of banks on the DRAM(s).

25/49

DDR2 SDRAM controller interface description

STLS2F02

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

CONF_CTL_02[31:0] Offset: 0x20

DDR2 667:0x00000000

Disable DRAM cmds until TDLL has

expired during initialization.

NO_CMD_INIT

24:24

16:16

0x0

0x0-0x1

Allow the controller to interrupt a

combined write cmd with auto pre-

charge with another write cmd.

INTRPTWRITENA

INTRPTREADA

Allow the controller to interrupt a

combined read with auto pre-charge

cmd with another read cmd.

8:8

0:0

0x0

0x0-0x1

Allow the controller to interrupt an auto

pre-charge cmd with another cmd.

INTRPTAPBURST

CONF_CTL_02[63:32] Offset: 0x20

PRIORITY_EN

DDR2 667:0x01000101

Enable priority for cmd queue

placement logic.

56:56

0x0

0x0-0x1

Disable clock enable and set DRAMs in

power-down state.

POWER_DOWN

PLACEMENT_EN

48:48

40:40

0x0

0x0-0x1

Enable placement logic for cmd queue.

Enable extra turn-around clock

between back-to-back reads/writes to

different chip selects.

ODT_ADD_TURN_CLK_EN

32:32

0x0

0x0-0x1

CONF_CTL_03[31:0] Offset: 0x30

DDR2 667:0x01000000

Enable read/write grouping for cmd

queue placement logic.

RW_SAME_EN

24:24

16:16

8:8

0x0

0x0-0x1

Enable registered DIMM operation of

the controller.

REG_DIMM_EN

REDUC

Enable the half datapath (32-bit)

feature of the controller.

Powerup via self-refresh instead of full

memory initialization.

PWRUP_SREFRESH_EXIT

0:0

CONF_CTL_03[63:32] Offset: 0x30

DDR2 667:0x01010000

Enable command swapping logic

SWAP_PORT_RW_SAME_EN

56:56

48:48

0x0

0x0-0x1

between commands of the same type

from the same port in execution unit.

Enable command swapping logic in

execution unit.

SWAP_EN

START

0x0

0x0-0x1

Initiate cmd processing in the

controller.

40:40

32:32

SREFRESH

0x0

0x0-0x1

Place DRAMs in self-refresh mode.

CONF_CTL_04[31:0] Offset: 0x40

DDR2 667:0x00010101

Write EMRS data to the DRAMs.

WRITE-ONLY

WRITE_MODEREG

24:24

0x0

0x0-0x1

26/49

STLS2F02

DDR2 SDRAM controller interface description

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

Allow controller to interrupt write bursts

to the DRAMs with a read cmd.

WRITEINTERP

TREF_ENABLE

16:16

8:8

0x0

0x0-0x1

Issue self-refresh cmds to the DRAMs

every TREF cycle.

0x0

Allow the controller to execute auto

pre-charge cmds before TRAS_MIN

expires.

TRAS_LOCKOUT

0:0

0x0-0x1

CONF_CTL_04[63:32] Offset: 0x40

DDR2 667:0x01000202

On-Die termination resistance setting

for all DRAM devices.

RTT_0

57:56

0x0

0x0-0x3

ECC error checking and correcting

control.

2’b00 – no ECC

CTRL_RAW

49:48

2’b01 – report error only, not corrected

2’b10 – no ECC device used

2’b11 – report and correct ECC error

AXI0_W_PRIORITY

AXI0_R_PRIORITY

41:40

33:32

0x0

0x0-0x3

Priority of write cmds from port 0.

Priority of read cmds from port 0.

CONF_CTL_05[31:0] Offset: 0x50

DDR2 667:0x04050202

Difference between number of column

pins available and number being used.

COLUMN_SIZE

CASLAT

26:24

18:16

10:8

1:0

0x0

0x0-0x7

0x0-0x3

Encoded CAS latency sent to DRAMs

during initialization.

Difference between number of addr

pins available and number being used.

ADDR_PINS

Set termination resistance in controller

pads.

RTT_PAD_TERMINATION

CONF_CTL_05[63:32] Offset: 0x50

Q_FULLNESS

DDR2 667:0x00000000

Quantity that determines cmd queue

58:56

0x0

0x0-0x7

full.

PORT_DATA

Type of error and access type that

caused the PORT data error. READ-

ONLY

bit 0 – Data Overflow. The wirte data

quantity exceeded the

Maximum_Byte_Request configured

option.

_ERROR_TYPE

50:48

0x0

0x0-0x7

bit 1 – Write data interleaved beyond

supported interleaving depth.

bit 2 – ECC 2-bit error.

27/49

DDR2 SDRAM controller interface description

STLS2F02

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

Type of cmd that caused and Out-of-

Range interrupt. READ-ONLY

OUT_OF_RANGE_TYPE

MAX_CS_REG

42:40

34:32

0x0

0x0-0x7

0x0-0x4

Maximum number of chip selects

available. READ-ONLY

0x4

CONF_CTL_06[31:0] Offset: 0x60

DDR2 667:0x03040203

TRTP

26:24

18:16

10:8

2:0

0x0

0x0-0x7

DRAM TRTP parameter in cycles.

DRAM TRRD parameter in cycles.

DRAM TEMRS parameter in cycles.

Minimum CKE pulse width.

TRRD

TEMRS

TCKE

CONF_CTL_06[63:32] Offset: 0x60

DDR2 667:0x0a040305

Location of the auto pre-charge bit in

the DRAM address.

APREBIT

59:56

0x0

0x0-0xF

WRLAT

TWTR

50:48

42:40

34:32

0x0

0x0-0x7

DRAM WRLAT parameter in cycles.

DRAM TWTR parameter in cycles.

DRAM TWR parameter in cycles.

TWR_INT

CONF_CTL_07[31:0] Offset: 0x70

DDR2 667:0x000F090A

Source ID associated with correctable

ECC event. READ-ONLY

ECC_C_ID

CS_MAP

27:24

19:16

11:8

3:0

0x0

0x0-0xF

Number of active chip selects used in

address decoding.

Adjusts data capture gate open by half

cycles.

CASLAT_LIN_GATE

Sets latency from read cmd send to

data receive from/to controller.

CASLAT_LIN

CONF_CTL_07[63:32] Offset: 0x70

MAX_ROW_REG

DDR2 667:0x00000400

Maximum width of memory address

bus. READ-ONLY

59:56

51:48

43:40

35:32

0xF

0xE

0x0

0x0-0xF

0x0-0xe

0x0-0xF

Maximum width of column address in

DRAMs. READ-ONLY

MAX_COL_REG

INITAREF

Number of auto-refresh cmds to

execute during DRAM initialization.

Source ID associated with the

uncorrectable ECC even. READ-ONLY

ECC_U_ID

CONF_CTL_08[31:0] Offset: 0x80

DDR2 667:0x01020408

ODT chip select 3 map for reads.

Determines which chip(s) have

termination when a read occurs on chip

3.

ODT_RD_MAP_CS3

27:24

0x0

0x0-0xF

28/49

STLS2F02

DDR2 SDRAM controller interface description

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

ODT chip select 2 map for reads.

Determines which chip(s) have

termination when a read occurs on chip

2.

ODT_RD_MAP_CS2

19:16

0x0

0x0-0xF

ODT chip select 1 map for reads.

Determines which chip(s) have

termination when a read occurs on chip

1.

ODT_RD_MAP_CS1

11:8

3:0

0x0

0x0-0xF

ODT chip select 0 map for reads.

Determines which chip(s) have

termination when a read occurs on chip

0.

ODT_RD_MAP_CS0

CONF_CTL_08[63:32] Offset: 0x80

ODT_WR_MAP_CS3

DDR2 667:0x01020408

ODT chip select 3 map for writes.

Determines which chip(s) have

termination when a write occurs on

chip 3.

59:56

51:48

43:40

35:32

0x0

0x0-0xF

ODT chip select 2 map for writes.

Determines which chip(s) have

termination when a write occurs on

chip 2.

ODT_WR_MAP_CS2

ODT_WR_MAP_CS1

ODT_WR_MAP_CS0

ODT chip select 1 map for writes.

Determines which chip(s) have

termination when a write occurs on

chip 1.

ODT chip select 0 map for writes.

Determines which chip(s) have

termination when a write occurs on

chip 0.

CONF_CTL_09[31:0]

Offset: 0x90

DDR2 667:0x00000000

Port number of cmd that caused the

PORT data error. READ-ONLY

PORT_DATA_ERROR_ID

27:24

19:16

0x0

0x0-0xF

Type of error and access type that

caused the PORT cmd error. READ-

ONLY)

PORT_CMD_ERROR_TYPE

Port number of cmd that caused the

PORT cmd error. READ-ONLY

PORT_CMD_ERROR_ID

11:8

3:0

0x0

0x0-0xF

Source ID of cmd that caused an Out-

of-Range interrupt. READ-ONLY

OUT_OF_RANGE_SOURCE_ID

CONF_CTL_09[63:32]

Offset: 0x90

DDR2 667:0x0000050b

OCD pull-up adjust setting for DRAMs

for chip select 0.

OCD_ADJUST_PUP_CS0

60:56

52:48

0x0

0x0-0x1F

OCD pull-down adjust setting for

DRAMs for chip select 0.

OCD_ADJUST_PDN_CS0

29/49

DDR2 SDRAM controller interface description

STLS2F02

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

TRP

TDAL

43:40

35:32

0x0

0x0-0xF

DRAM TRP parameter in cycles.

DRAM TDAL parameter in cycles.

CONF_CTL_10[31:0]

Offset: 0xA0

DDR2 667:0x3F130200

Initial value of master aging-rate

counter for cmd aging.

AGE_COUNT

29:24

0x0

0x0-0x3F

TRC

TMRD

20:16

12:8

4:0

0x0

0x0-0x1F

DRAM TRC parameter in cycles.

DRAM TMRD parameter in cycles.

DRAM TFAW parameter in cycles.

TFAW

CONF_CTL_10[63:32]

Offset: 0xA0

DDR2 667:0x1D1D1D3F

Fraction of a cycle to delay the dqs

DLL_DQS_DELAY_2

DLL_DQS_DELAY_1

62:56

54:48

0x0

0x0-0x7F

signal from the DRAMs for

dll_rd_dqs_slice 2 during reads.

Fraction of a cycle to delay the dqs

signal from the DRAMs for

0x0

0x0-0x7F

dll_rd_dqs_slice 1 during reads.

Fraction of a cycle to delay the dqs

signal from the DRAMs for

dll_rd_dqs_slice 0 during reads.

DLL_DQS_DELAY_0

46:40

37:32

0x0

0x0-0x7F

0x0-0x3F

Initial value of individual cmd aging

counters for cmd aging.

COMMAND_AGE_COUNT

CONF_CTL_11[31:0]

Offset: 0xB0

DDR2 667:0x1D1D1D1D

Fraction of a cycle to delay the dqs

DLL_DQS_DELAY_6

30:24

22:16

14:8

6:0

0x0

0x0-0x7F

signal from the DRAMs for

dll_rd_dqs_slice 6 during reads.

Fraction of a cycle to delay the dqs

signal from the DRAMs for

dll_rd_dqs_slice 5 during reads.

DLL_DQS_DELAY_5

DLL_DQS_DELAY_4

DLL_DQS_DELAY_3

Fraction of a cycle to delay the dqs

signal from the DRAMs for

dll_rd_dqs_slice 4 during reads.

Fraction of a cycle to delay the dqs

signal from the DRAMs for

dll_rd_dqs_slice 3 during reads.

CONF_CTL_11[63:32]

Offset: 0xB0

DDR2 667:0x507F1D1D

Fraction of a cycle to delay the clk_wr

signal in the controller.

WR_DQS_SHIFT

DQS_OUT_SHIFT

62:56

54:48

0x0

0x0-0x7F

Fraction of a cycle to delay the write

dqs signal to the DRAMs during writes.

Fraction of a cycle to delay the dqs

signal from the DRAMs for

DLL_DQS_DELAY_8

46:40

0x0

0x0-0x7F

dll_rd_dqs_slice 8 during reads.

30/49

STLS2F02

DDR2 SDRAM controller interface description

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

Fraction of a cycle to delay the dqs

signal from the DRAMs for

DLL_DQS_DELAY_7

38:32

0x0

0x0-0x7F

dll_rd_dqs_slice 7 during reads.

CONF_CTL_12[31:0]

Offset: 0xC0

DDR2 667:0x0E000000

TRAS_MIN

31:24

23:16

0x0

0x0-0xFF

DRAM TRAS_MIN parameter in cycles.

Length f cmd that caused an Out-of-

Range interrupt. READ-ONLY

OUT_OF_RANGE_LENGTH

0x0

Syndrome for uncorrectable ECC

event. READ-ONLY

ECC_U_SYND

ECC_C_SYND

15:8

7:0

0x0-0xFF

Syndrome for correctable ECC event.

READ-ONLY

CONF_CTL_12[63:32]

Offset: 0xC0

DDR2 667:0x002A3305

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 0 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_0

56:48

0x0

0x0-0x1FF

TRFC

47:40

39:32

0x0

0x0-0xFF

DRAM TRFC parameter in cycles.

DRAM TRCD parameter in cycles.

TRCD_INT

CONF_CTL_13[31:0]

Offset: 0xD0

DDR2 667:0x002A002A

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 2 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_2

24:16

8:0

0x0

0x0-0x1

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 1 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_1

0x0

0x0-0x1

CONF_CTL_13[63:32]

Offset: 0xD0

DDR2 667:0x002A002A

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 4 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_4

56:48

40:32

0x0

0x0-0x1FF

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 3 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_3

0x0

0x0-0x1FF

CONF_CTL_14[31:0]

Offset: 0xE0

DDR2 667:0x002A002A

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 6 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_6

24:16

0x0

0x0-0x1FF

31/49

DDR2 SDRAM controller interface description

STLS2F02

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 7 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_5

8:0

0x0

0x0-0x1FF

CONF_CTL_14[63:32]

Offset: 0xE0

DDR2 667:0x002A002A

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 8 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_8

56:48

40:32

0x0

0x0-0x1FF

Number of delay elements to include in

the dqs signal from the DRAMs for

dll_rd_dqs_slice 7 during reads when

DLL is being bypassed.

DLL_DQS_DELAY_BYPASS_7

0x0

0x0-0x1FF

CONF_CTL_15[31:0]

Offset: 0xF0

DDR2 667:0x00000004

Number of delay elements in master

DLL lock. READ-ONLY

DLL_LOCK

24:16

8:0

0x0

0x0-0x1FF

Number of elements to add to

DLL_START_POINT when searching

for lock.

DLL_INCREMENT

0x0

CONF_CTL_15[63:32]

Offset: 0xF0

DDR2 667:0x00B4000A

Number of delay elements to include in

the write dqs signal to the DRAMs

during writes when DLL is being

bypassed.

DQS_OUT_SHIFT_BYPASS

56:48

40:32

0x0

0x0-0x1FF

Initial delay count when searching for

lock in master DLL.

DLL_START_POINT

0x0

0x0-0x1FF

CONF_CTL_16[31:0]

Offset: 0x100

DDR2 667:0x00000087

Clear mask of the INT_STATUS

parameter. WRITE-ONLY

INT_ACK

25:16

8:0

0x0

0x0-0x3FF

0x0-0x1FF

Number of delay elements to include in

the clk_wr signal in the controller when

DLL is being bypassed.

WR_DQS_SHIFT_BYPASS

CONF_CTL_16[63:32] Offset: 0x100

DDR2 667:0x00000000

Status of interrupt features in the

controller. READ-ONLY

INT_STATUS

INT_MASK

58:48

0x0

0x0-0x7FF

Mask for controller_int signals from the

INT_STATUS parameter.

42:32

CONF_CTL_17[31:0]

Offset: 0x110

DDR2 667:0X0000181B

EMRS1_DATA

TREF

30:16

13:0

0x0

0x0-0x7FF

0x0-0x3FF

EMRS1 data.

DRAM TREF parameter in cycles.

CONF_CTL_17[63:32] Offset: 0x110

DDR2 667:0x00000000

32/49

STLS2F02

DDR2 SDRAM controller interface description

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

EMRS2_DATA_1

EMRS2_DATA_0

62:48

46:32

0x0000

0x0-0x7FFF EMRS2 data for chip select 1.

0x0-0x7FFF EMRS2 data for chip select 0.

CONF_CTL_18[31:0] Offset: 0x120

EMRS2_DATA_3

DDR2 667:0x00000000

30:16

14:0

0x0000

0x0-0x7FFF EMRS2 data for chip select 3.

0x0-0x7FFF EMRS2 data for chip select 2.

EMRS2_DATA_2

CONF_CTL_18[63:32] Offset: 0x120

DDR2 667:0x001C0000

Allow narrow instructions from port 0

requestors with bit enabled.

AXI0_EN_SIZE_LT_WIDTH_INSTR 63:48

0x0000

0x0-0xFFFF

EMRS3_DATA

CONF_CTL_19[31:0] Offset: 0x130

46:32

0x0-0x7FFF EMRS3 data.

DDR2 667:0x00C8006B

TDLL

31:16

15:0

0x0000

0x0-0xFFFF DRAM TDLL parameter in cycles.

0x0-0xFFFF DRAM TCPD parameter in cycles.

TCPD

CONF_CTL_19[63:32] Offset: 0x130

DDR2 667:0x48E10002

DRAM TRAS_MAX parameter in

cycles.

TRAS_MAX

63:48

0x0000

0x0-0xFFFF

TPDEX

CONF_CTL_20[31:0]

TXSR

47:32

0x0-0xFFFF DRAM TPDEX parameter in cycles.

Offset: 0x140

DDR2 667:0x00C8002F

31:16

15:0

0x0000

0x0-0xFFFF DRAM TXSR parameter in cycles.

0x0-0xFFFF DRAM TXSNR parameter in cycles.

TXSNR

CONF_CTL_20[63:32] Offset: 0x140

DDR2 667:0x00000000

Value to Xor with generated ECC

codes for forced write check.

XOR_CHECK_BITS

VERSION

63:48

47:32

0x0000

0x2041

0x0-0xFFFF

0x2041

Controller version number.

READ-ONLY

33/49

DDR2 SDRAM controller interface description

STLS2F02

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

DDR2 667:0x00000036

0x0- Address of correctable ECC event.

CONF_CTL_21[31:0]

Offset: 0x150

ECC_C_ADDR[7:0]

TINIT

31:24

23:0

0x0000

0x1FFFFFFFF READ-ONLY

0x0000 0x0-0xFFFFF DRAM TINIT parameter in cycles.

CONF_CTL_21[63:32] Offset: 0x150

ECC_C_ADDR[36:8] 60:32

CONF_CTL_22[31:0] Offset: 0x160

DDR2 667:0x00000000

0x0-

Address of correctable ECC event.

0x0

0x1FFFFFFFF READ-ONLY

DDR2 667:0x00000000

0x0-

Address of uncorrectable ECC event.

ECC_U_ADDR[31:0]

31:0

0x1FFFFFFFF READ-ONLY

CONF_CTL_22[63:32] Offset: 0x160

DDR2 667:0x00000000

0x0-

Address of uncorrectable ECC event.

ECC_U_ADDR[36:32]

CONF_CTL_23[31:0] Offset: 0x170

OUT_OF_RANGE_ADDR[31:0]

CONF_CTL_23[63:32] Offset: 0x170

OUT_OF_RANGE_ADDR[36:32] 36:32

36:32

0x0

0x1FFFFFFFF rEAD-ONLY

DDR2 667:0x00000000

0x0-

Address of cmd that caused an Out-of-

31:0

0x0

0x1FFFFFFFF Range interrupt. READ-ONLY

DDR2 667:0x00000000

0x0-

Address of cmd that caused an Out-of-

0x0

0x1FFFFFFFF Range interrupt. READE-ONLY

CONF_CTL_24[31:0]

Offset: 0x180

DDR2 667:0x00000000

0x0- Address of port that caused the PORT

PORT_CMD_ERROR_ADDR[31:0]

CONF_CTL_24[63:32] Offset: 0x180

31:0

0x0

0x1FFFFFFFF cmd error. READ-ONLY

DDR2 667:0x00000000

0x0-

Address of port that caused the PORT

PORT_CMD_ERROR_ADDR[36:32] 36:32

CONF_CTL_25[31:0] Offset: 0x190

ECC_C_DATA[31:0]

CONF_CTL_25[63:32] Offset: 0x190

ECC_C_DATA[63:32]

CONF_CTL_26[31:0] Offset: 0x1A0

ECC_U_DATA[31:0]

CONF_CTL_26[63:32] Offset: 0x1A0

ECC_U_DATA[63:32] 63:32

0x0

0x1FFFFFFFF cmd error. READ-ONLY

DDR2 667:0x00000000

0x0-

Data associated with correctable ECC

31:0

0x1FFFFFFFF event. READ-ONLY

DDR2 667:0x00000000

0x0-

Data associated with correctable ECC

63:32

31:0

0x0

0x1FFFFFFFF event. READ-ONLY

DDR2 667:0x00000000

0x0-

Data associated with uncorrectable

0x0

0x1FFFFFFFF ECC event. READ-ONLY

DDR2 667:0x00000000

0x0-

Data associated with uncorrectable

0x0

0x1FFFFFFFF ECC event. READ-ONLY

34/49

STLS2F02

DDR2 SDRAM controller interface description

Table 12. DDR SDRAM configuration parameter register format (continued)

Default

Parameters

Bits

Range

Description

value

CONF_CTL_27[63:32] Offset: 0x1B0

DDR2 667:0x00000000

Additional cycles to delay CKE for

status reporting

CKE_DELAY

2:0

0:0

0x0

0x0-0x7

CONF_CTL_28[63:32] Offset: 0x1C0

DDR2 667:0x00000001

0x0 0x0-0x1 Enable unbuffered DIMM

UB_DIMM

35/49

DDR2 SDRAM controller interface description

STLS2F02

4.5

DDR2 SDRAM sample mode configuration

A DDR2 SDRAM controller is integrated in the STLS2F02. A delay compensation circuit

(using a DLL) samples return data on DQS. Since there is a data return path delay between

the memory controller and the SDRAM module, it is necessary to introduce a set of control

signals to measure the delay.

The control signals of DDR2_GATE_I[3:0] and DDR2_GATE_O[3:0] are used for the delay

measurement. On the PCB the signals DDR2_GATE_I and DDR2_GAT_O are connected

together to imitate the wiring delay on the PCB. The sampling accuracy is thus guaranteed.

36/49

STLS2F02

Initialization process

5

Initialization process

The initialization of STLS2F02 is divided into core and interface parts.

When the STLS2F02 PCI interface is configured as main bridge, interface initialization is

finished internally and PCI_RESETn is output signal. When the processor works as a

PCI/PCIX device, PCI_RESETn acts as an input to reset the STLS2F02 PCI interface.

When the processor reset signal SYSRESETn is low, the related clock, test, and initial

signals must be valid.

●

SYSCLK, MEMCLK, CLKSEL and PCI_CLK must be stable

Initial signal PCI_CONFIG should set to the appropriate value

TEST_CTRL[7:0] are all high

When SYSRESETn is invalid, the processor internal reset logic begins to work to initialize

the chip. The SYSRESETn signal should be valid for at least one clock cycle to ensure that

it is sampled by the reset logic.

The work mode of the PCI bus is determined by the main bridge during the reset period. The

PCI_RESETn output generated by the processor when it works as the main bridge is used

to ensure that all devices working at the same mode. When not in main bridge mode, the

PCI_RESETn input receives the bus configuration.

Figure 10. Initialization process when in main bridge mode

SYSCLK

MEMCLK

PCI_CLK

PCICONFIG

TESTCTRL

SYSRESETn

PCI_RESETn

1ms

64K SYSCLK

˜

37/49

Electrical characteristics

STLS2F02

6

Electrical characteristics

6.1

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 13 may cause permanent

damage to the device. These are stress ratings only and functional operation of the device

at these conditions is not implied. Exposure to maximum rating conditions for extended

period may affect device reliability.

Table 13. Absolute maximum rating

Parameter

Description

CPU core voltage

Min

Max

Unit

Vdd

Vdde1v8

-0.3

-55

1.32

2.0

V

°C

V

DDR2 voltage

Vdde3v3

IO voltage

4.0

DDR2_VREF

Pll_vdd_1

Pll_vdd_0

Pllio_vdde1v8

Pll_vdde1v8_1

Pll_vdde1v8_0

Pllio_vdd

T_S

DDR2 voltage reference

1.0 V PLL1 digital voltage

1.0 V PLL0 digital voltage

1.8 V PLL IO voltage

1.8 V PLL1 analog voltage

1.8 V PLL0 analog voltage

1.2 V PLL IO voltage

Storage temperature

ESD susceptibility (CDM)

2.0

1.32

2.0

1.32

150

350

ESD

6.2

Recommended operation environment

Table 14.

Recommended operating temperature, voltage and frequency

Parameter

Description

Ambient temperature

Min

Typ

Max

Unit

T_A

-40

1.20

1.7

85

1.32

1.9

°C

V

Vdd

CPU core voltage

1.26

1.8

3.3

0.9

1.2

1.8

Vdde1v8

DDR2 voltage

Vdde3v3

IO voltage

3.0

3.6

DDR2_VREF

Pll_vdd_1

Pll_vdd_0

Pllio_vdde1v8

Pll_vdde1v8_1

Pll_vdde1v8_0

DDR2 voltage reference

1.0 V PLL1 digital voltage

1.0 V PLL0 digital voltage

1.8 V PLL IO voltage

1.8 V PLL1 analog voltage

1.8 V PLL0 analog voltage

0.83

1.08

1.7

0.97

1.26

1.9

1.7

1.9

1.7

1.9

38/49

STLS2F02

Electrical characteristics

Table 14. Recommended operating temperature, voltage and frequency (continued)

Parameter

Description

1.2 V PLL IO voltage

Junction temperature

Min

Typ

Max

Unit

Pllio_vdd

TJ

1.08

-40

1.2

1.26

125

V

°C

6.3

DC parameters

Table 15. DC parameters

Parameter

Description

Min

Typ

Max

Unit

Note

(1)

V_IH

V_IL

Input high level voltage

input low level voltage

output high level voltage

output low level voltage

input high level leakage current

input low level leakage current

output low level current

output high level current

Input pin capacitor

2

V

(1)

(2)

(3)

(4)

0.8

V_OH

V_OL

I_IH

vdde3v3-0.3

V

0.3

0.4

-65

V

0.002

-67.3

µA

mA

pF

KΩ

I_IL

I_OL

8

I_OH

C_IN

C_OUT

R_PH

4.4

23

32

7

7.5

27

81

Output pin capacitor

25

50

(5)

Pull-up resistance

1. Input pin level (including tri-state pin).

2. Individual output pin (including output state tri-state pin) level.

3. For tri-state input pin (excluding input).

4. Individual output pin (including output state tri-state pin) driving capability.

5. For input pin (excluding tri-state pin).

Table 16. DC parameters (JTAG)

Parameter

Description

Min

Typ

Max

Unit

Note

(1)

C_TIN

C_TOUT

C_TCK

Test input capacitance

Test output capacitance

TCK capacitance

4.4

23

7

25

7

7.5

27

pF

(2)

4.4

7.5

1. For TDI, TMS and TRST in JTAG.

2. For TDO in JTAG.

39/49

Electrical characteristics

STLS2F02

6.4

AC parameters

Table 17. Clock parameters

(Test conditions:SYSCLK=100 MHz, PCICLK=133 MHz, MEMCLK=333 MHz,

CoreClk=1000 MHz)

Parameter

SYSCLK high level time

Min

Typ

Max

Unit

2

1

5

8

ns

SYSCLK low level time

SYSCLK rising time

SYSCLK falling time

SYSCLK cycle variation

PCI_CLK high level time

PCI_CLK low level time

PCI_CLK rising slew

PCI_CLK falling slew

PCI_CLK cycle variation

MEMCLK high level time

MEMCLK low level time

MEMCLK rising slew

MEMCLK falling slew

MEMCLK cycle variation

DQS high level time

DQS low level time

1

ns

1

ns

300

ps

3

ns

3

ns

1.5

V/ns

ps

500

1.59

1.41

1

ns

V/ns

ps

1

225

1.65

1.35

1

ns

DQS rising slew

V/ns

ps

DQS falling slew

1

DQS cycle variation

225

Table 18. Input setup and hold time

(Test conditions:SYSCLK=100 MHz, PCICLK=133 MHz, MEMCLK=333 MHz,

CoreClk=1000 MHz)

Parameter

PCI_* signals setup time

Min

Typ

Max

Unit

1.2

0.5

ns

PCI_* signals hold time

LIO_* signals setup time

1.2

LIO_* signals hold time

0.5

DDR2_DQ*/CB* signals setup time

DDR2_DQ*/CB* signals hold time

0.1

0.175

40/49

STLS2F02

Electrical characteristics

Table 19. Input setup and hold time

(Test conditions:SYSCLK=100 MHz, PCICLK=66 MHz, CoreClk=1000 MHz)

Parameter

PCI_* signals setup time

Min

Typ

Max

Unit

3.0

0.0

3.0

0.0

ns

PCI_* signals hold time

LIO_* signals setup time

LIO_* signals hold time

Table 20. Output delay time

(Test conditions:SYSCLK=100 MHz, PCICLK=133 MHz, CoreClk=1000 MHz)

Parameter

Min

Typ

Max

Unit

PCI_* signals effective delay

LIO_* signals effective delay

0.7

1.5

3.8

6.0

ns

DDDR2_A*/RAS*/CAS*/WE*/CS*/CKE*/ODT*

signals effective delay

1.5

ns

DDR2_DQ*/DQM* effective delay

0.75

Table 21. JTAG parameters

(Test condition:TCK=100 MHz)

Parameter

Min

Typ

Max

Unit

TCK high level time

TCK low level time

TCK rising time

2

5

8

1

ns

1

TCK falling time

1

TRST pulse width

10

3.5

2.5

TDI,TMS setup time

TDI,TMS hold time

TDO output effective delay

TDO output disable delay

4.4

5.5

1.28

41/49

Thermal characteristics

STLS2F02

7

Thermal characteristics

7.1

Thermal resistivity

Heat spreader optimized with the following assumptions

●

Ambient temperature 40 °C

Package assembled on PCB as per JEDEC EIA/JESD51-9

Maximum power 7.45 W

Customer should implement power extraction from the top of the package so that package

case to ambient R is below 16 °C/W.

th

Without air flow, this can be achieved with a 40x40x15 heat spreader or 27x27x25 HS or

35x35x18 HS. This should guarantee 120 °C max junction temperature (low margin).

The preferred configuration is to use a 27x27x10 HS with 0.5m/sec. air flow. A single fan in

PC case should be enough. In such case, max Junction temp should be around 112 °C.

7.2

Reflow temperature to time curve

TheSTLS2F02 processor uses a flip chip eutectic packaging technology. It can endure

maximum reflow temperature ranging from 235 °C to 245 °C. The reflow temperature curve

and parameters are shown in Figure 11 and Table 22.

Figure 11. Reflow temperature to time curve

42/49

STLS2F02

Thermal characteristics

Table 22. Reflow temperature parameters

Parameter

Reference value

A

B

120 ~ 180 °C

90 ~ 120 seconds

0.3 ~ 2.0 °C/second

235 ~ 245 °C

C

D

E

85 ~ 105 seconds

< 1.2 °C/second

< 1.0 °C/second

F

F-1

43/49

Pin arrangement and package information

STLS2F02

8

Pin arrangement and package information

8.1

Pin arrangement

The STLS2F02 processor is packaged in HSFCBGA452. The pin arrangement is shown in

Figure 12: Pin arrangement (left-hand side), and Figure 14: Pin arrangement (right-hand

side),

Figure 12. Pin arrangement (left-hand side)

1

2

3

4

5

6

7

8

LIO_A5

LIO_A4

9

LIO_A7

sysclk

A

B

C

D

E

F

gnde

vdd

vvdddd

TEST_CTRL7

TEST_CTRL5

ggnnddee

LIO_AD01

TEST_CTRL6

memclk

LIO_AD04

LIO_AD05

LIO_AD12 LIO_A3

LIO_AD08 LIO_A1

gnde

vddd

TEST_CTRL3

TEST_CTRL1

gpio0

SYSRESETN LIO_AD06 LIO_AD14 LIO_A0

testclk

TEST_CTRL0

ppll_vdd_1

ppllio_vvddddee11vv88

ggppiio1

TEST_CTRL2

gpio2

ggnnddee

pllclock1

LIO_AD02 LIO_AD10 LIO_AD09

pllclock0

gpioo33

ppllll__ggnndd__11

ppllliioo__ggnndd

plll__ggnnddee__0

gnnddee

plll__vvddddee11vv88__11

pplllliioo__vdd

gnde

ppllll__ggnnddee__11

pllliioo__ggnnddee

gnde

G

H

J

vvdd

99

gnde

vvdd

pplll__ggnd_0

ggnnddee

pplll__vvddddee11vv88__00

gnde

JJ

K

LL

K

L

CLKSEL7

CLKSEL6

CLKSEL3

vvdddd

plll__vvdddd__00

CLKSEL5

CLKSEL4

CLKSEL1

CLKSEL8

CLKSEL0

CLKSEL9

CLKSEL2

M

N

P

R

T

MM

NN

PP

RR

TT

vvdd

PCI_CONFIG7 PCI_CONFIG6

vvdd

PCI_CONFIG5 PCI_CONFIG4 vvddddee33vv33

PCI_CONFIG0 PCI_CONFIG1 vdde3v3

vvdd

PCI_CONFIG3

PCI_CONFIG2

PCI_AD01

PCI_CBEn0

PCI_AD10

GND

vvdd

PCI_IDSEL

PCI_AD03

PCI_AD06

PCI_AD09

PCI_AD11

PCI_PAR

PCI_AD00

PCI_AD05

PCI_AD07

PCI_AD12

PCI_AD13

PCI_SERR

PCI_IRDYn

PCI_AD02

PCI_AD04

PCI_AD08

PCI_AD14

PCI_CBEn1

PCI_FRAMEn

VDD

vvdd

U

V

W

Y

UU

V

gnde

9

AA PCI_AD15

AB PCI_PERR

AC PCI_TRDYn

AD vdd

PCI_STOPn

PCI_DEVSELn vdd

gnddee

PCI_AD19

PCI_AD23

PCI_AD21

PCI_CBEn3

5

PCI_AD22 PCI_AD28 PCI_AD30

PCI_GNTn5

PCI_CBEn2

ggnnddee

PCI_AD17

PCI_AD18

PCI_AD20

4

PCI_AD24 PCI_AD27 PCI_GNTn6 PCI_REQn5

PCI_AD26 PCI_AD31 PCI_REQn6 PCI_GNTn3

PCI_AD25 PCI_AD29 PCI_REQn4 PCI_GNTn4

AE vdd

gndee

vvddd

2

PCI_AD16

AF gnde

vdd

1

3

6

7

8

9

CCoolloorr lleegend

Cooree power bbaallllss

Core and I/O ground balls

33.3 V I/O power balls

PPLLL power aannd grouunnd bballs

44/49

STLS2F02

Pin arrangement and package information

Figure 13. Pin arrangement (middle)

10

11

12

13

14

15

16

17

18

TEST_CTRL4

LIO_AD00

LIO_AD03

LIO_AD11

LIO_AD07

LIO_AD15

LIO_AD13

LIO_CSn

LIO_A2

LIO_ADLOCK

LIO_DIR

DDR2_VREF DDR2_DQSn0

DDR2_DQ00 DDR2_DQSp0

DDR2_DQ04 DDR2_DQ05

DDR2_DQ03

DDR2_DQ02

DDR2_DQ06

DDR2_DQ07

DDR2_DQ12

DDR2_DQ09

DDR2_DQ08

DDR2_DQ13

DDR2_DQM1

DDR2_DQSp1

DDR2_DQSn1

DDR2_GATEI0

A

B

LIO_A6

LIO_RDn

LIO_WRn

LIO_DEN

C

LIO_ROMCSn DDR2_DQ01 DDR2_DQM0

D

E

F

G

10

vvdd

11

vdd

12

vdd

13

14

15

16

vvddddee11vv88

ggnndd

17

vvddddee11vv8

vvddddee11vv88

vvddee11vv8

vvddddee11vv8

vvddee11vv8

vdde1v8

vvdddde1v8

17

18

ggnnddee

H

gnde

gnddee

ggnnddee

J

ggnnddee

vvddddee33vv33

vdde3v3

ggnndd

vvddddee33vv33

vdde3v3

gnd

vvdde3v3

gndd

vdde1v8

ggnndd

vddddee11vv88

vvddddee11vv88

ggnndd

ggnnddee

K

vvdde3v3

vvdde3v33

vvdde3v3

vvddee33vv3

ggnnddee

vdde1v8

gnddee

L

gnd

M

N

ggnndd

gnd

ggnndd

gnddee

ggnndd

gnd

ggnndd

gnddee

P

ggnndd

gnd

ggnndd

gnddee

R

vdde3v3

vvdddd

vdde3v3

vvdddd

gndd

ggnndd

vvddddee11vv88

vdde1v8

ggnnddee

vvddddee11vv88

vdde1v8

vvddddee11vv8

16

vdde1v8

gndee

T

vdde3v3

vvddde3v3

13

vdde1v8

gnde

14

U

gnddee

V

10

11

12

15

18

W

Y

AA

AB

AC

AD

AE

AF

PCI_REQn3

PCI_REQn2

PCI_GNTn2

PCI_REQn1

10

PCI_GNTn1

PCI_REQn0

PCI_GNTn0

PCI_IRQnA

PCI_IRQnC

PCI_IRQnB

INTN1

INTN2

INTN3

NMIN

13

tck

comp1v8_resistor DDR2_SCSn1 DDR2_A00

DDR2_ODT0

tdo

PCI_CLK

tms

DDR2_ODT3

DDR2_ODT1

DDR2_SCSn3 DDR2_ODT2

trst

DDR2_A01

DDR2_CASn

DDR2_A13

18

PCI_RESETn PCI_IRQnD

11 12

INTN0

14

tdi

comp1v8_gnd DDR2_A02

15

16

17

Color legend

Core power balls

Core and I/O ground balls

3.3 V I/O power balls

1.8 V I/O power balls

45/49

Pin arrangement and package information

Figure 14. Pin arrangement (right-hand side)

STLS2F02

19

20

21

22

23

24

25

vdde1vv88

26

DDR2_GATEO0 DDR2_DQM2 DDR2_DQ20

DDR2_DQ22

DDR2_DQ23

DDR2_CKE3

DDR2_CKn4

DDR2_CKp4

ggnndde

vvddddee11v8

ggnndde

A

B

C

D

E

F

DDR2_DQ14

DDR2_DQ15

DDR2_DQ11

DDR2_DQ16

DDR2_DQ10

DDR2_DQ21

DDR2_DQ17

DDR2_CKE1

gnde

ggnnddee

vvddde1v88

DDR2_DQSp2 DDR2_DQ18

DDR2_DQSn2 DDR2_DQ19

DDDDRR22__CCKKEE2

DDR22__CCKKpp11

DDR2_A11

DDR2_A05

DDR2_DQ29

DDR2_DQ24

DDR2_DQSn3

DDR2_A12

DDDDRR22__BBAA2

DDR2_A06

DDR2_A04

DDR2_DQ28

DDR2_DQ31

DDR2_CKn1

DDR2_A07

DDR2_CKE0

DDR2_A03

DDR2_DQ25

DDR2_DQ36

DDR2_DQ26

DDR2_DQ33

DDR2_DQ38

DDR2_DQ35

DDR2_A10

DDR2_A14

DDR2_A08

DDR2_A09

DDR2_DQM3

DDR2_DQ30

DDR2_DQ27

DDR2_DQ37

DDR2_DQ39

DDR2_DQ34

DDR2_BA1

G

H

J

K

L

DDR2_DQSp3

J

K

DDR2_GATEO1 DDR2_GATEI1

DDR2_DQ32

DDR2_DQSn4

DDR2_CKp3

DDR2_CKn0

DDR2_DQM4

DDR2_DQSp4

DDR2_CKn3

DDR2_CKp0

DDR2_RASn

DDR2_DQ41

DDR2_DQM5

DDR2_DQ46

DDR2_GATEO2

DDR2_DQSn6

DDR2_DQ50

DDR2_DQ56

DDR2_DQ57

DDDDRR22__DDQQ5588

vvddde1v88

L

M

N

P

R

T

M

N

P

DDR2_SCSn2 DDR2_SCSn0 DDR2_BA0

R

DDR2_DQ44

DDR2_DQ43

DDR2_DQ48

DDR2_DQ52

DDR2_DQ55

DDR2_DQM6

DDR2_DQ61

ggnnddee

DDR2_DQ40

DDR2_DQ45

T

U

V

DDR2_DQSn5 DDR2_DQSp5

U

DDR2_DQ47

DDR2_DQ49

DDR2_DQ51

DDR2_DQ53

DDR2_DQ60

DDR2_DQ42

DDR2_GATEI2

DDR2_DQSp6

DDR2_DQ54

DDR2_DQM7

V

W

Y

AA

AB

AC

AD

AE

AF

DDR2_WEn

DDR2_CKp2

DDR2_CKn2

DDR2_CKn5

19

DDR2_CB2

DDR2_CB3

DDR2_CB7

DDR2_CKp5

20

DDR2_DQM8

DDR2_CB6

DDR2_GATEI3

DDDDR2_DQSp7 DDR2_DQSn7

DDR2_GATEO3 DDR2_DQ59

gnddee

DDDDRR22__DDQQ6622

ggnnddee

DDR2_DQSp8 DDR2_CB5

DDR2_DQSn8 DDR2_CB1

DDR2_CB4

DDR2_CB0

23

DDR2_DQ63

vvddde1v8

24

vdde11vv88

25

ggnndde

21

22

26

Color legend

Core and I/O ground balls

1.8 V I/O power balls

46/49

STLS2F02

Package information

9

Package information

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect. The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 15. HFCBGA452 mechanical data and package dimensions

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN.

TYP. MAX. MIN.

TYP. MAX.

0.1240

A

A1

A3

A4

b

3.150

0.0098

0.250

1.300

0.0512

0.0394

1.000

0.450 0.500 0.550 0.0177 0.0197 0.0217

26.800 27.000 27.200 1.0551 1.0630 1.0709

D

D1

E

25.000

0.9843

26.800 27.000 27.200 1.0551 1.0630 1.0709

E1

e

25.000

1.000

0.9843

0.0394

F

aaa

ddd

eee

fff

0.200

0.250

0.100

0.0079

0.0098

0.0039

HFCBGA452 (27x27x2.9mm)

Heat Spreader Flip Chip Ball Grid Array

8061758 A

47/49

Revision history

STLS2F02

10

Revision history

Table 23. Document revision history

Date

Revision

Changes

28-Jul-2008

1

Initial relase.

48/49

STLS2F02

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49/49


型号：	STLS2F02
厂家：	ST
描述：	Loongson 2F high performance 64-bit superscalar MIPS㈢ microprocessor 龙芯2F高性能的64位超标量微处理器MIPS㈢微处理器
文件：	总49页 (文件大小：727K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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