STLVDS105 [STMICROELECTRONICS]
4-PORT LVDS AND 4-PORT TTL-TO LVDS REPEATERS; 4 - LVDS端口和4端口TTL到LVDS中继器
| 型号： | STLVDS105 |
| 厂家： | 
ST |
| 描述： | 4-PORT LVDS AND 4-PORT TTL-TO LVDS REPEATERS |
| 文件： | 总8页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLVDS105
4-PORT LVDS AND 4-PORT TTL-TO LVDS
REPEATERS
■
RECEIVER AND DRIVERS MEET OR
EXCEED THE REQUIREMENTS OF ANSI
EIA/TIA-644 STANDARD: RECEIVERS
LOW-VOLTAGE TTL (LVTTL) LEVELS
DESIGNED FOR SIGNALING RATES UP TO
630Mbps
■
■
OPERATES FROM A SINGLE 3.3V SUPPLY
LOW VOLTAGE DIFFERENTIAL SIGNALING
WITH TYPICAL OUTPUT VOLTAGE OF
350mV AND A 100Ω LOAD
SOP
TSSOP
■
■
PROPAGATION DELAY TIME: 2.2ns (TYP)
ELECTRICALLY COMPATIBLE WITH LVDS,
PECL, LVPECL, LVTTL, LVCOMOS, GTL,
BTL, CTT, SSTL, OR HSTL OUTPUTS WITH
EXTERNAL NETWORK
LVDS, as specified in EIA/TIA-644 is a data
signaling technique that offers low-power, low
noise coupling, and switching speed to transmit
data at a speed up to 630Mbps at relatively long
distances.
■
■
BUS TERMINAL ESD (HBM) EXCEEDS 7KV
SO AND TSSOP PACKAGING
The drivers integrated into the same substrate,
along with the low pulse skew of balanced
signaling, allow extremely precise timing
alignment of the signals repeated from the input.
The device allows extremely precise timing
alignment of the signal repeated from the input.
This is particularly advantageous in distribution or
expansion of signals such as clock or serial data
stream.
DESCRIPTION
The STLVDS105 is a differential line receiver and
a LVTTL input connected to four differential line
drivers
that
implement
the
electrical
characteristics of low voltage differential signaling,
for point to point baseband data transmission over
controlled impedance media of approximately
100Ω. The transmission media can be
printed-circuit board traces, backplanes, or cable.
ORDERING CODES
Temperature
Type
Package
Comments
Range
STLVDS105BD
STLVDS105BDR
STLVDS105BTR
-40 to 85 °C
-40 to 85 °C
-40 to 85 °C
SO-16 (Tube)
50parts per tube / 20tube per box
2500 parts per reel
SO-16 (Tape & Reel)
TSSOP16 (Tape & Reel)
2500 parts per reel
May 2003
1/8
STLVDS105
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
FUNCTIONAL TABLE
PIN DESCRIPTION
INPUT
A
ENABLES
#EN
OUTPUTS
PlN N°
SYMBOL
NAME AND FUNCTION
1, 2, 3, 8
EN1 to EN4 Enable Driver Inputs
#Y
#Z
6
A
Receiver Input
Not Connected
Driver Inputs
Driver Inputs
Ground
L
H
H
H
H
L
L
H
L
H
L
7
NC
9, 11, 13, 15
1Z to 4Z
1X to 4X
GND
Open
X
H
Z
Z
10, 12, 14, 16
Z
Z
5
4
X
X
V
Supply Voltage
CC
L=Low level, H=High Level, Z= High Impedance
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage (Note 1)
Voltage Range
-0.5 to 4
V
V
CC
V
Enable Inputs
A, Y or Z
-0.5 to 6
R
-0.5 to 4
V
ESD
ESD Protection Voltage (HBM)
Storage Temperature Range
Y, Z, to GND
All Pins
7
KV
KV
°C
2
T
-65 to +150
stg
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
Note 1: All voltages except differential I/O bus voltage, are with respect to the network ground terminal.
2/8
STLVDS105
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
3.0
Typ.
Max.
Unit
V
V
Supply Voltage
3.3
3.6
CC
V
HIGH Level Input Voltage
2.0
V
IH
V
LOW Level Input Voltage
0.8
3.6
V
IL
ID
IC
|V
V
|
Magnitude Of Differential Input Voltage
Common Mode Input Voltage
0.1
V
|V |/2
24-|V |/2
V
ID
ID
V
-0.8
CC
T
Operating Temperature Range
85
-40
°C
A
ELECTRICAL CHARACTERISTICS (T = -40 to 85°C, and V = 3.3V ±10% over recommended
A
CC
operating conditions unless otherwise noted. All typical values are at T = 25°C)
A
Symbol
|V
Parameter
Test Conditions
= ±100mV
Min.
Typ.
Max.
Unit
|
Differential Output Voltage R = 100Ω
V
ID
247
340
454
mV
OD
L
Magnitude
∆|V
|
Change in Differential
Output Voltage Magnitude
Between Logic State
-50
-50
50
50
mV
mV
OD
∆V
Change in Steady-state
Common Mode Output
Voltage Between Logic
State
OC(SS)
V
V
Steady-state Common
Mode Output Voltage
1.125
1.2
25
18
1.375
150
28
V
OC(SS)
OC(PP)
Peak to Paek Common
mode Output Voltage
mV
I
Supply Current
Enabled, R = 100Ω
mA
CC
L
Disabled
0.3
7
1
mA
I
High Level Input Current
Low Level Input Current
V
V
= 2V
20
µA
IH
IH
I
= 0.8V
3
10
µA
mA
mA
µA
IL
IL
I
Short Circuit Output Current V
V
or V = 0V
O(Z)
± 10
± 10
± 1
OC
O(Y)
= 0
OD
I
High Impedance Output
Current
V
= 0 or 2.4V
OZ
O
I
Power OFF Output Current
V
= 1.5V
V = 2.4V
O
0.3
5
± 1
µA
O(OFF)
CC
6πt
C
Input Capacitance (A or B
Inputs)
pF
IN
V = 0.4 sin (4e )+0.5V
I
6πt
C
Output Capacitance (Y or Z
Outputs)
9.4
pF
O
V = 0.4 sin (4e )+0.5V, Disabled
I
3/8
STLVDS105
SWITCHING CHARACTERISTICS (T = -40 to 85°C, and V = 3.3V unless otherwise noted. All typical
A
CC
values are at T = 25°C)
A
Symbol
Parameter
Test Conditions
R = 100Ω C = 10pF
Min.
Typ.
Max.
Unit
t
Propagation Delay Time,
Low to High Output
1.7
2.2
3
ns
PLH
L
L
t
Propagation Delay Time,
High to Low Output
1.7
0.3
0.3
2.2
0.7
0.7
3
ns
ns
ns
PHL
t
Differential Output Signal
Rise Time
1.2
1.2
r
t
Differential Output Signal
Fall Time
f
t
Pulse Skew (|t
- t |)
THL TLH
50
30
200
100
ps
ps
sk(P)
t
Channel-to-channel Output
Skew (note1)
sk(O)
t
Part to part Skew (note2)
1.5
15
ns
ns
sk(pp)
t
Propagation Delay Time,
High Impedance to High
Level Output
5
5
4
5
PZH
t
Propagation Delay Time,
High Impedance to Low
Level Output
15
15
15
ns
ns
ns
PZL
PHZ
t
Propagation Delay Time,
High Level to High
Impedance Output
t
Propagation Delay Time,
Low Level to High
PLZ
Impedance Output
Note 1: t
is the time difference between the t
or t
of all drivers of a single device with all their inputs connected together.
PHL
sk(O)
PLH
Note 2: t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
sk(pp)
operate with the same supply voltages, at the same temperature, and have identical packages and test circuit.
4/8
STLVDS105
TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified T = 25°C)
j
Figure 1 : Output Current vs Output High Voltage
Figure 3 : High to Low Propagation Delay Time
Figure 2 : Output Current vs Output Low Voltage
Figure 4 : Low to High Propagation Delay Time
5/8
STLVDS105
SO-16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.008
0.064
0.018
0.010
A
a1
a2
b
0.1
0.004
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45˚ (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8
˚ (max.)
PO13H
6/8
STLVDS105
TSSOP16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0079
0.201
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
5.1
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1
0.19
0.09
4.9
c
D
5
6.4
0.197
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
7/8
STLVDS105
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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