STM1403BSOQ6F [STMICROELECTRONICS]
3 V FIPS-140 security supervisor with battery switchover; 3 V FIPS -140安全监督员与电池切换
| 型号： | STM1403BSOQ6F |
| 厂家： | 
ST |
| 描述： | 3 V FIPS-140 security supervisor with battery switchover |
| 文件： | 总34页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM1403
3 V FIPS-140
security supervisor with battery switchover
Features
■ STM1403 supports FIPS-140 security level 3+
– Four high-impedance physical tamper
inputs
– Over/under operating voltage detector
– Security alarm (SAL) on tamper detection
■ Supervisory functions
– Automatic battery switchover
– RST output (open drain)
– Manual (push-button) reset input (MR)
– Power-fail comparator (PFI/PFO)
QFN16, 3 mm x 3 mm (Q)
■ Vccsw (V switch output)
CC
– Low when switched to V
CC
– High when switched to V
indicator)
(BATT ON
BAT
■ Battery low voltage detector (power-up)
■ Optional V (1.237 V)
REF
– (Available for STM1403A only)
■ Low battery supply current (2.8 µA, typ)
■ Secure low profile 16-pin, 3 x 3 mm, QFN
package
Table 1.
Device
Device summary
Standard
supervisory
functions(1)
Physical
tamper
inputs
Over/under
voltage
alarms
VREF
(1.237 V)
option
VOUT status,
during alarm
Vccsw status,
during alarm
STM1403A
STM1403B(3)
STM1403C
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
ON
Normal mode(2)
High
Note(4)
Note(4)
High-Z
Ground
High
1. Reset output, power-fail comparator, battery low detection (SAL, RST, PFO, and BLD are open drain).
2. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to battery.
3. Contact local ST sales office for availability.
4. Pin 9 is the VREF pin for STM1403A. It is the VTPU pin for STM1403B/C.
August 2008
Rev 5
1/35
www.st.com
1
Contents
STM1403
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
VOUT pin modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1
1.1.2
1.1.3
STM1403A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM1403B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM1403C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
SAL, security alarm output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
2.1.10
2.1.11
2.1.12
2.1.13
2.1.14
TP , TP
1
3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
TP , TP
2
Vccsw, V switch output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
BLD, V
low voltage detect output (open drain) . . . . . . . . . . . . . . . . . 12
BAT
Active-low RST output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MR, manual reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PFO, power-fail output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PFI, power-fail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
V
V
V
V
V
, reference voltage output (1.237, typ) . . . . . . . . . . . . . . . . . . . . . . 12
REF
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
TPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
BAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
3.2
3.3
3.4
3.5
3.6
Reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Negative-going VCC transients and undershoot . . . . . . . . . . . . . . . . . . . . 16
4
Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/35
STM1403
Contents
4.2
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
7
8
9
10
3/35
List of tables
STM1403
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating and AC measurement condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Physical and environmental tamper detection levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data . . . 31
Ordering information scheme (see Figure 30 on page 33 for marking information) . . . . . . 32
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4/35
STM1403
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
QFN16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Tamper pin (TP or TP ) normally high (NH) external hookup (switch closed) . . . . . . . . . . 9
1
3
Tamper pin (TP or TP ) normally high (NH) external hookup (switch open). . . . . . . . . . . 10
1
3
Tamper pin (TP or TP ) normally low (NL) external hookup (switch closed) . . . . . . . . . . 10
2
4
Tamper pin (TP or TP ) normally low (NL) external hookup (switch open). . . . . . . . . . . . 10
2
4
Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. -to-V on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
V
BAT
OUT
V
PFI
Figure 15. Power-up t vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
rec
Figure 16. Normalized reset threshold vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22.
V
to reset propagation delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CC
Figure 23. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 25. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 26. STM1403 switchover diagram, condition A (V
Figure 27. STM1403 switchover diagram, condition B (V
< V ) . . . . . . . . . . . . . . . . . . . . . . . . . 24
BAT
SW
> V ) . . . . . . . . . . . . . . . . . . . . . . . . . 25
BAT
SW
Figure 28. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 30
Figure 29. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . 31
Figure 30. Topside marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5/35
Description
STM1403
1
Description
The STM1403 family of security supervisors are a low power family of intrusion (tamper)
detection chips targeted at manufacturers of POS terminals and other systems, to enable
them to meet physical and/or environmental intrusion monitoring requirements as
mandated by various standards, such as Federal Information Processing Standards (FIPS)
Pub 140 entitled “Security Requirements for Cryptographic Modules,” published by the
National Institute of Standards and Technology, U.S. Department of Commerce), EMVCo,
ISO, ZKA, and VISA PED. STM1403 supports target levels 3 and lower.
The STM1403 includes automatic battery switchover, RST output (open drain), manual
(push-button) reset input (MR), power-fail comparator (PFI/PFO), physical and/or
environmental tamper detect/security alarm, and battery low voltage detect features.
The STM1403A also offers a V
(1.237 V) as an option on pin 9. On the STM1403B/C,
REF
this pin is V
(internally switched V or V ).
TPU
CC BAT
1.1
VOUT pin modes
The STM1403 is available in three versions, corresponding to three modes of the V
pin
OUT
(supply voltage out), when the SAL (security alarm) is asserted (active-low) upon tamper
detection:
1.1.1
1.1.2
1.1.3
STM1403A
V
stays ON (at V or V ) when SAL is driven low (activated).
CC BAT
OUT
STM1403B
V
is set to High-Z when SAL is driven low (activated).
OUT
STM1403C
V
is driven to ground when SAL is activated (may be used when V
is connected
OUT
OUT
directly to the V pin of the external SRAM that holds the cryptographic codes).
CC
All variants (see Table 1: Device summary) are pin-compatible and available in a security-
friendly, low profile, 16-pin QFN package.
6/35
STM1403
Description
Figure 1.
Logic diagram
V
REF
or
(3)
V
BLD
V
CC
BAT
(1)
V
TPU
(2)
V
V
OUT
CCSW
(3)
MR
PFI
RST
STM1403
(3)
PFO
SAL
(3)
TP (NH)
1
V
TP
TP
TP
4
SS
2
3
(NL) (NH) (NL)
AI09682
1. VREF only for STM1403A; VTPU for STM1403B/C.
2. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to
battery.
3. SAL, RST, PFO, and BLD are open drain.
Table 2.
Vccsw(1)
MR
Signal names
VCC switch output
Manual (push-button) reset input
Power-fail Input
PFI
TP1 - TP4
VOUT
Independent physical tamper detect pins 1 through 4
Supply voltage output
RST(2)
PFO(2)
SAL(2)
BLD(2)
Active-low reset output
Power-fail output
Security alarm output
Battery low voltage detect
1.237 V reference voltage
(3)
VREF
(3)
VTPU
Tamper pull-up (VCC or VBAT
Backup supply voltage
Supply voltage
)
VBAT
VCC
VSS
Ground
1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to
battery.
2. SAL, RST, PFO, and BLD are open drain.
3. VREF only for STM1403A; VTPU for STM1403B/C.
Note:
See Section 2: Pin descriptions on page 11 for details.
7/35
Description
STM1403
Figure 2.
QFN16 connections
(1)
(2)
V
V
CC
BLD PFI
CCSW
15
16
14
13
12
(2)
1
2
RST
V
OUT
V
MR
(2)
11
10
9
BAT
(2)
3
4
SAL
PFO
V
(3)
V
or
V
SS
REF
TPU
5
6
8
7
TP
(NH)
TP
(NL)
TP
(NH)
TP
2
(NL)
3
4
1
AI09683
Note:
See Section 2: Pin descriptions on page 11 for details.
1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to
battery.
2. SAL, RST, PFO, and BLD are open drain.
3. VREF only for STM1403A; VTPU for STM1403B/C
Figure 3.
Block diagram
V
V
CC
OUT
(1,2)
BAT54J
V
V
COMPARE
COMPARE
SO
(1)
BAT
V
V
CCSW
V
INT
RST
t
(3)
rec
Generator
RST
PFO
MR
PFI
(3)
V
V
COMPARE
PFI
COMPARE @
POWER-UP
(3)
BLD
V
DET
(4)
TPU
(4)
1.237V V
REF
V
REF
Generator
V
COMPARE
HV
V
COMPARE
LV
TP (NH)
1
TP (NL)
2
(3)
SAL
TP (NH)
3
TP (NL)
4
AI09684
1. BAT54J (from STMicroelectronics) recommended
2. Required for battery-reverse charging protection
3. Open drain
4. VREF only for STM1403; VTPU for STM1403B/C
8/35
STM1403
Description
Figure 4.
Hardware hookup
(1)
V
Regulator
CCSW
Unregulated
Voltage
V
V
V
V
V
OUT
CC
IN
CC
CC
V
CC
LPSRAM
(2)
C
0.1μF
STM1403
R1
R2
(3)
(3)
PFI
MR
PFO
To Microprocessor NMI
To Microprocessor Reset
RST
BLD
Push-Button
BAT54J
(4)
(3)
V
To Microprocessor
BAT
1.0μF
TP
1
TP
TP
TP
2
3
4
From Actuator Device
(e.g., Switches, Wire Mesh)
(3)
SAL
(5)
V
To ADC
REF
or
To Physical Tamper Pins TP
V
X
TPU
AI09690
1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to
battery.
2. Capacitor (C) is typically ≥ 10 µF.
3. Open drain
4. Diode is required for battery reverse charge protection.
5. VREF only for STM1403; VTPU for STM1403B/C.
Figure 5.
Tamper pin (TP or TP ) normally high (NH) external hookup (switch
1 3
closed)
V
(STM1403A)
or
OUT
V
(STM1403B/C)
TPU
Switch Normally Closed;
Tamper Detection on Open
TP or TP
1
3
(1)
R
AI09698
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
9/35
Description
STM1403
Tamper pin (TP or TP ) normally high (NH) external hookup (switch
Figure 6.
1
3
open)
V
(STM1403A)
or
OUT
V
(STM1403B/C)
TPU
(1)
R
TP or TP
1
3
Switch Normally Open
Tamper Detection when Closed
AI10461
1. R typical is 10MΩ. Resistors must be protected against conductive materials.
Figure 7.
Tamper pin (TP or TP ) normally low (NL) external hookup (switch
2 4
closed)
V
(STM1403A)
or
OUT
V
(STM1403B/C)
TPU
(1)
R
TP or TP
2
4
Switch Normally Closed;
Tamper Detection on Open
AI09699
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
Figure 8.
Tamper pin (TP or TP ) normally low (NL) external hookup (switch open)
2 4
V
(STM1403A)
or
OUT
V
(STM1403B/C)
TPU
Switch Normally Open;
Tamper Detection when Closed
TP or TP
2
4
(1)
R
AI10462
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
10/35
STM1403
Pin descriptions
2
Pin descriptions
See Figure 1: Logic diagram and Table 2: Signal names for a brief overview of the signals
connected to this device.
2.1
SAL, security alarm output (open drain)
This signal can be generated when ANY of the following conditions occur:
●
●
●
V
V
> V , where V = upper voltage trip limit (4.2 V typ); and where V
;
= V or
INT
HV
HV
INT CC
BAT
V
V
< V , where V = lower voltage trip limit (2.0 V typ); and where V
= V or
INT
LV
LV
INT CC
; or
BAT
When any of the physical tamper inputs, TP to TP , change from their normal states to
1
4
the opposite (i.e., intrusion of a physical enclosure).
The default state of the SAL output during initial power-up is undetermined.
The alarm function will operate either with V on or when the part is internally switched
Note:
1
2
CC
from V to V
.
CC
BAT
2.1.1
TP , TP
1 3
Physical tamper detect pin set normally to high (NH). They are connected externally through
a closed switch or a high-impedance resistor to V (in the case of STM1403A) or V (in
OUT
TPU
the case of STM1403B/C. A tamper condition will be detected when the input pin is pulled
low (see Figure 5 and Figure 6). If not used, tie the pin to V
(for STM1403A) or V
(for
OUT
TPU
STM1403B/C).
2.1.2
2.1.3
TP , TP
2 4
Physical tamper detect pin set normally to low (NL). They are connected externally through
a high-impedance resistor or a closed switch to V . A tamper condition will be detected
when the input pin is pulled high (see Figure 7 and Figure 8). If not used, tie the pin to V
SS
.
SS
Vccsw, V switch output
CC
This output is low when V
(see Section 2.1.10: V
on page 13) is internally switched
OUT
OUT
to V ; in this mode it may be used to turn on an external p-channel MOSFET switch which
CC
can source an external device directly from V for currents greater than 80 mA (bypassing
CC
the STM1403).
This pin goes high when V
ON” indicator.
is internally switched to V
and may be used as a “BATT
OUT
BAT
If a security alarm (SAL) is issued on tamper, then the state of the Vccsw pin is as follows:
11/35
Pin descriptions
1. STM1403A (V
STM1403
remains ON when SAL is active-low): Vccsw pin will continue to
OUT
operate in normal mode;
2. STM1403B (V is taken to High-Z when SAL is active-low): Vccsw pin will be set to
OUT
high when this occurs; and
3. STM1403C (V
is driven to ground when SAL is active-low): Vccsw pin will be set to
OUT
high when this occurs.
2.1.4
BLD, V
low voltage detect output (open drain)
BAT
This is an internally loaded test of the battery, activated only during a power-up sequence to
insure that the battery is good either prior to or after encapsulation of the module. There are
three customer options for V
:
DET
●
●
●
2.3 V (2.5 V – external diode drop of about 0.2 V) for a 3 V lithium cell
2.5 V (2.7 V – 0.2 V) for a 3 V lithium cell or
3.2 V (3.4 V – 0.2 V) for a 3.68 V lithium “AA” battery
This output pin will go active-low when it detects a voltage on the V
pin below V . BLD
DET
BAT
will be released when V drops below V
.
CC
RST
2.1.5
2.1.6
Active-low RST output (open drain)
Goes low and stays low when V drops below V
(reset threshold selected by the
RST
CC
customer), or when MR is logic low. It remains low for t (200ms, typical) AFTER V rises
rec
CC
above V
and MR goes from low to high.
RST
MR, manual reset input
A logic low on MR asserts the RST output. The RST output remains asserted as long as MR
is low and for t after MR returns to high. This active low input has an internal 40 kΩ
rec
(typical) pull-up resistor. It can be driven from a TTL or CMOS logic line or shorted to ground
with a switch. Leave it open if unused.
2.1.7
PFO, power-fail output (open drain)
When PFI is less than V
(power-fail input threshold voltage) or V falls below V
CC SW
PFI
(battery switchover threshold ~ 2.4 V), PFO goes low, otherwise, PFO remains high. Leave
this pin open if unused.
2.1.8
2.1.9
PFI, power-fail input
When PFI is less than V , or when V falls below V (see PFO, above), PFO goes
SW
PFI
CC
active-low. If this function is unused, connect this pin to V
.
SS
V
, reference voltage output (1.237, typ)
REF
This is valid only when V is between 2.4 V and 3.6 V. When V falls below 2.4 V (V ),
CC
CC
SW
V
is pulled to ground with an internal 100 kΩ resistor. This is an optional feature
REF
available on the STM1403A. On the STM1403B/C, this pin is V
(internally switched V
TPU
CC
or V ). If unused, this pin should float.
BAT
12/35
STM1403
Pin descriptions
2.1.10
V
OUT
This is the supply voltage output. When V rises above V (battery backup switchover
CC
SO
voltage), V
is supplied from V . In this condition, V
may be connected externally to
OUT
CC
OUT
V
through a p-channel MOSFET switch. When V falls below the lower value of V
CC
CC SW
(~2.4 V), or V , V
is supplied from V . It is recommended that the V
pin be
BAT OUT
BAT
OUT
connected externally to a capacitor that will retain a charge for a period of time, in case an
intruder forces V or V to ground. The rectifying diode connected from the positive
CC
BAT
terminal of the battery to the V
capacitor.
pin of the STM1403 will prevent discharge of the
BAT
Three variations of parts will be offered with the following options:
1. STM1403A: V remains ON when SAL is active-low; Vccsw pin will continue to
OUT
operate in normal mode (see Section 2.1.3: Vccsw, V switch output on page 11);
CC
2. STM1403B: V
is taken to High-Z when SAL is active-low; Vccsw pin will be set to
OUT
high when this occurs; and
3. STM1403C: V
is driven to ground when SAL is active-low; Vccsw pin will be set to
OUT
high when this occurs.
2.1.11
V
TPU
For STM1403B and STM1403C, this pin provides pull-up voltage for the physical tamper
pins (TP1-4). This pin is not to be used as voltage supply source for any other purpose.
Note:
V
is the internally switched supply voltage from either the V pin or the V
pin.
TPU
CC
BAT
2.1.12
V
CC
This is the supply voltage (2.2 V to 3.6 V).
2.1.13
2.1.14
V
BAT
This is the secondary (backup battery) supply voltage. The pin is connected to the positive
terminal of the battery with a rectifying diode like the BAT54J from STMicroelectronics for
reverse charge protection. Voltage at this pin, after diode rectification, will be approximately
0.2 V less than the battery voltage, and will depend on the type of battery used as well as
the I
being drawn. (A capacitor of at least 1.0 µF connected between the V
pin and
BAT
BAT
V
is required.) If no battery is used, connect the V
pin to the V pin.
SS
BAT CC
V
SS
Ground, V , is the reference for the power supply. It must be connected to system ground.
SS
13/35
Operation
STM1403
3
Operation
3.1
Reset input
The STM1403 security supervisor asserts a reset signal to the MCU whenever V goes
CC
below the reset threshold (V
), or when the push-button reset input (MR) is taken low.
RST
RST is guaranteed to be a logic low for 0V < V < V
if V
is greater than 1V. Without
CC
RST
BAT
a backup battery, RST is guaranteed valid down to V =1V.
CC
During power-up, once V exceeds the reset threshold an internal timer keeps RST low for
CC
the reset time-out period, t . After this interval RST returns high.
rec
If V drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
CC
low for at least the reset time-out period (t ). Any time V goes below the reset threshold
rec
CC
the internal timer clears. The reset timer starts when V returns above the reset threshold.
CC
3.2
Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t (see
rec
Figure 25 on page 24) after it returns high. The MR input has an internal 40 kΩ pull-up
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open-drain/collector outputs. Connect a normally open momentary switch from
MR to ground to create a manual reset function; external debounce circuitry is not required.
If MR is driven from long cables or the device is used in a noisy environment, connect a
0.1 µF capacitor from MR to V to provide additional noise immunity. MR may float, or be
SS
tied to V when not used.
CC
3.3
Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external
SRAM through V
. With a backup battery installed with voltage V , the devices
OUT
BAT
automatically switch the SRAM to the backup supply when V falls.
CC
Note:
If backup battery is not used, connect both V
and V
to V
.
CC
BAT
OUT
This family of security supervisors does not always connect V
to V
when V
is
BAT
BAT
OUT
greater than V . V
connects to V
(through a 100 Ω switch) when V is below V
CC BAT
OUT CC SW
(~2.4 V) or V
(whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V
BAT
battery) to have a higher voltage than V
.
CC
Assuming that V
> 2.0 V, switchover at V ensures that battery backup mode is entered
SO
BAT
before V
gets too close to the 2.0 V minimum required to reliably retain data in most
OUT
external SRAMs. When V recovers, hysteresis is used to avoid oscillation around the V
CC
SO
point. V
is connected to V through a 3 Ω PMOS power switch.
OUT
CC
Note:
The backup battery may be removed while V is valid, assuming V
is adequately
BAT
CC
decoupled (0.1 µF typ), without danger of triggering a reset.
14/35
STM1403
Operation
Table 3.
Pin
I/O status in battery backup
Status
VOUT
VCC
Connected to VBAT through internal switch
Disconnected from VOUT
Disabled
PFI
PFO
MR
Logic low
Disabled
RST
VBAT
Vccsw
VREF
BLD
VTPU
Logic low
Connected to VOUT
Logic high
Pulled to VSS below 2.4 V (VSW
)
Logic high
Connected to VBAT through an internal switch
3.4
Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the V comparator). If PFI is less than the power-fail threshold (V ), the power-fail
RST
PFI
output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 4 on page 9) to either the unregulated DC input (if it is available) or the
regulated output of the V regulator. The voltage divider can be set up such that the
CC
voltage at PFI falls below V
several milliseconds before the regulated V input to the
PFI
CC
STM1403 or the microprocessor drops below the minimum operating voltage.
During battery backup, the power-fail comparator is turned off and PFO goes (or remains)
low (see Figure 9 on page 16). This occurs after V drops below V
(~2.4V). When
CC
SW
power returns, the power-fail comparator is enabled and PFO follows PFI. If the comparator
is unused, PFI should be connected to V and PFO left unconnected. PFO may be
SS
connected to MR so that a low voltage on PFI will generate a reset output.
3.5
Applications information
These supervisor circuits are not short-circuit protected. Shorting V
to ground -
OUT
excluding power-up transients such as charging a decoupling capacitor - destroys the
device. Decouple both V and V
pins to ground by placing 0.1 µF capacitors as close to
CC
BAT
the device as possible.
15/35
Operation
STM1403
Figure 9.
Power-fail comparator waveform
V
V
CC
RST
V
(2.4V)
SW
trec
PFO
RST
PFO follows PFI
PFO follows PFI
AI08861a
3.6
Negative-going VCC transients and undershoot
The STM1403 devices are relatively immune to negative-going V transients (glitches).
CC
Figure 23 on page 22 was generated using a negative pulse applied to V , starting at V
CC
RST
+ 0.3 V and ending below the reset threshold by the magnitude indicated (comparator
overdrive). The graph indicates the maximum pulse width a negative V transient can have
CC
without causing a reset pulse. As the magnitude of the transient increases (further below the
threshold), the maximum allowable pulse width decreases. Any combination of duration and
overdrive which lies under the curve will NOT generate a reset signal. Typically, a V
CC
transient that goes 100 mV below the reset threshold and lasts 40 µs or less will not cause a
reset pulse. A 0.1 µF bypass capacitor mounted as close as possible to the V pin
CC
provides additional transient immunity (see Figure 10).
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from V to V (cathode connected to V , anode to V ).
CC
SS
CC
SS
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 10. Supply voltage protection
V
CC
V
CC
0.1μF
DEVICE
V
SS
AI02169
16/35
STM1403
Tamper detection
4
Tamper detection
4.1
Physical
There are four (4) high-impedance physical tamper detect input pins, 2 normally set to high
(NH) and 2 normally set to low (NL). Each input is designed with a glitch immunity (see
Table 7 on page 28). These inputs can be connected externally to several types of actuator
devices (e.g., switches, wire mesh). A tamper on any one of the four inputs that causes its
state to change will trigger the security alarm (SAL) and drive it to active-low. Once the
tamper condition no longer exists, the SAL will return to its normal high state.
TP and TP are set normally to high (NH). They are connected externally through a closed
1
3
switch or a high-impedance resistor to V
(in the case of STM1403A) or V
(in the case
OUT
TPU
of STM1403B/C), A tamper condition will be detected when the input pin is pulled low (see
Figure 5 and Figure 6). If not used, tie the pin to V or V
.
TPU
OUT
TP and TP are set normally to low (NL). They are connected externally through a high-
2
4
impedance resistor or a closed switch to V . A tamper condition will be detected when the
SS
input pin is pulled high (see Figure 7 and Figure 8). If not used, tie the pin to V
.
SS
4.2
Supply voltage
The internally switched supply voltage, V
(either V input or V
input) is continuously
BAT
INT
CC
monitored. If V
should exceed the over voltage trip point, V (set at 4.2V, typical), or
INT
HV
should go below the under voltage trip point, V (set at 2.0 V, typical). SAL will be driven
LV
active-low. Once the tamper condition no longer exists, the SAL pin will return to its normal
high state.
When no tamper condition exists, SAL is normally high (see Section 2: Pin descriptions on
page 11).
When a tamper is detected, the SAL is activated (driven low), independent of the part type.
V
can be driven to one of three states, depending on which variant of STM1403 is being
OUT
used (see Table 1: Device summary on page 1):
●
●
●
ON
High-Z or
Ground (V
)
SS
Note:
The STM1403 must be initially powered above V
to enable the tamper detection alarms.
RST
For example, if the battery is on while V = 0V, no alarm condition can be detected until
CC
V
rises above V
(and t expires). From this point on, alarms can be detected either
CC
RST rec
on battery or V . This is done to avoid false alarms when the device goes from no power to
CC
its operational state.
17/35
Typical operating characteristics
STM1403
5
Typical operating characteristics
Note:
Typical values are at T = 25°C.
A
Figure 11. V
-to-V
on-resistance vs. temperature
BAT
OUT
220
200
180
160
140
120
100
V
= 0V
CC
V
= 2V
BAT
V
= 3V
BAT
V
= 3.3V
BAT
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09691
Figure 12. Supply current vs. temperature (no load)
30
25
20
15
10
5
2.5V
3.3V
3.6V
0
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE [°C]
AI09692
18/35
STM1403
Typical operating characteristics
Figure 13. V
threshold vs. temperature
PFI
1.255
1.250
1.245
1.240
1.235
1.230
1.225
V
= 3.3V
CC
V
= 2.5V
CC
V
= 3.0V
30
BAT
–50
–30
–10
10
50
70
90
110
130
TEMPERATURE [°C]
AI09693
Figure 14. Reset comparator propagation delay vs. temperature
24
22
V
= 3.0V
BAT
20
18
16
14
12
10
100mV OVERDRIVE
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09143
Figure 15. Power-up t vs. temperature
rec
215
210
205
200
195
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE [°C]
AI09144
19/35
Typical operating characteristics
Figure 16. Normalized reset threshold vs. temperature
STM1403
1.002
1.000
0.998
0.996
0.994
V
= 3.0V
40
BAT
–60
–40
–20
0
20
60
80
100
120
140
TEMPERATURE [°C]
AI09145
Figure 17. PFI to PFO propagation delay vs. temperature
9
8
7
6
5
4
3
2
1
0
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE [°C]
AI09148
Figure 18. RST output voltage vs. supply voltage
3.5
3.0
2.5
V
CC
2.0
1.5
1.0
0.5
0
V
RST
500 ms/div
AI09149b
20/35
STM1403
Typical operating characteristics
Figure 19. RST response time (assertion)
4.0
3.0
2.0
1.0
0.0
V
CC
V
RST
2 µs/div
AI09151b
Figure 20. Power-fail comparator response time (assertion)
1.45
4.0
1.40
3.0
1.35
1.30
1.25
PFO
2.0
PFI
1.0
1.20
1.15
0.0
2µs/div
AI09153b
Figure 21. Power-fail comparator response time (de-assertion)
1.45
1.40
1.35
1.30
1.25
1.20
1.15
4.0
3.5
3.0
2.5
PFO
2.0
1.5
PFI
1.0
0.5
0.0
2 µs/div
AI09154
21/35
Typical operating characteristics
Figure 22. V to reset propagation delay vs. temperature
STM1403
CC
60
50
40
30
20
10
10V/ms
1V/ms
0.25V/ms
0
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09155
Figure 23. Maximum transient duration vs. reset threshold overdrive
250
200
150
100
50
0
1
10
100
1000
10000
AI09156
RESET COMPARATOR OVERDRIVE, V
– V [mV]
CC
RST
22/35
STM1403
Maximum ratings
6
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Symbol
TSTG
Absolute maximum ratings
Parameter
Value
Unit
Storage temperature (VCC off, VBAT off)
Lead solder temperature for 10 seconds
Input or output voltage
–55 to 150
260
°C
°C
V
(1)
TSLD
VIO
–0.3 to VCC +0.3
–0.3 to 4.5
20
VCC/VBAT
IO
Supply voltage
V
Output current
mA
mW
PD
Power dissipation
320
Note:
Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to
exceed 180°C for between 90 to 150 seconds).
23/35
DC and AC parameters
STM1403
7
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 5: Operating and AC measurement condition. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5.
Operating and AC measurement condition
Parameter
STM1403
Unit
V
CC/VBAT supply voltage
2.2 to 3.6
–40 to 85
≤ 5
V
°C
ns
V
Ambient operating temperature (TA)
Input rise and fall times
Input pulse voltages
0.2 to 0.8VCC
0.3 to 0.7VCC
Input and output timing ref. voltages
V
Figure 24. AC testing input/output waveforms
0.8V
CC
0.7V
CC
CC
0.3V
0.2V
CC
AI02568
Figure 25. MR timing waveform
MR
tMLRL
RST
trec
tMLMH
AI09694
Figure 26. STM1403 switchover diagram, condition A (V
< V
)
)
BAT
SW
V
V
= 3.3V
OUT
CC
V
RST
V
= 2.4V
SW
V
BAT
V
– 35mV
AI10463
BAT
V
– 75mV
BAT
Figure 27. STM1403 switchover diagram, condition B (V
> V
SW
BAT
V
V
= 3.3V
OUT
CC
V
BAT
V
= 2.4V
SW
V
+ 40mV
AI10464
SW
24/35
STM1403
DC and AC parameters
Table 6.
Sym
DC and AC characteristics
Alter-
native
Description
Test condition(1)
Min
Typ
Max
Unit
VCC
,
Operating voltage
TA = –40 to +85°C
2.2
3.6
60
45
V
(2)
VBAT
VCC supply current
(STM1403A)
45
30
µA
µA
Typ @ 3.3 V, 25°C
VCC supply current
(STM1403B,C)
ICC
Excluding IOUT
VCC supply current in
battery backup mode
25
35
µA
(VBAT = 2.3 V, VCC = 2.0
V, MR = VCC
)
Excluding IOUT
(VBAT = 3.6 V)
VBAT supply current in
battery backup mode
(3)
IBAT
2.8
4.0
µA
V
IOUT1 = 5 mA(4)
VCC
0.03
–
VCC –
0.015
(VCC > VSW
IOUT1 = 80 mA
(VCC > VSW
)
VCC
0.3
–
VCC
0.15
–
VOUT1
VOUT voltage (active)
V
)
IOUT1 = 250 µA,
VCC
0.0015
–
VCC –
0.0006
V
(4)
VCC > VSW
I
OUT2 = 250 µA,
VBAT = 2.2 V
VBAT
0.1
–
VBAT
0.04
–
V
VOUT voltage (battery
backup)
VOUT2
IOUT2 = 1 mA,
VBAT = 2.2 V
VBAT
0.16
–
V
ISOURCE = 500 µA
(VCC > VSW
Internal switched supply
voltage (active)
VCC
0.3
–
VTPU1
V
)
ISOURCE = 100 µA
(VBAT = 2.2 V)
Internal switched supply
voltage (battery backup)
VBAT
0.10
–
VTPU2
V
Input leakage current (MR)
Input leakage current (PFI)
MR = 0 V; VCC = 3 V
0 V = VIN = VCC
20
75
2
350
+25
µA
nA
–25
–1
ILI
Input leakage current
(TP1-TP4)
0 V = VIN = VCC
+1
+1
µA
(5)
ILO
VIH
VIL
Output leakage current
Input high voltage (MR)
Input low voltage (MR)
0 V = VIN = VCC
–1
µA
V
0.7VCC
VRST (max) < VCC < 3.6V
0.3VCC
0.3
V
VCC = VRST (max),
ISINK = 3.2mA
Output low voltage (PFO,
RST, Vccsw, SAL, BLD)
VOL
V
V
V
IOL = 40µA; VCC = 1.0V;
VBAT = VCC
TA = 0°C to 85°C
OL = 200µA;
CC = 1.2V; VBAT = VCC
;
0.3
0.3
VOL
Output low voltage (RST)
I
V
25/35
DC and AC parameters
STM1403
Table 6.
Sym
DC and AC characteristics (continued)
Alter-
Description
Test condition(1)
Min
Typ
Max
Unit
native
VOHB
VOH battery backup (Vccsw)
ISOURCE = 100 µA,
0.8VBAT
V
V
Pull-up supply voltage
(open drain)
RST, SAL, BLD, PFO
3.6
Power-fail comparator
VPFI PFI input threshold
PFI falling (VCC < 3.6 V)
PFI Rising (VCC < 3.6 V)
1.212
1.237
10
1.262
20
V
PFI hysteresis
mV
PFI to PFO propagation
delay
tPFD
2
µs
Battery switchover
VBAT > VSW
Power-
VSW
VBAT
VSW
VBAT
2.4
V
V
down
V
BAT < VSW
BAT > VSW
Battery backup
switchover voltage (6)(7)
V
V
VSO
Power-up
VBAT < VSW
V
VSW
V
Hysteresis
40
mV
Battery low voltage detect
M
N
O
2.25
2.45
3.14
2.30
2.50
3.20
2.34
2.55
3.26
V
V
V
On
power-up
only
VDET
Battery detect threshold
Voltage reference (option for STM1403A)(8)
Voltage reference
(see Section 2.1.9: VREF
reference voltage output
(1.237, typ) on page 12)
0°C to 85°C
1.212
1.200
1.237
1.237
1.262
1.274
V
V
,
VREF
–40° to 0°C
0°C to 85°C
–40° to 0°C
15
10
10
25
15
µA
µA
IREF+
Source current
IREF–
Vn
Sink current
13
µA
Output voltage noise
f = 100 Hz to 100 kH
10-100
µVrms
26/35
STM1403
DC and AC parameters
Table 6.
Sym
DC and AC characteristics (continued)
Alter-
native
Description
Test condition(1)
Min
Typ
Max
Unit
Reset thresholds
V
CC falling
VCC rising
CC falling
CC rising
CC falling
VCC rising
3.00
3.00
2.85
2.85
2.55
2.55
140
3.075
3.085
2.925
2.935
2.625
2.635
200
3.15
3.17
3.00
3.02
2.70
2.72
280
V
V
T
S
R
V
V
(9)
VRST
Reset threshold
V
V
V
V
V
trec
RST pulse width
ms
Push-button reset input
tMLMH tMR MR pulse width
tMLRL tMRD MR to RST output delay
100
ns
ns
60
500
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = VRST (max) to 3.6 V; and VBAT = 2.8 V (except where
noted); typical values are for 3.3 V and 25°C.
2. VCC supply current, logic input leakage, push-button reset functionality, PFI functionality, state of RST tested at
VBAT = 3.6 V, and VCC = 3.6 V. The state of RST and PFO is tested at VCC = VCC (min). VBAT is voltage measured at the
pin.
3. Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V.
4. Guaranteed by design.
5. The leakage current measured on the RST, SAL, PFO, and BLD pins are tested with the output not asserted (output high
impedance).
6. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW
.
7. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75 mV.
8. Maximum external capacitive load on VREF pin cannot exceed 1nF.
9. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents
internal oscillation.
27/35
DC and AC parameters
STM1403
Table 7.
Sym
Physical and environmental tamper detection levels
Test
Parameter
Min
Typ
Max
Unit
conditions(1)
VHV
VLV
Overvoltage trip level
Undervoltage trip level
4.0
1.9
4.2
2.0
4.4
2.1
V
V
SAL propagation delay time
VHV + 200 mV or
VLV – 200 mV
25
50
µs
(after over/under voltage
detection)
Trip point for NH physical
tamper input pins (TP1 or TP3)
VOUT
–
VOUT
–
VHTP
V
V
1.3 V(2)
0.3 V(2)
Trip point for NL physical
tamper input pins (TP2 or TP4)
VLTP
0.3
1.0
VHTP
VOUT/VTPU
=
SAL propagation delay time(3)
;
30
15
50
µs
µs
(after physical tamper pin
detection)
VLTP = VSS
VDD = 3.6
Physical tamper input (TPX)
glitch immunity
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = VLV to VHV (except where noted).
2. In the case of STM1403A, physical tamper input pins (TPX) are referenced to VOUT (pin 12). In the case of
STM1403B or C, TPX are referenced to VTPU pin (pin 9).
3. VCC = VRST (max) to 3.6 V
28/35
STM1403
Package mechanical data
8
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 28. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline
D
E
A3
A
A1
ddd C
e
b
L
K
1
2
3
Ch
E2
K
D2
QFN16-A
Note:
Drawing is not to scale.
29/35
Package mechanical data
STM1403
Table 8.
Symb
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size,
mechanical data
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A3
b
0.90
0.02
0.20
0.25
3.00
1.70
3.00
1.70
0.50
0.20
0.40
–
0.80
0.00
–
1.00
0.05
–
0.035
0.001
0.008
0.010
0.118
0.067
0.118
0.067
0.020
0.008
0.016
–
0.032
0.000
–
0.039
0.002
–
0.18
2.90
1.55
2.90
1.55
–
0.30
3.10
1.80
3.10
1.80
–
0.007
0.114
0.061
0.114
0.061
–
0.012
0.122
0.071
0.122
0.071
–
D
D2
E
E2
e
K
–
–
–
–
L
0.30
0.08
0.33
16
0.50
–
0.012
0.003
0.013
16
0.020
–
ddd
Ch
N
–
–
–
–
Figure 29. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended
footprint
1.60
3.55
2.0
0.28
AI09126
Note:
Substrate pad should be tied to V
.
SS
30/35
STM1403
Part numbering
9
Part numbering
Table 9.
Ordering information scheme (see Figure 30 on page 32 for marking information)
STM1403 F
Example:
A
T
M
Q
6
Device type
STM1403: physical, voltage tamper detect
VOUT status (SAL = active-low)
A: VOUT = ON; Vccsw = normal mode
B
(1): VOUT = High-Z; Vccsw = high
C: VOUT = ground; Vccsw = high
Reset threshold voltage
T: VRST = 3.00 V to 3.15 V
S: VRST = 2.85 V to 3.00 V
R: VRST = 2.55 V to 2.70 V
Battery low voltage detect threshold (VDET
)
M: VDET = 2.3 V (typ)
N: VDET = 2.5 V (typ)
O: VDET = 3.2 V (typ)
Package
Q = QFN16 (3 mm x 3 mm)
Temperature range
6 = –40 to 85°C
Shipping method
F = ECOPACK® package, tape & reel
1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST sales office
nearest you.
31/35
Part numbering
Figure 30. Topside marking information
STM1403
03
XXX(1)
YWW(2)
AI11878
1. Options codes:
X = A, B, or C (for VOUT
)
X = T, S, or R (for reset threshold)
X = M, N, or O (for battery low voltage detect threshold)
2. Traceability codes
Y = Year
WW = Work Week
32/35
STM1403
Revision history
10
Revision history
Table 10. Document revision history
Date
Revision
Changes
11-Oct-2004
1
First edition
Corrected footprint dimensions; update characteristics (Figure 1, 2,
3, 4, 5, 6, 7, 8, 26, 27, 29; Table 1, 2, 3, 6, 7)
26-Nov-2004
1.1
22-Dec-2004
03-Feb-2005
25-Feb-2005
06-May-2005
1.2
1.3
1.4
1.5
Update characteristics ( Figure 4; Table 6, 7, 9)
Update characteristics (Figure 4; Table 6, 7)
Update temperature trip limits (Table 9)
Update characteristics (Figure 3, 4, 28; Table 6, 7)
Removed STM1404 references (Figure 1, 2, 3, 4, 5, 6, 7, 8, 26, 27;
Table 1, 2, 5, 6, 7, 9)
05-Aug-2005
18-Oct-2005
2
3
Update hardware hookup, characteristics, Lead-free text; add
marking information (Figure 4, 30; Table 6, 7, 9)
07-Feb-2007
20-Aug-2008
4
5
Update cover page, Table 7, and part numbering (Table 9).
Minor formatting changes, updated Table 1 and 7.
33/35
STM1403
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