STM32F030CC_技术文档

STM32F030x4 STM32F030x6

STM32F030x8 STM32F030xC

Value-line Arm^®-based 32-bit MCU with up to 256 KB Flash, timers,

ADC, communication interfaces, 2.4-3.6 V operation

Datasheet - production data

Features

®

• Core: Arm 32-bit Cortex -M0 CPU, frequency

up to 48 MHz

• Memories

LQFP64 10 × 10 mm

LQFP48 7 × 7 mm

LQFP32 7 × 7 mm

TSSOP20 6.4 × 4.4 mm

– 16 to 256 Kbytes of Flash memory

– 4 to 32 Kbytes of SRAM with HW parity

• Communication interfaces

• CRC calculation unit

2

– Up to two I C interfaces

• Reset and power management

–

Fast Mode Plus (1 Mbit/s) support on

– Digital & I/Os supply: V = 2.4 V to 3.6 V

DD

one or two I/Fs, with 20 mA current sink

– Analog supply: V

= V to 3.6 V

DD

DDA

–

SMBus/PMBus support (on single I/F)

– Power-on/Power down reset (POR/PDR)

– Low power modes: Sleep, Stop, Standby

– Up to six USARTs supporting master

synchronous SPI and modem control; one

with auto baud rate detection

• Clock management

– Up to two SPIs (18 Mbit/s) with 4 to 16

programmable bit frames

– 4 to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC with x6 PLL option

– Internal 40 kHz RC oscillator

• Serial wire debug (SWD)

®

• All packages ECOPACK 2

• Up to 55 fast I/Os

Table 1. Device summary

– All mappable on external interrupt vectors

Reference

Part number

– Up to 55 I/Os with 5V tolerant capability

• 5-channel DMA controller

STM32F030x4 STM32F030F4

• One 12-bit, 1.0 µs ADC (up to 16 channels)

– Conversion range: 0 to 3.6 V

STM32F030x6 STM32F030C6, STM32F030K6

STM32F030x8 STM32F030C8, STM32F030R8

STM32F030xC STM32F030CC, STM32F030RC

– Separate analog supply: 2.4 V to 3.6 V

• Calendar RTC with alarm and periodic wakeup

from Stop/Standby

• 11 timers

– One 16-bit advanced-control timer for

six-channel PWM output

– Up to seven 16-bit timers, with up to four

IC/OC, OCN, usable for IR control

decoding

– Independent and system watchdog timers

– SysTick timer

January 2019

DS9773 Rev 4

1/93

This is information on a product in full production.

www.st.com

Contents

STM32F030x4/x6/x8/xC

Contents

1

2

3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1

3.2

3.3

3.4

3.5

Arm^®Cortex^®-M0 core with embedded Flash and SRAM . . . . . . . . . . . . 12

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5.1

3.5.2

3.5.3

3.5.4

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6

3.7

3.8

3.9

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16

Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.9.1

3.9.2

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17

Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 17

3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10.2 Internal voltage reference (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REFINT

3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.11.1

3.11.2

3.11.3

3.11.4

3.11.5

3.11.6

Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

General-purpose timers (TIM3, TIM14..17) . . . . . . . . . . . . . . . . . . . . . . 20

Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.12 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.13 Inter-integrated circuit interfaces (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.14 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 22

2/93

DS9773 Rev 4

STM32F030x4/x6/x8/xC

Contents

3.15 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4

5

6

Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.2

6.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

6.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 45

Embedded reset and power control block characteristics . . . . . . . . . . . 45

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

DS9773 Rev 4

3/93

4

Contents

STM32F030x4/x6/x8/xC

7

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.1

7.2

7.3

7.4

7.5

LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.5.1

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8

9

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4/93

DS9773 Rev 4

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F030x4/x6/x8/xC family device features and peripheral counts . . . . . . . . . . . . . . . 10

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2

STM32F030x4/x6/x8/xC I C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8.

Table 9.

STM32F0x0 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

STM32F030x4/x6/x8/xC SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

STM32F030x4/6/8/C pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 34

Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 35

Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 37

Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 37

Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 37

STM32F030x4/x6/x8/xC peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . 39

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 45

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Typical and maximum current consumption from V supply at V = 3.6 V . . . . . . . . . . 47

DD

Typical and maximum current consumption from the V

supply . . . . . . . . . . . . . . . . . . 48

DDA

Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 49

Typical current consumption in Run mode, code with data processing

running from Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

LSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

DS9773 Rev 4

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6

List of tables

STM32F030x4/x6/x8/xC

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

R

max for f

= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

AIN

ADC

ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

TSSOP20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6/93

DS9773 Rev 4

STM32F030x4/x6/x8/xC

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock tree of STM32F030x4/x6/x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Clock tree of STM32F030xC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

LQFP64 64-pin package pinout (top view), for STM32F030x4/6/8 devices . . . . . . . . . . . . 25

LQFP64 64-pin package pinout (top view), for STM32F030RC devices . . . . . . . . . . . . . . 25

LQFP48 48-pin package pinout (top view), for STM32F030x4/6/8 devices . . . . . . . . . . . . 26

LQFP48 48-pin package pinout (top view), for STM32F030CC devices . . . . . . . . . . . . . . 26

LQFP32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

TSSOP20 20-pin package pinout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10. STM32F030x4/x6/x8/xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 19. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 21. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 22. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 23. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 24. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 25. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 26. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 27. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 28. LQFP64 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 29. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 30. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 31. LQFP48 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 32. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 33. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 34. LQFP32 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 35. LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 36. LQFP32 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 37. TSSOP20 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 38. TSSOP20 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 39. TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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7

Introduction

STM32F030x4/x6/x8/xC

1

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F030x4/x6/x8/xC microcontrollers.

This document should be read in conjunction with the STM32F0x0xx reference manual

(RM0360). The reference manual is available from the STMicroelectronics website

www.st.com.

®(a)

®

For information on the Arm

Cortex -M0 core, please refer to the Cortex -M0 Technical

Reference Manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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Description

2

Description

®

The STM32F030x4/x6/x8/xC microcontrollers incorporate the high-performance Arm

®

Cortex -M0 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded

memories (up to 256 Kbytes of Flash memory and up to 32 Kbytes of SRAM), and an

extensive range of enhanced peripherals and I/Os. All devices offer standard

2

communication interfaces (up to two I Cs, up to two SPIs and up to six USARTs), one 12-bit

ADC, seven general-purpose 16-bit timers and an advanced-control PWM timer.

The STM32F030x4/x6/x8/xC microcontrollers operate in the -40 to +85 °C temperature

range from a 2.4 to 3.6V power supply. A comprehensive set of power-saving modes allows

the design of low-power applications.

The STM32F030x4/x6/x8/xC microcontrollers include devices in four different packages

ranging from 20 pins to 64 pins. Depending on the device chosen, different sets of

peripherals are included. The description below provides an overview of the complete range

of STM32F030x4/x6/x8/xC peripherals proposed.

These features make the STM32F030x4/x6/x8/xC microcontrollers suitable for a wide range

of applications such as application control and user interfaces, handheld equipment, A/V

receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,

PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.

DS9773 Rev 4

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24

Description

STM32F030x4/x6/x8/xC

Table 2. STM32F030x4/x6/x8/xC family device features and peripheral counts

STM32

F030F4

STM32

F030K6

STM32

F030C6

STM32

F030C8

STM32

F030CC

STM32

F030R8

STM32

F030RC

Peripheral

Flash (Kbytes)

SRAM (Kbytes)

16

32

4

32

64

8

256

32

64

8

256

32

Advanced

control

1 (16-bit)

Timers

General

purpose

4 (16-bit)⁽¹⁾

5 (16-bit)

Basic

-

1 (16-bit)⁽²⁾2 (16-bit) 1 (16-bit)⁽²⁾2 (16-bit)

SPI

1⁽³⁾

1⁽⁴⁾

1⁽⁵⁾

2

Comm.

I²C

interfaces

USART

2⁽⁶⁾

6

2⁽⁶⁾

6

1

12-bit ADC

(number of channels)

(10 ext.

+2 int.)

(16 ext.

+2 int.)

(9 ext.

+2 int.)

(10 ext.

+2 int.)

(10 ext.

+2 int.)

(10 ext.

+2 int.)

(16 ext.

+2 int.)

GPIOs

15

26

39

37

55

51

Max. CPU frequency

Operating voltage

48 MHz

2.4 to 3.6 V

Ambient operating temperature: -40°C to 85°C

Junction temperature: -40°C to 105°C

Operating temperature

Packages

TSSOP20

LQFP32

LQFP48

LQFP64

1. TIM15 is not present.

2. TIM7 is not present.

3. SPI2 is not present.

4. I2C2 is not present.

5. USART2 to USART6 are not present.

6. USART3 to USART6 are not present

10/93

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STM32F030x4/x6/x8/xC

Description

Figure 1. Block diagram

POWER

SWCLK

Serial Wire

Debug

VOLT.REG

3.3 V to 1.8 V

V_DD= 2.4 to 3.6 V

V_SS

SWDIO

V_DD18

as AF

Flash GPL

16/32/64/256 KB

32-bit

@ V_DD

CORTEX-M0 CPU

f_MAX= 48 MHz

SUPPLY

SUPERVISION

POR

Reset

Int

NRST

V_DDA

V_SSA

V_DD

SRAM

4/8/32 KB

POR/PDR

NVIC

@ V_DDA

HSI14

RC 14 MHz

HSI

PLLCLK

LSI

RC 8 MHz

PLL

@ V_DDA

@ V_DD

GP DMA

5 channels

XTAL OSC

4-32 MHz

RC 40 kHz

OSC_IN

OSC_OUT

Ind. Window WDG

Power

PA[15:0]

PB[15:0]

PC[15:0]

PD2

GPIO port A

GPIO port B

GPIO port C

GPIO port D

GPIO port F

Controller

RESET & CLOCK

CONTROL

OSC32_IN

OSC32_OUT

XTAL32 kHz

System and peripheral

clocks

TAMPER-RTC

(ALARM OUT)

RTC

PF[1:0]

PF[7:4]

RTC interface

CRC

4 channels

3 compl. channels

BRK, ETR input as AF

PWM TIMER 1

AHB

APB

TIMER 3

TIMER 14

TIMER 15

TIMER 16

TIMER 17

4 ch., ETR as AF

1 channel as AF

EXT. IT WKUP

55 AF

2 channels

1 compl, BRK as AF

1 channel

1 compl, BRK as AF

Window WDG

DBGMCU

1 channel

1 compl, BRK as AF

MOSI, MISO,

SCK, NSS,

as AF

IR_OUT as AF

SPI1

SPI2

RX, TX,CTS, RTS,

CK, as AF

USART1

USART2

USART3

USART4

USART5

USART6

MOSI, MISO,

SCK, NSS,

as AF

RX, TX,CTS, RTS,

CK, as AF

RX, TX,CTS, RTS,

CK, as AF

RX, TX,CTS, RTS,

CK, as AF

SYSCFG IF

RX, TX,CTS, RTS,

CK, as AF

Temp.

sensor

RX, TX,CTS, RTS,

CK, as AF

16x

AD input

12-bit ADC IF

SCL, SDA, SMBA

TIMER 6

TIMER 7

I2C1

I2C2

(20 mA FM+), as AF

V_DDA

V_SSA

SCL, SDA, as AF

@ V_DDA

Power domain of analog blocks :

V_DD

V_DDA

MSv32137V3

1. TIMER6, TIMER15, SPI, USART2 and I2C2 are available on STM32F030x8/C devices only.

2. USART3, USART4, USART5, USART6 and TIMER7 are available on STM32F030xC devices only.

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24

Functional overview

STM32F030x4/x6/x8/xC

3

Functional overview

3.1

Arm^®Cortex^®-M0 core with embedded Flash and SRAM

®

The Arm Cortex -M0 processor is the latest generation of Arm processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

®

The Arm Cortex -M0 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an Arm core in the memory size usually

associated with 8- and 16-bit devices.

The STM32F0xx family has an embedded Arm core and is therefore compatible with all Arm

tools and software.

Figure 3 shows the general block diagram of the device family.

3.2

Memories

The device has the following features:

•

4 to 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0

wait states and featuring embedded parity checking with exception generation for fail-

critical applications.

•

The non-volatile memory is divided into two arrays:

–

16 to 256 Kbytes of embedded Flash memory for programs and data

Option bytes

The option bytes are used to write-protect the memory (with 4 KB granularity) and/or

readout-protect the whole memory with the following options:

–

Level 0: no readout protection

Level 1: memory readout protection, the Flash memory cannot be read from or

written to if either debug features are connected or boot in RAM is selected

®

–

Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and boot

in RAM selection disabled

3.3

Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot

options:

•

Boot from User Flash

Boot from System Memory

Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART on pins PA14/PA15 or PA9/PA10.

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STM32F030x4/x6/x8/xC

Functional overview

3.4

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.5

Power management

3.5.1

Power supply schemes

•

V

= 2.4 to 3.6 V: external power supply for I/Os and the internal regulator. Provided

DD

externally through VDD pins.

•

V

= from V to 3.6 V: external analog power supply for ADC, Reset blocks, RCs

DDA

DD

and PLL. The V

voltage level must be always greater or equal to the V voltage

DD

DDA

level and must be provided first.

For more details on how to connect power pins, refer to Figure 13: Power supply scheme.

3.5.2

Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.

They are always active, and ensure proper operation above a threshold of 2 V. The device

remains in reset mode when the monitored supply voltage is below a specified threshold,

V

, without the need for an external reset circuit.

POR/PDR

•

The POR monitors only the V supply voltage. During the startup phase it is required

DD

that V

should arrive first and be greater than or equal to V

.

DDA

DD

•

The PDR monitors both the V and V

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce

the power consumption if the application design ensures that V is higher than or

supply voltages, however the V

power

DD

DDA

equal to V

.

DD

3.5.3

Voltage regulator

The regulator has two operating modes and it is always enabled after reset.

•

Main (MR) is used in normal operating mode (Run).

Low power (LPR) can be used in Stop mode where the power demand is reduced.

In Standby mode, it is put in power down mode. In this mode, the regulator output is in high

impedance and the kernel circuitry is powered down, inducing zero consumption (but the

contents of the registers and SRAM are lost).

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Functional overview

STM32F030x4/x6/x8/xC

3.5.4

Low-power modes

The STM32F030x4/x6/x8/xC microcontrollers support three low-power modes to achieve

the best compromise between low power consumption, short startup time and available

wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM

and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the

HSE crystal oscillators are disabled. The voltage regulator can also be put either in

normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line

source can be one of the 16 external lines and RTC.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the RTC

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pins, or an RTC event occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.6

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the application to configure the frequency of the AHB and the APB

domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

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Functional overview

Figure 2. Clock tree of STM32F030x4/x6/x8

Flash memory

programming

interface

FLITFCLK

I2C1SW

HSI

8 MHz

HSI RC

I2C1

SYSCLK

/2

AHB, core, memory, DMA,

Cortex FCLK free-run clock

HCLK

/8

SW SYSCLK

Cortex

system timer

PLLSRC

PLLMUL

HSI

PLLCLK

HSE

PLL

x2,x3,..

...x16

PCLK

APB

/1,/2,…

…/512

/1,/2,/4,

/8,/16

peripherals

PREDIV

HPRE

PPRE

x1, x2

/1,/2,..

../16

CSS

TIM1,3,6⁽²⁾

14,15⁽²⁾,16,17

OSC_OUT

OSC_IN

HSE

4-32 MHz

HSE OSC

CKMODE

/2, /4

ADC

(14 MHz max)

LSE

14 MHz

HSI14 RC

/32

LSE

USART1SW

RTCCLK

OSC32_IN

PCLK

32.768 kHz

LSE OSC

SYSCLK

HSI

OSC32_OUT

USART1

RTCSEL

LSE

LSI

40 kHz

LSI RC

RTC

PLLNODIV

IWDG

(1)

MCOPRE

/1⁽¹⁾,/2

PLLCLK

Main clock

output

HSI

HSI14

/1,/2,/4,..

../128

MCO

HSE

Legend

black

white

SYSCLK

LSE⁽¹⁾

LSI⁽¹⁾

clock tree element

clock tree control element

clock line

MCO

control line

MSv32138V3

1. Applies to STM32F030x4/x6 devices.

2. Applies to STM32F030x8 devices.

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24

Functional overview

STM32F030x4/x6/x8/xC

Figure 3. Clock tree of STM32F030xC

Flash memory

FLITFCLK

programming

interface

I2C1SW

HSI

8 MHz

HSI RC

I2C1

SYSCLK

AHB, core, memory, DMA,

Cortex FCLK free-run clock

HCLK

/8

PREDIV

SW SYSCLK

Cortex

system timer

PLLSRC

PLLMUL

HSI

PLLCLK

HSE

PLL

x2,x3,..

...x16

PCLK

APB

/1,/2,…

…/512

/1,/2,/4,

/8,/16

/1,/2,..

../16

peripherals

HPRE

PPRE

x1, x2

CSS

TIM1,3,6,7

OSC_OUT

14,15,16,17

CKMODE

HSE

4-32 MHz

HSE OSC

OSC_IN

/2, /4

ADC

(14 MHz max)

LSE

14 MHz

HSI14 RC

/32

LSE

USART1SW

USART1

RTCCLK

OSC32_IN

PCLK

32.768 kHz

LSE OSC

SYSCLK

HSI

OSC32_OUT

RTCSEL

LSE

LSI

40 kHz

LSI RC

RTC

PLLNODIV

IWDG

MCOPRE

PLLCLK

/1,/2

Main clock

output

HSI

HSE

LSI

HSI14

SYSCLK

LSE

/1,/2,/4,..

../128

MCO

Legend

black

clock tree element

clock tree control element

clock line

white

MCO

control line

MSv47988V1

3.7

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to

avoid spurious writing to the I/Os registers.

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STM32F030x4/x6/x8/xC

Functional overview

3.8

Direct memory access controller (DMA)

The 5-channel general-purpose DMA manages memory-to-memory, peripheral-to-memory

and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code

intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, all TIMx timers (except

TIM14) and ADC.

3.9

Interrupts and events

3.9.1

Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to

®

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M0) and 4

priority levels.

•

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.9.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 32 edge detector lines used to generate

interrupt/event requests and wake-up the system. Each line can be independently

configured to select the trigger event (rising edge, falling edge, both) and can be masked

independently. A pending register maintains the status of the interrupt requests. The EXTI

can detect an external line with a pulse width shorter than the internal clock period. Up to 55

GPIOs can be connected to the 16 external interrupt lines.

DS9773 Rev 4

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24

Functional overview

STM32F030x4/x6/x8/xC

3.10

Analog to digital converter (ADC)

The 12-bit analog to digital converter has up to 16 external and two internal (temperature

sensor, voltage reference measurement) channels and performs conversions in single-shot

or scan modes. In scan mode, automatic conversion is performed on a selected group of

analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

3.10.1

Temperature sensor

The temperature sensor (TS) generates a voltage V

temperature.

that varies linearly with

SENSE

The temperature sensor is internally connected to the ADC_IN16 input channel which is

used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall

accuracy of the temperature measurement. As the offset of the temperature sensor varies

from chip to chip due to process variation, the uncalibrated internal temperature sensor is

suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode.

Table 3. Temperature sensor calibration values

Calibration value name

Description

Memory address

TS ADC raw data acquired at a

temperature of 30 °C ( 5 °C),

TS_CAL1

0x1FFF F7B8 - 0x1FFF F7B9

V_DDA= 3.3 V ( 10 mV)

3.10.2

Internal voltage reference (V

)

REFINT

The internal voltage reference (V

) provides a stable (bandgap) voltage output for the

REFINT

ADC. V

is internally connected to the ADC_IN17 input channel. The precise voltage

REFINT

of V

is individually measured for each part by ST during production test and stored in

REFINT

the system memory area. It is accessible in read-only mode.

Table 4. Internal voltage reference calibration values

Calibration value name

Description

Memory address

Raw data acquired at a

VREFINT_CAL

temperature of 30 °C ( 5 °C), 0x1FFF F7BA - 0x1FFF F7BB

_DDA= 3.3 V ( 10 mV)

V

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Functional overview

3.11

Timers and watchdogs

The STM32F030x4/x6/x8/xC devices include up to five general-purpose timers, two basic

timers and one advanced control timer.

Table 5 compares the features of the different timers.

Table 5. Timer feature comparison

Timer

type

Counter

resolution

Counter

type

Prescaler DMA request Capture/compare Complementary

Timer

factor

generation

channels

outputs

Up,

down,

up/down and 65536

Any integer

between 1

Advanced

control

TIM1

16-bit

Yes

4

3

Up,

down,

up/down and 65536

Any integer

between 1

TIM3

TIM14

Yes

No

4

1

2

1

0

-

Any integer

between 1

and 65536

Up

General

purpose

Any integer

between 1

and 65536

TIM15⁽¹⁾

Yes

1

-

Any integer

between 1

and 65536

TIM16,

TIM17

Any integer

between 1

and 65536

TIM6,⁽¹⁾

TIM7⁽²⁾

Basic

1. Available on STM32F030x8 and STM32F030xC devices only.

2. Available on STM32F030xC devices only

3.11.1

Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six

channels. It has complementary PWM outputs with programmable inserted dead times. It

can also be seen as a complete general-purpose timer. The four independent channels can

be used for:

•

Input capture

Output compare

PWM generation (edge or center-aligned modes)

One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard timers which have the same

architecture. The advanced control timer can therefore work together with the other timers

via the Timer Link feature for synchronization or event chaining.

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24

Functional overview

STM32F030x4/x6/x8/xC

3.11.2

General-purpose timers (TIM3, TIM14..17)

There are four or five synchronizable general-purpose timers embedded in the

STM32F030x4/x6/x8/xC devices (see Table 5 for differences). Each general-purpose timer

can be used to generate PWM outputs, or as simple time base.

TIM3

STM32F030x4/x6/x8/xC devices feature one synchronizable 4-channel general-purpose

timer. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. It

features four independent channels each for input capture/output compare, PWM or

one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the

largest packages.

The TIM3 general-purpose timer can work with the TIM1 advanced-control timer via the

Timer Link feature for synchronization or event chaining.

TIM3 has an independent DMA request generation.

This timer is capable of handling quadrature (incremental) encoder signals and the digital

outputs from 1 to 3 hall-effect sensors.

The counter can be frozen in debug mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM14 features one single channel for input capture/output compare, PWM or one-pulse

mode output.

Its counter can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single

channel for input capture/output compare, PWM or one-pulse mode output.

The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate

withTIM1 via the Timer Link feature for synchronization or event chaining.

TIM15 can be synchronized with TIM16 and TIM17.

TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and

independent DMA request generation.

Their counters can be frozen in debug mode.

3.11.3

3.11.4

Basic timers TIM6 and TIM7

These timers can be used as a generic 16-bit time base.

Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with

user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it

operates independently from the main clock, it can operate in Stop and Standby modes. It

20/93

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STM32F030x4/x6/x8/xC

Functional overview

can be used either as a watchdog to reset the device when a problem occurs, or as a free

running timer for application timeout management. It is hardware or software configurable

through the option bytes. The counter can be frozen in debug mode.

3.11.5

3.11.6

System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free

running. It can be used as a watchdog to reset the device when a problem occurs. It is

clocked from the APB clock (PCLK). It has an early warning interrupt capability and the

counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

•

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source (HCLK or HCLK/8)

3.12

Real-time clock (RTC)

The RTC is an independent BCD timer/counter. Its main features are the following:

•

Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format.

•

Automatic correction for 28, 29 (leap year), 30, and 31 day of the month.

Programmable alarm with wake up from Stop and Standby mode capability.

Periodic wakeup unit with programmable resolution and period (on STM32F030xC

only).

•

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize the RTC with a master clock.

Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal

inaccuracy.

Tow anti-tamper detection pins with programmable filter. The MCU can be woken up

from Stop and Standby modes on tamper event detection.

Timestamp feature which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be

woken up from Stop and Standby modes on timestamp event detection.

•

Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision.

The RTC clock sources can be:

•

A 32.768 kHz external crystal

A resonator or oscillator

The internal low-power RC oscillator (typical frequency of 40 kHz)

The high-speed external clock divided by 32

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Functional overview

STM32F030x4/x6/x8/xC

3.13

Inter-integrated circuit interfaces (I²C)

Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both

can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s). I2C1 also

supports Fast Mode Plus (up to 1 Mbit/s), with 20 mA output drive.

Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two

addresses, one with configurable mask). They also include programmable analog and

digital noise filters.

Table 6. Comparison of I2C analog and digital filters

-

Analog filter

Digital filter

Pulse width of

suppressed spikes

Programmable length from 1 to 15

I2C peripheral clocks

≥ 50 ns

1. Extra filtering capability vs.

standard requirements.

2. Stable length

Benefits

Available in Stop mode

Variations depending on

temperature, voltage, process

Drawbacks

-

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP

capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts

verifications and ALERT protocol management

The I2C interfaces can be served by the DMA controller.

Refer to Table 7 for the differences between I2C1 and I2C2.

2

(1)

Table 7. STM32F030x4/x6/x8/xC I C implementation

I2C features

I2C1

I2C2⁽²⁾

7-bit addressing mode

10-bit addressing mode

X

-

X

-

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus (up to 1 Mbit/s), with 20mA output drive I/Os

Independent clock

-

SMBus

-

Wakeup from STOP

-

1. X = supported.

2. Only available on STM32F030x8/C devices.

3.14

Universal synchronous/asynchronous receiver/transmitter

(USART)

The device embeds up to six universal synchronous/asynchronous receivers/transmitters

that communicate at speeds of up to 6 Mbit/s.

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Functional overview

Table 8 gives an overview of features as implemented on the available USART interfaces.

All USART interfaces can be served by the DMA controller.

(1)

Table 8. STM32F0x0 USART implementation

STM32F030x4

STM32F030x6

STM32F030x8

STM32F030xC

USART modes/

features

USART1

USART1 USART2 USART2 USART4 USART5 USART6

USART3

Hardware flow control

for modem

X

-

Continuous

communication using

DMA

X

Multiprocessor

communication

Synchronous mode

Smartcard mode

X

-

X

-

X

-

X

-

X

-

X

-

Single-wire Half-duplex

communication

X

IrDA SIR ENDEC block

LIN mode

-

Dual clock domain and

wakeup from Stop mode

-

Receiver timeout

interrupt

X

-

X

-

X

-

Modbus communication

Auto baud rate detection

(supported modes)

2

X

2

X

-

2

X

-

Driver Enable

X

USART data length

1. X = supported.

8 and 9 bits

7, 8 and 9 bits

3.15

Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-

duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame size is configurable from 4 bits to 16 bits.

SPI1 and SPI2 are identical and implement the set of features shown in the following table.

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Functional overview

STM32F030x4/x6/x8/xC

(1)

Table 9. STM32F030x4/x6/x8/xC SPI implementation

SPI features

Hardware CRC calculation

SPI1

SPI2⁽²⁾

X

Rx/Tx FIFO

NSS pulse mode

TI mode

1. X = supported.

2. Not available on STM32F030x4/6.

3.16

Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to

the MCU.

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Pinouts and pin descriptions

4

Pinouts and pin descriptions

Figure 4. LQFP64 64-pin package pinout (top view), for STM32F030x4/6/8 devices

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PF7

PF6

VDD

PC13

PC14-OSC32_IN

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

3

4

5

6

7

8

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VDDA

PA0

PA1

PA2

LQFP64

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

IO pins replaced by supply pairs for STM32F030RC devices.

MSv36496V2

Figure 5. LQFP64 64-pin package pinout (top view), for STM32F030RC devices

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

VDD

PC13

PC14-OSC32_IN

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

3

4

5

6

7

8

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VDDA

PA0

PA1

PA2

LQFP64

9

10

11

12

13

14

15

16

PC6

PB15

PB14

PB13

PB12

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Additional supply pins required for STM32F030RC devices.

MSv36483V2

DS9773 Rev 4

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33

Pinouts and pin descriptions

STM32F030x4/x6/x8/xC

Figure 6. LQFP48 48-pin package pinout (top view), for STM32F030x4/6/8 devices

48 47 46 45 44 43 42 41 40 39 38 37

36

35

34

33

32

31

30

29

28

27

26

25

VDD

PC13

PC14-OSC32_IN

1

2

3

4

5

6

7

8

9

10

11

12

PF7

PF6

PA13

PA12

PA11

PA10

PA9

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

NRST

VSSA

LQFP48

PA8

PB15

PB14

PB13

PB12

VDDA

PA0

PA1

PA2

24

13 14 15 16 17 18 19 20 21 22 23

IO pins replaced by supply pairs for STM32F030CC devices.

MSv36497V2

Figure 7. LQFP48 48-pin package pinout (top view), for STM32F030CC devices

48 47 46 45 44 43 42 41 40 39 38 37

36

35

34

33

32

31

30

29

28

27

26

25

VDD

PC13

PC14-OSC32_IN

1

2

3

4

5

6

7

8

9

10

11

12

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

NRST

VSSA

LQFP48

PA8

PB15

PB14

PB13

PB12

VDDA

PA0

PA1

PA2

24

13 14 15 16 17 18 19 20 21 22 23

Additional supply pins required for STM32F030CC devices.

MSv36484V2

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Pinouts and pin descriptions

Figure 8. LQFP32 32-pin package pinout (top view)

32 31 30 29 28 27 26 25

24

23

22

1

2

3

4

5

6

7

8

PA14

PA13

PA12

PA11

PA10

PA9

VDD

PF0-OSC_IN

PF1-OSC_OUT

NRST

VDDA

PA0

PA1

PA2

21

20

19

18

17

LQFP32

PA8

VDD

9 10 11 12 13 14 15 16

MS32144V1

Figure 9. TSSOP20 20-pin package pinout (top view)

BOOT0

20

19

18

1

2

3

4

PA14

PA13

PA10

PF0-OSC_IN

PF1-OSC_OUT

17

16

15

14

13

12

11

PA 9

VDD

VSS

PB1

PA7

NRST

VDDA

PA0

5

6

PA1

PA2

7

8

9

10

PA6

PA3

PA4

PA5

MSv36473V1

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33

Pinouts and pin descriptions

STM32F030x4/x6/x8/xC

Table 10. Legend/abbreviations used in the pinout table

Abbreviation Definition

Name

Unless otherwise specified in brackets below the pin name, the pin function during and

after reset is the same as the actual pin name

Pin name

S

I

Supply pin

Pin type

Input only pin

I/O

FT

FTf

TTa

TC

B

Input / output pin

5 V tolerant I/O

5 V tolerant I/O, FM+ capable

3.3 V tolerant I/O directly connected to ADC

Standard 3.3 V I/O

I/O structure

Dedicated BOOT0 pin

RST

Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after

reset.

Notes

Alternate

Functions selected through GPIOx_AFR registers

functions

Additional

functions

Functions directly selected/enabled through peripheral registers

Table 11. STM32F030x4/6/8/C pin definitions

Pin functions

Pin number

Pin name

(function after

reset)

Notes

Alternate functions

Additional functions

1

2

1

-

VDD

S

-

Complementary power supply

RTC_TAMP1,

RTC_TS,

(1)

2

-

PC13

I/O TC

-

RTC_OUT,

WKUP2

PC14-OSC32_IN

(PC14)

(1)

3

4

5

6

7

3

4

5

6

7

-

I/O TC

I/O FT

I/O RST

-

OSC32_IN

OSC32_OUT

OSC_IN

PC15-OSC32_OUT

(PC15)

-

PF0-OSC_IN

(PF0)

2

3

4

2

3

4

-

I2C1_SDA⁽⁵⁾

I2C1_SCL⁽⁵⁾

PF1-OSC_OUT

(PF1)

OSC_OUT

Device reset input / internal reset output

(active low)

NRST

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STM32F030x4/x6/x8/xC

Pinouts and pin descriptions

Pin functions

Table 11. STM32F030x4/6/8/C pin definitions (continued)

Pin number

Pin name

(function after

reset)

Notes

Alternate functions

Additional functions

EVENTOUT,

USART6_TX⁽⁵⁾

8

-

PC0

I/O TTa

-

ADC_IN10

EVENTOUT,

USART6_RX⁽⁵⁾

9

-

PC1

PC2

PC3

I/O TTa

-

ADC_IN11

ADC_IN12

ADC_IN13

SPI2_MISO⁽⁵⁾

EVENTOUT

,

10

11

SPI2_MOSI⁽⁵⁾

EVENTOUT

,

12

13

8

9

-

VSSA

VDDA

S

-

Analog ground

5

Analog power supply

USART1_CTS⁽²⁾

,

USART2_CTS⁽³⁾⁽⁵⁾

USART4_TX⁽⁵⁾

ADC_IN0,

RTC_TAMP2,

WKUP1

14

15

10

11

6

7

6

7

PA0

PA1

I/O TTa

-

,

USART1_RTS⁽²⁾

,

USART2_RTS⁽³⁾⁽⁵⁾

EVENTOUT,

,

ADC_IN1

USART4_RX⁽⁵⁾

USART1_TX⁽²⁾

,

16

17

12

13

8

9

8

9

PA2

PA3

-

USART2_TX⁽³⁾⁽⁵⁾

TIM15_CH1⁽³⁾⁽⁵⁾

,

ADC_IN2, WKUP4⁽⁵⁾

USART1_RX⁽²⁾

,

I/O TTa

I/O FT

USART2_RX⁽³⁾⁽⁵⁾

TIM15_CH2⁽³⁾⁽⁵⁾

,

ADC_IN3

-

18⁽⁴⁾

18⁽⁵⁾

19⁽⁴⁾

19⁽⁵⁾

-

PF4

VSS

PF5

VDD

EVENTOUT

(4)

(5)

(4)

(5)

S

-

Ground

I/O FT

-

Complementary power supply

SPI1_NSS,

USART1_CK⁽²⁾

USART2_CK⁽³⁾⁽⁵⁾

TIM14_CH1,

20

21

14

15

10 10

11 11

PA4

PA5

I/O TTa

-

,

ADC_IN4

ADC_IN5

USART6_TX⁽⁵⁾

SPI1_SCK,

USART6_RX⁽⁵⁾

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33

Pinouts and pin descriptions

STM32F030x4/x6/x8/xC

Table 11. STM32F030x4/6/8/C pin definitions (continued)

Pin functions

Pin number

Pin name

(function after

reset)

Notes

Alternate functions

Additional functions

SPI1_MISO,

TIM3_CH1,

TIM1_BKIN,

TIM16_CH1,

EVENTOUT

USART3_CTS⁽⁵⁾

22

23

16

17

12 12

PA6

PA7

I/O TTa

-

ADC_IN6

SPI1_MOSI,

TIM3_CH2,

TIM14_CH1,

TIM1_CH1N,

TIM17_CH1,

EVENTOUT

13 13

I/O TTa

ADC_IN7

EVENTOUT,

24

25

-

PC4

PC5

I/O TTa

-

ADC_IN14

USART3_TX⁽⁵⁾

USART3_RX⁽⁵⁾

ADC_IN15, WKUP5⁽⁵⁾

TIM3_CH3,

TIM1_CH2N,

EVENTOUT,

USART3_CK⁽⁵⁾

26

18

14

-

PB0

I/O TTa

-

ADC_IN8

TIM3_CH4,

TIM14_CH1,

27

28

29

19

20

21

15 14

PB1

PB2

I/O TTa

I/O FT

-

ADC_IN9

TIM1_CH3N,

USART3_RTS⁽⁵⁾

(6)

-

SPI2_SCK⁽⁵⁾

I2C1_SCL⁽²⁾

I2C2_SCL⁽³⁾⁽⁵⁾

USART3_TX⁽⁵⁾

,

PB10

-

,

I2C1_SDA⁽²⁾

,

I2C2_SDA⁽³⁾⁽⁵⁾

EVENTOUT,

,

30

22

-

PB11

I/O FT

-

USART3_RX⁽⁵⁾

31

32

23

24

16

VSS

VDD

S

-

Ground

Digital power supply

17 16

SPI1_NSS⁽²⁾

,

SPI2_NSS⁽³⁾⁽⁵⁾

TIM1_BKIN,

,

33

25

-

PB12

I/O FT

-

EVENTOUT,

USART3_CK⁽⁵⁾

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STM32F030x4/x6/x8/xC

Pinouts and pin descriptions

Pin functions

Table 11. STM32F030x4/6/8/C pin definitions (continued)

Pin number

Pin name

(function after

reset)

Notes

Alternate functions

Additional functions

SPI1_SCK⁽²⁾

SPI2_SCK⁽³⁾⁽⁵⁾

I2C2_SCL⁽⁵⁾

TIM1_CH1N,

USART3_CTS⁽⁵⁾

,

34

35

36

26

27

28

-

PB13

PB14

PB15

I/O FT

-

,

-

SPI1_MISO⁽²⁾

SPI2_MISO⁽³⁾⁽⁵⁾

I2C2_SDA⁽⁵⁾

TIM1_CH2N,

TIM15_CH1⁽³⁾⁽⁵⁾

USART3_RTS⁽⁵⁾

,

-

,

SPI1_MOSI⁽²⁾

,

SPI2_MOSI⁽³⁾⁽⁵⁾

TIM1_CH3N,

,

RTC_REFIN,

WKUP7⁽⁵⁾

TIM15_CH1N⁽³⁾⁽⁵⁾

TIM15_CH2⁽³⁾⁽⁵⁾

,

37

38

39

40

-

PC6

PC7

PC8

PC9

I/O FT

-

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

-

USART1_CK,

TIM1_CH1,

EVENTOUT,

MCO

41

42

43

44

45

29

30

31

32

33

18

-

PA8

PA9

I/O FT

-

USART1_TX,

TIM1_CH2,

19 17

20 18

TIM15_BKIN⁽³⁾⁽⁵⁾

I2C1_SCL⁽²⁾⁽⁵⁾

USART1_RX,

TIM1_CH3,

PA10

PA11

PA12

TIM17_BKIN

I2C1_SDA⁽²⁾⁽⁵⁾

USART1_CTS,

TIM1_CH4,

21

22

-

EVENTOUT,

I2C2_SCL⁽⁵⁾

USART1_RTS,

TIM1_ETR,

EVENTOUT,

I2C2_SDA⁽⁵⁾

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33

Pinouts and pin descriptions

STM32F030x4/x6/x8/xC

Table 11. STM32F030x4/6/8/C pin definitions (continued)

Pin functions

Pin number

Pin name

(function after

reset)

Notes

Alternate functions

Additional functions

PA13

(SWDIO)

IR_OUT,

SWDIO

(7)

46

34

23 19

I/O FT

-

I2C1_SCL⁽²⁾

I2C2_SCL⁽³⁾

,

(4)

(5)

(4)

(5)

47⁽⁴⁾35⁽⁴⁾

47⁽⁵⁾35⁽⁵⁾

48⁽⁴⁾36⁽⁴⁾

48⁽⁵⁾36⁽⁵⁾

-

PF6

VSS

PF7

VDD

S

-

Ground

I2C1_SDA⁽²⁾

I2C2_SDA⁽³⁾

,

I/O FT

-

S

-

Complementary power supply

USART1_TX⁽²⁾

,

USART2_TX⁽³⁾⁽⁵⁾

SWCLK

PA14

(SWCLK)

(7)

49

50

37

38

24 20

I/O FT

,

-

SPI1_NSS,

USART1_RX⁽²⁾

,

25

-

PA15

-

USART2_RX⁽³⁾⁽⁵⁾

,

USART4_RTS⁽⁵⁾

EVENTOUT

,

USART3_TX⁽⁵⁾

USART4_TX⁽⁵⁾

,

51

52

-

PC10

PC11

I/O FT

-

USART3_RX⁽⁵⁾

USART4_RX⁽⁵⁾

,

USART3_CK⁽⁵⁾

USART4_CK⁽⁵⁾

,

53

54

55

-

PC12

PD2

PB3

I/O FT

-

,

-

USART5_TX⁽⁵⁾

TIM3_ETR,

USART3_RTS⁽⁵⁾

USART5_RX⁽⁵⁾

,

SPI1_SCK,

EVENTOUT,

USART5_TX⁽⁵⁾

39

26

SPI1_MISO,

TIM3_CH1,

EVENTOUT,

56

57

40

41

27

28

-

PB4

PB5

I/O FT

-

TIM17_BKIN⁽⁵⁾

,

USART5_RX⁽⁵⁾

SPI1_MOSI,

I2C1_SMBA,

TIM16_BKIN,

TIM3_CH2,

I/O FT

WKUP6⁽⁵⁾

USART5_CK_RTS⁽⁵⁾

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STM32F030x4/x6/x8/xC

Pinouts and pin descriptions

Pin functions

Table 11. STM32F030x4/6/8/C pin definitions (continued)

Pin number

Pin name

(function after

reset)

Notes

Alternate functions

Additional functions

I2C1_SCL,

USART1_TX,

TIM16_CH1N

58

59

42

43

29

30

-

PB6

PB7

I/O FTf

-

I2C1_SDA,

USART1_RX,

TIM17_CH1N,

USART4_CTS⁽⁵⁾

60

61

44

45

31

-

1

-

BOOT0

PB8

I

B

-

Boot memory selection

I2C1_SCL,

TIM16_CH1

(6)

I/O FTf

-

I2C1_SDA,

IR_OUT,

62

46

-

PB9

I/O FTf

-

SPI2_NSS⁽⁵⁾

,

TIM17_CH1,

EVENTOUT

63

64

47

48

32 15

16

VSS

VDD

S

-

Ground

Digital power supply

1

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. This feature is available on STM32F030x6 and STM32F030x4 devices only.

3. This feature is available on STM32F030x8 devices only.

4. For STM32F030x4/6/8 devices only.

5. For STM32F030xC devices only.

6. On LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not available on the

package, they are not forced to a defined level by hardware).

7. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on SWDIO pin

and internal pull-down on SWCLK pin are activated.

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33

STM32F030x4/x6/x8/xC

(1)

Table 14. Alternate functions selected through GPIOC_AFR registers for port C

Pin name

AF0⁽²⁾

AF1⁽¹⁾

AF2⁽¹⁾

PC0

PC1

EVENTOUT

-

USART6_TX

-

USART6_RX

PC2

SPI2_MISO

-

PC3

SPI2_MOSI

-

PC4

USART3_TX

-

PC5

USART3_RX

-

PC6

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

USART4_TX⁽¹⁾

USART4_RX⁽¹⁾

USART4_CK⁽¹⁾

-

PC7

-

PC8

-

PC9

-

PC10

PC11

PC12

PC13

PC14

PC15

USART3_TX

-

USART3_RX

-

USART3_CK

USART5_TX

-

1. Available on STM32F030xC devices only.

2. Default alternate functions for STM32F030x4/x6/x8 devices (they do not have the GPIOC_AFR registers).

(1)

Table 15. Alternate functions selected through GPIOD_AFR registers for port D

Pin name

AF0⁽²⁾

AF1⁽¹⁾

AF2⁽¹⁾

PD2

TIM3_ETR

USART3_RTS

USART5_RX

1. Available on STM32F030xC devices only.

2. Default alternate functions for STM32F030x4/x6/x8 devices (they do not have the GPIOD_AFR registers).

(1)

Table 16. Alternate functions selected through GPIOF_AFR registers for port F

Pin name

AF0⁽²⁾

AF1⁽¹⁾

PF0

PF1

PF4

PF5

PF6

PF7

-

I2C1_SDA

I2C1_SCL

-

EVENTOUT⁽¹⁾

I2C1_SCL⁽³⁾, I2C2_SCL⁽⁴⁾

I2C1_SDA⁽³⁾, I2C2_SDA⁽⁴⁾

1. Available on STM32F030xC devices only.

2. Default alternate functions for STM32F030x4/x6/x8 devices (they do not have the GPIOF_AFR registers).

3. Applies to STM32F030x4/x6

4. Applies to STM32F030x8

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37

Memory mapping

STM32F030x4/x6/x8/xC

5

Memory mapping

Figure 10. STM32F030x4/x6/x8/xC memory map

0xFFFF FFFF

0x4800 17FF

AHB2

0x4800 0000

Reserved

7

0xE010 0000

Cortex-M0 internal

peripherals

0xE000 0000

Reserved

6

0xC000 0000

0x4002 43FF

AHB1

0x4002 0000

Reserved

5

Reserved

0xA000 0000

0x4001 8000

APB

4

Reserved

0x1FFF FFFF

Reserved

0x1FFF FC00

0x4001 0000

Option Bytes

0x1FFF F800

0x8000 0000

Reserved

System memory

0x1FFF xx00⁽¹⁾

0x4000 8000

3

Reserved

APB

0x6000 0000

0x4000 0000

Reserved

2

Peripherals

Reserved

0x4000 0000

0x0804 0000

1

Flash memory

0x0800 0000

SRAM

CODE

0x2000 0000

Reserved

0

0x0004 0000

Flash, system

memory or SRAM,

depending on BOOT

configuration

0x0000 0000

MSv36474V2

1. The start address of the system memory is 0x1FFF EC00 for STM32F030x4, STM32F030x6 and STM32F030x8 devices,

and 0x1FFF D800 for STM32F030xC devices.

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Memory mapping

Table 17. STM32F030x4/x6/x8/xC peripheral register boundary addresses

Bus

Boundary address

Size

Peripheral

-

AHB2

-

0x4800 1800 - 0x5FFF FFFF

0x4800 1400 - 0x4800 17FF

0x4800 1000 - 0x4800 13FF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 3400 - 0x4002 43FF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0000 - 0x4002 03FF

0x4001 8000 - 0x4001 FFFF

0x4001 5C00 - 0x4001 7FFF

0x4001 5800 - 0x4001 5BFF

0x4001 4C00 - 0x4001 57FF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2800 - 0x4001 2BFF

0x4001 2400 - 0x4001 27FF

0x4001 1800 - 0x4001 23FF

0x4001 1400 - 0x4001 17FF

0x4001 0800 - 0x4001 13FF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

~384 MB Reserved

1 KB

GPIOF

Reserved

GPIOD

GPIOC

GPIOB

GPIOA

~128 MB Reserved

4 KB

1 KB

3 KB

1 KB

3 KB

1 KB

3 KB

1 KB

32 KB

9 KB

1 KB

3 KB

1 KB

3 KB

1 KB

3 KB

1 KB

Reserved

CRC

Reserved

FLASH Interface

Reserved

RCC

AHB1

Reserved

DMA

-

Reserved

DBGMCU

Reserved

TIM17

TIM16

TIM15⁽¹⁾

Reserved

USART1

Reserved

SPI1

APB

TIM1

Reserved

ADC

Reserved

USART6⁽²⁾

Reserved

EXTI

SYSCFG

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40

Memory mapping

STM32F030x4/x6/x8/xC

Table 17. STM32F030x4/x6/x8/xC peripheral register boundary addresses (continued)

Bus

Boundary address

Size

32 KB

Peripheral

Reserved

-

0x4000 8000 - 0x4000 FFFF

0x4000 7400 - 0x4000 7FFF

0x4000 7000 - 0x4000 73FF

0x4000 5C00 - 0x4000 6FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 3C00 - 0x4000 43FF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1800 - 0x4000 1FFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0800 - 0x4000 0FFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

3 KB

1 KB

5 KB

1 KB

2 KB

1 KB

2 KB

1 KB

2 KB

1 KB

Reserved

PWR

Reserved

I2C2⁽¹⁾

I2C1

USART5⁽²⁾

USART4⁽²⁾

USART3⁽²⁾

USART2⁽¹⁾

Reserved

SPI2⁽¹⁾

APB

Reserved

IWDG

WWDG

RTC

Reserved

TIM14

Reserved

TIM7⁽²⁾

TIM6⁽¹⁾

Reserved

TIM3

Reserved

1. This feature is available on STM32F030x8 and STM32F030xC devices only. For STM32F030x6 and

STM32F060x4, the area is Reserved.

2. This feature is available on STM32F030xC devices only. This area is reserved for STM32F030x4/6/8

devices.

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STM32F030x4/x6/x8/xC

Electrical characteristics

6

Electrical characteristics

6.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

6.1.1

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2

6.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3.3 V. They

DDA

are given only as design guidelines and are not tested.

A

DD

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean ±2σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

6.1.4

6.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

Figure 11. Pin loading conditions

Figure 12. Pin input voltage

MCU pin

C = 50 pF

V_IN

MS19210V1

MS19211V1

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Electrical characteristics

STM32F030x4/x6/x8/xC

6.1.6

Power supply scheme

Figure 13. Power supply scheme

LSE, RTC,

Wake-up logic

Power switch

V_DD

V_CORE

2 x V_DD

Regulator

V_DDIO1

OUT

Kernel logic

(CPU, Digital

& Memories)

IO

logic

2 x 100 nF

+1 x 4.7 μF

GPIOs

IN

2 x V_SS

V_DDA

10 nF

+1 μF

V^REF+

VREF-

Analog:

(RCs, PLL, …)

ADC

V_SSA

MSv39025V1

Caution:

Each power supply pair (V /V , V

/V

etc.) must be decoupled with filtering ceramic

DD SS DDA SSA

capacitors as shown above. These capacitors must be placed as close as possible to, or

below, the appropriate pins on the underside of the PCB to ensure the good functionality of

the device.

6.1.7

Current consumption measurement

Figure 14. Current consumption measurement scheme

I

DD

V

DD

I

DDA

V

DDA

MS32142V2

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Electrical characteristics

6.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,

Table 19: Current characteristics and Table 20: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

(1)

Table 18. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

V

_DD–V_SSExternal main supply voltage

-0.3

4.0

V

V_DDA–V_SSExternal analog supply voltage

V_DD–V_DDAAllowed voltage difference for V_DD> V_DDA

Input voltage on FT and FTf pins

-0.3

4.0

-

0.4

V_DDIOx+ 4.0 ⁽³⁾

4.0

V

V_SS−0.3

0

V

Input voltage on TTa pins

V

(2)

V_IN

BOOT0

V

_DDIOx+ 4.0 ⁽³⁾

V

Input voltage on any other pin

V_SS−0.3

-

4.0

50

V

|ΔV_DDx

|

Variations between different V_DDpower pins

mV

Variations between all the different ground

pins

|V_SSx−V_SS

|

-

50

mV

-

Electrostatic discharge voltage

(human body model)

see Section 6.3.12: Electrical

sensitivity characteristics

V_ESD(HBM)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. V_INmaximum must always be respected. Refer to Table 19: Current characteristics for the maximum

allowed injected current values.

3. V_DDIOxis internally connected with VDD pin.

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75

Electrical characteristics

Symbol

STM32F030x4/x6/x8/xC

Table 19. Current characteristics

Ratings

Max.

Unit

ΣI_VDD

ΣI_VSS

Total current into sum of all VDD power lines (source)⁽¹⁾

Total current out of sum of all VSS ground lines (sink)⁽¹⁾

Maximum current into each VDD power pin (source)⁽¹⁾

Maximum current out of each VSS ground pin (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins⁽²⁾

Total output current sourced by sum of all I/Os and control pins⁽²⁾

Injected current on FT and FTf pins

120

-120

100

-100

25

I_VDD(PIN)

I_VSS(PIN)

I_IO(PIN)

-25

mA

80

ΣI_IO(PIN)

-80

-5/+0⁽⁴⁾

(3)

I_INJ(PIN)

Injected current on TC and RST pin

± 5

Injected current on TTa pins⁽⁵⁾

± 5

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁶⁾

± 25

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the

permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be

sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. A positive injection is induced by V_IN> V_DDIOxwhile a negative injection is induced by V_IN< V_SS. I_INJ(PIN)must never be

exceeded. Refer to Table 18: Voltage characteristics for the maximum allowed input voltage values.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum

value.

5. On these I/Os, a positive injection is induced by V_IN> V_DDA. Negative injection disturbs the analog performance of the

device. See note ⁽²⁾below Table 52: ADC accuracy.

6. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the positive and

negative injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol

Ratings

Storage temperature range

Maximum junction temperature

Value

Unit

T_STG

T_J

–65 to +150

150

°C

6.3

Operating conditions

6.3.1

General operating conditions

Table 21. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK

V_DD

Internal AHB clock frequency

Internal APB clock frequency

Standard operating voltage

-

0

48

MHz

V

2.4

3.6

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STM32F030x4/x6/x8/xC

Symbol

Electrical characteristics

Table 21. General operating conditions (continued)

Parameter

Conditions

Min

Max

Unit

Must have a potential equal

to or higher than V_DD

V_DDA

Analog operating voltage

I/O input voltage

2.4

3.6

V

TC and RST I/O

TTa I/O

-0.3

0

V_DDIOx+0.3

V

_DDA+0.3⁽²⁾

5.5⁽²⁾

5.5

V_IN

V

FT and FTf I/O

BOOT0

LQFP64

-

455

LQFP48

-

364

Power dissipation at T_A= 85 °C

for suffix 6 ⁽¹⁾

P_D

mW

LQFP32

-

357

TSSOP20

-

263

Maximum power dissipation

Low power dissipation⁽²⁾

Suffix 6 version

-40

85

Ambient temperature for the

suffix 6 version

T_A

T_J

°C

105

Junction temperature range

105

1. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax

.

2. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax(see Section 7.5:

Thermal characteristics).

6.3.2

Operating conditions at power-up / power-down

The parameters given in Table 22 are derived from tests performed under the ambient

temperature condition summarized in Table 21.

Table 22. Operating conditions at power-up / power-down

Symbol

Parameter

V_DDrise time rate

V_DDfall time rate

V_DDArise time rate

V_DDAfall time rate

Conditions

Min

0

Max

Unit

∞

t_VDD

-

20

0

∞

µs/V

∞

t_VDDA

-

20

∞

6.3.3

Embedded reset and power control block characteristics

The parameters given in Table 23 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 21: General operating

conditions.

Table 23. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Falling edge⁽²⁾

Rising edge

1.96⁽³⁾

2.00

1.80

1.88

1.92

V

Power on/power down

reset threshold

(1)

V_POR/PDR

1.84⁽³⁾

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Electrical characteristics

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Table 23. Embedded reset and power control block characteristics (continued)

Symbol

Parameter

PDR hysteresis

Reset temporization

Conditions

Min

Typ

Max

Unit

V_PDRhyst

-

40

-

mV

ms

(4)

t_RSTTEMPO

1.50

2.50

4.50

1. The PDR detector monitors V_DDand also V_DDA(if kept enabled in the option bytes). The POR detector

monitors only V_DD

.

2. The product behavior is guaranteed by design down to the minimum V_POR/PDRvalue.

3. Data based on characterization results, not tested in production.

4. Guaranteed by design, not tested in production.

6.3.4

Embedded reference voltage

The parameters given in Table 24 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 21: General operating

conditions.

Table 24. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Internal reference

voltage

-40°C < T_A< +85°C

1.2

1.23

1.25

V

REFINT

ADC_IN17 buffer startup

time

t_START

-

10⁽¹⁾

µs

ADC sampling time when

reading the internal

reference voltage

4 ⁽¹⁾

t_{S_vrefint}

-

Internal reference

voltage spread over the

temperature range

10⁽¹⁾

ΔV_REFINT

V_DDA= 3 V

-

mV

-100⁽¹⁾

100⁽¹⁾

T_Coeff

Temperature coefficient

-

ppm/°C

1. Guaranteed by design, not tested in production.

6.3.5

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 14: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a

reduced code that gives a consumption equivalent to CoreMark code.

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Electrical characteristics

Typical and maximum current consumption

The MCU is placed under the following conditions:

•

All I/O pins are in analog input mode

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted to the f

frequency:

HCLK

–

0 wait state and Prefetch OFF from 0 to 24 MHz

1 wait state and Prefetch ON above 24 MHz

= f

•

When the peripherals are enabled f

PCLK

HCLK

The parameters given in Table 25 to Table 27 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in Table 21: General

operating conditions.

(1)

Table 25. Typical and maximum current consumption from V supply at V = 3.6 V

DD

All peripherals enabled

(2)

Max @ T_A

Parameter

Conditions

f_HCLK

Unit

Typ

85 °C

48 MHz

24 MHz

8 MHz

22.0

26.8

12.2

14.1

4.4

22.8

30.2

13.2

16.2

5.2

HSI or HSE clock, PLL on

HSI or HSE clock, PLL off

HSI or HSE clock, PLL on

HSI or HSE clock, PLL off

HSI or HSE clock, PLL on

HSI or HSE clock, PLL off

Supply current in

Run mode, code

executing from Flash

I_DD

mA

8 MHz

4.9

5.6

48 MHz

24 MHz

8 MHz

22.2

26.1

11.2

13.3

4.0

23.2

29.3

12.2

15.7

4.5

Supply current in

Run mode, code

executing from RAM

mA

8 MHz

4.6

5.2

48 MHz

24 MHz

8 MHz

14

15.3

19.0

7.8

17.0

7.3

Supply current in

Sleep mode, code

executing from Flash

or RAM

mA

8.7

10.1

2.9

2.6

8 MHz

3.0

3.5

1. The gray shading is used to distinguish the values for STM32F030xC devices.

2. Data based on characterization results, not tested in production unless otherwise specified.

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(1)

Table 26. Typical and maximum current consumption from the V

supply

DDA

V_DDA= 3.6 V

Max @ T_A

(3)

Symbol

Parameter

Conditions⁽²⁾

f_HCLK

Unit

Typ

85 °C

48 MHz

8 MHz

1 MHz

48 MHz

8 MHz

175

160

3.9

3.7

3.9

3.3

244

235

85

215

192

4.9

4.6

4.1

4.4

275

105

92

HSE bypass, PLL on

Supply current in

Run or Sleep mode,

code executing

from Flash memory

or RAM

HSE bypass, PLL off

I_DDA

µA

HSI clock, PLL on

HSI clock, PLL off

77

1. The gray shading is used to distinguish the values for STM32F030xC devices.

2. Current consumption from the V_DDAsupply is independent of whether the digital peripherals are enabled or disabled, being

in Run or Sleep mode or executing from Flash or RAM. Furthermore, when the PLL is off, I_DDAis independent of the

frequency.

3. Data based on characterization results, not tested in production.

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Table 27. Typical and maximum consumption in Stop and Standby modes

Typ @V_DD

(V_DD= V_DDA

Max⁽¹⁾

)

Symbol

Parameter

Conditions

Unit

3.6 V

19

T_A= 85 °C

Regulator in run mode, all oscillators OFF

48

32

Supply current in

Stop mode

Regulator in low-power mode, all oscillators OFF

5

I_DD

Supply current in

Standby mode

LSI ON and IWDG ON

2

-

Regulator in run or low-

power mode, all

oscillators OFF

Supply current in

Stop mode

2.9

3.5

V_DDAmonitoring ON

µA

LSI ON and IWDG ON

3.3

2.8

-

Supply current in

Standby mode

LSI OFF and IWDG OFF

3.5

I_DDA

Regulator in run or low-

power mode, all

oscillators OFF

Supply current in

Stop mode

1.7

-

V_DDAmonitoring OFF

LSI ON and IWDG ON

2.3

1.4

-

Supply current in

Standby mode

LSI OFF and IWDG OFF

1. Data based on characterization results, not tested in production unless otherwise specified.

Typical current consumption

The MCU is placed under the following conditions:

•

V

= V

= 3.3 V

DDA

DD

All I/O pins are in analog input configuration

The Flash access time is adjusted to f

frequency:

HCLK

–

0 wait state and Prefetch OFF from 0 to 24 MHz

1 wait state and Prefetch ON above 24 MHz

= f

•

When the peripherals are enabled, f

PCLK

HCLK

PLL is used for frequencies greater than 8 MHz

AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and

500 kHz respectively

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Table 28. Typical current consumption in Run mode, code with data processing

running from Flash

Typ

Symbol

Parameter

Conditions

f_HCLK

Unit

Peripherals Peripherals

enabled

disabled

Supply current in Run

mode from V_DD

supply

48 MHz

8 MHz

48 MHz

8 MHz

23.3

11.5

Running from

HSE crystal

clock 8 MHz,

code executing

from Flash

I_DD

mA

µA

4.5

3.0

Supply current in Run

mode from V_DDA

supply

158

I_DDA

2.43

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is

externally held low. The value of this current consumption can be simply computed by using

the pull-up/pull-down resistors values given in Table 46: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to

estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate

voltage level is externally applied. This current consumption is caused by the input Schmitt

trigger circuits used to discriminate the input value. Unless this specific configuration is

required by the application, this supply current consumption can be avoided by configuring

these I/Os in analog mode. This is notably the case of ADC input pins which should be

configured as analog inputs.

Caution:

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to

floating pins, they must either be configured in analog mode, or forced internally to a definite

digital value. This can be done either by using pull-up/down resistors or by configuring the

pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously, the I/Os

used by an application also contribute to the current consumption. When an I/O pin

switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to

charge/discharge the capacitive load (internal or external) connected to the pin:

I_SW= V_DDIOx× f_SW× C

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where

I

is the current sunk by a switching I/O to charge/discharge the capacitive load

SW

V

is the I/O supply voltage

DDIOx

f

is the I/O switching frequency

SW

C is the total capacitance seen by the I/O pin: C = C

+ C

EXT S

INT

C is the PCB board capacitance including the pad pin.

S

The test pin is configured in push-pull output mode and is toggled by software at a fixed

frequency.

Table 29. Switching output I/O current consumption

I/O toggling

Symbol

Parameter

Conditions⁽¹⁾

Typ

Unit

frequency (f_SW

)

4 MHz

8 MHz

16 MHz

24 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

4 MHz

8 MHz

0.18

0.37

0.76

1.39

2.188

0.49

0.94

2.38

3.99

0.81

1.7

V

_DDIOx= 3.3 V

C_EXT= 0 pF

C = C_INT+ C_EXT+ C_S

I/O current

consumption

I_SW

mA

V_DDIOx= 3.3 V

C_EXT= 22 pF

C = C_INT+ C_EXT+ C_S

V_DDIOx= 3.3 V

C_EXT= 47 pF

C = C_INT+ C_EXT+ C_S

C = C_int

16 MHz

3.67

1. C_S= 7 pF (estimated value).

6.3.6

Wakeup time from low-power mode

The wakeup times given in Table 30 are the latency between the event and the execution of

the first user instruction. The device goes in low-power mode after the WFE (Wait For

Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles

must be added to the following timings due to the interrupt latency in the Cortex M0

architecture.

The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.

During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.

The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.

The wakeup source from Standby mode is the WKUP1 pin (PA0).

All timings are derived from tests performed under the ambient temperature and supply

voltage conditions summarized in Table 21: General operating conditions.

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Table 30. Low-power mode wakeup timings

Typ @VDD =

VDDA

Symbol

Parameter

Conditions

Max Unit

= 3.3 V

t_WUSTOP

Wakeup from Stop mode

Regulator in run mode

-

2.8

51

5

t_WUSTANDBYWakeup from Standby mode

t_WUSLEEPWakeup from Sleep mode

-

µs

4 SYSCLK

cycles

-

6.3.7

External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,

the recommended clock input waveform is shown in Figure 15: High-speed external clock

source AC timing diagram.

Table 31. High-speed external user clock characteristics

Symbol

Parameter⁽¹⁾

Min

Typ

Max

Unit

f_{HSE_ext}User external clock source frequency

V_HSEHOSC_IN input pin high level voltage

1

8

-

32

MHz

0.7 V_DDIOx

V_SS

V_DDIOx

V

V_HSEL

OSC_IN input pin low level voltage

OSC_IN high or low time

-

0.3 V_DDIOx

t_w(HSEH)

t_w(HSEL)

15

-

ns

t_r(HSE)

t_f(HSE)

OSC_IN rise or fall time

20

1. Guaranteed by design, not tested in production.

Figure 15. High-speed external clock source AC timing diagram

t

w(HSEH)

V

HSEH

90%

10%

V

HSEL

t

r(HSE)

f(HSE)

w(HSEL)

T

HSE

MS19214V2

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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,

the recommended clock input waveform is shown in Figure 16.

Table 32. Low-speed external user clock characteristics

Symbol

Parameter⁽¹⁾

Min

Typ

Max

Unit

f_{LSE_ext}User external clock source frequency

V_LSEHOSC32_IN input pin high level voltage

V_LSELOSC32_IN input pin low level voltage

-

32.768

1000

V_DDIOx

kHz

0.7 V_DDIOx

V_SS

-

V

0.3 V_DDIOx

t_w(LSEH)

OSC32_IN high or low time

t_w(LSEL)

450

-

ns

t_r(LSE)

OSC32_IN rise or fall time

t_f(LSE)

50

1. Guaranteed by design, not tested in production.

Figure 16. Low-speed external clock source AC timing diagram

t

w(LSEH)

V

LSEH

90%

10%

V

LSEL

t

r(LSE)

f(LSE)

t

w(LSEL)

T

LSE

MS19215V2

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on design

simulation results obtained with typical external components specified in Table 33. In the

application, the resonator and the load capacitors have to be placed as close as possible to

the oscillator pins in order to minimize output distortion and startup stabilization time. Refer

to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Table 33. HSE oscillator characteristics

Symbol

f_{OSC_IN}Oscillator frequency

R_FFeedback resistor

Parameter

Conditions⁽¹⁾

Min⁽²⁾Typ Max⁽²⁾Unit

-

4

-

8

32

-

MHz

200

kΩ

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Symbol

STM32F030x4/x6/x8/xC

Table 33. HSE oscillator characteristics

Parameter

Conditions⁽¹⁾

Min⁽²⁾Typ Max⁽²⁾Unit

During startup⁽³⁾

-

8.5

V_DD= 3.3 V,

Rm = 45 Ω,

CL = 10 pF@8 MHz

-

0.5

-

I_DD

HSE current consumption

mA

V_DD= 3.3 V,

Rm = 30 Ω,

CL = 20 pF@32 MHz

-

1.5

-

g_m

Oscillator transconductance

Startup time

Startup

10

-

mA/V

ms

(4)

t_SU(HSE)

V_DDis stabilized

2

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design, not tested in production.

3. This consumption level occurs during the first 2/3 of the t_SU(HSE)startup time

4. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

For C and C , it is recommended to use high-quality external ceramic capacitors in the

L1

L2

5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 17). C and C are usually the

L1

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of C and C . PCB and MCU pin capacitance must be included (10 pF

L1

L2

can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C .

C

L1

L2

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 17. Typical application with an 8 MHz crystal

Resonator with integrated

capacitors

C_L1

OSC_IN

f_HSE

Bias

controlled

gain

8 MHz

resonator

R_F

(1)

OSC_OUT

R_EXT

C_L2

MS19876V1

1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator

oscillator. All the information given in this paragraph are based on design simulation results

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obtained with typical external components specified in Table 34. In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

Table 34. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Conditions⁽¹⁾

Min⁽²⁾Typ Max⁽²⁾Unit

low drive capability

medium-low drive capability

medium-high drive capability

high drive capability

-

0.5

0.9

-

1

LSE current

consumption

I_DD

µA

-

1.3

-

1.6

low drive capability

5

8

15

25

-

medium-low drive capability

medium-high drive capability

high drive capability

-

Oscillator

transconductance

g_m

µA/V

s

-

(3)

t_SU(LSE)

Startup time

V_DDIOxis stabilized

2

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator

design guide for ST microcontrollers”.

2. Guaranteed by design, not tested in production.

3. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly

with the crystal manufacturer

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 18. Typical application with a 32.768 kHz crystal

Resonator with integrated

capacitors

C_L1

OSC32_IN

f_LSE

Drive

32.768 kHz

resonator

programmable

amplifier

OSC32_OUT

C_L2

MS30253V2

Note:

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden

to add one.

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6.3.8

Internal clock source characteristics

The parameters given in Table 35 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 21: General operating

conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI) RC oscillator

(1)

Table 35. HSI oscillator characteristics

Symbol

Parameter

Frequency

HSI user trimming step

Conditions

Min

Typ

Max

Unit

f_HSI

-

8

-

1⁽²⁾

55⁽²⁾

-

MHz

%

TRIM

-

45⁽²⁾

-

DuCy_HSIDuty cycle

-

T_A= -40 to 85°C

T_A= 25°C

-

%

±5

±1⁽³⁾

-

%

Accuracy of the HSI oscillator

(factory calibrated)

ACC_HSI

-

%

t_SU(HSI)

HSI oscillator startup time

1⁽²⁾

2⁽²⁾

µs

HSI oscillator power

consumption

I_DDA(HSI)

-

80

-

µA

1. V_DDA= 3.3 V, T_A= -40 to 85°C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. With user calibration.

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

(1)

Table 36. HSI14 oscillator characteristics

Symbol

Parameter

Frequency

HSI14 user-trimming step

Conditions

Min

Typ

Max

Unit

f_HSI14

TRIM

-

14

-

MHz

%

1⁽²⁾

55⁽²⁾

DuCy_(HSI14)Duty cycle

Accuracy of the HSI14

45⁽²⁾

-

%

ACC_HSI14

T_A= –40 to 85 °C

-

1⁽²⁾

-

±5

-

2⁽²⁾

-

%

µs

µA

oscillator (factory calibrated)

t_su(HSI14)HSI14 oscillator startup time

-

HSI14 oscillator power

I_DDA(HSI14)

100

consumption

1. V_DDA= 3.3 V, T_A= -40 to 85 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

Low-speed internal (LSI) RC oscillator

(1)

Table 37. LSI oscillator characteristics

Symbol

Parameter

Min

Typ

Max

50

Unit

kHz

f_LSI

Frequency

30

40

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(1)

Table 37. LSI oscillator characteristics

Parameter

Min

Typ

Max

Unit

(2)

t_su(LSI)

LSI oscillator startup time

-

85

-

µs

(2)

I_DDA(LSI)

LSI oscillator power consumption

0.75

µA

1. V_DDA= 3.3 V, T_A= -40 to 85 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

6.3.9

PLL characteristics

The parameters given in Table 38 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 21: General operating

conditions.

Table 38. PLL characteristics

Value

Symbol

Parameter

Unit

Min

Typ

Max

PLL input clock⁽¹⁾

1⁽²⁾

40⁽²⁾

16⁽²⁾

-

8.0

24⁽²⁾

60⁽²⁾

48

MHz

%

f_{PLL_IN}

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

-

f_{PLL_OUT}

t_LOCK

MHz

µs

200⁽²⁾

300⁽²⁾

Jitter_PLL

Cycle-to-cycle jitter

-

ps

1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the

range defined by f_{PLL_OUT}

.

2. Guaranteed by design, not tested in production.

6.3.10

Memory characteristics

Flash memory

The characteristics are given at T = -40 to 85 °C unless otherwise specified.

A

Table 39. Flash memory characteristics

Symbol

Parameter

Conditions

Min

Typ

Max⁽¹⁾Unit

t_prog

16-bit programming time T_A= -40 to +85 °C

-

53.5

-

µs

ms

mA

V

t_ERASEPage erase time⁽²⁾

T_A= -40 to +85 °C

Write mode

Erase mode

-

30

-

t_ME

Mass erase time

-

10

12

3.6

I_DD

Supply current

-

V_progProgramming voltage

2.4

-

1. Guaranteed by design, not tested in production.

2. Page size is 1KB for STM32F030x4/6/8 devices and 2KB for STM32F030xC devices

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Table 40. Flash memory endurance and data retention

Parameter

Conditions

T_A= -40 to +85 °C

1 kcycle⁽²⁾at T_A= 85 °C

Min⁽¹⁾

Unit

N_END

t_RET

Endurance

kcycle

Years

1

Data retention

20

1. Data based on characterization results, not tested in production.

2. Cycling performed over the whole temperature range.

6.3.11

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

the device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

•

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

•

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 41. They are based on the EMS levels and classes

defined in application note AN1709.

Table 41. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD= 3.3V, LQFP48, T_A= +25 °C,

f_HCLK= 48 MHz,

conforming to IEC 61000-4-2

3B⁽¹⁾

2B⁽²⁾

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V_FESD

Fast transient voltage burst limits to be

V_DD= 3.3V, LQFP48, T_A= +25°C,

V_EFTBapplied through 100 pF on V_DDand V_SSf_HCLK= 48 MHz,

pins to induce a functional disturbance conforming to IEC 61000-4-4

4B

1. Applies to STM32F030xC.

2. Applies to STM32F030x4/x6/x8.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

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The software flowchart must include the management of runaway conditions such as:

•

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 42. EMI characteristics

Max vs. [f_HSE/f_HCLK

8/48 MHz

]

Monitored

frequency band

Symbol Parameter

Conditions

Unit

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

EMI Level

-3

23

17

4

V_DD= 3.6 V, T_A= 25 °C,

LQFP100 package

compliant with

dBµV

-

S_EMI

Peak level

IEC 61967-2

6.3.12

Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

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STM32F030x4/x6/x8/xC

Maximum

Table 43. ESD absolute maximum ratings

Conditions

Symbol

V_ESD(HBM)

V_ESD(CDM)

Ratings

Packages Class

Unit

value⁽¹⁾

Electrostatic discharge voltage T_A= +25 °C, conforming

(human body model)

All

2

2000

V

to JESD22-A114

C4⁽²⁾

C3⁽³⁾

500⁽²⁾

250⁽³⁾

Electrostatic discharge voltage T_A= +25 °C, conforming

(charge device model) to ANSI/ESD STM5.3.1

All

V

1. Data based on characterization results, not tested in production.

2. Applicable to STM32F030xC

3. Applicable to STM32F030x4, STM32F030x6, and STM32F030x8

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

•

A supply overvoltage is applied to each power supply pin.

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 44. Electrical sensitivities

Symbol

Parameter

Conditions

Class

II level A

LU

Static latch-up class

T_A= +105 °C conforming to JESD78A

6.3.13

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V or

SS

above V

(for standard, 3.3 V-capable I/O pins) should be avoided during normal

DDIOx

product operation. However, in order to give an indication of the robustness of the

microcontroller in cases when abnormal injection accidentally happens, susceptibility tests

are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher

than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out

of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or

oscillator frequency deviation).

The characterization results are given in Table 45.

Negative induced leakage current is caused by negative injection and positive induced

leakage current is caused by positive injection.

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Table 45. I/O current injection susceptibility

Functional

susceptibility

Symbol

Description

Unit

Negative Positive

injection injection

Injected current on BOOT0 and PF1 pins

-0

-5

NA

Injected current on PA9, PB3, PB13, PF11 pins with induced

leakage current on adjacent pins less than 50 µA

Injected current on PA11 and PA12 pins with induced

leakage current on adjacent pins less than -1 mA

-5

NA

I_INJ

mA

Injected current on all other FT and FTf pins

Injected current on PB0 and PB1 pins

Injected current on PC0 pin

-5

-0

-5

NA

+5

Injected current on all other TTa, TC and RST pins

+5

6.3.14

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 46 are derived from tests

performed under the conditions summarized in Table 21: General operating conditions. All

I/Os are designed as CMOS- and TTL-compliant (except BOOT0).

Table 46. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TC and TTa I/O

FT and FTf I/O

BOOT0

-

0.3 V_DDIOx+0.07⁽¹⁾

0.475 V_DDIOx–0.2⁽¹⁾

0.3 V_DDIOx–0.3⁽¹⁾

Low level input

voltage

V_IL

V

All I/Os except

BOOT0 pin

-

0.3 V_DDIOx

TC and TTa I/O

FT and FTf I/O

BOOT0

0.445 V_DDIOx+0.398⁽¹⁾

0.5 V_DDIOx+0.2⁽¹⁾

-

High level input

voltage

0.2 V_DDIOx+0.95⁽¹⁾

V_IH

V

All I/Os except

BOOT0 pin

0.7 V_DDIOx

-

TC and TTa I/O

FT and FTf I/O

BOOT0

-

200⁽¹⁾

100⁽¹⁾

300⁽¹⁾

-

Schmitt trigger

hysteresis

V_hys

mV

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Table 46. I/O static characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TC, FT and FTf I/O

TTa in digital mode

V_SS≤ V_IN≤ V_DDIOx

-

0.1

TTa in digital mode

V_DDIOx≤ V_IN≤ V_DDA

-

1

Input leakage

current⁽²⁾

I_lkg

µA

TTa in analog mode

V_SS≤ V_IN≤ V_DDA

0.2

10

FT and FTf I/O ⁽³⁾

V_DDIOx≤ V_IN≤ 5 V

Weak pull-up

R_PU

equivalent resistor V_IN= V_SS

25

40

55

kΩ

(4)

Weak pull-down

R_PD

C_IO

equivalent

V_IN= V_DDIOx

25

-

40

5

55

-

kΩ

resistor⁽⁴⁾

I/O pin capacitance

-

pF

1. Data based on design simulation only. Not tested in production.

2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 45:

I/O current injection susceptibility.

3. To sustain a voltage higher than V_DDIOx+ 0.3 V, the internal pull-up/pull-down resistors must be disabled.

4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 19 for standard I/Os, and in Figure 20 for

5 V tolerant I/Os. The following curves are design simulation results, not tested in

production.

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Figure 19. TC and TTa I/O input characteristics

3

2.5

2

TESTED RANGE

TTL standard requirement

V_IN(V)

1.5

UNDEFINED INPUT RANGE

1

0.5

0

TTL standard requirement

TESTED RANGE

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_DDIOx(V)

MSv32130V4

Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics

3

2.5

2

TESTED RANGE

TTL standard requirement

V_IN(V)

1.5

UNDEFINED INPUT RANGE

1

TTL standard requirement

0.5

0

TESTED RANGE

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_DDIOx(V)

MSv32131V4

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or

source up to +/- 20 mA (with a relaxed V /V ).

OL OH

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

•

The sum of the currents sourced by all the I/Os on V

plus the maximum

DDIOx,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

ΣI

(see Table 18: Voltage characteristics).

VDD

•

The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of

SS

the MCU sunk on V , cannot exceed the absolute maximum rating ΣI

(see

SS

VSS

Table 18: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or

TC unless otherwise specified).

(1)

Table 47. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max Unit

V_OL

V_OH

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

-

0.4

V

V_D^|I_DIO^{| =}_x≥⁸2^m.7^AV

IO

V_DDIOx–0.4

-

(2)

V_OL

-

1.3

V

-

|I_IO| = 20 mA

V_DDIOx≥ 2.7 V

(2)

V_OH

V_DDIOx–1.3

-

(2)

V_OL

0.4

V

-

|I_IO| = 6 mA

(2)

V_OH

V_DDIOx–0.4

|I_IO| = 20 mA

V_DDIOx≥ 2.7 V

-

0.4

V

Output low level voltage for an FTf I/O pin in

Fm+ mode

(2)

V_OLFm+

|I_IO| = 10 mA

1. The I_IOcurrent sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:

Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

respect the absolute maximum ratings ΣI

.

IO

2. Data based on characterization results. Not tested in production.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 21 and

Table 48, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under

the ambient temperature and supply voltage conditions summarized in Table 21: General

operating conditions.

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(1)(2)

Table 48. I/O AC characteristics

OSPEEDRy

Symbol

Parameter

Conditions

Min

Max

Unit

MHz

ns

[1:0] value⁽¹⁾

f_max(IO)outMaximum frequency⁽³⁾

t_f(IO)outOutput fall time

-

2

125

10

25

50

30

20

5

x0

01

C_L= 50 pF, V_DDIOx≥ 2.4 V

t_r(IO)outOutput rise time

f_max(IO)outMaximum frequency⁽³⁾

t_f(IO)outOutput fall time

MHz

ns

C_L= 50 pF, V_DDIOx≥ 2.4 V

t_r(IO)outOutput rise time

C_L= 30 pF, V_DDIOx≥ 2.7 V

C_L= 50 pF, V_DDIOx≥ 2.7 V

C_L= 50 pF, 2.4 V ≤V_DDIOx< 2.7 V

C_L= 30 pF, V_DDIOx≥ 2.7 V

C_L= 50 pF, V_DDIOx≥ 2.7 V

C_L= 50 pF, 2.4 V ≤V_DDIOx< 2.7 V

C_L= 30 pF, V_DDIOx≥ 2.7 V

C_L= 50 pF, V_DDIOx≥ 2.7 V

C_L= 50 pF, 2.4 V ≤V_DDIOx< 2.7 V

f_max(IO)outMaximum frequency⁽³⁾

MHz

11

t_f(IO)outOutput fall time

8

12

5

ns

t_r(IO)outOutput rise time

8

12

2

f_max(IO)outMaximum frequency⁽³⁾

t_f(IO)outOutput fall time

MHz

ns

Fm+

configuration

C_L= 50 pF, V_DDIOx≥ 2.4 V

12

34

(4)

t_r(IO)outOutput rise time

Pulse width of external

t_EXTIpwsignals detected by the

EXTI controller

-

10

-

ns

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0360 reference manual for a

description of GPIO Port configuration register.

2. Guaranteed by design, not tested in production.

3. The maximum frequency is defined in Figure 21.

4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0360

for a detailed description of Fm+ I/O configuration.

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Figure 21. I/O AC characteristics definition

10%

90%

50%

10%

90%

t

r(IO)out

f(IO)out

T

2

3

Maximum frequency is achieved if (t + t ) ≤

T and if the duty cycle is (45-55%)

r

f

when loaded by C (see the table I/O AC characteristics definition)

L

MS32132V3

6.3.15

NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-

up resistor, R

.

PU

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions.

Table 49. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL(NRST)NRST input low level voltage

V_IH(NRST)NRST input high level voltage

-

0.3 V_DD+0.07⁽¹⁾

-

V

0.445 V_DD+0.398⁽¹⁾

NRST Schmitt trigger voltage

V_hys(NRST)

hysteresis

-

200

40

-

mV

Weak pull-up equivalent

R_PU

V_IN= V_SS

25

55

kΩ

resistor⁽²⁾

V_F(NRST)NRST input filtered pulse

-

100⁽¹⁾

ns

2.7 < V_DD< 3.6

2.4 < V_DD< 3.6

300⁽³⁾

500⁽³⁾

-

V_NF(NRST)NRST input not filtered pulse

ns

1. Data based on design simulation only. Not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimal (~10% order).

3. Data based on design simulation only. Not tested in production.

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Figure 22. Recommended NRST pin protection

External

reset circuit⁽¹⁾

V_DD

R_PU

NRST⁽²⁾

Internal reset

Filter

0.1 μF⁽³⁾

MS19878V4

1. The external capacitor protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 49: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

6.3.16

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 50 are preliminary values derived

from tests performed under ambient temperature, f

frequency and V

supply voltage

PCLK

DDA

conditions summarized in Table 21: General operating conditions.

Note:

It is recommended to perform a calibration after each power-up.

Table 50. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

3.6

Unit

Analog supply voltage for

ADC ON

V_DDA

-

2.4

-

V

Current consumption of

the ADC⁽¹⁾

I_{DDA (ADC)}

f_ADC

V_DD= V_DDA= 3.3 V

-

0.9

-

mA

ADC clock frequency

Sampling rate

-

0.6

-

14

1

MHz

kHz

(2)

f_S

-

0.05

f_ADC= 14 MHz

-

823

17

External trigger

frequency

(2)

f_TRIG

-

1/f_ADC

V

V_AIN

Conversion voltage range

External input impedance

0

V_DDA

See Equation 1 and

Table 51 for details

(2)

R_AIN

-

50

1

kΩ

pF

Sampling switch

resistance

(2)

-

R_ADC

Internal sample and hold

capacitor

(2)

8

C_ADC

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Table 50. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

5.9

83

Max

Unit

µs

f_ADC= 14 MHz

-

(2)(3)

Calibration time

t_CAL

1/f_ADC

1.5 ADC

cycles + 3

f_PCLKcycles

1.5 ADC

cycles + 2

_PCLKcycles

ADC clock = HSI14

-

f

ADC_DR register write

latency

(2)(4)

f_PCLK

cycle

W_LATENCY

ADC clock = PCLK/2

ADC clock = PCLK/4

-

4.5

8.5

-

f_PCLK

cycle

f_ADC= f_PCLK/2 =

14 MHz

0.196

5.5

µs

1/f_PCLK

µs

f

_ADC= f_PCLK/2

Trigger conversion

latency

(2)

f_ADC= f_PCLK/4 =

12 MHz

t_latr

0.219

f_ADC= f_PCLK/4

10.5

-

1/f_PCLK

µs

f_ADC= f_HSI14= 14 MHz

0.188

-

0.259

-

ADC jitter on trigger

conversion

Jitter_ADC

f_ADC= f_HSI14

1

1/f_HSI14

f_ADC= 14 MHz

0.107

1.5

-

17.1

µs

(2)

Sampling time

t_S

-

239.5

1/f_ADC

(2)

t_STAB

Stabilization time

14

f_ADC= 14 MHz,

12-bit resolution

1

-

18

µs

Total conversion time

(including sampling time)

(2)

t_CONV

14 to 252 (t_Sfor sampling +12.5 for

successive approximation)

12-bit resolution

1/f_ADC

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I_DDAand 60 µA

on I_DDshould be taken into account.

2. Guaranteed by design, not tested in production.

3. Specified value includes only ADC timing. It does not include the latency of the register access.

4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.

Equation 1: R

max formula

AIN

T_S

R_AIN< --------------------------------------------------------------- – R_ADC

f_ADC× C_ADC× ln(2^{N + 2}

)

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

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Electrical characteristics

Table 51. R

max for f

t_S(µs)

= 14 MHz

ADC

AIN

R_AINmax (kΩ)⁽¹⁾

1.5

7.5

0.11

0.54

0.96

2.04

2.96

3.96

5.11

17.1

0.4

5.9

13.5

28.5

41.5

55.5

71.5

239.5

11.4

25.2

37.2

50

NA

1. Guaranteed by design, not tested in production.

(1)(2)(3)

Table 52. ADC accuracy

Symbol

Parameter

Test conditions

Typ

Max⁽⁴⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

±3.3

±1.9

±2.8

±0.7

±1.2

±4

f_PCLK= 48 MHz,

±2.8

±3

f_ADC= 14 MHz, R_AIN< 10 kΩ

V_DDA= 2.7 V to 3.6 V

T_A= −40 to 85 °C

Gain error

LSB

Differential linearity error

Integral linearity error

±1.3

±1.7

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input

pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog

input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject

negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 6.3.14 does not affect the ADC

accuracy.

3. Better performance may be achieved in restricted V_DDA, frequency and temperature ranges.

4. Data based on characterization results, not tested in production.

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Figure 23. ADC accuracy characteristics

V

SSA

EG

(1) Example of an actual transfer curve

4095

4094

4093

(2) The ideal transfer curve

(3) End point correlation line

E

T

= total unajusted error: maximum deviation

(2)

between the actual and ideal transfer curves.

ET

E

O

= offset error: maximum deviation

(3)

7

between the first actual transition and

the first ideal one.

(1)

6

5

4

3

2

1

E

G

= gain error: deviation between the last

ideal transition and the last actual one.

= differential linearity error: maximum

EO

EL

D

deviation between actual steps and the ideal ones.

= integral linearity error: maximum deviation

between any actual transition and the end point

correlation line.

ED

L

1 LSB IDEAL

0

4096

VDDA

4094 4095

7

4093

2

3

4

5

6

1

MS19880V2

Figure 24. Typical connection diagram using the ADC

V

DDA

Sample and hold ADC

converter

V

T

(1)

R

ADC

AIN

AINx

12-bit

converter

I

1 μA

L

C

V

parasitic

T

V

AIN

C

ADC

MS33900V1

1. Refer to Table 50: ADC characteristics for the values of R_AIN, R_ADCand C_ADC

.

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high C_parasiticvalue will downgrade conversion accuracy. To remedy

this, f_ADCshould be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13: Power supply

scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as

close as possible to the chip.

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Electrical characteristics

6.3.17

Temperature sensor characteristics

Table 53. TS characteristics

Parameter Min

V_SENSElinearity with temperature

Avg_Slope⁽¹⁾Average slope

Symbol

Typ

Max

Unit

(1)

T_L

-

4.0

1.34

-

1

4.3

1.43

-

2

4.6

1.52

10

°C

mV/°C

V

V₃₀

Voltage at 30 °C ( 5 °C)⁽²⁾

(1)

t_START

ADC_IN16 buffer startup time

µs

ADC sampling time when reading the

temperature

t_{S_temp}

4

-

µs

1. Guaranteed by design, not tested in production.

2. Measured at V_DDA= 3.3 V 10 mV. The V₃₀ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:

Temperature sensor calibration values.

6.3.18

Timer characteristics

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 54. TIMx characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_TIMxCLK

ns

-

1

-

t_res(TIM)

Timer resolution

f_TIMxCLK= 48 MHz

-

20.8

Timer external clock

frequency on CH1 to

CH4

f_TIMxCLK/2

MHz

f_EXT

f

_TIMxCLK= 48 MHz

-

24

-

MHz

2¹⁶

t_TIMxCLK

-

16-bit timer maximum

period

f_TIMxCLK= 48 MHz

-

1365

µs

t_{MAX_COUNT}

2³²

t_TIMxCLK

32-bit timer maximum

period

f_TIMxCLK= 48 MHz

89.48

s

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(1)

Table 55. IWDG min/max timeout period at 40 kHz (LSI)

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Prescaler divider PR[2:0] bits

Unit

/4

/8

0

0.1

0.2

0.4

0.8

1.6

3.2

6.4

409.6

819.2

1

/16

/32

/64

/128

/256

2

1638.4

3276.8

6553.6

13107.2

26214.4

3

4

ms

5

6 or 7

1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30

to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing

of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Table 56. WWDG min/max timeout value at 48 MHz (PCLK)

Prescaler

WDGTB

Min timeout value

Max timeout value

Unit

1

2

4

8

0

1

2

3

0.0853

0.1706

0.3413

0.6826

5.4613

10.9226

21.8453

43.6906

ms

6.3.19

Communication interfaces

I²C interface characteristics

2

The I2C interface meets the timings requirements of the I C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): with a bit rate up to 100 kbit/s

Fast-mode (Fm): with a bit rate up to 400 kbit/s

Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly

configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and V

is disabled, but is still present. Only FTf I/O pins

DDIOx

support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O

port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog

filter characteristics:

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Electrical characteristics

(1)

Table 57. I2C analog filter characteristics

Symbol

Parameter

Min

Max

Unit

Maximum pulse width of spikes that

are suppressed by the analog filter

t_AF

50⁽²⁾

260⁽³⁾

ns

1. Guaranteed by design, not tested in production.

2. Spikes with widths below t_AF(min)are filtered.

3. Spikes with widths above t_AF(max)are not filtered

SPI characteristics

Unless otherwise specified, the parameters given in Table 58 for SPI are derived from tests

performed under the ambient temperature, f frequency and supply voltage conditions

PCLKx

summarized in Table 21: General operating conditions.

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics.

(1)

Table 58. SPI characteristics

Symbol

Parameter

Conditions

Master mode

Min

Max

Unit

-

18

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

Slave mode

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 15 pF

-

6

ns

%

t_su(NSS)

t_h(NSS)

t_w(SCKH)

NSS setup time

NSS hold time

Slave mode

4Tpclk

-

2Tpclk + 10

Master mode, f_PCLK= 36 MHz,

presc = 4

SCK high and low time

Data input setup time

Tpclk/2 -2

Tpclk/2 + 1

t_w(SCKL)

Master mode

Slave mode

Master mode

Slave mode

4

5

-

t_su(MI)

t_su(SI)

-

t_h(MI)

t_h(SI)

4

-

Data input hold time

5

-

(2)

t_a(SO)

Data output access time Slave mode, f_PCLK= 20 MHz

Data output disable time Slave mode

0

3Tpclk

(3)

t_dis(SO)

0

18

t_v(SO)

t_v(MO)

t_h(SO)

t_h(MO)

Data output valid time

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

-

22.5

-

6

-

11.5

2

Data output hold time

-

SPI slave input clock

duty cycle

DuCy(SCK)

Slave mode

25

75

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

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STM32F030x4/x6/x8/xC

Figure 25. SPI timing diagram - slave mode and CPHA = 0

Figure 26. SPI timing diagram - slave mode and CPHA = 1

NSS input

t^SU(NSS)

th(NSS)

tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t^w(SCKH)

tw(SCKL)

tr(SCK)

tf(SCK)

th(SO)

tdis(SO)

tv(SO)

ta(SO)

MISO

MSB OUT

MSB IN

BIT6 OUT

LSB OUT

OUTPUT

th(SI)

t^su(SI)

MOSI

INPUT

LSB IN

BIT 1 IN

ai14135b

1. Measurement points are done at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

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Electrical characteristics

Figure 27. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

t

su(MI)

f(SCK)

MISO

INPUT

BIT6 IN

LSB IN

MSB IN

t

h(MI)

MOSI

OUTPUT

BIT1 OUT

LSB OUT

MSB OUT

t

h(MO)

v(MO)

ai14136c

1. Measurement points are done at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

DS9773 Rev 4

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75

Package information

STM32F030x4/x6/x8/xC

7

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

7.1

LQFP64 package information

LQFP64 is 64-pin, 10 x 10 mm low-profile quad flat package.

Figure 28. LQFP64 outline

SEATING PLANE

C

0.25 mm

GAUGE PLANE

ccc

C

D

D1

D3

L

L1

33

48

32

49

64

b

17

16

1

PIN 1

e

IDENTIFICATION

5W_ME_V3

1. Drawing is not to scale.

Table 59. LQFP64 mechanical data

millimeters

inches⁽¹⁾

Typ

Symbol

Min

Typ

Max

Min

Max

A

-

1.600

0.150

1.450

-

0.0630

0.0059

0.0571

A1

A2

0.050

1.350

0.0020

0.0531

-

1.400

0.0551

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Symbol

Package information

Table 59. LQFP64 mechanical data (continued)

millimeters

Typ

inches⁽¹⁾

Min

Max

Min

Typ

Max

b

c

0.170

0.220

-

0.270

0.0067

0.0087

-

0.0106

0.090

0.200

0.0035

0.0079

D

-

12.000

10.000

7.500

12.000

10.000

7.500

0.500

3.5°

-

0.4724

0.3937

0.2953

0.4724

0.3937

0.2953

0.0197

3.5°

-

D1

D3

E

-

E1

E3

e

-

7°

-

7°

K

0°

L

0.450

0.600

1.000

-

0.750

-

0.0177

0.0236

0.0394

-

0.0295

-

L1

ccc

-

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 29. LQFP64 recommended footprint

48

33

0.3

0.5

49

32

12.7

10.3

7.8

17

64

1.2

16

1

12.7

ai14909c

1. Dimensions are expressed in millimeters.

DS9773 Rev 4

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89

Package information

STM32F030x4/x6/x8/xC

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 30. LQFP64 marking example (package top view)

Revision code

R

Product identification ⁽¹⁾

STM32F030

RCT6

Date code

Y

WW

Pin 1 identifier

MSv36475V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

78/93

DS9773 Rev 4

STM32F030x4/x6/x8/xC

Package information

7.2

LQFP48 package information

LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package

Figure 31. LQFP48 outline

SEATING

PLANE

C

0.25 mm

GAUGE PLANE

ccc

C

D

L

D1

D3

L1

36

25

37

24

b

48

13

PIN 1

IDENTIFICATION

1

12

e

5B_ME_V2

1. Drawing is not to scale.

Table 60. LQFP48 mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

-

1.600

0.150

1.450

0.270

0.200

9.200

7.200

-

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

-

0.050

1.350

0.170

0.090

8.800

6.800

-

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

-

1.400

0.220

-

0.0551

0.0087

-

c

D

9.000

7.000

5.500

9.000

0.3543

0.2756

0.2165

0.3543

D1

D3

E

8.800

9.200

0.3465

0.3622

DS9773 Rev 4

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Package information

STM32F030x4/x6/x8/xC

Table 60. LQFP48 mechanical data (continued)

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

E1

E3

e

6.800

7.000

5.500

0.500

0.600

1.000

3.5°

7.200

0.2677

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.2835

-

0.750

-

0.0295

-

L

0.450

0.0177

L1

k

-

0°

-

0°

-

7°

ccc

-

0.080

-

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 32. LQFP48 recommended footprint

0.50

1.20

0.30

36

25

37

24

0.20

7.30

9.70 5.80

7.30

48

13

12

1

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

80/93

DS9773 Rev 4

STM32F030x4/x6/x8/xC

Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 33. LQFP48 marking example (package top view)

Product identification⁽¹⁾

STM32F

030CCT6

Date code

Y WW

Pin 1 identifier

Revision code

R

MSv36476V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

DS9773 Rev 4

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89

Package information

STM32F030x4/x6/x8/xC

7.3

LQFP32 package information

LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package

Figure 34. LQFP32 outline

SEATING

PLANE

C

0.25 mm

GAUGE PLANE

ccc

C

K

D

D1

D3

L

L1

24

17

16

25

32

9

PIN 1

IDENTIFICATION

1

8

e

5V_ME_V2

1. Drawing is not to scale.

Table 61. LQFP32 mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

-

1.600

0.150

1.450

-

0.0630

0.0059

0.0571

A1

A2

0.050

1.350

0.0020

0.0531

1.400

0.0551

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STM32F030x4/x6/x8/xC

Symbol

Package information

Table 61. LQFP32 mechanical data (continued)

millimeters

Typ

inches⁽¹⁾

Min

Max

Min

Typ

Max

b

c

0.300

0.370

-

0.450

0.200

9.200

7.200

-

0.0118

0.0146

-

0.0177

0.0079

0.3622

0.2835

-

0.090

0.0035

D

8.800

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

0.3465

0.3543

0.2756

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5°

D1

D3

E

6.800

0.2677

-

8.800

9.200

7.200

-

0.3465

0.3622

0.2835

-

E1

E3

e

6.800

0.2677

-

L

0.450

0.750

-

0.0177

0.0295

-

L1

k

-

0°

-

0°

-

7°

ccc

-

0.100

-

0.0039

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 35. LQFP32 recommended footprint

0.80

1.20

24

17

25

16

0.50

0.30

7.30

6.10

9.70

7.30

32

9

8

1

1.20

6.10

9.70

5V_FP_V2

1. Dimensions are expressed in millimeters.

DS9773 Rev 4

83/93

89

Package information

STM32F030x4/x6/x8/xC

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 36. LQFP32 marking example (package top view)

Product identification ⁽¹⁾

STM32F

030K6T6

Date code

Y WW

Pin 1 identification

Revision code

R

MSv36477V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

84/93

DS9773 Rev 4

STM32F030x4/x6/x8/xC

Package information

7.4

TSSOP20 package information

TSSOP20 is a 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch package.

Figure 37. TSSOP20 outline

D

20

11

10

c

E1

E

SEATING

PLANE

C

0.25 mm

GAUGE PLANE

1

PIN 1

IDENTIFICATION

k

aaa

C

A1

L

A

A2

L1

b

e

YA_ME_V3

1. Drawing is not to scale.

Table 62. TSSOP20 mechanical data

millimeters

inches⁽¹⁾

Typ.

Symbol

Min.

Typ.

Max.

Min.

Max.

A

A1

A2

b

-

1.200

0.150

1.050

0.300

0.200

6.600

4.500

-

0.0472

0.0059

0.0413

0.0118

0.0079

0.2598

0.1772

-

0.050

0.800

0.190

0.090

6.400

6.200

4.300

-

0.0020

0.0315

0.0075

0.0035

0.2520

0.2441

0.1693

-

1.000

-

0.0394

-

c

-

D

6.500

6.400

4.400

0.650

0.600

1.000

0.2559

0.2520

0.1732

0.0256

0.0236

0.0394

E

E1

e

L

0.450

-

0.750

-

0.0177

-

0.0295

-

L1

DS9773 Rev 4

85/93

89

Package information

STM32F030x4/x6/x8/xC

Table 62. TSSOP20 mechanical data (continued)

millimeters

Typ.

inches⁽¹⁾

Symbol

Min.

Max.

Min.

Typ.

Max.

k

0°

-

8°

0°

-

8°

aaa

0.100

0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.

Figure 38. TSSOP20 footprint

0.25

6.25

20

11

1.35

0.25

7.10 4.40

1.35

1

10

0.40

0.65

YA_FP_V1

1. Dimensions are expressed in millimeters.

86/93

DS9773 Rev 4

STM32F030x4/x6/x8/xC

Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 39. TSSOP20 marking example (package top view)

Device identification ⁽¹⁾

32F030F4P6

Date code

Pin 1 identification

Revision code

Y

WW

R

MSv36478V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

DS9773 Rev 4

87/93

89

Package information

STM32F030x4/x6/x8/xC

7.5

Thermal characteristics

The maximum chip junction temperature (T max) must never exceed the values given in

J

Table 21: General operating conditions.

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max x Θ )

J

A

D

JA

Where:

•

T max is the maximum ambient temperature in °C,

A

Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (V × I ) + Σ ((V

V

) × I ),

I/O

OL

DD - OH OH

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 63. Package thermal characteristics

Parameter

Symbol

Value

Unit

Thermal resistance junction-ambient

LQFP64 - 10 mm x 10 mm

44

Thermal resistance junction-ambient

LQFP48 - 7 mm x 7 mm

55

56

76

Θ

°C/W

J

Thermal resistance junction-ambient

LQFP32 - 7 mm x 7 mm

Thermal resistance junction-ambient

TSSOP20 - 6.5 mm x 6.4 mm

7.5.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

88/93

DS9773 Rev 4

STM32F030x4/x6/x8/xC

Ordering information

8

Ordering information

+

Example:

STM32

F

030

C

6

T

6

x

Device family

STM32 = Arm-based 32-bit microcontroller

Product type

F = General-purpose

Sub-family

030 = STM32F030xx

Pin count

F = 20 pins

K = 32 pins

C = 48 pins

R = 64 pins

Code size

4 = 16 Kbyte of Flash memory

6 = 32 Kbyte of Flash memory

8 = 64 Kbyte of Flash memory

C = 256 Kbyte of Flash memory

Package

P = TSSOP

T = LQFP

Temperature range

6 = –40 to 85 °C

Option

xxx = programmed parts

TR = tape and reel

For a list of available options (memory, package, and so on) or for further information on any

aspect of this device, please contact your nearest ST sales office.

DS9773 Rev 4

89/93

89

Revision history

STM32F030x4/x6/x8/xC

9

Revision history

Table 64. Document revision history

Date

Revision

Changes

04-Jul-2013

1

Initial release.

Extended the applicability to STM32F030xC.

Updated:

– Features and Table Device summary,

– Section: Description,

– Table: STM32F030x4/6/8/C family device features

and peripheral counts,

– Figure: Block diagram,

– Section: Memories,

– Section: General-purpose inputs/outputs (GPIOs),

– Section: Universal synchronous/asynchronous

receiver transmitters (USART),

– Table: STM32F030x4/6/8/C pin definitions,

– Table: Alternate functions selected through

GPIOA_AFR registers for port A,

– Table: Alternate functions selected through

GPIOB_AFR registers for port B

15-Jan-2015

2

– Table: Alternate functions selected through

GPIOC_AFR registers for port C

– Table: Alternate functions selected through

GPIOD_AFR registers for port D,

– Table: Alternate functions selected through

GPIOF_AFR registers for port F,

– Section: EMC characteristics,

– Section: Part numbering.

Added device marking examples:

– Figure: LQFP64 marking example (package top view),

– Figure: LQFP48 marking example (package top view),

– Figure: LQFP32 marking example (package top view),

– Figure: TSSOP20 marking example (package top

view).

Updated:

– Table 2: STM32F030x4/x6/x8/xC family device

features and peripheral counts

– Figure 1: Block diagram and figure footnotes

23-Jan-2017

3

– Figure 2: Clock tree of STM32F030x4/x6/x8 and

figure footnotes

– Section 3.11: Timers and watchdogs - number of

timers, counts of complementary outputs in the table

and the footnotes

90/93

DS9773 Rev 4

STM32F030x4/x6/x8/xC

Date

Revision history

Table 64. Document revision history (continued)

Revision

Changes

– Section 3.11.2: General-purpose timers (TIM3,

TIM14..17) - number of timers

– Table 5: Timer feature comparison - footnotes added

– Table 7: STM32F030x4/x6/x8/xC I²C implementation -

FM+ and footnote

– Figure 4 through Figure 7 - darker highlight on pins

– Table 11: STM32F030x4/6/8/C pin definitions -

corrections

– Table 12: Alternate functions selected through

GPIOA_AFR registers for port A - note order

– Table 14 through Table 16 - corrected footnotes

– Figure 10: STM32F030x4/x6/x8/xC memory map

footnote

– Figure 13: Power supply scheme

– Table 24: Embedded internal reference voltage:

added t_START, changed V_REFINTand t_{S_vrefint}values

and notes

– Table 25: Typical and maximum current consumption

from V_DDsupply at V_DD= 3.6 V footnotes

– Table 26: Typical and maximum current consumption

from the V_DDAsupply values for STM32F030xC and

footnotes

23-Jan-2017

3

– Table 34: LSE oscillator characteristics (f_LSE= 32.768

kHz) LSEDRV[1:0] values removed (see ref. manual)

– Table 50: ADC characteristics - t_STABdefined relative

to clock frequency; notes 3. and 4. added

– Section 3.14: Universal synchronous/asynchronous

receiver/transmitter (USART) - introduction and

Table 8: STM32F0x0 USART implementation

– Figure 10: STM32F030x4/x6/x8/xC memory map

footnote

– Table 43: ESD absolute maximum ratings - C4 or C3

class, depending on device variant; CDM values

updated to match the referenced standard. (CDM

standard was updated in the previous release, without

duly modifying the related values.)

– Table 53: TS characteristics: removed the min. value

for t_STARTand parameter name change

– Figure 19 and Figure 20 improved

– Section 7: Package information name and structure

change

– Section 8: Ordering information renamed from Part

numbering

DS9773 Rev 4

91/93

92

Revision history

STM32F030x4/x6/x8/xC

Table 64. Document revision history (continued)

Date

Revision

Changes

– Figure 2 split in two figures

– TIM15 complementary outputs count in Table 5

– Periodic wakeup unit feature in Section 3.12: Real-

time clock (RTC)

– Driver Enable for USART 6 in Table 8

15-Jan-2019

4

– Number of supported auto baud rate detection modes

corrected in Table 8

– AF4 and AF5 for PB10 in Table 13

– Notes in Table 14, Table 15, and Table 16

– Extension of Table 16

– V_FESDclass in Table 41

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DS9773 Rev 4

STM32F030x4/x6/x8/xC

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DS9773 Rev 4

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型号：	STM32F030CC
厂家：	ST
描述：	Value-line ArmÂ®-based 32-bit MCU with up to 256 KB Flash, timers, ADC, communication interfaces, 2.4-3.6 V operation 外围集成电路
文件：	总93页 (文件大小：1496K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM32F030CC [STMICROELECTRONICS]

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