STM32F050K4U6AXXXTR [STMICROELECTRONICS]
IC,MICROCONTROLLER,32-BIT,CORTEX-M0 CPU,CMOS,LLCC,32PIN,PLASTIC;
| 型号： | STM32F050K4U6AXXXTR |
| 厂家： | 
ST |
| 描述： | IC,MICROCONTROLLER,32-BIT,CORTEX-M0 CPU,CMOS,LLCC,32PIN,PLASTIC |
| 文件： | 总97页 (文件大小：1097K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F050x4 STM32F050x6
Low- and medium-density advanced ARM™-based 32-bit MCU with
up to 32 Kbytes Flash, timers, ADC and comm. interfaces
Datasheet −production data
Features
■ Core: ARM 32-bit Cortex™-M0 CPU,
frequency up to 48 MHz
■ Memories
LQFP48 7x7
UFQFPN32 5x5
UFQFPN28 4x4
TSSOP20
– 16 to 32 Kbytes of Flash memory
– 4 Kbytes of SRAM with HW parity checking
– 1 x 16-bit timer with 1 IC/OC
■ CRC calculation unit
– Independent and system watchdog timers
– SysTick timer: 24-bit downcounter
■ Reset and supply management
– Voltage range: 2.0 V to 3.6 V
■ Calendar RTC with alarm and periodic wakeup
from Stop/Standby
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop and
Standby
■ Communication interfaces
2
– 1 x I C interface; supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus, and wakeup from STOP
– V
supply for RTC and backup registers
BAT
– 1 x USART supporting master synchronous
SPI and modem control; one with ISO7816
interface, LIN, IrDA capability auto baud
rate detection and wakeup feature
■ Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
– 1 x SPI (18 Mbit/s) with 4 to 16
2
programmable bit frames, with I S interface
multiplexed
■ Up to 39 fast I/Os
■ Serial wire debug (SWD)
■ 96-bit unique ID
– All mappable on external interrupt vectors
– Up to 25 I/Os with 5 V tolerant capability
■ Extended temperature range: -40 to +105°C
■ 5-channel DMA controller
■ 1 × 12-bit, 1.0 µs ADC (up to 10 channels)
Table 1.
Device summary
Part number
– Conversion range: 0 to 3.6V
– Separate analog supply from 2.4 up to
3.6 V
Reference
STM32F050F4, STM32F050G4, STM32F050K4,
STM32F050C4
STM32F050x4
STM32F050x6
■ Up to 9 timers
STM32F050F6, STM32F050G6, STM32F050K6,
STM32F050C6
– 1 x 16-bit 7-channel advanced-control timer
for 6 channels PWM output, with deadtime
generation and emergency stop
– 1 x 32-bit and 1 x 16-bit timer, with up to 4
IC/OC, usable for IR control decoding
– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,
deadtime generation and emergency stop
– 1 x 16-bit timer, with IC/OC and OCN,
deadtime generation, emergency stop and
modulator gate for IR control
November 2012
Doc ID 023683 Rev 1
1/97
This is information on a product in full production.
www.st.com
1
Contents
STM32F050xx
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
3.5
ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1
3.5.2
3.5.3
3.5.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
3.7
3.8
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9.1
3.9.2
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REFINT
3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2 General-purpose timers (TIM2..3, TIM14..17) . . . . . . . . . . . . . . . . . . . . 18
3.11.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Universal synchronous/asynchronous receiver transmitter (USART) . . . 21
3.15 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 22
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Contents
3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4
5
6
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 40
Embedded reset and power control block characteristics . . . . . . . . . . . 40
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.17
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
BAT
6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Doc ID 023683 Rev 1
3/97
Contents
STM32F050xx
7
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.1
7.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.1
7.2.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93
8
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4/97
Doc ID 023683 Rev 1
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F050xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 30
Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 31
STM32F050x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical and maximum current consumption from V supply at VDD = 3.6 . . . . . . . . . . . 43
DD
Typical and maximum current consumption from the V
supply . . . . . . . . . . . . . . . . . . 44
DDA
Typical and maximum V consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 45
DD
Typical and maximum V
consumption in Stop and Standby modes. . . . . . . . . . . . . . . 45
DDA
Typical and maximum current consumption from V
supply. . . . . . . . . . . . . . . . . . . . . . 46
BAT
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 48
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Doc ID 023683 Rev 1
5/97
List of tables
STM32F050xx
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
R
max for f
= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
AIN
ADC
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
WWDG min-max timeout value @48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2
I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 85
UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
Table 63.
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TSSOP20 – 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 91
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 64.
Table 65.
Table 66.
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Doc ID 023683 Rev 1
STM32F050xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UFQFPN28 28-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F050xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 13. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 15. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 16. HSI oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 17. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 18. TC and TTa I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 19. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 68
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port. . . . . . . . . . . . . . . . . . . 68
Figure 22. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 24. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2
Figure 26. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 27. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
(1)
Figure 28. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
(1)
Figure 29. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 30. I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 31. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 32. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 85
Figure 33. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 34. UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline. . . 87
Figure 35. UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 36. UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline. . . 89
Figure 37. UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 38. TSSOP20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 39. TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Doc ID 023683 Rev 1
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Introduction
STM32F050xx
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F050x4 and STM32F050x6 microcontrollers, hereafter referred to as
STM32F050xx.
This datasheet should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM Cortex™-M0 core, please refer to the Cortex™-M0 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html.
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STM32F050xx
Description
2
Description
The STM32F050xx family incorporates the high-performance ARM Cortex™-M0 32-bit
RISC core operating at a 48 MHz maximum frequency, high-speed embedded memories
(Flash memory up to 32 Kbytes and SRAM up to 4 Kbytes), and an extensive range of
enhanced peripherals and I/Os. All devices offer standard communication interfaces (one
2
I C, one SPI, one I2S, and one USART), one 12-bit ADC, up to five general-purpose 16-bit
timers, a 32-bit timer and an advanced-control PWM timer.
The STM32F050xx family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes
allows the design of low-power applications.
The STM32F050xx family includes devices in five different packages ranging from 20 pins to
48 pins. Depending on the device chosen, different sets of peripherals are included. An
overview of the complete range of peripherals proposed in this family is provided.
These features make the STM32F050xx microcontroller family suitable for a wide range of
applications such as control application and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Doc ID 023683 Rev 1
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Description
Table 2.
STM32F050xx
STM32F050Cx
STM32F050xx family device features and peripheral counts
STM32F050Fx STM32F050Gx STM32F050Kx
16 32 16 32 16 32
Peripheral
Flash (Kbytes)
SRAM (Kbytes)
16
32
4
4
4
4
Advanced
control
1 (16-bit)
Timers
4 (16-bit)
1 (32-bit)
General
purpose
SPI (I2S)(1)
I2C
1
1
1
Comm.
interfaces
USART
12-bit synchronized
ADC
(number of channels)
1
1
(9 ext. + 3 int.)
(10 ext. + 3 int.)
GPIOs
15
23
27
39
Max. CPU frequency
Operating voltage
48 MHz
2.0 to 3.6 V
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: -40°C to 105°C / -40 °C to 125 °C
Operating temperature
Packages
TSSOP20
UFQFPN28
UFQFPN32
LQFP48
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
10/97
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STM32F050xx
Description
Figure 1.
Block diagram
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Doc ID 023683 Rev 1
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Functional overview
STM32F050xx
3
Functional overview
3.1
ARM® CortexTM-M0 core with embedded Flash and SRAM
The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F050xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2
Memories
The device has the following features:
●
4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
●
The non-volatile memory is divided into two arrays:
–
–
16 to 32 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
–
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
3.3
Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
●
●
●
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
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Functional overview
3.4
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes
●
V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V pins.
DD
●
V
= 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL
DDA
(minimum voltage to be applied to V
is 2.4 V when the ADC is used). The V
DDA
DDA
voltage level must be always greater or equal to the V voltage level and must be
DD
provided first.
●
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V is not present.
DD
3.5.2
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
, without the need for an external reset circuit.
POR/PDR
●
The POR monitors only the V supply voltage. During the startup phase it is required
DD
that V
should arrive first and be greater than or equal to V
.
DDA
DD
●
The PDR monitors both the V and V
supply voltages, however the V
power
DDA
DD
DDA
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V is higher than or
DDA
equal to V
.
DD
The device features an embedded programmable voltage detector (PVD) that monitors the
power supply and compares it to the V threshold. An interrupt can be generated
V
DD
PVD
when V drops below the V
threshold and/or when V is higher than the V
DD
PVD
DD PVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
Doc ID 023683 Rev 1
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Functional overview
STM32F050xx
3.5.3
Voltage regulator
The regulator has three operating modes: main (MR), low power (LPR) and power down.
●
●
●
MR is used in normal operating mode (Run)
LPR can be used in Stop mode where the power demand is reduced
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
3.5.4
Low-power modes
The STM32F050xx family supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC alarm, I2C1 or
USART1.
The I2C1 and the USART1 can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used, the voltage regulator should not be put in the
low-power mode but kept in normal mode.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pins, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
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Functional overview
3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Figure 2.
Clock tree
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Doc ID 023683 Rev 1
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Functional overview
STM32F050xx
3.7
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.
3.8
Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14) and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F050xx family embeds a nested vectored interrupt controller able to handle up
to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4
priority levels.
●
●
●
●
●
●
●
●
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2
Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 39
GPIOs can be connected to the 16 external interrupt lines.
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Functional overview
3.10
Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
that varies linearly with
SENSE
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3.
Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
temperature of 30 °C,
TS_CAL1
TS_CAL2
0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V
TS ADC raw data acquired at
temperature of 110 °C
0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V
3.10.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC. V
is internally connected to the ADC_IN17 input channel. The precise voltage
REFINT
of V
is individually measured for each part by ST during production test and stored in
REFINT
the system memory area. It is accessible in read-only mode.
Table 4.
Temperature sensor calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 30 °C
VREFINT_CAL
0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V
Doc ID 023683 Rev 1
17/97
Functional overview
STM32F050xx
3.11
Timers and watchdogs
The STM32F050xx family devices include up to six general-purpose timers, one basic timer
and an advanced control timer.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.
Table 5.
Timer feature comparison
Timer
type
Counter
resolution
Counter
type
Prescaler DMA request Capture/compare Complementary
Timer
factor
generation
channels
outputs
Any integer
between 1
and 65536
Advanced
control
Up,down,
up/down
TIM1
16-bit
32-bit
16-bit
16-bit
16-bit
Yes
4
Yes
Any integer
between 1
and 65536
Up,down,
up/down
TIM2
TIM3
Yes
Yes
No
4
4
1
1
No
No
No
Yes
Any integer
between 1
and 65536
Up,down,
up/down
General
purpose
Any integer
between 1
and 65536
TIM14
Up
Up
Any integer
between 1
and 65536
TIM16,
TIM17
Yes
3.11.1
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
●
●
●
●
Input capture
Output compare
PWM generation (edge or center-aligned modes)
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.11.2
General-purpose timers (TIM2..3, TIM14..17)
There are six synchronizable general-purpose timers embedded in the STM32F050xx
devices (see Table 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
18/97
Doc ID 023683 Rev 1
STM32F050xx
Functional overview
TIM2, TIM3
STM32F050xx devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or
one-pulse mode output.
TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
3.11.3
3.11.4
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-
defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
Doc ID 023683 Rev 1
19/97
Functional overview
STM32F050xx
3.11.5
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
●
●
●
●
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source (HCLK or HCLK/8)
3.12
Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power either
on V supply when present or through the V
pin. The backup registers are five 32-bit
DD
BAT
registers used to store 20 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
●
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
●
●
●
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.
Programmable alarm with wake up from Stop and Standby mode capability.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
●
●
●
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
●
●
●
●
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 40 kHz)
The high-speed external clock divided by 32.
20/97
Doc ID 023683 Rev 1
STM32F050xx
Functional overview
3.13
Inter-integrated circuit interface (I2C)
2
The I C interface (I2C1) can operate in multimaster or slave mode. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,
1 with configurable mask). It also includes programmable analog and digital noise filters.
Table 6.
Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
≥ 50 ns
1. Extra filtering capability vs.
standard requirements.
Benefits
Available in Stop mode
2. Stable length
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Variations depending on
temperature, voltage, process
Drawbacks
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interface can be served by the DMA controller.
3.14
Universal synchronous/asynchronous receiver transmitter
(USART)
The device embeds an universal synchronous/asynchronous receiver transmitters
(USART1), which communicates at speeds of up to 6 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. It also supports SmartCard communication (ISO 7816), IrDA SIR
ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain
independent from the CPU clock, allowing it to wake up the MCU from Stop mode.
The USART interface can be served by the DMA controller.
Doc ID 023683 Rev 1
21/97
Functional overview
STM32F050xx
3.15
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
The SPI (SPI1) is able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
2
One standard I S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit
programmable linear prescaler. When operating in master mode it can output a clock for an
external audio component at 256 times the sampling frequency.
3.16
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
22/97
Doc ID 023683 Rev 1
STM32F050xx
Pinouts and pin description
4
Pinouts and pin description
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Doc ID 023683 Rev 1
23/97
Pinouts and pin description
Figure 5. UFQFPN28 28-pin package pinout
STM32F050xx
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24/97
Doc ID 023683 Rev 1
STM32F050xx
Pinouts and pin description
Table 7.
Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
FTf
TTa
TC
B
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
3.3 V tolerant I/O directly connected to ADC
Standard 3.3V I/O
I/O structure
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Doc ID 023683 Rev 1
25/97
Pinouts and pin description
STM32F050xx
Table 8.
Pin definitions
Pin number
Pin functions
Pin name
(function after
reset)
Notes
Additional
functions
Alternate functions
1
2
-
-
-
-
-
-
VBAT
PC13
S
Backup power supply
RTC_TAMP1,
RTC_TS,
(1)(2)
I/O
TC
RTC_OUT,
WKUP2
PC14/OSC32_IN
(PC14)
(1)(2)
(1)(2)
3
4
5
6
7
-
-
-
-
I/O
I/O
I/O
I/O
I/O
TC
TC
OSC32_IN
OSC32_OUT
OSC_IN
PC15/OSC32_OUT
(PC15)
-
-
PF0/OSC_IN
(PF0)
2
3
4
2
3
4
2
3
4
FT
PF1/OSC_OUT
(PF1)
FT
OSC_OUT
Device reset input / internal reset output
(active low)
NRST
RST
8
9
0
5
-
-
VSSA
VDDA
S
S
Analog ground
5
5
Analog power supply
ADC_IN0,
TIM2_CH1_ETR,
RTC_TAMP2,
10
11
6
7
6
7
6
7
PA0
PA1
I/O
I/O
TTa
TTa
USART1_CTS(3)
WKUP1
TIM2_CH2,
EVENTOUT,
USART1_RTS(3)
ADC_IN1
TIM2_CH3,
12
13
8
9
8
9
8
9
PA2
PA3
I/O
I/O
TTa
TTa
ADC_IN2
ADC_IN3
USART1_TX(3)
TIM2_CH4,
USART1_RX(3)
SPI1_NSS,
I2S1_WS,
14 10
15 11
10
11
10
11
PA4
PA5
I/O
I/O
TTa
TTa
ADC_IN4
ADC_IN5
TIM14_CH1,
USART1_CK(3)
SPI1_SCK,
I2S1_CK,
TIM2_CH1_ETR
26/97
Doc ID 023683 Rev 1
STM32F050xx
Pinouts and pin description
Table 8.
Pin definitions (continued)
Pin number
Pin functions
Additional
Pin name
(function after
reset)
Notes
Alternate functions
functions
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
TIM1_BKIN,
TIM16_CH1,
EVENTOUT
16 12
12
13
12
13
PA6
PA7
I/O
I/O
TTa
TTa
ADC_IN6
SPI1_MOSI,
I2S1_SD,
TIM3_CH2,
TIM14_CH1,
TIM1_CH1N,
TIM17_CH1,
EVENTOUT
17 13
ADC_IN7
TIM3_CH3,
TIM1_CH2N,
EVENTOUT
18 14
14
15
-
PB0
PB1
I/O
I/O
TTa
TTa
ADC_IN8
ADC_IN9
TIM3_CH4,
TIM14_CH1,
TIM1_CH3N
19 15
20 16
14
-
-
-
-
PB2
I/O
I/O
FT
TIM2_CH3,
I2C1_SCL(3)
21
-
PB10
FTf
TIM2_CH4,
EVENTOUT,
I2C1_SDA(3)
22
23
-
-
-
PB11
I/O
FTf
0
16
17
15
16
VSS
VDD
S
S
Ground
Digital power supply
TIM1_BKIN,
24 17
25
-
-
-
PB12
I/O
FT
EVENTOUT,
SPI1_NSS(3)
TIM1_CH1N,
SPI1_SCK(3)
26
27
28
-
-
-
-
-
-
-
-
-
PB13
PB14
PB15
I/O
I/O
I/O
FT
FT
FT
TIM1_CH2N,
SPI1_MISO(3)
TIM1_CH3N,
SPI1_MOSI(3)
RTC_REFIN
Doc ID 023683 Rev 1
27/97
Pinouts and pin description
STM32F050xx
Table 8.
Pin definitions (continued)
Pin number
Pin functions
Pin name
(function after
reset)
Notes
Additional
functions
Alternate functions
USART1_CK,
TIM1_CH1,
EVENTOUT,
MCO
29 18
30 19
31 20
32 21
18
19
20
-
-
PA8
PA9
I/O
I/O
I/O
I/O
FT
FTf
FTf
FT
USART1_TX,
TIM1_CH2,
I2C1_SCL(3)
17
18
-
USART1_RX,
TIM1_CH3,
PA10
TIM17_BKIN,
I2C1_SDA(3)
USART1_CTS,
TIM1_CH4,
PA11
PA12
EVENTOUT
USART1_RTS,
TIM1_ETR,
33 22
34 23
-
-
I/O
I/O
FT
FT
EVENTOUT
PA13
IR_OUT,
SWDAT
(4)
(4)
21
19
(SWDAT)
35
36
-
-
-
-
-
-
PF6
PF7
I/O
I/O
FTf
FTf
I2C1_SCL(3)
I2C1_SDA(3)
PA14
SWCLK,
USART1_TX(3)
37 24
22
20
I/O
FT
(SWCLK)
SPI1_NSS,
I2S1_WS,
38 25
23
-
PA15
I/O
FT
TIM2_CH_ETR,
EVENTOUT,
USART1_RX(3)
SPI1_SCK,
I2S1_CK,
39 26
24
25
-
-
PB3
PB4
I/O
I/O
FT
FT
TIM2_CH2,
EVENTOUT
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
EVENTOUT
40 27
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Doc ID 023683 Rev 1
STM32F050xx
Pinouts and pin description
Table 8.
Pin definitions (continued)
Pin number
Pin functions
Additional
Pin name
(function after
reset)
Notes
Alternate functions
functions
SPI1_MOSI,
I2S1_SD,
41 28
26
-
PB5
I/O
FT
I2C1_SMBA,
TIM16_BKIN,
TIM3_CH2
I2C1_SCL,
USART1_TX,
TIM16_CH1N
42 29
43 30
27
28
-
-
PB6
PB7
I/O
I/O
FTf
FTf
I2C1_SDA,
USART1_RX,
TIM17_CH1N
44 31
45 32
1
-
1
-
BOOT0
PB8
I
B
Boot memory selection
I2C1_SCL,
I/O
FTf
TIM16_CH1
I2C1_SDA,
IR_OUT,
46
-
-
-
PB9
I/O
FTf
TIM17_CH1,
EVENTOUT
47
48
0
1
-
-
-
-
VSS
VDD
S
S
Ground
Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as a current sources (e.g. to drive an LED).
2. After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the
Battery backup domain and BKP register description sections in the STM32F05xx reference manual.
3. This alternate feature is available on standard dies only.
4. After reset, these pins are configured as SWDAT and SWCLK alternate functions, and the internal pull-up on SWDAT pin
and internal pull-down on SWCLK pin are activated.
Doc ID 023683 Rev 1
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Table 9.
Alternate functions selected through GPIOA_AFR registers for port A
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
TIM2_CH1_
ETR
PA0
USART1_CKS(1)
PA1
PA2
PA3
EVENTOUT
USART1_TX(1)
USART1_RX(1)
USART1_CTS(1)
TIM2_CH2
TIM2_CH3
TIM2_CH4
SPI1_NSS,
I2S1_WS
PA4
PA5
PA6
PA7
USART1_RTS(1)
TIM14_CH1
TIM14_CH1
SPI1_SCK,
I2S1_CK
TIM2_CH1_
ETR
SPI1_MISO,
I2S1_MCK
TIM3_CH1
TIM3_CH2
TIM1_BKIN
TIM1_CH1N
TIM16_CH1
TIM17_CH1
EVENTOUT
EVENTOUT
SPI1_MOSI,
I2S1_SD
PA8
PA9
MCO
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
USART1_RTS
IR_OUT
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
EVENTOUT
I2C1_SCL(1)
I2C1_SDA(1)
PA10
PA11
PA12
PA13
PA14
TIM17_BKIN
EVENTOUT
EVENTOUT
SWDAT
SWCLK
USART1_TX(1)
SPI1_NSS,
I2S1_WS
TIM2_CH1_
ETR
PA15
USART1_RX(1)
EVENTOUT
1. This alternate feature is available on standard dies only.
Table 10. Alternate functions selected through GPIOB_AFR registers for port B
Pin name
AF0
AF1
AF2
AF3
PB0
PB1
EVENTOUT
TIM14_CH1
TIM3_CH3
TIM3_CH4
TIM1_CH2N
TIM1_CH3N
PB2
PB3
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
USART1_TX
EVENTOUT
TIM3_CH1
TIM3_CH2
I2C1_SCL
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C1_SCL(1)
I2C1_SDA(1)
EVENTOUT
TIM2_CH2
EVENTOUT
TIM16_BKIN
TIM16_CH1N
TIM17_CH1N
TIM16_CH1
TIM17_CH1
TIM2_CH3
PB4
PB5
I2C1_SMBA
EVENTOUT
PB6
PB7
USART1_RX
PB8
PB9
IR_OUT
PB10
PB11
PB12
PB13
PB14
PB15
EVENTOUT
SPI1_NSS(1)
SPI1_SCK(1)
SPI1_MISO(1)
SPI1_MOSI(1)
TIM2_CH4
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
1. This alternate feature is available on standard dies only.
Memory mapping
STM32F050xx
5
Memory mapping
Figure 7.
STM32F050xx memory map
ꢃX&&&& &&&&
ꢃXꢊꢌꢃꢃ ꢀꢒ&&
ꢃXꢊꢌꢃꢃ ꢃꢃꢃꢃ
!("ꢆ
ꢒ
ꢃX%ꢃꢀꢃ ꢃꢃꢃꢃ
#ORTEXꢋ-ꢃ INTERNAL
PERIPHERALS
ꢃX%ꢃꢃꢃ ꢃꢃꢃꢃ
RESERVED
ꢈ
ꢃX#ꢃꢃꢃ ꢃꢃꢃꢃ
ꢃXꢊꢃꢃꢆ ꢊꢇ&&
ꢃXꢊꢃꢃꢆ ꢃꢃꢃꢃ
!("ꢀ
ꢁ
RESERVED
ꢃX!ꢃꢃꢃ ꢃꢃꢃꢃ
ꢃXꢊꢃꢃꢀ ꢌꢃꢃꢃ
ꢃXꢊꢃꢃꢀ ꢃꢃꢃꢃ
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ꢊ
ꢃXꢀ&&& &&&&
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RESERVED
/PTION BYTES
ꢃXꢀ&&& &ꢌꢃꢃ
ꢃXꢌꢃꢃꢃ ꢃꢃꢃꢃ
RESERVED
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3YSTEM MEMORY
ꢃXꢊꢃꢃꢃ ꢌꢃꢃꢃ
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RESERVED
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0ERIPHERALS
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ꢀ
&LASH MEMORY
RESERVED
32!-
ꢃXꢆꢃꢃꢃ ꢃꢃꢃꢃ
ꢃXꢃꢌꢃꢃ ꢃꢃꢃꢃ
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ꢃ
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"//4 CONFIGURATION
ꢃXꢃꢃꢃꢃ ꢃꢃꢃꢃ
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2ESERVED
-3ꢀꢉꢌꢊꢃ6ꢆ
32/97
Doc ID 023683 Rev 1
STM32F050xx
Memory mapping
Peripheral
Table 11. STM32F050x peripheral register boundary addresses
Bus
Boundary address
Size
~384 MB Reserved
0x4800 1800 - 0x5FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
0x4001 5C00 - 0x4001 7FFF
0x4001 5800 - 0x4001 5BFF
0x4001 4C00 - 0x4001 57FF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0x4001 0800 - 0x4001 23FF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 8000 - 0x4000 FFFF
1KB
1KB
1KB
1KB
1KB
1KB
GPIOF
Reserved
Reserved
GPIOC
GPIOB
AHB2
GPIOA
~128 MB Reserved
1KB
3KB
1KB
3KB
1KB
3KB
1KB
3KB
1KB
32KB
9KB
1KB
3KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
7KB
1KB
1KB
32KB
Reserved
Reserved
CRC
Reserved
FLASH Interface
Reserved
RCC
AHB1
Reserved
DMA
Reserved
Reserved
DBGMCU
Reserved
TIM17
TIM16
Reserved
Reserved
USART1
Reserved
SPI1/I2S1
TIM1
APB
Reserved
ADC
Reserved
EXTI
SYSCFG
Reserved
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Memory mapping
STM32F050xx
Table 11. STM32F050x peripheral register boundary addresses (continued)
Bus
Boundary address
Size
1KB
Peripheral
Reserved
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 5C00 - 0x4000 6FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 4800 - 0x4000 53FF
0x4000 4400 - 0x4000 47FF
0x4000 3C00 - 0x4000 43FF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1400 - 0x4000 1FFF
0x4000 1000 - 0x4000 13FF
0x4000 0800 - 0x4000 0FFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
1KB
1KB
1KB
5KB
1KB
1KB
3 KB
1KB
2KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
3KB
1KB
2KB
1KB
1KB
Reserved
Reserved
PWR
Reserved
Reserved
I2C1
Reserved
Reserved
Reserved
Reserved
Reserved
IWDG
APB
WWDG
RTC
Reserved
TIM14
Reserved
Reserved
Reserved
TIM3
TIM2
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Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3.3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8.
Pin loading conditions
Figure 9.
Pin input voltage
-#5 PIN
-#5 PIN
C = 50 pF
6
).
-3ꢀꢉꢆꢀꢃ6ꢀ
-3ꢀꢉꢆꢀꢀ6ꢀ
Doc ID 023683 Rev 1
35/97
Electrical characteristics
STM32F050xx
6.1.6
Power supply scheme
Figure 10. Power supply scheme
ꢀ
6
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"ACKUP CIRCUITRY
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7AKEꢋUP LOGIC
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)/
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6
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6
6
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2EGULATOR
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33
6
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6
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6
6
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2#Sꢍ 0,,ꢍ
ꢄꢄꢄ
6
33!
-3ꢀꢉꢌꢒꢁ6ꢀ
Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
6.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
*
%%@7#"5
6
"!4
)
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)
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6
$$!
-3ꢀꢉꢆꢀꢇ6ꢀ
36/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics,
Table 13: Current characteristics, and Table 14: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
(1)
Table 12. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
V
DD–VDDA Allowed voltage difference for VDD > VDDA
-
0.4
VDD + 4.0
4.0
V
V
Input voltage on FT and FTf pins
VSS −0.3
VSS −0.3
VSS −0.3
-
(2)
VIN
Input voltage on TTa pins
V
Input voltage on any other pin
4.0
V
|ΔVDDx
|
Variations between different VDD power pins
50
mV
Variations between all the different ground
pins
|VSSX −VSS
|
-
50
mV
Electrostatic discharge voltage (human
body model)
see Section 6.3.11: Electrical
sensitivity characteristics
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 13: Current characteristics for the maximum
allowed injected current values.
Table 13. Current characteristics
Symbol
Ratings
Max.
Unit
Total current into sum of all VDD_x and VDDSDx power lines
(source)(1)
IVDD(Σ)
IVSS(Σ)
120
Total current out of sum of all VSS_x and VSSSD ground lines
(sink)(1)
-120
IVDD(PIN)
IVSS(PIN)
Maximum current into each VDD_x or VDDSDx power pin (source)(1)
Maximum current out of each VSS_x or VSSSD ground pin (sink)(1)
Output current sunk by any I/O and control pin
100
-100
25
IIO(PIN)
mA
Output current source by any I/O and control pin
Total output current sunk by sum of all IOs and control pins(2)
Total output current sourced by sum of all IOs and control pins(2)
Injected current on FT, FTf and B pins(3)
- 25
80
ΣIIO(PIN)
-80
-5/+0
5
IINJ(PIN)
Injected current on TC and RST pin(4)
Injected current on TTa pins(5)
5
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(6)
25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
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Electrical characteristics
STM32F050xx
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 12: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 12: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note (2) below Table 51: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 14. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
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STM32F050xx
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 15. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK
VDD
Internal AHB clock frequency
Internal APB clock frequency
Standard operating voltage
0
0
2
48
48
MHz
V
3.6
Analog operating voltage
(ADC not used)
2
3.6
3.6
Must have a potential equal to or
higher than VDD
(1)
VDDA
V
V
Analog operating voltage
(ADC used)
2.4
VBAT
Backup operating voltage
1.65
–0.3
–0.3
–0.3
0
3.6
TC I/O
VDD+0.3
TTa I/O
V
DDA+0.3
5.5
VIN
I/O input voltage
V
FT and FTf I/O(2)
BOOT0
5.5
LQFP48
-
364
526
169
182
85
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(3)
UFQFPN32
-
PD
mW
UFQFPN28
-
TSSOP20
-
Maximum power dissipation
Low power dissipation(4)
Maximum power dissipation
Low power dissipation(4)
6 suffix version
7 suffix version
–40
–40
–40
–40
–40
–40
Ambient temperature for 6
suffix version
°C
°C
°C
105
105
125
105
125
TA
TJ
Ambient temperature for 7
suffix version
Junction temperature range
1. When the ADC is used, refer to Table 49: ADC characteristics.
2. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 14: Thermal characteristics).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 14:
Thermal characteristics).
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Electrical characteristics
STM32F050xx
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 16 are derived from tests performed under the ambient
temperature condition summarized in Table 15.
Table 16. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
0
Max
∞
Unit
VDD rise time rate
tVDD
V
DD fall time rate
20
0
∞
µs/V
VDDA rise time rate
VDDA fall time rate
∞
tVDDA
20
∞
6.3.3
Embedded reset and power control block characteristics
The parameter given in Table 17 is derived from tests performed under ambient temperature
and V supply voltage conditions summarized in Table 15: General operating conditions.
DD
Table 17. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
1.8(2)
Falling edge
Rising edge
1.88 1.96
V
V
Power on/power down
reset threshold
(1)
VPOR/PDR
1.84 1.92 2.0
(1)
VPDRhyst
PDR hysteresis
-
40
-
mV
ms
(3)
tRSTTEMPO
Reset temporization
1.5
2.5
4.5
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD
.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production.
Table 18. Programmable voltage detector characteristics
Symbol
Parameter
Conditions
Min(1)
Typ Max(1) Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.1
2
2.18
2.08
2.28
2.18
2.38
2.28
2.48
2.38
2.58
2.48
2.26
2.16
2.37
2.27
2.48
2.38
2.58
2.48
2.69
2.59
V
V
V
V
V
V
V
V
V
V
VPVD0
PVD threshold 0
2.19
2.09
2.28
2.18
2.38
2.28
2.47
2.37
VPVD1
VPVD2
VPVD3
VPVD4
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
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Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
Table 18. Programmable voltage detector characteristics (continued)
Symbol
Parameter
PVD threshold 5
Conditions
Min(1)
Typ Max(1) Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.57
2.47
2.66
2.56
2.76
2.66
-
2.68
2.58
2.78
2.68
2.88
2.78
100
2.79
2.69
2.9
2.8
3
V
V
VPVD5
V
VPVD6
PVD threshold 6
PVD threshold 7
V
V
VPVD7
2.9
-
V
(2)
VPVDhyst
IDD(PVD)
PVD hysteresis
mV
µA
PVD current consumption
-
0.15
0.26
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 19 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 15: General operating
DD
conditions.
Table 19. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min Typ Max
Unit
–40 °C < TA < +105 °C 1.16 1.2 1.25
–40 °C < TA < +85 °C 1.16 1.2 1.24(1)
V
V
Internal reference voltage
V
REFINT
ADC sampling time when
reading the internal
reference voltage
5.1 17.1(3)
µs
(2)
TS_vrefint
-
Internal reference voltage
spread over the
temperature range
10(3)
ΔVREFINT
VDDA = 3 V 10 mV
-
-
-
-
mV
100(3)
TCoeff
Temperature coefficient
ppm/°C
1. Data based on characterization results, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
3. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F050xx
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
The data provided apply to standard dies only.
Typical and maximum current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f
to 24 MHz and 1 wait state above 24 MHz)
frequency (0 wait state from 0
HCLK
●
Prefetch is ON when the peripherals are enabled, otherwise it is OFF (to enable
prefetch the PRFTBE bit in the FLASH_ACR register must be set before clock setting
and bus prescaling)
●
When the peripherals are enabled f
= f
HCLK
PCLK
The parameters given in Table 20 to Table 26 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 15: General
operating conditions.
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STM32F050xx
Electrical characteristics
Table 20. Typical and maximum current consumption from V supply at V = 3.6
DD
DD
All peripherals enabled
All peripherals disabled
Symbol
Conditions
fHCLK
Max @ TA(1)
Max @ TA(1)
Typ
Unit
Parameter
Typ
25 °C 85 °C 105 °C
25 °C 85 °C 105 °C
48 MHz 18.4 20.0 20.1
32 MHz 12.4 13.2 13.2
24 MHz 9.9 10.7 10.7
20.4
13.8
11.0
3.9
11.4 12.5 12.5
12.6
8.6
7.0
2.6
0.9
13.1
9.1
6.9
2.7
11.7
7.6
5.9
2.1
0.8
11.8
7.9
6.0
2.2
2.9
1.9
1.5
0.5
0.1
2.9
2.0
1.6
0.6
7.9
6.2
2.2
0.7
8.3
6.8
2.6
0.9
8.5
7.0
2.6
0.9
External
clock (HSE
bypass)
Supply
8 MHz
1 MHz
3.3
0.8
3.6
1.1
3.8
1.1
current in
Run mode,
executing
from Flash
1.1
48 MHz 18.9 20.9 21.1
32 MHz 12.8 13.7 14.2
24 MHz 9.7 10.4 11.2
21.5
14.8
11.3
4.1
11.7 12.3 12.9
8.0
6.1
2.4
8.7
6.5
2.6
9.1
6.7
2.7
Internal
clock (HSI)
8 MHz
3.5
4.0
4.0
48 MHz 17.3 19.7 19.8
32 MHz 11.2 12.5 12.7
24 MHz 8.9 10.0 10.1
20.0
12.7
10.2
3.4
10.3 11.2 11.3
6.7
5.1
1.7
0.2
7.3
5.5
2.0
0.5
7.6
5.8
2.1
0.8
External
clock (HSE
bypass)
Supply
8 MHz
1 MHz
2.8
0.3
3.1
0.6
3.3
0.6
current in
Run mode,
executing
from RAM
IDD
1.3
mA
48 MHz 17.4 19.7 20.0
32 MHz 11.8 12.8 13.1
24 MHz 9.0 10.0 10.1
20.2
13.3
10.2
3.6
10.4 11.2 11.3
6.8
5.2
1.8
2.4
1.6
1.3
0.4
0.1
2.4
1.7
1.3
0.5
7.4
5.7
2.0
2.6
1.7
1.4
0.4
0.1
2.7
1.9
1.5
0.5
7.7
6.0
2.2
2.7
1.9
1.5
0.5
0.1
2.7
1.9
1.5
0.5
Internal
clock (HSI)
8 MHz
3.0
3.2
3.5
48 MHz 10.7 11.7 11.9
12.5
8.2
32 MHz 7.1
24 MHz 5.5
7.8
6.3
2.0
0.5
8.1
6.4
2.0
0.5
External
clock (HSE
bypass)
6.4
Supply
current in
Sleep
8 MHz
1 MHz
1.8
0.2
2.1
mode,
0.5
executing
from Flash
or RAM
48 MHz 10.8 11.9 12.1
12.6
8.5
32 MHz 7.3
24 MHz 5.5
8.0
6.2
2.2
8.4
6.5
2.3
Internal
clock (HSI)
6.5
8 MHz
1.9
2.4
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Electrical characteristics
STM32F050xx
Table 21. Typical and maximum current consumption from the V
supply
DDA
V
= 2.4 V
V
= 3.6 V
DDA
DDA
Conditions
(2)
(2)
Symbol Parameter
fHCLK
Unit
Max @ TA
25 °C 85 °C 105 °C
Max @ TA
25 °C 85 °C 105 °C
(1)
Typ
Typ
48 MHz 150
32 MHz 104
24 MHz 82
170
121
96
178
126
100
3.1
182
128
103
3.3
164
113
88
183
129
102
3.8
195
135
106
4.1
198
138
108
4.4
HSE
bypass,
PLL on
Supply
current in
Run mode,
code
HSE
bypass,
PLL off
8 MHz
1 MHz
2.0
2.0
2.7
3.5
2.7
3.1
3.3
3.5
3.8
4.1
4.4
executing
from Flash
or RAM
48 MHz 220
32 MHz 174
24 MHz 152
240
191
167
248
196
173
252
198
174
244
193
168
263
209
183
275
215
190
278
218
192
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
72
79
82
83
83.5
91
94
95
IDDA
µA
48 MHz 150
32 MHz 104
24 MHz 82
170
121
96
178
126
100
3.1
182
128
103
3.3
164
113
88
183
129
102
3.8
195
135
106
4.1
198
138
108
4.4
HSE
bypass,
PLL on
Supply
current in
Sleep
mode,
code
HSE
bypass,
PLL off
8 MHz
1 MHz
2.0
2.0
2.7
3.5
2.7
3.1
3.3
3.5
3.8
4.1
4.4
48 MHz 220
32 MHz 174
24 MHz 152
240
191
167
248
196
173
252
198
174
244
193
168
263
209
183
275
215
190
278
218
192
executing
from Flash
or RAM
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
72
79
82
83
83.5
91
94
95
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
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STM32F050xx
Electrical characteristics
Table 22. Typical and maximum V consumption in Stop and Standby modes
DD
Typ @VDD (VDD = VDDA
)
Max(1)
Symbol Parameter
Conditions
Unit
TA = TA = TA =
25 °C 85 °C 105 °C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in run mode,
all oscillators OFF
15 15.1 15.25 15.45 15.7 16
18(2)
38
22
55(2)
41(2)
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators
OFF
3.15 3.25 3.35 3.45 3.7
0.8 0.95 1.05 1.2 1.35 1.5
0.65 0.75 0.85 0.95 1.1 1.3
4
5.5(2)
IDD
µA
Supply
current in
Standby
mode
LSI ON and IWDG ON
-
-
-
LSI OFF and IWDG
OFF
2(2)
2.5
3(2)
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production.
upply current
Table 23. Typical and maximum V
consumption in Stop and Standby modes
DDA
Typ @VDD (VDD = VDDA
)
Max(1)
Symbol Parameter
Conditions
Unit
TA = TA = TA =
25 °C 85 °C 105 °C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in run mode,
all oscillators OFF
1.85
1.85
2
2
2.15 2.3 2.45 2.6
2.15 2.3 2.45 2.6
3.5
3.5
3.5
3.5
4.5
4.5
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators
OFF
Supply
LSI ON and IWDG ON 2.25 2.5 2.65 2.85 3.05 3.3
-
-
-
current in
Standby
mode
LSI OFF and IWDG
OFF
1.75 1.9
2
2.15 2.3 2.5
3.5
3.5
4.5
IDDA
µA
Regulator in run mode,
all oscillators OFF
1.11 1.15 1.18 1.22 1.27 1.35
1.11 1.15 1.18 1.22 1.27 1.35
-
-
-
-
-
-
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators
OFF
Supply
current in
Standby
mode
LSI ON and IWDG ON 1.5 1.58 1.65 1.78 1.91 2.04
-
-
-
-
-
-
LSI OFF and IWDG
1
1.02 1.05 1.05 1.15 1.22
OFF
1. Data based on characterization results, not tested in production.
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Electrical characteristics
STM32F050xx
Table 24. Typical and maximum current consumption from V
Typ @ VBAT
supply
BAT
Max(1)
Symbol Parameter
Conditions
Unit
TA =
TA =
TA =
25 °C 85 °C 105 °C
LSE & RTC ON; “Xtal
mode”: lower driving
capability;
0.41 0.43 0.53 0.58 0.71 0.80 0.85
0.71 0.75 0.85 0.91 1.06 1.16 1.25
1.1
1.5
2
Backup
domain
supply
current
LSEDRV[1:0] = '00'
IDD
_
µA
VBAT
LSE & RTC ON; “Xtal
mode” higher driving
capability;
1.55
LSEDRV[1:0] = '11'
1. Data based on characterization results, not tested in production.
Typical current consumption
The MCU is placed under the following conditions:
●
●
●
V
=V
=3.3 V
DDA
DD
All I/O pins are in analog input configuration
The Flash access time is adjusted to f
1 wait state above)
frequency (0 wait states from 0 to 24 MHz,
HCLK
●
●
●
●
Prefetch is ON when the peripherals are enabled, otherwise it is OFF
When the peripherals are enabled, f = f
PCLK
HCLK
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
●
A development tool is connected to the board and the parasitic pull-up current is around
30 µA
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STM32F050xx
Electrical characteristics
Table 25. Typical current consumption in Run mode, code with data processing
running from Flash
Typ
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals
enabled
Peripherals
disabled
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
18.4
13.9
12.4
9.9
6.6
3.3
1.7
1.3
0.8
0.6
140
109
96
11.4
8.9
7.9
6.2
4.3
2.2
1.6
1.2
0.7
0.6
140
109
96
Supply current in Run
mode from VDD
supply
IDD
mA
4 MHz
2 MHz
Running from
HSE crystal
clock 8 MHz,
code
executing
from Flash
1 MHz
500 kHz
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
76
76
Supply current in Run
mode from VDDA
supply
51
51
IDDA
µA
1.7
1.6
1.5
1.1
1.1
1.7
1.6
1.5
1.1
1.1
4 MHz
2 MHz
1 MHz
500 kHz
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Electrical characteristics
STM32F050xx
Table 26. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals Peripherals
enabled
disabled
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
10.7
8.1
7.1
5.5
3.7
1.9
1.5
1.1
0.8
0.6
0.5
140
109
96
2.4
1.8
1.6
1.3
0.9
0.5
0.4
0.3
0.3
0.3
0.3
140
109
96
Supply current in
Sleep mode from VDD
supply
IDD
mA
4 MHz
2 MHz
1 MHz
Running from
HSE crystal
clock 8 MHz,
code executing
from Flash or
RAM
500 kHz
125 kHz
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
76
76
51
51
Supply current in
Sleep mode from
VDDA supply
IDDA
1.7
1.6
1.5
1.1
1.1
1.1
1.7
1.6
1.5
1.1
1.1
1.1
µA
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
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STM32F050xx
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 45: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 28: Peripheral current consumption), the I/Os used by an application also contribute to
the current consumption. When an I/O pin switches, it uses the current from the MCU supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or
external) connected to the pin:
ISW = VDD × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
+ C
S
INT
EXT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
STM32F050xx
Table 27. Switching output I/O current consumption
I/O toggling
frequency (fSW
Symbol
Parameter
Conditions(1)
Typ
Unit
)
4 MHz
0.07
8 MHz
16 MHz
24 MHz
48 MHz
4 MHz
0.15
0.31
0.53
0.92
0.18
0.37
0.76
1.39
2.188
0.32
0.64
1.25
2.23
4.442
0.49
0.94
2.38
3.99
0.64
1.25
3.24
5.02
0.81
1.7
VDD = 3.3 V
C =CINT
8 MHz
VDD = 3.3 V
CEXT = 0 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
8 MHz
VDD = 3.3 V
CEXT = 10 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
I/O current
consumption
ISW
mA
VDD = 3.3 V
8 MHz
CEXT = 22 pF
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDD = 3.3 V
CEXT = 33 pF
8 MHz
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDD = 3.3 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
8 MHz
16 MHz
3.67
4 MHz
8 MHz
0.66
1.43
2.45
4.97
VDD = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
16 MHz
24 MHz
1. CS = 7 pF (estimated value).
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Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 28. The MCU is placed
under the following conditions:
●
●
●
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
●
ambient operating temperature and V supply voltage conditions summarized in
DD
Table 12: Voltage characteristics
Table 28. Peripheral current consumption
Typical consumption at 25 °C
Unit
Peripheral
IDD
IDDA
ADC(1)
0.53
0.10
0.18
0.35
0.48
0.58
0.12
0.06
0.43
0.22
0.63
0.28
1.01
1.00
0.78
0.32
0.45
0.57
0.59
1.07
0.22
0.964
CRC
-
-
-
-
-
-
-
-
-
-
DBGMCU
DMA
GPIOA
GPIOB
GPIOC
GPIOF
I2C1
PWR
SPI1/I2S1
SYSCFG
TIM1
-
-
-
-
-
-
-
-
-
TIM2
TIM3
mA
TIM6
TIM14
TIM16
TIM17
USART1
WWDG
1. ADC is in ready state after setting the ADEN bit in the ADC_CR register (ADRDY bit in ADC_ISR is high).
Doc ID 023683 Rev 1
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Electrical characteristics
STM32F050xx
6.3.6
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 12: High-speed external clock
source AC timing diagram.
Table 29. High-speed external user clock characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fHSE_ext
1
8
32
MHz
VHSEH
VHSEL
tw(HSEH)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time
OSC_IN rise or fall time
15
-
-
-
-
tw(HSEL)
ns
tr(HSE)
tf(HSE)
20
1. Guaranteed by design, not tested in production.
Figure 12. High-speed external clock source AC timing diagram
T
7ꢐ(3%(ꢑ
6
(3%(
ꢉꢃꢔ
ꢀꢃꢔ
6
(3%,
T
T
T
T
Rꢐ(3%ꢑ
Fꢐ(3%ꢑ
7ꢐ(3%,ꢑ
4
(3%
-3ꢀꢉꢆꢀꢊ6ꢆ
52/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 13.
Table 30. Low-speed external user clock characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
User External clock source
frequency
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSEH)
0.7VDD
VSS
450
-
-
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level
voltage
OSC32_IN high or low time
OSC32_IN rise or fall time
tw(LSEL)
ns
tr(LSE)
tf(LSE)
50
1. Guaranteed by design, not tested in production.
Figure 13. Low-speed external clock source AC timing diagram
T
7ꢐ,3%(ꢑ
6
,3%(
ꢉꢃꢔ
ꢀꢃꢔ
6
,3%,
T
T
T
Rꢐ,3%ꢑ
Fꢐ,3%ꢑ
T
7ꢐ,3%,ꢑ
4
,3%
-3ꢀꢉꢆꢀꢁ6ꢆ
Doc ID 023683 Rev 1
53/97
Electrical characteristics
STM32F050xx
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 31. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 31. HSE oscillator characteristics
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency
4
-
8
32
-
MHz
RF
Feedback resistor
200
kΩ
During startup(3)
-
8.5
V
DD=3.3 V, Rm= 30Ω,
-
-
-
-
-
0.4
0.5
0.8
1
-
-
-
-
-
CL=10 pF@8 MHz
VDD=3.3 V, Rm= 45Ω,
CL=10 pF@8 MHz
IDD
HSE current consumption
mA
VDD=3.3 V, Rm= 30Ω,
CL=5 pF@32 MHz
VDD=3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz
V
DD=3.3 V, Rm= 30Ω,
1.5
CL=20 pF@32 MHz
gm
Oscillator transconductance
Startup time
Startup
10
-
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 14). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on electing the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
54/97
Doc ID 023683 Rev 1
STM32F050xx
Figure 14. Typical application with an 8 MHz crystal
Electrical characteristics
2ESONATOR WITH
INTEGRATED CAPACITORS
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CONTROLLED
GAIN
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RESONATOR
2
&
/3#?/54
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2
%84
#
,ꢆ
-3ꢀꢉꢌꢒꢈ6ꢀ
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 32. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
-
0.5
0.9
1
LSEDRV[1:0]= 01
medium low driving capability
-
-
-
-
-
-
IDD
LSE current consumption
µA
LSEDRV[1:0] = 10
medium high driving capability
-
1.3
1.6
-
LSEDRV[1:0]=11
higher driving capability
-
LSEDRV[1:0]=00
lower driving capability
5
8
15
LSEDRV[1:0]= 01
medium low driving capability
-
Oscillator
transconductance
gm
µA/V
LSEDRV[1:0] = 10
medium high driving capability
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
-
-
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
Figure 15. Typical application with a 32.768 kHz crystal
STM32F050xx
2ESONATOR WITH
INTEGRATED CAPACITORS
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to add one.
56/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
6.3.7
Internal clock source characteristics
The parameters given in Table 33 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 15: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI) RC oscillator
(1)
Table 33. HSI oscillator characteristics
Symbol
Parameter
Frequency
HSI user trimming step
Conditions
Min
Typ
Max
Unit
fHSI
-
8
-
-
-
-
-
-
MHz
%
TRIM
-
1(2)
55(2)
4.6(3)
2.9(3)
2.2(3)
1
DuCy(HSI) Duty cycle
45(2)
–3.8(3)
–2.9(3)
–2.3(3)
–1
%
TA = –40 to 105 °C
TA = –10 to 85 °C
TA = 0 to 70 °C
TA = 25 °C
%
Accuracy of the HSI
oscillator (factory
calibrated)
%
ACCHSI
%
%
HSI oscillator startup
time
tsu(HSI)
1(2)
-
2(2)
µs
HSI oscillator power
consumption
IDDA(HSI)
-
80
100(2)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 16. HSI oscillator accuracy characterization results
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Electrical characteristics
STM32F050xx
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
(1)
Table 34. HSI14 oscillator characteristics
Symbol
Parameter
Frequency
HSI14 user-trimming step
Conditions
Min
Typ
Max
Unit
fHSI14
TRIM
-
-
14
-
MHz
%
1(2)
55(2)
5.1(3)
3.1(3)
2.3(3)
1
DuCy(HSI14) Duty cycle
45(2)
-
%
TA = –40 to 105 °C –4.2(3)
TA = –10 to 85 °C –3.2(3)
-
%
-
%
Accuracy of the HSI14
oscillator (factory calibrated)
ACCHSI14
TA = 0 to 70 °C
TA = 25 °C
–2.5(3)
-
%
–1
-
%
tsu(HSI14) HSI14 oscillator startup time
1(2)
-
2(2)
µs
HSI14 oscillator power
IDDA(HSI14)
-
100 150(2)
µA
consumption
1.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Figure 17. HSI14 oscillator accuracy characterization results
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58/97
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STM32F050xx
Electrical characteristics
Low-speed internal (LSI) RC oscillator
(1)
Table 35. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI
Frequency
30
-
40
-
50
85
kHz
µs
(2)
tsu(LSI)
LSI oscillator startup time
(2)
IDDA(LSI)
LSI oscillator power consumption
-
0.75
1.2
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 36 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The event used to wake up the device depends from the current operating mode:
●
Stop or sleep mode: the wakeup event is WFE.
●
The wakeup pin used in sleep, stop and standby modes is PA0.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 15: General operating conditions.
Table 36. Low-power mode wakeup timings
Typ @VDD
Symbol
Parameter
Conditions
Max Unit
= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V
Regulator in run
mode
4.2
8.05
60.35
1.1
4.2
7.05
55.6
1.1
4.2
6.6
4.2
6.27
52.02
1.1
4.2
6.05
50.96
1.1
5
Wakeup from Stop
mode
tWUSTOP
Regulator in low
power mode
9
µs
Wakeup from
Standby mode
tWUSTANDBY
53.5
1.1
Wakeup from Sleep
mode
tWUSLEEP
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Electrical characteristics
STM32F050xx
6.3.8
PLL characteristics
The parameters given in Table 37 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 15: General operating
conditions.
Table 37. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max
PLL input clock(1)
1(2)
40(2)
16(2)
-
8.0
24(2)
60(2)
48
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
-
-
-
-
fPLL_OUT
tLOCK
MHz
µs
200(2)
300(2)
JitterPLL
Cycle-to-cycle jitter
-
ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT
.
2. Guaranteed by design, not tested in production.
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Electrical characteristics
6.3.9
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
Table 38. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
16-bit programming time TA = –40 to +105 °C
40
20
20
-
53.5
60
40
40
10
12
µs
ms
ms
mA
mA
tERASE Page (1 KB) erase time TA = –40 to +105 °C
-
-
-
-
tME
Mass erase time
TA = –40 to +105 °C
Write mode
IDD
Supply current
Erase mode
-
1. Guaranteed by design, not tested in production.
Table 39. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions
Unit
Min(1)
TA = –40 to +85 °C (6 suffix versions)
NEND
Endurance
kcycles
Years
10
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C
30
10
20
tRET
Data retention
1 kcycle(2) at TA = 105 °C
10 kcycles(2) at TA = 55 °C
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 40. They are based on the EMS levels and classes
defined in application note AN1709.
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Electrical characteristics
STM32F050xx
Table 40. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP64, TA = +25 °C,
fHCLK = 48 MHz
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
3B
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP64, TA = +25 °C,
fHCLK = 48 MHz
conforms to IEC 61000-4-4
VEFTB
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 41. EMI characteristics
Max vs. [fHSE/fHCLK
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/48 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
-3
28
23
4
VDD = 3.6 V, TA = 25 °C,
LQFP64 package
compliant with IEC
61967-2
dBµV
-
SEMI
Peak level
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Electrical characteristics
6.3.11
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 42. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
Electrostatic discharge
TA = +25 °C, conforming
V
2
II
2000
500
ESD(HBM) voltage (human body model) to JESD22-A114
V
Electrostatic discharge
TA = +25 °C, conforming
V
ESD(CDM) voltage (charge device model) to JESD22-C101
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 43. Electrical sensitivities
Symbol
Parameter
Conditions
Class
II level A
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
6.3.12
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (more
than 5 LSB TUE), out of conventional limits of current injection on adjacent pins (more than
–5 µA) or other functional failure (reset occurrence or oscillator frequency deviation, for
example).
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Electrical characteristics
The characterization results are given in Table 44.
STM32F050xx
Table 44. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
Injected current on BOOT0
–0
–5
NA
NA
Injected current on all FT and FTf pins with induced
leakage current on adjacent pins less than –5 µA
IINJ
mA
Injected current on all TTa pins with induced leakage
current on adjacent pins less than –5 µA
–5
–5
+5
+5
Injected current on all TC & RESET pins with induced
leakage current on adjacent pins less than –5 µA
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Electrical characteristics
6.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the conditions summarized in Table 15: General operating conditions. All
I/Os are CMOS and TTL compliant.
Table 45. I/O static characteristics
Symbol
Parameter
Conditions
TC and TTa I/O
Min
Typ
Max
Unit
-
-
0.3 VDD+0.07(1)
FT and FTf I/O
BOOT0
-
-
0.475 VDD–0.2(1)
Low level input
voltage
VIL
V
-
-
0.3 VDD–0.3(1)
All I/Os except BOOT0 pin
TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
0.3 VDD
0.445 VDD+0.398(1)
-
-
-
-
-
-
-
-
0.5 VDD+0.2(1)
-
High level input
voltage
VIH
V
0.2 VDD+0.95(1)
-
All I/Os except BOOT0 pin
TC and TTa I/O
FT and FTf I/O
BOOT0
0.7 VDD
-
-
-
-
200(1)
100(1)
300(1)
Schmitt trigger
hysteresis
Vhys
mV
VSS ≤VIN ≤VDD
I/O TC, FT and FTf
-
-
-
-
-
-
±±. 1
±±. 1
10
VSS ≤VIN ≤VDD
2 V≤VDD ≤VDDA ≤3.6 V
I/O TTa used in digital
mode
VIN= 5 V
I/O FT and FTf
Input leakage
current (2)
Ilkg
µA
VIN= 3.6 V,
2 V≤VDD ≤VIN
VDDA = 3.6 V
I/O TTa used in digital
mode
-
-
1
VSS ≤VIN ≤VDDA
2 V≤VDD ≤VDDA ≤3.6 V
-
-
±±. 2
I/O TTa used in analog
mode
Weak pull-up
equivalent
resistor(3)
RPU
VIN = VSS
25
40
55
kΩ
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Electrical characteristics
STM32F050xx
Table 45. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Weak pull-down
equivalent
RPD
VIN = VDD
25
40
55
-
kΩ
resistor(3)
I/O pin
capacitance
CIO
-
5
pF
1. Data based on design simulation only. Not tested in production.
2. Leakage could be higher than maximum value, if negative current is injected on adjacent pins.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Electrical characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os, and
in Figure 20 and Figure 21 for 5 V tolerant I/Os. The following curves are design simulation
results, not tested in production.
Figure 18. TC and TTa I/O input characteristics - CMOS port
VIL/VIH (V)
= 0.7V
+0.398
= 0.445V
= 0.3V
CMOS standard requirements V
V
V
VIHmin 2.0
+0.07
1.3
Input range not
guaranteed
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30255V1
Figure 19. TC and TTa I/O input characteristics - TTL port
VIL/VIH (V)
+0.398
TTL standard requirements VIHmin = 2 V
= 0.445V
= 0.3V
V
VIHmin 2.0
1.3
+0.07
V
Input range not
guaranteed
VILmax 0.8
0.7
TTL standard requirements VILmax = 0.8 V
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30256V1
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Electrical characteristics
STM32F050xx
Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
VIL/VIH (V)
+0.2
CMOS standard requirements VIH min= 0.7VDD
= 0.5V
V
V
2.0
-0.2
= 0.475V
Input range not
guaranteed
1.0
CMOS standard requirements VILmax = 0.3VDD
0.5
VDD (V)
2.0
3.6
MS30257V1
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port
VIL/VIH (V)
+0.2
TTL standard requirements VIHmin = 2 V
= 0.5V
V
V
2.0
-0.2
Input range not
guaranteed
= 0.475V
1.0
0.8
TTL standard requirements VILmax = 0.8 V
0.5
VDD (V)
2.0
2.7
3.6
MS30258V1
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Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed V ).
V
OL/ OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
●
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 13: Current characteristics).
VDD
●
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 13: Current characteristics).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 15: General operating conditions. All I/Os are CMOS and TTL compliant (FT, TTa or
TC unless otherwise specified).
Table 46. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
(1)
VOL
Output low level voltage for an I/O pin
CMOS port(2)
IIO = +8 mA
-
0.4
V
(3)
VOH
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
VDD–0.4
-
2.7 V < VDD < 3.6 V
(1)
VOL
TTL port(2)
IIO =+ 8mA
-
0.4
V
(3)
VOH
2.4
-
2.7 V < VDD < 3.6 V
(1)(4)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3
V
IIO = +20 mA
(3)(4)
2.7 V < VDD < 3.6 V
VOH
VDD–1.3
-
-
(1)(4)
VOL
0.4
V
-
IIO = +6 mA
(3)(4)
2 V < VDD < 2.7 V
VOH
VDD–0.4
IIO = +20 mA
Output low level voltage for an FTf I/O
pin in FM+ mode
(1)
VOLFM+
-
0.4
V
2.7 V < VDD < 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 13:
Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 13: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Data based on design simulation only. Not tested in production.
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Electrical characteristics
STM32F050xx
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and
Table 47, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 15: General
DD
operating conditions.
(1)
Table 47. I/O AC characteristics
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
Min Max
Unit
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 V to 3.6 V
-
-
2
MHz
Output high to low level
tf(IO)out
125(3)
x0
01
fall time
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
ns
MHz
ns
Output low to high level
rise time
tr(IO)out
-
-
-
125(3)
10
fmax(IO)out Maximum frequency(2)
Output high to low level
fall time
tf(IO)out
25(3)
Output low to high level
rise time
tr(IO)out
-
25(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 50 pF, VDD = 2 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
50
30
fmax(IO)out Maximum frequency(2)
MHz
20
5(3)
8(3)
12(3)
5(3)
8(3)
12(3)
2(3)
Output high to low level
fall time
11
tf(IO)out
ns
Output low to high level
rise time
tr(IO)out
fmax(IO)out Maximum frequency(2)
MHz
ns
FM+
Output high to low level
fall time
tf(IO)out
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
-
-
12(3)
34(3)
configuration
(4)
Output low to high level
rise time
tr(IO)out
Pulse width of external
tEXTIpw
signals detected by the
EXTI controller
10
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 22.
3. Guaranteed by design, not tested in production.
4. When FM+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F05xxx reference manual RM0091
for a detailed description of FM+ I/O configuration.
70/97
Doc ID 023683 Rev 1
STM32F050xx
Figure 22. I/O AC characteristics definition
Electrical characteristics
90%
10 %
50%
50%
90%
10%
t
EXTERNAL
OUTPUT
ON 50pF
t
r(IO)out
r(IO)out
T
Maximum frequency is achieved if (t + t ) £ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
ai14131
6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 45: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 48 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15: General operating conditions.
Table 48. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)
VIL(NRST)
NRST input low level voltage
NRST input high level voltage
–0.3
2
-
-
0.8
V
(1)
VIH(NRST)
Vhys(NRST)
RPU
VDD+0.3
NRST Schmitt trigger voltage
hysteresis
-
200
-
mV
Weak pull-up equivalent resistor(2)
VIN = VSS
25
-
40
-
55
100
-
kΩ
ns
ns
(1)
VF(NRST)
NRST input filtered pulse
(1)
VNF(NRST)
NRST input not filtered pulse
300
-
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 23. Recommended NRST pin protection
6
$$
%XTERNAL
RESET CIRCUITꢐꢀꢑ
2
05
ꢐꢆꢑ
)NTERNAL 2ESET
.234
&ILTER
ꢃꢄꢀ &
-3ꢀꢉꢌꢒꢌ6ꢀ
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 48. Otherwise the reset will not be taken into account by the device.
Doc ID 023683 Rev 1
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Electrical characteristics
STM32F050xx
6.3.15
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 49 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 15: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 49. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
3.6
Unit
Analog supply voltage for
ADC ON
VDDA
fADC
2.4
-
V
ADC clock frequency
Sampling rate
0.6
-
-
14
1
MHz
MHz
(1)
0.05
fS
f
ADC = 14 MHz
-
-
-
-
-
823
17
kHz
1/fADC
V
(1)
External trigger frequency
fTRIG
VAIN
Conversion voltage range
External input impedance
Sampling switch resistance
0
VDDA
See Equation 1 and
Table 50 for details
(1)
RAIN
-
-
-
-
-
-
50
1
kΩ
kΩ
pF
(1)
RADC
Internal sample and hold
capacitor
(1)
8
CADC
f
ADC = 14 MHz
5.9
µs
1/fADC
µs
(1)
Calibration time
tCAL
83
0.196
5.5
fADC = fPCLK/2 = 14 MHz
fADC = fPCLK/2
1/fPCLK
µs
(1)
Trigger conversion latency
fADC = fPCLK/4 = 12 MHz
0.219
10.5
-
tlatr
f
ADC = fPCLK/4
1/fPCLK
µs
fADC = fHSI14 = 14 MHz
0.188
-
0.259
-
ADC jitter on trigger
conversion
JitterADC
fADC = fHSI14
1
1/fHSI14
f
f
ADC = 14 MHz
0.107
1.5
0
-
-
17.1
239.5
1
µs
1/fADC
µs
(1)
Sampling time
Power-up time
tS
(1)
tSTAB
0
ADC = 14 MHz
1
18
µs
Total conversion time
(including sampling time)
(1)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Guaranteed by design, not tested in production.
72/97
Doc ID 023683 Rev 1
STM32F050xx
Equation 1: R
Electrical characteristics
max formula
AIN
TS
RAIN < --------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
(1)
Table 50.
R
max for f
= 14 MHz
AIN
ADC
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
7.5
0.11
0.54
0.96
2.04
2.96
3.96
5.11
17.1
0.4
5.9
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Guaranteed by design, not tested in production.
(1)(2) (3)
Table 51. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
1.3
1
2
1.5
1.5
1
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
Gain error
0.5
0.7
0.8
3.3
1.9
2.8
0.7
1.2
3.3
1.9
2.8
0.7
1.2
LSB
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
1.5
4
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
2.8
3
Gain error
LSB
LSB
VDDA = 2.7 V to 3.6 V
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
1.3
1.7
4
TA = −40 to 105 °C
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
TA = 25 °C
2.8
3
Gain error
Differential linearity error
Integral linearity error
1.3
1.7
1. ADC DC accuracy values are measured after internal calibration.
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Electrical characteristics
STM32F050xx
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not
affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
Figure 24. ADC accuracy characteristics
V
DDA
ꢁꢀ
1 LSB
IDEAL
ꢊꢃꢉꢈ
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
0
V
1
2
3
4
5
6
7
4093 4094 4095 4096
V
DDA
SSA
-3ꢀꢉꢌꢌꢃ6ꢀ
Figure 25. Typical connection diagram using the ADC
6
$$!
Sample and hold ADC
converter
V
0.6 V
T
(1)
AIN
R
R
ADC
AINx
12-bit
converter
I
1 μA
L
C
V
T
parasitic
V
AIN
0.6 V
C
ADC
-3ꢀꢉꢌꢌꢀ6ꢆ
1. Refer to Table 49: ADC characteristics for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
74/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
6.3.16
Temperature sensor characteristics
Table 52. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
-
±1
4.3
1.43
-
±2
4.6
1.52
10
°C
mV/°C
V
Avg_Slope(1) Average slope
4.0
1.34
4
V25
Voltage at 25 °C
Startup time
(1)
tSTART
µs
ADC sampling time when reading the
temperature
(1)(2)
TS_temp
17.1
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.17
V
monitoring characteristics
BAT
Table 53.
Symbol
V
monitoring characteristics
Parameter
BAT
Min
Typ
Max
Unit
R
Q
Er(1)
Resistor bridge for VBAT
Ratio on VBAT measurement
Error on Q
-
-
50
2
-
-
KΩ
–1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
(1)(2)
TS_vbat
5
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.18
Timer characteristics
The parameters given in Table 54 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 54. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
ns
1
-
tres(TIM)
Timer resolution time
fTIMxCLK = 48 MHz
20.8
-
fTIMxCLK/2
0
0
-
MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 48 MHz
TIMx (except TIM2)
TIM2
24
16
32
MHz
ResTIM
Timer resolution
bit
-
Doc ID 023683 Rev 1
75/97
Electrical characteristics
Table 54. TIMx characteristics (continued)
STM32F050xx
(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
µs
1
65536
1365
tCOUNTER
16-bit counter clock period
fTIMxCLK = 48 MHz 0.0208
-
tTIMxCLK
s
65536 × 65536
89.48
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 48 MHz
-
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17
timers.
(1)
Table 55. IWDG min/max timeout period at 40 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
/8
0
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
1
/16
/32
/64
/128
/256
2
1638.4
3276.8
6553.6
13107.2
26214.4
3
4
ms
5
6 or 7
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from
30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the
phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of
uncertainty.
Table 56. WWDG min-max timeout value @48 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0853
0.1706
0.3413
0.6826
5.4613
10.9226
21.8453
43.6906
ms
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Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
6.3.19
Communication interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature, f frequency and V supply voltage conditions
PCLK
DD
summarized in Table 15: General operating conditions.
2
2
The I C interface meets the requirements of the standard I C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and V is
DD
disabled, but is still present.
2
The I C characteristics are described in Table 57. Refer also to Section 6.3.13: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
(1)
Table 57. I C characteristics
Standard mode
Fast mode
Min Max
Fast Mode Plus
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
-
1.3
0.6
-
0.5
0.26
50
-
µs
-
-
-
250
0(3)
-
100
0(3)
-
-
SDA data hold time
3450(2)
900(2)
0(4)
450(2)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
1000
-
300
-
120
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
-
300
-
300
-
120
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
0.26
0.26
0.26
0.5
-
-
-
-
µs
Repeated Start condition
setup time
tsu(STO)
Stop condition setup time
μs
μs
Stop to Start condition time
(bus free)
tw(STO:STA)
Capacitive load for each bus
line
Cb
-
400
-
400
-
550
pF
The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in
production.
1.
The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
2.
3.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
4. The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
Doc ID 023683 Rev 1
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Electrical characteristics
STM32F050xx
(1)
Table 58. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Pulse width of spikes that are
suppressed by the analog filter
tSP
50
260
ns
1. Guaranteed by design, not tested in production.
2
Figure 26. I C bus AC waveforms and measurement circuit
6
6
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
SPI/I2S characteristics
2
Unless otherwise specified, the parameters given in Table 59 for SPI or in Table 60 for I S
are derived from tests performed under ambient temperature, f frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 15: General operating conditions.
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
78/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
Table 59. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
-
-
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
-
6
ns
ns
%
(1)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4Tpclk
-
-
(1)
th(NSS)
2Tpclk + 10
(1)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
Tpclk/2 -2
Tpclk/2 + 1
(1)
(1)
Master mode
Slave mode
Master mode
Slave mode
4
-
tsu(MI)
tsu(SI)
(1)
5
-
(1)
th(MI)
4
-
Data input hold time
(1)
th(SI)
5
-
(1)(2)
ta(SO)
Data output access time Slave mode, fPCLK = 20 MHz
Data output disable time Slave mode
0
3Tpclk
(1)(3)
tdis(SO)
tv(SO)
tv(MO)
th(SO)
0
18
(1)
(1)
(1)
(1)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
-
22.5
6
-
11.5
2
Data output hold time
th(MO)
-
SPI slave input clock duty
cycle
DuCy(SCK)
Slave mode
25
75
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
Doc ID 023683 Rev 1
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Electrical characteristics
STM32F050xx
Figure 27. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 28. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
80/97
Doc ID 023683 Rev 1
STM32F050xx
Electrical characteristics
(1)
Figure 29. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
BIT6 IN
LSB IN
t
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
Doc ID 023683 Rev 1
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Electrical characteristics
STM32F050xx
2
Table 60. I S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
1.597
1.601
fCK
1/tc(CK)
I2S clock frequency
MHz
Slave mode
0
-
6.5
tr(CK)
I2S clock rise time
I2S clock fall time
I2S clock high time
I2S clock low time
WS valid time
10
12
-
Capacitive load CL = 15 pF
tf(CK)
-
(1)
(1)
tw(CKH)
306
312
2
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
tw(CKL)
-
ns
%
(1)
tv(WS)
th(WS)
tsu(WS)
Master mode
Master mode
Slave mode
Slave mode
-
(1)
(1)
(1)
WS hold time
2
-
WS setup time
WS hold time
7
-
th(WS)
0
-
I2S slave input clock duty
cycle
DuCy(SCK)
Slave mode
25
75
(1)
tsu(SD_MR)
Data input setup time
Data input setup time
Master receiver
Slave receiver
Master receiver
Slave receiver
6
2
-
-
-
-
(1)
tsu(SD_SR)
(1)(2)
th(SD_MR)
th(SD_SR)
4
Data input hold time
(1)(2)
0.5
Slave transmitter (after enable
edge)
(1)(2)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
-
13
-
20
-
ns
Slave transmitter (after enable
edge)
(1)
Master transmitter (after enable
edge)
(1)(2)
(1)
4
-
Master transmitter (after enable
edge)
0
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
82/97
Doc ID 023683 Rev 1
STM32F050xx
Figure 30. I2S slave timing diagram (Philips protocol)
Electrical characteristics
t
c(CK)
CPOL = 0
CPOL = 1
WS input
t
t
t
w(CKL)
h(WS)
w(CKH)
t
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
transmit
(2)
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
(2)
LSB receive
Bitn receive
LSB receive
SD
receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 31. I2S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
h(WS)
t
v(WS)
w(CKL)
t
t
v(SD_MT)
h(SD_MT)
(2)
SD
transmit
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
(2)
SD
LSB receive
Bitn receive
LSB receive
receive
ai14884b
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Package characteristics
STM32F050xx
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
84/97
Doc ID 023683 Rev 1
STM32F050xx
Package characteristics
Figure 32. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline
D
ccc
C
D1
D3
A
A2
25
36
24
37
L1
b
E3
E1 E
48
L
13
A1
K
Pin 1
identification
1
12
c
5B_ME
1. Drawing is not to scale.
Table 61. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
9.200
7.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
0.050
1.350
0.170
0.090
8.800
6.800
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
1.400
0.220
0.0551
0.0087
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0°
0.750
7°
0.0177
0°
0.0295
7°
L1
k
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 023683 Rev 1
85/97
Package characteristics
Figure 33. LQFP48 recommended footprint
STM32F050xx
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911b
1. Drawing is not to scale.
2. Dimensions are in millimeters.
86/97
Doc ID 023683 Rev 1
STM32F050xx
Package characteristics
Figure 34. UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
b
E
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
A0B8_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must
be connected. It is referred to as pin 0 in Table 8: Pin definitions.
Table 62. UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data
millimeters
inches(1)
Dim.
Min
Typ
Max
Min
Typ
Max
A
A1
A3
b
0.5
0.55
0.02
0.152
0.23
5.00
3.50
5.00
0.6
0.0197
0
0.0217
0.0008
0.006
0.0236
0.0020
0.00
0.05
0.18
4.90
0.28
5.10
0.0071
0.1929
0.0091
0.1969
0.1378
0.1969
0.0110
0.2008
D
D2
E
4.90
3.40
5.10
3.60
0.1929
0.1339
0.2008
0.1417
E2
3.50
0.1378
e
L
0.500
0.40
0.08
0.0197
0.0157
0.0031
0.30
0.50
0.0118
0.0197
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 023683 Rev 1
87/97
Package characteristics
Figure 35. UFQFPN32 recommended footprint
STM32F050xx
1. Drawing is not to scale.
2. Dimensions are in millimeters.
88/97
Doc ID 023683 Rev 1
STM32F050xx
Package characteristics
Figure 36. UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline
$
3EATING
0LANE
"
$ꢀ
!
#O ꢀꢇꢃXꢊꢁ
0IN ꢀ CORNER
%ꢀ
%
,ꢀ
ꢀ
,
0IN ꢀ )$
ꢆꢌ
$ETAIL :
$ETAIL :
2Oꢄꢀꢆꢁ 4YPꢄ
E
4
!ꢀ
!
3EATING
0LANE
B
!ꢃ"ꢃ?-%?6ꢊ
1. Drawing is not to scale.
2. Dimensions are in millimeters.
3. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
X
Table 63. UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.5
-0.05
3.9
0.55
0
0.6
0.05
4.1
0.0197
-0.002
0.1535
0.1142
0.1535
0.1142
0.0118
0.0098
0.0217
0
0.0236
0.002
4
0.1575
0.1181
0.1575
0.1181
0.0157
0.0138
0.006
0.1614
0.122
D1
E
2.9
3
3.1
3.9
4
4.1
0.1614
0.122
E1
L
2.9
3
3.1
0.3
0.4
0.35
0.152
0.25
0.5
0.5
0.0197
0.0177
L1
T
0.25
0.45
b
0.2
0.3
0.0079
0.0098
0.0197
0.0118
e
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 023683 Rev 1
89/97
Package characteristics
Figure 37. UFQFPN28 recommended footprint
ꢇꢄꢇꢃ
STM32F050xx
ꢃꢄꢁꢃ
ꢇꢄꢆꢃ
ꢇꢄꢆꢃ
ꢊꢄꢇꢃ
ꢇꢄꢇꢃ
ꢃꢄꢇꢃ
ꢃꢄꢁꢃ
ꢃꢄꢁꢁ
!ꢃ"ꢃ?-%?&0
ꢃꢄꢁꢃ
1. Dimensions are in millimeters
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
90/97
Doc ID 023683 Rev 1
STM32F050xx
Package characteristics
Figure 38. TSSOP20 - 20-pin thin shrink small outline
$
ꢆꢃ
ꢀꢀ
C
%ꢀ
%
ꢀ
ꢀꢃ
K
AAA
#0
!ꢀ
,
!
!ꢆ
,ꢀ
B
E
9!?-%
1. Drawing is not to scale.
Table 64. TSSOP20 – 20-pin thin shrink small outline package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
A
A1
A2
b
1.2
0.15
1.05
0.3
0.0472
0.0059
0.0413
0.0118
0.0079
0.2598
0.2598
0.1772
0.05
0.8
0.002
0.0315
0.0075
0.0035
0.252
1
0.0394
0.19
0.09
6.4
c
0.2
D
6.5
6.4
4.4
0.65
0.6
1
6.6
0.2559
0.252
E
6.2
6.6
0.2441
0.1693
E1
e
4.3
4.5
0.1732
0.0256
0.0236
0.0394
L
0.45
0.0°
0.75
0.0177
0.0°
0.0295
L1
k
8.0°
0.1
8.0°
aaa
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 023683 Rev 1
91/97
Package characteristics
Figure 39. TSSOP20 recommended footprint
STM32F050xx
1. Dimensions are in millimeters
92/97
Doc ID 023683 Rev 1
STM32F050xx
Package characteristics
7.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 15: General operating conditions on page 39.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
●
●
●
●
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in ° C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 65. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
55
Thermal resistance junction-ambient
UFQFPN32 - 5 × 5 mm
38
Θ
°C/W
JA
Thermal resistance junction-ambient
UFQFPN28 - 4 × 4 mm
118
110
Thermal resistance junction-ambient
TSSOP20
7.2.1
7.2.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F05xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Doc ID 023683 Rev 1
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Package characteristics
STM32F050xx
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T = 80 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Using the values obtained in Table 65 T
is calculated as follows:
Jmax
–
T
For LQFP48, 55 °C/W
= 80 °C + (55°C/W × 447 mW) = 80 °C + 24.585 °C = 104.585 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Table 15:
J
General operating conditions on page 39.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Note:
With this given P
we can find the T
allowed for a given device temperature range
Dmax
Amax
(order code suffix 6 or 7).
Suffix 6: T
Suffix 7: T
= T
= T
- (55°C/W × 447 mW) = 105-24.585 = 80.415 °C
- (55°C/W × 447 mW) = 125-24.585 = 100.415 °C
Amax
Amax
Jmax
Jmax
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
= 100 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V= 70 mW
INTmax
= 20 × 8 mA × 0.4 V = 64 mW
IOmax
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
= 70 + 64 = 134 mW
Dmax
Thus: P
= 134 mW
Dmax
Using the values obtained in Table 65 T
is calculated as follows:
Jmax
–
T
For LQFP48, 55 °C/W
= 100 °C + (55 °C/W × 134 mW) = 100 °C + 7.37 °C = 107.37 °C
Jmax
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation in order to be able to
use suffix 6 parts.
94/97
Doc ID 023683 Rev 1
STM32F050xx
Part numbering
8
Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Example:
STM32
F
050
C
6
T
6
A
x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
050 = STM32F050xx
Pin count
F = 20 pins
G = 28 pins
K = 32 pins
C = 48 pins
Code size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
Package
P = TSSOP
U = UFQFPN
T = LQFP
Temperature range
6 = –40 °C to +85 °C
7 = –40 °C to +105 °C
Internal code
A = non-optimized die
Blank = standard die
Options
xxx = programmed parts
TR = tape and real
Doc ID 023683 Rev 1
95/97
Revision history
STM32F050xx
9
Revision history
Table 66. Document revision history
Date
Revision
Changes
22-Nov-2012
1
Initial release
96/97
Doc ID 023683 Rev 1
STM32F050xx
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