STM32F051T8 [STMICROELECTRONICS]
主流ARM Cortex-M0基本型系列MCU，具有64 KB Flash、48 MHz CPU、运动控制和CEC功能;
| 型号： | STM32F051T8 |
| 厂家： | 
ST |
| 描述： | 主流ARM Cortex-M0基本型系列MCU，具有64 KB Flash、48 MHz CPU、运动控制和CEC功能 |
| 文件： | 总104页 (文件大小：1170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F051x4 STM32F051x6
STM32F051x8
Low- and medium-density advanced ARM™-based 32-bit MCU with
16 to 64 Kbytes Flash, timers, ADC, DAC and comm. interfaces
Datasheet − production data
Features
■ Core: ARM 32-bit Cortex™-M0 CPU,
frequency up to 48 MHz
LQFP64 10x10 mm
■ Memories
UFQFPN32 5x5 mm
LQFP48 7x7 mm
– 16 to 64 Kbytes of Flash memory
LQFP32 7x7 mm
– 8 Kbytes of SRAM with HW parity checking
– One 16-bit timer, with 2 IC/OC, 1 OCN,
deadtime generation and emergency stop
■ CRC calculation unit
– Two 16-bit timers, each with IC/OC and
OCN, deadtime generation, emergency
stop and modulator gate for IR control
■ Reset and power management
– Voltage range: 2.0 V to 3.6 V
– Power-on/Power down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop, Standby
– One 16-bit timer with 1 IC/OC
– Independent and system watchdog timers
– SysTick timer: 24-bit downcounter
– One 16-bit basic timer to drive the DAC
– V
supply for RTC and backup registers
BAT
■ Clock management
■ Calendar RTC with alarm and periodic wakeup
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
from Stop/Standby
■ Communication interfaces
2
– Up to two I C interfaces; one supporting
Fast Mode Plus (1 Mbit/s) with 20 mA
current sink, SMBus/PMBus, and wakeup
from STOP
■ Up to 55 fast I/Os
– All mappable on external interrupt vectors
– Up to 36 I/Os with 5 V tolerant capability
– Up to two USARTs supporting master
synchronous SPI and modem control; one
with ISO7816 interface, LIN, IrDA
capability, auto baud rate detection and
wakeup feature
■ 5-channel DMA controller
■ 1 × 12-bit, 1.0 µs ADC (up to 16 channels)
– Conversion range: 0 to 3.6V
– Up to two SPIs (18 Mbit/s) with 4 to 16
– Separate analog supply from 2.4 up to 3.6
2
programmable bit frame, 1 with I S
interface multiplexed
■ One 12-bit D/A converter
■ Two fast low-power analog comparators with
– HDMI CEC interface, wakeup on header
reception
programmable input and output
■ Up to 18 capacitive sensing channels
supporting touchkey, linear and rotary touch
sensors
■ Serial wire debug (SWD)
■ 96-bit unique ID
■ Up to 11 timers
Table 1.
Device summary
– One 16-bit 7-channel advanced-control
timer for 6 channels PWM output, with
deadtime generation and emergency stop
– One 32-bit and one 16-bit timer, with up to
4 IC/OC, usable for IR control decoding
Reference
Part number
STM32F051x4
STM32F051x6
STM32F051x8
STM32F051K4, STM32F051C4, STM32F051R4
STM32F051K6, STM32F051C6, STM32F051R6
STM32F051C8, STM32F051R8, STM32F051K8
July 2012
Doc ID 022265 Rev 3
1/105
This is information on a product in full production.
www.st.com
1
Contents
STM32F051x
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
3.5
ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1
3.5.2
3.5.3
3.5.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
3.7
3.8
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9.1
3.9.2
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REFINT
3.10.3
V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
BAT
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.2 General-purpose timers (TIM2..3, TIM14..17) . . . . . . . . . . . . . . . . . . . . 21
3.14.3 Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17 Universal synchronous/asynchronous receiver transmitters (USART) . . . 24
3.18 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 24
3.19 High-definition multimedia interface (HDMI) - consumer electronics control
(CEC) 25
3.20 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4
5
6
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43
Embedded reset and power control block characteristics . . . . . . . . . . . 43
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.16 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.17 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.19
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
BAT
6.3.20 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.21 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1
7.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2.1
7.2.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 100
8
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F051x family device features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Capacitive sensing GPIOs available on STM32F051x devices . . . . . . . . . . . . . . . . . . . . . 19
No. of capacitive sensing channels available on STM32F051x devices. . . . . . . . . . . . . . . 19
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
Table 9.
STM32F051x I C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
STM32F051x USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F051x SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 33
Alternate functions selected through GPIOA_AFR registers for port B . . . . . . . . . . . . . . . 34
STM32F051x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical and maximum current consumption from V supply at VDD = 3.6 V. . . . . . . . . . 46
DD
Typical and maximum current consumption from the V
supply . . . . . . . . . . . . . . . . . . 47
DDA
Typical and maximum V consumption in Stop and Standby modes . . . . . . . . . . . . . . . 48
DD
Typical and maximum V
consumption in Stop and Standby modes . . . . . . . . . . . . . . 49
DDA
Typical and maximum current consumption from V
supply. . . . . . . . . . . . . . . . . . . . . . 49
BAT
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 51
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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List of tables
STM32F051x
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
R
max for f
= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AIN
ADC
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
WWDG min-max timeout value @48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2
I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . . 92
LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 94
LQFP32 7 x 7mm 32-pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . 96
UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 72.
Table 73.
Table 74.
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Doc ID 022265 Rev 3
STM32F051x
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP64 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LQFP32 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32F051x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 13. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 15. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 16. TC and TTa I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 17. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 71
Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port. . . . . . . . . . . . . . . . . . . 71
Figure 20. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 22. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 23. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 24. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2
Figure 25. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
(1)
Figure 27. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
(1)
Figure 28. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 29. I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 30. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 31. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 92
Figure 32. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 33. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 94
Figure 34. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 35. LQFP32 7 x 7mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 96
Figure 36. LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . . 98
Figure 38. UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 39. LQFP64 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
D
A
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Introduction
STM32F051x
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F051x microcontrollers.
This STM32F051x4, STM32F051x6, and STM32F051x8 datasheet should be read in
conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is
available from the STMicroelectronics website www.st.com.
For information on the ARM Cortex™-M0 core, please refer to the Cortex™-M0 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html.
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STM32F051x
Description
2
Description
The STM32F051x family incorporates the high-performance ARM Cortex™-M0 32-bit RISC
core operating at a 48 MHz frequency, high-speed embedded memories (Flash memory up
to 64 Kbytes and SRAM up to 8 Kbytes), and an extensive range of enhanced peripherals
2
and I/Os. All devices offer standard communication interfaces (up to two I Cs, two SPIs, one
I2S, one HDMI CEC, and up to two USARTs), one 12-bit ADC, one 12-bit DAC, up to five
general-purpose 16-bit timers, a 32-bit timer and an advanced-control PWM timer.
The STM32F051x family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes
allows the design of low-power applications.
The STM32F051x family includes devices in four different packages ranging from 32 pins to
64 pins. Depending on the device chosen, different sets of peripherals are included. The
description below provides an overview of the complete range of peripherals proposed in
this family.
These features make the STM32F051x microcontroller family suitable for a wide range of
applications such as application control and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Doc ID 022265 Rev 3
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Description
Table 2.
STM32F051x
STM32F051x family device features and peripheral counts
Peripheral
STM32F051Kx
STM32F051Cx
STM32F051Rx
32
Flash (Kbytes)
SRAM (Kbytes)
16
32
4
64
8
16
32
4
64
8
16
64
8
4
Advanced
control
1 (16-bit)
5 (16-bit)
1 (32-bit)
Timers
General
purpose
Basic
1 (16-bit)
SPI [I2S](1)
I2C
1[1] (2)
1(3)
2
1[1] (2)
2[1]
2
1[1] (2)
1(3)
2[1]
2
1(3)
Comm.
interfaces
USART
CEC
1(4)
1(4)
2
1(4)
2
1
12-bit synchronized
ADC
(number of channels)
1
1
(10 ext. + 3 int.)
(16 ext. + 3 int.)
25 (on LQFP32)
GPIOs
39
17
55
18
27 (on UFQFPN32)
13 (on LQFP32)
Capacitive sensing
channels
14 (on UFQFPN32)
12-bit DAC
1
(number of channels)
(1)
Analog comparator
Max. CPU frequency
Operating voltage
2
48 MHz
2.0 to 3.6 V
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: -40 °C to 125 °C
Operating temperature
Packages
LQFP32
LQFP48
LQFP64
UFQFPN32
1. The SPI1 interface can be used either in SPI mode or in I2S audio mode.
2. SPI2 is not present
3. I2C2 is not present
4. USART2 is not present
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Doc ID 022265 Rev 3
STM32F051x
Description
Figure 1.
Block diagram
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Functional overview
STM32F051x
3
Functional overview
3.1
ARM® CortexTM-M0 core with embedded Flash and SRAM
The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F051x family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2
Memories
The device has the following features:
●
Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0
wait states and featuring embedded parity checking with exception generation for fail-
critical applications.
●
The non-volatile memory is divided into two arrays:
–
–
16 to 64 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
–
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
3.3
Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
●
●
●
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
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STM32F051x
Functional overview
3.4
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes
●
V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V pins.
DD
●
V
= 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL
DDA
(minimum voltage to be applied to V
is 2.4 V when the ADC and DAC are used).
DDA
The V
voltage level must be always greater or equal to the V voltage level and
DDA
DD
must be provided first.
●
V
BAT
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V is not present.
DD
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.
3.5.2
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
, without the need for an external reset circuit.
POR/PDR
●
The POR monitors only the V supply voltage. During the startup phase it is required
DD
that V
should arrive first and be greater than or equal to V
.
DDA
DD
●
The PDR monitors both the V and V
supply voltages, however the V
power
DDA
DD
DDA
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V is higher than or
DDA
equal to V
.
DD
The device features an embedded programmable voltage detector (PVD) that monitors the
power supply and compares it to the V threshold. An interrupt can be generated
V
DD
PVD
when V drops below the V
threshold and/or when V is higher than the V
DD
PVD
DD PVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
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Functional overview
STM32F051x
3.5.3
Voltage regulator
The regulator has three operating modes: main (MR), low power (LPR) and power down.
●
●
●
MR is used in normal operating mode (Run)
LPR can be used in Stop mode where the power demand is reduced
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
3.5.4
Low-power modes
The STM32F051x family supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC alarm, COMPx, I2C1,
USART1 or the CEC.
The I2C1, USART1 and the CEC can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used, the voltage regulator should not be put in the
low-power mode but kept in normal mode.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pins, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
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STM32F051x
Functional overview
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Figure 2.
Clock tree
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3.7
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
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Functional overview
STM32F051x
The I/O configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.
3.8
Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14), DAC and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F051x family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4
priority levels.
●
●
●
●
●
●
●
●
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2
Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 55
GPIOs can be connected to the 16 external interrupt lines.
3.10
Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature
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Functional overview
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
that varies linearly with
SENSE
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3.
Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3.3 V
TS_CAL1
TS_CAL2
0x1FFF F7B8 - 0x1FFF F7B9
TS ADC raw data acquired at
temperature of 110 °C
0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V
3.10.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC and Comparators. V
is internally connected to the ADC_IN17 input channel. The
REFINT
precise voltage of V
is individually measured for each part by ST during production
REFINT
test and stored in the system memory area. It is accessible in read-only mode.
Table 4.
Temperature sensor calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 30 °C
VREFINT_CAL
0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V
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Functional overview
STM32F051x
3.10.3
V
battery voltage monitoring
BAT
This embedded hardware feature allows the application to measure the V
battery voltage
BAT
using the internal ADC channel ADC_IN18. As the V
voltage may be higher than V
,
BAT
DDA
and thus outside the ADC input range, the V
pin is internally connected to a bridge
BAT
divider by 2. As a consequence, the converted digital value is half the V
voltage.
BAT
3.11
Digital-to-analog converter (DAC)
The 12-bit buffered DAC channel can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in non-inverting configuration.
This digital Interface supports the following features:
●
●
●
●
Left or right data alignment in 12-bit mode
Synchronized update capability
DMA capability
External triggers for conversion
Five DAC trigger inputs are used in the device. The DAC is triggered through the timer
trigger outputs and the DAC interface is generating it’s own DMA requests.
3.12
Comparators (COMP)
The device embeds two fast rail-to-rail low-power comparators with programmable reference
voltage (internal or external), hysteresis and speed (low speed for low power) and with
selectable output polarity.
The reference voltage can be one of the following:
●
●
●
External I/O
DAC output pin
Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 24: Embedded
internal reference voltage for the value and precision of the internal reference voltage.
Both comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined into a window comparator.
The internal voltage reference is also connected to ADC_IN17 input channel of the ADC.
3.13
Touch sensing controller (TSC)
The STM32F051x devices provide a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect the presence
of a finger near an electrode which is protected from direct touch by a dielectric (glass,
plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle. It consists of charging the electrode capacitance and then transferring a part of the
accumulated charges into a sampling capacitor until the voltage across this capacitor has
reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly
managed by the hardware touch sensing controller and only requires few external
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Functional overview
components to operate. The STM32F051x devices offer up to 18 capacitive sensing
channels distributed over 6 analog I/O groups.
Table 5.
Group
Capacitive sensing GPIOs available on STM32F051x devices
Capacitive sensing
signal name
Pin
name
Capacitive sensing
signal name
Pin
name
Group
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC5
PB0
PB1
PB2
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
PA9
PA10
PA11
PA12
PB3
1
2
3
4
PB4
5
6
PB6
PB7
PB11
PB12
PB13
PB14
Table 6.
No. of capacitive sensing channels available on STM32F051x devices
Number of capacitive sensing channels
Analog I/O group
STM32F051Kx
(UFQFPN32)
STM32F051Kx
STM32F051Rx
STM32F051Cx
(LQFP32)
G1
G2
G3
G4
G5
G6
3
3
3
3
3
3
3
3
2
3
3
3
3
3
2
3
3
0
3
3
1
3
3
0
Number of capacitive
sensing channels
18
17
14
14
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Functional overview
STM32F051x
3.14
Timers and watchdogs
The STM32F051x family devices include up to six general-purpose timers, one basic timer
and an advanced control timer.
Table 7 compares the features of the advanced-control, general-purpose and basic timers.
Table 7.
Timer feature comparison
Timer
type
Counter
resolution
Counter
type
Prescaler DMA request Capture/compare Complementary
Timer
factor
generation
channels
outputs
Any integer
between 1
and 65536
Advanced
control
Up,down,
up/down
TIM1
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Yes
4
Yes
Any integer
between 1
and 65536
Up,down,
up/down
TIM2
TIM3
Yes
Yes
No
4
4
1
2
1
0
No
No
No
Yes
Yes
No
Any integer
between 1
and 65536
Up,down,
up/down
Any integer
between 1
and 65536
General
purpose
TIM14
TIM15
Up
Up
Up
Up
Any integer
between 1
and 65536
Yes
Yes
Yes
Any integer
between 1
and 65536
TIM16,
TIM17
Any integer
between 1
and 65536
Basic
TIM6
3.14.1
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
●
●
●
●
Input capture
Output compare
PWM generation (edge or center-aligned modes)
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
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Functional overview
3.14.2
General-purpose timers (TIM2..3, TIM14..17)
There are six synchronizable general-purpose timers embedded in the STM32F051x
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F051x devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with
TIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
3.14.3
3.14.4
Basic timer TIM6
This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit
time base.
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-
defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
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Functional overview
STM32F051x
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.14.5
3.14.6
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
●
●
●
●
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source (HCLK or HCLK/8)
3.15
Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power either
on V supply when present or through the V
pin. The backup registers are five 32-bit
DD
BAT
registers used to store 20 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
●
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
●
●
●
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.
Programmable alarm with wake up from Stop and Standby mode capability.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
●
●
●
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
●
●
●
●
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 40 kHz)
The high-speed external clock divided by 32.
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Functional overview
3.16
Inter-integrated circuit interfaces (I2C)
2
Up to two I C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s) and I2C1
supports also Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2
addresses, 1 with configurable mask). They also include programmable analog and digital
noise filters.
Table 8.
Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
≥ 50 ns
1. Extra filtering capability vs.
standard requirements.
Benefits
Available in Stop mode
2. Stable length
Variations depending on
temperature, voltage, process
Disabled when Wakeup from Stop
mode is enabled
Drawbacks
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 9 for the differences between I2C1 and I2C2.
2
Table 9.
STM32F051x I C implementation
I2C features(1)
I2C1
I2C2
X
X
X
X
X
X
X
X
X
X
X
X
7-bit addressing mode
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Independent clock
SMBus
Wakeup from STOP
1. X = supported.
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Functional overview
STM32F051x
3.17
Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds up to two universal synchronous/asynchronous receiver transmitters
(USART1 and USART2), which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. The USART1 supports also SmartCard communication
(ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has a
clock domain independent from the CPU clock, allowing the USART1 to wake up the MCU
from Stop mode.
The USART interfaces can be served by the DMA controller.
Refer to Table 10 for the differences between USART1 and USART2.
Table 10. STM32F051x USART implementation
USART modes/features(1)
USART1
USART2
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
X
1. X = supported.
3.18
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
2
One standard I S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at simplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit
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Functional overview
programmable linear prescaler. When operating in master mode it can output a clock for an
external audio component at 256 times the sampling frequency.
Refer to Table 11 for the differences between SPI1 and SPI2.
Table 11. STM32F051x SPI/I2S implementation
SPI features(1)
SPI1
SPI2
Hardware CRC calculation
X
X
X
X
X
X
X
X
Rx/Tx FIFO
NSS pulse mode
I2S mode
TI mode
X
1. X = supported.
3.19
3.20
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
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Pinouts and pin description
STM32F051x
4
Pinouts and pin description
Figure 3.
LQFP64 64-pin package pinout
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26/105
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STM32F051x
Figure 4.
Pinouts and pin description
LQFP48 48-pin package pinout
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0!ꢎ
633!
0"ꢀꢁ
0"ꢀꢋ
0"ꢀꢉ
0"ꢀꢅ
6$$!
0!ꢃ
0!ꢀ ꢀꢀ
ꢀꢅ
0!ꢅ
ꢅꢋ
ꢀꢉ ꢀꢋ ꢀꢁ ꢀꢇ ꢀꢑ ꢀꢎ ꢀꢓ ꢅꢃ ꢅꢀ ꢅꢅ ꢅꢉ
-3ꢀꢓꢎꢋꢅ6ꢀ
Figure 5.
LQFP32 32-pin package pinout
ꢉꢅ ꢉꢀ ꢉꢃ ꢅꢓ ꢅꢎ ꢅꢑ ꢅꢇ ꢅꢁ
ꢅꢋ
ꢅꢉ
ꢅꢅ
ꢀ
ꢅ
ꢉ
ꢋ
ꢁ
ꢇ
ꢑ
ꢎ
0!ꢀꢋ
0!ꢀꢉ
0!ꢀꢅ
0!ꢀꢀ
0!ꢀꢃ
0!ꢓ
6$$
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.234
6$$!
0!ꢃ
ꢅꢀ
ꢅꢃ
,1&0ꢉꢅ
ꢀꢓ
ꢀꢎ
ꢀꢑ
0!ꢎ
0!ꢀ
6$$
0!ꢅ
ꢓ ꢀꢃ ꢀꢀ ꢀꢅ ꢀꢉ ꢀꢋ ꢀꢁ ꢀꢇ
-3ꢉꢃꢋꢑꢁ6ꢀ
Doc ID 022265 Rev 3
27/105
Pinouts and pin description
Figure 6. UFQFPN32 32-pin package pinout
STM32F051x
ꢉꢅ ꢉꢀ ꢉꢃ ꢅꢓ ꢅꢎ ꢅꢑ ꢅꢇ ꢅꢁ
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ꢅ
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0!ꢀꢅ
0!ꢀꢀ
0!ꢀꢃ
0!ꢓ
ꢃ
ꢅꢉ
ꢅꢅ
ꢅꢀ
633
633!
ꢋ
6$$!
0!ꢃ
0!ꢀ
0!ꢅ
ꢁ
ꢇ
ꢑ
ꢎ
ꢅꢃ
ꢀꢓ
ꢀꢎ
ꢀꢑ
0!ꢎ
6$$
ꢓ
ꢀꢃ ꢀꢀ ꢀꢅ ꢀꢉ ꢀꢋ ꢀꢁ ꢀꢇ
-3ꢀꢓꢎꢋꢋ6ꢅ
Table 12. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
FTf
TTa
TC
B
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
3.3 V tolerant I/O directly connected to ADC
Standard 3.3V I/O
I/O structure
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
28/105
Doc ID 022265 Rev 3
STM32F051x
Pinouts and pin description
Pin functions
Table 13. Pin definitions
Pin number
Pin name
(function after
reset)
Notes
Alternate functions
Additional functions
1
2
1
2
-
-
-
-
VBAT
PC13
S
Backup power supply
RTC_TAMP1,
RTC_TS, RTC_OUT,
WKUP2
(1)(2)
(1)(2)
(1)(2)
I/O TC
PC14-OSC32_IN
(PC14)
3
4
3
4
-
-
-
-
I/O TC
I/O TC
OSC32_IN
OSC32_OUT
OSC_IN
PC15-
OSC32_OUT
(PC15)
PF0-OSC_IN
(PF0)
5
6
5
6
2
3
2
3
I/O
I/O
FT
FT
PF1-OSC_OUT
(PF1)
OSC_OUT
7
7
-
4
-
4
-
NRST
PC0
I/O RST
I/O TTa
I/O TTa
I/O TTa
I/O TTa
S
Device reset input / internal reset output (active low)
8
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
ADC_IN10
ADC_IN11
ADC_IN12
ADC_IN13
9
-
-
-
PC1
10
11
12
13
-
-
-
PC2
-
-
-
PC3
8
9
-
0
5
VSSA
VDDA
Analog ground
Analog power supply
5
S
USART2_CTS,
ADC_IN0,
COMP1_INM6,
RTC_TAMP2,
WKUP1
TIM2_CH1_ETR,
COMP1_OUT,
TSC_G1_IO1
14 10
15 11
16 12
17 13
6
7
8
9
6
7
8
9
PA0
PA1
PA2
PA3
I/O TTa
I/O TTa
I/O TTa
I/O TTa
USART2_RTS, TIM2_CH2,
TSC_G1_IO2, EVENTOUT
ADC_IN1,
COMP1_INP
USART2_TX, TIM2_CH3,
TIM15_CH1,
ADC_IN2,
COMP2_INM6
COMP2_OUT,
TSC_G1_IO3
USART2_RX, TIM2_CH4,
TIM15_CH2, TSC_G1_IO4
ADC_IN3,
COMP2_INP
18
19
-
-
-
-
-
-
PF4
PF5
I/O
I/O
FT
FT
EVENTOUT
EVENTOUT
Doc ID 022265 Rev 3
29/105
Pinouts and pin description
STM32F051x
Table 13. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function after
reset)
Notes
Alternate functions
Additional functions
ADC_IN4,
COMP1_INM4,
COMP2_INM4,
DAC1_OUT
SPI1_NSS/I2S1_WS,
USART2_CK, TIM14_CH1,
TSC_G2_IO1
20 14 10 10
21 15 11 11
PA4
PA5
I/O TTa
I/O TTa
SPI1_SCK/I2S1_CK, CEC,
TIM2_CH1_ETR,
ADC_IN5,
COMP1_INM5,
COMP2_INM5
TSC_G2_IO2
SPI1_MISO/I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
TIM16_CH1,
COMP1_OUT,
TSC_G2_IO3, EVENTOUT
22 16 12 12
PA6
PA7
I/O TTa
I/O TTa
ADC_IN6
ADC_IN7
SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM14_CH1,
TIM1_CH1N, TIM17_CH1,
COMP2_OUT,
23 17 13 13
TSC_G2_IO4, EVENTOUT
24
25
-
-
-
-
-
-
PC4
PC5
I/O TTa
I/O TTa
EVENTOUT
ADC_IN14
ADC_IN15
TSC_G3_IO1
TIM3_CH3, TIM1_CH2N,
TSC_G3_IO2, EVENTOUT
26 18 14 14
27 19 15 15
PB0
I/O TTa
I/O TTa
ADC_IN8
ADC_IN9
TIM3_CH4, TIM14_CH1,
TIM1_CH3N, TSC_G3_IO3
PB1
PB2
(3)
28 20
29 21
-
-
16
-
I/O
I/O
FT
FT
TSC_G3_IO4
I2C2_SCL, CEC,
TIM2_CH3, TSC_SYNC
PB10
I2C2_SDA, TIM2_CH4,
TSC_G6_IO1, EVENTOUT
30 22
-
-
PB11
I/O
FT
31 23 16
0
VSS
VDD
S
S
Ground
Digital power supply
SPI2_NSS, TIM1_BKIN,
32 24 17 17
33 25
34 26
35 27
36 28
-
-
-
-
-
-
PB12
PB13
PB14
I/O
I/O
I/O
FT
FT
FT
TSC_G6_IO2, EVENTOUT
SPI2_SCK, TIM1_CH1N,
TSC_G6_IO3
SPI2_MISO, TIM1_CH2N,
TIM15_CH1, TSC_G6_IO4
SPI2_MOSI, TIM1_CH3N,
TIM15_CH1N, TIM15_CH2
-
-
-
-
PB15
PC6
I/O
I/O
FT
FT
RTC_REFIN
37
-
TIM3_CH1
30/105
Doc ID 022265 Rev 3
STM32F051x
Pinouts and pin description
Pin functions
Table 13. Pin definitions (continued)
Pin number
Pin name
(function after
reset)
Notes
Alternate functions
Additional functions
38
39
40
-
-
-
-
-
-
-
-
-
PC7
PC8
PC9
I/O
I/O
I/O
FT
FT
FT
TIM3_CH2
TIM3_CH3
TIM3_CH4
USART1_CK, TIM1_CH1,
EVENTOUT, MCO
41 29 18 18
42 30 19 19
PA8
PA9
I/O
I/O
FT
FT
USART1_TX, TIM1_CH2,
TIM15_BKIN,
TSC_G4_IO1
USART1_RX, TIM1_CH3,
TIM17_BKIN,
43 31 20 20
44 32 21 21
PA10
PA11
PA12
I/O
I/O
FT
FT
TSC_G4_IO2
USART1_CTS, TIM1_CH4,
COMP1_OUT,
TSC_G4_IO3, EVENTOUT
USART1_RTS, TIM1_ETR,
COMP2_OUT,
TSC_G4_IO4, EVENTOUT
45 33 22 22
46 34 23 23
I/O
I/O
FT
FT
PA13
(4)
IR_OUT, SWDAT
(SWDAT)
47 35
48 36
-
-
-
-
PF6
PF7
I/O
I/O
FT
FT
I2C2_SCL
I2C2_SDA
PA14
(4)
49 37 24 24
I/O
FT
USART2_TX, SWCLK
(SWCLK)
SPI1_NSS/I2S1_WS,
USART2_RX,
TIM2_CH1_ETR,
EVENTOUT
50 38 25 25
PA15
I/O
FT
51
52
53
54
-
-
-
-
-
-
-
-
-
-
-
-
PC10
PC11
PC12
PD2
I/O
I/O
I/O
I/O
FT
FT
FT
FT
TIM3_ETR
SPI1_SCK/I2S1_CK,
TIM2_CH2, TSC_G5_IO1,
EVENTOUT
55 39 26 26
56 40 27 27
PB3
PB4
I/O
I/O
FT
FT
SPI1_MISO/I2S1_MCK,
TIM3_CH1, TSC_G5_IO2,
EVENTOUT
Doc ID 022265 Rev 3
31/105
Pinouts and pin description
STM32F051x
Table 13. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function after
reset)
Notes
Alternate functions
Additional functions
SPI1_MOSI/I2S1_SD,
I2C1_SMBA, TIM16_BKIN,
TIM3_CH2
57 41 28 28
58 42 29 29
PB5
PB6
PB7
I/O
FT
I2C1_SCL, USART1_TX,
TIM16_CH1N,
I/O FTf
I/O FTf
TSC_G5_IO3
I2C1_SDA, USART1_RX,
TIM17_CH1N,
59 43 30 30
60 44 31 31
TSC_G5_IO4
BOOT0
PB8
I
B
Boot memory selection
I2C1_SCL, CEC,
TIM16_CH1, TSC_SYNC
(3)
61 45
62 46
-
-
32
-
I/O FTf
I/O FTf
I2C1_SDA, IR_OUT,
TIM17_CH1, EVENTOUT
PB9
63 47 32
64 48
0
1
VSS
VDD
S
S
Ground
Digital power supply
1
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as a current sources (e.g. to drive an LED).
2. After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the reference manual.
3. On LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not available on the
package, they are not forced to a defined level by hardware).
4. After reset, these pins are configured as SWDAT and SWCLK alternate functions, and the internal pull-up on SWDAT pin
and internal pull-down on SWCLK pin are activated.
32/105
Doc ID 022265 Rev 3
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
TIM2_CH1_
ETR
PA0
USART2_CTS
TSC_G1_IO1
COMP1_OUT
PA1
PA2
PA3
EVENTOUT
TIM15_CH1
TIM15_CH2
USART2_RTS
USART2_TX
USART2_RX
TIM2_CH2
TIM2_CH3
TIM2_CH4
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
COMP2_OUT
SPI1_NSS/
I2S1_WS
PA4
PA5
PA6
PA7
USART2_CK
CEC
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TIM14_CH1
TIM14_CH1
SPI1_SCK/
I2S1_CK
TIM2_CH1_
ETR
SPI1_MISO/
I2S1_MCK
TIM3_CH1
TIM3_CH2
TIM1_BKIN
TIM1_CH1N
TIM16_CH1
TIM17_CH1
EVENTOUT
EVENTOUT
COMP1_OUT
COMP2_OUT
SPI1_MOSI/
I2S1_SD
PA8
PA9
MCO
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
USART1_RTS
IR_OUT
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
EVENTOUT
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
TIM15_BKIN
TIM17_BKIN
EVENTOUT
EVENTOUT
SWDAT
PA10
PA11
PA12
PA13
PA14
COMP1_OUT
COMP2_OUT
SWCLK
USART2_TX
SPI1_NSS/
I2S1_WS
TIM2_CH1_
ETR
PA15
USART2_RX
EVENTOUT
Table 15. Alternate functions selected through GPIOA_AFR registers for port B
Pin name
AF0
AF1
AF2
AF3
PB0
PB1
EVENTOUT
TIM14_CH1
TIM3_CH3
TIM3_CH4
TIM1_CH2N
TIM1_CH3N
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G5_IO1
TSC_G5_IO2
I2C1_SMBA
TSC_G5_IO3
TSC_G5_IO4
TSC_SYNC
PB2
PB3
SPI1_SCK / I2S1_CK
SPI1_MISO / I2S1_MCK
SPI1_MOSI / I2S1_SD
USART1_TX
USART1_RX
CEC
EVENTOUT
TIM3_CH1
TIM3_CH2
I2C1_SCL
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
EVENTOUT
TIM2_CH2
EVENTOUT
TIM16_BKIN
TIM16_CH1N
TIM17_CH1N
TIM16_CH1
TIM17_CH1
TIM2_CH3
PB4
PB5
PB6
PB7
PB8
PB9
IR_OUT
EVENTOUT
TSC_SYNC
PB10
PB11
PB12
PB13
PB14
PB15
CEC
EVENTOUT
SPI2_NSS
TIM2_CH4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TIM15_CH1N
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
SPI2_SCK
SPI2_MISO
TIM15_CH1
TIM15_CH2
SPI2_MOSI
STM32F051x
Memory mapping
5
Memory mapping
Figure 7.
STM32F051x memory map
ꢃX&&&& &&&&
ꢃXꢋꢎꢃꢃ ꢀꢑ&&
!("ꢅ
ꢑ
ꢃXꢋꢎꢃꢃ ꢃꢃꢃꢃ
ꢃX%ꢃꢀꢃ ꢃꢃꢃꢃ
#ORTEXꢆ -ꢀ )NTERNAL
0ERIPHERALS
ꢃX%ꢃꢃꢃ ꢃꢃꢃꢃ
RESERVED
ꢇ
ꢃX#ꢃꢃꢃ ꢃꢃꢃꢃ
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ꢃXꢋꢃꢃꢅ ꢃꢃꢃꢃ
")#ꢄ
ꢁ
RESERVED
ꢃX!ꢃꢃꢃ ꢃꢃꢃꢃ
ꢃXꢋꢃꢃꢀ ꢎꢃꢃꢃ
ꢃXꢋꢃꢃꢀ ꢃꢃꢃꢃ
"1#
ꢋ
ꢃXꢀ&&& &&&&
ꢃXꢀ&&& &#ꢃꢃ
RESERVED
/PTION "YTES
ꢃXꢀ&&& &ꢎꢃꢃ
ꢃXꢎꢃꢃꢃ ꢃꢃꢃꢃ
RESERVED
3YSTEM MEMORY
ꢃXꢋꢃꢃꢃ ꢎꢃꢃꢃ
ꢃXꢋꢃꢃꢃ ꢃꢃꢃꢃ
ꢉ
ꢃXꢀ&&& %#ꢃꢃ
"1#
ꢃXꢇꢃꢃꢃ ꢃꢃꢃꢃ
RESERVED
ꢅ
0ERIPHERALS
ꢃXꢋꢃꢃꢃ ꢃꢃꢃꢃ
ꢃXꢃꢎꢃꢀ ꢃꢃꢃꢃ
ꢀ
&LASH MEMORY
RESERVED
32!-
ꢃXꢅꢃꢃꢃ ꢃꢃꢃꢃ
ꢀYꢀꢃꢀꢀꢂꢀꢀꢀꢀ
#/$%
ꢃ
ꢃXꢃꢃꢃꢀ ꢃꢃꢃꢃ
'MBTIꢁꢂTZTUFNꢂNFNPSZ
PSꢂ43".ꢁꢂEFQFOEJOHꢂPO
#005ꢂDPOGJHVSBUJPO
ꢃXꢃꢃꢃꢃ ꢃꢃꢃꢃ
ꢃXꢃꢃꢃꢃ ꢃꢃꢃꢃ
2ESERVED
-3ꢀꢓꢎꢋꢃ6ꢀ
Doc ID 022265 Rev 3
35/105
Memory mapping
STM32F051x
Table 16. STM32F051x peripheral register boundary addresses
Bus
Boundary address
Size
Peripheral
0x4800 1800 - 0x5FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
0x4001 5C00 - 0x4001 7FFF
0x4001 5800 - 0x4001 5BFF
0x4001 4C00 - 0x4001 57FF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0x4001 0800 - 0x4001 23FF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 8000 - 0x4000 FFFF
~384 MB Reserved
1KB
1KB
1KB
1KB
1KB
1KB
GPIOF
Reserved
GPIOD
GPIOC
GPIOB
GPIOA
AHB2
~128 MB Reserved
1KB
3KB
1KB
3KB
1KB
3KB
1KB
3KB
1KB
32KB
9KB
1KB
3KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
7KB
1KB
1KB
32KB
TSC
Reserved
CRC
Reserved
AHB1
FLASH Interface
Reserved
RCC
Reserved
DMA
Reserved
Reserved
DBGMCU
Reserved
TIM17
TIM16
TIM15
Reserved
USART1
Reserved
SPI1/I2S1
TIM1
APB
Reserved
ADC
Reserved
EXTI
SYSCFG + COMP
Reserved
36/105
Doc ID 022265 Rev 3
STM32F051x
Memory mapping
Table 16. STM32F051x peripheral register boundary addresses (continued)
Bus
Boundary address
Size
1KB
Peripheral
Reserved
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 5C00 - 0x4000 6FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 4800 - 0x4000 53FF
0x4000 4400 - 0x4000 47FF
0x4000 3C00 - 0x4000 43FF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1400 - 0x4000 1FFF
0x4000 1000 - 0x4000 13FF
0x4000 0800 - 0x4000 0FFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
1KB
1KB
1KB
5KB
1KB
1KB
3 KB
1KB
2KB
1KB
1KB
1KB
1KB
1KB
1KB
1KB
3KB
1KB
2KB
1KB
1KB
CEC
DAC
PWR
Reserved
I2C2
I2C1
Reserved
USART2
Reserved
SPI2
APB
Reserved
IWDG
WWDG
RTC
Reserved
TIM14
Reserved
TIM6
Reserved
TIM3
TIM2
Doc ID 022265 Rev 3
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STM32F051x
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3.3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2Σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8.
Pin loading conditions
Figure 9.
Pin input voltage
-#5 PIN
-#5 PIN
C = 50 pF
6
).
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Doc ID 022265 Rev 3
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Electrical characteristics
STM32F051x
6.1.6
Power supply scheme
Figure 10. Power supply scheme
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Caution:
Each power supply pair (V /V , V
/V
etc..) must be decoupled with filtering
DD SS
DDA SSA
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
6.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
*
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40/105
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STM32F051x
Electrical characteristics
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics,
Table 18: Current characteristics, and Table 19: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
(1)
Table 17. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage
VDD–VSS
–0.3
4.0
V
(including VDDA and VDD
)
Allowed voltage difference for VDD
> VDDA
VDD–VDDA
-
0.4
V
Input voltage on FT and FTf pins
Input voltage on TTa pins
VSS − 0.3
VSS − 0.3
VSS − 0.3
VDD + 4.0
4.0
V
V
V
(2)
VIN
Input voltage on any other pin
4.0
Variations between different VDD
power pins
|ΔVDDx
|
-
-
50
50
mV
mV
Variations between all the different
ground pins
|VSSX − VSS
|
Electrostatic discharge voltage
(human body model)
see Section 6.3.11: Electrical
sensitivity characteristics
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 18: Current characteristics for the maximum
allowed injected current values.
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Electrical characteristics
STM32F051x
Unit
Table 18. Current characteristics
Symbol
Ratings
Max.
IVDD
IVSS
Total current into VDD power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on FT, FTf and B pins
Injected current on TC and RST pin
100
100
25
IIO
− 25
-5(2)
5(3)
5(4)
mA
IINJ(PIN)
Injected current on TTa pins
Total injected current (sum of all I/O and control
pins)(5)
ΣIINJ(PIN)
25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
3. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN <VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 17: Voltage characteristics for the maximum allowed input voltage
values.
4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 17: Voltage characteristics for the maximum allowed input voltage
values. Negative injection disturbs the analog performance of the device. See note 2 below Table 56 on
page 78.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 19. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
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STM32F051x
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 20. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK
VDD
Internal AHB clock frequency
Internal APB clock frequency
Standard operating voltage
0
0
2
48
48
MHz
V
3.6
Analog operating voltage
(ADC and DAC not used)
2
3.6
3.6
Must have a potential equal
to or higher than VDD
(1)
VDDA
V
V
Analog operating voltage
(ADC and DAC used)
2.4
VBAT
Backup operating voltage
1.65
3.6
444
364
357
526
85
LQFP64
LQFP48
LQFP32
-
-
-
-
Power dissipation at TA =
85 °C for suffix 6 or TA =
105 °C for suffix 7(2)
PD
mW
UFQFPN32
Maximum power dissipation –40
Low power dissipation(3)
–40
Maximum power dissipation –40
Ambient temperature for 6
suffix version
°C
°C
°C
105
105
125
105
125
TA
TJ
Ambient temperature for 7
suffix version
Low power dissipation(3)
–40
–40
–40
6 suffix version
Junction temperature range
7 suffix version
1. When the ADC is used, refer to Table 54: ADC characteristics.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 19: Thermal
characteristics).
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 19: Thermal characteristics).
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Electrical characteristics
STM32F051x
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 21 are derived from tests performed under the ambient
temperature condition summarized in Table 20.
Table 21. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
0
Max
∞
Unit
VDD rise time rate
tVDD
V
DD fall time rate
20
0
∞
µs/V
VDDA rise time rate
VDDA fall time rate
∞
tVDDA
20
∞
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 20.
DD
Table 22. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
1.8(2)
Falling edge
Rising edge
1.88 1.96
V
V
Power on/power down
reset threshold
(1)
VPOR/PDR
1.84 1.92 2.0
(1)
VPDRhyst
PDR hysteresis
-
40
-
mV
ms
(3)
tRSTTEMPO
Reset temporization
1.5
2.5
4.5
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD
.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production.
Table 23. Programmable voltage detector characteristics
Symbol
Parameter
Conditions
Min(1)
Typ Max(1) Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.1
2
2.18
2.08
2.28
2.18
2.38
2.28
2.48
2.38
2.58
2.48
2.26
2.16
2.37
2.27
2.48
2.38
2.58
2.48
2.69
2.59
V
V
V
V
V
V
V
V
V
V
VPVD0
PVD threshold 0
2.19
2.09
2.28
2.18
2.38
2.28
2.47
2.37
VPVD1
VPVD2
VPVD3
VPVD4
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
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Electrical characteristics
Table 23. Programmable voltage detector characteristics (continued)
Symbol
Parameter
PVD threshold 5
Conditions
Min(1)
Typ Max(1) Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.57
2.47
2.66
2.56
2.76
2.66
-
2.68
2.58
2.78
2.68
2.88
2.78
100
2.79
2.69
2.9
2.8
3
V
V
VPVD5
V
VPVD6
PVD threshold 6
PVD threshold 7
V
V
VPVD7
2.9
-
V
(2)
VPVDhyst
IDD(PVD)
PVD hysteresis
mV
µA
PVD current consumption
-
0.15
0.26
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 24 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 20.
DD
Table 24. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C 1.16
1.2
1.2
1.25
V
V
Internal reference voltage
V
REFINT
–40 °C < TA < +85 °C
1.16
-
1.24(1)
ADC sampling time when
reading the internal
reference voltage
17.1(3)
µs
(2)
TS_vrefint
5.1
Internal reference voltage
VRERINT spread over the
temperature range
10(3)
VDD = 3 V 10 mV
-
-
-
-
mV
100(3)
TCoeff
Temperature coefficient
ppm/°C
1. Data based on characterization results, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
3. Guaranteed by design, not tested in production.
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
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Electrical characteristics
STM32F051x
Typical and maximum current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f
to 24 MHz and 1 wait state above 24 MHz)
frequency (0 wait state from 0
HCLK
●
Prefetch is ON when the peripherals are enabled, otherwise it is OFF (to enable
prefetch the PRFTBE bit in the FLASH_ACR register must be set before clock setting
and bus prescaling)
●
When the peripherals are enabled f
= f
HCLK
PCLK
The parameters given in Table 25 to Table 29 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 20.
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Electrical characteristics
Table 25. Typical and maximum current consumption from V supply at V = 3.6 V
DD
DD
All peripherals enabled
All peripherals disabled
(1)
(1)
Symbol Parameter Conditions fHCLK
Max @ TA
Max @ TA
Unit
Typ
Typ
25 °C 85 °C 105 °C
25 °C 85 °C 105 °C
48 MHz 22
32 MHz 15
22.8
15.5
22.8
15.5
13.2
5.2
23.8
16.0
13.6
5.4
11.8 12.7
12.7
8.7
13.3
9.0
8.1
3.0
HSE
bypass,
PLL on
7.6
7.2
2.7
8.7
7.9
2.9
24 MHz 12.2 13.2
7.9
Supply
current in
Run mode,
code
executing
from Flash
HSE
bypass,
PLL off
8 MHz 4.4
1 MHz
5.2
1.3
2.9
1
1.3
1.4
0.7
0.9
0.9
0.9
48 MHz 22
32 MHz 15
22.8
15.5
22.8
15.5
13.2
23.8
16.0
13.6
11.8 12.7
12.7
8.7
13.3
9.0
HSI clock,
PLL on
7.6
7.2
8.7
7.9
24 MHz 12.2 13.2
8 MHz 4.4 5.2
7.9
8.1
HSI clock,
PLL off
5.2
5.4
2.7
2.9
2.9
3.0
48 MHz 22.2 23.2(2) 23.2 24.4(2) 12.0 12.7(2) 12.7 13.3(2)
HSE
bypass,
PLL on
32 MHz 15.4 16.3
24 MHz 11.2 12.2
16.3
12.2
4.5
16.8
12.8
4.7
7.8
6.2
1.9
8.7
7.9
2.9
8.7
7.9
2.9
9.0
8.1
3.0
Supply
current in
Run mode,
code
executing
from RAM
HSE
bypass,
PLL off
8 MHz 4.0
1 MHz 0.6
4.5
0.8
0.8
0.9
0.3
0.6
0.6
0.7
IDD
mA
48 MHz 22.2 23.2
32 MHz 15.4 16.3
24 MHz 11.2 12.2
23.2
16.3
12.2
24.4
16.8
12.8
12.0 12.7
12.7
8.7
13.3
9.0
HSI clock,
PLL on
7.8
6.2
8.7
7.9
7.9
8.1
HSI clock,
PLL off
8 MHz 4.0
4.5
4.5
4.7
1.9
2.9
2.9
3.0
48 MHz 14 15.3(2) 15.3 16.0(2) 2.8 3.0(2)
3.0
2.1
1.7
0.8
3.2(2)
2.3
HSE
bypass,
PLL on
32 MHz 9.5 10.2
10.2
7.8
10.7
8.3
2.0
1.5
0.6
2.1
1.7
0.8
24 MHz 7.3
8 MHz 2.6
7.8
2.9
1.9
Supply
current in
Sleep
mode,
code
HSE
2.9
3.0
0.8
bypass,
PLL off
1 MHz 0.4
48 MHz 14
0.6
0.6
0.6
0.2
0.4
0.4
0.4
15.3
15.3
10.2
7.8
16.0
10.7
8.3
3.8
2.6
2.0
4.0
2.7
2.1
4.1
2.8
2.1
4.2
2.8
2.1
executing
from Flash
or RAM
HSI clock,
PLL on
32 MHz 9.5 10.2
24 MHz 7.3
8 MHz 2.6
7.8
2.9
HSI clock,
PLL off
2.9
3.0
0.6
0.8
0.8
0.8
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production with code executing from RAM.
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Electrical characteristics
STM32F051x
Table 26. Typical and maximum current consumption from the V
supply
DDA
V
= 2.4 V
V
= 3.6 V
DDA
DDA
Conditions
(2)
(2)
Symbol Parameter
fHCLK
Unit
Max @ TA
25 °C 85 °C 105 °C
Max @ TA
25 °C 85 °C 105 °C
(1)
Typ
Typ
48 MHz 150
32 MHz 104
24 MHz 82
170
121
96
178
126
100
3.1
182
128
103
3.3
164
113
88
183
129
102
3.8
195
135
106
4.1
198
138
108
4.4
HSE
bypass,
PLL on
Supply
current in
Run mode,
code
HSE
bypass,
PLL off
8 MHz
1 MHz
2.0
2.0
2.7
3.5
2.7
3.1
3.3
3.5
3.8
4.1
4.4
executing
from Flash
or RAM
48 MHz 220
32 MHz 174
24 MHz 152
240
191
167
248
196
173
252
198
174
244
193
168
263
209
183
275
215
190
278
218
192
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
72
79
82
83
83.5
91
94
95
IDDA
µA
48 MHz 150
32 MHz 104
24 MHz 82
170
121
96
178
126
100
3.1
182
128
103
3.3
164
113
88
183
129
102
3.8
195
135
106
4.1
198
138
108
4.4
HSE
bypass,
PLL on
Supply
current in
Sleep
mode,
code
HSE
bypass,
PLL off
8 MHz
1 MHz
2.0
2.0
2.7
3.5
2.7
3.1
3.3
3.5
3.8
4.1
4.4
48 MHz 220
32 MHz 174
24 MHz 152
240
191
167
248
196
173
252
198
174
244
193
168
263
209
183
275
215
190
278
218
192
executing
from Flash
or RAM
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
72
79
82
83
83.5
91
94
95
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
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STM32F051x
Table 27.
Electrical characteristics
Typical and maximum V consumption in Stop and Standby modes
DD
Typ @VDD (VDD = VDDA
)
Max(1)
Symbol Parameter
Conditions
Unit
TA = TA = TA =
25 °C 85 °C 105 °C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in run mode,
all oscillators OFF
15 15.1 15.25 15.45 15.7 16
22(2)
48
32
64(2)
45(2)
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators
OFF
3.15 3.25 3.35 3.45 3.7
0.8 0.95 1.05 1.2 1.35 1.5
0.65 0.75 0.85 0.95 1.1 1.3
4
7(2)
IDD
µA
Supply
current in
Standby
mode
LSI ON and IWDG ON
-
-
-
LSI OFF and IWDG
OFF
2(2)
2.5
3(2)
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production.
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Electrical characteristics
STM32F051x
Table 28.
Typical and maximum V
consumption in Stop and Standby modes
DDA
Typ @VDD (VDD = VDDA
)
Max(1)
Symbol Parameter
Conditions
Unit
TA = TA = TA =
25 °C 85 °C 105 °C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in run mode,
all oscillators OFF
1.85
1.85
2
2
2.15 2.3 2.45 2.6
2.15 2.3 2.45 2.6
3.5
3.5
3.5
3.5
4.5
4.5
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators
OFF
Supply
LSI ON and IWDG ON 2.25 2.5 2.65 2.85 3.05 3.3
-
-
-
current in
Standby
mode
LSI OFF and IWDG
OFF
1.75 1.9
2
2.15 2.3 2.5
3.5
3.5
4.5
IDDA
µA
Regulator in run mode,
all oscillators OFF
1.11 1.15 1.18 1.22 1.27 1.35
1.11 1.15 1.18 1.22 1.27 1.35
-
-
-
-
-
-
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators
OFF
Supply
current in
Standby
mode
LSI ON and IWDG ON 1.5 1.58 1.65 1.78 1.91 2.04
-
-
-
-
-
-
LSI OFF and IWDG
1
1.02 1.05 1.05 1.15 1.22
OFF
1. Data based on characterization results, not tested in production.
Table 29. Typical and maximum current consumption from V
Typ @ VBAT
supply
BAT
Max(1)
TA =
Symbol Parameter
Conditions
Unit
TA =
TA =
25 °C 85 °C 105 °C
LSE & RTC ON; "Xtal
mode": lower driving
capability;
0.41 0.43 0.53 0.58 0.71 0.80 0.85
0.71 0.75 0.85 0.91 1.06 1.16 1.25
1.1
1.5
2
Backup
domain
supply
current
LSEDRV[1:0] = '00'
IDD
_
µA
VBAT
LSE & RTC ON; "Xtal
mode" higher driving
capability;
1.55
LSEDRV[1:0] = '11'
1. Data based on characterization results, not tested in production.
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Electrical characteristics
Typical current consumption
The MCU is placed under the following conditions:
●
●
●
V
=V
=3.3 V
DDA
DD
All I/O pins are in analog input configuration
The Flash access time is adjusted to f
1 wait state above)
frequency (0 wait states from 0 to 24 MHz,
HCLK
●
●
●
●
Prefetch is ON when the peripherals are enabled, otherwise it is OFF
When the peripherals are enabled, f = f
PCLK
HCLK
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
●
A development tool is connected to the board and the parasitic pull-up current is around
30 µA
Table 30. Typical current consumption in Run mode, code with data processing
running from Flash
Typ
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals
enabled
Peripherals
disabled
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
23.3
17.6
15.9
12.4
8.5
11.5
9.0
8.0
7.5
Supply current in Run
mode from VDD
supply
5.2
IDD
mA
4.5
3.0
4 MHz
2.8
1.9
2 MHz
1.7
1.3
Running from
HSE crystal
clock 8 MHz,
code
executing
from Flash
1 MHz
1.3
1.0
500 kHz
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
1.0
0.9
158
120
108
83
158
120
108
83
Supply current in Run
mode from VDDA
supply
60
60
IDDA
µA
2.43
2.43
2.43
2.43
2.43
2.43
2.43
2.43
2.43
2.43
4 MHz
2 MHz
1 MHz
500 kHz
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Electrical characteristics
STM32F051x
Table 31. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals Peripherals
enabled
disabled
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
13.9
10.55
9.6
2.98
2.84
2.6
7.23
5.01
2.68
1.81
1.27
1.03
0.9
2.09
1.58
0.99
0.85
0.77
0.73
0.71
0.69
157
119
107
83
Supply current in
Sleep mode from VDD
supply
IDD
mA
4 MHz
2 MHz
1 MHz
Running from
HSE crystal
clock 8 MHz,
code executing
from Flash or
RAM
500 kHz
125 kHz
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
0.78
158
119
108
83
60
60
Supply current in
Sleep mode from
VDDA supply
IDDA
2.36
2.36
2.36
2.36
2.36
2.36
2.38
2.38
2.38
2.38
2.38
2.38
µA
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
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STM32F051x
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 33: Peripheral current consumption), the I/Os used by an application also contribute to
the current consumption. When an I/O pin switches, it uses the current from the MCU supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or
external) connected to the pin:
ISW = VDD × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
+ C
S
INT
EXT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
STM32F051x
Table 32. Switching output I/O current consumption
I/O toggling
frequency (fSW
Symbol
Parameter
Conditions(1)
Typ
Unit
)
4 MHz
0.07
8 MHz
16 MHz
24 MHz
48 MHz
4 MHz
0.15
0.31
0.53
0.92
0.18
0.37
0.76
1.39
2.188
0.32
0.64
1.25
2.23
4.442
0.49
0.94
2.38
3.99
0.64
1.25
3.24
5.02
0.81
1.7
VDD = 3.3 V
C =CINT
8 MHz
VDD = 3.3 Volts
CEXT = 0 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
8 MHz
V
DD = 3.3 Volts
CEXT = 10 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
I/O current
consumption
ISW
mA
VDD = 3.3 Volts
CEXT = 22 pF
8 MHz
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDD = 3.3 Volts
CEXT = 33 pF
8 MHz
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDD = 3.3 Volts
CEXT = 47 pF
8 MHz
C = CINT + CEXT+ CS
C = Cint
16 MHz
3.67
4 MHz
8 MHz
0.66
1.43
2.45
4.97
V
DD = 2.4 Volts
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
16 MHz
24 MHz
1. CS = 7 pF (estimated value).
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STM32F051x
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 33. The MCU is placed
under the following conditions:
●
●
●
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
●
ambient operating temperature and V supply voltage conditions summarized in
DD
Table 17
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Electrical characteristics
STM32F051x
Unit
Table 33. Peripheral current consumption
Typical consumption at 25 °C
Peripheral
IDD
IDDA
ADC(1)
0.53
0.24
0.10
0.27
0.18
0.35
0.48
0.58
0.12
0.04
0.06
0.43
0.42
0.22
0.63
0.53
0.28
1.01
1.00
0.78
0.32
0.45
0.66
0.57
0.59
0.28
1.07
0.48
0.22
0.964
CEC
-
CRC
-
DAC(2)
DBGMCU
DMA
0.408
-
-
GPIOA
GPIOB
GPIOC
GPIOD
GPIOF
I2C1
-
-
-
-
-
-
I2C2
-
PWR
-
SPI1/I2S1
SPI2
-
mA
-
See note (3)
SYSCFG & COMP
TIM1
-
-
-
-
-
-
-
-
-
-
-
-
TIM2
TIM3
TIM6
TIM14
TIM15
TIM16
TIM17
TSC
USART1
USART2
WWDG
1. ADC is in ready state after setting the ADEN bit in the ADC_CR register (ADRDY bit in ADC_ISR is high).
2. DAC channel 1 enabled by setting EN1 bit in DAC_CR.
3. COMP IDDA is specified as IDD(COMP) in Table 58: Comparator characteristics
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STM32F051x
Electrical characteristics
6.3.6
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 12.
Table 34. High-speed external user clock characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fHSE_ext
1
8
32
MHz
VHSEH
VHSEL
tw(HSEH)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time
OSC_IN rise or fall time
15
-
-
-
-
tw(HSEL)
ns
tr(HSE)
tf(HSE)
20
1. Guaranteed by design, not tested in production.
Figure 12. High-speed external clock source AC timing diagram
T
7ꢌ(3%(ꢍ
6
(3%(
ꢓꢃꢔ
ꢀꢃꢔ
6
(3%,
T
T
T
T
Rꢌ(3%ꢍ
Fꢌ(3%ꢍ
7ꢌ(3%,ꢍ
4
(3%
-3ꢀꢓꢅꢀꢋ6ꢅ
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Electrical characteristics
STM32F051x
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,
the recommended clock input waveform is shown in Figure 13.
Table 35. Low-speed external user clock characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
User External clock source
frequency
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSEH)
0.7VDD
VSS
450
-
-
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level
voltage
OSC32_IN high or low time
OSC32_IN rise or fall time
tw(LSEL)
ns
tr(LSE)
tf(LSE)
50
1. Guaranteed by design, not tested in production.
Figure 13. Low-speed external clock source AC timing diagram
T
7ꢌ,3%(ꢍ
6
,3%(
ꢓꢃꢔ
ꢀꢃꢔ
6
,3%,
T
T
T
Rꢌ,3%ꢍ
Fꢌ,3%ꢍ
T
7ꢌ,3%,ꢍ
4
,3%
-3ꢀꢓꢅꢀꢁ6ꢅ
58/105
Doc ID 022265 Rev 3
STM32F051x
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 36. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 36. HSE oscillator characteristics
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency
4
-
8
32
-
MHz
RF
Feedback resistor
200
kΩ
During startup(3)
-
8.5
V
DD=3.3 V, Rm= 30Ω,
-
-
-
-
-
0.4
0.5
0.8
1
-
-
-
-
-
CL=10 pF@8 MHz
VDD=3.3 V, Rm= 45Ω,
CL=10 pF@8 MHz
IDD
HSE current consumption
mA
VDD=3.3 V, Rm= 30Ω,
CL=5 pF@32 MHz
VDD=3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz
V
DD=3.3 V, Rm= 30Ω,
1.5
CL=20 pF@32 MHz
gm
Oscillator transconductance
Startup time
Startup
10
-
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 14). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on electing the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
Figure 14. Typical application with an 8 MHz crystal
STM32F051x
2ESONATOR WITH
INTEGRATED CAPACITORS
#
,ꢀ
F
/3#?).
(3%
"IAS
CONTROLLED
GAIN
ꢎ -(Z
RESONATOR
2
&
/3#?/54
ꢌꢀꢍ
2
%84
#
,ꢅ
-3ꢀꢓꢎꢑꢇ6ꢀ
1. REXT value depends on the crystal characteristics.
60/105
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STM32F051x
Electrical characteristics
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 37. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
-
0.5
0.9
1
LSEDRV[1:0]= 01
medium low driving capability
-
-
-
-
-
-
IDD
LSE current consumption
µA
LSEDRV[1:0] = 10
medium high driving capability
-
1.3
1.6
-
LSEDRV[1:0]=11
higher driving capability
-
LSEDRV[1:0]=00
lower driving capability
5
8
15
LSEDRV[1:0]= 01
medium low driving capability
-
Oscillator
transconductance
gm
µA/V
LSEDRV[1:0] = 10
medium high driving capability
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
-
-
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
Figure 15. Typical application with a 32.768 kHz crystal
STM32F051x
2ESONATOR WITH
INTEGRATED CAPACITORS
#
,ꢀ
F
/3#ꢉꢅ?).
,3%
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AMPLIFIER
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RESONATOR
/3#ꢉꢅ?/54
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,ꢅ
-3ꢉꢃꢅꢁꢉ
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.7
Internal clock source characteristics
The parameters given in Table 38 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20.
High-speed internal (HSI) RC oscillator
(1)
Table 38. HSI oscillator characteristics
Symbol
Parameter
Frequency
HSI user trimming step
Conditions
Min
Typ
Max
Unit
fHSI
-
8
-
-
-
-
-
-
MHz
%
TRIM
-
1(2)
55(2)
4.6(3)
2.9(3)
2.2(3)
1
DuCy(HSI) Duty cycle
45(2)
–3.8(3)
–2.9(3)
–1.3(3)
–1
%
TA = –40 to 105 °C
TA = –10 to 85 °C
TA = 0 to 70 °C
TA = 25 °C
%
Accuracy of the HSI
oscillator (factory
calibrated)
%
ACCHSI
%
%
HSI oscillator startup
time
tsu(HSI)
1(2)
-
2(2)
µs
HSI oscillator power
consumption
IDD(HSI)
-
80
100(2)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
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STM32F051x
Electrical characteristics
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
(1)
Table 39. HSI14 oscillator characteristics
Symbol
Parameter
Frequency
HSI14 user-trimming step
Conditions
Min
Typ
Max
Unit
fHSI14
TRIM
-
-
14
-
MHz
%
1(2)
55(2)
5.1(3)
3.1(3)
2.2(3)
1
DuCy(HSI14) Duty cycle
45(2)
-
%
TA = –40 to 105 °C –4.2(3)
TA = –10 to 85 °C –3.2(3)
-
%
-
%
Accuracy of the HSI14
oscillator (factory calibrated)
ACCHSI14
TA = 0 to 70 °C
TA = 25 °C
–1.3(3)
-
%
–1
-
%
tsu(HSI14) HSI14 oscillator startup time
1(2)
-
2(2)
µs
HSI14 oscillator power
IDD(HSI14)
-
100 150(2)
µA
consumption
1.
VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Low-speed internal (LSI) RC oscillator
(1)
Table 40. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI
Frequency
30
-
40
-
50
85
kHz
µs
(2)
tsu(LSI)
LSI oscillator startup time
(2)
IDD(LSI)
LSI oscillator power consumption
-
0.75
1.2
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 41 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The event used to wake up the device depends from the current operating mode:
●
Stop or sleep mode: the wakeup event is WFE
●
The wakeup pin used in stop and sleep mode is PA0 and in standby mode is the PA1.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 20.
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Electrical characteristics
STM32F051x
Max Unit
Table 41. Low-power mode wakeup timings
Typ @VDD
Symbol
Parameter
Conditions
= 2.0 V = 2.4 V =2.7V
= 3 V =3.3V
Regulator in run
mode
4.2
8.05
60.35
1.1
4.2
7.05
55.6
1.1
4.2
6.6
4.2
6.27
52.02
1.1
4.2
6.05
50.96
1.1
5
9
Wakeup from Stop
mode
tWUSTOP
Regulator in low
power mode
µs
Wakeup from
Standby mode
tWUSTANDBY
53.5
1.1
Wakeup from Sleep
mode
tWUSLEEP
6.3.8
PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20.
Table 42. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max
PLL input clock(1)
1(2)
40(2)
16(2)
-
8.0
24(2)
60(2)
48
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
-
-
-
-
fPLL_OUT
tLOCK
MHz
µs
200(2)
300(2)
JitterPLL
Cycle-to-cycle jitter
-
ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT
.
2. Guaranteed by design, not tested in production.
6.3.9
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
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STM32F051x
Electrical characteristics
Table 43. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
16-bit programming time TA = –40 to +105 °C
40
20
20
-
53.5
60
40
40
10
12
3.6
µs
ms
ms
mA
mA
V
tERASE Page (1 KB) erase time TA = –40 to +105 °C
-
-
-
-
-
tME
Mass erase time
TA = –40 to +105 °C
Write mode
IDD
Supply current
Erase mode
-
Vprog Programming voltage
2
1. Guaranteed by design, not tested in production.
Table 44. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions
Unit
Min(1)
TA = –40 to +85 °C (6 suffix versions)
NEND
Endurance
kcycles
Years
10
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C
30
10
20
tRET
Data retention
1 kcycle(2) at TA = 105 °C
10 kcycles(2) at TA = 55 °C
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
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Electrical characteristics
STM32F051x
6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.
Table 45. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP64, TA = +25 °C,
fHCLK = 48 MHz
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
3B
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP64, TA = +25 °C,
fHCLK = 48 MHz
conforms to IEC 61000-4-4
VEFTB
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
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Prequalification trials
Electrical characteristics
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 46. EMI characteristics
Max vs. [fHSE/fHCLK
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/48 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
-3
28
23
4
VDD = 3.6 V, TA = 25 °C,
LQFP64 package
compliant with IEC
61967-2
dBµV
-
SEMI
Peak level
6.3.11
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 47. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
Electrostatic discharge
TA = +25 °C, conforming
V
2
II
2000
500
ESD(HBM) voltage (human body model) to JESD22-A114
V
Electrostatic discharge
TA = +25 °C, conforming
V
ESD(CDM) voltage (charge device model) to JESD22-C101
1. Data based on characterization results, not tested in production.
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Electrical characteristics
Static latch-up
STM32F051x
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
●
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 48. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
6.3.12
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of current injection on adjacent pins (lower than –5 µA
or lower than − 10 µA), or other functional failure (for example reset, oscillator frequency
deviation).
The characterization results are given in Table 49.
Table 49. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0, PF0-OSC_IN
and PF1-OSC_OUT pins
–0
–5
NA
NA
Injected current on PA10, PA12, PB4, PB5,
PB10, PB15 and PD2 with current injection
on adjacent pins > –5 µA and <–10 µA
mA
Injected current on other FT and FTf pins
with current injection on adjacent pins
<–5 µA
IINJ
–5
NA
Injected current on PA6 and PC0 pins
Injected current on all other TTa pins
Injected current on TC and RST pins
–0
–5
–5
+5
+5
+5
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Electrical characteristics
6.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 20. All I/Os are CMOS and TTL
compliant.
Table 50. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard I/O input low
level voltage
–0.3
-
0.3VDD+0.07
TTa I/O input low level
voltage
–0.3
–0.3
-
-
-
-
-
-
-
0.3VDD+0.07
0.475VDD–0.2
0.3VDD–0.3
VDD+0.3
VDD+0.3
5.5
VIL
FT and FTf(1) I/O input
low level voltage
BOOT0 input low level
voltage
0
V
Standard I/O input high
level voltage
0.445VDD+0.398
0.445VDD+0.398
0.5VDD+0.2
0.2VDD+0.95
TTa I/O input high level
voltage
VIH
FT and FTf(1) I/O input
high level voltage
BOOT0 input high level
voltage
5.5
Standard I/O Schmitt
trigger voltage
200
200
100
-
-
-
-
-
-
hysteresis(2)
TTa I/O Schmitt trigger
voltage hysteresis(2)
Vhys
mV
FT and FTf I/O Schmitt
trigger voltage
hysteresis(2)
BOOT0 input Schmitt
trigger voltage
300
-
-
hysteresis(2)
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Electrical characteristics
STM32F051x
Unit
Table 50. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
VSS ≤ VIN ≤ VDD
I/O TC, FT and FTf
-
-
±±01
VSS ≤ VIN ≤ VDD
2 V≤ VDD ≤ VDDA ≤ 3.6 V
-
-
-
-
±±01
I/O TTa used in digital
mode
VIN= 5 V
I/O FT and FTf
10
Ilkg
Input leakage current (3)
µA
VIN= 3.6 V,
2 V≤ VDD ≤ VIN
VDDA = 3.6 V
-
-
1
I/O TTa used in digital
mode
VSS ≤ VIN ≤ VDDA
2 V≤ VDD ≤ VDDA ≤ 3.6 V
-
-
±±02
I/O TTa used in analog
mode
Weak pull-up equivalent
resistor(4)
RPU
VIN = VSS
VIN = VDD
30
40
50
kΩ
Weak pull-down
RPD
CIO
30
-
40
5
50
-
kΩ
equivalent resistor(4)
I/O pin capacitance
pF
1. To sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Data based on characterization, not tested in production.
3. Leakage could be higher than max. if negative current is injected on adjacent pins.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 16 and Figure 17 for standard I/Os, and
in Figure 18 and Figure 19 for 5 V tolerant I/Os.
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Electrical characteristics
Figure 16. TC and TTa I/O input characteristics - CMOS port
VIL/VIH (V)
= 0.7V
+0.398
= 0.445V
CMOS standard requirements V
V
V
VIHmin 2.0
+0.07
= 0.3V
1.3
Input range not
guaranteed
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30255V1
Figure 17. TC and TTa I/O input characteristics - TTL port
VIL/VIH (V)
+0.398
TTL standard requirements VIHmin = 2 V
= 0.445V
= 0.3V
V
VIHmin 2.0
1.3
+0.07
V
Input range not
guaranteed
VILmax 0.8
0.7
TTL standard requirements VILmax = 0.8 V
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30256V1
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Electrical characteristics
STM32F051x
Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
VIL/VIH (V)
+0.2
CMOS standard requirements VIH min= 0.7VDD
= 0.5V
V
V
2.0
-0.2
= 0.475V
Input range not
guaranteed
1.0
CMOS standard requirements VILmax = 0.3VDD
0.5
VDD (V)
2.0
3.6
MS30257V1
Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port
VIL/VIH (V)
+0.2
TTL standard requirements VIHmin = 2 V
= 0.5V
V
V
2.0
-0.2
Input range not
guaranteed
= 0.475V
1.0
0.8
TTL standard requirements VILmax = 0.8 V
0.5
VDD (V)
2.0
2.7
3.6
MS30258V1
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STM32F051x
Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed V ).
V
OL/ OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
●
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 18).
VDD
●
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 18).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 20. All I/Os are CMOS and TTL compliant (FT, TTa or TC unless otherwise specified).
Table 51. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
CMOS port(2)
IIO = +8 mA
VOL
-
0.4
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)
2.7 V < VDD < 3.6 V
VOH
VDD–0.4
-
0.4
-
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
TTL port(2)
IIO =+ 8mA
VOL
-
V
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)
2.7 V < VDD < 3.6 V
VOH
2.4
Output low level voltage for an I/O pin
when 5 pins are sunk at same time
(1)(4)
VOL
-
1.3
-
IIO = +20 mA
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 5 pins are sourced at same time
(3)(4)
VOH
VDD–1.3
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(4)
VOL
-
0.4
-
IIO = +6 mA
V
V
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)(4)
VOH
VDD–0.4
-
IIO = +20 mA
Output low level voltage for an FTf I/O
pin in FM+ mode
VOLFM+
0.4
2.7 V < VDD < 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 18
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 18 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Data based on characterization results, not tested in production.
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Electrical characteristics
STM32F051x
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 20 and
Table 52, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 20.
DD
(1)
Table 52. I/O AC characteristics
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
Min Max
Unit
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 V to 3.6 V
-
-
2
MHz
Output high to low level
tf(IO)out
125(3)
x0
01
fall time
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
ns
MHz
ns
Output low to high level
rise time
tr(IO)out
-
-
-
125(3)
10
fmax(IO)out Maximum frequency(2)
Output high to low level
fall time
tf(IO)out
25(3)
Output low to high level
rise time
tr(IO)out
-
25(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
TBD
-
-
-
-
-
-
-
-
-
-
50
30
MHz
MHz
MHz
fmax(IO)out Maximum frequency(2)
20
5(3)
8(3)
12(3)
5(3)
8(3)
12(3)
Output high to low level
fall time
11
tf(IO)out
ns
Output low to high level
rise time
tr(IO)out
fmax(IO)out Maximum frequency(2)
TBD MHz
FM+
Output high to low level
fall time
tf(IO)out
TBD
TBD
-
-
TBD
ns
configuration
(4)
Output low to high level
rise time
tr(IO)out
TBD
Pulse width of external
tEXTIpw
signals detected by the
EXTI controller
10
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0091 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 20.
3. Guaranteed by design, not tested in production.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F05xxx reference manual RM0091 for a
description of FM+ I/O mode configuration.
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Figure 20. I/O AC characteristics definition
Electrical characteristics
90%
10 %
50%
50%
90%
10%
t
EXTERNAL
OUTPUT
ON 50pF
t
r(IO)out
r(IO)out
T
Maximum frequency is achieved if (t + t ) ≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
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Electrical characteristics
STM32F051x
6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 50).
PU
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 20.
Table 53. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)
VIL(NRST)
NRST Input low level voltage
NRST Input high level voltage
–0.3
2
-
-
0.8
V
(1)
VIH(NRST)
Vhys(NRST)
RPU
VDD+0.3
NRST Schmitt trigger voltage
hysteresis
-
200
-
mV
Weak pull-up equivalent resistor(2)
VIN = VSS
30
-
40
-
50
100
-
kΩ
ns
ns
(1)
VF(NRST)
NRST Input filtered pulse
(1)
VNF(NRST)
NRST Input not filtered pulse
300
-
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 21. Recommended NRST pin protection
6
$$
%XTERNAL
RESET CIRCUITꢌꢀꢍ
2
05
ꢌꢅꢍ
)NTERNAL 2ESET
.234
&ILTER
ꢃꢄꢀ &
-3ꢀꢓꢎꢑꢎ6ꢀ
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53. Otherwise the reset will not be taken into account by the device.
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Electrical characteristics
6.3.15
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 54 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 20.
Note:
It is recommended to perform a calibration after each power-up.
Table 54. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
3.6
Unit
Analog supply voltage for
ADC ON
VDDA
fADC
2.4
-
V
ADC clock frequency
Sampling rate
0.6
-
-
14
1
MHz
MHz
(1)
0.05
fS
f
ADC = 14 MHz
-
-
-
-
-
823
17
kHz
1/fADC
V
(1)
External trigger frequency
fTRIG
VAIN
Conversion voltage range
External input impedance
Sampling switch resistance
0
VDDA
See Equation 1 and
Table 55 for details
(1)
RAIN
-
-
-
-
-
-
50
1
kΩ
kΩ
pF
(1)
RADC
Internal sample and hold
capacitor
(1)
8
CADC
f
ADC = 14 MHz
5.9
µs
1/fADC
µs
(1)
Calibration time
tCAL
83
0.196
5.5
fADC = fPCLK/2 = 14 MHz
fADC = fPCLK/2
1/fPCLK
µs
(1)
Trigger conversion latency
fADC = fPCLK/4 = 12 MHz
0.219
10.5
-
tlatr
f
ADC = fPCLK/4
1/fPCLK
µs
fADC = fHSI14 = 14 MHz
0.188
-
0.259
-
ADC jitter on trigger
conversion
JitterADC
fADC = fHSI14
1
1/fHSI14
f
f
ADC = 14 MHz
0.107
1.5
0
-
-
17.1
239.5
1
µs
1/fADC
µs
(1)
Sampling time
Power-up time
tS
(1)
tSTAB
0
ADC = 14 MHz
1
18
µs
Total conversion time
(including sampling time)
(1)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Guaranteed by design, not tested in production.
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Electrical characteristics
Equation 1: R
STM32F051x
max formula
AIN
TS
RAIN < ------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
(1)
Table 55.
R
max for f
= 14 MHz
AIN
ADC
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
7.5
0.11
0.54
0.96
2.04
2.96
3.96
5.11
17.1
0.4
5.9
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Guaranteed by design, not tested in production.
(1)(2) (3)
Table 56. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
1.3
1
2
1.5
1.5
1
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
Gain error
0.5
0.7
0.8
3.3
1.9
2.8
0.7
1.2
3.3
1.9
2.8
0.7
1.2
LSB
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
1.5
4
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
2.8
3
Gain error
LSB
LSB
VDDA = 2.7 V to 3.6 V
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
1.3
1.7
4
TA = −40 to 105 °C
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
TA = 25 °C
2.8
3
Gain error
Differential linearity error
Integral linearity error
1.3
1.7
1. ADC DC accuracy values are measured after internal calibration.
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Electrical characteristics
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not
affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
Figure 22. ADC accuracy characteristics
V
DDA
ꢅꢂ
1 LSB
IDEAL
ꢋꢃꢓꢇ
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
0
V
1
2
3
4
5
6
7
4093 4094 4095 4096
V
DDA
SSA
-3ꢀꢓꢎꢎꢃ6ꢀ
Figure 23. Typical connection diagram using the ADC
6
$$!
Sample and hold ADC
V
0.6 V
T
converter
(1)
(1)
R
R
ADC
AIN
AINx
12-bit
converter
I
1 μA
L
C
V
T
parasitic
V
AIN
0.6 V
(1)
C
ADC
-3ꢀꢓꢎꢎꢀ6ꢅ
1. Refer to Table 54 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
Doc ID 022265 Rev 3
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Electrical characteristics
STM32F051x
6.3.16
DAC electrical specifications
Table 57. DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Comments
Analog supply voltage for
DAC ON
VDDA
2.4
5
-
-
3.6
-
V
(1)
RLOAD
Resistive load with buffer ON
kΩ Load is referred to ground
When the buffer is OFF, the Minimum
Impedance output with buffer
OFF
resistive load between DAC_OUT
and VSS to have a 1% accuracy is
(1)
RO
-
-
15
kΩ
1.5 MΩ
Maximum capacitive load at
pF DAC_OUT pin (when the buffer is
ON).
(1)
CLOAD
Capacitive load
-
-
-
50
-
It gives the maximum output
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
excursion of the DAC.
0.2
V
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VDDA = 3.6 V
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer ON
and (0x155) and (0xEAB) at VDDA
2.4 V
=
-
-
-
-
-
-
VDDA – 0.2
V
mV
V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
0.5
-
VDDA – 1LSB
380
It gives the maximum output
excursion of the DAC.
DAC_OUT Higher DAC_OUT voltage
-
-
-
max(1)
with buffer OFF
With no load, middle code (0x800) on
the input
µA
µA
DAC DC current
IDDA
consumption in quiescent
mode (Standby mode)
With no load, worst code (0xF1C) on
the input
480
Given for the DAC in 10-bit
configuration
-
-
0.5
LSB
Differential non linearity
Difference between two
consecutive code-1LSB)
DNL(2)
Given for the DAC in 12-bit
configuration
-
-
-
-
2
1
LSB
LSB
Integral non linearity
(difference between
Given for the DAC in 10-bit
configuration
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
INL(2)
Given for the DAC in 12-bit
configuration
-
-
4
LSB
Given for the DAC in 12-bit
configuration
-
-
-
-
-
-
-
-
10
3
mV
LSB
LSB
%
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VDDA/2)
Given for the DAC in 10-bit at VDDA
3.6 V
=
=
Offset(2)
Given for the DAC in 12-bit at VDDA
3.6 V
12
0.5
Gain
Given for the DAC in 12bit
configuration
Gain error
error(2)
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STM32F051x
Electrical characteristics
Comments
Table 57. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value 1LSB
(2)
tSETTLING
-
3
4
µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Update
rate(2)
-
-
1
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
(2)
tWAKEUP
-
-
6.5
10
µs
input code between lowest and
highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
–67
–40
dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. Data based on characterization results, not tested in production.
Figure 24. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RLOAD
DACx_OUT
12-bit
digital to
analog
converter
CLOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
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Electrical characteristics
STM32F051x
6.3.17
Comparator characteristics
Table 58. Comparator characteristics
Symbol
Parameter
Conditions
Min Typ Max(1) Unit
VDDA
Analog supply voltage
2
0
-
-
3.6
Comparator input
voltage range
VIN
VDDA
V
VBG
VSC
Scaler input voltage
Scaler offset voltage
-
-
1.2
5
10
mV
ms
Scaler startup time
from power down
tS_SC
-
-
-
-
0.1
Comparator startup
time
Startup time to reach propagation delay
specification
tSTART
60
µs
µs
Ultra-low power mode
Low power mode
-
-
-
-
-
-
-
-
-
-
-
2
4.5
1.5
0.6
100
240
7
0.7
0.3
50
Propagation delay for
200 mV step with 100 Medium power mode
mV overdrive
VDDA ≥ 2.7 V
VDDA < 2.7 V
High speed power mode
ns
µs
ns
100
2
tD
Ultra-low power mode
Low power mode
0.7
0.3
90
2.1
1.2
180
300
±10
Propagation delay for
full range step with 100 Medium power mode
mV overdrive
VDDA ≥ 2.7 V
VDDA < 2.7 V
High speed power mode
110
±4
Voffset
Comparator offset error
mV
Offset error
temperature coefficient
dVoffset/dT
-
18
-
µV/°C
Ultra-low power mode
-
-
-
-
1.2
3
1.5
5
Low power mode
COMP current
IDD(COMP)
µA
consumption
Medium power mode
10
75
15
100
High speed power mode
82/105
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STM32F051x
Electrical characteristics
Min Typ Max(1) Unit
Table 58. Comparator characteristics (continued)
Symbol
Parameter
Conditions
No hysteresis
(COMPxHYST[1:0]=00)
-
3
0
-
High speed power
mode
13
10
26
19
49
40
Low hysteresis
(COMPxHYST[1:0]=01)
8
All other power
modes
5
High speed power
mode
Vhys
Comparator hysteresis
7
mV
Medium hysteresis
(COMPxHYST[1:0]=10)
15
31
All other power
modes
9
High speed power
mode
18
19
High hysteresis
(COMPxHYST[1:0]=11)
All other power
modes
1. Data based on characterization results, not tested in production.
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Electrical characteristics
STM32F051x
6.3.18
Temperature sensor characteristics
Table 59. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
-
±1
4.3
1.43
-
±2
4.6
1.52
10
°C
mV/°C
V
Avg_Slope(1) Average slope
4.0
1.34
4
V25
Voltage at 25 °C
Startup time
(1)
tSTART
µs
ADC sampling time when reading the
temperature
(1)(2)
TS_temp
17.1
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.19
V
monitoring characteristics
BAT
Table 60.
Symbol
V
monitoring characteristics
Parameter
BAT
Min
Typ
Max
Unit
R
Q
Er(1)
Resistor bridge for VBAT
Ratio on VBAT measurement
Error on Q
-
-
50
2
-
-
KΩ
–1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
(1)(2)
TS_vbat
5
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.20
Timer characteristics
The parameters given in Table 61 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 61. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
ns
1
-
tres(TIM)
Timer resolution time
fTIMxCLK = 48 MHz
20.8
-
fTIMxCLK/2
0
0
-
MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 48 MHz
TIMx (except TIM2)
TIM2
24
16
32
MHz
ResTIM
Timer resolution
bit
-
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STM32F051x
Table 61. TIMx characteristics (continued)
Electrical characteristics
(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
1
65536
1365
tCOUNTER
16-bit counter clock period
fTIMxCLK = 48 MHz 0.0208
-
µs
tTIMxCLK
65536 × 65536
89.48
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 48 MHz
-
s
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17
timers.
(1)
Table 62. IWDG min/max timeout period at 40 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
/8
0
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
1
/16
/32
/64
/128
/256
2
1638.4
3276.8
6553.6
13107.2
26214.4
3
4
ms
5
6 or 7
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from
30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the
phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of
uncertainty.
Table 63. WWDG min-max timeout value @48 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0853
0.1706
0.3413
0.6826
5.4613
10.9226
21.8453
43.6906
ms
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Electrical characteristics
STM32F051x
6.3.21
Communication interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 64 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLK
DD
summarized in Table 20.
2
2
The I C interface meets the requirements of the standard I C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and V is
DD
disabled, but is still present.
2
The I C characteristics are described in Table 64. Refer also to Section 6.3.13: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
(1)
Table 64. I C characteristics
Standard mode
Fast mode
Min Max
Fast Mode Plus
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
-
1.3
0.6
-
0.5
0.26
50
-
µs
-
-
-
250
0(3)
-
100
0(3)
-
-
SDA data hold time
3450(2)
900(2)
0(4)
450(2)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
1000
-
300
-
120
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
-
300
-
300
-
120
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
0.26
0.26
0.26
0.5
-
-
-
-
µs
Repeated Start condition
setup time
tsu(STO)
Stop condition setup time
μs
μs
Stop to Start condition time
(bus free)
tw(STO:STA)
Capacitive load for each bus
line
Cb
-
400
-
400
-
550
pF
The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in
production.
1.
The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
2.
3.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
4. The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
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STM32F051x
Electrical characteristics
(1)
Table 65. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Pulse width of spikes that are
suppressed by the analog filter
tSP
50
260
ns
1. Guaranteed by design, not tested in production.
2
Figure 25. I C bus AC waveforms and measurement circuit
6
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
SPI/I2S characteristics
2
Unless otherwise specified, the parameters given in Table 66 for SPI or in Table 67 for I S
are derived from tests performed under ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 20.
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
Table 66. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
-
-
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
-
6
ns
Doc ID 022265 Rev 3
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Electrical characteristics
STM32F051x
Table 66. SPI characteristics (continued)
Symbol
Parameter
Conditions
Slave mode
Min
Max
Unit
(1)
tsu(NSS)
NSS setup time
NSS hold time
4Tpclk
-
-
(1)
th(NSS)
Slave mode
2Tpclk + 10
(1)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
Tpclk/2 -2
Tpclk/2 + 1
(1)
(1)
Master mode
Slave mode
Master mode
Slave mode
4
-
tsu(MI)
tsu(SI)
(1)
5
-
(1)
th(MI)
4
-
Data input hold time
ns
(1)
th(SI)
5
-
(1)(2)
ta(SO)
Data output access time Slave mode, fPCLK = 20 MHz
Data output disable time Slave mode
0
3Tpclk
(1)(3)
tdis(SO)
tv(SO)
tv(MO)
th(SO)
0
18
(1)
(1)
(1)
(1)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
-
22.5
6
-
11.5
2
Data output hold time
th(MO)
-
SPI slave input clock duty
cycle
DuCy(SCK)
Slave mode
25
75
%
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
Figure 26. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
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STM32F051x
Electrical characteristics
(1)
Figure 27. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
h(NSS)
SU(NSS)
t
c(SCK)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
(1)
Figure 28. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
BIT6 IN
LSB IN
t
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
Doc ID 022265 Rev 3
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Electrical characteristics
STM32F051x
2
Table 67. I S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
1.597
1.601
fCK
1/tc(CK)
I2S clock frequency
MHz
Slave mode
0
-
6.5
tr(CK)
I2S clock rise time
I2S clock fall time
I2S clock high time
I2S clock low time
WS valid time
10
12
-
Capacitive load CL = 15 pF
tf(CK)
-
(1)
(1)
tw(CKH)
306
312
2
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
tw(CKL)
-
ns
%
(1)
tv(WS)
th(WS)
tsu(WS)
Master mode
Master mode
Slave mode
Slave mode
-
(1)
(1)
(1)
WS hold time
2
-
WS setup time
WS hold time
7
-
th(WS)
0
-
I2S slave input clock duty
cycle
DuCy(SCK)
Slave mode
25
75
(1)
tsu(SD_MR)
Data input setup time
Data input setup time
Master receiver
Slave receiver
Master receiver
Slave receiver
6
2
-
-
-
-
(1)
tsu(SD_SR)
(1)(2)
th(SD_MR)
th(SD_SR)
4
Data input hold time
(1)(2)
0.5
Slave transmitter (after enable
edge)
(1)(2)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
-
13
-
20
-
ns
Slave transmitter (after enable
edge)
(1)
Master transmitter (after enable
edge)
(1)(2)
(1)
4
-
Master transmitter (after enable
edge)
0
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
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STM32F051x
Figure 29. I2S slave timing diagram (Philips protocol)
Electrical characteristics
t
c(CK)
CPOL = 0
CPOL = 1
WS input
t
t
t
w(CKL)
h(WS)
w(CKH)
t
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
transmit
(2)
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
(2)
LSB receive
Bitn receive
LSB receive
SD
receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 30. I2S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
h(WS)
t
v(WS)
w(CKL)
t
t
v(SD_MT)
h(SD_MT)
(2)
SD
transmit
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
(2)
SD
LSB receive
Bitn receive
LSB receive
receive
ai14884b
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Package characteristics
STM32F051x
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
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STM32F051x
Package characteristics
Figure 31. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline
D
ccc
C
D1
D3
A
A2
33
48
32
49
b
L1
E3
E1 E
L
A1
K
64
17
Pin 1
identification
1
16
c
5W_ME
1. Drawing is not to scale.
Table 68. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
12.200
10.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.4803
0.4016
0.050
1.350
0.170
0.090
11.800
9.800
0.0020
0.0531
0.0067
0.0035
0.4646
0.3858
1.400
0.220
0.0551
0.0087
c
D
12.000
10.000
7.500
12.000
10.00
0.500
3.5°
0.4724
0.3937
D1
D.
E
11.800
9.800
12.200
10.200
0.4646
0.3858
0.4724
0.3937
0.0197
3.5°
0.4803
0.4016
E1
e
k
0°
7°
0°
7°
L
0.450
0.600
1.000
0.080
0.75
0.0177
0.0236
0.0394
0.0031
0.0295
L1
ccc
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 022265 Rev 3
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Package characteristics
Figure 32. LQFP64 recommended footprint
STM32F051x
48
33
0.3
49
32
0.5
12.7
10.3
10.3
64
17
1.2
1
16
7.8
12.7
ai14909
1. Drawing is not to scale.
2. Dimensions are in millimeters.
94/105
Doc ID 022265 Rev 3
STM32F051x
Package characteristics
Figure 33. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package outline
D
ccc
C
D1
D3
A
A2
25
36
24
37
L1
b
E3
E1 E
48
L
13
A1
K
Pin 1
identification
1
12
c
5B_ME
1. Drawing is not to scale.
Table 69. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
9.200
7.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
0.050
1.350
0.170
0.090
8.800
6.800
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
1.400
0.220
0.0551
0.0087
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0°
0.750
7°
0.0177
0°
0.0295
7°
L1
k
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 022265 Rev 3
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Package characteristics
Figure 34. LQFP48 recommended footprint
STM32F051x
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911b
1. Drawing is not to scale.
2. Dimensions are in millimeters.
96/105
Doc ID 022265 Rev 3
STM32F051x
Package characteristics
Figure 35. LQFP32 7 x 7mm 32-pin low-profile quad flat package outline
CCC
#
$
$ꢀ
$ꢉ
!
!ꢅ
ꢅꢋ
ꢀꢑ
ꢀꢇ
ꢅꢁ
ꢉꢅ
,ꢀ
B
%ꢉ
%ꢀ %
ꢓ
,
0IN ꢀ
IDENTIFICATION
!ꢀ
+
ꢀ
ꢎ
C
ꢁ6?-%
1. Drawing is not to scale.
Table 70. LQFP32 7 x 7mm 32-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.450
0.200
9.200
7.200
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
0.050
1.350
0.300
0.090
8.800
6.800
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
1.400
0.370
0.0551
0.0146
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0.0°
0.750
0.0177
0.0°
0.0295
L1
k
7.0°
7.0°
ccc
0.100
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 022265 Rev 3
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Package characteristics
Figure 36. LQFP32 recommended footprint
STM32F051x
ꢓꢄꢋꢃ
ꢑꢄꢑꢃ
ꢃꢄꢁꢋ
ꢓꢄꢋꢃ
ꢃꢄꢎꢃ
ꢁ6?&0
1. Drawing is not to scale.
2. Dimensions are expressed in millimeters.
98/105
Doc ID 022265 Rev 3
STM32F051x
Package characteristics
Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
b
E
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
A0B8_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must
be connected. It is referred to as pin 0 in Table 13: Pin definitions.
Table 71. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A3
b
0.5
0.55
0.02
0.152
0.23
5.00
3.50
5.00
0.6
0.0197
0
0.0217
0.0008
0.006
0.0236
0.0020
0.00
0.05
0.18
4.90
0.28
5.10
0.0071
0.1929
0.0091
0.1969
0.1378
0.1969
0.0110
0.2008
D
D2
E
4.90
3.40
5.10
3.60
0.1929
0.1339
0.2008
0.1417
E2
3.50
0.1378
e
L
0.500
0.40
0.08
0.0197
0.0157
0.0031
0.30
0.50
0.0118
0.0197
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 38. UFQFPN32 recommended footprint
STM32F051x
1. Drawing is not to scale.
2. Dimensions are expressed in millimeters.
7.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 20: General operating conditions.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
●
●
●
●
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
100/105
Doc ID 022265 Rev 3
STM32F051x
Package characteristics
Table 72. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
55
56
38
ΘJA
°C/W
Thermal resistance junction-ambient
LQFP32 - 7 × 7 mm
Thermal resistance junction-ambient
UFQFPN32 - 5 × 5 mm
7.2.1
7.2.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F05xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Using the values obtained in Table 72 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Table 20:
J
General operating conditions.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
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Package characteristics
STM32F051x
Note:
With this given P
we can find the T
allowed for a given device temperature range
Dmax
Amax
(order code suffix 6 or 7).
Suffix 6: T
Suffix 7: T
= T
= T
- (45°C/W × 447 mW) = 105-20.115 = 84.885 °C
- (45°C/W × 447 mW) = 125-20.115 = 104.885 °C
Amax
Amax
Jmax
Jmax
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
= 100 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V= 70 mW
INTmax
= 20 × 8 mA × 0.4 V = 64 mW
IOmax
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
= 70 + 64 = 134 mW
Dmax
Thus: P
= 134 mW
Dmax
Using the values obtained in Table 72 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C
Jmax
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation in order to be able to
use suffix 6 parts.
Refer to figure 38 to select the required temperature range (suffix 6 or 7) according to your
ambient temperature or power requirements.
Figure 39. LQFP64 P max vs. T
D
A
700
600
500
400
300
200
100
0
Suffix 6
Suffix 7
65
75
85
95 105 115 125 135
TA (°C)
102/105
Doc ID 022265 Rev 3
STM32F051x
Part numbering
8
Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 73. Ordering information scheme
Example:
STM32
F
051 R
8
T
6
x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
051 = STM32F051xx
Pin count
K = 32 pins
C = 48 pins
R = 64 pins
Code size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory
Package
U = UFQFPN
T = LQFP
Temperature range
6 = –40 °C to +85 °C
7 = –40 °C to +105 °C
Options
xxx = programmed parts
TR = tape and real
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STM32F051x
Revision history
9
Revision history
Table 74. Document revision history
Date
Revision
Changes
05-Apr-2012
1
Initial release
Updated Table 2: STM32F051x family device features and
peripheral counts for 1 SPI and 1 I2C in 32-pin package
Corrected Group 3 pin order in Table 5: Capacitive sensing
GPIOs available on STM32F051x devices.
25-Apr-2012
2
Updated current consumptionTable 25 to Table 29.
Updated Table 39: HSI14 oscillator characteristics
Features reorganized and Section 3: Functional overview
structure changed.
Added LQFP32 package.
Updated Section 3.4: Cyclic redundancy check calculation
unit (CRC).
Modified number of priority levels in Section 3.9.1: Nested
vectored interrupt controller (NVIC).
Added note 3. for PB2 and PB8, changed TIM2_CH_ETR into
TIM2_CH1_ETR in Table 13: Pin definitions and Table 14:
Alternate functions selected through GPIOA_AFR registers
for port A. Added Table 15: Alternate functions selected
through GPIOA_AFR registers for port B.
Updated IVDD, IVSS, and IINJ(PIN) in Table 18: Current
characteristics .
23-Jul-2012
3
Updated ACCHSI in Table 38: HSI oscillator characteristics
and Table 39: HSI14 oscillator characteristics.
Updated Table 49: I/O current injection susceptibility.
Added BOOT0 input low and high level voltage in Table 50:
I/O static characteristics.
Modified number of pins in VOL and VOH description, and
changed condition for VOLFM+ in Table 51: Output voltage
characteristics.
Changed VDD to VDDA in Figure 23: Typical connection
diagram using the ADC.
Updated Ts_temp in Table 59: TS characteristics.
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STM32F051x
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