STM32F072VBT6TR [STMICROELECTRONICS]
32-BIT, FLASH, 48MHz, RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, ROHS COMPLIANT, LQFP-100;
| 型号： | STM32F072VBT6TR |
| 厂家： | 
ST |
| 描述： | 32-BIT, FLASH, 48MHz, RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, ROHS COMPLIANT, LQFP-100 时钟 外围集成电路 |
| 文件： | 总124页 (文件大小：1741K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F072xx
ARM-based 32-bit MCU, up to 128 KB Flash, crystal-less USB
FS 2.0, CAN, 12 timers, ADC, DAC & comm. interfaces, 2.0 - 3.6 V
Datasheet - production data
Features
®
®
Core: ARM 32-bit Cortex -M0 CPU,
frequency up to 48 MHz
LQFP100 14x14 mm
LQFP64 10x10 mm
LQFP48 7x7 mm
UFQFPN48
7x7 mm
UFBGA100
7x7 mm
WLCSP49
0.4 mm pitch
Memories
– 64 to 128 Kbytes of Flash memory
– 16 Kbytes of SRAM with HW parity
Calendar RTC with alarm and periodic wakeup
from Stop/Standby
CRC calculation unit
12 timers
Reset and power management
– One 16-bit advanced-control timer for
6 channel PWM output
– Digital & I/Os supply: V = 2.0 V to 3.6 V
DD
– One 32-bit and seven 16-bit timers, with up
to 4 IC/OC, OCN, usable for IR control
decoding or DAC control
– Analog supply: V
= V to 3.6 V
DD
DDA
– Selected I/Os: V
= 1.65 V to 3.6 V
DDIO2
– Power-on/Power down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop, Standby
– Independent and system watchdog timers
– SysTick timer
Communication interfaces
– V
supply for RTC and backup registers
BAT
2
– Two I C interfaces supporting Fast Mode
Clock management
Plus (1 Mbit/s) with 20 mA current sink; one
supporting SMBus/PMBus and wakeup
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
– Four USARTs supporting master
synchronous SPI and modem control; two
with ISO7816 interface, LIN, IrDA, auto
baud rate detection and wakeup feature
– Internal 48 MHz oscillator with automatic
trimming based on ext. synchronization
– Two SPIs (18 Mbit/s) with 4 to 16
2
programmable bit frames, and with I S
interface multiplexed
Up to 87 fast I/Os
– All mappable on external interrupt vectors
– CAN interface
– Up to 68 I/Os with 5V tolerant capability
– USB 2.0 full-speed interface, able to run
from internal 48 MHz oscillator and with
BCD and LPM support
and 19 with independent supply V
DDIO2
7-channel DMA controller
One 12-bit, 1.0 μs ADC (up to 16 channels)
– Conversion range: 0 to 3.6 V
HDMI CEC wakeup on header reception
Serial wire debug (SWD)
96-bit unique ID
– Separate analog supply: 2.4 V to 3.6 V
One 12-bit D/A converter (with 2 channels)
®
All packages ECOPACK 2
Two fast low-power analog comparators with
programmable input and output
Table 1. Device summary
Up to 24 capacitive sensing channels for
Reference
Part number
touchkey, linear and rotary touch sensors
STM32F072C8, STM32F072R8, STM32F072V8,
STM32F072CB, STM32F072RB, STM32F072VB
STM32F072xx
February 2014
DocID025004 Rev 2
1/124
This is information on a product in full production.
www.st.com
Contents
STM32F072xx
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
ARM Cortex-M0 core with embedded Flash and SRAM . . . . . . . . . . . . . 13
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1
3.5.2
3.5.3
3.5.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
3.7
3.8
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9.1
3.9.2
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 18
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REFINT
3.10.3
V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
BAT
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.2 General-purpose timers (TIM2..3, TIM14..17) . . . . . . . . . . . . . . . . . . . . 23
3.14.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/124
DocID025004 Rev 2
STM32F072xx
Contents
3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 24
2
3.16 Inter-integrated circuit interfaces (I C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Universal synchronous/asynchronous receiver transmitters (USART) . . 26
2
3.18 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I S) . 27
3.19 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.20 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.21 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.22 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.23 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4
5
6
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 52
Embedded reset and power control block characteristics . . . . . . . . . . . 52
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DocID025004 Rev 2
3/124
4
Contents
STM32F072xx
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.20
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BAT
6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.1
7.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.2.1
7.2.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 119
8
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4/124
DocID025004 Rev 2
STM32F072xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F072xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitive sensing GPIOs available on STM32F072xx devices . . . . . . . . . . . . . . . . . . . . 21
No. of capacitive sensing channels available on STM32F072xx devices. . . . . . . . . . . . . . 21
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2
Table 9.
STM32F072xx I C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
STM32F072xx USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32F072xx SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32F072xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 40
Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 41
Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 42
Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 42
Alternate functions selected through GPIOE_AFR registers for port E . . . . . . . . . . . . . . . 43
Alternate functions available on port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STM32F072xx peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 52
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical and maximum current consumption from V supply at V = 3.6 V . . . . . . . . . . 54
DD
DD
Typical and maximum current consumption from the V
supply . . . . . . . . . . . . . . . . . . 56
DDA
Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 57
Typical and maximum current consumption from the V supply. . . . . . . . . . . . . . . . . . . 58
BAT
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typical current consumption in Sleep mode, code running from Flash . . . . . . . . . . . . . . . 60
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DocID025004 Rev 2
5/124
6
List of tables
STM32F072xx
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
R
max for f
= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
AIN
ADC
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2
I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UFBGA100 – ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LQFP100 – 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . 104
LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 107
LQFP48 – 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . 110
UFQFPN48 – 7 x 7 mm, 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . 114
WLCSP49 – 0.4 mm pitch package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
WLCSP49 recommended PCB design rules (0.4 mm pitch BGA) . . . . . . . . . . . . . . . . . . 118
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
6/124
DocID025004 Rev 2
STM32F072xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
UFBGA100 package ballout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LQFP100 100-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LQFP64 64-pin package pinout (top view)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LQFP48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
UFQFPN48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WLCSP49 49-pin package ballout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32F072xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 18. HSI oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 19. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 20. HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 21. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 23. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 25. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 26. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 27. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 29. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 30. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 31. I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 32. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 33. UFBGA100 – ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 34. UFBGA100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 35. UFBGA100 package top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 36. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline. . . . . . . . . . . . . . . 104
Figure 37. LQFP100 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 38. LQFP100 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 39. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . 107
Figure 40. LQFP64 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 41. LQFP64 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 42. LQFP48 – 7 x 7 mm, 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 110
Figure 43. LQFP48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 44. LQFP48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 45. UFQFPN48 – 7 x 7 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 46. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 47. UFQFPN48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DocID025004 Rev 2
7/124
8
List of figures
STM32F072xx
Figure 48. WLCSP49 – 0.4 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 49. WLCSP49 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 50. WLCSP49 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 51. LQFP64 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
D
A
8/124
DocID025004 Rev 2
STM32F072xx
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F072xx microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
®
®
®
For information on the ARM Cortex -M0 core, please refer to the Cortex -M0 Technical
Reference Manual, available from the www.arm.com website.
DocID025004 Rev 2
9/124
28
Description
STM32F072xx
2
Description
®
®
The STM32F072xx microcontrollers incorporate the high-performance ARM Cortex -M0
32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to
128 Kbytes of Flash memory and 16 Kbytes of SRAM), and an extensive range of enhanced
2
peripherals and I/Os. All devices offer standard communication interfaces (two I Cs, two
SPIs/one I2S, one HDMI CEC and four USARTs), one USB Full speed device (crystal-less),
one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven general-purpose 16-bit
timers, a 32-bit timer and an advanced-control PWM timer.
The STM32F072xx microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
modes allows the design of low-power applications.
The STM32F072xx microcontrollers include devices in six different packages ranging from
48 pins to 100 pins with a die form also available upon request. Depending on the device
chosen, different sets of peripherals are included. The description below provides an
overview of the complete range of STM32F072xx peripherals proposed.
These features make the STM32F072xx microcontrollers suitable for a wide range of
applications such as application control and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
10/124
DocID025004 Rev 2
STM32F072xx
Description
Table 2. STM32F072xx family device features and peripheral counts
Peripheral
Flash (Kbytes)
SRAM (Kbytes)
Advanced
STM32F072Cx
64 128
STM32F072Rx
64 128
STM32F072Vx
64 128
16
16
16
1 (16-bit)
control
Timers
General
purpose
5 (16-bit)
1 (32-bit)
Basic
SPI [I2S](1)
I2C
2 (16-bit)
2 [1]
2
4
1
1
1
USART
CAN
Comm.
interfaces
USB
CEC
12-bit ADC
1
1
(number of channels)
(10 ext. + 3 int.)
(16 ext. + 3 int.)
GPIOs
37
51
18
87
24
Capacitive sensing
channels
17
12-bit DAC
1
(number of channels)
(2)
Analog comparator
Max. CPU frequency
Operating voltage
2
48 MHz
2.0 to 3.6 V
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: -40 °C to 125 °C
Operating temperature
LQFP48
LQFP100
Packages
UFQFPN48
WLCSP49
LQFP64
UFBGA100
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
DocID025004 Rev 2
11/124
28
Description
STM32F072xx
Figure 1. Block diagram
32:(5
ꢅ
9''ꢁꢍ
6HULDOꢅ:LUHꢅ
'HEXJ
6:&/.
6:',2
DVꢅ$)
9'',2ꢅ ꢅꢄꢅWRꢅꢀꢆꢒꢅ9
966ꢅ
92/7ꢆ5(*
ꢀꢆꢀꢅ9ꢅ72ꢅꢁꢆꢍꢅ9
ꢅ
)ODVKꢅ*3/ꢅ
ꢅ
#ꢅ9'',2
8SꢅWRꢅꢁꢄꢍꢅ.%
&257(;ꢑ0ꢃꢅ&38
I0$;ꢅ ꢅꢂꢍꢅ0+]
ꢀꢄꢅELWV
9''86%2.,1ꢅꢅ
6833/<ꢅ
683(59,6,21
325
5HVHW
,QW
1567
ꢅ
9''$ꢅ
325ꢏ3'5
39'
65$0
ꢁꢒꢅ.%
ꢅ
ꢅ
966$
#ꢅ9''$
19,&
5&ꢅ+6ꢅꢁꢂꢅ0+]
5&ꢅ+6ꢅꢍꢅ0+]
3//
ꢅ
#ꢅ9''$
ꢅ
#ꢅ9'',2
*3ꢅ'0$
ꢐꢅFKDQQHOV
26&B,1ꢅꢈ3)ꢃꢊ
26&B287ꢅꢈ3)ꢁꢊ
;7$/ꢅ26&
ꢂꢑꢀꢄꢅ0+]
5&ꢅ/6
5&ꢅ+6ꢅꢂꢍ0+]
,QGꢆꢅ:LQGRZꢅ:'*
3RZHU
3$>ꢁꢋꢌꢃ@
3%>ꢁꢋꢌꢃ@
3&>ꢁꢋꢌꢃ@
3'>ꢁꢋꢌꢃ@
$+%3&/.
*3,2ꢅSRUWꢅ$
*3,2ꢅSRUWꢅ%
*3,2ꢅSRUWꢅ&
*3,2ꢅSRUWꢅ'
*3,2ꢅSRUWꢅ(
*3,2ꢅSRUWꢅ)
&RQWUROOHU
$3%3&/.
$'&&/.
&(&&/.
86$57&/.
+&/.
)&/.
86%&/.
9%$7ꢅ ꢅꢁꢆꢒꢋꢅWRꢅꢀꢆꢒꢅ9
5(6(7ꢅꢓꢅ
&/2&.ꢅ
#ꢅ96:ꢅ
26&ꢀꢄB,1ꢅꢅ
26&ꢀꢄB287
&21752/
;7$/ꢀꢄꢅN+]
%DFNXSꢅ
57&
UHJ
ꢀꢅ7$03(5ꢑ57&
ꢈ$/$50ꢅ287ꢊ
3(>ꢁꢋꢌꢃ@
57&ꢅLQWHUIDFH
3:0ꢅ7,0(5ꢅꢁ
3)>ꢀꢁꢂꢃ@ꢄꢅ3)ꢆꢄꢅ
3)>ꢇꢂꢁ@
&56
6<1&
ꢂꢅFKDQQHOV
&5&
ꢀꢅFRPSOꢆꢅFKDQQHOV
%5.ꢇꢅ(75ꢅLQSXWꢅDVꢅ$)
3$'
ꢍꢅJURXSVꢅRI
ꢂꢅFKDQQHOV
7RXFKꢅ
$QDORJꢅ
6HQVLQJꢅ
ꢂꢅFKꢆꢇꢅ(75ꢅDVꢅ$)
7,0(5ꢅꢄꢅꢀꢄꢑELW
7,0(5ꢅꢀ
VZLWFKHV
&RQWUROOHU
$+%
$3%
6<1&
ꢍꢎꢅ$)
ꢂꢅFKꢆꢇꢅ(75ꢅDVꢅ$)
(;7ꢆꢅ,7
:.83
7,0(5ꢅꢁꢂ
ꢁꢅFKDQQHOꢅDVꢅ$)
ꢄꢅFKDQQHOV
ꢁꢅFRPSOꢇꢅ%5.ꢅDVꢅ$)
86%
3+<
7,0(5ꢅꢁꢋ
86%
'ꢉꢇꢅ'ꢑ
65$0ꢅ
ꢐꢒꢍ%
ꢅ
ꢁꢅFKDQQHO
#ꢅ9''86%
7,0(5ꢅꢁꢒ
7,0(5ꢅꢁꢐ
ꢁꢅFRPSOꢇꢅ%5.ꢅDVꢅ$)
65$0ꢅ
ꢄꢋꢒ%
:,QGRZꢅ:'*
'%*0&8
ꢁꢅFKDQQHO
ꢁꢅFRPSOꢇꢅ%5.ꢅDVꢅ$)
7;ꢇꢅ5;ꢅDVꢅ$)
%[&$1
,5B287ꢅDVꢅ$)
026,ꢏ6'ꢇ
0,62ꢏ0&.ꢇ
6&.ꢏ&.ꢇ
5;ꢇꢅ7;ꢇ&76ꢇꢅ576ꢇ
&.ꢅDVꢅ$)
86$57ꢁ
86$57ꢄ
86$57ꢀ
86$57ꢂ
63,ꢁꢏ,ꢄ6ꢁ
166ꢏ:6ꢅDVꢅ$)
5;ꢇꢅ7;ꢇ&76ꢇꢅ576ꢇ
&.ꢅDVꢅ$)
026,ꢏ6'ꢇ
0,62ꢏ0&.ꢇ
6&.ꢏ&.ꢇ
63,ꢄꢏ,ꢄ6ꢄ
5;ꢇꢅ7;ꢇ&76ꢇꢅ576ꢇ
&.ꢅDVꢅ$)
6<6&)*ꢅ,)
166ꢏ:6ꢅDVꢅ$)
5;ꢇꢅ7;ꢇ&76ꢇꢅ576ꢇ
&.ꢅDVꢅ$)
6&/ꢇꢅ6'$ꢇꢅ60%$
ꢈꢄꢃꢅP$ꢅIRUꢅ)0ꢉꢊ
DVꢅ$)
6&/ꢇꢅ6'$ꢅꢈꢄꢃꢅP$ꢅ
IRUꢅ)0ꢉꢊꢅDVꢅ$)
,ꢄ&ꢁ
,ꢄ&ꢄ
,1387ꢉꢇ
,1387ꢑꢇ
287387
ꢅDVꢅ$)
*3ꢅFRPSDUDWRUꢅꢁ
*3ꢅFRPSDUDWRUꢅꢄ
ꢅ
#ꢅ9''$
&(&ꢅDVꢅ$)
+'0,ꢑ&(&
ꢁꢄꢑELWꢅꢅ
7HPSꢆꢅ
VHQVRU
7,0(5ꢅꢒ
7,0(5ꢅꢐ
ꢁꢒꢅ
$'ꢅLQSXWV
ꢁꢄꢑELWꢅ
$'&
'$&B287ꢁ
'$&B287ꢄ
,)
'$&
,)
ꢁꢄꢑELWꢅ
'$&
ꢅ
9''$
ꢅ
966$
ꢅ
#ꢅ9''$
ꢅ
#ꢅ9''$
06Yꢀꢁꢂꢃꢂ9ꢄ
12/124
DocID025004 Rev 2
STM32F072xx
Functional overview
3
Functional overview
3.1
ARM Cortex-M0 core with embedded Flash and SRAM
The ARM Cortex-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex-M0 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
The STM32F0xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2
Memories
The device has the following features:
16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
The non-volatile memory is divided into two arrays:
–
–
64 to 128 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
–
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
3.3
Boot modes
At startup, the boot pin and boot selector option bits are used to select one of the three boot
options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART on pins PA14/PA15 or PA9/PA10, I2C on pins PB6/PB7 or through the USB
DFU interface.
DocID025004 Rev 2
13/124
28
Functional overview
STM32F072xx
3.4
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes
V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
DD
externally through V pins.
DD
V
= 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and
DDA
PLL (minimum voltage to be applied to V
is 2.4 V when the ADC is used). The V
DDA
DDA
voltage level must be always greater or equal to the V voltage level and must be
DD
provided first.
V
= 1.65 to 3.6 V: external power supply for marked I/Os. Provided externally
DDIO2
through the VDDIO2 pin. The V
or V
diagrams or tables for concerned I/Os list.
voltage level is completely independent from V
DDIO2
DD
, but it must not be provided without a valid supply on V . Refer to the pinout
DDA
DD
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
3.5.2
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
, without the need for an external reset circuit.
POR/PDR
The POR monitors only the V supply voltage. During the startup phase it is required
DD
that V
should arrive first and be greater than or equal to V
.
DDA
DD
The PDR monitors both the V and V
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V is higher than or
supply voltages, however the V
power
DDA
DD
DDA
DDA
equal to V
.
DD
The V
supply is monitored and compared with the internal reference voltage (V
).
REFINT
DDIO2
When the V
is below this threshold, all the I/Os supplied from this rail are disabled by
DDIO2
hardware. The output of this comparator is connected to EXTI line 31 and it can be used to
generate an interrupt.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
power supply and compares it to the V
threshold. An interrupt can be generated
DD
PVD
when V drops below the V
threshold and/or when V is higher than the V
DD
PVD
DD PVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
14/124
DocID025004 Rev 2
STM32F072xx
Functional overview
3.5.3
Voltage regulator
The regulator has two operating modes and it is always enabled after reset.
Main (MR) is used in normal operating mode (Run).
Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4
Low-power modes
The STM32F072xx microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC alarm, I2C1, USART1
or the CEC.
The I2C1, USART1 and the CEC can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used when the voltage regulator is put in low power
mode, the regulator is first switched to normal mode before the clock is provided to the
given peripheral.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering
Stop or Standby mode.
DocID025004 Rev 2
15/124
28
Functional overview
STM32F072xx
3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
16/124
DocID025004 Rev 2
STM32F072xx
Functional overview
Figure 2. Clock tree
)/,7)&/.
WRꢅ)ODVKꢅ
SURJUDPPLQJꢅLQWHUIDFH
+6,
&56
WRꢅ,ꢄ&ꢁ
6<6&/.
WRꢅ,ꢄ6ꢁꢇꢄ
ꢅ
ꢂꢍꢅ0+]
+6,ꢂꢍꢅ5&
+6,ꢂꢍ
/6(
ꢏꢄꢂꢂ
WRꢅ&(&
ꢍꢅ0+]
+6,ꢅ5&
+6,
+&/.
ꢏꢍ
WRꢅ$+%ꢅEXVꢇꢅFRUHꢇꢅ
PHPRU\ꢅDQGꢅ'0$
6:
WRꢅFRUWH[ꢅ6\VWHPꢅWLPHUꢅ
)&/.ꢅ&RUWH[ꢅIUHHꢅUXQQLQJꢅFORFNꢅ
3//65&
3//08/
3//
+6,
3//&/.
$+%
$3%
SUHVFDOHU
ꢏꢁꢇꢄꢇꢂꢇꢍꢇꢁꢒ
ꢏꢁꢇꢄꢇ
ꢀꢇꢆꢆꢁꢒ
3&/.
ꢅ
[ꢄꢇ[ ꢇꢆꢆ
WRꢅ$3%ꢅSHULSKHUDOV
SUHVFDOHU
[ꢁꢒ
ꢏꢁꢇꢄꢇꢆꢆꢋꢁꢄ
6<6&/.
+6(
35(',9
&66
,Iꢅꢈ$3%ꢁꢅSUHVFDOHUꢅ
ꢁꢊꢅ[ꢁꢅHOVHꢅ[ꢄ
WRꢅ7,0ꢁꢇꢄꢇꢀꢇꢒꢇꢐ
ꢁꢂꢇꢁꢋꢇꢁꢒꢇꢁꢐ
26&B287
26&B,1
ꢅ
ꢂꢑꢀꢄꢅ0+]
3&/.
+6(ꢅ26&
6<6&/.
WRꢅ86$57ꢁ
WRꢅ86$57ꢄ
+6,
/6(
ꢏꢀꢄ
57&&/.
26&ꢀꢄB,1
WRꢅ57&
WRꢅ86%
/6(ꢅ26&
ꢀꢄꢆꢐꢒꢍN+]
/6(
26&ꢀꢄB287
+6,ꢂꢍ
1--$-,
57&6(/>ꢁꢌꢃ@
/6,
/6,ꢅ5&ꢅ
ꢂꢃN+]
WRꢅ,:'*
3//12',9
0&235(
0DLQꢅFORFN
3//&/.
ꢏꢁꢇꢄ
+6,
+6,ꢂꢍ
+6,ꢁꢂ
+6(
ꢁꢂꢅ0+]
+6,ꢁꢂꢅ5&
+6,ꢁꢂ
RXWSXW
WRꢅ$'&ꢅ
ꢏꢁꢇꢄꢇꢂꢇ
0&2
DV\QFKURQRXV
FORFNꢅLQSXWꢅ
ꢆꢆꢅꢁꢄꢍ
6<6&/.
/6,
/6(
WRꢅ7,0ꢁꢂ
0&2
06ꢀꢁꢂꢁꢍ9ꢁ
3.7
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
DocID025004 Rev 2
17/124
28
Functional overview
STM32F072xx
3.8
Direct memory access controller (DMA)
The 7-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14), DAC and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex-M0) and 4
priority levels.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 32 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 87
GPIOs can be connected to the 16 external interrupt lines.
3.10
Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
18/124
DocID025004 Rev 2
STM32F072xx
Functional overview
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
that varies linearly with
SENSE
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
TS_CAL1
temperature of 30 °C (5 °C),
0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V (10 mV)
TS ADC raw data acquired at a
TS_CAL2
temperature of 110 °C (5 °C), 0x1FFF F7C2 - 0x1FFF F7C3
DDA= 3.3 V (10 mV)
V
3.10.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC. V
is internally connected to the ADC_IN17 input channel. The precise voltage
REFINT
of V
is individually measured for each part by ST during production test and stored in
REFINT
the system memory area. It is accessible in read-only mode.
Table 4. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT_CAL
temperature of 30 °C (5 °C), 0x1FFF F7BA - 0x1FFF F7BB
DDA= 3.3 V (10 mV)
V
3.10.3
V
battery voltage monitoring
BAT
This embedded hardware feature allows the application to measure the V
battery voltage
BAT
using the internal ADC channel ADC_IN18. As the V
voltage may be higher than V
,
BAT
DDA
and thus outside the ADC input range, the V
pin is internally connected to a bridge
BAT
divider by 2. As a consequence, the converted digital value is half the V
voltage.
BAT
DocID025004 Rev 2
19/124
28
Functional overview
STM32F072xx
3.11
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert digital signals into analog
voltage signal outputs. The chosen design structure is composed of integrated resistor
strings and an amplifier in non-inverting configuration.
This digital Interface supports the following features:
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Six DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger
outputs and the DAC interface is generating its own DMA requests.
3.12
Comparators (COMP)
The device embeds two fast rail-to-rail low-power comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low power) and
with selectable output polarity.
The reference voltage can be one of the following:
External I/O
DAC output pins
Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 28: Embedded
internal reference voltage for the value and precision of the internal reference voltage.
Both comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined into a window comparator.
3.13
Touch sensing controller (TSC)
The STM32F072xx devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 24 capacitive sensing channels
distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
20/124
DocID025004 Rev 2
STM32F072xx
Functional overview
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 5. Capacitive sensing GPIOs available on STM32F072xx devices
Capacitive sensing
signal name
Pin
name
Capacitive sensing
signal name
Pin
name
Group
Group
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC5
PB0
PB1
PB2
PA9
PA10
PA11
PA12
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
PB3
PB4
1
5
PB6
PB7
PB11
PB12
PB13
PB14
PE2
2
3
4
6
7
8
PE3
PE4
PE5
PD12
PD13
PD14
PD15
Table 6. No. of capacitive sensing channels available on STM32F072xx devices
Number of capacitive sensing channels
Analog I/O group
STM32F072Vx
STM32F072Rx
STM32F072Cx
G1
G2
G3
G4
G5
G6
G7
G8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
0
0
3
3
2
3
3
3
0
0
Number of capacitive
sensing channels
24
18
17
DocID025004 Rev 2
21/124
28
Functional overview
STM32F072xx
3.14
Timers and watchdogs
The STM32F072xx devices include up to six general-purpose timers, two basic timers and
an advanced control timer.
Table 7 compares the features of the advanced-control, general-purpose and basic timers.
Table 7. Timer feature comparison
Timer
type
Counter
resolution
Counter
type
Prescaler DMA request Capture/compare Complementary
Timer
factor
generation
channels
outputs
Up,
down,
up/down and 65536
Any integer
between 1
Advanced
control
TIM1
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Yes
4
Yes
Up,
down,
up/down and 65536
Any integer
between 1
TIM2
TIM3
Yes
Yes
No
4
4
1
2
1
0
No
No
Up,
down,
up/down and 65536
Any integer
between 1
Any integer
between 1
and 65536
General
purpose
TIM14
TIM15
Up
Up
Up
Up
No
Any integer
between 1
and 65536
Yes
Yes
Yes
Yes
Yes
No
Any integer
between 1
and 65536
TIM16,
TIM17
Any integer
between 1
and 65536
TIM6,
TIM7
Basic
22/124
DocID025004 Rev 2
STM32F072xx
Functional overview
3.14.1
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
Input capture
Output compare
PWM generation (edge or center-aligned modes)
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.14.2
General-purpose timers (TIM2..3, TIM14..17)
There are six synchronizable general-purpose timers embedded in the STM32F072xx
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F072xx devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
DocID025004 Rev 2
23/124
28
Functional overview
STM32F072xx
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate
withTIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.14.3
3.14.4
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.14.5
3.14.6
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source (HCLK or HCLK/8)
3.15
Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power either
on V supply when present or through the V
pin. The backup registers are five 32-bit
DD
BAT
registers used to store 20 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
24/124
DocID025004 Rev 2
STM32F072xx
Functional overview
The RTC is an independent BCD timer/counter. Its main features are the following:
Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.
Programmable alarm with wake up from Stop and Standby mode capability.
Periodic wakeup unit with programmable resolution and period.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
3 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
The RTC clock sources can be:
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 40 kHz)
The high-speed external clock divided by 32
3.16
Inter-integrated circuit interfaces (I2C)
2
Up to two I C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode
Plus (up to 1 Mbit/s) with 20 mA output drive on some I/Os.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2
addresses, 1 with configurable mask). They also include programmable analog and digital
noise filters.
Table 8. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
50 ns
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Benefits
Available in Stop mode
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Variations depending on
temperature, voltage, process
Drawbacks
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
DocID025004 Rev 2
25/124
28
Functional overview
STM32F072xx
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 9 for the differences between I2C1 and I2C2.
2
Table 9. STM32F072xx I C implementation
I2C features(1)
I2C1
I2C2
X
X
X
X
X
X
X
X
X
X
X
X
X
7-bit addressing mode
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Independent clock
SMBus
Wakeup from STOP
1. X = supported.
3.17
Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds up to four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART4), which communicate at speeds of up to 6
Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1 and USART2 support also SmartCard
communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud
rate feature, and have a clock domain independent from the CPU clock, allowing USART1
and USART2 to wake up the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.
Refer to Table 10 for the differences between USART1, USART2, USART3 and USART4.
Table 10. STM32F072xx USART implementation
USART1 and
USART2
USART3 and
USART4
USART modes/features(1)
Hardware flow control for modem
X
X
X
X
X
X
X
X
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
26/124
DocID025004 Rev 2
STM32F072xx
Functional overview
Table 10. STM32F072xx USART implementation (continued)
USART1 and
USART2
USART3 and
USART4
USART modes/features(1)
Smartcard mode
X
X
X
X
X
X
X
X
X
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
X
1. X = supported.
3.18
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
2
Two standard I S interfaces (multiplexed with SPI1 and SPI2 respectively) supporting four
different audio standards can operate as master or slave at half-duplex communication
mode. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, they can output a clock for an external audio component at 256 times the sampling
frequency.
Both SPI1 and SPI2 are identical and implement the set of features shown in the following
table.
Table 11. STM32F072xx SPI/I2S implementation
SPI features(1)
SPI1 and SPI2
Hardware CRC calculation
Rx/Tx FIFO
X
X
X
X
X
NSS pulse mode
I2S mode
TI mode
1. X = supported.
DocID025004 Rev 2
27/124
28
Functional overview
STM32F072xx
3.19
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.20
3.21
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
Universal serial bus (USB)
The STM32F072xx embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up-to 1 KB (the last 256 bytes are used for CAN peripheral if
enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be
generated from the internal main PLL (the clock source must use an HSE crystal oscillator)
or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this
oscillator can be taken from the USB data stream itself (SOF signalization) which allows
crystal-less operation.
3.22
Clock recovery system (CRS)
The STM32F072xx embeds a special block which allows automatic trimming of the internal
48 MHz oscillator to guarantee its optimal accuracy over the whole device operational
range. This automatic trimming is based on the external synchronization signal, which could
be either derived from USB SOF signalization, from LSE oscillator, from an external signal
on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.23
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
28/124
DocID025004 Rev 2
STM32F072xx
Pinouts and pin descriptions
4
Pinouts and pin descriptions
Figure 3. UFBGA100 package ballout (top view)
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈꢉ
ꢈꢈ
ꢈꢀ
ꢈ
3'ꢋ
3'ꢒ
3$ꢁꢄ
3$ꢁꢁ
%227ꢃ
3%ꢐ
3'ꢐ
3%ꢀ
3'ꢀ
3'ꢄ
3$ꢁꢀ
3&ꢁꢃ
3)ꢒ
3%ꢍ
3$ꢁꢋ
3'ꢁ
3%ꢂ
3'ꢂ
3$ꢁꢂ
3&ꢁꢄ
3(ꢀ
3(ꢂ
3(ꢁ
$
%
&
3%ꢎ
3(ꢃ
966
1&
3%ꢒ
3%ꢋ
3(ꢄ
3(ꢋ
9''
3$ꢁꢃ
3&ꢎ
3'ꢃ
3&ꢁꢁ
3$ꢎ
3&ꢁꢀ
'
(
3$ꢍ
3(ꢒ
3&ꢁꢂ
3&ꢁꢋ
3)ꢃ
3&ꢐ
3&ꢒ
3&ꢍ
9%$7
3)ꢎ
966
)
966
9'',2ꢄ
3'ꢁꢂ
3'ꢁꢁ
*
9''
3'ꢁꢀ
3'ꢁꢃ
3%ꢁꢀ
3%ꢁꢄ
3)ꢁꢃ
1567
3&ꢁ
3)ꢁ
3'ꢁꢋ
3'ꢁꢄ
3%ꢁꢋ
3%ꢁꢃ
3(ꢁꢀ
+
-
9''
3&ꢄ
3$ꢄ
3$ꢀ
3&ꢃ
3)ꢄ
3&ꢂ
3'ꢎ
3%ꢁꢂ
3%ꢁꢁ
3$ꢋ
3$ꢒ
3$ꢐ
3'ꢍ
.
/
966$
3&ꢀ
3%ꢄ
3%ꢁ
3(ꢁꢃ 3(ꢁꢄ
3(ꢍ
3(ꢐ
3&ꢋ
3%ꢃ
3)ꢀ
3$ꢃ
3$ꢁ
3(ꢎ
3(ꢁꢁ
3(ꢁꢂ
3(ꢁꢋ
3$ꢂ
0
9''$
,ꢏ2ꢅSLQꢅVXSSOLHGꢅE\ꢅ9'',2ꢄ
06ꢀꢀꢁꢒꢐ9ꢀ
DocID025004 Rev 2
29/124
39
Pinouts and pin descriptions
STM32F072xx
Figure 4. LQFP100 100-pin package pinout (top view)
3(ꢄ
ꢁ
ꢐꢋ
9'',2ꢄ
966
3(ꢀ
ꢄ
ꢐꢂ
ꢐꢀ
ꢐꢄ
ꢐꢁ
ꢐꢃ
ꢒꢎ
ꢒꢍ
ꢒꢐ
ꢒꢒ
ꢒꢋ
ꢒꢂ
ꢒꢀ
ꢒꢄ
ꢒꢁ
ꢒꢃ
ꢋꢎ
ꢋꢍ
ꢋꢐ
ꢋꢒ
ꢋꢋ
ꢋꢂ
ꢋꢀ
ꢋꢄ
ꢋꢁ
3(ꢂ
ꢀ
3)ꢒ
3(ꢋ
ꢂ
3$ꢁꢀꢅꢅꢅ
3$ꢁꢄꢅꢅꢅ
3$ꢁꢁ ꢅ ꢅ
3$ꢁꢃꢅꢅꢅ
3$ꢎꢅ ꢅ
3$ꢍꢅꢅ ꢅ
3&ꢎꢅꢅ
3(ꢒ
ꢋ
9%$7
ꢒ
3&ꢁꢀ
ꢐ
3&ꢁꢂꢑ26&ꢀꢄB,1
ꢍ
3&ꢁꢋꢑ26&ꢀꢄB287
ꢎ
3)ꢎ
3)ꢁꢃ
ꢁꢃ
ꢁꢁ
ꢁꢄ
ꢁꢀ
ꢁꢂ
ꢁꢋ
ꢁꢒ
ꢁꢐ
ꢁꢍ
ꢁꢎ
ꢄꢃ
ꢄꢁ
ꢄꢄ
ꢄꢀ
ꢄꢂ
ꢄꢋ
3&ꢍꢅꢅ
3)ꢃꢑ26&B,1
3)ꢁꢑ26&B287
1567
3&ꢃ
3&ꢐꢅꢅ
3&ꢒꢅꢅ
/4)3ꢁꢃꢃ
3'ꢁꢋꢅꢅ
3'ꢁꢂꢅꢅ
3'ꢁꢀꢅꢅ
3'ꢁꢄꢅꢅ
3'ꢁꢁꢅꢅ
3'ꢁꢃꢅꢅ
3'ꢎꢅꢅ
3&ꢁ
3&ꢄ
3&ꢀ
3)ꢄ
966$
9''$
3)ꢀ
3'ꢍꢅꢅ
3%ꢁꢋꢅꢅ
3%ꢁꢂꢅꢅ
3%ꢁꢀ ꢅ
3%ꢁꢄꢅꢅ
3$ꢃ
3$ꢁ
3$ꢄ
*ꢊ0ꢋQJOꢋTVQQMJFEꢋCZꢋ7%%*0ꢀ
06ꢀꢁꢂꢁꢃ9ꢁ
30/124
DocID025004 Rev 2
STM32F072xx
Pinouts and pin descriptions
Figure 5. LQFP64 64-pin package pinout (top view)
ꢒꢂ ꢒꢀ ꢒꢄ ꢒꢁ ꢒꢃ ꢋꢎ ꢋꢍ ꢋꢐ ꢋꢒ ꢋꢋ ꢋꢂ ꢋꢀ ꢋꢄ ꢋꢁ ꢋꢃ ꢂꢎ
ꢂꢍ
9'',2ꢄ
966
9%$7
3&ꢁꢀ
3&ꢁꢂꢑ26&ꢀꢄB,1
3&ꢁꢋꢑ26&ꢀꢄB287
ꢁ
ꢄ
ꢀ
ꢂ
ꢂꢐ
ꢅꢂꢒ
ꢅꢂꢋ
ꢅꢂꢂ
ꢅꢂꢀ
ꢂꢄ
ꢂꢁ
ꢂꢃ
ꢀꢎ
ꢀꢍ
ꢀꢐ
ꢀꢒ
ꢀꢋ
ꢀꢂ
ꢀꢀ
3$ꢁꢀ
3$ꢁꢄ
3$ꢁꢁ
3$ꢁꢃ
3$ꢎ
3$ꢍ
3&ꢎ
3&ꢍ
3&ꢐ
3)ꢃꢑ26&B,1
3)ꢁꢑ26&B287
1567
3&ꢃ
ꢋ
ꢒꢅ
ꢐꢅ
ꢍꢅ
ꢎꢅ
ꢁꢃ
ꢁꢁꢅ
ꢁꢄꢅ
ꢁꢀ
ꢁꢂ
ꢁꢋ
ꢁꢒ
/4)3ꢒꢂ
3&ꢁ
3&ꢄ
3&ꢀ
966$
9''$
3$ꢃ
3$ꢁ
3&ꢒ
3%ꢁꢋ
3%ꢁꢂ
3%ꢁꢀ
3%ꢁꢄ
3$ꢄ
ꢁꢐ ꢁꢍ ꢁꢎ ꢄꢃ ꢄꢁ ꢄꢄ ꢄꢀ ꢄꢂ ꢄꢋ ꢄꢒ ꢄꢐ ꢄꢍ ꢄꢎ ꢀꢃ ꢀꢁ ꢀꢄ
*ꢊ0ꢋQJOꢋTVQQMJFEꢋCZꢋ7%%*0ꢀ
06ꢀꢁꢂꢁꢁ9ꢁ
Figure 6. LQFP48 48-pin package pinout (top view)
ꢂꢍ ꢂꢐ ꢂꢒ ꢂꢋ ꢂꢂ ꢂꢀ ꢂꢄ ꢂꢁ ꢂꢃ ꢀꢎ ꢀꢍ ꢀꢐ
ꢀꢒ
ꢀꢋ
ꢀꢂ
ꢀꢀ
ꢀꢄ
ꢀꢁ
ꢀꢃ
ꢄꢎ
ꢄꢍ
ꢄꢐ
ꢄꢒ
ꢄꢋ
9'',2ꢄ
966
ꢁ
ꢄ
ꢀ
ꢂ
9%$7
3&ꢁꢀ
3&ꢁꢂꢑ26&ꢀꢄB,1
3$ꢁꢀ
3$ꢁꢄ
3$ꢁꢁ
3$ꢁꢃ
3$ꢎ
3&ꢁꢋꢑ26&ꢀꢄB287
3)ꢃꢑ26&B,1
ꢋ
3)ꢁꢑ26&B287
1567
ꢒꢅ
ꢐꢅ
ꢍꢅ
ꢎꢅ
/4)3ꢂꢍ
3$ꢍ
966$
9''$
3%ꢁꢋ
3%ꢁꢂ
3%ꢁꢀ
3%ꢁꢄ
3$ꢃ ꢁꢃ
3$ꢁ ꢁꢁ
ꢁꢄ
3$ꢄ
ꢄꢂ
ꢁꢀ ꢁꢂ ꢁꢋ ꢁꢒ ꢁꢐ ꢁꢍ ꢁꢎ ꢄꢃ ꢄꢁ ꢄꢄ ꢄꢀ
*ꢊ0ꢋQJOꢋTVQQMJFEꢋCZꢋ7%%*0ꢀ
06ꢀꢁꢂꢁꢄ9ꢁ
DocID025004 Rev 2
31/124
39
Pinouts and pin descriptions
STM32F072xx
Figure 7. UFQFPN48 48-pin package pinout (top view)
ꢂꢍ ꢂꢐ ꢂꢒ ꢂꢋ ꢂꢂ ꢂꢀ ꢂꢄ ꢂꢁ ꢂꢃ ꢀꢎ ꢀꢍ ꢀꢐ
ꢀꢒ
ꢀꢋ
6$$)/ꢅ
633
6"!4
0#ꢁꢂ
ꢀꢂ
ꢀꢀ
0!ꢁꢂ
0!ꢁꢅ
0!ꢁꢁ
ꢀ
0#ꢁꢃꢄ/3#ꢂꢅ?).
0#ꢁꢆꢄ/3#ꢂꢅ?/54
0&ꢀꢄ/3#?).
ꢂ
ꢀꢄ
ꢀꢁ
ꢋ
0!ꢁꢀ
0!ꢉ
0&ꢁꢄ/3#?/54
ꢒ
8)4)31ꢂꢍ
ꢀꢃ
ꢄꢎ
ꢐ
.234
633!
6$$!
0!ꢀ
ꢍ
0!ꢊ
ꢄꢍ
ꢄꢐ
ꢎ
0"ꢁꢆ
0"ꢁꢃ
0"ꢁꢂ
0"ꢁꢅ
ꢁꢃ
ꢄꢒ
0!ꢁ
0!ꢅ
ꢁꢁ
ꢁꢄ
ꢄꢋ
ꢄꢂ
ꢁꢀ ꢁꢂ ꢁꢋ ꢁꢒ ꢁꢐ ꢁꢍ ꢁꢎ ꢄꢃ ꢄꢁ ꢄꢄ ꢄꢀ
*ꢊ0ꢋQJOꢋTVQQMJFEꢋCZꢋ7%%*0ꢀ
06ꢀꢄꢁꢒꢒ9ꢁ
Figure 8. WLCSP49 49-pin package ballout (bottom view)
ꢐ
ꢒ
ꢋ
ꢂ
ꢀ
ꢄ
ꢁ
9''
966 %227ꢃ
3%ꢂ
3%ꢀ
3$ꢁꢋ
3$ꢁꢂ
$
%
9%$7
1&
3%ꢍ
3%ꢎ
3%ꢋ
3%ꢒ
3$ꢁꢀ
3$ꢁꢄ
966
9'',2ꢄ
3$ꢁꢃ
3&ꢁꢋꢑ
26&ꢀꢄ
B287
3&ꢁꢂꢑ
26&ꢀꢄ
B,1
3$ꢁꢁ
&
3)ꢃꢑ
3)ꢁꢑ
3&ꢁꢀ
3$ꢄ
3%ꢐ
3$ꢀ
966
3$ꢎ
3$ꢍ
'
(
26&B,126&B287
966$
3$ꢃ
3$ꢂ
3%ꢁꢃ
3%ꢁꢄ
3%ꢁꢋ
1567
9''$
3$ꢁ
3$ꢋ
3%ꢃ
3$ꢒ
3%ꢁ
3$ꢐ
3%ꢄ
9''
3%ꢁꢂ
3%ꢁꢀ
)
3%ꢁꢁ
*
)ꢋ/ PIN SUPPLIED BY 6$$)/ꢅ
06ꢀꢄꢁꢒꢋ9ꢄ
32/124
DocID025004 Rev 2
STM32F072xx
Pinouts and pin descriptions
Table 12. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
FTf
TTa
TC
B
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
3.3 V tolerant I/O directly connected to ADC
Standard 3.3 V I/O
I/O structure
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset.
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 13. STM32F072xx pin definitions
Pin functions
Pin numbers
Pin name
Pin
(function after
Additional
functions
type
Alternate functions
reset)
B2
A1
B1
C2
1
2
3
4
-
-
-
-
-
-
-
-
-
-
-
-
PE2
PE3
PE4
PE5
I/O
I/O
I/O
I/O
FT
FT
FT
FT
TSC_G7_IO1, TIM3_ETR
TSC_G7_IO2, TIM3_CH1
TSC_G7_IO3, TIM3_CH2
TSC_G7_IO4, TIM3_CH3
-
-
-
-
WKUP3,
RTC_TAMP3
D2
E2
5
6
-
-
-
PE6
I/O
S
FT
TIM3_CH4
1
1
B7
VBAT
Backup power supply
WKUP2,
RTC_TAMP1,
RTC_TS,
(1)
(2)
C1
7
2
2
D5
PC13
I/O
TC
-
RTC_OUT
DocID025004 Rev 2
33/124
39
Pinouts and pin descriptions
STM32F072xx
Table 13. STM32F072xx pin definitions (continued)
Pin numbers
Pin functions
Pin name
(function after
reset)
Pin
type
Additional
functions
Alternate functions
(1)
(2)
PC14-OSC32_IN
(PC14)
D1
E1
8
9
3
4
3
4
C7
C6
I/O
I/O
TC
TC
-
-
OSC32_IN
PC15-
OSC32_OUT
(PC15)
(1)
(2)
OSC32_OUT
F2 10
G2 11
-
-
-
-
-
-
PF9
I/O
I/O
FT
FT
TIM15_CH1
TIM15_CH2
-
-
PF10
PF0-OSC_IN
(PF0)
F1 12
G1 13
5
6
7
5
6
7
D7
D6
E7
I
FT
FT
CRS_ SYNC
-
OSC_IN
PF1-OSC_OUT
(PF1)
O
OSC_OUT
Device reset input / internal reset output
(active low)
H2 14
H1 15
NRST
I/O RST
8
9
-
-
-
-
PC0
PC1
I/O
I/O
TTa
TTa
EVENTOUT
EVENTOUT
ADC_IN10
ADC_IN11
J2
J3
16
SPI2_MISO, I2S2_MCK,
EVENTOUT
17 10
-
-
-
-
PC2
PC3
I/O
I/O
TTa
ADC_IN12
SPI2_MOSI, I2S2_SD,
EVENTOUT
K2 18 11
J1 19
TTa
FT
ADC_IN13
WKUP8
-
-
8
9
-
-
PF2
VSSA
VDDA
PF3
I/O
S
EVENTOUT
K1 20 12
M1 21 13
E6
F7
-
Analog ground
Analog power supply
EVENTOUT
S
L1 22
-
I/O
FT
RTC_ TAMP2,
WKUP1,
COMP1_OUT,
ADC_IN0,
USART2_CTS,
TIM2_CH1_ETR,
TSC_G1_IO1,
USART4_TX
L2 23 14 10 F6
PA0
PA1
I/O
I/O
TTa
COMP1_INM6
USART2_RTS, TIM2_CH2,
TIM15_CH1N,
ADC_IN1,
M2 24 15 11 G7
TTa
TSC_G1_IO2,
COMP1_INP
USART4_RX, EVENTOUT
34/124
DocID025004 Rev 2
STM32F072xx
Pinouts and pin descriptions
Table 13. STM32F072xx pin definitions (continued)
Pin numbers
Pin functions
Pin name
(function after
reset)
Pin
type
Additional
functions
Alternate functions
ADC_IN2,
USART2_TX, TIM2_CH3,
TIM15_CH1, TSC_G1_IO3 COMP2_INM6,
WKUP4
COMP2_OUT,
K3 25 16 12 E5
L3 26 17 13 E4
PA2
PA3
I/O
I/O
TTa
TTa
USART2_RX,TIM2_CH4,
TIM15_CH2, TSC_G1_IO4
ADC_IN3,
COMP2_INP
D3 27 18
H3 28 19
-
-
-
-
VSS
VDD
S
S
Ground
Digital power supply
COMP1_INM4,
COMP2_INM4,
ADC_IN4,
SPI1_NSS, I2S1_WS,
TIM14_CH1, TSC_G2_IO1,
USART2_CK
M3 29 20 14 G6
PA4
PA5
I/O
I/O
TTa
TTa
DAC_OUT1
COMP1_INM5,
COMP2_INM5,
ADC_IN5,
SPI1_SCK, I2S1_CK, CEC,
TIM2_CH1_ETR,
K4 30 21 15 F5
TSC_G2_IO2
DAC_OUT2
SPI1_MISO, I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
TIM16_CH1,
COMP1_OUT,
TSC_G2_IO3, EVENTOUT,
USART3_CTS
L4 31 22 16 F4
PA6
PA7
I/O
I/O
TTa
TTa
ADC_IN6
SPI1_MOSI, I2S1_SD,
TIM3_CH2, TIM14_CH1,
TIM1_CH1N, TIM17_CH1,
COMP2_OUT,
M4 32 23 17 F3
ADC_IN7
TSC_G2_IO4,
EVENTOUT
K5 33 24
L5 34 25
-
-
-
-
PC4
PC5
I/O
I/O
TTa
TTa
EVENTOUT, USART3_TX
ADC_IN14
TSC_G3_IO1,
USART3_RX
ADC_IN15,
WKUP5
TIM3_CH3, TIM1_CH2N,
TSC_G3_IO2, EVENTOUT,
USART3_CK
M5 35 26 18 G5
PB0
I/O
TTa
ADC_IN8
TIM3_CH4, USART3_RTS,
TIM14_CH1, TIM1_CH3N,
TSC_G3_IO3
M6 36 27 19 G4
L6 37 28 20 G3
PB1
PB2
I/O
I/O
TTa
FT
ADC_IN9
-
TSC_G3_IO4
DocID025004 Rev 2
35/124
39
Pinouts and pin descriptions
STM32F072xx
Table 13. STM32F072xx pin definitions (continued)
Pin numbers
Pin functions
Pin name
(function after
reset)
Pin
type
Additional
functions
Alternate functions
M7 38
L7 39
M8 40
L8 41
M9 42
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE7
PE8
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
-
-
-
-
-
PE9
PE10
PE11
SPI1_NSS, I2S1_WS,
TIM1_CH3N
L9 43
M10 44
M11 45
M12 46
-
-
-
-
-
-
-
-
-
-
-
-
PE12
PE13
PE14
PE15
I/O
I/O
I/O
I/O
FT
FT
FT
FT
-
-
-
-
SPI1_SCK, I2S1_CK,
TIM1_CH3
SPI1_MISO, I2S1_MCK,
TIM1_CH4
SPI1_MOSI, I2S1_SD,
TIM1_BKIN
SPI2_SCK, I2C2_SCL,
USART3_TX, CEC,
TSC_SYNC, TIM2_CH3
L10 47 29 21 E3
L11 48 30 22 G2
PB10
PB11
I/O
I/O
FT
FT
-
-
USART3_RX, TIM2_CH4,
EVENTOUT, TSC_G6_IO1,
I2C2_SDA
F12 49 31 23 D3
G12 50 32 24 F2
VSS
VDD
S
S
Ground
Digital power supply
TIM1_BKIN, TIM15_BKIN,
SPI2_NSS, I2S2_WS,
USART3_CK,
L12 51 33 25 E2
PB12
I/O
FT
-
TSC_G6_IO2,
EVENTOUT
SPI2_SCK, I2S2_CK,
I2C2_SCL, USART3_CTS,
TIM1_CH1N, TSC_G6_IO3
K12 52 34 26 G1
K11 53 35 27 F1
PB13
PB14
I/O
I/O
FTf
FTf
-
-
SPI2_MISO, I2S2_MCK,
I2C2_SDA, USART3_RTS,
TIM1_CH2N, TIM15_CH1,
TSC_G6_IO4
36/124
DocID025004 Rev 2
STM32F072xx
Pinouts and pin descriptions
Table 13. STM32F072xx pin definitions (continued)
Pin numbers
Pin functions
Pin name
(function after
reset)
Pin
type
Additional
functions
Alternate functions
SPI2_MOSI, I2S2_SD,
TIM1_CH3N,
WKUP7,
RTC_REFIN
K10 54 36 28 E1
PB15
I/O
FT
TIM15_CH1N,
TIM15_CH2
K9 55
K8 56
J12 57
J11 58
-
-
-
-
-
-
-
-
-
-
-
-
PD8
PD9
I/O
I/O
I/O
I/O
FT
FT
FT
FT
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
-
-
-
-
PD10
PD11
USART3_RTS,
TSC_G8_IO1
J10 59
-
-
-
PD12
I/O
FT
-
H12 60
H11 61
H10 62
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD13
PD14
PD15
PC6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
FT
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4, CRS_SYNC
TIM3_CH1
-
-
-
-
-
-
-
(3)
(3)
(3)
(3)
E12 63 37
E11 64 38
E10 65 39
D12 66 40
PC7
TIM3_CH2
PC8
TIM3_CH3
PC9
TIM3_CH4
USART1_CK, TIM1_CH1,
EVENTOUT, MCO,
CRS_SYNC
(3)
(3)
(3)
(3)
(3)
D11 67 41 29 D1
D10 68 42 30 D2
C12 69 43 31 C2
B12 70 44 32 C1
PA8
PA9
I/O
I/O
I/O
I/O
FT
FT
FT
FT
-
USART1_TX, TIM1_CH2,
TIM15_BKIN,
-
TSC_G4_IO1
USART1_RX, TIM1_CH3,
TIM17_BKIN,
PA10
PA11
-
TSC_G4_IO2
CAN_RX, USART1_CTS,
TIM1_CH4, COMP1_OUT,
TSC_G4_IO3, EVENTOUT
USB_DM
CAN_TX, USART1_RTS,
TIM1_ETR, COMP2_OUT,
TSC_G4_IO4, EVENTOUT
A12 71 45 33 C3
A11 72 46 34 B3
PA12
PA13
I/O
I/O
FT
FT
USB_DP
-
(3)
(4)
IR_OUT, SWDIO,
USB_NOE
DocID025004 Rev 2
37/124
39
Pinouts and pin descriptions
STM32F072xx
Table 13. STM32F072xx pin definitions (continued)
Pin numbers
Pin functions
Pin name
(function after
reset)
Pin
type
Additional
functions
Alternate functions
(3)
C11 73
-
-
-
PF6
VSS
I/O
S
FT
-
-
F11 74 47 35 B1
G11 75 48 36 B2
Ground
Digital power supply
VDDIO2
S
(3)
(4)
A10 76 49 37 A1
PA14
PA15
I/O
I/O
FT
FT
USART2_TX, SWCLK
-
-
SPI1_NSS, I2S1_WS,
USART2_RX,
USART4_RTS,
TIM2_CH1_ETR,
EVENTOUT
(3)
A9 77 50 38 A2
(3)
(3)
B11 78 51
C10 79 52
-
-
-
-
PC10
PC11
I/O
I/O
FT
FT
USART3_TX, USART4_TX
USART3_RX, USART4_RX
-
-
USART3_CK,
USART4_CK
(3)
(3)
B10 80 53
-
-
-
-
PC12
PD0
I/O
I/O
FT
FT
-
-
SPI2_NSS, I2S2_WS,
CAN_RX
C9 81
B9 82
-
-
SPI2_SCK, I2S2_CK,
CAN_TX
(3)
(3)
-
-
-
-
-
-
PD1
PD2
PD3
I/O
I/O
I/O
FT
FT
FT
-
-
-
C8 83 54
USART3_RTS, TIM3_ETR
SPI2_MISO, I2S2_MCK,
USART2_CTS
B8 84
B7 85
-
-
SPI2_MOSI, I2S2_SD,
USART2_RTS
-
-
PD4
I/O
FT
-
A6 86
B6 87
A5 88
-
-
-
-
-
-
-
-
-
PD5
PD6
PD7
I/O
I/O
I/O
FT
FT
FT
USART2_TX
USART2_RX
USART2_CK
-
-
-
SPI1_SCK, I2S1_CK,
TIM2_CH2, TSC_G5_IO1,
EVENTOUT
A8 89 55 39 A3
A7 90 56 40 A4
C5 91 57 41 B4
PB3
PB4
PB5
I/O
I/O
I/O
FT
FT
FT
-
SPI1_MISO, I2S1_MCK,
TIM17_BKIN, TIM3_CH1,
TSC_G5_IO2, EVENTOUT
-
SPI1_MOSI, I2S1_SD,
I2C1_SMBA, TIM16_BKIN,
TIM3_CH2
WKUP6
38/124
DocID025004 Rev 2
STM32F072xx
Pinouts and pin descriptions
Table 13. STM32F072xx pin definitions (continued)
Pin numbers
Pin functions
Pin name
(function after
reset)
Pin
type
Additional
functions
Alternate functions
I2C1_SCL, USART1_TX,
TIM16_CH1N,
B5 92 58 42 C4
PB6
PB7
I/O
I/O
FTf
FTf
-
-
TSC_G5_I03
I2C1_SDA, USART1_RX,
USART4_CTS,
B4 93 59 43 D4
TIM17_CH1N,
TSC_G5_IO4
A4 94 60 44 A5
A3 95 61 45 B5
BOOT0
PB8
I
B
Boot memory selection
I2C1_SCL, CEC,
TIM16_CH1, TSC_SYNC,
CAN_RX
I/O
FTf
-
-
SPI2_NSS, I2S2_WS,
I2C1_SDA, IR_OUT,
TIM17_CH1, EVENTOUT,
CAN_TX
B3 96 62 46 C5
PB9
I/O
FTf
C3 97
A2 98
-
-
-
-
-
-
PE0
PE1
VSS
VDD
I/O
I/O
S
FT
FT
EVENTOUT, TIM16_CH1
EVENTOUT, TIM17_CH1
Ground
-
-
D3 99 63 47 A6
C4 100 64 48 A7
S
Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of
current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends
on the content of the RTC registers which are not reset by the system reset. For details on how to manage
these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual.
3. PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1
and PD2 I/Os are supplied by VDDIO2.
4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on
the SWDIO pin and the internal pull-down on the SWCLK pin are activated.
DocID025004 Rev 2
39/124
39
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PA0
PA1
USART2_CTS TIM2_CH1_ETR TSC_G1_IO1
USART4_TX
COMP1_OUT
EVENTOUT
TIM15_CH1
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
CEC
TIM2_CH2
TIM2_CH3
TIM2_CH4
TSC_G1_IO2 USART4_RX TIM15_CH1N
TSC_G1_IO3
PA2
COMP2_OUT
PA3
TIM15_CH2
TSC_G1_IO4
PA4
SPI1_NSS, I2S1_WS
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
MCO
TSC_G2_IO1
TIM2_CH1_ETR TSC_G2_IO2
TIM14_CH1
PA5
PA6
TIM3_CH1
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
USB_NOE
TSC_G2_IO3 USART3_CTS TIM16_CH1
EVENTOUT COMP1_OUT
EVENTOUT COMP2_OUT
PA7
TIM3_CH2
TSC_G2_IO4
EVENTOUT
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
TIM14_CH1
CRS_SYNC
TIM17_CH1
PA8
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
USART1_RTS
IR_OUT
PA9
TIM15_BKIN
PA10
PA11
PA12
PA13
PA14
PA15
TIM17_BKIN
EVENTOUT
CAN_RX
CAN_TX
COMP1_OUT
COMP2_OUT
EVENTOUT
SWDIO
SWCLK
USART2_TX
USART2_RX
SPI1_NSS, I2S1_WS
TIM2_CH1_ETR EVENTOUT USART4_RTS
Table 15. Alternate functions selected through GPIOB_AFR registers for port B
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
PB0
PB1
EVENTOUT
TIM14_CH1
TIM3_CH3
TIM3_CH4
TIM1_CH2N
TIM1_CH3N
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G5_IO1
TSC_G5_IO2
I2C1_SMBA
TSC_G5_IO3
TSC_G5_IO4
TSC_SYNC
USART3_CK
USART3_RTS
PB2
PB3
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
USART1_TX
EVENTOUT
TIM3_CH1
TIM3_CH2
I2C1_SCL
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
EVENTOUT
TIM2_CH2
EVENTOUT
TIM16_BKIN
TIM16_CH1N
TIM17_CH1N
TIM16_CH1
TIM17_CH1
TIM2_CH3
PB4
TIM17_BKIN
PB5
PB6
PB7
USART1_RX
USART4_CTS
CAN_RX
PB8
CEC
PB9
IR_OUT
EVENTOUT
TSC_SYNC
CAN_TX
SPI2_NSS, I2S2_WS
SPI2_SCK, I2S2_CK
PB10
PB11
PB12
PB13
PB14
PB15
CEC
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
EVENTOUT
TIM2_CH4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TIM15_CH1N
SPI2_NSS, I2S2_WS
SPI2_SCK, I2S2_CK
SPI2_MISO, I2S2_MCK
SPI2_MOSI, I2S2_SD
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
TIM15_BKIN
I2C2_SCL
I2C2_SDA
TIM15_CH1
TIM15_CH2
STM32F072xx
Table 16. Alternate functions selected through GPIOC_AFR registers for port C
Pin name
AF0
AF1
PC0
PC1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TSC_G3_IO1
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
USART4_TX
USART4_RX
USART4_CK
-
-
-
PC2
SPI2_MISO, I2S2_MCK
PC3
SPI2_MOSI, I2S2_SD
PC4
USART3_TX
PC5
USART3_RX
PC6
-
PC7
-
PC8
-
PC9
-
PC10
PC11
PC12
PC13
PC14
PC15
USART3_TX
USART3_RX
USART3_CK
-
-
-
-
-
Table 17. Alternate functions selected through GPIOD_AFR registers for port D
Pin name
AF0
AF1
PD0
PD1
CAN_RX
CAN_TX
SPI2_NSS, I2S2_WS
SPI2_SCK, I2S2_CK
PD2
TIM3_ETR
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
-
USART3_RTS
PD3
SPI2_MISO, I2S2_MCK
PD4
SPI2_MOSI, I2S2_SD
PD5
-
PD6
-
PD7
-
PD8
-
PD9
-
PD10
PD11
PD12
PD13
PD14
PD15
-
-
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
-
CRS_SYNC
42/124
DocID025004 Rev 2
STM32F072xx
Table 18. Alternate functions selected through GPIOE_AFR registers for port E
Pin name
AF0
AF1
PE0
PE1
TIM16_CH1
TIM17_CH1
TIM3_ETR
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
EVENTOUT
EVENTOUT
PE2
TSC_G7_IO1
PE3
TSC_G7_IO2
PE4
TSC_G7_IO3
PE5
TSC_G7_IO4
PE6
-
PE7
-
PE8
-
PE9
-
PE10
PE11
PE12
PE13
PE14
PE15
-
-
SPI1_NSS, I2S1_WS
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
Table 19. Alternate functions available on port F
AF
Pin name
PF0
PF1
PF2
PF3
PF6
PF9
PF10
CRS_SYNC
-
EVENTOUT
EVENTOUT
-
TIM15_CH1
TIM15_CH2
DocID025004 Rev 2
43/124
43
Memory mapping
STM32F072xx
5
Memory mapping
Figure 9. STM32F072xx memory map
ꢀX&&&& &&&&
ꢀXꢃꢊꢀꢀ ꢁꢈ&&
ꢀXꢃꢊꢀꢀ ꢀꢀꢀꢀ
!("ꢅ
ꢈ
ꢀX%ꢀꢁꢀ ꢀꢀꢀꢀ
#ORTEXꢄ -ꢉ )NTERNAL
0ERIPHERALS
ꢀX%ꢀꢀꢀ ꢀꢀꢀꢀ
RESERVED
ꢇ
ꢀX#ꢀꢀꢀ ꢀꢀꢀꢀ
ꢀXꢃꢀꢀꢅ ꢃꢂ&&
ꢀXꢃꢀꢀꢅ ꢀꢀꢀꢀ
")#ꢈ
ꢆ
RESERVED
ꢀX!ꢀꢀꢀ ꢀꢀꢀꢀ
ꢀXꢃꢀꢀꢁ ꢊꢀꢀꢀ
ꢀXꢃꢀꢀꢁ ꢀꢀꢀꢀ
"1#
ꢃ
ꢀXꢁ&&& &&&&
/PTION BYTES
ꢀXꢁ&&& &ꢊꢀꢀ
ꢀXꢊꢀꢀꢀ ꢀꢀꢀꢀ
3YSTEM MEMORY
RESERVED
ꢀXꢃꢀꢀꢀ ꢊꢀꢀꢀ
ꢀXꢃꢀꢀꢀ ꢀꢀꢀꢀ
ꢂ
ꢀXꢁ&&& #ꢊꢀꢀ
"1#
ꢀXꢇꢀꢀꢀ ꢀꢀꢀꢀ
RESERVED
ꢅ
0ERIPHERALS
ꢀXꢃꢀꢀꢀ ꢀꢀꢀꢀ
ꢀXꢀꢊꢀꢅ ꢀꢀꢀꢀ
ꢁ
&LASH MEMORY
32!-
#/$%
ꢀXꢅꢀꢀꢀ ꢀꢀꢀꢀ
ꢉYꢉꢆꢉꢉꢋꢉꢉꢉꢉ
RESERVED
ꢀ
ꢀXꢀꢀꢀꢅ ꢀꢀꢀꢀ
'MBTIꢌꢋTZTUFNꢋNFNPSZ
PSꢋ43".ꢌꢋEFQFOEJOHꢋPO
#005ꢋDPOGJHVSBUJPO
ꢀXꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀXꢀꢀꢀꢀ ꢀꢀꢀꢀ
2ESERVED
-3ꢂꢁꢃꢀꢉ6ꢁ
44/124
DocID025004 Rev 2
STM32F072xx
Bus
Memory mapping
Table 20. STM32F072xx peripheral register boundary addresses
Boundary address
Size
Peripheral
0x4800 1800 - 0x5FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
0x4001 5C00 - 0x4001 7FFF
0x4001 5800 - 0x4001 5BFF
0x4001 4C00 - 0x4001 57FF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0x4001 0800 - 0x4001 23FF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 8000 - 0x4000 FFFF
~384 MB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
~128 MB
1 KB
3 KB
1 KB
3 KB
1 KB
3 KB
1 KB
3 KB
1 KB
32 KB
9 KB
1 KB
3 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
7 KB
1 KB
1 KB
32 KB
Reserved
GPIOF
GPIOE
GPIOD
AHB2
GPIOC
GPIOB
GPIOA
Reserved
TSC
Reserved
CRC
Reserved
FLASH Interface
Reserved
RCC
AHB1
Reserved
DMA
Reserved
Reserved
DBGMCU
Reserved
TIM17
TIM16
TIM15
Reserved
USART1
Reserved
SPI1/I2S1
TIM1
APB
Reserved
ADC
Reserved
EXTI
SYSCFG + COMP
Reserved
DocID025004 Rev 2
45/124
46
Memory mapping
STM32F072xx
Table 20. STM32F072xx peripheral register boundary addresses (continued)
Bus
Boundary address
Size
Peripheral
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 3C00 - 0x4000 43FF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1800 - 0x4000 1FFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0800 - 0x4000 0FFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
2 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
2 KB
1 KB
1 KB
2 KB
1 KB
1 KB
Reserved
CEC
DAC
PWR
CRS
Reserved
BxCAN
USB/CAN RAM
USB
I2C2
I2C1
Reserved
USART4
USART3
USART2
Reserved
SPI2
APB
Reserved
IWDG
WWDG
RTC
Reserved
TIM14
Reserved
TIM7
TIM6
Reserved
TIM3
TIM2
46/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3.3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
-#5 PIN
-#5 PIN
&ꢅ ꢅꢋꢃꢅS)
6
).
-3ꢁꢉꢅꢁꢀ6ꢁ
-3ꢁꢉꢅꢁꢁ6ꢁ
DocID025004 Rev 2
47/124
100
Electrical characteristics
STM32F072xx
6.1.6
Power supply scheme
Figure 12. Power supply scheme
9%$7
%DFNXSꢅFLUFXLWU\
ꢈ/6(ꢇꢅ57&ꢇ
%DFNXSꢅUHJLVWHUVꢊ
ꢁꢆꢒꢋꢅ±ꢅꢀꢆꢒꢅ9
3RZHUꢅVZLWFK
9''
9&25(
ꢀꢅ[ꢅ9''
5HJXODWRU
9'',2ꢁ
287
.HUQHOꢅORJLF
ꢈ&38ꢇꢅ'LJLWDO
ꢓꢅ0HPRULHVꢊ
,2
ꢀꢅ[ꢅꢁꢃꢃꢅQ)
ꢉꢁꢅ[ꢅꢂꢆꢐꢅ)
*3,2V
ORJLF
,1
ꢀꢅ[ꢅ966
9'',2ꢄ
9'',2ꢄ
9'',2ꢄ
287
ꢁꢃꢃꢅQ)
ꢉꢂꢆꢐꢅ)ꢅ
,2
*3,2V
ORJLF
,1
966
9''$
9''$
$QDORJꢌ
ꢈ5&Vꢇꢅ3//ꢇꢅ«ꢊ
ꢁꢃꢅQ)
ꢉꢁꢅ)
$'&ꢏ
'$&
95()ꢉ
95()ꢑ
966$
06Yꢀꢄꢁꢎꢃ9ꢁ
Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
48/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
6.1.7
Current consumption measurement
Figure 13. Current consumption measurement scheme
*
%%@7#"5
6
"!4
)
$$
6
$$
6
$$)/ꢅ
)
$$!
6
$$!
-3ꢂꢁꢉꢉꢉ6ꢁ
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics,
Table 22: Current characteristics and Table 23: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
(1)
Table 21. Voltage characteristics
Symbol
DDx–VSS
Ratings
Min
Max
Unit
External main supply voltage
(including VDDA, VDD, VDDIO2 and VBAT
V
–0.3
4.0
V
)
VDD–VDDA Allowed voltage difference for VDD > VDDA
-
0.4
V
V
Input voltage on FT and FTf pins
VSS 0.3
VSS 0.3
VSS 0.3
-
VDDIOx + 4.0
(2)
VIN
Input voltage on TTa pins
4.0
4.0
50
V
Input voltage on any other pin
V
|VDDx
|
Variations between different VDD power pins
mV
Variations between all the different ground
pins
|VSSx VSS
|
-
50
mV
Electrostatic discharge voltage
(human body model)
see Section 6.3.12: Electrical
sensitivity characteristics
VESD(HBM)
1. All main power (V , V
) and ground (V , V
) pins must always be connected to the external power
SSA
DD
DDA
SS
supply, in the permitted range.
V maximum must always be respected. Refer to Table 22: Current characteristics for the maximum
IN
2.
allowed injected current values.
DocID025004 Rev 2
49/124
100
Electrical characteristics
STM32F072xx
Table 22. Current characteristics
Ratings
Symbol
Max.
Unit
IVDD
IVSS
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
120
-120
100
-100
25
mA
IVDD(PIN)
IVSS(PIN)
IIO(PIN)
Output current source by any I/O and control pin
Total output current sunk by sum of all IOs and control pins(2)
Total output current sourced by sum of all IOs and control pins(2)
Total output current sourced by sum of all IOs supplied by VDDIO2
Injected current on FT, FTf and B pins
-25
80
IIO(PIN)
-80
-40
-5/+0(4)
(3)
IINJ(PIN)
Injected current on TC and RST pin
± 5
Injected current on TTa pins(5)
± 5
IINJ(PIN)
Total injected current (sum of all I/O and control pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by V > V
while a negative injection is induced by V < V . I
must never be
IN
DDIOx
IN
SS INJ(PIN)
exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by V > V
. Negative injection disturbs the analog performance of the
DDA
IN
(2)
device. See note
below Table 60: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum I
is the absolute sum of the positive and
INJ(PIN)
negative injected currents (instantaneous values).
Table 23. Thermal characteristics
Ratings
Symbol
Value
Unit
TSTG
TJ
Storage temperature range
Maximum junction temperature
–65 to +150
150
°C
°C
50/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 24. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK
VDD
Internal AHB clock frequency
Internal APB clock frequency
Standard operating voltage
0
0
2
48
48
MHz
3.6
V
V
Must not be supplied if VDD
is not present
VDDIO2
I/O supply voltage
1.65
2
3.6
3.6
3.6
Analog operating voltage
(ADC and DAC not used)
Must have a potential equal
to or higher than VDD
VDDA
V
V
Analog operating voltage
(ADC and DAC used)
2.4
VBAT
Backup operating voltage
1.65
–0.3
–0.3
–0.3
0
3.6
VDDIOx+0.3
VDDA+0.3
5.5(1)
9.0
TC and RST I/O
TTa I/O
VIN
PD
TA
I/O input voltage
V
FT and FTf I/O
BOOT0
UFBGA100
-
364
LQFP100
-
476
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(2)
LQFP64
-
455
mW
LQFP48
-
370
UFQFPN48
-
625
WLCSP49
-
408
Maximum power dissipation
Low power dissipation(3)
Maximum power dissipation
Low power dissipation(3)
Suffix 6 version
Suffix 7 version
–40
–40
–40
–40
–40
–40
85
Ambient temperature for the
suffix 6 version
°C
°C
°C
105
105
Ambient temperature for the
suffix 7 version
125
105
TJ
Junction temperature range
125
1. To sustain a voltage higher than V
+0.3 V, the internal pull-up/pull-down resistors must be disabled.
DDIOx
2. If T is lower, higher P values are allowed as long as T does not exceed T (see Section 7.2: Thermal characteristics).
Jmax
A
D
J
3. In low power dissipation state, T can be extended to this range as long as T does not exceed T (see Section 7.2:
Jmax
A
J
Thermal characteristics).
DocID025004 Rev 2
51/124
100
Electrical characteristics
STM32F072xx
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 25 are derived from tests performed under the ambient
temperature condition summarized in Table 24.
Table 25. Operating conditions at power-up / power-down
Symbol
Parameter
VDD rise time rate
VDD fall time rate
VDDA rise time rate
VDDA fall time rate
Conditions
Min
0
Max
Unit
tVDD
20
0
μs/V
tVDDA
20
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 26 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions.
Table 26. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Falling edge(2)
Rising edge
1.96(3)
2.00
-
1.80
1.84(3)
-
1.88
1.92
40
V
V
Power on/power down
reset threshold
(1)
VPOR/PDR
VPDRhyst
PDR hysteresis
mV
ms
(4)
tRSTTEMPO
Reset temporization
1.50
2.50
4.50
1. The PDR detector monitors V and also V
(if kept enabled in the option bytes). The POR detector
DD
DDA
monitors only V
.
DD
2. The product behavior is guaranteed by design down to the minimum V
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
value.
POR/PDR
Table 27. Programmable voltage detector characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.1
2
2.18
2.08
2.28
2.18
2.38
2.28
2.48
2.38
2.26
2.16
2.37
2.27
2.48
2.38
2.58
2.48
V
V
V
V
V
V
V
V
VPVD0
PVD threshold 0
2.19
2.09
2.28
2.18
2.38
2.28
VPVD1
VPVD2
VPVD3
PVD threshold 1
PVD threshold 2
PVD threshold 3
52/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Table 27. Programmable voltage detector characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.47
2.37
2.57
2.47
2.66
2.56
2.76
2.66
-
2.58
2.48
2.68
2.58
2.78
2.68
2.88
2.78
100
2.69
2.59
2.79
2.69
2.9
2.8
3
V
V
VPVD4
PVD threshold 4
V
VPVD5
VPVD6
VPVD7
PVD threshold 5
PVD threshold 6
PVD threshold 7
V
V
V
V
2.9
-
V
(1)
VPVDhyst
IDD(PVD)
PVD hysteresis
mV
μA
PVD current consumption
-
0.15 0.26(1)
1. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 28 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions.
Table 28. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ Max
Unit
–40 °C < TA < +105 °C
–40 °C < TA < +85 °C
1.16
1.16
1.2 1.25
V
V
Internal reference voltage
V
REFINT
1.2 1.24(1)
ADC sampling time when
reading the internal
reference voltage
4(2)
tS_vrefint
-
-
μs
Internal reference voltage
VREFINT spread over the
10(2)
VDDA = 3 V
-
-
-
-
mV
temperature range
100(2)
TCoeff
Temperature coefficient
ppm/°C
1. Data based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
DocID025004 Rev 2
53/124
100
Electrical characteristics
STM32F072xx
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f
frequency:
HCLK
–
–
0 wait state and Prefetch OFF from 0 to 24 MHz
1 wait state and Prefetch ON above 24 MHz
= f
When the peripherals are enabled f
PCLK
HCLK
The parameters given in Table 29 to Table 34 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 24: General
operating conditions.
Table 29. Typical and maximum current consumption from V supply at V = 3.6 V
DD
DD
All peripherals enabled(1)
All peripherals disabled
(2)
(2)
Max @ TA
Max @ TA
Conditions
fHCLK
Unit
Typ
Typ
25 °C
85 °C 105 °C
25 °C 85 °C 105 °C
HSI48
48 MHz 24.3
48 MHz 24.1
32 MHz 16.0
24 MHz 12.3
26.9
26.8
18.3
13.7
5.25
1.39
27.1
18.2
14.0
27.2
27.0
18.6
14.3
5.28
1.58
27.6
18.9
14.4
27.9
27.7
19.2
14.7
5.61
1.87
27.8
19.3
14.8
13.1 14.8
13.0 14.6
8.76 9.56
7.36 7.94
2.89 3.17
0.93 1.06
12.9 14.7
8.82 9.69
7.31 7.92
14.9
14.8
9.73
8.37
3.26
1.15
14.9
9.83
8.34
15.5
15.4
10.6
8.81
3.34
1.34
15.5
10.7
8.75
HSEbypass,
PLL on
8 MHz
1 MHz
4.52
1.25
HSEbypass,
PLL off
IDD
mA
48 MHz 24.1
32 MHz 16.1
24 MHz 12.4
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
4.52
5.25
5.35
5.61
2.87 3.16
3.25
3.33
54/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Table 29. Typical and maximum current consumption from V supply at V = 3.6 V (continued)
DD
DD
All peripherals enabled(1)
All peripherals disabled
(2)
(2)
Max @ TA
Max @ TA
Conditions
fHCLK
Unit
Typ
Typ
25 °C
85 °C 105 °C
25 °C 85 °C 105 °C
HSI48
48 MHz 23.1
25.4
25.8
25.7
17.8
13.5
4.89
0.92
25.0
17.7
13.6
26.6
12.8 13.5
13.7
13.9
48 MHz 23.0 25.3(3)
26.5(3) 12.6 13.3(3) 13.5 13.8(3)
HSEbypass,
PLL on
32 MHz 15.4
24 MHz 11.4
17.3
12.9
4.6
18.3
13.7
5.25
1.15
25.2
18.2
13.9
7.96 8.92
6.48 8.04
9.17
8.23
2.35
0.59
13.9
9.16
8.21
9.73
8.41
2.94
0.82
14.0
9.94
8.47
8 MHz
1 MHz
4.21
0.78
2.07
2.3
HSEbypass,
PLL off
0.9
0.36 0.48
12.6 13.7
8.05 8.85
6.49 8.06
48 MHz 23.1
32 MHz 15.4
24 MHz 11.5
24.5
17.4
13.0
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
4.34
4.75
5.03
5.41
2.11
2.36
2.38
2.98
IDD
mA
HSI48
48 MHz 15.1
16.6
16.8
16.7
11.6
8.71
3.26
0.55
17.3
11.6
8.87
17.5
3.08 3.43
3.56
3.61
48 MHz 15.0 16.5(3)
17.3(3) 2.93 3.28(3) 3.41 3.46(3)
HSEbypass,
PLL on
32 MHz
9.9
11.4
8.17
3.09
0.54
17.2
11.3
8.45
11.9
8.82
3.66
0.67
17.9
11.7
8.95
2.0
2.24
2.32
1.88
0.91
0.41
3.41
2.44
1.9
2.49
1.9
24 MHz 7.43
1.63 1.82
0.76 0.88
0.28 0.39
3.04 3.37
8 MHz
1 MHz
2.83
0.42
0.93
0.43
3.46
2.65
1.93
HSEbypass,
PLL off
48 MHz 15.0
32 MHz 9.93
24 MHz 7.53
HSI clock,
PLL on
2.11
2.35
1.64 1.83
HSI clock,
PLL off
8 MHz
2.95
3.24
3.41
3.8
0.8
0.92
0.94
0.97
1. USB is kept disabled as this IP functions only with a 48 MHz clock.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of I and I
).
DD
DDA
DocID025004 Rev 2
55/124
100
Electrical characteristics
STM32F072xx
Table 30. Typical and maximum current consumption from the V
supply
DDA
V
= 2.4 V
V
= 3.6 V
DDA
DDA
Para-
meter
Conditions
(2)
(2)
Symbol
fHCLK
Unit
Max @ TA
25 °C 85 °C 105 °C
Max @ TA
25 °C 85 °C 105 °C
(1)
Typ
Typ
HSI48
48 MHz 311
48 MHz 152 170(3)
32 MHz 105 121
24 MHz 81.9 95.9
326
334
178
126
99.5
4.3
343
322
337
345
354
200(3)
138
182(3) 165 184(3) 196
HSE
bypass,
PLL on
128
101
4.6
113
129
136
107
5.2
Supply
current in
Run or
Sleep
88.7 102
108
HSE
bypass,
PLL off
8 MHz
1 MHz
2.7
2.7
3.8
3.8
3.6
3.6
4.7
4.7
5.5
mode,
code
IDDA
μA
4.3
4.6
5.2
5.5
executing
from
Flash or
RAM
48 MHz 223
32 MHz 176
24 MHz 154
244
195
171
255
203
178
260
206
181
245
193
168
265
212
185
279
221
192
284
224
195
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz 74.2 83.4
86.4
87.3
83.4 92.5
95.3
96.6
1. Current consumption from the V
supply is independent of whether the digital peripherals are enabled or disabled, being
DDA
in Run or Sleep mode or executing from Flash or RAM. Furthermore, when the PLL is off, I
frequency.
is independent from the
DDA
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of I and I
).
DDA
DD
56/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Table 31. Typical and maximum consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA
)
Max(1)
Sym-
bol
Para-
meter
Conditions
Unit
TA =
TA =
TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 °C 85 °C 105 °C
Regulator in run
mode, all
oscillators OFF
15.4 15.5 15.6 15.7 15.8 15.9 23(2)
49
33
68(2)
51(2)
Supply
current in
Stop
Regulator in low-
power mode, all
oscillators OFF
8(2)
mode
3.2
3.3
3.4
3.5
3.6
3.7
IDD
LSI ON and IWDG
ON
Supply
current in
Standby
mode
0.8
0.6
1.0
0.7
1.1
0.9
1.2
0.9
1.3
1.0
1.4
1.1
-
-
-
LSI OFF and IWDG
OFF
2.1(2)
2.6
3.1(2)
Regulator in
run mode, all
oscillators
OFF
2.1
2.1
2.2
2.2
2.3
2.3
2.5
2.5
2.6
2.6
2.8
2.8
3.5(2)
3.6
3.6
4.6(2)
Supply
current in
Stop
Regulator in
low-power
mode, all
oscillators
OFF
mode
3.5(2)
4.6(2)
μA
LSI ON and
IWDG ON
Supply
current in
Standby
mode
2.5
1.9
2.7
2.1
2.8
2.2
3.0
2.3
3.2
2.5
3.5
2.6
-
-
-
LSI OFF and
IWDG OFF
3.5(2)
3.6
4.6(2)
IDDA
Regulator in
run mode, all
oscillators
OFF
1.3
1.3
1.3
1.3
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
-
-
-
-
-
-
Supply
current in
Stop
Regulator in
low-power
mode, all
oscillators
OFF
mode
LSI ON and
IWDG ON
Supply
current in
Standby
mode
1.7
1.2
1.8
1.2
1.9
1.2
2.0
1.3
2.1
1.3
2.2
1.4
-
-
-
-
-
-
LSI OFF and
IWDG OFF
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production (using one common test limit for sum of I and I
).
DDA
DD
DocID025004 Rev 2
57/124
100
Electrical characteristics
STM32F072xx
Table 32. Typical and maximum current consumption from the V
supply
BAT
Typ @ VBAT
Max(1)
Symbol Parameter
Conditions
Unit
TA =
TA =
TA =
25 °C 85 °C 105 °C
LSE & RTC ON; “Xtal
mode”: lower driving
capability;
0.5 0.6 0.7 0.8 1.1 1.2 TBD
TBD
TBD
TBD
TBD
RTC
domain
supply
current
LSEDRV[1:0] = '00'
IDD VBAT
_
μA
LSE & RTC ON; “Xtal
mode” higher driving
capability;
0.8 0.9 1.1 1.2 1.4 1.6 TBD
LSEDRV[1:0] = '11'
1. Data based on characterization results, not tested in production.
Typical current consumption
The MCU is placed under the following conditions:
V
=V
=3.3 V
DDA
DD
All I/O pins are in analog input configuration
The Flash access time is adjusted to f
frequency:
HCLK
–
–
0 wait state and Prefetch OFF from 0 to 24 MHz
1 wait state and Prefetch ON above 24 MHz
= f
When the peripherals are enabled, f
PCLK
HCLK
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
58/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Table 33. Typical current consumption in Run mode, code with data processing
running from Flash
Typ
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals
enabled
Peripherals
disabled
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
23.5
18.3
16.0
12.3
8.6
13.5
10.5
9.6
7.6
Supply current in Run
mode from VDD
supply
5.3
IDD
mA
4.8
3.1
4 MHz
3.1
2.1
2 MHz
2.1
1.6
Running from
HSE crystal
clock 8 MHz,
code
executing
from Flash
1 MHz
1.6
1.3
500 KHz
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
1.3
1.2
163.3
124.3
111.9
87.1
62.5
2.5
163.3
124.3
111.9
87.1
62.5
2.5
Supply current in Run
mode from VDDA
supply
IDDA
μA
4 MHz
2.5
2.5
2 MHz
2.5
2.5
1 MHz
2.5
2.5
500 KHz
2.5
2.5
DocID025004 Rev 2
59/124
100
Electrical characteristics
STM32F072xx
Table 34. Typical current consumption in Sleep mode, code running from Flash
Typ
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals Peripherals
enabled
disabled
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
14.6
11.1
10.0
7.8
3.5
2.9
2.7
2.2
Supply current in
Sleep mode from VDD
supply
5.5
1.7
IDD
mA
3.1
1.2
4 MHz
2.2
1.1
2 MHz
1.6
1.0
1 MHz
1.4
1.0
Running from
HSE crystal
clock 8 MHz,
code executing
from Flash
500 KHz
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
1.2
1.0
163.3
124.3
111.9
87.1
62.5
2.5
163.3
124.3
111.9
87.1
62.5
2.5
Supply current in
Sleep mode from
IDDA
μA
VDDA supply
4 MHz
2.5
2.5
2 MHz
2.5
2.5
1 MHz
2.5
2.5
500 KHz
2.5
2.5
60/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 36: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
ISW = VDDIOx fSW C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the I/O supply voltage
DDIOx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
+ C
S
INT
EXT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DocID025004 Rev 2
61/124
100
Electrical characteristics
Symbol
STM32F072xx
Table 35. Switching output I/O current consumption
I/O toggling
Parameter
Conditions(1)
Typ
Unit
frequency (fSW
)
4 MHz
0.07
8 MHz
16 MHz
24 MHz
48 MHz
4 MHz
0.15
0.31
0.53
0.92
0.18
0.37
0.76
1.39
2.188
0.32
0.64
1.25
2.23
4.442
0.49
0.94
2.38
3.99
0.64
1.25
3.24
5.02
0.81
1.7
V
DDIOx = 3.3 V
C =CINT
8 MHz
VDDIOx = 3.3 V
C
EXT = 0 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
8 MHz
VDDIOx = 3.3 V
CEXT = 10 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
I/O current
consumption
ISW
mA
VDDIOx = 3.3 V
8 MHz
C
EXT = 22 pF
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
EXT = 33 pF
8 MHz
C
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
C
EXT = 47 pF
8 MHz
C = CINT + CEXT+ CS
C = Cint
16 MHz
3.67
4 MHz
8 MHz
0.66
1.43
2.45
4.97
VDDIOx = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
16 MHz
24 MHz
1.
C = 7 pF (estimated value).
S
62/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 36. The MCU is placed
under the following conditions:
All I/O pins are in Analog mode
All peripherals are disabled unless otherwise mentioned
The given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
Ambient operating temperature and supply voltage conditions summarized in Table 21:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in Table
35. The power consumption of the analog part of the peripherals (where applicable) is
indicated in each related section of the datasheet.
Table 36. Peripheral current consumption
Peripheral
BusMatrix(1)
Typical consumption at 25 °C
Unit
2.2
1.6
5.7
13.0
8.2
8.5
2.3
1.9
2.2
1.2
0.9
5.0
52.6
CRC
DMA
Flash interface
GPIOA
GPIOB
AHB
GPIOC
μA/MHz
GPIOD
GPIOE
GPIOF
SRAM
TSC
ALL AHB Peripherals
DocID025004 Rev 2
63/124
100
Electrical characteristics
STM32F072xx
Unit
Table 36. Peripheral current consumption (continued)
Peripheral
Typical consumption at 25 °C
APB-Bridge(2)
2.8
4.1
12.4
1.5
0.8
4.7
0.1
3.9
4.0
1.3
8.7
8.5
1.7
14.9
15.5
11.4
2.5
2.3
5.3
9.1
6.6
6.8
17.0
16.7
5.4
5.4
7.2
1.4
182
ADC(3)
CAN
CEC
CRS
DAC(3)
DEBUG (MCU debug feature)
I2C1
I2C2
PWR
SPI1
SPI2
SYSCFG & COMP
TIM1
APB
TIM2
μA/MHz
TIM3
TIM6
TIM7
TIM14
TIM15
TIM16
TIM17
USART1
USART2
USART3
USART4
USB
WWDG
ALL APB Peripherals
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.
3. The power consumption of the analog part (I
) of peripherals such as ADC, DAC, Comparators, is not
DDA
included. Refer to the tables of characteristics in the subsequent sections.
64/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
6.3.6
Wakeup time from low-power mode
The wakeup times given in Table 37 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode. After
wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI Line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 24: General operating conditions except when
explicitly mentioned
Table 37. Low-power mode wakeup timings
Typ @VDD = VDDA
Symbol
Parameter
Conditions
Max Unit
= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V
Regulator in run
mode
3.2
7.0
3.1
5.8
2.9
5.2
2.9
4.9
52
2.8
4.6
51
5
Wakeup from Stop
mode
tWUSTOP
Regulator in low
power mode
9
μs
Wakeup from
Standby mode
tWUSTANDBY
60.4
55.6
53.5
-
Wakeup from Sleep
mode
tWUSLEEP
4 SYSCLK cycles
-
DocID025004 Rev 2
65/124
100
Electrical characteristics
STM32F072xx
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 14: High-speed external clock
source AC timing diagram.
Table 38. High-speed external user clock characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
fHSE_ext User external clock source frequency
VHSEH OSC_IN input pin high level voltage
VHSEL OSC_IN input pin low level voltage
1
8
-
32
MHz
0.7 VDDIOx
VSS
VDDIOx
V
-
0.3 VDDIOx
tw(HSEH)
OSC_IN high or low time
tw(HSEL)
15
-
-
-
-
ns
tr(HSE)
OSC_IN rise or fall time
tf(HSE)
20
1. Guaranteed by design, not tested in production.
Figure 14. High-speed external clock source AC timing diagram
T
Wꢌ(3%(ꢍ
6
(3%(
ꢉꢀꢎ
ꢁꢀꢎ
6
(3%,
T
T
T
T
Rꢌ(3%ꢍ
Fꢌ(3%ꢍ
Wꢌ(3%,ꢍ
4
(3%
-3ꢁꢉꢅꢁꢃ6ꢅ
66/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 15.
Table 39. Low-speed external user clock characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
32.768
1000
VDDIOx
kHz
0.7 VDDIOx
VSS
-
-
V
0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
450
-
-
-
-
ns
tr(LSE)
OSC32_IN rise or fall time
tf(LSE)
50
1. Guaranteed by design, not tested in production.
Figure 15. Low-speed external clock source AC timing diagram
T
Wꢌ,3%(ꢍ
6
,3%(
ꢉꢀꢎ
ꢁꢀꢎ
6
,3%,
T
T
T
Rꢌ,3%ꢍ
Fꢌ,3%ꢍ
T
Wꢌ,3%,ꢍ
4
,3%
-3ꢁꢉꢅꢁꢆ6ꢅ
DocID025004 Rev 2
67/124
100
Electrical characteristics
STM32F072xx
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 40. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 40. HSE oscillator characteristics
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency
4
-
8
32
-
MHz
RF
Feedback resistor
200
k
During startup(3)
-
8.5
VDD = 3.3 V,
Rm = 30 ,
CL = 10 pF@8 MHz
-
-
-
-
-
0.4
0.5
0.8
1
-
-
-
-
-
VDD = 3.3 V,
Rm = 45 ,
CL = 10 pF@8 MHz
VDD = 3.3 V,
IDD
HSE current consumption
mA
Rm = 30 ,
CL = 5 pF@32 MHz
VDD = 3.3 V,
Rm = 30 ,
CL = 10 pF@32 MHz
VDD = 3.3 V,
Rm = 30 ,
1.5
CL = 20 pF@32 MHz
gm
Oscillator transconductance
Startup time
Startup
10
-
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the t
startup time
SU(HSE)
4.
t
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
SU(HSE)
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
68/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Figure 16. Typical application with an 8 MHz crystal
2ESONATOR WITH
INTEGRATED CAPACITORS
#
,ꢁ
F
/3#?).
(3%
"IAS
CONTROLLED
GAIN
ꢊ -(Z
RESONATOR
2
&
/3#?/54
ꢌꢁꢍ
2
%84
#
,ꢅ
-3ꢁꢉꢊꢈꢇ6ꢁ
1.
R
value depends on the crystal characteristics.
EXT
DocID025004 Rev 2
69/124
100
Electrical characteristics
STM32F072xx
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 41. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
-
0.5
0.9
1
LSEDRV[1:0]= 01
medium low driving capability
-
-
-
-
-
-
IDD
LSE current consumption
μA
LSEDRV[1:0] = 10
medium high driving capability
-
1.3
1.6
-
LSEDRV[1:0]=11
higher driving capability
-
LSEDRV[1:0]=00
lower driving capability
5
8
15
LSEDRV[1:0]= 01
medium low driving capability
-
Oscillator
transconductance
gm
μA/V
LSEDRV[1:0] = 10
medium high driving capability
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
-
-
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3.
t
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
SU(LSE)
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
70/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Figure 17. Typical application with a 32.768 kHz crystal
5HVRQDWRUꢅZLWK
LQWHJUDWHGꢅFDSDFLWRUV
&
/ꢁ
I
26&ꢀꢄB,1
/6(
'ULYH
ꢅSURJUDPPDEOHꢅ
DPSOLILHU
ꢀꢄꢆꢐꢒꢍꢅN+]
UHVRQDWRU
26&ꢀꢄB287
&
/ꢄ
06ꢀꢃꢄꢋꢀ9ꢁ
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DocID025004 Rev 2
71/124
100
Electrical characteristics
STM32F072xx
6.3.8
Internal clock source characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI) RC oscillator
(1)
Table 42. HSI oscillator characteristics
Symbol
Parameter
Frequency
HSI user trimming step
Conditions
Min
Typ
Max
Unit
fHSI
-
8
-
-
-
-
-
-
-
MHz
%
TRIM
-
1(2)
DuCy(HSI) Duty cycle
45(2)
–3.8(3)
–2.9(3)
–1.3(3)
–1
55(2)
4.6(3)
2.9(3)
2.2(3)
1
%
TA = –40 to 105 °C
TA = –10 to 85 °C
TA = 0 to 70 °C
TA = 25 °C
%
Accuracy of the HSI
oscillator (factory
calibrated)
%
ACCHSI
%
%
HSI oscillator startup
time
tsu(HSI)
1(2)
-
2(2)
μs
HSI oscillator power
consumption
IDDA(HSI)
-
80
100(2)
μA
1.
V
= 3.3 V, T = –40 to 105 °C unless otherwise specified.
DDA A
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 18. HSI oscillator accuracy characterization results
ꢆꢎ
-!8
-).
ꢃꢎ
ꢂꢎ
ꢅꢎ
ꢁꢎ
ꢀꢎ
4 ; #=
!
ꢄꢃꢀ
ꢄꢅꢀ
ꢀ
ꢅꢀ
ꢃꢀ
ꢇꢀ
ꢊꢀ
ꢁꢀꢀ
ꢁꢅꢀ
ꢄꢁꢎ
ꢄꢅꢎ
ꢄꢂꢎ
ꢄꢃꢎ
ꢄꢆꢎ
-3ꢂꢀꢉꢊꢆ6ꢂ
72/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
(1)
Table 43. HSI14 oscillator characteristics
Symbol
Parameter
Frequency
HSI14 user-trimming step
Conditions
Min
Typ
Max
Unit
fHSI14
TRIM
-
-
14
-
-
MHz
%
1(2)
DuCy(HSI14) Duty cycle
45(2)
-
55(2)
5.1(3)
3.1(3)
2.2(3)
1
%
TA = –40 to 105 °C –4.2(3)
TA = –10 to 85 °C –3.2(3)
-
%
-
%
Accuracy of the HSI14
oscillator (factory calibrated)
ACCHSI14
TA = 0 to 70 °C
TA = 25 °C
–1.3(3)
-
%
–1
-
%
tsu(HSI14) HSI14 oscillator startup time
1(2)
-
2(2)
μs
HSI14 oscillator power
IDDA(HSI14)
-
100
150(2)
μA
consumption
1.
V
= 3.3 V, T = –40 to 105 °C unless otherwise specified.
DDA A
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 19. HSI14 oscillator accuracy characterization results
ꢆꢎ
-!8
-).
ꢃꢎ
ꢂꢎ
ꢅꢎ
ꢁꢎ
ꢀꢎ
4 ; #=
!
ꢄꢃꢀ
ꢄꢅꢀ
ꢀ
ꢅꢀ
ꢃꢀ
ꢇꢀ
ꢊꢀ
ꢁꢀꢀ
ꢁꢅꢀ
ꢁꢎ
ꢅꢎ
ꢂꢎ
ꢄ
ꢄ
ꢄ
ꢄꢃꢎ
ꢄꢆꢎ
-3ꢂꢀꢉꢊꢇ6ꢅ
DocID025004 Rev 2
73/124
100
Electrical characteristics
STM32F072xx
High-speed internal 48 MHz (HSI48) RC oscillator
(1)
Table 44. HSI48 oscillator characteristics
Symbol
Parameter
Frequency
HSI48 user-trimming step
Conditions
Min
Typ
Max
Unit
fHSI48
TRIM
-
48
-
MHz
%
0.09(2)
45(2)
0.14
0.2(2)
55(2)
4.7(3)
3.7(3)
3.4(3)
2.9
DuCy(HSI48) Duty cycle
-
-
-
-
-
-
%
TA = –40 to 105 °C -4.9(3)
%
TA = –10 to 85 °C
TA = 0 to 70 °C
TA = 25 °C
-4.1(3)
-3.8(3)
-2.8
-
%
Accuracy of the HSI48
oscillator (factory calibrated)
ACCHSI48
%
%
tsu(HSI48) HSI48 oscillator startup time
6(2)
μs
HSI48 oscillator power
IDDA(HSI48)
-
312
350(2)
μA
consumption
1.
V
= 3.3 V, T = –40 to 105 °C unless otherwise specified.
DDA A
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 20. HSI48 oscillator accuracy characterization results
ꢆꢎ
-!8
-).
ꢃꢎ
ꢂꢎ
ꢅꢎ
ꢁꢎ
ꢀꢎ
4 ; #=
!
ꢄꢃꢀ
ꢄꢅꢀ
ꢀ
ꢅꢀ
ꢃꢀ
ꢇꢀ
ꢊꢀ
ꢁꢀꢀ
ꢁꢅꢀ
ꢁꢎ
ꢅꢎ
ꢂꢎ
ꢄ
ꢄ
ꢄ
ꢄꢃꢎ
ꢄꢆꢎ
-3ꢂꢃꢅꢀꢇ6ꢁ
74/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Low-speed internal (LSI) RC oscillator
(1)
Table 45. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI
Frequency
30
-
40
-
50
85
kHz
μs
(2)
tsu(LSI)
LSI oscillator startup time
(2)
IDDA(LSI)
LSI oscillator power consumption
-
0.75
1.2
μA
1.
V
= 3.3 V, T = –40 to 105 °C unless otherwise specified.
DDA A
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 46 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions.
Table 46. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max
PLL input clock(1)
1(2)
40(2)
16(2)
-
8.0
24(2)
60(2)
48
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
-
-
-
-
fPLL_OUT
tLOCK
MHz
μs
200(2)
300(2)
JitterPLL
Cycle-to-cycle jitter
-
ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by f
.
PLL_OUT
2. Guaranteed by design, not tested in production.
DocID025004 Rev 2
75/124
100
Electrical characteristics
STM32F072xx
6.3.10
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
Table 47. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
16-bit programming time TA–40 to +105 °C
40
20
20
-
53.5
60
40
40
10
12
3.6
μs
ms
ms
mA
mA
V
tERASE Page (2 KB) erase time TA –40 to +105 °C
-
-
-
-
-
tME
Mass erase time
TA –40 to +105 °C
Write mode
IDD
Supply current
Erase mode
-
Vprog Programming voltage
2
1. Guaranteed by design, not tested in production.
Table 48. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Conditions
Min(1)
Unit
NEND
TA = –40 to +105 °C
kcycles
10
30
10
20
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
10 kcycles(2) at TA = 55 °C
tRET
Data retention
Years
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 49. They are based on the EMS levels and classes
defined in application note AN1709.
76/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Level/
Table 49. EMS characteristics
Symbol
Parameter
Conditions
Class
VDD 3.3 V, LQFP100, TA +25 °C,
fHCLK 48 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD3.3 V, LQFP100, TA +25 °C,
fHCLK 48 MHz,
conforming to IEC 61000-4-4
4B
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 50. EMI characteristics
Max vs. [fHSE/fHCLK
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/48 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
EMI Level
-3
23
14
4
VDD 3.6 V, TA 25 °C,
LQFP100 package
compliant with IEC
61967-2
dBμV
SEMI
Peak level
-
DocID025004 Rev 2
77/124
100
Electrical characteristics
STM32F072xx
6.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 51. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge
voltage (human body model) to JESD22-A114
TA +25 °C, conforming
VESD(HBM)
2
2000
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA +25 °C, conforming
to ANSI/ESD STM5.3.1
II
500
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 52. Electrical sensitivities
Symbol
Parameter
Conditions
Class
II level A
LU
Static latch-up class
TA +105 °C conforming to JESD78A
6.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V
(for standard, 3.3 V-capable I/O pins) should be avoided during normal
DDIOx
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
78/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 μA/+0 μA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 53.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 53. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
Injected current on BOOT0 and PF1 pins
Injected current on PC0 pin
–0
–0
NA
+5
Injected current on PA11 and PA12 pins with induced
leakage current on adjacent pins less than -1 mA
IINJ
–5
NA
mA
Injected current on all other FT and FTf pins
–5
–5
NA
+5
Injected current on all other TTa, TC and RST pins
6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 24: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).
Table 54. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
-
-
-
-
0.3 VDDIOx+0.07(1)
0.475 VDDIOx–0.2(1)
0.3 VDDIOx–0.3(1)
Low level input
voltage
VIL
V
All I/Os except
BOOT0 pin
-
-
0.3 VDDIOx
DocID025004 Rev 2
79/124
100
Electrical characteristics
STM32F072xx
Table 54. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TC and TTa I/O
FT and FTf I/O
BOOT0
0.445 VDDIOx+0.398(1)
0.5 VDDIOx+0.2(1)
-
-
-
-
-
-
High level input
voltage
0.2 VDDIOx+0.95(1)
VIH
V
All I/Os except
BOOT0 pin
0.7 VDDIOx
-
-
TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
-
200(1)
100(1)
300(1)
-
-
-
Schmitt trigger
hysteresis
Vhys
mV
TC, FT and FTf I/O
TTa in digital mode
VSS VIN VDDIOx
-
-
0.1
TTa in digital mode
VDDIOx VIN VDDA
-
-
-
-
-
-
1
Input leakage
current(2)
Ilkg
μA
k
TTa in analog mode
VSS VIN VDDA
0.2
10
FT and FTf I/O (3)
VDDIOx VIN 5 V
Weak pull-up
RPU
equivalent resistor VIN VSS
25
40
55
(4)
Weak pull-down
RPD
CIO
equivalent
VIN VDDIOx
25
-
40
5
55
-
k
resistor(4)
I/O pin capacitance
pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 53:
I/O current injection susceptibility.
3. To sustain a voltage higher than V
+0.3 V, the internal pull-up/pull-down resistors must be disabled.
DDIOx
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
80/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 20 for standard I/Os, and in Figure 21 for
5 V tolerant I/Os.
Figure 21. TC and TTa I/O input characteristics
ꢀ
9ꢅꢅꢈ9ꢊ
,1
ꢄꢆꢋ
7HVWHGꢅUDQJH
ꢄ
77/ꢅVWDQGDUGꢅUHTXLUHPHQW
ꢁꢆꢋ
ꢁ
8QGHILQHGꢅLQSXWꢅUDQJH
77/ꢅVWDQGDUGꢅUHTXLUHPHQW
7HVWHGꢅUDQJH
ꢃꢆꢋ
ꢃ
ꢄ
ꢄꢆꢄ
ꢄꢆꢂ
ꢄꢆꢒ
ꢄꢆꢍ
ꢀ
ꢀꢆꢄ
ꢀꢆꢂ
ꢀꢆꢒ
9'ꢅꢅ'ꢅ,ꢅ2ꢅꢅ[ꢅꢅꢈꢅ9ꢊ
06ꢀꢄꢁꢀꢃ9ꢄ
Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics
ꢀ
9ꢅꢅꢅꢈ9ꢊ
,1ꢅꢅ
ꢄꢆꢋ
ꢄ
7HVWHGꢅUDQJH
77/ꢅVWDQGDUGꢅUHTXLUHPHQW
ꢁꢆꢋ
ꢁ
8QGHILQHGꢅLQSXWꢅUDQJH
77/ꢅVWDQGDUGꢅUHTXLUHPHQW
ꢃꢆꢋ
ꢃ
7HVWHGꢅUDQJH
ꢄ
ꢄꢆꢄ
ꢄꢆꢂ
ꢄꢆꢒ
ꢄꢆꢍ
ꢀ
ꢀꢆꢄ
ꢀꢆꢂ
ꢀꢆꢒ
9'ꢅꢅ'ꢅ,ꢅ2ꢅꢅ[ꢅꢅꢈꢅ9ꢊ
06ꢀꢄꢁꢀꢁ9ꢄ
DocID025004 Rev 2
81/124
100
Electrical characteristics
STM32F072xx
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
The sum of the currents sourced by all the I/Os on V
plus the maximum
DDIOx,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 21: Voltage characteristics).
VDD
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating I
(see
SS
VSS
Table 21: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
(1)
Table 55. Output voltage characteristics
Symbol
VOL
Parameter
Conditions
Min
Max Unit
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port(2)
-
0.4
VD|IDIO| =x 8 2m.7AV
V
IO
VOH
VDDIOx–0.4
-
VOL
TTL port(2)
-
0.4
VD|IDIO| =x 8 2m.7AV
V
IO
VOH
2.4
-
(3)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3
V
-
|IIO| = 20 mA
VDDIOx 2.7 V
(3)
VOH
VDDIOx–1.3
(3)
VOL
-
0.4
V
-
|IIO| = 6 mA
VDDIOx 2 V
(3)
VOH
VDDIOx–0.4
-
(3)
VOL
0.4
-
V
V
|IIO| = 4 mA
(3)
VOH
VDDIOx–0.4
|IIO| = 20 mA
VDDIOx 2.7 V
-
-
0.4
0.4
V
V
Output low level voltage for an FTf I/O pin in
FM+ mode
(4)
VOLFM+
|IIO| = 10 mA
1. The I current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:
IO
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings I
.
IO
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
4. Data based on design simulation only. Not tested in production.
82/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 23 and
Table 56, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 24: General
operating conditions.
(1)(2)
Table 56. I/O AC characteristics
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
ns
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
125
125
1
CL = 50 pF, VDDIOx 2 V
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
x0
MHz
ns
CL = 50 pF, VDDIOx 2 V
CL = 50 pF, VDDIOx 2 V
CL = 50 pF, VDDIOx 2 V
125
125
10
25
25
4
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
MHz
ns
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
01
MHz
ns
62.5
62.5
50
30
20
10
5
tr(IO)out Output rise time
CL = 30 pF, VDDIOx 2.7 V
CL = 50 pF, VDDIOx 2.7 V
CL = 50 pF, 2 V VDDIOx 2.7 V
CL = 50 pF, VDDIOx 2 V
fmax(IO)out Maximum frequency(3)
MHz
CL = 30 pF, VDDIOx 2.7 V
CL = 50 pF, VDDIOx 2.7 V
CL = 50 pF, 2 V VDDIOx 2.7 V
CL = 50 pF, VDDIOx 2 V
8
11
tf(IO)out Output fall time
12
25
5
ns
CL = 30 pF, VDDIOx 2.7 V
CL = 50 pF, VDDIOx 2.7 V
CL = 50 pF, 2 V VDDIOx 2.7 V
CL = 50 pF, VDDIOx 2 V
8
tr(IO)out Output rise time
12
25
DocID025004 Rev 2
83/124
100
Electrical characteristics
STM32F072xx
(1)(2)
Table 56. I/O AC characteristics
(continued)
OSPEEDRy
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
ns
[1:0] value(1)
fmax(IO)out Maximum frequency(3)
-
-
-
-
-
-
2
tf(IO)out Output fall time
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
tr(IO)out Output rise time
CL = 50 pF, VDDIOx 2 V
12
34
0.5
16
44
FM+
configuration
(4)
MHz
ns
CL = 50 pF, VDDIOx 2 V
Pulse width of external
tEXTIpw signals detected by the
EXTI controller
10
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 23.
4. When FM+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091
for a detailed description of FM+ I/O configuration.
Figure 23. I/O AC characteristics definition
ꢁꢃꢔ
ꢎꢃꢔ
ꢋꢃꢔ
ꢋꢃꢔ
ꢁꢃꢔ
ꢎꢃꢔ
W
W
Uꢈ,2ꢊRXW
Iꢈ,2ꢊRXW
7
0D[LPXPꢅIUHTXHQF\ꢅLVꢅDFKLHYHGꢅLIꢅꢈWꢅꢅꢉꢅWꢅꢅꢈꢅꢄꢏꢀꢊ7ꢅDQGꢅLIꢅWKHꢅGXW\ꢅF\FOHꢅLVꢅꢈꢂꢋꢑꢋꢋꢔꢊ
U
I
ZKHQꢅORDGHGꢅE\ꢅWKHꢅVSHFLILHGꢅFDSDFLWDQFHꢆ
06ꢀꢄꢁꢀꢄ9ꢄ
6.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 24: General operating conditions.
Table 57. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST) NRST input low level voltage
VIH(NRST) NRST input high level voltage
-
-
-
0.3 VDD+0.07(1)
-
V
0.445 VDD+0.398(1)
84/124
DocID025004 Rev 2
STM32F072xx
Symbol
Electrical characteristics
Table 57. NRST pin characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
NRST Schmitt trigger voltage
hysteresis
Vhys(NRST)
-
200
-
mV
Weak pull-up equivalent
resistor(2)
RPU
VIN VSS
25
40
55
k
VF(NRST) NRST input filtered pulse
-
-
-
-
100(1)
ns
2.7 < VDD < 3.6
2.0 < VDD < 3.6
300(1)
500(1)
-
-
VNF(NRST) NRST input not filtered pulse
ns
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
Figure 24. Recommended NRST pin protection
([WHUQDO
9''
538
UHVHWꢅFLUFXLWꢈꢁꢊ
1567ꢈꢄꢊ
,QWHUQDOꢅUHVHW
)LOWHU
ꢃꢆꢁꢅ)
06ꢁꢎꢍꢐꢍ9ꢄ
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
max level specified in
IL(NRST)
Table 57: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 58 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK
DDA
conditions summarized in Table 24: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 58. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
3.6
Unit
Analog supply voltage for
ADC ON
VDDA
2.4
-
V
Current consumption of
the ADC(1)
IDDA (ADC)
fADC
VDD = VDDA = 3.3 V
-
0.9
-
mA
ADC clock frequency
Sampling rate
0.6
-
-
14
1
MHz
MHz
(2)
fS
0.05
DocID025004 Rev 2
85/124
100
Electrical characteristics
STM32F072xx
Table 58. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
ADC = 14 MHz
-
-
-
-
-
823
17
kHz
1/fADC
V
(2)
External trigger frequency
fTRIG
VAIN
Conversion voltage range
External input impedance
0
VDDA
See Equation 1 and
Table 59 for details
(2)
RAIN
-
-
-
-
-
-
50
1
k
k
pF
Sampling switch
resistance
(2)
RADC
Internal sample and hold
capacitor
(2)
8
CADC
fADC = 14 MHz
5.9
83
μs
(2)
Calibration time
tCAL
1/fADC
1.5 ADC
cycles + 3
fPCLK cycles
1.5 ADC
cycles + 2
fPCLK cycles
ADC clock = HSI14
-
ADC_DR register write
latency
(2)
fPCLK
cycle
WLATENCY
ADC clock = PCLK/2
ADC clock = PCLK/4
-
-
4.5
8.5
-
-
fPCLK
cycle
f
ADC = fPCLK/2 = 14 MHz
fADC = fPCLK/2
0.196
5.5
μs
1/fPCLK
μs
(2)
Trigger conversion latency fADC = fPCLK/4 = 12 MHz
fADC = fPCLK/4
0.219
10.5
-
tlatr
1/fPCLK
μs
fADC = fHSI14 = 14 MHz
0.188
-
0.259
-
ADC jitter on trigger
conversion
JitterADC
fADC = fHSI14
1
1/fHSI14
fADC = 14 MHz
0.107
1.5
0
-
-
17.1
239.5
1
μs
1/fADC
μs
(2)
Sampling time
Power-up time
tS
(2)
tSTAB
0
-
fADC = 14 MHz
1
18
μs
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 μA on I
and 60 μA
DDA
on I should be taken into account.
DD
2. Guaranteed by design, not tested in production.
Equation 1: R
max formula
AIN
TS
RAIN ------------------------------------------------------------- – RADC
fADC CADC ln2N + 2
86/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 59. R
max for f
= 14 MHz
AIN
ADC
Ts (cycles)
tS (μs)
RAIN max (k)(1)
1.5
7.5
0.11
0.54
0.96
2.04
2.96
3.96
5.11
17.1
0.4
5.9
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Guaranteed by design, not tested in production.
(1)(2)(3)
Table 60. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±1.3
±1
±2
±1.5
±1.5
±1
f
f
PCLK = 48 MHz,
ADC = 14 MHz, RAIN < 10 k
DDA = 3 V to 3.6 V
Gain error
±0.5
±0.7
±0.8
±3.3
±1.9
±2.8
±0.7
±1.2
±3.3
±1.9
±2.8
±0.7
±1.2
LSB
V
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
TA = 25 °C
±1.5
±4
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
f
±2.8
±3
ADC = 14 MHz, RAIN < 10 k
DDA = 2.7 V to 3.6 V
Gain error
LSB
LSB
V
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
±1.3
±1.7
±4
TA = 40 to 105 °C
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
±2.8
±3
f
ADC = 14 MHz, RAIN < 10 k
DDA = 2.4 V to 3.6 V
TA = 25 °C
Gain error
V
Differential linearity error
Integral linearity error
±1.3
±1.7
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
affect the ADC accuracy.
and I
in Section 6.3.14 does not
INJ(PIN)
INJ(PIN)
3. Better performance may be achieved in restricted V
, frequency and temperature ranges.
DDA
4. Data based on characterization results, not tested in production.
DocID025004 Rev 2
87/124
100
Electrical characteristics
STM32F072xx
Figure 25. ADC accuracy characteristics
(
*
ꢈꢁꢊ ([DPSOHꢅRIꢅDQꢅDFWXDO WUDQVIHUꢅFXUYH
ꢈꢄꢊꢅ7KHꢅLGHDOꢅWUDQVIHUꢅFXUYH
ꢈꢀꢊꢅ(QG SRLQWꢅFRUUHODWLRQꢅOLQH
ꢂꢃꢎꢋ
ꢂꢃꢎꢂ
ꢂꢃꢎꢀ
ꢈꢄꢊ
( 7RWDOꢅ 8QDGMXVWHG (UURUꢌꢅ PD[LPXP GHYLDWLRQ
7
(
EHWZHHQ WKHꢅDFWXDOꢅDQGꢅWKHꢅLGHDOꢅWUDQVIHU FXUYHVꢆ
7
ꢈꢀꢊ
ꢐ
ꢒ
ꢋ
( 2IIVHWꢅ(UURUꢌꢅGHYLDWLRQꢅEHWZHHQꢅWKHꢅILUVWꢅDFWXDO
2
WUDQVLWLRQꢅDQGꢅWKH ILUVWꢅLGHDOꢅRQHꢆ
ꢈꢁꢊ
( *DLQꢅ (UURUꢌ GHYLDWLRQꢅ EHWZHHQ WKHꢅ ODVWꢅ LGHDO
*
WUDQVLWLRQꢅDQGꢅWKH ODVWꢅDFWXDOꢅRQHꢆ
(
(
2
/
( 'LIIHUHQWLDOꢅ/LQHDULW\ꢅ(UURUꢌ PD[LPXPꢅGHYLDWLRQ
'
ꢂ
ꢀ
ꢄ
ꢁ
EHWZHHQ DFWXDOꢅVWHSVꢅDQGꢅWKHꢅLGHDOꢅRQHꢆ
( ,QWHJUDOꢅ /LQHDULW\ (UURUꢌꢅ PD[LPXPꢅ GHYLDWLRQ
/
(
EHWZHHQ DQ\ꢅ DFWXDOꢅ WUDQVLWLRQꢅ DQGꢅ WKH HQG SRLQW
FRUUHODWLRQꢅOLQHꢆ
'
ꢁ /6%
,'($/
ꢃ
9
ꢁ
ꢄ
ꢀ
ꢂ
ꢋ
ꢒ
ꢐ
ꢂꢃꢎꢀ ꢂꢃꢎꢂ ꢂꢃꢎꢋ ꢂꢃꢎꢒ
9
''$
66$
-3ꢁꢉꢊꢊꢀ6ꢁ
Figure 26. Typical connection diagram using the ADC
9
''$
6DPSOHꢅDQGꢅKROGꢅ$'&
FRQYHUWHU
9
7
ꢈꢁꢊ
5
5
$'&
$,1
$,1[
ꢁꢄꢑELW
FRQYHUWHU
, ꢁ $
/
&
9
SDUDVLWLF
7
9
$,1
&
$'&
06ꢀꢀꢎꢃꢃ9ꢁ
1. Refer to Table 58: ADC characteristics for the values of R , R
and C
.
ADC
AIN
ADC
2.
C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
parasitic
pad capacitance (roughly 7 pF). A high C
value will downgrade conversion accuracy. To remedy
parasitic
this, f
should be reduced.
ADC
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 12: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
88/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
6.3.17
DAC electrical specifications
Table 61. DAC characteristics
Symbol
VDDA
Parameter
Min
Typ
Max
Unit
Comments
Analog supply voltage for
DAC ON
2.4
-
3.6
V
Resistive load with buffer
ON
(1)
RLOAD
5
-
-
-
-
k Load is referred to ground
When the buffer is OFF, the
Impedance output with
buffer OFF
Minimum resistive load between
DAC_OUT and VSS to have a
(1)
RO
15
k
1% accuracy is 1.5 M
Maximum capacitive load at
pF DAC_OUT pin (when the buffer
is ON).
(1)
CLOAD
Capacitive load
-
-
-
50
-
It gives the maximum output
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
excursion of the DAC.
0.2
V
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer ON
V
DDA = 3.6 V and (0x155) and
-
-
-
-
-
-
V
DDA – 0.2
V
mV
V
(0xEAB) at VDDA = 2.4 V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
0.5
-
It gives the maximum output
excursion of the DAC.
DAC_OUT Higher DAC_OUT voltage
-
-
-
VDDA – 1LSB
max(1)
with buffer OFF
With no load, middle code
(0x800) on the input
380
μA
μA
DAC DC current
consumption in quiescent
mode(2)
(1)
IDDA
With no load, worst code
(0xF1C) on the input
480
Given for the DAC in 10-bit
configuration
-
-
±0.5
LSB
Differential non linearity
Difference between two
consecutive code-1LSB)
DNL(3)
Given for the DAC in 12-bit
configuration
-
-
-
-
±2
±1
LSB
LSB
Integral non linearity
(difference between
Given for the DAC in 10-bit
configuration
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
INL(3)
Given for the DAC in 12-bit
configuration
-
-
±4
LSB
-
-
-
-
±10
±3
mV
Offset error
Given for the DAC in 10-bit at
(difference between
measured value at Code
(0x800) and the ideal value
= VDDA/2)
LSB
Offset(3)
VDDA = 3.6 V
Given for the DAC in 12-bit at
-
-
-
-
±12
LSB
%
VDDA = 3.6 V
Given for the DAC in 12-bit
configuration
Gain error(3) Gain error
±0.5
DocID025004 Rev 2
89/124
100
Electrical characteristics
STM32F072xx
Table 61. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Comments
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
(3)
tSETTLING
-
3
4
μs CLOAD 50 pF, RLOAD 5 k
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Update
rate(3)
-
-
1
MS/s CLOAD 50 pF, RLOAD 5 k
CLOAD 50 pF, RLOAD 5 k
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
(3)
tWAKEUP
-
-
6.5
10
μs
input code between lowest and
highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
–67
–40
dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved.
3. Data based on characterization results, not tested in production.
Figure 27. 12-bit buffered / non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RLOAD
DACx_OUT
12-bit
digital to
analog
converter
CLOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
90/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
6.3.18
Comparator characteristics
Table 62. Comparator characteristics
Conditions
Symbol
VDDA
Parameter
Min(1) Typ Max(1) Unit
Analog supply voltage
2
0
-
-
3.6
V
Comparator input
voltage range
VIN
VDDA
VREFINT scaler offset
voltage
VSC
tS_SC
tSTART
-
-
-
±5
-
±10
0.2
60
mV
ms
μs
VREFINT scaler startup
time from power down
Comparator startup
time
Startup time to reach propagation delay
specification
-
Ultra-low power mode
Low power mode
-
-
-
-
-
-
-
-
-
-
-
2
4.5
1.5
0.6
100
240
7
0.7
0.3
50
μs
ns
μs
ns
Propagation delay for
200 mV step with
100 mV overdrive
Medium power mode
VDDA 2.7 V
High speed mode
VDDA 2.7 V
100
2
tD
Ultra-low power mode
Low power mode
0.7
0.3
90
2.1
1.2
180
300
10
Propagation delay for
full range step with
100 mV overdrive
Medium power mode
VDDA 2.7 V
High speed mode
VDDA 2.7 V
110
4
Voffset
Comparator offset error
mV
Offset error
temperature coefficient
dVoffset/dT
-
18
-
μV/°C
Ultra-low power mode
Low power mode
-
-
-
-
1.2
3
1.5
5
COMP current
consumption
IDD(COMP)
μA
Medium power mode
High speed mode
10
75
15
100
DocID025004 Rev 2
91/124
100
Electrical characteristics
STM32F072xx
Table 62. Comparator characteristics (continued)
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
No hysteresis
(COMPxHYST[1:0]=00)
-
3
0
8
-
High speed mode
13
10
26
19
49
40
Low hysteresis
(COMPxHYST[1:0]=01)
All other power
modes
5
Vhys
Comparator hysteresis
High speed mode
7
mV
Medium hysteresis
(COMPxHYST[1:0]=10)
15
31
All other power
modes
9
High speed mode
18
19
High hysteresis
(COMPxHYST[1:0]=11)
All other power
modes
1. Data based on characterization results, not tested in production.
6.3.19
Temperature sensor characteristics
Table 63. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
-
1
4.3
1.43
-
2
4.6
1.52
10
°C
mV/°C
V
Avg_Slope(1) Average slope
4.0
1.34
4
V30
Voltage at 30 °C (5 °C)(2)
(1)
(1)
tSTART
Startup time
μs
ADC sampling time when reading the
temperature
tS_temp
4
-
-
μs
1. Guaranteed by design, not tested in production.
2. Measured at V = 3.3 V 10 mV. The V ADC conversion result is stored in the TS_CAL1 byteRefer to
DDA
30
Table 3: Temperature sensor calibration values.
6.3.20
V
monitoring characteristics
BAT
Table 64. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
50
2
-
-
-
k
Ratio on VBAT measurement
Error on Q
Er(1)
–1
4
+1
-
%
(1)
tS_vbat
ADC sampling time when reading the VBAT
-
μs
1. Guaranteed by design, not tested in production.
92/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
6.3.21
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 65. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
ns
1
20.8
0
-
tres(TIM)
Timer resolution time
fTIMxCLK = 48 MHz
TIMxCLK = 48 MHz
-
fTIMxCLK/2
MHz
Timer external clock
frequency on CH1 to CH4
fEXT
f
0
24
16
MHz
TIMx (except
TIM2)
-
ResTIM
Timer resolution
bit
TIM2
-
32
65536
tTIMxCLK
1
16-bit counter clock
period
tCOUNTER
fTIMxCLK = 48 MHz 0.0208
-
1365
μs
tTIMxCLK
65536 × 65536
89.48
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 48 MHz
-
s
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM6, TIM14, TIM15, TIM16 and TIM17
timers.
(1)
Table 66. IWDG min/max timeout period at 40 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
/8
0
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
1
/16
/32
/64
/128
/256
2
1638.4
3276.8
6553.6
13107.2
26214.4
3
4
ms
5
6 or 7
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from
30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the
phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of
uncertainty.
DocID025004 Rev 2
93/124
100
Electrical characteristics
Prescaler
STM32F072xx
Table 67. WWDG min/max timeout value at 48 MHz (PCLK)
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0853
0.1706
0.3413
0.6826
5.4613
10.9226
21.8453
43.6906
ms
6.3.22
Communication interfaces
2
I C interface characteristics
2
The I2C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
is disabled, but is still present. Only FTf I/O pins
DDIOx
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
(1)
Table 68. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes
that are suppressed by the analog
filter
tAF
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with widths below t
3. Spikes with widths above t
are filtered.
AF(min)
are not filtered
AF(max)
94/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
2
SPI/I S characteristics
2
Unless otherwise specified, the parameters given in Table 69 for SPI or in Table 70 for I S
are derived from tests performed under the ambient temperature, f
frequency and
PCLKx
supply voltage conditions summarized in Table 24: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
(1)
Table 69. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
-
-
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
-
6
ns
ns
%
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
4Tpclk
-
-
2Tpclk + 10
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
Tpclk/2 -2
Tpclk/2 + 1
tw(SCKL)
Master mode
Slave mode
Master mode
Slave mode
4
5
-
tsu(MI)
tsu(SI)
-
th(MI)
th(SI)
4
-
Data input hold time
5
-
(2)
ta(SO)
Data output access time Slave mode, fPCLK = 20 MHz
Data output disable time Slave mode
0
3Tpclk
(3)
tdis(SO)
0
18
tv(SO)
tv(MO)
th(SO)
th(MO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
22.5
-
6
-
11.5
2
Data output hold time
-
SPI slave input clock
duty cycle
DuCy(SCK)
Slave mode
25
75
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
DocID025004 Rev 2
95/124
100
Electrical characteristics
STM32F072xx
Figure 28. SPI timing diagram - slave mode and CPHA = 0
.33 INPUT
T
Cꢌ3#+ꢍ
T
T
Hꢌ.33ꢍ
35ꢌ.33ꢍ
#0(!ꢏꢀ
#0/,ꢏꢀ
T
T
Wꢌ3#+(ꢍ
Wꢌ3#+,ꢍ
#0(!ꢏꢀ
#0/,ꢏꢁ
T
T
T
T
T
T
DISꢌ3/ꢍ
Rꢌ3#+ꢍ
Fꢌ3#+ꢍ
Vꢌ3/ꢍ
Aꢌ3/ꢍ
Hꢌ3/ꢍ
-)3/
/54 054
-3 " / 54
") 4ꢇ /54
")4ꢁ ).
,3" /54
T
SUꢌ3)ꢍ
-/3)
- 3" ).
,3" ).
).054
T
Hꢌ3)ꢍ
AIꢁꢃꢁꢂꢃC
Figure 29. SPI timing diagram - slave mode and CPHA = 1
.33 INPUT
T
T
T
Hꢌ.33ꢍ
35ꢌ.33ꢍ
T
Cꢌ3#+ꢍ
#0(!ꢏꢁ
#0/,ꢏꢀ
Wꢌ3#,(ꢍ
#0(!ꢏꢁ
#0/,ꢏꢁ
T
Wꢌ3#,,ꢍ
T
T
Rꢌ3#,ꢍ
Fꢌ3#,ꢍ
T
T
T
Vꢌ3/ꢍ
Hꢌ3/ꢍ
DISꢌ3/ꢍ
T
Aꢌ3/ꢍ
-)3/
/54 054
-3 " / 54
") 4ꢇ /54
,3" /54
T
T
SUꢌ3)ꢍ
Hꢌ3)ꢍ
-/3)
- 3" ).
")4ꢁ ).
,3" ).
).054
AIꢁꢃꢁꢂꢆ
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
96/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Figure 30. SPI timing diagram - master mode
(IGH
.33 INPUT
T
Cꢌ3#+ꢍ
#0(!ꢏꢀ
#0/,ꢏꢀ
#0(!ꢏꢀ
#0/,ꢏꢁ
#0(!ꢏꢁ
#0/,ꢏꢀ
#0(!ꢏꢁ
#0/,ꢏꢁ
T
T
T
T
Wꢌ3#+(ꢍ
Wꢌ3#+,ꢍ
Rꢌ3#+ꢍ
Fꢌ3#+ꢍ
T
SUꢌ-)ꢍ
-)3/
).054
-3").
T
")4ꢇ ).
,3" ).
Hꢌ-)ꢍ
-/3)
- 3" /54
")4ꢁ /54
,3" /54
/54054
T
T
Vꢌ-/ꢍ
Hꢌ-/ꢍ
AIꢁꢃꢁꢂꢇ6ꢅ
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
2
(1)
Table 70. I S characteristics
Conditions
Symbol
Parameter
Min
Max
Unit
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
1.597
1.601
fCK
1/tc(CK)
I2S clock frequency
MHz
Slave mode
0
-
6.5
10
12
tr(CK)
tf(CK)
I2S clock rise time
I2S clock fall time
Capacitive load CL = 15 pF
-
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
tw(CKH)
I2S clock high time
306
-
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
I2S clock low time
WS valid time
WS hold time
WS setup time
WS hold time
312
2
-
-
-
-
-
ns
Master mode
Master mode
Slave mode
Slave mode
2
7
0
I2S slave input clock duty
cycle
DuCy(SCK)
Slave mode
25
75
%
DocID025004 Rev 2
97/124
100
Electrical characteristics
STM32F072xx
2
(1)
Table 70. I S characteristics (continued)
Conditions
Symbol
Parameter
Data input setup time
Min
Max
Unit
tsu(SD_MR)
tsu(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
6
2
-
-
Data input setup time
(2)
th(SD_MR)
4
-
Data input hold time
(2)
th(SD_SR)
0.5
-
-
ns
(2)
tv(SD_ST)
th(SD_ST)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
20
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
13
-
(2)
tv(SD_MT)
th(SD_MT)
4
-
0
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on f . For example, if f = 8 MHz, then T = 1/f = 125 ns.
PCLK
PCLK
PCLK
PLCLK
Figure 31. I2S slave timing diagram (Philips protocol)
T
Cꢌ#+ꢍ
#0/, ꢏ ꢀ
#0/, ꢏ ꢁ
73 INPUT
T
T
T
Wꢌ#+,ꢍ
Hꢌ73ꢍ
Wꢌ#+(ꢍ
T
T
T
Hꢌ3$?34ꢍ
T
Vꢌ3$?34ꢍ
SUꢌ73ꢍ
3$
TRANSMIT
RECEIVE
ꢌꢅꢍ
,3" TRANSMIT
-3" TRANSMIT
-3" RECEIVE
"ITN TRANSMIT
,3" TRANSMIT
T
SUꢌ3$?32ꢍ
ꢌꢅꢍ
Hꢌ3$?32ꢍ
,3" RECEIVE
"ITN RECEIVE
,3" RECEIVE
3$
AIꢁꢃꢊꢊꢁB
1. Measurement points are done at CMOS levels: 0.3 × V
and 0.7 × V
.
DDIOx
DDIOx
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
98/124
DocID025004 Rev 2
STM32F072xx
Electrical characteristics
Figure 32. I2S master timing diagram (Philips protocol)
T
T
Rꢌ#+ꢍ
Fꢌ#+ꢍ
T
Cꢌ#+ꢍ
#0/, ꢏ ꢀ
#0/, ꢏ ꢁ
73 OUTPUT
T
Wꢌ#+(ꢍ
T
T
Hꢌ73ꢍ
T
Vꢌ73ꢍ
Wꢌ#+,ꢍ
T
T
Vꢌ3$?-4ꢍ
Hꢌ3$?-4ꢍ
ꢌꢅꢍ
3$
TRANSMIT
RECEIVE
,3" TRANSMIT
T
-3" TRANSMIT
-3" RECEIVE
"ITN TRANSMIT
,3" TRANSMIT
T
Hꢌ3$?-2ꢍ
SUꢌ3$?-2ꢍ
ꢌꢅꢍ
3$
,3" RECEIVE
"ITN RECEIVE
,3" RECEIVE
AIꢁꢃꢊꢊꢃB
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DocID025004 Rev 2
99/124
100
Electrical characteristics
STM32F072xx
USB characteristics
The STM32F072xx USB interface is fully compliant with the USB specification version 2.0
and is USB-IF certified (for Full-speed device operation).
Table 71. USB electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ
Max.
Unit
USB transceiver operating
voltage
VDDIO2
3.0(1)
-
-
-
3.6
1.0
1.5
V
(2)
tSTARTUP
USB transceiver startup time
μs
Embedded USB_DP pull-up
value during idle
RPUI
1.1
1.26
k
Embedded USB_DP pull-up
value during reception
RPUR
2.0
28
2.26
40
2.6
44
Driving high
and low
(2)
ZDRV
Output driver impedance(3)
1. The STM32F072xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V voltage range.
2. Guaranteed by design, not tested in production.
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
100/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
DocID025004 Rev 2
101/124
122
Package characteristics
STM32F072xx
Figure 33. UFBGA100 – ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch,
package outline
0.10
Z
D1
D
X
FD
A1 ball
pad corner
A1 ball
pad corner
Y
0.50
1.75
b
e
1.75
E1
E
A1
A
0.10
FE
A2
Top view
Side view
Bottom view
A0C2_ME
1. Drawing is not to scale.
Table 72. UFBGA100 – ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
0.460
0.530
0.080
0.450
0.250
7.000
5.500
7.000
5.500
0.500
0.750
0.750
0.600
0.0181
0.0209
0.0031
0.0177
0.0098
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
0.0295
0.0236
0.060
0.100
0.0024
0.0039
0.400
0.500
0.0157
0.0197
0.200
0.300
0.0079
0.0118
D
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D1
E
E1
e
FD
FE
1. Values in inches are converted from mm and rounded to 4 decimal digits.
102/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
Figure 34. UFBGA100 recommended footprint
'SDG
'VP
06ꢁꢍꢎꢒꢋ9ꢄ
Table 73. UFBGA100 recommended PCB design rules
Dimension
Recommended values
Pitch
0.50 mm
0.27 mm
Dpad
Dsm
0.35 mm typ (depending on the soldermask registration tolerance)
0.27 mm aperture diameter
Solder paste
Marking of engineering samples for UFBGA100
The following figure shows the engineering sample marking for the UFBGA100 package.
Only the information field containing the engineering sample marking is shown.
Figure 35. UFBGA100 package top view
ꢈ
(QJLQHHULQJꢅVDPSOHꢅPDUNLQJ
(6
06ꢀꢀꢁꢒꢍ9ꢁ
1. Samples marked “E” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
DocID025004 Rev 2
103/124
122
Package characteristics
STM32F072xx
Figure 36. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢀꢐꢅꢆ MM
'!5'% 0,!.%
CCC
#
,
$
,ꢁ
$ꢁ
$ꢂ
ꢈꢆ
ꢆꢁ
ꢆꢀ
ꢈꢇ
ꢁꢀꢀ
ꢅꢇ
0). ꢁ
)$%.4)&)#!4)/.
ꢁ
ꢅꢆ
E
ꢁ,?-%?6ꢂ
1. Drawing is not to scale.
Table 74. LQFP100 – 14 x 14 mm low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
0.6299
0.5512
0.4724
0.6299
D1
D3
E
15.800
16.200
0.6220
0.6378
104/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
Table 74. LQFP100 – 14 x 14 mm low-profile quad flat package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E1
E3
e
13.800
14.000
12.000
0.500
0.600
1.000
-
14.200
0.5433
0.5512
0.4724
0.0197
0.0236
0.0394
-
0.5591
-
-
-
-
-
-
0.750
-
-
-
0.0295
-
L
0.450
0.0177
L1
ccc
K
-
-
-
-
0.080
7°
0.0031
7°
0°
3.5°
0°
3.5°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 37. LQFP100 recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906b
1. Dimensions are in millimeters.
DocID025004 Rev 2
105/124
122
Package characteristics
STM32F072xx
Marking of engineering samples for LQFP100
The following figure shows the engineering sample marking for the LQFP100 package. Only
the information field containing the engineering sample marking is shown.
Figure 38. LQFP100 package top view
(QJLQHHULQJꢅVDPSOHꢅPDUNLQJꢁ
(6
.4ꢁꢈꢂꢅꢈ7ꢈ
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
106/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
Figure 39. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢀꢐꢅꢆ MM
'!5'% 0,!.%
CCC
#
,
$
,ꢁ
$ꢁ
$ꢂ
ꢂꢂ
ꢃꢊ
ꢂꢅ
ꢃꢉ
B
ꢇꢃ
ꢁꢈ
ꢁꢇ
ꢁ
0). ꢁ
)$%.4)&)#!4)/.
E
ꢆ7?-%?6ꢅ
1. Drawing is not to scale.
Table 75. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
12.200
10.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.4803
0.4016
-
0.050
1.350
0.170
0.090
11.800
9.800
-
-
0.0020
0.0531
0.0067
0.0035
0.4646
0.3858
-
-
1.400
0.220
0.0551
0.0087
-
c
D
12.000
10.000
7.500
0.4724
0.3937
0.2953
D1
D3
DocID025004 Rev 2
107/124
122
Package characteristics
STM32F072xx
Table 75. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E
E1
E3
e
11.800
12.000
10.000
7.500
0.500
0.600
1.000
-
12.200
0.4646
0.4724
0.3937
0.2953
0.0197
0.0236
0.0394
-
0.4803
9.800
10.200
0.3858
0.4016
-
-
-
-
-
-
0.750
-
-
-
0.0295
-
L
0.450
0.0177
L1
ccc
K
-
-
-
-
0.080
7°
0.0031
7°
0°
3.5°
0°
3.5°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 40. LQFP64 recommended footprint
ꢃꢊ
ꢂꢂ
ꢀꢐꢂ
ꢀꢐꢆ
ꢃꢉ
ꢂꢅ
ꢁꢅꢐꢈ
ꢁꢀꢐꢂ
ꢁꢀꢐꢂ
ꢇꢃ
ꢁꢈ
ꢁꢐꢅ
ꢁ
ꢁꢇ
ꢈꢐꢊ
ꢁꢅꢐꢈ
AIꢁꢃꢉꢀꢉB
1. Dimensions are in millimeters.
108/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
Marking of engineering samples for LQFP64
The following figure shows the engineering sample marking for the LQFP64 package. Only
the information field containing the engineering sample marking is shown.
Figure 41. LQFP64 package top view
(QJLQHHULQJꢅVDPSOHꢅPDUNLQJꢁ
(6
.4ꢁꢈꢂꢅꢉ7ꢈ
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
DocID025004 Rev 2
109/124
122
Package characteristics
STM32F072xx
Figure 42. LQFP48 – 7 x 7 mm, 48 pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢀꢐꢅꢆ MM
'!5'% 0,!.%
CCC
#
$
,
$ꢁ
$ꢂ
,ꢁ
ꢂꢇ
ꢅꢆ
ꢂꢈ
ꢅꢃ
B
ꢃꢊ
ꢁꢂ
0). ꢁ
)$%.4)&)#!4)/.
ꢁ
ꢁꢅ
E
ꢆ"?-%?6ꢅ
1. Drawing is not to scale.
Table 76. LQFP48 – 7 x 7 mm low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
110/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
Table 76. LQFP48 – 7 x 7 mm low-profile quad flat package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
e
L
-
0.500
0.600
1.000
-
-
0.750
-
-
0.0197
0.0236
0.0394
-
-
0.0295
-
0.450
0.0177
L1
ccc
K
-
-
-
-
0.080
7°
0.0031
7°
0°
3.5°
0°
3.5°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 43. LQFP48 recommended footprint
ꢀꢐꢆꢀ
ꢁꢐꢅꢀ
ꢀꢐꢂꢀ
ꢂꢇ
ꢅꢆ
ꢂꢈ
ꢅꢃ
ꢀꢐꢅꢀ
ꢈꢐꢂꢀ
ꢉꢐꢈꢀ ꢆꢐꢊꢀ
ꢈꢐꢂꢀ
ꢃꢊ
ꢁꢂ
ꢁꢅ
ꢁ
ꢁꢐꢅꢀ
ꢆꢐꢊꢀ
ꢉꢐꢈꢀ
AIꢁꢃꢉꢁꢁD
1. Dimensions are in millimeters.
DocID025004 Rev 2
111/124
122
Package characteristics
STM32F072xx
Marking of engineering samples for LQFP48
The following figure shows the engineering sample marking for the LQFP48 package. Only
the information field containing the engineering sample marking is shown.
Figure 44. LQFP48 package top view
ꢁ
(QJLQHHULQJꢅVDPSOHꢅPDUNLQJ
(6
06ꢀꢄꢁꢒꢃ9ꢁ
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
112/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
Figure 45. UFQFPN48 – 7 x 7 mm, 0.5 mm pitch, package outline
3LQꢅꢁꢅLGHQWLILHU
ODVHUꢅPDUNLQJꢅDUHD
'
$
(
<
(
6HDWLQJꢅ
SODQH
7
GGG
$ꢁ
E
H
'HWDLOꢅ<
'
([SRVHGꢅSDGꢅ
DUHD
'ꢄ
ꢁ
/
ꢂꢍ
&ꢅꢃꢆꢋꢃꢃ[ꢂꢋ
SLQꢁꢅFRUQHU
5ꢅꢃꢆꢁꢄꢋꢅW\Sꢆ
'HWDLOꢅ=
(ꢄ
ꢁ
ꢂꢍ
=
$ꢃ%ꢎB0(B9ꢀ
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DocID025004 Rev 2
113/124
122
Package characteristics
STM32F072xx
Table 77. UFQFPN48 – 7 x 7 mm, 0.5 mm pitch, package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
A1
D
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 46. UFQFPN48 recommended footprint
2
2
2
2
2
2
1. Dimensions are in millimeters.
114/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
Marking of engineering samples for UFQFPN48
The following figure shows the engineering sample marking for the UFQFPN48 package.
Only the information field containing the engineering sample marking is shown.
Figure 47. UFQFPN48 package top view
(QJLQHHULQJꢅVDPSOHꢅPDUNLQJꢁ
(6
06ꢀꢁꢂꢒꢎ9ꢁ
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
DocID025004 Rev 2
115/124
122
Package characteristics
STM32F072xx
Figure 48. WLCSP49 – 0.4 mm pitch, package outline
Hꢁ
EEE
=
)
$ꢁꢅEDOOꢅORFDWLRQ
ꢐ
ꢁ
$
*
'HWDLOꢅ$
Hꢄ
(
H
*
$
$ꢄ
H
%XPSꢅVLGH
6LGHꢅYLHZ
$ꢀ
)URQWꢅYLHZ
'
%XPS
$ꢁ
HHH
=
E
6HDWLQJꢅSODQH
(
'HWDLOꢅ$
$ꢁꢅRULHQWDWLRQꢅ
UHIHUHQFH
ꢈURWDWHGꢅꢎꢃꢅꢊ
DDD
ꢈꢂ;ꢊ
:DIHUꢅEDFNꢅVLGH
1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z
$ꢃ;/B0(B9ꢁ
116/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
Table 78. WLCSP49 – 0.4 mm pitch package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
b
0.525
0.555
0.175
0.380
0.025
0.250
3.277
3.109
0.400
2.400
2.400
0.438
0.354
0.585
0.0207
0.0219
0.0069
0.0150
0.0010
0.0098
0.1290
0.1224
0.0157
0.0945
0.0945
0.0173
0.0140
0.0230
-
-
-
-
-
-
-
-
-
-
-
-
0.220
0.280
0.0087
0.0110
D
3.242
3.312
0.1276
0.1304
E
3.074
3.144
0.1210
0.1238
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
F
G
N
49
aaa
bbb
ccc
ddd
eee
-
-
-
-
-
0.100
0.100
0.100
0.050
0.050
-
-
-
-
-
-
-
-
-
-
0.0039
0.0039
0.0039
0.0020
0.0020
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 49. WLCSP49 recommended footprint
'SDG
'VP
06ꢁꢍꢎꢒꢋ9ꢄ
DocID025004 Rev 2
117/124
122
Package characteristics
STM32F072xx
Table 79. WLCSP49 recommended PCB design rules (0.4 mm pitch BGA)
Dimension
Recommended values
Pitch
Dpad
0.4 mm
260 μm max. (circular)
220 μm recommended
Dsm
300 μm min. (for 260 μm diameter pad)
PCB pad design
Non-solder mask defined via underbump allowed
Marking of engineering samples for WLCSP49
The following figure shows the engineering sample marking for the WLCSP49 package.
Only the information field containing the engineering sample marking is shown.
Figure 50. WLCSP49 package top view
ꢈ
(QJLQHHULQJꢅVDPSOHꢅPDUNLQJ
(
06ꢀꢂꢄꢁꢐ9ꢁ
1. Samples marked “E” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
118/124
DocID025004 Rev 2
STM32F072xx
Package characteristics
7.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 24: General operating conditions.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x )
J
A
D
JA
Where:
T max is the maximum temperature in °C,
A
is the package junction-to- thermal resistance, in C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = (V × I ) + ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 80. Package thermal characteristics
Parameter
Symbol
Value
Unit
Thermal resistance junction-
UFBGA100 - 7 × 7 mm
55
Thermal resistance junction-
LQFP100 - 14 × 14 mm
42
44
54
32
49
Thermal resistance junction-
LQFP64 - 10 × 10 mm / 0.5 mm pitch
JA
°C/W
Thermal resistance junction-
LQFP48 - 7 × 7 mm
Thermal resistance junction-
UFQFPN48 - 7 × 7 mm
Thermal resistance junction-
WLCSP49 - 0.4 mm pitch
7.2.1
7.2.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed temperature at
maximum dissipation and to a specific maximum junction temperature.
DocID025004 Rev 2
119/124
122
Package characteristics
STM32F072xx
As applications do not commonly use the STM32F072xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum temperature T
= 82 °C (measured according to JESD51-2), I
= 50
DDmax
Amax
mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low level with I
DD
OL
= 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output at low level
OL
with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Using the values obtained in Table 80 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Note:
With this given P
we can find the T
allowed for a given device temperature range
Dmax
Amax
(order code suffix 6 or 7).
Suffix 6: T
Suffix 7: T
= T
= T
- (45°C/W × 447 mW) = 105-20.115 = 84.885 °C
- (45°C/W × 447 mW) = 125-20.115 = 104.885 °C
Amax
Amax
Jmax
Jmax
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high temperatures
with a low dissipation, as long as junction temperature T remains within the specified
J
range.
Assuming the following application conditions:
Maximum temperature T
= 100 °C (measured according to JESD51-2), I
=
DDmax
Amax
20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low level with
DD
I
= 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V= 70 mW
INTmax
= 20 × 8 mA × 0.4 V = 64 mW
IOmax
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
= 70 + 64 = 134 mW
Dmax
Thus: P
= 134 mW
Dmax
Using the values obtained in Table 80 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C
DocID025004 Rev 2
Jmax
120/124
STM32F072xx
Package characteristics
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering) unless we reduce the power dissipation in order to be able to
use suffix 6 parts.
Refer to Figure 51 to select the required temperature range (suffix 6 or 7) according to your
temperature or power requirements.
Figure 51. LQFP64 P max vs. T
D
A
ꢐꢃꢃ
ꢒꢃꢃ
ꢋꢃꢃ
ꢂꢃꢃ
ꢀꢃꢃ
ꢄꢃꢃ
ꢁꢃꢃ
ꢃ
6XIIL[ꢅꢒ
6XIIL[ꢅꢐ
ꢒꢋ
ꢐꢋ
ꢍꢋ
ꢎꢋ ꢁꢃꢋ ꢁꢁꢋ ꢁꢄꢋ ꢁꢀꢋ
7$ꢅꢈ&ꢊ
06Yꢀꢄꢁꢂꢀ9ꢁ
DocID025004 Rev 2
121/124
122
Part numbering
STM32F072xx
8
Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 81. Ordering information scheme
Example:
STM32
F
072
R
B
T
6
x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
072 = STM32F072xx
Pin count
C = 48/49 pins
R = 64 pins
V = 100 pins
Code size
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
H = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = –40 to 85 °C
7 = –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
122/124
DocID025004 Rev 2
STM32F072xx
Revision history
9
Revision history
Table 82. Document revision history
Date
Revision
Changes
13-Jan-2014
1
Initial release.
Updated “Reset and power management“ data in
Features.
Updated tS_vrefint in Table 28: Embedded internal
reference voltage.
Updated VHSEH and VHSEL in Table 38: High-speed
external user clock characteristics.
Updated VLSEH and VLSEL in Table 39: Low-speed
external user clock characteristics.
21-Feb-2014
2
Updated tS_temp in Table 63: TS characteristics.
Updated tS_vbat in Table 64: VBAT monitoring
characteristics.
Updated I2C interface characteristics section.
Updated Figure 35: UFBGA100 package top view and
Figure 50: WLCSP49 package top view.
Modified value of ts_sc and removed row VBG in
Table 62: Comparator characteristics.
DocID025004 Rev 2
123/124
123
STM32F072xx
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2014 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
124/124
DocID025004 Rev 2
相关型号：
STM32F091
ARM-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC & comm. interfaces, 2.0 - 3.6V
STMICROELECTR
STM32F091CB
ARM-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC & comm. interfaces, 2.0 - 3.6V
STMICROELECTR
STM32F091CBH6TP
ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC, and comm. interfaces, 2.0 - 3.6V
STMICROELECTR
STM32F091CBH7TP
ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC, and comm. interfaces, 2.0 - 3.6V
STMICROELECTR
STM32F091CBT6TP
ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC, and comm. interfaces, 2.0 - 3.6V
STMICROELECTR
STM32F091CBT7TP
ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC, and comm. interfaces, 2.0 - 3.6V
STMICROELECTR
STM32F091CBU6TP
ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC, and comm. interfaces, 2.0 - 3.6V
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明