STM32F091VBU6TP [STMICROELECTRONICS]
ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC, and comm. interfaces, 2.0 - 3.6V;
| 型号： | STM32F091VBU6TP |
| 厂家： | 
ST |
| 描述： | ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC, and comm. interfaces, 2.0 - 3.6V |
| 文件： | 总128页 (文件大小：1918K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F091xB STM32F091xC
ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers,
ADC, DAC, and comm. interfaces, 2.0 - 3.6V
Datasheet - production data
Features
)%*$
®
®
• Core: ARM 32-bit Cortex -M0 CPU,
frequency up to 48 MHz
LQFP100 14x14 mm
LQFP64 10x10 mm
LQFP48 7x7 mm
UFQFPN48
7x7 mm
UFBGA100
7x7 mm
UFBGA64
5x5 mm
WLCSP64
3.3x3.6mm
• Memories
– 128 to 256 Kbytes of Flash memory
– 32 Kbytes of SRAM with HW parity
• 12 timers
– One 16-bit advanced-control timer for
6 channel PWM output
• CRC calculation unit
• Reset and power management
– One 32-bit and seven 16-bit timers, with up
to 4 IC/OC, OCN, usable for IR control
decoding or DAC control
– Digital & I/Os supply: V = 2.0 V to 3.6 V
DD
– Analog supply: V
= V to 3.6 V
DD
DDA
– Power-on/Power down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop, Standby
– Independent and system watchdog timers
– SysTick timer
• Communication interfaces
– V
supply for RTC and backup registers
BAT
2
– Two I C interfaces supporting Fast Mode
• Clock management
Plus (1 Mbit/s) with 20 mA current sink, one
supporting SMBus/PMBus and wakeup
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
– Up to eight USARTs supporting master
synchronous SPI and modem control, three
with ISO7816 interface, LIN, IrDA, auto
baud rate detection and wakeup feature
– Internal 48 MHz oscillator with automatic
trimming based on ext. synchronization
– Two SPIs (18 Mbit/s) with 4 to 16
2
programmable bit frames, and with I S
• Up to 88 fast I/Os
interface multiplexed
– All mappable on external interrupt vectors
– CAN interface
– Up to 69 I/Os with 5V-tolerant capability
• HDMI CEC wakeup on header reception
• Serial wire debug (SWD)
• 96-bit unique ID
and 19 with independent supply V
DDIO2
• 12-channel DMA controller
• One 12-bit, 1.0 µs ADC (up to 16 channels)
– Conversion range: 0 to 3.6 V
®
• All packages ECOPACK 2
– Separate analog supply: 2.4 V to 3.6 V
Table 1. Device summary
• One 12-bit D/A converter (with 2 channels)
Reference
Part number
• Two fast low-power analog comparators with
STM32F091xB
STM32F091xC
STM32F091CB, STM32F091RB, STM32F091VB
STM32F091CC, STM32F091RC, STM32F091VC
programmable input and output
• Up to 24 capacitive sensing channels for
touchkey, linear and rotary touch sensors
• Calendar RTC with alarm and periodic wakeup
from Stop/Standby
January 2017
DocID026284 Rev 4
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This is information on a product in full production.
www.st.com
Contents
STM32F091xB STM32F091xC
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1
3.5.2
3.5.3
3.5.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
3.7
3.8
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9.1
3.9.2
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REFINT
3.10.3
V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
BAT
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22
3.14.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25
3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 26
3.19 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.20 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.22 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4
5
6
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 54
Embedded reset and power control block characteristics . . . . . . . . . . . 55
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.20
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
BAT
6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.8.1
7.8.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 121
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F091xB/xC family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 11
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitive sensing GPIOs available on STM32F091xB/xC devices . . . . . . . . . . . . . . . . . 20
Number of capacitive sensing channels available
on STM32F091xB/xC devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7.
Table 8.
Table 9.
2
Comparison of I C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
STM32F091xB/xC I C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
STM32F091xB/xC USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F091xB/xC SPI/I S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32F091xB/xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 41
Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 42
Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 43
Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 43
Alternate functions selected through GPIOE_AFR registers for port E . . . . . . . . . . . . . . . 44
Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 44
STM32F091xB/xC peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . 46
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 55
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Typical and maximum current consumption from V supply at V = 3.6 V . . . . . . . . . . 58
DD
DD
Typical and maximum current consumption from the V
supply . . . . . . . . . . . . . . . . . 59
DDA
Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 60
Typical and maximum current consumption from the V supply. . . . . . . . . . . . . . . . . . . 61
BAT
Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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List of tables
STM32F091xB STM32F091xC
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
R
max for f
= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
AIN
ADC
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2
I C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2
I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UFBGA64 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
WLCSP64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
WLCSP64 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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STM32F091xB STM32F091xC
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UFBGA100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LQFP100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
UFBGA64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LQFP64 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WLCSP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LQFP48 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. STM32F091xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 72
Figure 20. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 21. HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 22. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 26. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 29. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 30. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2
Figure 31. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2
Figure 32. I S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 33. UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 34. Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 35. UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 36. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 37. Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 38. LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 39. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 40. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 41. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 42. WLCSP64 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 43. Recommended footprint for WLCSP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 44. WLCSP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 45. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 46. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 47. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 48. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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8
List of figures
STM32F091xB STM32F091xC
Figure 49. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 50. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 51. UFQFPN48 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 52. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 53. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 54. LQFP64 P max versus T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
D
A
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STM32F091xB STM32F091xC
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F091xB/xC microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
®
®
®
For information on the ARM Cortex -M0 core, please refer to the Cortex -M0 Technical
Reference Manual, available from the www.arm.com website.
DocID026284 Rev 4
9/128
27
Description
STM32F091xB STM32F091xC
2
Description
The STM32F091xB/xC microcontrollers incorporate the high-performance
®
®
ARM Cortex -M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed
embedded memories (up to 256 Kbytes of Flash memory and 32 Kbytes of SRAM), and an
extensive range of enhanced peripherals and I/Os. The device offers standard
2
2
communication interfaces (two I Cs, two SPIs/one I S, one HDMI CEC and up to eight
USARTs), one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven 16-bit
timers, one 32-bit timer and an advanced-control PWM timer.
The STM32F091xB/xC microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
The STM32F091xB/xC microcontrollers include devices in seven different packages ranging
from 48 pins to 100 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included.
These features make the STM32F091xB/xC microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.
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DocID026284 Rev 4
STM32F091xB STM32F091xC
Description
Table 2. STM32F091xB/xC family device features and peripheral counts
Peripheral
STM32F091Cx
128 256
STM32F091Rx
128 256
STM32F091Vx
128 256
Flash memory (Kbyte)
SRAM (Kbyte)
32
Advanced
control
1 (16-bit)
Timers
General
purpose
5 (16-bit)
1 (32-bit)
Basic
SPI [I2S](1)
I2C
2 (16-bit)
2 [2]
2
Comm.
interfaces
USART
CAN
6
8
1
1
1
CEC
12-bit ADC
1
(number of channels)
(10 ext. + 3 int.)
(16 ext. + 3 int.)
12-bit DAC
1
(number of channels)
(2)
Analog comparator
GPIOs
2
38
17
52
88
24
Capacitive sensing
channels
18
Max. CPU frequency
Operating voltage
48 MHz
2.0 to 3.6 V
Ambient operating temperature: -40°C to 85°C / -40°C to 105°C
Junction temperature: -40°C to 105°C / -40°C to 125°C
Operating temperature
LQFP64
LQFP48
UFQFPN48
LQFP100
Packages
UFBGA64
WLCSP64
UFBGA100
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
DocID026284 Rev 4
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27
Description
STM32F091xB STM32F091xC
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12/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Functional overview
3
Functional overview
Figure 1 shows the general block diagram of the STM32F091xB/xC devices.
3.1
ARM®-Cortex®-M0 core
®
®
The ARM Cortex -M0 is a generation of ARM 32-bit RISC processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
®
®
The ARM Cortex -M0 processors feature exceptional code-efficiency, delivering the high
performance expected from an ARM core, with memory sizes usually associated with 8- and
16-bit devices.
The STM32F091xB/xC devices embed ARM core and are compatible with all ARM tools
and software.
3.2
Memories
The device has the following features:
•
32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
•
The non-volatile memory is divided into two arrays:
–
–
up to 256 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
–
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
®
–
Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and
boot in RAM selection disabled
3.3
Boot modes
At startup, the boot pin and boot selector option bits are used to select one of the three boot
options:
•
•
•
boot from User Flash memory
boot from System Memory
boot from embedded SRAM
The boot pin is shared with the standard GPIO and can be disabled through the boot
selector option bits. The boot loader is located in System Memory. It is used to reprogram
2
the Flash memory by using USART on pins PA14/PA15 or PA9/PA10 or I C on pins
PB6/PB7.
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27
Functional overview
STM32F091xB STM32F091xC
3.4
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes
•
V
= V
= 2.0 to 3.6 V: external power supply for I/Os (V
) and the internal
DDIO1
DD
DDIO1
regulator. It is provided externally through VDD pins.
•
V
= from V to 3.6 V: external analog power supply for ADC, DAC, Reset blocks,
DDA
DD
RCs and PLL (minimum voltage to be applied to V
is 2.4 V when the ADC or DAC
DDA
are used). It is provided externally through VDDA pin. The V
voltage level must be
DDA
always greater or equal to the V voltage level and must be established first.
DD
•
V
= 1.65 to 3.6 V: external power supply for marked I/Os. V
is provided
DDIO2
DDIO2
externally through the VDDIO2 pin. The V
voltage level is completely independent
DDIO2
from V or V
, but it must not be provided without a valid supply on V . The
DD
DDA
DD
V
supply is monitored and compared with the internal reference voltage
DDIO2
(V
). When the V
is below this threshold, all the I/Os supplied from this rail
REFINT
DDIO2
are disabled by hardware. The output of this comparator is connected to EXTI line 31
and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for
concerned I/Os list.
•
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
For more details on how to connect power pins, refer to Figure 13: Power supply scheme.
3.5.2
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
, without the need for an external reset circuit.
POR/PDR
•
The POR monitors only the V supply voltage. During the startup phase it is required
DD
that V
should arrive first and be greater than or equal to V
.
DDA
DD
•
The PDR monitors both the V and V
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V is higher than or
supply voltages, however the V
power
DD
DDA
DDA
DDA
equal to V
.
DD
The device features an embedded programmable voltage detector (PVD) that monitors the
power supply and compares it to the V threshold. An interrupt can be generated
V
DD
PVD
when V drops below the V
threshold and/or when V is higher than the V
DD
PVD
DD PVD
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DocID026284 Rev 4
STM32F091xB STM32F091xC
Functional overview
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3
3.5.4
Voltage regulator
The regulator has two operating modes and it is always enabled after reset.
•
•
Main (MR) is used in normal operating mode (Run).
Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
Low-power modes
The STM32F091xB/xC microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1, USART1,
USART2, USART3, COMPx, V
supply comparator or the CEC.
DDIO2
The CEC, USART1, USART2, USART3 and I2C1 peripherals can be configured to
enable the HSI RC oscillator so as to get clock for processing incoming data. If this is
used when the voltage regulator is put in low power mode, the regulator is first
switched to normal mode before the clock is provided to the given peripheral.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
DocID026284 Rev 4
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27
Functional overview
STM32F091xB STM32F091xC
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
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Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
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STM32F091xB STM32F091xC
Functional overview
Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
3.7
3.8
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Direct memory access controller (DMA)
The 12-channel general-purpose DMAs (seven channels for DMA1 and five channels for
DMA2) manage memory-to-memory, peripheral-to-memory and memory-to-peripheral
transfers.
The DMAs support circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers
(except TIM14), DAC and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
®
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M0) and 4
priority levels.
•
•
•
•
•
•
•
•
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
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27
Functional overview
STM32F091xB STM32F091xC
3.9.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 32 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 88
GPIOs can be connected to the 16 external interrupt lines.
3.10
Analog-to-digital converter (ADC)
The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
that varies linearly with
SENSE
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
TS_CAL1
0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V (± 10 mV)
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
TS_CAL2
0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V (± 10 mV)
3.10.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC and comparators. V
is internally connected to the ADC_IN17 input channel. The
REFINT
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STM32F091xB STM32F091xC
Functional overview
precise voltage of V
is individually measured for each part by ST during production
REFINT
test and stored in the system memory area. It is accessible in read-only mode.
Table 4. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT_CAL
temperature of 30 °C (± 5 °C),
0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V (± 10 mV)
3.10.3
V
battery voltage monitoring
BAT
This embedded hardware feature allows the application to measure the V
battery voltage
BAT
using the internal ADC channel ADC_IN18. As the V
voltage may be higher than V
,
BAT
DDA
and thus outside the ADC input range, the V
pin is internally connected to a bridge
BAT
divider by 2. As a consequence, the converted digital value is half the V
voltage.
BAT
3.11
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert digital signals into analog
voltage signal outputs. The chosen design structure is composed of integrated resistor
strings and an amplifier in non-inverting configuration.
This digital Interface supports the following features:
•
•
•
•
•
•
•
•
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Six DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger
outputs and the DAC interface is generating its own DMA requests.
3.12
Comparators (COMP)
The device embeds two fast rail-to-rail low-power comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low power) and
with selectable output polarity.
The reference voltage can be one of the following:
•
•
•
External I/O
DAC output pins
Internal reference voltage or submultiple (1/4, 1/2, 3/4).Refer to Table 28: Embedded
internal reference voltage for the value and precision of the internal reference voltage.
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Functional overview
STM32F091xB STM32F091xC
Both comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined into a window comparator.
3.13
Touch sensing controller (TSC)
The STM32F091xB/xC devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 24 capacitive sensing channels
distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists in
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
For operation, one capacitive sensing GPIO in each group is connected to an external
capacitor and cannot be used as effective touch sensing channel.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 5. Capacitive sensing GPIOs available on STM32F091xB/xC devices
Capacitive sensing
signal name
Pin
name
Capacitive sensing
signal name
Pin
name
Group
Group
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC5
PB0
PB1
PB2
PA9
PA10
PA11
PA12
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
PB3
PB4
1
5
PB6
PB7
PB11
PB12
PB13
PB14
PE2
2
3
4
6
7
8
PE3
PE4
PE5
PD12
PD13
PD14
PD15
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STM32F091xB STM32F091xC
Functional overview
Table 6. Number of capacitive sensing channels available
on STM32F091xB/xC devices
Number of capacitive sensing channels
STM32F091Vx STM32F091Rx STM32F091Cx
Analog I/O group
G1
G2
G3
G4
G5
G6
G7
G8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
0
0
3
3
2
3
3
3
0
0
Number of capacitive
sensing channels
24
18
17
3.14
Timers and watchdogs
The STM32F091xB/xC devices include up to six general-purpose timers, two basic timers
and an advanced control timer.
Table 7 compares the features of the different timers.
Table 7. Timer feature comparison
DMA
Timer
type
Counter
resolution
Counter
type
Prescaler
factor
Capture/compare Complementary
Timer
request
generation
channels
outputs
Advanced
control
Up, down, integer from
up/down 1 to 65536
TIM1
TIM2
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
No
4
4
4
1
2
1
-
3
-
Up, down, integer from
up/down 1 to 65536
Up, down, integer from
TIM3
-
up/down
1 to 65536
General
purpose
integer from
1 to 65536
TIM14
TIM15
Up
-
integer from
1 to 65536
Up
Up
Up
Yes
Yes
Yes
1
1
-
TIM16
TIM17
integer from
1 to 65536
TIM6
TIM7
integer from
1 to 65536
Basic
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27
Functional overview
STM32F091xB STM32F091xC
3.14.1
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
•
•
•
•
input capture
output compare
PWM generation (edge or center-aligned modes)
one-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.14.2
General-purpose timers (TIM2, 3, 14, 15, 16, 17)
There are six synchronizable general-purpose timers embedded in the STM32F091xB/xC
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F091xB/xC devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
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STM32F091xB STM32F091xC
Functional overview
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate
withTIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.14.3
3.14.4
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.14.5
3.14.6
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
•
•
•
a 24-bit down counter
autoreload capability
maskable system interrupt generation when the counter reaches 0
programmable clock source (HCLK or HCLK/8)
3.15
Real-time clock (RTC) and backup registers
The RTC and the five backup registers are supplied through a switch that takes power either
on V supply when present or through the V
pin. The backup registers are five 32-bit
DD
BAT
registers used to store 20 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, or at wake up from Standby mode.
DocID026284 Rev 4
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27
Functional overview
STM32F091xB STM32F091xC
The RTC is an independent BCD timer/counter. Its main features are the following:
•
calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
•
•
•
•
automatic correction for 28, 29 (leap year), 30, and 31 day of the month
programmable alarm with wake up from Stop and Standby mode capability
Periodic wakeup unit with programmable resolution and period.
on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock
•
•
•
digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection
timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection
•
reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
The RTC clock sources can be:
•
•
•
•
a 32.768 kHz external crystal
a resonator or oscillator
the internal low-power RC oscillator (typical frequency of 40 kHz)
the high-speed external clock divided by 32
3.16
Inter-integrated circuit interface (I2C)
2
Up to two I C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode
Plus (up to 1 Mbit/s) with 20 mA output drive on most of the associated I/Os.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). They also include programmable analog and
digital noise filters.
2
Table 8. Comparison of I C analog and digital filters
Aspect
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2Cx peripheral clocks
≥ 50 ns
–Extra filtering capability vs.
standard requirements
Benefits
Available in Stop mode
–Stable length
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Variations depending on
temperature, voltage, process
Drawbacks
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
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STM32F091xB STM32F091xC
Functional overview
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripherals can be served by the DMA controller.
Refer to Table 9 for the differences between I2C1 and I2C2.
2
Table 9. STM32F091xB/xC I C implementation
I2C features(1)
I2C1
I2C2
7-bit addressing mode
10-bit addressing mode
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive I/Os
Independent clock
SMBus
-
Wakeup from STOP
-
1. X = supported.
3.17
Universal synchronous/asynchronous receiver/transmitter
(USART)
The device embeds up to eight universal synchronous/asynchronous receivers/transmitters
(USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8) which
communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1, USART2 and USART3 support also SmartCard
communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud
rate feature, and have a clock domain independent of the CPU clock, allowing to wake up
the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.
Table 10. STM32F091xB/xC USART implementation
USART5
USART1
USART6
USART modes/features(1)
USART2
USART3
USART4
USART7
USART8
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
-
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
X
X
X
-
Smartcard mode
DocID026284 Rev 4
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27
Functional overview
STM32F091xB STM32F091xC
Table 10. STM32F091xB/xC USART implementation (continued)
USART5
USART6
USART7
USART8
USART1
USART2
USART3
USART modes/features(1)
USART4
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
X
X
X
-
X
-
-
-
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
-
-
-
-
-
-
-
-
X
X
1. X = supported.
3.18
Serial peripheral interface (SPI) / Inter-integrated sound
interface (I2S)
Two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
2
Two standard I S interfaces (multiplexed with SPI1 and SPI2 respectively) supporting four
different audio standards can operate as master or slave at half-duplex communication
mode. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, they can output a clock for an external audio component at 256 times the sampling
frequency.
2
Table 11. STM32F091xB/xC SPI/I S implementation
SPI features(1)
SPI1 and SPI2
Hardware CRC calculation
Rx/Tx FIFO
X
X
X
X
X
NSS pulse mode
I2S mode
TI mode
1. X = supported.
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STM32F091xB STM32F091xC
Functional overview
3.19
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.20
3.21
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
Clock recovery system (CRS)
The STM32F091xB/xC embeds a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from LSE oscillator, from an external signal on CRS_SYNC
pin or generated by user software. For faster lock-in during startup it is also possible to
combine automatic trimming with manual trimming action.
3.22
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
DocID026284 Rev 4
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27
Pinouts and pin descriptions
STM32F091xB STM32F091xC
4
Pinouts and pin descriptions
Figure 3. UFBGA100 package pinout
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28/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Pinouts and pin descriptions
Figure 4. LQFP100 package pinout
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DocID026284 Rev 4
29/128
40
Pinouts and pin descriptions
STM32F091xB STM32F091xC
Figure 5. UFBGA64 package pinout
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30/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Pinouts and pin descriptions
Figure 6. LQFP64 package pinout
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31/128
40
Pinouts and pin descriptions
STM32F091xB STM32F091xC
Figure 7. WLCSP64 package pinout
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versions.
Figure 8. LQFP48 package pinout
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32/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Pinouts and pin descriptions
Figure 9. UFQFPN48 package pinout
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ꢄ
966$
ꢍ
3$ꢍ
9''$
ꢂ
3%ꢊꢃ
3%ꢊꢁ
3%ꢊꢀ
3%ꢊꢅ
3$ꢋ
ꢊꢋ
ꢊꢊ
ꢊꢅ
([SRVHGꢆSDG
3$ꢊ
3$ꢅ
,ꢎ2ꢆVXSSOLHGꢆIURPꢆ9'',2ꢅ
06Yꢀꢁꢂꢀꢂ9ꢅ
Table 12. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin name
S
Supply pin
Pin type
I/O
Input / output pin
FT
5 V-tolerant I/O
FTf
TTa
TC
5 V-tolerant I/O, FM+ capable
3.3 V-tolerant I/O directly connected to ADC
Standard 3.3 V I/O
I/O structure
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset.
Notes
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
DocID026284 Rev 4
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40
Pinouts and pin descriptions
STM32F091xB STM32F091xC
Pin functions
Table 13. STM32F091xB/xC pin definitions
Pin numbers
Pin name
(function upon
reset)
Additional
functions
Alternate functions
B2
A1
B1
C2
1
2
3
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE2
PE3
PE4
PE5
I/O
I/O
I/O
I/O
FT
FT
FT
FT
TSC_G7_IO1, TIM3_ETR
TSC_G7_IO2, TIM3_CH1
TSC_G7_IO3, TIM3_CH2
TSC_G7_IO4, TIM3_CH3
-
-
-
-
WKUP3,
RTC_TAMP3
D2
E2
5
6
-
-
-
-
PE6
I/O
S
FT
-
TIM3_CH4
B2
1
B8
1
VBAT
-
Backup power supply
WKUP2,
RTC_TAMP1,
RTC_TS,
(1)
(2)
C1
7
A2
2
B7
2
PC13
I/O TC
-
RTC_OUT
PC14-
OSC32_IN
(PC14)
(1)
(2)
D1
E1
8
9
A1
B1
3
4
C8
C7
3
4
I/O TC
I/O TC
-
-
OSC32_IN
PC15-
OSC32_OUT
(PC15)
(1)
(2)
OSC32_OUT
F2 10
G2 11
-
-
-
-
-
-
-
-
PF9
I/O
I/O
FT
FT
TIM15_CH1, USART6_TX
TIM15_CH2, USART6_RX
-
-
PF10
PF0-OSC_IN
(PF0)
F1 12 C1
G1 13 D1
H2 14 E1
5
6
7
D8
E8
D7
5
6
7
I/O FTf
I/O FTf
I/O RST
CRS_ SYNC, I2C1_SDA
I2C1_SCL
OSC_IN
PF1-OSC_OUT
(PF1)
OSC_OUT
Device reset input / internal reset output
(active low)
NRST
PC0
EVENTOUT,
USART6_TX,
USART7_TX
H1 15 E3
8
9
E7
F8
-
-
I/O TTa
I/O TTa
ADC_IN10
ADC_IN11
EVENTOUT,
USART6_RX,
USART7_RX
J2
J3
16 E2
PC1
SPI2_MISO, I2S2_MCK,
EVENTOUT, USART8_TX
17 F2 10 D6
-
-
PC2
PC3
I/O TTa
I/O TTa
ADC_IN12
ADC_IN13
SPI2_MOSI, I2S2_SD,
EVENTOUT, USART8_RX
K2 18 G1 11 E6
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DocID026284 Rev 4
STM32F091xB STM32F091xC
Pinouts and pin descriptions
Pin functions
Table 13. STM32F091xB/xC pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Additional
functions
Alternate functions
EVENTOUT,
USART7_TX,
J1
19
-
-
-
-
PF2
I/O
FT
WKUP8
USART7_CK_RTS
K1 20 F1 12 G8
M1 21 H1 13 H8
8
9
VSSA
VDDA
S
S
-
-
Analog ground
Analog power supply
EVENTOUT,
L1 22
-
-
-
-
PF3
I/O
FT
USART7_RX,
USART6_CK_RTS
USART2_CTS,
TIM2_CH1_ETR,
TSC_G1_IO1,
USART4_TX
RTC_ TAMP2,
WKUP1,
ADC_IN0,
L2 23 G2 14 F7 10
PA0
I/O TTa
COMP1_INM6
COMP1_OUT
USART2_RTS,
TIM2_CH2,
TIM15_CH1N,
TSC_G1_IO2,
USART4_RX,
EVENTOUT
ADC_IN1,
COMP1_INP
M2 24 H2 15 F6 11
PA1
I/O TTa
USART2_TX, TIM2_CH3,
TIM15_CH1,
ADC_IN2,
WKUP4,
COMP2_INM6
K3 25 F3 16 E5 12
PA2
PA3
I/O TTa
I/O TTa
TSC_G1_IO3
COMP2_OUT
USART2_RX,TIM2_CH4,
TIM15_CH2,
ADC_IN3,
COMP2_INP
L3 26 G3 17 H7 13
TSC_G1_IO4
D3 27 C2 18 G7
H3 28 D2 19 G6
-
-
VSS
VDD
S
S
-
-
Ground
Digital power supply
SPI1_NSS, I2S1_WS,
TIM14_CH1,
COMP1_INM4,
COMP2_INM4,
ADC_IN4,
M3 29 H3 20 H6 14
PA4
PA5
I/O TTa
I/O TTa
TSC_G2_IO1,
USART2_CK,
USART6_TX
DAC_OUT1
SPI1_SCK, I2S1_CK,
CEC,
TIM2_CH1_ETR,
TSC_G2_IO2,
USART6_RX
COMP1_INM5,
COMP2_INM5,
ADC_IN5,
K4 30 F4 21 F5 15
DAC_OUT2
DocID026284 Rev 4
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40
Pinouts and pin descriptions
STM32F091xB STM32F091xC
Pin functions
Table 13. STM32F091xB/xC pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Additional
functions
Alternate functions
SPI1_MISO, I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
TIM16_CH1,
L4 31 G4 22 G5 16
PA6
PA7
I/O TTa
COMP1_OUT,
TSC_G2_IO3,
EVENTOUT,
USART3_CTS
ADC_IN6
SPI1_MOSI, I2S1_SD,
TIM3_CH2, TIM14_CH1,
TIM1_CH1N, TIM17_CH1,
COMP2_OUT,
M4 32 H4 23 E4 17
I/O TTa
ADC_IN7
TSC_G2_IO4,
EVENTOUT
K5 33 H5 24 H5
L5 34 H6 25 F4
-
-
PC4
PC5
I/O TTa
I/O TTa
EVENTOUT, USART3_TX
ADC_IN14
TSC_G3_IO1,
USART3_RX
ADC_IN15,
WKUP5
TIM3_CH3, TIM1_CH2N,
TSC_G3_IO2,
M5 35 F5 26 G4 18
PB0
PB1
I/O TTa
I/O TTa
ADC_IN8
ADC_IN9
EVENTOUT,
USART3_CK
TIM3_CH4,
USART3_RTS,
TIM14_CH1, TIM1_CH3N,
TSC_G3_IO3
M6 36 G5 27 F3 19
L6 37 G6 28 H4 20
PB2
PE7
I/O
I/O
FT
FT
TSC_G3_IO4
-
-
TIM1_ETR,
USART5_CK_RTS
M7 38
-
-
-
-
TIM1_CH1N,
USART4_TX
L7 39
M8 40
L8 41
M9 42
L9 43
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE8
PE9
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
-
-
-
-
-
TIM1_CH1, USART4_RX
TIM1_CH2N,
USART5_TX
PE10
PE11
PE12
TIM1_CH2, USART5_RX
SPI1_NSS, I2S1_WS,
TIM1_CH3N
SPI1_SCK, I2S1_CK,
TIM1_CH3
M10 44
-
-
-
-
PE13
I/O
FT
-
36/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Pinouts and pin descriptions
Pin functions
Table 13. STM32F091xB/xC pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Additional
functions
Alternate functions
SPI1_MISO, I2S1_MCK,
TIM1_CH4
M11 45
M12 46
-
-
-
-
-
-
-
-
PE14
PE15
I/O
I/O
FT
FT
-
-
SPI1_MOSI, I2S1_SD,
TIM1_BKIN
SPI2_SCK, I2S2_CK,
I2C2_SCL,
USART3_TX, CEC,
TSC_SYNC, TIM2_CH3
L10 47 G7 29 G3 21
PB10
PB11
I/O FTf
I/O FTf
-
-
USART3_RX, TIM2_CH4,
EVENTOUT,
L11 48 H7 30 H3 22
TSC_G6_IO1,
I2C2_SDA
F12 49 D5 31 H2 23
G12 50 E5 32 H1 24
VSS
VDD
S
S
-
-
Ground
Digital power supply
TIM1_BKIN, TIM15_BKIN,
SPI2_NSS, I2S2_WS,
USART3_CK,
L12 51 H8 33 G2 25
PB12
PB13
I/O
FT
-
-
-
TSC_G6_IO2,
EVENTOUT
SPI2_SCK, I2S2_CK,
I2C2_SCL,
K12 52 G8 34 F2 26
I/O FTf
USART3_CTS,
TIM1_CH1N,
TSC_G6_IO3
SPI2_MISO, I2S2_MCK,
I2C2_SDA,
USART3_RTS,
TIM1_CH2N, TIM15_CH1,
TSC_G6_IO4
K11 53 F8 35 G1 27
PB14
PB15
I/O FTf
SPI2_MOSI, I2S2_SD,
TIM1_CH3N,
WKUP7,
RTC_REFIN
K10 54 F7 36 F1 28
I/O
FT
TIM15_CH1N,
TIM15_CH2
K9 55
K8 56
J12 57
J11 58
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD8
PD9
I/O
I/O
I/O
I/O
FT
FT
FT
FT
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
-
-
-
-
PD10
PD11
DocID026284 Rev 4
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40
Pinouts and pin descriptions
STM32F091xB STM32F091xC
Pin functions
Table 13. STM32F091xB/xC pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Additional
functions
Alternate functions
USART3_RTS,
TSC_G8_IO1,
J10 59
-
-
-
-
PD12
I/O
FT
-
USART8_CK_RTS
TSC_G8_IO2,
USART8_TX
H12 60
H11 61
-
-
-
-
-
-
-
-
PD13
PD14
I/O
I/O
FT
FT
-
-
TSC_G8_IO3,
USART8_RX
TSC_G8_IO4,
CRS_SYNC,
H10 62
-
-
-
-
PD15
I/O
FT
-
USART7_CK_RTS
(3)
(3)
(3)
(3)
E12 63 F6 37 E1
E11 64 E7 38 D1
E10 65 E8 39 E2
D12 66 D8 40 E3
-
-
-
-
PC6
PC7
PC8
PC9
I/O
I/O
I/O
I/O
FT
FT
FT
FT
TIM3_CH1, USART7_TX
TIM3_CH2, USART7_RX
TIM3_CH3, USART8_TX
TIM3_CH4, USART8_RX
-
-
-
-
USART1_CK, TIM1_CH1,
EVENTOUT, MCO,
CRS_SYNC
(3)
(3)
(3)
D11 67 D7 41 D2 29
D10 68 C7 42 C1 30
C12 69 C6 43 C2 31
PA8
PA9
I/O
I/O
I/O
FT
FT
FT
-
-
-
USART1_TX, TIM1_CH2,
TIM15_BKIN, MCO,
TSC_G4_IO1, I2C1_SCL
USART1_RX, TIM1_CH3,
TIM17_BKIN,
PA10
TSC_G4_IO2, I2C1_SDA
CAN_RX, USART1_CTS,
TIM1_CH4,COMP1_OUT,
TSC_G4_IO3,
(3)
(3)
B12 70 C8 44 D3 32
PA11
I/O
FT
-
-
EVENTOUT, I2C2_SCL
CAN_TX, USART1_RTS,
TIM1_ETR,COMP2_OUT,
TSC_G4_IO4,
A12 71 B8 45 B1 33
A11 72 A8 46 C3 34
PA12
PA13
I/O
I/O
FT
FT
EVENTOUT, I2C2_SDA
(3)
(4)
IR_OUT, SWDIO
-
-
(3)
C11 73
-
-
-
-
PF6
VSS
I/O
S
FT
-
F11 74 D6 47 B2 35
G11 75 E6 48 A1 36
-
-
Ground
VDDIO2
S
Digital power supply
38/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Pinouts and pin descriptions
Pin functions
Table 13. STM32F091xB/xC pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Additional
functions
Alternate functions
(3)
(4)
A10 76 A7 49 B3 37
PA14
PA15
I/O
I/O
FT
FT
USART2_TX, SWCLK
-
-
SPI1_NSS, I2S1_WS,
USART2_RX,
USART4_RTS,
TIM2_CH1_ETR,
EVENTOUT
(3)
A9 77 A6 50 A2 38
USART3_TX,
USART4_TX
(3)
(3)
B11 78 B7 51 A3
C10 79 B6 52 C4
-
-
PC10
PC11
I/O
I/O
FT
FT
-
-
USART3_RX,
USART4_RX
USART3_CK,
USART4_CK,
USART5_TX
(3)
B10 80 C5 53 B4
-
PC12
I/O
FT
-
SPI2_NSS, I2S2_WS,
CAN_RX
(3)
(3)
(3)
C9 81
B9 82
-
-
-
-
-
-
-
-
-
-
-
PD0
PD1
PD2
PD3
PD4
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
-
-
-
-
-
SPI2_SCK, I2S2_CK
CAN_TX
USART3_RTS,
TIM3_ETR, USART5_RX
C8 83 B5 54 A4
SPI2_MISO, I2S2_MCK,
USART2_CTS
B8 84
B7 85
-
-
-
-
-
-
SPI2_MOSI, I2S2_SD,
USART2_RTS
A6 86
B6 87
A5 88
-
-
-
-
-
-
-
-
-
-
-
-
PD5
PD6
PD7
I/O
I/O
I/O
FT
FT
FT
USART2_TX
USART2_RX
USART2_CK
-
-
-
SPI1_SCK, I2S1_CK,
TIM2_CH2, TSC_G5_IO1,
EVENTOUT, USART5_TX
A8 89 A5 55 D4 39
PB3
PB4
I/O
I/O
FT
FT
-
-
SPI1_MISO, I2S1_MCK,
TIM17_BKIN, TIM3_CH1,
TSC_G5_IO2,
A7 90 A4 56 D5 40
EVENTOUT, USART5_RX
DocID026284 Rev 4
39/128
40
Pinouts and pin descriptions
STM32F091xB STM32F091xC
Pin functions
Table 13. STM32F091xB/xC pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Additional
functions
Alternate functions
SPI1_MOSI, I2S1_SD,
I2C1_SMBA,
C5 91 C4 57 C5 41
PB5
I/O
FT
TIM16_BKIN,
WKUP6
TIM3_CH2,
USART5_CK_RTS
I2C1_SCL, USART1_TX,
TIM16_CH1N,
B5 92 D3 58 A5 42
PB6
PB7
I/O FTf
I/O FTf
-
-
TSC_G5_I03
I2C1_SDA, USART1_RX,
USART4_CTS,
B4 93 C3 59 B5 43
TIM17_CH1N,
TSC_G5_IO4
Boot memory
selection
A4 94 B4 60 C6 44
A3 95 B3 61 A6 45
PF11-BOOT0
PB8
I/O
FT
-
I2C1_SCL, CEC,
TIM16_CH1, TSC_SYNC,
CAN_RX
I/O FTf
I/O FTf
-
-
SPI2_NSS, I2S2_WS,
I2C1_SDA, IR_OUT,
TIM17_CH1, EVENTOUT,
CAN_TX
B3 96 A3 62 B6 46
PB9
C3 97
A2 98
-
-
-
-
-
-
-
-
PE0
PE1
VSS
VDD
I/O
I/O
S
FT
FT
-
EVENTOUT, TIM16_CH1
EVENTOUT, TIM17_CH1
Ground
-
-
D3 99 D4 63 A7 47
C4 100 E4 64 A8 48
S
-
Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content
of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC
domain and RTC register descriptions in the reference manual.
3. PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1 and PD2 I/Os
are supplied by VDDIO2
4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin
and the internal pull-down on the SWCLK pin are activated.
40/128
DocID026284 Rev 4
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PA0
PA1
-
USART2_CTS TIM2_CH1_ETR TSC_G1_IO1
USART4_TX
-
-
-
-
-
-
-
COMP1_OUT
EVENTOUT
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
CEC
TIM2_CH2
TIM2_CH3
TIM2_CH4
-
TSC_G1_IO2 USART4_RX TIM15_CH1N
-
PA2
TIM15_CH1
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
-
-
COMP2_OUT
PA3
TIM15_CH2
-
-
-
-
-
PA4
SPI1_NSS, I2S1_WS
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
MCO
TIM14_CH1
-
USART6_TX
USART6_RX
PA5
TIM2_CH1_ETR TSC_G2_IO2
PA6
TIM3_CH1
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
-
TSC_G2_IO3 USART3_CTS TIM16_CH1
EVENTOUT COMP1_OUT
EVENTOUT COMP2_OUT
PA7
TIM3_CH2
TSC_G2_IO4
EVENTOUT
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
-
TIM14_CH1
CRS_SYNC
I2C1_SCL
I2C1_SDA
CAN_RX
CAN_TX
-
TIM17_CH1
PA8
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
USART1_RTS
IR_OUT
-
-
-
-
-
-
-
-
-
-
PA9
TIM15_BKIN
MCO
-
PA10
PA11
PA12
PA13
PA14
PA15
TIM17_BKIN
-
-
EVENTOUT
I2C2_SCL
COMP1_OUT
EVENTOUT
I2C2_SDA
COMP2_OUT
SWDIO
-
-
-
-
-
-
SWCLK
USART2_TX
USART2_RX
-
-
-
SPI1_NSS, I2S1_WS
TIM2_CH1_ETR EVENTOUT USART4_RTS
Table 15. Alternate functions selected through GPIOB_AFR registers for port B
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
PB0
PB1
EVENTOUT
TIM14_CH1
TIM3_CH3
TIM3_CH4
-
TIM1_CH2N
TIM1_CH3N
-
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G5_IO1
TSC_G5_IO2
I2C1_SMBA
TSC_G5_IO3
TSC_G5_IO4
TSC_SYNC
USART3_CK
USART3_RTS
-
-
-
PB2
-
-
PB3
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
USART1_TX
EVENTOUT
TIM3_CH1
TIM3_CH2
I2C1_SCL
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
EVENTOUT
-
TIM2_CH2
EVENTOUT
TIM16_BKIN
TIM16_CH1N
TIM17_CH1N
TIM16_CH1
TIM17_CH1
TIM2_CH3
TIM2_CH4
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
USART5_TX
USART5_RX
USART5_CK_RTS
-
-
PB4
TIM17_BKIN
PB5
-
PB6
-
PB7
USART1_RX
USART4_CTS
CAN_RX
-
PB8
CEC
-
PB9
IR_OUT
EVENTOUT
TSC_SYNC
CAN_TX
SPI2_NSS, I2S2_WS
PB10
PB11
PB12
PB13
PB14
PB15
CEC
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
-
SPI2_SCK, I2S2_CK
EVENTOUT
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TIM15_CH1N
-
SPI2_NSS, I2S2_WS
SPI2_SCK, I2S2_CK
SPI2_MISO, I2S2_MCK
SPI2_MOSI, I2S2_SD
TIM15_BKIN
I2C2_SCL
I2C2_SDA
-
TIM15_CH1
TIM15_CH2
STM32F091xB STM32F091xC
Table 16. Alternate functions selected through GPIOC_AFR registers for port C
Pin name
AF0
AF1
AF2
PC0
PC1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TSC_G3_IO1
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
USART4_TX
USART4_RX
USART4_CK
-
USART7_TX
USART7_RX
SPI2_MISO, I2S2_MCK
SPI2_MOSI, I2S2_SD
USART3_TX
USART3_RX
USART7_TX
USART7_RX
USART8_TX
USART8_RX
USART3_TX
USART3_RX
USART3_CK
-
USART6_TX
USART6_RX
PC2
USART8_TX
PC3
USART8_RX
PC4
-
PC5
-
PC6
-
PC7
-
PC8
-
PC9
-
PC10
PC11
PC12
PC13
PC14
PC15
-
-
USART5_TX
-
-
-
-
-
-
-
Table 17. Alternate functions selected through GPIOD_AFR registers for port D
Pin name
AF0
AF1
AF2
PD0
PD1
CAN_RX
CAN_TX
SPI2_NSS, I2S2_WS
-
SPI2_SCK, I2S2_CK
-
PD2
TIM3_ETR
USART3_RTS
USART5_RX
PD3
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
USART8_TX
USART8_RX
CRS_SYNC
SPI2_MISO, I2S2_MCK
-
PD4
SPI2_MOSI, I2S2_SD
-
PD5
-
-
PD6
-
-
PD7
-
-
PD8
-
-
PD9
-
-
PD10
PD11
PD12
PD13
PD14
PD15
-
-
-
-
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
USART8_CK_RTS
-
-
USART7_CK_RTS
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44
STM32F091xB STM32F091xC
Table 18. Alternate functions selected through GPIOE_AFR registers for port E
Pin name
AF0
AF1
PE0
PE1
TIM16_CH1
TIM17_CH1
TIM3_ETR
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
EVENTOUT
EVENTOUT
PE2
TSC_G7_IO1
PE3
TSC_G7_IO2
PE4
TSC_G7_IO3
PE5
TSC_G7_IO4
PE6
-
PE7
USART5_CK_RTS
USART4_TX
PE8
PE9
USART4_RX
PE10
PE11
PE12
PE13
PE14
PE15
USART5_TX
USART5_RX
SPI1_NSS, I2S1_WS
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
Table 19. Alternate functions selected through GPIOF_AFR registers for port F
Pin
AF0
AF1
AF2
name
PF0
PF1
PF2
PF3
PF6
PF9
PF10
CRS_SYNC
-
I2C1_SDA
I2C1_SCL
USART7_TX
USART7_RX
-
-
-
EVENTOUT
EVENTOUT
-
USART7_CK_RTS
USART6_CK_RTS
-
-
-
TIM15_CH1
TIM15_CH2
USART6_TX
USART6_RX
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STM32F091xB STM32F091xC
Memory mapping
5
Memory mapping
To the difference of STM32F091xC memory map in Figure 10, the two bottom code memory
spaces of STM32F091xB end at 0x0001 FFFF and 0x0801 FFFF, respectively.
Figure 10. STM32F091xC memory map
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DocID026284 Rev 4
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48
Memory mapping
STM32F091xB STM32F091xC
Table 20. STM32F091xB/xC peripheral register boundary addresses
Bus
Boundary address
Size
Peripheral
0x4800 1800 - 0x5FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
~384 MB
1 KB
Reserved
GPIOF
1 KB
GPIOE
1 KB
GPIOD
AHB2
1 KB
GPIOC
1 KB
GPIOB
1 KB
GPIOA
~128 MB
1 KB
Reserved
TSC
3 KB
Reserved
CRC
1 KB
3 KB
Reserved
Flash memory interface
Reserved
RCC
AHB1
1 KB
3 KB
1 KB
3 KB
Reserved
DMA
1 KB
32 KB
Reserved
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STM32F091xB STM32F091xC
Memory mapping
Table 20. STM32F091xB/xC peripheral register boundary addresses (continued)
Bus
Boundary address
Size
Peripheral
0x4001 5C00 - 0x4001 7FFF
0x4001 5800 - 0x4001 5BFF
0x4001 4C00 - 0x4001 57FF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0x4001 2000 - 0x4001 23FF
0x4001 1C00 – 0x4001 1FFF
0x4001 1800 – 0x4001 1BFF
0x4001 1400 – 0x4001 17FF
0x4001 0800 - 0x4001 13FF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 8000 - 0x4000 FFFF
9 KB
1 KB
3 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
3 KB
1 KB
1 KB
32 KB
Reserved
DBGMCU
Reserved
TIM17
TIM16
TIM15
Reserved
USART1
Reserved
SPI1/I2S1
TIM1
APB
Reserved
ADC
Reserved
USART8
USART7
USART6
Reserved
EXTI
SYSCFG + COMP
Reserved
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Memory mapping
STM32F091xB STM32F091xC
Table 20. STM32F091xB/xC peripheral register boundary addresses (continued)
Bus
Boundary address
Size
Peripheral
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6100 - 0x4000 63FF
0x4000 6000 - 0x4000 60FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 3C00 - 0x4000 43FF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1800 - 0x4000 1FFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0800 - 0x4000 0FFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
768 B
256 B
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
2 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
2 KB
1 KB
1 KB
2 KB
1 KB
1 KB
Reserved
CEC
DAC
PWR
CRS
Reserved
BxCAN
Reserved
CAN RAM
Reserved
I2C2
I2C1
USART5
USART4
USART3
USART2
Reserved
SPI2
APB
Reserved
IWDG
WWDG
RTC
Reserved
TIM14
Reserved
TIM7
TIM6
Reserved
TIM3
TIM2
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STM32F091xB STM32F091xC
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3.3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
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99
Electrical characteristics
STM32F091xB STM32F091xC
6.1.6
Power supply scheme
Figure 13. Power supply scheme
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Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
50/128
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STM32F091xB STM32F091xC
Electrical characteristics
6.1.7
Current consumption measurement
Figure 14. Current consumption measurement scheme
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99
Electrical characteristics
STM32F091xB STM32F091xC
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics,
Table 22: Current characteristics and Table 23: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
(1)
Table 21. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
V
DD–VSS External main supply voltage
- 0.3
- 0.3
4.0
V
V
VDDIO2–VSS External I/O supply voltage
VDDA–VSS External analog supply voltage
4.0
- 0.3
4.0
V
VDD–VDDA Allowed voltage difference for VDD > VDDA
-
0.4
V
VBAT–VSS External backup supply voltage
- 0.3
4.0
V
Input voltage on FT and FTf pins
VSS - 0.3
VSS - 0.3
VSS - 0.3
-
VDDIOx + 4.0 (3)
V
(2)
VIN
Input voltage on TTa pins
4.0
4.0
50
V
Input voltage on any other pin
V
|∆VDDx
|
Variations between different VDD power pins
mV
Variations between all the different ground
pins
|VSSx - VSS
|
-
50
mV
-
Electrostatic discharge voltage
(human body model)
see Section 6.3.12: Electrical
sensitivity characteristics
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to for the maximum allowed injected current values.
3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is
enabled, the maximum limit is 4 V.
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STM32F091xB STM32F091xC
Symbol
Electrical characteristics
Table 22. Current characteristics
Ratings
Max.
Unit
ΣIVDD
ΣIVSS
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
120
-120
100
-100
25
IVDD(PIN)
IVSS(PIN)
IIO(PIN)
Output current source by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os supplied by VDDIO2
Injected current on FT and FTf pins
-25
80
ΣIIO(PIN)
-80
mA
-40
-5/+0(4)
(3)
IINJ(PIN)
Injected current on TC and RST pin
± 5
Injected current on TTa pins(5)
± 5
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 59: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 23. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
TSTG
TJ
–65 to +150
150
°C
°C
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Electrical characteristics
STM32F091xB STM32F091xC
6.3
Operating conditions
6.3.1
General operating conditions
Table 24. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK
VDD
Internal AHB clock frequency
Internal APB clock frequency
Standard operating voltage
-
-
-
0
0
48
48
MHz
2.0
3.6
V
V
Must not be supplied if VDD
is not present
VDDIO2
I/O supply voltage
1.65
VDD
2.4
3.6
3.6
3.6
Analog operating voltage
(ADC and DAC not used)
Must have a potential equal
to or higher than VDD
VDDA
V
Analog operating voltage
(ADC and DAC used)
VBAT
Backup operating voltage
-
TC and RST I/O
TTa I/O
1.65
-0.3
-0.3
-0.3
-
3.6
V
V
VDDIOx+0.3
VIN
I/O input voltage
V
DDA+0.3(1)
5.5(1)
364
FT and FTf I/O
UFBGA100
LQFP100
-
476
LQFP64
-
455
Power dissipation at TA = 85 °C
PD
for suffix 6 or TA = 105 °C for WLCSP64
-
377
mW
suffix 7(2)
UFBGA64
-
308
LQFP48
-
370
UFQFPN48
-
625
Maximum power dissipation
–40
–40
–40
–40
–40
–40
85
Ambient temperature for the
suffix 6 version
°C
°C
°C
Low power dissipation(3)
Maximum power dissipation
Low power dissipation(3)
Suffix 6 version
105
TA
TJ
105
Ambient temperature for the
suffix 7 version
125
105
Junction temperature range
Suffix 7 version
125
1. For operation with a voltage higher than VDDIOx + 0.3 V, the internal pull-up resistor must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Section 7.8: Thermal characteristics
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristics).
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 25 are derived from tests performed under the ambient
temperature condition summarized in Table 24.
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Electrical characteristics
Table 25. Operating conditions at power-up / power-down
Symbol
Parameter
VDD rise time rate
VDD fall time rate
VDDA rise time rate
VDDA fall time rate
Conditions
Min
0
Max
∞
Unit
tVDD
-
20
0
∞
µs/V
∞
tVDDA
-
20
∞
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 26 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions.
Table 26. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Falling edge(2)
1.96(3)
2.00
-
1.80
1.84(3)
-
1.88
1.92
40
V
V
Power on/power down
reset threshold
(1)
VPOR/PDR
Rising edge
VPDRhyst
PDR hysteresis
-
-
mV
ms
(4)
tRSTTEMPO
Reset temporization
1.50
2.50
4.50
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD
.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
Table 27. Programmable voltage detector characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.1
2
2.18
2.08
2.28
2.18
2.38
2.28
2.48
2.38
2.58
2.48
2.68
2.58
2.26
2.16
2.37
2.27
2.48
2.38
2.58
2.48
2.69
2.59
2.79
2.69
V
V
V
V
V
V
V
V
V
V
V
V
VPVD0
PVD threshold 0
2.19
2.09
2.28
2.18
2.38
2.28
2.47
2.37
2.57
2.47
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
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Table 27. Programmable voltage detector characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
-
2.66
2.56
2.76
2.66
-
2.78
2.68
2.88
2.78
100
2.9
2.8
3
V
V
VPVD6
PVD threshold 6
V
VPVD7
PVD threshold 7
2.9
V
(1)
VPVDhyst
IDD(PVD)
PVD hysteresis
-
mV
µA
PVD current consumption
-
-
0.15 0.26(1)
1. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 28 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions.
Table 28. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Internal reference voltage –40 °C < TA < +105 °C
1.2
1.23 1.25
V
V
REFINT
ADC_IN17 buffer startup
time
tSTART
-
-
-
-
10(1)
µs
µs
ADC sampling time when
reading the internal
reference voltage
4(1)
tS_vrefint
-
-
Internal reference voltage
spread over the
temperature range
10(1)
∆VREFINT
VDDA = 3 V
-
-
-
mV
- 100(1)
100(1)
TCoeff
Temperature coefficient
-
ppm/°C
1. Guaranteed by design, not tested in production.
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
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Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f
frequency:
HCLK
–
–
0 wait state and Prefetch OFF from 0 to 24 MHz
1 wait state and Prefetch ON above 24 MHz
= f
•
When the peripherals are enabled f
PCLK
HCLK
The parameters given in Table 29 to Table 32 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 24: General
operating conditions.
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STM32F091xB STM32F091xC
Table 29. Typical and maximum current consumption from V supply at V = 3.6 V
DD
DD
All peripherals enabled
All peripherals disabled
(1)
(1)
Max @ TA
Max @ TA
Conditions
fHCLK
Unit
Typ
Typ
25 °C
85 °C 105 °C
25 °C 85 °C 105 °C
HSI48
48 MHz 26.9
48 MHz 26.7
32 MHz 18.0
24 MHz 14.0
29.5
29.2
20.4
15.7
5.3
30.3
30.1
20.8
16.1
5.5
30.6
30.3
21.0
16.2
5.9
14.7 16.1
14.6 16.0
10.1 10.8
16.3
16.2
10.9
9.2
16.4
16.2
11.0
9.4
HSEbypass,
PLL on
8.5
3.0
1.0
9.0
3.2
1.1
8 MHz
1 MHz
4.8
1.3
3.3
3.5
HSEbypass,
PLL off
1.5
1.6
1.9
1.2
1.4
48 MHz 26.8
32 MHz 18.1
24 MHz 14.1
29.4
20.5
15.9
30.2
20.9
16.2
30.5
21.2
16.4
14.7 16.1
10.2 10.9
16.3
11.0
9.2
16.3
11.1
9.5
HSI clock,
PLL on
8.6
3.1
9.1
3.2
HSI clock,
PLL off
8 MHz
4.9
5.4
5.6
5.9
3.4
3.5
mA
HSI48
48 MHz 26.3
48 MHz 26.0
32 MHz 17.4
24 MHz 13.3
28.7
28.4
19.5
15.1
4.9
29.5
29.2
19.9
15.5
5.1
29.7
29.4
20.1
15.6
5.3
14.0 15.3
13.9 15.2
15.5
15.4
10.4
8.4
15.7
15.6
10.5
8.5
HSEbypass,
PLL on
9.6
7.6
2.4
0.5
10.3
8.2
8 MHz
1 MHz
4.4
0.9
2.6
0.6
2.8
2.9
HSEbypass,
PLL off
IDD
0.9
1.0
1.2
0.7
0.8
48 MHz 26.1
32 MHz 17.5
24 MHz 13.3
28.5
19.6
15.3
29.3
20.0
15.7
29.5
20.3
15.8
13.9 15.3
15.5
10.5
8.5
15.6
10.6
8.6
HSI clock,
PLL on
9.7
7.7
10.4
8.2
HSI clock,
PLL off
8 MHz
4.6
5.0
5.2
5.4
2.5
2.7
2.9
3.0
HSI48
48 MHz 17.0
48 MHz 16.9
32 MHz 11.3
18.7
18.5
12.6
9.8
19.1
19.0
12.8
10.0
3.4
19.4
19.3
13.1
10.1
3.7
3.2
3.1
2.2
1.7
0.8
0.3
3.1
2.3
1.8
3.5
3.5
2.4
1.9
0.9
0.4
3.5
2.5
2.0
3.6
3.5
2.5
2.0
0.9
0.4
3.6
2.6
2.1
3.7
3.6
2.6
2.0
1.0
0.5
3.7
2.7
2.2
HSEbypass,
PLL on
24 MHz
8 MHz
1 MHz
8.6
2.9
0.4
3.2
HSEbypass,
PLL off
mA
0.6
0.6
0.7
48 MHz 17.0
32 MHz 11.4
18.6
12.7
9.9
19.0
13.0
10.1
19.4
13.2
10.2
HSI clock,
PLL on
24 MHz
8 MHz
8.7
3.0
HSI clock,
PLL off
3.3
3.5
3.8
0.8
0.9
1.0
1.1
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1. Data based on characterization results, not tested in production unless otherwise specified.
Table 30. Typical and maximum current consumption from the V
supply
= 3.6 V
DDA
DDA
V
= 2.4 V
V
DDA
(2)
(2)
Conditions
Max @ TA
25 °C 85 °C 105 °C
Max @ TA
25 °C 85 °C 105 °C
Symbol
fHCLK
Unit
(1)
Typ
Typ
HSI48
48 MHz 312
48 MHz 147
32 MHz 101
24 MHz 80
333
168
119
96
338
178
125
98
347
181
127
100
3.9
316
160
109
87
334
181
127
101
4.3
341
192
135
106
4.6
350
197
138
109
4.7
HSE
bypass,
PLL on
Supply
current in
Run or
Sleep
HSE
bypass,
PLL off
8 MHz
1 MHz
2.8
2.7
3.5
3.7
3.7
mode,
IDDA
code
µA
3.2
3.5
3.8
3.3
3.9
4.4
4.7
executing
from
Flash
memory
or RAM
48 MHz 214
32 MHz 166
24 MHz 144
243
193
171
254
203
177
259
204
178
235
185
161
262
207
180
275
216
187
281
220
190
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
65
83
85
86
77
90
92
93
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent from
the frequency.
2. Data based on characterization results, not tested in production unless otherwise specified.
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Table 31. Typical and maximum consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA
)
Max(1)
Sym-
bol
Para-
meter
Conditions
Unit
TA =
TA =
TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 °C 85 °C 105 °C
Regulator in run
mode, all
oscillators OFF
14.6 14.8 14.9 15.1 15.4 15.8
18
11
51
53
97
Supply
current in
Stop
Regulator in low-
power mode, all
oscillators OFF
mode
3.3
3.4
3.6
3.8
4.1
4.4
106
IDD
LSI ON and IWDG
ON
Supply
current in
Standby
mode
0.9
0.6
1.0
0.7
1.1
0.8
1.2
0.9
1.3
1.0
1.4
1.1
2.3
1.9
2.7
2.3
3.6
3.0
LSI OFF and IWDG
OFF
Regulator in
run mode, all
oscillators
OFF
1.9
1.9
2.0
2.0
2.2
2.2
2.3
2.3
2.4
2.4
2.6
2.6
3.8
3.8
4.2
4.2
4.6
4.6
Supply
current in
Stop
Regulator in
low-power
mode, all
oscillators
OFF
mode
µA
LSI ON and
IWDG ON
Supply
current in
Standby
mode
2.3
1.8
2.5
1.9
2.7
2.0
2.8
2.2
3.0
2.3
3.3
2.5
3.8
3.6
4.2
3.9
4.8
4.2
LSI OFF and
IWDG OFF
IDDA
Regulator in
run mode, all
oscillators
OFF
1.2
1.2
1.2
1.2
1.3
1.3
1.3
1.3
1.4
1.4
1.4
1.4
-
-
-
-
-
-
Supply
current in
Stop
Regulator in
low-power
mode, all
oscillators
OFF
mode
LSI ON and
IWDG ON
Supply
current in
Standby
mode
1.6
1.1
1.7
1.1
1.8
1.1
1.9
1.2
2.0
1.3
2.1
1.3
-
-
-
-
-
-
LSI OFF and
IWDG OFF
1. Data based on characterization results, not tested in production unless otherwise specified.
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Table 32. Typical and maximum current consumption from the V
supply
Max(1)
BAT
Typ @ VBAT
Symbol Parameter
Conditions
Unit
TA =
TA =
TA =
25 °C 85 °C 105 °C
LSE & RTC ON; “Xtal
mode”: lower driving
capability;
0.5 0.5 0.6 0.7 0.9 1.0
1.0
1.4
1.3
1.7
1.8
2.2
RTC
domain
supply
current
LSEDRV[1:0] = '00'
IDD VBAT
_
µA
LSE & RTC ON; “Xtal
mode” higher driving
capability;
0.8 0.8 0.9 1.0 1.2 1.3
LSEDRV[1:0] = '11'
1. Data based on characterization results, not tested in production.
Typical current consumption
The MCU is placed under the following conditions:
•
•
•
V
= V
= 3.3 V
DDA
DD
All I/O pins are in analog input configuration
The Flash memory access time is adjusted to f
frequency:
HCLK
–
–
0 wait state and Prefetch OFF from 0 to 24 MHz
1 wait state and Prefetch ON above 24 MHz
= f
•
•
•
When the peripherals are enabled, f
PCLK
HCLK
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
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Table 33. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal
Typical consumption in
Run mode
Typical consumption in
Sleep mode
Symbol Parameter
fHCLK
Unit
Peripherals Peripherals Peripherals Peripherals
enabled
disabled
enabled
disabled
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
26.7
20.4
18.5
14.6
10.2
5.1
15.1
11.8
11.0
8.7
16.4
12.7
11.4
9.0
3.8
3.3
3.0
2.3
1.8
1.2
1.1
1.1
1.1
1.0
Current
consumption
from VDD
supply
6.1
6.4
IDD
mA
3.3
3.2
4 MHz
3.3
2.2
2.3
2 MHz
2.2
1.7
1.7
1 MHz
1.6
1.4
1.4
500 kHz
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
1.4
1.2
1.2
172
131
119
93
Current
consumption
from VDDA
supply
67
IDDA
μA
2.7
2.7
2.7
2.7
2.7
4 MHz
2 MHz
1 MHz
500 kHz
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 53: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
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trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 35: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
ISW = VDDIOx × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the I/O supply voltage
DDIOx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C
+ C
+ C
EXT S
INT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
Symbol
STM32F091xB STM32F091xC
Table 34. Switching output I/O current consumption
I/O toggling
frequency (fSW
Parameter
Conditions(1)
Typ
Unit
)
4 MHz
0.07
8 MHz
16 MHz
24 MHz
48 MHz
4 MHz
0.15
0.31
0.53
0.92
0.18
0.37
0.76
1.39
2.188
0.32
0.64
1.25
2.23
4.442
0.49
0.94
2.38
3.99
0.64
1.25
3.24
5.02
0.81
1.7
VDDIOx = 3.3 V
C =CINT
8 MHz
VDDIOx = 3.3 V
CEXT = 0 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
8 MHz
VDDIOx = 3.3 V
CEXT = 10 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
I/O current
consumption
ISW
mA
VDDIOx = 3.3 V
8 MHz
CEXT = 22 pF
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 33 pF
8 MHz
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 47 pF
8 MHz
C = CINT + CEXT+ CS
C = Cint
16 MHz
3.67
4 MHz
8 MHz
0.66
1.43
2.45
4.97
VDDIOx = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
16 MHz
24 MHz
1. CS = 7 pF (estimated value).
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On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 35. The MCU is placed
under the following conditions:
•
•
•
All I/O pins are in analog mode
All peripherals are disabled unless otherwise mentioned
The given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
•
Ambient operating temperature and supply voltage conditions summarized in Table 21:
Voltage characteristics
Table 35. Peripheral current consumption
Peripheral
BusMatrix(1)
Typical consumption at 25 °C
Unit
3.1
2.0
5.5
5.1
15.4
5.5
5.4
3.2
3.1
4.0
2.5
0.8
5.5
61.0
CRC
DMA1
DMA2
Flash memory interface
GPIOA
GPIOB
AHB
µA/MHz
GPIOC
GPIOD
GPIOE
GPIOF
SRAM
TSC
All AHB peripherals
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Table 35. Peripheral current consumption (continued)
Peripheral
Typical consumption at 25 °C
Unit
APB-Bridge(2)
ADC(3)
3.6
4.3
CAN
12.4
0.4
CEC
CRS
0.0
DAC(3)
4.2
DBG (MCU Debug Support)
I2C1
0.2
2.9
I2C2
2.4
PWR
0.6
SPI1
8.8
SPI2
7.8
SYSCFG and COMP
TIM1
1.9
15.2
2.6
TIM14
TIM15
8.7
APB
µA/MHz
TIM16
5.8
TIM17
7.0
TIM2
16.2
11.9
11.8
2.5
TIM3
TIM6
TIM7
USART1
USART2
USART3
USART4
USART5
USART6
USART7
USART8
WWDG
All APB peripherals
17.6
16.3
16.2
4.7
4.4
5.5
5.2
5.1
1.1
207.2
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.
3. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, comparators, is not
included. Refer to the tables of characteristics in the subsequent sections.
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6.3.6
Wakeup time from low-power mode
The wakeup times given in Table 36 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 24: General operating conditions.
Table 36. Low-power mode wakeup timings
Typ @VDD = VDDA
Symbol
Parameter
Conditions
Max Unit
= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V
Regulator in run
mode
3.2
7.0
3.1
5.8
2.9
5.2
2.9
4.9
52
2.8
4.6
51
5
Wakeup from Stop
mode
tWUSTOP
Regulator in low
power mode
9
µs
Wakeup from
Standby mode
tWUSTANDBY
-
-
60.4
55.6
53.5
-
Wakeup from Sleep
mode
tWUSLEEP
4 SYSCLK cycles
-
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 15: High-speed external clock
source AC timing diagram.
Table 37. High-speed external user clock characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
fHSE_ext User external clock source frequency
VHSEH OSC_IN input pin high level voltage
-
8
-
32
MHz
0.7 VDDIOx
VSS
VDDIOx
V
VHSEL
OSC_IN input pin low level voltage
OSC_IN high or low time
-
0.3 VDDIOx
tw(HSEH)
tw(HSEL)
15
-
-
-
-
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
20
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Electrical characteristics
STM32F091xB STM32F091xC
1. Guaranteed by design, not tested in production.
Figure 15. High-speed external clock source AC timing diagram
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Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 16.
Table 38. Low-speed external user clock characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
32.768
1000
VDDIOx
kHz
0.7 VDDIOx
VSS
-
-
V
0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
450
-
-
-
-
ns
tr(LSE)
OSC32_IN rise or fall time
tf(LSE)
50
1. Guaranteed by design, not tested in production.
Figure 16. Low-speed external clock source AC timing diagram
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STM32F091xB STM32F091xC
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 39. HSE oscillator characteristics
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency
-
4
-
8
200
-
32
-
MHz
RF
Feedback resistor
-
kΩ
During startup(3)
-
8.5
VDD = 3.3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
-
-
-
-
0.4
0.5
0.8
1
-
-
-
-
-
VDD = 3.3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
VDD = 3.3 V,
IDD
HSE current consumption
mA
Rm = 30 Ω,
CL = 5 pF@32 MHz
VDD = 3.3 V,
Rm = 30 Ω,
CL = 10 pF@32 MHz
VDD = 3.3 V,
Rm = 30 Ω,
1.5
CL = 20 pF@32 MHz
gm
Oscillator transconductance
Startup time
Startup
10
-
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
STM32F091xB STM32F091xC
Figure 17. Typical application with an 8 MHz crystal
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Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 40. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
low drive capability
medium-low drive capability
medium-high drive capability
high drive capability
-
-
0.5
0.9
-
-
1
IDD
LSE current consumption
µA
-
1.3
-
-
1.6
low drive capability
5
8
15
25
-
-
-
-
-
-
-
medium-low drive capability
medium-high drive capability
high drive capability
-
Oscillator
transconductance
gm
µA/V
s
-
-
(3)
tSU(LSE)
Startup time
VDDIOx is stabilized
2
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
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STM32F091xB STM32F091xC
Electrical characteristics
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 18. Typical application with a 32.768 kHz crystal
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Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8
Internal clock source characteristics
The parameters given in Table 41 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions. The provided curves are characterization results, not tested in production.
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Electrical characteristics
STM32F091xB STM32F091xC
High-speed internal (HSI) RC oscillator
(1)
Table 41. HSI oscillator characteristics
Symbol
Parameter
Frequency
HSI user trimming step
Conditions
Min
Typ
Max
Unit
fHSI
-
-
-
8
-
-
-
-
-
-
-
-
-
-
MHz
%
TRIM
-
1(2)
55(2)
3.8(3)
2.3(3)
2(3)
2(3)
2(3)
1
DuCy(HSI) Duty cycle
-
45(2)
-2.8(3)
-1.9(3)
-1.9(3)
-1.3(3)
-1(3)
-1
%
TA = -40 to 105°C
TA = -10 to 85°C
TA = 0 to 85°C
TA = 0 to 70°C
TA = 0 to 55°C
TA = 25°C(4)
-
Accuracy of the HSI
oscillator
ACCHSI
%
tsu(HSI)
HSI oscillator startup time
1(2)
2(2)
µs
HSI oscillator power
consumption
IDDA(HSI)
-
-
80
100(2)
µA
1. VDDA = 3.3 V, TA = -40 to 105°C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
4. Factory calibrated, parts not soldered.
Figure 19. HSI oscillator accuracy characterization results for soldered parts
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STM32F091xB STM32F091xC
Electrical characteristics
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
(1)
Table 42. HSI14 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fHSI14
TRIM
Frequency
-
-
-
-
-
14
-
-
MHz
%
HSI14 user-trimming step
1(2)
DuCy(HSI14) Duty cycle
45(2)
-
55(2)
5.1(3)
3.1(3)
2.3(3)
1
%
TA = –40 to 105 °C –4.2(3)
TA = –10 to 85 °C –3.2(3)
-
%
-
%
Accuracy of the HSI14
oscillator (factory calibrated)
ACCHSI14
TA = 0 to 70 °C
–2.5(3)
-
%
TA = 25 °C
-
–1
-
%
tsu(HSI14) HSI14 oscillator startup time
1(2)
-
2(2)
µs
HSI14 oscillator power
IDDA(HSI14)
-
-
100 150(2)
µA
consumption
1.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Figure 20. HSI14 oscillator accuracy characterization results
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Electrical characteristics
STM32F091xB STM32F091xC
High-speed internal 48 MHz (HSI48) RC oscillator
(1)
Table 43. HSI48 oscillator characteristics
Symbol
Parameter
Frequency
HSI48 user-trimming step
Conditions
Min
Typ
Max
Unit
fHSI48
TRIM
-
-
-
-
48
-
MHz
%
0.09(2)
45(2)
0.14
0.2(2)
55(2)
4.7(3)
3.7(3)
3.4(3)
2.9
DuCy(HSI48) Duty cycle
-
-
-
-
-
-
%
TA = –40 to 105 °C -4.9(3)
%
TA = –10 to 85 °C
TA = 0 to 70 °C
TA = 25 °C
-
-4.1(3)
-3.8(3)
-2.8
-
%
Accuracy of the HSI48
oscillator (factory calibrated)
ACCHSI48
%
%
tsu(HSI48) HSI48 oscillator startup time
6(2)
µs
HSI48 oscillator power
IDDA(HSI48)
-
-
312
350(2)
µA
consumption
1.
VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 21. HSI48 oscillator accuracy characterization results
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Electrical characteristics
Low-speed internal (LSI) RC oscillator
(1)
Table 44. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI
Frequency
30
-
40
-
50
85
kHz
µs
(2)
tsu(LSI)
LSI oscillator startup time
LSI oscillator power consumption
(2)
IDDA(LSI)
-
0.75
1.2
µA
1.
VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 45 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24: General operating
conditions.
Table 45. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max
PLL input clock(1)
1(2)
40(2)
16(2)
-
8.0
24(2)
60(2)
48
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
-
-
-
-
fPLL_OUT
tLOCK
MHz
µs
200(2)
300(2)
JitterPLL
Cycle-to-cycle jitter
-
ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT
.
2. Guaranteed by design, not tested in production.
6.3.10
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
Table 46. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
16-bit programming time TA = - 40 to +105 °C
40
20
20
-
53.5
60
40
40
10
12
µs
ms
ms
mA
mA
tERASE Page (2 KB) erase time TA = - 40 to +105 °C
-
-
-
-
tME
Mass erase time
TA = - 40 to +105 °C
Write mode
IDD
Supply current
Erase mode
-
1. Guaranteed by design, not tested in production.
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Electrical characteristics
Symbol
STM32F091xB STM32F091xC
Table 47. Flash memory endurance and data retention
Parameter
Conditions
Min(1)
Unit
NEND
Endurance
TA = –40 to +105 °C
kcycle
10
30
10
20
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
10 kcycle(2) at TA = 55 °C
tRET
Data retention
Year
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709.
Table 48. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 48 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
2B
4B
Fast transient voltage burst limits to be
VDD = 3.3 V, LQFP100, TA = +25°C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 48 MHz,
pins to induce a functional disturbance
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
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Electrical characteristics
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 49. EMI characteristics
Max vs. [fHSE/fHCLK
8/48 MHz
]
Monitored
frequency band
Symbol Parameter
Conditions
Unit
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
EMI Level
3
23
15
4
VDD = 3.6 V, TA = 25 °C,
LQFP100 package
compliant with
dBµV
-
SEMI
Peak level
IEC 61967-2
6.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
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Electrical characteristics
STM32F091xB STM32F091xC
Maximum
Table 50. ESD absolute maximum ratings
Conditions
Symbol
Ratings
Packages Class
Unit
value(1)
Electrostatic discharge voltage TA = +25 °C, conforming
All
VESD(HBM)
2
2000
V
(human body model)
to JESD22-A114
WLCSP64,
LQFP100
C3
C4
250
500
Electrostatic discharge voltage TA = +25 °C, conforming
VESD(CDM)
V
(charge device model)
to ANSI/ESD STM5.3.1
All others
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 51. Electrical sensitivities
Symbol
Parameter
Conditions
Class
II level A
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
6.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V
(for standard, 3.3 V-capable I/O pins) should be avoided during normal
DDIOx
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 52.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
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Electrical characteristics
Table 52. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
Injected current on BOOT0
-0
-0
-0
NA
NA
+5
Injected current on PF1 pin (FTf pin)
Injected current on PC0 pin (TTA pin)
IINJ
mA
Injected current on PA4, PA5 pins with induced leakage
current on adjacent pins less than -20 μA
-5
NA
Injected current on other FT and FTf pins
-5
-5
NA
+5
Injected current on all other TC, TTa and RST pins
6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under the conditions summarized in Table 24: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 53. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TC and TTa I/O
FT and FTf I/O
All I/Os
-
-
0.3 VDDIOx+0.07(1)
Low level input
voltage
VIL
-
-
0.475 VDDIOx–0.2(1)
V
-
-
0.3 VDDIOx
TC and TTa I/O
FT and FTf I/O
All I/Os
0.445 VDDIOx+0.398(1)
-
-
-
-
-
-
High level input
voltage
VIH
0.5 VDDIOx+0.2(1)
-
V
0.7 VDDIOx
-
TC and TTa I/O
FT and FTf I/O
-
-
200(1)
100(1)
Schmitt trigger
hysteresis
Vhys
mV
TC, FT and FTf I/O
TTa in digital mode
VSS ≤ VIN ≤ VDDIOx
-
-
± 0.1
TTa in digital mode
VDDIOx ≤ VIN ≤ VDDA
-
-
-
-
-
-
1
Input leakage
current(2)
Ilkg
µA
TTa in analog mode
VSS ≤ VIN ≤ VDDA
± 0.2
10
FT and FTf I/O
VDDIOx ≤ VIN ≤ 5 V
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Electrical characteristics
STM32F091xB STM32F091xC
Table 53. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Weak pull-up
RPU
equivalent resistor VIN = VSS
25
40
55
kΩ
(3)
Weak pull-down
RPD
CIO
equivalent
VIN = - VDDIOx
25
-
40
5
55
-
kΩ
resistor(3)
I/O pin capacitance
-
pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 52:
I/O current injection susceptibility.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 for standard I/Os, and in Figure 23 for
5 V-tolerant I/Os. The following curves are design simulation results, not tested in
production.
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Electrical characteristics
Figure 22. TC and TTa I/O input characteristics
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DocID026284 Rev 4
81/128
99
Electrical characteristics
STM32F091xB STM32F091xC
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on V
, plus the maximum
DDIOx
consumption of the MCU sourced on V , cannot exceed the absolute maximum rating
DD
ΣI
(see Table 21: Voltage characteristics).
VDD
•
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating ΣI
(see
SS
VSS
Table 21: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
(1)
Table 54. Output voltage characteristics
Symbol
VOL
Parameter
Conditions
Min
Max Unit
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port(2)
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
-
0.4
V
VOH
VDDIOx–0.4
-
VOL
TTL port(2)
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
-
0.4
V
VOH
2.4
-
(3)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3
V
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
(3)
VOH
VDDIOx–1.3
-
(3)
VOL
-
0.4
V
-
|IIO| = 6 mA
(3)
VDDIOx ≥ 2 V
VOH
VDDIOx–0.4
-
(4)
VOL
0.4
-
V
V
|IIO| = 4 mA
(4)
VOH
VDDIOx–0.4
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
-
-
0.4
0.4
V
V
Output low level voltage for an FTf I/O pin in
Fm+ mode
(3)
VOLFm+
|IIO| = 10 mA
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣI
.
IO
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
4. Data based on characterization results. Not tested in production.
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STM32F091xB STM32F091xC
Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 55, respectively. Unless otherwise specified, the parameters given are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 24: General operating conditions.
(1)(2)
Table 55. I/O AC characteristics
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
ns
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
125
125
1
CL = 50 pF, VDDIOx ≥ 2 V
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
x0
MHz
ns
CL = 50 pF, VDDIOx < 2 V
CL = 50 pF, VDDIOx ≥ 2 V
CL = 50 pF, VDDIOx < 2 V
125
125
10
25
25
4
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
MHz
ns
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
01
MHz
ns
62.5
62.5
50
30
20
10
5
tr(IO)out Output rise time
CL = 30 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V
CL = 50 pF, VDDIOx < 2 V
fmax(IO)out Maximum frequency(3)
MHz
CL = 30 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V
CL = 50 pF, VDDIOx < 2 V
8
11
tf(IO)out Output fall time
12
25
5
ns
CL = 30 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V
CL = 50 pF, VDDIOx < 2 V
8
tr(IO)out Output rise time
12
25
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Electrical characteristics
STM32F091xB STM32F091xC
(1)(2)
Table 55. I/O AC characteristics
Parameter
(continued)
OSPEEDRy
Symbol
Conditions
Min
Max
Unit
MHz
ns
[1:0] value(1)
fmax(IO)out Maximum frequency(3)
-
-
-
-
-
-
2
tf(IO)out Output fall time
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
tr(IO)out Output rise time
CL = 50 pF, VDDIOx ≥ 2 V
12
34
0.5
16
44
Fm+
configuration
(4)
MHz
ns
CL = 50 pF, VDDIOx < 2 V
Pulse width of external
tEXTIpw signals detected by the
EXTI controller
-
-
10
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 24.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091
for a detailed description of Fm+ I/O configuration.
Figure 24. I/O AC characteristics definition
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6.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 24: General operating conditions.
Table 56. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST) NRST input low level voltage
VIH(NRST) NRST input high level voltage
-
-
-
-
-
0.3 VDD+0.07(1)
-
V
0.445 VDD+0.398(1)
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STM32F091xB STM32F091xC
Electrical characteristics
Table 56. NRST pin characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST Schmitt trigger voltage
hysteresis
Vhys(NRST)
-
-
200
-
mV
Weak pull-up equivalent
resistor(2)
RPU
VIN = VSS
25
40
55
kΩ
VF(NRST) NRST input filtered pulse
-
-
-
-
-
100(1)
ns
2.7 < VDD < 3.6
2.0 < VDD < 3.6
300(3)
500(3)
-
-
VNF(NRST) NRST input not filtered pulse
ns
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
3. Data based on design simulation only. Not tested in production.
Figure 25. Recommended NRST pin protection
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1. The external capacitor protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 56: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under the conditions summarized in Table 24: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 57. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage for
ADC ON
VDDA
-
2.4
-
3.6
V
Current consumption of
the ADC(1)
IDDA (ADC)
fADC
VDDA = 3.3 V
-
0.9
-
mA
ADC clock frequency
Sampling rate
-
0.6
-
-
14
1
MHz
MHz
(2)
fS
12-bit resolution
0.043
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99
Electrical characteristics
STM32F091xB STM32F091xC
Table 57. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fADC = 14 MHz,
12-bit resolution
-
-
823
kHz
(2)
External trigger frequency
fTRIG
12-bit resolution
-
-
-
-
17
1/fADC
V
VAIN
Conversion voltage range
External input impedance
0
VDDA
See Equation 1 and
Table 58 for details
(2)
RAIN
-
-
-
-
-
-
50
1
kΩ
kΩ
pF
Sampling switch
resistance
(2)
-
-
RADC
Internal sample and hold
capacitor
(2)
8
CADC
f
ADC = 14 MHz
5.9
83
µs
(2)(3)
Calibration time
tCAL
-
1/fADC
1.5 ADC
cycles + 3
fPCLK cycles
1.5 ADC
cycles + 2
fPCLK cycles
ADC clock = HSI14
-
-
ADC_DR register ready
latency
(2)(4)
WLATENCY
fPCLK
cycle
ADC clock = PCLK/2
ADC clock = PCLK/4
-
-
4.5
8.5
-
-
fPCLK
cycle
fADC = fPCLK/2 = 14 MHz
fADC = fPCLK/2
0.196
5.5
µs
1/fPCLK
µs
(2)
Trigger conversion latency fADC = fPCLK/4 = 12 MHz
fADC = fPCLK/4
0.219
10.5
-
tlatr
1/fPCLK
µs
fADC = fHSI14 = 14 MHz
0.179
-
0.250
-
ADC jitter on trigger
fADC = fHSI14
JitterADC
1
1/fHSI14
conversion
f
ADC = 14 MHz
0.107
1.5
-
-
17.1
µs
(2)
Sampling time
tS
-
-
239.5
1/fADC
1/fADC
(2)
tSTAB
Stabilization time
14
f
ADC = 14 MHz,
1
-
18
µs
12-bit resolution
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
12-bit resolution
1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
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Electrical characteristics
Equation 1: R
max formula
AIN
TS
RAIN < --------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 58. R
max for f
tS (µs)
= 14 MHz
ADC
AIN
Ts (cycles)
RAIN max (kΩ)(1)
1.5
7.5
0.11
0.54
0.96
2.04
2.96
3.96
5.11
17.1
0.4
5.9
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Guaranteed by design, not tested in production.
(1)(2)(3)
Table 59. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±1.3
±1
±2
±1.5
±1.5
±1
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
VDDA = 3 V to 3.6 V
TA = 25 °C
Gain error
±0.5
±0.7
±0.8
±3.3
±1.9
±2.8
±0.7
±1.2
±3.3
±1.9
±2.8
±0.7
±1.2
LSB
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
±1.5
±4
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
±2.8
±3
Gain error
LSB
LSB
VDDA = 2.7 V to 3.6 V
TA = - 40 to 105 °C
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
±1.3
±1.7
±4
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
±2.8
±3
Gain error
VDDA = 2.4 V to 3.6 V
TA = 25 °C
Differential linearity error
Integral linearity error
±1.3
±1.7
1. ADC DC accuracy values are measured after internal calibration.
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99
Electrical characteristics
STM32F091xB STM32F091xC
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
Figure 26. ADC accuracy characteristics
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1. Refer to Table 57: ADC characteristics for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 13: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
88/128
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Electrical characteristics
6.3.17
DAC electrical specifications
Table 60. DAC characteristics
Symbol
VDDA
Parameter
Min
Typ
Max
Unit
Comments
Analog supply voltage for
DAC ON
2.4
-
3.6
V
-
5
-
-
-
-
kꢀ Load connected to VSSA
kꢀ Load connected to VDDA
When the buffer is OFF, the
Resistive load with buffer
ON
(1)
RLOAD
25
Impedance output with
buffer OFF
Minimum resistive load between
DAC_OUT and VSS to have a
(1)
RO
-
-
15
kꢀ
1% accuracy is 1.5 Mꢀ
Maximum capacitive load at
pF DAC_OUT pin (when the buffer
is ON).
(1)
CLOAD
Capacitive load
-
-
-
50
-
It gives the maximum output
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
excursion of the DAC.
0.2
V
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer ON
VDDA = 3.6 V and (0x155) and
(0xEAB) at VDDA = 2.4 V
-
-
-
-
-
-
VDDA – 0.2
V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
0.5
-
VDDA – 1LSB
600
mV
It gives the maximum output
excursion of the DAC.
V
DAC_OUT Higher DAC_OUT voltage
-
-
-
max(1)
with buffer OFF
With no load, middle code
(0x800) on the input
µA
DAC DC current
consumption in quiescent
mode(2)
(1)
IDDA
With no load, worst code
µA
700
(0xF1C) on the input
Given for the DAC in 10-bit
configuration
-
-
±0.5
LSB
Differential non linearity
Difference between two
consecutive code-1LSB)
DNL(3)
Given for the DAC in 12-bit
configuration
-
-
-
-
±2
±1
LSB
Integral non linearity
(difference between
Given for the DAC in 10-bit
configuration
LSB
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
INL(3)
Given for the DAC in 12-bit
configuration
-
-
±4
LSB
-
-
-
-
±10
±3
mV
-
Offset error
Given for the DAC in 10-bit at
(difference between
measured value at Code
(0x800) and the ideal value
= VDDA/2)
LSB
Offset(3)
VDDA = 3.6 V
Given for the DAC in 12-bit at
VDDA = 3.6 V
-
-
±12
LSB
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STM32F091xB STM32F091xC
Comments
Table 60. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Given for the DAC in 12-bit
configuration
Gain error(3) Gain error
-
-
±0.5
%
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
(3)
tSETTLING
-
-
3
-
4
1
µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kꢀ
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Update
rate(3)
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kꢀ
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
CLOAD ≤ 50 pF, RLOAD ≥ 5 kꢀ
µs input code between lowest and
highest possible ones.
(3)
tWAKEUP
-
-
6.5
10
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
–67
–40
dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved.
3. Data based on characterization results, not tested in production.
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Electrical characteristics
6.3.18
Comparator characteristics
Table 61. Comparator characteristics
Conditions
Symbol
VDDA
Parameter
Min(1) Typ Max(1) Unit
Analog supply voltage
-
-
VDD
0
-
-
3.6
V
-
Comparator input
voltage range
VIN
VDDA
VREFINT scaler offset
voltage
VSC
tS_SC
tSTART
-
-
-
-
-
±5
-
±10
0.2
60
mV
ms
µs
VREFINT scaler startup
time from power down
Comparator startup
time
Startup time to reach propagation delay
specification
-
Ultra-low power mode
Low power mode
-
-
-
-
-
-
-
-
-
-
-
2
4.5
1.5
0.6
100
240
7
0.7
0.3
50
µs
ns
µs
ns
Propagation delay for
200 mV step with
100 mV overdrive
Medium power mode
V
DDA ≥ 2.7 V
High speed mode
VDDA < 2.7 V
100
2
tD
Ultra-low power mode
Low power mode
0.7
0.3
90
2.1
1.2
180
300
±10
Propagation delay for
full range step with
100 mV overdrive
Medium power mode
VDDA ≥ 2.7 V
High speed mode
VDDA < 2.7 V
110
±4
Voffset
Comparator offset error
-
mV
Offset error
temperature coefficient
dVoffset/dT
-
-
18
-
µV/°C
Ultra-low power mode
-
-
-
-
1.2
3
1.5
5
Low power mode
Medium power mode
High speed mode
COMP current
consumption
IDD(COMP)
µA
10
75
15
100
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Electrical characteristics
STM32F091xB STM32F091xC
Table 61. Comparator characteristics (continued)
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
No hysteresis
(COMPxHYST[1:0]=00)
-
-
3
0
8
-
High speed mode
13
10
26
19
49
40
Low hysteresis
(COMPxHYST[1:0]=01)
All other power
modes
5
Vhys
Comparator hysteresis
High speed mode
7
mV
Medium hysteresis
(COMPxHYST[1:0]=10)
15
31
All other power
modes
9
High speed mode
18
19
High hysteresis
(COMPxHYST[1:0]=11)
All other power
modes
1. Data based on characterization results, not tested in production.
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Electrical characteristics
6.3.19
Temperature sensor characteristics
Table 62. TS characteristics
Symbol
Parameter
VSENSE linearity with temperature
Avg_Slope(1) Average slope
Min
Typ
Max
Unit
(1)
TL
-
4.0
1.34
-
± 1
4.3
1.43
-
± 2
4.6
°C
mV/°C
V
V30
Voltage at 30 °C (± 5 °C)(2)
1.52
10
(1)
(1)
tSTART
ADC_IN16 buffer startup time
µs
ADC sampling time when reading the
temperature
tS_temp
4
-
-
µs
1. Guaranteed by design, not tested in production.
2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:
Temperature sensor calibration values.
6.3.20
V
monitoring characteristics
BAT
Table 63. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
2 x 50
-
-
kꢀ
-
Ratio on VBAT measurement
Error on Q
2
-
Er(1)
–1
4
+1
-
%
µs
(1)
tS_vbat
ADC sampling time when reading the VBAT
-
1. Guaranteed by design, not tested in production.
6.3.21
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 64. TIMx characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tTIMxCLK
ns
-
-
-
-
1
-
-
-
tres(TIM)
Timer resolution time
fTIMxCLK = 48 MHz
-
20.8
Timer external clock
frequency on CH1 to
CH4
fTIMxCLK/2
MHz
fEXT
fTIMxCLK = 48 MHz
-
24
-
MHz
216
tTIMxCLK
-
-
-
-
-
-
-
-
-
16-bit timer maximum
period
fTIMxCLK = 48 MHz
-
1365
µs
tMAX_COUNT
232
tTIMxCLK
32-bit counter
maximum period
fTIMxCLK = 48 MHz
89.48
s
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Electrical characteristics
STM32F091xB STM32F091xC
(1)
Table 65. IWDG min/max timeout period at 40 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
/8
0
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
1
/16
/32
/64
/128
/256
2
1638.4
3276.8
6553.6
13107.2
26214.4
3
4
ms
5
6 or 7
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 66. WWDG min/max timeout value at 48 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0853
0.1706
0.3413
0.6826
5.4613
10.9226
21.8453
43.6906
ms
6.3.22
Communication interfaces
I2C interface characteristics
2
2
The I C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
The I C timings requirements are guaranteed by design when the I2Cx peripheral is
properly configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
is disabled, but is still present. Only FTf I/O pins
DDIOx
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
2
port characteristics for the I C I/Os characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
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Symbol
Electrical characteristics
2
(1)
Table 67. I C analog filter characteristics
Parameter
Min
Max
Unit
Maximum width of spikes that are
suppressed by the analog filter
tAF
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI/I2S characteristics
2
Unless otherwise specified, the parameters given in Table 68 for SPI or in Table 69 for I S
are derived from tests performed under the ambient temperature, f frequency and
PCLKx
supply voltage conditions summarized in Table 24: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
(1)
Table 68. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
-
-
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
-
6
ns
ns
%
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
4Tpclk
-
-
2Tpclk + 10
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
Tpclk/2 -2
Tpclk/2 + 1
tw(SCKL)
Master mode
Slave mode
Master mode
Slave mode
4
5
-
tsu(MI)
tsu(SI)
-
th(MI)
th(SI)
4
-
Data input hold time
5
-
(2)
ta(SO)
Data output access time Slave mode, fPCLK = 20 MHz
Data output disable time Slave mode
0
3Tpclk
(3)
tdis(SO)
0
18
tv(SO)
tv(MO)
th(SO)
th(MO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
22.5
-
6
-
11.5
2
Data output hold time
-
SPI slave input clock
duty cycle
DuCy(SCK)
Slave mode
25
75
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
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Electrical characteristics
STM32F091xB STM32F091xC
Figure 28. SPI timing diagram - slave mode and CPHA = 0
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Figure 29. SPI timing diagram - slave mode and CPHA = 1
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
96/128
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Electrical characteristics
Figure 30. SPI timing diagram - master mode
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
2
(1)
Table 69. I S characteristics
Conditions
Symbol
Parameter
Min
Max
Unit
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
1.597
1.601
fCK
1/tc(CK)
I2S clock frequency
MHz
Slave mode
0
-
6.5
tr(CK)
tf(CK)
I2S clock rise time
I2S clock fall time
I2S clock high time
I2S clock low time
WS valid time
10
12
-
Capacitive load CL = 15 pF
-
tw(CKH)
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
306
312
2
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
-
ns
%
Master mode
Master mode
Slave mode
Slave mode
-
WS hold time
2
-
WS setup time
7
-
WS hold time
0
-
I2S slave input clock duty
cycle
DuCy(SCK)
Slave mode
25
75
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Electrical characteristics
STM32F091xB STM32F091xC
2
(1)
Table 69. I S characteristics (continued)
Conditions
Symbol
Parameter
Data input setup time
Min
Max
Unit
tsu(SD_MR)
tsu(SD_SR)
Master receiver
6
2
-
-
Slave receiver
(2)
th(SD_MR)
Master receiver
Slave receiver
4
-
Data input hold time
Data output valid time
Data output hold time
(2)
th(SD_SR)
0.5
-
-
ns
(2)
tv(SD_MT)
Master transmitter
Slave transmitter
Master transmitter
Slave transmitter
4
20
-
(2)
tv(SD_ST)
th(SD_MT)
th(SD_ST)
-
0
13
-
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns.
2
Figure 31. I S slave timing diagram (Philips protocol)
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1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
2
Figure 32. I S master timing diagram (Philips protocol)
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1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
DocID026284 Rev 4
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99
Package information
STM32F091xB STM32F091xC
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
7.1
UFBGA100 package information
UFBGA100 is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra-fine-profile ball grid array
package.
Figure 33. UFBGA100 package outline
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1. Drawing is not to scale.
Table 70. UFBGA100 package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
-
-
-
-
-
-
0.600
-
-
-
-
-
-
0.0236
A1
A2
A3
A4
-
0.110
-
0.0043
0.450
0.130
0.320
-
-
-
0.0177
0.0051
0.0126
-
0.0094
-
100/128
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Package information
Table 70. UFBGA100 package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
b
D
0.240
0.290
7.000
5.500
7.000
5.500
0.500
0.750
-
0.340
0.0094
0.0114
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
-
0.0134
6.850
7.150
0.2697
0.2815
D1
E
-
-
7.150
-
-
-
6.850
0.2697
0.2815
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Z
-
-
ddd
eee
fff
0.080
0.150
0.050
0.0031
0.0059
0.0020
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 34. Recommended footprint for UFBGA100 package
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Table 71. UFBGA100 recommended PCB design rules
Dimension
Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the solder mask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.280 mm
Between 0.100 mm and 0.125 mm
DocID026284 Rev 4
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124
Package information
STM32F091xB STM32F091xC
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 35. UFBGA100 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
102/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Package information
7.2
LQFP100 package information
LQFP100 is a100-pin, 14 x 14 mm low-profile quad flat package.
Figure 36. LQFP100 package outline
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1. Drawing is not to scale.
Table 72. LQPF100 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
0.6299
0.5512
0.4724
0.6299
D1
D3
E
15.800
16.200
0.6220
0.6378
DocID026284 Rev 4
103/128
124
Package information
STM32F091xB STM32F091xC
Table 72. LQPF100 package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E1
E3
e
13.800
14.000
12.000
0.500
0.600
1.000
3.5°
14.200
0.5433
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.5591
-
-
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
-
0.0°
-
7.0°
0.080
7.0°
0.0031
ccc
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 37. Recommended footprint for LQFP100 package
ꢄꢃ
ꢃꢊ
ꢄꢌ
ꢃꢋ
ꢋꢈꢃ
ꢋꢈꢀ
ꢊꢌꢈꢄ ꢊꢁꢈꢀ
ꢊꢋꢋ
ꢅꢌ
ꢊꢈꢅ
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ꢅꢃ
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ꢊꢌꢈꢄ
DLꢊꢁꢂꢋꢌF
1. Dimensions are expressed in millimeters.
104/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 38. LQFP100 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID026284 Rev 4
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124
Package information
STM32F091xB STM32F091xC
7.3
UFBGA64 package information
UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-fine-profile ball grid array
package.
Figure 39. UFBGA64 package outline
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1. Drawing is not to scale.
Table 73. UFBGA64 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
A4
b
0.460
0.050
0.400
0.080
0.270
0.170
4.850
3.450
4.850
3.450
-
0.530
0.080
0.450
0.130
0.320
0.280
5.000
3.500
5.000
3.500
0.500
0.750
0.600
0.110
0.500
0.180
0.370
0.330
5.150
3.550
5.150
3.550
-
0.0181
0.0020
0.0157
0.0031
0.0106
0.0067
0.1909
0.1358
0.1909
0.1358
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.1969
0.1378
0.1969
0.1378
0.0197
0.0295
0.0236
0.0043
0.0197
0.0071
0.0146
0.0130
0.2028
0.1398
0.2028
0.1398
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
106/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Package information
Table 73. UFBGA64 package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
0.460
0.530
0.600
0.080
0.150
0.050
0.0181
0.0209
0.0236
0.0031
0.0059
0.0020
ddd
eee
fff
-
-
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 40. Recommended footprint for UFBGA64 package
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Table 74. UFBGA64 recommended PCB design rules
Dimension
Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.280 mm
Between 0.100 mm and 0.125 mm
0.100 mm
DocID026284 Rev 4
107/128
124
Package information
STM32F091xB STM32F091xC
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 41. UFBGA64 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
108/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Package information
7.4
WLCSP64 package information
WLCSP64 is a 64-ball, 3.347 x 3.585 mm, 0.4 mm pitch wafer-level chip-scale package.
Figure 42. WLCSP64 package outline
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$ꢋꢅꢁB0(B9ꢊ
1. Drawing is not to scale.
Table 75. WLCSP64 package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.525
0.555
0.175
0.380
0.025
0.585
0.0207
0.0219
0.0069
0.0150
0.0010
0.0230
A1
A2
A3
-
-
-
-
-
-
-
-
-
-
-
-
DocID026284 Rev 4
109/128
124
Package information
Symbol
STM32F091xB STM32F091xC
Table 75. WLCSP64 package mechanical data (continued)
millimeters
inches(1)
Min
Typ
0.250
3.347
3.585
0.400
2.800
2.800
0.2735
0.3925
-
Max
0.280
3.382
3.620
-
Min
Typ
0.0098
0.1318
0.1411
0.0157
0.1102
0.1102
0.0108
0.0155
-
Max
0.0110
0.1331
0.1425
-
b(2)
D
0.220
0.0087
3.312
0.1304
E
3.550
0.1398
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
F
-
-
-
-
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.100
0.100
0.100
0.050
0.050
0.0039
0.0039
0.0039
0.0020
0.0020
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 43. Recommended footprint for WLCSP64 package
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Table 76. WLCSP64 recommended PCB design rules
Dimension
Recommended values
0.4
Pitch
260 µm max. (circular)
220 µm recommended
300 µm min. (for 260 µm diameter pad)
Dpad
Dsm
PCB pad design
Non-solder mask defined via underbump allowed.
110/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Device marking
Package information
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 44. WLCSP64 package marking example
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ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ
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ꢁĂƚĞꢀĐŽĚĞ
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5
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID026284 Rev 4
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124
Package information
STM32F091xB STM32F091xC
7.5
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 45. LQFP64 package outline
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ꢋꢈꢅꢃꢆPP
*$8*(ꢆ3/$1(
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&
'
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ꢀꢀ
ꢁꢍ
ꢀꢅ
ꢁꢂ
ꢌꢁ
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ꢊꢌ
ꢊ
3,1ꢆꢊ
H
,'(17,),&$7,21
ꢃ:B0(B9ꢀ
1. Drawing is not to scale.
Table 77. LQFP64 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
-
-
-
-
12.000
10.000
7.500
12.000
10.000
-
-
-
-
-
-
-
-
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
-
-
-
-
-
D1
D3
E
E1
112/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Package information
Table 77. LQFP64 package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E3
e
-
7.500
0.500
3.5°
-
-
0.2953
0.0197
3.5°
-
-
-
7°
-
-
7°
K
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 46. Recommended footprint for LQFP64 package
ꢁꢍ
ꢀꢀ
ꢋꢈꢀ
ꢋꢈꢃ
ꢁꢂ
ꢀꢅ
ꢊꢅꢈꢄ
ꢊꢋꢈꢀ
ꢊꢋꢈꢀ
ꢄꢈꢍ
ꢊꢄ
ꢌꢁ
ꢊꢈꢅ
ꢊꢌ
ꢊ
ꢊꢅꢈꢄ
DLꢊꢁꢂꢋꢂF
1. Dimensions are expressed in millimeters.
DocID026284 Rev 4
113/128
124
Package information
STM32F091xB STM32F091xC
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 47. LQFP64 package marking example
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WƌŽĚƵĐƚꢀŝĚĞŶƚŝĨŝĐĂƚŝŽŶ
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D^ϯϱϱϱϲsϭ
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
114/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Package information
7.6
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Figure 48. LQFP48 package outline
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3/$1(
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3,1ꢆꢊ
,'(17,),&$7,21
ꢊ
ꢊꢅ
H
ꢃ%B0(B9ꢅ
1. Drawing is not to scale.
DocID026284 Rev 4
115/128
124
Package information
STM32F091xB STM32F091xC
Table 78. LQFP48 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 49. Recommended footprint for LQFP48 package
ꢋꢈꢃꢋ
ꢊꢈꢅꢋ
ꢋꢈꢀꢋ
ꢀꢌ
ꢅꢃ
ꢀꢄ
ꢅꢁ
ꢋꢈꢅꢋ
ꢄꢈꢀꢋ
ꢂꢈꢄꢋ ꢃꢈꢍꢋ
ꢄꢈꢀꢋ
ꢁꢍ
ꢊꢀ
ꢊꢅ
ꢊ
ꢊꢈꢅꢋ
ꢃꢈꢍꢋ
ꢂꢈꢄꢋ
DLꢊꢁꢂꢊꢊG
1. Dimensions are expressed in millimeters.
116/128
DocID026284 Rev 4
STM32F091xB STM32F091xC
Device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 50. LQFP48 package marking example
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WƌŽĚƵĐƚꢀŝĚĞŶƚŝĨŝĐĂƚŝŽŶ
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WŝŶꢀϭꢀŝĚĞŶƚŝĨŝĞƌ
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ZĞǀŝƐŝŽŶꢀĐŽĚĞ
5
D^ϯϱϱϱϳsϭ
1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID026284 Rev 4
117/128
124
Package information
STM32F091xB STM32F091xC
7.7
UFQFPN48 package information
UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 51. UFQFPN48 package outline
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SLQꢊꢆFRUQHU
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1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
118/128
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STM32F091xB STM32F091xC
Package information
Table 79. UFQFPN48 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 52. Recommended footprint for UFQFPN48 package
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1. Dimensions are expressed in millimeters.
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124
Package information
STM32F091xB STM32F091xC
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 53. UFQFPN48 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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STM32F091xB STM32F091xC
Package information
7.8
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 24: General operating conditions.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ ((V
– V ) × I ),
DDIOx OH OH
I/O
OL
OL
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 80. Package thermal characteristics
Parameter
Symbol
Value
Unit
Thermal resistance junction-ambient
UFBGA100 - 7 × 7 mm
55
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm
42
65
44
53
54
32
Thermal resistance junction-ambient
UFBGA64 - 5 × 5 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
Θ
°C/W
JA
Thermal resistance junction-ambient
WLCSP64 - 0.4 mm pitch
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
Thermal resistance junction-ambient
UFQFPN48 - 7 × 7 mm
7.8.1
7.8.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
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124
Package information
STM32F091xB STM32F091xC
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F091xB/xC at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum temperature T
= 82 °C (measured according to JESD51-2), I
= 50
Amax
DDmax
mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low level with I
DD
OL
= 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output at low level
OL
with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Using the values obtained in Table 80 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Ordering information).
Note:
With this given P
we can find the T
allowed for a given device temperature range
Dmax
Amax
(order code suffix 6 or 7).
Suffix 6: T
Suffix 7: T
= T
= T
- (45°C/W × 447 mW) = 105-20.115 = 84.885 °C
- (45°C/W × 447 mW) = 125-20.115 = 104.885 °C
Amax
Amax
Jmax
Jmax
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high temperatures
with a low dissipation, as long as junction temperature T remains within the specified
J
range.
Assuming the following application conditions:
Maximum temperature T
= 100 °C (measured according to JESD51-2), I
=
Amax
DDmax
20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low level with
DD
I
= 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V= 70 mW
INTmax
= 20 × 8 mA × 0.4 V = 64 mW
IOmax
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
= 70 + 64 = 134 mW
Dmax
Thus: P
= 134 mW
Dmax
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DocID026284 Rev 4
STM32F091xB STM32F091xC
Package information
Using the values obtained in Table 80 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C
Jmax
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
Refer to the figure below to select the required temperature range (suffix 6 or 7) according to
your temperature or power requirements.
Figure 54. LQFP64 P max versus T
D
A
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DocID026284 Rev 4
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124
Ordering information
STM32F091xB STM32F091xC
8
Ordering information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 81. Ordering information scheme
Example:
STM32
F
091
R
C
T
6
x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
091= STM32F091xx
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
User code memory size
B = 128 Kbyte
C = 256 Kbyte
Package
H = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = –40 to 85 °C
7 = –40 to 105 °C
Options
xxx = code ID of programmed parts (includes packing type)
TR = tape and reel packing
blank = tray packing
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STM32F091xB STM32F091xC
Revision history
9
Revision history
Table 82. Document revision history
Date
Revision
Changes
30-Oct-2014
1
Initial release.
Updated:
– Table: HSI oscillator characteristics,
– Figure : HSI oscillator accuracy characterization
results for soldered parts,
– Figure: WLCSP64 wafer level chip size package
mechanical drawing,
09-Feb-2015
2
– Table: WLCSP64 - 64-pin, 3.347 x 3.585 mm, 0.4 mm
pitch wafer level chip scale package mechanical data,.
Added:
– Figure: WLCSP64 - 64-pin, 3.347 x 3.585 mm,
0.4 mm pitch wafer level chip scale recommended
footprint.
Section 2: Description:
– Table 2: STM32F091xB/xC family device features and
peripheral counts- I/O and capacitive channel
numbers corrected
Section 3: Functional overview:
– updated Figure 1: Block diagram (number of AF) and
Figure 2: Clock tree
– Section 3.5.4: Low-power modes - added info. on
comm. peripherals configurable to operate with HSI
– Section 3.13: Touch sensing controller (TSC) -
number of channels corrected
– added number of complementary outputs for the
general purpose and for the advance control timers in
Table 7: Timer feature comparison
– Table 9: STM32F091xB/xC I2C implementation -
17-Dec-2015
3
added 20mA value to Fast Mode Plus output drive
Section 4: Pinouts and pin descriptions:
– Package pinout figures updated (look and feel)
– Figure 7: WLCSP64 package pinout - now presented
in top view
– Table 13: STM32F091xB/xC pin definitions - MCO
moved from additional to alternate functions column
– Table 19: Alternate functions selected through
GPIOF_AFR registers for port F- lines PF4 and PF5
removed
– Section 5: Memory mapping:
– added information on STM32F091xB difference
versus STM32F091xC map in Figure 10
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127
Revision history
STM32F091xB STM32F091xC
Table 82. Document revision history (continued)
Date
Revision
Changes
Section 6: Electrical characteristics:
– footnote for VIN max value in Table 21: Voltage
characteristics
– Table 28: Embedded internal reference voltage:
added tSTART parameter and removal of -40°-to-85°
condition for VREFINT and associated note
– Figure 18: Typical application with a 32.768 kHz
crystal - correction of OSC_IN and OSC_OUT to
OSC32_IN and OSC32_OUT and fHSE to fLSE
– Table 50: ESD absolute maximum ratings updated
– VDDIOx replaced VDD in Figure 22: TC and TTa I/O
input characteristics and Figure 23: Five volt tolerant
(FT and FTf) I/O input characteristics
– Table 53: I/O static characteristics- note removed
– Table 57: ADC characteristics - updated some
parameter values, test conditions and added
footnotes (3) and (4)
– IDDA max value (DAC DC current consumption) in
Table 60: DAC characteristics
– Table 61: Comparator characteristics - min value
added for VDDA
– Table 62: TS characteristics: removed the minimum
value for tSTART symbol and updated parameter name
3
– R parameter typical. value in Table 63: VBAT
monitoring characteristics
17-Dec-2015
(continued)
– Table 64: TIMx characteristics: removed ResTM
parameter line and all values put in new Typ column,
tCOUNTER substituted with tMAX_COUNT, values defined
as powers of two
– Table 69: I2S characteristics reorganized and max
value added for tv(SD_ST)
– Figure 32: I2S master timing diagram (Philips protocol)
added definition of edge level references
Section 7: Package information:
– Figure 33: UFBGA100 package outline and
associated Table 70 updated
– Figure 34 and associated Table 71 updated
– Figure 35: UFBGA100 package marking example and
associated text updated
– Figure 38: LQFP100 package marking example and
associated text updated
– Table 74: UFBGA64 recommended PCB design rules
added
– Figure 41: UFBGA64 package marking example
added
Section 8: Part numbering:
– added tray packing to options
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STM32F091xB STM32F091xC
Date
Revision history
Table 82. Document revision history (continued)
Revision
Changes
Section 6: Electrical characteristics:
– Table 40: LSE oscillator characteristics (fLSE = 32.768
kHz) - information on configuring different drive
capabilities removed. See the corresponding
reference manual.
– Table 28: Embedded internal reference voltage -
VREFINT values
10-Jan-2017
4
– Table 60: DAC characteristics - min. RLOAD to VDDA
defined
– Figure 28: SPI timing diagram - slave mode and
CPHA = 0 and Figure 29: SPI timing diagram - slave
mode and CPHA = 1 enhanced and corrected
Section 8: Ordering information:
– The name of the section changed from the previous
“Part numbering”
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127
STM32F091xB STM32F091xC
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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