STM32F100R4_技术文档

STM32F100x4 STM32F100x6

STM32F100x8 STM32F100xB

Low & medium-density value line, advanced ARM-based 32-bit MCU

with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

Preliminary data

Features

FBGA

■ Core: ARM 32-bit Cortex™-M3 CPU

– 24 MHz maximum frequency,

LQFP100 14 × 14 mm

LQFP64 10 × 10 mm

LQFP48 7 × 7 mm

1.25 DMIPS/MHz (Dhrystone 2.1)

performance

TFBGA64 (5 × 5 mm)

– Single-cycle multiplication and hardware

division

■ Up to 12 timers

– Up to three 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 16-bit, 6-channel advanced-control timer:

up to 6 channels for PWM output, dead

time generation and emergency stop

■ Memories

– 16 to 128 Kbytes of Flash memory

– 4 to 8 Kbytes of SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage

detector (PVD)

– One 16-bit timer, with 2 IC/OC, 1

OCN/PWM, dead-time generation and

emergency stop

– 4-to-24 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– Two 16-bit timers, each with

IC/OC/OCN/PWM, dead-time generation

and emergency stop

– 2 watchdog timers (Independent and

Window)

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

– SysTick timer: 24-bit downcounter

– Two 16-bit basic timers to drive the DAC

■ Low power

– Sleep, Stop and Standby modes

■ Up to 8 communication interfaces

– V

supply for RTC and backup registers

BAT

2

– Up to two I C interfaces (SMBus/PMBus)

■ Debug mode

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Serial wire debug (SWD) and JTAG

interfaces

– Up to 2 SPIs (12 Mbit/s)

– Consumer electronics control (CEC)

interface

■ DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

■ CRC calculation unit, 96-bit unique ID

2

I Cs, USARTs and DACs

®

■ ECOPACK packages

■ 1 × 12-bit, 1.2 µs A/D converter (up to 16

channels)

Table 1.

Device summary

– Conversion range: 0 to 3.6 V

– Temperature sensor

Reference

Part number

STM32F100x4

STM32F100x6

STM32F100C4, STM32F100R4

STM32F100C6, STM32F100R6

■ 2 × 12-bit D/A converters

■ Up to 80 fast I/O ports

STM32F100C8, STM32F100R8,

STM32F100V8

STM32F100x8

STM32F100xB

– 37/51/80 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

STM32F100CB, STM32F100RB,

STM32F100VB

February 2010

Doc ID 16455 Rev 2

1/84

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

2.2

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1

ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 14

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 14

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 15

External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 15

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.10 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.11 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.12 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.13 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.14 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.15 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . . 17

2.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.16.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.16.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16 & TIM17) . 18

2.16.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.16.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.16.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.16.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

²

2.17 I C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.18 Universal synchronous/asynchronous receiver transmitter (USART) . . . 20

2.19 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.20 HDMI (high-definition multimedia interface) consumer

electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 21

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Contents

2.22 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.23 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.24 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.26 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3

4

5

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2

5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35

Embedded reset and power control block characteristics . . . . . . . . . . . 35

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 53

5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3.14 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.1

6.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.2.1

6.2.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 80

7

8

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4/84

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F100xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

STM32F100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 36

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

STM32F100xxB maximum current consumption in Sleep mode, code

Table 13.

Table 14.

running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 40

Typical current consumption in Run mode, code with data processing

Table 15.

Table 16.

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 43

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

HSE 4-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

SCL frequency (f

= 24 MHz, V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PCLK1

DD

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

R

max for f

= 12 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

AIN

ADC

ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 45.

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 74

LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 75

TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 76

LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 78

Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6/84

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STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

STM32F100xx value line block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

STM32F100xx value line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

STM32F100xx value line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

STM32F100xx value line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

STM32F100xx value line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12. Maximum current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 39

Figure 13. Maximum current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 39

Figure 14. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DD

Figure 15. Typical current consumption in Stop mode with regulator in Low-power mode versus

temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DD

Figure 16. Typical current consumption in Standby mode versus temperature at V = 3.3 V and

DD

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 18. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 21. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 22. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 23. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 24. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 25. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 26. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

2

(1)

Figure 27. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

(1)

Figure 29. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 30. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

(1)

Figure 31. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 32. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 33. Power supply and reference decoupling (V

Figure 34. Power supply and reference decoupling (V

not connected to V

). . . . . . . . . . . . . . 69

). . . . . . . . . . . . . . . . . 69

REF+

DDA

connected to V

REF+

DDA

Figure 35. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 36. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 74

(1)

Figure 37. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 38. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 75

(1)

Figure 39. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 40. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 76

Figure 41. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 77

Figure 42. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Doc ID 16455 Rev 2

7/84

List of figures

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

(1)

Figure 43. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 44. LQFP100 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

D

A

8/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Introduction

1

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F100x4, STM32F100x6, STM32F100x8 and STM32F100xB value line

microcontrollers. In the rest of the document, the STM32F100x4 and STM32F100x6 are

referred to as low-density devices while the STM32F100x8 and STM32F100xB are

identified as medium-density devices.

The STM32F100xx datasheet should be read in conjunction with the low- and medium-

density STM32F100xx reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F100xx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Doc ID 16455 Rev 2

9/84

Description

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

2

Description

The STM32F100xx value line family incorporates the high-performance ARM Cortex™-M3

32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash

memory up to 128 Kbytes and SRAM up to 8 Kbytes), and an extensive range of enhanced

peripherals and I/Os connected to two APB buses. All devices offer standard communication

2

interfaces (up to two I Cs, two SPIs, one HDMI CEC, and up to three USARTs), one 12-bit

ADC, two 12-bit DACs, up to six general-purpose 16-bit timers and an advanced-control

PWM timer.

The STM32F100xx low- and medium-density value line family operates in the –40 to +85 °C

and –40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive

set of power-saving mode allows the design of low-power applications.

The STM32F100xx value line family includes devices in three different packages ranging

from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are

included, the description below gives an overview of the complete range of peripherals

proposed in this family.

These features make the STM32F100xx value line microcontroller family suitable for a wide

range of applications:

●

Application control and user interface

Medical and handheld equipment

PC peripherals, gaming and GPS platforms

Industrial applications: PLC, inverters, printers, and scanners

Alarm systems, Video intercom, and HVAC

Figure 1 shows the general block diagram of the device family.

10/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Description

STM32F100Vx

2.1

Device overview

Table 2.

STM32F100xx features and peripheral counts

Peripheral

STM32F100Cx

STM32F100Rx

Flash - Kbytes

SRAM - Kbytes

16

4

32

4

64

8

128

8

16

4

32

4

64

8

128

8

64

8

128

8

Advanced-control

1

6

2

3

1

6

2

3

1

6

2

3

Timers

General-purpose

5⁽¹⁾

1⁽²⁾

1⁽³⁾

2⁽⁴⁾

5⁽¹⁾

1⁽²⁾

1⁽³⁾

2⁽⁴⁾

SPI

I²C

Communication

interfaces

USART

CEC

1

12-bit synchronized ADC

number of channels

1

10 channels

37

16 channels

51

16 channels

80

GPIOs

12-bit DAC

2

Number of channels

CPU frequency

24 MHz

Operating voltage

2.0 to 3.6 V

Ambient operating temperature: –40 to +85 °C /–40 to +105 °C (see Table 8)

Junction temperature: –40 to +125 °C (see Table 8)

Operating temperatures

Packages

LQFP48

LQFP64, TFBGA64

LQFP100

1. TIM4 not present.

2. SPI2 is not present.

3. I2C2 is not present.

4. USART3 is not present.

Doc ID 16455 Rev 2

11/84

Description

Figure 1.

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

STM32F100xx value line block diagram

42!#%#,+

42!#%$;ꢃꢂꢌ=

AS !&

4RACE

CONTROLLER

PBUS

*4!' ꢒ 37

0OWER

6

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6

ꢋ ꢅꢄꢃ 6 TO ꢌꢄꢇ 6

$$

6OLTAGE REGꢄ

ꢌꢄꢌ 6 TO ꢀꢄꢍ 6

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6$$!

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ꢐ CHANNELS

84!, /3#

ꢎꢆꢅꢎ -(Z

0,,

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0#,+ꢀ

2ESET ꢒ

CLOCK

CONTROL

0#,+ꢅ

(#,+

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3TANDBY

INTERFACE

6

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7+50

6

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/3#ꢌꢅ?/54

84!, ꢌꢅ K(Z

'0)/ PORT !

'0)/ PORT "

0!;ꢀꢁꢂꢃ=

0";ꢀꢁꢂꢃ=

0#;ꢀꢁꢂꢃ=

0$;ꢀꢁꢂꢃ=

0%;ꢀꢁꢂꢃ=

"ACKUP

REGISTER

24#

!75

4!- 0%2ꢆ24#

ꢈ!,!2- /54ꢉ

"ACKUP INTERFACE

'0)/ PORT #

ꢎ CHANNELS

AS !&

ꢎ CHANNELS

AS !&

4)-ꢅ

!("ꢅ

!0"ꢅ

!("ꢅ

!0"ꢀ

'0)/ PORT $

'0)/ PORT %

4)-ꢌ

ꢈꢀꢉ

ꢎ CHANNELS

AS !&

4)-ꢎ

ꢅ CHANNELSꢑ ꢀ COMPLꢄ

CHANNEL AND "+).

AS !&

4)-ꢀꢁ

4)-ꢀꢇ

4)-ꢀꢐ

28ꢑ48ꢑ #43ꢑ 243ꢑ

#+ AS !&

53!24ꢅ

ꢀ CHANNELꢑ ꢀ COMPLꢄ

CHANNEL AND "+).

AS !&

ꢈꢀꢉ

28ꢑ48ꢑ #43ꢑ 243ꢑ

#+ AS !&

53!24ꢌ

-/3)ꢑ -)3/ꢑ

3#+ꢑ .33 AS !&

ꢈꢀꢉ

ꢀ CHANNELꢑ ꢀ COMPLꢄ

CHANNEL AND "+).

AS !&

30)ꢅ

($-) #%#

)ꢅ#ꢀ

($-) #%# AS !&

ꢎ CHANNELSꢑ ꢌ COMPLꢄ

CHANNELSꢑ %42 AND

"+). AS !&

4)-ꢀ

3#,ꢑ 3$!ꢑ 3-"! AS !&

-/3)ꢑ -)3/ꢑ

3#+ꢑ .33 AS !&

30)ꢀ

ꢈꢀꢉ

)ꢅ#ꢅ

77$'

28ꢑ48ꢑ #43ꢑ 243ꢑ

#+ AS !&

53!24ꢀ

4EMP SENSOR

ꢀꢅꢆBIT $!#ꢀ

ꢀꢅꢆBIT $!#ꢅ

)&

4)-ꢇ

4)-ꢐ

$!#ꢀ?/54 AS !&

$!#ꢅ?/54 AS !&

ꢀꢇ !$# CHANNELS

ꢈ!$#?).Xꢉ

ꢀꢅꢆBIT !$#ꢀ )&

6

2%&ꢏ

6$$!

6

2%&n

6$$!

AIꢀꢁꢓꢃꢀB

1. Peripherals not present in low-density value line devices.

2. AF = alternate function on I/O port pin.

3. T_A= –40 °C to +85 °C (junction temperature up to 105 °C) or T_A= –40 °C to +105 °C (junction temperature up to 125 °C).

12/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Description

Figure 2.

Clock tree

ꢍ -(Z

(3) 2#

(3)

ꢊꢅ

(#,+

ꢅꢎ -(Z MAX

TO !(" BUSꢑ COREꢑ

MEMORY AND $-!

#LOCK

%NABLE

TO #ORTEX 3YSTEM TIMER

ꢊꢍ

37

0,,32#

&#,+ #ORTEX

FREE RUNNING CLOCK

ꢅꢎ -(Z MAX

0,,-5,

(3)

!("

0RESCALER

ꢊꢀꢑ ꢅꢄꢄꢁꢀꢅ

!0"ꢀ

0RESCALER

ꢊꢀꢑ ꢅꢑ ꢎꢑ ꢍꢑ ꢀꢇ

393#,+

ꢄꢄꢄꢑ Xꢀꢇ

Xꢅꢑ Xꢌꢑ Xꢎ

0,,

0#,+ꢀ

0,,#,+

(3%

ꢅꢎ -(Z

MAX

TO !0"ꢀ

PERIPHERALS

0ERIPHERAL #LOCK

%NABLE

4)-ꢅꢑꢌꢑꢎꢑꢇꢑꢐ

)F ꢈ!0"ꢀ PRESCALER ꢋꢀꢉ Xꢀ

ELSE Xꢅ

TO 4)-ꢅꢑꢌꢑꢎꢑꢇ AND ꢐ

4)-X#,+

#33

0ERIPHERAL #LOCK

%NABLE

02%$)6ꢀ

!0"ꢅ

0RESCALER

ꢊꢀꢑ ꢅꢑ ꢎꢑ ꢍꢑ ꢀꢇ

ꢅꢎ -(Z MAX

0#,+ꢅ

ꢊꢀꢊꢅꢊꢌꢄꢄꢄꢊ

ꢄꢄꢄꢊꢀꢁꢊꢀꢇ

/3#?/54

/3#?).

PERIPHERALS TO !0"ꢅ

ꢎꢆꢅꢎ -(Z

(3% /3#

0ERIPHERAL #LOCK

%NABLE

TO 4)-ꢀꢑ 4)-ꢀꢁꢑ

4)-ꢀꢇ AND 4)-ꢀꢐ

4)-ꢀꢊꢀꢁꢊꢀꢇꢊꢀꢐ TIMERS

)F ꢈ!0"ꢅ PRESCALER ꢋꢀꢉ Xꢀ

ELSE Xꢅ

4)-X#,+

0ERIPHERAL #LOCK

%NABLE

ꢊꢀꢅꢍ

,3%

!$#

0RESCALER

ꢊꢅꢑ ꢎꢑ ꢇꢑ ꢍ

TO !$#ꢀ

/3#ꢌꢅ?).

TO 24#

,3% /3#

!$##,+ ꢀꢅ -(Z MAX

24##,+

ꢌꢅꢄꢐꢇꢍ K(Z

/3#ꢌꢅ?/54

24#3%,;ꢀꢂꢃ=

TO INDEPENDENT WATCHDOG ꢈ)7$'ꢉ

)7$'#,+

,3)

,3) 2#

ꢎꢃ K(Z

,EGENDꢀ

-AIN

CLOC K OUT PUT

ꢊꢅ

0,,#,+

(3% ꢋ (IGHꢆSPEED EXTERNAL CLOCK SIGNAL

(3) ꢋ (IGHꢆSPEED INTERNAL CLOCK SIGNAL

,3) ꢋ ,OWꢆSPEED INTERNAL CLOCK SIGNAL

,3% ꢋ ,OWꢆSPEED EXTERNAL CLOCK SIGNAL

-#/

(3)

(3%

393#,+

-#/

AIꢀꢐꢌꢀꢀ

4. To have an ADC conversion time of 1.2 µs, APB2 must be at 24 MHz.

Doc ID 16455 Rev 2

13/84

Description

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

2.2

Overview

®

2.2.1

ARM Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The STM32F100xx value line family having an embedded ARM core, is therefore

compatible with all ARM tools and software.

2.3

2.4

Embedded Flash memory

Up to 128 Kbytes of embedded Flash memory is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

2.5

Embedded SRAM

Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

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Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Description

2.6

Nested vectored interrupt controller (NVIC)

The STM32F100xx value line embeds a nested vectored interrupt controller able to handle

up to 41 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)

and 16 priority levels.

●

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.7

2.8

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 18 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected

to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 24 MHz.

2.9

Boot modes

At startup, boot pins are used to select one of three boot options:

●

Boot from user Flash

Boot from system memory

Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1. For further details please refer to AN2606.

Doc ID 16455 Rev 2

15/84

Description

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

2.10

Power supply schemes

●

V

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

DD

Provided externally through V pins.

DD

●

V

, V

= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs

DDA

SSA

and PLL (minimum voltage to be applied to V

is 2.4 V when the ADC is used).

DDA

V

and V

must be connected to V and V , respectively.

DDA

SSA DD SS

●

V

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup

BAT

registers (through power switch) when V is not present.

DD

2.11

Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V is below a specified threshold, V

, without the need for an

DD

POR/PDR

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

/V power supply and compares it to the V threshold. An interrupt can be

V

DD DDA

PVD

generated when V /V

drops below the V

threshold and/or when V /V

is higher

DD DDA

PVD

DD DDA

than the V

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

2.12

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●

MR is used in the nominal regulation mode (Run)

LPR is used in the Stop mode

Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

2.13

Low-power modes

The STM32F100xx value line supports three low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

●

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode.

16/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Description

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output or the RTC alarm.

●

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.14

DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

2

The DMA can be used with the main peripherals: SPI, DAC, I C, USART, all timers and

ADC.

2.15

RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

V

supply when present or through the V_BATpin. The backup registers are ten 16-bit

DD

registers used to store 20 bytes of user application data when V power is not present.

DD

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural crystal deviation. The RTC

features a 32-bit programmable counter for long term measurement using the Compare

register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by

default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.16

Timers and watchdogs

The STM32F100xx devices include an advanced-control timer, six general-purpose timers,

two basic timers and two watchdog timers.

Table 3 compares the features of the advanced-control, general-purpose and basic timers.

Doc ID 16455 Rev 2

17/84

Description

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 3.

Timer

Timer feature comparison

Counter

Counter Prescaler DMA request Capture/compare Complementary

resolution

type

factor

generation

channels

outputs

Up,

down,

Any integer

between 1

TIM1

16-bit

Yes

4

Yes

up/down and 65536

TIM2,

TIM3,

TIM4

Up,

down,

Any integer

between 1

Yes

4

2

1

0

No

Yes

No

up/down and 65536

Any integer

TIM15

Up

between 1

and 65536

Any integer

between 1

and 65536

TIM16,

TIM17

Any integer

between 1

and 65536

TIM6,

TIM7

2.16.1

Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6

channels. It has complementary PWM outputs with programmable inserted dead times. It

can also be seen as a complete general-purpose timer. The 4 independent channels can be

used for:

●

Input capture

Output compare

PWM generation (edge or center-aligned modes)

One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same

architecture. The advanced control timer can therefore work together with the TIM timers via

the Timer Link feature for synchronization or event chaining.

2.16.2

General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16 & TIM17)

There are six synchronizable general-purpose timers embedded in the STM32F100xx

devices (see Table 3 for differences). Each general-purpose timers can be used to generate

PWM outputs, or as simple time base.

TIM2, TIM3, TIM4

STM32F100xx devices feature three synchronizable 4-channels general-purpose timers.

These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.

They feature 4 independent channels each for input capture/output compare, PWM or one-

18/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Description

pulse mode output. This gives up to 12 input captures/output compares/PWMs on the

largest packages.

The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM1

advanced-control timer via the Timer Link feature for synchronization or event chaining.

TIM2, TIM3, TIM4 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Their counters can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single

channel for input capture/output compare, PWM or one-pulse mode output.

The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with

TIM1 via the Timer Link feature for synchronization or event chaining.

TIM15 can be synchronized with TIM16 and TIM17.

TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and

independent DMA request generation

Their counters can be frozen in debug mode.

2.16.3

2.16.4

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a

generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to

reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

2.16.5

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

Doc ID 16455 Rev 2

19/84

Description

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

2.16.6

SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It

features:

●

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0.

Programmable clock source

²

2.17

2.18

I C bus

The I²C bus interface can operate in multimaster and slave modes. It can support standard

and fast modes.

It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.

A hardware CRC generation/verification is embedded.

The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.

Universal synchronous/asynchronous receiver transmitter

(USART)

The STM32F100xx value line embeds three universal synchronous/asynchronous receiver

transmitters (USART1, USART2 and USART3).

The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware

management of the CTS and RTS signals, they support IrDA SIR ENDEC, the

multiprocessor communication mode, the single-wire half-duplex communication mode and

have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

2.19

2.20

Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-

duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits.

Both SPIs can be served by the DMA controller.

HDMI (high-definition multimedia interface) consumer

electronics control (CEC)

The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware

support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI

standard).

This protocol provides high-level control functions between all audiovisual products in an

environment. It is specified to operate at low speeds with minimum processing and memory

overhead.

20/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Description

2.21

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

2.22

Remap capability

This feature allows the use of a maximum number of peripherals in a given application.

Indeed, alternate functions are available not only on the default pins but also on other

specific pins onto which they are remappable. This has the advantage of making board

design and port usage much more flexible.

For details refer to Table 4: STM32F100xx pin definitions; it shows the list of remappable

alternate functions and the pins onto which they can be remapped. See the STM32F10xxx

reference manual for software considerations.

2.23

2.24

ADC (analog-to-digital converter)

The 12-bit analog to digital converter has up to 16 external channels and performs

conversions in single-shot or scan modes. In scan mode, automatic conversion is performed

on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two

analog voltage signal outputs. The chosen design structure is composed of integrated

resistor strings and an amplifier in noninverting configuration.

This dual digital Interface supports the following features:

●

two DAC converters: one for each output channel

up to 10-bit output

left or right data alignment in 12-bit mode

synchronized update capability

noise-wave generation

triangular-wave generation

dual DAC channels’ independent or simultaneous conversions

DMA capability for each channel

external triggers for conversion

input voltage reference V

REF+

Doc ID 16455 Rev 2

21/84

Description

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Eight DAC trigger inputs are used in the STM32F100xx. The DAC channels are triggered

through the timer update outputs that are also connected to different DMA channels.

2.25

Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The

conversion range is between 2 V < V

< 3.6 V. The temperature sensor is internally

DDA

connected to the ADC1_IN16 input channel which is used to convert the sensor output

voltage into a digital value.

2.26

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a

specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

22/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Pinouts and pin description

3

Pinouts and pin description

Figure 3.

STM32F100xx value line LQFP100 pinout

PE2

PE3

PE4

PE5

PE6

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD_2

VSS_2

NC

PA 13

PA 12

PA 11

PA 10

PA 9

PA 8

PC9

PC8

PC7

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

9

10

VDD_5 11

LQFP100

OSC_IN

OSC_OUT

NRST

PC0

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0-WKUP

PA1

PD8

PB15

PB14

PB13

PB12

PA2

ai14386b

Doc ID 16455 Rev 2

23/84

Pinouts and pin description

Figure 4.

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

STM32F100xx value line LQFP64 pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

3

4

5

6

7

PC0

PC1

PC2

PC3

8

LQFP64

9

10

11

12

13

14

15

16

PC6

VSSA

VDDA

PA0-WKUP

PB15

PB14

PB13

PB12

PA1

PA2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

ai14387b

Figure 5.

STM32F100xx value line LQFP48 pinout

48 47 46 45 44 43 42 41 40 39 38 37

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

36

1

2

3

4

5

6

7

8

9

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

35

34

33

32

31

30

29

28

27

26

25

LQFP48

PA8

VSSA

VDDA

PB15

PB14

PB13

PB12

PA0-WKUP 10

PA1 11

12

PA2

24

13 14 15 16 17 18 19 20 21 22 23

ai14378d

24/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Pinouts and pin description

Figure 6.

STM32F100xx value line TFBGA64 ballout

1

2

3

4

5

6

7

8

PC14-

OSC32_IN

PC13-

TAMPER-RTC

A

B

PB9

PB8

PB7

PB6

PB4

BOOT0

PB5

PB3

PD2

PA15

PC11

PA10

PA14

PC10

PA9

PA13

PA12

PA11

PC9

PC15-

OSC32_OUT

V

BAT

C

D

E

F

OSC_IN

V

PC12

SS_4

OSC_OUT

NRST

V

PA8

DD_4

SS_3

SS_2

SS_1

PC1

PC2

PC0

PA2

V

PC7

PC8

DD_3

DD_2

DD_1

V

PA5

PB0

PC6

PB15

PB14

SSA

V

REF+

G

H

PA0-WKUP

PA1

PA3

PA4

PA6

PA7

PB1

PC4

PB2

PC5

PB10

PB11

PB13

PB12

V

DDA

AI15494

Table 4.

Pins

STM32F100xx pin definitions

Pin name

Alternate functions⁽³⁾⁽⁴⁾

Default

Main

function⁽³⁾

Remap

(after reset)

1

2

3

4

5

6

-

PE2

PE3

PE4

PE5

PE6

V_BAT

I/O FT

S

PE2

PE3

PE4

PE5

PE6

V_BAT

TRACECLK

TRACED0

TRACED1

TRACED2

TRACED3

-

1

B2

1

PC13-TAMPER-

RTC⁽⁵⁾

7

2

A2

2

I/O

PC13⁽⁶⁾

TAMPER-RTC

Doc ID 16455 Rev 2

25/84

Pinouts and pin description

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 4.

Pins

STM32F100xx pin definitions (continued)

Alternate functions⁽³⁾⁽⁴⁾

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

PC14-

8

9

3

A1

B1

3

4

I/O

PC14⁽⁶⁾

PC15⁽⁶⁾

OSC32_IN

OSC32_IN⁽⁵⁾

PC15-

4

OSC32_OUT

OSC32_OUT⁽⁵⁾

10

11

12

13

14

15

16

-

V_{SS_5}

V_{DD_5}

OSC_IN

OSC_OUT

NRST

PC0

S

V_{SS_5}

V_{DD_5}

OSC_IN

OSC_OUT

NRST

PC0

-

5

6

7

8

9

C1

D1

E1

E3

E2

5

6

7

-

I

O

I/O

S

ADC1_IN10

ADC1_IN11

ADC1_IN12

ADC1_IN13

-

PC1

17 10 F2

-

PC2

(7)

18 11

-

PC3

19 12 F1

8

-

V_SSA

20

21

-

V_REF-

V_REF+

V_DDA

S

V_REF-

V_REF+

V_DDA

G1

-

S

22 13 H1

9

S

WKUP / USART2_CTS⁽¹²⁾

/

23 14 G2 10

24 15 H2 11

25 16 F3 12

26 17 G3 13

PA0-WKUP

PA1

I/O

PA0

PA1

PA2

PA3

ADC1_IN0 / TIM2_CH1_ETR⁽¹²⁾

USART2_RTS⁽¹²⁾/ ADC1_IN1 /

TIM2_CH2⁽¹²⁾

USART2_TX⁽¹²⁾/ ADC1_IN2 /

TIM2_CH3⁽¹²⁾/ TIM15_CH1⁽¹²⁾

PA2

USART2_RX⁽¹²⁾/ ADC1_IN3 /

TIM2_CH4⁽¹²⁾/ TIM15_CH2⁽¹²⁾

PA3

27 18 C2

28 19 D2

-

V_{SS_4}

V_{DD_4}

S

V_{SS_4}

V_{DD_4}

SPI1_NSS⁽¹²⁾/ADC1_IN4

29 20 H3 14

30 21 F4 15

31 22 G4 16

32 23 H4 17

PA4

PA5

PA6

I/O

PA4

PA5

PA6

USART2_CK⁽¹²⁾/ DAC1_OUT

SPI1_SCK⁽¹²⁾/ADC1_IN5 /

DAC2_OUT

SPI1_MISO⁽¹²⁾/ADC1_IN6 /

TIM3_CH1⁽¹²⁾

TIM1_BKIN /

TIM16_CH1

SPI1_MOSI⁽¹²⁾/ADC1_IN7 /

TIM3_CH2⁽¹²⁾

TIM1_CH1N /

TIM17_CH1

PA7

PC4

I/O

PA7

PC4

33 24 H5

-

ADC1_IN14

26/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Pinouts and pin description

Alternate functions⁽³⁾⁽⁴⁾

Table 4.

Pins

STM32F100xx pin definitions (continued)

Main

Pin name

function⁽³⁾

Default

Remap

(after reset)

34 25 H6

-

PC5

PB0

I/O

PC5

PB0

PB1

ADC1_IN15

35 26 F5 18

36 27 G5 19

37 28 G6 20

ADC1_IN8/TIM3_CH3⁽¹²⁾

ADC1_IN9/TIM3_CH4⁽¹²⁾

TIM1_CH2N

TIM1_CH3N

PB1

PB2

I/O FT PB2/BOOT1

38

39

40

41

42

43

44

45

46

-

PE7

I/O FT

PE7

PE8

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PE10

PE11

PE12

PE13

PE14

PE15

TIM2_CH3 /

CEC

(12)

47 29 G7 21

PB10

I/O FT

PB10

I2C2_SCL⁽⁸⁾/USART3_TX

48 30 H7 22

49 31 D6 23

50 32 E6 24

PB11

V_{SS_1}

V_{DD_1}

I/O FT

PB11

V_{SS_1}

V_{DD_1}

I2C2_SDA⁽⁸⁾/USART3_RX⁽¹²⁾

TIM2_CH4

S

SPI2_NSS⁽⁹⁾/ I2C2_SMBA⁽⁸⁾

/

51 33 H8 25

52 34 G8 26

53 35 F8 27

54 36 F7 28

PB12

PB13

PB14

PB15

I/O FT

PB12

PB13

PB14

PB15

TIM1_BKIN⁽¹²⁾/USART3_CK⁽¹²⁾

SPI2_SCK⁽⁹⁾/TIM1_CH1N⁽¹²⁾

USART3_CTS⁽¹²⁾

SPI2_MISO⁽⁹⁾/ TIM1_CH2N⁽¹²⁾

USART3_RTS⁽¹²⁾

/

TIM15_CH1

TIM15_CH2

SPI2_MOSI⁽⁹⁾/ TIM1_CH3N /

TIM15_CH1N⁽¹²⁾

55

56

57

58

-

PD8

PD9

I/O FT

PD8

PD9

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

PD10

PD11

PD10

PD11

TIM4_CH1⁽¹⁰⁾

USART3_RTS

/

59

-

PD12

I/O FT

PD12

60

61

-

PD13

PD14

I/O FT

PD13

PD14

TIM4_CH2⁽¹⁰⁾

TIM4_CH3⁽¹⁰⁾

Doc ID 16455 Rev 2

27/84

Pinouts and pin description

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 4.

Pins

STM32F100xx pin definitions (continued)

Alternate functions⁽³⁾⁽⁴⁾

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

62

-

PD15

PC6

PC7

PC8

PC9

I/O FT

PD15

PC6

PC7

PC8

PC9

TIM4_CH4⁽¹⁰⁾

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

63 37 F6

64 38 E7

65 39 E8

66 40 D8

-

USART1_CK / MCO /

TIM1_CH1

67 41 D7 29

PA8

I/O FT

PA8

68 42 C7 30

69 43 C6 31

70 44 C8 32

71 45 B8 33

PA9

I/O FT

PA9

USART1_TX⁽¹²⁾/ TIM1_CH2

USART1_RX⁽¹²⁾/ TIM1_CH3

USART1_CTS / TIM1_CH4

USART1_RTS / TIM1_ETR

TIM15_BKIN

TIM17_BKIN

PA10

PA11

PA12

PA10

PA11

PA12

JTMS-

SWDIO

72 46 A8 34

PA13

I/O FT

PA13

73

-

Not connected

V_{SS_2}

74 47 D5 35

75 48 E5 36

V_{SS_2}

V_{DD_2}

S

V_{DD_2}

JTCK/SWCL

K

76 49 A7 37

77 50 A6 38

PA14

PA15

I/O FT

PA14

TIM2_CH1_ETR

/ PA15/

JTDI

SPI1_NSS

78 51 B7

79 52 B6

80 53 C5

-

PC10

PC11

PC12

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

I/O FT

PC10

PC11

PC12

USART3_TX

USART3_RX

USART3_CK

-

81

82

5

6

C1

D1

5

6

I/O FT OSC_IN⁽¹¹⁾

I/O FT OSC_OUT⁽¹¹⁾

83 54 B5

I/O FT

PD2

PD3

PD4

PD5

PD6

PD7

TIM3_ETR

84

85

86

87

88

-

USART2_CTS

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

TIM2_CH2 / PB3

TRACESWO

SPI1_SCK

89 55 A5 39

PB3

I/O FT

JTDO

28/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Pinouts and pin description

Alternate functions⁽³⁾⁽⁴⁾

Table 4.

Pins

STM32F100xx pin definitions (continued)

Main

Pin name

function⁽³⁾

Default

Remap

(after reset)

PB4 / TIM3_CH1

SPI1_MISO

90 56 A4 40

91 57 C4 41

92 58 D3 42

PB4

PB5

PB6

I/O FT

I/O

NJTRST

PB5

TIM3_CH2 /

SPI1_MOSI

I2C1_SMBA / TIM16_BKIN

I2C1_SCL⁽¹²⁾/ TIM4_CH1^(10)(12)

TIM16_CH1N

I/O FT

PB6

USART1_TX

USART1_RX

I2C1_SDA⁽¹²⁾/ TIM17_CH1N

TIM4_CH2^(10)(12)

93 59 C3 43

94 60 B4 44

95 61 B3 45

PB7

BOOT0

PB8

I/O FT

I

PB7

BOOT0

PB8

TIM4_CH3^(10)(12)

TIM16_CH1⁽¹²⁾/ CEC⁽¹²⁾

/

I/O FT

I2C1_SCL

I2C1_SDA

TIM4_CH4^(10)(12)

TIM17_CH1⁽¹²⁾

/

96 62 A3 46

PB9

I/O FT

PB9

97

98

-

PE0

PE1

I/O FT

PE0

PE1

TIM4_ETR⁽¹⁰⁾

I/O FT

99 63 D4 47

100 64 E4 48

V_{SS_3}

V_{DD_3}

S

V_{SS_3}

V_{DD_3}

1. I = input, O = output, S = supply, HiZ= high impedance.

2. FT= 5 V tolerant.

3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower

number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be

called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should

be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed should not exceed 2 MHz with a maximum

load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even

after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com.

7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V_REF+functionality is provided instead.

8. I2C2 is not present on low-density value line devices.

9. SPI2 is not present on low-density value line devices.

10. TIM4 is not present on low-density value line devices.

11. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the

TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be

remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in

the STM32F10xxx reference manual.

12. This alternate function can be remapped by software to some other port pins (if available on the used package). For more

details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available

from the STMicroelectronics website: www.st.com.

Doc ID 16455 Rev 2

29/84

Memory mapping

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

4

Memory mapping

The memory map is shown in Figure 7.

Figure 7.

Memory map

APB memory space

0xFFFF FFFF

reserved

0x4002 3400

CRC

0x4002 3000

reserved

0x4002 2400

Flash interface

0xFFFF FFFF

0x4002 2000

reserved

0x4002 1400

RCC

0x4002 1000

7

reserved

0x4002 0400

0xE010 0000

0xE000 0000

DMA

0x4002 0000

Cortex-M3 internal

peripherals

reserved

0x4001 4C00

TIM17

0x4001 4800

TIM16

0x4001 4400

6

TIM15

0x4001 4000

reserved

0x4001 3C00

0xC000 0000

USART1

0x4001 3800

reserved

0x4001 3400

SPI1

0x4001 3000

5

TIM1

0x4001 2C00

reserved

0xA000 0000

0x4001 2800

ADC1

0x4001 2400

reserved

0x4001 1C00

Port E

0x4001 1800

4

0x1FFF FFFF

reserved

Port D

Port C

Port B

Port A

EXTI

0x4001 1400

0x4001 1000

0x4001 0C00

0x4001 0800

0x4001 0400

0x4001 0000

0x4000 7C00

0x4000 7800

0x1FFF F80F

0x8000 0000

Option Bytes

0x1FFF F800

System memory

3

AFIO

0x1FFF F000

reserved

CEC

0x6000 0000

DAC

0x4000 7400

0x4000 7000

0x4000 6C00

0x4000 5C00

0x4000 5800

0x4000 5400

2

PWR

BKP

reserved

Peripherals

I2C2

0x4000 0000

reserved

I2C1

1

reserved

USART3

USART2

0x4000 4C00

0x4000 4800

0x4000 4400

SRAM

0x2000 0000

0x0801 FFFF

reserved

SPI2

0x4000 3C00

0x4000 3800

0x4000 3400

0x4000 3000

0x4000 2C00

0x4000 2800

Flash memory

0

reserved

IWDG

0x0800 0000

0x0000 0000

Aliased to Flash or

system memory

depending on

BOOT pins

WWDG

RTC

0x0000 0000

reserved

Reserved

0x4000 1800

0x4000 1400

0x4000 1000

0x4000 0C00

0x4000 0800

0x4000 0400

0x4000 0000

TIM7

TIM6

reserved

TIM4

TIM3

TIM2

ai17156

30/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

5

Electrical characteristics

5.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

5.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3).

5.1.2

5.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the

A

DD

2 V  V  3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean 2).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

5.1.4

5.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Doc ID 16455 Rev 2

31/84

Electrical characteristics

Figure 8.

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Pin loading conditions

Figure 9.

Pin input voltage

STM32F10xxx pin

C= 50 pF

V

IN

ai14124b

ai14123b

5.1.6

Power supply scheme

Figure 10. Power supply scheme

V

BAT

Backup circuitry

(OSC32K,RTC,

Wake-up logic

Power switch

1.8-3.6V

Backup registers)

OUT

IN

IO

Logic

GP I/Os

Kernel logic

(CPU,

Digital

& Memories)

V

DD

V

DD

1/2/3/4/5

Regulator

5 × 100 nF

+ 1 × 4.7 µF

V

SS

1/2/3/4/5

V

DD

V

DDA

V

REF

V

REF+

Analog:

RCs, PLL,

...

10 nF

+ 1 µF

10 nF

+ 1 µF

V

ADC

REF-

V

SSA

ai14125d

Caution:

In Figure 10, the 4.7 µF capacitor must be connected to V

.

DD3

32/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

5.1.7

Current consumption measurement

Figure 11. Current consumption measurement scheme

I

_V

DD BAT

V

BAT

I

DD

V

DD

V

DDA

ai14126

5.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,

Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device

at these conditions is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Table 5.

Symbol

Voltage characteristics

Ratings

Min

Max

Unit

External main supply voltage (including

V_DD V_SS

–0.3

4.0

(1)

V_DDAand V_DD

)

V

Input voltage on five volt tolerant pin⁽²⁾

Input voltage on any other pin⁽²⁾

V_SS 0.3

V_SS0.3

+5.5

V_DD+0.3

50

V_IN

|V_DDx

|

Variations between different V_DDpower pins

mV

Variations between all the different ground

pins

|V_SSXV_SS

|

50

see Section 5.3.11:Absolute

maximum ratings (electrical

sensitivity)

Electrostatic discharge voltage (human body

model)

V_ESD(HBM)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. I_INJ(PIN)must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if V_IN

maximum is respected. If V_INmaximum cannot be respected, the injection current must be limited

externally to the I_INJ(PIN)value. A positive injection is induced by V_IN> V_INmax while a negative injection is

induced by V_IN<V_SS

.

Doc ID 16455 Rev 2

33/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 6.

Symbol

Current characteristics

Ratings

Max.

Unit

I_VDD

I_VSS

Total current into V_DD/V_DDApower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on NRST pin

150

25

I_IO

25

5

mA

Injected current on High-speed external OSC_IN and Low-

speed external OSC_IN pins

5

(2)(3)

I_INJ(PIN)

Injected current on the PA5 and PA6 pins⁽⁴⁾

Injected current on any other pin⁽⁴⁾

+5 / –0

5

Total injected current (sum of all I/O and control pins)⁽⁴⁾

25

(2)

I_INJ(PIN)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS

.

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC

characteristics.

4. When several inputs are submitted to a current injection, the maximum I_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterization with I_INJ(PIN)maximum current injection on four I/O port pins of the device.

Table 7.

Thermal characteristics

Ratings

Symbol

Value

Unit

T_STG

T_J

Storage temperature range

–65 to +150

150

°C

Maximum junction temperature

5.3

Operating conditions

5.3.1

General operating conditions

Table 8.

Symbol

General operating conditions

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK1

f_PCLK2

V_DD

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

0

2

24

3.6

MHz

V

Analog operating voltage

(ADC not used)

2

3.6

Must be the same potential

as V_DD

(1)

V_DDA

V

Analog operating voltage

(ADC used)

2.4

34/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

Table 8.

Symbol

General operating conditions (continued)

Parameter

Conditions

Min

Max

Unit

V_BAT

Backup operating voltage

1.8

3.6

434

444

308

363

85

V

LQFP100

Power dissipation at T_A=

85 °C for suffix 6 or T_A=

105 °C for suffix 7⁽²⁾

LQFP64

TFBGA64

LQFP48

P_D

mW

Maximum power dissipation –40

Low power dissipation⁽³⁾

–40

Maximum power dissipation –40

Ambient temperature for 6

suffix version

°C

105

125

105

125

TA

TJ

Ambient temperature for 7

suffix version

Low power dissipation⁽³⁾

–40

6 suffix version

Junction temperature range

7 suffix version

1. When the ADC is used, refer to Table 41: ADC characteristics.

2. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax (see Table 6.2: Thermal

characteristics on page 79).

3. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax (see

Table 6.2: Thermal characteristics on page 79).

5.3.2

Operating conditions at power-up / power-down

Subject to general operating conditions for T .

A

Table 9.

Symbol

Operating conditions at power-up / power-down

Parameter

V_DDrise time rate

_DDfall time rate

Min

Max



Unit

0

t_VDD

µs/V

V

20



5.3.3

Embedded reset and power control block characteristics

The parameters given in Table 10 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Doc ID 16455 Rev 2

35/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

.

Table 10. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

2.1

2

2.18 2.26

2.08 2.16

V

2.19 2.28 2.37

2.09 2.18 2.27

2.28 2.38 2.48

2.18 2.28 2.38

2.38 2.48 2.58

2.28 2.38 2.48

2.47 2.58 2.69

2.37 2.48 2.59

2.57 2.68 2.79

2.47 2.58 2.69

2.66 2.78 2.9

2.56 2.68 2.8

V

Programmable voltage

detector level selection

V_PVD

V

2.76 2.88

3

V

2.66 2.78 2.9

100

V

(2)

V_PVDhyst

PVD hysteresis

mV

V

1.8⁽¹⁾

Falling edge

Rising edge

1.88 1.96

Power on/power down

reset threshold

V_POR/PDR

1.84 1.92 2.0

40

V

(2)

V_PDRhyst

PDR hysteresis

mV

ms

(2)

t_RSTTEMPO

Reset temporization

1.5

2.5

4.5

1. The product behavior is guaranteed by design down to the minimum V_POR/PDRvalue.

2. Guaranteed by design, not tested in production.

36/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

5.3.4

Embedded reference voltage

The parameters given in Table 11 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Table 11. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

–40 °C < T_A< +105 °C 1.16 1.20

1.26

1.24

V

V_REFINTInternal reference voltage

–40 °C < T_A< +85 °C

1.16 1.20

5.1

ADC sampling time when

reading the internal

reference voltage

(1)

17.1⁽²⁾

10

T_{S_vrefint}

µs

Internal reference voltage

spread over the temperature

range

(2)

V_RERINT

V_DD= 3 V 10 mV

mV

(2)

T_Coeff

Temperature coefficient

100 ppm/°C

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

5.3.5

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 11: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a

reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V or V (no load)

DD SS

All peripherals are disabled except if it is explicitly mentioned

Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f

= f

, f

= f

PCLK1

HCLK PCLK2 HCLK

The parameters given in Table 12 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Doc ID 16455 Rev 2

37/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 12. Maximum current consumption in Run mode, code with data processing

running from Flash

Max⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C T_A= 105 °C

24 MHz

16 MHz

8 MHz

15.4

11

15.7

11.5

6.9

External clock ⁽²⁾, all

peripherals enabled

Supply

current in

Run mode

6.7

10.3

7.8

5.1

I_DD

mA

24 MHz

16 MHz

8 MHz

10.5

8.1

External clock⁽²⁾, all

peripherals disabled

5.3

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

Table 13. Maximum current consumption in Run mode, code with data processing

running from RAM

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C T_A= 105 °C

24 MHz

16 MHz

8 MHz

14.5

10

15

10.5

6.3

9.7

7.2

4.7

External clock ⁽²⁾, all

peripherals enabled

6

Supply current

in Run mode

I_DD

mA

24MHz

16 MHz

8 MHz

9.3

6.8

4.4

External clock⁽²⁾all

peripherals disabled

1. Based on characterization, tested in production at V_DDmax, f_HCLKmax.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

38/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

Figure 12. Maximum current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled

ꢀꢇ

ꢀꢎ

ꢀꢅ

ꢀꢃ

ꢅꢎ -(Z

ꢀꢇ -(Z

ꢍ -(Z

ꢍ

ꢇ

ꢎ

ꢅ

ꢃ

nꢎꢃ

#

ꢅꢁ

#

ꢍꢁ

#

ꢀꢃꢁ #

4EMPERATURE ꢈ #ꢉ

AIꢀꢐꢐꢇꢁ

Figure 13. Maximum current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled

ꢀꢃ

ꢓ

ꢍ

ꢐ

ꢇ

ꢅꢎ -(Z

ꢀꢇ -(Z

ꢍ -(Z

ꢁ

ꢎ

ꢌ

ꢅ

ꢀ

ꢃ

nꢎꢃ

#

ꢅꢁ

#

ꢍꢁ

#

ꢀꢃꢁ #

4EMPERATURE ꢈ #ꢉ

AIꢀꢐꢐꢇꢇ

Table 14. STM32F100xxB maximum current consumption in Sleep mode, code

running from Flash or RAM

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C

T_A= 105 °C

24 MHz

16 MHz

8 MHz

9.6

7.1

4.5

3.8

3.3

2.7

10

7.5

4.8

4

External clock⁽²⁾all

peripherals enabled

Supply current

in Sleep mode

I_DD

mA

24 MHz

16 MHz

8 MHz

External clock⁽²⁾, all

peripherals disabled

3.5

3

1. Based on characterization, tested in production at V_DDmax and f_HCLKmax with peripherals enabled.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

Doc ID 16455 Rev 2

39/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

(1)

Table 15. Typical and maximum current consumptions in Stop and Standby modes

Typ⁽²⁾

Max

Symbol

Parameter

Conditions

Unit

V_DD/V_BATV_DD/ V_BATV_DD/V_BATT_A=

T_A=

= 2.0 V

= 2.4 V

= 3.3 V 85 °C 105 °C

Regulator in Run mode,

Low-speed and high-speed

internal RC oscillators and high-

speed oscillator OFF (no

independent watchdog)

23.5

24

14

190

170

350

330

Supply current

in Stop mode

Regulator in Low-Power mode,

Low-speed and high-speed

internal RC oscillators and high-

speed oscillator OFF (no

13.5

independent watchdog)

I_DD

Low-speed internal RC oscillator

and independent watchdog ON

µA

2.6

2.4

3.4

3.2

-

Low-speed internal RC oscillator

ON, independent watchdog OFF

Supply current

in Standby

mode

Low-speed internal RC oscillator

and independent watchdog OFF,

low-speed oscillator and RTC

OFF

1.7

1.1

2

4

5

Backup

I_{DD_VBAT}domain supply

current

Low-speed oscillator and RTC

ON

0.9

1.4

2.0

2.3

1. TBD stands for to be determined.

2. Typical values are measured at T_A= 25 °C.

Figure 14. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at V = 3.3 V and 3.6 V

DD

ꢀꢇꢃ

ꢀꢎꢃ

ꢀꢅꢃ

ꢀꢃꢃ

ꢍꢃ

ꢌꢄꢌ 6

ꢌꢄꢇ 6

ꢇꢃ

ꢎꢃ

ꢅꢃ

ꢃ

nꢎꢁ

#

ꢅꢁ

#

ꢍꢁ

#

ꢀꢃꢁ #

AIꢀꢐꢅꢍꢀ

4EMPERATURE ꢈ #ꢉ

40/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

Figure 15. Typical current consumption in Stop mode with regulator in Low-power mode versus

temperature at V = 3.3 V and 3.6 V

DD

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DD

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Typical current consumption

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V or V (no load)

DD SS

All peripherals are disabled except if it is explicitly mentioned

When the peripherals are enabled f = f , f = f

, f

= f

PCLK2

/2

PCLK1

HCLK PCLK2

HCLK ADCCLK

The parameters given in Table 16 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Doc ID 16455 Rev 2

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Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 16. Typical current consumption in Run mode, code with data processing

running from Flash

Typical values⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

Allperipherals All peripherals

enabled⁽²⁾

disabled

24 MHz

16 MHz

8 MHz

15.4

11.2

6.2

9

6.50

3.9

2.5

1.8

1.35

1.2

1

Running on high-speed

external clock with an

8 MHz crystal⁽³⁾

4 MHz

3.75

2.3

2 MHz

1 MHz

1.65

1.3

500 kHz

125 kHz

24 MHz

16 MHz

8 MHz

Supply

1.1

I_DD

current in

mA

15

8.4

6.1

3.4

1.9

1.15

0.8

0.6

0.43

Run mode

10.3

5.5

4 MHz

3.1

Running on high-speed

internal RC (HSI)

2 MHz

1.7

1 MHz

1

500 kHz

125 kHz

0.75

0.5

1. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In

applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. AHB prescaler used to reduce the frequency (when f_HCLK> 8 MHz).

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STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

Table 17. Typical current consumption in Sleep mode, code running from Flash or

RAM

Typical values⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

Allperipherals Allperipherals

enabled⁽²⁾

disabled

24 MHz

16 MHz

8 MHz

9.8

7

2.6

2

3.8

2.5

1.7

1.35

1.1

1

1.3

1.2

1.1

1

Running on high-speed

external clock with an

8 MHz crystal⁽³⁾

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

24 MHz

16 MHz

8 MHz

1

Supply

0.95

2

current in

Sleep

I_DD

mA

9.6

6.8

3.2

1.9

1.1

0.75

0.56

0.43

mode

1.4

0.7

0.55

0.46

0.41

0.39

0.37

4 MHz

Running on high-speed

internal RC (HSI)

2 MHz

1 MHz

500 kHz

125 kHz

1. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In

applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. AHB prescaler used to reduce the frequency (when f_HCLK> 8 MHz).

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed

under the following conditions:

●

all I/O pins are in input mode with a static value at V or V (no load)

DD SS

all peripherals are disabled unless otherwise mentioned

the given value is calculated by measuring the current consumption

–

with all peripherals clocked off

with only one peripheral clocked on

●

ambient operating temperature and V supply voltage conditions summarized in

DD

Table 5.

Doc ID 16455 Rev 2

43/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 18. Peripheral current consumption

Peripheral

Typical consumption at 25 °C⁽¹⁾

Unit

TIM2

0.52

0.46

0.5

TIM3

TIM4

TIM6

0.125

0.19

0.5⁽²⁾

0.13

0.2

TIM7

DAC

APB1

WWDG

SPI2

USART2

USART3

I2C1

0.38

0.32

0.27

0.28

0.16

0.25

0.12

0.18

0.15

0.12

0.27

0.63

0.33

0.26

0.25

I2C2

HDMI CEC

GPIO A

GPIO B

GPIO C

GPIO D

GPIO E

ADC1⁽³⁾

SPI1

mA

APB2

USART1

TIM1

TIM15

TIM16

TIM17

1. f_HCLK= f_APB1= f_APB2= 24 MHz, default prescaler value for each peripheral.

2. Specific conditions for DAC: EN1 bit in DAC_CR register set to 1.

3. Specific conditions for ADC: f_HCLK= 24 MHz, f_APB1= f_APB2= f_HCLK, f_ADCCLK= f_APB2/2, ADON bit in the

ADC_CR2 register is set to 1.

5.3.6

External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Table 19 result from tests performed using an high-speed

external clock source, and under the ambient temperature and supply voltage conditions

summarized in Table 8.

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Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 19. High-speed external user clock characteristics

Electrical characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency⁽¹⁾

f_{HSE_ext}

1

8

24

MHz

V_HSEH

V_HSEL

t_w(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

0.7V_DD

V_SS

V_DD

V

0.3V_DD

OSC_IN high or low time⁽¹⁾

OSC_IN rise or fall time⁽¹⁾

16

45

t_w(HSE)

ns

t_r(HSE)

t_f(HSE)

20

C_in(HSE)OSC_IN input capacitance⁽¹⁾

5

pF

%

DuCy_(HSE)Duty cycle

55

1

I_L

OSC_IN Input leakage current

V_SS V_IN V_DD

µA

1. Guaranteed by design, not tested in production.

Low-speed external user clock generated from an external source

The characteristics given in Table 20 result from tests performed using an low-speed

external clock source, and under the ambient temperature and supply voltage conditions

summarized in Table 8.

Table 20. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency⁽¹⁾

f_{LSE_ext}

32.768

1000

kHz

OSC32_IN input pin high level

voltage

V_LSEH

V_LSEL

0.7V_DD

V_SS

V_DD

V

OSC32_IN input pin low level

voltage

0.3V_DD

t_w(LSE)

OSC32_IN high or low time⁽¹⁾

OSC32_IN rise or fall time⁽¹⁾

450

ns

t_r(LSE)

t_f(LSE)

50

C_in(LSE)OSC32_IN input capacitance⁽¹⁾

5

pF

%

DuCy_(LSE)Duty cycle

30

70

1

I_L

OSC32_IN Input leakage current V_SS V_IN V_DD

µA

1. Guaranteed by design, not tested in production.

Doc ID 16455 Rev 2

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Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Figure 17. High-speed external clock source AC timing diagram

V

HSEH

90%

10%

V

HSEL

t

W(HSE)

t

W(HSE)

r(HSE)

f(HSE)

T

HSE

f

HSE_ext

External

clock source

I

L

OSC _IN

STM32F10xxx

ai14127b

Figure 18. Low-speed external clock source AC timing diagram

V

LSEH

90%

10%

V

LSEL

t

W(LSE)

t

W(LSE)

r(LSE)

f(LSE)

T

LSE

f

LSE_ext

External

clock source

I

L

OSC32_IN

STM32F10xxx

ai14140c

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 21. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

46/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 21. HSE 4-24 MHz oscillator characteristics

Electrical characteristics

(1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_{OSC_IN}Oscillator frequency

4

8

24

MHz

R_F

Feedback resistor

200

k

Recommended load capacitance

versus equivalent serial

C_L1

R_S= 30

_DD= 3.3 V

30

pF

(3)

C_L2

resistance of the crystal (R_S)⁽⁴⁾

V

i₂

HSE driving current

V_IN= V_SSwith 30 pF

load

1

mA

g_m

Oscillator transconductance

Startup time

Startup

25

mA/V

ms

t_SU(HSE)

V_DDis stabilized

2

(5)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.),

designed for high-frequency applications, and selected to match the requirements of the crystal or

resonator. C_L1and C_L2,are usually the same size. The crystal manufacturer typically specifies a load

capacitance which is the series combination of C_L1and C_L2. PCB and MCU pin capacitance must be

included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

_L1and C_L2

C

.

4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a

humid environment, due to the induced leakage and the bias condition change. However, it is

recommended to take this point into account if the MCU is used in tough humidity conditions.

5. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

Figure 19. Typical application with an 8 MHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC_IN

HSE

Bias

controlled

gain

8 MHz

resonator

R

F

STM32F10xxx

OSC_OUT

(1)

R

EXT

C

L2

ai14128b

1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 22. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

Doc ID 16455 Rev 2

47/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Note:

For C and C it is recommended to use high-quality ceramic capacitors in the 5 pF to

L1

L2

15 pF range selected to match the requirements of the crystal or resonator. C and C are

L1

L2,

usually the same size. The crystal manufacturer typically specifies a load capacitance which

is the series combination of C and C .

L1

L2

Load capacitance C has the following formula: C = C x C / (C + C ) + C where

L

L1

L2

L1

L2

stray

C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

between 2 pF and 7 pF.

Caution:

To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended

L1

L2

to use a resonator with a load capacitance C  7 pF. Never use a resonator with a load

L

capacitance of 12.5 pF.

Example: if you choose a resonator with a load capacitance of C = 6 pF, and C

= 2 pF,

L

stray

then C = C = 8 pF.

L1

L2

(1)

Table 22. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Feedback resistor

Conditions

Min

Typ

Max

Unit

R_F

5

M

Recommended load capacitance

versus equivalent serial

C_L1

R_S= 30 K

15

pF

µA

(2)

C_L2

resistance of the crystal (R_S)⁽³⁾

V_DD= 3.3 V

V_IN= V_SS

I₂

LSE driving current

1.4

g_m

Oscillator transconductance

Startup time

5

µA/V

s

(4)

t_SU(LSE)

V_DDis stabilized

3

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs above the table.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with

small R_Svalue for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details

4. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary

significantly with the crystal manufacturer

Figure 20. Typical application with a 32.768 kHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC32_IN

LSE

Bias

controlled

gain

32.768 KHz

resonator

R

F

STM32F10xxx

OSC32_OUT

C

L2

ai14129b

48/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

5.3.7

Internal clock source characteristics

The parameters given in Table 23 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

High-speed internal (HSI) RC oscillator

(1)(2)

Table 23. HSI oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_HSI

Frequency

8

MHz

%

T_A= –40 to 105 °C

T_A= –10 to 85 °C

T_A= 0 to 70 °C

T_A= 25 °C

–2.7

–2

3

2.5

1

%

ACC_HSIAccuracy of HSI oscillator

–2

%

–0.7

1

%

t_su(HSI)HSI oscillator startup time

2

µs

µA

I_DD(HSI)HSI oscillator power consumption

1. Guaranteed by design, not tested in production.

80

100

2. V_DD= 3.3 V, T_A= –40 to 105 °C °C unless otherwise specified.

Low-speed internal (LSI) RC oscillator

(1)

Table 24. LSI oscillator characteristics

Symbol

Parameter

Min

Typ

Max

Unit

f_LSI

Frequency

30

40

60

85

kHz

µs

(2)

t_su(LSI)

LSI oscillator startup time

(2)

I_DD(LSI)

LSI oscillator power consumption

0.65

1.2

µA

1.

V_DD= 3 V, T_A= –40 to 105 °C °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

Wakeup time from low-power mode

The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI

RC oscillator. The clock source used to wake up the device depends from the current

operating mode:

●

Stop or Standby mode: the clock source is the RC oscillator

●

Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under the ambient temperature and V supply

DD

voltage conditions summarized in Table 8.

Table 25. Low-power mode wakeup timings

Symbol

Parameter

Wakeup from Sleep mode

Typ

Unit

(1)

1.8

µs

t_WUSLEEP

Doc ID 16455 Rev 2

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Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 25. Low-power mode wakeup timings (continued)

Symbol

Parameter

Typ

Unit

Wakeup from Stop mode (regulator in run mode)

Wakeup from Stop mode (regulator in low-power mode)

Wakeup from Standby mode

3.6

5.4

50

(1)

µs

t_WUSTOP

(1)

t_WUSTDBY

1. The wakeup times are measured from the wakeup event to the point at which the user application code

reads the first instruction.

5.3.8

PLL characteristics

The parameters given in Table 26 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Table 26. PLL characteristics

Value

Symbol

Parameter

Unit

Min⁽¹⁾

Typ

Max⁽¹⁾

PLL input clock⁽²⁾

1

8.0

24

60

MHz

%

f_{PLL_IN}

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

40

16

f_{PLL_OUT}

t_LOCK

24

MHz

µs

200

300

Jitter

Cycle-to-cycle jitter

ps

1. Based on device characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

the range defined by f_{PLL_OUT}

.

50/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

5.3.9

Memory characteristics

Flash memory

The characteristics are given at T = –40 to 105 °C unless otherwise specified.

A

Table 27. Flash memory characteristics

Symbol

Parameter

Conditions

Min⁽¹⁾Typ Max⁽¹⁾Unit

t_prog

t_ERASE

t_ME

16-bit programming time

Page (1 KB) erase time

Mass erase time

T_A–40 to +105 °C

T_A–40 to +105 °C

40

20

52.5

70

40

µs

ms

Read mode

f_HCLK= 24 MHz, V_DD= 3.3 V

20

5

mA

Write / Erase modes

f_HCLK= 24 MHz, V_DD= 3.3 V

I_DD

Supply current

Power-down mode / Halt,

V_DD= 3.0 to 3.6 V

50

µA

V

V_prog

Programming voltage

2

3.6

1. Guaranteed by design, not tested in production.

Table 28. Flash memory endurance and data retention

Value

Symbol

Parameter

Conditions

Unit

Min⁽¹⁾Typ Max

T_A= –40 to +85 °C (6 suffix versions)

T_A= –40 to +105 °C (7 suffix versions)

1 kcycle⁽²⁾at T_A= 85 °C

N_END

Endurance

kcycles

Years

10

30

10

20

t_RET

Data retention 1 kcycle⁽²⁾at T_A= 105 °C

10 kcycles⁽²⁾at T_A= 55 °C

1. Based on characterization not tested in production.

2. Cycling performed over the whole temperature range.

Doc ID 16455 Rev 2

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Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

5.3.10

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the

device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

●

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

●

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 29. They are based on the EMS levels and classes

defined in application note AN1709.

Table 29. EMS characteristics

Symbol

Parameter

Conditions

Level/Class

V_DD3.3 V, T_A+25 °C,

Voltage limits to be applied on any I/O pin to f_HCLK 24 MHz, LQFP100

V_FESD

2B

induce a functional disturbance

package, conforms to

IEC 61000-4-2

V_DD3.3 V, T_A+25 °C,

f_HCLK24 MHz, LQFP100

package, conforms to

IEC 61000-4-4

Fast transient voltage burst limits to be

applied through 100 pF on V_DDand V_SSpins

to induce a functional disturbance

V_EFTB

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre

qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

●

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second. To complete these trials, ESD stress can be applied directly on the device, over the

range of specification values. When unexpected behavior is detected, the software can be

hardened to prevent unrecoverable errors occurring (see application note AN1015).

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Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electromagnetic Interference (EMI)

Electrical characteristics

The electromagnetic field emitted by the device is monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 30. EMI characteristics

Max vs. [f_HSE/f_HCLK

]

Monitored

frequency band

Symbol Parameter

Conditions

Unit

8/24 MHz

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1GHz

SAE EMI Level

9

17

16

4

V_DD3.3 V, T_A25°C,

LQFP100 package

compliant with

dBµV

-

S_EMI

Peak level

IEC 61967-2

5.3.11

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 31. ESD absolute maximum ratings

Maximum

Symbol

Ratings

Conditions

Class

Unit

value⁽¹⁾

Electrostatic discharge

voltage (human body model) conforming to JESD22-A114

T_A+25 °C

V_ESD(HBM)

2

II

TBD

V

Electrostatic discharge T_A+25 °C

voltage (charge device model) conforming to JESD22-C101

V_ESD(CDM)

TBD

1. Based on characterization results, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

●

A supply overvoltage is applied to each power supply pin

●

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD78 IC latch-up standard.

Table 32. Electrical sensitivities

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T_A+105 °C conforming to JESD78

TBD

Doc ID 16455 Rev 2

53/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

5.3.12

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 33 are derived from tests

performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL

compliant.

Table 33. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

0.28 (V_DD–2)

+0.8

Standard I/O input low level voltage

–0.5

V_IL

0.32 (V_DD–2)

+0.75

I/O FT⁽¹⁾input low level voltage

Standard I/O input high level voltage

I/O FT⁽¹⁾input high level voltage

–0.5

V

0.41 (V_DD–2)

+1.3

V_DD+0.5

V_IH

V_hys

I_lkg

0.42 (V_DD–2)

+1

5.5

Standard I/O Schmitt trigger voltage

hysteresis⁽²⁾

200

mV

I/O FT Schmitt trigger voltage

hysteresis⁽²⁾

(3)

5% V_DD

V_SS V_IN V_DD

Standard I/Os

1

Input leakage current⁽⁴⁾

µA

V_IN= 5 V

I/O FT

3

R_PU

R_PD

C_IO

Weak pull-up equivalent resistor⁽⁵⁾

V_INV_SS

V_INV_DD

30

40

5

50

k

pF

Weak pull-down equivalent

resistor⁽⁵⁾

I/O pin capacitance

1. FT = 5V tolerant. To sustain a voltage higher than V_DD+0.5 the internal pull-up/pull-down resistors must be disabled.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order).

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 21 and Figure 22 for standard I/Os, and

in Figure 23 and Figure 24 for 5 V tolerant I/Os.

54/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Figure 21. Standard I/O input characteristics - CMOS port

Electrical characteristics

6

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Doc ID 16455 Rev 2

55/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Figure 23. 5 V tolerant I/O input characteristics - CMOS port

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Figure 24. 5 V tolerant I/O input characteristics - TTL port

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink

+20 mA (with a relaxed V ).

OL

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 5.2:

●

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

I

(see Table 6).

VDD

●

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

I

(see Table 6).

VSS

56/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Output voltage levels

Electrical characteristics

Unless otherwise specified, the parameters given in Table 34 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 8. All I/Os are CMOS and TTL compliant.

Table 34. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max Unit

Output Low level voltage for an I/O pin

when 8 pins are sunk at the same time

(1)

0.4

V

V_OL

TTL port,

I_IO= +8 mA,

2.7 V < V_DD< 3.6 V

Output High level voltage for an I/O pin

when 8 pins are sourced at the same time

(2)

V_DD–0.4

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

(1)

0.4

V

V_OL

CMOS port

I_IO= +8 mA

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

(2)

2.7 V < V_DD< 3.6 V

2.4

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

(1)

1.3

V

V_OL

I

_IO= +20 mA⁽³⁾

2.7 V < V_DD< 3.6 V

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

(2)

V_DD–1.3

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

(1)

0.4

V

V_OL

I_IO= +6 mA⁽³⁾

2 V < V_DD< 2.7 V

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

(2)

V_DD–0.4

V_OH

1. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 6

and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in

Table 6 and the sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

3. Based on characterization data, not tested in production.

Doc ID 16455 Rev 2

57/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 25 and

Table 35, respectively.

Unless otherwise specified, the parameters given in Table 35 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 8.

(1)

Table 35. I/O AC characteristics

MODEx

[1:0] bit Symbol

Parameter

Conditions

Max Unit

value⁽¹⁾

f_max(IO)outMaximum frequency⁽²⁾

C_L= 50 pF, V_DD= 2 V to 3.6 V

2

MHz

ns

Output high to low level fall

t_f(IO)out

time

125⁽³⁾

10

01

C_L= 50 pF, V_DD= 2 V to 3.6 V

Output low to high level rise

t_r(IO)out

time

125⁽³⁾

10

f_max(IO)outMaximum frequency⁽²⁾

MHz

ns

Output high to low level fall

t_f(IO)out

time

25⁽³⁾

Output low to high level rise

t_r(IO)out

time

25⁽³⁾

24

F_max(IO)outMaximum frequency⁽²⁾

MHz

C_L= 30 pF, V_DD= 2.7 V to 3.6 V 5⁽³⁾

C_L= 50 pF, V_DD= 2.7 V to 3.6 V 8⁽³⁾

Output high to low level fall

t_f(IO)out

time

11

C_L= 50 pF, V_DD= 2 V to 2.7 V

12⁽³⁾

ns

C_L= 30 pF, V_DD= 2.7 V to 3.6 V 5⁽³⁾

C_L= 50 pF, V_DD= 2.7 V to 3.6 V 8⁽³⁾

Output low to high level rise

t_r(IO)out

time

C_L= 50 pF, V_DD= 2 V to 2.7 V

12⁽³⁾

Pulse width of external

t_EXTIpwsignals detected by the

EXTI controller

-

10

ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a

description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 25.

3. Guaranteed by design, not tested in production.

58/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Figure 25. I/O AC characteristics definition

Electrical characteristics

90%

10 %

50%

90%

10%

t

EXTERNAL

OUTPUT

ON 50pF

t

r(IO)out

T

Maximum frequency is achieved if (t + t ) 2/3)T and if the duty cycle is (45-55%)

r

f

when loaded by 50pF

ai14131

5.3.13

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, R (see Table 33).

PU

Unless otherwise specified, the parameters given in Table 36 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 8.

Table 36. NRST pin characteristics

Symbol

Parameter

Conditions Min

Typ

Max

Unit

(1)

V_IL(NRST)

NRST Input low level voltage

NRST Input high level voltage

–0.5

2

0.8

V

(1)

V_IH(NRST)

V_hys(NRST)

R_PU

V_DD+0.5

NRST Schmitt trigger voltage

hysteresis

200

40

mV

Weak pull-up equivalent resistor⁽²⁾V_INV_SS

30

50

k

ns

(1)

V_F(NRST)

NRST Input filtered pulse

100

(1)

V_NF(NRST)

NRST Input not filtered pulse

300

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance must be minimum (~10% order).

Figure 26. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 36. Otherwise the reset will not be taken into account by the device.

Doc ID 16455 Rev 2

59/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

5.3.14

TIMx characteristics

The parameters given in Table 37 are guaranteed by design.

Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 37. TIMx characteristics

Conditions⁽¹⁾

f_TIMxCLK= 24 MHz

Symbol

Parameter

Min

Max

Unit

1

41.7

0

t_TIMxCLK

ns

t_res(TIM)

Timer resolution time

f_TIMxCLK/2

12

MHz

bit

Timer external clock

frequency on CHx⁽²⁾

f_EXT

0

Res_TIM

Timer resolution

16

16-bit counter clock period

when the internal clock is

selected

1

65536

t_TIMxCLK

t_COUNTER

f_TIMxCLK= 24 MHz

2730

µs

65536 × 65536 t_TIMxCLK

178

t_{MAX_COUNT}

Maximum possible count

s

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM15, TIM16 and TIM17 timers.

2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3 and TIM4, to the CH1 to CH2

for TIM15, and to CH1 for TIM16 and TIM17.

5.3.15

Communications interfaces

I²C interface characteristics

Unless otherwise specified, the parameters given in Table 38 are derived from tests

performed under the ambient temperature, f

frequency and V supply voltage

PCLK1

DD

conditions summarized in Table 8.

2

The STM32F100xx value line I C interface meets the requirements of the standard I C

communication protocol with the following restrictions: t

he I/O pins SDA and SCL are

mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected

between the I/O pin and V is disabled, but is still present.

DD

2

The I C characteristics are described in Table 38. Refer also to

Section 5.3.12: I/O port

for more details on the input/output alternate function characteristics (SDA

characteristics

and SCL)

.

60/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

2

Table 38. I C characteristics

Standard mode I²C⁽¹⁾Fast mode I²C⁽¹⁾⁽²⁾

Symbol

Parameter

Unit

Min

Max

Min

Max

t_w(SCLL)SCL clock low time

t_w(SCLH)SCL clock high time

t_su(SDA)SDA setup time

4.7

4.0

1.3

0.6

100

0⁽⁴⁾

µs

250

0⁽³⁾

t_h(SDA)

SDA data hold time

900⁽³⁾

300

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

1000

300

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

Start condition hold time

300

t_h(STA)

4.0

4.7

4.0

4.7

0.6

1.3

µs

Repeated Start condition setup

time

t_su(STA)

t_su(STO)Stop condition setup time

µs

pF

Stop to Start condition time (bus

t_w(STO:STA)

free)

C_b

Capacitive load for each bus line

400

Guaranteed by design, not tested in production.

1.

2. f_PCLK1must be higher than 2 MHz to achieve standard mode I²C frequencies. It must be higher than

4 MHz to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz

maximum I2C fast mode clock.

The maximum hold time of the Start condition only has to be met if the interface does not stretch the low

period of SCL signal.

3.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

4.

Doc ID 16455 Rev 2

61/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

2

(1)

Figure 27. I C bus AC waveforms and measurement circuit

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1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

(1)(2)

Table 39. SCL frequency (f

f_SCL(kHz)

= 24 MHz, V_DD= 3.3 V)

PCLK1

I2C_CCR value

R_P= 4.7 k

400

300

200

100

50

0x8011

0x8016

0x8021

0x0064

0x00C8

0x01F4

20

1. R_P= External pull-up resistance, f_SCL= I²C speed,

2. For speeds around 400 kHz, the tolerance on the achieved speed is of 2%. For other speed ranges, the

tolerance on the achieved speed 1%. These variations depend on the accuracy of the external

components used to design the application.

62/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

SPI interface characteristics

Electrical characteristics

Unless otherwise specified, the parameters given in Table 40 are derived from tests

performed under the ambient temperature, f

frequency and V supply voltage

PCLKx

DD

conditions summarized in Table 8.

Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO).

(1)

Table 40. SPI characteristics

Symbol

Parameter

Conditions

Master mode

Min

Max

Unit

12

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

Slave mode

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

8

ns

%

SPI slave input clock

duty cycle

DuCy(SCK)

Slave mode

30

70

(2)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

4t_PCLK

2t_PCLK

(2)

t_h(NSS)

(2)

t_w(SCKH)

t_w(SCKL)

Master mode, f_PCLK= 24 MHz,

presc = 4

SCK high and low time

Data input setup time

50

60

(2)

Master mode

Slave mode

Master mode

Slave mode

5

4

0

2

t_su(MI)

t_su(SI)

(2)

t_h(MI)

Data input hold time

(2)

t_h(SI)

ns

(2)(3)

t_a(SO)

Data output access time Slave mode, f_PCLK= 24 MHz

Data output disable time Slave mode

3t_PCLK

10

(2)(4)

t_dis(SO)

(2)(1)

t_v(SO)

Data output valid time

Slave mode (after enable edge)

25

Master mode (after enable

edge)

(2)(1)

t_v(MO)

5

(2)

t_h(SO)

Slave mode (after enable edge)

15

2

Data output hold time

Master mode (after enable

edge)

(2)

t_h(MO)

1. Remapped SPI1 characteristics to be determined.

2. Based on characterization, not tested in production.

3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

Doc ID 16455 Rev 2

63/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Figure 28. SPI timing diagram - slave mode and CPHA = 0

NSS input

t

c(SCK)

t

h(NSS)

SU(NSS)

CPHA=0

CPOL=0

t

w(SCKH)

CPHA=0

CPOL=1

t

w(SCKL)

t

dis(SO)

r(SCK)

f(SCK)

v(SO)

a(SO)

h(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134c

(1)

Figure 29. SPI timing diagram - slave mode and CPHA = 1

NSS input

t

SU(NSS)

c(SCK)

h(NSS)

CPHA=1

CPOL=0

t

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

64/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

(1)

Figure 30. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

r(SCK)

f(SCK)

t

su(MI)

t

w(SCKL)

MISO

INPUT

MSBIN

BIT6 IN

LSB IN

t

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTUT

t

v(MO)

h(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

HDMI consumer electronics control (CEC)

Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate

function characteristics.

5.3.16

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 41 are derived from tests

performed under the ambient temperature, f

frequency and V

supply voltage

PCLK2

DDA

conditions summarized in Table 8.

Note:

It is recommended to perform a calibration after each power-up.

Doc ID 16455 Rev 2

65/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 41. ADC characteristics

Symbol

Parameter

Power supply

Conditions

Min

Typ

Max

Unit

V_DDA

2.4

3.6

V

V_REF+Positive reference voltage

V_DDA

Current on the V_REFinput

I_VREF

160⁽¹⁾220⁽¹⁾

µA

f_ADC

ADC clock frequency

Sampling rate

0.6

10

1

MHz

(2)

0.05

f_S

f_ADC= 12 MHz

823

17

kHz

(2)

External trigger frequency

Conversion voltage range

f_TRIG

1/f_ADC

0 (V_SSAtied to

ground)

(3)

V_REF+

V

V_AIN

See Equation 1 and

Table 42 for details

(2)

R_AIN

External input impedance

Sampling switch resistance

50

1

k

pF

R_ADC

Internal sample and hold

capacitor

(2)

8

C_ADC

f

_ADC= 12 MHz

5.9

83

µs

1/f_ADC

µs

(2)

Calibration time

t_CAL

f_ADC= 12 MHz

0.214

3⁽⁴⁾

Injection trigger conversion

latency

(2)

t_lat

1/f_ADC

µs

0.143

2⁽⁴⁾

Regular trigger conversion

latency

(2)

t_latr

1/f_ADC

µs

0.125

1.5

17.1

239.5

1

(2)

Sampling time

Power-up time

f_ADC= 12 MHz

t_S

1/f_ADC

µs

(2)

t_STAB

0

f_ADC= 12 MHz

1.17

21

µs

Total conversion time

(including sampling time)

(2)

t_CONV

14 to 252 (t_Sfor sampling +12.5 for

successive approximation)

1/f_ADC

1. Based on characterization results, not tested in production.

2. Guaranteed by design, not tested in production.

3. In devices delivered in LQFP packages, V_REF+is internally connected to V_DDAand V_REF-is internally connected to V_SSA

Devices that come in the TFBGA64 package have a V_REF+pin but no V_REF-pin (V_REF-is internally connected to V_SSA),

see Table 4: STM32F100xx pin definitions and Figure 6.

.

4. For external triggers, a delay of 1/f_PCLK2must be added to the latency specified in Table 41.

Equation 1: R

max formula:

AIN

T_S

R_AIN ------------------------------------------------------------- – R_ADC

f_ADC C_ADC ln2^{N + 2}

66/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

The above formula (Equation 1) is used to determine the maximum external impedance allowed for an

error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

(1)

Table 42.

R

max for f

= 12 MHz

AIN

ADC

T_s(cycles)

t_S(µs)

R_AINmax (k)

1.5

0.125

0.625

1.125

2.375

3.45

0.4

7.5

5.9

13.5

28.5

41.5

55.5

71.5

239.5

11.4

25.2

37.2

50

4.625

5.96

NA

20

NA

1. Guaranteed by design, not tested in production.

(1)(2)

Table 43. ADC accuracy - limited test conditions

Symbol

Parameter

Test conditions

Typ

Max

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

1.3

1

2

f_PCLK2= 24 MHz,

f_ADC= 12 MHz, R_AIN< 10 k,

V_DDA= 3 V to 3.6 V

T_A= 25 °C

1.5

1

Gain error

0.5

0.7

0.8

LSB

Differential linearity error

Integral linearity error

Measurements made after

ADC calibration

1.5

1. ADC DC accuracy values are measured after internal calibration.

2. Based on characterization, not tested in production.

(1) (2)

Table 44. ADC accuracy

Symbol

Parameter

Test conditions

Typ

Max⁽³⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

2

5

2.5

3

f

_PCLK2= 24 MHz,

1.5

1

f_ADC= 12 MHz, R_AIN< 10 k,

V_DDA= 2.4 V to 3.6 V

Gain error

LSB

Measurements made after

ADC calibration

Differential linearity error

Integral linearity error

2

1.5

3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V_DD, frequency, V_REFand temperature ranges.

3. Based on characterization, not tested in production.

Note:

ADC accuracy vs. negative injection current: Injecting a negative current on any of the

standard (non-robust) analog input pins should be avoided as this significantly reduces the

accuracy of the conversion being performed on another analog input. It is recommended to

add a Schottky diode (pin to ground) to standard analog pins which may potentially inject

Doc ID 16455 Rev 2

67/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

negative currents.

Any positive injection current within the limits specified for I

and I

in

INJ(PIN)

Section 5.3.12 does not affect the ADC accuracy.

Figure 31. ADC accuracy characteristics

V

DDA

REF+

[1LSB

=

(or

depending on package)]

IDEAL

4096

E_G

(1) Example of an actual transfer curve

(2) The ideal transfer curve

4095

4094

4093

(3) End point correlation line

(2)

E_T=Total Unadjusted Error: maximum deviation

E_T

between the actual and the ideal transfer curves.

(3)

7

6

5

4

3

2

1

E_O=Offset Error: deviation between the first actual

transition and the first ideal one.

(1)

E_G=Gain Error: deviation between the last ideal

transition and the last actual one.

E_O

E_L

E_D=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

E_L=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

E_D

1 LSB_IDEAL

0

1

2

3

4

5

6

7

4093 4094 4095 4096

V_DDA

V_SSA

ai14395b

Figure 32. Typical connection diagram using the ADC

STM32F10xxx

V

DD

Sample and hold ADC

V

0.6 V

T

converter

(1)

C

(1)

R

AIN

ADC

AINx

12-bit

converter

V

T

V

AIN

0.6 V

C

(1)

ADC

parasitic

I

1 µA

L

ai14139d

1. Refer to Table 41 for the values of R_AIN, R_ADCand C_ADC

.

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high C_parasiticvalue will downgrade conversion accuracy. To remedy

this, f_ADCshould be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 33 or Figure 34,

depending on whether V

is connected to V

or not. The 10 nF capacitors should be

REF+

DDA

ceramic (good quality). They should be placed them as close as possible to the chip.

68/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Figure 33. Power supply and reference decoupling (V

Electrical characteristics

not connected to V

)

DDA

REF+

STM32F10xxx

V

REF+

DDA

1 µF // 10 nF

V

1 µF // 10 nF

/V

SSA REF-

ai14380b

1. V_REF+is available on 100-pin packages and on TFBGA64 packages. V_REF-is available on 100-pin

packages only.

Figure 34. Power supply and reference decoupling (V

connected to V

)

DDA

REF+

STM32F10xxx

V

/V

REF+ DDA

1 µF // 10 nF

V

/V

REF– SSA

ai14381b

1. V_REF+and V_REF-inputs are available only on 100-pin packages.

Doc ID 16455 Rev 2

69/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

5.3.17

DAC electrical specifications

Table 45. DAC characteristics

Symbol

Parameter

Min Typ Max⁽¹⁾Unit

Comments

V_DDA

Analog supply voltage

2.4

3.6

V

V_REF+must always be below

V_DDA

V_REF+

Reference supply voltage

3.6

0

V_SSA

Ground

0

5

V

(2)

R_LOAD

Resistive load with buffer ON

k

When the buffer is OFF, the

Minimum resistive load between

DAC_OUT and V_SSto have a

1% accuracy is 1.5 M

(1)

R_O

Impedance output with buffer OFF

Capacitive load

15

50

k

Maximum capacitive load at

DAC_OUT pin (when the buffer

is ON).

(1)

C_LOAD

pF

V

It gives the maximum output

excursion of the DAC.

DAC_OUT Lower DAC_OUT voltage with buffer

min⁽¹⁾

ON

0.2

It corresponds to 12-bit input

code (0x0E0) to (0xF1C) at

V_REF+= 3.6 V and (0x155) and

(0xEAB) at V_REF+= 2.4 V

DAC_OUT Higher DAC_OUT voltage with buffer

max⁽¹⁾

ON

V_DDA

0.2

–

V

DAC_OUT Lower DAC_OUT voltage with buffer

min⁽¹⁾

OFF

0.5

mV

V

It gives the maximum output

excursion of the DAC.

DAC_OUT Higher DAC_OUT voltage with buffer

V_REF+

– 1LSB

max⁽¹⁾

OFF

With no load, worst code

(0xF1C) at V_REF+= 3.6 V in

terms of DC consumption on the

inputs

DAC DC current consumption in

quiescent mode (Standby mode)

I_DDVREF+

220

380

480

µA

With no load, middle code

(0x800) on the inputs

DAC DC current consumption in

quiescent mode (Standby mode)

With no load, worst code

(0xF1C) at V_REF+= 3.6 V in

terms of DC consumption on the

inputs

I_DDA

Given for the DAC in 10-bit

configuration

0.5

LSB

Differential non linearity Difference

between two consecutive code-1LSB)

DNL⁽³⁾

Given for the DAC in 12-bit

configuration

2

1

LSB

Integral non linearity (difference

between measured value at Code i

and the value at Code i on a line

drawn between Code 0 and last Code

1023)

Given for the DAC in 10-bit

configuration

INL⁽³⁾

Given for the DAC in 12-bit

configuration

4

LSB

70/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 45. DAC characteristics (continued)

Electrical characteristics

Comments

Symbol

Parameter

Min Typ Max⁽¹⁾Unit

Given for the DAC in 12-bit

configuration

10

3

mV

LSB

%

Offset error

Given for the DAC in 10-bit at

V_REF+= 3.6 V

(difference between measured value

at Code (0x800) and the ideal value =

V_REF+/2)

Offset⁽³⁾

Given for the DAC in 12-bit at

12

0.5

V_REF+= 3.6 V

Gain

Given for the DAC in 12bit

configuration

Gain error

error⁽³⁾

Settling time (full scale: for a 10-bit

input code transition between the

lowest and the highest input codes

when DAC_OUT reaches final value

1LSB

(

t_SETTLING

3

4

1

µs

C_LOAD 50 pF, R_LOAD 5 k

3)

Max frequency for a correct

DAC_OUT change when small

variation in the input code (from code i

to i+1LSB)

Update

rate⁽³⁾

MS/s C_LOAD 50 pF, R_LOAD 5 k

C_LOAD 50 pF, R_LOAD 5 k

Wakeup time from off state (Setting

the ENx bit in the DAC Control

register)

(3)

t_WAKEUP

6.5

10

µs

input code between lowest and

highest possible ones.

Power supply rejection ratio (to V_DDA

(static DC measurement

)

PSRR+ ⁽¹⁾

–67

–40

dB

No R_LOAD, C_LOAD= 50 pF

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Guaranteed by characterization, not tested in production.

Figure 35. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

R

C

LOAD

DACx_OUT

12-bit

digital to

analog

converter

LOAD

ai17157

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

5.3.18

Temperature sensor characteristics

Doc ID 16455 Rev 2

71/84

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Table 46. TS characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(1)

T_L

V_SENSElinearity with temperature

Average slope

1

4.3

2

4.6

°C

mV/°C

V

Avg_Slope⁽¹⁾

4.0

1.32

4

(1)

V₂₅

Voltage at 25°C

1.41

1.50

10

(2)

t_START

Startup time

µs

(3)(2)

T_{S_temp}

ADC sampling time when reading the temperature

17.1

µs

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

72/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Package characteristics

6

Package characteristics

6.1

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Doc ID 16455 Rev 2

73/84

Package characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

(1)(2)

Figure 36. LQFP100, 14 x 14 mm, 100-pin low-profile Figure 37. Recommended footprint

(1)

quad flat package outline

0.25 mm

0.10 inch

GAGE PLANE

75

51

k

D

L

76

50

D1

0.5

L1

D3

51

75

C

0.3

76

50

16.7 14.3

b

E3 E1

E

100

26

1.2

1

25

100

26

12.3

16.7

Pin 1

1

25

ccc

C

identification

e

A1

ai14906

A2

A

SEATING PLANE

C

1L_ME

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 47. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.2

0.063

0.05

1.35

0.002

0.0531

0.0067

0.0035

0.622

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

1.40

0.22

0.0551

0.0087

0.17

c

0.09

D

15.80

13.80

16.00

14.00

12.00

16.00

14.00

12.00

0.50

16.2

14.2

0.6299

0.5512

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

D1

D3

E

0.5433

15.80

13.80

16.2

14.2

0.622

0.6378

0.5591

E1

E3

e

0.5433

L

0.45

0°

0.60

0.75

7°

0.0177

0.0°

0.0295

7.0°

L1

k

1.00

3.5°

ccc

0.08

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

74/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Package characteristics

Figure 38. LQFP64 – 10 x 10 mm, 64 pin low-profile quad Figure 39. Recommended

(1)

(1)(2)

flat package outline

footprint

D

48

33

ccc

C

D1

0.3

A

A2

D3

49

32

0.5

33

48

32

49

12.7

10.3

b

L1

10.3

E3 E1

E

64

17

1.2

L

A1

K

1

16

64

7.8

17

Pin 1

identification

12.7

1

16

c

5W_ME

ai14909

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 48. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.0630

0.0059

0.0571

0.0106

0.0079

0.05

1.35

0.17

0.09

0.0020

0.0531

0.0067

0.0035

1.40

0.22

0.0551

0.0087

c

D

12.00

10.00

12.00

10.00

0.50

0.4724

0.3937

0.4724

0.3937

0.0197

3.5°

D1

E

E1

e



0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.0177

0.0236

0.0394

0.0295

L1

1.00

Number of pins

N

64

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 16455 Rev 2

75/84

Package characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Figure 40. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline

B

D

D1

A

e

F

A1

H

G

F

E

D

C

B

A

E1

E

e

1

2

3

4

5

6

7

8

Øb (64 balls)

A1 ball pad corner

A3

A4

A2

Seating

plane

C

Bottom view

ME_R8

1. Drawing is not to scale.

Table 49. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package

mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

1.200

0.0472

A1

A2

A3

A4

b

0.150

0.0059

0.785

0.200

0.0309

0.0079

0.600

0.350

5.150

0.0236

0.0138

0.2028

0.250

4.850

0.300

5.000

3.500

5.000

3.500

0.500

0.750

0.080

0.150

0.050

0.0098

0.1909

0.0118

0.1969

0.1378

0.1969

0.1378

0.0197

0.0295

0.0031

0.0059

0.0020

D

D1

E

4.850

5.150

0.1909

0.2028

E1

e

F

ddd

eee

fff

1. Values in inches are converted from mm and rounded to 4 decimal digits.

76/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Package characteristics

Figure 41. Recommended PCB design rules for pads (0.5 mm pitch BGA)

0.5 mm

Pitch

D pad

0.27 mm

0.35 mm typ (depends on

the soldermask registration

tolerance)

Dsm

Solder paste

0.27 mm aperture diameter

Dpad

Dsm

ai15495

1. Non solder mask defined (NSMD) pads are recommended

2. 4 to 6 mils solder paste screen printing process

Doc ID 16455 Rev 2

77/84

Package characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Figure 42. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat Figure 43. Recommended

(1)

(1)(2)

package outline

footprint

Seating plane

C

A

A2

0.50

A1

c

b

1.20

0.25 mm

ccc

C

Gage plane

0.30

36

25

D

37

24

D1

D3

k

0.20

7.30

A1

L

9.70 5.80

25

36

L1

7.30

24

48

13

12

37

1

1.20

5.80

E3

E1

E

9.70

ai14911b

48

13

Pin 1

identification

1

12

5B_ME

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 50. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

9.200

7.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

0.050

1.350

0.170

0.090

8.800

6.800

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

1.400

0.220

0.0551

0.0087

c

D

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

0.3543

0.2756

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

D1

D3

E

8.800

6.800

9.200

7.200

0.3465

0.2677

0.3622

0.2835

E1

E3

e

L

0.450

0°

0.750

7°

0.0177

0°

0.0295

7°

L1

k

ccc

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

78/84

Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Package characteristics

6.2

Thermal characteristics

The maximum chip junction temperature (T max) must never exceed the values given in

J

Table 8: General operating conditions on page 34.

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max x  )

J

A

D

JA

Where:

●

T max is the maximum ambient temperature in C,

A



is the package junction-to-ambient thermal resistance, in C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = (V × I ) + ((V – V ) × I ),

OL OL DD OH OH

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 51. Package thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

LQFP 100 - 14 × 14 mm / 0.5 mm pitch

46

Thermal resistance junction-ambient

LQFP 64 - 10 × 10 mm / 0.5 mm pitch

45

65

55

_JA

°C/W

Thermal resistance junction-ambient

TFBGA64 - 5 × 5 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP 48 - 7 × 7 mm / 0.5 mm pitch

6.2.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

Doc ID 16455 Rev 2

79/84

Package characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

6.2.2

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 52: Ordering information scheme.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F10xxx at maximum dissipation, it is useful

to calculate the exact power consumption and junction temperature to determine which

temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given

application.

Example: high-performance application

Assuming the following application conditions:

Maximum ambient temperature T

= 82 °C (measured according to JESD51-2),

Amax

I

= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output

OL

mode at low level with I = 20 mA, V = 1.3 V

OL

P

= 50 mA × 3.5 V= 175 mW

INTmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

IOmax

This gives: P

= 175 mW and P

= 272 mW

IOmax

INTmax

P

= 175 + 272 = 447 mW

Dmax

Thus: P

= 447 mW

Dmax

Using the values obtained in Table 51 T

is calculated as follows:

Jmax

–

T

For LQFP64, 45 °C/W

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C

Jmax

This is within the range of the suffix 6 version parts (–40 < T < 105 °C).

J

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Table 52: Ordering information scheme).

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient

temperatures with a low dissipation, as long as junction temperature T remains within the

J

specified range.

Assuming the following application conditions:

Maximum ambient temperature T

= 115 °C (measured according to JESD51-2),

Amax

I

= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V

OL

P

= 20 mA × 3.5 V= 70 mW

INTmax

= 20 × 8 mA × 0.4 V = 64 mW

IOmax

This gives: P

= 70 mW and P

= 64 mW:

IOmax

INTmax

P

= 70 + 64 = 134 mW

Dmax

Thus: P

= 134 mW

Dmax

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Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Package characteristics

Using the values obtained in Table 51 T is calculated as follows:

Jmax

–

T

For LQFP100, 46 °C/W

= 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C

Jmax

This is within the range of the suffix 7 version parts (–40 < T < 125 °C).

J

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Table 52: Ordering information scheme).

Figure 44. LQFP100 P max vs. T

D

A

700

600

500

400

300

200

100

0

Suffix 6

Suffix 7

65

75

85

95 105 115 125 135

T_A(°C)

Doc ID 16455 Rev 2

81/84

Ordering information scheme

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

7

Ordering information scheme

Table 52. Ordering information scheme

Example:

STM32 F 100 C

6

T

6

B xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = General-purpose

Device subfamily

100 = value line

Pin count

C = 48 pins

R = 64 pins

V = 100 pins

Flash memory size

4 = 16 Kbytes of Flash memory

6 = 32 Kbytes of Flash memory

8 = 64 Kbytes of Flash memory

B = 128 Kbytes of Flash memory

Package

T = LQFP

H = BGA

Temperature range

6 = Industrial temperature range, –40 to 85 °C

7 = Industrial temperature range, –40 to 105 °C

Internal code

B

Options

xxx = programmed parts

TR = tape and real

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

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Doc ID 16455 Rev 2

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Revision history

8

Revision history

Table 53. Document revision history

Date

Revision

Changes

12-Oct-2009

1

Initial release.

TFBGA64 package added (see Table 49 and Table 40).

Note 5 modified in Table 4: STM32F100xx pin definitions.

I_INJ(PIN)modified in Table 6: Current characteristics. Conditions

removed from Table 25: Low-power mode wakeup timings.

Notes modified in Table 33: I/O static characteristics.

Figure 26: Recommended NRST pin protection modified.

19-Jan-2010

2

Note modified in Table 38: I2C characteristics. Figure 27: I2C bus AC

waveforms and measurement circuit(1) modified.

Table 45: DAC characteristics modified. Figure 35: 12-bit buffered

/non-buffered DAC added.

TIM2, TIM3, TIM4 and TIM15, TIM16 and TIM17 updated.

HDMI-CEC electrical characteristics added.

Values added to:

– Table 12: Maximum current consumption in Run mode, code with

data processing running from Flash

– Table 13: Maximum current consumption in Run mode, code with

data processing running from RAM

– Table 14: STM32F100xxB maximum current consumption in Sleep

mode, code running from Flash or RAM

– Table 15: Typical and maximum current consumptions in Stop and

Standby modes

– Table 18: Peripheral current consumption

– Table 29: EMS characteristics

– Table 30: EMI characteristics

– Table 46: TS characteristics

26-Feb-2010

3

Section 5.3.12: I/O port characteristics modified.

Added figures:

– Figure 12: Maximum current consumption in Run mode versus

frequency (at 3.6 V) - code with data processing running from RAM,

peripherals enabled

– Figure 13: Maximum current consumption in Run mode versus

frequency (at 3.6 V) - code with data processing running from RAM,

peripherals disabled

– Figure 14: Typical current consumption in Stop mode with regulator

in Run mode versus temperature at VDD = 3.3 V and 3.6 V

– Figure 15: Typical current consumption in Stop mode with regulator

in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V

– Figure 16: Typical current consumption in Standby mode versus

temperature at VDD = 3.3 V and 3.6 V

Doc ID 16455 Rev 2

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STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

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Doc ID 16455 Rev 2


型号：	STM32F100R4
厂家：	ST
描述：	Low & medium-density value line, advanced ARM-based 32-bit MCU Low & medium-density value line, advanced ARM-based 32-bit MCU
文件：	总84页 (文件大小：1153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM32F100R4 [STMICROELECTRONICS]

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