STM32F101RC [STMICROELECTRONICS]
High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces; 基于ARM的高密度接入线路的32位MCU，具有256至512 KB的闪存，9个定时器，1个ADC和10个通信接口
| 型号： | STM32F101RC |
| 厂家： | 
ST |
| 描述： | High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces |
| 文件： | 总106页 (文件大小：1388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F101xC STM32F101xD
STM32F101xE
High-density access line, ARM-based 32-bit MCU with 256 to
512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 36 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance
– Single-cycle multiplication and hardware
division
LQFP144
20 × 20 mm
LQFP100
14 × 14 mm
LQFP64
10 × 10 mm
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
■ Memories
– 256 to 512 Kbytes of Flash memory
– up to 48 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND
memories
■ Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
■ Up to 9 timers
– LCD parallel interface, 8080/6800 modes
– Up to four 16-bit timers, each with up to 4
IC/OC/PWM or pulse counters
■ Clock, reset and supply management
– 2 × watchdog timers (Independent and
Window)
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
capability
■ Up to 10 communication interfaces
2
– Up to 2 x I C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– 32 kHz oscillator for RTC with calibration
– Up to 3 SPIs (18 Mbit/s)
■ Low power
– Sleep, Stop and Standby modes
■ CRC calculation unit, 96-bit unique ID
– V
supply for RTC and backup registers
®
BAT
■ ECOPACK packages
■ 1 x 12-bit, 1 µs A/D converters (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
Table 1.
Device summary
Part number
Reference
STM32F101RC STM32F101VC
STM32F101ZC
STM32F101xC
STM32F101xD
STM32F101xE
■ 2 × 12-bit D/A converters
■ DMA
STM32F101RD STM32F101VD
STM32F101ZD
– 12-channel DMA controller
– Peripherals supported: timers, ADC, DAC,
STM32F101RE STM32F101ZE
STM32F101VE
2
SPIs, I Cs and USARTs
■ Up to 112 fast I/O ports
September 2009
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www.st.com
1
Contents
STM32F101xC, STM32F101xD, STM32F101xE
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
®
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
ARM Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 14
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 20
2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.22 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.23 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.26 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Contents
4
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38
Embedded reset and power control block characteristics . . . . . . . . . . . 38
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 76
5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1
6.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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6.2.2
Evaluating the maximum junction temperature for an application . . . . 100
7
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts . . . . 11
STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
High-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maximum current consumption in Run mode, code with data processing
Table 15.
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 43
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 43
Typical current consumption in Run mode, code with data processing
Table 16.
Table 17.
Table 18.
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 47
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 57
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 58
Asynchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Asynchronous multiplexed NOR/PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 65
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 71
Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 74
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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List of tables
STM32F101xC, STM32F101xD, STM32F101xE
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SCL frequency (f
= 36 MHz, V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PCLK1
DD
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
R
max for f
= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
AIN
ADC
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . . 96
LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 97
LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . . 98
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32F101xC, STM32F101xD and STM32F101xE access line block diagram . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout . . . . . . 23
STM32F101xC, STM32F101xD and STM32F101xE LQFP100 pinout . . . . . . . . . . . . . . . 24
STM32F101xC, STM32F101xD and STM32F101xE LQFP64 pinout . . . . . . . . . . . . . . . . 25
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42
Figure 13. Typical current consumption on V
with RTC on vs. temperature at
BAT
different V
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
BAT
Figure 14. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DD
Figure 15. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DD
Figure 16. Typical current consumption in Standby mode versus temperature at
different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DD
Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 18. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 56
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 57
Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 25. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 26. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 28. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 29. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 67
Figure 30. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . . 68
Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 33. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 70
Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 71
Figure 35. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 36. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 37. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 73
Figure 38. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 74
Figure 39. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 40. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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List of figures
STM32F101xC, STM32F101xD, STM32F101xE
2
(1)
Figure 41. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 42. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
(1)
Figure 43. SPI timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 44. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
(1)
Figure 45. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 46. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 47. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . . 90
REF+
DDA
Figure 48. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . 91
Figure 49. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 50. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 94
Figure 51. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 52. LQFP144, 20 x 20 mm, 144-pin thin quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
(1)
Figure 53. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 54. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 97
(1)
Figure 55. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 56. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 98
(1)
Figure 57. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 58. LQFP64 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
D
A
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F101xC, STM32F101xD and STM32F101xE high-density access line
microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family,
please refer to Section 2.2: Full compatibility throughout the family.
The high-density STM32F101xx datasheet should be read in conjunction with the
STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
Doc ID 14610 Rev 7
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Description
STM32F101xC, STM32F101xD, STM32F101xE
2
Description
The STM32F101xC, STM32F101xD and STM32F101xE access line family incorporates the
®
high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency,
high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 48
Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB
buses. All devices offer one 12-bit ADC, four general-purpose 16-bit timers, as well as
2
standard and advanced communication interfaces: up to two I Cs, three SPIs and five
USARTs.
The STM32F101xx high-density access line family operates in the –40 to +85 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F101xx high-density access line family offers devices in 3 different package
types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F101xx high-density access line microcontroller family
suitable for a wide range of applications:
●
●
●
●
Medical and handheld equipment
PC peripherals gaming and GPS platforms
Industrial applications, PLC, printers, and scanners
Alarm systems and video intercom
Figure 1 shows the general block diagram of the device family.
10/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Description
2.1
Device overview
Table 2.
STM32F101xC, STM32F101xD and STM32F101xE features and peripheral
counts
Peripherals
STM32F101Rx
STM32F101Vx
STM32F101Zx
Flash memory in Kbytes
SRAM in Kbytes
FSMC
256
32
384
No
512
256
32
384
512
256
32
384
Yes
512
48
48
48
Yes(1)
4
General-
purpose
Timers
Basic
SPI
2
3
Comm
I2C
2
USART
5
GPIOs
51
80
112
12-bit ADC
1
1
1
Number of channels
16
16
16
12-bit DAC
1
2
Number of channels
CPU frequency
36 MHz
Operating voltage
2.0 to 3.6 V
Ambient temperature: –40 to +85 °C (see Table 10)
Junction temperature: –40 to +105 °C (see Table 10)
Operating temperatures
Package
LQFP64
LQFP100
LQFP144
1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a
multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit
NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not
available in this package.
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Description
STM32F101xC, STM32F101xD, STM32F101xE
Figure 1.
STM32F101xC, STM32F101xD and STM32F101xE access line block
diagram
TRACECLK
TRACED[0:3]
as AS
TPIU
@V
DD
Power
Trace/trig
Trace
controller
Pbus
Ibus
V
SW/JTAG
DD
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
Volt. reg.
3.3 V to 1.8 V
V
SS
Flash 512 Kbytes
64 bit
Cortex-M3 CPU
@V
DDA
Dbus
System
Supply
as AF
F
: 36 MHz
max
NRST
supervision
SRAM
48 KB
POR
Reset
V
V
POR /PDR
DDA
SSA
@VDDA
RC 8 MHz
RC 40 kHz
PLL
NVIC
PVD
Int
GP DMA1
@V
DD
XTAL OSC
4-16 MHz
OSC_IN
OSC_OUT
7 channels
GP DMA2
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[4:1]
NBL[1:0]
NWAIT
NL
IWDG
5 channels
PCLK1
PCLK2
HCLK
FCLK
Reset &
Clock
control
Standby
interface
V
=1.8 V to 3.6 V
BAT
V
@
BAT
FSMC
OSC32_IN
OSC32_OUT
XTAL32kHz
Backup
TAMPER-RTC/
ALARM/SECOND OUT
RTC
AWU
reg
as AF
Backup interface
AHB2
APB2
AHB2
APB1
4 channels as AF
4 channels as AF
4 channels as AF
4 channels as AF
TIM2
EXT.IT
WKUP
112AF
PA[15:0]
PB[15:0]
TIM3
GPIO port A
GPIO port B
GPIO port C
GPIO port D
GPIO port E
GPIO port F
GPIO port G
TIM4
TIM5
RX, TX, CTS, RT,S
CK, as AF
PC[15:0]
PD[15:0]
USART2
USART3
UART4
UART5
RX, TX, CTS, R T S,
CK, as AF
PE[15:0]
PF[15:0]
PG[15:0]
RX,TXasAF
RX,TX asAF
MOSI, MISO
SCK, NSS as AF
SPI2
SPI3
MOSI, MISO, SCK,
NSS as AF
MOSI, MISO
SCK, NSS as AF
SPI1
RX, TX, CTS, RTS
as AF
I2C1
I2C2
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
USART1
WWDG
Temp. sensor
ADC_IN[0:15]
TIM6
TIM7
12bit DAC1
12bit DAC 2
IF
DAC_OUT1 as AF
DAC_OUT2 as AF
12-bit ADC IF
VREF–
VREF+
@ V
DDA
@V
DDA
ai14693d
1. TA = –40 °C to +85 °C (junction temperature up to 105 °C).
2. AF = alternate function on I/O port pin.
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Description
Figure 2.
Clock tree
8 MHz
HSI RC
HSI
FSMCCLK
to FSMC
Peripheral clock
enable
/2
HCLK
36 MHz max
to AHB bus, core,
memory and DMA
Clock
Enable (7 bits)
/8
to Cortex System timer
SW
PLLSRC
FCLK Cortex
free running clock
36 MHz max
PLLMUL
HSI
AHB
Prescaler
/1, 2..512
APB1
Prescaler
/1, 2, 4, 8, 16
SYSCLK
..., x16
x2, x3, x4
PLL
PCLK1
PLLCLK
HSE
36 MHz
max
to APB1
peripherals
Peripheral Clock
Enable (18 bits)
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
else x2
to TIM2,3,4,5,6 and 7
TIMXCLK
CSS
Peripheral Clock
Enable (6 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
/2
36 MHz max
PCLK2
OSC_OUT
OSC_IN
peripherals to APB2
4-16 MHz
HSE OSC
Peripheral Clock
Enable (11 bits)
ADC
to ADC
Prescaler
/2, 4, 6, 8
ADCCLK
/128
LSE
OSC32_IN
to RTC
LSE OSC
RTCCLK
32.768 kHz
OSC32_OUT
RTCSEL[1:0]
to Independent Watchdog (IWDG)
IWDGCLK
LSI
LSI RC
40 kHz
Legend:
Main
Clock Output
/2
PLLCLK
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
MCO
HSI
HSE
SYSCLK
MCO
ai15100
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
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Description
STM32F101xC, STM32F101xD, STM32F101xE
2.2
Full compatibility throughout the family
The STM32F101xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are
identified as low-density devices, the STM32F101x8 and STM32F101xB are referred to as
medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are
referred to as high-density devices.
Low- and high-density devices are an extension of the STM32F101x8/B medium-density
devices, they are specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets,
respectively.
Low-density devices feature lower Flash memory and RAM capacities, less timers and
peripherals. High-density devices have higher Flash memory and RAM densities, and
additional peripherals like FSMC and DACwhile remaining fully compatible with the other
members of the family.
The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE
are a drop-in replacement for the STM32F101x8/B devices, allowing the user to try different
memory densities and providing a greater degree of freedom during the development cycle.
Moreover, the STM32F101xx access line family is fully compatible with all existing
STM32F103xx performance line and STM32F102xx USB access line devices.
Table 3.
STM32F101xx family
Memory size
Low-density devices Medium-density devices
High-density devices
16 KB
Flash
32 KB
64 KB
Flash
128 KB
Flash
256 KB
Flash
384 KB
Flash
512 KB
Flash
Pinout
Flash(1)
32 KB
RAM
48 KB
RAM
48 KB
RAM
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM
144
100
64
5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I2Cs, 1 × ADC, 2 × DACs
FSMC (100 and 144 pins)
3 × USARTs
3 × 16-bit timers
2 × USARTs
2 × SPIs, 2 × I2Cs,
2 × 16-bit timers
1 × ADC
48
1 × SPI, 1 × I2C
1 × ADC
36
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.
2.3
Overview
®
2.3.1
ARM Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Description
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xC, STM32F101xD and STM32F101xE access line family having an
embedded ARM core, is therefore compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
2.3.2
2.3.3
Embedded Flash memory
256 to 512 Kbytes of embedded Flash are available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.3.4
2.3.5
Embedded SRAM
Up to 48 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
FSMC (flexible static memory controller)
The FSMC is embedded in the STM32F101xC, STM32F101xD and STM32F101xE access
line family. It has four Chip Select outputs supporting the following modes: PC
Card/Compact Flash, SRAM, PSRAM, NOR and NAND.
Functionality overview:
●
●
●
●
●
The three FSMC interrupt lines are ORed in order to be connected to the NVIC
No read FIFO
Code execution from external memory except for NAND Flash and PC Card
No boot capability
The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at
36 MHz
2.3.6
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high-
performance solutions using external controllers with dedicated acceleration.
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Description
STM32F101xC, STM32F101xD, STM32F101xE
2.3.7
Nested vectored interrupt controller (NVIC)
The STM32F101xC, STM32F101xD and STM32F101xE access line embeds a nested
vectored interrupt controller able to handle up to 60 maskable interrupt channels (not
including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.
●
●
●
●
●
●
●
●
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.8
2.3.9
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock is available when necessary (for example with failure
of an indirectly used external oscillator).
Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)
domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and
APB domains is 36 MHz. See Figure 2 for details on the clock tree.
2.3.10
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
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STM32F101xC, STM32F101xD, STM32F101xE
Description
2.3.11
Power supply schemes
●
V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V pins.
DD
●
V
, V
= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
DDA
SSA
and PLL (minimum voltage to be applied to V
is 2.4 V when the ADC is used). V
DDA
DDA
and V
must be connected to V and V , respectively.
SSA
DD SS
●
V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V is not present.
DD
For more details on how to connect power pins, refer to Figure 9: Power supply scheme.
2.3.12
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V is below a specified threshold, V
, without the need for an
DD
POR/PDR
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
/V power supply and compares it to the V threshold. An interrupt can be
V
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is higher
DD DDA
PVD
DD DDA
than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics for the values of
V
and V
.
POR/PDR
PVD
2.3.13
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop modes.
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
2.3.14
Low-power modes
The STM32F101xC, STM32F101xD and STM32F101xE access line supports three low-
power modes to achieve the best compromise between low power consumption, short
startup time and available wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
Doc ID 14610 Rev 7
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Description
STM32F101xC, STM32F101xD, STM32F101xE
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.3.15
DMA
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-
peripheral transfers.
The two DMA controllers support circular buffer management, removing the need for user
code intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
2
DMA can be used with the main peripherals: SPI, I C, USART, general-purpose and basic
timers TIMx, DAC and ADC.
2.3.16
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
supply when present or through the V
pin. The backup registers are forty-two 16-bit
DD
BAT
registers used to store 84 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.17
Timers and watchdogs
The high-density STM32F101xx access line devices include up to four general-purpose
timers, two basic timers, two watchdog timers and a SysTick timer.
Table 4 compares the features of the general-purpose and basic timers.
18/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Description
Table 4.
Timer
Timer feature comparison
Counter
Counter Prescaler DMA request Capture/compare Complementary
resolution
type
factor
generation
channels
outputs
TIM2,
TIM3,
TIM4,
TIM5
Up,
down,
up/down and 65536
Any integer
between 1
16-bit
16-bit
Yes
4
No
Any integer
between 1
and 65536
TIM6,
TIM7
Up
Yes
0
No
General-purpose timers (TIMx)
There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)
embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line devices.
These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and
feature 4 independent channels each for input capture/output compare, PWM or one-pulse
mode output. This gives up to 16 input captures / output compares / PWMs on the largest
packages.
The general-purpose timers can work together with the advanced-control timer via the Timer
Link feature for synchronization or event chaining. Their counter can be frozen in debug
mode. Any of the general-purpose timers can be used to generate PWM outputs. They all
have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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Description
STM32F101xC, STM32F101xD, STM32F101xE
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
●
●
●
●
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
2.3.18
2.3.19
I²C bus
Up to two I²C bus interfaces can operate in multi-master and slave modes. They support
standard and fast modes.
They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
Universal synchronous/asynchronous receiver transmitters (USARTs)
The STM32F101xC, STM32F101xD and STM32F101xE access line embeds three
universal synchronous/asynchronous receiver transmitters (USART1, USART2 and
USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of
up to 2.25 Mbit/s.
USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.
2.3.20
2.3.21
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
All SPIs can be served by the DMA controller.
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
20/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Description
2.3.22
ADC (analog to digital converter)
A 12-bit analog-to-digital converter is embedded into STM32F101xC, STM32F101xD and
STM32F101xE access line devices. It has up to 16 external channels, performing
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start trigger and injection trigger, respectively, to allow the application to
synchronize A/D conversion and timers.
2.3.23
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.
This dual digital Interface supports the following features:
●
●
●
●
●
●
●
●
●
●
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference V
REF+
Seven DAC trigger inputs are used in the STM32F101xC, STM32F101xD and
STM32F101xE access line family. The DAC channels are triggered through the timer update
outputs that are also connected to different DMA channels.
2.3.24
2.3.25
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
< 3.6 V. The temperature sensor is internally
DDA
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Doc ID 14610 Rev 7
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Description
STM32F101xC, STM32F101xD, STM32F101xE
2.3.26
Embedded Trace Macrocell™
®
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F10xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using Ethernet, or any
other high-speed channel. Real-time instruction and data flow activity can be recorded and
then formatted for display on the host computer running debugger software. TPA hardware
is commercially available from common development tool vendors. It operates with third
party debugger software tools.
22/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Pinouts and pin descriptions
3
Pinouts and pin descriptions
Figure 3.
STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
V
V
NC
DD_2
SS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
9
PF0
PF1
PF2
PF3
PF4
PF5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
V
V
DD_9
SS_9
V
V
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
SS_5
LQFP144
DD_5
PF6
PF7
PF8
PF9
PF10
OSC_IN
OSC_OUT
NRST
PC0
V
V
DD_8
SS_8
PC1
PC2
PC3
PD13
PD12
PD11
PD10
PD9
V
V
V
V
SSA
REF-
PD8
REF+
PB15
PB14
PB13
PB12
DDA
PA0-WKUP
PA1
PA2
ai14667
Doc ID 14610 Rev 7
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Pinouts and pin descriptions
STM32F101xC, STM32F101xD, STM32F101xE
Figure 4. STM32F101xC, STM32F101xD and STM32F101xE LQFP100 pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD_5
OSC_IN
OSC_OUT
NRST
LQFP100
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PD8
PB15
PB14
PB13
PB12
PA0-WKUP
PA1
PA2
ai14391
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Pinouts and pin descriptions
Figure 5.
STM32F101xC, STM32F101xD and STM32F101xE LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
VBAT
1
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
5
6
7
PC0
PC1
PC2
PC3
VSSA
VDDA
8
LQFP64
9
10
11
12
13
14
15
16
PC6
PB15
PB14
PB13
PB12
PA0-WKUP
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ai14392
Table 5.
Pins
High-density STM32F101xx pin definitions
Main
Alternate functions(4)
Pin name
function(3)
Default
Remap
(after reset)
FT
FT
FT
FT
FT
1
2
-
-
1
2
3
4
5
6
7
8
9
-
PE2
PE3
PE4
PE5
PE6
VBAT
I/O
I/O
I/O
I/O
I/O
S
PE2
PE3
TRACECLK/ FSMC_A23
TRACED0/FSMC_A19
TRACED1/FSMC_A20
TRACED2/FSMC_A21
TRACED3/FSMC_A22
3
-
PE4
4
-
PE5
5
-
PE6
6
1
2
3
4
-
VBAT
PC13(6)
PC14(6)
PC15(6)
PF0
7
PC13-TAMPER-RTC(5) I/O
PC14-OSC32_IN(5)
I/O
PC15-OSC32_OUT(5) I/O
TAMPER-RTC
OSC32_IN
OSC32_OUT
FSMC_A0
FSMC_A1
FSMC_A2
FSMC_A3
FSMC_A4
FSMC_A5
8
9
10
11
12
13
14
15
16
17
PF0
PF1
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
-
-
PF1
-
-
PF2
PF2
-
-
PF3
PF3
-
-
PF4
PF4
-
-
PF5
PF5
-
10
11
VSS_5
VDD_5
VSS_5
VDD_5
-
S
Doc ID 14610 Rev 7
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Pinouts and pin descriptions
STM32F101xC, STM32F101xD, STM32F101xE
Alternate functions(4)
Table 5.
Pins
High-density STM32F101xx pin definitions (continued)
Main
Pin name
function(3)
Default
Remap
(after reset)
18
19
20
21
22
23
24
25
26
27
-
-
-
PF6
PF7
I/O
I/O
I/O
I/O
I/O
I
PF6
PF7
FSMC_NIORD
FSMC_NREG
FSMC_NIOWR
FSMC_CD
-
-
-
PF8
PF8
-
-
PF9
PF9
-
-
PF10
OSC_IN
OSC_OUT
NRST
PC0
PF10
OSC_IN
OSC_OUT
NRST
PC0
FSMC_INTR
5
6
7
8
9
12
13
14
15
16
O
I/O
I/O
I/O
I/O
I/O
S
ADC_IN10
ADC_IN11
ADC_IN12
ADC_IN13
PC1
PC1
28 10 17
29 11 18
30 12 19
PC2
PC2
PC3
PC3
VSSA
VSSA
31
32
-
-
20
21
VREF-
VREF+
VDDA
S
VREF-
VREF+
VDDA
S
33 13 22
S
WKUP/ USART2_CTS(7)
ADC_IN0/TIM5_CH1/
TIM2_CH1_ETR(7)
/
34 14 23
PA0-WKUP
PA1
I/O
I/O
I/O
I/O
PA0
PA1
PA2
PA3
USART2_RTS(7)
/
35 15 24
36 16 25
37 17 26
ADC_IN1/TIM5_CH2
TIM2_CH2(7)
USART2_TX(7)
/
PA2
TIM5_CH3/ADC_IN2/
TIM2_CH3(7)
USART2_RX(7)
/
PA3
TIM5_CH4 / ADC_IN3/
TIM2_CH4(7)
38 18 27
39 19 28
VSS_4
VDD_4
S
S
VSS_4
VDD_4
SPI1_NSS/ DAC_OUT1
40 20 29
41 21 30
42 22 31
PA4
PA5
PA6
I/O
I/O
I/O
PA4
PA5
PA6
ADC_IN4 / USART2_CK(7)
SPI1_SCK/
DAC_OUT2/ADC_IN5
SPI1_MISO / ADC_IN6 /
TIM3_CH1(7)
26/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Pinouts and pin descriptions
Alternate functions(4)
Table 5.
Pins
High-density STM32F101xx pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
SPI1_MOSI / ADC_IN7/
TIM3_CH2(7)
43 23 32
PA7
I/O
PA7
44 24 33
45 25 34
46 26 35
47 27 36
48 28 37
PC4
PC5
I/O
I/O
I/O
I/O
PC4
PC5
PB0
PB1
ADC_IN14
ADC_IN15
PB0
ADC_IN8 / TIM3_CH3(7)
ADC_IN9/TIM3_CH4(7)
PB1
PB2
I/O FT PB2/BOOT1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF11
PF12
VSS_6
VDD_6
PF13
PF14
PF15
PG0
I/O FT
I/O FT
S
PF11
PF12
VSS_6
VDD_6
PF13
PF14
PF15
PG0
FSMC_NIOS16
FSMC_A6
-
-
S
-
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
FSMC_A7
FSMC_A8
FSMC_A9
FSMC_A10
FSMC_A11
FSMC_D4
FSMC_D5
FSMC_D6
-
-
-
-
PG1
PG1
38
39
40
-
PE7
PE7
PE8
PE8
PE9
PE9
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
-
S
41
42
43
44
45
46
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
FSMC_D7
FSMC_D8
FSMC_D9
FSMC_D10
FSMC_D11
FSMC_D12
69 29 47
70 30 48
71 31 49
72 32 50
I2C2_SCL/ USART3_TX(7)
I2C2_SDA/ USART3_RX(7)
TIM2_CH3
TIM2_CH4
S
SPI2_NSS(7)/ I2C2_SMBA
USART3_CK(7)
73 33 51
PB12
I/O FT
PB12
Doc ID 14610 Rev 7
27/106
Pinouts and pin descriptions
STM32F101xC, STM32F101xD, STM32F101xE
Alternate functions(4)
Table 5.
Pins
High-density STM32F101xx pin definitions (continued)
Main
Pin name
function(3)
Default
Remap
(after reset)
SPI2_SCK(7)
/
74 34 52
PB13
PB14
I/O FT
I/O FT
PB13
PB14
USART3_CTS(7)
SPI2_MISO(7)
/
75 35 53
76 36 54
USART3_RTS(7)
SPI2_MOSI(7)
FSMC_D13
PB15
PD8
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
PB15
PD8
77
78
79
80
-
-
-
-
55
56
57
58
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
PD9
PD9
FSMC_D14
PD10
PD11
PD10
PD11
FSMC_D15
FSMC_A16
TIM4_CH1 /
USART3_RTS
81
-
59
PD12
I/O FT
PD12
FSMC_A17
FSMC_A18
82
83
84
85
86
87
88
89
90
91
92
93
94
95
-
-
-
-
-
-
-
-
-
-
-
-
-
-
60
-
PD13
VSS_8
VDD_8
PD14
PD15
PG2
PG3
PG4
PG5
PG6
PG7
PG8
VSS_9
VDD_9
PC6
I/O FT
S
PD13
VSS_8
VDD_8
PD14
PD15
PG2
PG3
PG4
PG5
PG6
PG7
PG8
VSS_9
VDD_9
PC6
TIM4_CH2
-
S
61
62
-
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
FSMC_D0
FSMC_D1
TIM4_CH3
TIM4_CH4
FSMC_A12
FSMC_A13
FSMC_A14
FSMC_A15
FSMC_INT2
FSMC_INT3
-
-
-
-
-
-
-
-
S
96 37 63
97 38 64
98 39 65
99 40 66
100 41 67
101 42 68
102 43 69
103 44 70
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
PC7
PC7
PC8
PC8
PC9
PC9
PA8
PA8
USART1_CK/ MCO
USART1_TX(7)
USART1_RX(7)
USART1_CTS
PA9
PA9
PA10
PA11
PA10
PA11
28/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Pinouts and pin descriptions
Alternate functions(4)
Table 5.
Pins
High-density STM32F101xx pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
104 45 71
105 46 72
PA12
PA13
I/O FT
PA12
USART1_RTS
I/O FT JTMS-SWDIO
Not connected
PA13
106
-
73
107 47 74
108 48 75
109 49 76
V
S
S
V
SS_2
SS_2
DD_2
V
V
DD_2
PA14
PA15
I/O FT JTCK-SWCLK
PA14
TIM2_CH1_ETR/
PA15 /SPI1_NSS
110 50 77
I/O FT
JTDI
SPI3_NSS
111 51 78
112 52 79
113 53 80
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
I/O FT
I/O FT
I/O FT
I/O FT
PC10
PC11
UART4_TX
UART4_RX
UART5_TX
USART3_TX
USART3_RX
USART3_CK
PC12
(8)
(9)
114
115
5
6
81
82
OSC_IN
FSMC_D2
(8)
(9)
I/O FT OSC_OUT
FSMC_D3
116 54 83
I/O FT
I/O FT
I/O FT
I/O FT
S
PD2
PD3
PD4
PD5
TIM3_ETR/UART5_RX
FSMC_CLK
117
118
119
120
121
122
-
-
-
-
-
-
84
85
86
-
USART2_CTS
USART2_RTS
USART2_TX
FSMC_NOE
FSMC_NWE
V
V
SS_10
DD_10
SS_10
DD_10
-
V
S
V
87
PD6
PD7
I/O FT
PD6
PD7
FSMC_NWAIT
USART2_RX
USART2_CK
FSMC_NE1/
FSMC_NCE2
123
124
125
-
-
-
88
-
I/O FT
I/O FT
I/O FT
FSMC_NE2/
FSMC_NCE3
PG9
PG9
FSMC_NE3/
FSMC_NCE4_1
-
PG10
PG10
126
127
128
129
130
131
132
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PG11
PG12
PG13
PG14
I/O FT
I/O FT
I/O FT
I/O FT
S
PG11
PG12
PG13
PG14
FSMC_NCE4_2
FSMC_NE4
FSMC_A24
FSMC_A25
V
V
SS_11
DD_11
SS_11
DD_11
V
S
V
PG15
I/O FT
PG15
Doc ID 14610 Rev 7
29/106
Pinouts and pin descriptions
STM32F101xC, STM32F101xD, STM32F101xE
Alternate functions(4)
Table 5.
Pins
High-density STM32F101xx pin definitions (continued)
Main
Pin name
function(3)
Default
Remap
(after reset)
TIM2_CH2 /PB3
TRACESWO
SPI1_SCK
133 55 89
134 56 90
PB3
PB4
I/O FT
I/O FT
JTDO
SPI3_SCK
PB4 / TIM3_CH1
SPI1_MISO
NJTRST
SPI3_MISO
TIM3_CH2 /
SPI1_MOSI
135 57 91
136 58 92
137 59 93
PB5
PB6
PB7
I/O
PB5
PB6
PB7
I2C1_SMBA/ SPI3_MOSI
I2C1_SCL/ TIM4_CH1(7)
I/O FT
I/O FT
USART1_TX
USART1_RX
I2C1_SDA/FSMC_NADV
TIM4_CH2(7)
138 60 94
139 61 95
140 62 96
BOOT0
PB8
I
BOOT0
PB8
I/O FT
I/O FT
TIM4_CH3 (7)
TIM4_CH4 (7)
I2C1_SCL
I2C1_SDA
PB9
PB9
TIM4_ETR(7)
FSMC_NBL0
/
141
142
-
-
97
98
PE0
I/O FT
PE0
PE1
I/O FT
PE1
FSMC_NBL1
143 63 99
144 64 100
VSS_3
VDD_3
S
S
VSS_3
VDD_3
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F10xxx reference manual
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
30/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Pinouts and pin descriptions
Table 6.
Pins
FSMC pin definition
FSMC
NOR/PSRAM/ NOR/PSRAM
LQFP100
BGA100(1)
CF
CF/IDE
NAND 16 bit
SRAM
Mux
PE2
PE3
A23
A19
A20
A21
A22
A0
A23
A19
A20
A21
A22
Yes
Yes
PE4
Yes
PE5
Yes
PE6
Yes
PF0
A0
A1
A0
A1
A2
-
PF1
A1
-
PF2
A2
A2
-
PF3
A3
A3
-
PF4
A4
A4
-
PF5
A5
A5
-
PF6
NIORD
NREG
NIOWR
CD
NIORD
NREG
NIOWR
CD
-
PF7
-
-
PF8
PF9
-
PF10
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PE7
INTR
NIOS16
A6
INTR
-
NIOS16
-
A6
A7
-
A7
-
A8
A8
-
A9
A9
-
A10
A10
A11
D4
-
-
D4
D5
D4
D5
DA4
DA5
D4
D5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PE8
D5
PE9
D6
D6
D6
DA6
D6
PE10
PE11
PE12
PE13
PE14
PE15
PD8
D7
D7
D7
DA7
D7
D8
D8
D8
DA8
D8
D9
D9
D9
DA9
D9
D10
D11
D12
D13
D10
D11
D12
D13
D10
D11
D12
D13
DA10
DA11
DA12
DA13
D10
D11
D12
D13
Doc ID 14610 Rev 7
31/106
Pinouts and pin descriptions
STM32F101xC, STM32F101xD, STM32F101xE
Table 6.
Pins
FSMC pin definition (continued)
FSMC
LQFP100
BGA100(1)
NOR/PSRAM/ NOR/PSRAM
CF
CF/IDE
NAND 16 bit
SRAM
Mux
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PG2
PG3
PG4
PG5
PG6
PG7
PD0
D14
D15
D14
D15
D14
D15
A16
A17
A18
D0
DA14
DA15
A16
D14
D15
CLE
ALE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
A17
A18
D0
D1
D0
D1
DA0
DA1
D0
D1
D1
A12
A13
A14
A15
-
-
-
INT2
INT3
D2
-
-
D2
D3
D2
D3
D2
D3
DA2
DA3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
PD1
D3
PD3
CLK
NOE
NWE
NWAIT
NE1
NE2
NE3
CLK
PD4
NOE
NWE
NOE
NWE
NOE
NWE
NWAIT
NE1
NOE
NWE
PD5
PD6
NWAIT
NWAIT
NWAIT
NCE2
NCE3
PD7
PG9
PG10
PG11
PG12
PG13
PG14
PB7
NE2
NCE4_1
NCE4_2
NCE4_1
NCE4_2
NE3
-
-
NE4
A24
NE4
A24
-
-
A25
A25
-
NADV
NBL0
NBL1
NADV
NBL0
NBL1
Yes
Yes
Yes
PE0
PE1
1. Ports F and G are not available in devices delivered in 100-pin packages.
32/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Memory mapping
4
Memory mapping
The memory map is shown in Figure 6.
Figure 6.
Memory map
Reserved
FSMC register
0xA000 1000 - 0xBFFF FFFF
0xA000 0000 - 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
0x8000 0000 - 0x8FFF FFFF
0x7000 0000 - 0x7FFF FFFF
0x6C00 0000 - 0x6FFF FFFF
0x6800 0000 - 0x6BFF FFFF
0x6400 0000 - 0x67FF FFFF
0x6000 0000 - 0x63FF FFFF
0x4002 3400 - 0x5FFF FFFF
0x4002 3000 - 0x4002 33FF
FSMC bank 4 PCCARD
FSMC bank 3 NAND (NAND2)
FSMC bank 2 NAND (NAND1)
FSMC bank 1 NOR/PSRAM 4
FSMC bank 1 NOR/PSRAM 3
FSMC bank 1 NOR/PSRAM 2
FSMC bank 1 NOR/PSRAM 1
Reserved
CRC
Reserved
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
Flash interface
Reserved
RCC
Reserved
DMA2
DMA1
Reserved
Reserved
0x4002 0000 - 0x4002 03FF
0x4001 8400 - 0x4001 FFFF
0x4001 8000 - 0x4001 83FF
0xFFFF FFFF
Reserved
0x4001 3C00 - 0x4001 7FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
512-Mbyte
block 7
Cortex-M3's
internal
USART1
Reserved
SPI1
Reserved
0x4001 2800 - 0x4001 2FFF
0x4001 2400 - 0x4001 27FF
0xE000 0000
0xDFFF FFFF
peripherals
ADC1
Port G
Port F
0x4001 2000 - 0x4001 23FF
0x4001 1C00 - 0x4001 1FFF
0x4001 1800 - 0x4001 1BFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0C00 - 0x4001 0FFF
0x4001 0800 - 0x4001 0BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 7800 - 0x4000 FFFF
512-Mbyte
block 6
Not used
Port E
Port D
Port C
Port B
Port A
EXTI
0xC000 0000
0xBFFF FFFF
512-Mbyte
block 5
FSMC register
AFIO
Reserved
0xA000 0000
0x9FFF FFFF
DAC
PWR
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
512-Mbyte
block 4
FSMC bank3
& bank4
BKP
0x4000 6C00 - 0x4000 6FFF
0x4000 5C00 - 0x4000 6BFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1800 - 0x4000 27FF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
Reserved
I2C2
I2C1
0x8000 0000
0x7FFF FFFF
UART5
UART4
512-Mbyte
block 3
FSMC bank1
& bank2
USART3
USART2
0x6000 0000
0x5FFF FFFF
Reserved
SPI3
512-Mbyte
block 2
Peripherals
SPI2
Reserved
IWDG
0x4000 0000
0x3FFF FFFF
WWDG
RTC
512-Mbyte
block 1
SRAM
Reserved
TIM7
TIM6
0x2000 0000
0x1FFF FFFF
TIM5
512-Mbyte
block 0
Code
TIM4
TIM3
TIM2
0x0000 0000
0x3FFF FFFF
Reserved
0x2000 C000
0x2000 BFFF
SRAM (48 KB aliased
by bit-banding)
0x2000 0000
Option Bytes
0x1FFF F800 - 0x1FFF F80F
0x1FFF F000- 0x1FFF F7FF
0x1FFF EFFF
0x0808 0000
0x0807 FFFF
0x0800 0000
0x07FF FFFF
0x0008 0000
System memory
Reserved
Flash
Reserved
Aliased to Flash or system 0x0007 FFFF
memory depending on
0x0000 0000
BOOT pins
ai14811c
Doc ID 14610 Rev 7
33/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
2 V V 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2).
5.1.3
5.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
34/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
Figure 7.
Pin loading conditions
Figure 8.
Pin input voltage
STM32F101 PIN
STM32F101 PIN
C=50pF
V
IN
ai14123
ai14124
5.1.6
Power supply scheme
Figure 9.
Power supply scheme
V
BAT
Backup circuitry
(OSC32K,RTC,
Wake-up logic
Power switch
1.8-3.6V
Backup registers)
OUT
IN
IO
Logic
GP I/Os
Kernel logic
(CPU,
Digital
& Memories)
V
DD
V
DD1/2/.../11
Regulator
11 × 100 nF
+ 1 × 4.7 µF
V
SS1/2/.../11
V
DD
V
DDA
V
REF
V
REF+
Analog:
RCs, PLL,
...
10 nF
+ 1 µF
10 nF
+ 1 µF
V
ADC
REF-
V
SSA
ai15401
Caution:
In Figure 9, the 4.7 µF capacitor must be connected to V
.
DD3
Doc ID 14610 Rev 7
35/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
5.1.7
Current consumption measurement
Figure 10. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics,
Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 7.
Symbol
Voltage characteristics
Ratings
Min
Max
Unit
External main supply voltage (including
VDD VSS
–0.3
4.0
(1)
VDDA and VDD
)
V
Input voltage on five volt tolerant pin(2)
Input voltage on any other pin(2)
VSS 0.3
VSS 0.3
+5.5
VDD+0.3
50
VIN
|VDDx
|
Variations between different VDD power pins
mV
Variations between all the different ground
pins
|VSSX VSS
|
50
seeSection 5.3.12:Absolute
maximum ratings (electrical
sensitivity)
Electrostatic discharge voltage (human body
model)
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded (see Table 8: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is
induced by VIN<VSS
.
36/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Table 8.
Symbol
IVDD
IVSS
Current characteristics
Ratings
Max.
Unit
Total current into VDD/VDDA power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on NRST pin
150
150
25
IIO
25
5
mA
Injected current on High-speed external OSC_IN and Low-
speed external OSC_IN pins
(2)(3)
IINJ(PIN)
5
Injected current on any other pin(4)
5
(2)
IINJ(PIN)
Total injected current (sum of all I/O and control pins)(4)
25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS
.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
characteristics.
4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 9.
Thermal characteristics
Ratings
Symbol
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
°C
°C
Maximum junction temperature
150
Doc ID 14610 Rev 7
37/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
5.3
Operating conditions
5.3.1
General operating conditions
Table 10. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK1
fPCLK2
VDD
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
0
0
0
2
36
36
36
3.6
MHz
V
Analog operating voltage
(ADC not used)
2
3.6
3.6
Must be the same potential
as VDD
(1)
VDDA
V
(2)
Analog operating voltage
(ADC used)
2.4
1.8
VBAT
Backup operating voltage
3.6
666
434
444
85
V
LQFP144
Power dissipation at TA =
85 °C(3)
PD
LQFP100
mW
LQFP64
Maximum power dissipation
Low power dissipation(4)
–40
–40
–40
°C
°C
°C
TA
TJ
Ambient temperature
105
105
Junction temperature range
1. When the ADC is used, refer to Table 53: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 99).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 99).
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 11 are derived from tests performed under the ambient
temperature condition summarized in Table 10.
Table 11. Operating conditions at power-up / power-down
Symbol
Parameter
VDD rise time rate
VDD fall time rate
Conditions
Min
0
Max
Unit
tVDD
µs/V
20
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 12 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
38/106
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
.
Table 12. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
2.1
2
2.18 2.26
2.08 2.16
V
V
2.19 2.28 2.37
2.09 2.18 2.27
2.28 2.38 2.48
2.18 2.28 2.38
2.38 2.48 2.58
2.28 2.38 2.48
2.47 2.58 2.69
2.37 2.48 2.59
2.57 2.68 2.79
2.47 2.58 2.69
2.66 2.78 2.9
2.56 2.68 2.8
V
V
V
V
V
V
Programmable voltage
detector level selection
VPVD
V
V
V
V
V
V
2.76 2.88
3
V
2.66 2.78 2.9
100
V
(2)
VPVDhyst
PVD hysteresis
mV
V
1.8(1)
Falling edge
Rising edge
1.88 1.96
Power on/power down
reset threshold
VPOR/PDR
1.84 1.92 2.0
40
V
(2)
VPDRhyst
PDR hysteresis
mV
ms
(2)
tRSTTEMPO
Reset temporization
1.5
2.5
3.5
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
5.3.4
Embedded reference voltage
The parameters given in Table 13 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
Table 13. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VREFINT Internal reference voltage
–40 °C < TA < +85 °C 1.16 1.20
5.1
1.24
V
ADC sampling time when reading
the internal reference voltage
(1)
17.1(2)
10
TS_vrefint
µs
Internal reference voltage spread
over the temperature range
(2)
VRERINT
VDD = 3 V 10 mV
mV
ppm/
°C
(2)
TCoeff
Temperature coefficient
100
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except if it is explicitly mentioned
The Flash access time is adjusted to f
wait state from 24 to 36 MHz)
frequency (0 wait state from 0 to 24 MHz, 1
HCLK
●
●
Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f = f , f = f
PCLK1
HCLK/2 PCLK2
HCLK
The parameters given in Table 14 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
40/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Table 14. Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
36 MHz
39
27
External clock (2), all
peripherals enabled
24 MHz
16 MHz
8 MHz
20
11
Supply current
in Run mode
IDD
mA
36 MHz
24 MHz
16 MHz
8 MHz
22
External clock (2), all
peripherals Disabled
16.5
12.5
8
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15. Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
36 MHz
34
24
17
10
18
13
10
6
External clock (2), all
peripherals enabled
24 MHz
16 MHz
8 MHz
Supply current in
Run mode
IDD
mA
36 MHz
24 MHz
16 MHz
8 MHz
External clock(2) all
peripherals disabled
1. Based on characterization, tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
35
30
8 MHz
16 MHz
25
20
15
10
5
24 MHz
36 MHz
0
-45
25
70
85
Temperature (°C)
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled
18
16
8 MHz
16 MHz
24 MHz
36 MHz
14
12
10
8
6
4
2
0
-45
25
70
85
Temperature (°C)
42/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Table 16. Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
36 MHz
24
17
12.5
8
External clock(2) all
peripherals enabled
24 MHz
16 MHz
8 MHz
Supply current in
Sleep mode
IDD
mA
36 MHz
24 MHz
16 MHz
8 MHz
6
External clock(2), all
peripherals disabled
5
4.5
4
1. Based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 17. Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Max
Symbol
Parameter
Conditions
Unit
VDD/VBAT
VDD/VBAT
VDD/VBAT TA =
= 2.0 V
= 2.4 V
= 3.3 V 85 °C
Regulator in Run mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
34.5
24.5
35
25
379
365
Supply current
in Stop mode
Regulator in Low-power mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
IDD
Low-speed internal RC oscillator and
independent watchdog ON
µA
3
3.8
3.6
-
-
Supply current Low-speed internal RC oscillator ON,
2.8
in Standby
mode
independent watchdog OFF
Low-speed internal RC oscillator and
independent watchdog OFF, low-speed
oscillator and RTC OFF
1.9
1.1
2.1
1.4
5(2)
Backup domain
supply current
IDD_VBAT
Low-speed oscillator and RTC ON
1.05
2(2)
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not tested in production.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 13. Typical current consumption on V
with RTC on vs. temperature at
BAT
different V
values
BAT
2.5
2
1.8 V
1.5
1
2 V
2.4 V
3.3 V
3.6 V
0.5
0
–45
25
85
105
Temperature (°C)
ai17337
Figure 14. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different V values
DD
300
250
200
150
100
50
2.4V
2.7V
3.0V
3.3V
3.6V
0
-45
25
70
85
Temperature (°C)
44/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 15. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different V values
DD
300
250
200
150
100
50
2.4V
2.7V
3.0V
3.3V
3.6V
0
-45
25
70
85
Temperature (°C)
Figure 16. Typical current consumption in Standby mode versus temperature at
different V values
DD
3.5
3
2.5
2
1.5
1
2.4V
2.7V
3.0V
3.3V
3.6V
0.5
0
-45
25
70
85
Temperature (°C)
Doc ID 14610 Rev 7
45/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Typical current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except if it is explicitly mentioned
The Flash access time is adjusted to f
wait state from 24 to 36 MHz)
frequency (0 wait state from 0 to 24 MHz, 1
HCLK
●
●
Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f = f , f = f , f
=
HCLK/2 ADCCLK
PCLK1
HCLK/4 PCLK2
f
/4
PCLK2
The parameters given in Table 18 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
Table 18. Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
All peripherals
enabled(2)
All peripherals
disabled
36 MHz
24 MHz
16 MHz
8 MHz
26.6
18.5
12.8
7.2
4.2
2.7
2
16.2
11.4
8.2
5
External
clock(3)
4 MHz
3.1
2.1
1.7
1.4
1.2
15.6
10.8
7.6
4.4
2.5
1.5
1.1
0.8
0.6
2 MHz
1 MHz
500 kHz
125 kHz
36 MHz
24 MHz
16 MHz
8 MHz
1.6
1.3
26
Supply
IDD
current in
mA
Run mode
17.9
12.2
6.6
3.6
2.1
1.4
1
Running on
high speed
internal RC
(HSI), AHB
prescaler
used to
reduce the
frequency
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
0.7
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Table 19. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Typ(1)
Symbol
Parameter
Conditions
fHCLK
Unit
Allperipherals Allperipherals
enabled(2)
disabled
36 MHz
24 MHz
16 MHz
8 MHz
15.1
10.4
7.2
3.9
2.6
1.85
1.5
1.3
1.2
14.5
9.8
6.6
3.3
2
3.6
2.6
2
1.3
1.2
1.15
1.1
1.05
1.05
3
External clock(3)
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
36 MHz
24 MHz
16 MHz
8 MHz
Supply
IDD
current in
Sleep mode
mA
2
1.4
0.7
0.6
0.55
0.5
0.45
0.45
Running on High
Speed Internal
RC (HSI), AHB
prescaler used to
reduce the
4 MHz
2 MHz
1.25
0.9
0.7
0.6
frequency
1 MHz
500 kHz
125 kHz
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed
under the following conditions:
●
●
●
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
●
ambient operating temperature and V supply voltage conditions summarized in
DD
Table 7.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Table 20. Peripheral current consumption
Peripheral
Typical consumption at 25 °C(1)
Unit
TIM2
0.6
0.6
TIM3
TIM4
0.6
TIM5
0.6
TIM6
0.2
TIM7
0.2
SPI2
0.15
0.15
0.25
0.25
0.3
APB1
SPI3
USART2
USART3
UART4
UART5
I2C1
0.3
0.22
0.22
0.72
0.3
mA
I2C2
DAC
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
ADC(2)
SPI1
0.4
0.4
0.3
0.5
APB2
0.4
0.5
1.4
0.3
USART1
0.6
1. fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit
in the ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 10.
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Table 21. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fHSE_ext
1
8
25
MHz
OSC_IN input pin high level
voltage
VHSEH
VHSEL
0.7VDD
VSS
VDD
V
OSC_IN input pin low level
voltage
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
16
ns
tr(HSE)
tf(HSE)
20
Cin(HSE) OSC_IN input capacitance(1)
5
pF
%
DuCy(HSE) Duty cycle
45
55
1
IL
OSC_IN Input leakage current
VSS VIN VDD
µA
1. Guaranteed by design, not tested in production
Low-speed external user clock generated from an external source
The characteristics given in Table 22 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 10.
Table 22. Low-speed user external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fLSE_ext
32.768
1000
kHz
OSC32_IN input pin high
level voltage
VLSEH
VLSEL
0.7VDD
VSS
VDD
V
OSC32_IN input pin low level
voltage
0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
OSC32_IN rise or fall time(1)
450
ns
tr(LSE)
tf(LSE)
50
OSC32_IN input
capacitance(1)
Cin(LSE)
5
pF
%
DuCy(LSE) Duty cycle
OSC32_IN Input leakage
30
70
1
IL
VSS VIN VDD
µA
current
1. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 17. High-speed external clock source AC timing diagram
V
HSEH
90%
10%
V
HSEL
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
clock source
I
L
OSC _IN
STM32F10xxx
ai14127b
Figure 18. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
t
W(LSE)
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
clock source
I
L
OSC32_IN
STM32F10xxx
ai14140c
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 23. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
(1)(2)
Table 23. HSE 4-16 MHz oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fOSC_IN Oscillator frequency
4
8
16
MHz
RF
C
Feedback resistor
200
k
Recommended load capacitance
versus equivalent serial
RS = 30
30
pF
resistance of the crystal (RS)(3)
VDD = 3.3 V
VIN = VSS with 30 pF
load
i2
HSE driving current
1
mA
gm
Oscillator transconductance
Startup time
Startup
25
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 19). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C . Refer to the application note AN2867 “Oscillator design guide for ST
C
L1
L2
microcontrollers” available from the ST website www.st.com.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 19. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
STM32F10xxx
OSC_OUT
(1)
R
EXT
C
L2
ai14128b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 24. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
(1)
Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Feedback resistor
Conditions
Min
Typ
Max
Unit
RF
5
M
Recommended load capacitance
versus equivalent serial
C(2)
RS = 30 K
15
pF
µA
resistance of the crystal (RS)(3)
VDD = 3.3 V
I2
LSE driving current
1.4
VIN = VSS
gm
Oscillator transconductance
Startup time
5
µA/V
s
(4)
tSU(LSE)
VDD is stabilized
3
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Note:
For C and C , it is recommended to use high-quality ceramic capacitors in the 5 pF to
L1 L2
15 pF range selected to match the requirements of the crystal or resonator. C and C are
L1
L2,
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C and C .
L1
L2
Load capacitance C has the following formula: C = C x C / (C + C ) + C where
L
L
L1
L2
L1
L2
stray
C
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
stray
between 2 pF and 7 pF.
52/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Caution:
To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended
L1
L2
to use a resonator with a load capacitance C 7 pF. Never use a resonator with a load
L
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C = 6 pF, and C
= 2 pF,
L
stray
then C = C = 8 pF.
L1
L2
Figure 20. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_IN
LSE
Bias
controlled
gain
32.768 KHz
resonator
R
F
STM32F10xxx
OSC32_OUT
C
L2
ai14129b
5.3.7
Internal clock source characteristics
The parameters given in Table 25 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
High-speed internal (HSI) RC oscillator
(1)
Table 25. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max
Unit
fHSI
8
MHz
User-trimmed with the RCC_CR
register(2)
1(3)
%
TA = –40 to 105 °C
–2
2.5
2.2
2
%
%
%
%
Accuracy of the HSI
oscillator
ACCHSI
TA = –10 to 85 °C
Factory-
–1.5
–1.3
–1.1
calibrated(4)
TA = 0 to 70 °C
TA = 25 °C
1.8
HSI oscillator startup
time
(4)
tsu(HSI)
1
2
µs
HSI oscillator power
consumption
(4)
IDD(HSI)
80
100
µA
1. VDD = 3.3 V, TA = –40 to 85 °C unless otherwise specified.
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Low-speed internal (LSI) RC oscillator
(1)
Table 26. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
30
40
60
85
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
(3)
IDD(LSI)
LSI oscillator power consumption
0.65
1.2
µA
1.
VDD = 3 V, TA = –40 to 85 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 27 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 10.
Table 27. Low-power mode wakeup timings
Symbol
Parameter
Wakeup from Sleep mode
Typ
Unit
(1)
1.8
µs
tWUSLEEP
Wakeup from Stop mode (regulator in run mode)
Wakeup from Stop mode (regulator in low-power mode)
Wakeup from Standby mode
3.6
5.4
50
(1)
µs
µs
tWUSTOP
(1)
tWUSTDBY
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
54/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.3.8
PLL characteristics
The parameters given in Table 28 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
Table 28. PLL characteristics
Value
Symbol
Parameter
Unit
Min(1)
Typ
Max(1)
PLL input clock(2)
1
8.0
25
60
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
40
16
fPLL_OUT
tLOCK
36
MHz
µs
200
300
Jitter
Cycle-to-cycle jitter
ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 85 °C unless otherwise specified.
A
Table 29. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
tERASE
tME
16-bit programming time
Page (2 KB) erase time
Mass erase time
TA–40 to +85 °C
TA –40 to +85 °C
TA –40 to +85 °C
40
20
20
52.5
70
40
40
µs
ms
ms
Read mode
fHCLK = 36 MHz with 1
wait state, VDD = 3.3 V
28
7
mA
mA
mA
Write mode
fHCLK = 36 MHz, VDD
3.3 V
=
IDD
Supply current
Erase mode
fHCLK = 36 MHz, VDD
3.3 V
=
5
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
50
µA
V
Vprog
Programming voltage
2
3.6
1. Guaranteed by design, not tested in production.
Doc ID 14610 Rev 7
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Electrical characteristics
Symbol
STM32F101xC, STM32F101xD, STM32F101xE
Table 30. Flash memory endurance and data retention
Value
Typ
Parameter
Conditions
Unit
Min(1)
Max
NEND Endurance
tRET Data retention
TA = –40 °C to 85 °C
TA = 85 °C, 1 kcycle(2)
TA = 55 °C, 10 kcycle(2)
kcycles
Years
10
30
20
1. Based on characterization, not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10
FSMC characteristics
Asynchronous waveforms and timings
Figure 21 through Figure 24 represent asynchronous waveforms and Table 31 through
Table 34 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●
●
●
AddressSetupTime = 0
AddressHoldTime = 1
DataSetupTime = 1
Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FSMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FSMC_NOE
FSMC_NWE
tv(A_NE)
t
h(A_NOE)
FSMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FSMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FSMC_D[15:0]
FSMC_NADV(1)
t
v(NADV_NE)
t
w(NADV)
ai14991B
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Doc ID 14610 Rev 7
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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
(1) (2)
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol Parameter Min Max
tw(NE) FSMC_NE low time 5THCLK – 1.5 5THCLK + 2
tv(NOE_NE) 0.5 1.5
tw(NOE) 5THCLK – 1.5 5THCLK + 1.5 ns
th(NE_NOE)
tv(A_NE)
Unit
ns
ns
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time –1.5
FSMC_NEx low to FSMC_A valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
th(A_NOE)
tv(BL_NE)
th(BL_NOE)
Address hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
0.1
0
FSMC_BL hold time after FSMC_NOE high
0
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOEx high setup time
th(Data_NOE) Data hold time after FSMC_NOE high
2THCLK + 25
2THCLK + 25
0
0
th(Data_NE)
Data hold time after FSMC_NEx high
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
5
tw(NADV)
FSMC_NADV low time
THCLK + 1.5
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
FSMC_NWE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FSMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FSMC_NADV
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
(1)(2)
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
ns
3THCLK – 1
THCLK – 0.5
THCLK – 0.5
3THCLK + 2
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
THCLK + 1.5 ns
THCLK + 1.5 ns
ns
FSMC_NWE high to FSMC_NE high hold time THCLK
FSMC_NEx low to FSMC_A valid
7.5
ns
ns
ns
ns
ns
ns
ns
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to Data valid
THCLK
1.5
THCLK – 0.5
THCLK + 7
th(Data_NWE) Data hold time after FSMC_NWE high
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
THCLK
5.5
tw(NADV)
FSMC_NADV low time
THCLK + 1.5 ns
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms
t
w(NE)
FSMC_NE
t
t
h(NE_NOE)
v(NOE_NE)
FSMC_NOE
t
w(NOE)
FSMC_NWE
t
tv(A_NE)
h(A_NOE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NOE)
FSMC_NBL[1:0]
NBL
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
su(Data_NOE)
Address
Data
FSMC_AD[15:0]
FSMC_NADV
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
ai14892b
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
(1)(2)
Table 33. Asynchronous multiplexed NOR/PSRAM read timings
Symbol
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
7THCLK – 2
7THCLK + 2
ns
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
3THCLK – 0.5 3THCLK + 1.5 ns
4THCLK – 1
4THCLK + 2
ns
ns
ns
ns
ns
FSMC_NOE high to FSMC_NE high hold time –1
FSMC_NEx low to FSMC_A valid
0
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
3
5
tw(NADV)
FSMC_NADV low time
THCLK –1.5
THCLK + 1.5
FSMC_AD (address) valid hold time after
FSMC_NADV high
th(AD_NADV)
THCLK
ns
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FSMC_NOE high
FSMC_BL hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
THCLK
0
ns
ns
ns
ns
ns
ns
ns
0
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOE high setup time
2THCLK + 24
2THCLK + 25
th(Data_NE)
Data hold time after FSMC_NEx high
0
0
th(Data_NOE) Data hold time after FSMC_NOE high
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
FSMC_NWE
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[1:0]
FSMC_AD[15:0]
NBL
t
t
h(Data_NWE)
t
v(A_NE)
v(Data_NADV)
Address
Data
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
FSMC_NADV
ai14891B
(1)(2)
Table 34. Asynchronous multiplexed NOR/PSRAM write timings
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
5THCLK – 1
2THCLK
5THCLK + 2
2THCLK + 1
2THCLK + 2
ns
ns
ns
ns
ns
ns
ns
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
2THCLK – 1
THCLK – 1
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
7
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
3
5
tw(NADV)
FSMC_NADV low time
THCLK – 1
THCLK + 1
FSMC_AD (address) valid hold time after
FSMC_NADV high
th(AD_NADV)
T
HCLK – 3
ns
th(A_NWE)
tv(BL_NE)
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
4THCLK
ns
ns
ns
1.6
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
THCLK – 1.5
tv(Data_NADV) FSMC_NADV high to Data valid
THCLK + 1.5 ns
ns
th(Data_NWE) Data hold time after FSMC_NWE high
THCLK – 5
1. CL = 15 pF.
2. Based on characterization, not tested in production.
60/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Synchronous waveforms and timings
Electrical characteristics
Figure 25 through Figure 28 represent synchronous waveforms and Table 36 through
Table 38 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●
●
●
●
●
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 25. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
Data latency = 1
d(CLKL-NExL)
t
t
t
d(CLKH-NExH)
FSMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FSMC_NADV
t
d(CLKH-AIV)
d(CLKL-AV)
FSMC_A[25:16]
t
t
d(CLKH-NOEH)
d(CLKL-NOEL)
FSMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FSMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
ai14893e
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
(1)(2)
Table 35. Synchronous multiplexed NOR/PSRAM read timings
Symbol Parameter
tw(CLK)
Min
27.7
Max
Unit
FSMC_CLK period
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
1.5
THCLK + 2
4
0
FSMC_CLK low to FSMC_NADV high
5
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25) THCLK + 2
FSMC_CLK low to FSMC_NOE low
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
THCLK +1 ns
ns
FSMC_CLK high to FSMC_NOE high
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
THCLK + 0.5
12
ns
ns
0
6
FSMC_A/D[15:0] valid data before FSMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
ns
FSMC_A/D[15:0] valid data after FSMC_CLK high THCLK – 10
ns
ns
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
8
2
1. CL = 15 pF.
2. Based on characterization, not tested in production.
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Figure 26. Synchronous multiplexed PSRAM write timings
Electrical characteristics
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
Data latency = 1
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FSMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FSMC_NADV
t
t
t
d(CLKL-AV)
d(CLKH-AIV)
FSMC_A[25:16]
FSMC_NWE
t
d(CLKL-NWEL)
d(CLKH-NWEH)
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
D1
t
d(CLKL-Data)
d(CLKL-ADV)
FSMC_AD[15:0]
AD[15:0]
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NBL
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
t
d(CLKL-NBLH)
ai14992d
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
(1)(2)
Table 36. Synchronous multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Min
27.7
Max
Unit
FSMC_CLK period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_Nex low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
2
THCLK + 2
4
FSMC_CLK low to FSMC_NADV high
5
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
0
td(CLKH-AIV)
TCK + 2
THCLK +1
3
td(CLKL-NWEL)
td(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
td(CLKL-Data)
1
FSMC_CLK high to FSMC_NWE high
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid after FSMC_CLK low
12
6
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
7
2
1
th(CLKH-NWAITV)
td(CLKL-NBLH)
FSMC_NWAIT valid after FSMC_CLK high
FSMC_CLK low to FSMC_NBL high
1. CL = 15 pF.
2. Based on characterization, not tested in production.
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Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 1
d(CLKL-NADVH)
FSMC_NEx
t
t
d(CLKL-NADVL)
FSMC_NADV
t
t
d(CLKH-AIV)
d(CLKL-AV)
FSMC_A[25:0]
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FSMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
t
t
h(CLKH-DV)
su(DV-CLKH)
FSMC_D[15:0]
FSMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
(WAITCFG = 1b, WAITPOL + 0b)
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
ai14894d
(1)(2)
Table 37. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol Parameter Min
tw(CLK) 27.7
Max
Unit
FSMC_CLK period
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
1.5
4
THCLK + 2
FSMC_CLK low to FSMC_NADV high
5
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
0
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x = 0...25) THCLK + 4
FSMC_CLK low to FSMC_NOE low
td(CLKL-NOEL)
td(CLKH-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
THCLK + 1.5 ns
FSMC_CLK high to FSMC_NOE high
THCLK + 1.5
ns
ns
ns
ns
ns
FSMC_D[15:0] valid data before FSMC_CLK high 6.5
FSMC_D[15:0] valid data after FSMC_CLK high
7
7
2
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 28. Synchronous non-multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
t
t
d(CLKL-NExL)
FSMC_NEx
d(CLKH-NExH)
Data latency = 1
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FSMC_NADV
FSMC_A[25:0]
FSMC_NWE
t
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
d(CLKL-NWEL)
t
d(CLKH-NWEH)
t
d(CLKL-Data)
d(CLKL-Data)
FSMC_D[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NBL
t
t
d(CLKL-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14993e
(1)(2)
Table 38. Synchronous non-multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Min
27.7
Max Unit
FSMC_CLK period
ns
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
THCLK + 2
4
0
1
6
FSMC_CLK low to FSMC_NADV high
5
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
td(CLKH-AIV)
TCK + 2
td(CLKL-NWEL)
td(CLKH-NWEH)
td(CLKL-Data)
FSMC_CLK high to FSMC_NWE high
THCLK + 1
FSMC_D[15:0] valid data after FSMC_CLK low
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
7
2
1
td(CLKL-NBLH)
1. CL = 15 pF.
FSMC_CLK low to FSMC_NBL high
2. Based on characterization, not tested in production.
66/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
PC Card/CompactFlash controller waveforms and timings
Figure 29 through Figure 34 represent synchronous waveforms and Table 39 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
COM.FSMC_SetupTime = 0x04;
COM.FSMC_WaitSetupTime = 0x07;
COM.FSMC_HoldSetupTime = 0x04;
COM.FSMC_HiZSetupTime = 0x00;
ATT.FSMC_SetupTime = 0x04;
ATT.FSMC_WaitSetupTime = 0x07;
ATT.FSMC_HoldSetupTime = 0x04;
ATT.FSMC_HiZSetupTime = 0x00;
IO.FSMC_SetupTime = 0x04;
IO.FSMC_WaitSetupTime = 0x07;
IO.FSMC_HoldSetupTime = 0x04;
IO.FSMC_HiZSetupTime = 0x00;
TCLRSetupTime = 0;
TARSetupTime = 0;
Figure 29. PC Card/CompactFlash controller waveforms for common memory read
access
FSMC_NCE4_2(1)
FSMC_NCE4_1
t
h(NCEx-AI)
t
v(NCEx-A)
FSMC_A[10:0]
t
t
t
h(NCEx-NREG)
h(NCEx-NIORD)
t
t
d(NREG-NCEx)
d(NIORD-NCEx)
h(NCEx-NIOWR
)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
FSMC_NWE
t
t
d(NCE4_1-NOE)
w(NOE)
FSMC_NOE
t
t
h(NOE-D)
su(D-NOE)
FSMC_D[15:0]
ai14895b
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 30. PC Card/CompactFlash controller waveforms for common memory write
access
FSMC_NCE4_1
FSMC_NCE4_2
FSMC_A[10:0]
High
t
t
h(NCE4_1-AI)
v(NCE4_1-A)
t
t
t
h(NCE4_1-NREG)
h(NCE4_1-NIORD)
h(NCE4_1-NIOWR)
t
t
d(NREG-NCE4_1)
d(NIORD-NCE4_1)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
t
t
t
d(NCE4_1-NWE)
w(NWE)
d(NWE-NCE4_1)
FSMC_NWE
FSMC_NOE
MEMxHIZ =1
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FSMC_D[15:0]
ai14896b
68/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read
access
FSMC_NCE4_1
t
t
h(NCE4_1-AI)
v(NCE4_1-A)
FSMC_NCE4_2
FSMC_A[10:0]
High
FSMC_NIOWR
FSMC_NIORD
t
t
h(NCE4_1-NREG)
d(NREG-NCE4_1)
FSMC_NREG
FSMC_NWE
t
t
t
d(NOE-NCE4_1)
d(NCE4_1-NOE)
w(NOE)
FSMC_NOE
t
t
su(D-NOE)
h(NOE-D)
FSMC_D[15:0](1)
ai14897b
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write
access
FSMC_NCE4_1
High
FSMC_NCE4_2
FSMC_A[10:0]
t
t
h(NCE4_1-AI)
v(NCE4_1-A)
FSMC_NIOWR
FSMC_NIORD
t
t
d(NREG-NCE4_1)
h(NCE4_1-NREG)
FSMC_NREG
t
t
d(NCE4_1-NWE)
w(NWE)
FSMC_NWE
t
d(NWE-NCE4_1)
FSMC_NOE
t
v(NWE-D)
FSMC_D[7:0](1)
ai14898b
1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).
Figure 33. PC Card/CompactFlash controller waveforms for I/O space read access
FSMC_NCE4_1
FSMC_NCE4_2
t
t
h(NCE4_1-AI)
v(NCEx-A)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIOWR
t
t
w(NIORD)
t
d(NIORD-NCE4_1)
FSMC_NIORD
t
su(D-NIORD)
d(NIORD-D)
FSMC_D[15:0]
ai14899B
70/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access
FSMC_NCE4_1
FSMC_NCE4_2
t
t
h(NCE4_1-AI)
v(NCEx-A)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIORD
t
t
t
d(NCE4_1-NIOWR)
w(NIOWR)
FSMC_NIOWR
ATTxHIZ =1
t
v(NIOWR-D)
h(NIOWR-D)
FSMC_D[15:0]
ai14900b
(1)(2)
Table 39. Switching characteristics for PC Card/CF read and write cycles
Symbol
Parameter
Min
Max
Unit
FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y =
tv(NCEx-A)
tv(NCE4_1-A)
0...10)
0
5
ns
FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y =
0...10)
FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x =
0...10)
FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x
= 0...10)
th(NCEx-AI)
th(NCE4_1-AI)
2.5
ns
td(NREG-NCEx)
FSMC_NCEx low to FSMC_NREG valid
ns
ns
td(NREG-NCE4_1) FSMC_NCE4_1 low to FSMC_NREG valid
th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid
th(NCE4_1-NREG) FSMC_NCE4_1 high to FSMC_NREG invalid
THCLK + 3
td(NCE4_1-NOE)
tw(NOE)
td(NOE-NCE4_1
tsu(D-NOE)
FSMC_NCE4_1 low to FSMC_NOE low
FSMC_NOE low width
5THCLK + 2
ns
ns
ns
ns
ns
ns
ns
8THCLK –1.5 8THCLK + 1
FSMC_NOE high to FSMC_NCE4_1 high
FSMC_D[15:0] valid data before FSMC_NOE high
FSMC_D[15:0] valid data after FSMC_NOE high
FSMC_NWE low width
5THCLK + 2
25
th(NOE-D)
15
tw(NWE)
8THCLK – 1 8THCLK + 2
5THCLK + 2
td(NWE-NCE4_1)
td(NCE4_1-NWE)
tv(NWE-D)
FSMC_NWE high to FSMC_NCE4_1 high
FSMC_NCE4_1 low to FSMC_NWE low
FSMC_NWE low to FSMC_D[15:0] valid
FSMC_NWE high to FSMC_D[15:0] invalid
5THCLK + 1.5 ns
0
ns
ns
th(NWE-D)
11THCLK
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
(1)(2)
Table 39. Switching characteristics for PC Card/CF read and write cycles
(continued)
Max
Symbol
td(D-NWE)
Parameter
Min
Unit
FSMC_D[15:0] valid before FSMC_NWE high
FSMC_NIOWR low width
13THCLK
ns
ns
ns
ns
tw(NIOWR)
8THCLK + 3
tv(NIOWR-D)
th(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid
FSMC_NIOWR high to FSMC_D[15:0] invalid
5THCLK +1
11THCLK
td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid
5THCLK+3ns ns
ns
th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid
5THCLK – 5
th(NCE4_1-NIOWR) FSMC_NCE4_1 high to FSMC_NIOWR invalid
td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid
5THCLK + 2.5 ns
ns
td(NIORD-NCE4_1) FSMC_NCE4_1 low to FSMC_NIORD valid
th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD invalid
th(NCE4_1-NIORD) FSMC_NCE4_1 high to FSMC_NIORD invalid
5THCLK – 5
tsu(D-NIORD)
td(NIORD-D)
tw(NIORD)
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
FSMC_NIORD low width
4.5
ns
ns
ns
9
8THCLK + 2
1. CL = 15 pF.
2. Based on characterization, not tested in production.
NAND controller waveforms and timings
Figure 35 through Figure 38 represent synchronous waveforms and Table 40 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0;
72/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Figure 35. NAND controller waveforms for read access
Electrical characteristics
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NWE
td(ALE-NOE)
th(NOE-ALE)
FSMC_NOE (NRE)
FSMC_D[15:0]
t
t
su(D-NOE)
h(NOE-D)
ai14901b
Figure 36. NAND controller waveforms for write access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NWE)
th(NWE-ALE)
FSMC_NWE
FSMC_NOE (NRE)
FSMC_D[15:0]
tv(NWE-D)
th(NWE-D)
ai14902b
Figure 37. NAND controller waveforms for common memory read access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE)
th(NOE-ALE)
FSMC_NWE
FSMC_NOE
tw(NOE)
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0]
ai14912b
Doc ID 14610 Rev 7
73/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 38. NAND controller waveforms for common memory write access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE)
tw(NWE)
th(NOE-ALE)
FSMC_NWE
FSMC_NOE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FSMC_D[15:0]
ai14913b
(1)
Table 40. Switching characteristics for NAND Flash read and write cycles
Symbol
Parameter
Min
Max
Unit
(2)
td(D-NWE)
FSMC_D[15:0] valid before FSMC_NWE high
FSMC_NOE low width
6THCLK + 12
ns
(2)
tw(NOE)
4THCLK – 1.5 4THCLK + 1.5 ns
FSMC_D[15:0] valid data before FSMC_NOE
high
(2)
(2)
tsu(D-NOE)
25
ns
th(NOE-D)
FSMC_D[15:0] valid data after FSMC_NOE high 7
ns
(2)
tw(NWE)
FSMC_NWE low width
4THCLK – 1
4THCLK + 2.5 ns
(2)
tv(NWE-D)
FSMC_NWE low to FSMC_D[15:0] valid
FSMC_NWE high to FSMC_D[15:0] invalid
FSMC_ALE valid before FSMC_NWE low
FSMC_NWE high to FSMC_ALE invalid
FSMC_ALE valid before FSMC_NOE low
FSMC_NWE high to FSMC_ALE invalid
0
ns
ns
(2)
th(NWE-D)
td(ALE-NWE)
th(NWE-ALE)
10THCLK + 4
3THCLK + 4.5
3THCLK + 4.5
(3)
(3)
3THCLK + 1.5 ns
ns
(3)
td(ALE-NOE)
th(NOE-ALE)
3THCLK + 2
ns
ns
(3)
1. CL = 15 pF.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
74/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 41. They are based on the EMS levels and classes
defined in application note AN1709.
Table 41. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VDD 3.3 V, LQFP144,
TA +25 °C, fHCLK 36 MHz
conforms to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD3.3 V, LQFP144,
TA +25 °C, fHCLK 36 MHz
conforms to IEC 61000-4-4
VEFTB
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 42. EMI characteristics
Max vs. [fHSE/fHCLK
8/36 MHz
]
Monitored
frequency band
Symbol Parameter
Conditions
Unit
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
8
27
26
4
VDD 3.3 V, TA 25 °C,
LQFP144 package
compliant with
dBµV
-
SEMI
Peak level
IEC 61967-2
5.3.12
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 43. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
Electrostatic discharge
voltage (human body model) to JESD22-A114
TA +25 °C, conforming
VESD(HBM)
2
2000
500
V
Electrostatic discharge
voltage (charge device model) to JESD22-C101
TA +25 °C, conforming
VESD(CDM)
II
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 44. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA +85 °C conforming to JESD78A
II level A
76/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL
compliant.
Table 45. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
–0.5
0.8
V
Standard IO input high level
voltage
TTL ports
2
VDD+0.5
VIH
IO FT(1) input high level voltage
2
5.5V
VIL
VIH
Input low level voltage
–0.5
0.35 VDD
VDD+0.5
CMOS ports
V
Input high level voltage
0.65 VDD
Standard IO Schmitt trigger
voltage hysteresis(2)
200
mV
mV
Vhys
IO FT Schmitt trigger voltage
hysteresis(2)
(3)
5% VDD
VSS VIN VDD
Standard I/Os
1
3
Ilkg
Input leakage current (3)
µA
VIN = 5 V
I/O FT
Weak pull-up equivalent
resistor(4)
RPU
VIN VSS
VIN VDD
30
30
40
50
50
k
Weak pull-down equivalent
resistor(5)
RPD
CIO
40
5
k
I/O pin capacitance
pF
1. FT = Five-volt tolerant.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in
production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required), their
characteristics consider the most strict CMOS-technology or TTL parameters:
●
For V :
IH
–
–
if V is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included
DD
if V is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included
DD
●
For V :
IL
–
–
if V is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included
DD
if V is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included
DD
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed V ).
OL
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 8).
VDD
●
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 8).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 10. All I/Os are CMOS and TTL compliant.
Table 46. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
TTL port,
IIO = +8 mA,
2.7 V < VDD < 3.6 V
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–0.4
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
CMOS port
IIO = +8 mA
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
2.7 V < VDD < 3.6 V
2.4
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
1.3
V
VOL
IIO = +20 mA(3)
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–1.3
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
IIO = +6 mA(3)
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–0.4
VOH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
3. Based on characterization data, not tested in production.
78/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Input/output AC characteristics
Electrical characteristics
The definition and values of input/output AC characteristics are given in Figure 39 and
Table 47, respectively.
Unless otherwise specified, the parameters given in Table 47 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 10.
(1)
Table 47. I/O AC characteristics
MODEx
[1:0] bit Symbol
Parameter
Conditions
Max Unit
value(1)
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 V to 3.6 V
2
MHz
ns
Output high to low level fall
tf(IO)out
time
125(3)
10
01
CL = 50 pF, VDD = 2 V to 3.6 V
CL= 50 pF, VDD = 2 V to 3.6 V
CL= 50 pF, VDD = 2 V to 3.6 V
Output low to high level rise
tr(IO)out
time
125(3)
10
fmax(IO)out Maximum frequency(2)
MHz
ns
Output high to low level fall
tf(IO)out
time
25(3)
Output low to high level rise
tr(IO)out
time
25(3)
CL= 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
50
30
20
MHz
MHz
MHz
Fmax(IO)out Maximum Frequency(2)
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
Output high to low level fall
11
tf(IO)out
time
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
ns
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
Output low to high level rise
tr(IO)out
time
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
Pulse width of external
tEXTIpw signals detected by the
EXTI controller
-
10
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 39.
3. Guaranteed by design, not tested in production.
Doc ID 14610 Rev 7
79/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 39. I/O AC characteristics definition
90%
10 %
50%
50%
90%
10%
t
EXTERNAL
OUTPUT
ON 50pF
t
r(IO)out
r(IO)out
T
Maximum frequency is achieved if (t + t ) 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
ai14131
5.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 45).
PU
Unless otherwise specified, the parameters given in Table 48 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 10.
Table 48. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)
VIL(NRST)
NRST Input low level voltage
NRST Input high level voltage
–0.5
2
0.8
V
(1)
VIH(NRST)
Vhys(NRST)
RPU
VDD+0.5
NRST Schmitt trigger voltage
hysteresis
200
40
mV
Weak pull-up equivalent resistor(2)
VIN VSS
30
50
k
ns
ns
(1)
VF(NRST)
NRST Input filtered pulse
100
(1)
VNF(NRST)
NRST Input not filtered pulse
300
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
Figure 40. Recommended NRST pin protection
V
DD
External
reset circuit(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 µF
STM32F10xxx
ai14132c
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 48. Otherwise the reset will not be taken into account by the device.
80/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.3.15
TIM timer characteristics
The parameters given in Table 49 are guaranteed by design.
Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 49. TIMx characteristics
Symbol
Parameter
Conditions
Min
1
Max
Unit
tTIMxCLK
tres(TIM)
Timer resolution time
fTIMxCLK = 36 MHz
TIMxCLK = 36 MHz
27.8
0
ns
MHz
MHz
bit
f
TIMxCLK/2
18
Timer external clock
frequency on CH1 to CH4
fEXT
f
0
ResTIM
Timer resolution
16
16-bit counter clock period
when internal clock is
selected
tTIMxCLK
1
65536
1820
tCOUNTER
fTIMxCLK = 36 MHz
fTIMxCLK = 36 MHz
0.0278
µs
tTIMxCLK
s
65536 × 65536
119.2
tMAX_COUNT
Maximum possible count
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
5.3.16
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLK1
DD
summarized in Table 10.
2
The STM32F101xC, STM32F101xD and STM32F101xE access line I C interface meets the
2
requirements of the standard I C communication protocol with the following restrictions: t
he
I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-
drain, the PMOS connected between the I/O pin and V is disabled, but is still present.
DD
2
The I C characteristics are described in Table 50. Refer also to
Section 5.3.13: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
Doc ID 14610 Rev 7
81/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
2
Table 50. I C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2)
Unit
Symbol Parameter
Min
Max
Min
Max
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
1.3
0.6
100
0(4)
µs
ns
250
0(3)
th(SDA)
SDA data hold time
900(3)
300
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
300
20+0.1Cb
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
300
th(STA)
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
µs
Repeated Start condition setup
time
tsu(STA)
tsu(STO) Stop condition setup time
µs
µs
pF
Stop to Start condition time (bus
tw(STO:STA)
free)
Cb
Capacitive load for each bus line
400
400
Guaranteed by design, not tested in production.
1.
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
82/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
2
(1)
Figure 41. I C bus AC waveforms and measurement circuit
V
V
DD
DD
STM32F10xxx
4.7kΩ
4.7kΩ
100 Ω
100 Ω
SDA
SCL
I²C bus
START REPEATED
START
START
t
su(STA)
SDA
t
t
t
r(SDA)
f(SDA)
su(SDA)
t
su(STA:STO)
STOP
t
t
t
w(SCKL)
h(SDA)
h(STA)
SCL
t
t
t
su(STO)
r(SCK)
t
f(SCK)
w(SCKH)
ai14127c
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
(1)(2)
Table 51. SCL frequency (f
= 36 MHz, VDD = 3.3 V)
PCLK1
I2C_CCR value
fSCL
(kHz)
RP = 4.7 k
400
300
200
100
50
0x801E
0x8028
0x803C
0x00B4
0x0168
0x0384
20
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
Doc ID 14610 Rev 7
83/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLKx
DD
summarized in Table 10.
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
(1)
Table 52. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
%
SPI slave input clock duty
cycle
DuCy(SCK)
Slave mode
30
70
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4tPCLK
2tPCLK
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
50
60
(2)
(2)
Master mode
Slave mode
Master mode
Slave mode
5
5
5
4
0
2
tsu(MI)
tsu(SI)
(2)
(2)
th(MI)
Data input hold time
ns
(2)
th(SI)
(2)(3)
ta(SO)
Data output access time Slave mode, fPCLK = 20 MHz
Data output disable time Slave mode
3tPCLK
10
(2)(4)
tdis(SO)
(2)(1)
tv(SO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
25
(2)(1)
tv(MO)
5
(2)
th(SO)
15
2
Data output hold time
(2)
th(MO)
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
84/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Figure 42. SPI timing diagram - slave mode and CPHA=0
NSS input
Electrical characteristics
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 43. SPI timing diagram - slave mode and CPHA=1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
Doc ID 14610 Rev 7
85/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
(1)
Figure 44. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
BIT6 IN
LSB IN
t
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 10.
Note:
It is recommended to perform a calibration after each power-up.
86/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Table 53. ADC characteristics
Electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA Power supply
2.4
2.4
3.6
V
V
VREF+ Positive reference voltage
VDDA
Current on the VREF input
IVREF
pin
160(1) 220(1)
µA
fADC
ADC clock frequency
Sampling rate
0.6
14
1
MHz
MHz
(2)
0.05
fS
f
ADC = 14 MHz
823
17
kHz
(2)
External trigger frequency
Conversion voltage range(3)
fTRIG
1/fADC
0 (VSSA or VREF-
tied to ground)
VAIN
VREF+
V
See Equation
1 andTable 54
for details
(2)
RAIN
External input impedance
Sampling switch resistance
50
k
(2)
(2)
1
8
k
RADC
Internal sample and hold
capacitor
pF
CADC
f
ADC = 14 MHz
5.9
83
µs
1/fADC
µs
(2)
Calibration time
tCAL
fADC = 14 MHz
fADC = 14 MHz
0.214
3(4)
Injection trigger conversion
latency
(2)
tlat
1/fADC
µs
0.143
2(4)
Regular trigger conversion
latency
(2)
tlatr
1/fADC
µs
f
f
ADC = 14 MHz
ADC = 14 MHz
0.107
1.5
0
17.1
(2)
Sampling time
Power-up time
tS
239.5 1/fADC
(2)
tSTAB
0
1
µs
µs
1
18
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package. Refer to Section 3: Pinouts and pin descriptions for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 53.
Equation 1: R
max formula:
AIN
TS
RAIN ------------------------------------------------------------- – RADC
fADC CADC ln2N + 2
Doc ID 14610 Rev 7
87/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
(1)
Table 54.
R
max for f
= 14 MHz
AIN
ADC
Ts (cycles)
tS (µs)
RAIN max (k)
1.5
0.11
0.4
7.5
0.54
0.96
2.04
2.96
3.96
5.11
17.1
5.9
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Guaranteed by design, not tested in production.
(1)(2)
Table 55. ADC accuracy - limited test conditions
Symbol
Parameter
Test conditions
Typ
Max(3)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
1.3
1
2
fPCLK2 = 28 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 3 V to 3.6 V, TA = 25 °C
1.5
1.5
1
Gain error
0.5
0.7
0.8
LSB
Measurements made after
ADC calibration
VREF+ = VDDA
Differential linearity error
Integral linearity error
1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.13 does not
affect the ADC accuracy.
3. Based on characterization, not tested in production.
88/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
(1) (2)(3)
Table 56. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
2
5
2.5
3
fPCLK2 = 28 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 2.4 V to 3.6 V
1.5
1.5
1
Gain error
LSB
Measurements made after
ADC calibration
Differential linearity error
Integral linearity error
2
1.5
3
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
3. ADC accuracy vs. negative injection current: Injecting negative current on any of the standard (non-robust)
analog input pins should be avoided as this significantly reduces the accuracy of the conversion being
performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard
analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.13 does not
affect the ADC accuracy.
4. Based on characterization, not tested in production.
Figure 45. ADC accuracy characteristics
V
V
DDA
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
4096
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4095
4094
4093
(3) End point correlation line
(2)
ET=Total Unadjusted Error: maximum deviation
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
(1)
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
ED
1 LSBIDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
VSSA
ai14395b
Doc ID 14610 Rev 7
89/106
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 46. Typical connection diagram using the ADC
STM32F10xxx
V
DD
Sample and hold ADC
V
0.6 V
T
converter
(1)
C
(1)
R
R
AIN
ADC
AINx
12-bit
converter
V
T
V
AIN
0.6 V
C
(1)
ADC
parasitic
I
1 µA
L
ai14139d
1. Refer to Table 53 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 47 or Figure 48,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 47. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
STM32F10xxx
V
REF+
DDA
1 µF // 10 nF
V
V
1 µF // 10 nF
/V
SSA REF-
ai14380b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
90/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 48. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32F10xxx
VREF+/VDDA
1 µF // 10 nF
VREF–/VSSA
ai14381b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
5.3.18
DAC electrical specifications
Table 57. DAC characteristics
Symbol
Parameter
Min
2.4
Typ
Max(1)
Unit
Comments
VDDA
Analog supply voltage
3.6
V
VREF+ must always be below
VDDA
VREF+
Reference supply voltage
2.4
3.6
0
V
VSSA
Ground
0
5
V
(2)
RLOAD
Resistive load with buffer ON
k
When the buffer is OFF, the
minimum resistive load
between DAC_OUT and VSS to
have a 1% accuracy is 1.5 M
Impedance output with buffer
OFF
(2)
RO
15
50
k
Maximum capacitive load at
DAC_OUT pin (when the buffer
is ON).
(2)
CLOAD
Capacitive load
pF
V
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x155) and
(0xEAB) at VREF+ = 2.4 V.
DAC_OUT
min(2)
Lower DAC_OUT voltage with
buffer ON
0.2
DAC_OUT
max(2)
Higher DAC_OUT voltage with
buffer ON
VDDA – 0.2
V
DAC_OUT
min(2)
Lower DAC_OUT voltage with
buffer OFF
0.5
mV
It gives the maximum output
excursion of the DAC.
DAC_OUT
max(2)
Higher DAC_OUT voltage with
buffer OFF
VREF+ – 1LSB V
Doc ID 14610 Rev 7
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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Table 57. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max(1)
Unit
Comments
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs.
DAC DC current consumption
in quiescent mode (Standby
mode)
IDDVREF+
220
380
480
µA
With no load, middle code
(0x800) on the inputs.
µA
µA
DAC DC current consumption
in quiescent mode (Standby
mode)
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs.
IDDA
Given for the DAC in 10-bit
configuration.
0.5
LSB
Differential non linearity
Difference between two
consecutive code-1LSB)
DNL(3)
Given for the DAC in 12-bit
configuration.
2
1
LSB
LSB
Integral non linearity (difference
between measured value at
Code i and the value at Code i
on a line drawn between Code
0 and last Code 1023)
Given for the DAC in 10-bit
configuration.
INL(3)
Given for the DAC in 12-bit
configuration.
4
LSB
Given for the DAC in 12-bit
configuration.
10
3
mV
LSB
LSB
%
Offset error
Given for the DAC in 10-bit at
VREF+ = 3.6 V.
(difference between measured
value at Code (0x800) and the
ideal value = VREF+/2)
Offset(3)
Given for the DAC in 12-bit at
12
0.5
VREF+ = 3.6 V.
Given for the DAC in 12bit
configuration.
Gain error(3) Gain error
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final value
1LSB
(3)
tSETTLING
3
4
1
µs
CLOAD 50 pF, RLOAD 5 k
Max frequency for a correct
DAC_OUT change when small
variation in the input code (from
code i to i+1LSB)
Update rate(3)
MS/s CLOAD 50 pF, RLOAD 5 k
CLOAD 50 pF, RLOAD 5 k
Wakeup time from off state
(Setting the ENx bit in the DAC
Control register)
(3)
tWAKEUP
6.5
10
µs
input code between lowest and
highest possible ones.
Power supply rejection ratio (to
VDDA) (static DC measurement
PSRR+ (2)
–67
–40
dB
No RLOAD, CLOAD = 50 pF
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Guaranteed by characterization, not tested in production.
92/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Figure 49. 12-bit buffered /non-buffered DAC
Electrical characteristics
Buffered/Non-buffered DAC
Buffer(1)
R
LOAD
DACx_OUT
12-bit
digital to
analog
converter
C
LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
5.3.19
Temperature sensor characteristics
Table 58. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
1
4.3
2
4.6
1.52
10
°C
mV/°C
V
Avg_Slope(1) Average slope
4.0
1.34
4
(1)
V25
Voltage at 25°C
Startup time
1.43
(2)
tSTART
µs
ADC sampling time when reading the
temperature
(3)(2)
TS_temp
17.1
µs
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
Doc ID 14610 Rev 7
93/106
Package characteristics
STM32F101xC, STM32F101xD, STM32F101xE
6
Package characteristics
6.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 50. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
Dpad
0.37 mm
0.52 mm typ. (depends on solder mask
registration tolerance
Dsm
Solder paste
0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
ai15469
94/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Package characteristics
Figure 51. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline
Seating plane
C
A2
A4
ddd
C
A
A3
A1
B
D
D1
A
e
F
M
F
E1
E
e
Øb (144 balls)
Ball A1
C
A
B
M
Øeee
Ø fff
M
C
X3_ME
1. Drawing is not to scale.
Table 59. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package data
millimeters
inches(1)
Symbol
Min
Typ
Max
Typ
Min
Max
A
A1
A2
A3
A4
b
1.70
0.0669
0.21
0.0083
1.07
0.27
0.0421
0.0106
0.85
0.45
0.0335
0.0177
0.3996
0.35
9.85
0.40
10.00
8.80
10.00
8.80
0.80
0.60
0.10
0.15
0.08
0.0138
0.3878
0.0157
0.3937
0.3465
0.3937
0.3465
0.0315
0.0236
0.0039
0.0059
0.0031
D
10.15
D1
E
9.85
10.15
0.3878
0.3996
E1
e
F
ddd
eee
fff
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 14610 Rev 7
95/106
Package characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 52. LQFP144, 20 x 20 mm, 144-pin thin quad flat
Figure 53. Recommended
(1)
(1)(2)
package outline
footprint
Seating plane
C
A
A2 A1
c
b
0.25 mm
gage plane
1.35
73
108
ccc
C
D
109
72
0.35
k
D1
A1
0.5
D3
L
108
73
L1
17.85
22.6
19.9
72
109
144
37
E1
E
1
36
E3
19.9
22.6
ai149
144
37
Pin 1
identification
1
36
e
ME_1A
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 60. LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
0.063
0.0059
0.0571
0.0106
0.0079
0.874
0.05
1.35
0.002
0.0531
0.0067
0.0035
0.8583
0.7795
1.40
0.22
1.45
0.0551
0.0087
0.17
0.27
c
0.09
0.20
D
21.80
19.80
22.00
20.00
17.50
22.00
20.00
17.50
0.50
22.20
20.20
0.8661
0.7874
0.689
D1
D3
E
0.7953
21.80
19.80
22.20
20.20
0.8583
0.7795
0.8661
0.7874
0.689
0.874
E1
E3
e
0.7953
0.0197
0.0236
0.0394
3.5°
L
0.45
0°
0.60
0.75
7°
0.0177
0°
0.0295
7°
L1
k
1.00
3.5°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
96/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Package characteristics
(1)(2)
Figure 54. LQFP100 – 14 x 14 mm, 100-pin low-profile Figure 55. Recommended footprint
(1)
quad flat package outline
0.25 mm
0.10 inch
GAGE PLANE
k
75
51
D
L
D1
76
50
0.5
L1
D3
51
75
C
0.3
76
50
16.7 14.3
b
E3 E1
E
100
26
1.2
1
25
100
26
12.3
16.7
Pin 1
1
25
ccc
C
identification
ai14906b
e
A1
A2
A
SEATING PLANE
C
1L_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 61. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
0.063
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
0.05
1.35
0.002
0.0531
0.0067
0.0035
0.622
1.40
0.22
1.45
0.0551
0.0087
0.17
0.27
c
0.09
0.20
D
15.80
13.80
16.00
14.00
12.00
16.00
14.00
12.00
0.50
16.20
14.20
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
0.5433
15.80
13.80
16.20
14.20
0.622
0.6378
0.5591
E1
E3
e
0.5433
L
0.45
0°
0.60
0.75
7°
0.0177
0°
0.0295
7°
L1
k
1.00
3.5°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 14610 Rev 7
97/106
Package characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 56. LQFP64 – 10 x 10 mm, 64 pin low-profile quad Figure 57. Recommended
(1)
(1)(2)
flat package outline
footprint
A
A2
48
33
A1
0.3
49
32
0.5
b
e
E
E1
12.7
10.3
10.3
64
17
1.2
1
16
7.8
D1
D
c
12.7
L1
ai14909
L
ai14398b
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 62. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
0.0630
0.0059
0.0571
0.0106
0.0079
0.05
1.35
0.17
0.09
0.0020
0.0531
0.0067
0.0035
1.40
0.22
0.0551
0.0087
c
D
12.00
10.00
12.00
10.00
0.50
0.4724
0.3937
0.4724
0.3937
0.0197
3.5°
D1
E
E1
e
0°
3.5°
7°
0°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0394
0.0295
L1
1.00
Number of pins
64
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
98/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Package characteristics
6.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 10: General operating conditions on page 38.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × )
J
A
D
JA
Where:
●
●
●
●
T max is the maximum ambient temperature in °C,
A
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = (V × I ) + ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 63. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm / 0.5 mm pitch
30
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
JA
46
45
°C/W
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
6.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Doc ID 14610 Rev 7
99/106
Package characteristics
STM32F101xC, STM32F101xD, STM32F101xE
6.2.2
Evaluating the maximum junction temperature for an application
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 64: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).
The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F10xxx junction temperature range.
Example: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
mode at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Thus: P
= 447 mW
Dmax
Using the values obtained in Table 64 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
Jmax
This is within the junction temperature range of the STM32F10xxx (–40 < T < 105 °C).
J
Figure 58. LQFP64 P max vs. T
D
A
700
600
500
400
300
200
100
0
Suffix 6
65
75
85
95
105
115
TA (°C)
100/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Part numbering
7
Part numbering
Table 64. Ordering information scheme
Example:
STM32 F 101 R
C
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
101 = access line
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Flash memory size
C = 256 Kbytes of Flash memory
D = 384 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
Options
xxx = programmed parts
TR = tape and real
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 14610 Rev 7
101/106
Revision history
STM32F101xC, STM32F101xD, STM32F101xE
8
Revision history
Table 65. Document revision history
Date
Revision
Changes
07-Apr-2008
1
Initial release.
Document status promoted from Target Specification to Preliminary
Data.
Section 1: Introduction and Section 2.2: Full compatibility throughout
the family modified. Small text changes.
Note 1 added in Table 2: STM32F101xC, STM32F101xD and
STM32F101xE features and peripheral counts on page 11.
LQPF100/BGA100 column added to Table 6: FSMC pin definition on
page 31.
22-May-2008
2
Values added to Maximum current consumption on page 40 (see
Table 14, Table 15, Table 16 and Table 17).
Values added to Typical current consumption on page 46 (see Table 18,
Table 19 and Table 20 and see Figure 11, Figure 12, Figure 14,
Figure 15 and Figure 16). Table 19: Typical current consumption in
Standby mode removed.
Figure 53: Recommended footprint(1) on page 96 corrected.
Equation 1 corrected. Section 6.2.2: Evaluating the maximum junction
temperature for an application on page 100 added.
Document status promoted from Preliminary Data to full datasheet.
FSMC (flexible static memory controller) on page 15 modified.
Power supply supervisor on page 17 modified and VDDA added to
Table 10: General operating conditions on page 38.
Table notes revised in Section 5: Electrical characteristics.
Capacitance modified in Figure 9: Power supply scheme on page 35.
Table 51: SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) updated.
Table 52: SPI characteristics modified, th(NSS) modified in Figure 42:
SPI timing diagram - slave mode and CPHA=0 on page 85.
Minimum SDA and SCL fall time value for Fast mode removed from
Table 50: I2C characteristics on page 82, note 1 modified.
IDD_VBAT values added to Table 17: Typical and maximum current
consumptions in Stop and Standby modes on page 43.
21-Jul-2008
3
Table 30: Flash memory endurance and data retention on page 56
updated.
fHCLK corrected in Table 41: EMS characteristics.
tsu(NSS) modified in Table 52: SPI characteristics.
EO corrected in Table 56: ADC accuracy on page 89. fPCLK2 corrected
in Table 55: ADC accuracy - limited test conditions and Table 56: ADC
accuracy.
Figure 46: Typical connection diagram using the ADC on page 90 and
note below corrected.
Typical TS_temp value removed from Table 58: TS characteristics on
page 93.
Section 6.1: Package mechanical data on page 94 updated.
Small text changes.
102/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Table 65. Document revision history (continued)
Revision history
Date
Revision
Changes
General-purpose timers (TIMx) on page 19 updated. Table 3:
STM32F101xx family updated to show the low-density family.
Table 4: Timer feature comparison added
Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access
line block diagram updated.
Note 9 added, main function after reset and Note 5 updated in Table 5:
High-density STM32F101xx pin definitions.
Note 2 modified below Table 7: Voltage characteristics on page 36,
|VDDx| min and |VDDx| min removed.
Measurement conditions specified in Section 5.3.5: Supply current
characteristics on page 40.
12-Dec-2008
4
General input/output characteristics on page 77 modified.
Max values at TA = 85 °C updated in Table 17: Typical and maximum
current consumptions in Stop and Standby modes on page 43.
Section 5.3.10: FSMC characteristics on page 56 revised.
Values added to Table 42: EMI characteristics on page 76.
IVREF added to Table 53: ADC characteristics on page 87.
Table 63: Package thermal characteristics on page 99 updated.
Small text changes.
Doc ID 14610 Rev 7
103/106
Revision history
STM32F101xC, STM32F101xD, STM32F101xE
Table 65. Document revision history (continued)
Date
Revision
Changes
I/O information clarified on page 1. Number of ADC peripherals
corrected in Table 2: STM32F101xC, STM32F101xD and
STM32F101xE features and peripheral counts.
In Table 5: High-density STM32F101xx pin definitions:
– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15
updated
– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column.
PG14 pin description modified in Table 6: FSMC pin definition.
Figure 6: Memory map on page 33 modified.
Note modified in Table 14: Maximum current consumption in Run mode,
code with data processing running from Flash and Table 16: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
Figure 14, Figure 15 and Figure 16 show typical curves (titles
changed).
Table 21: High-speed external user clock characteristics and Table 22:
Low-speed user external clock characteristics modified.
ACCHSI max values modified in Table 25: HSI oscillator characteristics
30-Mar-2009
5
FSMC configuration modified for Asynchronous waveforms and timings.
Notes modified below Figure 21: Asynchronous non-multiplexed
SRAM/PSRAM/NOR read waveforms and Figure 22: Asynchronous
non-multiplexed SRAM/PSRAM/NOR write waveforms.
tw(NADV) values modified in Table 31: Asynchronous non-multiplexed
SRAM/PSRAM/NOR read timings and Table 34: Asynchronous
multiplexed NOR/PSRAM write timings. th(Data_NWE) modified in
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings.
In Table 36: Synchronous multiplexed PSRAM write timings and
Table 38: Synchronous non-multiplexed PSRAM write timings:
– tv(Data-CLK) renamed as td(CLKL-Data)
– td(CLKL-Data) min value removed and max value added
– th(CLKL-DV) / th(CLKL-ADV) removed
Figure 25: Synchronous multiplexed NOR/PSRAM read timings,
Figure 26: Synchronous multiplexed PSRAM write timings and
Figure 28: Synchronous non-multiplexed PSRAM write timings
modified. Small text changes.
104/106
Doc ID 14610 Rev 7
STM32F101xC, STM32F101xD, STM32F101xE
Table 65. Document revision history (continued)
Revision history
Date
Revision
Changes
Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access
line block diagram modified.
Note 5 updated and Note 4 added in Table 5: High-density
STM32F101xx pin definitions.
VRERINT and TCoeff added to Table 13: Embedded internal reference
voltage.
fHSE_ext min modified in Table 21: High-speed external user clock
characteristics.
Table 23: HSE 4-16 MHz oscillator characteristics modified. Note 1
modified below Figure 19: Typical application with an 8 MHz crystal.
Figure 40: Recommended NRST pin protection modified. CL1 and CL2
replaced by C in Table 23: HSE 4-16 MHz oscillator characteristics and
Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz), notes
modified and moved below the tables.
Table 25: HSI oscillator characteristics modified. Conditions removed
from Table 27: Low-power mode wakeup timings.
Jitter added to Table 28: PLL characteristics.
21-Jul-2009
6
In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read
timings: th(BL_NOE) and th(A_NOE) modified.
In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings: th(A_NWE) and th(Data_NWE) modified.
In Table 33: Asynchronous multiplexed NOR/PSRAM read timings:
th(AD_NADV) and th(A_NOE) modified.
In Table 34: Asynchronous multiplexed NOR/PSRAM write timings:
th(A_NWE) modified.
In Table 35: Synchronous multiplexed NOR/PSRAM read timings:
th(CLKH-NWAITV) modified.
In Table 40: Switching characteristics for NAND Flash read and write
cycles: th(NOE-D) modified.
Table 52: SPI characteristics modified.
CADC and RAIN parameters modified in Table 53: ADC characteristics.
RAIN max values modified in Table 54: RAIN max for fADC = 14 MHz.
Table 57: DAC characteristics modified. Figure 49: 12-bit buffered /non-
buffered DAC added.
Number of DACs corrected in Table 3: STM32F101xx family.
IDD_VBAT updated in Table 17: Typical and maximum current
consumptions in Stop and Standby modes.
Figure 13: Typical current consumption on VBAT with RTC on vs.
temperature at different VBAT values added.
24-Sep-2009
7
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.11: EMC characteristics on page 75.
Table 57: DAC characteristics modified.
Small text changes.
Doc ID 14610 Rev 7
105/106
STM32F101xC, STM32F101xD, STM32F101xE
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