STM32F101T4U6_技术文档

STM32F101x4

STM32F101x6

Low-density access line, ARM-based 32-bit MCU with

16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 36 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

LQFP64

10 x 10 mm

LQFP48

7 x 7 mm

VFQFPN48

7 × 7 mm

VFQFPN36

6 × 6 mm

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

■

Up to 5 timers

–

Up to two16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

■ Memories

– 2 watchdog timers (Independent and

Window)

– 16 to 32 Kbytes of Flash memory

– 4 to 6 Kbytes of SRAM

– SysTick timer: 24-bit downcounter

■ Clock, reset and supply management

■ Up to 4 communication interfaces

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

2

– 1 x I C interface (SMBus/PMBus)

– Up to 2 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– 1 × SPI (18 Mbit/s)

■ CRC calculation unit, 96-bit unique ID

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

®

■ ECOPACK packages

Table 1.

Device summary

Part number

STM32F101C4,

■ Low power

– Sleep, Stop and Standby modes

Reference

– V

supply for RTC and backup registers

BAT

STM32F101x4

STM32F101R4,

STM32F101T4

■ Debug mode

– Serial wire debug (SWD) and JTAG

interfaces

STM32F101C6,

STM32F101R6,

STM32F101T6

STM32F101x6

■ DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

2

I Cs and USARTs

■ 1 × 12-bit, 1 µs A/D converter (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Temperature sensor

■ Up to 51 fast I/O ports

– 26/37/51 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

April 2011

Doc ID 15058 Rev 5

1/79

www.st.com

1

Contents

STM32F101x4, STM32F101x6

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

2.2

2.3

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

®

2.3.1

2.3.2

2.3.3

2.3.4

2.3.5

2.3.6

2.3.7

2.3.8

2.3.9

ARM Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15

External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18

2.3.15 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.16 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.18 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

²

2.3.19 I C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . 19

2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.23 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20

3

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Contents

4

5

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2

5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 31

Embedded reset and power control block characteristics . . . . . . . . . . . 31

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 50

5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.1

6.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.2.1

6.2.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Evaluating the maximum junction temperature for an application . . . . . 75

Doc ID 15058 Rev 5

3/79

Contents

STM32F101x4, STM32F101x6

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7

8

4/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Low-density STM32F101xx device features and peripheral counts . . . . . . . . . . . . . . . . . . 11

STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Low-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 32

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Maximum current consumption in Sleep mode, code running from Flash

Table 13.

Table 14.

or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 36

Typical current consumption in Run mode, code with data processing

Table 15.

Table 16.

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 40

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

LSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

SCL frequency (f

= MHz, V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

PCLK1

DD

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

R

max for f

= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

AIN

ADC

ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Doc ID 15058 Rev 5

5/79

List of tables

STM32F101x4, STM32F101x6

Table 45.

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 70

VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 71

LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 72

LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 73

Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

STM32F101xx Low-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

STM32F101xx Low-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 21

STM32F101xx Low-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 21

STM32F101xx Low-density access line VFQPFN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . 22

STM32F101xx Low-density access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . 22

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 35

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 35

Figure 14. Typical current consumption on V

with RTC on versus temperature at different

BAT

V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

BAT

Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DD

Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus

temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DD

Figure 17. Typical current consumption in Standby mode versus temperature at V = 3.3 V and

DD

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 22. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 23. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 24. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2

(1)

Figure 28. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

(1)

Figure 30. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 31. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

(1)

Figure 32. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 33. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 34. Power supply and reference decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 35. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline

Figure 36. Recommended footprint (dimensions in mm)

Figure 37. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline

Figure 38. Recommended footprint (dimensions in mm)

(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 72

(1)

Figure 40. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 41. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Doc ID 15058 Rev 5

7/79

List of figures

STM32F101x4, STM32F101x6

(1)

Figure 42. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 43. LQFP64 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

D

A

8/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Introduction

1

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F101x4 and STM32F101x6 low-density access line microcontrollers. For more

details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2:

Full compatibility throughout the family.

The Low-density STM32F101xx datasheet should be read in conjunction with the low-,

medium- and high-density STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Doc ID 15058 Rev 5

9/79

Description

STM32F101x4, STM32F101x6

2

Description

The STM32F101x4 and STM32F101x6 Low-density access line family incorporates the

high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency,

high-speed embedded memories (Flash memory of 16 to 32 Kbytes and SRAM of 4 to 6

Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB

2

buses. All devices offer standard communication interfaces (one I C, one SPI, and two

USARTs), one 12-bit ADC and up to two general-purpose 16-bit timers.

The STM32F101xx Low-density access line family operates in the –40 to +85 °C

temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving

mode allows the design of low-power applications.

The STM32F101xx Low-density access line family includes devices in three different

packages ranging from 36 pins to 64 pins. Depending on the device chosen, different sets of

peripherals are included, the description below gives an overview of the complete range of

peripherals proposed in this family.

These features make the STM32F101xx Low-density access line microcontroller family

suitable for a wide range of applications such as application control and user interface,

medical and handheld equipment, PC peripherals, gaming and GPS platforms, industrial

applications, PLCs, inverters, printers, scanners, alarm systems, Video intercoms, and

HVACs.

10/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Description

2.1

Device overview

Figure 1 shows the general block diagram of the device family.

Table 2.

Low-density STM32F101xx device features and peripheral counts

STM32F101Tx STM32F101Cx STM32F101Rx

Peripheral

Flash - Kbytes

SRAM - Kbytes

16

4

32

6

16

4

32

6

16

4

32

6

General-purpose

2

SPI

I²C

1

USART

2

12-bit synchronized ADC

number of channels

1

10 channels

16 channels

GPIOs

26

37

51

CPU frequency

Operating voltage

36 MHz

2.0 to 3.6 V

Ambient temperature: –40 to +85 °C (see Table 8)

Junction temperature: –40 to +105 °C (see Table 8)

Operating temperatures

Packages

LQFP48,

VFQFPN36

LQFP64

VFQFPN48

Doc ID 15058 Rev 5

11/79

Description

STM32F101x4, STM32F101x6

Figure 1.

STM32F101xx Low-density access line block diagram

TRACECLK

TRACED[0:3]

as AS

TPIU

Trace

controller

Trace/trig

SWD

pbus

POWER

SW/JTAG

NJTRST

JTDI

JTCK/SWCLK

JTMS/SWDIO

V

= 2 to 3.6 V

DD

V_SS

VOLT. REG.

3.3V TO 1.8V

Ibus

Cortex M3 CPU

Flash 32 KB

64 bit

JTDO

as AF

@VDD

F_max: 3 6M Hz

Dbus

NVIC

SRAM

6 KB

NVIC

System

@VDD

OSC_IN

OSC_OUT

PCLK1

PCLK2

HCLK

FCLK

PLL &

XTAL OSC

4-16 MHz

GP DMA

CLOCK

MANAGT

7 channels

RC 8 MHz

RC 42 kHz

@VDDA

IWDG

@VDDA

Stand by

interface

SUPPLY

SUPERVISION

V_BAT

NRST

VDDA

VSSA

@VBAT

Rst

POR / PDR

OSC32_IN

OSC32_OUT

XTAL 32 kHz

Backup

Int

PVD

RTC

AWU

AHB2

APB2

AHB2

APB1

TAMPER-RTC

reg

Backu p interface

EXTI

80AF

WAKEUP

4 Channels

TIM2

PA[15:0]

PB[15:0]

PC[15:0]

PD[3:0]

GPIOA

GPIOB

GPIOC

GPIOD

TIM3

RX,TX, CTS, RTS,

CK, SmartCard as AF

USART2

I2C

SCL,SDA,SMBA

as AF

W W D G

MOSI,MISO,

SCK,NSS as AF

SPI

RX,TX, CTS, RTS,

Smartcard as AF

USART1

@VDDA

12bit ADC

IF

16AF

Temp sensor

ai15173c

1. AF = alternate function on I/O port pin.

2. T_A= –40 °C to +85 °C (junction temperature up to 105 °C).

12/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Figure 2. Clock tree

Description

8 MHz

HSI RC

HSI

/2

HCLK

36 MHz max

Clock

to AHB bus, core,

memory and DMA

Enable (3 bits)

to Cortex System timer

/8

SW

PLLSRC

FCLK Cortex

free running clock

36 MHz max

PLLMUL

HSI

AHB

Prescaler

/1, 2..512

APB1

Prescaler

/1, 2, 4, 8, 16

SYSCLK

..., x16

x2, x3, x4

PLL

PCLK1

PLLCLK

HSE

36 MHz

max

to APB1

peripherals

Peripheral Clock

Enable (13 bits)

to TIM2, TIM3

TIMXCLK

Peripheral Clock

Enable (3 bits)

TIM2, TIM3

If (APB1 prescaler =1) x1

else x2

CSS

APB2

Prescaler

/1, 2, 4, 8, 16

PLLXTPRE

/2

36 MHz max

PCLK2

to APB2

OSC_OUT

peripherals

4-16 MHz

HSE OSC

Peripheral Clock

Enable (11 bits)

OSC_IN

ADC

to ADC

Prescaler

/2, 4, 6, 8

ADCCLK

/128

LSE

OSC32_IN

to RTC

LSE OSC

RTCCLK

32.768 kHz

OSC32_OUT

RTCSEL[1:0]

to Independent Watchdog (IWDG)

IWDGCLK

LSI

LSI RC

40 kHz

Legend:

HSE = high-speed external clock signal

HSI = high-speed internal clock signal

LSI = low-speed internal clock signal

LSE = low-speed external clock signal

Main

Clock Output

/2

PLLCLK

MCO

HSI

HSE

SYSCLK

MCO

ai15174

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is

36 MHz.

2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

Doc ID 15058 Rev 5

13/79

Description

STM32F101x4, STM32F101x6

2.2

Full compatibility throughout the family

The STM32F101xx is a complete family whose members are fully pin-to-pin, software and

feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are

referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as

medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are

referred to as high-density devices.

Low- and high-density devices are an extension of the STM32F101x8/B devices, they are

specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Low-

density devices feature lower Flash memory and RAM capacities and a timer less. High-

density devices have higher Flash memory and RAM capacities, and additional peripherals

like FSMC and DAC, while remaining fully compatible with the other members of the

STM32F101xx family.

The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE

are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the

user to try different memory densities and providing a greater degree of freedom during the

development cycle.

Moreover, the STM32F101xx performance line family is fully compatible with all existing

STM32F101xx access line and STM32F102xx USB access line devices.

Table 3.

Pinout

STM32F101xx family

Memory size

Low-density devices Medium-density devices

High-density devices

16 KB

Flash

32 KB

64 KB

Flash

128 KB

Flash

256 KB

384 KB

Flash

512 KB

Flash⁽¹⁾

Flash

32 KB

RAM

48 KB

RAM

48 KB

RAM

4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM

144

100

64

5 × USARTs

4 × 16-bit timers, 2 × basic timers

3 × SPIs, 2 × I²Cs, 1 × ADC,

3 × USARTs

2 × DACs, FSMC (100 and 144 pins)

2 × USARTs

2 × 16-bit timers

1 × SPI, 1 × I²C

1 × ADC

3 × 16-bit timers

2 × SPIs, 2 × I2Cs,

1 × ADC

48

36

1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the

reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.

14/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Description

2.3

Overview

®

2.3.1

ARM Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The STM32F101xx Low-density access line family having an embedded ARM core, is

therefore compatible with all ARM tools and software.

2.3.2

2.3.3

Embedded Flash memory

16 or 32 Kbytes of embedded Flash is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

2.3.4

2.3.5

Embedded SRAM

Up to 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

Nested vectored interrupt controller (NVIC)

The STM32F101xx Low-density access line embeds a nested vectored interrupt controller

able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of

Cortex™-M3) and 16 priority levels.

●

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

Doc ID 15058 Rev 5

15/79

Description

STM32F101x4, STM32F101x6

2.3.6

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected

to the 16 external interrupt lines.

2.3.7

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 36 MHz. See Figure 2 for details on the clock tree.

2.3.8

2.3.9

Boot modes

At startup, boot pins are used to select one of three boot options:

●

Boot from User Flash

Boot from System Memory

Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1. For further details please refer to AN2606.

Power supply schemes

●

V

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

DD

Provided externally through V pins.

DD

●

V

, V

= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs

DDA

SSA

and PLL (minimum voltage to be applied to V

is 2.4 V when the ADC is used).

DDA

V

and V

must be connected to V and V , respectively.

DDA

SSA DD SS

●

V

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup

BAT

registers (through power switch) when V is not present.

DD

For more details on how to connect power pins, refer to Figure 10: Power supply scheme.

2.3.10

Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V is below a specified threshold, V

, without the need for an

DD

POR/PDR

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

/V power supply and compares it to the V threshold. An interrupt can be

V

DD DDA

PVD

generated when V /V

drops below the V

threshold and/or when V /V

is higher

DD DDA

PVD

DD DDA

16/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Description

than the V threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 10: Embedded reset and power control block characteristics for the values of

V

and V

.

POR/PDR

PVD

2.3.11

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●

MR is used in the nominal regulation mode (Run)

LPR is used in the Stop mode

Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

2.3.12

Low-power modes

The STM32F101xx Low-density access line supports three low-power modes to achieve the

best compromise between low power consumption, short startup time and available wakeup

sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

●

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output or the RTC alarm.

●

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.13

DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Doc ID 15058 Rev 5

17/79

Description

STM32F101x4, STM32F101x6

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

2

The DMA can be used with the main peripherals: SPI, I C, USART, general purpose timers

TIMx and ADC.

2.3.14

RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

V

supply when present or through the V_BATpin. The backup registers are ten 16-bit

DD

registers used to store 20 bytes of user application data when V power is not present.

DD

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural crystal deviation. The RTC

features a 32-bit programmable counter for long term measurement using the Compare

register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by

default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.15

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to

reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

2.3.16

2.3.17

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It

features:

●

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0.

Programmable clock source

2.3.18

General-purpose timers (TIMx)

There areup to two synchronizable general-purpose timers embedded in the STM32F101xx

Low-density access line devices. These timers are based on a 16-bit auto-reload up/down

counter, a 16-bit prescaler and feature 4 independent channels each for input capture,

18/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Description

output compare, PWM or one pulse mode output. This gives up to 12 input captures / output

compares / PWMs on the largest packages.

The general-purpose timers can work together via the Timer Link feature for synchronization

or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose

timers can be used to generate PWM outputs. They all have independent DMA request

generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

²

2.3.19

I C bus

The I²C bus interface can operate in multimaster and slave modes. It can support standard

and fast modes.

It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.

A hardware CRC generation/verification is embedded.

The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.

2.3.20

2.3.21

Universal synchronous/asynchronous receiver transmitter (USART)

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware

management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816

compliant and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

Serial peripheral interface (SPI)

The SPI interface is able to communicate up to 18 Mbit/s in slave and master modes in full-

duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

The SPI interface can be served by the DMA controller.

2.3.22

2.3.23

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

ADC (analog to digital converter)

The 12-bit analog to digital converter has up to 16 external channels and performs

conversions in single-shot or scan modes. In scan mode, automatic conversion is performed

on a selected group of analog inputs.

The ADC can be served by the DMA controller.

Doc ID 15058 Rev 5

19/79

Description

2.3.24

STM32F101x4, STM32F101x6

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The

conversion range is between 2 V < V

< 3.6 V. The temperature sensor is internally

DDA

connected to the ADC_IN16 input channel which is used to convert the sensor output

voltage into a digital value.

2.3.25

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a

specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

20/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Pinouts and pin description

3

Pinouts and pin description

Figure 3.

STM32F101xx Low-density access line LQFP64 pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

1

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

4

5

6

7

PC0

PC1

PC2

PC3

8

LQFP64

9

10

11

12

13

14

15

16

PC6

VSSA

VDDA

PA0-WKUP

PB15

PB14

PB13

PB12

PA1

PA2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

ai14387b

Figure 4.

STM32F101xx Low-density access line LQFP48 pinout

48 47 46 45 44 43 42 41 40 39 38 37

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

LQFP48

PA8

VSSA

VDDA

PB15

PB14

PB13

PB12

PA0-WKUP 10

PA1 11

12

PA2

24

13 14 15 16 17 18 19 20 21 22 23

ai14378d

Doc ID 15058 Rev 5

21/79

Pinouts and pin description

Figure 5.

STM32F101x4, STM32F101x6

STM32F101xx Low-density access line VFQPFN48 pinout

48 47 46 45 44 43 42 41 40 39 38 37

1

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

36

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

35

34

33

32

31

30

29

28

27

26

25

2

3

4

5

6

VFQFPN48

7

8

PA8

VSSA

VDDA

PA0-WKUP

PA1

9

PB15

PB14

PB13

PB12

10

11

12

PA2

13 14 15 16 17 18 19 20 21 22 23 24

ai18300

Figure 6.

STM32F101xx Low-density access line VFQPFN36 pinout

36 35 34

33 32 31 30 29 28

27

V

1

DD_3

DD_2

SS_2

OSC_IN/PD0

OSC_OUT/PD1

NRST

2

3

4

5

6

7

8

9

26

PA13

PA12

PA11

PA10

PA9

25

24

QFN36

V

23

22

SSA

V

DDA

PA0-WKUP

PA1

21

20

PA8

PA2

V

19

DD_1

10 11 12 13

14 15 16 17

18

ai14654

22/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Pinouts and pin description

Alternate functions⁽³⁾⁽⁴⁾

Table 4.

Pins

Low-density STM32F101xx pin definitions

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

1

2

3

4

5

6

7

-

1

2

-

V_BAT

S

V_BAT

PC13⁽⁶⁾

PC14⁽⁶⁾

PC15⁽⁶⁾

OSC_IN

OSC_OUT

NRST

PC0

PC13-TAMPER-RTC⁽⁵⁾I/O

PC14-OSC32_IN⁽⁵⁾

I/O

PC15-OSC32_OUT⁽⁵⁾I/O

TAMPER-RTC

OSC32_IN

3

-

4

-

OSC32_OUT

5

2

3

4

-

OSC_IN

OSC_OUT

NRST

PC0

I

6

O

7

I/O

S

8

ADC_IN10

ADC_IN11

ADC_IN12

ADC_IN13

-

9

-

PC1

-

10

11

12

13

-

PC2

-

PC3

8

9

5

6

V_SSA

V_DDA

S

V_DDA

WKUP/USART2_CTS/

ADC_IN0/

10 14

7

PA0-WKUP

I/O

PA0

TIM2_CH1_ETR⁽⁷⁾

USART2_RTS/

11 15

12 16

8

9

PA1

PA2

PA3

I/O

PA1

PA2

PA3

ADC_IN1/TIM2_CH2⁽⁷⁾

USART2_TX/

ADC_IN2/TIM2_CH3⁽⁷⁾

USART2_RX/

13 17 10

ADC_IN3/TIM2_CH4⁽⁷⁾

-

18

19

-

V_{SS_4}

V_{DD_4}

S

V_{SS_4}

V_{DD_4}

SPI_NSS⁽⁷⁾/ADC_IN4

USART2_CK

14 20 11

15 21 12

16 22 13

PA4

PA5

PA6

I/O

PA4

PA5

PA6

SPI_SCK⁽⁷⁾/ADC_IN5

SPI_MISO⁽⁷⁾/ADC_IN6/

TIM3_CH1⁽⁷⁾

SPI_MOSI⁽⁷⁾/ADC_IN7/

TIM3_CH2⁽⁷⁾

17 23 14

PA7

I/O

PA7

-

24

25

PC4

PC5

PB0

PB1

I/O

PC4

PC5

PB0

PB1

ADC_IN14

ADC_IN15

18 26 15

19 27 16

ADC_IN8/TIM3_CH3⁽⁷⁾

ADC_IN9/TIM3_CH4⁽⁷⁾

Doc ID 15058 Rev 5

23/79

Pinouts and pin description

STM32F101x4, STM32F101x6

Alternate functions⁽³⁾⁽⁴⁾

Table 4.

Pins

Low-density STM32F101xx pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

20 28 17

PB2

PB10

PB11

V_{SS_1}

V_{DD_1}

PB12

PB13

PB14

PB15

PC6

I/O

S

FT

PB2/BOOT1

PB10

PB11

V_{SS_1}

V_{DD_1}

PB12

PB13

PB14

PB15

PC6

21 29

22 30

-

TIM2_CH3

TIM2_CH4

23 31 18

24 32 19

S

25 33

26 34

27 35

28 36

-

I/O

S

FT

-

37

38

39

40

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

PC7

PC8

-

PC9

29 41 20

30 42 21

31 43 22

32 44 23

33 45 24

34 46 25

35 47 26

36 48 27

37 49 28

PA8

USART1_CK/MCO

USART1_TX⁽⁷⁾

USART1_RX⁽⁷⁾

USART1_CTS

USART1_RTS

PA9

PA10

PA11

PA12

PA13

V_{SS_2}

V_{DD_2}

PA14

PA10

PA11

PA12

FT JTMS-SWDIO

V_{SS_2}

PA13

PA14

S

V_{DD_2}

I/O

FT JTCK/SWCLK

TIM2_CH1_ETR/

PA15 / SPI_NSS

38 50 29

PA15

I/O

FT

JTDI

-

51

52

53

5

PC10

PC11

PC12

PD0

I/O

FT

PC10

PC11

-

PC12

5

6

2

3

-

OSC_IN⁽⁸⁾

OSC_OUT⁽⁸⁾

PD2

6

PD1

54

PD2

TIM3_ETR

TIM2_CH2 / PB3

TRACESWO

SPI_SCK

39 55 30

PB3

I/O

FT

JTDO

24/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Pinouts and pin description

Alternate functions⁽³⁾⁽⁴⁾

Table 4.

Pins

Low-density STM32F101xx pin definitions (continued)

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

TIM3_CH1 / PB4

SPI_MISO

40 56 31

41 57 32

PB4

PB5

I/O

FT

NJTRST

PB5

TIM3_CH2 /

SPI_MOSI

I2C_SMBA

42 58 33

43 59 34

44 60 35

PB6

PB7

I/O

I

FT

PB6

PB7

I2C_SCL⁽⁷⁾

I2C_SDA⁽⁷⁾

USART1_TX

USART1_RX

BOOT0

PB8

BOOT0

PB8

45 61

46 62

-

I/O

S

FT

I2C_SCL

I2C_SDA

PB9

47 63 36

48 64

V_{SS_3}

V_{DD_3}

V_{SS_3}

V_{DD_3}

1

S

1. I = input, O = output, S = supply.

2. FT= 5 V tolerant.

3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower

number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be

called SPI, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should

be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum

load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even

after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com.

7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more

details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available

from the STMicroelectronics website: www.st.com.

8. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as

OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For

more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

Doc ID 15058 Rev 5

25/79

Memory mapping

STM32F101x4, STM32F101x6

4

Memory mapping

The memory map is shown in Figure 7.

Figure 7.

Memory map

APB memory space

0xFFFF FFFF

reserved

0xE010 0000

0xFFFF FFFF

reserved

0x6000 0000

reserved

0x4002 3400

CRC

0x4002 3000

7

reserved

0x4002 2400

0xE010 0000

Cortex-M3 internal

peripherals

Flash interface

0x4002 2000

0xE000 0000

reserved

0x4002 1400

RCC

0x4002 1000

reserved

6

0x4002 0400

DMA

0x4002 0000

reserved

0xC000 0000

0x4001 3C00

USART1

0x4001 3800

reserved

0x4001 3400

5

SPI

0x4001 3000

reserved

0x4001 2C00

0xA000 0000

reserved

0x4001 2800

ADC

0x4001 2400

reserved

0x4001 1800

4

0x1FFF FFFF

0x1FFF F80F

reserved

Port D

0x4001 1400

Port C

0x4001 1000

0x8000 0000

Option Bytes

Port B

0x1FFF F800

0x4001 0C00

Port A

0x4001 0800

System memory

EXTI

3

0x4001 0400

AFIO

0x4001 0000

0x1FFF F000

reserved

0x4000 7400

0x6000 0000

PWR

0x4000 7000

BKP

0x4000 6C00

2

reserved

0x4000 6800

reserved

0x4000 6400

Peripherals

reserved

0x4000 0000

0x4000 6000

reserved

0x4000 5800

I2C

0x4000 5400

1

reserved

USART2

0x4000 4800

0x4000 4400

0x4000 3400

0x4000 3000

0x4000 2C00

SRAM

reserved

0x2000 0000

0x0801 FFFF

IWDG

WWDG

RTC

Flash memory

0

0x4000 2800

0x4000 0800

reserved

TIM3

0x0800 0000

0x0000 0000

0x4000 0400

0x4000 0000

Aliased to Flash or

system memory

depending on

BOOT pins

TIM2

Reserved

ai15175b

26/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

5

Electrical characteristics

5.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

5.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3Σ).

5.1.2

5.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the

A

DD

2 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean 2Σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

5.1.4

5.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

Doc ID 15058 Rev 5

27/79

Electrical characteristics

Figure 8.

STM32F101x4, STM32F101x6

Pin input voltage

Pin loading conditions

Figure 9.

STM32F10xxx pin

C= 50 pF

V

IN

ai14124b

ai14123b

5.1.6

Power supply scheme

Figure 10. Power supply scheme

V

BAT

Backup circuitry

(OSC32K,RTC,

Wakeup logic

Power switch

1.8-3.6V

Backup registers)

OUT

IN

IO

Logic

GP I/Os

Kernel logic

(CPU,

Digital

& Memories)

V

DD

V

DD

1/2/3/4/5

Regulator

5 × 100 nF

+ 1 × 4.7 µF

V

SS

1/2/3/4/5

V

DD

V

DDA

V

REF+

Analog:

RCs, PLL,

...

10 nF

+ 1 µF

ADC

REF-

V

SSA

ai15496

Caution:

In Figure 10, the 4.7 µF capacitor must be connected to V

.

DD3

28/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

5.1.7

Current consumption measurement

Figure 11. Current consumption measurement scheme

I

_V

DD BAT

V

BAT

I

DD

V

DD

V

DDA

ai14126

5.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,

Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device

at these conditions is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Table 5.

Symbol

Voltage characteristics

Ratings

Min

Max

Unit

External main supply voltage (including

V_DD− V_SS

–0.3

4.0

(1)

V_DDAand V_DD

)

V

Input voltage on five volt tolerant pin

Input voltage on any other pin

V_SS− 0.3

V_DD+ 4.0

4.0

(2)

V_IN

|ΔV_DDx

|

Variations between different V_DDpower pins

50

mV

Variations between all the different ground

pins

|V_SSX− V_SS

|

50

seeSection 5.3.11:Absolute

maximum ratings (electrical

sensitivity)

Electrostatic discharge voltage (human body

model)

V_ESD(HBM)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. V_INmaximum must always be respected. Refer to Table 6: Current characteristics for the maximum

allowed injected current values.

Doc ID 15058 Rev 5

29/79

Electrical characteristics

STM32F101x4, STM32F101x6

Table 6.

Symbol

Current characteristics

Ratings

Max.

Unit

I_VDD

I_VSS

Total current into V_DD/V_DDApower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on five volt tolerant pins⁽³⁾

Injected current on any other pin⁽⁴⁾

150

25

I_IO

− 25

-5/+0

5

mA

(2)

I_INJ(PIN)

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁵⁾

25

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC

characteristics.

3. Positive injection is not possible on these I/Os. A negative injection is induced by V_IN<V_SS. I_INJ(PIN)must

never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage

values.

4. A positive injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS. I_INJ(PIN)must

never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage

values.

5. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values).

Table 7.

Thermal characteristics

Ratings

Symbol

Value

Unit

T_STG

T_J

Storage temperature range

–65 to +150

150

°C

Maximum junction temperature

5.3

Operating conditions

5.3.1

General operating conditions

Table 8.

Symbol

General operating conditions

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK1

f_PCLK2

V_DD

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

0

2

36

3.6

MHz

V

Analog operating voltage

(ADC not used)

2

3.6

Must be the same potential

as V_DD

(1)

V_DDA

V

(2)

Analog operating voltage

(ADC used)

2.4

1.8

3.6

V_BAT

Backup operating voltage

30/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

Table 8.

Symbol

General operating conditions (continued)

Parameter

Conditions

Min

Max

Unit

LQFP64

LQFP48

444

363

1000

85

Power dissipation at T_A=

85 °C⁽³⁾

P_D

mW

VFQFPN36

Maximum power dissipation –40

°C

TA

TJ

Ambient temperature

Low power dissipation⁽⁴⁾

–40

105

Junction temperature range

1. When the ADC is used, refer to Table 42: ADC characteristics.

2. It is recommended to power V_DDand V_DDAfrom the same source. A maximum difference of 300 mV

between V_DDand V_DDAcan be tolerated during power-up and operation.

3. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax (see Table 6.2: Thermal

characteristics on page 74).

4. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax (see

Table 6.2: Thermal characteristics on page 74).

5.3.2

Operating conditions at power-up / power-down

Subject to general operating conditions for T .

A

Table 9.

Symbol

Operating conditions at power-up / power-down

Parameter

V_DDrise time rate

V_DDfall time rate

Conditions

Min

0

Max

∞

Unit

t_VDD

µs/V

20

∞

5.3.3

Embedded reset and power control block characteristics

The parameters given in Table 10 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Doc ID 15058 Rev 5

31/79

Electrical characteristics

STM32F101x4, STM32F101x6

.

Table 10. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

2.1

2

2.18 2.26

2.08 2.16

V

2.19 2.28 2.37

2.09 2.18 2.27

2.28 2.38 2.48

2.18 2.28 2.38

2.38 2.48 2.58

2.28 2.38 2.48

2.47 2.58 2.69

2.37 2.48 2.59

2.57 2.68 2.79

2.47 2.58 2.69

2.66 2.78 2.9

2.56 2.68 2.8

V

Programmable voltage

detector level selection

V_PVD

V

2.76 2.88

3

V

2.66 2.78 2.9

100

V

(2)

V_PVDhyst

PVD hysteresis

mV

V

1.8⁽¹⁾

Falling edge

Rising edge

1.88 1.96

Power on/power down

reset threshold

V_POR/PDR

1.84 1.92 2.0

40

V

(2)

V_PDRhyst

PDR hysteresis

mV

ms

(2)

t_RSTTEMPO

Reset temporization

1.5

2.5

4.5

1. The product behavior is guaranteed by design down to the minimum V_POR/PDRvalue.

2. Guaranteed by design, not tested in production.

32/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

5.3.4

Embedded reference voltage

The parameters given in Table 11 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Table 11. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_REFINTInternal reference voltage

–40 °C < T_A< +85 °C 1.16 1.20

5.1

1.24

V

ADC sampling time when reading

the internal reference voltage

(1)

17.1⁽²⁾

10

T_{S_vrefint}

µs

Internal reference voltage spread

over the temperature range

(2)

V_RERINT

V_DD= 3 V 10 mV

mV

ppm/

°C

(2)

T_Coeff

Temperature coefficient

100

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

5.3.5

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 11: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a

reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V or V (no load)

DD SS

All peripherals are disabled except if it is explicitly mentioned

The Flash access time is adjusted to f

wait state from 24 to 36 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

●

Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f = f , f = f

PCLK1

HCLK/2 PCLK2

HCLK

The parameters given in Table 12 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Doc ID 15058 Rev 5

33/79

Electrical characteristics

STM32F101x4, STM32F101x6

Table 12. Maximum current consumption in Run mode, code with data processing

running from Flash

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C

36 MHz

26

18

13

7

External clock ⁽²⁾, all

peripherals enabled

24 MHz

16 MHz

8 MHz

Supply current

in Run mode

I_DD

mA

36 MHz

24 MHz

16 MHz

8 MHz

19

13

10

6

External clock ⁽²⁾, all

peripherals Disabled

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

Table 13. Maximum current consumption in Run mode, code with data processing

running from RAM

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C

36 MHz

20

14

10

6

External clock ⁽²⁾, all

peripherals enabled

24 MHz

16 MHz

8 MHz

Supply current in

Run mode

I_DD

mA

36 MHz

24 MHz

16 MHz

8 MHz

15

10

7

External clock⁽²⁾all

peripherals disabled

5

1. Based on characterization, tested in production at V_DDmax, f_HCLKmax.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

34/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled

25

20

15

36 MHz

16 MHz

8 MHz

10

5

0

– 45°C

25 °C

70 °C

85 °C

Temperature (°C)

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled

16

14

12

10

36 MHz

8

6

4

2

0

16 MHz

8 MHz

– 45°C

25 °C

70 °C

85 °C

Temperature (°C)

Doc ID 15058 Rev 5

35/79

Electrical characteristics

STM32F101x4, STM32F101x6

Table 14. Maximum current consumption in Sleep mode, code running from Flash

or RAM

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C

36 MHz

24 MHz

16 MHz

8 MHz

14

10

7

External clock⁽²⁾all

peripherals enabled

4

Supplycurrentin

Sleep mode

I_DD

mA

36 MHz

24 MHz

16 MHz

8 MHz

5

External clock⁽²⁾, all

peripherals disabled

4.5

4

3

1. Based on characterization, tested in production at V_DDmax and f_HCLKmax with peripherals enabled.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

Table 15. Typical and maximum current consumptions in Stop and Standby modes

Typ⁽¹⁾

Max

Symbol

Parameter

Conditions

Unit

V

_DD/V_BAT

V

_DD/ V_BAT

= 2.4 V

V

_DD/V_BATT_A=

= 2.0 V

= 3.3 V 85 °C⁽²⁾

Regulator in Run mode,

Low-speed and high-speed internal RC

oscillators and high-speed oscillator OFF

(no independent watchdog)

-

21.3

11.3

21.7

11.7

160

145

Supply current

in Stop mode

Regulator in Low Power mode,

Low-speed and high-speed internal RC

oscillators and high-speed oscillator OFF

(no independent watchdog)

-

I_DD

Low-speed internal RC oscillator and

independent watchdog ON

µA

-

2.6

2.4

3.4

3.2

-

Supply current Low-speed internal RC oscillator ON,

in Standby

mode

independent watchdog OFF

Low-speed internal RC oscillator and

independent watchdog OFF, low-speed

oscillator and RTC OFF

-

1.7

1.1

2

3.2

1.9

Backup domain

I

Low-speed oscillator and RTC ON

0.9

1.4

^DD_VBATsupply current

1. Typical values are measured at T_A= 25 °C.

2. Based on characterization, not rested in production.

36/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

Figure 14. Typical current consumption on V

with RTC on versus temperature at different

BAT

V

values

BAT

2.5

2

1.5

1

2 V

2.4 V

3 V

0.5

0

3.6 V

–40 °C

25 °C

70 °C

85 °C

105 °C

Temperature (°C)

ai17351

Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at V = 3.3 V and 3.6 V

DD

45

40

35

30

25

20

15

10

5

3.3 V

3.6 V

0

–45 °C

25 °C

85 °C

Temperature (°C)

Doc ID 15058 Rev 5

37/79

Electrical characteristics

STM32F101x4, STM32F101x6

Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus

temperature at V = 3.3 V and 3.6 V

DD

30

25

20

15

10

5

3.3 V

3.6 V

0

–45 °C

25 °C

85 °C

Temperature (°C)

Figure 17. Typical current consumption in Standby mode versus temperature at V = 3.3 V and

DD

3.6 V

3.5

3

2.5

2

3.3 V

3.6 V

1.5

1

0.5

0

–45 °C

25 °C

85 °C

Temperature (°C)

38/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

Typical current consumption

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V or V (no load)

DD SS

All peripherals are disabled except if it is explicitly mentioned

The Flash access time is adjusted to f

wait state from 24 to 36 MHz)

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

●

Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f = f , f = f , f

=

HCLK/2 ADCCLK

PCLK1

HCLK/4 PCLK2

f

/4

PCLK2

The parameters given in Table 16 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Table 16. Typical current consumption in Run mode, code with data processing

running from Flash

Typ⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

All peripherals

enabled⁽²⁾

All peripherals

disabled

36 MHz

24 MHz

16 MHz

8 MHz

17.2

11.2

8.1

5

13.8

8.9

6.6

4.2

2.6

1.8

1.4

1.2

1

External

clock⁽³⁾

4 MHz

3

2 MHz

2

1 MHz

1.5

1.2

1.05

16.5

10.5

7.4

4.3

2.4

1.5

1

500 kHz

125 kHz

36 MHz

24 MHz

16 MHz

8 MHz

Supply

I_DD

current in

mA

13.1

8.2

5.9

3.6

2

Run mode

Running on

high speed

internal RC

(HSI), AHB

prescaler

used to

reduce the

frequency

4 MHz

2 MHz

1.3

0.9

0.65

0.45

1 MHz

500 kHz

125 kHz

0.7

0.5

1. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this

consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

Doc ID 15058 Rev 5

39/79

Electrical characteristics

STM32F101x4, STM32F101x6

Table 17. Typical current consumption in Sleep mode, code running from Flash or

RAM

Typ⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

All peripherals All peripherals

enabled⁽²⁾

disabled

36 MHz

24 MHz

16 MHz

8 MHz

6.7

4.8

3.4

2

3.1

2.3

1.8

1.2

External clock⁽³⁾

4 MHz

1.5

1.25

1.1

1.05

1

1.1

2 MHz

1

1 MHz

0.98

0.96

0.95

2.5

500 kHz

125 kHz

36 MHz

24 MHz

16 MHz

8 MHz

Supply

I_DD

current in

mA

6.1

4.2

2.8

1.4

0.9

0.7

0.55

0.48

0.4

Sleep mode

1.7

1.2

Running on High

Speed Internal RC

(HSI), AHB

prescaler used to

reduce the

0.55

0.5

4 MHz

2 MHz

0.45

0.42

0.4

frequency

1 MHz

500 kHz

125 kHz

0.38

1. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this

consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

40/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed

under the following conditions:

●

all I/O pins are in input mode with a static value at V or V (no load)

DD SS

all peripherals are disabled unless otherwise mentioned

the given value is calculated by measuring the current consumption

–

with all peripherals clocked off

with only one peripheral clocked on

●

ambient operating temperature and V supply voltage conditions summarized in

DD

Table 5.

Table 18. Peripheral current consumption

Peripheral

Typical consumption at 25 °C

Unit

TIM2

0.6

TIM3

APB1

USART2

0.21

0.18

0.21

1.4

I2C

GPIO A

GPIO B

GPIO C

mA

APB2

GPIO D

ADC⁽¹⁾

SPI

0.24

0.35

USART1

1. Specific conditions for ADC: f_HCLK= 28 MHz, f_APB1= f_HCLK/2, f_APB2= f_HCLK, f_ADCCLK= f_APB2/2, ADON bit

in the ADC_CR2 register is set to 1.

5.3.6

External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Table 19 result from tests performed using an high-speed

external clock source, and under the ambient temperature and supply voltage conditions

summarized in Table 8.

Doc ID 15058 Rev 5

41/79

Electrical characteristics

STM32F101x4, STM32F101x6

Table 19. High-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency⁽¹⁾

f_{HSE_ext}

1

8

25

MHz

V_HSEH

V_HSEL

t_w(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

0.7V_DD

V_SS

V_DD

V

0.3V_DD

OSC_IN high or low time⁽¹⁾

OSC_IN rise or fall time⁽¹⁾

5

t_w(HSE)

ns

t_r(HSE)

t_f(HSE)

20

C_in(HSE)OSC_IN input capacitance⁽¹⁾

5

pF

%

DuCy_(HSE)Duty cycle

45

55

1

I_L

OSC_IN Input leakage current

V_SS≤ V_IN≤ V_DD

µA

1. Guaranteed by design, not tested in production.

Low-speed external user clock generated from an external source

The characteristics given in Table 20 result from tests performed using an low-speed

external clock source, and under the ambient temperature and supply voltage conditions

summarized in Table 8.

Table 20. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency⁽¹⁾

f_{LSE_ext}

32.768

1000

kHz

OSC32_IN input pin high level

voltage

V_LSEH

V_LSEL

0.7V_DD

V_SS

V_DD

V

OSC32_IN input pin low level

voltage

0.3V_DD

t_w(LSE)

OSC32_IN high or low time⁽¹⁾

OSC32_IN rise or fall time⁽¹⁾

450

ns

t_r(LSE)

t_f(LSE)

50

C_in(LSE)OSC32_IN input capacitance⁽¹⁾

5

pF

%

DuCy_(LSE)Duty cycle

30

70

1

I_L

OSC32_IN Input leakage current V_SS≤ V_IN≤ V_DD

µA

1. Guaranteed by design, not tested in production.

42/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

Figure 18. High-speed external clock source AC timing diagram

V

HSEH

90%

10%

V

HSEL

t

W(HSE)

t

W(HSE)

r(HSE)

f(HSE)

T

HSE

f

HSE_ext

External

clock source

I

L

OSC _IN

STM32F10xxx

ai14127b

Figure 19. Low-speed external clock source AC timing diagram

V

LSEH

90%

10%

V

LSEL

t

W(LSE)

t

W(LSE)

r(LSE)

f(LSE)

T

LSE

f

LSE_ext

External

clock source

I

L

OSC32_IN

STM32F10xxx

ai14140c

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 21. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

Doc ID 15058 Rev 5

43/79

Electrical characteristics

STM32F101x4, STM32F101x6

(1)(2)

Table 21. HSE 4-16 MHz oscillator characteristics

Symbol Parameter Conditions

f_{OSC_IN}Oscillator frequency

Min

Typ

Max Unit

4

8

16

MHz

R_F

Feedback resistor

200

kΩ

Recommended load capacitance

versus equivalent serial

C

R_S= 30 Ω

30

pF

resistance of the crystal (R_S)⁽³⁾

V_DD= 3.3 V, V_IN= V_SS

with 30 pF load

i₂

HSE driving current

1

mA

g_m

Oscillator transconductance

Startup time

Startup

25

mA/V

ms

(4)

t_SU(HSE)

V_DDis stabilized

2

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a

humid environment, due to the induced leakage and the bias condition change. However, it is

recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

For C and C , it is recommended to use high-quality external ceramic capacitors in the

L1

L2

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 20). C and C are usually the

L1

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of C and C . PCB and MCU pin capacitance must be included (10 pF

L1

L2

can be used as a rough estimate of the combined pin and board capacitance) when sizing

C

and C . Refer to the application note AN2867 “Oscillator design guide for ST

L1

L2

microcontrollers” available from the ST website www.st.com.

Figure 20. Typical application with an 8 MHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC_IN

HSE

Bias

controlled

gain

8 MHz

resonator

R

F

STM32F10xxx

OSC_OUT

(1)

R

EXT

C

L2

ai14128b

1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 22. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

44/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

(1) (2)

Table 22. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Feedback resistor

Conditions

Min

Typ

Max

Unit

R_F

5

MΩ

Recommended load capacitance

versus equivalent serial

C

R_S= 30 KΩ

15

pF

resistance of the crystal (R_S)

V

_DD= 3.3 V

I₂

LSE driving current

1.4

µA

V_IN= V_SS

g_m

Oscillator transconductance

5

µA/V

T_A= 50 °C

T_A= 25 °C

T_A= 10 °C

T_A= 0 °C

1.5

2.5

4

6

V_DDis

stabilized

(3)

t_SU(LSE)

Startup time

s

T_A= -10 °C

T_A= -20 °C

T_A= -30 °C

T_A= -40 °C

10

17

32

60

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note:

For C and C it is recommended to use high-quality ceramic capacitors in the 5 pF to

L1 L2

15 pF range selected to match the requirements of the crystal or resonator. C and C are

L1

L2,

usually the same size. The crystal manufacturer typically specifies a load capacitance which

is the series combination of C and C .

L1

L2

Load capacitance C has the following formula: C = C x C / (C + C ) + C where

L

L1

L2

L1

L2

stray

C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

between 2 pF and 7 pF.

Caution:

To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended

L1

L2

to use a resonator with a load capacitance C ≤ 7 pF. Never use a resonator with a load

L

capacitance of 12.5 pF.

Example: if you choose a resonator with a load capacitance of C = 6 pF, and C

= 2 pF,

L

stray

then C = C = 8 pF.

L1

L2

Doc ID 15058 Rev 5

45/79

Electrical characteristics

Figure 21. Typical application with a 32.768 kHz crystal

STM32F101x4, STM32F101x6

Resonator with

integrated capacitors

C

L1

f

OSC32_IN

LSE

Bias

controlled

gain

32.768 KHz

resonator

R

F

STM32F10xxx

OSC32_OUT

C

L2

ai14129b

5.3.7

Internal clock source characteristics

The parameters given in Table 23 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

High-speed internal (HSI) RC oscillator

(1)

Table 23. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ

Max Unit

f_HSI

8

MHz

DuCy_(HSI)Duty cycle

45

55

%

User-trimmed with the RCC_CR

register⁽²⁾

1⁽³⁾

T_A= –40 to 105 °C

–2

2.5

2.2

2

%

Accuracy of the HSI

oscillator

ACC_HSI

T_A= –10 to 85 °C

Factory-

–1.5

–1.3

–1.1

calibrated⁽⁴⁾

T_A= 0 to 70 °C

T_A= 25 °C

1.8

HSI oscillator

startup time

(4)

t_su(HSI)

1

2

µs

HSI oscillator power

consumption

(4)

I_DD(HSI)

80

100

µA

1. V_DD= 3.3 V, T_A= –40 to 105 °C unless otherwise specified.

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from

the ST website www.st.com.

3. Guaranteed by design, not tested in production.

4. Based on characterization, not tested in production.

46/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

Low-speed internal (LSI) RC oscillator

(1)

Table 24. LSI oscillator characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(2)

f_LSI

Frequency

30

40

60

85

kHz

µs

(3)

t_su(LSI)

LSI oscillator startup time

(3)

I_DD(LSI)

LSI oscillator power consumption

0.65

1.2

µA

1. V_DD= 3 V, T_A= –40 to 85 °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Wakeup time from low-power mode

The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI

RC oscillator. The clock source used to wake up the device depends from the current

operating mode:

●

Stop or Standby mode: the clock source is the RC oscillator

●

Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under the ambient temperature and V supply

DD

voltage conditions summarized in Table 8.

Table 25. Low-power mode wakeup timings

Symbol

Parameter

Wakeup from Sleep mode

Typ

Unit

(1)

1.8

µs

t_WUSLEEP

Wakeup from Stop mode (regulator in run mode)

Wakeup from Stop mode (regulator in low-power mode)

Wakeup from Standby mode

3.6

5.4

50

(1)

µs

t_WUSTOP

(1)

t_WUSTDBY

1. The wakeup times are measured from the wakeup event to the point at which the user application code

reads the first instruction.

5.3.8

PLL characteristics

The parameters given in Table 26 are derived from tests performed under the ambient

temperature and V supply voltage conditions summarized in Table 8.

DD

Table 26. PLL characteristics

Value

Symbol

Parameter

Unit

Min⁽¹⁾

Typ

Max⁽¹⁾

PLL input clock⁽²⁾

1

8.0

25

60

36

MHz

%

f_{PLL_IN}

f_{PLL_OUT}

PLL input clock duty cycle

PLL multiplier output clock

40

16

MHz

Doc ID 15058 Rev 5

47/79

Electrical characteristics

Table 26. PLL characteristics

Symbol Parameter

STM32F101x4, STM32F101x6

Value

Unit

Min⁽¹⁾

Typ

Max⁽¹⁾

t_LOCK

Jitter

1. Based on device characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

PLL lock time

200

µs

Cycle-to-cycle jitter

300

ps

the range defined by f_{PLL_OUT}

.

5.3.9

Memory characteristics

Flash memory

The characteristics are given at T = –40 to 85 °C unless otherwise specified.

A

Table 27. Flash memory characteristics

Symbol

Parameter

Conditions

Min⁽¹⁾Typ Max⁽¹⁾Unit

t_prog

t_ERASE

t_ME

16-bit programming time

Page (1 KB) erase time

Mass erase time

T_A= –40 to +85 °C

40

20

52.5

70

40

µs

ms

Read mode

f_HCLK= 36 MHz with 1 wait

state, V_DD= 3.3 V

20

5

mA

I_DD

Supply current

Write / Erase modes

f_HCLK= 36 MHz, V_DD= 3.3 V

Power-down mode / Halt,

V_DD= 3.0 to 3.6 V

50

µA

V

V_prog

Programming voltage

2

3.6

1. Guaranteed by design, not tested in production.

Table 28. Flash memory endurance and data retention

Value

Typ

Symbol

N_ENDEndurance

t_RETData retention

Parameter

Conditions

Unit

Min⁽¹⁾

Max

T_A= –40 °C to 85 °C

T_A= 85 °C, 1 kcycle⁽²⁾

T_A= 55 °C, 10 kcycle⁽²⁾

kcycles

Years

10

30

20

1. Based on characterization not tested in production.

2. Cycling performed over the whole temperature range.

5.3.10

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

48/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the

device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

●

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

●

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 29. They are based on the EMS levels and classes

defined in application note AN1709.

Table 29. EMS characteristics

Symbol

Parameter

Conditions

Level/Class

V_DD= 3.3 V, T_A= +25 °C,

f_HCLK= 36 MHz

conforms to IEC 61000-4-2

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

V_FESD

2B

Fast transient voltage burst limits to be

V_DD= 3.3 V, T_A= +25 °C,

V_EFTB

applied through 100 pF on V_DDand V_SSpins f_HCLK= 36 MHz

to induce a functional disturbance conforms to IEC 61000-4-4

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre

qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

●

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second. To complete these trials, ESD stress can be applied directly on the device, over the

range of specification values. When unexpected behavior is detected, the software can be

hardened to prevent unrecoverable errors occurring (see application note AN1015).

Doc ID 15058 Rev 5

49/79

Electrical characteristics

STM32F101x4, STM32F101x6

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC61967-2 standard which specifies the test board and the pin loading.

Table 30. EMI characteristics

Max vs. [f_HSE/f_HCLK

]

Monitored

Symbol Parameter

Conditions

Unit

frequency band

8/36 MHz

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1GHz

SAE EMI Level

7

8

V_DD= 3.3 V, T_A= 25 °C,

LQFP100 package

compliant with

dBµV

-

S_EMI

Peak level

13

3.5

IEC 61967-2

5.3.11

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 31. ESD absolute maximum ratings

Maximum

Symbol

Ratings

Conditions

Class

Unit

value⁽¹⁾

Electrostatic discharge

voltage (human body model) conforming to JESD22-A114

T_A= +25 °C

V_ESD(HBM)

2

II

2000

V

Electrostatic discharge T_A= +25 °C

voltage (charge device model) conforming to JESD22-C101

V_ESD(CDM)

500

1. Based on characterization results, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

●

A supply overvoltage is applied to each power supply pin

●

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78 IC latch-up standard.

Table 32. Electrical sensitivities

Symbol

Parameter

Conditions

Class

II level A

LU

Static latch-up class

T_A= +85 °C conforming to JESD78A

50/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

5.3.12

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V or

SS

above V (for standard, 3 V-capable I/O pins) should be avoided during normal product

DD

operation. However, in order to give an indication of the robustness of the microcontroller in

cases when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into the

I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for

example reset, oscillator frequency deviation).

The test results are given in Table 33

Table 33. I/O current injection susceptibility

Functional susceptibility

Symbol

Description

Unit

Negative

injection

Positive

injection

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

-0

+0

I_INJ

mA

Injected current on all FT pins

Injected current on any other pin

-5

+0

+5

Doc ID 15058 Rev 5

51/79

Electrical characteristics

STM32F101x4, STM32F101x6

5.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 34 are derived from tests

performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL

compliant.

Table 34. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Standard IO input low

level voltage

–0.3

0.28*(V_DD-2 V)+0.8 V

V

V_IL

IO FT⁽¹⁾input low level

voltage

–0.3

0.32*(V_DD-2V)+0.75 V

V_DD+0.3

V

Standard IO input high

level voltage

0.41*(V_DD-2 V)+1.3 V

V_IH

IO FT⁽¹⁾input high level

voltage

V_DD> 2 V

5.5

5.2

0.42*(V_DD-2 V)+1 V

200

V

V_DD≤ 2 V

Standard IO Schmitt

trigger voltage

hysteresis⁽²⁾

mV

V_hys

IO FT Schmitt trigger

voltage hysteresis⁽²⁾

(3)

5% V_DD

V_SS≤ V_IN≤ V_DD

Standard I/Os

±1

3

I_lkg

Input leakage current ⁽⁴⁾

µA

V_IN= 5 V

I/O FT

Weak pull-up equivalent

resistor⁽⁵⁾

R_PU

V_IN= V_SS

V_IN= V_DD

30

40

50

kΩ

Weak pull-down

R_PD

C_IO

40

5

kΩ

equivalent resistor⁽⁵⁾

I/O pin capacitance

pF

1. FT = Five-volt tolerant. In order to sustain a voltage higher than V_DD+0.3 the internal pull-up/pull-down resistors must be

disabled.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order).

52/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 22 and Figure 23 for standard I/Os, and

in Figure 24 and Figure 25 for 5 V tolerant I/Os.

Figure 22. Standard I/O input characteristics - CMOS port

V

/V (V)

IH IL

1.96

1.25

1.71

1.08

1.71

1.08

Input range

not guaranteed

1.59

V_IHmin

1.3

1

V_ILmax

0.8

0.7

V

(V)

DD

2

2.7

3

3.3

3.6

ai17277b

Figure 23. Standard I/O input characteristics - TTL port

6

ꢇ6 ꢈ6ꢉ

)( ),

44, REQUIREMENTS

6

ꢍꢂ6

)(

7_)(MIN

ꢂꢅꢊ

ꢀꢅꢋꢆ

ꢀꢅꢂꢌ

)NPUT RANGE

NOT GUARANTEED

ꢀꢅꢄ

ꢊꢅꢃ

7_),MAX

44, REQUIREMENTS

6

ꢍꢊꢅꢃ6

),

6

ꢈ6ꢉ

$$

ꢂ

ꢂꢅꢀꢆ

ꢄꢅꢆ

AIꢀꢁꢂꢁꢃ

Doc ID 15058 Rev 5

53/79

Electrical characteristics

STM32F101x4, STM32F101x6

Figure 24. 5 V tolerant I/O input characteristics - CMOS port

6

ꢇ6 ꢈ6ꢉ

)( ),

ꢀꢅꢆꢁ

ꢀꢅꢌꢌ

ꢀꢅꢀꢆ

)NPUT RANGE

NOT GUARANTEED

ꢀ

ꢀꢅꢎꢂ

ꢀꢅꢊꢁ

ꢀꢅꢄ

ꢊꢅꢁ

ꢀꢅꢂꢋꢌ

ꢊꢅꢋꢁꢌ

ꢀ

ꢊꢅꢁꢌ

6

ꢈ6ꢉ

$$

ꢂ

ꢂꢅꢁ

ꢄ

ꢄꢅꢄ

ꢄꢅꢆ

6$$

AIꢀꢁꢂꢁꢋB

Figure 25. 5 V tolerant I/O input characteristics - TTL port

6

ꢇ6 ꢈ6ꢉ

)( ),

44, REQUIREMENT 6 ꢍꢂ6

)(

ꢂꢅꢊ

ꢀꢅꢆꢁ

ꢀ

)NPUT RANGE

NOT GUARANTEED

7_)(MIN

7_),MAX

ꢊꢅꢃ

ꢊꢅꢁꢌ

44, REQUIREMENTS 6 ꢍꢊꢅꢃ6

),

6

ꢈ6ꢉ

$$

ꢂ

ꢂꢅꢀꢆ

ꢄꢅꢆ

AIꢀꢁꢂꢃꢊ

54/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

Output driving current

The GPIOs (general-purpose inputs/outputs) can sink or source up to 8 mA, and sink or

source up to 20 mA (with a relaxed V /V ).

OL OH

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 5.2:

●

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

I

(see Table 6).

VDD

●

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

I

(see Table 6).

VSS

Output voltage levels

Unless otherwise specified, the parameters given in Table 35 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 8. All I/Os are CMOS and TTL compliant.

Table 35. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max Unit

Output Low level voltage for an I/O pin

when 8 pins are sunk at the same time

(1)

CMOS port⁽²⁾,,

I_IO= +8 mA,

2.7 V < V_DD< 3.6 V

0.4

V

V_OL

Output High level voltage for an I/O pin

when 8 pins are sourced at the same time

(3)

V_DD–0.4

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

(1)

TTL port⁽²⁾

I_IO= +8 mA

0.4

V

V_OL

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

(3)

2.7 V < V_DD< 3.6 V

2.4

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

(1)

1.3

V

V_OL

I_IO= +20 mA⁽⁴⁾

2.7 V < V_DD< 3.6 V

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

(3)

V_DD–1.3

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

(1)

0.4

V

V_OL

I_IO= +6 mA⁽⁴⁾

2 V < V_DD< 2.7 V

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

(3)

V_DD–0.4

V_OH

1. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 6

and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in

Table 6 and the sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

4. Based on characterization data, not tested in production.

Doc ID 15058 Rev 5

55/79

Electrical characteristics

STM32F101x4, STM32F101x6

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 26 and

Table 36, respectively.

Unless otherwise specified, the parameters given in Table 36 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 8.

(1)

Table 36. I/O AC characteristics

MODEx

[1:0] bit Symbol

Parameter

Conditions

Max Unit

value⁽¹⁾

f_max(IO)outMaximum frequency⁽²⁾

C_L= 50 pF, V_DD= 2 V to 3.6 V

2

MHz

ns

Output high to low level fall

t_f(IO)out

time

125⁽³⁾

10

01

C_L= 50 pF, V_DD= 2 V to 3.6 V

Output low to high level rise

t_r(IO)out

time

125⁽³⁾

10

f_max(IO)outMaximum frequency⁽²⁾

MHz

ns

Output high to low level fall

t_f(IO)out

time

25⁽³⁾

Output low to high level rise

t_r(IO)out

time

25⁽³⁾

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

50

30

20

MHz

F_max(IO)outMaximum Frequency⁽²⁾

C_L= 30 pF, V_DD= 2.7 V to 3.6 V 5⁽³⁾

C_L= 50 pF, V_DD= 2.7 V to 3.6 V 8⁽³⁾

Output high to low level fall

11

t_f(IO)out

time

C_L= 50 pF, V_DD= 2 V to 2.7 V

12⁽³⁾

ns

C_L= 30 pF, V_DD= 2.7 V to 3.6 V 5⁽³⁾

C_L= 50 pF, V_DD= 2.7 V to 3.6 V 8⁽³⁾

Output low to high level rise

t_r(IO)out

time

C_L= 50 pF, V_DD= 2 V to 2.7 V

12⁽³⁾

Pulse width of external

t_EXTIpwsignals detected by the

EXTI controller

-

10

ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a

description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 26.

3. Guaranteed by design, not tested in production.

56/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Figure 26. I/O AC characteristics definition

Electrical characteristics

90%

10 %

50%

90%

10%

t

EXTERNAL

OUTPUT

ON 50pF

t

r(IO)out

T

Maximum frequency is achieved if (t + t ) ≤ 2/3)T and if the duty cycle is (45-55%)

r

f

when loaded by 50pF

ai14131

5.3.14

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, R (see Table 34).

PU

Unless otherwise specified, the parameters given in Table 37 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 8.

Table 37. NRST pin characteristics

Symbol

Parameter

Conditions Min

Typ

Max

Unit

(1)

V_IL(NRST)

NRST Input low level voltage

NRST Input high level voltage

–0.5

2

0.8

V

(1)

V_IH(NRST)

V_hys(NRST)

R_PU

V_DD+0.5

NRST Schmitt trigger voltage

hysteresis

200

40

mV

Weak pull-up equivalent resistor⁽²⁾V_IN= V_SS

30

50

kΩ

ns

(1)

V_F(NRST)

NRST Input filtered pulse

100

(1)

V_NF(NRST)

NRST Input not filtered pulse

300

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance must be minimum (~10% order).

Figure 27. Recommended NRST pin protection

V

DD

External

reset circuit

(1)

R

PU

(2)

Internal reset

STM32F10x

NRST

Filter

0.1 µF

ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 37. Otherwise the reset will not be taken into account by the device.

Doc ID 15058 Rev 5

57/79

Electrical characteristics

STM32F101x4, STM32F101x6

5.3.15

TIM timer characteristics

The parameters given in Table 38 are guaranteed by design.

Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output

alternate function characteristics (output compare, input capture, external clock, PWM

output).

(1)

Table 38. TIMx characteristics

Symbol

Parameter

Conditions

Min

1

Max

Unit

t_TIMxCLK

t_res(TIM)

Timer resolution time

f_TIMxCLK= 36 MHz

_TIMxCLK= 36 MHz

27.8

0

ns

MHz

bit

f

_TIMxCLK/2

18

Timer external clock

frequency on CH1 to CH4

f_EXT

f

0

Res_TIM

Timer resolution

16

16-bit counter clock period

when internal clock is

selected

t_TIMxCLK

1

65536

1820

t_COUNTER

f_TIMxCLK= 36 MHz

0.0278

µs

t_TIMxCLK

s

65536 × 65536

119.2

t_{MAX_COUNT}

Maximum possible count

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

5.3.16

Communications interfaces

I²C interface characteristics

Unless otherwise specified, the parameters given in Table 39 are derived from tests

performed under the ambient temperature, f

frequency and V supply voltage

PCLK1

DD

conditions summarized in Table 8.

2

The STM32F101xx Low-density access line I C interface meets the requirements of the

2

standard I C communication protocol with the following restrictions: t

he I/O pins SDA and

SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and V is disabled, but is still present.

DD

2

The I C characteristics are described in Table 39. Refer also to

Section 5.3.12: I/O current

for more details on the input/output alternate function characteristics

injection characteristics

(SDA and SCL)

.

58/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

2

Table 39. I C characteristics

Standard mode I²C⁽¹⁾Fast mode I²C⁽¹⁾⁽²⁾

Symbol

Parameter

Unit

Min

Max

Min

Max

t_w(SCLL)SCL clock low time

t_w(SCLH)SCL clock high time

t_su(SDA)SDA setup time

4.7

4.0

1.3

0.6

100

0⁽⁴⁾

µs

250

0⁽³⁾

t_h(SDA)

SDA data hold time

900⁽³⁾

300

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

1000

300

20+0.1C_b

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

Start condition hold time

300

t_h(STA)

4.0

4.7

4.0

4.7

0.6

1.3

µs

Repeated Start condition setup

time

t_su(STA)

t_su(STO)Stop condition setup time

µs

pF

Stop to Start condition time (bus

t_w(STO:STA)

free)

C_b

Capacitive load for each bus line

400

Guaranteed by design, not tested in production.

1.

2. f_PCLK1must be higher than 2 MHz to achieve standard mode I²C frequencies. It must be higher than

4 MHz to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz

maximum I2C fast mode clock.

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

period of SCL signal.

3.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

4.

Doc ID 15058 Rev 5

59/79

Electrical characteristics

STM32F101x4, STM32F101x6

2

(1)

Figure 28. I C bus AC waveforms and measurement circuit

V

DD

STM32F10x

SDA

4.7kΩ

100 Ω

I²C bus

SCL

Start repeated

Start

t

su(STA)

SDA

t

su(SDA)

f(SDA)

r(SDA)

t

su(STO:STA)

Stop

t

h(SDA)

h(STA)

w(SCLL)

SCL

t

f(SCL)

su(STO)

w(SCLH)

r(SCL)

ai14133d

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

(1)(2)

Table 40. SCL frequency (f

f_SCL(kHz)

= MHz, V_DD= 3.3 V)

PCLK1

I2C_CCR value

R_P= 4.7 kΩ

400

300

200

100

50

0x801E

0x8028

0x803C

0x00B4

0x0168

0x0384

20

1. R_P= External pull-up resistance, f_SCL= I²C speed,

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the

tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external

components used to design the application.

60/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 41 are derived from tests

performed under the ambient temperature, f

frequency and V supply voltage

PCLKx

DD

conditions summarized in Table 8.

Refer to Section 5.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 41. SPI characteristics

Symbol

Parameter

Conditions

Master mode

Min

Max

Unit

0

18

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

Slave mode

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

8

(1)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

4 t_PCLK

73

(1)

t_h(NSS)

(1)

t_w(SCKH)

t_w(SCKL)

Master mode, f_PCLK= 36 MHz,

presc = 4

SCK high and low time

50

1

60

(1)

Data input setup time

Master mode

(1)

t_su(MI)

t_su(SI)

t_h(MI)

SPI

Data input setup time

Slave mode

(1)

1

Data input hold time

Master mode

(1)

1

Data input hold time

Slave mode

(1)

t_h(SI)

3

Slave mode, f_PCLK= 36 MHz,

presc = 4

ns

0

55

(1)(2)

t_a(SO)

Data output access time

Slave mode, f_PCLK= 24 MHz

0

4 t_PCLK

(1)(3)

t_dis(SO)

Data output disable time Slave mode

10

(1)

t_v(SO)

t_v(MO)

t_h(SO)

t_h(MO)

Data output valid time

Slave mode (after enable edge)

25

3

Master mode (after enable

edge)

Slave mode (after enable edge)

25

4

Data output hold time

Master mode (after enable

edge)

1. Based on characterization, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

Doc ID 15058 Rev 5

61/79

Electrical characteristics

STM32F101x4, STM32F101x6

Figure 29. SPI timing diagram - slave mode and CPHA = 0

NSS input

t

c(SCK)

t

h(NSS)

SU(NSS)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

r(SCK)

f(SCK)

v(SO)

a(SO)

h(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134c

(1)

Figure 30. SPI timing diagram - slave mode and CPHA = 1

NSS input

t

SU(NSS)

t

c(SCK)

h(NSS)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

62/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Electrical characteristics

(1)

Figure 31. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

INPUT

MSBIN

BIT6 IN

LSB IN

t

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTUT

t

v(MO)

h(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

Doc ID 15058 Rev 5

63/79

Electrical characteristics

STM32F101x4, STM32F101x6

5.3.17

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 42 are derived from tests

performed under the ambient temperature, f

frequency and V

supply voltage

PCLK2

DDA

conditions summarized in Table 8.

Note:

It is recommended to perform a calibration after each power-up.

Table 42. ADC characteristics

Symbol

Parameter

Power supply

Conditions

Min

Typ

Max

Unit

V_DDA

f_ADC

2.4

0.6

3.6

14

V

ADC clock frequency

Sampling rate

MHz

(1)

0.05

1

MHz

f_S

f_ADC= 14 MHz

823

17

kHz

(1)

External trigger frequency

Conversion voltage range⁽²⁾

f_TRIG

1/f_ADC

0 (V_SSAor V_REF-

tied to ground)

V_AIN

V_REF+

V

See Equation 1 and

Table 43 for details

(1)

R_AIN

External input impedance

Sampling switch resistance

50

1

kΩ

pF

(1)

R_ADC

Internal sample and hold

capacitor

(1)

8

C_ADC

f_ADC= 14 MHz

f_ADC= MHz

5.9

83

µs

1/f_ADC

µs

(1)

Calibration time

t_CAL

0.214

3⁽³⁾

Injection trigger conversion

latency

(1)

t_lat

1/f_ADC

µs

f_ADC= 14 MHz

0.143

2⁽³⁾

Regular trigger conversion

latency

(1)

t_latr

1/f_ADC

µs

0.107

1.5

0

17.1

239.5

1

(1)

Sampling time

Power-up time

f_ADC= 14 MHz

t_S

1/f_ADC

µs

(1)

t_STAB

0

1

18

µs

Total conversion time

(including sampling time)

(1)

t_CONV

14 to 252 (t_Sfor sampling +12.5 for

successive approximation)

1/f_ADC

1. Guaranteed by design, not tested in production.

2. V_REF+is internally connected to V_DDAand V_REF-is be internally connected to V_SSA

3. For external triggers, a delay of 1/f_PCLK2must be added to the latency specified in Table 42.

.

64/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Equation 1: R

Electrical characteristics

max formula:

AIN

T_S

R_AIN< ------------------------------------------------------------- – R_ADC

f_ADC× C_ADC× ln(2^{N + 2}

)

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an

error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

(1)

Table 43.

R

max for f

= 14 MHz

AIN

ADC

T_s(cycles)

t_S(µs)

R_AINmax (kΩ)

1.5

0.11

0.4

7.5

0.54

0.96

2.04

2.96

3.96

5.11

17.1

5.9

13.5

28.5

41.5

55.5

71.5

239.5

11.4

25.2

37.2

50

NA

1. Guaranteed by design, not tested in production.

(1) (2)

Table 44. ADC accuracy - limited test conditions

Symbol

Parameter

Test conditions

Typ

Max⁽³⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

1.3

1

2

f_PCLK2= 28 MHz,

f_ADC= 14 MHz, R_AIN< 10 kΩ,

V_DDA= 3 V to 3.6 V

T_A= 25 °C

1.5

1

Gain error

0.5

0.7

0.8

LSB

Differential linearity error

Integral linearity error

Measurements made after

ADC calibration

1.5

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to

standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 5.3.12 does not

affect the ADC accuracy.

3. Based on characterization, not tested in production.

Doc ID 15058 Rev 5

65/79

Electrical characteristics

STM32F101x4, STM32F101x6

(1) (2) (3)

Table 45. ADC accuracy

Symbol

Parameter

Test conditions

Typ

Max⁽⁴⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

2

5

2.5

3

f_PCLK2= 28 MHz,

f_ADC= 14 MHz, R_AIN< 10 kΩ,

V_DDA= 2.4 V to 3.6 V

1.5

1

Gain error

LSB

Measurements made after

ADC calibration

Differential linearity error

Integral linearity error

2

1.5

3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V_DD, frequency and temperature ranges.

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to

standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 5.3.12 does not

affect the ADC accuracy.

4. Based on characterization, not tested in production.

Figure 32. ADC accuracy characteristics

V_DDA

[1LSB_IDEAL

=

4096

E_G

(1) Example of an actual transfer curve

(2) The ideal transfer curve

4095

4094

4093

(3) End point correlation line

(2)

E_T=Total u nadjusted error: maximum deviation

E_T

between the actual and the ideal transfer curves.

(3)

7

6

5

4

3

2

1

E_O=Offset error: deviation between the first actual

transition and the first ideal one.

(1)

E_G=Gain error: deviation between the last ideal

transition and the last actual one.

E_O

E_L

E_D=Differential linearity error: maximum deviation

between actual steps and the ideal one.

E_L=Integral linearity error: maximum deviation

between any actual transition and the end point

correlation line.

E_D

1 LSB_IDEAL

0

1

2

3

4

5

6

7

4093 4094 4095 4096

V_DDA

ai15497

V_SSA

66/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Figure 33. Typical connection diagram using the ADC

Electrical characteristics

STM32F10xxx

V

DD

Sample and hold ADC

V

0.6 V

T

converter

(1)

C

(1)

R

AIN

ADC

AINx

12-bit

converter

V

T

V

AIN

0.6 V

C

(1)

ADC

parasitic

I

1 µA

L

ai14139d

1. Refer to Table 42 for the values of R_AIN, R_ADCand C_ADC

2.

.

C

_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high C_parasiticvalue will downgrade conversion accuracy. To remedy

this, f_ADCshould be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 34. The 10 nF capacitors

should be ceramic (good quality). They should be placed them as close as possible to the

chip.

Figure 34. Power supply and reference decoupling

STM32F10xx4/6

V

DDA

1 µF // 10 nF

V

SSA

ai15498

Doc ID 15058 Rev 5

67/79

Electrical characteristics

STM32F101x4, STM32F101x6

5.3.18

Temperature sensor characteristics

Table 46. TS characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(1)

V_SENSElinearity with temperature

Average slope

±1

4.3

±2

4.6

°C

mV/°C

V

T

L

Avg_Slope⁽¹⁾

4.0

(1)

Voltage at 25°C

1.34

1.43

1.52

V₂₅

(2)

Startup time

4

10

µs

t_START

ADC sampling time when reading the

temperature

(3)(2)

17.1

T_{S_temp}

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

68/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Package characteristics

6

Package characteristics

6.1

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Doc ID 15058 Rev 5

69/79

Package characteristics

STM32F101x4, STM32F101x6

Figure 35. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package Figure 36. Recommended footprint

(1)

(1)(2)

outline

(dimensions in mm)

Seating

Plane

C

0.75

5.80

37

48

D

36

1

Pin no. 1 ID

R = 0.20

e

5.60

37

48

0.20

0.30

1

36

5.80

5.60

6.20

12

25

0.55

13

24

0.50

25

12

7.30

ai15799

24

13

L

b

Bottom View

D2

V0_ME

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.

Table 47. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

0.800

0.900

0.020

0.650

0.250

0.230

7.000

4.700

7.000

4.700

0.500

0.400

0.080

1.000

0.050

1.000

0.0315

0.0354

0.0008

0.0256

0.0098

0.0091

0.2756

0.1850

0.2756

0.1850

0.0197

0.0157

0.0031

0.0394

0.0020

0.0394

A1

A2

A3

b

0.180

6.850

2.250

6.850

2.250

0.450

0.300

7.150

5.250

7.150

5.250

0.550

0.500

0.0071

0.2697

0.0886

0.2697

0.0886

0.0177

0.0118

0.2815

0.2067

0.2815

0.2067

0.0217

0.0197

D

D2

E

E2

e

L

ddd

1. Values in inches are converted from mm and rounded to 4 decimal digits.

70/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Package characteristics

Figure 37. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package Figure 38. Recommended footprint

(1)

(1)(2)

outline

(dimensions in mm)

Seating plane

C

ddd

C

A2

A

1.00

4.30

27

19

A1

A3

E2

28

18

b

0.50

27

19

4.10

18

28

4.30

4.10

4.80

e

D2

D

36

10

0.75

9

1

0.30

36

10

6.30

ai14870b

1

9

Pin # 1 ID

R = 0.20

L

E

ZR_ME

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.

Table 48. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

0.800

0.900

0.020

0.650

0.250

0.230

6.000

3.700

6.000

3.700

0.500

0.550

0.080

1.000

0.050

1.000

0.0315

0.0354

0.0008

0.0256

0.0098

0.0091

0.2362

0.1457

0.2362

0.1457

0.0197

0.0217

0.0031

0.0394

0.0020

0.0394

A1

A2

A3

b

0.180

5.875

1.750

5.875

1.750

0.450

0.350

0.300

6.125

4.250

6.125

4.250

0.550

0.750

0.0071

0.2313

0.0689

0.2313

0.0689

0.0177

0.0138

0.0118

0.2411

0.1673

0.2411

0.1673

0.0217

0.0295

D

D2

E

E2

e

L

ddd

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 15058 Rev 5

71/79

Package characteristics

STM32F101x4, STM32F101x6

Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile

Figure 40. Recommended

(1)

(1)(2)

quad flat package outline

footprint

A

A2

48

33

A1

0.3

49

32

0.5

b

12.7

E

E1

10.3

e

64

17

1.2

1

16

7.8

D1

D

c

L1

12.7

ai14909

L

ai14398b

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 49. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.0630

0.0059

0.0571

0.0106

0.0079

0.05

1.35

0.17

0.09

0.0020

0.0531

0.0067

0.0035

1.40

0.22

0.0551

0.0087

c

D

12.00

10.00

12.00

10.00

0.50

0.4724

0.3937

0.4724

0.3937

0.0197

3.5°

D1

E

E1

e

θ

0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.0177

0.0236

0.0394

0.0295

L1

1.00

Number of pins

N

64

1. Values in inches are converted from mm and rounded to 4 decimal digits.

72/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Package characteristics

Figure 41. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat Figure 42. Recommended

(1)

(1)(2)

package outline

footprint

Seating plane

C

A

A2

0.50

A1

c

b

1.20

0.25 mm

ccc

C

Gage plane

0.30

36

25

D

37

24

D1

D3

k

0.20

7.30

A1

L

9.70 5.80

25

36

L1

7.30

24

48

13

12

37

1

1.20

5.80

E3

E1

E

9.70

ai14911b

48

13

Pin 1

identification

1

12

5B_ME

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 50. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

9.200

7.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

0.050

1.350

0.170

0.090

8.800

6.800

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

1.400

0.220

0.0551

0.0087

c

D

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

0.3543

0.2756

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

D1

D3

E

8.800

6.800

9.200

7.200

0.3465

0.2677

0.3622

0.2835

E1

E3

e

L

0.450

0°

0.750

7°

0.0177

0°

0.0295

7°

L1

k

ccc

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 15058 Rev 5

73/79

Package characteristics

STM32F101x4, STM32F101x6

6.2

Thermal characteristics

The maximum chip junction temperature (T max) must never exceed the values given in

J

Table 8: General operating conditions on page 30.

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max x Θ )

J

A

D

JA

Where:

●

T max is the maximum ambient temperature in °C,

A

Θ

is the package junction-to-ambient thermal resistance, in °C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (V × I ) + Σ((V – V ) × I ),

OL OL DD OH OH

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 51. Package thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm / 0.5 mm pitch

45

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm / 0.5 mm pitch

55

16

18

Θ_JA

°C/W

Thermal resistance junction-ambient

VFQFPN 48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch

6.2.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

74/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Package characteristics

6.2.2

Evaluating the maximum junction temperature for an application

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 52: Ordering information scheme.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature. Here, only

temperature range 6 is available (–40 to 85 °C).

The following example shows how to calculate the temperature range needed for a given

application, making it possible to check whether the required temperature range is

compatible with the STM32F101xx junction temperature range.

Example: high-performance application

Assuming the following application conditions:

Maximum ambient temperature T

= 82 °C (measured according to JESD51-2),

Amax

I

= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output

OL

mode at low level with I = 20 mA, V = 1.3 V

OL

P

= 50 mA × 3.5 V= 175 mW

INTmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

IOmax

This gives: P

= 175 mW and P

= 272 mW

IOmax

INTmax

P

= 175 + 272 = 447 mW

Dmax

Thus: P

= 447 mW

Dmax

Using the values obtained in Table 51 T

is calculated as follows:

Jmax

–

T

For LQFP64, 45 °C/W

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C

Jmax

This is within the junction temperature range of the STM32F101xx (–40 < T < 105 °C).

J

Figure 43. LQFP64 P max vs. T

D

A

700

600

500

400

300

200

100

0

Suffix 6

65

75

85

95

105

115

T_A(°C)

Doc ID 15058 Rev 5

75/79

Ordering information scheme

STM32F101x4, STM32F101x6

7

Ordering information scheme

Table 52. Ordering information scheme

Example:

STM32 F 101 C

4

T

6

A

xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

101 = access line

Pin count

T = 36 pins

C = 48 pins

R = 64 pins

Flash memory size

4 = 16 Kbytes of Flash memory

6 = 32 Kbytes of Flash memory

Package

T = LQFP

U = VFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

Internal code

“A” or blank⁽¹⁾

Options

xxx = programmed parts

TR = tape and real

1. For STM32F101x6 devices with a blank internal code, please refer to the STM32F103x6/8/B datasheet

available from the ST website: www.st.com.

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

76/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Revision history

8

Revision history

Table 53. Document revision history

Date

Revision

Changes

23-Sep-2008

1

Initial release.

I/O information clarified on page 1. Figure 7: Memory map modified.

In Table 4: Low-density STM32F101xx pin definitions: PB4, PB13, PB14,

PB15, PB3/TRACESWO moved from Default column to Remap column.

V_REF-is not available in the offered packages: Figure 1: STM32F101xx

Low-density access line block diagram, Figure 10: Power supply scheme

and Figure 34: Power supply and reference decoupling updated,

Figure 30: Power supply and reference decoupling (V_REF+not connected

to V_DDA) removed.

07-Apr-2009

2

Note modified in Table 12: Maximum current consumption in Run mode,

code with data processing running from Flash and Table 14: Maximum

current consumption in Sleep mode, code running from Flash or RAM.

Figure 15, Figure 16 and Figure 17 show typical curves.

ACC_HSImax values modified in Table 23: HSI oscillator characteristics.

Small text changes.

Note 5 updated and Note 4 added in Table 4: Low-density

STM32F101xx pin definitions.

V_RERINTand T_Coeffadded to Table 11: Embedded internal reference

voltage. Typical I_{DD_VBAT}value added in Table 15: Typical and maximum

current consumptions in Stop and Standby modes. Figure 14: Typical

current consumption on VBAT with RTC on versus temperature at

different VBAT values added.

f_{HSE_ext}min modified in Table 19: High-speed external user clock

characteristics.

C_L1and C_L2replaced by C in Table 21: HSE 4-16 MHz oscillator

characteristics and Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz), notes modified and moved below the tables.

24-Sep-2009

3

Note 1 modified below Figure 20: Typical application with an 8 MHz

crystal.

Table 23: HSI oscillator characteristics modified. Conditions removed

from Table 25: Low-power mode wakeup timings.

Figure 27: Recommended NRST pin protection modified.

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to

IEC 61967-2 in Section 5.3.10: EMC characteristics on page 48.

Jitter added to Table 26: PLL characteristics.

C_ADCand R_AINparameters modified in Table 42: ADC characteristics.

R_AINmax values modified in Table 43: RAIN max for fADC = 14 MHz.

Small text changes.

Doc ID 15058 Rev 5

77/79

Revision history

Table 53. Document revision history (continued)

STM32F101x4, STM32F101x6

Date

Revision

Changes

Added VFQFPN48 package.

Updated note 2 below Table 39: I2C characteristics

20-May-2010

19-Apr-2011

4

Updated Figure 28: I2C bus AC waveforms and measurement circuit(1)

Updated Figure 27: Recommended NRST pin protection

Updated Section 5.3.12: I/O current injection characteristics

Updated footnotes below Table 5: Voltage characteristics on page 29

and Table 6: Current characteristics on page 30

Updated tw min in Table 19: High-speed external user clock

characteristics on page 42

5

Updated startup time in Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz) on page 45

Added Section 5.3.12: I/O current injection characteristics

Updated Section 5.3.13: I/O port characteristics

78/79

Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

Doc ID 15058 Rev 5

79/79


型号：	STM32F101T4U6
厂家：	ST
描述：	IC,MICROCONTROLLER,32-BIT,CORTEX-M3 CPU,CMOS,LLCC,36PIN,PLASTIC
文件：	总79页 (文件大小：1110K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM32F101T4U6 [STMICROELECTRONICS]

相关型号：

STM32F101T4U6ATR

STM32F101T4U6AXXX

STM32F101T4U6AXXXTR

STM32F101T4U6TR

STM32F101T4U6XXX

STM32F101T4U6XXXTR

STM32F101T6

STM32F101T6T6ATR

STM32F101T6T6AXXX

STM32F101T6T6TR

STM32F101T6T6XXX

STM32F101T6U6