STM32F103RFT7 [STMICROELECTRONICS]
Mainstream Performance line, Arm Cortex-M3 MCU with 768 Kbytes of Flash memory, 72 MHz CPU, motor control, USB and CAN;
| 型号： | STM32F103RFT7 |
| 厂家： | 
ST |
| 描述： | Mainstream Performance line, Arm Cortex-M3 MCU with 768 Kbytes of Flash memory, 72 MHz CPU, motor control, USB and CAN |
| 文件： | 总120页 (文件大小：2547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F103xF
STM32F103xG
XL-density performance line ARM-based 32-bit MCU with 768 KB to
1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces
Target specification
Features
FBGA
■ Core: ARM 32-bit Cortex™-M3 CPU with MPU
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
– 72 MHz maximum frequency,
LFBGA144 10 × 10 mm
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
LQFP144 20 × 20 mm
■ Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
– Single-cycle multiplication and hardware
division
■ Memories
■ Up to 17 timers
– 768 Kbytes to 1 Mbyte of Flash memory
– 96 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
– Up to ten 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 × 16-bit motor control PWM timers with
dead-time generation and emergency stop
– LCD parallel interface, 8080/6800 modes
– 2 × watchdog timers (Independent and
Window)
■ Clock, reset and supply management
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
■ Up to 13 communication interfaces
2
– 4-to-16 MHz crystal oscillator
– Up to 2 × I C interfaces (SMBus/PMBus)
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I S
interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
2
■ Low power
– Sleep, Stop and Standby modes
– V
supply for RTC and backup registers
BAT
■ 3 × 12-bit, 1 µs A/D converters (up to 21
■ CRC calculation unit, 96-bit unique ID
channels)
®
■ ECOPACK packages
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
Table 1.
Device summary
Part number
Reference
■ 2 × 12-bit D/A converters
STM32F103RF STM32F103VF
STM32F103ZF
■ DMA: 12-channel DMA controller
STM32F103xF
STM32F103xG
– Supported peripherals: timers, ADCs, DAC,
2
2
SDIO, I Ss, SPIs, I Cs and USARTs
STM32F103RG STM32F103VG
STM32F103ZG
■ Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
January 2012
Doc ID 16554 Rev 3
1/120
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
www.st.com
1
Contents
STM32F103xF, STM32F103xG
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
®
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
ARM Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 16
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.11 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19
2.3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.19 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.20 Universal synchronous/asynchronous receiver transmitters (USARTs) 21
2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
2.3.22 Inter-integrated sound (I S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.23 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.24 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.25 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.26 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.27 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.28 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Contents
2.3.29 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.30 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.31 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3
4
5
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 42
Embedded reset and power control block characteristics . . . . . . . . . . . 42
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 82
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.18 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 100
Doc ID 16554 Rev 3
3/120
Contents
STM32F103xF, STM32F103xG
5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.1
6.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2.1
6.2.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 115
7
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F103xF and STM32F103xG features and peripheral counts . . . . . . . . . . . . . . . . . 11
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F103xF and STM32F103xG timer feature comparison. . . . . . . . . . . . . . . . . . . . . . 19
STM32F103xF and STM32F103xG pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maximum current consumption in Run mode, code with data processing
Table 15.
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 46
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 47
Typical current consumption in Run mode, code with data processing
Table 16.
Table 17.
Table 18.
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typical current consumption in Sleep mode, code running from Flash or
Table 19.
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 63
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 64
Asynchronous read muxed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 71
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Switching characteristics for PC Card/CF read and write cycles in
attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . 78
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 41.
Table 42.
Table 43.
Doc ID 16554 Rev 3
5/120
List of tables
STM32F103xF, STM32F103xG
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SCL frequency (f
= 36 MHz.,V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
PCLK1
DD
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2
I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
R
max for f
= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
AIN
ADC
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111
LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 113
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
STM32F103xF and STM32F103xG ordering information scheme . . . . . . . . . . . . . . . . . . 117
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
6/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
STM32F103xF and STM32F103xG performance line block diagram. . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F103xF and STM32F103xG XL-density performance line BGA144 ballout . . . . . . 25
STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout. . . . . . 26
STM32F103xF and STM32F103xG XL-density performance line LQFP100 pinout. . . . . . 27
STM32F103xF and STM32F103xG XL-density performance line
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7.
Figure 8.
Figure 9.
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 45
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V)-
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 45
Figure 14. Typical current consumption on V
with RTC on vs. temperature at different V
BAT
BAT
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 15. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
DD
Figure 16. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DD
Figure 17. Typical current consumption in Standby mode versus temperature at
different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DD
Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 62
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 63
Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 26. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 27. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 29. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 30. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 73
Figure 31. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . . 74
Figure 32. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 33. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 34. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 76
Figure 35. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 77
Figure 36. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 37. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 38. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 79
Figure 39. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 80
Doc ID 16554 Rev 3
7/120
List of figures
STM32F103xF, STM32F103xG
Figure 40. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 41. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 42. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 43. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 44. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 45. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2
Figure 46. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 47. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
(1)
Figure 48. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
(1)
Figure 49. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2
(1)
Figure 50. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2
(1)
Figure 51. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 52. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 53. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 54. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 55. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 56. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 57. Power supply and reference decoupling (V
Figure 58. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 104
). . . . . . . . . . . . . . . . 105
REF+
DDA
connected to V
REF+
DDA
Figure 59. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 60. Recommended PCB design rules (0.80/0.75 mm pitch BGA . . . . . . . . . . . . . . . . . . . . . . 109
Figure 61. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 62. LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
(1)
Figure 63. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 64. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 112
(1)
Figure 65. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 66. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 113
(1)
Figure 67. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 68. LQFP100 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
D
A
8/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103xF and STM32F103xG XL-density performance line microcontrollers. For
more details on the whole STMicroelectronics STM32F103xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The XL-density STM32F103xx datasheet should be read in conjunction with the
STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
Doc ID 16554 Rev 3
9/120
Description
STM32F103xF, STM32F103xG
2
Description
The STM32F103xF and STM32F103xG performance line family incorporates the high-
®
performance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-
speed embedded memories (Flash memory up to 1 Mbyte and SRAM up to 96 Kbytes), and
an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer three 12-bit ADCs, ten general-purpose 16-bit timers plus two PWM timers, as
2
well as standard and advanced communication interfaces: up to two I Cs, three SPIs, two
2
I Ss, one SDIO, five USARTs, an USB and a CAN.
The STM32F103xx XL-density performance line family operates in the –40 to +105 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
These features make the STM32F103xx high-density performance line microcontroller
family suitable for a wide range of applications such as motor drives, application control,
medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems and video intercom.
10/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Description
2.1
Device overview
The STM32F103xx XL-density performance line family offers devices in four different
package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
Figure 1 shows the general block diagram of the device family.
Table 2.
STM32F103xF and STM32F103xG features and peripheral counts
STM32F103Rx STM32F103Vx STM32F103Zx
768 KB 1 MB 768 KB 1 MB 768 KB 1 MB
Peripherals
Flash memory
SRAM in Kbytes
FSMC
96
96
Yes(1)
10
2
96
No
Yes
General-purpose
Timers Advanced-control
Basic
2
SPI(I2S)(2)
I2C
3(2)
2
USART
Comm
5
USB
1
CAN
SDIO
1
1
GPIOs
51
80
112
12-bit ADC
3
3
3
Number of channels
16
16
21
12-bit DAC
Number of channels
2
2
CPU frequency
72 MHz
Operating voltage
2.0 to 3.6 V
Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10)
Junction temperature: –40 to + 125 °C (see Table 10)
Operating temperatures
Package
LQFP64
LQFP100
LQFP144, BGA144
1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a
multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND
Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available
in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the
I2S audio mode.
Doc ID 16554 Rev 3
11/120
Description
Figure 1.
STM32F103xF, STM32F103xG
STM32F103xF and STM32F103xG performance line block diagram
TRACECLK
TRACED[0:3]
as AF
TPIU
V
POWER
ETM
Trace/Trig
DD
Flash1 512 KB
64 bit
V
=2 to 3.6V
DD
VOLT. REG.
3.3V TO 1.8V
SWJTAG
V
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDAT
Ib u s
SS
MPU
@V
DD
Flash2 512 KB
64 bit
JTDO
as AF
Dbus
POR
Reset
Cortex-M3 CPU
SUPPLY
SUPERVISION
NRST
F
: 48/72 MHz
max
Int
V
V
POR / PDR
DDA
SSA
System
NVIC
@V
PVD
DDA
RC HS
@V
SRAM
96 Kbyte
DDA
@V
DD
OSC_IN
OSC_OUT
RC LS
XTAL OSC
4-16 MHz
PLL
GP DMA1
IWDG
7 channels
Standby
interface
GP DMA2
V
=1.8V to 3.6V
A[25:0]
D[15:0]
CLK
NOE
NWE
PCLK1
BAT
5 channels
Reset &
clock
controller
PCLK2
PCLK3
HCLK
FCLK
@VSW
OSC32_IN
OSC32_OUT
XTAL 32 kHz
Backup
NE[3:0]
NBL[1:0]
NWAIT
NL
RTC
AWU
TAMPER-RTC
(ALARM OUT)
reg
FSMC
SDIO
Backup interface
as AF
4 Ch, ETR as AF
4 Ch, ETR as AF
TIM2
AHB2
APB2
D[7:0], CMD
CK as AF
APB3
APB1
TIM3
TIM4
TIM5
4 Ch, ETR as AF
4 Ch, ETR as AF
EXT.IT
WKUP
112 AF
GPIO port A
PA[15:0]
PB[15:0]
PC[15:0]
2 channels as AF
1 channel as AF
TIM12
GPIO port B
GPIO port C
TIM13
GPIO port D
GPIO port E
GPIO port F
GPIO port G
PD[15:0]
PE[15:0]
1 channel as AF
TIM14
RX,TX, CTS, RTS,
CK as AF
USART2
USART3
PF[15:0]
PG[15:0]
RX,TX, CTS, RTS,
CK as AF
4 channels
RX,TX as AF
UART4
UART5
4 compl. channels
TIM1
BKIN, ETR input as AF
RX,TX as AF
4 channels
4 compl. channels
BKIN, ETR input as AF
TIM8
MOSI/SD,MISO,
SCK/CK,NSS/WS,
MCLK as AF
MOSI/SD,MISO,
SCK/CK,NSS/WS,
MCLK as AF
SPI2/I2S2
SPI3/I2S3
2 channels as AF
1 channel as AF
TIM9
TIM10
TIM11
1 channel as AF
I2C1
I2C2
SCL,SDA,SMBA
as AF
MOSI,MISO,
SCK,NSS as AF
WWDG
SCL,SDA,SMBA
as AF
SPI1
RX,TX, CTS, RTS,
CK as AF
USART1
bxCAN device
SRAM 512B
Temp sensor
12bit ADC1
USBDP/CAN_TX
USBDM/CAN_RX
8 ADINs common
to the 3 ADCs
USB 2.0 FS device
IF
IF
IF
8 ADINs common
to the ADC1 & 2
12bit DAC1
12bit DAC2
IF
TIM6
TIM7
DAC1_OUT as AF
DAC2_OUT as AF
12bit ADC2
5 ADINs on ADC3
12bit ADC3
VREF–
VREF+
@VDDA
@V
DDA
ai17352
1. TA = –40 °C to +85 °C (suffix 6, see Table 73) or –40 °C to +105 °C (suffix 7, see Table 73), junction temperature up to
105 °C or 125 °C, respectively.
2. AF = alternate function on I/O port pin.
12/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Description
Figure 2.
Clock tree
FLITFCLK
to Flash programming interface
USBCLK
48 MHz
USB
Prescaler
/1, 1.5
to USB interface
I2S3CLK
I2S2CLK
to I2S3
to I2S2
Peripheral clock
enable
Peripheral clock
enable
SDIOCLK
FSMCCLK
to SDIO
8 MHz
Peripheral clock
HSI
HSI RC
enable
to FSMC
Peripheral clock
enable
/2
HCLK
to AHB bus, core,
memory and DMA
72 MHz max
Clock
Enable
/8
to Cortex System timer
SW
PLLSRC
FCLK Cortex
free running clock
36 MHz max
PLLMUL
HSI
AHB
APB1
SYSCLK
..., x16
x2, x3, x4
PLL
PCLK1
Prescaler
Prescaler
PLLCLK
72 MHz
to APB1
/1, 2..512
/1, 2, 4, 8, 16
max
peripherals
Peripheral Clock
Enable
HSE
to TIM2/3/4/5/12/13/14
and TIM6/7
TIMxCLK
TIM2,3,4,5,12,13,14,6,7
If (APB1 prescaler =1) x1
else x2
CSS
Peripheral Clock
Enable
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
/2
72 MHz max
PCLK2
OSC_OUT
OSC_IN
peripherals to APB2
4-16 MHz
Peripheral Clock
Enable
HSE OSC
to TIM1/8
and TIM9/10/11
TIMxCLK
TIM1, 8, 9, 10, 11
If (APB2 prescaler =1) x1
else x2
Peripheral Clock
Enable
/128
LSE
ADC
Prescaler
/2, 4, 6, 8
to ADC1, 2 or 3
OSC32_IN
to RTC
LSE OSC
ADCCLK
RTCCLK
32.768 kHz
OSC32_OUT
HCLK/2
To SDIO AHB interface
/2
RTCSEL[1:0]
Peripheral clock
enable
to Independent Watchdog (IWDG)
LSI
LSI RC
40 kHz
IWDGCLK
Legend:
Main
Clock Output
/2
PLLCLK
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
MCO
HSI
HSE
LSI = Low-speed internal clock signal
LSE = Low-speed external clock signal
SYSCLK
MCO
ai17354
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
Doc ID 16554 Rev 3
13/120
Description
STM32F103xF, STM32F103xG
2.2
Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are
identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as
medium-density devices, the STM32F103xC, STM32F103xD and STM32F103xE are
referred to as high-density devices and the STM32F103xF and STM32F103xG are called
XL-density devices.
Low-density, high-density and XL-density devices are an extension of the STM32F103x8/B
medium-density devices, they are specified in the STM32F103x4/6, STM32F103xC/D/E and
STM32F103xF/G datasheets, respectively. Low-density devices feature lower Flash
memory and RAM capacities, less timers and peripherals. High-density devices have higher
2
Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I S and
DAC. XL-density devices bring even more Flash and RAM memory, and extra features,
namely an MPU, a greater number of timers and a dual bank Flash structure while
remaining fully compatible with the other members of the family.
The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD, STM32F103xE,
STM32F103xF and STM32F103xG are a drop-in replacement for the STM32F103x8/B
devices, allowing the user to try different memory densities and providing a greater degree
of freedom during the development cycle.
Moreover, the STM32F103xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3.
STM32F103xx family
Low-density
devices
Medium-density
devices
High-density devices
XL-density devices
16 KB
Pinout Flash
32 KB
64 KB
Flash
128 KB
Flash
256 KB 384 KB 512 KB
768 KB Flash 1 MB Flash
Flash(1)
Flash
Flash
Flash
48 or
64 KB(2)
RAM
6 KB
RAM
10 KB
RAM
20 KB
RAM
20 KB
RAM
64 KB
RAM
64 KB
RAM
96 KB RAM
96 KB RAM
144
100
5 × USARTs
10 × 16-bit timers,
2 × basic timers
5 × USARTs
4 × 16-bit timers,
2 × basic timers
3 × SPIs, 2 × I2Ss, 2 × I2Cs
USB, CAN, 2 × PWM timers
3 × ADCs, 2 × DACs, 1 × SDIO,
Cortex-M3 with MPU
3 × SPIs, 2 × I2Ss, 2 × I2Cs
USB, CAN, 2 × PWM timers
3 × ADCs, 2 × DACs,
1 × SDIO
3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs,
USB, CAN,
1 × PWM timer
2 × ADCs
2 × USARTs
64
2 × 16-bit timers
1 × SPI, 1 × I2C,
USB, CAN,
FSMC (100- and 144-pin
packages(4)), dual bank Flash
memory
FSMC (100- and 144-pin
packages(3)
)
1 × PWM timer
2 × ADCs
48
36
1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference
datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices.
2. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.
3. Ports F and G are not available in devices delivered in 100-pin packages.
4. Ports F and G are not available in devices delivered in 100-pin packages.
14/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Description
2.3
Overview
®
2.3.1
ARM Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
With its embedded ARM core, STM32F103xF and STM32F103xG performance line family
is compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
2.3.2
Memory protection unit
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
2.3.3
2.3.4
Embedded Flash memory
768 Kbytes to 1 Mbyte of embedded Flash are available for storing programs and data. The
Flash memory is organized as two banks. The first bank has a size of 512 Kbytes. The
second bank is either 256 or 512 Kbytes depending on the device. This gives the device the
capability of writing to one bank while executing code from the other bank (read-while-write
capability).
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Doc ID 16554 Rev 3
15/120
Description
STM32F103xF, STM32F103xG
2.3.5
Embedded SRAM
96 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
2.3.6
FSMC (flexible static memory controller)
The FSMC is embedded in the STM32F103xF and STM32F103xG performance line family.
It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash,
SRAM, PSRAM, NOR and NAND.
Functionality overview:
●
●
●
●
The three FSMC interrupt lines are ORed in order to be connected to the NVIC
Write FIFO
Code execution from external memory except for NAND Flash and PC Card
The targeted frequency, f
, is HCLK/2, so external access is at 36 MHz when HCLK
CLK
is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz
2.3.7
2.3.8
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high-
performance solutions using external controllers with dedicated acceleration.
Nested vectored interrupt controller (NVIC)
The STM32F103xF and STM32F103xG performance line embeds a nested vectored
interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16
interrupt lines of Cortex™-M3) and 16 priority levels.
●
●
●
●
●
●
●
●
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.9
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
16/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Description
2.3.10
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed
APB domain is 36 MHz. See Figure 2 for details on the clock tree.
2.3.11
Boot modes
At startup, boot pins are used to select one of three boot options:
●
Boot from user Flash: you have an option to boot from any of two memory banks. By
default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash
memory bank 2 by setting a bit in the option bytes.
●
●
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1.
2.3.12
Power supply schemes
●
V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V pins.
DD
●
V
, V
= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
SSA DDA
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC
is used). V and V must be connected to V and V , respectively.
DDA
SSA
DD
SS
●
V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V is not present.
DD
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.
2.3.13
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V is below a specified threshold, V
, without the need for an
DD
POR/PDR
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
/V power supply and compares it to the V threshold. An interrupt can be
V
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is higher
DD DDA
PVD
DD DDA
than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics for the values of
V
and V
.
POR/PDR
PVD
Doc ID 16554 Rev 3
17/120
Description
STM32F103xF, STM32F103xG
2.3.14
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop modes.
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode.
2.3.15
Low-power modes
The STM32F103xF and STM32F103xG performance line supports three low-power modes
to achieve the best compromise between low power consumption, short startup time and
available wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.3.16
DMA
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-
peripheral transfers. The two DMA controllers support circular buffer management,
removing the need for user code intervention when the controller reaches the end of the
buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
18/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Description
2
The DMA can be used with the main peripherals: SPI, I C, USART, general-purpose, basic
2
and advanced-control timers TIMx, DAC, I S, SDIO and ADC.
2.3.17
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
supply when present or through the V
pin. The backup registers are forty-two 16-bit
DD
BAT
registers used to store 84 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.18
Timers and watchdogs
The XL-density STM32F103xx performance line devices include up to two advanced-control
timers, up to ten general-purpose timers, two basic timers, two watchdog timers and a
SysTick timer.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4.
STM32F103xF and STM32F103xG timer feature comparison
Counter Counter
DMArequest Capture/compare Complementary
Timer
Prescaler factor
resolution
type
generation
channels
outputs
Up,
down,
up/down
Any integer between
1 and 65536
TIM1, TIM8
16-bit
Yes
4
Yes
Up,
down,
up/down
TIM2, TIM3,
TIM4, TIM5
Any integer between
1 and 65536
16-bit
Yes
4
No
Any integer between
1 and 65536
TIM9, TIM12
16-bit
16-bit
16-bit
Up
Up
Up
No
No
2
1
0
No
No
No
TIM10, TIM11
TIM13, TIM14
Any integer between
1 and 65536
Any integer between
1 and 65536
TIM6, TIM7
Yes
Doc ID 16554 Rev 3
19/120
Description
STM32F103xF, STM32F103xG
Advanced-control timers (TIM1 and TIM8)
The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase
PWM multiplexed on 6 channels. They have complementary PWM outputs with
programmable inserted dead-times. They can also be seen as a complete general-purpose
timer. The 4 independent channels can be used for:
●
●
●
●
Input capture
Output compare
PWM generation (edge or center-aligned modes)
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switch driven by these outputs.
Many features are shared with those of the general-purpose TIM timers which have the
same architecture. The advanced-control timer can therefore work together with the TIM
timers via the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)
There are10 synchronizable general-purpose timers embedded in the STM32F103xF and
STM32F103xG performance line devices (see Table 4 for differences).
●
TIM2, TIM3, TIM4, TIM5
There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)
embedded in the STM32F103xF and STM32F103xG access line devices.
These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler
and feature 4 independent channels each for input capture/output compare, PWM or
one-pulse mode output. This gives up to 16 input captures / output compares / PWMs
on the largest packages.
Their counter can be frozen in debug mode. Any of the general-purpose timers can be
used to generate PWM outputs. They all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
●
TIM10, TIM11 and TIM9
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10 and TIM11 feature one independent channel, whereas TIM9 has two
independent channels for input capture/output compare, PWM or one-pulse mode
output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured
general-purpose timers. They can also be used as simple time bases.
●
TIM13, TIM14 and TIM12
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13 and TIM14 feature one independent channel, whereas TIM12 has two
independent channels for input capture/output compare, PWM or one-pulse mode
output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured
general-purpose timers. They can also be used as simple time bases.
20/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Description
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
●
●
●
●
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
2.3.19
2.3.20
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
Universal synchronous/asynchronous receiver transmitters (USARTs)
The STM32F103xF and STM32F103xG performance line embeds three universal
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and
two universal asynchronous receiver transmitters (UART4 and UART5).
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other
available interfaces communicate at up to 2.25 Mbit/s.
USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.
Doc ID 16554 Rev 3
21/120
Description
STM32F103xF, STM32F103xG
2.3.21
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
All SPIs can be served by the DMA controller.
2
2.3.22
2.3.23
Inter-integrated sound (I S)
2
Two standard I S interfaces (multiplexed with SPI2 and SPI3) are available, that can be
operated in master or slave mode. These interfaces can be configured to operate with 16/32
bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to
48 kHz are supported. When either or both of the I S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
2
SDIO
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD
Memory Card Specifications Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital
protocol Rev1.1.
2.3.24
2.3.25
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
Universal serial bus (USB)
The STM32F103xF and STM32F103xG performance line embed a USB device peripheral
compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12
Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume
support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock
source must use a HSE crystal oscillator).
2.3.26
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable.
22/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Description
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.3.27
ADC (analog to digital converter)
Three 12-bit analog-to-digital converters are embedded into STM32F103xF and
STM32F103xG performance line devices and each ADC shares up to 21 external channels,
performing conversions in single-shot or scan modes. In scan mode, automatic conversion
is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
●
●
●
Simultaneous sample and hold
Interleaved sample and hold
Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control
timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection
trigger, respectively, to allow the application to synchronize A/D conversion and timers.
2.3.28
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.
This dual digital Interface supports the following features:
●
●
●
●
●
●
●
●
●
●
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference V
REF+
Eight DAC trigger inputs are used in the STM32F103xF and STM32F103xG performance
line family. The DAC channels are triggered through the timer update outputs that are also
connected to different DMA channels.
Doc ID 16554 Rev 3
23/120
Description
STM32F103xF, STM32F103xG
2.3.29
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V < 3.6 V. The temperature sensor is internally
DDA
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.3.30
2.3.31
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Embedded Trace Macrocell™
®
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F10xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.
24/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
3
Pinouts and pin descriptions
Figure 3.
STM32F103xF and STM32F103xG XL-density performance line BGA144 ballout
1
2
3
4
5
6
7
8
9
10
11
12
PB4
JTRST
PC13-
TAMPER-RTC
PB3
JTDO
PA15
JTDI
PA14
JTCK
PA13
JTMS
PE3
PE2
PE1
PE0
PD6
PD7
A
B
C
D
E
F
PC14-
OSC32_IN
PE4
PE5
PF0
PE6
PF1
PF2
PF5
PB9
PB8
PB5
PB6
PB7
PG15
PG14
PG13
PG12
PG11
PG10
PG9
PD5
PD4
PD3
PD2
PC11
PC12
PD1
PC10
NC
PA12
PA11
PA9
PA8
PC7
PC6
PG5
PC15-
OSC32_OUT
V
BAT
OSC_IN
V
V
BOOT0
PA10
PC9
PC8
PG8
PG6
SS_5
DD_5
PF4
OSC_OUT
V
V
V
SS_10
PF3
PD0
SS_3
SS_11
V
V
V
V
V
DD_8
NRST
PF10
PC0
PF7
PF9
PF6
PF8
PC2
PA4
PA5
PA6
PA7
V
V
DD_9
DD_4
DD_3
DD_11
DD_10
DD_2
G
H
J
V
V
V
V
SS_8
V
V
V
SS_9
DD_6
DD_7
DD_1
SS_4
SS_2
V
V
V
PE11
PD11
PG7
PC1
PC3
SS_6
SS_7
PG1
SS_1
PE10
PE9
PB2/
BOOT1
V
PA0-WKUP
PA1
PC4
PC5
PB0
PB1
PE12
PE13
PE14
PE15
PD10
PD9
PG4
PD13
PD12
PB11
PG3
PD14
PB14
PB12
PG2
PD15
PB15
PB13
SSA
K
L
V
V
PF13
PF12
PF11
PG0
REF–
PA2
PF15
PF14
PE8
PD8
REF+
V
PA3
PE7
M
PB10
DDA
AI14798b
Doc ID 16554 Rev 3
25/120
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Figure 4. STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
V
V
NC
DD_2
SS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
9
PF0
PF1
PF2
PF3
PF4
PF5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
V
V
DD_9
SS_9
V
V
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
SS_5
LQFP144
DD_5
PF6
PF7
PF8
PF9
PF10
OSC_IN
OSC_OUT
NRST
PC0
V
V
DD_8
SS_8
PC1
PC2
PC3
PD13
PD12
PD11
PD10
PD9
V
V
V
V
SSA
REF-
PD8
REF+
PB15
PB14
PB13
PB12
DDA
PA0-WKUP
PA1
PA2
ai14667
26/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Figure 5.
Pinouts and pin descriptions
STM32F103xF and STM32F103xG XL-density performance line LQFP100
pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD_5
OSC_IN
OSC_OUT
NRST
LQFP100
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PD8
PB15
PB14
PB13
PB12
PA0-WKUP
PA1
PA2
ai14391
Doc ID 16554 Rev 3
27/120
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Figure 6. STM32F103xF and STM32F103xG XL-density performance line
LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
PC0
PC1
PC2
PC3
8
LQFP64
9
10
11
12
13
14
15
16
PC6
VSSA
VDDA
PA0-WKUP
PB15
PB14
PB13
PB12
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ai14392
28/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Alternate functions(4)
Table 5.
Pins
STM32F103xF and STM32F103xG pin definitions
Main
Pin name
function(3)
(after reset)
Default
Remap
FT
FT
FT
FT
FT
A3
A2
B2
B3
B4
C2
-
1
1
2
3
4
5
6
PE2
PE3
PE4
PE5
PE6
VBAT
I/O
I/O
I/O
I/O
I/O
S
PE2
PE3
PE4
PE5
PE6
VBAT
TRACECK / FSMC_A23
TRACED0 / FSMC_A19
TRACED1/ FSMC_A20
TRACED2/ FSMC_A21
TRACED3 / FSMC_A22
-
-
2
3
4
5
6
-
TIM9_CH1
TIM9_CH2
-
1
PC13-TAMPER-
RTC(5)
A1
B1
C1
2
3
4
7
8
9
7
I/O
PC13(6)
PC14(6)
PC15(6)
TAMPER-RTC
OSC32_IN
8 PC14-OSC32_IN(5) I/O
PC15-
9
I/O
OSC32_OUT
OSC32_OUT(5)
PF0
C3
C4
D4
E2
E3
E4
D2
D3
F3
F2
G3
G2
G1
D1
E1
F1
H1
H2
-
-
-
-
-
-
-
-
10
11
12
13
14
15
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
PF0
PF1
FSMC_A0
FSMC_A1
FSMC_A2
FSMC_A3
FSMC_A4
FSMC_A5
PF1
-
PF2
PF2
-
PF3
PF3
-
PF4
PF4
-
PF5
PF5
-
10 16
11 17
VSS_5
VDD_5
PF6
VSS_5
VDD_5
PF6
-
S
-
-
-
-
-
-
18
19
20
21
22
I/O
ADC3_IN4 / FSMC_NIORD
ADC3_IN5 / FSMC_NREG
ADC3_IN6 / FSMC_NIOWR
ADC3_IN7 / FSMC_CD
TIM10_CH1
TIM11_CH1
TIM13_CH1
TIM14_CH1
-
PF7
I/O
PF7
-
PF8
I/O
PF8
-
PF9
I/O
PF9
-
PF10
OSC_IN
OSC_OUT
NRST
PC0
I/O
PF10
OSC_IN
OSC_OUT
NRST
PC0
ADC3_IN8 / FSMC_INTR
5
6
7
8
9
12 23
13 24
14 25
15 26
16 27
I
PD0(7)
PD1(7)
O
I/O
I/O
ADC123_IN10
ADC123_IN11
ADC123_IN12
ADC123_IN13
PC1
I/O
PC1
H3 10 17 28
H4 11 18 29
J1 12 19 30
PC2
I/O
PC2
PC3
I/O
PC3
VSSA
VREF-
S
VSSA
VREF-
K1
-
20 31
S
Doc ID 16554 Rev 3
29/120
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Alternate functions(4)
Table 5.
Pins
STM32F103xF and STM32F103xG pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
L1
-
21 32
VREF+
VDDA
S
S
VREF+
VDDA
M1 13 22 33
WKUP/USART2_CTS(8)
/
J2 14 23 34
PA0-WKUP
PA1
I/O
I/O
I/O
PA0
PA1
PA2
ADC123_IN0 / TIM2_CH1_ETR /
TIM5_CH1 / TIM8_ETR
USART2_RTS(7) / ADC123_IN1 /
TIM5_CH2 / TIM2_CH2(7)
K2 15 24 35
L2 16 25 36
USART2_TX(7) / TIM5_CH3 /
ADC123_IN2 / TIM9_CH1 /
TIM2_CH3 (7)
PA2
USART2_RX(7) / TIM5_CH4 /
M2 17 26 37
PA3
I/O
PA3
ADC123_IN3 / TIM2_CH4(7)
TIM9_CH2
/
G4 18 27 38
F4 19 28 39
VSS_4
VDD_4
S
S
VSS_4
VDD_4
SPI1_NSS(7) / USART2_CK(7)
DAC_OUT1 / ADC12_IN4
/
J3 20 29 40
K3 21 30 41
PA4
PA5
I/O
I/O
PA4
PA5
SPI1_SCK(7) / DAC_OUT2 /
ADC12_IN5
SPI1_MISO(7) / TIM8_BKIN /
L3 22 31 42
M3 23 32 43
PA6
PA7
I/O
I/O
PA6
PA7
ADC12_IN6 / TIM3_CH1(7)
TIM13_CH1
/
TIM1_BKIN
TIM1_CH1N
SPI1_MOSI(7)/ TIM8_CH1N /
ADC12_IN7 / TIM3_CH2(7)
TIM14_CH1
/
J4 24 33 44
K4 25 34 45
PC4
PC5
I/O
I/O
PC4
PC5
ADC12_IN14
ADC12_IN15
ADC12_IN8 / TIM3_CH3 /
TIM8_CH2N
L4 26 35 46
PB0
PB1
I/O
I/O
PB0
PB1
TIM1_CH2N
TIM1_CH3N
ADC12_IN9 / TIM3_CH4(7)
TIM8_CH3N
/
M4 27 36 47
J5 28 37 48
PB2
PF11
PF12
VSS_6
VDD_6
PF13
I/O FT PB2/BOOT1
M5
L5
-
-
-
-
-
-
-
-
-
-
49
50
51
52
53
I/O FT
I/O FT
S
PF11
PF12
VSS_6
VDD_6
PF13
FSMC_NIOS16
FSMC_A6
H5
G5
K5
S
I/O FT
FSMC_A7
30/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Alternate functions(4)
Table 5.
Pins
STM32F103xF and STM32F103xG pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
M6
L6
K6
J6
-
-
54
55
56
57
PF14
PF15
PG0
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
PF14
PF15
PG0
FSMC_A8
FSMC_A9
FSMC_A10
FSMC_A11
FSMC_D4
FSMC_D5
FSMC_D6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PG1
PG1
M7
L7
K7
H6
G6
J7
38 58
39 59
40 60
PE7
PE7
TIM1_ETR
TIM1_CH1N
TIM1_CH1
PE8
PE8
PE9
PE9
-
-
61
62
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
S
41 63
42 64
43 65
44 66
45 67
46 68
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
FSMC_D7
FSMC_D8
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
TIM2_CH3
TIM2_CH4
H8
J8
FSMC_D9
K8
L8
M8
FSMC_D10
FSMC_D11
FSMC_D12
M9 29 47 69
M10 30 48 70
H7 31 49 71
G7 32 50 72
I2C2_SCL / USART3_TX(7)
I2C2_SDA / USART3_RX(7)
S
SPI2_NSS / I2S2_WS /
I2C2_SMBA / USART3_CK(7)
TIM1_BKIN(7)
M11 33 51 73
PB12
I/O FT
PB12
/
SPI2_SCK / I2S2_CK /
M12 34 52 74
L11 35 53 75
L12 36 54 76
PB13
PB14
PB15
I/O FT
I/O FT
I/O FT
PB13
PB14
PB15
USART3_CTS(7) / TIM1_CH1N
SPI2_MISO / TIM1_CH2N /
USART3_RTS(7)/ TIM12_CH1
SPI2_MOSI / I2S2_SD /
TIM1_CH3N(7) / TIM12_CH2
L9
K9
J9
-
-
-
-
55 77
56 78
57 79
58 80
PD8
PD9
I/O FT
I/O FT
I/O FT
I/O FT
PD8
PD9
FSMC_D13
FSMC_D14
FSMC_D15
FSMC_A16
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
PD10
PD11
PD10
PD11
H9
TIM4_CH1 /
USART3_RTS
L10
-
59 81
PD12
I/O FT
PD12
FSMC_A17
Doc ID 16554 Rev 3
31/120
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Alternate functions(4)
Table 5.
Pins
STM32F103xF and STM32F103xG pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
K10
G8
-
60 82
PD13
VSS_8
VDD_8
PD14
PD15
PG2
I/O FT
S
PD13
VSS_8
VDD_8
PD14
PD15
PG2
FSMC_A18
TIM4_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
84
F8
S
K11
K12
J12
J11
J10
H12
H11
H10
G11
G10
F10
61 85
62 86
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
FSMC_D0
FSMC_D1
TIM4_CH3
TIM4_CH4
-
-
-
-
-
-
-
-
-
87
88
89
90
91
92
93
94
95
FSMC_A12
FSMC_A13
FSMC_A14
FSMC_A15
FSMC_INT2
FSMC_INT3
PG3
PG3
PG4
PG4
PG5
PG5
PG6
PG6
PG7
PG7
PG8
PG8
VSS_9
VDD_9
VSS_9
VDD_9
S
I2S2_MCK / TIM8_CH1 /
SDIO_D6
G12 37 63 96
F12 38 64 97
PC6
PC7
I/O FT
I/O FT
PC6
PC7
TIM3_CH1
TIM3_CH2
I2S3_MCK / TIM8_CH2 /
SDIO_D7
F11 39 65 98
E11 40 66 99
PC8
PC9
I/O FT
I/O FT
PC8
PC9
TIM8_CH3 / SDIO_D0
TIM8_CH4 / SDIO_D1
TIM3_CH3
TIM3_CH4
USART1_CK / TIM1_CH1(7)
MCO
/
E12 41 67 100
PA8
I/O FT
PA8
D12 42 68 101
D11 43 69 102
PA9
I/O FT
I/O FT
PA9
USART1_TX(7) / TIM1_CH2(7)
USART1_RX(7) / TIM1_CH3(7)
PA10
PA10
USART1_CTS / USBDM /
CAN_RX(7) / TIM1_CH4(7)
C12 44 70 103
B12 45 71 104
A12 46 72 105
PA11
PA12
PA13
I/O FT
I/O FT
I/O FT
PA11
PA12
USART1_RTS / USBDP /
CAN_TX(7) / TIM1_ETR(7)
JTMS-
SWDIO
PA13
PA14
C11
-
73 106
Not connected
G9 47 74 107
F9 48 75 108
V
S
S
V
SS_2
SS_2
DD_2
V
V
DD_2
JTCK-
SWCLK
A11 49 76 109
PA14
I/O FT
32/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Alternate functions(4)
Table 5.
Pins
STM32F103xF and STM32F103xG pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
TIM2_CH1_ETR
PA15 / SPI1_NSS
A10 50 77 110
PA15
I/O FT
JTDI
SPI3_NSS / I2S3_WS
B11 51 78 111
B10 52 79 112
C10 53 80 113
PC10
PC11
PC12
PD0
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
PC10
PC11
PC12
PD0
UART4_TX / SDIO_D2
UART4_RX / SDIO_D3
UART5_TX / SDIO_CK
USART3_TX
USART3_RX
USART3_CK
CAN_RX
(9)
E10
D10
-
-
81 114
82 115
FSMC_D2
(9)
PD1
PD1
FSMC_D3
CAN_TX
TIM3_ETR / UART5_RX /
SDIO_CMD
E9 54 83 116
PD2
I/O FT
PD2
D9
C9
B9
E7
F7
A8
A9
E8
D8
C8
B8
D7
C7
E6
F6
B7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
84 117
85 118
86 119
PD3
PD4
PD5
I/O FT
I/O FT
I/O FT
S
PD3
PD4
PD5
FSMC_CLK
FSMC_NOE
FSMC_NWE
USART2_CTS
USART2_RTS
USART2_TX
-
-
120
121
V
V
SS_10
DD_10
SS_10
DD_10
V
S
V
87 122
88 123
PD6
PD7
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
PD6
PD7
FSMC_NWAIT
FSMC_NE1 / FSMC_NCE2
FSMC_NE2 / FSMC_NCE3
FSMC_NCE4_1 / FSMC_NE3
FSMC_NCE4_2
USART2_RX
USART2_CK
-
-
-
-
-
-
-
-
-
124
125
126
127
128
129
130
131
132
PG9
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
FSMC_NE4
FSMC_A24
FSMC_A25
S
I/O FT
PB3/TRACESWO
TIM2_CH2 /
A7 55 89 133
A6 56 90 134
PB3/
PB4
I/O FT
I/O FT
JTDO
SPI3_SCK / I2S3_CK/
SPI3_MISO
SPI1_SCK
PB4 / TIM3_CH1
SPI1_MISO
NJTRST
I2C1_SMBA / SPI3_MOSI /
I2S3_SD
TIM3_CH2 /
SPI1_MOSI
B6 57 91 135
C6 58 92 136
D6 59 93 137
PB5
PB6
PB7
I/O
PB5
PB6
PB7
I/O FT
I/O FT
I2C1_SCL(8)/ TIM4_CH1(8)
USART1_TX
USART1_RX
I2C1_SDA(8) / FSMC_NADV /
TIM4_CH2(8)
Doc ID 16554 Rev 3
33/120
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Alternate functions(4)
Table 5.
Pins
STM32F103xF and STM32F103xG pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
D5 60 94 138
C5 61 95 139
BOOT0
PB8
I
BOOT0
PB8
TIM4_CH3(8) / SDIO_D4 /
TIM10_CH1
I2C1_SCL/
CAN_RX
I/O FT
TIM4_CH4(8) / SDIO_D5 /
TIM11_CH1
I2C1_SDA /
CAN_TX
B5 62 96 140
PB9
I/O FT
PB9
A5
A4
-
-
97 141
98 142
PE0
PE1
I/O FT
PE0
PE1
TIM4_ETR / FSMC_NBL0
FSMC_NBL1
I/O FT
E5 63 99 143
F5 64 100 144
VSS_3
VDD_3
S
S
VSS_3
VDD_3
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144/BGA144
packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate
function I/O and debug configuration section in the STM32F10xxx reference manual.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
34/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Pinouts and pin descriptions
Table 6.
Pins
FSMC pin definition
FSMC
LQFP100(1)
NOR/PSRAM/
CF
CF/IDE
NOR/PSRAM Mux NAND 16 bit
SRAM
PE2
PE3
A23
A19
A20
A21
A22
A0
A23
A19
A20
A21
A22
Yes
Yes
PE4
Yes
PE5
Yes
PE6
Yes
PF0
A0
A1
A0
A1
A2
-
PF1
A1
-
PF2
A2
A2
-
PF3
A3
A3
-
PF4
A4
A4
-
PF5
A5
A5
-
PF6
NIORD
NREG
NIOWR
CD
NIORD
NREG
NIOWR
CD
-
PF7
-
-
PF8
PF9
-
PF10
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PE7
INTR
NIOS16
A6
INTR
-
NIOS16
-
A6
A7
-
A7
-
A8
A8
-
A9
A9
-
A10
A10
A11
D4
-
-
D4
D5
D4
D5
DA4
DA5
D4
D5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PE8
D5
PE9
D6
D6
D6
DA6
D6
PE10
PE11
PE12
PE13
PE14
PE15
PD8
D7
D7
D7
DA7
D7
D8
D8
D8
DA8
D8
D9
D9
D9
DA9
D9
D10
D11
D12
D13
D10
D11
D12
D13
D10
D11
D12
D13
DA10
DA11
DA12
DA13
D10
D11
D12
D13
Doc ID 16554 Rev 3
35/120
Pinouts and pin descriptions
STM32F103xF, STM32F103xG
Table 6.
Pins
FSMC pin definition (continued)
FSMC
LQFP100(1)
NOR/PSRAM/
CF
CF/IDE
NOR/PSRAM Mux NAND 16 bit
SRAM
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PG2
PG3
PG4
PG5
PG6
PG7
PD0
D14
D15
D14
D15
D14
D15
A16
A17
A18
D0
DA14
DA15
A16
D14
D15
CLE
ALE
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
A17
A18
D0
D1
D0
D1
DA0
DA1
D0
D1
D1
A12
A13
A14
A15
-
-
-
INT2
INT3
D2
-
-
D2
D3
D2
D3
D2
D3
DA2
DA3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
PD1
D3
PD3
CLK
NOE
NWE
NWAIT
NE1
NE2
NE3
CLK
PD4
NOE
NWE
NOE
NWE
NOE
NWE
NWAIT
NE1
NOE
NWE
PD5
PD6
NWAIT
NWAIT
NWAIT
NCE2
NCE3
PD7
PG9
PG10
PG11
PG12
PG13
PG14
PB7
NE2
NCE4_1 NCE4_1
NCE4_2 NCE4_2
NE3
-
-
NE4
A24
NE4
A24
-
-
A25
A25
-
NADV
NBL0
NBL1
NADV
NBL0
NBL1
Yes
Yes
Yes
PE0
PE1
1. Ports F and G are not available in devices delivered in 100-pin packages.
36/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Memory mapping
4
Memory mapping
The memory map is shown in Figure 7.
Figure 7. Memory map
Reserved
0xA000 1000 - 0xBFFF FFFF
0xA000 0000 - 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
FSMC register
FSMC bank4 PCCARD
FSMC bank3 NAND (NAND2)
0x8000 0000 - 0x8FFF FFFF
FSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF
FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF
FSMC bank1 NOR/PSRAM 3
0x6800 0000 - 0x6BFF FFFF
0x6400 0000 - 0x67FF FFFF
FSMC bank1 NOR/PSRAM 2
0x6000 0000 - 0x63FF FFFF
0x4002 4400 - 0x5FFF FFFF
0x4002 3000 - 0x4002 33FF
FSMC bank1 NOR/PSRAM 1
Reserved
CRC
Reserved
Flash interfaces 1 & 2
Reserved
RCC
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
Reserved
DMA2
DMA1
0x4001 8400 - 0x4001 FFFF
0x4001 8000 - 0x4001 83FF
0x4001 5800 - 0x4001 7FFF
0x4001 5400 - 0x4001 57FF
Reserved
SDIO
Reserved
TIM11
TIM10
TIM9
0x4001 5000 - 0x4001 53FF
0x4001 4C00 - 0x4001 4FFF
Reserved
ADC3
USART1
TIM8
SPI1
TIM1
ADC2
ADC1
Port G
Port F
Port E
Port D
Port C
Port B
Port A
EXTI
0x4001 4000 - 0x4001 4BFF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0xFFFF FFFF
512-Mbyte
block 7
Cortex-M3's
internal
0x4001 2000 - 0x4001 23FF
0x4001 1C00 - 0x4001 1FFF
0x4001 1800 - 0x4001 1BFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0xE000 0000
0xDFFF FFFF
peripherals
512-Mbyte
block 6
Not used
0x4001 0C00 - 0x4001 0FFF
0x4001 0800 - 0x4001 0BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 7800 - 0x4000 FFFF
0xC000 0000
0xBFFF FFFF
AFIO
Reserved
DAC
PWR
BKP
512-Mbyte
block 5
FSMC register
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
Reserved
BxCAN
0xA000 0000
0x9FFF FFFF
0x4000 6400 - 0x4000 67FF
512-Mbyte
block 4
FSMC bank 3
& bank4
Shared USB/CAN SRAM 512
0x4000 6000 - 0x4000 63FF
bytes
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
USB registers
I2C2
0x8000 0000
I2C1
0x7FFF FFFF
UART5
512-Mbyte
block 3
FSMC bank1
& bank2
UART4
USART3
USART2
Reserved
0x6000 0000
0x5FFF FFFF
SPI3/I2S3
512-Mbyte
block 2
Peripherals
SPI2/I2S2
Reserved
IWDG
WWDG
RTC
0x4000 0000
0x3FFF FFFF
512-Mbyte
block 1
SRAM
Reserved
TIM14
TIM13
TIM12
TIM7
0x2000 0000
0x1FFF FFFF
512-Mbyte
block 0
Code
TIM6
TIM5
0x3FFF FFFF
Reserved
TIM4
0x2001 8000
0x2001 7FFF
0x0000 0000
TIM3
SRAM (96 KB aliased
by bit-banding)
TIM2
0x2000 0000
Option bytes
System memory
Reserved
Flash memory bank 2
(256 KB or 512 KB)
0x1FFF F800 - 0x1FFF F80F
0x1FFF E000- 0x1FFF F7FF
0x0810 0000 - 0x1FFF DFFF
0x080F FFFF
0x0808 0000
0x0807 FFFF
Flash memory bank 1
(512 KB)
0x0800 0000
Reserved
0x0010 0000 - 0x07FF FFFF
Aliased to Flash or system 0x000F FFFF
memory depending on
BOOT pins
0x0000 0000
ai17353
Doc ID 16554 Rev 3
37/120
Electrical characteristics
STM32F103xF, STM32F103xG
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
2 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2Σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8.
Pin loading conditions
Figure 9.
Pin input voltage
STM32F103xx pin
STM32F103xx pin
C = 50 pF
V
IN
ai14141
ai14142
38/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
5.1.6
Power supply scheme
Figure 10. Power supply scheme
ꢀ
6
"!4
"ACKUP CIRCUITRY
ꢉ/3#ꢌꢅ+ꢈ24#ꢈ
7AKEꢍUP LOGIC
0O WER SWITCH
ꢀꢆꢐꢍꢌꢆꢑ6
"ACKUP REGISTERSꢋ
/54
).
)/
,OGIC
'0 )ꢄ/S
+ERNEL LOGIC
ꢉ#05ꢈ
$IGITAL
ꢊ -EMORIESꢋ
6
$$
6
$$ꢀꢄꢅꢄꢆꢆꢆꢄꢀꢀ
2EGULATOR
ꢀꢀ § ꢀꢃꢃ N&
ꢎ ꢀ § ꢂꢆꢏ &
6
33ꢀꢄꢅꢄꢆꢆꢆꢄꢀꢀ
6
$$
6
$$!
6
2%&
6
2%&ꢎ
!$#ꢄ
$!#
!NALOGꢇ
2#Sꢈ 0,,ꢈ
ꢆꢆꢆ
ꢀꢃ N&
ꢎ ꢀ &
ꢀꢃ N&
ꢎ ꢀ &
6
2%&ꢍ
6
33!
AIꢀꢁꢂꢃꢀ
Caution:
In Figure 10, the 4.7 µF capacitor must be connected to V
.
DD3
5.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
Doc ID 16554 Rev 3
39/120
Electrical characteristics
STM32F103xF, STM32F103xG
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics,
Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 7.
Symbol
Voltage characteristics
Ratings
External main supply voltage (including VDDA
Min
Max
Unit
VDD–VSS
–0.3
4.0
(1)
and VDD
)
V
Input voltage on five volt tolerant pin
Input voltage on any other pin
VSS −0.3
VDD + 4.0
(2)
VIN
VSS −0.3
4.0
50
50
|ΔVDDx
|
Variations between different VDD power pins
Variations between all the different ground pins
-
-
mV
|VSSX −VSS
|
see Section 5.3.12:
Absolute maximum ratings
(electrical sensitivity)
Electrostatic discharge voltage (human body
model)
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum
allowed injected current values.
Table 8.
Symbol
IVDD
IVSS
Current characteristics
Ratings
Max.
Unit
Total current into VDD/VDDA power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on five volt tolerant pins(3)
Injected current on any other pin(4)
150
150
25
IIO
−25
-5/+0
5
mA
(2)
IINJ(PIN)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note 3 below Table 65 on page 103.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage
values.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
40/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Table 9.
Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Table 10. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK1
fPCLK2
VDD
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
0
0
0
2
72
36
72
3.6
MHz
V
Analog operating voltage
(ADC not used)
2
3.6
3.6
Must be the same potential
as VDD
(1)
VDDA
V
V
(2)
Analog operating voltage
(ADC used)
2.4
VBAT
Backup operating voltage
1.8
3.6
666
434
444
500
LQFP144
LQFP100
LQFP64
-
-
-
-
Power dissipation at TA =
85 °C for suffix 6 or TA =
105 °C for suffix 7(3)
PD
mW
LFBGA144
WLCSP64
-
400
Maximum power dissipation –40
Low power dissipation(4)
–40
Maximum power dissipation –40
85
Ambient temperature for 6
suffix version
°C
°C
°C
105
105
125
105
125
TA
TJ
Ambient temperature for 7
suffix version
Low power dissipation(4)
–40
–40
–40
6 suffix version
Junction temperature range
7 suffix version
1. When the ADC is used, refer to Table 62: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 114).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 114).
Doc ID 16554 Rev 3
41/120
Electrical characteristics
STM32F103xF, STM32F103xG
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 11 are derived from tests performed under the ambient
temperature condition summarized in Table 10.
Table 11. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
∞
Unit
VDD rise time rate
0
tVDD
µs/V
V
DD fall time rate
20
∞
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 12 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
Table 12. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
2.1 2.18 2.26
2.08 2.16
V
V
2
2.19 2.28 2.37
2.09 2.18 2.27
2.28 2.38 2.48
2.18 2.28 2.38
2.38 2.48 2.58
2.28 2.38 2.48
2.47 2.58 2.69
2.37 2.48 2.59
2.57 2.68 2.79
2.47 2.58 2.69
2.66 2.78 2.9
2.56 2.68 2.8
V
V
V
V
V
V
Programmable voltage
detector level selection
VPVD
V
V
V
V
V
V
2.76 2.88
3
V
2.66 2.78 2.9
V
(2)
VPVDhyst
PVD hysteresis
-
100
-
mV
V
1.8(1)
Falling edge
Rising edge
1.88 1.96
Power on/power down
reset threshold
VPOR/PDR
1.84 1.92 2.0
V
(2)
VPDRhyst
PDR hysteresis
-
40
-
mV
mS
(2)
TRSTTEMPO
Reset temporization
1
2.5
4.5
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
42/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
5.3.4
Embedded reference voltage
The parameters given in Table 13 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
Table 13. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
–40 °C < TA < +105 °C 1.16 1.20 1.26
–40 °C < TA < +85 °C 1.16 1.20 1.24
V
V
VREFINT Internal reference voltage
ADC sampling time when
reading the internal reference
voltage
(1)
TS_vrefint
-
5.1
17.1(2)
µs
Internal reference voltage
spread over the temperature
range
(2)
VRERINT
VDD = 3 V 10 mV
-
-
-
10
mV
(2)
TCoeff
Temperature coefficient
-
100 ppm/°C
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f frequency (0 wait state from 0
HCLK
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
●
●
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f
= f
/2, f
= f
PCLK1
HCLK
PCLK2 HCLK
The parameters given in Table 14, Table 15 and Table 16 are derived from tests performed
under ambient temperature and V supply voltage conditions summarized in Table 10.
DD
Doc ID 16554 Rev 3
43/120
Electrical characteristics
STM32F103xF, STM32F103xG
Table 14. Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C TA = 105 °C
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
68
51
69
51
External clock(2), all
peripherals enabled
41
41
29
30
22
22.5
14
12.5
39
Supplycurrent in
Run mode
IDD
mA
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
39
29.5
24
30
External clock(3), all
peripherals disabled
24.5
19
17.5
14
15
8.5
10.5
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15. Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
65
46.5
37
65.5
47
37
27
20
13
36
26
21
16
13
9
External clock(2), all
peripherals enabled
26.5
19
11.5
34.5
25
Supply current
in Run mode
IDD
mA
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
External clock(3), all
peripherals disabled
20.5
15
11
7.5
1. Data based on characterization results, tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
44/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
ꢏꢃ
ꢑꢃ
ꢁꢃ
ꢏꢅ-(Z
ꢂꢃ
ꢂꢐ-(Z
ꢌꢑ-(Z
ꢌꢃ
ꢅꢂ-(Z
ꢀꢑ-(Z
ꢅꢃ
ꢀꢃ
ꢃ
ꢐ-(Z
ꢍꢂꢁ
ꢅꢁ
ꢏꢃ
ꢐꢁ
ꢀꢃꢁ
4EMPERATURE ꢀ #ꢁ
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V)-
code with data processing running from RAM, peripherals disabled
ꢂꢃ
ꢌꢁ
ꢌꢃ
ꢏꢅ-(Z
ꢂꢐ-(Z
ꢌꢑ-(Z
ꢅꢂ-(Z
ꢀꢑ-(Z
ꢐ-(Z
ꢅꢁ
ꢅꢃ
ꢀꢁ
ꢀꢃ
ꢁ
ꢃ
ꢍꢂꢁ
ꢅꢁ
ꢏꢃ
ꢐꢁ
ꢀꢃꢁ
4EMPERATURE ꢉ #ꢋ
AIꢀꢐꢁꢅꢃ
Doc ID 16554 Rev 3
45/120
Electrical characteristics
STM32F103xF, STM32F103xG
Table 16. Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C TA = 105 °C
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
47.5
34
48.5
35
External clock(2), all
peripherals enabled
27.5
20
27.5
20.5
16
15
9
11
Supply current
in Sleep mode
IDD
mA
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
9.5
7.7
6.9
5.9
5.4
4.7
11.2
9.5
8.5
7.8
7.2
6.4
External clock(3), all
peripherals disabled
1. Based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
46/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Table 17. Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Max
Symbol
Parameter
Conditions
Unit
VDD/VBAT VDD/VBAT VDD/VBAT TA =
TA =
= 2.0 V = 2.4 V = 3.3 V 85 °C 105 °C
Regulator in run mode, low-speed
and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog),
fCK=8 MHz
44.8
37.4
45.3
37.8
46.4
38.7
810
790
1680
1660
Supply current in
Stop mode
Regulator in low-power mode, low-
speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
IDD
µA
Low-speed internal RC oscillator
and independent watchdog OFF,
low-speed oscillator and RTC OFF
Supply current in
Standby mode
1.8
2.0
1.1
2.5
1.4
5(2)
8(2)
Backup domain
I
Low-speed oscillator and RTC ON
1.05
2(2)
2.3(2)
DD_VBAT supply current
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not tested in production.
Figure 14. Typical current consumption on V
values
with RTC on vs. temperature at different V
BAT
BAT
2.5
2
1.8 V
2 V
1.5
1
2.4 V
3.3 V
3.6 V
0.5
0
–45
25
85
105
Temperature (°C)
ai17337
Doc ID 16554 Rev 3
47/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 15. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different V values
DD
ꢑꢃꢃ
ꢁꢃꢃ
ꢂꢃꢃ
ꢌꢃꢃ
ꢅꢃꢃ
ꢀꢃꢃ
ꢃ
ꢅꢆꢂ6
ꢅꢆꢏ6
ꢌꢆꢃ6
ꢌꢆꢌ6
ꢌꢆꢑ6
ꢍꢂꢁ#
ꢅꢁ#
ꢐꢁ#
ꢀꢃꢁ#
4EMPERATURE ꢉ #ꢋ
AIꢀꢐꢁꢅꢀ
48/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 16. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different V values
DD
ꢑꢃꢃ
ꢁꢃꢃ
ꢂꢃꢃ
ꢌꢃꢃ
ꢅꢃꢃ
ꢀꢃꢃ
ꢃ
ꢅꢆꢂ6
ꢅꢆꢏ6
ꢌꢆꢃ6
ꢌꢆꢌ6
ꢌꢆꢑ6
ꢍꢂꢁ#
ꢅꢁ#
ꢐꢁ#
ꢀꢃꢁ#
4EMPERATURE ꢉ #ꢋ
AIꢀꢐꢁꢅꢅ
Figure 17. Typical current consumption in Standby mode versus temperature at
different V values
DD
ꢂꢆꢁ
ꢂ
ꢌꢆꢁ
ꢌ
ꢅꢆꢂ6
ꢅꢆꢏ6
ꢌꢆꢃ6
ꢌꢆꢌ6
ꢌꢆꢑ6
ꢅꢆꢁ
ꢅ
ꢀꢆꢁ
ꢀ
ꢃꢆꢁ
ꢃ
ꢍꢂꢁ#
ꢅꢁ#
ꢏꢃ#
ꢐꢁ#
AIꢀꢐꢁꢅꢌ
4EMPERATURE ꢉ #ꢋ
Doc ID 16554 Rev 3
49/120
Electrical characteristics
STM32F103xF, STM32F103xG
Typical current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load).
DD SS
All peripherals are disabled except if it is explicitly mentioned.
The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1
HCLK
wait state from 24 to 48 MHZ and 2 wait states above).
●
●
Ambient temperature and V supply voltage conditions summarized in Table 10.
DD
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f
= f
/4, f
2 = f
/2, f
= f
/4
PCLK1
HCLK
PCLK
HCLK
ADCCLK
PCLK2
Table 18. Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
Allperipherals Allperipherals
enabled(2)
disabled
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
52.5
36.6
28.5
24.1
14
33.5
23.8
18.7
12.8
9.2
External clock(3)
7.7
5.4
mA
4 MHz
4.6
3.4
2 MHz
3
2.3
1 MHz
2.2
1.8
500 kHz
125 kHz
64 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
1.7
1.5
Supply
current in
Run mode
1.4
1.3
IDD
45.5
35.1
27.5
18.9
12.2
7.2
28.6
22.4
17.5
11.6
8.2
Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
4.8
mA
4 MHz
4
2.7
frequency
2 MHz
2.3
1.7
1 MHz
1.5
1.2
500 kHz
125 kHz
1.1
0.9
0.75
0.7
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
50/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Table 19. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
All peripherals All peripherals
enabled(2)
disabled
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
32.5
23
7
5
17.7
12.2
8.4
4.6
3
4
3.1
2.3
1.5
1.3
1.25
1.2
1.15
1.15
5.7
4.4
3.35
2.3
1.6
0.8
0.7
0.6
0.5
0.5
0.5
External clock(3)
4 MHz
2 MHz
2.15
1.7
1.5
1.35
28.7
22
1 MHz
500 kHz
125 kHz
64 MHz
48 MHz
36 MHz
24 MHz
16 MHz
Supply
IDD
current in
mA
Sleep mode
17
11.6
7.7
3.9
2.3
1.5
1.1
0.9
0.7
Running on high
speed internal RC
(HSI), AHB prescaler 8 MHz
used to reduce the
frequency
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Doc ID 16554 Rev 3
51/120
Electrical characteristics
STM32F103xF, STM32F103xG
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed
under the following conditions:
●
●
●
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
●
ambient operating temperature and V supply voltage conditions summarized in
DD
Table 7
(1)
Table 20. Peripheral current consumption
Peripheral
Unit
Typical consumption at 25 °C
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
1.6
1.5
1.5
1.5
0.6
0.6
0.95
0.7
0.75
0.6
SPI2
APB1
SPI3
mA
0.6
USART2
USART3
USART4
USART5
I2C1
0.7
0.7
0.7
0.7
0.65
0.65
0.9
I2C2
USB
CAN
0.9
DAC(2)
1.35
52/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Table 20. Peripheral current consumption
Electrical characteristics
(1)
(continued)
Peripheral
Typical consumption at 25 °C
Unit
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
TIM1
0.55
0.55
0.55
0.6
0.6
0.55
0.55
1.95
1.9
APB2
TIM8
mA
TIM9
1
TIM10
TIM11
ADC1(3)
ADC2(3)
ADC3(3)
SPI1
0.8
0.8
1.85
1.8
1.8
0.45
0.8
USART1
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for DAC: EN1, EN2 bits in the DAC_CR register are set to 1 and the converted value
set to 0x800.
3. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit
in the ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 10.
Doc ID 16554 Rev 3
53/120
Electrical characteristics
STM32F103xF, STM32F103xG
Table 21. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fHSE_ext
1
8
25
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
5
-
-
-
-
tw(HSE)
ns
tr(HSE)
tf(HSE)
20
Cin(HSE) OSC_IN input capacitance(1)
-
45
-
5
-
-
pF
%
DuCy(HSE) Duty cycle
55
1
IL
OSC_IN Input leakage current
VSS ≤VIN ≤VDD
-
µA
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 22 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 10.
Table 22. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
0.7VDD
VSS
450
-
-
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level
voltage
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
OSC32_IN rise or fall time(1)
ns
tr(LSE)
tf(LSE)
50
Cin(LSE) OSC32_IN input capacitance(1)
-
30
-
5
-
-
70
1
pF
%
DuCy(LSE) Duty cycle
IL
OSC32_IN Input leakage current VSS ≤VIN ≤VDD
-
µA
1. Guaranteed by design, not tested in production.
54/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 18. High-speed external clock source AC timing diagram
V
HSEH
90%
10%
V
HSEL
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
EXTERNAL
CLOCK SOURCE
I
L
OSC _IN
STM32F103xx
ai14143
Figure 19. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
t
W(LSE)
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
EXTERNAL
CLOCK SOURCE
I
L
OSC32_IN
STM32F103xx
ai14144b
Doc ID 16554 Rev 3
55/120
Electrical characteristics
STM32F103xF, STM32F103xG
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 23. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
(1)(2)
Table 23. HSE 4-16 MHz oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
fOSC_IN Oscillator frequency
4
-
8
16
-
MHz
RF
C
Feedback resistor
200
kΩ
Recommended load capacitance
versus equivalent serial
RS = 30 Ω
-
-
30
-
-
pF
resistance of the crystal (RS)(3)
V
DD= 3.3 V, VIN = VSS
with 30 pF load
i2
HSE driving current
1
mA
gm
Oscillator transconductance
Startup time
Startup
25
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 20). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C . Refer to the application note AN2867 “Oscillator design guide for ST
C
L1
L2
microcontrollers” available from the ST website www.st.com.
Figure 20. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
STM32F103xx
OSC_OUT
(1)
R
EXT
C
L2
ai14145
1. REXT value depends on the crystal characteristics.
56/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 24. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
(1)(2)
Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Feedback resistor
Conditions
Min
Typ Max Unit
RF
-
5
-
MΩ
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)
C(2)
RS = 30 kΩ
-
-
15
pF
I2
LSE driving current
VDD = 3.3 V, VIN = VSS
-
5
-
-
1.4
µA
gm
Oscillator transconductance
-
-
-
-
-
-
-
-
-
-
µA/V
TA = 50 °C
TA = 25 °C
TA = 10 °C
TA = 0 °C
1.5
2.5
4
-
-
-
6
VDD is
stabilized
(3)
tSU(LSE)
Startup time
s
TA = -10 °C
TA = -20 °C
TA = -30 °C
TA = -40 °C
-
10
17
32
60
-
-
-
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer, PCB
layout and humidity
Note:
For C and C , it is recommended to use high-quality ceramic capacitors in the 5 pF to
L1 L2
15 pF range selected to match the requirements of the crystal or resonator (see Figure 21).
and C are usually the same size. The crystal manufacturer typically specifies a load
C
L1
L2,
capacitance which is the series combination of C and C .
L1
L2
Load capacitance C has the following formula: C = C x C / (C + C ) + C where
L
L
L1
L2
L1
L2
stray
C
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
stray
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended
L1
L2
to use a resonator with a load capacitance C ≤ 7 pF. Never use a resonator with a load
L
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C = 6 pF, and C
= 2 pF,
57/120
L
stray
then C = C = 8 pF.
L1
L2
Doc ID 16554 Rev 3
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 21. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_IN
LSE
Bias
controlled
gain
32.768 kHz
resonator
R
F
STM32F103xx
OSC32_OUT
C
L2
ai14146
5.3.7
Internal clock source characteristics
The parameters given in Table 25 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
High-speed internal (HSI) RC oscillator
(1)
Table 25. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ Max Unit
fHSI
-
8
-
MHz
%
DuCy(HSI) Duty cycle
45
55
User-trimmed with the RCC_CR
register(2)
-
-
1(3)
%
TA = –40 to 105 °C
–2
-
-
-
-
2.5
2.2
2
%
%
%
%
Accuracy of the HSI
oscillator
ACCHSI
TA = –10 to 85 °C
Factory-
–1.5
–1.3
–1.1
calibrated(4)
TA = 0 to 70 °C
TA = 25 °C
1.8
HSI oscillator
startup time
(4)
tsu(HSI)
1
-
-
2
µs
HSI oscillator power
consumption
(4)
IDD(HSI)
80
100
µA
1.
VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
58/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Low-speed internal (LSI) RC oscillator
(1)
Table 26. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
30
-
40
-
60
85
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
(3)
IDD(LSI)
LSI oscillator power consumption
-
0.65
1.2
µA
1.
VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 27 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 10.
Table 27. Low-power mode wakeup timings
Symbol
Parameter
Wakeup from Sleep mode
Typ
Unit
(1)
1.8
µs
tWUSLEEP
Wakeup from Stop mode (regulator in run mode)
3.6
5.4
(1)
µs
µs
tWUSTOP
Wakeup from Stop mode (regulator in low power mode)
(1)
Wakeup from Standby mode
50
tWUSTDBY
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Doc ID 16554 Rev 3
59/120
Electrical characteristics
STM32F103xF, STM32F103xG
5.3.8
PLL characteristics
The parameters given in Table 28 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
Table 28. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
1
40
16
-
8.0
25
60
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
-
-
-
-
fPLL_OUT
tLOCK
72
MHz
µs
200
300
Jitter
Cycle-to-cycle jitter
-
ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
Table 29. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
16-bit programming time TA = –40 to +105 °C
40
20
20
52.5
70
40
40
µs
ms
ms
tERASE Page (2 KB) erase time TA = –40 to +105 °C
-
-
tME
Mass erase time
Supply current
TA = –40 to +105 °C
Read mode
fHCLK = 72 MHz with 2 wait
states, VDD = 3.3 V
-
-
28
mA
Write mode
fHCLK = 72 MHz, VDD = 3.3 V
-
-
-
-
7
5
mA
mA
IDD
Erase mode
fHCLK = 72 MHz, VDD = 3.3 V
Power-down mode / Halt,
-
-
-
50
µA
V
VDD = 3.0 to 3.6 V
Vprog Programming voltage
2
3.6
1. Guaranteed by design, not tested in production.
60/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Table 30. Flash memory endurance and data retention
Value
Unit
Symbol
Parameter
Conditions
Min(1)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND
Endurance
kcycles
Years
10
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
10 kcycles(2) at TA = 55 °C
30
10
20
tRET
Data retention
1. Based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10
FSMC characteristics
Asynchronous waveforms and timings
Figure 22 through Figure 25 represent asynchronous waveforms and Table 31 through
Table 35 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●
●
●
AddressSetupTime = 0
AddressHoldTime = 1
DataSetupTime = 1
Note:
On all tables, the t
is the HCLK clock period.
HCLK
Doc ID 16554 Rev 3
61/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
T
Wꢉ.%ꢋ
&3-#?.%
T
Vꢉ./%?.%ꢋ
T
T
Hꢉ.%?./%ꢋ
Wꢉ./%ꢋ
&3-#?./%
&3-#?.7%
TVꢉ!?.%ꢋ
T
Hꢉ!?./%ꢋ
&3-#?!;ꢅꢁꢇꢃ=
!DDRESS
TVꢉ",?.%ꢋ
T
Hꢉ",?./%ꢋ
&3-#?.",;ꢀꢇꢃ=
T
Hꢉ$ATA?.%ꢋ
T
T
SUꢉ$ATA?./%ꢋ
Hꢉ$ATA?./%ꢋ
T
SUꢉ$ATA?.%ꢋ
$ATA
&3-#?$;ꢀꢁꢇꢃ=
T
Vꢉ.!$6?.%ꢋ
T
Wꢉ.!$6ꢋ
ꢉꢀꢋ
&3-#?.!$6
-3ꢀꢐꢁꢐꢑ6ꢀ
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Note:
FSMC_BusTurnAroundDuration = 0.
62/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
(1)
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
ns
5tHCLK + 0.5
5tHCLK + 2
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
0.5
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5tHCLK – 1
5tHCLK + 1
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NOE high
0
-
-
3
th(A_NOE)
tv(BL_NE)
th(BL_NOE)
0
-
-
0
0.5
-
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOEx high setup time
th(Data_NOE) Data hold time after FSMC_NOE high
2tHCLK - 1
-
2tHCLK - 1
-
0
0
-
-
th(Data_NE)
Data hold time after FSMC_NEx high
-
0
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
tw(NADV)
FSMC_NADV low time
-
tHCLK + 2
1. CL = 15 pF.
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
FSMC_NWE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[3:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FSMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FSMC_NADV
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Doc ID 16554 Rev 3
63/120
Electrical characteristics
STM32F103xF, STM32F103xG
(1)
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol Parameter Min Max
tw(NE) FSMC_NE low time 3tHCLK + 0.5 3tHCLK + 1.5 ns
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Unit
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
tHCLK + 0.5
tHCLK + 1.5 ns
tHCLK – 0.5
tHCLK + 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to Data valid
tHCLK – 0.5
-
-
0
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
tHCLK
-
-
1.5
tHCLK – 1.5
-
-
tHCLK
th(Data_NWE) Data hold time after FSMC_NWE high
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
tHCLK
-
-
-
0
tw(NADV)
FSMC_NADV low time
tHCLK + 1.5 ns
1. CL = 15 pF.
Table 33. Asynchronous read muxed
Symbol Parameter
tw(NE) FSMC_NE low time
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Min
Max
Unit
7tHCLK + 0.5 7tHCLK + 2
3tHCLK + 0.5 3tHCLK + 1.5
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
4tHCLK – 1
4tHCLK + 1
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
0.5
-
-
0
1
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
0
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 2
FSMC_AD (address) valid hold time after
FSMC NADV high
th(AD_NADV)
tHCLK
-
ns
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FSMC_NOE high
FSMC_BL time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
tHCLK – 2
-
-
0.5
-
0
-
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOE high setup time
4tHCLK – 0.5
4tHCLK – 1
-
th(Data_NE)
Data hold time after FSMC_NEx high
0
0
-
th(Data_NOE) Data hold time after FSMC_NOE high
-
64/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FSMC_NE
t
t
h(NE_NOE)
v(NOE_NE)
FSMC_NOE
t
w(NOE)
FSMC_NWE
t
tv(A_NE)
h(A_NOE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NOE)
FSMC_NBL[1:0]
NBL
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
su(Data_NOE)
Address
Data
FSMC_AD[15:0]
FSMC_NADV
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
ai14892b
(1)
Table 34. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
ns
7tHCLK + 0.5
7tHCLK + 2
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
3tHCLK + 0.5 3tHCLK + 1.5 ns
4tHCLK – 1
4tHCLK + 1
ns
ns
ns
ns
ns
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
0.5
-
-
0
1
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
0
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 2
FSMC_AD (address) valid hold time after
FSMC_NADV high
th(AD_NADV)
tHCLK
-
ns
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FSMC_NOE high
FSMC_BL hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
tHCLK -2
-
-
ns
ns
ns
ns
ns
ns
ns
0.5
-
0
-
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOE high setup time
4tHCLK - 0.5
4tHCLK - 1
-
th(Data_NE)
Data hold time after FSMC_NEx high
0
0
-
th(Data_NOE) Data hold time after FSMC_NOE high
1. CL = 15 pF.
-
Doc ID 16554 Rev 3
65/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
FSMC_NWE
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[1:0]
FSMC_AD[15:0]
NBL
t
t
t
v(A_NE)
v(Data_NADV)
h(Data_NWE)
Address
Data
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
FSMC_NADV
ai14891B
(1)
Table 35. Asynchronous multiplexed PSRAM/NOR write timings
Symbol Parameter Min
tw(NE) FSMC_NE low time
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Max
Unit
5tHCLK + 0.5 5tHCLK + 2 ns
tHCLK + 1 tHCLK + 1.5 ns
3tHCLK + 0.5 3tHCLK + 1 ns
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
tHCLK – 0.5
-
3.5
1
ns
ns
ns
-
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
0
tw(NADV)
FSMC_NADV low time
tHCLK + 0.5
tHCLK + 1.5 ns
FSMC_AD (address) valid hold time after
FSMC_NADV high
th(AD_NADV)
t
HCLK – 0.5
-
ns
th(A_NWE)
tv(BL_NE)
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
4tHCLK – 2
-
ns
ns
ns
ns
ns
-
0.5
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tHCLK – 1.5
-
-
tv(Data_NADV) FSMC_NADV high to Data valid
th(Data_NWE) Data hold time after FSMC_NWE high
1. CL = 15 pF.
tHCLK + 6
-
tHCLK – 0.5
66/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Synchronous waveforms and timings
Figure 26 through Figure 29 represent synchronous waveforms and Table 37 through
Table 39 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●
●
●
●
●
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 26. Synchronous multiplexed NOR/PSRAM read timings
"53452. ꢓ ꢃ
Dꢉ#,+,ꢍ.%X(ꢋ
T
T
Wꢉ#,+ꢋ
Wꢉ#,+ꢋ
&3-#?#,+
$ATA LATENCY ꢓ ꢃ
Dꢉ#,+,ꢍ.%X,ꢋ
T
T
T
&3-#?.%X
T
T
Dꢉ#,+,ꢍ.!$6,ꢋ
Dꢉ#,+,ꢍ.!$6(ꢋ
&3-#?.!$6
T
Dꢉ#,+,ꢍ!)6ꢋ
Dꢉ#,+,ꢍ!6ꢋ
&3-#?!;ꢅꢁꢇꢀꢑ=
T
T
Dꢉ#,+,ꢍ./%(ꢋ
Dꢉ#,+,ꢍ./%,ꢋ
&3-#?./%
T
T
T
Hꢉ#,+(ꢍ!$6ꢋ
Dꢉ#,+,ꢍ!$)6ꢋ
T
T
T
SUꢉ!$6ꢍ#,+(ꢋ
SUꢉ!$6ꢍ#,+(ꢋ
Dꢉ#,+,ꢍ!$6ꢋ
Hꢉ#,+(ꢍ!$6ꢋ
$ꢌ
&3-#?!$;ꢀꢁꢇꢃ=
!$;ꢀꢁꢇꢃ=
T
$ꢀ
$ꢅ
T
SUꢉ.7!)46ꢍ#,+(ꢋ
Hꢉ#,+(ꢍ.7!)46ꢋ
&3-#?.7!)4
ꢉ7!)4#&' ꢓ ꢀBꢈ 7!)40/, ꢎ ꢃBꢋ
T
T
SUꢉ.7!)46ꢍ#,+(ꢋ
Hꢉ#,+(ꢍ.7!)46ꢋ
&3-#?.7!)4
ꢉ7!)4#&' ꢓ ꢃBꢈ 7!)40/, ꢎ ꢃBꢋ
T
T
Hꢉ#,+(ꢍ.7!)46ꢋ
SUꢉ.7!)46ꢍ#,+(ꢋ
AIꢀꢂꢐꢒꢌH
Doc ID 16554 Rev 3
67/120
Electrical characteristics
STM32F103xF, STM32F103xG
(1)
Table 36. Synchronous multiplexed NOR/PSRAM read timings
Symbol
tw(CLK)
Parameter
Min
Max
Unit
FSMC_CLK period
27.6
-
0.5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
-
1
-
1
FSMC_CLK low to FSMC_NADV high
0.5
-
-
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NOE low
0
td(CLKL-AIV)
1.5
-
-
td(CLKL-NOEL)
td(CLKL-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
14
-
FSMC_CLK low to FSMC_NOE high
1
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
-
11
-
0.5
FSMC_A/D[15:0] valid data before FSMC_CLK
high
tsu(ADV-CLKH)
2
0
-
-
ns
ns
th(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high
1. CL = 15 pF.
68/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Figure 27. Synchronous multiplexed PSRAM write timings
Electrical characteristics
"53452. ꢓ ꢃ
T
T
Wꢉ#,+ꢋ
Wꢉ#,+ꢋ
&3-#?#,+
$ATA LATENCY ꢓ ꢃ
Dꢉ#,+,ꢍ.%X,ꢋ
T
T
Dꢉ#,+,ꢍ.%X(ꢋ
&3-#?.%X
T
T
Dꢉ#,+,ꢍ.!$6,ꢋ
Dꢉ#,+,ꢍ.!$6(ꢋ
&3-#?.!$6
T
T
T
Dꢉ#,+,ꢍ!6ꢋ
Dꢉ#,+,ꢍ!)6ꢋ
&3-#?!;ꢅꢁꢇꢀꢑ=
&3-#?.7%
T
Dꢉ#,+,ꢍ.7%,ꢋ
Dꢉ#,+,ꢍ.7%(ꢋ
T
T
Dꢉ#,+,ꢍ!$)6ꢋ
T
Dꢉ#,+,ꢍ$ATAꢋ
$ꢀ
T
Dꢉ#,+,ꢍ$ATAꢋ
Dꢉ#,+,ꢍ!$6ꢋ
&3-#?!$;ꢀꢁꢇꢃ=
!$;ꢀꢁꢇꢃ=
$ꢅ
&3-#?.7!)4
ꢉ7!)4#&' ꢓ ꢃBꢈ 7!)40/, ꢎ ꢃBꢋ
&3-#?.",
T
T
SUꢉ.7!)46ꢍ#,+(ꢋ
Hꢉ#,+(ꢍ.7!)46ꢋ
T
Dꢉ#,+,ꢍ.",(ꢋ
AIꢀꢂꢒꢒꢅG
Doc ID 16554 Rev 3
69/120
Electrical characteristics
STM32F103xF, STM32F103xG
(1)
Table 37. Synchronous multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Min
Max
Unit
FSMC_CLK period
27.5
-
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_Nex low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
-
1
-
1
-
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
1
-
0
-
td(CLKL-AIV)
1
-
td(CLKL-NWEL)
td(CLKL-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
td(CLKL-Data)
td(CLKL-NBLH)
1. CL = 15 pF.
1
-
FSMC_CLK low to FSMC_NWE high
1.5
-
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid after FSMC_CLK low
FSMC_CLK low to FSMC_NBL high
10
-
1
-
6
-
1
70/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings
"53452. ꢓ ꢃ
T
Dꢉ#,+,ꢍ.%X(ꢋ
T
T
Wꢉ#,+ꢋ
Wꢉ#,+ꢋ
&3-#?#,+
T
Dꢉ#,+,ꢍ.%X,ꢋ
$ATA LATENCY ꢓ ꢃ
Dꢉ#,+,ꢍ.!$6(ꢋ
&3-#?.%X
T
T
Dꢉ#,+,ꢍ.!$6,ꢋ
&3-#?.!$6
T
T
Dꢉ#,+,ꢍ!)6ꢋ
Dꢉ#,+,ꢍ!6ꢋ
&3-#?!;ꢅꢁꢇꢃ=
T
T
Dꢉ#,+,ꢍ./%,ꢋ
Dꢉ#,+,ꢍ./%(ꢋ
&3-#?./%
T
T
SUꢉ$6ꢍ#,+(ꢋ
Hꢉ#,+(ꢍ$6ꢋ
T
T
SUꢉ$6ꢍ#,+(ꢋ
Hꢉ#,+(ꢍ$6ꢋ
$ꢌ
&3-#?$;ꢀꢁꢇꢃ=
&3-#?.7!)4
$ꢀ
$ꢅ
T
T
SUꢉ.7!)46ꢍ#,+(ꢋ
T
Hꢉ#,+(ꢍ.7!)46ꢋ
ꢉ7!)4#&' ꢓ ꢀBꢈ 7!)40/, ꢎ ꢃBꢋ
T
SUꢉ.7!)46ꢍ#,+(ꢋ
Hꢉ#,+(ꢍ.7!)46ꢋ
&3-#?.7!)4
ꢉ7!)4#&' ꢓ ꢃBꢈ 7!)40/, ꢎ ꢃBꢋ
T
T
Hꢉ#,+(ꢍ.7!)46ꢋ
SUꢉ.7!)46ꢍ#,+(ꢋ
AIꢀꢂꢐꢒꢂG
(1)
Table 38. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
tw(CLK)
Parameter
Min
Max
Unit
FSMC_CLK period
27.6
-
1.5
-
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
-
2
-
0.5
-
FSMC_CLK low to FSMC_NADV high
1
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
FSMC_CLK low to FSMC_Ax invalid (x = 0...25)
FSMC_CLK low to FSMC_NOE low
-
0
td(CLKL-AIV)
2
-
td(CLKL-NOEL)
td(CLKL-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
-
tHCLK + 1 ns
FSMC_CLK low to FSMC_NOE high
1.5
3.5
0
-
-
-
ns
ns
ns
FSMC_D[15:0] valid data before FSMC_CLK high
FSMC_D[15:0] valid data after FSMC_CLK high
1. CL = 15 pF.
Doc ID 16554 Rev 3
71/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 29. Synchronous non-multiplexed PSRAM write timings
"53452. ꢓ ꢃ
Dꢉ#,+,ꢍ.%X(ꢋ
T
T
Wꢉ#,+ꢋ
Wꢉ#,+ꢋ
&3-#?#,+
T
T
Dꢉ#,+,ꢍ.%X,ꢋ
$ATA LATENCY ꢓ ꢃ
Dꢉ#,+,ꢍ.!$6(ꢋ
&3-#?.%X
T
T
Dꢉ#,+,ꢍ.!$6,ꢋ
&3-#?.!$6
&3-#?!;ꢅꢁꢇꢃ=
&3-#?.7%
T
T
T
Dꢉ#,+,ꢍ!6ꢋ
Dꢉ#,+,ꢍ!)6ꢋ
T
Dꢉ#,+,ꢍ.7%,ꢋ
T
Dꢉ#,+,ꢍ.7%(ꢋ
T
Dꢉ#,+,ꢍ$ATAꢋ
Dꢉ#,+,ꢍ$ATAꢋ
&3-#?$;ꢀꢁꢇꢃ=
$ꢀ
$ꢅ
&3-#?.7!)4
ꢉ7!)4#&' ꢓ ꢃBꢈ 7!)40/, ꢎ ꢃBꢋ
&3-#?.",
T
T
Dꢉ#,+,ꢍ.",(ꢋ
SUꢉ.7!)46ꢍ#,+(ꢋ
T
Hꢉ#,+(ꢍ.7!)46ꢋ
AIꢀꢂꢒꢒꢌH
(1)
Table 39. Synchronous non-multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Min
Max Unit
FSMC_CLK period
27.6
-
-
0.5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
1.5
-
1
FSMC_CLK low to FSMC_NADV high
0.5
-
-
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
0
td(CLKL-AIV)
1.5
-
-
td(CLKL-NWEL)
td(CLKL-NWEH)
td(CLKL-Data)
td(CLKL-NBLH)
1. CL = 15 pF.
1
FSMC_CLK low to FSMC_NWE high
1.5
-
-
FSMC_D[15:0] valid data after FSMC_CLK low
FSMC_CLK low to FSMC_NBL high
2.5
-
0.5
72/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
PC Card/CompactFlash controller waveforms and timings
Figure 30 through Figure 35 represent synchronous waveforms and Table 42 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
COM.FSMC_SetupTime = 0x04;
COM.FSMC_WaitSetupTime = 0x07;
COM.FSMC_HoldSetupTime = 0x04;
COM.FSMC_HiZSetupTime = 0x00;
ATT.FSMC_SetupTime = 0x04;
ATT.FSMC_WaitSetupTime = 0x07;
ATT.FSMC_HoldSetupTime = 0x04;
ATT.FSMC_HiZSetupTime = 0x00;
IO.FSMC_SetupTime = 0x04;
IO.FSMC_WaitSetupTime = 0x07;
IO.FSMC_HoldSetupTime = 0x04;
IO.FSMC_HiZSetupTime = 0x00;
TCLRSetupTime = 0;
TARSetupTime = 0;
Figure 30. PC Card/CompactFlash controller waveforms for common memory read
access
FSMC_NCE4_2(1)
FSMC_NCE4_1
t
h(NCEx-AI)
t
v(NCEx-A)
FSMC_A[10:0]
t
t
t
h(NCEx-NREG)
h(NCEx-NIORD)
t
t
d(NREG-NCEx)
d(NIORD-NCEx)
h(NCEx-NIOWR
)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
FSMC_NWE
t
t
d(NCE4_1-NOE)
w(NOE)
FSMC_NOE
t
t
h(NOE-D)
su(D-NOE)
FSMC_D[15:0]
ai14895b
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
Doc ID 16554 Rev 3
73/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 31. PC Card/CompactFlash controller waveforms for common memory write
access
FSMC_NCE4_1
FSMC_NCE4_2
FSMC_A[10:0]
High
t
t
h(NCE4_1-AI)
v(NCE4_1-A)
t
t
t
h(NCE4_1-NREG)
h(NCE4_1-NIORD)
h(NCE4_1-NIOWR)
t
t
d(NREG-NCE4_1)
d(NIORD-NCE4_1)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
t
t
t
d(NCE4_1-NWE)
w(NWE)
d(NWE-NCE4_1)
FSMC_NWE
FSMC_NOE
MEMxHIZ =1
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FSMC_D[15:0]
ai14896b
74/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 32. PC Card/CompactFlash controller waveforms for attribute memory read
access
FSMC_NCE4_1
t
t
h(NCE4_1-AI)
v(NCE4_1-A)
FSMC_NCE4_2
FSMC_A[10:0]
High
FSMC_NIOWR
FSMC_NIORD
t
t
h(NCE4_1-NREG)
d(NREG-NCE4_1)
FSMC_NREG
FSMC_NWE
t
t
t
d(NOE-NCE4_1)
d(NCE4_1-NOE)
w(NOE)
FSMC_NOE
t
t
su(D-NOE)
h(NOE-D)
FSMC_D[15:0](1)
ai14897b
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
Doc ID 16554 Rev 3
75/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 33. PC Card/CompactFlash controller waveforms for attribute memory write
access
FSMC_NCE4_1
High
FSMC_NCE4_2
FSMC_A[10:0]
t
t
h(NCE4_1-AI)
v(NCE4_1-A)
FSMC_NIOWR
FSMC_NIORD
t
t
d(NREG-NCE4_1)
h(NCE4_1-NREG)
FSMC_NREG
t
t
d(NCE4_1-NWE)
w(NWE)
FSMC_NWE
t
d(NWE-NCE4_1)
FSMC_NOE
t
v(NWE-D)
FSMC_D[7:0](1)
ai14898b
1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).
Figure 34. PC Card/CompactFlash controller waveforms for I/O space read access
FSMC_NCE4_1
FSMC_NCE4_2
t
t
h(NCE4_1-AI)
v(NCEx-A)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIOWR
t
t
w(NIORD)
t
d(NIORD-NCE4_1)
FSMC_NIORD
t
su(D-NIORD)
d(NIORD-D)
FSMC_D[15:0]
ai14899B
76/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 35. PC Card/CompactFlash controller waveforms for I/O space write access
&3-#?.#%ꢂ?ꢀ
&3-#?.#%ꢂ?ꢅ
T
T
Hꢉ.#%ꢂ?ꢀꢍ!)ꢋ
Vꢉ.#%Xꢍ!ꢋ
&3-#?!;ꢀꢃꢇꢃ=
&3-#?.2%'
&3-#?.7%
&3-#?./%
&3-#?.)/2$
T
T
Dꢉ.#%ꢂ?ꢀꢍ.)/72ꢋ
Wꢉ.)/72ꢋ
&3-#?.)/72
!44X(): ꢓꢀ
T
Hꢉ.)/72ꢍ$ꢋ
T
Vꢉ.)/72ꢍ$ꢋ
&3-#?$;ꢀꢁꢇꢃ=
AIꢀꢂꢒꢃꢃB
Table 40. Switching characteristics for PC Card/CF read and write cycles in
attribute/common space
Symbol
tv(NCEx-A)
Parameter
Min
Max
Unit
FSMC_NCEx low to FSMC_Ay valid
FSMC_NCEx high to FSMC_Ax invalid
FSMC_NCEx low to FSMC_NREG valid
FSMC_NCEx high to FSMC_NREG invalid
FSMC_NCEx low to FSMC_NWE low
FSMC_NCEx low to FSMC_NOE low
FSMC_NOE low width
-
0
th(NCEx-AI)
td(NREG-NCEx)
th(NCEx-NREG)
td(NCEx_NWE)
td(NCEx_NOE)
tw(NOE)
0
-
-
2
tHCLK + 4
-
-
5tHCLK + 1
-
8tHCLK - 0.5
5tHCLK - 0.5
32
5tHCLK + 1
8tHCLK + 1
td(NOE-NCEx
tsu(D-NOE)
FSMC_NOE high to FSMC_NCEx high
FSMC_D[15:0] valid data before FSMC_NOE high
FSMC_NOE high to FSMC_D[15:0] invalid
FSMC_NWE low width
-
ns
-
th(NOE-D)
tHCLK
-
tw(NWE)
8tHCLK – 1
5tHCLK + 1.5
-
8tHCLK + 4
td(NWE_NCEx)
td(NCEx-NWE)
tv(NWE-D)
FSMC_NWE high to FSMC_NCEx high
FSMC_NCEx low to FSMC_NWE low
FSMC_NWE low to FSMC_D[15:0] valid
FSMC_NWE high to FSMC_D[15:0] invalid
FSMC_D[15:0] valid before FSMC_NWE high
-
5tHCLK + 1
-
0
-
th(NWE-D)
11tHCLK
13tHCLK + 2.5
td(D-NWE)
-
Doc ID 16554 Rev 3
77/120
Electrical characteristics
STM32F103xF, STM32F103xG
Table 41. Switching characteristics for PC Card/CF read and write cycles in I/O space
Symbol
Parameter
FSMC_NIOWR low width
Min
Max
Unit
tw(NIOWR)
8 THCLK
-
ns
5 THCLK -
4
tv(NIOWR-D)
th(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid
FSMC_NIOWR high to FSMC_D[15:0] invalid
FSMC_NCE4_1 low to FSMC_NIOWR valid
FSMC_NCEx high to FSMC_NIOWR invalid
FSMC_NCEx low to FSMC_NIORD valid
FSMC_NCEx high to FSMC_NIORD) valid
-
ns
ns
ns
ns
ns
ns
11THCLK-
7
-
5THCLK +
1
td(NCE4_1-NIOWR)
th(NCEx-NIOWR)
td(NIORD-NCEx)
th(NCEx-NIORD)
-
5THCLK -
2.5
-
5THCLK -
0.5
-
5 THCLK -
0.5
-
-
tw(NIORD)
tsu(D-NIORD)
td(NIORD-D)
FSMC_NIORD low width
8THCLK
ns
ns
ns
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
28
3
NAND controller waveforms and timings
Figure 36 through Figure 39 represent synchronous waveforms and Table 43 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
COM.FSMC_SetupTime = 0x00;
COM.FSMC_WaitSetupTime = 0x02;
COM.FSMC_HoldSetupTime = 0x01;
COM.FSMC_HiZSetupTime = 0x00;
ATT.FSMC_SetupTime = 0x00;
ATT.FSMC_WaitSetupTime = 0x02;
ATT.FSMC_HoldSetupTime = 0x01;
ATT.FSMC_HiZSetupTime = 0x00;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0;
78/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Figure 36. NAND controller waveforms for read access
Electrical characteristics
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NWE
td(ALE-NOE)
th(NOE-ALE)
FSMC_NOE (NRE)
FSMC_D[15:0]
t
t
su(D-NOE)
h(NOE-D)
ai14901b
Figure 37. NAND controller waveforms for write access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NWE)
th(NWE-ALE)
FSMC_NWE
FSMC_NOE (NRE)
FSMC_D[15:0]
tv(NWE-D)
th(NWE-D)
ai14902b
Figure 38. NAND controller waveforms for common memory read access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE)
th(NOE-ALE)
FSMC_NWE
FSMC_NOE
tw(NOE)
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0]
ai14912b
Doc ID 16554 Rev 3
79/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 39. NAND controller waveforms for common memory write access
FSMC_NCEx
Low
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE)
tw(NWE)
th(NOE-ALE)
FSMC_NWE
FSMC_NOE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FSMC_D[15:0]
ai14913b
(1)
Table 42. Switching characteristics for NAND Flash read cycles
Symbol
tw(NOE)
Parameter
FSMC_NOE low width
Min
Max
Unit
3tHCLK – 1
3tHCLK + 1
ns
FSMC_D[15:0] valid data before FSMC_NOE
high
tsu(D-NOE)
13
-
ns
th(NOE-D)
FSMC_D[15:0] valid data after FSMC_NOE high
FSMC_ALE valid before FSMC_NOE low
FSMC_NWE high to FSMC_ALE invalid
0
-
-
ns
ns
ns
td(ALE-NOE)
th(NOE-ALE)
1. CL = 15 pF.
2tHCLK
-
2tHCLK
(1)
Table 43. Switching characteristics for NAND Flash write cycles
Symbol
tw(NWE)
Parameter
FSMC_NWE low width
Min
Max
Unit
3tHCLK
3tHCLK
ns
ns
ns
tv(NWE-D)
FSMC_NWE low to FSMC_D[15:0] valid
FSMC_NWE high to FSMC_D[15:0] invalid
FSMC_ALE valid before FSMC_NWE low
FSMC_NWE high to FSMC_ALE invalid
FSMC_ALE valid before FSMC_NOE low
FSMC_NWE high to FSMC_ALE invalid
-
0
-
th(NWE-D)
2tHCLK + 2
td(ALE-NWE)
th(NWE-ALE)
td(ALE-NOE)
th(NOE-ALE)
1. CL = 15 pF.
-
3tHCLK + 8
-
3tHCLK + 1.5 ns
-
ns
ns
ns
2tHCLK
-
2tHCLK
80/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
5.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 44. They are based on the EMS levels and classes
defined in application note AN1709.
Table 44. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP144, TA = +25 °C,
fHCLK = 72 MHz
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
4A
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP144, TA = +25 °C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
VEFTB
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Doc ID 16554 Rev 3
81/120
Electrical characteristics
Prequalification trials
STM32F103xF, STM32F103xG
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be appFlied directly on the device, over the range
of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 45. EMI characteristics
Max vs. [fHSE/fHCLK
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/48 MHz 8/72 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
8
31
28
4
12
21
33
4
VDD = 3.3 V, TA = 25 °C,
LQFP144 package
compliant with IEC
61967-2
dBµV
-
SEMI
Peak level
5.3.12
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 46. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
Electrostatic discharge
TA = +25 °C, conforming
V
2
2000
500
ESD(HBM) voltage (human body model) to JESD22-A114
V
Electrostatic discharge
TA = +25 °C, conforming
V
II
ESD(CDM) voltage (charge device model) to JESD22-C101
1. Based on characterization results, not tested in production.
82/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Static latch-up
Electrical characteristics
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
●
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 47. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
5.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 48
Table 48. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0
+0
IINJ
mA
Injected current on all FT pins
Injected current on any other pin
-5
-5
+0
+5
Doc ID 16554 Rev 3
83/120
Electrical characteristics
STM32F103xF, STM32F103xG
5.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL
compliant.
Table 49. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard IO input low
level voltage
0.28*(VDD-2
V)+0.8 V
–0.3
-
V
VIL
IO FT(1) input low level
voltage
0.32*(VDD-2
V)+0.75 V
–0.3
-
-
V
V
Standard IO input high
level voltage
0.41*(VDD-2
V)+1.3 V
VDD+0.3
VIH
IO FT(1) input high level
voltage
0.42*(VDD-2
V)+1 V
VDD > 2 V
5.5
5.2
-
V
VDD ≤2 V
Standard IO Schmitt
trigger voltage
hysteresis(2)
200
-
-
-
mV
mV
Vhys
IO FT Schmitt trigger
voltage hysteresis(2)
(3)
-
5% VDD
VSS ≤VIN ≤VDD
Standard I/Os
-
-
-
-
1
3
Ilkg
Input leakage current (4)
µA
VIN= 5 V, I/O FT
Weak pull-up equivalent
resistor(5)
RPU
VIN = VSS
30
40
50
kΩ
Weak pull-down
RPD
CIO
VIN = VDD
30
-
40
5
50
-
kΩ
equivalent resistor(5)
I/O pin capacitance
pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 40 and Figure 41 for standard I/Os, and
in Figure 42 and Figure 43 for 5 V tolerant I/Os.
84/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 40. Standard I/O input characteristics - CMOS port
6
ꢄ6 ꢉ6ꢋ
)( ),
ꢁꢂꢅꢆ
ꢁꢂꢇꢁ
ꢁꢂꢈꢉ
ꢁꢂꢇꢁ
ꢁꢂꢈꢉ
)NPUT RANGE
NOT GUARANTEED
ꢁꢂꢄꢅ
ꢁꢂꢃꢄ
7)(MIN
ꢀꢆꢌ
ꢁ
7),MAX
ꢃꢆꢐ
ꢃꢆꢏ
6
ꢉ6ꢋ
$$
ꢅ
ꢅꢆꢏ
ꢌ
ꢌꢆꢌ
ꢌꢆꢑ
AIꢀꢏꢅꢏꢏB
Figure 41. Standard I/O input characteristics - TTL port
6
ꢄ6 ꢉ6ꢋ
)( ),
44, REQUIREMENTS
6
ꢓꢅ6
)(
7)(MIN
ꢅꢆꢃ
ꢀꢆꢒꢑ
ꢀꢆꢅꢁ
)NPUT RANGE
NOT GUARANTEED
ꢀꢆꢌ
ꢃꢆꢐ
7),MAX
44, REQUIREMENTS
6
ꢓꢃꢆꢐ6
),
6
ꢉ6ꢋ
$$
ꢅ
ꢅꢆꢀꢑ
ꢌꢆꢑ
AIꢀꢏꢅꢏꢐ
Doc ID 16554 Rev 3
85/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 42. 5 V tolerant I/O input characteristics - CMOS port
6
ꢄ6 ꢉ6ꢋ
)( ),
ꢀꢆꢑꢏ
ꢀꢆꢁꢁ
ꢀꢆꢀꢑ
)NPUT RANGE
NOT GUARANTEED
ꢀ
ꢀꢆꢂꢅ
ꢀꢆꢃꢏ
ꢀꢆꢌ
ꢃꢆꢏ
ꢀꢆꢅꢒꢁ
ꢃꢆꢒꢏꢁ
ꢀ
ꢃꢆꢏꢁ
6
ꢉ6ꢋ
$$
ꢅ
ꢅꢆꢏ
ꢌ
ꢌꢆꢌ
ꢌꢆꢑ
6$$
AIꢀꢏꢅꢏꢒB
Figure 43. 5 V tolerant I/O input characteristics - TTL port
6
ꢄ6 ꢉ6ꢋ
)( ),
44, REQUIREMENT 6 ꢓꢅ6
)(
ꢅꢆꢃ
ꢀꢆꢑꢏ
ꢀ
)NPUT RANGE
NOT GUARANTEED
7)(MIN
7),MAX
ꢃꢆꢐ
ꢃꢆꢏꢁ
44, REQUIREMENTS 6 ꢓꢃꢆꢐ6
),
6
ꢉ6ꢋ
$$
ꢅ
ꢅꢆꢀꢑ
ꢌꢆꢑ
AIꢀꢏꢅꢐꢃ
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA (with a relaxedV ) except PC13, PC14 and PC15 which can sink
V
OL/ OH
or source up to 3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 8).
VDD
●
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 8).
VSS
86/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Output voltage levels
Electrical characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 10. All I/Os are CMOS and TTL compliant.
Table 50. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
TTL port(3)
IIO = +8 mA
2.7 V < VDD < 3.6 V
VOL
-
0.4
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)
VOH
VDD–0.4
-
0.4
-
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
CMOS port(3)
IIO =+ 8mA
2.7 V < VDD < 3.6 V
VOL
-
V
V
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)
VOH
2.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(4)
VOL
-
1.3
-
I
IO = +20 mA
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)(4)
VOH
VDD–1.3
-
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(4)
VOL
0.4
-
IIO = +6 mA
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)(4)
VOH
VDD–0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
4. Based on characterization data, not tested in production.
Doc ID 16554 Rev 3
87/120
Electrical characteristics
STM32F103xF, STM32F103xG
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 44 and
Table 51, respectively.
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 10.
(1)
Table 51. I/O AC characteristics
MODEx[1:0]
Symbol
Parameter
Conditions
Min Max Unit
bit value(1)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
-
-
2
MHz
ns
Output high to low
tf(IO)out
125(3)
10
level fall time
CL = 50 pF, VDD = 2 V to 3.6 V
Output low to high
tr(IO)out
-
-
-
125(3)
10
level rise time
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
MHz
ns
Output high to low
tf(IO)out
25(3)
01
level fall time
CL = 50 pF, VDD = 2 V to 3.6 V
Output low to high
tr(IO)out
-
25(3)
level rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V
Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
-
-
-
-
-
-
-
-
-
50
30
MHz
MHz
MHz
20
CL = 30 pF, VDD = 2.7 V to 3.6 V
Output high to low
5(3)
8(3)
12(3)
5(3)
8(3)
12(3)
11
tf(IO)out
tr(IO)out
tEXTIpw
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
level fall time
ns
Output low to high
level rise time
Pulse width of
external signals
detected by the EXTI
controller
-
10
-
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 44.
3. Guaranteed by design, not tested in production.
88/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Figure 44. I/O AC characteristics definition
Electrical characteristics
90%
10 %
50%
50%
90%
10%
t
EXTERNAL
OUTPUT
ON 50pF
t
r(IO)out
r(IO)out
T
Maximum frequency is achieved if (t + t ) £ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
ai14131
5.3.15
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 49).
PU
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 10.
Table 52. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)
VIL(NRST)
NRST Input low level voltage
NRST Input high level voltage
–0.5
2
-
-
0.8
V
(1)
VIH(NRST)
Vhys(NRST)
RPU
VDD+0.5
NRST Schmitt trigger voltage
hysteresis
-
200
-
mV
Weak pull-up equivalent resistor(2)
VIN = VSS
30
-
40
-
50
100
-
kΩ
ns
ns
(1)
VF(NRST)
NRST Input filtered pulse
(1)
VNF(NRST)
NRST Input not filtered pulse
300
-
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 45. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 µF
STM32F10xxx
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 52. Otherwise the reset will not be taken into account by the device.
Doc ID 16554 Rev 3
89/120
Electrical characteristics
STM32F103xF, STM32F103xG
5.3.16
TIM timer characteristics
The parameters given in Table 53 are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 53. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
ns
1
-
tres(TIM)
Timer resolution time
fTIMxCLK = 72 MHz 13.9
0
-
fTIMxCLK/2
MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 72 MHz
0
-
36
16
MHz
ResTIM
Timer resolution
bit
16-bit counter clock period
when internal clock is
selected
tTIMxCLK
1
65536
tCOUNTER
fTIMxCLK = 72 MHz 0.0139
-
910
µs
tTIMxCLK
s
65536 × 65536
59.6
tMAX_COUNT
Maximum possible count
fTIMxCLK = 72 MHz
-
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
90/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
5.3.17
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLK1
DD
summarized in Table 10.
The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG
2
2
I
performance line C interface meets the requirements of the standard I C communication
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and V is disabled, but is still present.
DD
2
The I C characteristics are described in Table 54. Refer also to Section 5.3.14: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
Table 54. I C characteristics
Standard mode I2C(1)
Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
-
-
-
-
1.3
0.6
-
µs
-
250
0(3)
100
0(4)
-
SDA data hold time
900(3)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
-
300
300
-
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
-
-
-
-
0.6
-
-
-
-
µs
Repeated Start condition
setup time
0.6
0.6
1.3
tsu(STO)
Stop condition setup time
μs
μs
Stop to Start condition time
(bus free)
tw(STO:STA)
Capacitive load for each bus
line
Cb
-
400
-
400
pF
Guaranteed by design, not tested in production.
1.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast
mode maximum clock speed of 400 kHz.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
3.
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
Doc ID 16554 Rev 3
91/120
Electrical characteristics
STM32F103xF, STM32F103xG
2
Figure 46. I C bus AC waveforms and measurement circuit
V
DD
V
DD
STM32F103xx
SDA
4.7k
4.7k
100
100
I2C bus
SCL
START REPEATED
START
START
t
su(STA)
SDA
t
t
t
r(SDA)
f(SDA)
su(SDA)
t
w(STO:STA)
STOP
t
t
t
w(SCLL)
h(SDA)
h(STA)
SCL
t
t
t
su(STO)
r(SCL)
t
f(SCL)
w(SCLH)
1.
ai14149c
Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
(1)(2)
Table 55. SCL frequency (f
= 36 MHz.,VDD = 3.3 V)
PCLK1
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
300
200
100
50
0x801E
0x8028
0x803C
0x00B4
0x0168
0x0384
20
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
92/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
I2S - SPI characteristics
2
Unless otherwise specified, the parameters given in Table 56 for SPI or in Table 57 for I S
are derived from tests performed under ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
Table 56. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
-
-
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
-
8
ns
%
SPI slave input clock duty
cycle
DuCy(SCK)
Slave mode
30
70
(1)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4tPCLK
2tPCLK
-
-
(1)
th(NSS)
(1)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
50
60
(1)
(1)
Master mode
Slave mode
Master mode
Slave mode
5
5
5
4
0
2
-
-
tsu(MI)
tsu(SI)
(1)
-
(1)
th(MI)
-
Data input hold time
ns
(1)
th(SI)
-
(1)(2)
ta(SO)
Data output access time Slave mode, fPCLK = 20 MHz
Data output disable time Slave mode
3tPCLK
(1)(3)
tdis(SO)
10
25
5
(1)
tv(SO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
(1)
tv(MO)
-
(1)
th(SO)
15
2
-
Data output hold time
(1)
th(MO)
-
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Doc ID 16554 Rev 3
93/120
Electrical characteristics
STM32F103xF, STM32F103xG
Figure 47. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 48. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
94/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
(1)
Figure 49. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
BIT6 IN
LSB IN
t
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
Doc ID 16554 Rev 3
95/120
Electrical characteristics
STM32F103xF, STM32F103xG
2
Table 57. I S characteristics
Symbol
Parameter
I2S slave input clock duty cycle Slave mode
Master mode (data: 16 bits,
Conditions
Min
Max
Unit
DuCy(SCK)
30
70
%
1.522
1.525
6.5
8
fCK
I2S clock frequency
MHz
Audio frequency = 48 kHz)
1/tc(CK)
Slave mode
0
-
tr(CK)
tf(CK)
I2S clock rise and fall time
WS valid time
Capacitive load CL = 50 pF
Master mode
(1)
tv(WS)
3
2
-
-
-
-
-
-
-
-
-
-
-
-
I2S2
I2S3
(1)
th(WS)
WS hold time
Master mode
0
(1)
tsu(WS)
WS setup time
WS hold time
Slave mode
Slave mode
4
(1)
th(WS)
0
(1)
tw(CKH)
312.5
345
2
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
CK high and low time
(1)
tw(CKL)
I2S2
Master receiver
I2S3
(1)
tsu(SD_MR)
Data input setup time
Data input setup time
Data input hold time
ns
6.5
1.5
0
(1)
tsu(SD_SR)
Slave receiver
Master receiver
Slave receiver
(1)(2)
(1)(2)
th(SD_MR)
th(SD_SR)
0.5
Slave transmitter (after enable
edge)
(1)(2)
(1)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
-
18
-
Slave transmitter (after enable
edge)
11
-
Master transmitter (after enable
edge)
(1)(2)
(1)
3
-
Master transmitter (after enable
edge)
0
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
96/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
2
(1)
Figure 50. I S slave timing diagram (Philips protocol)
t
c(CK)
CPOL = 0
CPOL = 1
WS input
t
t
t
w(CKL)
h(WS)
w(CKH)
t
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
transmit
(2)
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
(2)
LSB receive
Bitn receive
LSB receive
SD
receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 51. I S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
h(WS)
t
v(WS)
w(CKL)
t
t
v(SD_MT)
h(SD_MT)
(2)
SD
transmit
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
(2)
SD
LSB receive
Bitn receive
LSB receive
receive
ai14884b
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Doc ID 16554 Rev 3
97/120
Electrical characteristics
STM32F103xF, STM32F103xG
SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLKx
DD
summarized in Table 10.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (D[7:0], CMD, CK).
Figure 52. SDIO high-speed mode
t
t
r
f
t
C
t
t
W(CKH)
W(CKL)
CK
t
t
OV
OH
D, CMD
(output)
t
t
ISU
IH
D, CMD
(input)
ai14887
Figure 53. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
98/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Table 58. SD / MMC characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Clock frequency in data transfer
mode
fPP
CL ≤ 30 pF
0
48
MHz
tW(CKL)
Clock low time, fPP = 16 MHz
Clock high time, fPP = 16 MHz
Clock rise time
CL ≤ 30 pF
CL ≤ 30 pF
CL ≤ 30 pF
CL ≤ 30 pF
32
30
-
-
-
tW(CKH)
ns
tr
tf
4
5
Clock fall time
-
CMD, D inputs (referenced to CK)
tISU
tIH
Input setup time
Input hold time
CL ≤ 30 pF
CL ≤ 30 pF
2
0
-
-
ns
ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
tOH
Output valid time
Output hold time
CL ≤ 30 pF
CL ≤ 30 pF
-
6
-
0
CMD, D outputs (referenced to CK) in SD default mode(1)
tOVD
tOHD
Output valid default time
Output hold default time
CL ≤ 30 pF
CL ≤ 30 pF
-
7
-
ns
0.5
1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 59. USB startup time
Symbol
Parameter
Max
Unit
µs
(1)
tSTARTUP
USB transceiver startup time
1
1. Guaranteed by design, not tested in production.
Doc ID 16554 Rev 3
99/120
Electrical characteristics
STM32F103xF, STM32F103xG
Table 60. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1) Unit
Input levels
VDD
USB operating voltage(2)
Differential input sensitivity
3.0(3)
0.2
3.6
V
V
(4)
VDI
I(USBDP, USBDM)
(4)
VCM
Differential common mode range Includes VDI range
Single ended receiver threshold
0.8
2.5
2.0
(4)
VSE
Output levels
1.3
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩto 3.6 V(5)
0.3
3.6
V
(5)
RL of 15 kΩto VSS
2.8
1. All the voltages are measured from the local ground potential.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. Guaranteed by characterization, not tested in production.
RL is the load connected on the USB drivers
5.
Figure 54. USB timings: definition of data signal rise and fall time
Crossover
points
Differential
data lines
V
CR S
V
SS
t
t
r
f
ai14137
Table 61.
Symbol
USB: full-speed electrical characteristics
Driver characteristics(1)
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall Time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
5.3.18
CAN (controller area network) interface
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
100/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
5.3.19
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 62 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 10.
Note:
It is recommended to perform a calibration after each power-up.
Table 62. ADC characteristics
Symbol
Parameter
Power supply
Conditions
Min
Typ
Max
Unit
VDDA
2.4
2.4
-
-
3.6
V
V
VREF+
Positive reference voltage
VDDA
Current on the VREF input
pin
IVREF
fADC
-
160
220(1)
µA
ADC clock frequency
Sampling rate
0.6
-
-
14
1
MHz
MHz
(2)
0.05
fS
f
ADC = 14 MHz
-
-
-
-
823
17
kHz
(2)
External trigger frequency
Conversion voltage range(3)
fTRIG
1/fADC
0 (VSSA or VREF-
tied to ground)
VAIN
-
VREF+
V
See Equation 1 and
Table 63 for details
(2)
RAIN
External input impedance
Sampling switch resistance
-
-
-
-
-
-
50
1
kΩ
kΩ
pF
(2)
RADC
Internal sample and hold
capacitor
(2)
8
CADC
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
5.9
83
µs
1/fADC
µs
(2)
Calibration time
tCAL
-
-
-
0.214
3(4)
Injection trigger conversion
latency
(2)
tlat
-
1/fADC
µs
-
-
0.143
2(4)
Regular trigger conversion
latency
(2)
tlatr
-
0.107
1.5
0
-
1/fADC
µs
-
17.1
239.5
1
(2)
Sampling time
Power-up time
tS
-
1/fADC
µs
(2)
tSTAB
0
fADC = 14 MHz
1
18
µs
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pinouts and pin descriptions for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 62.
Doc ID 16554 Rev 3
101/120
Electrical characteristics
Equation 1: R
STM32F103xF, STM32F103xG
max formula
AIN
TS
RAIN < --------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
(1)
Table 63.
R
max for f
= 14 MHz
AIN
ADC
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
0.11
0.4
7.5
0.54
0.96
2.04
2.96
3.96
5.11
17.1
5.9
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Guaranteed by design, not tested in production.
(1)(2)
Table 64. ADC accuracy - limited test conditions
Symbol
Parameter
Test conditions
Typ
Max(3)
Unit
ET
EO
EG
ED
Total unadjusted error
Offset error
fPCLK2 = 56 MHz,
1.3
1
2
1.5
1.5
1
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
Gain error
0.5
0.7
LSB
Measurements made after
ADC calibration
VREF+ = VDDA
Differential linearity error
EL
Integral linearity error
0.8
1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not
affect the ADC accuracy.
3. Based on characterisation, not tested in production.
102/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
(1) (2)(3)
Table 65. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
2
5
2.5
3
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
1.5
1.5
1
Gain error
LSB
Measurements made after
ADC calibration
Differential linearity error
Integral linearity error
2
1.5
3
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not
affect the ADC accuracy.
4. Preliminary values.
Figure 55. ADC accuracy characteristics
VREF+
VDDA
4096
[1LSBIDEAL
=
(or
depending on package)]
4096
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4095
4094
4093
(3) End point correlation line
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
(1)
transition and the first ideal one.
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
V
V
DDA
SSA
ai14395b
Doc ID 16554 Rev 3
103/120
Electrical characteristics
Figure 56. Typical connection diagram using the ADC
STM32F103xF, STM32F103xG
V
DD
STM32F103xx
Sample and hold ADC
V
0.6 V
T
converter
(1)
(1)
AIN
R
R
ADC
AINx
12-bit
converter
I
1 µA
L
C
V
T
parasitic
V
AIN
0.6 V
(1)
C
ADC
ai14150c
1. Refer to Table 62 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 57 or Figure 58,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 57. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
STM32F103xx
V
REF+
(see note 1)
1 µF // 10 nF
V
DDA
SSA
1 µF // 10 nF
V
/V
REF–
(see note 1)
ai14388b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
104/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Figure 58. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32F103xx
V
/V
REF+ DDA
(See note 1)
1 µF // 10 nF
V
/V
REF– SSA
(See note 1)
ai14389
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Doc ID 16554 Rev 3
105/120
Electrical characteristics
STM32F103xF, STM32F103xG
5.3.20
DAC electrical specifications
Table 66. DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Comments
VDDA
Analog supply voltage
2.4
-
3.6
V
VREF+
VSSA
Reference supply voltage
Ground
2.4
0
-
-
3.6
0
V
V
VREF+ must always be below VDDA
Resistive load vs. VSSA with
buffer ON
5
-
-
-
-
kΩ
kΩ
(1)
RLOAD
Resistive load vs. VDDA with
buffer ON
15
When the buffer is OFF, the Minimum
resistive load between DAC_OUT
and VSS to have a 1% accuracy is
1.5 MΩ
Impedance output with buffer
OFF
(1)
RO
-
-
15
50
kΩ
Maximum capacitive load at
pF DAC_OUT pin (when the buffer is
ON).
(1)
CLOAD
Capacitive load
-
-
-
It gives the maximum output
excursion of the DAC.
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
0.2
-
V
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V
DAC_OUT Higher DAC_OUT voltage
max(1)
with buffer ON
and (0x155) and (0xEAB) at VREF+
2.4 V
=
-
-
-
-
VDDA – 0.2
V
mV
V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
0.5
It gives the maximum output
excursion of the DAC.
DAC_OUT Higher DAC_OUT voltage
VREF+ –
10 mV
max(1)
with buffer OFF
DAC DC current
With no load, worst code (0x0E4) at
IDDVREF+
consumption in quiescent
mode (Standby mode)
-
-
-
380
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
With no load, middle code (0x800) on
the inputs
380
480
µA
DAC DC current
consumption in quiescent
mode (Standby mode)
IDDA
With no load, worst code (0xF1C) at
µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
Given for the DAC in 10-bit
configuration
-
-
0.5
3
LSB
Differential non linearity
Difference between two
consecutive code-1LSB)
DNL(2)
Given for the DAC in 12-bit
configuration
LSB
106/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Electrical characteristics
Comments
Table 66. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Integral non linearity
(difference between
Given for the DAC in 10-bit
configuration
-
-
1
LSB
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
INL(2)
Given for the DAC in 12-bit
configuration
-
-
4
LSB
Given for the DAC in 12-bit
configuration
-
-
-
-
-
-
-
-
10
3
mV
LSB
LSB
%
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
Given for the DAC in 10-bit at VREF+
= 3.6 V
Offset(2)
Given for the DAC in 12-bit at VREF+
= 3.6 V
12
0.5
Gain
Given for the DAC in 12bit
configuration
Gain error
error(2)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value 1LSB
(2)
tSETTLING
-
-
3
-
4
1
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Update
rate(2)
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
(2)
tWAKEUP
-
-
6.5
10
µs
input code between lowest and
highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
–67
–40
dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. Preliminary values.
Figure 59. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
LOAD
DACx_OUT
12-bit
digital to
analog
converter
C
LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
Doc ID 16554 Rev 3
107/120
Electrical characteristics
STM32F103xF, STM32F103xG
5.3.21
Temperature sensor characteristics
Table 67. TS characteristics
Symbol Parameter
VSENSE linearity with temperature
Min
Typ
Max
Unit
(1)
TL
-
4.0
1.34
4
1
4.3
1.43
-
2
4.6
1.52
10
°C
mV/°C
V
Avg_Slope(1) Average slope
(1)
V25
Voltage at 25 °C
Startup time
(2)
tSTART
µs
ADC sampling time when reading the
temperature
(3)(2)
TS_temp
-
-
17.1
µs
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
108/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Package characteristics
6
Package characteristics
6.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 60. Recommended PCB design rules (0.80/0.75 mm pitch BGA
Dpad
0.37 mm
0.52 mm typ. (depends on solder mask
registration tolerance
Dsm
Solder paste
0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
ai15469
Doc ID 16554 Rev 3
109/120
Package characteristics
STM32F103xF, STM32F103xG
Figure 61. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package outline
Seating plane
C
A2
A4
ddd
C
A
A3
A1
B
D
D1
A
e
F
M
F
E1
E
e
Øb (144 balls)
Ball A1
C
A
B
M
Øeee
Ø fff
M
C
X3_ME
1. Drawing is not to scale.
Table 68. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package data
millimeters
inches(1)
Symbol
Min
Typ
Max
Typ
Min
Max
A
A1
A2
A3
A4
b
1.70
0.0669
0.21
0.0083
1.07
0.27
0.0421
0.0106
0.85
0.45
0.0335
0.0177
0.3996
0.35
9.85
0.40
10.00
8.80
10.00
8.80
0.80
0.60
0.10
0.15
0.08
0.0138
0.3878
0.0157
0.3937
0.3465
0.3937
0.3465
0.0315
0.0236
0.0039
0.0059
0.0031
D
10.15
D1
E
9.85
10.15
0.3878
0.3996
E1
e
F
ddd
eee
fff
1. Values in inches are converted from mm and rounded to 4 decimal digits.
110/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Package characteristics
Figure 62. LQFP144, 20 x 20 mm, 144-pin low-profile quad
Figure 63. Recommended
(1)
(1)(2)
flat package outline
footprint
Seating plane
C
A
A2 A1
c
b
1.35
73
0.25 mm
108
gage plane
ccc
C
109
72
0.35
D
k
D1
0.5
A1
D3
L
108
73
17.85
22.6
L1
19.9
72
109
144
37
E1
E
1
36
19.9
22.6
E3
ai149
144
37
Pin 1
identification
1
36
e
ME_1A
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 69. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
0.063
A
A1
A2
b
1.60
0.15
0.05
1.35
0.002
0.0531
0.0067
0.0035
0.8583
0.7795
0.0059
0.0571
0.0106
0.0079
0.874
1.40
0.22
1.45
0.0551
0.0087
0.17
0.27
c
0.09
0.20
D
21.80
19.80
22.00
20.00
17.50
22.00
20.00
17.50
0.50
22.20
20.20
0.8661
0.7874
0.689
D1
D3
E
0.7953
21.80
19.80
22.20
20.20
0.8583
0.7795
0.8661
0.7874
0.689
0.874
E1
E3
e
0.7953
0.0197
0.0236
0.0394
3.5°
L
0.45
0°
0.60
0.75
7°
0.0177
0°
0.0295
7°
L1
k
1.00
3.5°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 16554 Rev 3
111/120
Package characteristics
STM32F103xF, STM32F103xG
(1)(2)
Figure 64. LQFP100, 14 x 14 mm 100-pin low-profile
Figure 65. Recommended footprint
(1)
quad flat package outline
0.25 mm
0.10 inch
GAGE PLANE
k
75
51
D
L
D1
76
50
L1
D3
0.5
51
75
C
76
50
0.3
16.7 14.3
b
E3 E1
E
100
26
1.2
100
26
1
25
Pin 1
identification
1
25
ccc
C
12.3
16.7
e
A1
A2
A
ai14906b
SEATING PLANE
C
1L_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 70. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
0.063
0.05
1.35
0.002
0.0531
0.0067
0.0035
0.622
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
1.40
0.22
1.45
0.0551
0.0087
0.17
0.27
c
0.09
0.20
D
15.80
13.80
16.00
14.00
12.00
16.00
14.00
12.00
0.50
16.20
14.20
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
0.5433
15.80
13.80
16.20
14.20
0.622
0.6378
0.5591
E1
E3
e
0.5433
L
0.45
0°
0.60
0.75
7°
0.0177
0°
0.0295
7°
L1
k
1.00
3.5°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
112/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Package characteristics
(1)(2)
Figure 66. LQFP64 – 10 x 10 mm 64 pin low-profile
Figure 67. Recommended footprint
(1)
quad flat package outline
48
33
D
0.3
ccc
C
D1
D3
49
32
0.5
A
A2
33
48
32
49
12.7
10.3
b
L1
E3 E1
E
10.3
64
17
L
A1
K
1.2
64
1
16
17
Pin 1
identification
7.8
1
16
c
5W_ME
12.7
ai14909
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 71. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
12.200
10.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.4803
0.4016
0.050
1.350
0.170
0.090
11.800
9.800
0.0020
0.0531
0.0067
0.0035
0.4646
0.3858
1.400
0.220
0.0551
0.0087
c
D
12.000
10.000
7.500
12.000
10.00
0.500
3.5°
0.4724
0.3937
D1
D.
E
11.800
9.800
12.200
10.200
0.4646
0.3858
0.4724
0.3937
0.0197
3.5°
0.4803
0.4016
E1
e
k
0°
7°
0°
7°
L
0.450
0.600
1.000
0.080
0.75
0.0177
0.0236
0.0394
0.0031
0.0295
L1
ccc
Number of pins
64
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 16554 Rev 3
113/120
Package characteristics
STM32F103xF, STM32F103xG
6.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 10: General operating conditions on page 41.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
●
●
●
●
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in ° C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 72. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LFBGA144 - 10 × 10 mm / 0.8 mm pitch
40
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch
30
46
45
Θ
°C/W
JA
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
6.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
114/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Package characteristics
6.2.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 73: STM32F103xF and STM32F103xG ordering
information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F103xF and STM32F103xG at maximum
dissipation, it is useful to calculate the exact power consumption and junction temperature to
determine which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Thus: P
= 447 mW
Dmax
Using the values obtained in Table 72 T
is calculated as follows:
Jmax
–
T
For LQFP100, 46 °C/W
= 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 73: STM32F103xF and STM32F103xG ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
= 115 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V= 70 mW
INTmax
= 20 × 8 mA × 0.4 V = 64 mW
IOmax
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
= 70 + 64 = 134 mW
Dmax
Thus: P
= 134 mW
Dmax
Doc ID 16554 Rev 3
115/120
Package characteristics
Using the values obtained in Table 72 T
STM32F103xF, STM32F103xG
is calculated as follows:
Jmax
–
T
For LQFP100, 46 °C/W
= 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C
Jmax
This is within the range of the suffix 7 version parts (–40 < T < 125 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 73: STM32F103xF and STM32F103xG ordering information scheme).
Figure 68. LQFP100 P max vs. T
D
A
700
600
500
400
300
200
100
0
Suffix 6
Suffix 7
65
75
85
95 105 115 125 135
TA (°C)
116/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Part numbering
7
Part numbering
Table 73. STM32F103xF and STM32F103xG ordering information scheme
Example:
STM32 F103 RF T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
103 = performance line
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Flash memory size
F = 768 Kbytes of Flash memory
G = 1 Mbyte of Flash memory
Package
H = BGA
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and real
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 16554 Rev 3
117/120
Revision history
STM32F103xF, STM32F103xG
8
Revision history
Table 74. Document revision history
Date
Revision
Changes
27-Oct-2009
1
Initial release.
LQFP64 package mechanical data updated: see Figure 66: LQFP64 –
10 x 10 mm 64 pin low-profile quad flat package outline and Table 71:
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical
data.
Internal code removed from Table 73: STM32F103xF and
STM32F103xG ordering information scheme.
Updated note 2 below Table 54: I2C characteristics
Updated Figure 46: I2C bus AC waveforms and measurement circuit
Updated Figure 45: Recommended NRST pin protection
Updated note 1 below Table 49: I/O static characteristics
Updated Table 20: Peripheral current consumption
Updated Table 14: Maximum current consumption in Run mode, code
with data processing running from Flash
15-Nov-2010
2
Updated Table 15: Maximum current consumption in Run mode, code
with data processing running from RAM
Updated Table 16: Maximum current consumption in Sleep mode, code
running from Flash or RAM
Updated Table 17: Typical and maximum current consumptions in Stop
and Standby modes
Updated Table 18: Typical current consumption in Run mode, code with
data processing running from Flash
Updated Table 19: Typical current consumption in Sleep mode, code
running from Flash or RAM
Updated Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz)
Updated Figure 22: Asynchronous non-multiplexed
SRAM/PSRAM/NOR read waveforms on page 62
Added Section 5.3.13: I/O current injection characteristics on page 83
Section 2.3.26: GPIOs (general-purpose inputs/outputs): modified text
of last sentence.
Table 5: STM32F103xF and STM32F103xG pin definitions: updated
pins PD0, PD1, OSC_IN, OSC_OUT, PB8, PB9, and PF8.
Table 7: Voltage characteristics: Removed the previous footnotes 2 and
3 and added current footnote 2.
18-Jan-2012
3
Table 8: Current characteristics: updated footnotes 3, 4, and 5.
Table 21: High-speed external user clock characteristics: replaced the
tw(HSE) min value by 5 (instead of 16).
Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz): updated
symbols and footnotes.
118/120
Doc ID 16554 Rev 3
STM32F103xF, STM32F103xG
Table 74. Document revision history
Revision history
Date
Revision
Changes
Asynchronous waveforms and timings: added notes about tHCLK clock
period and FSMC_BusTurnAroundDuration; updated conditions,
modified Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR
read timings, Table 32: Asynchronous non-multiplexed
SRAM/PSRAM/NOR write timings, Table 34: Asynchronous multiplexed
PSRAM/NOR read timings, and Table 35: Asynchronous multiplexed
PSRAM/NOR write timings; added Table 33: Asynchronous read
muxed.
Synchronous waveforms and timings: updated Figure 27: Synchronous
multiplexed PSRAM write timings; updated Table 36: Synchronous
multiplexed NOR/PSRAM read timings, Table 37: Synchronous
multiplexed PSRAM write timings, Table 38: Synchronous non-
multiplexed NOR/PSRAM read timings, and Table 39: Synchronous
non-multiplexed PSRAM write timings.
PC Card/CompactFlash controller waveforms and timings: updated
Figure 35: PC Card/CompactFlash controller waveforms for I/O space
write access; split switching characteristics into Table 40: Switching
characteristics for PC Card/CF read and write cycles in
18-Jan-2012
3
attribute/common space and Table 41: Switching characteristics for PC
Card/CF read and write cycles in I/O space, modified values, and
removed footnote concerning preliminary values.
NAND controller waveforms and timings: updated conditions, split
switching characteristics into Table 42: Switching characteristics for
NAND Flash read cycles and Table 43: Switching characteristics for
NAND Flash write cycles, and values modified.
Section 5.3.14: I/O port characteristics: updated footnote1 of Table 49:
I/O static characteristics; updated Output driving current.
Table 50: Output voltage characteristics: swapped “TTL and “CMOS”
ports in the conditions column.
Table 54: I2C characteristics: updated footnote 2.
Updated Table 58: SD / MMC characteristics.
Table 62: ADC characteristics: updated footnote 1.
Table 64: ADC accuracy - limited test conditions: updated footnote 3.
Table 67: TS characteristics: updated footnote 1.
Doc ID 16554 Rev 3
119/120
STM32F103xF, STM32F103xG
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2012 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
120/120
Doc ID 16554 Rev 3
相关型号：
STM32F103RG
XL-density performance line ARM-based 32-bit MCU with 768 KB to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces
STMICROELECTR
STM32F103RGT6
XL-density performance line ARM-based 32-bit MCU with 768 KB to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces
STMICROELECTR
STM32F103T4
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4H6ATR
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4H6AXXX
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4H6TR
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4H6XXX
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4H7ATR
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4H7AXXX
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4H7TR
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4H7XXX
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
STM32F103T4T6ATR
Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明