STM32F103TBT6XXX [STMICROELECTRONICS]
Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces; 中密度高性能线的基于ARM的32位MCU，具有64或128 KB的闪存， USB ， CAN ，7个定时器， 2的ADC ，9个通信接口
| 型号： | STM32F103TBT6XXX |
| 厂家： | 
ST |
| 描述： | Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces |
| 文件： | 总92页 (文件大小：1212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F103x8
STM32F103xB
Medium-density performance line ARM-based 32-bit MCU with 64 or
128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz maximum frequency,
VFQFPN36
LQFP100 14 × 14 m
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
6 × 6 mm
LQFP64 10 × 10 m
LQFP48 7 × 7 m
access
– Single-cycle multiplication and hardware
BGA100 10 × 10 mm
BGA64 5 × 5 mm
division
■ Memories
■ Debug mode
– 64 or 128 Kbytes of Flash memory
– Serial wire debug (SWD) & JTAG interfaces
– 20 Kbytes of SRAM
■ 7 timers
■ Clock, reset and supply management
– Three 16-bit timers, each with up to 4
– 2.0 to 3.6 V application supply and I/Os
IC/OC/PWM or pulse counter and
– POR, PDR, and programmable voltage
detector (PVD)
quadrature (incremental) encoder input
– 16-bit, motor control PWM timer with dead-
time generation and emergency stop
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– 2 watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
■ Up to 9 communication interfaces
2
– Up to 2 x I C interfaces (SMBus/PMBus)
■ Low power
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Sleep, Stop and Standby modes
– V
supply for RTC and backup registers
BAT
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full-speed interface
■ 2 x 12-bit, 1 µs A/D converters (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Temperature sensor
■ CRC calculation unit, 96-bit unique ID
®
■ Packages are ECOPACK
■ DMA
Table 1.
Reference
Device summary
Part number
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
2
I Cs and USARTs
STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103x8
STM32F103xB
■ Up to 80 fast I/O ports
STM32F103RB STM32F103VB,
STM32F103CB
– 26/37/51/80 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
September 2009
Doc ID 13587 Rev 11
1/92
www.st.com
1
Contents
STM32F103x8, STM32F103xB
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
®
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
ARM Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 12
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 12
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 12
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 13
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 15
2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 17
2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Contents
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 36
Embedded reset and power control block characteristics . . . . . . . . . . . 36
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 56
5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.16 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6
7
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1
6.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2.1
6.2.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 83
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Doc ID 13587 Rev 11
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Contents
STM32F103x8, STM32F103xB
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4/92
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Maximum current consumption in Run mode, code with data processing
Table 14.
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 41
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 42
Typical current consumption in Run mode, code with data processing
Table 15.
Table 16.
Table 17.
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Typical current consumption in Sleep mode, code running from Flash or
Table 18.
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SCL frequency (f
= 36 MHz.,V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PCLK1
DD
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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List of tables
STM32F103x8, STM32F103xB
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
max for f = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
R
AIN
ADC
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 74
LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 77
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 78
TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 79
LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 81
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F103xx Performance Line VFQFPN36 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 40
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 40
Figure 16. Typical current consumption on V
with RTC on versus temperature at different
BAT
V
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
BAT
Figure 17. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DD
Figure 18. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DD
Figure 19. Typical current consumption in Standby mode versus temperature at
V
= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DD
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2
Figure 26. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 27. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
(1)
Figure 28. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
(1)
Figure 29. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 30. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 31. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 32. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 33. Power supply and reference decoupling (V
Figure 34. Power supply and reference decoupling (V
Figure 35. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline
not connected to V
). . . . . . . . . . . . . . 71
). . . . . . . . . . . . . . . . . 72
REF+
DDA
connected to V
REF+
DDA
(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
(1)(2)(3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 36. Recommended footprint (dimensions in mm)
Figure 37. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 38. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 76
Figure 39. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 77
(1)
Figure 40. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 41. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 78
Doc ID 13587 Rev 11
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List of figures
STM32F103x8, STM32F103xB
(1)
Figure 42. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 43. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 79
Figure 44. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 80
Figure 45. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 81
(1)
Figure 46. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 47. LQFP100 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
D
A
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Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers.
For more details on the whole STMicroelectronics STM32F103xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The medium-density STM32F103xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2
Description
The STM32F103x8 and STM32F103xB performance line family incorporates the high-
performance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-
speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes),
and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as
2
well as standard and advanced communication interfaces: up to two I Cs and SPIs, three
USARTs, an USB and a CAN.
The STM32F103xx medium-density performance line family operates from a 2.0 to 3.6 V
power supply. It is available in both the –40 to +85 °C temperature range and the –40 to
+105 °C extended temperature range. A comprehensive set of power-saving mode allows
the design of low-power applications.
The STM32F103xx medium-density performance line family includes devices in six different
package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F103xx medium-density performance line microcontroller
family suitable for a wide range of applications:
●
●
●
●
●
Motor drive and application control
Medical and handheld equipment
PC peripherals gaming and GPS platforms
Industrial applications: PLC, inverters, printers, and scanners
Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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Description
STM32F103x8, STM32F103xB
2.1
Device overview
Table 2.
STM32F103xx medium-density device features and peripheral counts
STM32F103Tx STM32F103Cx STM32F103Rx
Peripheral
STM32F103Vx
64 128
Flash - Kbytes
SRAM - Kbytes
64
20
3
64
20
3
128
20
3
64
128
20
3
20
3
General-purpose
Advanced-control
1
1
1
1
SPI
1
2
2
3
1
1
2
2
3
1
1
2
2
I2C
1
2
2
USART
USB
CAN
2
3
3
1
1
1
1
1
1
GPIOs
26
37
2
51
80
12-bit synchronized ADC
Number of channels
2
2
2
10 channels
10 channels
16 channels
16 channels
CPU frequency
72 MHz
2.0 to 3.6 V
Operating voltage
Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9)
Junction temperature: –40 to + 125 °C (see Table 9)
Operating temperatures
Packages
LQFP64,
LQFP100,
LFBGA100
VFQFPN36
LQFP48
TFBGA64
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STM32F103x8, STM32F103xB
Description
2.2
Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are
identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as
medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are
referred to as high-density devices.
Low- and high-density devices are an extension of the STM32F103x8/B devices, they are
specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-
density devices feature lower Flash memory and RAM capacities, less timers and
peripherals. High-density devices have higher Flash memory and RAM capacities, and
2
additional peripherals like SDIO, FSMC, I S and DAC, while remaining fully compatible with
the other members of the STM32F103xx family.
The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE
are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user
to try different memory densities and providing a greater degree of freedom during the
development cycle.
Moreover, the STM32F103xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3.
STM32F103xx family
Low-density devices Medium-density devices
High-density devices
16 KB
Flash
32 KB
64 KB
Flash
128 KB
Flash
256 KB
Flash
384 KB
Flash
512 KB
Flash
Pinout
Flash(1)
6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM
144
100
5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I2Ss, 2 × I2Cs
3 × USARTs
USB, CAN, 2 × PWM timers
3 × ADCs, 2 × DACs, 1 × SDIO
FSMC (100 and 144 pins)
3 × 16-bit timers
2 × USARTs
64
2 × SPIs, 2 × I2Cs, USB,
CAN, 1 × PWM timer
2 × ADCs
2 × 16-bit timers
1 × SPI, 1 × I2C, USB,
CAN, 1 × PWM timer
2 × ADCs
48
36
1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),
the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density
devices.
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Description
STM32F103x8, STM32F103xB
2.3
Overview
®
2.3.1
ARM Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F103xx performance line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
2.3.2
2.3.3
Embedded Flash memory
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.3.4
2.3.5
Embedded SRAM
Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F103xx performance line embeds a nested vectored interrupt controller able to
handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
●
●
●
●
●
●
●
●
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
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STM32F103x8, STM32F103xB
Description
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.6
2.3.7
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed
APB domain is 36 MHz. See Figure 2 for details on the clock tree.
2.3.8
2.3.9
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
●
V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V pins.
DD
●
V
, V
= 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
DDA
SSA
and PLL (minimum voltage to be applied to V
is 2.4 V when the ADC is used).
DDA
V
and V
must be connected to V and V , respectively.
DDA
SSA DD SS
●
V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V is not present.
DD
For more details on how to connect power pins, refer to Figure 12: Power supply scheme.
2.3.10
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
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Description
STM32F103x8, STM32F103xB
, without the need for an
POR/PDR
in reset mode when V is below a specified threshold, V
DD
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
/V power supply and compares it to the V threshold. An interrupt can be
V
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is higher
DD DDA
PVD
DD DDA
than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 11: Embedded reset and power control block characteristics for the values of
and V
V
.
PVD
POR/PDR
2.3.11
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop mode
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.3.12
Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
The Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
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STM32F103x8, STM32F103xB
Description
2.3.13
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
2
The DMA can be used with the main peripherals: SPI, I C, USART, general-purpose and
advanced-control timers TIMx and ADC.
2.3.14
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
supply when present or through the V
pin. The backup registers are ten 16-bit
DD
BAT
registers used to store 20 bytes of user application data when V power is not present.
DD
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low-power RC oscillator or the high-speed external clock divided by 128. The
internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC features
a 32-bit programmable counter for long-term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.15
Timers and watchdogs
The medium-density STM32F103xx performance line devices include an advanced-control
timer, three general-purpose timers, two watchdog timers and a SysTick timer.
Table 4 compares the features of the advanced-control and general-purpose timers.
Table 4.
Timer
Timer feature comparison
Counter Counter Prescaler DMA request Capture/compare Complementary
resolution
type
factor
generation
channels
outputs
Up,
down,
Any integer
between 1
TIM1
16-bit
Yes
4
Yes
up/down and 65536
TIM2,
TIM3,
TIM4
Up,
down,
up/down and 65536
Any integer
between 1
16-bit
Yes
4
No
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
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Description
STM32F103x8, STM32F103xB
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for
●
●
●
●
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switch driven by these outputs.
Many features are shared with those of the general-purpose TIM timers which have the
same architecture. The advanced-control timer can therefore work together with the TIM
timers via the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)
There are up to three synchronizable general-purpose timers embedded in the
STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload
up/down counter, a 16-bit prescaler and feature 4 independent channels each for input
capture/output compare, PWM or one-pulse mode output. This gives up to 12 input
captures/output compares/PWMs on the largest packages.
The general-purpose timers can work together with the advanced-control timer via the Timer
Link feature for synchronization or event chaining. Their counter can be frozen in debug
mode. Any of the general-purpose timers can be used to generate PWM outputs. They all
have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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STM32F103x8, STM32F103xB
SysTick timer
Description
This timer is dedicated for OS, but could also be used as a standard downcounter. It
features:
●
●
●
●
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
2.3.16
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
2.3.17
2.3.18
Universal synchronous/asynchronous receiver transmitter (USART)
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The
other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816
compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
2.3.19
2.3.20
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
Universal serial bus (USB)
The STM32F103xx performance line embeds a USB device peripheral compatible with the
USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function
interface. It has software-configurable endpoint setting and suspend/resume support. The
dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use
a HSE crystal oscillator).
Doc ID 13587 Rev 11
17/92
Description
STM32F103x8, STM32F103xB
2.3.21
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed
2.3.22
ADC (analog-to-digital converter)
Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line
devices and each ADC shares up to 16 external channels, performing conversions in single-
shot or scan modes. In scan mode, automatic conversion is performed on a selected group
of analog inputs.
Additional logic functions embedded in the ADC interface allow:
●
●
●
Simultaneous sample and hold
Interleaved sample and hold
Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control timer
(TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA
trigger respectively, to allow the application to synchronize A/D conversion and timers.
2.3.23
2.3.24
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
connected to the ADC12_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
< 3.6 V. The temperature sensor is internally
DDA
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
18/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Figure 1. STM32F103xx performance line block diagram
Description
TRACECLK
TRACED[0:3]
as AS
Trace
Controlle r
TPIU
pbu s
POWER
Trace/trig
SW/JTAG
V
= 2 to 3.6V
NJTRST
JTDI
JTCK/SWCLK
DD
VOLT. REG.
3.3V TO 1.8V
VSS
Ibus
Cortex-M3 CPU
Flash 128 KB
64 bit
JTMS/SWDIO
@VDD
JTDO
as AF
Fmax: 7 2M Hz
Dbus
SRAM
20 KB
Syst em
NVIC
@VDD
OSC_IN
OSC_OUT
PCLK1
PCLK2
HCLK
FCLK
PLL &
XTAL OSC
4-16 MHz
GP DMA
CLOCK
7 channels
MANAGT
RC 8 MHz
RC 40 kHz
@VDDA
IWDG
@VDDA
Stand by
interface
SUPPLY
SUPERVISION
VBAT
NRST
@VBAT
VDDA
VSSA
Rst
POR / PDR
OSC32_IN
OSC32_OUT
XTAL 32 kHz
Backup
AHB2
APB2
AHB2
APB1
Int
PVD
RTC
AWU
TAMPER-RTC
reg
EXTI
WAKEUP
80AF
Backu p interface
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
4 Channels
4 Channels
TIM2
TIM3
TIM 4
4 Channels
RX,TX, CTS, RTS,
CK, SmartCard as AF
USART2
USART3
RX,TX, CTS, RTS,
CK, SmartCard as AF
MOSI,MISO,SCK,NSS
as AF
SPI2
4 Channels
3 compl. Channels
ETR and BKIN
TIM1
SPI1
I2C1
I2C2
SCL,SDA,SMBA
as AF
MOSI,MISO,
SCK,NSS as AF
SCL,SDA
as AF
RX,TX, CTS, RTS,
Smart Card as AF
USART1
bxCAN
USBDP/CAN_TX
USBDM/CAN_RX
@VDDA
USB 2.0 FS
16AF
12bit ADC1
12bit ADC2
IF
IF
VREF+
SRAM 512B
VREF-
W W D G
Temp sensor
ai14390d
1. TA = –40 °C to +105 °C (junction temperature up to 125 °C).
2. AF = alternate function on I/O port pin.
Doc ID 13587 Rev 11
19/92
Description
STM32F103x8, STM32F103xB
Figure 2.
Clock tree
8 MHz
HSI RC
HSI
USBCLK
48 MHz
USB
Prescaler
/1, 1.5
to USB interface
/2
HCLK
72 MHz max
to AHB bus, core,
memory and DMA
Clock
Enable (3 bits)
to Cortex System timer
/8
SW
PLLSRC
FCLK Cortex
free running clock
36 MHz max
PLLMUL
HSI
AHB
Prescaler
/1, 2..512
APB1
Prescaler
/1, 2, 4, 8, 16
SYSCLK
..., x16
x2, x3, x4
PLL
PCLK1
PLLCLK
HSE
72 MHz
max
to APB1
peripherals
Peripheral Clock
Enable (13 bits)
to TIM2, 3
and 4
TIMXCLK
TIM2,3, 4
If (APB1 prescaler =1) x1
else x2
CSS
Peripheral Clock
Enable (3 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
/2
72 MHz max
PCLK2
to APB2
OSC_OUT
peripherals
4-16 MHz
HSE OSC
Peripheral Clock
Enable (11 bits)
OSC_IN
TIM1 timer
If (APB2 prescaler =1) x1
else x2
to TIM1
TIM1CLK
Peripheral Clock
Enable (1 bit)
to ADC
/128
LSE
ADC
Prescaler
/2, 4, 6, 8
OSC32_IN
to RTC
LSE OSC
ADCCLK
RTCCLK
32.768 kHz
OSC32_OUT
RTCSEL[1:0]
to Independent Watchdog (IWDG)
IWDGCLK
LSI
LSI RC
40 kHz
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
Main
Clock Output
/2
PLLCLK
MCO
HSI
HSE
SYSCLK
MCO
ai14903
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
48 MHz or 72 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
20/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Pinouts and pin description
3
Pinouts and pin description
Figure 3.
STM32F103xx performance line LFBGA100 ballout
1
2
3
4
5
6
7
8
9
10
PC14-
OSC32_IN
PC13-
TAMPER-RTC
A
B
C
D
E
F
PE2
PE3
PE4
PE5
PE6
PC3
PA4
PA5
PA6
PA7
PB9
PB8
PE1
PE0
PB7
PB4
PD5
PD6
PD7
PB3
PD2
PD3
PD4
PA15
PC11
PC12
PD0
PA14
PC10
PA9
PA13
PA12
PA11
PA10
PC7
PC15-
OSC32_OUT
V
PB6
BAT
OSC_IN
OSC_OUT
NRST
V
V
PB5
SS_5
BOOT0
PA8
DD_5
V
V
V
V
PD1
PC2
PC9
PC8
PD11
PD10
PD9
PD8
SS_4
SS_3
SS_2
SS_1
V
V
V
V
NC
PC0
PC1
PA0-WKUP
PA1
PC6
DD_4
DD_3
DD_2
DD_1
G
H
J
V
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
PB15
PB14
PC4
PD15
PD14
PD13
PD12
SSA
V
PC5
PB0
PB1
REF–
V
PA2
PB13
PB12
REF+
K
V
PA3
DDA
AI16001c
Doc ID 13587 Rev 11
21/92
Pinouts and pin description
STM32F103x8, STM32F103xB
Figure 4. STM32F103xx performance line LQFP100 pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD_5
OSC_IN
OSC_OUT
NRST
LQFP100
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PD8
PB15
PB14
PB13
PB12
PA0-WKUP
PA1
PA2
ai14391
22/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Pinouts and pin description
Figure 5. STM32F103xx performance line LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
PC0
PC1
PC2
PC3
8
LQFP64
9
10
11
12
13
14
15
16
PC6
VSSA
VDDA
PA0-WKUP
PB15
PB14
PB13
PB12
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ai14392
Doc ID 13587 Rev 11
23/92
Pinouts and pin description
STM32F103x8, STM32F103xB
Figure 6.
STM32F103xx performance line TFBGA64 ballout
1
2
3
4
5
6
7
8
PC14-
OSC32_IN
PC13-
TAMPER-RTC
A
B
PB9
PB8
PB7
PB6
PB4
BOOT0
PB5
PB3
PD2
PA15
PC11
PA10
PA14
PC10
PA9
PA13
PA12
PA11
PC9
PC15-
OSC32_OUT
V
BAT
C
D
E
F
OSC_IN
V
PC12
SS_4
OSC_OUT
NRST
V
V
V
V
PA8
DD_4
SS_3
SS_2
SS_1
PC1
PC2
PC0
PA2
V
V
V
PC7
PC8
DD_3
DD_2
DD_1
PC6
V
PA5
PB0
PB15
PB14
SSA
V
REF+
G
H
PA0-WKUP
PA1
PA3
PA4
PA6
PA7
PB1
PC4
PB2
PC5
PB10
PB11
PB13
PB12
V
DDA
AI15494
24/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Pinouts and pin description
Figure 7. STM32F103xx performance line LQFP48 pinout
48 47 46 45 44 43 42 41 40 39 38 37
36
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
1
2
3
4
5
6
7
8
9
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
35
34
33
32
31
30
29
28
27
26
25
LQFP48
PA8
VSSA
VDDA
PB15
PB14
PB13
PB12
PA0-WKUP 10
PA1 11
12
PA2
24
13 14 15 16 17 18 19 20 21 22 23
ai14393b
Figure 8.
STM32F103xx Performance Line VFQFPN36 pinout
36 35 34
33 32 31 30 29 28
27
VDD_3
OSC_IN/PD0
OSC_OUT/PD1
NRST
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
1
2
3
4
5
6
7
8
9
26
25
24
QFN36
VSSA
23
22
VDDA
PA0-WKUP
PA1
21
20
PA8
PA2
VDD_1
19
10 11 12 13
14 15 16 17
18
ai14654
Doc ID 13587 Rev 11
25/92
Pinouts and pin description
STM32F103x8, STM32F103xB
Alternate functions(4)
Table 5.
Medium-density STM32F103xx pin definitions
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
A3
B3
C3
D3
E3
B2
-
-
-
-
1
2
3
4
5
6
-
-
-
-
-
-
PE2
PE3
PE4
PE5
PE6
VBAT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
PE2
PE3
PE4
PE5
PE6
VBAT
TRACECK
TRACED0
TRACED1
TRACED2
TRACED3
-
-
-
-
-
-
1
B2
1
PC13-TAMPER-
RTC(5)
A2
A1
B1
2
3
4
A2
A1
B1
2
3
4
7
8
9
-
-
-
I/O
PC13(6)
PC14(6)
PC15(6)
TAMPER-RTC
OSC32_IN
PC14-OSC32_IN(5) I/O
PC15-
I/O
OSC32_OUT
OSC32_OUT(5)
C2
D2
C1
D1
E1
F1
F2
E2
F3
G1
H1
J1
-
-
-
-
10
11
12
13
14
15
16
-
-
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
S
S
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
-
-
5
6
7
-
C1
D1
E1
E3
E2
5
6
7
8
9
2
3
4
-
I
O
I/O
I/O
I/O
I/O
I/O
S
ADC12_IN10
ADC12_IN11
ADC12_IN12
ADC12_IN13
-
-
PC1
PC1
-
F2 10 17
-
PC2
PC2
(7)
-
-
11 18
-
PC3
PC3
8
-
F1 12 19
5
-
VSSA
VSSA
-
-
-
20
21
VREF-
VREF+
VDDA
S
VREF-
VREF+
VDDA
-
G1(7)
-
S
K1
9
H1 13 22
6
S
WKUP/
USART2_CTS(8)
ADC12_IN0/
/
G2 10 G2 14 23
7
PA0-WKUP
I/O
PA0
TIM2_CH1_ETR(8)
USART2_RTS(8)
ADC12_IN1/
/
H2 11 H2 15 24
J2 12 F3 16 25
8
9
PA1
PA2
I/O
I/O
PA1
PA2
TIM2_CH2(8)
USART2_TX(8)
ADC12_IN2/
TIM2_CH3(8)
/
26/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Pinouts and pin description
Alternate functions(4)
Table 5.
Medium-density STM32F103xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
USART2_RX(8)
ADC12_IN3/
TIM2_CH4(8)
/
/
K2 13 G3 17 26 10
PA3
I/O
PA3
E4
F4
-
-
C2 18 27
D2 19 28
-
-
VSS_4
VDD_4
S
S
VSS_4
VDD_4
SPI1_NSS(8)
/
G3 14 H3 20 29 11
H3 15 F4 21 30 12
J3 16 G4 22 31 13
PA4
PA5
PA6
I/O
I/O
I/O
PA4
PA5
PA6
USART2_CK(8)
ADC12_IN4
SPI1_SCK(8)
ADC12_IN5
/
SPI1_MISO(8)
ADC12_IN6/
TIM3_CH1(8)
/
/
TIM1_BKIN
TIM1_CH1N
SPI1_MOSI(8)
ADC12_IN7/
TIM3_CH2(8)
K3 17 H4 23 32 14
PA7
I/O
PA7
G4
H4
-
-
H5 24 33
H6 25 34
PC4
PC5
I/O
I/O
PC4
PC5
ADC12_IN14
ADC12_IN15
ADC12_IN8/
TIM3_CH3(8)
J4 18 F5 26 35 15
PB0
PB1
I/O
I/O
PB0
PB1
TIM1_CH2N
TIM1_CH3N
ADC12_IN9/
TIM3_CH4(8)
K4 19 G5 27 36 16
G5 20 G6 28 37 17
PB2
PE7
I/O FT PB2/BOOT1
H5
J5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
38
39
40
41
42
43
44
45
46
-
-
-
-
-
-
-
-
-
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
PE7
PE8
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
PE8
K5
G6
H6
J6
PE9
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE10
PE11
PE12
PE13
PE14
PE15
K6
G7
H7
I2C2_SCL/
J7 21 G7 29 47
K7 22 H7 30 48
-
-
PB10
I/O FT
PB10
TIM2_CH3
TIM2_CH4
USART3_TX(8)
I2C2_SDA/
PB11
VSS_1
I/O FT
S
PB11
VSS_1
USART3_RX(8)
E7 23 D6 31 49 18
Doc ID 13587 Rev 11
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Pinouts and pin description
STM32F103x8, STM32F103xB
Alternate functions(4)
Table 5.
Medium-density STM32F103xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
F7 24 E6 32 50 19
VDD_1
PB12
S
VDD_1
PB12
SPI2_NSS/
I2C2_SMBAl/
USART3_CK(8)
TIM1_BKIN(8)
K8 25 H8 33 51
-
-
I/O FT
/
SPI2_SCK/
J8 26 G8 34 52
PB13
I/O FT
PB13
USART3_CTS(8)
TIM1_CH1N (8)
/
SPI2_MISO/
H8 27 F8 35 53
G8 28 F7 36 54
-
-
PB14
PB15
I/O FT
I/O FT
PB14
PB15
USART3_RTS(8)
TIM1_CH2N (8)
SPI2_MOSI/
TIM1_CH3N(8)
K9
J9
-
-
-
-
-
-
-
-
-
-
-
-
55
56
57
58
-
-
-
-
PD8
PD9
I/O FT
I/O FT
I/O FT
I/O FT
PD8
PD9
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
H9
G9
PD10
PD11
PD10
PD11
TIM4_CH1 /
USART3_RTS
K10
-
-
-
59
-
PD12
I/O FT
PD12
J10
H10
G10
F10
E10
F9
-
-
-
-
-
-
-
-
-
-
60
61
62
-
-
-
-
-
-
-
PD13
PD14
PD15
PC6
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
PD13
PD14
PD15
PC6
TIM4_CH2
TIM4_CH3
TIM4_CH4
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
F6 37 63
E7 38 64
E8 39 65
D8 40 66
PC7
PC7
PC8
PC8
E9
-
PC9
PC9
USART1_CK/
D9 29 D7 41 67 20
C9 30 C7 42 68 21
D10 31 C6 43 69 22
PA8
PA9
I/O FT
I/O FT
I/O FT
PA8
PA9
TIM1_CH1(8)/MCO
USART1_TX(8)
TIM1_CH2(8)
/
USART1_RX(8)
TIM1_CH3(8)
/
PA10
PA10
USART1_CTS/
CANRX(8)/ USBDM
TIM1_CH4(8)
C10 32 C8 44 70 23
B10 33 B8 45 71 24
PA11
PA12
I/O FT
I/O FT
PA11
PA12
USART1_RTS/
CANTX(8) //USBDP
TIM1_ETR(8)
28/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Pinouts and pin description
Alternate functions(4)
Table 5.
Medium-density STM32F103xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
A10 34 A8 46 72 25
F8 73
PA13
I/O FT JTMS/SWDIO
Not connected
PA13
-
-
-
-
E6 35 D5 47 74 26
F6 36 E5 48 75 27
A9 37 A7 49 76 28
VSS_2
VDD_2
PA14
S
S
VSS_2
VDD_2
I/O FT JTCK/SWCLK
PA14
TIM2_CH1_ETR/
PA15 /SPI1_NSS
A8 38 A6 50 77 29
PA15
I/O FT
JTDI
B9
B8
C8
D8
E8
B7
C7
D7
B6
C6
D6
-
-
B7 51 78
B6 52 79
C5 53 80
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
I/O FT
I/O FT
I/O FT
PC10
PC11
PC12
USART3_TX
USART3_RX
USART3_CK
CANRX
-
5
6
C1
D1
5
6
81
82
2
3
-
I/O FT OSC_IN(9)
I/O FT OSC_OUT(9)
CANTX
B5 54 83
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
PD2
PD3
PD4
PD5
PD6
PD7
TIM3_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
84
85
86
87
88
-
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
-
-
-
-
TIM2_CH2 / PB3
TRACESWO
SPI1_SCK
A7 39 A5 55 89 30
A6 40 A4 56 90 31
PB3
PB4
I/O FT
I/O FT
JTDO
TIM3_CH1/ PB4/
SPI1_MISO
JNTRST
TIM3_CH2 /
SPI1_MOSI
C5 41 C4 57 91 32
B5 42 D3 58 92 33
PB5
PB6
I/O
PB5
PB6
I2C1_SMBAl
I2C1_SCL(8)
TIM4_CH1(8)
/
I/O FT
USART1_TX
USART1_RX
I2C1_SDA(8)
TIM4_CH2(8)
/
A5 43 C3 59 93 34
D5 44 B4 60 94 35
PB7
BOOT0
PB8
I/O FT
I
PB7
BOOT0
PB8
I2C1_SCL /
CANRX
B4 45 B3 61 95
A4 46 A3 62 96
-
-
I/O FT
TIM4_CH3(8)
TIM4_CH4(8)
I2C1_SDA/
CANTX
PB9
I/O FT
PB9
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Pinouts and pin description
STM32F103x8, STM32F103xB
Alternate functions(4)
Table 5.
Medium-density STM32F103xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
D4
C4
-
-
-
-
-
97
98
-
-
PE0
PE1
I/O FT
I/O FT
S
PE0
PE1
TIM4_ETR
-
E5 47 D4 63 99 36
F5 48 E4 64 100
VSS_3
VDD_3
VSS_3
VDD_3
1
S
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 10.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no
need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
30/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Memory mapping
4
Memory mapping
The memory map is shown in Figure 9.
Figure 9.
Memory map
APB memory space
0xFFFF FFFF
reserved
0xE010 0000
0x6000 0000
0xFFFF FFFF
reserved
reserved
CRC
0x4002 3400
0x4002 3000
7
reserved
0x4002 2400
0x4002 2000
0x4002 1400
0x4002 1000
0xE010 0000
Cortex-M3 Internal
Peripherals
Flash Interface
reserved
0xE000 0000
RCC
reserved
6
0x4002 0400
0x4002 0000
DMA
reserved
0xC000 0000
0x4001 3C00
0x4001 3800
0x4001 3400
USART1
reserved
SPI1
5
0x4001 3000
0x4001 2C00
0x4001 2800
0x4001 2400
TIM1
0xA000 0000
ADC2
ADC1
reserved
Port E
0x4001 1C00
0x4001 1800
0x4001 1400
0x4001 1000
0x1FFF FFFF
0x1FFF F80F
4
reserved
Port D
Port C
0x8000 0000
Option Bytes
0x1FFF F800
Port B
Port A
EXTI
0x4001 0C00
0x4001 0800
3
System memory
0x4001 0400
0x4001 0000
0x1FFF F000
AFIO
0x6000 0000
reserved
0x4000 7400
0x4000 7000
0x4000 6C00
PWR
BKP
2
reserved
bxCAN
reserved
0x4000 6800
0x4000 6400
Peripherals
0x4000 0000
shared 512 byte
USB/CAN SRAM
0x4000 6000
0x4000 5C00
0x4000 5800
USB Registers
1
I2C2
I2C1
0x4000 5400
0x4000 4C00
SRAM
0x2000 0000
reserved
USART3
0x0801 FFFF
0x4000 4800
0x4000 4400
0x4000 3C00
USART2
0
Flash memory
reserved
SPI2
0x4000 3800
0x0800 0000
0x0000 0000
0x0000 0000
reserved
IWDG
Aliased to Flash or system
memory depending on
BOOT pins
0x4000 3400
0x4000 3000
0x4000 2C00
0x4000 2800
0x4000 0C00
0x4000 0800
WWDG
RTC
reserved
TIM4
Reserved
TIM3
TIM2
0x4000 0400
0x4000 0000
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Electrical characteristics
STM32F103x8, STM32F103xB
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
2 V V 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
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STM32F103x8, STM32F103xB
Electrical characteristics
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
STM32F103xx pin
STM32F103xx pin
C = 50 pF
V
IN
ai14141
ai14142
5.1.6
Power supply scheme
Figure 12. Power supply scheme
V
BAT
Backup circuitry
(OSC32K,RTC,
Wake-up logic
Power switch
1.8-3.6V
Backup registers)
OUT
IN
IO
Logic
GP I/Os
Kernel logic
(CPU,
Digital
& Memories)
V
DD
V
DD
1/2/3/4/5
Regulator
5 × 100 nF
+ 1 × 4.7 µF
V
SS
1/2/3/4/5
V
DD
V
DDA
V
REF
V
REF+
Analog:
RCs, PLL,
...
10 nF
+ 1 µF
10 nF
+ 1 µF
V
ADC
REF-
V
SSA
ai14125d
Caution:
In Figure 12, the 4.7 µF capacitor must be connected to V
.
DD3
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Electrical characteristics
STM32F103x8, STM32F103xB
5.1.7
Current consumption measurement
Figure 13. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics,
Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 6.
Symbol
Voltage characteristics
Ratings
External main supply voltage (including VDDA
Min
Max
Unit
VDD–VSS
–0.3
4.0
(1)
and VDD
)
V
Input voltage on five volt tolerant pin(2)
Input voltage on any other pin(2)
VSS 0.3
VSS 0.3
+5.5
VDD+0.3
50
VIN
|VDDx
|
Variations between different VDD power pins
Variations between all the different ground pins
mV
|VSSX VSS
|
50
see Section 5.3.11:
Absolute maximum ratings
(electrical sensitivity)
Electrostatic discharge voltage (human body
model)
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is
induced by VIN < VSS
.
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STM32F103x8, STM32F103xB
Electrical characteristics
Table 7.
Symbol
IVDD
IVSS
Current characteristics
Ratings
Max.
Unit
Total current into VDD/VDDA power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on NRST pin
150
150
25
25
5
IIO
mA
(2)(3)
IINJ(PIN)
Injected current on HSE OSC_IN and LSE OSC_IN pins
Injected current on any other pin(4)
5
5
(2)
IINJ(PIN)
Total injected current (sum of all I/O and control pins)(4)
25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS
.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
characteristics.
4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 8.
Thermal characteristics
Ratings
Symbol
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Table 9.
Symbol
General operating conditions
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK1
fPCLK2
VDD
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
0
0
0
2
72
36
72
3.6
MHz
V
Analog operating voltage
(ADC not used)
2
3.6
Must be the same potential
as VDD
(1)
VDDA
V
V
(2)
Analog operating voltage
(ADC used)
2.4
1.8
3.6
3.6
VBAT
Backup operating voltage
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Electrical characteristics
STM32F103x8, STM32F103xB
Table 9.
Symbol
General operating conditions (continued)
Parameter
Conditions
Min
Max
Unit
LFBGA100
454
434
308
444
363
1110
85
LQFP100
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(3)
TFBGA64
PD
mW
LQFP64
LQFP48
VFQFPN36
Maximum power dissipation
Low power dissipation(4)
Maximum power dissipation
Low power dissipation(4)
6 suffix version
7 suffix version
–40
–40
–40
–40
–40
–40
Ambient temperature for 6
suffix version
°C
°C
°C
105
105
125
105
125
TA
TJ
Ambient temperature for 7
suffix version
Junction temperature range
1. When the ADC is used, refer to Table 45: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 82).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 82).
5.3.2
5.3.3
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 10. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
VDD fall time rate
0
tVDD
µs/V
20
Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 9.
DD
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STM32F103x8, STM32F103xB
Electrical characteristics
Table 11. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
2.1
2
2.18 2.26
2.08 2.16
V
V
2.19 2.28 2.37
2.09 2.18 2.27
2.28 2.38 2.48
2.18 2.28 2.38
2.38 2.48 2.58
2.28 2.38 2.48
2.47 2.58 2.69
2.37 2.48 2.59
2.57 2.68 2.79
2.47 2.58 2.69
V
V
V
V
V
V
Programmable voltage
detector level selection
VPVD
V
V
V
V
2.66 2.78
2.56 2.68
2.76 2.88
2.66 2.78
100
2.9
2.8
3
V
V
V
2.9
V
(2)
VPVDhyst
PVD hysteresis
mV
V
1.8(1)
Falling edge
Rising edge
1.88 1.96
Power on/power down
reset threshold
VPOR/PDR
1.84 1.92
40
2.0
V
(2)
VPDRhyst
PDR hysteresis
mV
ms
(2)
TRSTTEMPO
Reset temporization
1
2.5
4.5
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F103x8, STM32F103xB
5.3.4
Embedded reference voltage
The parameters given in Table 12 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 9.
DD
Table 12. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
–40 °C < TA < +105 °C 1.16 1.20
1.26
1.24
V
V
VREFINT Internal reference voltage
–40 °C < TA < +85 °C
1.16 1.20
5.1
ADC sampling time when
reading the internal reference
voltage
(1)
17.1(2)
10
TS_vrefint
µs
Internal reference voltage
spread over the temperature
range
(2)
VRERINT
VDD = 3 V 10 mV
mV
(2)
TCoeff
Temperature coefficient
100 ppm/°C
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f frequency (0 wait state from 0
HCLK
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
●
●
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f
= f
/2, f
= f
PCLK1
HCLK
PCLK2 HCLK
The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed
under ambient temperature and V supply voltage conditions summarized in Table 9.
DD
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STM32F103x8, STM32F103xB
Electrical characteristics
Table 13. Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C TA = 105 °C
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
50
50.3
36.2
28.7
20.1
14.9
8.9
36.1
28.6
19.9
14.7
8.6
External clock(2), all
peripherals enabled
Supplycurrent in
Run mode
IDD
mA
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
32.8
24.4
19.8
13.9
10.7
6.8
32.9
24.5
19.9
14.2
11
External clock(2), all
peripherals disabled
7.1
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 14. Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol Parameter
Conditions
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz
48
31.5
24
50
32
25.5
18
13
8
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
External clock(2), all
peripherals enabled
17.5
12.5
7.5
Supply
IDD
current in
Run mode
mA
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
29
29.5
21
16.5
12
9
20.5
16
External clock(2), all
peripherals disabled
11.5
8.5
5.5
6
1. Based on characterization, tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F103x8, STM32F103xB
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
45
40
35
30
72 MHz
25
36 MHz
16 MHz
8 MHz
20
15
10
5
0
-40
0
25
70
85
105
Temperature (°C)
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled
30
25
20
72 MHz
36 MHz
15
16 MHz
8 MHz
10
5
0
-40
0
25
70
85
105
Temperature (°C)
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Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Electrical characteristics
Table 15. Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
TA = 105 °C
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
30
20
15.5
11.5
8.5
5.5
7.5
6
32
20.5
16
12
9
External clock(2), all
peripherals enabled
6
Supply current in
Sleep mode
IDD
mA
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
8
6.5
5.5
5
External clock(2), all
peripherals disabled
5
4.5
4
4.5
4
3
1. based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F103x8, STM32F103xB
Table 16. Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Max
Symbol Parameter
Conditions
Unit
VDD/VBAT VDD/VBAT VDD/VBAT TA = TA =
= 2.0 V
= 2.4 V
= 3.3 V 85 °C 105 °C
Regulator in Run mode, low-speed
and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
-
23.5
24
14
200
180
370
340
Supplycurrent
in Stop mode
Regulator in Low Power mode, low-
speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
-
13.5
IDD
Low-speed internal RC oscillator and
independent watchdog ON
-
-
2.6
2.4
3.4
3.2
-
-
-
-
µA
Supplycurrent Low-speed internal RC oscillator
in Standby
mode
ON, independent watchdog OFF
Low-speed internal RC oscillator and
independent watchdog OFF, low-
speed oscillator and RTC OFF
-
1.7
1.1
2
4
5
Backup
IDD_VBAT domainsupply Low-speed oscillator and RTC ON
current
0.9
1.4
1.9(2)
2.2
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not tested in production.
Figure 16. Typical current consumption on V
with RTC on versus temperature at different
BAT
V
values
BAT
2.5
2
2 V
1.5
1
2.4 V
3 V
0.5
0
3.6 V
–40 °C
25 °C
70 °C
85 °C
105 °C
Temperature (°C)
ai17351
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STM32F103x8, STM32F103xB
Electrical characteristics
Figure 17. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at V = 3.3 V and 3.6 V
DD
300
250
200
150
100
50
3.3 V
3.6 V
0
-45
25
70
90
110
Temperature (°C)
Figure 18. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at V = 3.3 V and 3.6 V
DD
300
250
200
150
100
50
3.3 V
3.6 V
0
-40
0
25
70
85
105
Temperature (°C)
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Electrical characteristics
STM32F103x8, STM32F103xB
Figure 19. Typical current consumption in Standby mode versus temperature at
V
= 3.3 V and 3.6 V
DD
4.5
4
3.5
3
2.5
2
3.3 V
3.6 V
1.5
1
0.5
0
–45 °C
25 °C
85 °C
105 °C
Temperature (°C)
Typical current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load).
DD SS
All peripherals are disabled except if it is explicitly mentioned.
The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1
HCLK
wait state from 24 to 48 MHz and 2 wait states above).
●
●
●
Ambient temperature and V supply voltage conditions summarized in Table 9.
DD
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f
= f
/4, f
2 = f
/2, f
=
PCLK1
HCLK
PCLK
HCLK
ADCCLK
f
/4
PCLK2
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STM32F103x8, STM32F103xB
Electrical characteristics
Table 17. Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
Allperipherals Allperipherals
enabled(2)
disabled
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
36
24.2
19
27
18.6
14.8
10.1
7.4
12.9
9.3
External clock(3)
5.5
4.6
mA
4 MHz
3.3
2.8
2 MHz
2.2
1.9
1 MHz
1.6
1.45
1.25
1.06
23.9
17.9
14.1
9.5
500 kHz
125 kHz
64 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
1.3
Supply
1.08
31.4
23.5
18.3
12.2
8.5
IDD
current in
Run mode
Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
6.8
4.9
4
mA
4 MHz
2.7
2.2
frequency
2 MHz
1.6
1.4
1 MHz
1.02
0.73
0.5
0.9
500 kHz
125 kHz
0.67
0.48
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F103x8, STM32F103xB
Table 18. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
All peripherals All peripherals
enabled(2)
disabled
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
14.4
9.9
5.5
3.9
7.6
3.1
5.3
2.3
3.8
1.8
External clock(3)
2.1
1.2
4 MHz
1.6
1.1
2 MHz
1.3
1
1 MHz
1.11
1.04
0.98
12.3
9.3
0.98
0.96
0.95
4.4
500 kHz
125 kHz
64 MHz
48 MHz
36 MHz
24 MHz
16 MHz
Supply
IDD
current in
mA
Sleep mode
3.3
7
2.5
4.8
1.8
Running on high
speed internal RC
3.2
1.2
(HSI), AHB prescaler 8 MHz
1.6
0.6
used to reduce the
frequency
4 MHz
1
0.5
2 MHz
0.72
0.56
0.49
0.43
0.47
0.44
0.42
0.41
1 MHz
500 kHz
125 kHz
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F103x8, STM32F103xB
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed
under the following conditions:
●
●
●
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
●
ambient operating temperature and V supply voltage conditions summarized in
DD
Table 6
(1)
Table 19. Peripheral current consumption
Peripheral
Typical consumption at 25 °C
Unit
TIM2
TIM3
TIM4
SPI2
1.2
1.2
0.9
0.2
USART2
0.35
0.35
0.39
0.39
0.65
0.72
0.47
0.47
0.47
0.47
0.47
1.81
1.78
1.6
APB1
mA
USART3
I2C1
I2C2
USB
CAN
GPIO A
GPIO B
GPIO C
GPIO D
GPIO E
APB2
mA
ADC1(2)
ADC2
TIM1
SPI1
0.43
0.85
USART1
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit
in the ADC_CR2 register is set to 1.
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Electrical characteristics
STM32F103x8, STM32F103xB
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 9.
Table 20. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fHSE_ext
1
8
25
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
VDD
V
0.3VDD
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
16
45
tw(HSE)
ns
tr(HSE)
tf(HSE)
20
Cin(HSE) OSC_IN input capacitance(1)
5
pF
%
DuCy(HSE) Duty cycle
55
1
IL
OSC_IN Input leakage current
VSS VIN VDD
µA
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 9.
Table 21. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
0.7VDD
VSS
VDD
V
OSC32_IN input pin low level
voltage
0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
OSC32_IN rise or fall time(1)
450
ns
tr(LSE)
tf(LSE)
50
Cin(LSE) OSC32_IN input capacitance(1)
5
pF
%
DuCy(LSE) Duty cycle
30
70
1
OSC32_IN Input leakage
current
IL
VSS VIN VDD
µA
1. Guaranteed by design, not tested in production.
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STM32F103x8, STM32F103xB
Electrical characteristics
Figure 20. High-speed external clock source AC timing diagram
V
HSEH
90%
10%
V
HSEL
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
EXTERNAL
CLOCK SOURCE
I
L
OSC _IN
STM32F103xx
ai14143
Figure 21. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
t
W(LSE)
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
EXTERNAL
CLOCK SOURCE
I
L
OSC32_IN
STM32F103xx
ai14144b
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 22. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
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Electrical characteristics
STM32F103x8, STM32F103xB
(1) (2)
Table 22. HSE 4-16 MHz oscillator characteristics
Symbol Parameter Conditions
fOSC_IN Oscillator frequency
Min
Typ
Max Unit
4
8
16
MHz
RF
Feedback resistor
200
k
Recommended load capacitance
versus equivalent serial
C
RS = 30
30
pF
resistance of the crystal (RS)(3)
VDD = 3.3 V, VIN = VSS
with 30 pF load
i2
HSE driving current
1
mA
gm
Oscillator transconductance
startup time
Startup
25
mA/V
ms
(4)
tSU(HSE
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 22). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C . Refer to the application note AN2867 “Oscillator design guide for ST
C
L1
L2
microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
STM32F103xx
OSC_OUT
(1)
R
EXT
C
L2
ai14145
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 23. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
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STM32F103x8, STM32F103xB
Electrical characteristics
(1)
Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Feedback resistor
Conditions
Min
Typ
Max
Unit
RF
5
M
Recommended load capacitance
versus equivalent serial
C(2)
RS = 30 k
15
pF
resistance of the crystal (RS)(3)
I2
LSE driving current
Oscillator Transconductance
startup time
VDD = 3.3 V, VIN = VSS
1.4
µA
µA/V
s
gm
5
(4)
tSU(LSE)
VDD is stabilized
3
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768
kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Note:
For C and C it is recommended to use high-quality ceramic capacitors in the 5 pF to
L1 L2
15 pF range selected to match the requirements of the crystal or resonator. C and C are
L1
L2,
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C and C .
L1
L2
Load capacitance C has the following formula: C = C x C / (C + C ) + C where
L
L
L1
L2
L1
L2
stray
C
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
stray
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended
L1
L2
to use a resonator with a load capacitance C 7 pF. Never use a resonator with a load
L
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C = 6 pF, and C
= 2 pF,
L
stray
then C = C = 8 pF.
L1
L2
Figure 23. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_IN
LSE
Bias
controlled
gain
32.768 kHz
resonator
R
F
STM32F103xx
OSC32_OUT
C
L2
ai14146
5.3.7
Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 9.
DD
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Electrical characteristics
STM32F103x8, STM32F103xB
High-speed internal (HSI) RC oscillator
(1)
Table 24. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max Unit
fHSI
8
MHz
User-trimmed with the RCC_CR
register(2)
1(3)
%
TA = –40 to 105 °C
–2
2.5
2.2
2
%
%
%
%
Accuracy of the HSI
oscillator
ACCHSI
TA = –10 to 85 °C
Factory-
–1.5
–1.3
–1.1
calibrated(4)
TA = 0 to 70 °C
TA = 25 °C
1.8
HSI oscillator
startup time
(4)
tsu(HSI)
1
2
µs
HSI oscillator power
consumption
(4)
IDD(HSI)
80
100
µA
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
Low-speed internal (LSI) RC oscillator
(1)
Table 25. LSI oscillator characteristics
Symbol
Parameter
Typ
Max
Unit
Min
(2)
fLSI
Frequency
30
40
60
85
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
(3)
IDD(LSI)
LSI oscillator power consumption
0.65
1.2
µA
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 9.
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STM32F103x8, STM32F103xB
Electrical characteristics
Table 26. Low-power mode wakeup timings
Symbol Parameter
Typ
Unit
(1)
Wakeup from Sleep mode
1.8
3.6
µs
tWUSLEEP
Wakeup from Stop mode (regulator in run mode)
(1)
µs
µs
tWUSTOP
Wakeup from Stop mode (regulator in low power
mode)
5.4
50
(1)
Wakeup from Standby mode
tWUSTDBY
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 27 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 9.
DD
Table 27. PLL characteristics
Value
Symbol
Parameter
Unit
Min(1)
Typ
Max(1)
PLL input clock(2)
1
8.0
25
60
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
40
16
fPLL_OUT
tLOCK
72
MHz
µs
200
300
Jitter
Cycle-to-cycle jitter
ps
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
Table 28. Flash memory characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
tprog
16-bit programming time TA–40 to +105 °C
40
20
20
52.5
70
40
40
µs
ms
ms
tERASE Page (1 KB) erase time TA –40 to +105 °C
tME
Mass erase time
TA –40 to +105 °C
Doc ID 13587 Rev 11
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Electrical characteristics
Table 28. Flash memory characteristics (continued)
STM32F103x8, STM32F103xB
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Read mode
fHCLK = 72 MHz with 2 wait
states, VDD = 3.3 V
20
5
mA
mA
IDD
Supply current
Write / Erase modes
fHCLK = 72 MHz, VDD = 3.3 V
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
50
µA
V
Vprog Programming voltage
2
3.6
1. Guaranteed by design, not tested in production.
Table 29. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions
Unit
Min(1) Typ
Max
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND Endurance
kcycles
10
1 kcycle(2) at TA = 85 °C
30
10
20
tRET
Data retention 1 kcycle(2) at TA = 105 °C
Years
10 kcycles(2) at TA = 55 °C
1. Based on characterization, not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 30. They are based on the EMS levels and classes
defined in application note AN1709.
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STM32F103x8, STM32F103xB
Electrical characteristics
Level/
Table 30. EMS characteristics
Symbol
Parameter
Conditions
Class
VDD 3.3 V, TA +25 °C,
fHCLK 72 MHz
conforms to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD3.3 V, TA +25 °C,
fHCLK 72 MHz
conforms to IEC 61000-4-4
VEFTB
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 31. EMI characteristics
Max vs. [fHSE/fHCLK
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/48 MHz 8/72 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
12
22
23
4
12
19
29
4
VDD 3.3 V, TA 25 °C,
LQFP100 package
compliant with
dBµV
-
SEMI
Peak level
IEC 61967-2
Doc ID 13587 Rev 11
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Electrical characteristics
STM32F103x8, STM32F103xB
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 32. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
TA +25 °C
conforming to
JESD22-A114
Electrostatic discharge
voltage (human body model)
VESD(HBM)
2
2000
500
V
Electrostatic discharge
TA +25 °C
conforming to
JESD22-C101
VESD(CDM) voltage (charge device
model)
II
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 33. Electrical sensitivities
Symbol
Parameter
Conditions
Class
II level A
LU
Static latch-up class
TA +105 °C conforming to JESD78A
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Electrical characteristics
5.3.12
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL
compliant.
Table 34. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
–0.5
0.8
V
Standard IO input high level
voltage
TTL ports
2
VDD+0.5
VIH
IO FT(1) input high level voltage
2
5.5V
VIL
Input low level voltage
–0.5
0.35 VDD
VDD+0.5
CMOS ports
V
VIH
Input high level voltage
0.65 VDD
Standard IO Schmitt trigger
voltage hysteresis(2)
200
mV
mV
Vhys
IO FT Schmitt trigger voltage
hysteresis(2)
(3)
5% VDD
VSS VIN VDD
Standard I/Os
1
3
Ilkg
Input leakage current (4)
µA
VIN= 5 V
I/O FT
Weak pull-up equivalent
resistor(5)
RPU
VIN VSS
VIN VDD
30
30
40
50
50
k
Weak pull-down equivalent
resistor(5)
RPD
CIO
40
5
k
I/O pin capacitance
pF
1. FT = Five-volt tolerant.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in
production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required), their
characteristics consider the most strict CMOS-technology or TTL parameters:
●
For V :
IH
–
–
if V is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included
DD
if V is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included
DD
●
For V :
IL
–
–
if V is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included
DD
if V is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included
DD
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Electrical characteristics
STM32F103x8, STM32F103xB
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed V ).
OL
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 7).
VDD
●
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 7).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 9. All I/Os are CMOS and TTL compliant.
Table 35. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
VOL
0.4
TTL port
IIO = +8 mA
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)
2.7 V < VDD < 3.6 V
VOH
VDD–0.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)
VOL
0.4
1.3
0.4
CMOS port
IIO =+ 8mA
V
V
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)
2.7 V < VDD < 3.6 V
VOH
2.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(3)
VOL
IIO = +20 mA
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)(3)
VOH
VDD–1.3
VDD–0.4
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(3)
VOL
IIO = +6 mA
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(2)(3)
VOH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
3. Based on characterization data, not tested in production.
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STM32F103x8, STM32F103xB
Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 36, respectively.
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 9.
(1)
Table 36. I/O AC characteristics
MODEx[1:0]
Symbol
Parameter
Conditions
Min Max Unit
bit value(1)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
2
MHz
ns
Output high to low
tf(IO)out
125(3)
10
level fall time
CL = 50 pF, VDD = 2 V to 3.6 V
Output low to high
tr(IO)out
125(3)
10
level rise time
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
MHz
ns
Output high to low
tf(IO)out
25(3)
01
level fall time
CL = 50 pF, VDD = 2 V to 3.6 V
Output low to high
tr(IO)out
25(3)
level rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V
Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
50
30
MHz
MHz
MHz
20
CL = 30 pF, VDD = 2.7 V to 3.6 V
Output high to low
level fall time
5(3)
8(3)
12(3)
5(3)
8(3)
12(3)
11
tf(IO)out
tr(IO)out
tEXTIpw
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
ns
Output low to high
level rise time
Pulse width of
external signals
detected by the EXTI
controller
-
10
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 24.
3. Guaranteed by design, not tested in production.
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Electrical characteristics
Figure 24. I/O AC characteristics definition
STM32F103x8, STM32F103xB
90%
10 %
50%
50%
90%
10%
t
EXTERNAL
OUTPUT
ON 50pF
t
r(IO)out
r(IO)out
T
Maximum frequency is achieved if (t + t ) 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 34).
PU
Unless otherwise specified, the parameters given in Table 37 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 9.
Table 37. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)
VIL(NRST)
NRST Input low level voltage
NRST Input high level voltage
–0.5
2
0.8
V
(1)
VIH(NRST)
Vhys(NRST)
RPU
VDD+0.5
NRST Schmitt trigger voltage
hysteresis
200
40
mV
Weak pull-up equivalent resistor(2)
VIN VSS
30
50
k
ns
ns
(1)
VF(NRST)
NRST Input filtered pulse
100
(1)
VNF(NRST)
NRST Input not filtered pulse
300
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
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STM32F103x8, STM32F103xB
Figure 25. Recommended NRST pin protection
Electrical characteristics
V
DD
External
reset circuit(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 µF
STM32F10xxx
ai14132c
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 37. Otherwise the reset will not be taken into account by the device.
5.3.14
TIM timer characteristics
The parameters given in Table 38 are guaranteed by design.
Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 38. TIMx characteristics
Symbol
Parameter
Conditions
Min
1
Max
Unit
tTIMxCLK
tres(TIM)
Timer resolution time
fTIMxCLK = 72 MHz
TIMxCLK = 72 MHz
13.9
0
ns
MHz
MHz
bit
fTIMxCLK/2
Timer external clock
frequency on CH1 to CH4
fEXT
f
0
36
16
ResTIM
Timer resolution
16-bit counter clock period
when internal clock is
selected
tTIMxCLK
1
65536
910
tCOUNTER
fTIMxCLK = 72 MHz
fTIMxCLK = 72 MHz
0.0139
µs
tTIMxCLK
s
65536 × 65536
59.6
tMAX_COUNT
Maximum possible count
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
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Electrical characteristics
STM32F103x8, STM32F103xB
5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 39 are derived from tests
performed under the ambient temperature, f
frequency and V supply voltage
PCLK1
DD
conditions summarized in Table 9.
2
I
The STM32F103xx performance line C interface meets the requirements of the standard
2
I C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V is disabled, but is still present.
DD
2
The I C characteristics are described in Table 39. Refer also to Section 5.3.12: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
Table 39. I C characteristics
Standard mode I2C(1)
Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
1.3
0.6
µs
250
0(3)
100
0(4)
SDA data hold time
900(3)
300
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
1000
300
20 + 0.1Cb
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
300
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
µs
Repeated Start condition
setup time
tsu(STO)
Stop condition setup time
s
s
Stop to Start condition time
(bus free)
tw(STO:STA)
Capacitive load for each bus
line
Cb
400
400
pF
Guaranteed by design, not tested in production.
1.
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
3.
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
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STM32F103x8, STM32F103xB
Electrical characteristics
2
Figure 26. I C bus AC waveforms and measurement circuit
V
V
DD
DD
STM32F103xx
SDA
4.7kΩ
4.7kΩ
100Ω
100Ω
2
I C bus
SCL
START REPEATED
START
START
t
su(STA)
SDA
t
t
t
r(SDA)
f(SDA)
su(SDA)
t
su(STA:STO)
STOP
t
t
t
w(SCKL)
h(SDA)
h(STA)
SCL
t
t
t
su(STO)
r(SCK)
t
f(SCK)
w(SCKH)
ai14149b
Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
1.
(1)(2)
Table 40. SCL frequency (f
= 36 MHz.,VDD = 3.3 V)
PCLK1
I2C_CCR value
fSCL (kHz)
RP = 4.7 k
400
300
200
100
50
0x801E
0x8028
0x803C
0x00B4
0x0168
0x0384
20
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
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Electrical characteristics
STM32F103x8, STM32F103xB
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under the ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 9.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
(1)
Table 41. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
%
SPI slave input clock
duty cycle
DuCy(SCK)
Slave mode
30
70
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4tPCLK
2tPCLK
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
50
60
(2)
(2)
Master mode
Slave mode
Master mode
Slave mode
5
5
5
4
tsu(MI)
tsu(SI)
(2)
(2)
th(MI)
Data input hold time
(2)
th(SI)
ns
Data output access
time
(2)(3)
ta(SO)
Slave mode, fPCLK = 20 MHz
Slave mode
0
2
3tPCLK
10
Data output disable
time
(2)(4)
tdis(SO)
(2)(1)
tv(SO)
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
25
5
(2)(1)
tv(MO)
(2)
th(SO)
Slave mode (after enable edge)
Data output hold time
15
2
(2)
th(MO)
Master mode (after enable edge)
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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STM32F103x8, STM32F103xB
Electrical characteristics
Figure 27. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 28. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
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Electrical characteristics
Figure 29. SPI timing diagram - master mode
STM32F103x8, STM32F103xB
(1)
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
t
BIT6 IN
LSB IN
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 42. USB startup time
Symbol
Parameter
Max
Unit
(1)
tSTARTUP
USB transceiver startup time
1
µs
1. Guaranteed by design, not tested in production.
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Electrical characteristics
Table 43. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1) Unit
Input levels
VDD
USB operating voltage(2)
3.0(3)
0.2
3.6
V
V
(4)
VDI
Differential input sensitivity
Differential common mode range
Single ended receiver threshold
I(USBDP, USBDM)
Includes VDI range
(4)
VCM
0.8
2.5
2.0
(4)
VSE
Output levels
1.3
VOL
VOH
Static output level low
Static output level high
RL of 1.5 k to 3.6 V(5)
0.3
3.6
V
(5)
RL of 15 k to VSS
2.8
1. All the voltages are measured from the local ground potential.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled
up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range.
3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. Guaranteed by design, not tested in production.
RL is the load connected on the USB drivers
5.
Figure 30. USB timings: definition of data signal rise and fall time
Crossover
points
Differential
data lines
V
CR S
V
SS
t
t
r
f
ai14137
Table 44.
Symbol
USB: Full-speed electrical characteristics(1)
Parameter
Conditions
Min
Max
Unit
Driver characteristics
tr
tf
Rise time(2)
Fall time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
5.3.16
CAN (controller area network) interface
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
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Electrical characteristics
STM32F103x8, STM32F103xB
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 9.
Note:
It is recommended to perform a calibration after each power-up.
Table 45. ADC characteristics
Symbol
Parameter
Power supply
Conditions
Min
Typ
Max
Unit
VDDA
VREF+
IVREF
fADC
2.4
2.4
3.6
VDDA
220(1)
14
V
V
Positive reference voltage
Current on the VREF input pin
ADC clock frequency
160(1)
µA
MHz
0.6
(2)
Sampling rate
0.05
1
MHz
fS
f
ADC = 14 MHz
823
17
kHz
(2)
External trigger frequency
fTRIG
1/fADC
0 (VSSA or VREF-
tied to ground)
(3)
Conversion voltage range
VREF+
V
VAIN
See Equation 1 and
Table 46 for details
(2)
RAIN
External input impedance
Sampling switch resistance
50
1
k
k
pF
(2)
RADC
Internal sample and hold
capacitor
(2)
8
CADC
f
ADC = 14 MHz
5.9
83
µs
1/fADC
µs
(2)
Calibration time
tCAL
fADC = 14 MHz
fADC = 14 MHz
0.214
3(4)
Injection trigger conversion
latency
(2)
tlat
1/fADC
µs
0.143
2(4)
Regular trigger conversion
latency
(2)
tlatr
1/fADC
µs
f
f
ADC = 14 MHz
ADC = 14 MHz
0.107
1.5
0
17.1
239.5
1
(2)
Sampling time
Power-up time
tS
1/fADC
µs
(2)
tSTAB
0
1
18
µs
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally
connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally
connected to VSSA), see Table 5 and Figure 6.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 45.
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STM32F103x8, STM32F103xB
Equation 1: R
Electrical characteristics
max formula:
AIN
TS
RAIN ------------------------------------------------------------- – RADC
fADC CADC ln2N + 2
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
(1)
Table 46.
R
max for f
= 14 MHz
AIN
ADC
Ts (cycles)
tS (µs)
RAIN max (k)
1.5
0.11
0.4
7.5
0.54
0.96
2.04
2.96
3.96
5.11
17.1
5.9
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Based on characterization, not tested in production.
(1) (2)
Table 47. ADC accuracy - limited test conditions
Symbol
Parameter
Test conditions
Typ
Max(3)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
1.3
1
2
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 3 V to 3.6 V
TA = 25 °C
1.5
1.5
1
Gain error
0.5
0.7
0.8
LSB
Differential linearity error
Integral linearity error
Measurements made after
ADC calibration
1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
3. Based on characterization, not tested in production.
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Electrical characteristics
STM32F103x8, STM32F103xB
(1) (2) (3)
Table 48. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
2
5
2.5
3
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 2.4 V to 3.6 V
1.5
1.5
1
Gain error
LSB
Measurements made after
ADC calibration
Differential linearity error
Integral linearity error
2
1.5
3
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
4. Based on characterization, not tested in production.
Figure 31. ADC accuracy characteristics
VREF+
VDDA
4096
[1LSBIDEAL
=
(or
depending on package)]
4096
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4095
4094
4093
(3) End point correlation line
(2)
ET=Total Unadjusted Error: maximum deviation
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
(1)
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
ED
1 LSBIDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
VSSA
ai14395b
70/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Figure 32. Typical connection diagram using the ADC
Electrical characteristics
V
DD
STM32F103xx
Sample and hold ADC
V
0.6 V
T
converter
(1)
(1)
AIN
R
R
ADC
AINx
12-bit
converter
I
1 µA
L
C
V
T
parasitic
V
AIN
0.6 V
(1)
C
ADC
ai14150c
1. Refer to Table 45 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 33 or Figure 34,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 33. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
STM32F103xx
V
REF+
(see note 1)
1 µF // 10 nF
V
DDA
SSA
1 µF // 10 nF
V
/V
REF–
(see note 1)
ai14388b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Doc ID 13587 Rev 11
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Electrical characteristics
STM32F103x8, STM32F103xB
Figure 34. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32F103xx
V
/V
REF+ DDA
(See note 1)
1 µF // 10 nF
V
/V
REF– SSA
(See note 1)
ai14389
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Temperature sensor characteristics
Table 49. TS characteristics
5.3.18
Symbol
Parameter
VSENSE linearity with temperature
Average slope
Min
Typ
Max
Unit
(1)
°C
mV/°C
V
1
4.3
2
4.6
TL
Avg_Slope(1)
4.0
(1)
Voltage at 25 °C
1.34
1.43
1.52
V25
(2)
Startup time
4
10
µs
µs
tSTART
ADC sampling time when reading the
temperature
(3)(2)
17.1
TS_temp
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
72/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Package characteristics
6
Package characteristics
6.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Doc ID 13587 Rev 11
73/92
Package characteristics
STM32F103x8, STM32F103xB
Figure 35. VFQFPN36 6 x 6 mm, 0.5 mm pitch,
Figure 36. Recommended footprint
(1)
(1)(2)(3)
package outline
(dimensions in mm)
Seating plane
C
ddd
C
1.00
4.30
A2
A
27
19
A1
A3
28
E2
18
b
0.50
4.10
27
19
18
4.30
28
4.10
4.80
4.80
e
D2
D
36
10
0.75
9
1
0.30
36
10
6.30
ai14870b
1
9
Pin # 1 ID
R = 0.20
L
E
ZR_ME
1. Drawing is not to scale.
2. The back-side pad is not internally connected to the VSS or VDD power pads.
3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should
also be soldered to the PCB. It is recommended to connect it to VSS
.
Table 50. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.800
0.900
0.020
0.650
0.250
0.230
6.000
3.700
6.000
3.700
0.500
0.550
0.080
1.000
0.050
1.000
0.0315
0.0354
0.0008
0.0256
0.0098
0.0091
0.2362
0.1457
0.2362
0.1457
0.0197
0.0217
0.0031
0.0394
0.0020
0.0394
A1
A2
A3
b
0.180
5.875
1.750
5.875
1.750
0.450
0.350
0.300
6.125
4.250
6.125
4.250
0.550
0.750
0.0071
0.2313
0.0689
0.2313
0.0689
0.0177
0.0138
0.0118
0.2411
0.1673
0.2411
0.1673
0.0217
0.0295
D
D2
E
E2
e
L
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
74/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Package characteristics
Figure 37. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline
1. Drawing is not to scale.
Table 51. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
1.700
0.0669
A1
A2
A3
A4
b
0.270
0.0106
1.085
0.30
0.0427
0.0118
0.80
0.55
0.0315
0.0217
0.3996
0.45
9.85
0.50
10.00
7.20
0.0177
0.3878
0.0197
0.3937
0.2835
0.3937
0.2835
0.0315
0.0551
D
10.15
D1
E
9.85
10.00
7.20
10.15
0.3878
0.3996
E1
e
0.80
F
1.40
ddd
eee
fff
0.12
0.15
0.08
0.0047
0.0059
0.0031
N (number of balls)
100
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 13587 Rev 11
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Package characteristics
STM32F103x8, STM32F103xB
Figure 38. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
Dpad
Dsm
0.37 mm
0.52 mm typ. (depends on solder
mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
76/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Package characteristics
(1)(2)
Figure 39. LQFP100, 14 x 14 mm 100-pin low-profile
Figure 40. Recommended footprint
(1)
quad flat package outline
0.25 mm
0.10 inch
GAGE PLANE
75
51
k
D
L
76
50
D1
0.5
L1
D3
51
75
C
0.3
76
50
16.7 14.3
b
E3 E1
E
100
26
1.2
1
25
100
26
12.3
16.7
Pin 1
1
25
ccc
C
identification
e
A1
ai14906
A2
A
SEATING PLANE
C
1L_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 52. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
0.063
A
A1
A2
b
1.6
0.15
1.45
0.27
0.2
0.05
1.35
0.17
0.09
15.8
13.8
0.002
0.0531
0.0067
0.0035
0.622
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
1.4
0.0551
0.0087
0.22
c
D
16
14
16.2
14.2
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
0.5433
12
15.8
13.8
16
16.2
14.2
0.622
0.6378
0.5591
E1
E3
e
14
0.5433
12
0.5
0.6
1
L
0.45
0.0°
0.75
7.0°
0.0177
0.0°
0.0295
7.0°
L1
k
3.5°
0.08
ccc
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 13587 Rev 11
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Package characteristics
STM32F103x8, STM32F103xB
Figure 42. Recommended
Figure 41. LQFP64, 10 x 10 mm, 64-pin low-profile quad
(1)
(1)(2)
flat package outline
footprint
A
A2
48
33
A1
0.3
49
32
0.5
b
E
E1
12.7
10.3
10.3
e
64
17
1.2
1
16
7.8
D1
D
c
12.7
L1
ai14909
L
ai14398b
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 53. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
0.0630
0.0059
0.0571
0.0106
0.0079
0.05
1.35
0.17
0.09
0.0020
0.0531
0.0067
0.0035
1.40
0.22
0.0551
0.0087
c
D
12.00
10.00
12.00
10.00
0.50
0.4724
0.3937
0.4724
0.3937
0.0197
3.5°
D1
E
E1
e
0°
3.5°
7°
0°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0394
0.0295
L1
1.00
Number of pins
64
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
78/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Package characteristics
Figure 43. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline
B
D
D1
A
A
e
F
A1
H
G
F
F
E
D
C
B
A
E1
E
e
1
2
3
4
5
6
7
8
Øb (64 balls)
A1 ball pad corner
A3
A4
A2
Seating
plane
C
Bottom view
ME_R8
1. Drawing is not to scale.
Table 54. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
1.200
0.0472
A1
A2
A3
A4
b
0.150
0.0059
0.785
0.200
0.0309
0.0079
0.600
0.350
5.150
0.0236
0.0138
0.2028
0.250
4.850
0.300
5.000
3.500
5.000
3.500
0.500
0.750
0.080
0.150
0.050
0.0098
0.1909
0.0118
0.1969
0.1378
0.1969
0.1378
0.0197
0.0295
0.0031
0.0059
0.0020
D
D1
E
4.850
5.150
0.1909
0.2028
E1
e
F
ddd
eee
fff
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 13587 Rev 11
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Package characteristics
STM32F103x8, STM32F103xB
Figure 44. Recommended PCB design rules for pads (0.5 mm pitch BGA)
0.5 mm
Pitch
D pad
0.27 mm
0.35 mm typ (depends on
the soldermask registration
tolerance)
Dsm
Solder paste
0.27 mm aperture diameter
Dpad
Dsm
ai15495
1. Non solder mask defined (NSMD) pads are recommended
2. 4 to 6 mils solder paste screen printing process
80/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Package characteristics
Figure 45. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat
Figure 46. Recommended
(1)
(1)(2)
package outline
footprint
Seating plane
C
A
A2
A1
c
b
0.50
1.20
0.25 mm
Gage plane
ccc
C
D
0.30
36
25
37
24
D1
D3
k
0.20
A1
L
7.30
9.70 5.80
25
36
L1
7.30
24
48
13
12
37
1
1.20
5.80
E3
E1
E
9.70
ai14911b
48
13
Pin 1
identification
1
12
5B_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 55. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
9.200
7.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
0.050
1.350
0.170
0.090
8.800
6.800
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
1.400
0.220
0.0551
0.0087
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0°
0.750
7°
0.0177
0°
0.0295
7°
L1
k
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 13587 Rev 11
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Package characteristics
STM32F103x8, STM32F103xB
6.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 9: General operating conditions on page 35.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × )
J
A
D
JA
Where:
●
●
●
●
T max is the maximum ambient temperature in C,
A
is the package junction-to-ambient thermal resistance, in C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = (V × I ) + ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 56. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LFBGA100 - 10 × 10 mm / 0.8 mm pitch
44
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
46
45
65
55
18
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
JA
°C/W
Thermal resistance junction-ambient
TFBGA64 - 5 × 5 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
VFQFPN 36 - 6 × 6 mm / 0.5 mm pitch
6.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
82/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Package characteristics
6.2.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 57: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Thus: P
= 447 mW
Dmax
Using the values obtained in Table 56 T
is calculated as follows:
Jmax
–
T
For LQFP100, 46 °C/W
= 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 57: Ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
= 115 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V= 70 mW
INTmax
= 20 × 8 mA × 0.4 V = 64 mW
IOmax
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
= 70 + 64 = 134 mW
Dmax
Thus: P
= 134 mW
Dmax
Doc ID 13587 Rev 11
83/92
Package characteristics
Using the values obtained in Table 56 T
STM32F103x8, STM32F103xB
is calculated as follows:
Jmax
–
T
For LQFP100, 46 °C/W
= 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C
Jmax
This is within the range of the suffix 7 version parts (–40 < T < 125 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 57: Ordering information scheme).
Figure 47. LQFP100 P max vs. T
D
A
700
600
500
400
300
200
100
0
Suffix 6
Suffix 7
65
75
85
95 105 115 125 135
TA (°C)
84/92
Doc ID 13587 Rev 11
STM32F103x8, STM32F103xB
Ordering information scheme
7
Ordering information scheme
Table 57. Ordering information scheme
Example:
STM32 F 103 C
8
T
7 xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
103 = performance line
Pin count
T = 36 pins
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size(1)
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
H = BGA
T = LQFP
U = VFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and real
1. Although STM32F103x6 devices are not described in this datasheet, orderable part numbers that do not
show the A internal code after temperature range code 6 or 7 should be referred to this datasheet for the
electrical characteristics. The low-density datasheet only covers STM32F103x6 devices that feature the
A code.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 13587 Rev 11
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Revision history
STM32F103x8, STM32F103xB
8
Revision history
Table 58. Document revision history
Date
Revision
Changes
01-jun-2007
1
Initial release.
Flash memory size modified in Note 8, Note 5, Note 7, Note 9 and
BGA100 pins added to Table 5: Medium-density STM32F103xx pin
definitions. Figure 3: STM32F103xx performance line LFBGA100
ballout added.
THSE changed to TLSE in Figure 21: Low-speed external clock source
AC timing diagram. VBAT ranged modified in Power supply schemes.
tSU(LSE) changed to tSU(HSE) in Table 22: HSE 4-16 MHz oscillator
characteristics. IDD(HSI) max value added to Table 24: HSI oscillator
characteristics.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static
latch-up. 25 °C and 85 °C conditions removed and class name modified
in Table 33: Electrical sensitivities. RPU and RPD min and max values
added to Table 34: I/O static characteristics. RPU min and max values
added to Table 37: NRST pin characteristics.
20-Jul-2007
2
Figure 26: I2C bus AC waveforms and measurement circuit and
Figure 25: Recommended NRST pin protection corrected.
Notes removed below Table 9, Table 37, Table 43.
IDD typical values changed in Table 11: Maximum current consumption
in Run and Sleep modes. Table 38: TIMx characteristics modified.
tSTAB, VREF+ value, tlat and fTRIG added to Table 45: ADC
characteristics.
In Table 29: Flash memory endurance and data retention, typical
endurance and data retention for TA = 85 °C added, data retention for
TA = 25 °C removed.
VBG changed to VREFINT in Table 12: Embedded internal reference
voltage. Document title changed. Controller area network (CAN)
section modified.
Figure 12: Power supply scheme modified.
Features on page 1 list optimized. Small text changes.
86/92
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STM32F103x8, STM32F103xB
Table 58. Document revision history (continued)
Revision history
Date
Revision
Changes
STM32F103CBT6, STM32F103T6 and STM32F103T8 root part
numbers added (see Table 2: STM32F103xx medium-density device
features and peripheral counts)
VFQFPN36 package added (see Section 6: Package characteristics).
All packages are ECOPACK® compliant. Package mechanical data
inch values are calculated from mm and rounded to 4 decimal digits
(see Section 6: Package characteristics).
Table 5: Medium-density STM32F103xx pin definitions updated and
clarified.
Table 26: Low-power mode wakeup timings updated.
TA min corrected in Table 12: Embedded internal reference voltage.
Note 2 added below Table 22: HSE 4-16 MHz oscillator characteristics.
VESD(CDM) value added to Table 32: ESD absolute maximum ratings.
Note 3 added and VOH parameter description modified in Table 35:
Output voltage characteristics.
Note 1 modified under Table 36: I/O AC characteristics.
Equation 1 and Table 46: RAIN max for fADC = 14 MHz added to
Section 5.3.17: 12-bit ADC characteristics.
VAIN, tS max, tCONV, VREF+ min and tlat max modified, notes modified
and tlatr added in Table 45: ADC characteristics.
Figure 31: ADC accuracy characteristics updated. Note 1 modified
below Figure 32: Typical connection diagram using the ADC.
Electrostatic discharge (ESD) on page 56 modified.
Number of TIM4 channels modified in Figure 1: STM32F103xx
performance line block diagram.
Maximum current consumption Table 13, Table 14 and Table 15
updated. Vhysmodified in Table 34: I/O static characteristics.
Table 48: ADC accuracy updated. tVDD modified in Table 10: Operating
conditions at power-up / power-down. VFESD value added in Table 30:
EMS characteristics.
18-Oct-2007
3
Values corrected, note 2 modified and note 3 removed in Table 26:
Low-power mode wakeup timings.
Table 16: Typical and maximum current consumptions in Stop and
Standby modes: Typical values added for VDD/VBAT = 2.4 V, Note 2
modified, Note 2 added.
Table 21: Typical current consumption in Standby mode added. On-chip
peripheral current consumption on page 47 added.
ACCHSI values updated in Table 24: HSI oscillator characteristics.
Vprog added to Table 28: Flash memory characteristics.
Upper option byte address modified in Figure 9: Memory map.
Typical fLSI value added in Table 25: LSI oscillator characteristics and
internal RC value corrected from 32 to 40 kHz in entire document.
TS_temp added to Table 49: TS characteristics. NEND modified in
Table 29: Flash memory endurance and data retention.
TS_vrefint added to Table 12: Embedded internal reference voltage.
Handling of unused pins specified in General input/output
characteristics on page 57. All I/Os are CMOS and TTL compliant.
Figure 33: Power supply and reference decoupling (VREF+ not
connected to VDDA) modified.
tJITTER and fVCO removed from Table 27: PLL characteristics.
Appendix A: Important notes on page 81 added.
Added Figure 14, Figure 15, Figure 17 and Figure 19.
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Revision history
Table 58. Document revision history (continued)
STM32F103x8, STM32F103xB
Date
Revision
Changes
Document status promoted from preliminary data to datasheet.
The STM32F103xx is USB certified. Small text changes.
Power supply schemes on page 13 modified. Number of
communication peripherals corrected for STM32F103Tx and number of
GPIOs corrected for LQFP package in Table 2: STM32F103xx medium-
density device features and peripheral counts.
Main function and default alternate function modified for PC14 and
PC15 in, Note 6 added and Remap column added in Table 5: Medium-
density STM32F103xx pin definitions.
VDD–VSS ratings and Note 1 modified in Table 6: Voltage
characteristics, Note 1 modified in Table 7: Current characteristics.
Note 1 and Note 2 added in Table 11: Embedded reset and power
control block characteristics.
IDD value at 72 MHz with peripherals enabled modified in Table 14:
Maximum current consumption in Run mode, code with data
processing running from RAM.
IDD value at 72 MHz with peripherals enabled modified in Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM on page 41.
IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum values
added in Table 16: Typical and maximum current consumptions in Stop
and Standby modes. Note added in Table 17 on page 45 and Table 18
on page 46. ADC1 and ADC2 consumption and notes modified in
Table 19: Peripheral current consumption.
tSU(HSE) and tSU(LSE) conditions modified in Table 22 and Table 23,
respectively.
22-Nov-2007
4
Maximum values removed from Table 26: Low-power mode wakeup
timings. tRET conditions modified in Table 29: Flash memory endurance
and data retention. Figure 12: Power supply scheme corrected.
Figure 18: Typical current consumption in Stop mode with regulator in
Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.
Note removed below Figure 27: SPI timing diagram - slave mode and
CPHA = 0. Note added below Figure 28: SPI timing diagram - slave
mode and CPHA = 1(1).
Details on unused pins removed from General input/output
characteristics on page 57.
Table 41: SPI characteristics updated. Table 42: USB startup time
added. VAIN, tlat and latr modified, note added and Ilkg removed in
t
Table 45: ADC characteristics. Test conditions modified and note added
in Table 48: ADC accuracy. Note added below Table 46 and Table 49.
Inch values corrected in Table 52: LQPF100, 14 x 14 mm 100-pin low-
profile quad flat package mechanical data, Table 53: LQFP64, 10 x 10
mm, 64-pin low-profile quad flat package mechanical data and
Table 55: LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package
mechanical data.
JAvalue for VFQFPN36 package added in Table 56: Package thermal
characteristics
Order codes replaced by Section 7: Ordering information scheme.
MCU ‘s operating conditions modified in Typical current consumption
on page 44. Avg_Slope and V25 modified in Table 49: TS
characteristics. I2C interface characteristics on page 62 modified.
Impedance size specified in A.4: Voltage glitch on ADC input 0 on
page 81.
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Table 58. Document revision history (continued)
Revision history
Date
Revision
Changes
Figure 2: Clock tree on page 20 added.
Maximum TJ value given in Table 8: Thermal characteristics on
page 35.
CRC feature added (see CRC (cyclic redundancy check) calculation
unit on page 9 and Figure 9: Memory map on page 31 for address).
IDD modified in Table 16: Typical and maximum current consumptions in
Stop and Standby modes.
ACCHSI modified in Table 24: HSI oscillator characteristics on page 52,
note 2 removed.
PD, TA and TJ added, tprog values modified and tprog description clarified
in Table 28: Flash memory characteristics on page 53.
tRET modified in Table 29: Flash memory endurance and data retention.
14-Mar-2008
5
VNF(NRST) unit corrected in Table 37: NRST pin characteristics on
page 60.
Table 41: SPI characteristics on page 64 modified.
IVREF added to Table 45: ADC characteristics on page 68.
Table 47: ADC accuracy - limited test conditions added. Table 48: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
characteristics on page 73).
Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36
footprints added (see Figure 40, Figure 42, Figure 46 and Figure 36).
Section 6.2: Thermal characteristics on page 82 modified,
Section 6.2.1 and Section 6.2.2 added.
Appendix A: Important notes on page 81 removed.
Small text changes. Figure 9: Memory map clarified.
In Table 29: Flash memory endurance and data retention:
– NEND tested over the whole temperature range
– cycling conditions specified for tRET
21-Mar-2008
6
– tRET min modified at TA = 55 °C
V25, Avg_Slope and TL modified in Table 49: TS characteristics.
CRC feature removed.
CRC feature added back. Small text changes. Section 1: Introduction
modified. Section 2.2: Full compatibility throughout the family added.
IDD at TA max = 105 °C added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes on page 42.
IDD_VBAT removed from Table 21: Typical current consumption in
Standby mode on page 47.
Values added to Table 40: SCL frequency (fPCLK1= 36 MHz.,VDD =
3.3 V) on page 63.
22-May-2008
7
Figure 27: SPI timing diagram - slave mode and CPHA = 0 on page 65
modified. Equation 1 corrected.
tRET at TA = 105 °C modified in Table 29: Flash memory endurance and
data retention on page 54.
VUSB added to Table 43: USB DC electrical characteristics on page 67.
Figure 47: LQFP100 PD max vs. TA on page 84 modified.
Axx option added to Table 57: Ordering information scheme on
page 85.
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Revision history
Table 58. Document revision history (continued)
STM32F103x8, STM32F103xB
Date
Revision
Changes
Power supply supervisor updated and VDDA added to Table 9: General
operating conditions.
Capacitance modified in Figure 12: Power supply scheme on page 33.
Table notes revised in Section 5: Electrical characteristics.
Table 16: Typical and maximum current consumptions in Stop and
Standby modes modified.
Data added to Table 16: Typical and maximum current consumptions in
Stop and Standby modes and Table 21: Typical current consumption in
Standby mode removed.
fHSE_ext modified in Table 20: High-speed external user clock
characteristics on page 48. fPLL_IN modified in Table 27: PLL
characteristics on page 53.
21-Jul-2008
8
Minimum SDA and SCL fall time value for Fast mode removed from
Table 39: I2C characteristics on page 62, note 1 modified.
th(NSS) modified in Table 41: SPI characteristics on page 64 and
Figure 27: SPI timing diagram - slave mode and CPHA = 0 on page 65.
CADC modified in Table 45: ADC characteristics on page 68 and
Figure 32: Typical connection diagram using the ADC modified.
Typical TS_temp value removed from Table 49: TS characteristics on
page 72.
LQFP48 package specifications updated (see Table 55 and Table 46),
Section 6: Package characteristics revised.
Axx option removed from Table 57: Ordering information scheme on
page 85.
Small text changes.
STM32F103x6 part numbers removed (see Table 57: Ordering
information scheme). Small text changes.
General-purpose timers (TIMx) and Advanced-control timer (TIM1) on
page 15 updated.
Notes updated in Table 5: Medium-density STM32F103xx pin
definitions on page 26.
Note 2 modified below Table 6: Voltage characteristics on page 34,
|VDDx| min and |VDDx| min removed.
22-Sep-2008
9
Measurement conditions specified in Section 5.3.5: Supply current
characteristics on page 38.
IDD in standby mode at 85 °C modified in Table 16: Typical and
maximum current consumptions in Stop and Standby modes on
page 42.
General input/output characteristics on page 57 modified.
fHCLK conditions modified in Table 30: EMS characteristics on page 55.
JA and pitch value modified for LFBGA100 package in Table 56:
Package thermal characteristics. Small text changes.
90/92
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STM32F103x8, STM32F103xB
Table 58. Document revision history (continued)
Revision history
Date
Revision
Changes
I/O information clarified on page 1.
Figure 3: STM32F103xx performance line LFBGA100 ballout modified.
Figure 9: Memory map modified. Table 4: Timer feature comparison
added.
PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column in Table 5: Medium-density STM32F103xx
pin definitions.
PD for LFBGA100 corrected in Table 9: General operating conditions.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
23-Apr-2009
10
Table 20: High-speed external user clock characteristics and Table 21:
Low-speed external user clock characteristics modified.
Figure 18 shows a typical curve (title modified). ACCHSI max values
modified in Table 24: HSI oscillator characteristics.
TFBGA64 package added (see Table 54 and Table 43). Small text
changes.
Note 5 updated and Note 4 added in Table 5: Medium-density
STM32F103xx pin definitions.
VRERINT and TCoeff added to Table 12: Embedded internal reference
voltage. IDD_VBAT value added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes. Figure 16: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
fHSE_ext min modified in Table 20: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator
characteristics and Table 23: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables. Table 24: HSI
oscillator characteristics modified. Conditions removed from Table 26:
Low-power mode wakeup timings.
22-Sep-2009
11
Note 1 modified below Figure 22: Typical application with an 8 MHz
crystal.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 54.
Jitter added to Table 27: PLL characteristics.
Table 41: SPI characteristics modified.
CADC and RAIN parameters modified in Table 45: ADC characteristics.
RAIN max values modified in Table 46: RAIN max for fADC = 14 MHz.
Figure 37: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array
package outline updated.
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STM32F103x8, STM32F103xB
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