STM32F103VD_技术文档

STM32F103xC STM32F103xD

STM32F103xE

Performance line, ARM-based 32-bit MCU with up to 512 KB Flash,

USB, CAN, 11 timers, 3 ADCs and 13 communication interfaces

Preliminary Data

Features

FBGA

■ Core: ARM 32-bit Cortex™-M3 CPU

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm,

LQFP144 20 × 20 mm

– 72 MHz maximum frequency,

LFBGA100 10 × 10 mm

LFBGA144 10 × 10 mm

1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

■ Up to 112 fast I/O ports

– Single-cycle multiplication and hardware

division

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors, all 5 V-tolerant

except for analog inputs

■ Memories

– 256-to-512 Kbytes of Flash memory

– up to 64 Kbytes of SRAM

– Flexible static memory controller with 4

Chip Select. Supports Compact Flash,

SRAM, PSRAM, NOR and NAND memories

■ Up to 11 timers

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 2 × 16-bit, 6-channel timers with PWM

output and dead-time generation

– 2 × watchdog timers (Independent and

Window)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

– LCD parallel interface, 8080/6800 modes

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

■ Up to 13 communication interfaces

2

– Up to 2 × I C interfaces (SMBus/PMBus)

– 4-to-16 MHz crystal oscillator

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

– 32 kHz oscillator for RTC with calibration

2

– Up to 3 SPIs (18 Mbit/s), 2 with I S

interface multiplexed

– CAN interface (2.0B Active)

– USB 2.0 full speed interface

– SDIO interface

■ Low power

– Sleep, Stop and Standby modes

– V

supply for RTC and backup registers

BAT

■ 3 × 12-bit, 1 µs A/D converters (up to 21

■ CRC calculation unit, 96-bit unique ID

channels)

®

■ ECOPACK packages

– Conversion range: 0 to 3.6 V

– Triple-sample and hold capability

– Temperature sensor

Table 1.

Device summary

Part number

Reference

■ 2-channel 12-bit D/A converter

STM32F103RC STM32F103VC

STM32F103ZC

STM32F103xC

STM32F103xD

STM32F103xE

■ DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

STM32F103RD STM32F103VD

STM32F103ZD

2

SDIO, I Ss, SPIs, I Cs and USARTs

■ Debug mode

STM32F103RE STM32F103ZE

STM32F103VE

– Serial wire debug (SWD) & JTAG interfaces

– Cortex-M3 Embedded Trace Macrocell™

May 2008

Rev 2

1/118

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

STM32F103xC, STM32F103xD, STM32F103xE

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3

4

5

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1

Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2

5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38

Embedded reset and power control block characteristics . . . . . . . . . . . 39

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 83

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STM32F103xC, STM32F103xD, STM32F103xE

Contents

5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.3.17 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.1

6.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

6.2.1

6.2.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 114

7

8

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

3/118

List of tables

STM32F103xC, STM32F103xD, STM32F103xE

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . . 9

STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Maximum current consumption in Run mode, code with data processing

Table 14.

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 43

Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 44

Typical current consumption in Run mode, code with data processing

Table 15.

Table 16.

Table 17.

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Typical current consumption in Sleep mode, code with data processing

Table 18.

code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

High-speed external (HSE) user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

LSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 58

Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 59

Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Asynchronous multiplexed SRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 68

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Switching characteristics for CF read and write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 81

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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STM32F103xC, STM32F103xD, STM32F103xE

List of tables

Table 45.

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

SCL frequency (f

= 36 MHz.,V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PCLK1

DD

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

2

I S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

R

max for f

= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

AIN

ADC

ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 107

LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . 108

LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . 110

LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . 111

LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 68.

Table 69.

5/118

List of figures

STM32F103xC, STM32F103xD, STM32F103xE

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram

. 19

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout. . 21

STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP100 pinout. . 22

STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP64 pinout. . . 23

STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout . . 24

STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout . . 25

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42

Figure 15. Current consumption in Stop mode with regulator in main mode versus

temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DD

Figure 16. Current consumption in Stop mode with regulator in low-power mode

versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DD

Figure 17. Current consumption in Standby mode versus temperature at different

V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DD

Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 20. Typical application with a 8-MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 22. Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 23. Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 24. Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 25. Asynchronous multiplexed SRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 26. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 27. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 29. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 30. PC-card controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 31. PC-card controller timing for common memory write access . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 32. PC-card controller timing for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 33. PC-card controller timing for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 34. PC-card controller timing for I/O space read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 35. PC-card controller timing for I/O space write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 36. NAND controller timing for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 37. NAND controller timing for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 38. NAND controller timing for common memory read access. . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 39. NAND controller timing for common memory write access. . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 40. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 41. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

2

Figure 42. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 43. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6/118

STM32F103xC, STM32F103xD, STM32F103xE

List of figures

(1)

Figure 44. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

(1)

Figure 45. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

2

(1)

Figure 46. I S slave timing diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

2

(1)

Figure 47. I S master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 48. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 49. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 50. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 51. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 52. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 53. Power supply and reference decoupling (V

Figure 54. Power supply and reference decoupling (V

not connected to V

). . . . . . . . . . . . . 102

). . . . . . . . . . . . . . . . 103

REF+

DDA

connected to V

REF+

DDA

Figure 55. LQFP144, 20 x 20 mm, 144-pin low-profile quad

flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

(1)

Figure 56. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 57. LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . 108

Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 109

Figure 59. LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 110

(1)

Figure 60. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 61. LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 111

(1)

Figure 62. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 64. LQFP100 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

D

A

7/118

Introduction

STM32F103xC, STM32F103xD, STM32F103xE

1

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F103xC, STM32F103xD and STM32F103xE High-density performance line

microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family,

please refer to Section 2.2: Full compatibility throughout the family.

The High-density STM32F103xx datasheet should be read in conjunction with the Medium-

and High-density STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

2

Description

The STM32F103xC, STM32F103xD and STM32F103xE performance line family

®

incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at a

72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and

SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals

connected to two APB buses. All devices offer three 12-bit ADCs, four general purpose 16-

bit timers plus two PWM timer, as well as standard and advanced communication interfaces:

2

up to two I Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN.

The STM32F103xx High-density performance line family operates in the −40 to +105 °C

temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving

mode allows the design of low-power applications.

The STM32F103xx High-density performance line family offers devices in 5 different

package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of

peripherals are included, the description below gives an overview of the complete range of

peripherals proposed in this family.

These features make the STM32F103xx High-density performance line microcontroller

family suitable for a wide range of applications:

●

Motor drive and application control

●

Medical and handheld equipment

PC peripherals gaming and GPS platforms

Industrial applications: PLC, inverters, printers, and scanners

Alarm systems, Video intercom, and HVAC

Figure 1 shows the general block diagram of the device family.

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STM32F103xC, STM32F103xD, STM32F103xE

Description

2.1

Device overview

Table 2.

STM32F103xC, STM32F103xD and STM32F103xE features and peripheral

counts

Peripherals

STM32F103Rx

STM32F103Vx

STM32F103Zx

Flash memory in Kbytes

SRAM in Kbytes

FSMC

256

48

384

No

512

256

48

384

512

256

48

384

Yes

512

64

Yes

4

General-

purpose

Timers

Advanced-

control

2

Basic

SPI(I²S)⁽¹⁾

I²C

2

3(2)

2

USART

USB

5

Comm

1

CAN

1

SDIO

1

GPIOs

51

80

112

12-bit ADC

3

Number of channels

16

21

12-bit DAC

1

2

Number of channels

CPU frequency

72 MHz

Operating voltage

2.0 to 3.6 V

Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9)

Junction temperature: –40 to + 125 °C (see Table 9)

Operating temperatures

Package

LQFP64

LQFP100⁽²⁾, BGA100

LQFP144, BGA144

1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the

I²S audio mode.

2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only

support a multiplexed NOR Flash memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-

bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not

available in this package.

9/118

Description

STM32F103xC, STM32F103xD, STM32F103xE

2.2

Full compatibility throughout the family

The STM32F103xx is a complete family whose members are fully pin-to-pin, software and

feature compatible. In the reference manual, the STM32F103x6, STM32F103x8 and

STM32F103xB are referred to as Medium-density devices, while the STM32F103xC,

STM32F103xD and STM32F103xE are referred to as High-density devices. High-density

devices are an extension of the Medium-density STM32F103x6/8/B/C devices specified in

the STM32F103xx datasheet.

High-density STM32F103xx devices feature higher Flash memory and RAM capacities, and

2

additional peripherals like SDIO, FSMC, I S and DAC, while remaining fully compatible with

the other members of the family.

The STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the

STM32F103x6/8/A/B/C devices, allowing the user to try different memory densities and

providing a greater degree of freedom during the development cycle.

Table 3.

STM32F103xx family

Memory size

Medium-density STM32F103xx devices

High-density STM32F103xx devices

Pinout

128 KB

32 KB Flash 64 KB Flash

Flash

256 KB

Flash

384 KB

Flash

512 KB

Flash

10 KB RAM

20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM

144

100

5 × USARTs

4 × 16-bit timers, 2 × basic timers

3 × SPIs, 2 × I²Ss, 2 × I2Cs

3 × USARTs

USB, CAN, 2 × PWM timers

3 × 16-bit timers

2 × SPIs, 2 × I²Cs, USB,

CAN, 1 × PWM timer

1 × ADC

2 × USARTs

2 × 16-bit timers

1 × SPI, 1 × I²C,

USB, CAN,

3 × ADCs, 1 × DAC, 1 × SDIO

64

FSMC (100- and 144-pin packages⁽¹⁾

)

48

36

1 × PWM timer

1 × ADC

1. Ports F and G are not available in devices delivered in 100-pin packages.

2.3

Overview

ARM^®Cortex^TM-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE

performance line family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

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STM32F103xC, STM32F103xD, STM32F103xE

Embedded Flash memory

Description

Up to 512 Kbytes of embedded Flash is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

Embedded SRAM

Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE

performance line family. It has four Chip Select outputs supporting the following modes:

RAM, PSRAM, NOR and NAND.

Functionality overview:

●

The three FSMC interrupt lines are ORed in order to be connected to the NVIC

Write FIFO

Code execution from external memory except for

The targeted frequency is SYSCLK/2, so external access is at 36 MHz when the

system is at 72 MHz and external access is at 24 MHz when the system is at 48 MHz

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high-

performance solutions using external controllers with dedicated acceleration.

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Description

STM32F103xC, STM32F103xD, STM32F103xE

Nested vectored interrupt controller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested

vectored interrupt controller able to handle up to 60 maskable interrupt channels (not

including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and

the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed

APB domain is 36 MHz. See Figure 2 for details on the clock tree.

Boot modes

At startup, boot pins are used to select one of three boot options:

●

Boot from User Flash

Boot from System Memory

Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1.

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STM32F103xC, STM32F103xD, STM32F103xE

Power supply schemes

Description

●

V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

DD

Provided externally through V pins.

DD

●

V

, V

= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs

DDA

SSA

and PLL (minimum voltage to be applied to V

is 2.4 V when the ADC is used). V

DDA

and V

must be connected to V and V , respectively.

SSA

DD SS

●

V

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

BAT

registers (through power switch) when V is not present.

DD

For more details on how to connect power pins, refer to Figure 11: Power supply scheme.

Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V is below a specified threshold, V

, without the need for an

DD

POR/PDR

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

power supply and compares it to the V threshold. An interrupt can be generated

V

DD

PVD

when V drops below the V

and/or when V is higher than the V

threshold. The

DD

PVD

DD

PVD

interrupt service routine can then generate a warning message and/or put the MCU into a

safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power

control block characteristics for the values of V

and V

.

POR/PDR

PVD

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●

MR is used in the nominal regulation mode (Run)

LPR is used in the Stop modes.

Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

Low-power modes

The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three

low-power modes to achieve the best compromise between low power consumption, short

startup time and available wakeup sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

●

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

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Description

STM32F103xC, STM32F103xD, STM32F103xE

●

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers. The two DMA controllers support circular buffer management,

removing the need for user code intervention when the controller reaches the end of the

buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

2

The DMA can be used with the main peripherals: SPI, I C, USART, general-purpose, basic

2

and advanced control timers TIMx, DAC, I S, SDIO and ADC.

RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

V

supply when present or through the V

pin. The backup registers are forty-two 16-bit

DD

BAT

registers used to store 84 bytes of user application data. They are not reset by a system or

power reset, and they are not reset when the device wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural quartz deviation. The RTC features

a 32-bit programmable counter for long term measurement using the Compare register to

generate an alarm. A 20-bit prescaler is used for the time base clock and is by default

configured to generate a time base of 1 second from a clock at 32.768 kHz.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

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STM32F103xC, STM32F103xD, STM32F103xE

Window watchdog

Description

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

●

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0.

Programmable clock source

General-purpose timers (TIMx)

There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded

in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These

timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4

independent channels each for input capture/output compare, PWM or one pulse mode

output. This gives up to 16 input captures / output compares / PWMs on the largest

packages. They can work together with the Advanced Control timer via the Timer Link

feature for synchronization or event chaining.

The counter can be frozen in debug mode.

Any of the standard timers can be used to generate PWM outputs. Each of the timers has

independent DMA request generations.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a

generic 16-bit time base.

Advanced control timers (TIM1 and TIM8)

The two advanced control timers (TIM1 and TIM8) can each be seen as a three-phase PWM

multiplexed on 6 channels. They can also be seen as a complete general-purpose timer.

The 4 independent channels can be used for

●

Input Capture

Output Compare

PWM generation (edge or center-aligned modes)

One-pulse mode output

Complementary PWM outputs with programmable inserted dead-times.

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same

architecture. The advanced control timer can therefore work together with the TIM timers via

the Timer Link feature for synchronization or event chaining.

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Description

STM32F103xC, STM32F103xD, STM32F103xE

I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support

standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A

hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three

universal synchronous/asynchronous receiver transmitters (USART1, USART2 and

USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other

available interfaces communicate at up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS

signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All

interfaces can be served by the DMA controller except for UART5.

Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in

full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

Inter-integrated sound (I²S)

2

Two standard I S interfaces (multiplexed with SPI2 and SPI3) are available, that can be

operated in master or slave mode. These interfaces can be configured to operate with 16/32

bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to

2

48 kHz are supported. When either or both of the I S interfaces is/are configured in master

mode, the master clock can be output to the external DAC/CODEC at 256 times the

sampling frequency.

SDIO

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD

Memory Card Specifications Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack

of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital

protocol Rev1.1.

16/118

STM32F103xC, STM32F103xD, STM32F103xE

Controller area network (CAN)

Description

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It

can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

Universal serial bus (USB)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB

device peripheral compatible with the USB full-speed 12 Mbs. The USB interface

implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint

setting and suspend/resume support. The dedicated 48 MHz clock is generated from the

internal main PLL (the clock source must use a HSE crystal oscillator).

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

ADC (analog to digital converter)

Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD

and STM32F103xE performance line devices and each ADC shares up to 21 external

channels, performing conversions in single-shot or scan modes. In scan mode, automatic

conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

●

Simultaneous sample and hold

Interleaved sample and hold

Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the standard timers (TIMx) and the advanced-control timers (TIM1

and TIM8) can be internally connected to the ADC start trigger and injection trigger,

respectively, to allow the application to synchronize A/D conversion and timers.

17/118

Description

STM32F103xC, STM32F103xD, STM32F103xE

DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two

analog voltage signal outputs. The chosen design structure is composed of integrated

resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

●

two DAC converters: one for each output channel

8-bit or 12-bit monotonic output

left or right data alignment in 12-bit mode

synchronized update capability

noise-wave generation

triangular-wave generation

dual DAC channel independent or simultaneous conversions

DMA capability for each channel

external triggers for conversion

input voltage reference V

REF+

Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and

STM32F103xE performance line family. The DAC channels are triggered through the timer

update outputs that are also connected to different DMA channels.

Temperature sensor

The temperature sensor has to generate a linear voltage with any variation in temperature.

The conversion range is between 2 V < V

< 3.6 V. The temperature sensor is internally

DDA

connected to the ADC1_IN16 input channel which is used to convert the sensor output

voltage into a digital value.

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a

specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

Embedded Trace Macrocell™

®

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and

data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F10xxx through a small number of ETM pins to an external hardware trace port

analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or

any other high-speed channel. Real-time instruction and data flow activity can be recorded

and then formatted for display on the host computer running debugger software. TPA

hardware is commercially available from common development tool vendors. It operates

with third party debugger software tools.

18/118

STM32F103xC, STM32F103xD, STM32F103xE

Description

Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram

TRACECLK

TRACED[0:3]

as AS

@V

DD

TPIU

Trace/trig

Trace

controller

Power

Pbus

Ibus

V

SW/JTAG

DD

JNTRST

JTDI

JTCK/SWCLK

JTMS/SWDIO

JTDO

Volt. reg.

3.3 V to 1.8 V

V

SS

Flash 512 Kbytes

64 bit

Cortex-M3 CPU

@V

Supply

DDA

Dbus

System

as AF

F

: 48/72 MHz

NVIC

max

NRST

supervision

POR

Reset

V

POR /PDR

DDA

SSA

SRAM

64 KB

@V

DDA

PVD

Int

RC 8 MHz

RC 40 kHz

PLL

GP DMA1

@V

DD

XTAL OSC

4-16 MHz

A[25:0]

D[15:0]

CLK

NOE

NWE

OSC_IN

OSC_OUT

7 channels

GP DMA2

IWDG

5 channels

PCLK1

PCLK2

HCLK

FCLK

Reset &

Clock

control

Standby

interface

NE[4:1]

NBL[1:0]

NWAIT

NL (or NADV)

as AF

V

=1.8 V to 3.6 V

BAT

V

@

FSMC

SDIO

BAT

OSC32_IN

OSC32_OUT

XTAL32kHz

Backup

TAMPER-RTC/

ALARM/SECOND OUT

RTC

AWU

reg

D[7:0]

CMD

CK as AF

Backup interface

AHB2

APB2

AHB2

APB1

4 channels, ETR as AF

4 channels as AF

TIM2

EXT.IT

WKUP

112AF

PA[15:0]

PB[15:0]

TIM3

TIM4

GPIO port A

GPIO port B

GPIO port C

TIM5

RX, TX, CTS, RTS,

CK as AF

PC[15:0]

PD[15:0]

USART2

USART3

UART4

UART5

RX, TX, CTS,RTS,

CK as AF

GPIO port D

GPIO port E

PE[15:0]

PF[15:0]

PG[15:0]

RX,TXasAF

GPIO port F

GPIO port G

RX,TX asAF

MOSI/SD, MISO

SCK/CK, MCK, NSS/WS as AF

SPI2/ I2S2

2x(8xi1t)6b

4 channels

4 compl. channels

BKIN as AF

4 channels

4 compl. channels

BKIN as AF

TIM1

TIM8

MOSI/SD, MISO

SCK/CK, MCK, NSS/WS as AF

SPI3 / I2S3

2x(8xi1t)6b

I2C1

I2C2

SCL, SDA, SMBAL as AF

MOSI, MISO,

SCK, NSS as AF

SPI1

SRAM 512 B

bxCAN device

RX, TX, CTS,

RTS, CK as AF

USART1

WWDG

USBDP/CANTX

USBDM/CANRX

USB 2.0 FS

device

Temp. sensor

DAC_OUT1 as AF

DAC_OUT2 as AF

V_REF+

12bit DAC

IF

TIM6

TIM7

8 ADC123_INs

12-bit ADC1 IF

12-bit ADC2 IF

12-bit ADC3 IF

common to the 3 ADCs

@V

DDA

8 ADC12_INs common

to ADC1 & ADC2

5 ADC3_INs on ADC3

V_REF–

V_REF+

@ V

DDA

ai14666

1. T_A= –40 °C to +85 °C (suffix 6, see Table 69) or –40 °C to +105 °C (suffix 7, see Table 69), junction temperature up to

105 °C or 125 °C, respectively.

2. AF = alternate function on I/O port pin.

19/118

Description

STM32F103xC, STM32F103xD, STM32F103xE

Figure 2.

Clock tree

USBCLK

to USB interface

USB

Prescaler

/1, 1.5

48 MHz

I2S3CLK

to I2S3

Peripheral clock

enable

I2S2CLK

to I2S2

Peripheral clock

enable

SDIOCLK

to SDIO

to FSMC

8 MHz

Peripheral clock

HSI

HSI RC

enable

FSMCCLK

Peripheral clock

enable

/2

HCLK

to AHB bus, core,

memory and DMA

72 MHz max

Clock

Enable (4 bits)

/8

to Cortex System timer

SW

PLLSRC

FCLK Cortex

free running clock

36 MHz max

PLLMUL

HSI

AHB

APB1

SYSCLK

..., x16

x2, x3, x4

PLL

PCLK1

Prescaler

PLLCLK

HSE

72 MHz

max

to APB1

/1, 2..512

/1, 2, 4, 8, 16

peripherals

Peripheral Clock

Enable (20 bits)

TIM2,3,4,5,6,7

If (APB1 prescaler =1) x1

else x2

to TIM2,3,4,5,6 and 7

TIMXCLK

CSS

Peripheral Clock

Enable (6 bits)

APB2

Prescaler

/1, 2, 4, 8, 16

PLLXTPRE

/2

72 MHz max

PCLK2

OSC_OUT

OSC_IN

peripherals to APB2

4-16 MHz

HSE OSC

Peripheral Clock

Enable (15 bits)

TIM1 & 8 timers

If (APB2 prescaler =1) x1

else x2

to TIM1 and TIM8

TIMxCLK

Peripheral Clock

Enable (2 bit)

to ADC1, 2 or 3

/128

LSE

ADC

Prescaler

/2, 4, 6, 8

OSC32_IN

to RTC

LSE OSC

ADCCLK

RTCCLK

32.768 kHz

OSC32_OUT

HCLK/2

/2

RTCSEL[1:0]

To SDIO AHB interface

Peripheral clock

enable

to Independent Watchdog (IWDG)

IWDGCLK

LSI

LSI RC

40 kHz

Legend:

Main

Clock Output

/2

PLLCLK

HSE = High Speed External clock signal

HSI = High Speed Internal clock signal

MCO

HSI

HSE

LSI = Low Speed Internal clock signal

LSE = Low Speed External clock signal

SYSCLK

MCO

ai14752b

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is

64 MHz.

2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either

48 MHz or 72 MHz.

3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.

20/118

STM32F103xC, STM32F103xD, STM32F103xE

Pin descriptions

3

Pin descriptions

Figure 3.

STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout

PE2

PE3

PE4

PE5

PE6

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

V

NC

DD_2

SS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

9

PF0

PF1

PF2

PF3

PF4

PF5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

V

DD_9

SS_9

V

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

SS_5

LQFP144

DD_5

PF6

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

V

DD_8

SS_8

PC1

PC2

PC3

PD13

PD12

PD11

PD10

PD9

V

SSA

REF-

PD8

REF+

PB15

PB14

PB13

PB12

DDA

PA0-WKUP

PA1

PA2

ai14667

21/118

Pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Figure 4.

STM32F103xC, STM32F103xD and STM32F103xE performance line

LQFP100 pinout

PE2

PE3

PE4

PE5

PE6

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD_2

VSS_2

NC

PA 13

PA 12

PA 11

PA 10

PA 9

PA 8

PC9

PC8

PC7

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VDD_5

OSC_IN

OSC_OUT

NRST

LQFP100

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PD8

PB15

PB14

PB13

PB12

PA0-WKUP

PA1

PA2

ai14391

22/118

STM32F103xC, STM32F103xD, STM32F103xE

Pin descriptions

Figure 5. STM32F103xC, STM32F103xD and STM32F103xE performance line

LQFP64 pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

V_{DD_2}

V_{SS_2}

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

V_BAT

1

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

4

5

6

7

PC0

PC1

PC2

PC3

V_SSA

V_DDA

8

LQFP64

9

10

11

12

13

14

15

16

PC6

PB15

PB14

PB13

PB12

PA0-WKUP

PA1

PA2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

ai14392

23/118

Pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Figure 6. STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout

1

2

3

4

5

6

7

8

9

10

PC14-

OSC32_IN

PC13-

TAMPER-RTC

A

B

C

D

E

F

PE2

PE3

PE4

PE5

PE6

PC3

PA4

PA5

PA6

PA7

PB9

PB8

PE1

PE0

PB7

PB4

PD5

PD6

PD7

PB3

PD2

PD3

PD4

PA15

PC11

PC12

PD0

PA14

PC10

PA9

APA13

PA12

PA11

PA10

PC7

PC15-

OSC32_OUT

V

PB6

BAT

OSC_IN

OSC_OUT

NRST

V

PB5

SS_5

BOOT0

PA8

DD_5

V

PD1

PCD

PC9

PC8

PD11

PD10

PD9

PD8

SS_4

SS_3

SS_2

SS_1

V

NC

PC0

PC1

PA0-WKUP

PA1

PC6

DD_4

DD_3

DD_2

DD_1

G

H

J

V

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

PB15

PB14

PC4

PD15

PD14

PD13

PD12

SSA

V

PC5

PB0

PB1

REF–

V

PA2

PB13

PB12

REF+

K

V

PA3

DDA

AI16001

24/118

STM32F103xC, STM32F103xD, STM32F103xE

Pin descriptions

Figure 7. STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout

1

2

3

4

5

6

7

8

9

10

11

12

PB4

JTRST

PC13-

TAMPER-RTC

PB3

JTDO

PA15

JTDI

PA14

JTCK

PA13

JTMS

PE3

PE2

PE1

PE0

PD6

PD7

A

B

C

D

E

F

PC14-

OSC32_IN

PE4

PE5

PF0

PE6

PF1

PF2

PF5

PB9

PB8

PB5

PB6

PB7

PG15

PG14

PG13

PG12

PG11

PG10

PG9

PD5

PD4

PD3

PD2

PC11

PC12

PD1

PC10

NC

PA12

PA11

PA9

PA8

PC7

PC6

PG5

PC15-

OSC32_OUT

V

BAT

OSC_IN

V

BOOT0

PA10

PC9

PC8

PG8

PG6

SS_5

DD_5

PF4

OSC_OUT

V

PF3

PD0

SS_3

SS_11

SS_10

V

DD_8

NRST

PF10

PC0

PF7

PF9

PF6

PF8

PC2

PA4

PA5

PA6

PA7

V

DD_9

DD_4

DD_3

DD_11

DD_10

DD_2

G

H

J

V

DD_6

DD_7

DD_1

SS_8

SS_4

SS_2

SS_9

V

PE11

PD11

PG7

PC1

PC3

SS_6

SS_7

PG1

SS_1

PE10

PE9

PB2/

BOOT1

V

PA0-WKUP

PA1

PC4

PC5

PB0

PB1

PE12

PE13

PE14

PE15

PD10

PD9

PG4

PD13

PD12

PB11

PG3

PD14

PB14

PB12

PG2

PD15

PB15

PB13

SSA

K

L

V

PF13

PF12

PF11

PG0

REF–

PA2

PF15

PF14

PE8

PD8

REF+

V

PA3

PE7

M

PB10

DDA

AI14789b

25/118

Pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Table 4.

Pin definitions

Pins

Alternate functions

Main

Pin name

function⁽³⁾

Default

Remap

(after reset)

FT

A3 A3

A2 B3

B2 C3

B3 D3

B4 E3

C2 B2

-

1

2

3

4

5

6

1

2

3

4

5

6

PE2

PE3

PE4

PE5

PE6

V_BAT

I/O

S

PE2

PE3

PE4

PE5

PE6

V_BAT

TRACECK/ FSMC_A23

TRACED0/FSMC_A19

TRACED1/FSMC_A20

TRACED2/FSMC_A21

TRACED3/FSMC_A22

-

1

PC13-TAMPER-

RTC⁽⁴⁾

A1 A2

B1 A1

C1 B1

2

3

4

7

8

9

7

8

9

I/O

PC13⁽⁵⁾

PC14⁽⁵⁾

PC15⁽⁵⁾

TAMPER-RTC

OSC32_IN

PC14-OSC32_IN⁽⁴⁾I/O

PC15-

I/O

OSC32_OUT

OSC32_OUT⁽⁴⁾

C3

C4

D4

E2

E3

E4

-

10

11

12

13

14

15

PF0

PF1

I/O FT

S

PF0

PF1

FSMC_A0

FSMC_A1

FSMC_A2

FSMC_A3

FSMC_A4

FSMC_A5

PF2

PF3

PF4

PF5

D2 C2

D3 D2

10 16

11 17

V_{SS_5}

V_{DD_5}

V_{SS_5}

V_{DD_5}

S

ADC3_IN4/

FSMC_NIORD

F3

F2

-

18

19

20

21

22

PF6

PF7

PF8

PF9

PF10

I/O

PF6

PF7

PF8

PF9

PF10

ADC3_IN5/

FSMC_NREG

ADC3_IN6/

FSMC_NIOWR

G3

G2

G1

ADC3_IN7/

FSMC_CD

ADC3_IN8/

FSMC_INTR

D1 C1

E1 D1

F1 E1

H1 F1

H2 F2

5

6

7

8

9

12 23

13 24

14 25

15 26

16 27

OSC_IN

OSC_OUT

NRST

PC0

I

OSC_IN

OSC_OUT

NRST

PC0

O

I/O

ADC123_IN10

ADC123_IN11

ADC123_IN12

PC1

H3 E2 10 17 28

PC2

26/118

STM32F103xC, STM32F103xD, STM32F103xE

Pin descriptions

Table 4.

Pin definitions (continued)

Pins

Alternate functions

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

H4 F3 11 18 29

J1 G1 12 19 30

PC3

V_SSA

V_REF-

V_REF+

V_DDA

I/O

S

PC3

V_SSA

V_REF-

V_REF+

V_DDA

ADC123_IN13

K1 H1

L1 J1

-

20 31

21 32

S

M1 K1 13 22 33

S

WKUP/USART2_CTS⁽⁶⁾

ADC123_IN0

J2 G2 14 23 34

PA0-WKUP

I/O

PA0

TIM2_CH1_ETR

TIM5_CH1/TIM8_ETR

USART2_RTS⁽⁶⁾

ADC123_IN1/TIM5_CH2

TIM2_CH2⁽⁶⁾

K2 H2 15 24 35

L2 J2 16 25 36

M2 K2 17 26 37

PA1

PA2

PA3

I/O

PA1

PA2

PA3

USART2_TX⁽⁶⁾

/

TIM5_CH3/ADC123_IN2/

TIM2_CH3 ⁽⁶⁾

USART2_RX⁽⁶⁾

/

TIM5_CH4/ADC123_IN3

TIM2_CH4⁽⁶⁾

G4 E4 18 27 38

F4 F4 19 28 39

V_{SS_4}

V_{DD_4}

S

V_{SS_4}

V_{DD_4}

SPI1_NSS⁽⁶⁾/DAC_OUT1

USART2_CK⁽⁶⁾

J3 G3 20 29 40

K3 H3 21 30 41

L3 J3 22 31 42

PA4

PA5

PA6

I/O

PA4

PA5

PA6

ADC12_IN4

SPI1_SCK⁽⁶⁾

DAC_OUT2 ADC12_IN5

SPI1_MISO⁽⁶⁾

TIM8_BKIN/ADC12_IN6

TIM3_CH1⁽⁶⁾

TIM1_BKIN

TIM1_CH1N

SPI1_MOSI⁽⁶⁾

TIM8_CH1N/ADC12_IN7

TIM3_CH2⁽⁶⁾

M3 K3 23 32 43

PA7

I/O

PA7

J4 G4 24 33 44

K4 H4 25 34 45

PC4

PC5

I/O

PC4

PC5

ADC12_IN14

ADC12_IN15

ADC12_IN8/TIM3_CH3

TIM8_CH2N

L4 J4 26 35 46

PB0

I/O

PB0

PB1

TIM1_CH2N

TIM1_CH3N

ADC12_IN9

TIM3_CH4⁽⁶⁾

TIM8_CH3N

M4 K4 27 36 47

J5 G5 28 37 48

PB1

PB2/BOOT1

I/O FT PB2/BOOT1

27/118

Pin descriptions

Table 4. Pin definitions (continued)

STM32F103xC, STM32F103xD, STM32F103xE

Pins

Alternate functions

Main

Pin name

function⁽³⁾

Default

Remap

(after reset)

M5

L5

-

49

50

51

52

53

54

55

56

57

PF11

PF12

V_{SS_6}

V_{DD_6}

PF13

PF14

PF15

PG0

I/O

FSMC_NIOS16

FSMC_A6

I/O

H5

G5

K5

M6

L6

S

I/O

FSMC_A7

FSMC_A8

FSMC_A9

FSMC_A10

FSMC_A11

FSMC_D4

FSMC_D5

FSMC_D6

I/O

K6

J6

I/O

PG1

I/O

M7 H5

L7 J5

K7 K5

38 58

39 59

40 60

PE7

I/O FT

S

PE7

PE8

PE9

TIM1_ETR

TIM1_CH1N

TIM1_CH1

PE8

PE9

H6

G6

-

61

62

V_{SS_7}

V_{DD_7}

PE10

PE11

PE12

PE13

PE14

PE15

S

J7 G6

H8 H6

J8 J6

K8 K6

L8 G7

M8 H7

41 63

42 64

43 65

44 66

45 67

46 68

I/O FT

PE10

PE11

PE12

PE13

PE14

PE15

FSMC_D7

FSMC_D8

FSMC_D9

FSMC_D10

FSMC_D11

FSMC_D12

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

I2C2_SCL

M9 J7 29 47 69

M10 K7 30 48 70

PB10

PB11

I/O FT

PB10

PB11

TIM2_CH3

TIM2_CH4

USART3_TX⁽⁶⁾

I2C2_SDA

USART3_RX⁽⁶⁾

H7 E7 31 49 71

G7 F7 32 50 72

V_{SS_1}

V_{DD_1}

S

V_{SS_1}

V_{DD_1}

SPI2_NSS/I2S2_WS/

I2C2_SMBAl/

M11 K8 33 51 73

PB12

I/O FT

PB12

USART3_CK⁽⁶⁾

TIM1_BKIN⁽⁶⁾

/

SPI2_SCK/I2S2_CK

M12 J8 34 52 74

L11 H8 35 53 75

PB13

PB14

I/O FT

PB13

PB14

USART3_CTS⁽⁶⁾

TIM1_CH1N

/

SPI2_MISO/TIM1_CH2N

USART3_RTS⁽⁶⁾

28/118

STM32F103xC, STM32F103xD, STM32F103xE

Pin descriptions

Table 4.

Pin definitions (continued)

Pins

Alternate functions

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

SPI2_MOSI/I2S2_SD

TIM1_CH3N⁽⁶⁾

L12 G8 36 54 76

PB15

I/O FT

PB15

L9 K9

K9 J9

J9 H9

H9 G9

-

55 77

56 78

57 79

58 80

PD8

PD9

I/O FT

PD8

PD9

FSMC_D13

FSMC_D14

FSMC_D15

FSMC_A16

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

PD10

PD11

PD10

PD11

TIM4_CH1 /

USART3_RTS

L10 K10

K10 J10

-

59 81

60 82

PD12

I/O FT

PD12

PD13

FSMC_A17

FSMC_A18

-

PD13

V_{SS_8}

V_{DD_8}

PD14

PD15

PG2

I/O FT

S

TIM4_CH2

G8

F8

-

83

84

S

K11 H10

K12 G10

61 85

62 86

I/O FT

S

PD14

PD15

FSMC_D0

FSMC_D1

TIM4_CH3

TIM4_CH4

J12

J11

-

87

88

89

90

91

92

93

94

95

FSMC_A12

FSMC_A13

FSMC_A14

FSMC_A15

FSMC_INT2

FSMC_INT3

PG3

J10

PG4

H12

H11

H10

G11

G10

F10

PG5

PG6

PG7

PG8

V_{SS_9}

V_{DD_9}

S

I2S2_MCK/

TIM8_CH1/SDIO_D6

G12 F10 37 63 96

F12 E10 38 64 97

PC6

PC7

I/O FT

PC6

PC7

TIM3_CH1

TIM3_CH2

I2S3_MCK/

TIM8_CH2/SDIO_D7

F11 F9 39 65 98

E11 E9 40 66 99

PC8

PC9

I/O FT

PC8

PC9

TIM8_CH3/SDIO_D0

TIM8_CH4/SDIO_D1

TIM3_CH3

TIM3_CH4

USART1_CK/

E12 D9 41 67 100

D12 C9 42 68 101

D11 D10 43 69 102

PA8

PA9

I/O FT

PA8

PA9

TIM1_CH1⁽⁶⁾/MCO

USART1_TX⁽⁶⁾

TIM1_CH2⁽⁶⁾

/

USART1_RX⁽⁶⁾

TIM1_CH3⁽⁶⁾

/

PA10

29/118

Pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Table 4.

Pin definitions (continued)

Pins

Alternate functions

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

USART1_CTS/CANRX

TIM1_CH4⁽⁶⁾/USBDM

C12 C10 44 70 103

B12 B10 45 71 104

PA11

PA12

I/O FT

PA11

PA12

USART1_RTS/USBDP/

CANTX⁽⁶⁾/TIM1_ETR⁽⁶⁾

A12 A10 46 72 105 PA13/JTMS-SWDIO I/O FT JTMS-SWDIO

C11 F8 73 106 Not connected

PA13

-

G9 E6 47 74 107

F9 F6 48 75 108

V

S

V

SS_2

DD_2

SS_2

DD_2

V

A11 A9 49 76 109 PA14/JTCK-SWCLK I/O FT JTCK-SWCLK

PA14

PA15/SPI3_NSS/

I2S3_WS

TIM2_CH1_ETR

SPI1_NSS

A10 A8 50 77 110

PA15/JTDI

I/O FT

JTDI

B11 B9 51 78 111

B10 B8 52 79 112

C10 C8 53 80 113

PC10

PC11

PC12

PD0

I/O FT

PC10

PC11

PC12

UART4_TX/SDIO_D2

UART4_RX/SDIO_D3

UART5_TX/SDIO_CK

FSMC_D2

USART3_TX

USART3_RX

USART3_CK

CANRX

(7)

E10 D8

D10 E8

5

6

81 114

82 115

I/O FT OSC_IN

(7)

PD1

I/O FT OSC_OUT

FSMC_D3

CANTX

TIM3_ETR/UART5_RX

SDIO_CMD

E9 B7 54 83 116

PD2

I/O FT

PD2

D9 C7

C9 D7

B9 B6

-

84 117

85 118

86 119

PD3

PD4

PD5

I/O FT

S

PD3

PD4

PD5

FSMC_CLK

FSMC_NOE

FSMC_NWE

USART2_CTS

USART2_RTS

USART2_TX

E7

F7

-

120

121

V

SS_10

DD_10

V

S

A8 C6

A9 D6

87 122

88 123

PD6

PD7

I/O FT

PD6

PD7

FSMC_NWAIT

USART2_RX

USART2_CK

FSMC_NE1/

FSMC_NCE2

-

I/O FT

FSMC_NE2/

FSMC_NCE3

E8

D8

-

124

125

PG9

FSMC_NCE4_1/

FSMC_NE3

PG10

C8

B8

D7

C7

E6

-

126

127

128

129

130

PG11

PG12

PG13

PG14

V_{SS_11}

I/O FT

S

FSMC_NCE4_2

FSMC_NE4

FSMC_A24

FSMC_A25

30/118

STM32F103xC, STM32F103xD, STM32F103xE

Pin descriptions

Table 4.

Pin definitions (continued)

Pins

Alternate functions

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

F6

B7

-

131

132

V_{DD_11}

PG15

S

I/O

PB3/TRACESWO

JTDO

SPI3_SCK/I2S3_CK/

TIM2_CH2 /

SPI1_SCK

A7 A7 55 89 133

PB3/JTDO

I/O FT

JTDO

TIM3_CH1 /

SPI1_MISO

A6 A6 56 90 134

B6 C5 57 91 135

C6 B5 58 92 136

PB4/JNTRST

PB5

I/O FT

I/O

JNTRST

PB5

PB4/SPI3_MISO

I2C1_SMBAl/

SPI3_MOSI/I2S3_SD

TIM3_CH2 /

SPI1_MOSI

I2C1_SCL⁽⁶⁾

TIM4_CH1⁽⁶⁾

/

PB6

I/O FT

PB6

USART1_TX

USART1_RX

I2C1_SDA⁽⁶⁾

/

D6 A5 59 93 137

PB7

I/O FT

PB7

FSMC_NADV/

TIM4_CH2⁽⁶⁾

D5 D5 60 94 138

C5 B4 61 95 139

BOOT0

PB8

I

BOOT0

PB8

I2C1_SCL/

CANRX

I/O FT

TIM4_CH3⁽⁶⁾/SDIO_D4

TIM4_CH4⁽⁶⁾/SDIO_D5

I2C1_SDA /

CANTX

B5 A4 62 96 140

PB9

PE0

I/O FT

PB9

PE0

TIM4_ETR

FSMC_NBL0

A5 D4

A4 C4

-

97 141

98 142

PE1

I/O FT

PE1

FSMC_NBL1

E5 E5 63 99 143

F5 F5 64 100 144

V_{SS_3}

V_{DD_3}

S

V_{SS_3}

V_{DD_3}

1. I = input, O = output, S = supply, HiZ = high impedance.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used

only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.

5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even

after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com.

6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more

details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available

from the STMicroelectronics website: www.st.com.

7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the

functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and

LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details,

refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

31/118

Pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Table 5.

FSMC pin definition

FSMC

LQFP100

Pins

BGA100⁽¹⁾

CF

CF/IDE

NOR/PSRAM NOR/SRAM Mux NAND 16 bit

PE2

PE3

PE4

PE5

PE6

PF0

A23

A19

A20

A21

A22

A0

A23

A19

A20

A21

A22

Yes

A0

A1

A0

A1

A2

-

PF1

A1

-

PF2

A2

-

PF3

A3

-

PF4

A4

-

PF5

A5

-

PF6

NIORD

NREG

NIOWR

CD

NIORD

NREG

NIOWR

CD

-

PF7

-

PF8

PF9

-

PF10

PF11

PF12

PF13

PF14

PF15

PG0

PG1

PE7

INTR

NIOS16

A6

INTR

-

NIOS16

-

A6

A7

-

A7

-

A8

-

A9

-

A10

A11

D4

-

D4

D5

D4

D5

DA4

DA5

D4

D5

Yes

PE8

D5

PE9

D6

DA6

D6

PE10

PE11

PE12

PE13

PE14

PE15

PD8

D7

DA7

D7

D8

DA8

D8

D9

DA9

D9

D10

D11

D12

D13

D10

D11

D12

D13

D10

D11

D12

D13

DA10

DA11

DA12

DA13

D10

D11

D12

D13

32/118

STM32F103xC, STM32F103xD, STM32F103xE

Pin descriptions

Table 5.

Pins

FSMC pin definition (continued)

FSMC

LQFP100

BGA100⁽¹⁾

CF

CF/IDE

NOR/PSRAM NOR/SRAM Mux NAND 16 bit

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PG2

PG3

PG4

PG5

PG6

PG7

PD0

D14

D15

D14

D15

D14

D15

A16

A17

A18

D0

DA14

DA15

A16

D14

D15

CLE

ALE

Yes

-

A17

A18

D0

D1

D0

D1

DA0

DA1

D0

D1

A12

A13

A14

A15

-

INT2

INT3

D2

-

D2

D3

D2

D3

D2

D3

DA2

DA3

Yes

-

PD1

D3

PD3

CLK

NOE

NWE

NWAIT

NE1

NE2

NE3

CLK

PD4

NOE

NWE

NOE

NWE

NOE

NWE

NWAIT

NE1

NOE

NWE

PD5

PD6

NWAIT

NCE2

NCE3

PD7

PG9

PG10

PG11

PG12

PG13

PG14

PB7

NE2

NCE4_1

NCE4_2

NCE4_1

NCE4_2

NE3

-

NE4

A24

NE4

A24

-

A25

Yes

NADV

NBL0

NBL1

NADV

NBL0

NBL1

PE0

PE1

1. Ports F and G are not available in devices delivered in 100-pin packages.

33/118

Memory mapping

STM32F103xC, STM32F103xD, STM32F103xE

4

Memory mapping

The memory map is shown in Figure 8.

Figure 8. Memory map

Reserved

FSMC register

0xA000 1000 - 0xBFFF FFFF

0xA000 0000 - 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

0x8000 0000 - 0x8FFF FFFF

0x7000 0000 - 0x7FFF FFFF

0x6C00 0000 - 0x6FFF FFFF

0x6800 0000 - 0x6BFF FFFF

0x6400 0000 - 0x67FF FFFF

0x6000 0000 - 0x63FF FFFF

0x4002 4400 - 0x5FFF FFFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0400 - 0x4002 07FF

FSMC bank4 PCCARD

FSMC bank3 NAND (NAND2)

FSMC bank2 NAND (NAND1)

FSMC bank1 NOR/PSRAM 4

FSMC bank1 NOR/PSRAM 3

FSMC bank1 NOR/PSRAM 2

FSMC bank1 NOR/PSRAM 1

Reserved

CRC

Reserved

Flash interface

Reserved

RCC

Reserved

DMA2

DMA1

Reserved

SDIO

0x4002 0000 - 0x4002 03FF

0x4001 8400 - 0x4001 FFFF

0x4001 8000 - 0x4001 83FF

Reserved

ADC3

USART1

TIM8

SPI1

TIM1

0x4001 400 - 0x4001 7FFF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0xFFFF FFFF

512-Mbyte

block 7

ADC2

0x4001 2800 - 0x4001 2BFF

Cortex-M3's

internal

peripherals

ADC1

Port G

Port F

0x4001 2400 - 0x4001 27FF

0x4001 2000 - 0x4001 23FF

0x4001 1C00 - 0x4001 1FFF

0x4001 1800 - 0x4001 1BFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0C00 - 0x4001 0FFF

0x4001 0800 - 0x4001 0BFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 7800 - 0x4000 FFFF

0xE000 0000

0xDFFF FFFF

Port E

Port D

Port C

Port B

Port A

EXTI

AFIO

Reserved

DAC

PWR

512-Mbyte

block 6

Not used

0xC000 0000

0xBFFF FFFF

512-Mbyte

block 5

FSMC register

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

BKP

Reserved

BxCAN

0xA000 0000

0x9FFF FFFF

512-Mbyte

block 4

FSMC bank 3

& bank4

Shared USB/CAN SRAM 512

0x4000 6000 - 0x4000 63FF

bytes

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

USB registers

I2C2

0x8000 0000

0x7FFF FFFF

I2C1

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 1800 - 0x4000 27FF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

UART5

UART4

512-Mbyte

block 3

FSMC bank1

& bank2

USART3

USART2

0x6000 0000

0x5FFF FFFF

Reserved

SPI3/I²S3

SPI2/I²S2

512-Mbyte

block 2

Peripherals

Reserved

IWDG

0x4000 0000

0x3FFF FFFF

WWDG

RTC

512-Mbyte

block 1

SRAM

Reserved

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

0x2000 0000

0x1FFF FFFF

512-Mbyte

block 0

Code

0x0000 0000

0x3FFF FFFF

Reserved

0x2001 0000

0x2000 FFFF

SRAM (64 KB aliased

by bit-banding)

0x2000 0000

Option Bytes

0x1FFF F800 - 0x1FFF F80F

0x1FFF F000- 0x1FFF F7FF

0x1FFF EFFF

0x0808 0000

0x0807 FFFF

0x0800 0000

0x07FF FFFF

0x0008 0000

0x0007 FFFF

System memory

Reserved

Flash

Reserved

Aliased to Flash, system

memory or SRAM

depending on BOOT pins

ai14753c

0x0000 0000

34/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5

Electrical characteristics

5.1

Test conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

5.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3Σ).

5.1.2

5.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the

A

DD

2 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean 2Σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

5.1.4

5.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9.

Pin loading conditions

Figure 10. Pin input voltage

STM32F103xx pin

C = 50 pF

V

IN

ai14141

ai14142

35/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.1.6

Power supply scheme

Figure 11. Power supply scheme

V

BAT

Backup circuitry

(OSC32K,RTC,

Power switch

1.8-3.6V

Wake-up logic

Backup registers)

OUT

IO

Logic

GP I/Os

IN

Kernel logic

(CPU,

Digital

& Memories)

V

DD

V

DD

1/2/3/4/5

Regulator

5 × 100 nF

+ 1 × 10 µF

V

SS

1/2/3/4/5

V

DD

V

DDA

V

REF

V

REF+

Analog:

RCs, PLL,

...

10 nF

+ 1 µF

10 nF

+ 1 µF

V

ADC

REF-

V

SSA

ai14125c

5.1.7

Current consumption measurement

Figure 12. Current consumption measurement scheme

I

_V

DD BAT

V

BAT

I

DD

V

DD

V

DDA

ai14126

36/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics,

Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device

at these conditions is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Table 6.

Symbol

Voltage characteristics

Ratings

External main supply voltage (including V_DDA

Min

Max

Unit

V_DD–V_SS

–0.3

4.0

(1)

and V_DD

)

V

Input voltage on five volt tolerant pin⁽²⁾

Input voltage on any other pin⁽²⁾

V_SS−0.3

50

+5.5

V_DD+0.3

50

V_IN

|ΔV_DDx

|

Variations between different power pins

Variations between all the different ground pins

mV

|V_SSX−V_SS

|

50

see Section 5.3.12:

Absolute maximum ratings

(electrical sensitivity)

Electrostatic discharge voltage (human body

model)

V_ESD(HBM)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. I_INJ(PIN)must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if V_IN

maximum is respected. If V_INmaximum cannot be respected, the injection current must be limited

externally to the I_INJ(PIN)value. A positive injection is induced by V_IN>V_DDwhile a negative injection is

induced by V_IN< V_SS

.

Table 7.

Symbol

I_VDD

I_VSS

Current characteristics

Ratings

Max.

Unit

Total current into V_DDpower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on NRST pin

150

25

−25

5

I_IO

mA

(2)(3)

I_INJ(PIN)

Injected current on HSE OSC_IN and LSE OSC_IN pins

Injected current on any other pin⁽⁴⁾

5

(2)

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁴⁾

25

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN> V_DDwhile a negative injection is induced by V_IN< V_SS

.

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.18: 12-bit ADC

characteristics.

4. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterization with ΣI_INJ(PIN)maximum current injection on four I/O port pins of the device.

37/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 8.

Thermal characteristics

Ratings

Symbol

Value

Unit

T_STG

T_J

Storage temperature range

–65 to +150

150

°C

Maximum junction temperature

5.3

Operating conditions

5.3.1

General operating conditions

Table 9.

Symbol

General operating conditions

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK1

f_PCLK2

V_DD

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

Backup operating voltage

0

72

36

MHz

0

72

2

3.6

V

V_BAT

1.8

3.6

LQFP144

TBD⁽²⁾

434

444

487

TBD⁽²⁾

85

LQFP100

LQFP64

Power dissipation at T_A=

85 °C for suffix 6 or T_A=

105 °C for suffix 7⁽¹⁾

P_D

mW

LFBGA100

LFBGA144

Maximum power dissipation –40

Low power dissipation⁽³⁾

–40

Maximum power dissipation –40

Ambient temperature for 6

suffix version

°C

105

125

105

125

TA

TJ

Ambient temperature for 7

suffix version

Low power dissipation⁽³⁾

–40

6 suffix version

Junction temperature range

7 suffix version

1. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax (see Table 6.2: Thermal

characteristics on page 113).

2. TBD = to be determined.

3. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax (see

Table 6.2: Thermal characteristics on page 113).

5.3.2

Operating conditions at power-up / power-down

The parameters given in Table 10 are derived from tests performed under the ambient

temperature condition summarized in Table 9.

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STM32F103xC, STM32F103xD, STM32F103xE

Table 10. Operating conditions at power-up / power-down

Electrical characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

V_DDrise time rate

V_DDfall time rate

0

∞

t_VDD

µs/V

20

5.3.3

Embedded reset and power control block characteristics

The parameters given in Table 11 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 9.

DD

Table 11. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

2.1 2.18 2.26

2.08 2.16

V

2

2.19 2.28 2.37

2.09 2.18 2.27

2.28 2.38 2.48

2.18 2.28 2.38

2.38 2.48 2.58

2.28 2.38 2.48

2.47 2.58 2.69

2.37 2.48 2.59

2.57 2.68 2.79

2.47 2.58 2.69

2.66 2.78 2.9

2.56 2.68 2.8

V

Programmable voltage

detector level selection

V_PVD

V

2.76 2.88

3

V

2.66 2.78 2.9

100

V

(2)

V_PVDhyst

V_POR/PDR

V_PDRhyst

PVD hysteresis

mV

V

1.8⁽¹⁾

Falling edge

Rising edge

1.88 1.96

Power on/power down

reset threshold

1.84 1.92 2.0

40

V

PDR hysteresis

mV

mS

(2)

T_RSTTEMPO

Reset temporization

1

2.5

4.5

1. The product behavior is guaranteed by design down to the minimum V_POR/PDRvalue.

2. Guaranteed by design, not tested in production.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.4

Embedded reference voltage

The parameters given in Table 12 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 9.

DD

Table 12. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Max Unit

Typ

−40 °C < T_A< +105 °C

−40 °C < T_A< +85 °C

1.16 1.20 1.26

1.16 1.20 1.24

V

V_REFINTInternal reference voltage

ADC sampling time when

reading the internal reference

voltage

(1)

T_{S_vrefint}

5.1

17.1

µs

1. Shortest sampling time can be determined in the application by multiple iterations.

5.3.5

Supply current characteristics

The current consumption is measured as described in Figure 12: Current consumption

measurement scheme.

Maximum current consumption

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V or V (no load)

DD SS

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted to the f frequency (0 wait state from 0

HCLK

to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)

●

Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f

= f

/2, f

= f

PCLK1

HCLK

PCLK2 HCLK

The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed

under ambient temperature and V supply voltage conditions summarized in Table 9.

DD

40/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 13. Maximum current consumption in Run mode, code with data processing

running from Flash

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C T_A= 105 °C

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

69

50

70

50.5

39.5

28

External clock⁽²⁾, all

peripherals enabled

39

27

20

20.5

11.5

37.5

28.5

22.5

17

11

Supplycurrent in

Run mode

I_DD

mA

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

37

28

External clock⁽²⁾, all

peripherals disabled

22

16.5

12.5

8

13

8

1. Data based on characterization results, not tested in production.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz; external clock is 9 MHz for f_HCLK= 36 MHz.

Table 14. Maximum current consumption in Run mode, code with data processing

running from RAM

Max

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C T_A= 105 °C

72 MHz⁽²⁾

48 MHz⁽³⁾

36 MHz⁽³⁾

24 MHz⁽³⁾

16 MHz⁽³⁾

8 MHz⁽³⁾

72 MHz

66

43.5

33

23

16

9

67

45.5

35

External clock⁽¹⁾, all

peripherals enabled

24.5

18

10.5

33.5

23.5

18.5

13.5

10.5

6.5

Supply current

in Run mode

I_DD

mA

33

23

18

13

10

6

48 MHz

External clock⁽¹⁾, all

peripherals

36 MHz

disabled⁽³⁾

24 MHz

16 MHz

8 MHz

1. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz; external clock is 9 MHz for f_HCLK= 36 MHz.

2. Data based on characterization results, tested in production at V_{DD max}, f_HCLKmax. and T_Amax, and code

executed from RAM.

3. Based on characterization, not tested in production.

41/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled

70

60

8 MHz

16 MHz

24 MHz

36 MHz

48 MHz

72 MHz

50

40

30

20

10

0

-45

25

70

85

105

Temperature (°C)

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled

35

30

8 MHz

16 MHz

24 MHz

36 MHz

25

48 MHz

72 MHz

20

15

10

5

0

-45

25

70

85

105

Temperature (°C)

42/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 15. Maximum current consumption in Sleep mode, code running from Flash

or RAM

Max

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C T_A= 105 °C

72 MHz⁽²⁾

48 MHz⁽³⁾

36 MHz⁽³⁾

24 MHz⁽³⁾

16 MHz⁽³⁾

8 MHz⁽³⁾

72 MHz

66

43.5

33

23

16

9

67

45.5

35

External clock⁽¹⁾, all

peripherals enabled

24.5

18

10.5

33.5

23.5

18.5

13.5

10.5

6.5

Supply current

in Sleep mode

I_DD

mA

33

23

18

13

10

6

48 MHz

External clock⁽¹⁾, all

peripherals

36 MHz

disabled⁽³⁾

24 MHz

16 MHz

8 MHz

1. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz; external clock is 9 MHz for f_HCLK= 36 MHz.

2. Data based on characterization results, tested in production at V_{DD max}, f_HCLKmax. and T_Amax.

3. Based on characterization, not tested in production.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Table 16. Typical and maximum current consumptions in Stop and Standby modes

Typ⁽²⁾

Max

Symbol

Parameter

Conditions

Unit

V_DD/V_BATV_DD/V_BATT_A=

T_A=

= 2.4 V

= 3.3 V 85 °C 105 °C

Regulator in main mode, low-speed

and high-speed internal RC oscillators

and high-speed oscillator OFF (no

independent watchdog)

34.5

35

25

TBD⁽³⁾TBD⁽³⁾

Supply current in

Stop mode

Regulator in low-power mode, low-

speed and high-speed internal RC

oscillators and high-speed oscillator

OFF (no independent watchdog)

24.5

TBD⁽³⁾TBD⁽³⁾

I_DD

Low-speed internal RC oscillator and

independent watchdog ON

µA

3

3.8

3.6

TBD

Low-speed internal RC oscillator ON,

independent watchdog OFF

Supply current in

Standby mode⁽⁴⁾

2.8

Low-speed internal RC oscillator and

independent watchdog OFF, low-speed

oscillator and RTC OFF

1.9

1.1

2.1

1.4

5⁽⁵⁾

6.5⁽⁵⁾

Backup domain

supply current

I_{DD_VBAT}

Low-speed oscillator and RTC ON

TBD⁽⁵⁾TBD⁽⁵⁾

1. TBD stands for to be determined.

2. Typical values are measured at T_A= 25 °C, V_DD= 3.3 V, unless otherwise specified.

3. Data based on characterization results, tested in production at V_DDmax and f_HCLKmax.

4. To have the Standby consumption with RTC ON, add I_{DD_VBAT}(Low-speed oscillator and RTC ON) to I_DDStandby (when

_DDis present the Backup Domain is powered by V_DDsupply).

V

5. Data based on characterization results, not tested in production.

44/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 15. Current consumption in Stop mode with regulator in main mode versus

temperature at different V values

DD

700

600

500

400

300

200

100

0

2.4V

2.7V

3.0V

3.3V

3.6V

-45

25

70

85

105

Temperature (°C)

Figure 16. Current consumption in Stop mode with regulator in low-power mode

versus temperature at different V values

DD

700

600

500

400

300

200

100

0

2.4V

2.7V

3.0V

3.3V

3.6V

-45

25

70

85

105

Temperature (°C)

45/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 17. Current consumption in Standby mode versus temperature at different

values

V

DD

4.5

4

3.5

3

2.5

2

1.5

1

2.4V

2.7V

3.0V

3.3V

3.6V

0.5

0

-45

25

70

85

105

Temperature (°C)

Typical current consumption

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V or V (no load).

DD SS

All peripherals are disabled except if it is explicitly mentioned.

The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1

HCLK

wait state from 24 to 48 MHZ and 2 wait states above).

●

Ambient temperature and V supply voltage conditions summarized in Table 9.

DD

Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f

= f

/4, f

2 = f

/2, f

= f

/4

PCLK1

HCLK

PCLK

HCLK

ADCCLK

PCLK2

46/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 17. Typical current consumption in Run mode, code with data processing

running from Flash

Typ⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

Allperipherals Allperipherals

enabled⁽²⁾

disabled

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

51

34.6

26.6

18.5

12.8

7.2

4.2

2.7

2

30.5

20.7

16.2

11.4

8.2

5

External clock⁽³⁾

mA

4 MHz

3.1

2.1

1.7

1.4

1.2

27

2 MHz

1 MHz

500 kHz

125 kHz

64 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

1.6

1.3

45

Supply

I_DD

current in

Run mode

34

20.1

15.6

10.8

7.6

4.4

2.5

1.5

1.1

0.8

0.6

26

17.9

12.2

6.6

3.6

2.1

1.4

1

Running on high

speed internal RC

(HSI), AHB

prescaler used to

reduce the

mA

4 MHz

frequency

2 MHz

1 MHz

500 kHz

125 kHz

0.7

1. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this

consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

47/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 18. Typical current consumption in Sleep mode, code with data processing

code running from Flash or RAM

Typ⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

All peripherals All peripherals

enabled⁽²⁾

disabled

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

29.5

20

6.4

4.6

3.6

2.6

2

15.1

10.4

7.2

External clock⁽³⁾

3.9

1.3

1.2

1.15

1.1

1.05

5.1

4

4 MHz

2.6

2 MHz

1.85

1.5

1 MHz

500 kHz

125 kHz

64 MHz

48 MHz

36 MHz

24 MHz

16 MHz

1.3

Supply

1.2

I_DD

current in

mA

25.6

19.4

14.5

9.8

Sleep mode

3

2

Running on high

speed internal RC

6.6

1.4

0.7

0.6

0.55

0.5

0.45

(HSI), AHB prescaler 8 MHz

3.3

used to reduce the

frequency

4 MHz

2

2 MHz

1.25

0.9

1 MHz

500 kHz

125 kHz

0.7

0.6

1. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this

consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed

under the following conditions:

●

all I/O pins are in input mode with a static value at V or V (no load)

DD SS

all peripherals are disabled unless otherwise mentioned

the given value is calculated by measuring the current consumption

–

with all peripherals clocked off

with only one peripheral clocked on

●

ambient operating temperature and V supply voltage conditions summarized in

DD

Table 6

(1)

Table 19. Peripheral current consumption

Peripheral

Typical consumption at 25 °C

Unit

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

SPI2

SPI3

1.2

0.4

0.2

0.4

0.5

0.6

0.4

0.65

0.72

APB1

USART2

USART3

UART4

UART5

I2C1

mA

I2C2

USB

CAN

DAC

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Table 19. Peripheral current consumption

(continued)

Peripheral

Typical consumption at 25 °C

Unit

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

ADC1⁽²⁾

ADC2

0.55

0.72

0.55

1

0.72

1

APB2

mA

1.9

1.7

1.8

0.4

1.7

0.9

1.7

TIM1

SPI1

TIM8

USART1

ADC3

1. f_HCLK= 72 MHz, f_APB1= f_HCLK/2, f_APB2= f_HCLK, default prescaler value for each peripheral.

2. Specific conditions for ADC: f_HCLK= 56 MHz, f_APB1= f_HCLK/2, f_APB2= f_HCLK, f_ADCCLK= f_APB2/4, ADON bit

in the ADC_CR2 register is set to 1.

5.3.6

External clock source characteristics

High-speed external user clock

The characteristics given in Table 20 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 9.

Table 20. High-speed external (HSE) user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency⁽¹⁾

f_{HSE_ext}

8

25

MHz

OSC_IN input pin high level

voltage

V_HSEH

V_HSEL

0.7V_DD

V_SS

V_DD

V

OSC_IN input pin low level

voltage

0.3V_DD

t_w(HSE)

OSC_IN high or low time⁽¹⁾

OSC_IN rise or fall time⁽¹⁾

16

ns

t_r(HSE)

t_f(HSE)

5

1

OSC_IN Input leakage

current

I_L

V_SS≤V_IN≤V_DD

µA

1. Value based on design simulation and/or technology characteristics. It is not tested in production.

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STM32F103xC, STM32F103xD, STM32F103xE

Low-speed external user clock

Electrical characteristics

The characteristics given in Table 21 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 9.

Table 21. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User External clock source

frequency⁽¹⁾

f_{LSE_ext}

32.768

1000

kHz

OSC32_IN input pin high level

voltage

V_LSEH

V_LSEL

t_w(LSE)

0.7V_DD

V_SS

V_DD

V

OSC32_IN input pin low level

voltage

0.3V_DD

OSC32_IN high or low time⁽¹⁾

OSC32_IN rise or fall time⁽¹⁾

450

t_w(LSE)

ns

t_r(LSE)

t_f(LSE)

5

1

OSC32_IN Input leakage

current

I_L

V_SS≤V_IN≤V_DD

µA

1. Value based on design simulation and/or technology characteristics. It is not tested in production.

Figure 18. High-speed external clock source AC timing diagram

V

HSEH

90%

10%

V

HSEL

t

W(HSE)

t

W(HSE)

r(HSE)

f(HSE)

T

HSE

f

HSE_ext

EXTERNAL

CLOCK SOURCE

I

L

OSC _IN

STM32F103xx

ai14143

51/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 19. Low-speed external clock source AC timing diagram

V

LSEH

90%

10%

V

LSEL

t

W(LSE)

t

W(LSE)

r(LSE)

f(LSE)

T

LSE

f

LSE_ext

EXTERNAL

CLOCK SOURCE

I

L

OSC32_IN

STM32F103xx

ai14144b

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STM32F103xC, STM32F103xD, STM32F103xE

High-speed external clock

Electrical characteristics

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 22. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

(1)

Table 22. HSE 4-16 MHz oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_{OSC_IN}Oscillator frequency

4

8

16

MHz

R_F

Feedback resistor

200

kΩ

Recommended load capacitance

versus equivalent serial

C_L1

R_S= 30 Ω

30

pF

(2)

C_L2

resistance of the crystal (R_S)⁽³⁾

V_DD= 3.3 V

V_IN= V_SSwith 30 pF

load

i₂

HSE driving current

1

mA

(4)

g_m

t_SU(HSE)

Oscillator transconductance

startup time

Startup

25

mA/V

ms

(5)

V_DDis stabilized

2

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. For C_L1and C_L2it is recommended to use high-quality ceramic capacitors in the 5 pF to 25pF range (typ.),

designed for high-frequency applications, and selected to match the requirements of the crystal or

resonator. C_L1and C_L2,are usually the same size. The crystal manufacturer typically specifies a load

capacitance which is the series combination of C_L1and C_L2. PCB and MCU pin capacitance must be

included when sizing C_L1and C_L2(10 pF can be used as a rough estimate of the combined pin and board

capacitance).

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a

humid environment, due to the induced leakage and the bias condition change. However, it is

recommended to take this point into account if the MCU is used in tough humidity conditions.

4. Based on characterization results, not tested in production.

5. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

Figure 20. Typical application with a 8-MHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC_IN

HSE

Bias

controlled

gain

8 MHz

resonator

R

F

STM32F103xx

OSC_OUT

(1)

R

EXT

C

L2

ai14145

1. R_EXTvalue depends on the crystal characteristics. Typical value is in the range of 5 to 6R_S.

53/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Low-speed external clock

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 23. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

Table 23. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Feedback resistor

Conditions

Min

Typ

Max

Unit

R_F

5

MΩ

Recommended load capacitance

versus equivalent serial

C_L1

C_L2

R_S= 30 kΩ

15

pF

µA

resistance of the crystal (R_S)⁽¹⁾

V_DD= 3.3 V

V_IN= V_SS

I₂

LSE driving current

1.4

g_m

Oscillator Transconductance

startup time

5

µA/V

s

(2)

t_SU(LSE)

V_DDis stabilized

3

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with

small R_Svalue for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details

2. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768

kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary

significantly with the crystal manufacturer

Figure 21. Typical application with a 32.768 kHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC32_IN

LSE

Bias

controlled

gain

32.768 kHz

resonator

R

F

STM32F103xx

OSC32_OUT

C

L2

ai14146

54/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.3.7

Internal clock source characteristics

The parameters given in Table 24 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 9.

DD

High-speed internal (HSI) RC oscillator

(1)

Table 24. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ

Max

Unit

f_HSI

8

MHz

%

T_A= –40 to 105 °C

T_A= 25°C

3⁽²⁾

2

ACC_HSIAccuracy of HSI oscillator

t_su(HSI)HSI oscillator start up time

1

%

1

2

µs

HSI oscillator power

I_DD(HSI)

80

100

µA

consumption

1.

V_DD= 3.3 V, T_A= −40 to 105 °C unless otherwise specified.

2. Values based on device characterization, not tested in production.

LSI low speed internal RC oscillator

(1)

Table 25. LSI oscillator characteristics

Min⁽²⁾

Symbol

Parameter

Frequency

Conditions

Typ

Max

Unit

f_LSI

30

40

60

85

kHz

µs

t_su(LSI)LSI oscillator startup time

LSI oscillator power

I_DD(LSI)

0.65

1.2

µA

consumption

1. V_DD= 3 V, T_A= −40 to 105 °C unless otherwise specified.

2. Value based on device characterization, not tested in production.

55/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Wakeup time from low-power mode

The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC

oscillator. The clock source used to wake up the device depends from the current operating

mode:

●

Stop or Standby mode: the clock source is the RC oscillator

●

Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V supply

DD

voltage conditions summarized in Table 9.

Table 26. Low-power mode wakeup timings

Symbol

Parameter

Conditions

Typ Unit

(1)

Wakeup from Sleep mode

Wakeup on HSI RC clock

1.8

3.6

µs

t_WUSLEEP

Wakeup from Stop mode

(regulator in run mode)

HSI RC wakeup time = 2 µs

(1)

µs

t_WUSTOP

HSI RC wakeup time = 2 µs,

Regulator wakeup from LP mode

time = 5 µs

Wakeup from Stop mode

(regulator in low power mode)

5.4

50

HSI RC wakeup time = 2 µs,

Regulator wakeup from power down

time = 38 µs

(1)

Wakeup from Standby mode

µs

t_WUSTDBY

1. The wakeup times are measured from the wakeup event to the point in which the user application code

reads the first instruction.

5.3.8

PLL characteristics

The parameters given in Table 27 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 9.

DD

Table 27. PLL characteristics

Value

Symbol

Parameter

Test conditions

Unit

Min

Typ

Max⁽¹⁾

PLL input clock

8.0

MHz

%

f_{PLL_IN}

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

40

16

60

72

f_{PLL_OUT}

t_LOCK

MHz

µs

200

1. Data based on device characterization, not tested in production.

56/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.3.9

Memory characteristics

Flash memory

The characteristics are given at T = −40 to 105 °C unless otherwise specified.

A

Table 28. Flash memory characteristics

Symbol

Parameter

Conditions

Min

Typ

Max⁽¹⁾Unit

t_prog

Word programming time T_A= −40 to +105 °C

40

20

52.5

70

40

µs

ms

t_ERASEPage (2 KB) erase time T_A= −40 to +105 °C

t_ME

Mass erase time

Supply current

T_A= −40 to +105 °C

Read mode

f_HCLK= 72 MHz with 2 wait

28

mA

states, V_DD= 3.3 V

Write mode

7

5

mA

f_HCLK= 72 MHz, V_DD= 3.3 V

I_DD

Erase mode

f_HCLK= 72 MHz, V_DD= 3.3 V

Power-down mode / Halt,

V_DD= 3.0 to 3.6 V

50

µA

V

V_progProgramming voltage

2

3.6

1. Values based on characterization and not tested in production.

Table 29. Flash memory endurance and data retention

Value

Typ

Symbol

Parameter

Conditions

Unit

Min⁽¹⁾

Max

TBD⁽²⁾

30

N_ENDEndurance

kcycles

Years

T_A= 85 °C, 1000 cycles

t_RET

Data retention

T_A= 105 °C, 1000

cycles

10

1. Values based on characterization not tested in production.

2. TBD = to be determined.

57/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.10

FSMC characteristics

All the timing characteristics are relative to the FSMC_CLK signal for synchronous

SRAM/NOR Flash memory accesses.

Figure 22. Asynchronous non-multiplexed SRAM/NOR write timings

t

w(NE)

FSMC_NEx

FSMC_NOE

FSMC_NWE

t

h(NE_NWE)

v(NWE_NE)

w(NWE)

t

t_{v(A_NE)}

h(A_NWE)

FSMC_A[25:0]

Address

t_{v(BL_NE)}

t

h(BL_NWE)

FSMC_NBL[3:0]

NBL

t

v(Data_NE)

h(Data_NWE)

Data

FSMC_D[15:0]

t

v(NADV_NE)

t

w(NADV)

(1)

FSMC_NADV

ai14990

1. Mode 2/B, C and D only.

(1)

Table 30. Asynchronous non-multiplexed SRAM/NOR write timings

V_{DD_IO}= V and C_L= 15 pF

Symbol

Parameter

FSMC_NE low time

Min

Max

Unit

t_w(

TBD

t_CK/ns

ns

NE

)

t_v(

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

WEN_NE

)

t_w(

NWE

)

t_h(

t_v(

t_h(

t_v(

t_h(

t_v(

t_h(

t_v(

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NEx low to Data valid

NE_NWE

)

TBD

A_NE

)

TBD

t_CK/ns

ns

A_NWE

)

BL_NE

)

t_CK/ns

BL_NWE

)

Data_NE

)

Data hold time after FSMC_NWE high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

Data_NWE

)

TBD

NADV_NE

)

t_w(

NADV

)

1. TBD = to be determined.

58/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 23. Asynchronous non-multiplexed SRAM/NOR read timings

t

w(NE)

FSMC_NE

t

h(NE_NOE)

w(NOE)

v(NOE_NE)

FSMC_NOE

FSMC_NWE

t_{v(A_NE)}

t

h(A_NOE)

FSMC_A[25:0]

Address

NBL

t_{v(BL_NE)}

t

h(BL_NOE)

FSMC_NBL[3:0]

t

h(Data_NE)

t

su(Data_NOE)

h(Data_NOE)

t

su(Data_NE)

Data

FSMC_D[15:0]

t

v(NADV_NE)

t

w(NADV)

FSMC_NADV⁽¹⁾

ai14991

1. Mode 2/B, C and D only.

(1)

Table 31. Asynchronous non-multiplexed SRAM/NOR read timings

V_{DD_IO}= V and C_L= 15 pF

Symbol

Parameter

FSMC_NE low time

Min

Max

Unit

t_w(

TBD

t_CK/ns

ns

NE

)

t_v(

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

NOE_NE

)

t_w(

NOE

)

t_h(

t_v(

t_h(

t_v(

t_h(

FSMC_NOE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

Address hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NOE high

Data to FSMC_NEx high setup time

Data to FSMC_NOEx high setup time

Data hold time after FSMC_NOE high

Data hold time after FSMC_NEx high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

NE_NOE

)

TBD

A_NE

)

TBD

t_CK/ns

ns

A_NOE

)

BL_NE

)

TBD

t_CK/ns

ns

BL_NOE

)

t_su(

t_h(

Data_NE

)

Data_NOE

)

Data_NOE

)

t_h(

Data_NE

)

t_v(

TBD

t_CK/ns

NADV_NE

)

t_w(

NADV

)

1. TBD = to be determined.

59/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 24. Asynchronous multiplexed SRAM/NOR write timings

t

wNE

FSMC_NEx

FSMC_NOE

t

h(NE_NWE)

v(NWE_NE)

w(WENL)

FSMC_NWE

t

t_{v(A_NE)}

h(A_NWE)

FSMC_A[25:16]

Address

t_{v(BL_NE)}

t

h(BL_NWE)

FSMC_NBL[3:0]

FSMC_AD[15:0]

NBL

t

h(Data_NW)

t

v(A_NE)

v(Data_NL)

Address

Data

t

t_{h(AD_NADV)}

v(NADV_NE)

t

w(NADV)

FSMC_NADV

t_{dis(AD_NADV)}

ai14891

(1)

Table 32. Asynchronous multiplexed SRAM/NOR write timings

FSMC - Asynchronous multiplexed SRAM/NOR write timings

V_{DD_IO}= V and C_L= 15 pF

Symbol

t_w(

Parameter

Min

Max

Unit

FSMC_NE low time

TBD

t_CK/ns

ns

NE

)

t_v(

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

NWE_NE

)

t_w(

NWE

)

t_h(

NE_NWE

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

)

t_v(

TBD

A_NE

)

TBD

t_CK/ns

ns

NADV_NE

)

t_w(

NADV

)

t_h(

AD_NADV

FSMC_AD (address) valid hold time after FSMC_NADV high TBD

FSMC_AD (address) disable time after FSMC_NADV high

)

t_dis(

TBD

AD_NADV

)

t_h(

t_v(

t_h(

t_v(

t_h(

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NADV high to Data valid

TBD

A_NWE

)

BL_NE

)

TBD

t_CK/ns

BL_NWE

)

Data_NADV

Data_NWE

)

Data hold time after FSMC_NWE high

)

1. TBD = to be determined.

60/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 25. Asynchronous multiplexed SRAM/NOR read timings

t

w(NE)

FSMC_NE

t

h(NE_NOE)

v(NOE_NE)

FSMC_NOE

t

w(NOE)

FSMC_NWE

t

t_{v(A_NE)}

h(A_NOE)

FSMC_A[25:16]

Address

t_{v(BL_NE)}

t

h(BL_NOE)

FSMC_NBL[3:0]

NBL

t

h(Data_NE)

t

su(Data_NE)

t

h(Data_NOE)

v(A_NE)

su(Data_NOE)

Address

Data

FSMC_AD[15:0]

FSMC_NADV

t

t_{h(AD_NADV)}

t_{dis(AD_NADV)}

v(NADV_NE)

t

w(NADV)

ai14892

61/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 33. Asynchronous multiplexed SRAM/NOR read timings

V_{DD_IO}= V and C_L= 15 pF

Symbol

t_w(

Parameter

Min

Max

Unit

FSMC_NE low time

TBD

t_CK/ns

ns

NE

)

t_v(

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

NOE_NE

)

t_w(

NOE

)

t_h(

FSMC_WEN high to FSMC_NE high hold time

FSMC_NOE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

NE_WEN

NE_NOE

)

t_h(

t_v(

)

TBD

A_NE

)

TBD

t_CK/ns

NADV_NE

)

t_w(

NADV

)

FSMC_AD (address) valid hold time after FSMC_NADV

high

t_h(

AD_NADV

TBD

t_CK/ns

)

t_dis(

FSMC_AD (address) disable time after FSMC_NADV high

Address hold time after FSMC_NOE high

FSMC_BL hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

TBD

t_CK/ns

ns

AD_NADV

)

t_h(

t_v(

TBD

A_NOE

)

BL_NOE

)

BL_NE

)

t_su(

t_h(

Data to FSMC_NEx high setup time

TBD

t_CK/ns

ns

Data_NE

)

Data to FSMC_NOE high setup time

Data_NOE

)

Data hold time after FSMC_NEx high

Data hold time after FSMC_NOE high

Data_NE

)

t_h(

Data_NOE

ns

)

62/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 26. Synchronous multiplexed NOR/PSRAM read timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

Data latency = 1

d(CLKH-NExL)

t

d(CLKH-NExH)

FSMC_NEx

t

d(CLKH-NADVL)

d(CLKH-NADVH)

FSMC_NADV

t

d(CLKH-AV)

d(CLKH-AIV)

FSMC_A[24:16]

FSMC_NWE

d(CLKH-NWEH)

d(CLKH-NWEL

t

d(CLKH-NOEH)

d(CLKH-NOEL)

FSMC_NOE

t

h(CLKH-ADV)

d(CLKH-ADIV)

t

h(CLKH-ADV)

su(ADV-CLKH)

d(CLKH-ADV)

FSMC_AD[15:0]

AD[15:0]

t

D1

D2

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

t

h(CLKH-NWAITV)

su(NWAITV-CLKH)

ai14893

63/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Table 34. Synchronous multiplexed NOR/PSRAM read timings

V_{DD_IO}= V and C_L= 15 pF

Symbol

t_w(CLK)

Parameter

Min

Max

Unit

FSMC_CLK period

TBD

-

ns

t_d(CLKH-NExL)

t_d(CLKH-NExH)

t_d(

FSMC_CLK high to FSMC_NEx low (x = 0...2)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

FSMC_CLK high to FSMC_NADV low

TBD

-

TBD

CLK NADVL

H-

)

t_{d(CLKH-NADVH)}FSMC_CLK high to FSMC_NADV high

TBD

-

t_d(CLKH-AV)

t_d(CLKH-AIV)

FSMC_CLK high to FSMC_Ax valid (x = 16...25)

FSMC_CLK high to FSMC_Ax invalid (x = 16...25)

TBD

-

t_d(CLKH-NWEL)FSMC_CLK high to FSMC_NWE low

t_d(CLKH-NWEH)FSMC_CLK high to FSMC_NWE high

TBD

-

t_d(CLKH-NOEL)

FSMC_CLK high to FSMC_NOE low

TBD

t_d(CLKH-NOEH)FSMC_CLK high to FSMC_NOE high

TBD

-

t_d(CLKH-ADV)

t_d(CLKH-ADIV)

t_su(ADV-CLKH)

t_h(CLKH-ADV)

FSMC_CLK high to FSMC_AD[15:0] valid

TBD

FSMC_CLK high to FSMC_AD[15:0] invalid

FSMC_A/D[15:0] valid data before FSMC_CLK high

FSMC_A/D[15:0] valid data after FSMC_CLK high

TBD

-

t_su(NWAITV-

FSMC_NWAIT valid before FSMC_CLK high

TBD

-

ns

CLKH)

t_{h(CLKH-NWAITV)}FSMC_NWAIT valid after FSMC_CLK high

1. TBD = to be determined.

64/118

STM32F103xC, STM32F103xD, STM32F103xE

Figure 27. Synchronous multiplexed PSRAM write timings

Electrical characteristics

BUSTURN = 0

t

w(CLK)

FSMC_CLK

Data latency = 1

d(CLKH-NExL)

t

d(CLKH-NExH)

FSMC_NEx

t

d(CLKH-NADVL)

d(CLKH-NADVH)

FSMC_NADV

t

d(CLKH-AV)

d(CLKH-AIV)

FSMC_A[24:16]

FSMC_NWE

t

d(CLKH-NWEH)

d(CLKH-NWEL)

t

d(CLKH-NOEL)

d(CLKH-NOEH)

t

FSMC_NOE

t

d(CLKH-ADIV)

t

h(CLKH-ADV)

t

v(Data-CLK)

d(CLKH-ADV)

h(CLKH-ADV)

FSMC_AD[15:0]

AD[15:0]

D1

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

t

h(CLKH-NWAITV)

su(NWAITV-CLKH)

ai14992

65/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Table 35. Synchronous multiplexed PSRAM write timings

V_{DD_IO}= V and C_L= 15 pF

Symbol

t_w(CLK)

Parameter

Min

Max

Unit

FSMC_CLK period

TBD

-

ns

t_d(CLKH-NExL)

t_d(CLKH-NExH)

t_d(

FSMC_CLK high to FSMC_NEx low (x = 0...2)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

FSMC_CLK high to FSMC_NADV low

TBD

-

TBD

CLK NADVL

H-

)

t_{d(CLKH-NADVH)}

t_d(CLKH-AV)

FSMC_CLK high to FSMC_NADV high

FSMC_CLK high to FSMC_Ax valid (x = 16...25)

FSMC_CLK high to FSMC_Ax invalid (x = 16...25)

FSMC_CLK high to FSMC_NWE low

TBD

-

TBD

t_d(CLKH-AIV)

TBD

-

t_d(CLKH-NWEL)

t_d(CLKH-NWEH)

t_d(CLKH-NOEL)

t_d(CLKH-NOEH)

t_d(CLKH-ADV)

t_d(CLKH-ADIV)

t_h(CLKH-ADV)

t_{su(NWAITV-CLKH)}

t_{h(CLKH-NWAITV)}

t_v(Data-CLK)

TBD

FSMC_CLK high to FSMC_NWE high

TBD

-

FSMC_CLK high to FSMC_NOE low

TBD

FSMC_CLK high to FSMC_NOE high

TBD

-

FSMC_CLK high to FSMC_AD[15:0] valid

FSMC_CLK high to FSMC_AD[15:0] invalid

FSMC_A/D[15:0] valid data after FSMC_CLK high

FSMC_NWAIT valid before FSMC_CLK high

FSMC_NWAIT valid after FSMC_CLK high

FSMC_CLK high to FSMC_CLK valid

TBD

-

1. TBD = to be determined.

66/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

t

d(CLKH-NExL)

d(CLKH-NExH

Data latency = 1

d(CLKH-NADVH)

FSMC_NEx

t

d(CLKH-NADVL)

FSMC_NADV

FSMC_A[24:0]

FSMC_NWE

t

d(CLKH-AV)

d(CLKH-AIV)

d(CLKH-NWEH)

d(CLKH-NWEL

t

d(CLKH-NOEH)

d(CLKH-NOEL)

FSMC_NOE

t

su(DV-CLKH)

h(CLKH-DV)

t

h(CLKH-DV)

su(DV-CLKH)

FSMC_D[15:0]

FSMC_NWAIT

D1

D2

t

su(NWAITV-CLKH)

t

h(CLKH-NWAITV)

(WAITCFG = 1b, WAITPOL + 0b)

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

t

h(CLKH-NWAITV)

su(NWAITV-CLKH)

ai14893

67/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Table 36. Synchronous non-multiplexed NOR/PSRAM read timings

V_{DD_IO}= V and C_L= 15 pF

Symbol

t_w(CLK)

Parameter

Min

Max

Unit

FSMC_CLK period

TBD

-

ns

t_d(CLKH-NExL)

t_d(CLKH-NExH)

t_d(

FSMC_CLK high to FSMC_NEx low (x = 0...2)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

FSMC_CLK high to FSMC_NADV low

TBD

-

TBD

CLK NADVL

H-

)

t_{d(CLKH-NADVH)}

t_d(CLKH-AV)

FSMC_CLK high to FSMC_NADV high

TBD

-

FSMC_CLK high to FSMC_Ax valid (x = 0...25)

FSMC_CLK high to FSMC_Ax invalid (x = 0...25)

FSMC_CLK high to FSMC_NWE low

TBD

t_d(CLKH-AIV)

TBD

-

t_d(CLKH-NWEL)

t_d(CLKH-NWEH)

t_d(CLKH-NOEL)

t_d(CLKH-NOEH)

t_su(DV-CLKH)

t_h(CLKH-DV)

TBD

FSMC_CLK high to FSMC_NWE high

TBD

-

FSMC_CLK high to FSMC_NOE low

TBD

FSMC_CLK high to FSMC_NOE high

TBD

-

FSMC_D[15:0] valid data before FSMC_CLK high

FSMC_D[15:0] valid data after FSMC_CLK high

t_{su(NWAITV-CLKH)}FSMC_NWAIT valid before FSMC_SMCLK high

t_{h(CLKH-NWAITV)}FSMC_NWAIT valid after FSMC_CLK high

1. TBD = to be determined.

68/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 29. Synchronous non-multiplexed PSRAM write timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

t

d(CLKH-NExL)

d(CLKH-NExH)

Data latency = 1

d(CLKH-NADVH)

FSMC_NEx

t

d(CLKH-NADVL)

FSMC_NADV

FSMC_A[24:0]

FSMC_NWE

t

d(CLKH-AIV)

d(CLKH-AV)

t

d(CLKH-NWEH)

d(CLKH-NWEL)

t

d(CLKH-NOEH)

d(CLKH-NOEL)

t

FSMC_NOE

t

h(CLKH-DV)

v(Data-CLK)

h(CLKH-DV)

D1

FSMC_D[15:0]

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

ai14993

69/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Table 37. Synchronous non-multiplexed PSRAM write timings

V_{DD_IO}= V and C_L= 15 pF

Symbol

t_w(CLK)

Parameter

Min

Max

Unit

FSMC_CLK period

TBD

-

ns

t_d(CLKH-NExL)

t_d(CLKH-NExH)

t_d(

FSMC_CLK high to FSMC_NEx low (x = 0...2)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

FSMC_CLK high to FSMC_NADV low

TBD

x

-

TBD

CLK NADVL

H-

)

t_{d(CLKH-NADVH)}FSMC_CLK high to FSMC_NADV high

TBD

-

t_d(CLKH-AV)

FSMC_CLK high to FSMC_Ax valid (x = 16...25)

FSMC_CLK high to FSMC_Ax invalid (x = 16...25)

FSMC_CLK high to FSMC_NWE low

TBD

t_d(CLKH-AIV)

t_d(CLKH-NWEL)

t_d(CLKH-NWEH)

t_d(CLKH-NOEL)

t_d(CLKH-NOEH)

t_su(DV-CLKH)

t_h(CLKH-DV)

TBD

-

TBD

FSMC_CLK high to FSMC_NWE high

TBD

-

FSMC_CLK high to FSMC_NOE low

TBD

FSMC_CLK high to FSMC_NOE high

TBD

-

FSMC_D[15:0] valid data before FSMC_CLK high

FSMC_D[15:0] valid data after FSMC_CLK high

FSMC_CLK high to FSMC_CLK valid

t_v(Data-CLK)

t_{h(CLKH-NWAITV)}FSMC_NWAIT valid after FSMC_CLK high

1. TBD = to be determined.

70/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 30. PC-card controller timing for common memory read access

FSMC_NCE4_2⁽¹⁾

FSMC_NCE4_1

t

h(NCEx-AI)

t

v(NCEx-A)

FSMC_A[10:0]

t

d(NREG-NCEx)

d(NIORD-NCEx)

d(NIOWR-NCEx)

h(NCEx-NREG)

h(NCEx-NIORD)

h(NCEx-NIOWR

)

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

FSMC_NWE

FSMC_NOE

t

w(NOE)

su(D-NIORD)

t

su(D-NOE)

h(NOE-D)

FSMC_D[15:0]

t

d(NOE-NWAITH)

t

d(NWAIT-NOE)

d(NOE-NWAITL)

FSMC_NWAIT

(PWAITEN = 1b)

ai14895

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

71/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 31. PC-card controller timing for common memory write access

FSMC_NCE4_2⁽¹⁾

FSMC_NCE4_1

t

v(NCEx-A)

h(NCEx-AI)

FSMC_A[10:0]

t

d(NREG-NCEx)

d(NIORD-NCEx)

d(NIOWR-NCEx)

h(NCEx-NREG)

h(NCEx-NIORD)

h(NCEx-NIOWR)

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

t

d(NCEx-NWE)

w(NWE)

d(NWE-NCEx)

FSMC_NWE

FSMC_NOE

MEMxHIZ =1

t

d(D-NWE)

t

v(NWE-D)

h(NWE-D)

FSMC_D[15:0]

t

d(NWE-NWAITH)

d(NWAIT-NWE)

t

d(NWE-NWAITL)

FSMC_NWAIT

(PWAITEN = 1b)

ai14896

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

72/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 32. PC-card controller timing for attribute memory read access

FSMC_NCE4_1

FSMC_NCE4_2

t

h(NCE4_1-AI)

v(NCE4_1-A)

High

FSMC_A[10:0]

t

d(NIORD-NCE4_1)

d(NIOWR-NCE4_1)

h(NCE4_1-NIORD)

h(NCE4_1-NIOWR)

FSMC_NIOWR

FSMC_NIORD

t

d(NREG-NCE4_1)

h(NCE4_1-NREG)

FSMC_NREG

FSMC_NWE

t

d(NOE-NCE4_1)

d(NCE4_1-NOE)

w(NOE)

FSMC_NOE

t

su(D-NOE)

h(NOE-D)

FSMC_D[15:0]⁽¹⁾

FSMC_NWAIT

t

d(NOE-NWAITH)

t

d(NOE-NWAITL)

d(NWAIT-NOE)

(PWAITEN = 1b)

ai14897

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

73/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 33. PC-card controller timing for attribute memory write access

FSMC_NCE4_1

FSMC_NCE4_2

High

t

v(NCE4_1-A)

h(NCE4_1-AI)

FSMC_A[10:0]

t

d(NIORD-NCE4_1)

d(NIOWR-NCE4_1)

h(NCE4_1-NIORD)

h(NCE4_1-NIOWR)

FSMC_NIOWR

FSMC_NIORD

t

d(NREG-NCE4_1)

h(NCE4_1-NREG)

FSMC_NREG

t

d(NCE4_1-NWE)

w(NWE)

FSMC_NWE

t

d(NWE-NCE4_1)

FSMC_NOE

t

v(NWE-D)

h(NCE4_1-D)

FSMC_D[7:0](1)

t

d(NWE-NWAITH)

t

d(NWE-NWAITl)

d(NWAIT-NWE)

FSMC_NWAIT

(PWAITEN = 1b)

ai14898

1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).

74/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 34. PC-card controller timing for I/O space read access

FSMC_NCE4_1

t

h(NCE4_1-AI)

v(NCEx-A)

FSMC_A[10:0]

FSMC_NCE4_2

(1)

assumes same level as FSMC_NIOS16

t

ELIWL

FSMC_NREG

FSMC_NWE

FSMC_NOE

FSMC_NIOWR

t

w(NIORD)

t

d(NCE4_1-NIORD)

FSMC_NIORD

t

su(D-NIORD)

h(NIORD-D)

(2)

FSMC_D[15:0]

t

d(NCE4_1-NIOIS16)

(3)

t

AVISL/H

FSMC_NIOIS16

ai14899

1. FSMC_NCE4_2 is high independently of FSMC_NIOIS16 if the AHB transfer is for one byte.

2. Only data bits 0...7 are read (bits 8...15 are disregarded) if FSMC_NIOIS16 is high.

3. The CF card asserts FSMC_NIOIS16 after t_AVISL/H

.

4. FSMC_NWAIT not shown but behaves as in the previous figures.

75/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 35. PC-card controller timing for I/O space write access

FSMC_NCE4_1

FSMC_A[10:0]

FSMC_NCE4_2

t

h(NCE4_1-AI)

v(NCEx-A)

(1)

assumes same level as FSMC_NIOS16

FSMC_NREG

FSMC_NWE

FSMC_NOE

FSMC_NIORD

t

d(NCE4_1-NIOWR)

w(NIOWR)

FSMC_NIOWR

ATTxHIZ =1

t

h(NIOWR-D)

v(NIOWR-D)

(2)

FSMC_D[15:0]

(3)

t

AVISL/H

t

d(NCE4_1-NIOIS16)

FSMC_NIOIS16

ai14900

1. FSMC_NCE4_2 is high independently of FSMC_NIOIS16 if the AHB transfer is for one byte.

2. Only data bits 0...7 are driven (bits 8...15 remains HiZ) if FSMC_NIOIS16 is high.

3. The CF card asserts FSMC_NIOIS16 after t_AVISL/H

.

4. FSMC_NWAIT not shown but behaves as in the previous figures.

76/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

(1)

Table 38. Switching characteristics for CF read and write cycles

Timing

Symbol

Parameter

Unit

Min

Max

FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y

= 0...10)

t_v(NCEx-A)

-

TBD

ns

t_{v(NCE4_1-A)}

FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid

(y = 0...10)

FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid

(x = 0...10)

t_h(NCEx-AI)

TBD

-

ns

t_{h(NCE4_1-AI)}

FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax

invalid (x = 0...10)

t_d(NREG-NCEx)

FSMC_NCEx low to FSMC_NREG valid

-

TBD

ns

t_{d(NREG-NCE4_1)}FSMC_NCE4_1 low to FSMC_NREG valid

t_h(NCEx-NREG)FSMC_NCEx high to FSMC_NREG invalid

t_{h(NCE4_1-NREG)}FSMC_NCE4_1 high to FSMC_NREG invalid

t_{d(NIORD-NCEx)}FSMC_NCEx low to FSMC_NIORD valid

t_{d(NIORD-NCE4_1)}FSMC_NCE4_1 low to FSMC_NIORD valid

t_{h(NCEx-NIORD)}FSMC_NCEx high to FSMC_NIORD invalid

t_{h(NCE4_1-NIORD)}FSMC_NCE4_1 high to FSMC_NIORD invalid

t_{d(NIOWR-NCEx)}FSMC_NIOWR valid to FSMC_NCEx low

t_{d(NIOWR-NCE4_1)}FSMC_NIOWR valid to FSMC_NCE4_1 low

t_{h(NCEx-NIOWR)}FSMC_NCEx high to FSMC_NIOWR invalid

t_{h(NCE4_1-NIOWR)}FSMC_NCE4_1 high to FSMC_NIOWR invalid

TBD

-

TBD

-

TBD

t_su(D-NIORD)

t_d(NIORD-D)

t_d(D-NWE)

FSMC_D[15:0] valid before FSMC_NIORD high

FSMC_D[15:0] valid after FSMC_NIORD high

FSMC_D[15:0] valid before FSMC_NWE high

TBD

-

ns

-

t_{d(NCE4_1-NIOWR)}FSMC_NCE4_1 low to FSMC_NIOWR valid

TBD

-

t_w(NIOWR)

FSMC_NIOWR low width

TBD

-

t_v(NIOWR-D)

t_h(NIOWR-D)

FSMC_NIOWR low to FSMC_D[15:0] valid

FSMC_NIOWR high to FSMC_D[15:0] invalid

TBD

-

TBD

-

t_{d(NCE4_1-NIOIS16)}FSMC_NIOS16 valid after FSMC_NCE4_1 low

TBD

t_{d(NCE4_1-NOE)}

t_w(NOE)

FSMC_NCE4_1 low to FSMC_NOE low

FSMC_NOE low width

-

TBD

TBD cycles/ns

t_d(NOE-NCEx)

FSMC_NOE high to FSMC_NCEx high

FSMC_NOE high to FSMC_NCE4_1 high

TBD

t_{d(NOE-NCE4_1}

t_{d(NOE-NWAITL)}

t_{d(NOE-NWAITH)}

t_d(NWAIT-NOE)

t_su(D-NOE)

FSMC_NWAIT low after FSMC_NOE low⁽²⁾

FSMC_NWAIT high after FSMC_NOE low⁽²⁾

FSMC_NOE high after FSMC_NWAIT high

FSMC_D[15:0] valid data before FSMC_NOE high

FSMC_D[15:0] valid data after FSMC_NOE high

TBD

-

ns

t_h(NOE-D)

77/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Table 38. Switching characteristics for CF read and write cycles (continued)

Timing

Symbol

Parameter

Unit

Min

Max

t_d(NCEx-NWE)

t_w(NWE)

FSMC_NCEx low to FSMC_NWE low

FSMC_NWE low width

-

TBD

ns

TBD

TBD cycles/ns

t_d(NWE-NCEx)

FSMC_NWE high to FSMC_NCEx high

FSMC_NWE high to FSMC_NCE4_1 high

TBD

ns

t_{d(NWE-NCE4_1)}

t_{d(NCE4_1-NWE)}

t_{d(NWE-NWAITL)}

t_{d(NWE-NWAITH)}

t_d(NWAIT-NWE)

t_v(NWE-D)

FSMC_NCE4_1 low to FSMC_NWE low

FSMC_NWAIT low after FSMC_NWE low⁽²⁾

FSMC_NWAIT high after FSMC_NWE low⁽²⁾

FSMC_NWE high after FSMC_NWAIT high

FSMC_NWE low to FSMC_D[15:0] valid

FSMC_NWE high to FSMC_D[15:0] invalid

FSMC_NCE4_1 high to FSMC_D[15:0] invalid

FSMC_NIORD low width

TBD

ns

TBD

-

TBD

-

t_h(NWE-D)

TBD

t_{h(NCE4_1-D)}

t_w(NIORD)

t_ELIWL

FSMC_NCEx setup before FSMC_NWE low

Address valid to FSMC_NIOIS16 valid

t_AVISL/H

35

1. TBD = to be determined.

2. When one or more wait states are inserted. If no wait state needs inserted, NWAIT should be kept high or

the wait feature should be disabled (WAITEN=0) in the control register.

78/118

STM32F103xC, STM32F103xD, STM32F103xE

Figure 36. NAND controller timing for read access

Electrical characteristics

FSMC_NCEx

t

v(NCEx-A)

h(NCEx-AI)

ALE (FSMC_A17)

CLE (FSMC_A16)

FSMC_NWE

t

d(NCEx-NOE)

t

FSMC_NOE (NRE)

FSMC_D[15:0]

t

su(D-NOE)

h(NOE-D)

t

d(NOE-NWAITL)

t

d(NOE-NWAITH)

d(NWAIT-NOE)

FSMC_NWAIT

(PWAITEN = 1b)

ai14901

Figure 37. NAND controller timing for write access

FSMC_NCEx

t

h(NCEx-AI)

v(NCEx-A)

ALE (FSMC_A17)

CLE (FSMC_A16)

t

d(NCEx-NWE)

FSMC_NWE

t

d(NWE-NCEx)

FSMC_NOE (NRE)

MEMxHIZ =1

t

v(NWE-D)

h(NWE-D)

FSMC_D[15:0]

t

d(NWE-NWAITH)

t

d(NWE-NWAITL)

d(NWAIT-NWE)

FSMC_NWAITW

(PWAITEN = 1b)

ai14902

79/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 38. NAND controller timing for common memory read access

FSMC_NCEx

t

iv(NCEx-AI)

v(NCEx-A)

ALE (FSMC_A17)

CLE (FSMC_A16)

FSMC_NWE

t

w(NOE)

FSMC_NOE

t

su(D-NOE)

h(NOE-D)

FSMC_D[15:0]

FSMC_NWAIT

t

d(NOE-NWAITH)

t

d(NWAIT-NOE)

d(NOE-NWAITL)

(PWAITEN = 1b)

ai14912

Figure 39. NAND controller timing for common memory write access

FSMC_NCEx

t

h(NCEx-AI)

v(NCEx-A)

ALE (FSMC_A17)

CLE (FSMC_A16)

t

w(NWE)

d(NWE-NCEx)

FSMC_NWE

FSMC_NOE

MEMxHIZ =1

t

d(D-NWE)

t

d(NWE-D)

h(NWE-D)

FSMC_D[15:0]

t

d(NWE-NWAITH)

d(NWAIT-NWE)

t

d(NWE-NWAITL)

FSMC_NWAIT

(PWAITEN = 1b)

ai14913

80/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

(1)

Table 39. Switching characteristics for NAND Flash read and write cycles

Timing

Symbol

Parameter

Unit

Min

Max

t_v(NCEx-A)

t_h(NCEx-AI)

FSMC_NCEx low (x = 2/3) to FSMC_Ay valid (y = 16/17)

-

TBD

ns

FSMC_NCEx high (x = 2/3) to FSMC_Ax invalid (x =

16/17)

TBD

-

t_d(D-NWE)

t_d(NWE-D)

t_d(NCEx-NOE)

t_w(NOE)

FSMC_D[15:0] valid before FSMC_NWE high

FSMC_D[15:0] valid after FSMC_NWE high

FSMC_NCEx low to FSMC_NOE low

FSMC_NOE low width

TBD

-

ns

TBD

TBD cycles/ns

t_h(NWE-D)

FSMC_NWE high to FSMC_D[15:0] invalid

ns

t_{d(NOE-NWAITL)}FSMC_NWAIT low after FSMC_NOE low⁽²⁾

t_{d(NOE-NWAITH)}FSMC_NWAIT high after FSMC_NOE low⁽²⁾

TBD

-

t_d(NWAIT-NOE)

t_su(D-NOE)

FSMC_NOE high after FSMC_NWAIT high

FSMC_D[15:0] valid data before FSMC_NOE high

FSMC_D[15:0] valid data after FSMC_NOE high

FSMC_NCEx low to FSMC_NWE low

FSMC_NWE low width

-

ns

-

t_h(NOE-D)

t_d(NCEx-NWE)

t_w(NWE)

TBD

TBD cycles/ns

ns

t_d(NWE-NCEx)

FSMC_NWE high to FSMC_NCEx high

t_{d(NWE-NWAITL)}FSMC_NWAIT low after FSMC_NWE low⁽²⁾

t_{d(NWE-NWAITH)}FSMC_NWAIT high after FSMC_NWE low⁽²⁾

t_d(NWAIT-NWE)FSMC_NWE high after FSMC_NWAIT high

TBD

ns

TBD

-

TBD

-

t_v(NWE-D)

t_h(NWE-D)

FSMC_NWE low to FSMC_D[15:0] valid

FSMC_NWE high to FSMC_D[15:0] invalid

TBD

1. TBD = to be determined.

2. When one or more wait states are inserted. If no wait state needs inserted, NWAIT should be kept high or

the wait feature should be disabled (WAITEN=0) in the control register.

81/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.11

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the

device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

●

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.

●

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 40. They are based on the EMS levels and classes

defined in application note AN1709.

Table 40. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD= 3.3 V, T_A= +25 °C,

f_HCLK=48 MHz

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

V_FESD

2B

4A

conforms to IEC 1000-4-2

Fast transient voltage burst limits to be

applied through 100 pF on V_DDand V_SS

pins to induce a functional disturbance

V_DD= 3.3 V, T_A= +25 °C,

f_HCLK= 48 MHz

conforms to IEC 1000-4-4

V_EFTB

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

●

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

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STM32F103xC, STM32F103xD, STM32F103xE

Electromagnetic Interference (EMI)

Electrical characteristics

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J

1752/3 standard which specifies the test board and the pin loading.

(1)

Table 41. EMI characteristics

Max vs. [f_HSE/f_HCLK

]

Monitored

Symbol Parameter

Conditions

Unit

frequency band

8/48 MHz 8/72 MHz

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

TBD

V_DD= 3.3 V, T_A= 25 °C,

LQFP100 package

compliant with SAE J

1752/3

dBµV

-

S_EMI

Peak level

1. TBD = to be determined.

5.3.12

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 42. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class Maximum value⁽¹⁾Unit

T_A= +25 °C

conforming to

JESD22-A114

Electrostatic discharge

voltage (human body model)

V_ESD(HBM)

2

2000

500

V

Electrostatic discharge

V_ESD(CDM)voltage (charge device

model)

T_A= +25 °C

conforming to

JESD22-C101

II

1. Values based on characterization results, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

●

A supply overvoltage is applied to each power supply pin

●

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

83/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 43. Electrical sensitivities

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T_A= +105 °C conforming to JESD78A

II level A

5.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 44 are derived from tests

performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL

compliant.

Table 44. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL

Input low level voltage⁽¹⁾

–0.5

0.8

V

Standard IO input high level

voltage⁽¹⁾

2

V_DD+0.5

5.5V

TTL ports

V_IH

IO FT⁽²⁾input high level

voltage⁽¹⁾

V_IL

Input low level voltage⁽¹⁾

Input high level voltage⁽¹⁾

–0.5

0.35 V_DD

V_DD+0.5

CMOS ports

V

V_IH

0.65 V_DD

Standard IO Schmitt trigger

voltage hysteresis⁽³⁾

200

mV

V_hys

IO FT Schmitt trigger voltage

hysteresis⁽³⁾

(4)

5% V_DD

V_SS≤V_IN≤V_DD

Standard I/Os

1

3

I_lkg

Input leakage current ⁽⁵⁾

µA

V_IN= 5 V

I/O FT

Weak pull-up equivalent

resistor⁽⁶⁾

R_PU

V_IN= V_SS

V_IN= V_DD

30

40

50

kΩ

Weak pull-down equivalent

resistor⁽⁶⁾

R_PD

C_IO

40

5

kΩ

I/O pin capacitance

pF

1. Values based on characterization results, and not tested in production.

2. FT = Five-volt tolerant.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. With a minimum of 100 mV.

5. Leakage could be higher than max. if negative current is injected on adjacent pins.

6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable

PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).

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STM32F103xC, STM32F103xD, STM32F103xE

Output driving current

Electrical characteristics

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink

+20 mA (with a relaxed V ).

OL

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 5.2:

●

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

I

(see Table 7).

VDD

●

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

I

(see Table 7).

VSS

Output voltage levels

Unless otherwise specified, the parameters given in Table 45 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 9. All I/Os are CMOS and TTL compliant.

Table 45. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)

V_OL

0.4

TTL port

I_IO= +8 mA

V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(2)

2.7 V < V_DD< 3.6 V

V_OH

V_DD–0.4

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)

V_OL

0.4

1.3

0.4

CMOS port

I_IO=+ 8mA

V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(2)

2.7 V < V_DD< 3.6 V

V_OH

2.4

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)(3)

V_OL

I_IO= +20 mA

2.7 V < V_DD< 3.6 V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(2)(3)

V_OH

V_DD–1.3

V_DD–0.4

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)(3)

V_OL

I_IO= +6 mA

2 V < V_DD< 2.7 V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(2)(3)

V_OH

1. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 7

and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in

Table 7 and the sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

3. Based on characterization data, not tested in production.

85/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 40 and

Table 46, respectively.

Unless otherwise specified, the parameters given in Table 46 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 9.

(1)

Table 46. I/O AC characteristics

MODEx[1:0]

Symbol

Parameter

Conditions

Min Max Unit

bit value⁽¹⁾

f_max(IO)outMaximum frequency⁽²⁾C_L= 50 pF, V_DD= 2 V to 3.6 V

2

MHz

ns

Output high to low

t_f(IO)out

125⁽³⁾

10

level fall time

C_L= 50 pF, V_DD= 2 V to 3.6 V

Output low to high

t_r(IO)out

125⁽³⁾

10

level rise time

f_max(IO)outMaximum frequency⁽²⁾C_L= 50 pF, V_DD= 2 V to 3.6 V

MHz

ns

Output high to low

t_f(IO)out

25⁽³⁾

01

level fall time

C_L= 50 pF, V_DD= 2 V to 3.6 V

Output low to high

t_r(IO)out

25⁽³⁾

level rise time

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

F_max(IO)outMaximum frequency⁽²⁾C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

50

30

MHz

20

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

Output high to low

level fall time

5⁽³⁾

8⁽³⁾

12⁽³⁾

5⁽³⁾

8⁽³⁾

12⁽³⁾

11

t_f(IO)out

t_r(IO)out

t_EXTIpw

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

ns

Output low to high

level rise time

Pulse width of

external signals

detected by the EXTI

controller

-

10

ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a

description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 40.

3. Values based on design simulation and validated on silicon, not tested in production.

86/118

STM32F103xC, STM32F103xD, STM32F103xE

Figure 40. I/O AC characteristics definition

Electrical characteristics

90%

50%

10 %

50%

90%

10%

t

EXTERNAL

OUTPUT

ON 50pF

t

r(IO)out

T

Maximum frequency is achieved if (t + t ) £ 2/3)T and if the duty cycle is (45-55%)

r

f

when loaded by 50pF

ai14131

5.3.14

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, R (see Table 44).

PU

Unless otherwise specified, the parameters given in Table 47 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 9.

Table 47. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL(NRST)NRST Input low level voltage

V_IH(NRST)NRST Input high level voltage

–0.5

2

0.8

V

V_DD+0.5

NRST Schmitt trigger voltage

V_hys(NRST)

hysteresis

200

40

R_PU

Weak pull-up equivalent resistor⁽¹⁾

V_IN= V_SS

30

50

kΩ

ns

V_F(NRST)NRST Input filtered pulse⁽²⁾

100

V_NF(NRST)NRST Input not filtered pulse⁽²⁾

300

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

to the series resistance must be minimum (~10% order).

2. Values guaranteed by design, not tested in production.

87/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 41. Recommended NRST pin protection

V

DD

External

reset circuit

R

PU

Internal Reset

NRST

FILTER

0.1 µF

STM32F101xx

ai14132b

5. The reset network protects the device against parasitic resets.

6. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 47. Otherwise the reset will not be taken into account by the device.

5.3.15

TIM timer characteristics

The parameters given in Table 48 are guaranteed by fabrication.

Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

(1)

Table 48. TIMx characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

t_TIMxCLK

ns

1

t_res(TIM)

Timer resolution time

f_TIMxCLK= 72 MHz 13.9

0

f_TIMxCLK/2

36

MHz

Timer external clock

frequency on CH1 to CH4

f_EXT

f_TIMxCLK= 72 MHz

0

MHz

Res_TIM

Timer resolution

16

bit

16-bit counter clock period

when internal clock is

selected

t_TIMxCLK

1

65536

t_COUNTER

f_TIMxCLK= 72 MHz 0.0139

910

µs

t_TIMxCLK

s

65536 × 65536

59.6

t_{MAX_COUNT}

Maximum possible count

f_TIMxCLK= 72 MHz

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

88/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.3.16

Communications interfaces

I²C interface characteristics

Unless otherwise specified, the parameters given in Table 49 are derived from tests

performed under ambient temperature, f

frequency and V supply voltage conditions

PCLK1

DD

summarized in Table 9.

2

I

The STM32F103xC performance line C interface meets the requirements of the standard

2

I C communication protocol with the following restrictions: the I/O pins SDA and SCL are

mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected

between the I/O pin and V is disabled, but is still present.

DD

2

The I C characteristics are described in Table 49. Refer also to Section 5.3.13: I/O port

for more details on the input/output alternate function characteristics (SDA

characteristics

and SCL)

.

2

Table 49. I C characteristics

Standard mode I²C⁽¹⁾

Fast mode I²C⁽¹⁾⁽²⁾

Symbol

Parameter

Unit

Min

Max

Min

Max

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

SCL clock high time

SDA setup time

4.7

4.0

1.3

0.6

µs

250

0⁽³⁾

100

0⁽⁴⁾

SDA data hold time

900⁽³⁾

300

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

1000

300

20 + 0.1C_b

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

Start condition hold time

20 + 0.1C_b

300

t_h(STA)

t_su(STA)

4.0

4.7

4.0

4.7

0.6

1.3

µs

Repeated Start condition

setup time

t_su(STO)

Stop condition setup time

μs

Stop to Start condition time

(bus free)

t_w(STO:STA)

Capacitive load for each bus

line

C_b

400

pF

Values based on standard I²C protocol requirement, not tested in production.

1.

2. f_PCLK1must be higher than 2 MHz to achieve the maximum standard mode I²C frequency. It must be

higher than 4 MHz to achieve the maximum fast mode I²C frequency.

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

period of SCL signal.

3.

4.

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

89/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

2

Figure 42. I C bus AC waveforms and measurement circuit

V

DD

STM32F103xx

SDA

4.7kΩ

100Ω

2

I C bus

SCL

START REPEATED

START

t

su(STA)

SDA

t

r(SDA)

f(SDA)

su(SDA)

t

su(STA:STO)

STOP

t

w(SCKL)

h(SDA)

h(STA)

SCL

t

su(STO)

r(SCK)

t

f(SCK)

w(SCKH)

ai14149b

Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

1.

(1)(2)(3)

Table 50. SCL frequency (f

f_SCL(kHz)

= 36 MHz.,V_DD= 3.3 V)

PCLK1

I2C_CCR value

R_P= 4.7 kΩ

400

TBD

300

200

100

50

20

1. TBD = to be determined.

2. R_P= External pull-up resistance, f_SCL= I²C speed,

3. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the

tolerance on the achieved speed 2%. These variations depend on the accuracy of the external

components used to design the application.

90/118

STM32F103xC, STM32F103xD, STM32F103xE

I²S - SPI characteristics

Electrical characteristics

2

Unless otherwise specified, the parameters given in Table 51 for SPI or in Table 52 for I S

are derived from tests performed under ambient temperature, f

frequency and V

PCLKx

DD

supply voltage conditions summarized in Table 9.

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate

2

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).

(1) (2)

Table 51. SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Master mode

Slave mode

0

18

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

8

(3)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

t_C(SCK)

(3)

t_h(NSS)

0.5t_C(SCK)

(3)

t_w(SCKH)

t_w(SCKL)

SCK high and low time Master mode, f_PCLK= 36 MHz, presc = 4

50

60

(3)

Master mode

Data input setup time

10

t_su(MI)

t_su(SI)

(3)

Slave mode

5

Master mode, f_PCLK= 36 MHz, presc = 4

15

(3)

Slave mode, f_PCLK= 36 MHz, presc = 4

Data input hold time

5

t_h(MI)

t_h(SI)

(3)

Master mode, f_PCLK= TBD

TBD⁽⁴⁾

Slave mode, f_PCLK= TBD

TBD⁽⁴⁾

ns

Slave mode, f_PCLK= 36 MHz, presc = 4

Data output access time

0

5

60

(3)(5)

(3)(6)

t_a(SO)

Slave mode, f_PCLK= TBD

TBD

t_dis(SO)

Data output disable time Slave mode

Slave mode (after enable edge),

f_PCLK= 36 MHz, presc = 4

Data output valid time

30

TBD

10

(3)(1)

t_v(SO)

f_PCLK= TBD

Master mode (after enable edge),

f_PCLK= 36 MHz, presc = 4

(3)(1)

(3)

t_v(MO)

Data output valid time

f_PCLK= TBD

TBD

30

TBD

t_h(SO)

Slave mode (after enable edge)

Data output hold time

(3)

t_h(MO)

Master mode (after enable edge)

10

1. TBD = to be determined.

2. Remapped SPI1 characteristics to be determined.

3. Values based on design simulation and/or characterization results, and not tested in production.

4. Depends on f_PCLK. For example, if f_PCLK= 8MHz, then t_PCLK= 1/f_PLCLK=125 ns and t_v(MO)= 255 ns.

5. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

6. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

91/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 43. SPI timing diagram - slave mode and CPHA = 0

NSS input

t

h(NSS)

SU(NSS)

c(SCK)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

v(SO)

r(SCK)

f(SCK)

h(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134

(1)

Figure 44. SPI timing diagram - slave mode and CPHA = 1

NSS input

t

SU(NSS)

t

c(SCK)

h(NSS)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

92/118

STM32F103xC, STM32F103xD, STM32F103xE

Figure 45. SPI timing diagram - master mode

Electrical characteristics

(1)

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

INPUT

MSBIN

t

BIT6 IN

LSB IN

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTPUT

t

v(MO)

h(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

93/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

2

(1)

Table 52. I S characteristics

Symbol

Parameter

Conditions

Master

Min

Max

Unit

TBD

0

TBD

f_CK

I²S clock frequency

MHz

1/t_c(CK)

Slave

t_r(CK)

t_f(CK)

capacitive load

C_L= 50 pF

I²S clock rise and fall time

TBD

(2)

t_v(WS)

WS valid time

WS hold time

WS setup time

WS hold time

Master

Slave

TBD

(2)

t_h(WS)

(2)

t_su(WS)

(2)

t_h(WS)

Slave

(2)

t_w(CKH)

t_w(CKL)

Master f_PCLK= TBD,

presc = TBD

CK high and low time

Data input setup time

Data input hold time

TBD

(2)

t_{su(SD_MR)}

t_{su(SD_SR)}

Master receiver

Slave receiver

TBD

(2)(3)

t_{h(SD_MR)}

t_{h(SD_SR)}

Master receiver

Slave receiver

TBD

ns

(2)

t_{h(SD_MR)}

t_{h(SD_SR)}

Master f_PCLK= TBD

Slave f_PCLK= TBD

TBD

Slave transmitter

(after enable edge)

TBD

(2)(3)

(2)

t_{v(SD_ST)}

t_{h(SD_ST)}

t_{v(SD_MT)}

t_{h(SD_MT)}

Data output valid time

Data output hold time

Data output valid time

Data output hold time

f_PCLK= TBD

Slave transmitter

(after enable edge)

TBD

Master transmitter

(after enable edge)

TBD

(2)(3)

(2)

f_PCLK= TBD

TBD

Master transmitter

(after enable edge)

1. TBD = to be determined.

2. Data based on design simulation and/or characterization results, not tested in production.

3. Depends on f_PCLK. For example, if f_PCLK=8 MHz, then T_PCLK= 1/f_PLCLK=125 ns.

94/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

2

(1)

Figure 46. I S slave timing diagram

t

c(CK)

CPOL = 0

CPOL = 1

t

w(CKL)

h(WS)

w(CKH)

WS input

t

h(SD_ST)

t

v(SD_ST)

su(WS)

SD

transmit

MSB transmit

MSB receive

Bitn transmit

LSB transmit

t

su(SD_SR)

h(SD_SR)

Bit1 receive

LSB receive

SD

receive

ai14881

1. Measurement points are done at CMOS levels: 0.3 × V_DDand 0.7 × V_DD

.

2

(1)

Figure 47. I S master timing diagram

t

f(CK)

r(CK)

t

c(CK)

CPOL = 0

t

w(CKH)

CPOL = 1

t

v(WS)

h(WS)

w(CKL)

WS output

t

h(SD_MT)

t

v(SD_MT)

su(SD_MR)

SD

receive

MSB receive

Bitn receive

LSB receive

t

h(SD_MR)

Bitn transmit

MSB transmit

LSB transmit

SD

transmit

ai14884

1. Data based on design simulation and/or characterization results, not tested in production.

95/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 53 are derived from tests

performed under ambient temperature, f

frequency and V supply voltage conditions

PCLKx

DD

summarized in Table 9.

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate

function characteristics (D[7:0], CMD, CK).

Figure 48. SDIO high-speed mode

t

r

f

t

C

t

W(CKH)

W(CKL)

CK

t

OV

OH

D, CMD

(output)

t

ISU

IH

D, CMD

(input)

ai14887

Figure 49. SD default mode

CK

t

OVD

OHD

D, CMD

(output)

ai14888

96/118

STM32F103xC, STM32F103xD, STM32F103xE

Table 53. SD / MMC characteristics

Electrical characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Clock frequency in data transfer

mode

f_PP

C_L≤ 30 pF

0

TBD

MHz

t_W(CKL)

Clock low time

Clock high time

Clock rise time

Clock fall time

C_L≤ 30 pF

TBD

t_W(CKH)

ns

t_r

t_f

TBD

t_C

CMD, D inputs (referenced to CK)

t_ISU

t_IH

Input setup time

Input hold time

C_L≤ 30 pF

TBD

ns

CMD, D outputs (referenced to CK) in MMC and SD HS mode

t_OV

t_OH

Output valid time

Output hold time

C_L≤ 30 pF

TBD

CMD, D outputs (referenced to CK) in SD default mode⁽¹⁾

t_OVD

t_OHD

Output valid default time

Output hold default time

C_L≤ 30 pF

ns

TBD

1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.

USB characteristics

The USB interface is USB-IF certified (Full Speed).

Table 54. USB startup time

Symbol

t_STARTUP

Parameter

Max

Unit

µs

USB transceiver startup time

1

97/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 55. USB DC electrical characteristics

Symbol

Parameter

Conditions

Min.⁽¹⁾

Max.⁽¹⁾Unit

Input levels

V_USB

USB voltage⁽²⁾

Within V_DDvoltage range

I(USBDP, USBDM)

3.0⁽³⁾

0.2

3.6

V

(4)

V_DI

Differential input sensitivity

(4)

V_CM

Differential common mode range Includes V_DIrange

Single ended receiver threshold

0.8

2.5

2.0

(4)

V_SE

1.3

Output levels

V_OL

V_OH

Static output level low

Static output level high

R_Lof 1.5 kΩto 3.6 V⁽⁵⁾

0.3

3.6

V

(5)

R_Lof 15 kΩto V_SS

2.8

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled

up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.

3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical

characteristics which are degraded in the 2.7-to-3.0 V V_DDvoltage range.

4. Guaranteed by characterization, not tested in production.

R_Lis the load connected on the USB drivers

5.

Figure 50. USB timings: definition of data signal rise and fall time

Crossover

points

Differential

Data Lines

V

CR S

V

SS

t

r

f

ai14137

Table 56.

Symbol

USB: full-speed electrical characteristics

Driver characteristics⁽¹⁾

Parameter

Conditions

Min

Max

Unit

t_r

t_f

Rise time⁽²⁾

Fall Time⁽²⁾

C_L= 50 pF

t_r/t_f

4

20

ns

%

V

t_rfm

V_CRS

Rise/ fall time matching

90

1.3

110

2.0

Output signal crossover voltage

1. Guaranteed by characterization, not tested in production.

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

2.

5.3.17

CAN (controller area network) interface

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate

function characteristics (CANTX and CANRX).

98/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.3.18

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 57 are derived from tests

performed under ambient temperature, f

frequency and V

supply voltage

PCLK2

DDA

conditions summarized in Table 9.

Note:

It is recommended to perform a calibration after each power-up.

Table 57. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDA

V_REF+

f_ADC

ADC power supply

2.4

0.6

3.6

V_DDA

14

V

Positive reference voltage

ADC clock frequency

MHz

(1)

Sampling rate

0.05

1

MHz

f_S

823

17

kHz

(1)

External trigger frequency

f_ADC= 14 MHz

f_TRIG

1/f_ADC

0 (V_SSAor V_REF-

tied to ground)

Conversion voltage range⁽²⁾

V_REF+

V

V_AIN

(1)

R_AIN

External input impedance

Sampling switch resistance

See Equation 1 and Table 58

kΩ

(1)

1

R_ADC

Internal sample and hold

capacitor

(1)

5

pF

C_ADC

5.9

83

µs

1/f_ADC

µs

(1)

Calibration time

f_ADC= 14 MHz

t_CAL

0.214

Injection trigger conversion

latency

(1)

t_lat

3⁽³⁾

0.143

2⁽³⁾

1/f_ADC

µs

Regular trigger conversion

latency

(1)

f

_ADC= 14 MHz

t_latr

1/f_ADC

µs

0.107

1.5

0

17.1

239.5

1

(1)

Sampling time

Power-up time

f_ADC= 14 MHz

t_S

1/f_ADC

µs

(1)

t_STAB

0

1

18

µs

Total conversion time

(including sampling time)

(1)

f_ADC= 14 MHz

t_CONV

14 to 252 (t_Sfor sampling +12.5 for

successive approximation)

1/f_ADC

1. Guaranteed by design, not tested in production.

2. V_REF+can be internally connected to V_DDAand V_REF-can be internally connected to V_SSA, depending on the package.

Refer to Section 3: Pin descriptions for further details.

3. For external triggers, a delay of 1/f_PCLK2must be added to the latency specified in Table 57.

99/118

Electrical characteristics

Equation 1: R

STM32F103xC, STM32F103xD, STM32F103xE

max formula:

AIN

T_S

R_AIN< --------------------------------------------------------------- – R_ADC

f_ADC× C_ADC× ln(2^{N + 2}

)

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an

error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

(1)

Table 58.

R

max for f

= 14 MHz

AIN

ADC

T_s(cycles)

t_S(µs)

R_AINmax (kΩ)

1.5

0.11

1.2

10

7.5

0.54

0.96

2.04

2.96

3.96

5.11

17.1

13.5

28.5

41.5

55.5

71.5

239.5

19

41

60

80

104

350

1. Data guaranteed by design, not tested in production.

(1)

Table 59. ADC accuracy - limited test conditions

Symbol

Parameter

Test conditions

Typ

Max⁽²⁾

Unit

ET

EO

EG

ED

Total unadjusted error⁽³⁾

Offset error⁽³⁾

f_PCLK2= 56 MHz,

1.3

1

2

1.5

1

f_ADC= 14 MHz, R_AIN< 10 kΩ,

V_DDA= 3 V to 3.6 V

T_A= 25 °C

Gain error⁽³⁾

0.5

0.7

LSB

Differential linearity error⁽³⁾

Measurements made after

ADC calibration

V_REF+= V_DDA

EL

Integral linearity error⁽³⁾

0.8

1.5

1. ADC DC accuracy values are measured after internal calibration.

2. Data based on characterization, not tested in production.

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to

standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 5.3.13 does not

affect the ADC accuracy.

100/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

(1) (2)

Table 60. ADC accuracy

Symbol

Parameter

Test conditions

Typ

Max⁽³⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error⁽⁴⁾

Offset error⁽³⁾

2

5

25

3

f_PCLK2= 56 MHz,

f_ADC= 14 MHz, R_AIN< 10 kΩ,

V_DDA= 2.4 V to 3.6 V

1.5

1

Gain error⁽³⁾

LSB

Measurements made after

ADC calibration

Differential linearity error⁽³⁾

Integral linearity error⁽³⁾

2

1.5

3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V_DD, frequency, V_REFand temperature ranges.

3. Data based on characterization, not tested in production.

4. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to

standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 5.3.13 does not

affect the ADC accuracy.

Figure 51. ADC accuracy characteristics

V

DDA

REF+

[1LSB

=

(or

depending on package)]

IDEAL

4096

E_G

(1) Example of an actual transfer curve

(2) The ideal transfer curve

4095

4094

4093

(3) End point correlation line

(2)

E_T=Total Unadjusted Error: maximum deviation

E_T

between the actual and the ideal transfer curves.

(3)

7

6

5

4

3

2

1

E_O=Offset Error: deviation between the first actual

transition and the first ideal one.

(1)

E_G=Gain Error: deviation between the last ideal

transition and the last actual one.

E_O

E_L

E_D=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

E_L=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

E_D

1 LSB_IDEAL

0

1

2

3

4

5

6

7

4093 4094 4095 4096

V_DDA

V_SSA

ai14395b

101/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 52. Typical connection diagram using the ADC

V

DD

STM32F103xx

V

0.6 V

T

(1)

AIN

(1)

ADC

R

I

AINx

12-bit A/D

conversion

(1)

C

ADC

V

T

1 µA

V

C

L

AIN

0.6 V

AIN

ai14150b

1. Refer to Table 57 for the values of C_AIN, R_AIN, R_ADCand C_ADC

.

2. C_PARASITICmust be added to C_AIN. It represents the capacitance of the PCB (dependent on soldering and

PCB layout quality) plus the pad capacitance (3 pF). A high C_PARASITICvalue will downgrade conversion

accuracy. To remedy this, f_ADCshould be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 53 or Figure 54,

depending on whether V

is connected to V

or not. The 10 nF capacitors should be

REF+

DDA

ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 53. Power supply and reference decoupling (V not connected to V

)

DDA

REF+

STM32F103xx

V

REF+

(see note 1)

1 µF // 10 nF

V

DDA

SSA

1 µF // 10 nF

V

/V

REF–

(see note 1)

ai14388b

1. V_REF+and V_REF–inputs are available only on 100-pin packages.

102/118

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 54. Power supply and reference decoupling (V

connected to V

)

DDA

REF+

STM32F103xx

V

/V

REF+ DDA

(See note 1)

1 µF // 10 nF

V

/V

REF– SSA

(See note 1)

ai14389

1. V_REF+and V_REF–inputs are available only on 100-pin packages.

103/118

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.19

DAC electrical specifications

Table 61. DAC characteristics

Symbol

Parameter

Min Typ

Max⁽¹⁾

Unit

Comments

V_DD33A

V_DD18D

Analog supply voltage

Digital supply voltage

2.4

3.6

2

V

1.6

2.4

0

1.8

V_REF+must always be below

V_DD33A

V_REF+

V_SSA

R_L

Reference supply voltage

Ground

3.6

0

V

Minimum resistive load between

DAC_OUT and V_SSA

Resistive load with buffer ON

5

kΩ

Maximum capacitive load at

DAC_OUT pin.

C_L

Capacitive load

50

pF

V

DAC_OUT Lower DAC_OUT voltage with

min buffer ON

It gives the maximum output

excursion of the DAC

0.2

it corresponds to 12-bit input

code (0E0)h to (F1C)h @ V_REF+

= 3.6 V and (155)h and (EAB)h

@ V_REF+= 2.4 V

DAC_OUT Higher DAC_OUT voltage with

V_REF+– 0.2 V

V

max

buffer ON

With no load, middle code

(800)H on the inputs

425

500

600

µA

DAC DC current consumption

in quiescent mode (Standby

With no load, worst code

(F1C)H @ V_REF+= 3.6 V in

terms of DC consumption on the

inputs

I_DD

mode) (in V_DD18D+V_DD33A

V_REF+

+

700

µA

)

DAC DC current consumption

in Power Down mode (in

5

350

200

V_DD18D+V_DD33A+V_REF+

)

I_DDQ

nA With no load.

DAC DC current consumption

in Power Down mode (in

5

V_DD33A+V_REF+

)

Differential non linearity

(Difference between two

consecutive code-1LSB)

Given for the DAC in 10-bit

configuration (B1=B0=0 always)

DNL

INL

0.5

LSB

Integral non linearity (difference

between measured value at

Code i and the value at Code i

on a line drawn between Code

0 and last Code 1023)

Given for the DAC in 10-bit

configuration (B1=B0=0 always)

1

Given for the DAC in 10-bit

configuration (B1=B0=0 always)

Offset error

10

3

mV

LSB

%

(difference between measured

value at Code (800)H and the

ideal value = V_REF+/2

Offset

Given for the DAC in 10-bit @

V_REF+= 3.6 V

Given for the DAC in 10-bit

configuration (B1=B0=0 always)

Gain error Gain error

0.5

104/118

STM32F103xC, STM32F103xD, STM32F103xE

Table 61. DAC characteristics (continued)

Electrical characteristics

Comments

Symbol

Parameter

Min Typ

Max⁽¹⁾

Unit

Amplifier

gain

Gain of the amplifier in open

loop

80

85

dB with a 5 kΩ load (worst case)

Settling time (full scale: for an

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final value

1LSB

C_LOAD≤ 50 pF,

µs

t_SETTLING

3

4

1

R_LOAD≥ 5 kΩ

Max frequency for a correct

DAC_OUT change when small

variation in the input code (from

code i to i+1LSB)

Update

rate

C_LOAD≤ 50 pF,

MS/s

R_LOAD≥ 5 kΩ

C_LOAD≤ 50 pF,

R_LOAD≥ 5 kΩ

input code between lowest and

Wakeup time from off state

(PDV18 from 1 to 0)

t_WAKEUP

6.5

10

µs

highest possible ones.

Power supply rejection ratio (to

V_DD33A) (static DC

PSRR+

–67

–40

dB No R_LOAD, C_LOAD= 50 pF

measurement

1. Guaranteed by characterization, not tested in production.

5.3.20

Temperature sensor characteristics

Table 62. TS characteristics

Symbol Parameter

Conditions

Min

Typ

Max

Unit

(1)

T_L

V_SENSElinearity with temperature

°C

1

4.3

2

4.6

1.52

10

Avg_Slope⁽¹⁾

Average slope

Voltage at 25 °C

Startup time

4.0

1.34

4

mV/°C

V

(1)

V₂₅

1.43

(2)

t_START

µs

ADC sampling time when reading the

temperature

(3)(2)

T_{S_temp}

2.2

17.1

µs

1. Guaranteed by characterization, not tested in production.

2. Data guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

105/118

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

6

Package characteristics

6.1

Package mechanical data

®

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These packages have a Lead-free second-level interconnect. The category of

second-level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

106/118

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

Figure 55. LQFP144, 20 x 20 mm, 144-pin low-profile quad

Figure 56. Recommended

(1)

(1)(2)

flat package outline

footprint

Seating plane

C

A

A2 A1

c

b

0.25 mm

gage plane

ccc

C

D

k

0.5

0.35

D1

A1

D3

L

108

73

22.6

19.9

L1

72

109

19.9

1.35

17.85

22.6

E1

E

E3

ai14905b

144

37

Pin 1

identification

1

36

e

ME_1A

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 63. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Typ

Min

Max

Typ

Min

Max

A

A1

A2

b

1.60

0.15

0.063

0.0059

0.0571

0.0106

0.0079

0.874

0.05

1.35

0.002

0.0531

0.0067

0.0035

0.8583

0.7795

1.40

0.22

1.45

0.0551

0.0087

0.17

0.27

c

0.09

0.20

D

22.00

20.00

17.50

22.00

20.00

17.50

0.50

21.80

19.80

22.20

20.20

0.8661

0.7874

0.689

D1

D3

E

0.7953

21.80

19.80

22.20

20.20

0.8661

0.7874

0.689

0.8583

0.7795

0.874

E1

E3

e

0.7953

0.0197

0.0236

0.0394

3.5°

L

0.60

0.45

0.75

7°

0.0177

0.0295

7°

L1

k

1.00

3.5°

0°

ccc

0.08

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

107/118

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 57. LFBGA100 - low profile fine pitch ball grid array package outline

Seating plane

C

ddd

C

A2 A4 A3

A1

A

D

B

D1

F

e

A

K

J

F

H

G

F

E

E1

E

D

C

B

A

e

1

2

3

4

5

6

7 8 9 10

A1 corner index area

(see note 5)

∅b(100 balls)

∅eee

C

A

B

M

∅

fff

Bottom view

ai14396

Table 64. LFBGA100 - low profile fine pitch ball grid array package mechanical data

mm

inches⁽¹⁾

Dim.

Min

Typ

Max

Min

Typ

Max

A

1.700

0.0026

A1

A2

A3

A4

b

0.270

0.0004

1.085

0.30

0.0017

0.0005

0.80

0.55

0.0012

0.0009

0.0157

0.45

9.85

0.50

10.00

7.20

10.00

7.20

0.80

1.40

0.12

0.15

0.08

0.0007

0.0153

0.0008

0.0155

0.0111

0.0155

0.0111

0.0012

0.0022

0.0002

0.0001

D

10.15

D1

E

9.85

10.15

0.0153

0.0157

E1

e

F

ddd

eee

fff

N (number of balls)

100

1. Values in inches are converted from mm and rounded to 4 decimal digits.

108/118

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA)

Dpad

Dsm

0.37 mm

0.52 mm typ. (depends on solder

mask registration tolerance

Solder paste 0.37 mm aperture diameter

– Non solder mask defined pads are recommended

– 4 to 6 mils screen print

Dpad

Dsm

109/118

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)(2)

Figure 59. LQFP100, 100-pin low-profile quad flat

Figure 60. Recommended footprint

(1)

package outline

0.25 mm

0.10 inch

GAGE PLANE

75

51

k

76

50

D

0.5

L

D1

L1

D3

51

75

C

0.3

76

50

.3

b

E3 E1

E

100

26

1.2

1

25

100

26

Pin 1

1

25

ccc

C

identification

12.3

16.7

e

A1

A2

A

ai14906

SEATING PLANE

C

1L_ME

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 65. LQPF100 – 100-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Typ

Min

Max

Typ

Min

Max

A

A1

A2

b

1.60

0.15

0.063

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

0.05

1.35

0.002

0.0531

0.0067

0.0035

0.622

1.40

0.22

1.45

0.0551

0.0087

0.17

0.27

c

0.09

0.20

D

16.00

14.00

12.00

16.00

14.00

12.00

0.50

15.80

13.80

16.20

14.20

0.6299

0.5512

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

D1

D3

E

0.5433

15.80

13.80

16.20

14.20

0.622

0.6378

0.5591

E1

E3

e

0.5433

L

0.60

0.45

0.75

7°

0.0177

0.0295

7°

L1

k

1.00

3.5°

0°

ccc

0.08

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

110/118

STM32F103xC, STM32F103xD, STM32F103xE

Figure 61. LQFP64 – 64 pin low-profile quad flat

Package characteristics

(1)(2)

Figure 62. Recommended footprint

(1)

package outline

D

A

48

33

D1

A2

0.3

A1

49

32

0.5

b

12.7

10.3

E1

E

e

10.3

64

17

1.2

1

16

c

7.8

L1

12.7

L

ai14398

ai14909

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 66. LQFP64 – 64 pin low-profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Dim.

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.0630

0.0059

0.0571

0.0106

0.0079

0.05

1.35

0.17

0.09

0.0020

0.0531

0.0067

0.0035

1.40

0.22

0.0551

0.0087

c

D

12.00

10.00

12.00

10.00

0.50

0.4724

0.3937

0.4724

0.3937

0.0197

3.5°

D1

E

E1

e

θ

0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.0177

0.0236

0.0394

0.0295

L1

1.00

Number of pins

64

N

1. Values in inches are converted from mm and rounded to 4 decimal digits.

111/118

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package outline

Seating plane

C

A2

A4

ddd

C

A

A3

A1

B

D

D1

A

e

F

M

F

E1

E

e

12

Øb (144 balls)

C

A

B

M

Øeee

Ø fff

M

C

X3_ME

1. Drawing is not to scale.

Table 67. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package data

millimeters

inches⁽¹⁾

Symbol

Typ

Min

Max

Typ

Min

Max

A

A1

A2

A3

A4

b

1.70

0.0669

0.21

0.0083

1.07

0.27

0.0421

0.0106

0.85

0.45

0.0335

0.0177

0.3996

0.35

9.85

0.40

10.00

8.80

10.00

8.80

0.80

0.60

0.10

0.15

0.08

0.0138

0.3878

0.0157

0.3937

0.3465

0.3937

0.3465

0.0315

0.0236

0.0039

0.0059

0.0031

D

10.15

D1

E

9.85

10.15

0.3878

0.3996

E1

e

F

ddd

eee

fff

1. Values in inches are converted from mm and rounded to 4 decimal digits.

112/118

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

6.2

Thermal characteristics

The maximum chip junction temperature (T max) must never exceed the values given in

J

Table 9: General operating conditions on page 38.

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max x Θ )

J

A

D

JA

Where:

●

T max is the maximum ambient temperature in °C,

A

Θ

is the package junction-to-ambient thermal resistance, in ° C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (V × I ) + Σ((V – V ) × I ),

OL OL DD OH OH

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 68. Thermal characteristics

Symbol

Parameter

Thermal resistance junction-ambient

Value

Unit

TBD

LFBGA144 - 10 × 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP144 - 20 × 20 mm / 0.5 mm pitch

TBD

41

Thermal resistance junction-ambient

LFBGA100 - 10 × 10 mm / 0.5 mm pitch

Θ

°C/W

JA

Thermal resistance junction-ambient

LQFP100 - 14 × 14 mm / 0.5 mm pitch

46

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

45

6.2.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

113/118

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

6.2.2

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 69: Ordering information scheme.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F103xC at maximum dissipation, it is

useful to calculate the exact power consumption and junction temperature to determine

which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given

application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

= 82 °C (measured according to JESD51-2),

Amax

I

= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output

OL

at low level with I = 20 mA, V = 1.3 V

OL

P

= 50 mA × 3.5 V= 175 mW

INTmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

IOmax

This gives: P

= 175 mW and P

= 272 mW:

IOmax

INTmax

P

= 175 + 272 = 447 mW

Dmax

Thus: P

= 464 mW

Dmax

Using the values obtained in Table 68 T

is calculated as follows:

Jmax

–

T

For LQFP100, 46 °C/W

= 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C

Jmax

This is within the range of the suffix 6 version parts (–40 < T < 105 °C).

J

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Table 69: Ordering information scheme).

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient

temperatures with a low dissipation, as long as junction temperature T remains within the

J

specified range.

Assuming the following application conditions:

Maximum ambient temperature T

= 115 °C (measured according to JESD51-2),

Amax

I

= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V

OL

P

= 20 mA × 3.5 V= 70 mW

INTmax

= 20 × 8 mA × 0.4 V = 64 mW

IOmax

This gives: P

= 70 mW and P

= 64 mW:

IOmax

INTmax

P

= 70 + 64 = 134 mW

Dmax

Thus: P

= 134 mW

Dmax

114/118

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

is calculated as follows:

Using the values obtained in Table 68 T

Jmax

–

T

For LQFP100, 46 °C/W

= 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C

Jmax

This is within the range of the suffix 7 version parts (–40 < T < 125 °C).

J

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Table 69: Ordering information scheme).

Figure 64. LQFP100 P max vs. T

D

A

700

600

500

400

300

200

100

0

Suffix 6

Suffix 7

65

75

85

95 105 115 125 135

T_A(°C)

115/118

Part numbering

STM32F103xC, STM32F103xD, STM32F103xE

7

Part numbering

Table 69. Ordering information scheme

Example:

STM32

F 103 R

C

T

6

xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

103 = performance line

Pin count

R = 64 pins

V = 100 pins

Z = 144 pins

Flash memory size

C = 256 Kbytes of Flash memory

D = 384 Kbytes of Flash memory

E = 512 Kbytes of Flash memory

Package

H = BGA

T = LQFP

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

7 = Industrial temperature range, –40 to 105 °C.

Options

xxx = programmed parts

TR = tape and real

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

116/118

STM32F103xC, STM32F103xD, STM32F103xE

Revision history

8

Revision history

Table 70. Document revision history

Date

Revision

Changes

07-Apr-2008

1

Initial release.

Document status promoted from Target Specification to Preliminary

Data.

Section 1: Introduction and Section 2.2: Full compatibility throughout

the family modified. Small text changes.

Note 2 added in Table 2: STM32F103xC, STM32F103xD and

STM32F103xE features and peripheral counts on page 9.

LQPF100/BGA100 column added to Table 5: FSMC pin definition on

page 32.

Values and Figures added to Maximum current consumption on

page 40 (see Table 13, Table 14, Table 15 and Table 16 and see

Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17).

Values added to Typical current consumption on page 46 (see Table 17,

Table 18 and Table 19). Table 19: Typical current consumption in

Standby mode removed.

22-May-2008

2

Note 4 and Note 1 added to Table 55: USB DC electrical characteristics

and Table 56: USB: full-speed electrical characteristics on page 98,

respectively.

V_USBadded to Table 55: USB DC electrical characteristics on page 98.

Figure 56: Recommended footprint(1) on page 107 corrected.

Equation 1 corrected. Figure 64: LQFP100 PD max vs. TA on page 115

modified.

Tolerance values corrected in Table 67: LFBGA144 – 144-ball low

profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package

data on page 112.

117/118

STM32F103xC, STM32F103xD, STM32F103xE

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118/118


型号：	STM32F103VD
厂家：	ST
描述：	Performance line, ARM-based 32-bit MCU with up to 512 KB Flash, USB, CAN, 11 timers, 3 ADCs and 13 communication interfaces 基于ARM的高性能线的32位MCU，具有高达512 KB的闪存， USB ， CAN ，11个定时器，3个ADC和13通信接口闪存通信
文件：	总118页 (文件大小：1231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM32F103VD [STMICROELECTRONICS]

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