STM32F103ZEH6TR_技术文档

STM32F103xC STM32F103xD

STM32F103xE

High-density performance line ARM-based 32-bit MCU with 256 to

512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

Features

FBGA

■ Core: ARM 32-bit Cortex™-M3 CPU

WLCSP64

LQFP64 10 × 10 mm,

– 72 MHz maximum frequency,

LFBGA100 10 × 10 mm

LQFP100 14 × 14 mm,

LFBGA144 10 × 10 mm

1.25 DMIPS/MHz (Dhrystone 2.1)

LQFP144 20 × 20 mm

performance at 0 wait state memory

access

■ Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors and almost all

5 V-tolerant

– Single-cycle multiplication and hardware

division

■ Memories

■ Up to 11 timers

– 256 to 512 Kbytes of Flash memory

– up to 64 Kbytes of SRAM

– Flexible static memory controller with 4

Chip Select. Supports Compact Flash,

SRAM, PSRAM, NOR and NAND memories

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– 2 × 16-bit motor control PWM timers with

dead-time generation and emergency stop

– LCD parallel interface, 8080/6800 modes

– 2 × watchdog timers (Independent and

Window)

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

■ Up to 13 communication interfaces

2

– 4-to-16 MHz crystal oscillator

– Up to 2 × I C interfaces (SMBus/PMBus)

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

– 32 kHz oscillator for RTC with calibration

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 3 SPIs (18 Mbit/s), 2 with I S

interface multiplexed

– CAN interface (2.0B Active)

– USB 2.0 full speed interface

– SDIO interface

2

■ Low power

– Sleep, Stop and Standby modes

– V

supply for RTC and backup registers

BAT

■ 3 × 12-bit, 1 µs A/D converters (up to 21

■ CRC calculation unit, 96-bit unique ID

channels)

®

■ ECOPACK packages

– Conversion range: 0 to 3.6 V

– Triple-sample and hold capability

– Temperature sensor

Table 1.

Device summary

Part number

Reference

■ 2 × 12-bit D/A converters

STM32F103RC STM32F103VC

STM32F103ZC

■ DMA: 12-channel DMA controller

STM32F103xC

STM32F103xD

STM32F103xE

– Supported peripherals: timers, ADCs, DAC,

2

SDIO, I Ss, SPIs, I Cs and USARTs

STM32F103RD STM32F103VD

STM32F103ZD

■ Debug mode

STM32F103RE STM32F103ZE

STM32F103VE

– Serial wire debug (SWD) & JTAG interfaces

– Cortex-M3 Embedded Trace Macrocell™

September 2009

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1

Contents

STM32F103xC, STM32F103xD, STM32F103xE

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

2.2

2.3

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

®

2.3.1

2.3.2

2.3.3

2.3.4

2.3.5

2.3.6

2.3.7

2.3.8

2.3.9

ARM Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15

LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16

External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 21

2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2

2.3.21 Inter-integrated sound (I S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.22 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.26 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.27 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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Contents

2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3

4

5

Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2

5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43

Embedded reset and power control block characteristics . . . . . . . . . . . 43

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 81

5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.3.17 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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STM32F103xC, STM32F103xD, STM32F103xE

5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6

6.1

6.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.2.1

6.2.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 115

7

8

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . 11

STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

High-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Maximum current consumption in Run mode, code with data processing

Table 15.

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 47

Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 48

Typical current consumption in Run mode, code with data processing

Table 16.

Table 17.

Table 18.

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Typical current consumption in Sleep mode, coderunning from Flash or

Table 19.

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

LSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 62

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 63

Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 76

Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 79

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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List of tables

STM32F103xC, STM32F103xD, STM32F103xE

Table 45.

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

SCL frequency (f

= 36 MHz.,V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

PCLK1

DD

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

2

I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

R

max for f

= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

AIN

ADC

ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale

Table 65.

Table 66.

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111

LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112

LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 113

Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 67.

Table 68.

Table 69.

Table 70.

Table 71.

6/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24

STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25

STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26

STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27

STM32F103xC and STM32F103xE performance line

LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

STM32F103xC and STM32F103xE performance line

WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 8.

Figure 9.

Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 46

Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 46

Figure 16. Typical current consumption on V

with RTC on vs. temperature at different V

BAT

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 17. Typical current consumption in Stop mode with regulator in run mode

versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DD

Figure 18. Typical current consumption in Stop mode with regulator in low-power

mode versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DD

Figure 19. Typical current consumption in Standby mode versus temperature at

different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DD

Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 62

Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 63

Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 29. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 32. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 72

Figure 33. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . . 73

Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 75

Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 76

Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Doc ID 14611 Rev 7

7/123

List of figures

STM32F103xC, STM32F103xD, STM32F103xE

Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 40. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 78

Figure 41. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 79

Figure 42. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 43. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2

Figure 44. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 45. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

(1)

Figure 46. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

(1)

Figure 47. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

2

(1)

Figure 48. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

2

(1)

Figure 49. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 50. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 51. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 52. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 53. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 54. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 55. Power supply and reference decoupling (V

Figure 56. Power supply and reference decoupling (V

not connected to V

). . . . . . . . . . . . . 101

). . . . . . . . . . . . . . . . 102

REF+

DDA

connected to V

REF+

DDA

Figure 57. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 106

Figure 59. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 60. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 61. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 62. Recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 63. LQFP144, 20 x 20 mm, 144-pin low-profile quad

flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

(1)

Figure 64. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 65. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 112

(1)

Figure 66. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 67. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 113

(1)

Figure 68. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 69. LQFP100 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

D

A

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Introduction

1

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line

microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family,

please refer to Section 2.2: Full compatibility throughout the family.

The high-density STM32F103xx datasheet should be read in conjunction with the

STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Doc ID 14611 Rev 7

9/123

Description

STM32F103xC, STM32F103xD, STM32F103xE

2

Description

The STM32F103xC, STM32F103xD and STM32F103xE performance line family

®

incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at a

72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and

SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals

connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16-

bit timers plus two PWM timers, as well as standard and advanced communication

2

interfaces: up to two I Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a

CAN.

The STM32F103xx high-density performance line family operates in the –40 to +105 °C

temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving

mode allows the design of low-power applications.

The STM32F103xx high-density performance line family offers devices in six different

package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of

peripherals are included, the description below gives an overview of the complete range of

peripherals proposed in this family.

These features make the STM32F103xx high-density performance line microcontroller

family suitable for a wide range of applications:

●

Motor drive and application control

Medical and handheld equipment

PC peripherals gaming and GPS platforms

Industrial applications, PLC, inverters, printers, and scanners

Alarm systems, video intercom, and HVAC

Figure 1 shows the general block diagram of the device family.

10/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Description

2.1

Device overview

Table 2.

STM32F103xC, STM32F103xD and STM32F103xE features and peripheral

counts

Peripherals

STM32F103Rx

256 384

48

64⁽¹⁾

STM32F103Vx

256 384 512

48

STM32F103Zx

Flash memory in Kbytes

SRAM in Kbytes

FSMC

512

256

48

384

Yes

512

64

No

Yes⁽²⁾

General-purpose

Timers Advanced-control

Basic

4

2

SPI(I²S)⁽³⁾

3(2)

I²C

2

5

1

USART

Comm

USB

CAN

SDIO

GPIOs

51

80

112

12-bit ADC

3

Number of channels

16

21

12-bit DAC

Number of channels

2

CPU frequency

72 MHz

2.0 to 3.6 V

Operating voltage

Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10)

Junction temperature: –40 to + 125 °C (see Table 10)

Operating temperatures

Package

LQFP64

WLCSP64

LQFP100, BGA100 LQFP144, BGA144

1. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.

2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only

support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or

8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is

not available in this package.

3. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the

I²S audio mode.

Doc ID 14611 Rev 7

11/123

Description

STM32F103xC, STM32F103xD, STM32F103xE

Figure 1.

STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram

TRACECLK

TRACED[0:3]

as AS

@V

DD

TPIU

Trace/trig

Trace

controller

Power

Pbus

Ibus

V

SW/JTAG

DD

NJTRST

JTDI

JTCK/SWCLK

JTMS/SWDIO

JTDO

Volt. reg.

3.3 V to 1.8 V

V

SS

Flash 512 Kbytes

64 bit

Cortex-M3 CPU

@V

Supply

DDA

Dbus

System

as AF

F

: 48/72 MHz

max

NRST

supervision

POR

Reset

V

POR /PDR

DDA

V

SRAM

SSA

@V

DDA

NVIC

64 KB

PVD

Int

RC 8 MHz

RC 40 kHz

PLL

GP DMA1

@V

DD

XTAL OSC

4-16 MHz

A[25:0]

D[15:0]

CLK

NOE

NWE

OSC_IN

OSC_OUT

7 channels

GP DMA2

IWDG

5 channels

PCLK1

PCLK2

HCLK

FCLK

Reset &

Clock

control

Standby

interface

NE[4:1]

NBL[1:0]

NWAIT

NL (or NADV)

as AF

V

=1.8 V to 3.6 V

BAT

V

@

FSMC

SDIO

BAT

OSC32_IN

OSC32_OUT

XTAL32kHz

Backup

TAMPER-RTC/

ALARM/SECOND OUT

RTC

AWU

reg

D[7:0]

CMD

CK as AF

Backup interface

AHB2

APB2

AHB2

APB1

4 channels, ETR as AF

4 channels as AF

TIM2

EXT.IT

WKUP

112AF

PA[15:0]

PB[15:0]

TIM3

TIM4

GPIO port A

GPIO port B

GPIO port C

TIM5

RX, TX, CTS, RTS,

CK as AF

PC[15:0]

PD[15:0]

USART2

USART3

UART4

UART5

RX, TX, CTS, R T S,

CK as AF

GPIO port D

GPIO port E

PE[15:0]

PF[15:0]

PG[15:0]

RX,TXasAF

GPIO port F

GPIO port G

RX,TX asAF

MOSI/SD, MISO

SCK/CK, MCK, NSS/WS as AF

SPI2/ I2S2

2x(8xi1t)6b

4 channels

3 compl. channels

BKIN, ETR as AF

4 channels

3 compl. channels

BKIN, ETR as AF

TIM1

MOSI/SD, MISO

SCK/CK, MCK, NSS/WS as AF

SPI3 / I2S3

2x(8xi1t)6b

TIM8

I2C1

I2C2

SCL, SDA, SMBA as AF

MOSI, MISO,

SCK, NSS as AF

SPI1

SRAM 512 B

bxCAN device

RX, TX, CTS,

RTS, CK as AF

USART1

WWDG

USBDP/CAN_TX

USBDM/CAN_RX

USB 2.0 FS

device

Temp. sensor

TIM6

TIM7

12bit DAC1

12bit DAC 2

IF

DAC_OUT1 as AF

DAC_OUT2 as AF

8 ADC123_INs

12-bit ADC1 IF

12-bit ADC2 IF

12-bit ADC3 IF

common to the 3 ADCs

8 ADC12_INs common

to ADC1 & ADC2

5 ADC3_INs on ADC3

@V

DDA

V_REF–

V_REF+

@ V

DDA

ai14666f

1. T_A= –40 °C to +85 °C (suffix 6, see Table 71) or –40 °C to +105 °C (suffix 7, see Table 71), junction temperature up to

105 °C or 125 °C, respectively.

2. AF = alternate function on I/O port pin.

12/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Description

Figure 2.

Clock tree

USBCLK

to USB interface

USB

Prescaler

/1, 1.5

48 MHz

I2S3CLK

to I2S3

Peripheral clock

enable

I2S2CLK

to I2S2

Peripheral clock

enable

SDIOCLK

to SDIO

8 MHz

Peripheral clock

HSI

HSI RC

enable

FSMCCLK

to FSMC

Peripheral clock

enable

/2

HCLK

to AHB bus, core,

memory and DMA

72 MHz max

Clock

Enable (4 bits)

/8

to Cortex System timer

SW

PLLSRC

FCLK Cortex

free running clock

36 MHz max

PLLMUL

HSI

AHB

APB1

SYSCLK

..., x16

x2, x3, x4

PLL

PCLK1

Prescaler

PLLCLK

HSE

72 MHz

max

to APB1

/1, 2..512

/1, 2, 4, 8, 16

peripherals

Peripheral Clock

Enable (20 bits)

TIM2,3,4,5,6,7

If (APB1 prescaler =1) x1

else x2

to TIM2,3,4,5,6 and 7

TIMXCLK

CSS

Peripheral Clock

Enable (6 bits)

APB2

Prescaler

/1, 2, 4, 8, 16

PLLXTPRE

/2

72 MHz max

PCLK2

OSC_OUT

OSC_IN

peripherals to APB2

4-16 MHz

HSE OSC

Peripheral Clock

Enable (15 bits)

TIM1 & 8 timers

If (APB2 prescaler =1) x1

else x2

to TIM1 and TIM8

TIMxCLK

Peripheral Clock

Enable (2 bit)

to ADC1, 2 or 3

/128

LSE

ADC

Prescaler

/2, 4, 6, 8

OSC32_IN

to RTC

LSE OSC

ADCCLK

RTCCLK

32.768 kHz

OSC32_OUT

HCLK/2

/2

RTCSEL[1:0]

To SDIO AHB interface

Peripheral clock

enable

to Independent Watchdog (IWDG)

IWDGCLK

LSI

LSI RC

40 kHz

Legend:

Main

Clock Output

/2

PLLCLK

HSE = High Speed External clock signal

HSI = High Speed Internal clock signal

MCO

HSI

HSE

LSI = Low Speed Internal clock signal

LSE = Low Speed External clock signal

SYSCLK

MCO

ai14752b

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is

64 MHz.

2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either

48 MHz or 72 MHz.

3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.

Doc ID 14611 Rev 7

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Description

STM32F103xC, STM32F103xD, STM32F103xE

2.2

Full compatibility throughout the family

The STM32F103xx is a complete family whose members are fully pin-to-pin, software and

feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are

identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as

medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are

referred to as high-density devices.

Low-density and high-density devices are an extension of the STM32F103x8/B medium-

density devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E

datasheets, respectively. Low-density devices feature lower Flash memory and RAM

capacities, less timers and peripherals. High-density devices have higher Flash memory

2

and RAM capacities, and additional peripherals like SDIO, FSMC, I S and DAC while

remaining fully compatible with the other members of the family.

The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE

are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different

memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F103xx performance line family is fully compatible with all existing

STM32F101xx access line and STM32F102xx USB access line devices.

Table 3.

STM32F103xx family

Low-density devices Medium-density devices

High-density devices

16 KB

Flash

32 KB

64 KB

Flash

128 KB

Flash

256 KB

Flash

384 KB

Flash

512 KB

Flash

Flash⁽¹⁾

Pinout

48 or

6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 64 KB⁽²⁾64 KB RAM 64 KB RAM

RAM

144

100

5 × USARTs

4 × 16-bit timers, 2 × basic timers

3 × SPIs, 2 × I²Ss, 2 × I2Cs

3 × USARTs

USB, CAN, 2 × PWM timers

3 × 16-bit timers

2 × SPIs, 2 × I²Cs, USB,

CAN, 1 × PWM timer

2 × ADCs

2 × USARTs

3 × ADCs, 2 × DACs, 1 × SDIO

64

2 × 16-bit timers

1 × SPI, 1 × I²C, USB,

CAN, 1 × PWM timer

2 × ADCs

FSMC (100- and 144-pin packages⁽³⁾

)

48

36

1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),

the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density

devices.

2. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.

3. Ports F and G are not available in devices delivered in 100-pin packages.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Description

2.3

Overview

®

2.3.1

ARM Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE

performance line family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2

2.3.3

Embedded Flash memory

Up to 512 Kbytes of embedded Flash is available for storing programs and data.

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

2.3.4

2.3.5

Embedded SRAM

Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE

performance line family. It has four Chip Select outputs supporting the following modes: PC

Card/Compact Flash, SRAM, PSRAM, NOR and NAND.

Functionality overview:

●

The three FSMC interrupt lines are ORed in order to be connected to the NVIC

Write FIFO

Code execution from external memory except for NAND Flash and PC Card

The targeted frequency, f

, is HCLK/2, so external access is at 36 MHz when HCLK

CLK

is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz

Doc ID 14611 Rev 7

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Description

STM32F103xC, STM32F103xD, STM32F103xE

2.3.6

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high-

performance solutions using external controllers with dedicated acceleration.

2.3.7

Nested vectored interrupt controller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested

vectored interrupt controller able to handle up to 60 maskable interrupt channels (not

including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.8

2.3.9

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and

the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed

APB domain is 36 MHz. See Figure 2 for details on the clock tree.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Description

2.3.10

Boot modes

At startup, boot pins are used to select one of three boot options:

●

Boot from User Flash

Boot from System Memory

Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1.

2.3.11

Power supply schemes

●

V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

DD

Provided externally through V pins.

DD

●

V

, V

= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs

DDA

SSA

and PLL (minimum voltage to be applied to V

is 2.4 V when the ADC is used). V

DDA

and V

must be connected to V and V , respectively.

SSA

DD SS

●

V

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

BAT

registers (through power switch) when V is not present.

DD

For more details on how to connect power pins, refer to Figure 12: Power supply scheme.

2.3.12

Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V is below a specified threshold, V

, without the need for an

DD

POR/PDR

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

/V power supply and compares it to the V threshold. An interrupt can be

V

DD DDA

PVD

generated when V /V

drops below the V

threshold and/or when V /V

is higher

DD DDA

PVD

DD DDA

than the V

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

V

and V

.

POR/PDR

PVD

2.3.13

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●

MR is used in the nominal regulation mode (Run)

LPR is used in the Stop modes.

Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

Doc ID 14611 Rev 7

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Description

STM32F103xC, STM32F103xD, STM32F103xE

2.3.14

Low-power modes

The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three

low-power modes to achieve the best compromise between low power consumption, short

startup time and available wakeup sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

●

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

●

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.15

DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers. The two DMA controllers support circular buffer management,

removing the need for user code intervention when the controller reaches the end of the

buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

2

The DMA can be used with the main peripherals: SPI, I C, USART, general-purpose, basic

2

and advanced-control timers TIMx, DAC, I S, SDIO and ADC.

2.3.16

RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

V

supply when present or through the V

pin. The backup registers are forty-two 16-bit

DD

BAT

registers used to store 84 bytes of user application data when V power is not present.

DD

They are not reset by a system or power reset, and they are not reset when the device

wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

18/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Description

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural quartz deviation. The RTC features

a 32-bit programmable counter for long term measurement using the Compare register to

generate an alarm. A 20-bit prescaler is used for the time base clock and is by default

configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.17

Timers and watchdogs

The high-density STM32F103xx performance line devices include up to two advanced-

control timers, up to four general-purpose timers, two basic timers, two watchdog timers and

a SysTick timer.

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4.

Timer

High-density timer feature comparison

Counter Counter Prescaler DMA request Capture/compare Complementary

resolution

type

factor

generation

channels

outputs

Up,

down,

up/down and 65536

Any integer

between 1

TIM1,

TIM8

16-bit

Yes

4

Yes

TIM2,

TIM3,

TIM4,

TIM5

Up,

down,

up/down and 65536

Any integer

between 1

16-bit

Yes

4

0

No

Any integer

between 1

and 65536

TIM6,

TIM7

Up

Advanced-control timers (TIM1 and TIM8)

The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase

PWM multiplexed on 6 channels. They have complementary PWM outputs with

programmable inserted dead-times. They can also be seen as a complete general-purpose

timer. The 4 independent channels can be used for:

●

Input capture

Output compare

PWM generation (edge or center-aligned modes)

One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the

same architecture. The advanced-control timer can therefore work together with the TIM

timers via the Timer Link feature for synchronization or event chaining.

Doc ID 14611 Rev 7

19/123

Description

STM32F103xC, STM32F103xD, STM32F103xE

General-purpose timers (TIMx)

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)

embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line

devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler

and feature 4 independent channels each for input capture/output compare, PWM or one-

pulse mode output. This gives up to 16 input captures / output compares / PWMs on the

largest packages.

The general-purpose timers can work together with the advanced-control timer via the Timer

Link feature for synchronization or event chaining. Their counter can be frozen in debug

mode. Any of the general-purpose timers can be used to generate PWM outputs. They all

have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a

generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

●

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0.

Programmable clock source

2.3.18

I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support

standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A

hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Description

2.3.19

Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three

universal synchronous/asynchronous receiver transmitters (USART1, USART2 and

USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other

available interfaces communicate at up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS

signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All

interfaces can be served by the DMA controller except for UART5.

2.3.20

2.3.21

Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in

full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2

Inter-integrated sound (I S)

2

Two standard I S interfaces (multiplexed with SPI2 and SPI3) are available, that can be

operated in master or slave mode. These interfaces can be configured to operate with 16/32

bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to

2

48 kHz are supported. When either or both of the I S interfaces is/are configured in master

mode, the master clock can be output to the external DAC/CODEC at 256 times the

sampling frequency.

2.3.22

SDIO

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD

Memory Card Specifications Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack

of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital

protocol Rev1.1.

2.3.23

Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It

can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

Doc ID 14611 Rev 7

21/123

Description

STM32F103xC, STM32F103xD, STM32F103xE

2.3.24

Universal serial bus (USB)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB

device peripheral compatible with the USB full-speed 12 Mbs. The USB interface

implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint

setting and suspend/resume support. The dedicated 48 MHz clock is generated from the

internal main PLL (the clock source must use a HSE crystal oscillator).

2.3.25

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

2.3.26

ADC (analog to digital converter)

Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD

and STM32F103xE performance line devices and each ADC shares up to 21 external

channels, performing conversions in single-shot or scan modes. In scan mode, automatic

conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

●

Simultaneous sample and hold

Interleaved sample and hold

Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control

timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection

trigger, respectively, to allow the application to synchronize A/D conversion and timers.

2.3.27

DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two

analog voltage signal outputs. The chosen design structure is composed of integrated

resistor strings and an amplifier in inverting configuration.

22/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

This dual digital Interface supports the following features:

Description

●

two DAC converters: one for each output channel

8-bit or 12-bit monotonic output

left or right data alignment in 12-bit mode

synchronized update capability

noise-wave generation

triangular-wave generation

dual DAC channel independent or simultaneous conversions

DMA capability for each channel

external triggers for conversion

input voltage reference V

REF+

Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and

STM32F103xE performance line family. The DAC channels are triggered through the timer

update outputs that are also connected to different DMA channels.

2.3.28

2.3.29

2.3.30

Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The

conversion range is between 2 V < V

connected to the ADC1_IN16 input channel which is used to convert the sensor output

voltage into a digital value.

< 3.6 V. The temperature sensor is internally

DDA

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a

specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

Embedded Trace Macrocell™

®

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and

data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F10xxx through a small number of ETM pins to an external hardware trace port

analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or

any other high-speed channel. Real-time instruction and data flow activity can be recorded

and then formatted for display on the host computer running debugger software. TPA

hardware is commercially available from common development tool vendors. It operates

with third party debugger software tools.

Doc ID 14611 Rev 7

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Pinouts and pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

3

Pinouts and pin descriptions

Figure 3.

STM32F103xC and STM32F103xE performance line BGA144 ballout

1

2

3

4

5

6

7

8

9

10

11

12

PB4

JTRST

PC13-

TAMPER-RTC

PB3

JTDO

PA15

JTDI

PA14

JTCK

PA13

JTMS

PE3

PE2

PE1

PE0

PD6

PD7

A

B

C

D

E

F

PC14-

OSC32_IN

PE4

PE5

PF0

PE6

PF1

PF2

PF5

PB9

PB8

PB5

PB6

PB7

PG15

PG14

PG13

PG12

PG11

PG10

PG9

PD5

PD4

PD3

PD2

PC11

PC12

PD1

PC10

NC

PA12

PA11

PA9

PA8

PC7

PC6

PG5

PC15-

OSC32_OUT

V

BAT

OSC_IN

V

BOOT0

PA10

PC9

PC8

PG8

PG6

SS_5

DD_5

PF4

OSC_OUT

V

SS_10

PF3

PD0

SS_3

SS_11

V

DD_8

NRST

PF10

PC0

PF7

PF9

PF6

PF8

PC2

PA4

PA5

PA6

PA7

V

DD_9

DD_4

DD_3

DD_11

DD_10

DD_2

G

H

J

V

SS_8

V

SS_9

DD_6

DD_7

DD_1

SS_4

SS_2

V

PE11

PD11

PG7

PC1

PC3

SS_6

SS_7

PG1

SS_1

PE10

PE9

PB2/

BOOT1

V

PA0-WKUP

PA1

PC4

PC5

PB0

PB1

PE12

PE13

PE14

PE15

PD10

PD9

PG4

PD13

PD12

PB11

PG3

PD14

PB14

PB12

PG2

PD15

PB15

PB13

SSA

K

L

V

PF13

PF12

PF11

PG0

REF–

PA2

PF15

PF14

PE8

PD8

REF+

V

PA3

PE7

M

PB10

DDA

AI14798b

24/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Pinouts and pin descriptions

Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout

1

2

3

4

5

6

7

8

9

10

PC14-

OSC32_IN

PC13-

TAMPER-RTC

A

B

C

D

E

F

PE2

PE3

PE4

PE5

PE6

PC3

PA4

PA5

PA6

PA7

PB9

PB8

PE1

PE0

PB7

PB4

PD5

PD6

PD7

PB3

PD2

PD3

PD4

PA15

PC11

PC12

PD0

PA14

PC10

PA9

PA13

PA12

PA11

PA10

PC7

PC15-

OSC32_OUT

V

PB6

BAT

OSC_IN

OSC_OUT

NRST

V

PB5

SS_5

BOOT0

PA8

DD_5

V

PD1

PC2

PC9

PC8

PD11

PD10

PD9

PD8

SS_4

SS_3

SS_2

SS_1

V

NC

PC0

PC1

PA0-WKUP

PA1

PC6

DD_4

DD_3

DD_2

DD_1

G

H

J

V

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

PB15

PB14

PC4

PD15

PD14

PD13

PD12

SSA

V

PC5

PB0

PB1

REF–

V

PA2

PB13

REF+

K

V

PA3

PB12

DDA

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Pinouts and pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout

PE2

PE3

PE4

PE5

PE6

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

V

NC

DD_2

SS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

9

PF0

PF1

PF2

PF3

PF4

PF5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

V

DD_9

SS_9

V

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

SS_5

LQFP144

DD_5

PF6

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

V

DD_8

SS_8

PC1

PC2

PC3

PD13

PD12

PD11

PD10

PD9

V

SSA

REF-

PD8

REF+

PB15

PB14

PB13

PB12

DDA

PA0-WKUP

PA1

PA2

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Pinouts and pin descriptions

Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout

PE2

PE3

PE4

PE5

PE6

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD_2

VSS_2

NC

PA 13

PA 12

PA 11

PA 10

PA 9

PA 8

PC9

PC8

PC7

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VDD_5

OSC_IN

OSC_OUT

NRST

LQFP100

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PD8

PB15

PB14

PB13

PB12

PA0-WKUP

PA1

PA2

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Pinouts and pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Figure 7. STM32F103xC and STM32F103xE performance line

LQFP64 pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

VDD_2

VSS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

3

4

5

6

7

PC0

PC1

PC2

PC3

8

LQFP64

9

10

11

12

13

14

15

16

PC6

VSSA

VDDA

PA0-WKUP

PB15

PB14

PB13

PB12

PA1

PA2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Pinouts and pin descriptions

Figure 8.

STM32F103xC and STM32F103xE performance line

WLCSP64 ballout, ball side

8

7

6

5

4

3

2

1

A

B

C

D

E

F

V_{DD_3}

V_{SS_3}

V_{DD_2}

BOOT0

PB9

PB5

PB6

PB7

PB3

PD2

PC10

PA14

PA12

BYPASS/

V_{SS_2}

PC14

PC13

PC15

NRST

PB4

PC11

PA15

V_BAT

PC12

PA11

OSC_IN OSC_OUT PC2

PB8

PA5

PA13

PA8

PA10

PC8

PA9

PC7

PC9

PC6

PC0

V_SSA

PA1

PA0-

WKUP

V_REF+

V_{SS_4}

PC1

PB1

PA7

PB11

PB10

PB14

PB12

V_{SS_1}

PB15

PB13

V_{DD_1}

V_DDA

V_{DD_4}

G

H

PA3

PA4

PA6

PC5

PA2

PC4

PB0

PB2

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Pinouts and pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Alternate functions⁽⁴⁾

Table 5.

High-density STM32F103xx pin definitions

Pins

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

FT

A3 A3

A2 B3

B2 C3

B3 D3

B4 E3

-

1

2

3

4

5

6

1

2

3

4

5

6

PE2

PE3

PE4

PE5

PE6

V_BAT

I/O

S

PE2

PE3

PE4

PE5

PE6

V_BAT

TRACECK/ FSMC_A23

TRACED0/FSMC_A19

TRACED1/FSMC_A20

TRACED2/FSMC_A21

TRACED3/FSMC_A22

-

C2 B2 C6

A1 A2 C8

1

PC13-TAMPER-

RTC⁽⁵⁾

2

3

4

7

8

9

7

8

9

I/O

PC13⁽⁶⁾

PC14⁽⁶⁾

PC15⁽⁶⁾

TAMPER-RTC

OSC32_IN

PC14-

B1 A1 B8

C1 B1 B7

OSC32_IN⁽⁵⁾

PC15-

OSC32_OUT

OSC32_OUT⁽⁵⁾

C3

C4

D4

E2

E3

E4

-

10

11

12

13

14

15

PF0

PF1

I/O FT

S

PF0

PF1

FSMC_A0

FSMC_A1

FSMC_A2

FSMC_A3

FSMC_A4

FSMC_A5

-

PF2

-

PF3

-

PF4

-

PF5

D2 C2

D3 D2

-

10 16

11 17

V_{SS_5}

V_{DD_5}

PF6

V_{SS_5}

V_{DD_5}

PF6

-

S

F3

F2

-

18

19

20

21

22

I/O

ADC3_IN4/FSMC_NIORD

ADC3_IN5/FSMC_NREG

ADC3_IN6/FSMC_NIOWR

ADC3_IN7/FSMC_CD

-

PF7

I/O

PF7

G3

G2

G1

-

PF8

I/O

PF8

-

PF9

I/O

PF9

-

PF10

OSC_IN

OSC_OUT

NRST

PC0

I/O

PF10

OSC_IN

OSC_OUT

NRST

PC0

ADC3_IN8/FSMC_INTR

D1 C1 D8

E1 D1 D7

F1 E1 C7

H1 F1 E8

H2 F2 F8

5

6

7

8

9

12 23

13 24

14 25

15 26

16 27

I

O

I/O

ADC123_IN10

ADC123_IN11

ADC123_IN12

ADC123_IN13

PC1

I/O

PC1

H3 E2 D6 10 17 28

H4 F3 11 18 29

J1 G1 E7 12 19 30

PC2

I/O

PC2

-

PC3

I/O

PC3

V_SSA

S

V_SSA

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Pinouts and pin descriptions

Alternate functions⁽⁴⁾

Table 5.

High-density STM32F103xx pin definitions (continued)

Pins

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

K1 H1

L1 J1

-

20 31

21 32

V_REF-

V_REF+

V_DDA

S

V_REF-

V_REF+

V_DDA

F7

(7)

M1 K1 G8 13 22 33

J2 G2 F6 14 23 34

WKUP/USART2_CTS⁽⁸⁾

ADC123_IN0

TIM2_CH1_ETR

TIM5_CH1/TIM8_ETR

PA0-WKUP

PA1

I/O

PA0

PA1

USART2_RTS⁽⁸⁾

ADC123_IN1/

K2 H2 E6 15 24 35

TIM5_CH2/TIM2_CH2⁽⁸⁾

USART2_TX⁽⁸⁾/TIM5_CH3

ADC123_IN2/

L2 J2 H8 16 25 36

M2 K2 G7 17 26 37

PA2

PA3

I/O

PA2

PA3

TIM2_CH3 ⁽⁸⁾

USART2_RX⁽⁸⁾/TIM5_CH4

ADC123_IN3/TIM2_CH4⁽⁸⁾

G4 E4 F5 18 27 38

F4 F4 G6 19 28 39

V_{SS_4}

V_{DD_4}

S

V_{SS_4}

V_{DD_4}

SPI1_NSS⁽⁸⁾

/

J3 G3 H7 20 29 40

K3 H3 E5 21 30 41

L3 J3 G5 22 31 42

PA4

PA5

PA6

I/O

PA4

PA5

PA6

USART2_CK⁽⁸⁾

DAC_OUT1/ADC12_IN4

SPI1_SCK⁽⁸⁾

DAC_OUT2 ADC12_IN5

SPI1_MISO⁽⁸⁾

TIM8_BKIN/ADC12_IN6

TIM3_CH1⁽⁸⁾

TIM1_BKIN

TIM1_CH1N

SPI1_MOSI⁽⁸⁾

/

M3 K3 G4 23 32 43

PA7

I/O

PA7

TIM8_CH1N/ADC12_IN7

TIM3_CH2⁽⁸⁾

J4 G4 H6 24 33 44

K4 H4 H5 25 34 45

PC4

PC5

I/O

PC4

PC5

ADC12_IN14

ADC12_IN15

ADC12_IN8/TIM3_CH3

TIM8_CH2N

L4 J4 H4 26 35 46

PB0

PB1

I/O

PB0

PB1

TIM1_CH2N

TIM1_CH3N

ADC12_IN9/TIM3_CH4⁽⁸⁾

TIM8_CH3N

M4 K4 F4 27 36 47

J5 G5 H3 28 37 48

PB2

PF11

PF12

I/O FT PB2/BOOT1

M5

L5

-

49

50

I/O FT

PF11

PF12

FSMC_NIOS16

FSMC_A6

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Pinouts and pin descriptions

Table 5.

STM32F103xC, STM32F103xD, STM32F103xE

Alternate functions⁽⁴⁾

High-density STM32F103xx pin definitions (continued)

Pins

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

H5

G5

K5

M6

L6

-

51

52

53

54

55

56

57

V_{SS_6}

V_{DD_6}

PF13

PF14

PF15

PG0

S

V_{SS_6}

V_{DD_6}

PF13

PF14

PF15

PG0

S

I/O FT

S

FSMC_A7

FSMC_A8

FSMC_A9

FSMC_A10

FSMC_A11

FSMC_D4

FSMC_D5

FSMC_D6

K6

J6

PG1

M7 H5

L7 J5

K7 K5

38 58

39 59

40 60

PE7

TIM1_ETR

TIM1_CH1N

TIM1_CH1

PE8

PE9

H6

G6

-

61

62

V_{SS_7}

V_{DD_7}

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

V_{SS_1}

V_{DD_1}

V_{SS_7}

V_{DD_7}

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

V_{SS_1}

V_{DD_1}

S

J7 G6

H8 H6

J8 J6

K8 K6

L8 G7

M8 H7

41 63

42 64

43 65

44 66

45 67

46 68

I/O FT

S

FSMC_D7

FSMC_D8

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

TIM2_CH3

TIM2_CH4

FSMC_D9

FSMC_D10

FSMC_D11

FSMC_D12

M9 J7 G3 29 47 69

M10 K7 F3 30 48 70

H7 E7 H2 31 49 71

G7 F7 H1 32 50 72

I2C2_SCL/USART3_TX⁽⁸⁾

I2C2_SDA/USART3_RX⁽⁸⁾

S

SPI2_NSS/I2S2_WS/

I2C2_SMBA/

M11 K8 G2 33 51 73

M12 J8 G1 34 52 74

PB12

PB13

I/O FT

PB12

PB13

USART3_CK⁽⁸⁾

TIM1_BKIN⁽⁸⁾

/

SPI2_SCK/I2S2_CK

USART3_CTS⁽⁸⁾

TIM1_CH1N

/

SPI2_MISO/TIM1_CH2N

USART3_RTS⁽⁸⁾

L11 H8 F2 35 53 75

L12 G8 F1 36 54 76

PB14

PB15

I/O FT

PB14

PB15

/

SPI2_MOSI/I2S2_SD

TIM1_CH3N⁽⁸⁾

FSMC_D13

FSMC_D14

/

L9 K9

K9 J9

-

55 77

56 78

PD8

PD9

I/O FT

PD8

PD9

USART3_TX

USART3_RX

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Pinouts and pin descriptions

Alternate functions⁽⁴⁾

Table 5.

High-density STM32F103xx pin definitions (continued)

Pins

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

J9 H9

H9 G9

-

57 79

58 80

PD10

PD11

I/O FT

PD10

PD11

FSMC_D15

FSMC_A16

USART3_CK

USART3_CTS

TIM4_CH1 /

USART3_RTS

L10 K10

K10 J10

-

59 81

60 82

PD12

I/O FT

PD12

FSMC_A17

FSMC_A18

-

PD13

V_{SS_8}

V_{DD_8}

PD14

PD15

PG2

I/O FT

S

PD13

V_{SS_8}

V_{DD_8}

PD14

PD15

PG2

TIM4_CH2

G8

F8

-

83

84

S

K11 H10

K12 G10

61 85

62 86

I/O FT

S

FSMC_D0

FSMC_D1

TIM4_CH3

TIM4_CH4

J12

J11

-

87

88

89

90

91

92

93

94

95

FSMC_A12

FSMC_A13

FSMC_A14

FSMC_A15

FSMC_INT2

FSMC_INT3

PG3

J10

PG4

H12

H11

H10

G11

G10

F10

PG5

PG6

PG7

PG8

V_{SS_9}

V_{DD_9}

V_{SS_9}

V_{DD_9}

S

I2S2_MCK/

TIM8_CH1/SDIO_D6

G12 F10 E1 37 63 96

F12 E10 E2 38 64 97

PC6

PC7

I/O FT

PC6

PC7

TIM3_CH1

TIM3_CH2

I2S3_MCK/

TIM8_CH2/SDIO_D7

F11 F9 E3 39 65 98

E11 E9 D1 40 66 99

PC8

PC9

I/O FT

PC8

PC9

TIM8_CH3/SDIO_D0

TIM8_CH4/SDIO_D1

TIM3_CH3

TIM3_CH4

USART1_CK/

E12 D9 E4 41 67 100

D12 C9 D2 42 68 101

D11 D10 D3 43 69 102

C12 C10 C1 44 70 103

B12 B10 C2 45 71 104

PA8

PA9

I/O FT

PA8

PA9

TIM1_CH1⁽⁸⁾/MCO

USART1_TX⁽⁸⁾

TIM1_CH2⁽⁸⁾

/

USART1_RX⁽⁸⁾

TIM1_CH3⁽⁸⁾

/

PA10

PA11

PA12

PA10

PA11

PA12

USART1_CTS/USBDM

CAN_RX⁽⁸⁾/TIM1_CH4⁽⁸⁾

USART1_RTS/USBDP/

CAN_TX⁽⁸⁾/TIM1_ETR⁽⁸⁾

Doc ID 14611 Rev 7

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Pinouts and pin descriptions

Table 5.

STM32F103xC, STM32F103xD, STM32F103xE

Alternate functions⁽⁴⁾

High-density STM32F103xx pin definitions (continued)

Pins

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

JTMS-

SWDIO

A12 A10 D4 46 72 105

C11 F8 73 106

PA13

I/O FT

PA13

-

Not connected

G9 E6 B1 47 74 107

F9 F6 A1 48 75 108

V

S

V

SS_2

DD_2

V

DD_2

JTCK-

SWCLK

A11 A9 B2 49 76 109

A10 A8 C3 50 77 110

PA14

PA15

I/O FT

PA14

SPI3_NSS/

I2S3_WS

TIM2_CH1_ETR

PA15 / SPI1_NSS

JTDI

B11 B9 A2 51 78 111

B10 B8 B3 52 79 112

C10 C8 C4 53 80 113

PC10

PC11

PC12

PD0

I/O FT

PC10

PC11

PC12

UART4_TX/SDIO_D2

UART4_RX/SDIO_D3

UART5_TX/SDIO_CK

USART3_TX

USART3_RX

USART3_CK

CAN_RX

(9)

(10)

E10 D8 D8

D10 E8 D7

5

6

81 114

82 115

I/O FT OSC_IN

FSMC_D2

(9)

(10)

PD1

I/O FT OSC_OUT

FSMC_D3

CAN_TX

TIM3_ETR/UART5_RX

SDIO_CMD

E9 B7 A3 54 83 116

PD2

I/O FT

PD2

D9 C7

C9 D7

B9 B6

-

84 117

85 118

86 119

PD3

PD4

PD5

I/O FT

S

PD3

PD4

PD5

FSMC_CLK

FSMC_NOE

FSMC_NWE

USART2_CTS

USART2_RTS

USART2_TX

E7

F7

-

120

121

V

SS_10

DD_10

SS_10

DD_10

V

S

V

A8 C6

A9 D6

87 122

88 123

PD6

PD7

PG9

I/O FT

PD6

PD7

PG9

FSMC_NWAIT

USART2_RX

USART2_CK

FSMC_NE1/FSMC_NCE2

FSMC_NE2/FSMC_NCE3

E8

D8

-

124

125

FSMC_NCE4_1/

FSMC_NE3

-

PG10

I/O FT

PG10

C8

B8

D7

C7

E6

F6

B7

-

126

127

128

129

130

131

132

PG11

PG12

PG13

PG14

V_{SS_11}

V_{DD_11}

PG15

I/O FT

S

PG11

PG12

PG13

PG14

V_{SS_11}

V_{DD_11}

PG15

FSMC_NCE4_2

FSMC_NE4

FSMC_A24

FSMC_A25

S

I/O FT

34/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Pinouts and pin descriptions

Alternate functions⁽⁴⁾

Table 5.

High-density STM32F103xx pin definitions (continued)

Pins

Main

Pin name

function⁽³⁾

(after reset)

Default

Remap

PB3/TRACESWO

TIM2_CH2 /

A7 A7 A4 55 89 133

A6 A6 B4 56 90 134

PB3/

PB4

I/O FT

JTDO

SPI3_SCK / I2S3_CK/

SPI3_MISO

SPI1_SCK

PB4 / TIM3_CH1

SPI1_MISO

NJTRST

I2C1_SMBA/ SPI3_MOSI

I2S3_SD

TIM3_CH2 /

SPI1_MOSI

B6 C5 A5 57 91 135

C6 B5 B5 58 92 136

PB5

PB6

I/O

PB5

PB6

I/O FT

I2C1_SCL⁽⁸⁾/ TIM4_CH1⁽⁸⁾

USART1_TX

I2C1_SDA⁽⁸⁾

/

D6 A5 C5 59 93 137

PB7

I/O FT

PB7

FSMC_NADV /

USART1_RX

TIM4_CH2⁽⁸⁾

D5 D5 A6 60 94 138

C5 B4 D5 61 95 139

BOOT0

PB8

I

BOOT0

PB8

I2C1_SCL/

CAN_RX

I/O FT

TIM4_CH3⁽⁸⁾/SDIO_D4

TIM4_CH4⁽⁸⁾/SDIO_D5

I2C1_SDA /

CAN_TX

B5 A4 B6 62 96 140

PB9

I/O FT

PB9

A5 D4

A4 C4

-

97 141

98 142

PE0

PE1

I/O FT

PE0

PE1

TIM4_ETR / FSMC_NBL0

FSMC_NBL1

I/O FT

E5 E5 A7 63 99 143

F5 F5 A8 64 100 144

V_{SS_3}

V_{DD_3}

S

V_{SS_3}

V_{DD_3}

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should

be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3

mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load

of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even

after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com.

7. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The V_REF+functionality is provided instead.

8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more

details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,

available from the STMicroelectronics website: www.st.com.

9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the

functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and

LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details,

refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

10. For devices delivered in LQFP64 packages, the FSMC function is not available.

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Pinouts and pin descriptions

STM32F103xC, STM32F103xD, STM32F103xE

Table 6.

Pins

FSMC pin definition

FSMC

LQFP100

BGA100⁽¹⁾

NOR/PSRAM/

CF

CF/IDE

NOR/PSRAM Mux NAND 16 bit

SRAM

PE2

PE3

A23

A19

A20

A21

A22

A0

A23

A19

A20

A21

A22

Yes

PE4

Yes

PE5

Yes

PE6

Yes

PF0

A0

A1

A0

A1

A2

-

PF1

A1

-

PF2

A2

-

PF3

A3

-

PF4

A4

-

PF5

A5

-

PF6

NIORD

NREG

NIOWR

CD

NIORD

NREG

NIOWR

CD

-

PF7

-

PF8

PF9

-

PF10

PF11

PF12

PF13

PF14

PF15

PG0

PG1

PE7

INTR

NIOS16

A6

INTR

-

NIOS16

-

A6

A7

-

A7

-

A8

-

A9

-

A10

A11

D4

-

D4

D5

D4

D5

DA4

DA5

D4

D5

Yes

PE8

D5

PE9

D6

DA6

D6

PE10

PE11

PE12

PE13

PE14

PE15

PD8

D7

DA7

D7

D8

DA8

D8

D9

DA9

D9

D10

D11

D12

D13

D10

D11

D12

D13

D10

D11

D12

D13

DA10

DA11

DA12

DA13

D10

D11

D12

D13

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Pinouts and pin descriptions

Table 6.

Pins

FSMC pin definition (continued)

FSMC

LQFP100

BGA100⁽¹⁾

NOR/PSRAM/

CF

CF/IDE

NOR/PSRAM Mux NAND 16 bit

SRAM

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PG2

PG3

PG4

PG5

PG6

PG7

PD0

D14

D15

D14

D15

D14

D15

A16

A17

A18

D0

DA14

DA15

A16

D14

D15

CLE

ALE

Yes

-

A17

A18

D0

D1

D0

D1

DA0

DA1

D0

D1

A12

A13

A14

A15

-

INT2

INT3

D2

-

D2

D3

D2

D3

D2

D3

DA2

DA3

Yes

-

PD1

D3

PD3

CLK

NOE

NWE

NWAIT

NE1

NE2

NE3

CLK

PD4

NOE

NWE

NOE

NWE

NOE

NWE

NWAIT

NE1

NOE

NWE

PD5

PD6

NWAIT

NCE2

NCE3

PD7

PG9

PG10

PG11

PG12

PG13

PG14

PB7

NE2

NCE4_1 NCE4_1

NCE4_2 NCE4_2

NE3

-

NE4

A24

NE4

A24

-

A25

-

NADV

NBL0

NBL1

NADV

NBL0

NBL1

Yes

PE0

PE1

1. Ports F and G are not available in devices delivered in 100-pin packages.

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Memory mapping

STM32F103xC, STM32F103xD, STM32F103xE

4

Memory mapping

The memory map is shown in Figure 9.

Figure 9. Memory map

Reserved

FSMC register

0xA000 1000 - 0xBFFF FFFF

0xA000 0000 - 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

0x8000 0000 - 0x8FFF FFFF

0x7000 0000 - 0x7FFF FFFF

0x6C00 0000 - 0x6FFF FFFF

0x6800 0000 - 0x6BFF FFFF

0x6400 0000 - 0x67FF FFFF

0x6000 0000 - 0x63FF FFFF

0x4002 4400 - 0x5FFF FFFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0400 - 0x4002 07FF

FSMC bank4 PCCARD

FSMC bank3 NAND (NAND2)

FSMC bank2 NAND (NAND1)

FSMC bank1 NOR/PSRAM 4

FSMC bank1 NOR/PSRAM 3

FSMC bank1 NOR/PSRAM 2

FSMC bank1 NOR/PSRAM 1

Reserved

CRC

Reserved

Flash interface

Reserved

RCC

Reserved

DMA2

DMA1

Reserved

SDIO

0x4002 0000 - 0x4002 03FF

0x4001 8400 - 0x4001 FFFF

0x4001 8000 - 0x4001 83FF

Reserved

ADC3

USART1

TIM8

SPI1

TIM1

0x4001 400 - 0x4001 7FFF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0xFFFF FFFF

512-Mbyte

block 7

ADC2

0x4001 2800 - 0x4001 2BFF

Cortex-M3's

internal

peripherals

ADC1

Port G

Port F

0x4001 2400 - 0x4001 27FF

0x4001 2000 - 0x4001 23FF

0x4001 1C00 - 0x4001 1FFF

0x4001 1800 - 0x4001 1BFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0C00 - 0x4001 0FFF

0x4001 0800 - 0x4001 0BFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 7800 - 0x4000 FFFF

0xE000 0000

0xDFFF FFFF

Port E

Port D

Port C

Port B

Port A

EXTI

AFIO

Reserved

DAC

PWR

512-Mbyte

block 6

Not used

0xC000 0000

0xBFFF FFFF

512-Mbyte

block 5

FSMC register

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

BKP

Reserved

BxCAN

0xA000 0000

0x9FFF FFFF

512-Mbyte

block 4

FSMC bank 3

& bank4

Shared USB/CAN SRAM 512

0x4000 6000 - 0x4000 63FF

bytes

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

USB registers

I2C2

0x8000 0000

0x7FFF FFFF

I2C1

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 1800 - 0x4000 27FF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

UART5

UART4

512-Mbyte

block 3

FSMC bank1

& bank2

USART3

USART2

0x6000 0000

0x5FFF FFFF

Reserved

SPI3/I²S3

SPI2/I²S2

512-Mbyte

block 2

Peripherals

Reserved

IWDG

0x4000 0000

0x3FFF FFFF

WWDG

RTC

512-Mbyte

block 1

SRAM

Reserved

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

0x2000 0000

0x1FFF FFFF

512-Mbyte

block 0

Code

0x0000 0000

0x3FFF FFFF

Reserved

0x2001 0000

0x2000 FFFF

SRAM (64 KB aliased

by bit-banding)

0x2000 0000

Option Bytes

0x1FFF F800 - 0x1FFF F80F

0x1FFF F000- 0x1FFF F7FF

0x1FFF EFFF

0x0808 0000

0x0807 FFFF

0x0800 0000

0x07FF FFFF

0x0008 0000

System memory

Reserved

Flash

Reserved

Aliased to Flash or system 0x0007 FFFF

memory depending on

ai14753d

BOOT pins

0x0000 0000

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5

Electrical characteristics

5.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

5.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3).

5.1.2

5.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the

A

DD

2 V  V  3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean 2).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

5.1.4

5.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

Figure 10. Pin loading conditions

Figure 11. Pin input voltage

STM32F103xx pin

C = 50 pF

STM32F103xx pin

V

IN

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.1.6

Power supply scheme

Figure 12. Power supply scheme

V

BAT

Backup circuitry

(OSC32K,RTC,

Power switch

1.8-3.6V

Wake-up logic

Backup registers)

OUT

IO

Logic

GP I/Os

IN

Kernel logic

(CPU,

Digital

& Memories)

V

DD

V

DD1/2/.../11

Regulator

11 × 100 nF

+ 1 × 4.7 µF

V

SS1/2/.../11

V

DD

V

DDA

V

REF

V

REF+

Analog:

RCs, PLL,

...

10 nF

+ 1 µF

10 nF

+ 1 µF

V

ADC

REF-

V

SSA

ai15401

Caution:

In Figure 12, the 4.7 µF capacitor must be connected to V

.

DD3

5.1.7

Current consumption measurement

Figure 13. Current consumption measurement scheme

I

_V

DD BAT

V

BAT

I

DD

V

DD

V

DDA

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics,

Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device

at these conditions is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Table 7.

Symbol

Voltage characteristics

Ratings

External main supply voltage (including V_DDA

Min

Max

Unit

V_DD–V_SS

–0.3

4.0

(1)

and V_DD

)

V

Input voltage on five volt tolerant pin⁽²⁾

Input voltage on any other pin⁽²⁾

V_SS 0.3

V_SS0.3

+5.5

V_DD+0.3

50

V_IN

|V_DDx

|

Variations between different V_DDpower pins

Variations between all the different ground pins

mV

|V_SSXV_SS

|

50

see Section 5.3.12:

Absolute maximum ratings

(electrical sensitivity)

Electrostatic discharge voltage (human body

model)

V_ESD(HBM)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. I_INJ(PIN)must never be exceeded (see Table 8: Current characteristics). This is implicitly insured if V_IN

maximum is respected. If V_INmaximum cannot be respected, the injection current must be limited

externally to the I_INJ(PIN)value. A positive injection is induced by V_IN> V_INmax while a negative injection is

induced by V_IN< V_SS

.

Table 8.

Symbol

I_VDD

I_VSS

Current characteristics

Ratings

Max.

Unit

Total current into V_DD/V_DDApower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on NRST pin

150

25

 25

5

I_IO

mA

(2)(3)

I_INJ(PIN)

Injected current on HSE OSC_IN and LSE OSC_IN pins

Injected current on any other pin⁽⁴⁾

5

Total injected current (sum of all I/O and control pins)⁽⁴⁾

25

(2)

I_INJ(PIN)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN> V_DDwhile a negative injection is induced by V_IN< V_SS

.

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.18: 12-bit ADC

characteristics.

4. When several inputs are submitted to a current injection, the maximum I_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterization with I_INJ(PIN)maximum current injection on four I/O port pins of the device.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 9.

Thermal characteristics

Ratings

Symbol

Value

Unit

T_STG

T_J

Storage temperature range

–65 to +150

150

°C

Maximum junction temperature

5.3

Operating conditions

5.3.1

General operating conditions

Table 10. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK1

f_PCLK2

V_DD

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

0

2

72

36

72

3.6

MHz

V

Analog operating voltage

(ADC not used)

2

3.6

Must be the same potential

as V_DD

(1)

V_DDA

V

(2)

Analog operating voltage

(ADC used)

2.4

1.8

V_BAT

Backup operating voltage

3.6

666

434

444

500

85

LQFP144

LQFP100

LQFP64

Power dissipation at T_A=

85 °C for suffix 6 or T_A=

105 °C for suffix 7⁽³⁾

P_D

mW

LFBGA100

LFBGA144

Maximum power dissipation –40

Low power dissipation⁽⁴⁾

–40

Maximum power dissipation –40

Ambient temperature for 6

suffix version

°C

105

125

105

125

TA

TJ

Ambient temperature for 7

suffix version

Low power dissipation⁽⁴⁾

–40

6 suffix version

Junction temperature range

7 suffix version

1. When the ADC is used, refer to Table 58: ADC characteristics.

2. It is recommended to power V_DDand V_DDAfrom the same source. A maximum difference of 300 mV

between V_DDand V_DDAcan be tolerated during power-up and operation.

3. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax (see Table 6.2: Thermal

characteristics on page 114).

4. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax (see

Table 6.2: Thermal characteristics on page 114).

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.3.2

Operating conditions at power-up / power-down

The parameters given in Table 11 are derived from tests performed under the ambient

temperature condition summarized in Table 10.

Table 11. Operating conditions at power-up / power-down

Symbol

Parameter

Conditions

Min

Max



Unit

V_DDrise time rate

0

t_VDD

µs/V

V

_DDfall time rate

20



5.3.3

Embedded reset and power control block characteristics

The parameters given in Table 12 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 10.

DD

Table 12. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

2.1 2.18 2.26

2.08 2.16

V

2

2.19 2.28 2.37

2.09 2.18 2.27

2.28 2.38 2.48

2.18 2.28 2.38

2.38 2.48 2.58

2.28 2.38 2.48

2.47 2.58 2.69

2.37 2.48 2.59

2.57 2.68 2.79

2.47 2.58 2.69

2.66 2.78 2.9

2.56 2.68 2.8

V

Programmable voltage

detector level selection

V_PVD

V

2.76 2.88

3

V

2.66 2.78 2.9

100

V

(2)

V_PVDhyst

PVD hysteresis

mV

V

1.8⁽¹⁾

Falling edge

Rising edge

1.88 1.96

Power on/power down

reset threshold

V_POR/PDR

1.84 1.92 2.0

40

V

(2)

V_PDRhyst

PDR hysteresis

mV

mS

(2)

T_RSTTEMPO

Reset temporization

1

2.5

4.5

1. The product behavior is guaranteed by design down to the minimum V_POR/PDRvalue.

2. Guaranteed by design, not tested in production.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.4

Embedded reference voltage

The parameters given in Table 13 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 10.

DD

Table 13. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Max

Unit

Typ

–40 °C < T_A< +105 °C 1.16 1.20 1.26

–40 °C < T_A< +85 °C 1.16 1.20 1.24

V

V_REFINTInternal reference voltage

ADC sampling time when

reading the internal reference

voltage

(1)

T_{S_vrefint}

5.1

17.1⁽²⁾

µs

Internal reference voltage

spread over the temperature

range

(2)

V_RERINT

V_DD= 3 V 10 mV

10

mV

(2)

T_Coeff

Temperature coefficient

100 ppm/°C

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

5.3.5

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 13: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a

reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V or V (no load)

DD SS

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted to the f frequency (0 wait state from 0

HCLK

to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)

●

Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f

= f

/2, f

= f

PCLK1

HCLK

PCLK2 HCLK

The parameters given in Table 14, Table 15 and Table 16 are derived from tests performed

under ambient temperature and V supply voltage conditions summarized in Table 10.

DD

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 14. Maximum current consumption in Run mode, code with data processing

running from Flash

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C T_A= 105 °C

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

69

50

70

50.5

39.5

28

External clock⁽²⁾, all

peripherals enabled

39

27

20

20.5

11.5

37.5

28.5

22.5

17

11

Supplycurrent in

Run mode

I_DD

mA

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

37

28

External clock⁽²⁾, all

peripherals disabled

22

16.5

12.5

8

13

8

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

Table 15. Maximum current consumption in Run mode, code with data processing

running from RAM

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C

T_A= 105 °C

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

66

43.5

33

23

16

9

67

45.5

35

External clock⁽²⁾, all

peripherals enabled

24.5

18

10.5

33.5

23.5

18.5

13.5

10.5

6.5

Supply current

in Run mode

I_DD

mA

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

33

23

18

13

10

6

External clock⁽²⁾, all

peripherals disabled

1. Data based on characterization results, tested in production at V_DDmax, f_HCLKmax.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled

70

8 MHz

16 MHz

24 MHz

60

36 MHz

48 MHz

72 MHz

50

40

30

20

10

0

-45

25

70

85

105

Temperature (°C)

Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled

35

8 MHz

16 MHz

30

24 MHz

36 MHz

48 MHz

25

72 MHz

20

15

10

5

0

-45

25

70

85

105

Temperature (°C)

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 16. Maximum current consumption in Sleep mode, code running from Flash

or RAM

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 85 °C T_A= 105 °C

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

45

31

24

17

12.5

8

46

32

25

17.5

13

8

External clock⁽²⁾, all

peripherals enabled

Supply current

in Sleep mode

I_DD

mA

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

8.5

7

9

7.5

6.5

5.5

5

External clock⁽²⁾, all

peripherals disabled

6

5

4.5

4

1. Based on characterization, tested in production at V_DDmax, f_HCLKmax with peripherals enabled.

2. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 17. Typical and maximum current consumptions in Stop and Standby modes

Typ⁽¹⁾

Max

Symbol

Parameter

Conditions

Unit

V_DD/V_BATV_DD/V_BATV_DD/V_BATT_A=

T_A=

= 2.0 V = 2.4 V = 3.3 V 85 °C 105 °C

Regulator in run mode, low-speed

and high-speed internal RC

oscillators and high-speed oscillator

OFF (no independent watchdog)

34.5

24.5

35

25

379

365

1130

1110

Supply current in

Stop mode

Regulator in low-power mode, low-

speed and high-speed internal RC

oscillators and high-speed oscillator

OFF (no independent watchdog)

I_DD

Low-speed internal RC oscillator

and independent watchdog ON

µA

3

3.8

3.6

-

Low-speed internal RC oscillator

ON, independent watchdog OFF

Supply current in

Standby mode

2.8

Low-speed internal RC oscillator

and independent watchdog OFF,

low-speed oscillator and RTC OFF

1.9

1.1

2.1

1.4

5⁽²⁾

6.5⁽²⁾

2.3⁽²⁾

Backup domain

I

Low-speed oscillator and RTC ON

1.05

2⁽²⁾

^DD_VBATsupply current

1. Typical values are measured at T_A= 25 °C.

2. Based on characterization, not tested in production.

Figure 16. Typical current consumption on V

values

with RTC on vs. temperature at different V

BAT

2.5

2

1.8 V

2 V

1.5

1

2.4 V

3.3 V

3.6 V

0.5

0

–45

25

85

105

Temperature (°C)

ai17337

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 17. Typical current consumption in Stop mode with regulator in run mode

versus temperature at different V values

DD

700

600

500

400

300

200

100

0

2.4V

2.7V

3.0V

3.3V

3.6V

-45

25

70

85

105

Temperature (°C)

Figure 18. Typical current consumption in Stop mode with regulator in low-power

mode versus temperature at different V values

DD

700

600

500

400

300

200

100

0

2.4V

2.7V

3.0V

3.3V

3.6V

-45

25

70

85

105

Temperature (°C)

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 19. Typical current consumption in Standby mode versus temperature at

different V values

DD

4.5

4

3.5

3

2.5

2

1.5

1

2.4V

2.7V

3.0V

3.3V

3.6V

0.5

0

-45

25

70

85

105

Temperature (°C)

Typical current consumption

The MCU is placed under the following conditions:

●

All I/O pins are in input mode with a static value at V or V (no load).

DD SS

All peripherals are disabled except if it is explicitly mentioned.

The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1

HCLK

wait state from 24 to 48 MHZ and 2 wait states above).

●

Ambient temperature and V supply voltage conditions summarized in Table 10.

DD

Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled f

= f

/4, f

2 = f

/2, f

= f

/4

PCLK1

HCLK

PCLK

HCLK

ADCCLK

PCLK2

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 18. Typical current consumption in Run mode, code with data processing

running from Flash

Typ⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

Allperipherals Allperipherals

enabled⁽²⁾

disabled

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

51

34.6

26.6

18.5

12.8

7.2

4.2

2.7

2

30.5

20.7

16.2

11.4

8.2

5

External clock⁽³⁾

mA

4 MHz

3.1

2.1

1.7

1.4

1.2

27

2 MHz

1 MHz

500 kHz

125 kHz

64 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

1.6

1.3

45

Supply

I_DD

current in

Run mode

34

20.1

15.6

10.8

7.6

4.4

2.5

1.5

1.1

0.8

0.6

26

17.9

12.2

6.6

3.6

2.1

1.4

1

Running on high

speed internal RC

(HSI), AHB

prescaler used to

reduce the

mA

4 MHz

frequency

2 MHz

1 MHz

500 kHz

125 kHz

0.7

1. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this

consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 19. Typical current consumption in Sleep mode, coderunning from Flash or

RAM

Typ⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Unit

All peripherals All peripherals

enabled⁽²⁾

disabled

72 MHz

48 MHz

36 MHz

24 MHz

16 MHz

8 MHz

29.5

20

6.4

4.6

3.6

2.6

2

15.1

10.4

7.2

External clock⁽³⁾

3.9

1.3

1.2

1.15

1.1

1.05

5.1

4

4 MHz

2.6

2 MHz

1.85

1.5

1 MHz

500 kHz

125 kHz

64 MHz

48 MHz

36 MHz

24 MHz

16 MHz

1.3

Supply

1.2

I_DD

current in

mA

25.6

19.4

14.5

9.8

Sleep mode

3

2

Running on high

speed internal RC

6.6

1.4

0.7

0.6

0.55

0.5

0.45

(HSI), AHB prescaler 8 MHz

3.3

used to reduce the

frequency

4 MHz

2

2 MHz

1.25

0.9

1 MHz

500 kHz

125 kHz

0.7

0.6

1. Typical values are measures at T_A= 25 °C, V_DD= 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this

consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f_HCLK> 8 MHz.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed

under the following conditions:

●

all I/O pins are in input mode with a static value at V or V (no load)

DD SS

all peripherals are disabled unless otherwise mentioned

the given value is calculated by measuring the current consumption

–

with all peripherals clocked off

with only one peripheral clocked on

●

ambient operating temperature and V supply voltage conditions summarized in

DD

Table 7

(1)

Table 20. Peripheral current consumption

Peripheral

Unit

Typical consumption at 25 °C

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

SPI2

SPI3

1.2

0.4

0.2

0.4

0.5

0.6

0.4

0.65

0.72

APB1

USART2

USART3

UART4

UART5

I2C1

mA

I2C2

USB

CAN

DAC

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Table 20. Peripheral current consumption

(continued)

Peripheral

Typical consumption at 25 °C

Unit

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

ADC1⁽²⁾

ADC2

0.55

0.72

0.55

1

0.72

1

APB2

mA

1.9

1.7

1.8

0.4

1.7

0.9

1.7

TIM1

SPI1

TIM8

USART1

ADC3

1. f_HCLK= 72 MHz, f_APB1= f_HCLK/2, f_APB2= f_HCLK, default prescaler value for each peripheral.

2. Specific conditions for ADC: f_HCLK= 56 MHz, f_APB1= f_HCLK/2, f_APB2= f_HCLK, f_ADCCLK= f_APB2/4, ADON bit

in the ADC_CR2 register is set to 1.

5.3.6

External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Table 21 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 10.

Table 21. High-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency⁽¹⁾

f_{HSE_ext}

1

8

25

MHz

V_HSEH

V_HSEL

t_w(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

0.7V_DD

V_SS

V_DD

V

0.3V_DD

OSC_IN high or low time⁽¹⁾

OSC_IN rise or fall time⁽¹⁾

16

45

t_w(HSE)

ns

t_r(HSE)

t_f(HSE)

20

C_in(HSE)OSC_IN input capacitance⁽¹⁾

5

pF

%

DuCy_(HSE)Duty cycle

55

1

I_L

OSC_IN Input leakage current

V_SS V_IN V_DD

µA

1. Guaranteed by design, not tested in production.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Low-speed external user clock generated from an external source

The characteristics given in Table 22 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 10.

Table 22. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User External clock source

frequency⁽¹⁾

f_{LSE_ext}

32.768

1000

kHz

OSC32_IN input pin high level

voltage

V_LSEH

V_LSEL

t_w(LSE)

0.7V_DD

V_SS

V_DD

V

OSC32_IN input pin low level

voltage

0.3V_DD

OSC32_IN high or low time⁽¹⁾

OSC32_IN rise or fall time⁽¹⁾

450

t_w(LSE)

ns

t_r(LSE)

t_f(LSE)

50

C_in(LSE)OSC32_IN input capacitance⁽¹⁾

5

pF

%

DuCy_(LSE)Duty cycle

30

70

1

V_SS V_IN V_D

I_L

OSC32_IN Input leakage current

µA

D

1. Guaranteed by design, not tested in production.

Figure 20. High-speed external clock source AC timing diagram

V

HSEH

90%

10%

V

HSEL

t

W(HSE)

t

W(HSE)

r(HSE)

f(HSE)

T

HSE

f

HSE_ext

EXTERNAL

CLOCK SOURCE

I

L

OSC _IN

STM32F103xx

ai14143

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 21. Low-speed external clock source AC timing diagram

V

LSEH

90%

10%

V

LSEL

t

W(LSE)

t

W(LSE)

r(LSE)

f(LSE)

T

LSE

f

LSE_ext

EXTERNAL

CLOCK SOURCE

I

L

OSC32_IN

STM32F103xx

ai14144b

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 23. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

(1)(2)

Table 23. HSE 4-16 MHz oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

f_{OSC_IN}Oscillator frequency

4

8

16

MHz

R_F

C

Feedback resistor

200

k

Recommended load capacitance

versus equivalent serial

R_S= 30

30

pF

resistance of the crystal (R_S)⁽³⁾

V_DD= 3.3 V, V_IN= V_SS

with 30 pF load

i₂

HSE driving current

1

mA

g_m

Oscillator transconductance

Startup time

Startup

25

mA/V

ms

(4)

t_SU(HSE)

V_DDis stabilized

2

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization results, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a

humid environment, due to the induced leakage and the bias condition change. However, it is

recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

For C and C , it is recommended to use high-quality external ceramic capacitors in the

L1

L2

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 22). C and C are usually the

L1

L2

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of C and C . PCB and MCU pin capacitance must be included (10 pF

L1

L2

can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C . Refer to the application note AN2867 “Oscillator design guide for ST

C

L1

L2

microcontrollers” available from the ST website www.st.com.

Figure 22. Typical application with an 8 MHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC_IN

HSE

Bias

controlled

gain

8 MHz

resonator

R

F

STM32F103xx

OSC_OUT

(1)

R

EXT

C

ai14145

L2

1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on characterization

results obtained with typical external components specified in Table 24. In the application,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

(1)

Table 24. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Feedback resistor

Conditions

Min

Typ Max Unit

R_F

5

M

Recommended load capacitance

versus equivalent serial

C⁽²⁾

R_S= 30 k

15

pF

resistance of the crystal (R_S)⁽³⁾

I₂

LSE driving current

Oscillator transconductance

Startup time

V_DD= 3.3 V, V_IN= V_SS

1.4

µA

µA/V

s

g_m

5

(4)

t_SU(LSE)

V_DDis stabilized

3

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator

design guide for ST microcontrollers”.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with

small R_Svalue for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details

4. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary

significantly with the crystal manufacturer

Note:

For C and C , it is recommended to use high-quality ceramic capacitors in the 5 pF to

L1 L2

15 pF range selected to match the requirements of the crystal or resonator (see Figure 23).

and C are usually the same size. The crystal manufacturer typically specifies a load

C

L1

L2,

capacitance which is the series combination of C and C .

L1

L2

Load capacitance C has the following formula: C = C x C / (C + C ) + C where

L

L1

L2

L1

L2

stray

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

between 2 pF and 7 pF.

Caution:

To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended

L1

L2

to use a resonator with a load capacitance C  7 pF. Never use a resonator with a load

L

capacitance of 12.5 pF.

Example: if you choose a resonator with a load capacitance of C = 6 pF, and C

= 2 pF,

L

stray

then C = C = 8 pF.

L1

L2

Figure 23. Typical application with a 32.768 kHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC32_IN

LSE

Bias

controlled

gain

32.768 kHz

resonator

R

F

STM32F103xx

OSC32_OUT

C

L2

ai14146

5.3.7

Internal clock source characteristics

The parameters given in Table 25 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 10.

DD

High-speed internal (HSI) RC oscillator

(1)

Table 25. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ

Max Unit

f_HSI

8

MHz

User-trimmed with the RCC_CR

register⁽²⁾

1⁽³⁾

%

T_A= –40 to 105 °C

–2

2.5

2.2

2

%

Accuracy of the HSI

oscillator

ACC_HSI

T_A= –10 to 85 °C

Factory-

–1.5

–1.3

–1.1

calibrated⁽⁴⁾

T_A= 0 to 70 °C

T_A= 25 °C

1.8

HSI oscillator

startup time

(4)

t_su(HSI)

1

2

µs

HSI oscillator power

consumption

(4)

I_DD(HSI)

80

100

µA

1. V_DD= 3.3 V, T_A= –40 to 105 °C unless otherwise specified.

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from

the ST website www.st.com.

3. Guaranteed by design, not tested in production.

4. Based on characterization, not tested in production.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Low-speed internal (LSI) RC oscillator

Electrical characteristics

(1)

Table 26. LSI oscillator characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(2)

f_LSI

Frequency

30

40

60

85

kHz

µs

(3)

t_su(LSI)

LSI oscillator startup time

(3)

I_DD(LSI)

LSI oscillator power consumption

0.65

1.2

µA

1.

V_DD= 3 V, T_A= –40 to 105 °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Wakeup time from low-power mode

The wakeup times given in Table 27 is measured on a wakeup phase with a 8-MHz HSI RC

oscillator. The clock source used to wake up the device depends from the current operating

mode:

●

Stop or Standby mode: the clock source is the RC oscillator

●

Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V supply

DD

voltage conditions summarized in Table 10.

Table 27. Low-power mode wakeup timings

Symbol

Parameter

Wakeup from Sleep mode

Typ

Unit

(1)

1.8

µs

t_WUSLEEP

Wakeup from Stop mode (regulator in run mode)

3.6

5.4

(1)

µs

t_WUSTOP

Wakeup from Stop mode (regulator in low power mode)

(1)

Wakeup from Standby mode

50

t_WUSTDBY

1. The wakeup times are measured from the wakeup event to the point in which the user application code

reads the first instruction.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.8

PLL characteristics

The parameters given in Table 28 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 10.

DD

Table 28. PLL characteristics

Value

Symbol

Parameter

Unit

Min

Typ

Max⁽¹⁾

PLL input clock⁽²⁾

1

8.0

25

60

MHz

%

f_{PLL_IN}

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

40

16

f_{PLL_OUT}

t_LOCK

72

MHz

µs

200

300

Jitter

Cycle-to-cycle jitter

ps

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

the range defined by f_{PLL_OUT}

.

5.3.9

Memory characteristics

Flash memory

The characteristics are given at T = –40 to 105 °C unless otherwise specified.

A

Table 29. Flash memory characteristics

Symbol

Parameter

Conditions

Min

Typ

Max⁽¹⁾Unit

t_prog

16-bit programming time T_A–40 to +105 °C

40

20

52.5

70

40

µs

ms

t_ERASEPage (2 KB) erase time T_A–40 to +105 °C

t_ME

Mass erase time

Supply current

T_A–40 to +105 °C

Read mode

f_HCLK= 72 MHz with 2 wait

states, V_DD= 3.3 V

28

mA

Write mode

f_HCLK= 72 MHz, V_DD= 3.3 V

7

5

mA

I_DD

Erase mode

f_HCLK= 72 MHz, V_DD= 3.3 V

Power-down mode / Halt,

50

µA

V

V_DD= 3.0 to 3.6 V

V_progProgramming voltage

2

3.6

1. Guaranteed by design, not tested in production.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 30. Flash memory endurance and data retention

Value

Unit

Symbol

Parameter

Conditions

Min⁽¹⁾

Typ

Max

T_A= –40 to +85 °C (6 suffix versions)

T_A= –40 to +105 °C (7 suffix versions)

N_ENDEndurance

kcycles

Years

10

1 kcycle⁽²⁾at T_A= 85 °C

30

10

20

t_RET

Data retention 1 kcycle⁽²⁾at T_A= 105 °C

10 kcycles⁽²⁾at T_A= 55 °C

1. Based on characterization not tested in production.

2. Cycling performed over the whole temperature range.

5.3.10

FSMC characteristics

Asynchronous waveforms and timings

Figure 24 through Figure 27 represent asynchronous waveforms and Table 31 through

Table 34 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

●

AddressSetupTime = 0

AddressHoldTime = 1

DataSetupTime = 1

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

t

w(NE)

FSMC_NE

t

h(NE_NOE)

w(NOE)

v(NOE_NE)

FSMC_NOE

FSMC_NWE

t_{v(A_NE)}

t

h(A_NOE)

FSMC_A[25:0]

Address

t_{v(BL_NE)}

t

h(BL_NOE)

FSMC_NBL[1:0]

t

h(Data_NE)

t

su(Data_NOE)

h(Data_NOE)

t

su(Data_NE)

Data

FSMC_D[15:0]

FSMC_NADV⁽¹⁾

t

v(NADV_NE)

t

w(NADV)

ai14991B

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

(1) (2)

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

Symbol Parameter Min Max

t_w(NE)FSMC_NE low time 5T_HCLK– 1.5 5T_HCLK+ 2

t_{v(NOE_NE)}0.5 1.5

t_w(NOE)

t_{h(NE_NOE)}

t_{v(A_NE)}

Unit

ns

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

5T_HCLK– 1.5 5T_HCLK+ 1.5 ns

FSMC_NOE high to FSMC_NE high hold time –1.5

FSMC_NEx low to FSMC_A valid

ns

7

0

t_{h(A_NOE)}

t_{v(BL_NE)}

t_{h(BL_NOE)}

Address hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

0.1

FSMC_BL hold time after FSMC_NOE high

0

t_{su(Data_NE)}Data to FSMC_NEx high setup time

t_{su(Data_NOE)}Data to FSMC_NOEx high setup time

t_{h(Data_NOE)}Data hold time after FSMC_NOE high

2T_HCLK+ 25

0

t_{h(Data_NE)}

Data hold time after FSMC_NEx high

t_{v(NADV_NE)}FSMC_NEx low to FSMC_NADV low

5

t_w(NADV)

FSMC_NADV low time

T_HCLK+ 1.5

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

t

w(NE)

FSMC_NEx

FSMC_NOE

FSMC_NWE

t

h(NE_NWE)

v(NWE_NE)

w(NWE)

t

t_{v(A_NE)}

h(A_NWE)

FSMC_A[25:0]

Address

t_{v(BL_NE)}

t

h(BL_NWE)

FSMC_NBL[1:0]

NBL

t

v(Data_NE)

h(Data_NWE)

Data

FSMC_D[15:0]

t

v(NADV_NE)

t

w(NADV)

(1)

FSMC_NADV

ai14990

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

(1)(2)

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

Symbol

t_w(NE)

t_{v(NWE_NE)}

t_w(NWE)

t_{h(NE_NWE)}

t_{v(A_NE)}

Parameter

FSMC_NE low time

Min

Max

Unit

ns

3T_HCLK– 1

T_HCLK– 0.5

3T_HCLK+ 2

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

T_HCLK+ 1.5 ns

ns

FSMC_NWE high to FSMC_NE high hold time T_HCLK

FSMC_NEx low to FSMC_A valid

7.5

ns

t_{h(A_NWE)}

t_{v(BL_NE)}

t_{h(BL_NWE)}

t_{v(Data_NE)}

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

FSMC_NEx low to Data valid

T_HCLK

1.5

T_HCLK– 0.5

T_HCLK+ 7

t_{h(Data_NWE)}Data hold time after FSMC_NWE high

t_{v(NADV_NE)}FSMC_NEx low to FSMC_NADV low

T_HCLK

5.5

t_w(NADV)

FSMC_NADV low time

T_HCLK+ 1.5 ns

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms

t

w(NE)

FSMC_NE

t

h(NE_NOE)

v(NOE_NE)

FSMC_NOE

t

w(NOE)

FSMC_NWE

t

t_{v(A_NE)}

h(A_NOE)

FSMC_A[25:16]

Address

t_{v(BL_NE)}

t

h(BL_NOE)

FSMC_NBL[1:0]

NBL

t

h(Data_NE)

t

su(Data_NE)

t

h(Data_NOE)

v(A_NE)

su(Data_NOE)

Address

Data

FSMC_AD[15:0]

FSMC_NADV

t

t_{h(AD_NADV)}

v(NADV_NE)

t

w(NADV)

ai14892b

(1)(2)

Table 33. Asynchronous multiplexed PSRAM/NOR read timings

Symbol

t_w(NE)

t_{v(NOE_NE)}

t_w(NOE)

t_{h(NE_NOE)}

t_{v(A_NE)}

Parameter

FSMC_NE low time

Min

Max

7T_HCLK+ 2

Unit

ns

7T_HCLK– 2

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

3T_HCLK– 0.5 3T_HCLK+ 1.5 ns

4T_HCLK– 1

4T_HCLK+ 2

ns

FSMC_NOE high to FSMC_NE high hold time –1

FSMC_NEx low to FSMC_A valid

0

t_{v(NADV_NE)}FSMC_NEx low to FSMC_NADV low

3

5

t_w(NADV)

FSMC_NADV low time

T_HCLK–1.5

T_HCLK+ 1.5

FSMC_AD (address) valid hold time after

FSMC_NADV high

t_{h(AD_NADV)}

T_HCLK

ns

t_{h(A_NOE)}

t_{h(BL_NOE)}

t_{v(BL_NE)}

Address hold time after FSMC_NOE high

FSMC_BL hold time after FSMC_NOE high

FSMC_NEx low to FSMC_BL valid

T_HCLK

0

ns

0

t_{su(Data_NE)}Data to FSMC_NEx high setup time

t_{su(Data_NOE)}Data to FSMC_NOE high setup time

2T_HCLK+ 24

2T_HCLK+ 25

t_{h(Data_NE)}

Data hold time after FSMC_NEx high

0

t_{h(Data_NOE)}Data hold time after FSMC_NOE high

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

64/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms

t

w(NE)

FSMC_NEx

FSMC_NOE

t

h(NE_NWE)

v(NWE_NE)

w(NWE)

FSMC_NWE

t

t_{v(A_NE)}

h(A_NWE)

FSMC_A[25:16]

Address

t_{v(BL_NE)}

t

h(BL_NWE)

FSMC_NBL[1:0]

FSMC_AD[15:0]

NBL

t

h(Data_NWE)

t

v(A_NE)

v(Data_NADV)

Address

Data

t

t_{h(AD_NADV)}

v(NADV_NE)

t

w(NADV)

FSMC_NADV

ai14891B

(1)(2)

Table 34. Asynchronous multiplexed PSRAM/NOR write timings

Symbol

t_w(NE)

t_{v(NWE_NE)}

t_w(NWE)

t_{h(NE_NWE)}

t_{v(A_NE)}

Parameter

FSMC_NE low time

Min

Max

Unit

5T_HCLK– 1

2T_HCLK

5T_HCLK+ 2

2T_HCLK+ 1

2T_HCLK+ 2

ns

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

2T_HCLK– 1

T_HCLK– 1

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

7

t_{v(NADV_NE)}FSMC_NEx low to FSMC_NADV low

3

5

t_w(NADV)

FSMC_NADV low time

T_HCLK– 1

T_HCLK+ 1

FSMC_AD (address) valid hold time after

FSMC_NADV high

t_{h(AD_NADV)}

T

_HCLK– 3

ns

t_{h(A_NWE)}

t_{v(BL_NE)}

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

4T_HCLK

ns

1.6

t_{h(BL_NWE)}

FSMC_BL hold time after FSMC_NWE high

T_HCLK– 1.5

t_{v(Data_NADV)}FSMC_NADV high to Data valid

T_HCLK+ 1.5 ns

ns

t_{h(Data_NWE)}Data hold time after FSMC_NWE high

T_HCLK– 5

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Synchronous waveforms and timings

Figure 28 through Figure 31 represent synchronous waveforms and Table 36 through

Table 38 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

●

BurstAccessMode = FSMC_BurstAccessMode_Enable;

MemoryType = FSMC_MemoryType_CRAM;

WriteBurst = FSMC_WriteBurst_Enable;

CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)

DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

Figure 28. Synchronous multiplexed NOR/PSRAM read timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

Data latency = 1

d(CLKL-NExL)

t

d(CLKH-NExH)

FSMC_NEx

t

d(CLKL-NADVL)

d(CLKL-NADVH)

FSMC_NADV

t

d(CLKH-AIV)

d(CLKL-AV)

FSMC_A[25:16]

t

d(CLKH-NOEH)

d(CLKL-NOEL)

FSMC_NOE

t

h(CLKH-ADV)

d(CLKL-ADIV)

t

su(ADV-CLKH)

d(CLKL-ADV)

h(CLKH-ADV)

FSMC_AD[15:0]

AD[15:0]

t

D1

D2

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

t

h(CLKH-NWAITV)

su(NWAITV-CLKH)

ai14893e

66/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

(1)(2)

Table 35. Synchronous multiplexed NOR/PSRAM read timings

Symbol Parameter

t_w(CLK)

Min

27.7

Max

Unit

FSMC_CLK period

ns

t_d(CLKL-NExL)

t_d(CLKH-NExH)

t_{d(CLKL-NADVL)}

t_{d(CLKL-NADVH)}

t_d(CLKL-AV)

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

1.5

T_HCLK+ 2

4

0

FSMC_CLK low to FSMC_NADV high

5

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

t_d(CLKH-AIV)

FSMC_CLK high to FSMC_Ax invalid (x = 16...25) T_HCLK+ 2

FSMC_CLK low to FSMC_NOE low

t_d(CLKL-NOEL)

t_d(CLKH-NOEH)

t_d(CLKL-ADV)

t_d(CLKL-ADIV)

T_HCLK+1 ns

ns

FSMC_CLK high to FSMC_NOE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid

T_HCLK+ 0.5

12

ns

0

6

FSMC_A/D[15:0] valid data before FSMC_CLK

high

t_su(ADV-CLKH)

t_h(CLKH-ADV)

ns

FSMC_A/D[15:0] valid data after FSMC_CLK high T_HCLK– 10

ns

t_{su(NWAITV-CLKH)}FSMC_NWAIT valid before FSMC_CLK high

t_{h(CLKH-NWAITV)}FSMC_NWAIT valid after FSMC_CLK high

8

2

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 29. Synchronous multiplexed PSRAM write timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

Data latency = 1

d(CLKL-NExL)

t

d(CLKH-NExH)

FSMC_NEx

t

d(CLKL-NADVL)

d(CLKL-NADVH)

FSMC_NADV

t

d(CLKH-AIV)

d(CLKL-AV)

FSMC_A[25:16]

FSMC_NWE

t

d(CLKL-NWEL)

d(CLKH-NWEH)

t

d(CLKL-ADIV)

t

d(CLKL-Data)

D1

t

d(CLKL-Data)

d(CLKL-ADV)

FSMC_AD[15:0]

AD[15:0]

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

FSMC_NBL

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

t

d(CLKL-NBLH)

ai14992d

68/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

(1)(2)

Table 36. Synchronous multiplexed PSRAM write timings

Symbol Parameter

t_w(CLK)

Min

27.7

Max

Unit

FSMC_CLK period

ns

t_d(CLKL-NExL)

t_d(CLKH-NExH)

t_{d(CLKL-NADVL)}

t_{d(CLKL-NADVH)}

t_d(CLKL-AV)

FSMC_CLK low to FSMC_Nex low (x = 0...2)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

2

T_HCLK+ 2

4

FSMC_CLK low to FSMC_NADV high

5

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK high to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NWE low

0

t_d(CLKH-AIV)

T_CK+ 2

T_HCLK+1

3

t_d(CLKL-NWEL)

t_d(CLKH-NWEH)

t_d(CLKL-ADV)

t_d(CLKL-ADIV)

t_d(CLKL-Data)

1

FSMC_CLK high to FSMC_NWE high

FSMC_CLK low to FSMC_AD[15:0] valid

FSMC_CLK low to FSMC_AD[15:0] invalid

FSMC_A/D[15:0] valid after FSMC_CLK low

12

6

t_{su(NWAITV-CLKH)}FSMC_NWAIT valid before FSMC_CLK high

7

2

1

t_{h(CLKH-NWAITV)}

t_d(CLKL-NBLH)

FSMC_NWAIT valid after FSMC_CLK high

FSMC_CLK low to FSMC_NBL high

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

t

d(CLKL-NExL)

d(CLKH-NExH)

Data latency = 1

d(CLKL-NADVH)

FSMC_NEx

t

d(CLKL-NADVL)

FSMC_NADV

t

d(CLKH-AIV)

d(CLKL-AV)

FSMC_A[25:0]

FSMC_NOE

t

d(CLKL-NOEL)

d(CLKH-NOEH)

t

su(DV-CLKH)

h(CLKH-DV)

t

h(CLKH-DV)

su(DV-CLKH)

FSMC_D[15:0]

FSMC_NWAIT

D1

D2

t

su(NWAITV-CLKH)

t

h(CLKH-NWAITV)

(WAITCFG = 1b, WAITPOL + 0b)

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

t

h(CLKH-NWAITV)

su(NWAITV-CLKH)

ai14894d

(1)(2)

Table 37. Synchronous non-multiplexed NOR/PSRAM read timings

Symbol Parameter Min

t_w(CLK)27.7

Max

Unit

FSMC_CLK period

ns

t_d(CLKL-NExL)

t_d(CLKH-NExH)

t_{d(CLKL-NADVL)}

t_{d(CLKL-NADVH)}

t_d(CLKL-AV)

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

1.5

4

T_HCLK+ 2

FSMC_CLK low to FSMC_NADV high

5

FSMC_CLK low to FSMC_Ax valid (x = 0...25)

0

t_d(CLKH-AIV)

FSMC_CLK high to FSMC_Ax invalid (x = 0...25) T_HCLK+ 4

FSMC_CLK low to FSMC_NOE low

t_d(CLKL-NOEL)

t_d(CLKH-NOEH)

t_su(DV-CLKH)

t_h(CLKH-DV)

T_HCLK+ 1.5 ns

FSMC_CLK high to FSMC_NOE high

T_HCLK+ 1.5

ns

FSMC_D[15:0] valid data before FSMC_CLK high 6.5

FSMC_D[15:0] valid data after FSMC_CLK high

7

2

t_{su(NWAITV-CLKH)}FSMC_NWAIT valid before FSMC_SMCLK high

t_{h(CLKH-NWAITV)}FSMC_NWAIT valid after FSMC_CLK high

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 31. Synchronous non-multiplexed PSRAM write timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

t

d(CLKL-NExL)

d(CLKH-NExH)

Data latency = 1

d(CLKL-NADVH)

FSMC_NEx

t

d(CLKL-NADVL)

FSMC_NADV

FSMC_A[25:0]

FSMC_NWE

t

d(CLKH-AIV)

d(CLKL-AV)

t

d(CLKL-NWEL)

t

d(CLKH-NWEH)

t

d(CLKL-Data)

FSMC_D[15:0]

D1

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

FSMC_NBL

t

d(CLKL-NBLH)

su(NWAITV-CLKH)

t

h(CLKH-NWAITV)

ai14993e

(1)(2)

Table 38. Synchronous non-multiplexed PSRAM write timings

Symbol Parameter

t_w(CLK)

Min

27.7

Max Unit

FSMC_CLK period

ns

t_d(CLKL-NExL)

t_d(CLKH-NExH)

t_{d(CLKL-NADVL)}

t_{d(CLKL-NADVH)}

t_d(CLKL-AV)

FSMC_CLK low to FSMC_NEx low (x = 0...2)

FSMC_CLK high to FSMC_NEx high (x = 0...2)

FSMC_CLK low to FSMC_NADV low

2

ns

T_HCLK+ 2

4

0

1

6

FSMC_CLK low to FSMC_NADV high

5

FSMC_CLK low to FSMC_Ax valid (x = 16...25)

FSMC_CLK high to FSMC_Ax invalid (x = 16...25)

FSMC_CLK low to FSMC_NWE low

t_d(CLKH-AIV)

T_CK+ 2

t_d(CLKL-NWEL)

t_d(CLKH-NWEH)

t_d(CLKL-Data)

FSMC_CLK high to FSMC_NWE high

T_HCLK+ 1

FSMC_D[15:0] valid data after FSMC_CLK low

t_{su(NWAITV-CLKH)}FSMC_NWAIT valid before FSMC_CLK high

t_{h(CLKH-NWAITV)}FSMC_NWAIT valid after FSMC_CLK high

7

2

1

t_d(CLKL-NBLH)

1. C_L= 15 pF.

FSMC_CLK low to FSMC_NBL high

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

PC Card/CompactFlash controller waveforms and timings

Figure 32 through Figure 37 represent synchronous waveforms and Table 39 provides the

corresponding timings. The results shown in this table are obtained with the following FSMC

configuration:

●

COM.FSMC_SetupTime = 0x04;

COM.FSMC_WaitSetupTime = 0x07;

COM.FSMC_HoldSetupTime = 0x04;

COM.FSMC_HiZSetupTime = 0x00;

ATT.FSMC_SetupTime = 0x04;

ATT.FSMC_WaitSetupTime = 0x07;

ATT.FSMC_HoldSetupTime = 0x04;

ATT.FSMC_HiZSetupTime = 0x00;

IO.FSMC_SetupTime = 0x04;

IO.FSMC_WaitSetupTime = 0x07;

IO.FSMC_HoldSetupTime = 0x04;

IO.FSMC_HiZSetupTime = 0x00;

TCLRSetupTime = 0;

TARSetupTime = 0;

Figure 32. PC Card/CompactFlash controller waveforms for common memory read

access

FSMC_NCE4_2⁽¹⁾

FSMC_NCE4_1

t

h(NCEx-AI)

t

v(NCEx-A)

FSMC_A[10:0]

t

h(NCEx-NREG)

h(NCEx-NIORD)

t

d(NREG-NCEx)

d(NIORD-NCEx)

h(NCEx-NIOWR

)

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

FSMC_NWE

t

d(NCE4_1-NOE)

w(NOE)

FSMC_NOE

t

h(NOE-D)

su(D-NOE)

FSMC_D[15:0]

ai14895b

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 33. PC Card/CompactFlash controller waveforms for common memory write

access

FSMC_NCE4_1

FSMC_NCE4_2

FSMC_A[10:0]

High

t

h(NCE4_1-AI)

v(NCE4_1-A)

t

h(NCE4_1-NREG)

h(NCE4_1-NIORD)

h(NCE4_1-NIOWR)

t

d(NREG-NCE4_1)

d(NIORD-NCE4_1)

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

t

d(NCE4_1-NWE)

w(NWE)

d(NWE-NCE4_1)

FSMC_NWE

FSMC_NOE

MEMxHIZ =1

t

d(D-NWE)

t

v(NWE-D)

h(NWE-D)

FSMC_D[15:0]

ai14896b

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read

access

FSMC_NCE4_1

t

h(NCE4_1-AI)

v(NCE4_1-A)

FSMC_NCE4_2

FSMC_A[10:0]

High

FSMC_NIOWR

FSMC_NIORD

t

h(NCE4_1-NREG)

d(NREG-NCE4_1)

FSMC_NREG

FSMC_NWE

t

d(NOE-NCE4_1)

d(NCE4_1-NOE)

w(NOE)

FSMC_NOE

t

su(D-NOE)

h(NOE-D)

FSMC_D[15:0]⁽¹⁾

ai14897b

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write

access

FSMC_NCE4_1

High

FSMC_NCE4_2

FSMC_A[10:0]

t

h(NCE4_1-AI)

v(NCE4_1-A)

FSMC_NIOWR

FSMC_NIORD

t

d(NREG-NCE4_1)

h(NCE4_1-NREG)

FSMC_NREG

t

d(NCE4_1-NWE)

w(NWE)

FSMC_NWE

t

d(NWE-NCE4_1)

FSMC_NOE

t

v(NWE-D)

FSMC_D[7:0](1)

ai14898b

1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).

Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access

FSMC_NCE4_1

FSMC_NCE4_2

t

h(NCE4_1-AI)

v(NCEx-A)

FSMC_A[10:0]

FSMC_NREG

FSMC_NWE

FSMC_NOE

FSMC_NIOWR

t

w(NIORD)

t

d(NIORD-NCE4_1)

FSMC_NIORD

t

su(D-NIORD)

d(NIORD-D)

FSMC_D[15:0]

ai14899B

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access

FSMC_NCE4_1

FSMC_NCE4_2

t

h(NCE4_1-AI)

v(NCEx-A)

FSMC_A[10:0]

FSMC_NREG

FSMC_NWE

FSMC_NOE

FSMC_NIORD

t

d(NCE4_1-NIOWR)

w(NIOWR)

FSMC_NIOWR

ATTxHIZ =1

t

v(NIOWR-D)

h(NIOWR-D)

FSMC_D[15:0]

ai14900b

(1)(2)

Table 39. Switching characteristics for PC Card/CF read and write cycles

Symbol

Parameter

Min

Max

Unit

FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y =

0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid

(y = 0...10)

t_v(NCEx-A)

t_{v(NCE4_1-A)}

0

5

ns

FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x =

0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax

invalid (x = 0...10)

t_h(NCEx-AI)

t_{h(NCE4_1-AI)}

2.5

ns

t_d(NREG-NCEx)

FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1

t_{d(NREG-NCE4_1)}low to FSMC_NREG valid

ns

t_h(NCEx-NREG)

FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1

t_{h(NCE4_1-NREG)}high to FSMC_NREG invalid

T_HCLK+ 3

t_{d(NCE4_1-NOE)}

t_w(NOE)

t_{d(NOE-NCE4_1}

t_su(D-NOE)

FSMC_NCE4_1 low to FSMC_NOE low

5T_HCLK+ 2

ns

FSMC_NOE low width

8T_HCLK–1.5 8T_HCLK+ 1

FSMC_NOE high to FSMC_NCE4_1 high

FSMC_D[15:0] valid data before FSMC_NOE high

FSMC_D[15:0] valid data after FSMC_NOE high

FSMC_NWE low width

5T_HCLK+ 2

25

t_h(NOE-D)

15

t_w(NWE)

8T_HCLK– 1 8T_HCLK+ 2

5T_HCLK+ 2

t_{d(NWE-NCE4_1)}

t_{d(NCE4_1-NWE)}

t_v(NWE-D)

FSMC_NWE high to FSMC_NCE4_1 high

FSMC_NCE4_1 low to FSMC_NWE low

FSMC_NWE low to FSMC_D[15:0] valid

FSMC_NWE high to FSMC_D[15:0] invalid

FSMC_D[15:0] valid before FSMC_NWE high

5T_HCLK+ 1.5 ns

0

ns

t_h(NWE-D)

11T_HCLK

t_d(D-NWE)

13T_HCLK

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

(1)(2)

Table 39. Switching characteristics for PC Card/CF read and write cycles

(continued)

Max

Symbol

t_w(NIOWR)

t_v(NIOWR-D)

t_h(NIOWR-D)

Parameter

FSMC_NIOWR low width

Min

Unit

8T_HCLK+ 3

ns

FSMC_NIOWR low to FSMC_D[15:0] valid

FSMC_NIOWR high to FSMC_D[15:0] invalid

5T_HCLK+1

11T_HCLK

t_{d(NCE4_1-NIOWR)}FSMC_NCE4_1 low to FSMC_NIOWR valid

5T_HCLK+3ns ns

ns

t_{h(NCEx-NIOWR)}FSMC_NCEx high to FSMC_NIOWR invalid

5T_HCLK– 5

t_{h(NCE4_1-NIOWR)}FSMC_NCE4_1 high to FSMC_NIOWR invalid

t_{d(NIORD-NCEx)}FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1

5T_HCLK+ 2.5 ns

ns

t_{d(NIORD-NCE4_1)}low to FSMC_NIORD valid

t_{h(NCEx-NIORD)}

FSMC_NCEx high to FSMC_NIORD invalid

5T_HCLK– 5

t_{h(NCE4_1-NIORD)}FSMC_NCE4_1 high to FSMC_NIORD invalid

t_su(D-NIORD)

t_d(NIORD-D)

t_w(NIORD)

FSMC_D[15:0] valid before FSMC_NIORD high

FSMC_D[15:0] valid after FSMC_NIORD high

FSMC_NIORD low width

4.5

ns

9

8T_HCLK+ 2

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

NAND controller waveforms and timings

Figure 38 through Figure 41 represent synchronous waveforms and Table 40 provides the

corresponding timings. The results shown in this table are obtained with the following FSMC

configuration:

●

COM.FSMC_SetupTime = 0x01;

COM.FSMC_WaitSetupTime = 0x03;

COM.FSMC_HoldSetupTime = 0x02;

COM.FSMC_HiZSetupTime = 0x01;

ATT.FSMC_SetupTime = 0x01;

ATT.FSMC_WaitSetupTime = 0x03;

ATT.FSMC_HoldSetupTime = 0x02;

ATT.FSMC_HiZSetupTime = 0x01;

Bank = FSMC_Bank_NAND;

MemoryDataWidth = FSMC_MemoryDataWidth_16b;

ECC = FSMC_ECC_Enable;

ECCPageSize = FSMC_ECCPageSize_512Bytes;

TCLRSetupTime = 0;

TARSetupTime = 0;

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 38. NAND controller waveforms for read access

FSMC_NCEx

Low

ALE (FSMC_A17)

CLE (FSMC_A16)

FSMC_NWE

t_d(ALE-NOE)

t_h(NOE-ALE)

FSMC_NOE (NRE)

FSMC_D[15:0]

t

h(NOE-D)

su(D-NOE)

ai14901b

Figure 39. NAND controller waveforms for write access

FSMC_NCEx

Low

ALE (FSMC_A17)

CLE (FSMC_A16)

t_d(ALE-NWE)

t_h(NWE-ALE)

FSMC_NWE

FSMC_NOE (NRE)

FSMC_D[15:0]

t_v(NWE-D)

t_h(NWE-D)

ai14902b

Figure 40. NAND controller waveforms for common memory read access

FSMC_NCEx

Low

ALE (FSMC_A17)

CLE (FSMC_A16)

t_d(ALE-NOE)

t_h(NOE-ALE)

FSMC_NWE

FSMC_NOE

t_w(NOE)

t_su(D-NOE)

t_h(NOE-D)

FSMC_D[15:0]

ai14912b

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 41. NAND controller waveforms for common memory write access

FSMC_NCEx

Low

ALE (FSMC_A17)

CLE (FSMC_A16)

t_d(ALE-NOE)

t_w(NWE)

t_h(NOE-ALE)

FSMC_NWE

FSMC_NOE

t_d(D-NWE)

t_v(NWE-D)

t_h(NWE-D)

FSMC_D[15:0]

ai14913b

(1)

Table 40. Switching characteristics for NAND Flash read and write cycles

Symbol

Parameter

Min

Max

Unit

(2)

t_d(D-NWE)

FSMC_D[15:0] valid before FSMC_NWE high

FSMC_NOE low width

6T_HCLK+ 12

ns

(2)

t_w(NOE)

4T_HCLK– 1.5 4T_HCLK+ 1.5 ns

FSMC_D[15:0] valid data before FSMC_NOE

high

(2)

t_su(D-NOE)

25

ns

t_h(NOE-D)

FSMC_D[15:0] valid data after FSMC_NOE high 7

ns

(2)

t_w(NWE)

FSMC_NWE low width

4T_HCLK– 1

4T_HCLK+ 2.5 ns

(2)

t_v(NWE-D)

FSMC_NWE low to FSMC_D[15:0] valid

FSMC_NWE high to FSMC_D[15:0] invalid

FSMC_ALE valid before FSMC_NWE low

FSMC_NWE high to FSMC_ALE invalid

FSMC_ALE valid before FSMC_NOE low

FSMC_NWE high to FSMC_ALE invalid

0

ns

(2)

t_h(NWE-D)

t_d(ALE-NWE)

t_h(NWE-ALE)

10T_HCLK+ 4

3T_HCLK+ 4.5

(3)

3T_HCLK+ 1.5 ns

ns

(3)

t_d(ALE-NOE)

t_h(NOE-ALE)

3T_HCLK+ 2

ns

(3)

1. C_L= 15 pF.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.11

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the

device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

●

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

●

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 41. They are based on the EMS levels and classes

defined in application note AN1709.

Table 41. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD3.3 V, LQFP144, T_A+25 °C,

f_HCLK72 MHz

conforms to IEC 61000-4-2

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

V_FESD

2B

4A

Fast transient voltage burst limits to be

applied through 100 pF on V_DDand V_SS

pins to induce a functional disturbance

V_DD3.3 V, LQFP144, T_A+25 °C,

f_HCLK72 MHz

conforms to IEC 61000-4-4

V_EFTB

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

●

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

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STM32F103xC, STM32F103xD, STM32F103xE

Prequalification trials

Electrical characteristics

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 42. EMI characteristics

Max vs. [f_HSE/f_HCLK

]

Monitored

Symbol Parameter

Conditions

Unit

frequency band

8/48 MHz 8/72 MHz

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

8

31

28

4

12

21

33

4

V_DD3.3 V, T_A25 °C,

LQFP144 package

compliant with IEC

61967-2

dBµV

-

S_EMI

Peak level

5.3.12

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 43. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class Maximum value⁽¹⁾Unit

Electrostatic discharge

T_A+25 °C, conforming

V

2

2000

500

^ESD(HBM)voltage (human body model) to JESD22-A114

V

Electrostatic discharge

T_A+25 °C, conforming

V

II

^ESD(CDM)voltage (charge device model) to JESD22-C101

1. Based on characterization results, not tested in production.

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Electrical characteristics

Static latch-up

STM32F103xC, STM32F103xD, STM32F103xE

Two complementary static tests are required on six parts to assess the latch-up

performance:

●

A supply overvoltage is applied to each power supply pin

A current injection is applied to each input, output and configurable I/O pin

●

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 44. Electrical sensitivities

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T_A+105 °C conforming to JESD78A

II level A

5.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 45 are derived from tests

performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL

compliant.

Table 45. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL

Input low level voltage

–0.5

0.8

V

Standard IO input high level voltage

IO FT⁽¹⁾input high level voltage

Input low level voltage

TTL ports

2

V_DD+0.5

5.5V

V_IH

V_IL

V_IH

–0.5

0.35 V_DD

V_DD+0.5

CMOS ports

V

Input high level voltage

0.65 V_DD

Standard IO Schmitt trigger voltage

hysteresis⁽²⁾

200

mV

V_hys

IO FT Schmitt trigger voltage

hysteresis⁽²⁾

(3)

5% V_DD

V_SS V_IN V_DD

Standard I/Os

1

I_lkg

Input leakage current ⁽⁴⁾

µA

V_IN= 5 V, I/O FT

V_INV_SS

3

R_PU

R_PD

C_IO

Weak pull-up equivalent resistor⁽⁵⁾

Weak pull-down equivalent resistor⁽⁵⁾

I/O pin capacitance

30

40

5

50

k

pF

V_INV_DD

1. FT = Five-volt tolerant.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

All I/Os are CMOS and TTL compliant (no software configuration required), their

characteristics consider the most strict CMOS-technology or TTL parameters:

●

For V :

IH

–

if V is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included

DD

if V is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included

DD

●

For V :

IL

–

if V is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included

DD

if V is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included

DD

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink

+20 mA (with a relaxed V ).

OL

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 5.2:

●

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

I

(see Table 8).

VDD

●

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

I

(see Table 8).

VSS

Output voltage levels

Unless otherwise specified, the parameters given in Table 46 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 10. All I/Os are CMOS and TTL compliant.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 46. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)

V_OL

0.4

TTL port

I_IO= +8 mA

V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(2)

2.7 V < V_DD< 3.6 V

V_OH

V_DD–0.4

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)

V_OL

0.4

1.3

0.4

CMOS port

I_IO=+ 8mA

V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(2)

2.7 V < V_DD< 3.6 V

V_OH

2.4

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)(3)

V_OL

I_IO= +20 mA

2.7 V < V_DD< 3.6 V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(2)(3)

V_OH

V_DD–1.3

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(1)(3)

V_OL

I_IO= +6 mA

2 V < V_DD< 2.7 V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(2)(3)

V_OH

V_DD–0.4

1. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 8

and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in

Table 8 and the sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

3. Based on characterization data, not tested in production.

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STM32F103xC, STM32F103xD, STM32F103xE

Input/output AC characteristics

Electrical characteristics

The definition and values of input/output AC characteristics are given in Figure 42 and

Table 47, respectively.

Unless otherwise specified, the parameters given in Table 47 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 10.

(1)

Table 47. I/O AC characteristics

MODEx[1:0]

Symbol

Parameter

Conditions

Min Max Unit

bit value⁽¹⁾

f_max(IO)outMaximum frequency⁽²⁾C_L= 50 pF, V_DD= 2 V to 3.6 V

2

MHz

ns

Output high to low

t_f(IO)out

125⁽³⁾

10

level fall time

C_L= 50 pF, V_DD= 2 V to 3.6 V

Output low to high

t_r(IO)out

125⁽³⁾

10

level rise time

f_max(IO)outMaximum frequency⁽²⁾C_L= 50 pF, V_DD= 2 V to 3.6 V

MHz

ns

Output high to low

t_f(IO)out

25⁽³⁾

01

level fall time

C_L= 50 pF, V_DD= 2 V to 3.6 V

Output low to high

t_r(IO)out

25⁽³⁾

level rise time

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

F_max(IO)outMaximum frequency⁽²⁾C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

50

30

MHz

20

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

Output high to low

level fall time

5⁽³⁾

8⁽³⁾

12⁽³⁾

5⁽³⁾

8⁽³⁾

12⁽³⁾

11

t_f(IO)out

t_r(IO)out

t_EXTIpw

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 2 V to 2.7 V

ns

Output low to high

level rise time

Pulse width of

external signals

detected by the EXTI

controller

-

10

ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a

description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 42.

3. Guaranteed by design, not tested in production.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 42. I/O AC characteristics definition

90%

10 %

50%

90%

10%

t

EXTERNAL

OUTPUT

ON 50pF

t

r(IO)out

T

Maximum frequency is achieved if (t + t ) 2/3)T and if the duty cycle is (45-55%)

r

f

when loaded by 50pF

ai14131

5.3.14

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, R (see Table 45).

PU

Unless otherwise specified, the parameters given in Table 48 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 10.

Table 48. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

(1)

V_IL(NRST)

NRST Input low level voltage

NRST Input high level voltage

–0.5

2

0.8

V

(1)

V_IH(NRST)

V_hys(NRST)

R_PU

V_DD+0.5

NRST Schmitt trigger voltage

hysteresis

200

40

mV

Weak pull-up equivalent resistor⁽²⁾

V_INV_SS

30

50

k

ns

(1)

V_F(NRST)

NRST Input filtered pulse

100

(1)

V_NF(NRST)

NRST Input not filtered pulse

300

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

to the series resistance must be minimum (~10% order).

Figure 43. Recommended NRST pin protection

V

DD

External

reset circuit⁽¹⁾

R

PU

(2)

Internal Reset

NRST

Filter

0.1 µF

STM32F10xxx

ai14132c

2. The reset network protects the device against parasitic resets.

3. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 48. Otherwise the reset will not be taken into account by the device.

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.3.15

TIM timer characteristics

The parameters given in Table 49 are guaranteed by design.

Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

(1)

Table 49. TIMx characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

t_TIMxCLK

ns

1

t_res(TIM)

Timer resolution time

f_TIMxCLK= 72 MHz 13.9

0

f_TIMxCLK/2

36

MHz

Timer external clock

frequency on CH1 to CH4

f_EXT

f_TIMxCLK= 72 MHz

0

MHz

Res_TIM

Timer resolution

16

bit

16-bit counter clock period

when internal clock is

selected

t_TIMxCLK

1

65536

t_COUNTER

f_TIMxCLK= 72 MHz 0.0139

910

µs

t_TIMxCLK

s

65536 × 65536

59.6

t_{MAX_COUNT}

Maximum possible count

f_TIMxCLK= 72 MHz

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.16

Communications interfaces

I²C interface characteristics

Unless otherwise specified, the parameters given in Table 50 are derived from tests

performed under ambient temperature, f

frequency and V supply voltage conditions

PCLK1

DD

summarized in Table 10.

2

I

The STM32F103xC, STM32F103xD and STM32F103xE performance line C interface

2

meets the requirements of the standard I C communication protocol with the following

restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When

configured as open-drain, the PMOS connected between the I/O pin and V is disabled,

DD

but is still present.

2

The I C characteristics are described in Table 50. Refer also to Section 5.3.13: I/O port

for more details on the input/output alternate function characteristics (SDA

characteristics

and SCL)

.

2

Table 50. I C characteristics

Standard mode I²C⁽¹⁾

Fast mode I²C⁽¹⁾⁽²⁾

Symbol

Parameter

Unit

Min

Max

Min

Max

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

SCL clock high time

SDA setup time

4.7

4.0

1.3

0.6

µs

250

0⁽³⁾

100

0⁽⁴⁾

SDA data hold time

900⁽³⁾

300

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

1000

300

20 + 0.1C_b

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

Start condition hold time

300

t_h(STA)

t_su(STA)

4.0

4.7

4.0

4.7

0.6

1.3

µs

Repeated Start condition

setup time

t_su(STO)

Stop condition setup time

s

Stop to Start condition time

(bus free)

t_w(STO:STA)

Capacitive load for each bus

line

C_b

400

pF

Guaranteed by design, not tested in production.

1.

2. f_PCLK1must be higher than 2 MHz to achieve the maximum standard mode I²C frequency. It must be

higher than 4 MHz to achieve the maximum fast mode I²C frequency.

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

period of SCL signal.

3.

4.

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

88/123

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

2

Figure 44. I C bus AC waveforms and measurement circuit

V

DD

STM32F103xx

SDA

4.7kΩ

100Ω

2

I C bus

SCL

START REPEATED

START

t

su(STA)

SDA

t

r(SDA)

f(SDA)

su(SDA)

t

su(STA:STO)

STOP

t

w(SCKL)

h(SDA)

h(STA)

SCL

t

su(STO)

r(SCK)

t

f(SCK)

w(SCKH)

ai14149b

Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

1.

(1)(2)

Table 51. SCL frequency (f

f_SCL(kHz)

= 36 MHz.,V_DD= 3.3 V)

PCLK1

I2C_CCR value

R_P= 4.7 k

400

300

200

100

50

0x801E

0x8028

0x803C

0x00B4

0x0168

0x0384

20

1. R_P= External pull-up resistance, f_SCL= I²C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the

tolerance on the achieved speed 2%. These variations depend on the accuracy of the external

components used to design the application.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

I²S - SPI characteristics

2

Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I S

are derived from tests performed under ambient temperature, f

frequency and V

PCLKx

DD

supply voltage conditions summarized in Table 10.

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate

2

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).

(1)

Table 52. SPI characteristics

Symbol

Parameter

Conditions

Master mode

Min

Max

Unit

18

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

Slave mode

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

8

ns

%

SPI slave input clock duty

cycle

DuCy(SCK)

Slave mode

30

70

(2)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

4t_PCLK

2t_PCLK

(2)

t_h(NSS)

(2)

t_w(SCKH)

t_w(SCKL)

Master mode, f_PCLK= 36 MHz,

presc = 4

SCK high and low time

Data input setup time

50

60

(2)

Master mode

Slave mode

Master mode

Slave mode

5

4

0

2

t_su(MI)

t_su(SI)

(2)

t_h(MI)

Data input hold time

ns

(2)

t_h(SI)

(2)(3)

t_a(SO)

Data output access time Slave mode, f_PCLK= 20 MHz

Data output disable time Slave mode

3t_PCLK

10

(2)(4)

t_dis(SO)

(2)(1)

t_v(SO)

Data output valid time

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

25

(2)(1)

t_v(MO)

5

(2)

t_h(SO)

15

2

Data output hold time

(2)

t_h(MO)

1. Remapped SPI1 characteristics to be determined.

2. Based on characterization, not tested in production.

3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z

90/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Figure 45. SPI timing diagram - slave mode and CPHA = 0

NSS input

Electrical characteristics

t

c(SCK)

t

h(NSS)

SU(NSS)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

r(SCK)

f(SCK)

v(SO)

a(SO)

h(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134c

(1)

Figure 46. SPI timing diagram - slave mode and CPHA = 1

NSS input

t

SU(NSS)

t

c(SCK)

h(NSS)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)

Figure 47. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

INPUT

MSBIN

t

BIT6 IN

LSB IN

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTPUT

t

v(MO)

h(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

92/123

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

2

Table 53. I S characteristics

Symbol

Parameter

Conditions

Slave mode

Min

Max

Unit

I2S slave input clock duty

cycle

DuCy(SCK)

30

70

%

Master mode (data: 16 bits,

Audio frequency = 48 kHz)

1.522

0

1.525

6.5

8

f_CK

1/t_c(CK)

I²S clock frequency

MHz

ns

Slave mode

t_r(CK)

t_f(CK)

I²S clock rise and fall time

WS valid time

Capacitive load C_L= 50 pF

Master mode

(1)

t_v(WS)

3

2

I2S2

I2S3

(1)

t_h(WS)

WS hold time

Master mode

0

(1)

t_su(WS)

WS setup time

WS hold time

Slave mode

4

(1)

t_h(WS)

0

(1)

t_w(CKH)

312.5

345

2

Master f_PCLK= 16 MHz, audio

frequency = 48 kHz

CK high and low time

(1)

t_w(CKL)

I2S2

Master receiver

I2S3

(1)

t_{su(SD_MR)}

Data input setup time

Data input hold time

6.5

1.5

0

(1)

t_{su(SD_SR)}

Slave receiver

Master receiver

Slave receiver

(1)(2)

t_{h(SD_MR)}

t_{h(SD_SR)}

(1)(2)

0.5

Slave transmitter (after enable

edge)

(1)(2)

t_{v(SD_ST)}

t_{h(SD_ST)}

t_{v(SD_MT)}

t_{h(SD_MT)}

Data output valid time

Data output hold time

Data output valid time

Data output hold time

18

3

Slave transmitter (after enable

edge)

(1)

11

0

Master transmitter (after enable

edge)

(1)(2)

(1)

Master transmitter (after enable

edge)

1. Based on design simulation and/or characterization results, not tested in production.

2. Depends on f_PCLK. For example, if f_PCLK=8 MHz, then T_PCLK= 1/f_PLCLK=125 ns.

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

2

(1)

Figure 48. I S slave timing diagram (Philips protocol)

t

c(CK)

CPOL = 0

CPOL = 1

WS input

t

w(CKL)

h(WS)

w(CKH)

t

v(SD_ST)

h(SD_ST)

su(WS)

SD

transmit

(2)

LSB transmit

MSB transmit

MSB receive

Bitn transmit

LSB transmit

t

su(SD_SR)

h(SD_SR)

(2)

LSB receive

Bitn receive

LSB receive

SD

receive

ai14881b

1. Measurement points are done at CMOS levels: 0.3 × V_DDand 0.7 × V_DD

.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

2

(1)

Figure 49. I S master timing diagram (Philips protocol)

t

r(CK)

f(CK)

t

c(CK)

CPOL = 0

CPOL = 1

WS output

t

w(CKH)

t

h(WS)

t

v(WS)

w(CKL)

t

v(SD_MT)

h(SD_MT)

(2)

SD

transmit

LSB transmit

MSB transmit

MSB receive

Bitn transmit

LSB transmit

t

h(SD_MR)

su(SD_MR)

(2)

SD

LSB receive

Bitn receive

LSB receive

receive

ai14884b

1. Based on characterization, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

94/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 54 are derived from tests

performed under ambient temperature, f

frequency and V supply voltage conditions

PCLKx

DD

summarized in Table 10.

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate

function characteristics (D[7:0], CMD, CK).

Figure 50. SDIO high-speed mode

t

r

f

t

C

t

W(CKH)

W(CKL)

CK

t

OV

OH

D, CMD

(output)

t

ISU

IH

D, CMD

(input)

ai14887

Figure 51. SD default mode

CK

t

OVD

OHD

D, CMD

(output)

ai14888

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 54. SD / MMC characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Clock frequency in data transfer

mode

f_PP

C_L 30 pF

0

48

MHz

t_W(CKL)

Clock low time, f_PP= 16 MHz

Clock high time, f_PP= 16 MHz

Clock rise time

C_L 30 pF

32

31

t_W(CKH)

ns

t_r

t_f

3.5

5

Clock fall time

CMD, D inputs (referenced to CK)

t_ISU

t_IH

Input setup time

Input hold time

C_L 30 pF

2

0

ns

CMD, D outputs (referenced to CK) in MMC and SD HS mode

t_OV

t_OH

Output valid time

Output hold time

C_L 30 pF

6

7

0.3

0.5

CMD, D outputs (referenced to CK) in SD default mode⁽¹⁾

t_OVD

t_OHD

Output valid default time

Output hold default time

C_L 30 pF

ns

1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.

USB characteristics

The USB interface is USB-IF certified (Full Speed).

Table 55. USB startup time

Symbol

Parameter

Max

Unit

µs

(1)

t_STARTUP

USB transceiver startup time

1

1. Guaranteed by design, not tested in production.

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Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 56. USB DC electrical characteristics

Symbol Parameter

Conditions

Min.⁽¹⁾

Max.⁽¹⁾Unit

Input levels

V_DD

USB operating voltage⁽²⁾

Differential input sensitivity

3.0⁽³⁾

0.2

3.6

V

(4)

V_DI

I(USBDP, USBDM)

(4)

V_CM

Differential common mode range Includes V_DIrange

Single ended receiver threshold

0.8

2.5

2.0

(4)

V_SE

Output levels

1.3

V_OL

V_OH

Static output level low

Static output level high

R_Lof 1.5 k to 3.6 V⁽⁵⁾

0.3

3.6

V

(5)

R_Lof 15 k to V_SS

2.8

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled

up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range.

3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical

characteristics which are degraded in the 2.7-to-3.0 V V_DDvoltage range.

4. Guaranteed by characterization, not tested in production.

R_Lis the load connected on the USB drivers

5.

Figure 52. USB timings: definition of data signal rise and fall time

Crossover

points

Differential

Data Lines

V

CR S

V

SS

t

r

f

ai14137

Table 57.

Symbol

USB: full-speed electrical characteristics

Driver characteristics⁽¹⁾

Parameter

Conditions

Min

Max

Unit

t_r

t_f

Rise time⁽²⁾

Fall Time⁽²⁾

C_L= 50 pF

t_r/t_f

4

20

ns

%

V

t_rfm

V_CRS

Rise/ fall time matching

90

1.3

110

2.0

Output signal crossover voltage

1. Guaranteed by design, not tested in production.

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

2.

5.3.17

CAN (controller area network) interface

Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate

function characteristics (CAN_TX and CAN_RX).

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

5.3.18

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 58 are derived from tests

performed under ambient temperature, f

frequency and V

supply voltage

PCLK2

DDA

conditions summarized in Table 10.

Note:

It is recommended to perform a calibration after each power-up.

Table 58. ADC characteristics

Symbol

Parameter

Power supply

Conditions

Min

Typ

Max

Unit

V_DDA

2.4

3.6

V

V_REF+

Positive reference voltage

V_DDA

Current on the V_REFinput

I_VREF

f_ADC

160⁽¹⁾220⁽¹⁾

µA

ADC clock frequency

Sampling rate

0.6

14

1

MHz

(2)

0.05

f_S

f

_ADC= 14 MHz

823

17

kHz

(2)

External trigger frequency

Conversion voltage range⁽³⁾

f_TRIG

1/f_ADC

0 (V_SSAor V_REF-

tied to ground)

V_AIN

V_REF+

V

See Equation 1 and

Table 59 for details

(2)

R_AIN

External input impedance

Sampling switch resistance

50

1

k

pF

(2)

R_ADC

Internal sample and hold

capacitor

(2)

8

C_ADC

f_ADC= 14 MHz

5.9

83

µs

1/f_ADC

µs

(2)

Calibration time

t_CAL

0.214

3⁽⁴⁾

Injection trigger conversion

latency

(2)

t_lat

1/f_ADC

µs

0.143

2⁽⁴⁾

Regular trigger conversion

latency

(2)

t_latr

1/f_ADC

µs

0.107

1.5

0

17.1

239.5

(2)

Sampling time

Power-up time

t_S

1/f_ADC

µs

(2)

t_STAB

0

1

f_ADC= 14 MHz

1

18

µs

Total conversion time

(including sampling time)

(2)

t_CONV

14 to 252 (t_Sfor sampling +12.5 for

successive approximation)

1/f_ADC

1. Based on characterization results, not tested in production.

2. Guaranteed by design, not tested in production.

3. V_REF+can be internally connected to V_DDAand V_REF-can be internally connected to V_SSA, depending on the package.

Refer to Section 3: Pinouts and pin descriptions for further details.

4. For external triggers, a delay of 1/f_PCLK2must be added to the latency specified in Table 58.

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STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Equation 1: R

max formula

AIN

T_S

R_AIN ------------------------------------------------------------- – R_ADC

f_ADC C_ADC ln2^{N + 2}

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an

error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

(1)

Table 59.

R

max for f

= 14 MHz

AIN

ADC

T_s(cycles)

t_S(µs)

R_AINmax (k)

1.5

0.11

0.4

7.5

0.54

0.96

2.04

2.96

3.96

5.11

17.1

5.9

13.5

28.5

41.5

55.5

71.5

239.5

11.4

25.2

37.2

50

NA

1. Guaranteed by design, not tested in production.

(1)(2)

Table 60. ADC accuracy - limited test conditions

Symbol

Parameter

Test conditions

Typ

Max⁽³⁾

Unit

ET

EO

EG

ED

Total unadjusted error

Offset error

f

_PCLK2= 56 MHz,

1.3

1

2

1.5

1

f_ADC= 14 MHz, R_AIN< 10 k,

V_DDA= 3 V to 3.6 V

T_A= 25 °C

Gain error

0.5

0.7

LSB

Measurements made after

ADC calibration

V_REF+= V_DDA

Differential linearity error

EL

Integral linearity error

0.8

1.5

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to

standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and I_INJ(PIN)in Section 5.3.13 does not

affect the ADC accuracy.

3. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

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Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1) (2)(3)

Table 61. ADC accuracy

Symbol

Parameter

Test conditions

Typ

Max⁽⁴⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

2

5

2.5

3

f_PCLK2= 56 MHz,

f_ADC= 14 MHz, R_AIN< 10 k,

V_DDA= 2.4 V to 3.6 V

1.5

1

Gain error

LSB

Measurements made after

ADC calibration

Differential linearity error

Integral linearity error

2

1.5

3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V_DD, frequency, V_REFand temperature ranges.

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-

robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to

standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and I_INJ(PIN)in Section 5.3.13 does not

affect the ADC accuracy.

4. Based on characterization, not tested in production.

Figure 53. ADC accuracy characteristics

V

DDA

REF+

[1LSB

=

(or

depending on package)]

IDEAL

4096

E_G

(1) Example of an actual transfer curve

(2) The ideal transfer curve

4095

4094

4093

(3) End point correlation line

(2)

E_T=Total Unadjusted Error: maximum deviation

E_T

between the actual and the ideal transfer curves.

(3)

7

6

5

4

3

2

1

E_O=Offset Error: deviation between the first actual

transition and the first ideal one.

(1)

E_G=Gain Error: deviation between the last ideal

transition and the last actual one.

E_O

E_L

E_D=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

E_L=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

E_D

1 LSB_IDEAL

0

1

2

3

4

5

6

7

4093 4094 4095 4096

V_DDA

V_SSA

ai14395b

100/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Figure 54. Typical connection diagram using the ADC

Electrical characteristics

V

DD

STM32F103xx

Sample and hold ADC

V

0.6 V

T

converter

(1)

AIN

R

ADC

AINx

12-bit

converter

I

1 µA

L

C

V

T

parasitic

V

AIN

0.6 V

(1)

C

ADC

ai14150c

1. Refer to Table 58 for the values of R_AIN, R_ADCand C_ADC

.

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high C_parasiticvalue will downgrade conversion accuracy. To remedy

this, f_ADCshould be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 55 or Figure 56,

depending on whether V

is connected to V

or not. The 10 nF capacitors should be

REF+

DDA

ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 55. Power supply and reference decoupling (V not connected to V

)

DDA

REF+

STM32F103xx

V

REF+

(see note 1)

1 µF // 10 nF

V

DDA

SSA

1 µF // 10 nF

V

/V

REF–

(see note 1)

ai14388b

1. V_REF+and V_REF–inputs are available only on 100-pin packages.

Doc ID 14611 Rev 7

101/123

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 56. Power supply and reference decoupling (V

connected to V

)

DDA

REF+

STM32F103xx

V

/V

REF+ DDA

(See note 1)

1 µF // 10 nF

V

/V

REF– SSA

(See note 1)

ai14389

1. V_REF+and V_REF–inputs are available only on 100-pin packages.

102/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.3.19

DAC electrical specifications

Table 62. DAC characteristics

Symbol

Parameter

Min

2.4

Typ

Max

Unit

Comments

V_DDA

Analog supply voltage

3.6

V

V_REF+

V_SSA

Reference supply voltage

Ground

2.4

0

3.6

0

V

V_REF+must always be below V_DDA

V

(1)

R_LOAD

Resistive load with buffer ON 5

k

When the buffer is OFF, the Minimum

resistive load between DAC_OUT

and V_SSto have a 1% accuracy is

1.5 M

Impedance output with buffer

OFF

(1)

R_O

15

50

k

Maximum capacitive load at

DAC_OUT pin (when the buffer is

ON).

(1)

C_LOAD

Capacitive load

pF

V

It gives the maximum output

excursion of the DAC.

DAC_OUT Lower DAC_OUT voltage

min⁽¹⁾

with buffer ON

0.2

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V_REF+= 3.6 V

DAC_OUT Higher DAC_OUT voltage

max⁽¹⁾

with buffer ON

and (0x155) and (0xEAB) at V_REF+

2.4 V

=

V_DDA– 0.2

V

DAC_OUT Lower DAC_OUT voltage

min⁽¹⁾

with buffer OFF

0.5

mV

It gives the maximum output

excursion of the DAC.

DAC_OUT Higher DAC_OUT voltage

V_REF+– 1LSB V

max⁽¹⁾

with buffer OFF

DAC DC current

With no load, worst code (0xF1C) at

I_DDVREF+

consumption in quiescent

mode (Standby mode)

220

380

480

µA V_REF+= 3.6 V in terms of DC

consumption on the inputs

With no load, middle code (0x800) on

the inputs

µA

DAC DC current

consumption in quiescent

mode (Standby mode)

I_DDA

With no load, worst code (0xF1C) at

µA V_REF+= 3.6 V in terms of DC

consumption on the inputs

Given for the DAC in 10-bit

configuration

0.5

LSB

Differential non linearity

Difference between two

consecutive code-1LSB)

DNL⁽²⁾

Given for the DAC in 12-bit

configuration

2

1

LSB

Integral non linearity

(difference between

Given for the DAC in 10-bit

configuration

LSB

measured value at Code i

and the value at Code i on a

line drawn between Code 0

and last Code 1023)

INL⁽²⁾

Given for the DAC in 12-bit

configuration

4

LSB

Doc ID 14611 Rev 7

103/123

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Table 62. DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

Given for the DAC in 12-bit

configuration

10

3

mV

Offset error

(difference between

measured value at Code

(0x800) and the ideal value =

V_REF+/2)

Given for the DAC in 10-bit at V_REF+

= 3.6 V

Offset⁽²⁾

LSB

%

Given for the DAC in 12-bit at V_REF+

= 3.6 V

12

0.5

Gain

Given for the DAC in 12bit

configuration

Gain error

error⁽²⁾

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value 1LSB

(2)

t_SETTLING

3

4

1

µs

C_LOAD 50 pF, R_LOAD 5 k

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

Update

rate⁽²⁾

MS/s C_LOAD 50 pF, R_LOAD 5 k

C_LOAD 50 pF, R_LOAD 5 k

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

(2)

t_WAKEUP

6.5

10

µs

input code between lowest and

highest possible ones.

Power supply rejection ratio

PSRR+ ⁽¹⁾(to V_DDA) (static DC

measurement

–67

–40

dB No R_LOAD, C_LOAD= 50 pF

1. Guaranteed by design, not tested in production.

2. Guaranteed by characterization, not tested in production.

Figure 57. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

R

LOAD

DACx_OUT

12-bit

digital to

analog

converter

C

LOAD

ai17157

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

104/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

5.3.20

Temperature sensor characteristics

Table 63. TS characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(1)

T_L

V_SENSElinearity with temperature

1

4.3

2

4.6

1.52

10

°C

mV/°C

V

Avg_Slope⁽¹⁾Average slope

4.0

1.34

4

(1)

V₂₅

Voltage at 25 °C

Startup time

1.43

(2)

t_START

µs

ADC sampling time when reading the

temperature

(3)(2)

T_{S_temp}

17.1

µs

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

Doc ID 14611 Rev 7

105/123

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

6

Package characteristics

6.1

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA)

Dpad

0.37 mm

0.52 mm typ. (depends on solder mask

registration tolerance

Dsm

Solder paste

0.37 mm aperture diameter

– Non solder mask defined pads are recommended

– 4 to 6 mils screen print

Dpad

Dsm

ai15469

106/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

Figure 59. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package outline

Seating plane

C

A2

A4

ddd

C

A

A3

A1

B

D

D1

A

e

F

M

F

E1

E

e

Øb (144 balls)

Ball A1

C

A

B

M

Øeee

Ø fff

M

C

X3_ME

1. Drawing is not to scale.

Table 64. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Typ

Min

Max

A

A1

A2

A3

A4

b

1.70

0.0669

0.21

0.0083

1.07

0.27

0.0421

0.0106

0.85

0.45

0.0335

0.0177

0.3996

0.35

9.85

0.40

10.00

8.80

10.00

8.80

0.80

0.60

0.10

0.15

0.08

0.0138

0.3878

0.0157

0.3937

0.3465

0.3937

0.3465

0.0315

0.0236

0.0039

0.0059

0.0031

D

10.15

D1

E

9.85

10.15

0.3878

0.3996

E1

e

F

ddd

eee

fff

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 14611 Rev 7

107/123

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 60. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

outline

1. Drawing is not to scale.

Table 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

1.700

0.0669

A1

A2

A3

A4

b

0.270

0.0106

1.085

0.30

0.0427

0.0118

0.80

0.55

0.0315

0.0217

0.3996

0.45

9.85

0.50

10.00

7.20

10.00

7.20

0.80

1.40

0.12

0.15

0.08

0.0177

0.3878

0.0197

0.3937

0.2835

0.3937

0.2835

0.0315

0.0551

D

10.15

D1

E

9.85

10.15

0.3878

0.3996

E1

e

F

ddd

eee

fff

0.0047

0.0059

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

108/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

Figure 61. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale

package outline

e1

A1 ball corner

e

A1 ball corner

e

D

A

B

C

H

Detail A

D

E

e1

E

F

Notch

G

H

F

L

aaa

Marking area

A2

L

G

2

8

7

6

5

4

3

1

Wafer back side

A

Ball side

Side view

Ball

eee

A1

b

Seating plane (see note 2)

Detail A rotated 90 ˚

CR_ME

1. Drawing is not to scale.

2. Primary datum Z and seating plane are defined by the spherical crowns of the ball.

Table 66. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale

package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

0.535

Max

0.635

Min

Typ

Max

A

0.585

0.230

0.355

0.320

0.500

3.500

0.447

0.483

4.466

4.395

0.250

0.200

0.05

0.0211

0.0081

0.0130

0.0114

0.0230

0.0091

0.0140

0.0126

0.0197

0.1378

0.0176

0.0190

0.1758

0.1730

0.0098

0.0079

0.0020

0.0039

0.0250

0.0100

0.0150

0.0138

A1

A2

b⁽²⁾

e

0.205

0.330

0.290

0.255

0.380

0.350

e1

F

G

D

4.446

4.375

4.486

4.415

0.1750

0.1722

0.1766

0.1738

E

H

L

eee

aaa

0.10

Number of balls

64

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Dimension is measured at the maximum ball diameter parallel to primary datum Z.

Doc ID 14611 Rev 7

109/123

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 62. Recommended PCB design rules (0.5 mm pitch BGA)

Dpad

0.37 mm

0.52 mm typ. (depends on solder mask

registration tolerance

Dsm

Solder paste

0.37 mm aperture diameter

– Non solder mask defined pads are recommended

– 4 to 6 mils screen print

Dpad

Dsm

ai15469

110/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

Figure 63. LQFP144, 20 x 20 mm, 144-pin low-profile quad

Figure 64. Recommended

(1)

(1)(2)

flat package outline

footprint

Seating plane

C

A

A2 A1

c

b

1.35

73

0.25 mm

108

gage plane

ccc

C

109

72

0.35

D

k

D1

0.5

A1

D3

L

108

73

17.85

22.6

L1

19.9

72

109

144

37

E1

E

1

36

19.9

22.6

E3

ai149

144

37

Pin 1

identification

1

36

e

ME_1A

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

0.063

A

A1

A2

b

1.60

0.15

0.05

1.35

0.002

0.0531

0.0067

0.0035

0.8583

0.7795

0.0059

0.0571

0.0106

0.0079

0.874

1.40

0.22

1.45

0.0551

0.0087

0.17

0.27

c

0.09

0.20

D

21.80

19.80

22.00

20.00

17.50

22.00

20.00

17.50

0.50

22.20

20.20

0.8661

0.7874

0.689

D1

D3

E

0.7953

21.80

19.80

22.20

20.20

0.8583

0.7795

0.8661

0.7874

0.689

0.874

E1

E3

e

0.7953

0.0197

0.0236

0.0394

3.5°

L

0.45

0°

0.60

0.75

7°

0.0177

0°

0.0295

7°

L1

k

1.00

3.5°

ccc

0.08

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 14611 Rev 7

111/123

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

(1)(2)

Figure 65. LQFP100, 14 x 14 mm 100-pin low-profile

Figure 66. Recommended footprint

(1)

quad flat package outline

0.25 mm

0.10 inch

GAGE PLANE

k

75

51

D

L

D1

76

50

L1

D3

0.5

51

75

C

76

50

0.3

16.7 14.3

b

E3 E1

E

100

26

1.2

100

26

1

25

Pin 1

identification

1

25

ccc

C

12.3

16.7

e

A1

A2

A

ai14906b

SEATING PLANE

C

1L_ME

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 68. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

0.063

0.05

1.35

0.002

0.0531

0.0067

0.0035

0.622

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

1.40

0.22

1.45

0.0551

0.0087

0.17

0.27

c

0.09

0.20

D

15.80

13.80

16.00

14.00

12.00

16.00

14.00

12.00

0.50

16.20

14.20

0.6299

0.5512

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

D1

D3

E

0.5433

15.80

13.80

16.20

14.20

0.622

0.6378

0.5591

E1

E3

e

0.5433

L

0.45

0°

0.60

0.75

7°

0.0177

0°

0.0295

7°

L1

k

1.00

3.5°

ccc

0.08

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

112/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

(1)(2)

Figure 67. LQFP64 – 10 x 10 mm 64 pin low-profile

Figure 68. Recommended footprint

(1)

quad flat package outline

A

48

33

A2

0.3

A1

49

32

0.5

b

12.7

E

E1

10.3

e

10.3

64

17

1.2

1

16

D1

D

c

7.8

L1

12.7

L

ai14909

ai14398b

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 69. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.0630

0.0059

0.0571

0.0106

0.0079

0.05

1.35

0.17

0.09

0.0020

0.0531

0.0067

0.0035

1.40

0.22

0.0551

0.0087

c

D

12.00

10.00

12.00

10.00

0.50

0.4724

0.3937

0.4724

0.3937

0.0197

3.5°

D1

E

E1

e



0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.0177

0.0236

0.0394

0.0295

L1

1.00

Number of pins

64

N

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 14611 Rev 7

113/123

Package characteristics

STM32F103xC, STM32F103xD, STM32F103xE

6.2

Thermal characteristics

The maximum chip junction temperature (T max) must never exceed the values given in

J

Table 10: General operating conditions on page 42.

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max x  )

J

A

D

JA

Where:

●

T max is the maximum ambient temperature in °C,

A



is the package junction-to-ambient thermal resistance, in C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = (V × I ) + ((V – V ) × I ),

OL OL DD OH OH

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 70. Package thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

LFBGA144 - 10 × 10 mm / 0.8 mm pitch

40

Thermal resistance junction-ambient

LQFP144 - 20 × 20 mm / 0.5 mm pitch

30

40

46

45

50

Thermal resistance junction-ambient

LFBGA100 - 10 × 10 mm / 0.8 mm pitch

_JA

°C/W

Thermal resistance junction-ambient

LQFP100 - 14 × 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

WLCSP64

6.2.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

114/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Package characteristics

6.2.2

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Table 71: Ordering information scheme.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F103xC, STM32F103xD and

STM32F103xE at maximum dissipation, it is useful to calculate the exact power

consumption and junction temperature to determine which temperature range will be best

suited to the application.

The following examples show how to calculate the temperature range needed for a given

application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

= 82 °C (measured according to JESD51-2),

Amax

I

= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output

OL

at low level with I = 20 mA, V = 1.3 V

OL

P

= 50 mA × 3.5 V= 175 mW

INTmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

IOmax

This gives: P

= 175 mW and P

= 272 mW:

IOmax

INTmax

P

= 175 + 272 = 447 mW

Dmax

Thus: P

= 447 mW

Dmax

Using the values obtained in Table 70 T

is calculated as follows:

Jmax

–

T

For LQFP100, 46 °C/W

= 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C

Jmax

This is within the range of the suffix 6 version parts (–40 < T < 105 °C).

J

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Table 71: Ordering information scheme).

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient

temperatures with a low dissipation, as long as junction temperature T remains within the

J

specified range.

Assuming the following application conditions:

Maximum ambient temperature T

= 115 °C (measured according to JESD51-2),

Amax

I

= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V

OL

P

= 20 mA × 3.5 V= 70 mW

INTmax

= 20 × 8 mA × 0.4 V = 64 mW

IOmax

This gives: P

= 70 mW and P

= 64 mW:

IOmax

INTmax

P

= 70 + 64 = 134 mW

Dmax

Thus: P

= 134 mW

Dmax

Doc ID 14611 Rev 7

115/123

Package characteristics

Using the values obtained in Table 70 T

STM32F103xC, STM32F103xD, STM32F103xE

is calculated as follows:

Jmax

–

T

For LQFP100, 46 °C/W

= 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C

Jmax

This is within the range of the suffix 7 version parts (–40 < T < 125 °C).

J

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Table 71: Ordering information scheme).

Figure 69. LQFP100 P max vs. T

D

A

700

600

500

400

300

200

100

0

Suffix 6

Suffix 7

65

75

85

95 105 115 125 135

T_A(°C)

116/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Part numbering

7

Part numbering

Table 71. Ordering information scheme

Example:

STM32

F 103 R

C

T

6

xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

103 = performance line

Pin count

R = 64 pins

V = 100 pins

Z = 144 pins

Flash memory size

C = 256 Kbytes of Flash memory

D = 384 Kbytes of Flash memory

E = 512 Kbytes of Flash memory

Package

H = BGA

T = LQFP

Y = WLCSP64

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

7 = Industrial temperature range, –40 to 105 °C.

Options

xxx = programmed parts

TR = tape and real

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

Doc ID 14611 Rev 7

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Revision history

STM32F103xC, STM32F103xD, STM32F103xE

8

Revision history

Table 72. Document revision history

Date

Revision

Changes

07-Apr-2008

1

Initial release.

Document status promoted from Target Specification to Preliminary

Data.

Section 1: Introduction and Section 2.2: Full compatibility throughout

the family modified. Small text changes.

Note 2 added in Table 2: STM32F103xC, STM32F103xD and

STM32F103xE features and peripheral counts on page 11.

LQPF100/BGA100 column added to Table 6: FSMC pin definition on

page 36.

Values and Figures added to Maximum current consumption on

page 44 (see Table 14, Table 15, Table 16 and Table 17 and see

Figure 14, Figure 15, Figure 17, Figure 18 and Figure 19).

Values added to Typical current consumption on page 50 (see Table 18,

Table 19 and Table 20). Table 19: Typical current consumption in

Standby mode removed.

22-May-2008

2

Note 4 and Note 1 added to Table 56: USB DC electrical characteristics

and Table 57: USB: full-speed electrical characteristics on page 97,

respectively.

V_USBadded to Table 56: USB DC electrical characteristics on page 97.

Figure 64: Recommended footprint(1) on page 111 corrected.

Equation 1 corrected. Figure 69: LQFP100 PD max vs. TA on page 116

modified.

Tolerance values corrected in Table 64: LFBGA144 – 144-ball low

profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data

on page 107.

118/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

Table 72. Document revision history

Revision history

Date

Revision

Changes

Document status promoted from Preliminary Data to full datasheet.

FSMC (flexible static memory controller) on page 15 modified.

Number of complementary channels corrected in Figure 1:

STM32F103xC, STM32F103xD and STM32F103xE performance line

block diagram.

Power supply supervisor on page 17 modified and V_DDAadded to

Table 10: General operating conditions on page 42.

Table notes revised in Section 5: Electrical characteristics.

Capacitance modified in Figure 12: Power supply scheme on page 40.

Table 51: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) updated.

Table 52: SPI characteristics modified, t_h(NSS)modified in Figure 45:

SPI timing diagram - slave mode and CPHA = 0 on page 91.

Minimum SDA and SCL fall time value for Fast mode removed from

Table 50: I2C characteristics on page 88, note 1 modified.

21-Jul-2008

3

I_{DD_VBAT}values and some I_DDvalues with regulator in run mode added

to Table 17: Typical and maximum current consumptions in Stop and

Standby modes on page 48.

Table 30: Flash memory endurance and data retention on page 61

updated.

t_su(NSS)modified in Table 52: SPI characteristics on page 90.

EO corrected in Table 61: ADC accuracy on page 100. Figure 54:

Typical connection diagram using the ADC on page 101 and note below

corrected.

Typical T_{S_temp}value removed from Table 63: TS characteristics on

page 105.

Section 6.1: Package mechanical data on page 106 updated.

Small text changes.

Doc ID 14611 Rev 7

119/123

Revision history

Table 72. Document revision history

STM32F103xC, STM32F103xD, STM32F103xE

Changes

Date

Revision

Timers specified on page 1 (motor control capability mentioned).

Section 2.2: Full compatibility throughout the family updated.

Table 4: High-density timer feature comparison added.

General-purpose timers (TIMx) and Advanced-control timers (TIM1 and

TIM8) on page 19 updated.

Figure 1: STM32F103xC, STM32F103xD and STM32F103xE

performance line block diagram modified.

Note 10 added, main function after reset and Note 5 on page 35

updated in Table 5: High-density STM32F103xx pin definitions.

Note 2 modified below Table 7: Voltage characteristics on page 41,

|V_DDx| min and |V_DDx| min removed.

12-Dec-2008

4

Note 2 and P_Dvalues for LQFP144 and LFBGA144 packages added to

Table 10: General operating conditions on page 42.

Measurement conditions specified in Section 5.3.5: Supply current

characteristics on page 44.

Max values at T_A= 85 °C and T_A= 105 °C updated in Table 17: Typical

and maximum current consumptions in Stop and Standby modes on

page 48.

Section 5.3.10: FSMC characteristics on page 61 updated.

Data added to Table 42: EMI characteristics on page 81.

I_VREFadded to Table 58: ADC characteristics on page 98.

Table 70: Package thermal characteristics on page 114 updated.

Small text changes.

120/123

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STM32F103xC, STM32F103xD, STM32F103xE

Table 72. Document revision history

Revision history

Date

Revision

Changes

I/O information clarified on page 1. Figure 4: STM32F103xC and

STM32F103xE performance line BGA100 ballout corrected.

I/O information clarified on page 1.

In Table 5: High-density STM32F103xx pin definitions:

– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15

updated

– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default

column to Remap column

PG14 pin description modified in Table 6: FSMC pin definition.

Figure 9: Memory map on page 38 modified.

Note modified in Table 14: Maximum current consumption in Run mode,

code with data processing running from Flash and Table 16: Maximum

current consumption in Sleep mode, code running from Flash or RAM.

Figure 17, Figure 18 and Figure 19 show typical curves (titles

changed).

Table 21: High-speed external user clock characteristics and Table 22:

Low-speed external user clock characteristics modified. ACC_HSImax

values modified in Table 25: HSI oscillator characteristics.

FSMC configuration modified for Asynchronous waveforms and timings.

Notes modified below Figure 24: Asynchronous non-multiplexed

SRAM/PSRAM/NOR read waveforms and Figure 25: Asynchronous

non-multiplexed SRAM/PSRAM/NOR write waveforms.

t_w(NADV)values modified in Table 31: Asynchronous non-multiplexed

SRAM/PSRAM/NOR read timings and Table 34: Asynchronous

multiplexed PSRAM/NOR write timings. t_{h(Data_NWE)}modified in

Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write

timings

30-Mar-2009

5

In Table 36: Synchronous multiplexed PSRAM write timings and

Table 38: Synchronous non-multiplexed PSRAM write timings:

– t_v(Data-CLK)renamed as t_d(CLKL-Data)

– t_d(CLKL-Data)min value removed and max value added

– t_h(CLKL-DV)/ t_h(CLKL-ADV)removed

Figure 28: Synchronous multiplexed NOR/PSRAM read timings,

Figure 29: Synchronous multiplexed PSRAM write timings and

Figure 31: Synchronous non-multiplexed PSRAM write timings

modified.

Figure 48: I2S slave timing diagram (Philips protocol)(1) and Figure 49:

I2S master timing diagram (Philips protocol)(1) modified.

WLCSP64 package added (see Figure 8: STM32F103xC and

STM32F103xE performance line WLCSP64 ballout, ball side, Table 5:

High-density STM32F103xx pin definitions, Figure 61: WLCSP, 64-ball

4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package

outline and Table 66: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm

pitch, wafer-level chip-scale package mechanical data).

Small text changes.

Doc ID 14611 Rev 7

121/123

Revision history

Table 72. Document revision history

STM32F103xC, STM32F103xD, STM32F103xE

Changes

Date

Revision

Figure 1: STM32F103xC, STM32F103xD and STM32F103xE

performance line block diagram updated.

Note 5 updated and Note 4 added in Table 5: High-density

STM32F103xx pin definitions.

V_RERINTand T_Coeffadded to Table 13: Embedded internal reference

voltage.

Table 16: Maximum current consumption in Sleep mode, code running

from Flash or RAM modified.

f_{HSE_ext}min modified in Table 21: High-speed external user clock

characteristics.

C_L1and C_L2replaced by C in Table 23: HSE 4-16 MHz oscillator

characteristics and Table 24: LSE oscillator characteristics (fLSE =

32.768 kHz), notes modified and moved below the tables.

Note 1 modified below Figure 22: Typical application with an 8 MHz

crystal. Table 25: HSI oscillator characteristics modified. Conditions

removed from Table 27: Low-power mode wakeup timings.

Jitter added to Table 28: PLL characteristics.

Figure 43: Recommended NRST pin protection modified.

In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read

timings: t_{h(BL_NOE)}and t_{h(A_NOE)}modified.

21-Jul-2009

6

In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write

timings: t_{h(A_NWE)}and t_{h(Data_NWE)}modified.

In Table 33: Asynchronous multiplexed PSRAM/NOR read timings:

t_{h(AD_NADV)}and t_{h(A_NOE)}modified.

In Table 34: Asynchronous multiplexed PSRAM/NOR write timings:

t_{h(A_NWE)}modified.

In Table 35: Synchronous multiplexed NOR/PSRAM read timings:

t_{h(CLKH-NWAITV)}modified.

In Table 40: Switching characteristics for NAND Flash read and write

cycles: t_h(NOE-D)modified.

Table 52: SPI characteristics modified. Values added to Table 53: I2S

characteristics and Table 54: SD / MMC characteristics.

C_ADCand R_AINparameters modified in Table 58: ADC characteristics.

R_AINmax values modified in Table 59: RAIN max for fADC = 14 MHz.

Table 62: DAC characteristics modified. Figure 57: 12-bit buffered /non-

buffered DAC added.

Figure 60: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array

package outline and Table 65: LFBGA100 - 10 x 10 mm low profile fine

pitch ball grid array package mechanical data updated.

Number of DACs corrected in Table 3: STM32F103xx family.

I_{DD_VBAT}updated in Table 17: Typical and maximum current

consumptions in Stop and Standby modes.

Figure 16: Typical current consumption on VBAT with RTC on vs.

temperature at different VBAT values added.

24-Sep-2009

7

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to

IEC 61967-2 in Section 5.3.11: EMC characteristics on page 80.

Table 62: DAC characteristics modified. Small text changes.

122/123

Doc ID 14611 Rev 7

STM32F103xC, STM32F103xD, STM32F103xE

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Doc ID 14611 Rev 7

123/123


型号：	STM32F103ZEH6TR
厂家：	ST
描述：	High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces 高密度高性能线的基于ARM的32位MCU，具有256至512KB闪存， USB ， CAN ，11个定时器， 3的ADC ，13个通信接口闪存通信
文件：	总123页 (文件大小：1691K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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