STM32F303 [STMICROELECTRONICS]
ARM Cortex-M4F 32b MCUFPU, up to 256KB Flash48KB SRAM;
| 型号： | STM32F303 |
| 厂家： | 
ST |
| 描述： | ARM Cortex-M4F 32b MCUFPU, up to 256KB Flash48KB SRAM 静态存储器 |
| 文件： | 总133页 (文件大小：2061K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F302xB STM32F302xC
STM32F303xB STM32F303xC
ARM Cortex-M4F 32b MCU+FPU, up to 256KB Flash+48KB SRAM
4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V operation
Datasheet − production data
Features
■ Core: ARM® 32-bit Cortex™-M4F CPU (72 MHz
max), single-cycle multiplication and HW
division, DSP instruction with FPU (floating-point
unit) and MPU (memory protection unit).
LQFP48 (7 × 7 mm)
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
■ Operating conditions:
■ Up to 13 timers
– V , V
voltage range: 2.0 V to 3.6 V
DD DDA
– One 32-bit timer and two 16-bit timers with
up to 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– Up to two 16-bit 6-channel advanced-control
timers, with up to 6 PWM channels,
deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs, 1
OCN/PWM, deadtime generation and
emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
– Two watchdog timers (independent, window)
– SysTick timer: 24-bit downcounter
– Up to two 16-bit basic timers to drive the
DAC
■ Memories
– 128 to 256 Kbytes of Flash memory
– Up to 40 Kbytes of SRAM on data bus with
HW parity check
– 8 Kbytes of SRAM on instruction bus with
HW parity check (CCM)
■ CRC calculation unit
■ Reset and supply management
– Power-on/Power down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop and Standby
– V
supply for RTC and backup registers
BAT
■ Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x 16 PLL option
– Internal 40 kHz oscillator
■ Calendar RTC with Alarm, periodic wakeup from
Stop/Standby
■ Communication interfaces
■ Up to 87 fast I/Os
– CAN interface (2.0B Active)
2
– All mappable on external interrupt vectors
– Several 5 V-tolerant
■ 12-channel DMA controller
■ Up to four ADC 0.20 µS (up to 39 channels) with
selectable resolution of 12/10/8/6 bits, 0 to 3.6 V
conversion range, separate analog supply from
2 to 3.6 V
■ Up to two 12-bit DAC channels with analog
supply from 2.4 to 3.6 V
■ Seven fast rail-to-rail analog comparators with
analog supply from 2 to 3.6 V
■ Up to four operational amplifiers that can be
used in PGA mode, all terminal accessible with
analog supply from 2.4 to 3.6 V
– Two I C Fast mode plus (1 Mbit/s) with 20
mA current sink, SMBus/PMBus, wakeup
from STOP
– Up to five USART/UARTs (ISO 7816
interface, LIN, IrDA, modem control)
– Up to three SPIs, two with multiplexed I S
2
interface, 4 to 16 programmable bit frame
– USB 2.0 full speed interface
– Infrared Transmitter
■ Serial wire debug, JTAG, Cortex-M4F ETM
■ 96-bit unique ID
Table 1.
Device summary
Reference
Part number
■ Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensors
STM32F302CB, STM32F302CC, STM32F302RB,
STM32F302RC, STM32F302VB, STM32F302VC
STM32F302xx
STM32F303xx
STM32F303CB, STM32F303CC, STM32F303RB,
STM32F303RC, STM32F303VB, STM32F303VC
January 2013
Doc ID 023353 Rev 5
1/133
This is information on a product in full production.
www.st.com
1
Contents
STM32F302xx/STM32F303xx
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
3.6
3.7
ARM® Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . . 13
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.1
3.7.2
3.7.3
3.7.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REFINT
3.12.3
V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
BAT
3.12.4 OPAMP reference voltage (VOPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16.1 Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . 24
3.16.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Contents
3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.16.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25
3.18 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19 Universal synchronous/asynchronous receiver transmitter (USART) . . . 27
3.20 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 27
3.21 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 28
3.22 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.23 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.24 Infrared Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.25 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.26 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.26.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.26.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 59
Embedded reset and power control block characteristics . . . . . . . . . . . 59
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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6.3.6
6.3.7
6.3.8
6.3.9
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.16 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.18 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.23
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
BAT
7
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.1
7.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.2.1
7.2.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 127
8
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F30xB/C family device features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . 10
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2
Table 5.
STM32F30xB/C I C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6.
Table 7.
Table 8.
Table 9.
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32F30xB/C SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Capacitive sensing GPIOs available on STM32F302xx/STM32F303xx devices . . . . . . . . 29
No. of capacitive sensing channels available on STM32F302xx/STM32F303xx devices . 30
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32F302xx/STM32F303xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Alternate functions for port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Alternate functions for port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Alternate functions for port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32F30xB/C memory map and peripheral register boundary addresses . . . . . . . . . . . 51
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 59
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Typical and maximum current consumption from V supply at V = 3.6V . . . . . . . . . . . 62
DD
DD
Typical and maximum current consumption from the V
supply . . . . . . . . . . . . . . . . . . 63
DDA
Typical and maximum V consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 65
DD
Typical and maximum V
consumption in Stop and Standby modes. . . . . . . . . . . . . . . 65
DDA
Typical and maximum current consumption from V
supply. . . . . . . . . . . . . . . . . . . . . . 66
BAT
Typical current consumption in Run mode, code with data processing running from Flash67
Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 68
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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List of tables
STM32F302xx/STM32F303xx
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2
I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
BAT
LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 120
LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 122
LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 124
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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STM32F302xx/STM32F303xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32F302xB/STM32F302xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM32F303xB/STM32F303xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM32F302xx/STM32F303xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32F302xx/STM32F303xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32F302xx/STM32F303xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32F30xB/C memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 13. Typical V
current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 66
BAT
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 18. HSI oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 19. TC and TTa I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 20. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 88
Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port. . . . . . . . . . . . . . . . . . . 89
Figure 23. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2
Figure 25. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
(1)
Figure 27. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
(1)
Figure 28. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2
(1)
Figure 29. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2
(1)
Figure 30. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 31. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 32. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 33. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 34. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 35. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 120
Figure 36. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 37. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 122
Figure 38. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 39. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 124
Figure 40. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Doc ID 023353 Rev 5
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Introduction
STM32F302xx/STM32F303xx
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F30xB/C microcontrollers.
This STM32F30xB/C datasheet should be read in conjunction with the STM32F30xB/C
reference manual. The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the Cortex™-M4F core please refer to:
●
Cortex™-M4F Technical Reference Manual, available from the www.arm.com
website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.cortexm.m4/
index.html
●
STM32F3xxx and STM32F4xxx Cortex-M4 programming manual (PM0214)
available from the www.st.com website at the following address:
http://www.st.com/internet/com/TECHNICAL_RESOURCES/
TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/DM00046982.pdf
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STM32F302xx/STM32F303xx
Description
2
Description
The STM32F302xx/STM32F303xx family is based on the high-performance ARM®
Cortex™-M4F 32-bit RISC core operating at a frequency of up to 72 MHz, and embedding a
floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell
(ETM). The family incorporates high-speed embedded memories (up to 256 Kbytes of Flash
memory, up to 48 Kbytes of SRAM) and an extensive range of enhanced I/Os and
peripherals connected to two APB buses.
The devices offer up to four fast 12-bit ADCs (5 Msps), up to seven comparators, up to four
operational amplifiers, up to two DAC channels, a low-power RTC, up to five general-
purpose 16-bit timers, one general-purpose 32-bit timer, and two timers dedicated to motor
2
control. They also feature standard and advanced communication interfaces: up to two I Cs,
up to three SPIs (two SPIs are with multiplexed full-duplex I2Ss on
STM32F303xB/STM32F303xC devices), three USARTs, up to two UARTs, CAN and USB.
To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL.
The STM32F302xx/STM32F303xx family operates in the -40 to +85 °C and -40 to +105 °C
temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F302xx/STM32F303xx family offers devices in three packages ranging from 48
pins to 100 pins.
The set of included peripherals changes with the device chosen.
Doc ID 023353 Rev 5
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Description
Table 2.
STM32F302xx/STM32F303xx
STM32F30xB/C family device features and peripheral counts
STM32F
302Cx
STM32F
302Rx
STM32F
302Vx
STM32F
303Cx
STM32F
303Rx
STM32F
303Vx
Peripheral
Flash (Kbytes)
128
24
256
32
128
24
256
32
128 256 128 256
128
32
256
40
128
32
256
40
SRAM (Kbytes) on
data bus
24
32
8
32
40
SRAM (Kbytes) on
instruction bus (CCM:
core coupled memory)
Advanced
control
1 (16-bit)
2 (16-bit)
Timers
General
purpose
5 (16-bit)
1 (32-bit)
Basic
SPI(I2S)(1)
I2C
1 (16-bit)
3
2 (16-bit)
3(2)
2
3
Comm.
interfaces
USART
UART
CAN
0
2
0
2
1
1
USB
Normal
I/Os
(TC, TTa)
20
17
27
25
45
20
17
27
25
45
42
GPIOs
5 volts
Tolerant
I/Os
42
24
(FT, FTf)
DMA channels
12
Capacitive sensing
channels
17
18
17
18
24
12-bit ADCs
2
1
4
2
4
2
7
4
12-bit DAC channels
Analog comparator
Operational amplifiers
CPU frequency
72 MHz
2.0 to 3.6 V
Operating voltage
Operating
temperature
Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Junction temperature: - 40 to 125 °C
Packages
LQFP48
LQFP64
LQFP100
LQFP48
LQFP64
LQFP100
1. In STM32F303xB/STM32F303xC devices the SPI interfaces can work in an exclusive way in either the SPI mode or the I2S
audio mode.
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Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Figure 1. STM32F302xB/STM32F302xC block diagram
Description
Power
TPIU
VDD18
VDDIO = 2 to 3.6 V
VSS
ETM
TRADECLK
TRACED[0-3]
as AF
Trace/Trig
Voltage reg.
3.3 V to 1.8V
SWJTAG
MPU/FPU
@VDDIO
FLASH 256 KB
64 bits
JTRST
JTDI
Ibus
Dbus
Supply
Supervision
POR
Cortex M4 CPU
Fmax: 72 MHz
JTCK/SWCLK
JTMS/SWDIO
JTDO
Reset
Int.
NRESET
VDDA
VSSA
POR /PDR
PVD
CCM RAM
8KB
As AF
System
SRAM
40 KB
NVIC
@VDDA
@VDDA
RC HS 8MHz
@VDDIO
GP DMA1
7 channels
RC LS
PLL
XTAL OSC
4 -32 MHz
OSC_IN
OSC_OUT
GP DMA2
5 channels
Ind. WDG32K
Standby
interface
AHBPCLK
Temp. sensor
APBP1CLK
APBP2CLK
HCLK
VBAT = 1.65V to 3.6V
12-bit ADC1
12-bit ADC2
VREF+
VREF-
IF
@VSW
Reset &
OSC32_IN
OSC32_OUT
clock
FCLK
XTAL 32kHz
Backup
control
USARTCLK
I2CCLK
ADC SAR
1/2/3/4 CLK
RTC
Reg
(64Byte)
Backup
interface
ANTI-TAMP
AWU
TIMER2
CRC
4 Channels, ETR as AF
4 Channels, ETR as AF
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
(32-bit/PWM)
TIMER 3
TIMER 4
4 Channels, ETR as AF
MOSI, MISO,
SCK, NSS as AF
SPI2
SPI3
GPIO PORT E
GPIO PORT F
PE[15:0]
PF[7:0]
MOSI, MISO,
SCK, NSS as AF
USART2
USART3
UART4
RX, TX, CTS, RTS, as AF
RX, TX, CTS, RTS, as AF
RX, TX as AF
Touch Sensing
Controller
XX Groups of
4 channels as AF
AHB2
APB2
AHB2
APB1
UART5
I2C1
RX, TX as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
EXT.IT
WKUP
XX AF
I2C2
WinWATCHDOG
USB SRAM 512B
bx CAN &
512B SRAM
CAN TX, CAN RX
USB_DP, USB_DM
2 Channels,1 Comp
Channel, BRK as AF
TIMER 15
TIMER 16
USB 2.0 FS
1 Channel, 1 Comp
Channel, BRK as AF
TIMER6
1 Channel, 1 Comp
Channel, BRK as AF
IF 12bit DAC1
@VDDA
TIMER 17
DAC1_CH1 as AF
4 Channels,
4 Comp channels,
ETR, BRK as AF
SYSCFG CTL
TIMER 1 / PWM
OpAmp1
OpAmp2
INxx / OUTxx
INxx / OUTxx
@VDDA
SPI1
MOSI, MISO,
SCK,NSS as AF
GP Comparator 6
GP Comparator 4
GP Comparator 2
@VDDA
RX, TX, CTS, RTS,
SmartCard as AF
USART1
GP Comparator 1
MS18959V5
Xx Ins, 4 OUTs as AF
1. AF: alternate function on I/O pins.
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Description
Figure 2.
STM32F302xx/STM32F303xx
STM32F303xB/STM32F303xC block diagram
Power
TPIU
ETM
VDD18
VDDIO = 2 to 3.6 V
VSS
TRADECLK
TRACED[0-3]
as AF
Trace/Trig
SWJTAG
Voltage reg.
3.3 V to 1.8V
MPU/FPU
@VDDIO
FLASH 256 KB
64 bits
JTRST
JTDI
Ibus
Dbus
Supply
Supervision
POR
Cortex M4 CPU
Fmax: 72 MHz
JTCK/SWCLK
JTMS/SWDIO
JTDO
Reset
Int.
NRESET
VDDA
VSSA
POR /PDR
PVD
CCM RAM
8KB
As AF
System
SRAM
40 KB
NVIC
@VDDA
@VDDA
RC HS 8MHz
@VDDIO
GP DMA1
7 channels
RC LS
PLL
XTAL OSC
4 -32 MHz
OSC_IN
OSC_OUT
GP DMA2
5 channels
Ind. WDG32K
Standby
interface
AHBPCLK
Temp. sensor
APBP1CLK
APBP2CLK
HCLK
VBAT = 1.65V to 3.6V
12-bit ADC1
12-bit ADC2
IF
IF
@VSW
VREF+
VREF-
Reset &
OSC32_IN
OSC32_OUT
clock
FCLK
XTAL 32kHz
Backup
control
USARTCLK
I2CCLK
ADC SAR
1/2/3/4 CLK
RTC
12-bit ADC3
12-bit ADC4
Reg
(64Byte)
Backup
interface
ANTI-TAMP
AWU
TIMER2
CRC
4 Channels, ETR as AF
4 Channels, ETR as AF
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
(32-bit/PWM)
TIMER 3
TIMER 4
4 Channels, ETR as AF
MOSI/SD, MISO/ext_SD,
SCK/CK, NSS/WS, MCLK as AF
SPI2/I2S
SPI3/I2S
USART2
USART3
UART4
GPIO PORT E
GPIO PORT F
PE[15:0]
PF[7:0]
MOSI/SD, MISO/ext_SD,
SCK/CK, NSS/WS, MCLK as AF
RX, TX, CTS, RTS, as AF
RX, TX, CTS, RTS, as AF
RX, TX as AF
Touch Sensing
Controller
XX Groups of
4 channels as AF
AHB2
APB2
AHB2
APB1
UART5
I2C1
RX, TX as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
I2C2
WinWATCHDOG
USB SRAM 512B
bx CAN &
512B SRAM
CAN TX, CAN RX
USB_DP, USB_DM
EXT.IT
WKUP
XX AF
USB 2.0 FS
2 Channels,1 Comp
Channel, BRK as AF
TIMER 15
TIMER 16
TIMER6
TIMER7
DAC1_CH1 as AF
DAC1_CH2 as AF
1 Channel, 1 Comp
Channel, BRK as AF
IF 12bit DAC1
@VDDA
1 Channel, 1 Comp
Channel, BRK as AF
TIMER 17
4 Channels,
TIMER 1 / PWM
TIMER 8 / PWM
4 Comp channels,
ETR, BRK as AF
OpAmp1
OpAmp2
OpAmp3
OpAmp4
INxx / OUTxx
INxx / OUTxx
INxx / OUTxx
INxx / OUTxx
4 Channels,
4 Comp channels,
ETR, BRK as AF
SYSCFG CTL
MOSI, MISO,
SCK,NSS as AF
@VDDA
SPI1
@VDDA
GP Comparator 7
GP Comparator...
GP Comparator 1
RX, TX, CTS, RTS,
SmartCard as AF
USART1
MS18960V4
Xx Ins, 7 OUTs as AF
1. AF: alternate function on I/O pins.
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STM32F302xx/STM32F303xx
Functional overview
3
Functional overview
3.1
ARM® Cortex™-M4F core with embedded Flash and SRAM
The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded
systems. It was developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing
and complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32F302xx/STM32F303xx family is compatible with
all ARM tools and software.
Figure 1 and Figure 2 show the general block diagrams of the
STM32F302xx/STM32F303xx family devices.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3
Embedded Flash memory
All STM32F302xx/STM32F303xx devices feature up to 256 Kbytes of embedded Flash
memory available for storing programs and data. The Flash memory access time is adjusted
to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz
and 2 wait states above).
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Functional overview
STM32F302xx/STM32F303xx
3.4
3.5
3.6
Embedded SRAM
STM32F302xx/STM32F303xx devices feature up to 48 Kbytes of embedded SRAM with
hardware parity check. The memory can be accessed in read/write at CPU clock speed with
0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running
code from CCM, core coupled memory).
●
8 Kbytes of SRAM mapped on the instruction bus (Core Coupled Memory (CCM)),
used to execute critical routines or to access data (parity check on all of CCM RAM).
●
40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).
Boot modes
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
●
●
●
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU (device
firmware upgrade) .
Cyclic redundancy check (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
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Functional overview
3.7
Power management
3.7.1
Power supply schemes
●
V
, V = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
SS DD
provided externally through V pins
DD
●
V
, V
= 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators
DDA
SSA
operational amplifiers, reset blocks, RCs and PLL (minimum voltage to be applied to
is 2.4 V when the DACs and operational amplifiers are used). The V voltage
V
DDA
DDA
level must be always greater or equal to the V voltage level and must be provided
DD
first.
●
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V is not present.
DD
3.7.2
Power supply supervisor
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
●
The POR monitors only the V supply voltage. During the startup phase it is required
DD
that V
should arrive first and be greater than or equal to V
.
DDA
DD
●
The PDR monitors both the V and V
supply voltages, however the V
power
DDA
DD
DDA
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V is higher than or
DDA
equal to V
.
DD
The device features an embedded programmable voltage detector (PVD) that monitors the
power supply and compares it to the VPVD threshold. An interrupt can be generated
V
DD
when V drops below the V
threshold and/or when V is higher than the V
DD
PVD
DD PVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.7.3
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR), and power-down.
●
●
●
The MR mode is used in the nominal regulation mode (Run)
The LPR mode is used in Stop mode.
The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
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Functional overview
STM32F302xx/STM32F303xx
3.7.4
Low-power modes
The STM32F302xx/STM32F303xx supports three low power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the USB wakeup on
STM32F303xB/STM32F303xC devices, the RTC alarm, COMPx, I2Cx or U(S)ARTx.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin or an RTC alarm occurs.
Note:
The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
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Functional overview
3.8
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
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Functional overview
Figure 3. Clock tree
STM32F302xx/STM32F303xx
FLITFCLK
to Flash programming interface
HSI
to I2Cx (x = 1,2)
SYSCLK
I2SSRC
SYSCLK
to I2Sx (x = 2,3)
Ext. clock
I2S_CKIN
USB
prescaler
/1,1.5
USBCLK
to USB interface
HSI
8 MHz
HSI RC
/2
HCLK
/8
to AHB bus, core,
memory and DMA
PLLSRC
to cortex System timer
FHCLK Cortex free
running clock
SW
HSI
PLLMUL
AHB
APB1
PLL
x2,x3,..
x16
PLLCLK
PCLK1
to APB1 peripherals
prescaler
/1,2,..512
prescaler
/1,2,4,8,16
HSE
SYSCLK
If (APB1 prescaler
=1) x1 else x2
CSS
to TIM 2,3,4,6,7
/2,/3,...
/16
PCLK1
SYSCLK
to U(S)ARTx (x = 2..5)
OSC_OUT
OSC_IN
HSI
4-32 MHz
HSE OSC
LSE
APB2
prescaler
/1,2,4,8,16
PCLK2
to APB2 peripherals
to TIM 15,16,17
/32
RTCCLK
OSC32_IN
to RTC
LSE OSC
If (APB2 prescaler
=1) x1 else x2
32.768kHz LSE
OSC32_OUT
RTCSEL[1:0]
PCLK2
LSI
/2
IWDGCLK
to IWDG
LSI RC
40kHz
SYSCLK
to USART1
TIM1/8
HSI
LSE
x2
PLLCLK
Main clock
output
HSI
MCO
LSI
HSE
SYSCLK
MCO
ADC
Prescaler
/1,2,4
to ADCxy
(xy = 12, 34)
ADC
Prescaler
/1,2,4,6,8,10,12,16,
32,64,128,256
MS19989V4
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Functional overview
3.9
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.10
Direct memory access (DMA)
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-
memory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.
Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.
3.11
Interrupts and events
3.11.1
Nested vectored interrupt controller (NVIC)
The STM32F302xx/STM32F303xx devices embed a nested vectored interrupt controller
(NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
●
●
●
●
●
●
●
●
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
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Functional overview
STM32F302xx/STM32F303xx
3.12
Fast analog-to-digital converter (ADC)
Up to four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12
and 6 bit, are embedded in the STM32F302xx/STM32F303xx family devices. The ADCs
have up to 39 external channels. Some of the external channels are shared between
ADC1&2 and between ADC3&4, performing conversions in single-shot or scan modes. In
scan mode, automatic conversion is performed on a selected group of analog inputs.
The ADCs have also internal channels: Temperature sensor connected to ADC1 channel
16, V
connected to ADC1 channel 17, Voltage reference V
connected to the 4
BAT/2
REFINT
ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to
ADC2 channel 17, VOPAMP3 connected to ADC3 channel 17, VOPAMP4 connected to
ADC4 channel 17.
Additional logic functions embedded in the ADC interface allow:
●
●
●
Simultaneous sample and hold
Interleaved sample and hold
Single-shunt phase current reading techniques.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers and the advanced-control timers (TIM1
on all devices and TIM8 on STM32F303xB/STM32F303xC devices) can be internally
connected to the ADC start trigger and injection trigger, respectively, to allow the application
to synchronize A/D conversion and timers.
3.12.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
that varies linearly with
SENSE
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.12.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC and Comparators. V
is internally connected to the ADC_IN18 input channel. The
REFINT
precise voltage of V
is individually measured for each part by ST during production
REFINT
test and stored in the system memory area. It is accessible in read-only mode.
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STM32F302xx/STM32F303xx
Functional overview
3.12.3
V
battery voltage monitoring
BAT
This embedded hardware feature allows the application to measure the V
battery voltage
BAT
using the internal ADC channel ADC_IN17. As the V
voltage may be higher than V
,
BAT
DDA
and thus outside the ADC input range, the V
pin is internally connected to a bridge
BAT
divider by 2. As a consequence, the converted digital value is half the V
voltage.
BAT
3.12.4
OPAMP reference voltage (VOPAMP)
Every OPAMP reference voltage can be measured using a corresponding ADC internal
channel: VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to ADC2
channel 17, VOPAMP3 connected to ADC3 channel 17, VOPAMP4 connected to ADC4
channel 17.
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Functional overview
STM32F302xx/STM32F303xx
3.13
Digital-to-analog converter (DAC)
Up to two 12-bit buffered DAC channels can be used to convert digital signals into analog
voltage signal outputs. The chosen design structure is composed of integrated resistor
strings and an amplifier in inverting configuration.
This digital interface supports the following features:
●
●
●
●
●
●
●
Up to two DAC output channels on STM32F303xB/STM32F303xC devices
8-bit or 10-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability on STM32F303xB/STM32F303xC devices
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions on
STM32F303xB/STM32F303xC devices
●
●
DMA capability (for each channel on STM32F303xB/STM32F303xC devices)
External triggers for conversion
3.14
Operational amplifier (OPAMP)
The STM32F302xx/STM32F303xx embeds up to four operational amplifiers with external or
internal follower routing and PGA capability (or even amplifier and filter capability with
external components). When an operational amplifier is selected, an external ADC channel
is used to enable output measurement.
The operational amplifier features:
●
●
●
●
8.2 MHz bandwidth
0.5 mA output capability
Rail-to-rail input/output
In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.
3.15
Fast comparators (COMP)
The STM32F302xx/STM32F303xx devices embed seven fast rail-to-rail comparators with
programmable reference voltage (internal or external), hysteresis and speed (low speed for
low power) and with selectable output polarity.
The reference voltage can be one of the following:
●
●
●
External I/O
DAC output pin
Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 26: Embedded
internal reference voltage on page 60 for the value and precision of the internal
reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined per pair into a window comparator
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Functional overview
3.16
Timers and watchdogs
The STM32F302xx/STM32F303xx includes up to two advanced control timers, up to 6
general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. The
table below compares the features of the advanced control, general purpose and basic
timers.
Table 3.
Timer feature comparison
DMA
request
generation Channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
TIM1,
TIM8
(on
Any integer
between 1
and 65536
Up, Down,
Up/Down
Advanced
16-bit
Yes
4
Yes
STM32F303xB
/STM32F303x
C devices only)
Any integer
between 1
and 65536
General-
purpose
Up, Down,
Up/Down
TIM2
TIM3, TIM4
TIM15
32-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
Yes
4
4
2
1
No
No
1
Any integer
between 1
and 65536
General-
purpose
Up, Down,
Up/Down
Any integer
between 1
and 65536
General-
purpose
Up
Up
Any integer
between 1
and 65536
General-
purpose
TIM16, TIM17
1
TIM6,
TIM7
(on
Any integer
between 1
and 65536
Basic
16-bit
Up
Yes
0
No
STM32F303xB
/STM32F303x
C devices only)
3.16.1
Advanced timers (TIM1, TIM8)
The advanced-control timers (TIM1 on all devices and TIM8 on
STM32F303xB/STM32F303xC devices) can each be seen as a three-phase PWM
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead-times. They can also be seen as complete general-purpose timers. The 4
independent channels can be used for:
●
●
●
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
●
One-pulse mode output
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Functional overview
STM32F302xx/STM32F303xx
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
Section 3.16.2 using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
3.16.2
General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)
There are up to six synchronizable general-purpose timers embedded in the
STM32F302xx/STM32F303xx (see Table 3 for differences). Each general-purpose timer
can be used to generate PWM outputs, or act as a simple time base.
●
TIM2, 3, and TIM4
These are full-featured general-purpose timers:
–
–
TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler
TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.
These timers all feature 4 independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
TIM15, 16 and 17
●
These three timers general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
–
TIM15 has 2 channels and 1 complementary channel
TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.16.3
3.16.4
Basic timers (TIM6, TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
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Functional overview
3.16.5
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.16.6
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
●
●
●
●
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
3.17
Real-time clock (RTC) and backup registers
The RTC and the 16 backup registers are supplied through a switch that takes power from
either the V supply when present or the V
pin. The backup registers are sixteen 32-bit
DD
BAT
registers used to store 64 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. It supports the following features:
●
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
●
●
●
Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.
Two programmable alarms with wake up from Stop and Standby mode capability.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
●
●
●
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stopand Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
●
17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY
capability.
The RTC clock sources can be:
●
●
●
●
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 40 kHz)
The high-speed external clock divided by 32.
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Functional overview
STM32F302xx/STM32F303xx
3.18
Inter-integrated circuit interface (I2C)
2
Up to two I C bus interfaces can operate in multimaster and slave modes. They can support
standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses
(2 addresses, 1 with configurable mask). They also include programmable analog and
digital noise filters.
Table 4.
Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
≥ 50 ns
1. Extra filtering capability vs.
standard requirements.
Benefits
Available in Stop mode
2. Stable length
Disabled when Wakeup from Stop
mode is enabled
Variations depending on
temperature, voltage, process
Drawbacks
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU
clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 5 for the features available in I2C1 and I2C2.
2
Table 5.
STM32F30xB/C I C implementation
I2C features(1)
I2C1
I2C2
7-bit addressing mode
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Independent clock
SMBus
Wakeup from STOP
1. X = supported.
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Functional overview
3.19
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32F302xx/STM32F303xx devices have three embedded universal
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode and have LIN Master/Slave capability. The USART interfaces can be
served by the DMA controller.
3.20
Universal asynchronous receiver transmitter (UART)
The STM32F302xx/STM32F303xx devices have 2 embedded universal asynchronous
receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC,
multiprocessor communication mode and single-wire half-duplex communication mode. The
UART interfaces can be served by the DMA controller.
Refer to Table 6 for the features available in all U(S)ARTs interfaces
Table 6.
USART features
USART modes/features(1)
USART1
USART2
USART3
UART4
UART5
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
X
X
X
X
X
X
X
X
X
X
X
X
LIN mode
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
1. X = supported.
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Functional overview
STM32F302xx/STM32F303xx
3.21
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio
standards can operate as master or slave at half-duplex and full duplex communication
modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode
it can output a clock for an external audio component at 256 times the sampling frequency.
Refer to Table 7 for the features available in SPI1, SPI2 and SPI3.
Table 7.
STM32F30xB/C SPI/I2S implementation
SPI features(1)
SPI1
SPI2
SPI3
Hardware CRC calculation
Rx/Tx FIFO
X
X
X
X
X
X
X
X
X
X
X
X
X
NSS pulse mode
I2S mode
TI mode
X
1. X = supported.
3.22
3.23
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
Universal serial bus (USB)
The STM32F302xx/STM32F303xx devices embed an USB device peripheral compatible
with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s)
function interface. It has software-configurable endpoint setting and suspend/resume
support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock
source must use a HSE crystal oscillator). The USB has a dedicated 512-bytes SRAM
memory for data transmission and reception.
3.24
Infrared Transmitter
The STM32F302xx/STM32F303xx devices provide an infrared transmitter solution. The
solution is based on internal connections between TIM16 and TIM17 as shown in the figure
below.
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STM32F302xx/STM32F303xx
Functional overview
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
Figure 4.
Infrared transmitter
TIMER 16
(for envelop)
OC
PB9/PA13
TIMER 17
(for carrier)
OC
MS30365V1
3.25
Touch sensing controller (TSC)
The STM32F302xx/STM32F303xx devices provide a simple solution for adding capacitive
sensing functionality to any application. These devices offer up to 24 capacitive sensing
channels distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
Table 8.
Group
Capacitive sensing GPIOs available on STM32F302xx/STM32F303xx
devices
Capacitive sensing
signal name
Pin
name
Capacitive sensing
signal name
Pin
name
Group
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
PB3
PB4
1
2
5
PB6
PB7
PB11
PB12
PB13
PB14
6
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Functional overview
Table 8.
STM32F302xx/STM32F303xx
Capacitive sensing GPIOs available on STM32F302xx/STM32F303xx
devices (continued)
Capacitive sensing
signal name
Pin
name
Capacitive sensing
signal name
Pin
name
Group
Group
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
PC5
PB0
PB1
PB2
PA9
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
PE2
PE3
3
7
PE4
PE5
PD12
PD13
PD14
PD15
PA10
PA13
PA14
4
8
Table 9.
No. of capacitive sensing channels available on
STM32F302xx/STM32F303xx devices
Number of capacitive sensing channels
STM32F30xVx STM32F30xRx STM32F30xCx
Analog I/O group
G1
G2
G3
G4
G5
G6
G7
G8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
0
0
3
3
2
3
3
3
0
0
Number of capacitive
sensing channels
24
18
17
3.26
Development support
3.26.1
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3.26.2
Embedded trace macrocell™
The ARM embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
30/133
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STM32F302xx/STM32F303xx
Functional overview
STM32F302xx/STM32F303xx through a small number of ETM pins to an external hardware
trace port analyzer (TPA) device. The TPA is connected to a host computer using a high-
speed channel. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer running debugger software. TPA hardware is
commercially available from common development tool vendors. It operates with third party
debugger software tools.
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Pinouts and pin description
STM32F302xx/STM32F303xx
4
Pinouts and pin description
Figure 5.
STM32F302xx/STM32F303xx LQFP48 pinout
48 47 46 45 44 43 42 41 40 39 38 37
VDD_3
VSS_3
PA13
PA12
PA11
PA10
PA9
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
VBAT
PC13
PC14/OSC32_IN
PC15/OSC32_OUT
PF0/OSC_IN
4
5
6
7
8
9
PF1/OSC_OUT
,1&0ꢀꢁ
NRST
PA8
VSSA/VREF-
PB15
PB14
PB13
PB12
VDDA/VREF+
PA0
PA1
PA2
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
.4ꢀꢁꢂꢀꢁ7ꢃ
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Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Figure 6. STM32F302xx/STM32F303xx LQFP64 pinout
Pinouts and pin description
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD_3
VSS_3
PA13
PA12
PA11
PA10
PA9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
VBAT
PC13
PC14/OSC32_IN
PC15/OSC32_OUT
PF0/OSC_IN
PF1/OSC_OUT
NRST
PA8
PC0
,1&0ꢂꢀ
PC9
PC1
9
PC8
PC2
10
11
12
13
14
15
16
PC7
PC3
PC6
VSSA/VREF-
VDDA
PB15
PB14
PB13
PB12
PA0
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AIꢃꢁꢀꢁꢀ6ꢀ
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Pinouts and pin description
STM32F302xx/STM32F303xx
Figure 7.
STM32F302xx/STM32F303xx LQFP100 pinout
0%ꢉ
0%ꢈ
0%ꢀ
0%ꢇ
ꢃ
ꢉ
ꢈ
ꢀ
ꢇ
ꢂ
ꢆ
ꢁ
ꢆꢇ
ꢆꢀ
ꢆꢈ
ꢆꢉ
ꢆꢃ
ꢆꢄ
ꢂꢅ
ꢂꢁ
ꢂꢆ
ꢂꢂ
ꢂꢇ
ꢂꢀ
ꢂꢈ
ꢂꢉ
ꢂꢃ
ꢂꢄ
ꢇꢅ
ꢇꢁ
ꢇꢆ
ꢇꢂ
ꢇꢇ
ꢇꢀ
ꢇꢈ
ꢇꢉ
ꢇꢃ
6$$?ꢈ
633?ꢈ
0&ꢂ
0!ꢃꢈ
0!ꢃꢉ
0!ꢃꢃ
0!ꢃꢄ
0!ꢅ
0!ꢁ
0#ꢅ
0#ꢁ
0#ꢆ
0%ꢂ
6"!4
0#ꢃꢈ
0#ꢃꢀꢊ/3#ꢈꢉ?).
0#ꢃꢇꢊ/3#ꢈꢉ?/54
ꢅ
0&ꢅ
0&ꢃꢄ
0&ꢄꢊ/3#?).
0&ꢃꢊ/3#?/54
.234
ꢃꢄ
ꢃꢃ
ꢃꢉ
ꢃꢈ
ꢃꢀ
ꢃꢇ
ꢃꢂ
ꢃꢆ
ꢃꢁ
ꢃꢅ
ꢉꢄ
ꢉꢃ
ꢉꢉ
ꢉꢈ
ꢉꢀ
ꢉꢇ
0#ꢂ
,1&0ꢃꢄꢄ
0$ꢃꢇ
0$ꢃꢀ
0$ꢃꢈ
0$ꢃꢉ
0$ꢃꢃ
0$ꢃꢄ
0$ꢅ
0#ꢄ
0#ꢃ
0#ꢉ
0#ꢈ
0&ꢉ
633!ꢊ62%&ꢋ
62%&ꢌ
6$$!
0!ꢄ
0$ꢁ
0"ꢃꢇ
0"ꢃꢀ
0"ꢃꢈ
0"ꢃꢉ
0!ꢃ
0!ꢉ
AIꢃꢁꢀꢁꢇ6ꢀ
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Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Pinouts and pin description
Table 10. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
FTf
TTa
TC
B
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
3.3 V tolerant I/O directly connected to ADC
Standard 3.3V I/O
I/O structure
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Doc ID 023353 Rev 5
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Pinouts and pin description
STM32F302xx/STM32F303xx
Table 11. STM32F302xx/STM32F303xx pin definitions
Pin number
Pin functions
Pin name
(function
after
reset)
Alternate functions
Additional functions
TRACECK, TIM3_CH1,
TSC_G7_IO1
(1)
(1)
(1)
1
2
3
4
PE2
PE3
PE4
PE5
I/O FT
I/O FT
I/O FT
I/O FT
TRACED0, TIM3_CH2,
TSC_G7_IO2
TRACED1, TIM3_CH3,
TSC_G7_IO3
TRACED2, TIM3_CH4,
TSC_G7_IO4
(1)
(1)
5
6
PE6
I/O FT
S
TRACED3
WKUP3, RTC_TAMP3
1
2
1
2
VBAT
Backup power supply
WKUP2, RTC_TAMP1,
RTC_TS, RTC_OUT
7
PC13(2) I/O TC
TIM1_CH1N
PC14(2)
8
3
4
3
4
OSC32_IN I/O TC
(PC14)
PC15(2)
OSC32_
I/O TC
OUT
OSC32_IN
9
OSC32_OUT
(PC15)
(1)
(1)
10
11
PF9
PF10
PF0-
I/O FT
I/O FT
TIM15_CH1, SPI2_SCK
TIM15_CH2, SPI2_SCK
12
13
5
6
5
OSC_IN I/O FTf
(PF0)
TIM1_CH3N, I2C2_SDA
I2C2_SCL
OSC_IN
PF1-
6
7
OSC_OUT I/O FTf
(PF1)
OSC_OUT
14
15
16
17
18
19
7
8
NRST
PC0
PC1
PC2
PC3
PF2
I/O RST
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
Device reset input / internal reset output (active low)
ADC12_IN6, COMP7_INM(3)
(1)
(1)
(1)
(1)
(1)
9
ADC12_IN7, COMP7_INP(3)
10
11
COMP7_OUT(3)
TIM1_BKIN2
ADC12_IN8
ADC12_IN9
ADC12_IN10
VSSA/
VREF-
20
12
13
8
9
S
Analog ground/Negative reference voltage
21
22
VREF+
VDDA
S
S
Positive reference voltage
Analog power supply
VDDA/
VREF+
S
Analog power supply/Positive reference voltage
36/133
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STM32F302xx/STM32F303xx
Pinouts and pin description
Table 11. STM32F302xx/STM32F303xx pin definitions (continued)
Pin number
Pin functions
Pin name
(function
after
Alternate functions
Additional functions
reset)
USART2_CTS,
ADC1_IN1, COMP1_INM,
RTC_ TAMP2, WKUP1,
COMP7_INP(3)
TIM2_CH1_ETR,
23
14
10
PA0
I/O TTa
TIM8_BKIN(3), TIM8_ETR(3)
,
TSC_G1_IO1, COMP1_OUT
ADC1_IN2, COMP1_INP,
OPAMP1_VINP,
USART2_RTS, TIM2_CH2,
TSC_G1_IO2, TIM15_CH1N
24
25
26
15
16
17
11
12
13
PA1
PA2
PA3
I/O TTa
I/O TTa
I/O TTa
OPAMP3_VINP(3)
USART2_TX, TIM2_CH3,
TIM15_CH1, TSC_G1_IO3,
COMP2_OUT
ADC1_IN3, COMP2_INM,
OPAMP1_VOUT
ADC1_IN4, OPAMP1_VINP,
COMP2_INP,
OPAMP1_VINM
USART2_RX, TIM2_CH4,
TIM15_CH2, TSC_G1_IO4
(1)
27
28
18
19
PF4
I/O TTa
S
COMP1_OUT
ADC1_IN5
VDD_4
ADC2_IN1, DAC1_OUT1,
OPAMP4_VINP(3)
,
COMP1_INM, COMP2_INM,
SPI1_NSS, SPI3_NSS,
I2S3_WS(3), USART2_CK,
TSC_G2_IO1, TIM3_CH2
COMP3_INM(3)
COMP4_INM,
COMP5_INM(3)
COMP6_INM,
COMP7_INM(3)
,
29
20
14
PA4
I/O TTa
,
ADC2_IN2, DAC1_OUT2(3)
OPAMP1_VINP,
OPAMP2_VINM,
OPAMP3_VINP(3)
,
SPI1_SCK, TIM2_CH1_ETR,
TSC_G2_IO2
COMP1_INM, COMP2_INM,
30
21
15
PA5
I/O TTa
COMP3_INM(3)
COMP4_INM,
COMP5_INM(3)
COMP6_INM,
COMP7_INM(3)
,
,
SPI1_MISO, TIM3_CH1,
TIM8_BKIN(3), TIM1_BKIN,
TIM16_CH1, COMP1_OUT,
TSC_G2_IO3
31
32
22
23
16
17
PA6
PA7
I/O TTa
I/O TTa
ADC2_IN3, OPAMP2_VOUT
SPI1_MOSI, TIM3_CH2,
TIM17_CH1, TIM1_CH1N,
TIM8_CH1N(3), TSC_G2_IO4,
COMP2_OUT
ADC2_IN4, COMP2_INP,
OPAMP2_VINP,
OPAMP1_VINP
(1)
(1)
33
34
24
25
PC4
PC5
I/O TTa
I/O TTa
USART1_TX
ADC2_IN5
ADC2_IN11,OPAMP2_VINM,
OPAMP1_VINM
USART1_RX, TSC_G3_IO1
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Pinouts and pin description
STM32F302xx/STM32F303xx
Table 11. STM32F302xx/STM32F303xx pin definitions (continued)
Pin number
Pin functions
Pin name
(function
after
Alternate functions
Additional functions
reset)
ADC3_IN12(3), COMP4_INP,
TIM3_CH3, TIM1_CH2N,
35
26
18
PB0
I/O TTa
OPAMP3_VINP(3)
OPAMP2_VINP
,
TIM8_CH2N(3), TSC_G3_IO2
TIM3_CH4, TIM1_CH3N,
TIM8_CH3N(3), COMP4_OUT,
TSC_G3_IO3
ADC3_IN1(3)
,
36
37
27
28
19
20
PB1
PB2
I/O TTa
I/O TTa
OPAMP3_VOUT(3)
ADC2_IN12, COMP4_INM,
OPAMP3_VINM(3)
TSC_G3_IO4
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
38
39
40
41
42
43
44
45
46
PE7
PE8
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
I/O TTa
TIM1_ETR
ADC3_IN13(3), COMP4_INP
COMP4_INM, ADC34_IN6(3)
ADC3_IN2(3)
ADC3_IN14(3)
ADC3_IN15(3)
ADC3_IN16(3)
ADC3_IN3(3)
ADC4_IN1(3)
ADC4_IN2(3)
TIM1_CH1N
PE9
TIM1_CH1
PE10
PE11
PE12
PE13
PE14
PE15
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4, TIM1_BKIN2
USART3_RX, TIM1_BKIN
COMP5_INM(3)
,
USART3_TX, TIM2_CH3,
TSC_SYNC
47
29
30
21
22
PB10
I/O TTa
OPAMP4_VINM(3)
OPAMP3_VINM(3)
,
USART3_RX, TIM2_CH4,
TSC_G6_IO1
COMP6_INP,
48
PB11
I/O TTa
OPAMP4_VINP(3)
49
50
31
32
23
24
VSS_2
VDD_2
S
S
Digital ground
Digital power supply
SPI2_NSS, I2S2_WS(3)
,
I2C2_SMBA, USART3_CK,
TIM1_BKIN, TSC_G6_IO2
ADC4_IN3(3)
,
51
52
53
33
25
PB12
PB13
PB14
I/O TTa
I/O TTa
I/O TTa
COMP3_INM(3)
,
OPAMP4_VOUT(3)
,
ADC3_IN5(3)
,
SPI2_SCK, I2S2_CK(3)
USART3_CTS, TIM1_CH1N,
TSC_G6_IO3
,
COMP5_INP(3)
,
34
26
OPAMP4_VINP(3)
OPAMP3_VINP(3)
,
SPI2_MISO, I2S2ext_SD(3)
USART3_RTS, TIM1_CH2N,
TIM15_CH1, TSC_G6_IO4
SPI2_MOSI, I2S2_SD(3)
TIM1_CH3N, TIM15_CH1N,
TIM15_CH2
,
COMP3_INP(3)
,
35
36
27
28
ADC4_IN4(3), OPAMP2_VINP
,
ADC4_IN5(3), RTC_REFIN,
COMP6_INM
54
55
PB15
PD8
I/O TTa
I/O TTa
ADC4_IN12(3)
,
(1)
USART3_TX
OPAMP4_VINM(3)
(1)
(1)
56
57
PD9
I/O TTa
I/O TTa
USART3_RX
USART3_CK
ADC4_IN13(3)
ADC34_IN7(3), COMP6_INM
PD10
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Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Pinouts and pin description
Table 11. STM32F302xx/STM32F303xx pin definitions (continued)
Pin number
Pin functions
Pin name
(function
after
Alternate functions
Additional functions
reset)
ADC34_IN8(3), COMP6_INP,
OPAMP4_VINP(3)
(1)
(1)
(1)
58
PD11
PD12
PD13
I/O TTa
I/O TTa
I/O TTa
USART3_CTS
USART3_RTS, TIM4_CH1,
TSC_G8_IO1
ADC34_IN9(3)
,
59
60
COMP5_INP(3)
ADC34_IN10(3)
,
TIM4_CH2, TSC_G8_IO2
COMP5_INM(3)
COMP3_INP(3)
,
,
(1)
61
PD14
I/O TTa
TIM4_CH3, TSC_G8_IO3
ADC34_IN11(3)
OPAMP2_VINP
COMP3_INM(3)
SPI2_NSS, TIM4_CH4,
TSC_G8_IO4
(1)
(1)
(1)
(1)
(1)
62
63
64
65
66
PD15
PC6
PC7
PC8
PC9
I/O TTa
I/O FT
I/O FT
I/O FT
I/O FT
I2S2_MCK(3), COMP6_OUT,
37
38
39
40
TIM8_CH1(3), TIM3_CH1
I2S3_MCK(3), TIM8_CH2(3)
,
TIM3_CH2, COMP5_OUT(3)
TIM8_CH3(3), TIM3_CH3,
COMP3_OUT(3)
TIM8_CH4(3), TIM8_BKIN2(3)
TIM3_CH4, I2S_CKIN(3)
,
I2C2_SMBA, I2S2_MCK(3)
USART1_CK, TIM1_CH1,
TIM4_ETR, MCO,
,
67
68
69
70
71
41
42
43
44
29
30
31
32
PA8
PA9
I/O FT
I/O FTf
I/O FTf
I/O FT
I/O FT
COMP3_OUT(3)
I2C2_SCL, I2S3_MCK(3)
,
USART1_TX, TIM1_CH2,
TIM2_CH3, TIM15_BKIN,
TSC_G4_IO1, COMP5_OUT(3)
I2C2_SDA, USART1_RX,
TIM1_CH3, TIM2_CH4,
PA10
PA11
PA12
TIM8_BKIN(3), TIM17_BKIN,
TSC_G4_IO2, COMP6_OUT
USART1_CTS, USB_DM,
CAN_RX, TIM1_CH1N,
TIM1_CH4, TIM1_BKIN2,
TIM4_CH1, COMP1_OUT
USART1_RTS, USB_DP,
CAN_TX, TIM1_CH2N,
TIM1_ETR, TIM4_CH2,
TIM16_CH1, COMP2_OUT
45
46
33
34
USART3_CTS, TIM4_CH3,
TIM16_CH1N, TSC_G4_IO3,
IR_OUT, SWDIO-JTMS
72
73
PA13
PF6
I/O FT
I/O FTf
I2C2_SCL, USART3_RTS,
TIM4_CH4
(1)
Doc ID 023353 Rev 5
39/133
Pinouts and pin description
STM32F302xx/STM32F303xx
Additional functions
Table 11. STM32F302xx/STM32F303xx pin definitions (continued)
Pin number
Pin functions
Pin name
(function
after
Alternate functions
reset)
74
47
48
35
VSS_3
VDD_3
S
S
Ground
Digital power supply
75
36
I2C1_SDA, USART2_TX,
76
49
37
PA14
I/O FTf
TIM8_CH2(3), TIM1_BKIN,
TSC_G4_IO4, SWCLK-JTCK
I2C1_SCL, SPI1_NSS,
SPI3_NSS, I2S3_WS(3), JTDI,
USART2_RX, TIM1_BKIN,
TIM2_CH1_ETR, TIM8_CH1(3)
77
50
38
PA15
I/O FTf
SPI3_SCK, I2S3_CK(3)
,
(1)
(1)
(1)
78
79
80
51
52
53
PC10
PC11
PC12
I/O FT
I/O FT
I/O FT
USART3_TX, UART4_TX,
TIM8_CH1N(3)
SPI3_MISO, I2S3ext_SD(3)
USART3_RX, UART4_RX,
TIM8_CH2N(3)
,
SPI3_MOSI, I2S3_SD(3)
,
USART3_CK, UART5_TX,
TIM8_CH3N(3)
(1)
(1)
81
82
PD0
PD1
I/O FT
I/O FT
CAN_RX
CAN_TX, TIM8_CH4(3)
,
TIM8_BKIN2(3)
UART5_RX, TIM3_ETR,
TIM8_BKIN(3)
(1)
(1)
83
84
54
PD2
PD3
I/O FT
I/O FT
USART2_CTS,
TIM2_CH1_ETR
(1)
(1)
(1)
(1)
85
86
87
88
PD4
PD5
PD6
PD7
I/O FT
I/O FT
I/O FT
I/O FT
USART2_RTS, TIM2_CH2
USART2_TX
USART2_RX, TIM2_CH4
USART2_CK, TIM2_CH3
SPI3_SCK, I2S3_CK(3)
,
SPI1_SCK, USART2_TX,
TIM2_CH2, TIM3_ETR,
TIM4_ETR, TIM8_CH1N(3)
TSC_G5_IO1, JTDO-
TRACESWO
89
90
55
56
39
40
PB3
PB4
I/O FT
,
SPI3_MISO, I2S3ext_SD(3)
SPI1_MISO, USART2_RX,
TIM3_CH1, TIM16_CH1,
,
I/O FT
TIM17_BKIN, TIM8_CH2N(3)
TSC_G5_IO2, NJTRST
,
40/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Pinouts and pin description
Table 11. STM32F302xx/STM32F303xx pin definitions (continued)
Pin number
Pin functions
Pin name
(function
after
Alternate functions
Additional functions
reset)
SPI3_MOSI, SPI1_MOSI,
I2S3_SD(3), I2C1_SMBA,
USART2_CK, TIM16_BKIN,
91
57
58
41
PB5
PB6
I/O FT
TIM3_CH2, TIM8_CH3N(3)
TIM17_CH1
,
I2C1_SCL, USART1_TX,
TIM16_CH1N, TIM4_CH1,
92
42
I/O FTf
I/O FTf
TIM8_CH1(3), TSC_G5_IO3,
TIM8_ETR(3), TIM8_BKIN2(3)
I2C1_SDA, USART1_RX,
TIM3_CH4, TIM4_CH2,
93
94
95
59
60
61
43
44
45
PB7
BOOT0
PB8
TIM17_CH1N, TIM8_BKIN(3)
TSC_G5_IO4
,
I
B
Boot memory selection
I2C1_SCL, CAN_RX,
TIM16_CH1, TIM4_CH3,
TIM8_CH2(3), TIM1_BKIN,
TSC_SYNC, COMP1_OUT
I/O FTf
I2C1_SDA, CAN_TX,
TIM17_CH1, TIM4_CH4,
TIM8_CH3(3), IR_OUT,
COMP2_OUT
96
97
62
46
PB9
PE0
I/O FTf
I/O FT
USART1_TX, TIM4_ETR,
TIM16_CH1
(1)
(1)
98
99
PE1
I/O FT
USART1_RX, TIM17_CH1
63
64
47
48
VSS_1
VDD_1
S
S
Ground
Digital power supply
100
1. Function availability depends on the chosen device.
When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must
not be configured in analog mode.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the reference manual.
3. On STM32F303xx devices only.
Doc ID 023353 Rev 5
41/133
Table 12. Alternate functions for port A
Port
&
Pin
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF14
AF15
Name
TIM2_
CH1_
ETR
TSC_
G1_IO1
USART2 COMP1 TIM8_
TIM8_
ETR
EVENT
OUT
PA0
_CTS
_OUT
BKIN
TIM2_
CH2
TSC_
G1_IO2
USART2
_RTS
TIM15_
CH1N
EVENT
OUT
PA1
PA2
PA3
PA4
TIM2_
CH3
TSC_
G1_IO3
USART2 COMP2 TIM15_
_TX
EVENT
OUT
_OUT
CH1
TIM2_
CH4
TSC_
G1_IO4
USART2
_RX
TIM15_
CH2
EVENT
OUT
TIM3_ TSC_
CH2 G2_IO1
SPI1_ SPI3_NSS, USART2
EVENT
OUT
NSS
I2S3_WS
_CK
TIM2_
CH1_
ETR
TSC_
G2_IO2
SPI1_
SCK
EVENT
OUT
PA5
TIM16_ TIM3_ TSC_
CH1 CH1 G2_IO3 BKIN
TIM8_ SPI1_
COMP1
_OUT
EVENT
OUT
PA6
PA7
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH1N
MISO
TIM17_ TIM3_ TSC_
TIM8_ SPI1_
COMP2
_OUT
EVENT
OUT
CH1
CH2
G2_IO4 CH1N MOSI
I2C2_ I2S2_
SMBA MCK
USART1 COMP3
_CK _OUT
TIM4_
ETR
EVENT
OUT
PA8 MCO
PA9
TSC_
G4_IO1 SCL
I2C2_ I2S3_
MCK
USART1 COMP5 TIM15_ TIM2_
EVENT
OUT
_TX
_OUT
BKIN
CH3
TIM17_
BKIN
TSC_
G4_IO2 SDA
I2C2_
USART1 COMP6
_RX _OUT
TIM2_ TIM8_
CH4
EVENT
OUT
PA10
BKIN
USB_
DM
USART1 COMP1
TIM4_
CH1
TIM1_
BKIN2
EVENT
OUT
PA11
CAN_RX
TIM1_CH4
_CTS
_OUT
Table 12. Alternate functions for port A (continued)
Port
&
Pin
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF14
AF15
Name
TIM16_
CH1
USART1 COMP2
TIM4_
CH2
USB_
DP
EVENT
OUT
PA12
PA13
PA14
TIM1_CH2N
CAN_TX
TIM1_ETR
_RTS
_OUT
SWDIO TIM16_
-JTMS CH1N
TSC_
G4_IO3
IR_
OUT
USART3
_CTS
TIM4_
CH3
EVENT
OUT
SWCLK
-JTCK
TSC_
G4_IO4 SDA
I2C1_ TIM8_
USART2
_TX
EVENT
OUT
TIM1_BKIN
CH2
TIM2_
CH1_
ETR
TIM8_
CH1
I2C1_ SPI1_ SPI3_NSS, USART2
SCL NSS I2S3_WS _RX
TIM1_
BKIN
EVENT
OUT
PA15 JTDI
Table 13. Alternate functions for port B
Port
&
Pin
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
Name
TIM3_ TSC_
CH3 G3_IO2 CH2N
TIM8_
EVENT
OUT
PB0
PB1
PB2
TIM1_CH2N
TIM1_CH3N
TIM3_ TSC_ TIM8_
COMP4_
OUT
EVENT
OUT
CH4
G3_IO3 CH3N
TSC_
G3_IO4
EVENT
OUT
JTDO-
PB3 TRACES
WO
TIM2_ TIM4_ TSC_
TIM8_
SPI1_
SCK
SPI3_SCK,
I2S3_CK
USART2_
TX
TIM3_
ETR
EVENT
OUT
CH2
ETR
G5_IO1 CH1N
TIM16_ TIM3_ TSC_
TIM8_
SPI1_
MISO
SPI3_MISO, USART2_
I2S3ext_SD RX
TIM17_
BKIN
EVENT
OUT
PB4 NJTRST
PB5
CH1
CH1
G5_IO2 CH2N
TIM16_ TIM3_ TIM8_
BKIN CH2 CH3N
I2C1_
SMBA
SPI1_
MOSI
SPI3_MOSI, USART2_
TIM17_
CH1
EVENT
OUT
I2S3_SD
CK
TIM16_ TIM4_ TSC_
CH1N CH1 G5_IO3
TIM8_
ETR
USART1_
TX
TIM8_
BKIN2
EVENT
OUT
PB6
I2C1_SCL TIM8_CH1
TIM17_ TIM4_ TSC_
CH1N CH2 G5_IO4 SDA
I2C1_
TIM8_
BKIN
USART1_
RX
TIM3_
CH4
EVENT
OUT
PB7
TIM16_ TIM4_ TSC_
COMP1_
OUT
TIM8_
CH2
TIM1_ EVENT
PB8
I2C1_SCL
CAN_RX
CAN_TX
CH1
CH3
SYNC
BKIN
OUT
TIM17_ TIM4_
I2C1_
SDA
COMP2_
OUT
TIM8_
CH3
EVENT
OUT
PB9
IR_OUT
CH1
CH4
TIM2_
CH3
TSC_
SYNC
USART3_
TX
EVENT
OUT
PB10
PB11
PB12
TIM2_
CH4
TSC_
G6_IO1
USART3_
RX
EVENT
OUT
TSC_
G6_IO2 SMBA
I2C2_
SPI2_NSS,
I2S2_WS
TIM1_
BKIN
USART3_
CK
EVENT
OUT
Table 13. Alternate functions for port B (continued)
Port
&
Pin
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
Name
TSC_
G6_IO3
SPI2_SCK, TIM1_
I2S2_CK CH1N
USART3_
CTS
EVENT
OUT
PB13
PB14
PB15
TIM15_
CH1
TSC_
G6_IO4
SPI2_MISO, TIM1_
I2S2ext_SD CH2N
USART3_
RTS
EVENT
OUT
TIM15_ TIM15_
CH2 CH1N
TIM1_
CH3N
SPI2_MOSI,
I2S2_SD
EVENT
OUT
Table 14. Alternate functions for port C
Port &
Pin
AF1
AF2
AF3
AF4
AF5
AF6
AF7
Name
PC0
PC1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PC2
COMP7_OUT
TSC_G3_IO1
PC3
TIM1_BKIN2
PC4
USART1_TX
USART1_RX
COMP6_OUT
COMP5_OUT
COMP3_OUT
PC5
PC6
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
TIM8_CH1
TIM8_CH2
TIM8_CH3
TIM8_CH4
TIM8_CH1N
TIM8_CH2N
TIM8_CH3N
TIM1_CH1N
I2S2_MCK
I2S3_MCK
PC7
PC8
PC9
I2S_CKIN
TIM8_BKIN2
PC10
PC11
PC12
PC13
PC14
PC15
UART4_TX
UART4_RX
UART5_TX
SPI3_SCK, I2S3_CK
SPI3_MISO, I2S3ext_SD
SPI3_MOSI, I2S3_SD
USART3_TX
USART3_RX
USART3_CK
Table 15. Alternate functions for port D
Port &
AF1
AF2
AF3
AF4
AF5
AF6
AF7
CAN_RX
Pin Name
PD0
PD1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TIM8_CH4
TIM8_BKIN
TIM8_BKIN2
CAN_TX
PD2
TIM3_ETR
UART5_RX
PD3
TIM2_CH1_ETR
TIM2_CH2
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
PD4
PD5
PD6
TIM2_CH4
TIM2_CH3
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
SPI2_NSS
Table 16. Alternate functions for port E
Port &
AF0
AF1
AF2
TIM4_ETR
AF3
AF4
AF6
AF7
Pin Name
PE0
PE1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TIM16_CH1
TIM17_CH1
USART1_TX
USART1_RX
PE2
TRACECK
TRACED0
TRACED1
TRACED2
TRACED3
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
PE3
PE4
PE5
PE6
PE7
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
TIM1_BKIN2
USART3_RX
Table 17. Alternate functions for port F
Port &
AF1
AF2
AF3
AF4
AF5
AF6
AF7
Pin Name
PF0
PF1
PF2
PF4
PF6
PF9
PF10
I2C2_SDA
I2C2_SCL
TIM1_CH3N
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
COMP1_OUT
TIM4_CH4
I2C2_SCL
USART3_RTS
TIM15_CH1
TIM15_CH2
SPI2_SCK
SPI2_SCK
Memory mapping
STM32F302xx/STM32F303xx
5
Memory mapping
Figure 8.
STM32F30xB/C memory map
0x5000 07FF
AHB3
0xFFFF FFFF
0x5000 0000
Reserved
Cortex-M4F
Internal
Peripherals
7
0x4800 1800
0x4800 0000
AHB2
0xE000 0000
Reserved
AHB1
6
0x4002 43FF
0x4002 0000
0xC000 0000
Reserved
5
0x4001 6C00
0x4001 0000
APB2
Reserved
APB1
0xA000 0000
4
0x4000 A000
0x4000 0000
0x8000 0000
3
0x1FFF FFFF
0x1FFF F800
Option bytes
0x6000 0000
System memory
2
0x1FFF D800
0x1000 2000
Reserved
Peripherals
0x4000 0000
CCM RAM
0x1000 0000
0x0804 0000
Reserved
1
SRAM
CODE
0x2000 0000
Flash memory
0x0800 0000
0x0004 0000
0
Reserved
0x0000 0000
Flash, system memory
or SRAM, depending
on BOOT configuration
Reserved
0x0000 0000
MS30355V1
50/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Memory mapping
Table 18. STM32F30xB/C memory map and peripheral register boundary
addresses
Size
(bytes)
Bus
Boundary address
Peripheral
0x5000 0400 - 0x5000 07FF
0x5000 0000 - 0x5000 03FF
0x4800 1800 - 0x4FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0800 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
0x4001 4C00 - 0x4001 7FFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 0800 - 0x4001 2BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
1 K
1 K
ADC3 - ADC4
AHB3
ADC1 - ADC2
Reserved
GPIOF
~132 M
1 K
1 K
GPIOE
1 K
GPIOD
AHB2
1 K
GPIOC
1 K
GPIOB
1 K
GPIOA
~128 M
1 K
Reserved
TSC
3 K
Reserved
CRC
1 K
3 K
Reserved
Flash interface
Reserved
RCC
1 K
AHB1
3 K
1 K
2 K
Reserved
DMA2
1 K
1 K
DMA1
32 K
13 K
1 K
Reserved
Reserved
TIM17
1 K
TIM16
1 K
TIM15
1 K
Reserved
USART1
TIM8
1 K
APB2
1 K
1 K
SPI1
1 K
TIM1
9 K
Reserved
EXTI
1 K
1 K
SYSCFG + COMP + OPAMP
Doc ID 023353 Rev 5
51/133
Memory mapping
STM32F302xx/STM32F303xx
Table 18. STM32F30xB/C memory map and peripheral register boundary addresses
(continued)
Size
(bytes)
Bus
Boundary address
Peripheral
0x4000 8000 - 0x4000 FFFF
0x4000 7800 - 0x4000 7FFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1800 - 0x4000 27FF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
32 K
2 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
1 K
4 K
1 K
1 K
1 K
1 K
1 K
1 K
Reserved
Reserved
DAC (dual)
PWR
Reserved
Reserved
bxCAN
USB SRAM 512 bytes
USB device FS
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3/I2S3
SPI2/I2S2
I2S2ext
IWDG
APB1
WWDG
RTC
Reserved
TIM7
TIM6
Reserved
TIM4
TIM3
TIM2
52/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3.3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9.
Pin loading conditions
Figure 10. Pin input voltage
-#5 PIN
-#5 PIN
C = 50 pF
6
).
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-3ꢃꢅꢉꢃꢃ6ꢃ
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Electrical characteristics
STM32F302xx/STM32F303xx
6.1.6
Power supply scheme
Figure 11. Power supply scheme
V
BAT
Backup circuitry
Power switch
(LSE,RTC,
1.65 - 3.6V
Wake-up logic
Backup registers)
OUT
IN
IO
Logic
GP I/Os
Kernel logic
(CPU,
Digital
V
DD
& Memories)
4 ×
3 ×
V
V
DD
Regulator
4 × 100 nF
+ 1 × 4.7 μF
SS
V
DDA
V
DDA
V
REF
!NALOGꢍ 2#Sꢎ 0,,ꢎ
COMPARATORSꢎ /0!-0ꢎ ꢏꢏꢏꢏ
V
ADC/
DAC
REF+
10 nF
+ 1 μF
V
REF-
10 nF
+ 1 μF
V
SSA
MS19875V3
1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply
pins.
Caution:
Each power supply pair (V /V , V
/V
etc..) must be decoupled with filtering
DD SS
DDA SSA
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
54/133
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STM32F302xx/STM32F303xx
Electrical characteristics
6.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
)
?6
$$ "!4
6
"!4
)
$$
6
$$
)
$$!
6
$$!
-3ꢃꢅꢉꢃꢈ6ꢃ
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Electrical characteristics
STM32F302xx/STM32F303xx
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics,
Table 20: Current characteristics, and Table 21: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
(1)
Table 19. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDDA, VBAT
and VDD
VDD–VSS
-0.3
4.0
)
VDD–VDDA
REF+–VDDA
Allowed voltage difference for VDD > VDDA
Allowed voltage difference for VREF+ > VDDA
Input voltage on FT and FTf pins
-
0.4
0.4
(2)
V
-
V
VSS − 0.3
VDD + 4.0
4.0
(3)
VIN
Input voltage on TTa pins
VSS − 0.3
Input voltage on any other pin
VSS − 0.3
4.0
|ΔVDDx
|
Variations between different VDD power pins
Variations between all the different ground pins
-
-
50
mV
|VSSX − VSS
|
50
Electrostatic discharge voltage (human body
model)
see Section 6.3.12: Electrical
sensitivity characteristics
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range. The following relationship must be respected between VDDA and VDD
:
VDDA must power on before or at the same time as VDD in the power up sequence.
V
DDA must be greater than or equal to VDD.
2. VREF+ must be always lower or equal than VDDA (VREF+ ≤ VDDA). If unused then it must be connected to VDDA
.
3. VIN maximum must always be respected. Refer to Table 20: Current characteristics for the maximum allowed injected
current values.
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Electrical characteristics
Table 20. Current characteristics
Symbol
Ratings
Max.
Unit
IVDD(Σ)
IVSS(Σ)
IVDD
Total current into sum of all VDD_x power lines (source)
Total current out of sum of all VSS_x ground lines (sink)
Maximum current into each VDD_x power line (source)(1)
Maximum current out of each VSS _x ground line (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/O and control pin
Total output current sunk by sum of all IOs and control pins(2)
Total output current sourced by sum of all IOs and control pins(2)
Injected current on FT, FTf and B pins(3)
160
− 160
100
− 100
25
IVSS
IIO(PIN)
− 25
80
mA
ΣIIO(PIN)
− 80
-5/+0
5
IINJ(PIN)
Injected current on TC and RST pin(4)
Injected current on TTa pins(5)
5
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(6)
25
1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in
the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 19: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 19: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note (2) below Table 68.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 21. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
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Electrical characteristics
STM32F302xx/STM32F303xx
6.3
Operating conditions
6.3.1
General operating conditions
Table 22. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK1
fPCLK2
VDD
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
0
0
0
2
72
36
72
3.6
MHz
V
Analog operating voltage
(OPAMP and DAC not used)
2
3.6
Must have a potential
equal to or higher than
VDD
VDDA
V
V
Analog operating voltage
(OPAMP and DAC used)
2.4
3.6
3.6
VBAT
Backup operating voltage
1.65
TC I/O
–0.3 VDD+0.3
TTa I/O
–0.3
V
DDA+0.3
VIN
I/O input voltage
V
FT and FTf I/O(1)
–0.3
5.5
BOOT0
0
-
5.5
LQFP100
LQFP64
488
Power dissipation at TA =
85 °C for suffix 6 or TA =
105 °C for suffix 7(2)
PD
-
444
mW
°C
LQFP48
-
364
Maximum power
dissipation
–40
–40
–40
85
Ambient temperature for 6
suffix version
Low power dissipation(3)
105
105
TA
TJ
Maximum power
dissipation
Ambient temperature for 7
suffix version
°C
°C
Low power dissipation(3)
–40
–40
–40
125
105
125
6 suffix version
Junction temperature range
7 suffix version
1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 21: Thermal
characteristics).
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 21: Thermal characteristics).
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Electrical characteristics
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 23 are derived from tests performed under the ambient
temperature condition summarized in Table 22.
Table 23. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
0
∞
∞
∞
∞
tVDD
VDD fall time rate
20
0
µs/V
VDDA rise time rate
VDDA fall time rate
tVDDA
20
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 24 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22.
DD
Table 24. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
1.8(2)
Falling edge
Rising edge
1.88 1.96
V
V
Power on/power down
reset threshold
(1)
VPOR/PDR
1.84 1.92 2.0
(1)
VPDRhyst
PDR hysteresis
-
40
-
mV
POR reset
temporization
(3)
tRSTTEMPO
1.5
2.5
4.5
ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD
.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production
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Electrical characteristics
STM32F302xx/STM32F303xx
Table 25. Programmable voltage detector characteristics
Symbol
Parameter
Conditions
Rising edge
Min(1)
Typ Max(1) Unit
2.1
2
2.18
2.08
2.28
2.18
2.38
2.28
2.48
2.38
2.58
2.48
2.68
2.58
2.78
2.68
2.88
2.78
100
2.26
2.16
2.37
2.27
2.48
2.38
2.58
2.48
2.69
2.59
2.79
2.69
2.9
VPVD0
PVD threshold 0
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.19
2.09
2.28
2.18
2.38
2.28
2.47
2.37
2.57
2.47
2.66
2.56
2.76
2.66
-
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
VPVD7
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
V
2.8
3
PVD threshold 7
PVD hysteresis
2.9
(2)
VPVDhyst
-
mV
µA
PVD current
consumption
IDD(PVD)
-
0.15
0.26
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 26 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22.
DD
Table 26. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C 1.16
–40 °C < TA < +85 °C 1.16
1.2
1.25
V
V
Internal reference voltage
V
REFINT
1.2 1.24(1)
ADC sampling time when
reading the internal
reference voltage
TS_vrefint
2.2
-
-
µs
Internal reference voltage
spread over the
temperature range
10(2)
VRERINT
VDD = 3 V 10 mV
-
-
-
-
mV
100(2)
TCoeff
Temperature coefficient
ppm/°C
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Electrical characteristics
1. Data based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production
Table 27. Internal reference voltage calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 30 °C
VREFINT_CAL
0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f frequency (0 wait state from 0
HCLK
to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
●
●
●
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f
= f
and f
= f
PCLK2
HCLK
PCLK1 HCLK/2
When f
> 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HCLK
HSE (8 MHz) in bypass mode.
The parameters given in Table 28 to Table 32 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 22.
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Electrical characteristics
STM32F302xx/STM32F303xx
Table 28. Typical and maximum current consumption from V supply at V = 3.6V
DD
DD
All peripherals enabled
All peripherals disabled
(1)
(1)
Symbol Parameter Conditions fHCLK
Max @ TA
Max @ TA
Unit
Typ
Typ
25 °C 85 °C 105 °C
25 °C 85 °C 105 °C
72 MHz 61.2 65.8
67.6
60.2
46.2
32.5
24.4
8.6
68.5
61.1
47.2
32.7
25.2
9.4
27.8 30.3
24.6 27.2
19.2 21.1
12.9 14.6
10.0 11.4
30.7
27.6
21.4
14.8
11.4
4.4
31.5
28.3
21.8
15.3
12.1
5.0
64 MHz 54.7 59.1
48 MHz 41.7 45.1
External
clock (HSE 32 MHz 28.1 31.5
bypass)
24 MHz 21.4 23.7
Supply
current in
Run mode,
executing
from Flash
8 MHz
1 MHz
7.4
1.3
8.4
1.6
3.6
0.8
4.1
1.0
1.8
2.6
1.2
2.1
64 MHz 49.7 54.4
48 MHz 37.9 42.2
32 MHz 25.8 29.2
24 MHz 19.7 22.3
55.4
43.0
29.2
22.6
8.3
56.3
43.5
30.0
23.2
8.8
24.5 27.2
18.9 21.4
12.7 14.2
27.4
21.5
14.6
7.9
28.1
21.6
15.2
8.5
Internal
clock (HSI)
6.7
7.7
8 MHz
6.9
7.8
3.5
4.0
4.4
5.0
IDD
mA
72 MHz 60.8 66.2(2) 69.7 70.4(2) 27.4 31.7(2) 32.2 32.5(2)
64 MHz 54.3 59.1
48 MHz 41.0 45.6
62.2
47.3
32.4
24.3
8.7
63.3
47.9
32.9
25.0
9.0
24.3 28.3
18.3 21.6
12.3 15.0
28.7
21.9
15.2
11.4
4.2
28.8
22.1
15.4
12.0
4.9
External
clock (HSE 32 MHz 27.6 32.4
bypass)
24 MHz 20.8 23.9
9.3
3.1
0.4
11.3
3.7
Supply
current in
Run mode,
executing
from RAM
8 MHz
1 MHz
6.9
0.9
7.8
1.2
1.5
2.3
0.6
1.0
1.8
64 MHz 49.2 53.9
48 MHz 37.3 40.8
32 MHz 25.1 27.6
24 MHz 19.0 21.6
55.2
41.4
29.1
22.1
7.9
57.4
44.1
30.1
22.9
8.4
23.9 27.8
18.2 21.0
12.0 14.0
28.2
21.6
14.5
7.7
28.4
21.9
15.1
8.1
Internal
clock (HSI)
6.3
3.0
7.2
3.5
8 MHz
6.4
7.3
4.0
4.7
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Electrical characteristics
Table 28. Typical and maximum current consumption from V supply at V = 3.6V
DD
DD
All peripherals enabled
All peripherals disabled
(1)
(1)
Symbol Parameter Conditions fHCLK
Max @ TA
Max @ TA
Unit
Typ
Typ
25 °C 85 °C 105 °C
25 °C 85 °C 105 °C
72 MHz 44.0 48.4
49.4
44.0
33.3
23.3
17.8
6.1
50.5
45.2
34.3
23.5
18.3
6.9
6.6
6.0
4.5
3.1
2.4
0.8
0.1
5.7
4.3
2.9
1.5
0.7
7.5
6.8
5.2
3.5
2.8
1.0
0.3
6.3
4.8
3.2
1.8
0.9
7.9
7.2
5.6
4.0
3.3
1.4
0.6
6.8
5.2
3.7
2.2
1.2
8.7
7.9
6.3
4.8
3.9
2.2
1.5
7.5
5.9
4.5
2.9
2.1
64 MHz 39.2 43.3
48 MHz 29.6 32.7
External
clock (HSE 32 MHz 19.7 23.3
Supply
current in
Sleep
bypass)
24 MHz 14.9 17.6
8 MHz
1 MHz
4.9
0.6
5.7
0.9
IDD
mode,
mA
1.2
2.1
executing
from Flash
or RAM
64 MHz 34.2 38.1
48 MHz 25.8 28.7
32 MHz 17.4 19.4
24 MHz 13.2 15.1
39.2
29.6
19.9
15.6
5.6
40.3
30.3
20.7
15.9
6.2
Internal
clock (HSI)
8 MHz
4.5
5.0
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production with code executing from RAM.
Table 29. Typical and maximum current consumption from the V
supply
DDA
V
= 2.4 V
V
= 3.6 V
DDA
DDA
Conditions
(2)
(2)
Symbol Parameter
fHCLK
Max @ TA
25 °C 85 °C 105 °C
Max @ TA
25 °C 85 °C 105 °C
Unit
(1)
Typ
Typ
72 MHz 225
64 MHz 198
48 MHz 149
32 MHz 102
24 MHz 80
276
249
195
145
119
3
289
261
204
152
124
4
297
268
211
157
128
6
245
216
159
110
86
302
270
209
154
126
4
319
284
222
162
131
5
329
293
230
169
135
9
HSE
bypass
Supply
current in
Run mode,
8 MHz
1 MHz
2
2
3
IDDA
code
µA
3
5
7
3
4
6
9
executing
from Flash
or RAM
64 MHz 270
48 MHz 220
323
269
218
194
97
337
280
228
200
99
344
286
233
204
103
299
244
193
169
88
354
293
239
211
105
371
309
251
219
110
381
318
257
225
116
HSI clock 32 MHz 173
24 MHz 151
8 MHz
73
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Electrical characteristics
STM32F302xx/STM32F303xx
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
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Electrical characteristics
Table 30. Typical and maximum V consumption in Stop and Standby modes
DD
Typ @VDD (VDD=VDDA
)
Max(1)
Symbol Parameter
Conditions
Unit
TA = TA = TA =
25 °C 85 °C 105 °C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in run mode,
all oscillators OFF
20.05 20.33 20.42 20.50 20.67 20.80 44.2(2) 553 1202(2)
7.63 7.77 7.90 8.07 8.17 8.33 30.6(2) 529 1156(2)
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators OFF
IDD
µA
Supply
current in
Standby
mode
LSI ON and IWDG ON
0.80 0.96 1.09 1.23 1.37 1.51
-
-
-
LSI OFF and IWDG OFF 0.60 0.74 0.83 0.93 1.02 1.11 5.0(2) 7.8 13.3(2)
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production.
Table 31. Typical and maximum V
consumption in Stop and Standby modes
DDA
Typ @VDD (VDD = VDDA
)
Max(1)
Symbol Parameter
Conditions
Unit
TA = TA = TA =
25 °C 85 °C 105 °C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in run mode,
all oscillators OFF
1.81 1.95 2.07 2.20 2.35 2.52 3.7
1.81 1.95 2.07 2.20 2.35 2.52 3.7
5.5
5.5
8.8
8.8
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators
OFF
Supply
LSI ON and IWDG ON 2.22 2.42 2.59 2.78 3.0 3.24
-
-
-
current in
Standby
mode
LSI OFF and IWDG
OFF
1.69 1.82 1.94 2.08 2.23 2.40 3.5
5.4
9.2
IDDA
µA
Regulator in run mode,
all oscillators OFF
1.05 1.08 1.10 1.15 1.22 1.29
1.05 1.08 1.10 1.15 1.22 1.29
-
-
-
-
-
-
Supply
current in
Stop mode
Regulator in low-power
mode, all oscillators
OFF
Supply
current in
Standby
mode
LSI ON and IWDG ON 1.44 1.52 1.60 1.71 1.84 1.98
-
-
-
-
-
-
LSI OFF and IWDG
0.93 0.95 0.98 1.02 1.08 1.15
OFF
1. Data based on characterization results, not tested in production.
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Electrical characteristics
STM32F302xx/STM32F303xx
Table 32. Typical and maximum current consumption from V
supply
BAT
Max
Typ @VBAT
@VBAT = 3.6 V(2)
Para Conditions
meter
Symbol
Unit
(1)
TA = TA = TA =
25°C 85°C 105°C
1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V
LSE & RTC
ON; "Xtal
mode"lower
driving
capability;
LSEDRV[1:
0] = '00'
0.48 0.50 0.52 0.58 0.65 0.72 0.80 0.90 1.1
1.5
2.2
2.0
2.9
Backup
domain
supply
current
IDD_VBAT
µA
LSE & RTC
ON; "Xtal
mode"
higher
driving
0.83 0.86 0.90 0.98 1.03 1.10 1.20 1.30 1.5
capability;
LSEDRV[1:
0] = '11'
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Data based on characterization results, not tested in production.
Figure 13. Typical V
current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’)
BAT
ꢃꢏꢀ
ꢃꢏꢉ
ꢃ
ꢃꢏꢂꢇ 6
ꢃꢏꢁ 6
ꢉ 6
ꢄꢏꢁ
ꢄꢏꢂ
ꢄꢏꢀ
ꢄꢏꢉ
ꢄ
ꢉꢏꢀ 6
ꢉꢏꢆ 6
ꢈ 6
ꢈꢏꢈ 6
ꢈꢏꢂ 6
ꢉꢇ #
ꢂꢄ #
ꢁꢇ #
ꢃꢄꢇ #
ꢀ #ꢁ
4!
-3ꢈꢃꢃꢉꢀ6ꢃ
66/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
Typical current consumption
The MCU is placed under the following conditions:
●
●
●
V
= V
= 3.3 V
DDA
DD
All I/O pins available on each package are in analog input configuration
The Flash access time is adjusted to f frequency (0 wait states from 0 to 24 MHz,
HCLK
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash
prefetch is ON
●
●
●
When the peripherals are enabled, f
= f
, f
= f
APB1
AHB/2 APB2 AHB
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
Table 33. Typical current consumption in Run mode, code with data processing running from
Flash
Typ
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals
enabled
Peripherals
disabled
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
61.3
54.8
41.9
28.5
21.8
14.9
7.7
28.0
25.4
19.3
13.3
10.4
7.2
Supply current in
Run mode from
VDD supply
IDD
mA
3.9
4 MHz
4.5
2.5
2 MHz
2.8
1.7
1 MHz
1.9
1.3
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
1.4
1.1
Running from HSE
crystal clock 8 MHz,
code executing from
Flash
1.1
0.9
240.3
210.9
155.8
105.7
82.1
58.8
2.4
239.5
210.3
155.6
105.6
82.0
58.8
2.4
Supply current in
Run mode from
VDDA supply
(1) (2)
IDDA
µA
4 MHz
2.4
2.4
2 MHz
2.4
2.4
1 MHz
2.4
2.4
500 kHz
125 kHz
2.4
2.4
2.4
2.4
1. VDDA monitoring is ON.
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Electrical characteristics
STM32F302xx/STM32F303xx
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
Table 34. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals
enabled
Peripherals
disabled
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
44.1
39.7
30.3
20.5
15.4
10.6
5.4
7.0
6.3
4.9
3.5
2.8
Supply current in
Sleep mode from
VDD supply
2.0
IDD
mA
1.1
4 MHz
3.2
1.0
2 MHz
2.1
0.9
1 MHz
1.5
0.8
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
1.2
0.8
Running from HSE
crystal clock 8 MHz,
code executing from
Flash or RAM
1.0
0.8
239.7
210.5
155.0
105.3
81.9
58.7
2.4
238.5
209.6
155.6
105.2
81.8
58.6
2.4
Supply current in
Sleep mode from
VDDA supply
(1) (2)
IDDA
µA
4 MHz
2.4
2.4
2 MHz
2.4
2.4
1 MHz
2.4
2.4
500 kHz
125 kHz
2.4
2.4
2.4
2.4
1. VDDA monitoring is ON
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
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Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 52: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (seeTable 36: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
+C
S
INT
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
STM32F302xx/STM32F303xx
Table 35. Switching output I/O current consumption
I/O toggling
frequency (fSW
Symbol
Parameter
Conditions(1)
Typ
Unit
)
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
48 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
48 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
0.90
0.93
1.16
1.60
2.51
2.97
0.93
1.06
1.47
2.26
3.39
5.99
1.03
1.30
1.79
3.01
5.99
1.10
1.31
2.06
3.47
8.35
1.20
1.54
2.46
4.51
9.98
V
DD = 3.3 V
Cext = 0 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
Cext = 10 pF
C = CINT + CEXT +CS
I/O current
consumption
ISW
mA
VDD = 3.3 V
Cext = 22 pF
C = CINT + CEXT +CS
VDD = 3.3 V
Cext = 33 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
Cext = 47 pF
C = CINT + CEXT+ CS
1. CS = 5 pF (estimated value).
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STM32F302xx/STM32F303xx
Electrical characteristics
On-chip peripheral current consumption
The MCU is placed under the following conditions:
●
●
●
all I/O pins are in analog input configuration
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
●
ambient operating temperature at 25°C and V = V
= 3.3 V.
DD
DDA
Table 36. Peripheral current consumption
(1)
Typical consumption
IDD
Unit
Peripheral
BusMatrix (2)
DMA1
5.6
15.3
12.5
2.1
DMA2
CRC
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
TSC
10.0
10.3
2.2
8.8
3.3
3.0
5.5
ADC1&2
ADC3&4
APB2-Bridge (3)
SYSCFG
TIM1
17.3
18.8
3.6
µA/MHz
7.3
40.0
8.8
SPI1
TIM8
36.4
23.3
17.1
10.1
11.0
6.1
USART1
TIM15
TIM16
TIM17
APB1-Bridge (3)
TIM2
49.1
38.8
38.3
TIM3
TIM4
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Electrical characteristics
Table 36. Peripheral current consumption (continued)
STM32F302xx/STM32F303xx
(1)
Typical consumption
IDD
Peripheral
Unit
TIM6
TIM7
9.7
12.1
6.4
WWDG
SPI2
40.4
40.0
41.9
40.2
36.5
30.8
10.5
10.4
26.2
33.4
5.7
SPI3
USART2
USART3
UART4
UART5
I2C1
µA/MHz
I2C2
USB
CAN
PWR
DAC
15.4
1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp
etc. is not included. Refer to the tables of characteristics in the subsequent sections.
2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
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STM32F302xx/STM32F303xx
Electrical characteristics
6.3.6
Wakeup time from low-power mode
The wakeup times given in Table 37 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
●
For Stop or Sleep mode: the wakeup event is WFE.
●
WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 22.
Table 37. Low-power mode wakeup timings
Typ @VDD, VDD = VDDA
Symbol
Parameter
Conditions
Max Unit
2.0 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
Regulator in
run mode
4.1
3.9
3.8
3.7
3.6
3.5
4.5
Wakeup from
Stop mode
tWUSTOP
Regulator in
low power
mode
7.9
6.7
6.1
5.7
5.4
5.2
50
9
100
-
µs
Wakeup from LSI and
Standby mode IWDG OFF
(1)
tWUSTANDBY
69.2
60.3
56.4
53.7
51.7
CPU
clock
Wakeup from
Sleep mode
tWUSLEEP
6
cycles
1. Data based on characterization results, not tested in production.
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Electrical characteristics
STM32F302xx/STM32F303xx
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 14.
Table 38. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fHSE_ext
1
8
32
MHz
VHSEH
VHSEL
tw(HSEH)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
15
-
-
-
-
tw(HSEL)
ns
tr(HSE)
tf(HSE)
20
1. Guaranteed by design, not tested in production.
Figure 14. High-speed external clock source AC timing diagram
T
7ꢐ(3%(ꢑ
6
(3%(
ꢅꢄꢒ
ꢃꢄꢒ
6
(3%,
T
T
T
Rꢐ(3%ꢑ
T
7ꢐ(3%,ꢑ
Fꢐ(3%ꢑ
4
(3%
-3ꢃꢅꢉꢃꢀ6ꢉ
74/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 15
Table 39. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSEH)
0.7VDD
VSS
450
-
-
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level
voltage
OSC32_IN high or low time(1)
OSC32_IN rise or fall time(1)
tw(LSEL)
ns
tr(LSE)
tf(LSE)
50
1. Guaranteed by design, not tested in production.
Figure 15. Low-speed external clock source AC timing diagram
T
7ꢐ,3%(ꢑ
6
,3%(
ꢅꢄꢒ
ꢃꢄꢒ
6
,3%,
T
T
T
Rꢐ,3%ꢑ
Fꢐ,3%ꢑ
T
7ꢐ,3%,ꢑ
4
,3%
-3ꢃꢅꢉꢃꢇ6ꢉ
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 40. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 40. HSE oscillator characteristics
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency
4
-
8
200
-
32
MHz
RF
Feedback resistor
kΩ
During startup(3)
-
8.5
-
V
DD=3.3 V, Rm= 30Ω,
CL=10 pF@8 MHz
-
-
-
-
-
0.4
0.5
0.8
1
VDD=3.3 V, Rm= 45Ω,
CL=10 pF@8 MHz
-
-
-
-
IDD
HSE current consumption
mA
VDD=3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz
VDD=3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz
V
DD=3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz
1.5
gm
Oscillator transconductance
Startup time
Startup
10
-
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
76/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 16. Typical application with an 8 MHz crystal
2ESONATOR WITH
INTEGRATED CAPACITORS
#
,ꢃ
F
/3#?).
(3%
"IAS
CONTROLLED
GAIN
ꢁ -(Z
RESONATOR
2
&
/3#?/54
ꢐꢃꢑ
2
%84
#
,ꢉ
-3ꢃꢅꢁꢆꢂ6ꢃ
1. REXT value depends on the crystal characteristics.
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 41. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(1)
Min(2)
Typ Max(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
0.5
0.9
1
LSEDRV[1:0]=01
medium low driving capability
-
-
-
-
-
-
-
-
IDD
LSE current consumption
µA
LSEDRV[1:0]=10
medium high driving capability
1.3
1.6
-
LSEDRV[1:0]=11
higher driving capability
-
LSEDRV[1:0]=00
lower driving capability
5
8
15
LSEDRV[1:0]=01
medium low driving capability
-
Oscillator
transconductance
gm
µA/V
LSEDRV[1:0]=10
medium high driving capability
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
-
-
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
78/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Figure 17. Typical application with a 32.768 kHz crystal
Electrical characteristics
2ESONATOR WITH
INTEGRATED CAPACITORS
#
,ꢃ
F
/3#ꢈꢉ?).
,3%
$RIVE
PROGRAMMABLE
AMPLIFIER
ꢈꢉꢏꢆꢂꢁ K(Z
RESONATOR
/3#ꢈꢉ?/54
#
,ꢉ
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
6.3.8
Internal clock source characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22.
High-speed internal (HSI) RC oscillator
(1)
Table 42. HSI oscillator characteristics
Symbol
Parameter
Frequency
HSI user trimming step
Conditions
Min
Typ
Max
Unit
fHSI
-
-
8
-
-
-
-
-
-
-
MHz
%
TRIM
1(2)
55(2)
4.6(3)
2.9(3)
-
DuCy(HSI) Duty cycle
45(2)
–3.8(3)
–2.9(3)
-
%
TA = –40 to 105 °C
TA = –10 to 85 °C
TA = 0 to 70 °C
TA = 25 °C
%
Accuracy of the HSI
oscillator (factory
calibrated)
%
ACCHSI
%
–1
1
%
HSI oscillator startup
time
tsu(HSI)
1(2)
-
2(2)
µs
HSI oscillator power
consumption
IDD(HSI)
-
80
100(3)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 18. HSI oscillator accuracy characterization results
!##
(3)
ꢇꢒ
ꢀꢒ
ꢈꢒ
ꢉꢒ
ꢃꢒ
ꢄꢒ
-!8
-).
4! ; #=
ꢋꢀꢄ
ꢋꢉꢄ
ꢄ
ꢉꢄ
ꢀꢄ
ꢂꢄ
ꢁꢄ
ꢃꢄꢄ
ꢃꢉꢄ
ꢋꢃꢒ
ꢋꢉꢒ
ꢋꢈꢒ
ꢋꢀꢒ
ꢋꢇꢒ
-3ꢈꢄꢅꢁꢇ6ꢉ
1. The above curves are based on characterisation results, not tested in production
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STM32F302xx/STM32F303xx
Electrical characteristics
Low-speed internal (LSI) RC oscillator
(1)
Table 43. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI
Frequency
30
-
40
-
50
85
kHz
µs
(2)
tsu(LSI)
LSI oscillator startup time
(2)
IDD(LSI)
LSI oscillator power consumption
-
0.75
1.2
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 44 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22.
Table 44. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max
PLL input clock(1)
1(2)
40(2)
16(2)
-
-
-
-
-
-
24(2)
60(2)
72
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
fPLL_OUT
tLOCK
MHz
µs
200(2)
300(2)
Jitter
Cycle-to-cycle jitter
-
ps
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
2. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F302xx/STM32F303xx
6.3.10
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
Table 45. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
16-bit programming time TA = –40 to +105 °C
40
20
20
-
53.5
60
40
40
10
12
µs
ms
ms
mA
mA
tERASE Page (2 KB) erase time TA = –40 to +105 °C
-
-
-
-
tME
Mass erase time
TA = –40 to +105 °C
Write mode
IDD
Supply current
Erase mode
-
1. Guaranteed by design, not tested in production.
Table 46. Flash memory endurance and data retention
Value
Min(1)
Symbol
Parameter
Conditions
Unit
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND
Endurance
10
kcycles
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
10 kcycles(2) at TA = 55 °C
30
10
20
tRET
Data retention
Years
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
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Electrical characteristics
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 47. They are based on the EMS levels and classes
defined in application note AN1709.
Table 47. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 72 MHz
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
3B
4A
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
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Electrical characteristics
Prequalification trials
STM32F302xx/STM32F303xx
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 48. EMI characteristics
Max vs. [fHSE/fHCLK
8/72 MHz
]
Monitored
frequency band
Symbol Parameter
Conditions
Unit
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
7
20
27
4
VDD = 3.3 V, TA = 25 °C,
LQFP100 package
compliant with IEC
61967-2
dBµV
-
SEMI
Peak level
6.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 49. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
Electrostatic discharge
TA = +25 °C, conforming
V
2
II
2000
500
ESD(HBM) voltage (human body model) to JESD22-A114
V
Electrostatic discharge
TA = +25 °C, conforming
V
ESD(CDM) voltage (charge device model) to JESD22-C101
1. Data based on characterization results, not tested in production.
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Static latch-up
Electrical characteristics
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
●
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 50. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
6.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator
frequency deviation).
The test results are given in Table 51
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Electrical characteristics
STM32F302xx/STM32F303xx
Table 51. I/O current injection susceptibility
Functionalsusceptibility
Unit
Symbol
Description
Negative
injection
Positive
injection
Injected current on BOOT0
– 0
NA
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5,
PB2 with induced leakage current on other pins from this
group less than -50 µA
– 5
-
Injected current on PB0, PB1, PE7, PE8, PE9, PE10,
PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14,
PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with
induced leakage current on other pins from this group
less than -50 µA
– 5
-
IINJ
mA
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5,
PB2, PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12,
PE13, PE14, PE15, PB12, PB13, PB14, PB15, PD8,
PD9, PD10, PD11, PD12, PD13, PD14 with induced
leakage current on other pins from this group less than
400 µA
-
+5
Injected current on any other FT and FTf pins
Injected current on any other pins
– 5
– 5
NA
+5
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
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Electrical characteristics
6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under the conditions summarized in Table 22. All I/Os are CMOS and TTL
compliant.
Table 52. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
0.3 VDD+0.07 (1)
0.475 VDD-0.2 (1)
0.3 VDD–0.3 (1)
-
-
Low level input
voltage
VIL
-
-
(2)
All I/Os except BOOT0
TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
0.3 VDD
V
0.445 VDD+0.398 (1)
0.5 VDD+0.2 (1)
0.2 VDD+0.95 (1)
-
-
-
-
-
-
-
-
-
High level input
voltage
VIH
-
(2)
All I/Os except BOOT0
TC and TTa I/O
FT and FTf I/O
BOOT0
0.7 VDD
-
-
-
-
200 (1)
100 (1)
300 (1)
Schmitt trigger
hysteresis
Vhys
mV
TC, FT and FTf I/O
TTa I/O in digital mode
VSS ≤ VIN ≤ VDD
-
-
0.1
TTa I/O in digital mode
-
-
-
-
1
Input leakage
current (3)
VDD ≤ VIN ≤ VDDA
Ilkg
µA
TTa I/O in analog mode
0.2
10
55
VSS ≤ VIN ≤ VDDA
FT and FTf I/O(4)
-
-
VDD ≤ VIN ≤ 5 V
Weak pull-up
RPU
VIN = VSS
VIN = VDD
25
40
kΩ
equivalent resistor(5)
Weak pull-down
RPD
CIO
25
-
40
5
55
-
kΩ
equivalent resistor(5)
I/O pin capacitance
pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 51: I/O
current injection susceptibility.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 19 and Figure 20 for standard I/Os.
Figure 19. TC and TTa I/O input characteristics - CMOS port
VIL/VIH (V)
+0.398
= 0.445V
V
VIHmin 2.0
+0.07
= 0.3V
V
1.3
Area not determined
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30255V2
Figure 20. TC and TTa I/O input characteristics - TTL port
VIL/VIH (V)
+0.398
TTL standard requirements VIHmin = 2 V
= 0.445V
= 0.3V
V
VIHmin 2.0
1.3
+0.07
V
Area not determined
VILmax 0.8
0.7
TTL standard requirements VILmax = 0.8 V
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30256V2
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
VIL/VIH (V)
+0.2
= 0.5V
V
V
2.0
-0.2
= 0.475V
Area not determined
1.0
CMOS standard requirements VILmax = 0.3VDD
0.5
VDD (V)
2.0
3.6
MS30257V2
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Electrical characteristics
Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port
VIL/VIH (V)
+0.2
TTL standard requirements VIHmin = 2 V
Area not determined
= 0.5V
V
V
2.0
-0.2
= 0.475V
1.0
0.8
TTL standard requirements VILmax = 0.8 V
0.5
VDD (V)
2.0
2.7
3.6
MS30258V2
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Electrical characteristics
STM32F302xx/STM32F303xx
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed V ).
V
OL/ OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
●
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
IVDD(Σ) (see Table 20).
●
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
IVSS(Σ) (see Table 20).
Output voltage levels
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 22. All I/Os (FT, TTa and Tc unless otherwise specified) are CMOS and TTL
compliant.
Table 53. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
0.4
-
Unit
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
(1)
(3)
VOH
VDD–0.4
VOL
TTL port(2)
IIO =+ 8mA
2.7 V < VDD < 3.6 V
-
0.4
-
(1)
(3)
VOH
2.4
(1)(4)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3
-
V
I
IO = +20 mA
(3)(4)
2.7 V < VDD < 3.6 V
VOH
VDD–1.3
-
(1)(4)
VOL
0.4
-
I
IO = +6 mA
(3)(4)
2 V < VDD < 2.7 V
VOH
VDD–0.4
Output low level voltage for an FTf I/O pin in
FM+ mode
IIO = +20 mA
2.7 V < VDD < 3.6 V
(1)(4)
VOLFM+
-
0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 20 and the sum of
IIO (I/O ports and control pins) must not exceed ΣIIO(PIN)
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 20 and the sum
of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN)
.
4. Data based on design simulation.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 23 and
Table 54, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 22.
DD
(1)
Table 54. I/O AC characteristics
OSPEEDRy[1:0]
value(1)
Symbol
Parameter
Conditions
Min Max Unit
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 V to 3.6 V
-
-
2(3) MHz
Output high to low level fall
tf(IO)out
time
125(3)
ns
125(3)
x0
01
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
CL = 50 pF, VDD = 2 V to 3.6 V
Output low to high level
rise time
tr(IO)out
-
-
-
fmax(IO)out Maximum frequency(2)
10(3) MHz
Output high to low level fall
tf(IO)out
time
25(3)
ns
Output low to high level
rise time
tr(IO)out
-
25(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
-
-
-
-
-
-
-
-
-
-
50(3) MHz
30(3) MHz
20(3) MHz
5(3)
fmax(IO)out Maximum frequency(2)
Output high to low level fall
11
tf(IO)out
time
8(3)
12(3)
ns
5(3)
Output low to high level
rise time
tr(IO)out
8(3)
12(3)
fmax(IO)out Maximum frequency(2)
2(4) MHz
Output high to low level fall
FM+
tf(IO)out
time
-
-
12(4)
CL = 50 pF, VDD = 2 V to 3.6 V
configuration(4)
ns
Output low to high level
rise time
tr(IO)out
34(4)
Pulse width of external
signals detected by the
EXTI controller
-
tEXTIpw
10(3)
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0316 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 23.
3. Guaranteed by design, not tested in production.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F30xB/C reference manual RM0316 for a
description of FM+ I/O mode configuration.
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Electrical characteristics
STM32F302xx/STM32F303xx
Figure 23. I/O AC characteristics definition
90%
10 %
50%
50%
90%
10%
t
EXTERNAL
OUTPUT
ON 50pF
t
r(IO)out
r(IO)out
T
Maximum frequency is achieved if (t + t ) ≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
ai14131
6.3.15
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 52).
PU
Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 22.
Table 55. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.3VDD
+
(1)
VIL(NRST)
NRST Input low level voltage
-
-
0.07(1)
V
0.445VDD
0.398(1)
+
(1)
VIH(NRST)
NRST Input high level voltage
-
-
Vhys(NRST) NRST Schmitt trigger voltage hysteresis
-
25
-
200
-
55
100
-
mV
kΩ
ns
RPU
Weak pull-up equivalent resistor(2)
VIN = VSS
40
-
(1)
VF(NRST)
NRST Input filtered pulse
(1)
VNF(NRST)
NRST Input not filtered pulse
500
-
ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
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Figure 24. Recommended NRST pin protection
Electrical characteristics
6
$$
%XTERNAL
RESET CIRCUITꢐꢃꢑ
2
05
ꢐꢉꢑ
)NTERNAL 2ESET
.234
&ILTER
ꢄꢏꢃ &
-3ꢃꢅꢁꢆꢁ6ꢃ
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 55. Otherwise the reset will not be taken into account by the device.
6.3.16
Timer characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.475VDDA
- 0.2
(1)
VIL(NPOR)
NPOR Input low level voltage
V
0.5VDDA
+ 0.2
(1)
VIH(NPOR)
NPOR Input high level voltage
NPOR Schmitt trigger voltage
hysteresis
(1)
Vhys(NPOR)
200
40
mV
RPU
Weak pull-up equivalent resistor(2)
VIN = VSS
25
55
kΩ
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
The parameters given in Table 56 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 56. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
1
-
fTIMxCLK = 72 MHz
(except TIM1/8)
13.9
6.95
-
ns
ns
(2)
Timer resolution time
tres(TIM)
f
TIMxCLK = 144 MHz,
-
x= 1.8
fTIMxCLK/2
0
0
-
MHz
MHz
Timer external clock
frequency on CH1 to CH4
(2)
fEXT
f
TIMxCLK = 72 MHz
36
16
32
TIMx (except TIM2)
TIM2
(2)
Timer resolution
bit
ResTIM
-
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Electrical characteristics
Table 56. TIMx characteristics (continued)
STM32F302xx/STM32F303xx
(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
1
65536
fTIMxCLK = 72 MHz
(except TIM1/8)
0.0139
0.0069
910
455
µs
µs
(2)
16-bit counter clock period
tCOUNTER
fTIMxCLK = 144 MHz,
x= 1.8
tTIMxCLK
s
-
-
65536 × 65536
59.65
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 72 MHz
(2)
f
TIMxCLK = 144 MHz,
-
29.825
s
x= 1.8
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17
timers
2. Guaranteed by design, not tested in production.
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Electrical characteristics
(1)
Table 57. IWDG min/max timeout period at 40 kHz (LSI)
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
/4
/8
0
1
2
3
4
5
7
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
/16
/32
/64
/128
/256
1638.4
3276.8
6553.6
13107.2
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 58. WWDG min-max timeout value @72 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
1
2
4
8
0
1
2
3
0.05687 (1)
0.1137 (1)
0.2275 (1)
0.4551 (1)
3.6409 (1)
7.2817 (1)
14.564 (1)
29.127 (1)
1. Guaranteed by design, not tested in production.
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STM32F302xx/STM32F303xx
6.3.17
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLK1
DD
summarized in Table 22.
2
2
The I C interface meets the requirements of the standard I C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and V is
DD
disabled, but is still present.
2
The I C characteristics are described in Table 59. Refer also to Section 6.3.14: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
(1)
Table 59. I C characteristics
Standard
mode
Fast mode
Fast Mode Plus
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
4.7
4.0
-
1.3
0.6
-
0.5
0.26
50
-
µs
SCL clock high time
SDA setup time
-
-
-
-
-
250
0(3)
-
100
0(3)
SDA data hold time
3450(2)
900(2)
0
450
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
SDA and SCL fall time
-
-
1000
300
300
300
120
120
-
-
-
-
tf(SDA)
tf(SCL)
th(STA)
tsu(STA)
tsu(STO)
Start condition hold time
4.0
4.7
4.0
4.7
-
-
0.6
0.6
0.6
1.3
-
-
0.26
0.26
0.26
0.5
-
-
µs
Repeated Start condition setup time
Stop condition setup time
-
-
-
-
-
-
-
-
-
μs
μs
pF
tw(STO:STA) Stop to Start condition time (bus free)
Cb Capacitive load for each bus line
400
400
550
The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in
production.
1.
The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal.
2.
3.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of
the falling edge of SCL.
(1)
Table 60. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Pulse width of spikes that are
suppressed by the analog filter
tSP
50
260
ns
1. Guaranteed by design, not tested in production.
96/133
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STM32F302xx/STM32F303xx
Electrical characteristics
2
Figure 25. I C bus AC waveforms and measurement circuit
6
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Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
1.
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
SPI/I2S characteristics
2
Unless otherwise specified, the parameters given in Table 61 for SPI or in Table 62 for I S
are derived from tests performed under ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 22.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
Table 61. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
-
-
18
18
fSCK
SPI clock frequency
MHz
(1)
1/tc(SCK)
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
-
8
ns
%
(1)
SPI slave input clock
duty cycle
DuCy(SCK)(1)
Slave mode
30
70
(1)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
2Tpclk
4Tpclk
-
-
(1)
th(NSS)
(1)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk/2 Tpclk/2
SCK high and low time
Data input setup time
(1)
- 3
5.5
6.5
5
+ 3
(1)
Master mode
Slave mode
Master mode
Slave mode
-
tsu(MI)
tsu(SI)
(1)
-
(1)
th(MI)
-
Data input hold time
ns
(1)
th(SI)
5
-
(1)(2)
ta(SO)
Data output access time Slave mode, fPCLK = 24 MHz
Data output disable time Slave mode
0
4Tpclk
(1)(3)
tdis(SO)
0
24
39
3
(1)
tv(SO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
(1)
tv(MO)
-
(1)
th(SO)
15
4
-
Data output hold time
(1)
th(MO)
-
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z.
98/133
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STM32F302xx/STM32F303xx
Electrical characteristics
Figure 26. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
w(SCKH)
CPHA=0
CPOL=1
t
w(SCKL)
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 27. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
c(SCK)
h(NSS)
CPHA=1
CPOL=0
t
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
(1)
Figure 28. SPI timing diagram - master mode
(IGH
.33 INPUT
T
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T
T
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AIꢃꢀꢃꢈꢂ6ꢉ
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
2
Table 62. I S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master data: 16 bits,
audio freq=48 kHz
1.496
1.503
12.288
8
fCK
1/tc(CK)
I2S clock frequency
MHz
(1)
Slave
0
-
tr(CK)
I2S clock rise and fall
time
Capacitive load
CL = 30 pF
(1)
tf(CK)
tw(CKH)
I2S clock high time
I2S clock low time
Master fPCLK= 36 MHz,
audio frequency =
48 kHz
331
332
-
-
(1)
(1)
tw(CKL)
ns
%
(1)
(1)
(1)
(1)
tv(WS)
th(WS)
tsu(WS)
th(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
Slave mode
4
4
4
0
-
-
-
-
I2S slave input clock
duty cycle
Duty Cycle(1)
Slave mode
30
70
100/133
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STM32F302xx/STM32F303xx
Electrical characteristics
2
Table 62. I S characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
(1)
tsu(SD_MR)
tsu(SD_SR)
Data input setup time
Data input setup time
Master receiver
Slave receiver
Master receiver
Slave receiver
9
2
0
0
(1)
(1)
th(SD_MR)
Data input hold time
(1)
th(SD_SR)
Slave transmitter
(after enable edge)
(1)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
29
3
ns
Slave transmitter
(after enable edge)
(1)
(1)
(1)
12
2
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
1. Data based on characterization results, not tested in production.
2
(1)
Figure 29. I S slave timing diagram (Philips protocol)
t
c(CK)
CPOL = 0
CPOL = 1
t
t
t
w(CKL)
h(WS)
w(CKH)
WS input
t
t
t
h(SD_ST)
t
v(SD_ST)
su(WS)
SD
transmit
(2)
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
(2)
LSB receive
Bitn receive
LSB receive
SD
receive
ai14881b
1. Measurement points are done at 0.5VDD and with external CL=30 pF
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
STM32F302xx/STM32F303xx
2
(1)
Figure 30. I S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
h(WS)
t
v(WS)
w(CKL)
t
t
v(SD_MT)
h(SD_MT)
(2)
SD
transmit
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
(2)
SD
LSB receive
Bitn receive
LSB receive
receive
ai14884b
1. Measurement points are done at 0.5VDD and with external CL=30 pF
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
USB characteristics
Table 63. USB startup time
Symbol
Parameter
Max
Unit
(1)
tSTARTUP
USB transceiver startup time
1
µs
1. Guaranteed by design, not tested in production.
102/133
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STM32F302xx/STM32F303xx
Electrical characteristics
Table 64. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1) Unit
Input levels
VDD
USB operating voltage(2)
3.0(3)
0.2
3.6
-
V
V
(4)
VDI
Differential input sensitivity
Differential common mode range
Single ended receiver threshold
I(USB_DP, USB_DM)
Includes VDI range
(4)
VCM
0.8
2.5
2.0
(4)
VSE
Output levels
1.3
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩ to 3.6 V(5)
-
0.3
3.6
V
(5)
RL of 15 kΩ to VSS
2.8
1. All the voltages are measured from the local ground potential.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
3. The STM32F3xxx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics
which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. Guaranteed by design, not tested in production.
RL is the load connected on the USB drivers
5.
Figure 31. USB timings: definition of data signal rise and fall time
Crossover
points
Differential
Data Lines
V
CR S
V
SS
t
t
r
f
ai14137
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Electrical characteristics
STM32F302xx/STM32F303xx
Table 65.
Symbol
USB: Full-speed electrical characteristics(1)
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
tr
tf
Rise time(2)
Fall time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
-
-
-
-
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
Output driver
Impedance(3)
ZDRV
driving high and low
28
40
44
Ω
1. Guaranteed by design, not tested in production.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter
7 (version 2.0).
2.
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-), the matching impedance is
already included in the embedded driver.
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
104/133
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STM32F302xx/STM32F303xx
Electrical characteristics
6.3.18
ADC characteristics
Unless otherwise specified, the parameters given in Table 66 to Table 69 are guaranteed by
design, with conditions summarized in Table 22.
Table 66. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage for
ADC
VDDA
fADC
2
-
-
-
3.6
72
V
ADC clock frequency
Sampling rate
0.14
0.01
MHz
Resolution = 12 bits,
Fast Channel
5.14
Resolution = 10 bits,
Fast Channel
0.012
0.014
0.0175
-
-
-
-
-
6
7.2
9
(1)
fS
MSPS
Resolution = 8 bits,
Fast Channel
Resolution = 6 bits,
Fast Channel
fADC = 72 MHz
Resolution = 12 bits
5.14
MHz
(1)
fTRIG
External trigger frequency
Resolution = 12 bits
-
0
-
-
-
-
14
1/fADC
V
VAIN
Conversion voltage range
External input impedance
VDDA
100
(1)
RAIN
kΩ
Internal sample and hold
capacitor
(1)
CADC
-
5
-
pF
f
ADC = 72 MHz
1.56
112
µs
(1)
tCAL
Calibration time
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
µs
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
1.5
2
-
2.5
2
Trigger conversion latency
Regular and injected
channels without conversion
abort
-
(1)
tlatr
-
-
2.25
2.125
3.5
-
-
2.5
3
-
Trigger conversion latency
Injected channels aborting a
regular conversion
-
3
(1)
tlatrinj
-
-
-
3.25
3.125
8.35
601.5
-
f
ADC = 72 MHz
0.021
1.5
-
(1)
tS
Sampling time
-
1/fADC
ADC Voltage Regulator
Start-up time
TADCVREG
(1)
-
-
-
10
µs
µs
_STUP
fADC = 72 MHz
Resolution = 12 bits
0.19
3.5
Total conversion time
(including sampling time)
(1)
tCONV
14 to 252 (tS for sampling + 12.5 for
successive approximation)
Resolution = 12 bits
1/fADC
1. Data guaranteed by design
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
Table 67. Maximum ADC R
Sampling
AIN
R
AIN max (kΩ)
Sampling
time [ns] @
72 MHz
Resolution
cycle @
72 MHz
Fast
Slow
channels
Other
channels(1)
channels(2)
1.5
2.5
20.83
34.72
0.018
0.150
0.470
0.820
2.70
NA
NA
NA
0.022
0.180
0.470
1.50
4.5
62.50
0.220
0.560
1.80
6.80
18.0
68.0
NA
7.5
104.17
270.83
854.17
2520.83
8354.17
20.83
12 bits
19.5
61.5
181.5
601.5
1.5
8.20
4.70
22.0
15.0
82.0
47.0
0.082
0.270
0.560
1.20
NA
2.5
34.72
0.082
0.390
0.82
2.70
8.2
0.100
0.330
0.68
4.5
62.50
7.5
104.17
270.83
854.17
2520.83
8354.17
20.83
10 bits
8 bits
6 bits
19.5
61.5
181.5
601.5
1.5
3.30
2.20
10.0
6.8
33.0
27.0
82.0
NA
22.0
100.0
0.150
0.390
0.820
1.50
68.0
0.039
0.180
0.470
1.00
2.5
34.72
0.180
0.560
1.20
3.30
12.00
33.00
100.00
0.100
0.390
0.820
1.80
4.70
15.0
47.0
100.0
4.5
62.50
7.5
104.17
270.83
854.17
2520.83
8354.17
20.83
19.5
61.5
181.5
601.5
1.5
3.90
2.70
12.00
39.00
100.00
0.270
0.560
1.200
2.20
8.20
27.00
82.00
0.150
0.330
0.820
1.50
2.5
34.72
4.5
62.50
7.5
104.17
270.83
854.17
2520.83
8354.17
19.5
61.5
181.5
601.5
5.60
3.90
18.0
12.0
56.0
39.0
100.00
100.0
1. All fast channels, expect channels on PA2, PA6, PB1, PB12.
2. Channels available on PA2, PA6, PB1 and PB12.
106/133
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STM32F302xx/STM32F303xx
Electrical characteristics
Min
(1)(2)
Table 68. ADC accuracy - limited test conditions
Symbol Parameter
Conditions
Typ Max(3) Unit
(3)
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.5
4.5
3.5
3.5
1
6
7
Single ended
Differential
Total
unadjusted
error
ET
EO
EG
ED
EL
6
6
5
Single ended
Differential
1
5
Offset error
Gain error
1
3
1
3
3
6
Single ended
Differential
4
6
LSB
1
2
1.5
1
3
1
Single ended
Differential
Differential
linearity
error
ADC clock freq.
1
1.5
1
≤ 72 MHz
1
Sampling freq ≤ 5
1
1
Msps
VDDA = VREF+ = 3.3 V
25°C
1.5
2
3
Single ended
Differential
Integral
linearity
error
3
1
2
1
2
Fast channel 5.1 Ms 10.3 10.7
Slow channel 4.8 Ms 10.4 10.7
Fast channel 5.1 Ms 10.9 11.3
Slow channel 4.8 Ms 10.9 11.3
-
-
-
Single ended
Differential
Effective
ENOB number of
bits
bits
-
-
-
-
-
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
64
65
67
67
66
66
70
70
Single ended
Differential
Signal-to-
noise and
distortion
ratio
SINAD
dB
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
Min
(1)(2)
Table 68. ADC accuracy - limited test conditions
(continued)
Symbol Parameter
Conditions
Typ Max(3) Unit
(3)
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
64
65
68
69
67
67
70
70
-
-
-
Single ended
Signal-to-
SNR
ADC clock freq. ≤ 72
noise ratio
MHz
Sampling freq ≤ 5
Differential
dB
Msps
-
VDDA = VREF+ = 3.3 V
25°C
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
-
-
−75
−72
−80
−76
−72
−70
−74
−71
Single ended
Differential
Total
THD
harmonic
distortion
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
108/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
Min (4) Max(4) Unit
(1)(2)(3)
Table 69. ADC accuracy
Symbol
Parameter
Conditions
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
7
Single Ended
Total
unadjusted
error
ET
7
Differential
Single Ended
Differential
7
5
5
EO
EG
ED
EL
Offset error
Gain error
4
4
7
Single Ended
Differential
7
LSB
3
3
ADC clock freq.
≤ 72 MHz,
1.5
1.5
1.5
1
Sampling freq. ≤ 5
Single Ended
Differential
Msps
Differential
linearity error
2V ≤ VDDA , VREF+
≤
3.6 V
3
Single Ended
Differential
3
Integral
linearity error
2
2
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
10.2
10.2
10.8
10.8
-
-
-
-
Single Ended
Differential
Effective
number of bits
ENOB
bits
Doc ID 023353 Rev 5
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Electrical characteristics
Table 69. ADC accuracy
STM32F302xx/STM32F303xx
Min (4) Max(4) Unit
(1)(2)(3)
(continued)
Conditions
Symbol
Parameter
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
-
-
63
63
67
67
Single Ended
Differential
Signal-to-
noise and
distortion ratio
SINAD
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
64
64
67
67
-
-
-
ADC clock freq.
Single Ended
Differential
≤ 72 MHz,
Signal-to-
noise ratio
Sampling freq. ≤ 5
SNR
THD
dB
Msps,
2V ≤ VDDA , VREF+
≤
3.6 V
-
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
-
-
−71
−69
−73
−70
Single Ended
Differential
Total
harmonic
distortion
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
Figure 32. ADC accuracy characteristics
V
V
DDA
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
4096
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4095
4094
4093
(3) End point correlation line
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
(1)
transition and the first ideal one.
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
V
V
DDA
SSA
ai14395b
110/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Figure 33. Typical connection diagram using the ADC
Electrical characteristics
6
$$!
Sample and hold ADC
converter
V
0.6 V
T
(1)
AIN
R
R
ADC
AINx
12-bit
converter
I
1 μA
L
C
V
T
parasitic
V
AIN
0.6 V
C
ADC
-3ꢃꢅꢁꢁꢃ6ꢉ
1. Refer to Table 66 for the values of RAIN
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 11. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
6.3.19
DAC electrical specifications
Table 70. DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Comments
Analog supply voltage for
DAC ON
VDDA
2.4
5
-
-
3.6
-
V
(1)
RLOAD
Resistive load with buffer ON
kΩ
When the buffer is OFF, the Minimum
resistive load between DAC_OUT
and VSS to have a 1% accuracy is
1.5 MΩ
Impedance output with buffer
OFF
(1)
RO
-
-
15
kΩ
Maximum capacitive load at
pF DAC_OUT pin (when the buffer is
ON).
(1)
CLOAD
Capacitive load
-
-
-
50
-
It gives the maximum output
excursion of the DAC.
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
0.2
V
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VDDA = 3.6 V
DAC_OUT Higher DAC_OUT voltage
max(1) with buffer ON
and (0x155) and (0xEAB) at VDDA
2.4 V
=
-
-
-
-
-
-
VDDA – 0.2
V
mV
V
DAC_OUT Lower DAC_OUT voltage
0.5
-
VDDA – 1LSB
380
min(1)
with buffer OFF
It gives the maximum output
excursion of the DAC.
DAC_OUT Higher DAC_OUT voltage
max(1) with buffer OFF
-
-
-
With no load, middle code (0x800) on
the input
µA
µA
DAC DC current
(3)
IDDA
consumption in quiescent
mode (Standby mode)(2)
With no load, worst code (0xF1C) on
the input
480
Differential non linearity
-
-
0.5
LSB Given for a 10-bit input code
DNL(3) Difference between two
consecutive code-1LSB)
-
-
-
-
2
1
LSB Given for a 12-bit input code
LSB Given for a 10-bit input code
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
INL(3)
-
-
4
LSB Given for a 12-bit input code
mV
line drawn between Code 0
and last Code 1023)
-
-
-
-
10
3
Offset error
Given for a 10-bit input code at VDDA
(difference between
measured value at Code
LSB
Offset(3)
= 3.6 V
(0x800) and the ideal value =
VDDA/2)
Given for a 12-bit input code at VDDA
= 3.6 V
-
-
-
-
12
LSB
Gain
Gain error
error(3)
0.5
% Given for a 12-bit input code
112/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
Comments
Table 70. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Settling time (full scale: for a
10-bit input code transition
(3) between the lowest and the
highest input codes when
DAC_OUT reaches final
value 1LSB
tSETTLING
-
3
4
µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Max frequency for a correct
Update DAC_OUT change when
-
-
1
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
rate(3)
small variation in the input
code (from code i to i+1LSB)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
(3)
tWAKEUP
-
-
6.5
10
µs
input code between lowest and
highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
–67
–40
dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is
involved.
3. Data based on characterization results, not tested in production.
Figure 34. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RLOAD
DACx_OUT
12-bit
digital to
analog
converter
CLOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
6.3.20
Comparator characteristics
Table 71. Comparator characteristics
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
VDDA
Analog supply voltage
2
0
-
-
3.6
Comparator input voltage
range
VIN
VDDA
V
VBG
VSC
Scaler input voltage
Scaler offset voltage
-
-
1.2
5
-
10
mV
ms
Scaler startup time from
power down
tS_SC
-
-
-
-
0.1
60
Startup time to reach propagation delay
specification
tSTART
Comparator startup time
µs
µs
Ultra-low power mode
Low power mode
-
-
-
-
-
-
-
-
-
-
-
2
0.7
0.3
50
100
2
4.5
1.5
0.6
100
240
7
Propagation delay for
200 mV step with 100 mV Medium power mode
overdrive
VDDA ≥ 2.7 V
VDDA < 2.7 V
High speed mode
ns
µs
tD
Ultra-low power mode
Low power mode
0.7
0.3
90
110
4
2.1
1.2
180
300
10
Propagation delay for full
range step with 100 mV
overdrive
Medium power mode
VDDA ≥ 2.7 V
VDDA < 2.7 V
High speed mode
ns
Voffset
Comparator offset error
mV
Offset error temperature
coefficient
µV/°
C
dVoffset/dT
-
18
-
Ultra-low power mode
Low power mode
-
-
-
-
1.2
3
1.5
5
COMP current
consumption
IDD(COMP)
µA
Medium power mode
High speed mode
10
75
15
100
114/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
Min(1) Typ Max(1) Unit
Table 71. Comparator characteristics (continued)
Symbol
Parameter
Conditions
No hysteresis
(COMPxHYST[1:0]=00)
-
3
0
8
-
High speed mode
13
10
26
19
49
40
Low hysteresis
(COMPxHYST[1:0]=01)
All other power
modes
5
Vhys
Comparator hysteresis
High speed mode
7
mV
Medium hysteresis
(COMPxHYST[1:0]=10)
15
31
All other power
modes
9
High speed mode
18
19
High hysteresis
(COMPxHYST[1:0]=11)
All other power
modes
1. Data based on characterization results, not tested in production.
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
6.3.21
Operational amplifier characteristics
(1)
Table 72. Operational amplifier characteristics
Symbol
Parameter
Analog supply voltage
Common mode input range
Condition
Min
Typ
Max
Unit
VDDA
CMIR
2.4
0
-
-
3.6
V
V
VDDA
25°C, No Load
on output.
-
-
-
-
-
-
-
-
4
6
Maximum
calibration range
All
voltage/Temp.
VIOFFSET
Input offset voltage
mV
25°C, No Load
on output.
1.6
3
After offset
calibration
All
voltage/Temp.
ΔVIOFFSET
Input offset voltage drift
Drive current
-
-
5
-
-
µV/°C
µA
ILOAD
500
No load,
quiescent mode
IDDOPAMP Consumption
-
690
1450
µA
CMRR
PSRR
GBW
SR
Common mode rejection ratio
-
73
-
90
117
8.2
4.7
-
-
-
dB
dB
Power supply rejection ratio
Bandwidth
DC
-
MHz
V/µs
kΩ
Slew rate
-
-
RLOAD
CLOAD
Resistive load
Capacitive load
4
-
-
-
50
pF
R
load = min,
-
-
-
-
-
-
100
20
Input at VDDA
.
VOHSAT
High saturation voltage
Rload = 20K,
Input at VDDA
.
mV
Rload = min,
input at 0V
100
VOLSAT
Low saturation voltage
Phase margin
Rload = 20K,
input at 0V.
-
-
-
20
-
ϕm
62
°
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
tOFFTRIM
-
-
-
2
5
ms
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ,
Follower
tWAKEUP
Wake up time from OFF state.
2.8
µs
configuration
116/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Electrical characteristics
(1)
Table 72. Operational amplifier characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
-
2
-
-
4
-
PGA gain
Non inverting gain value
-
8
16
-
-
-
Gain=2
Gain=4
Gain=8
Gain=16
-
5.4/5.4
16.2/5.4
37.8/5.4
40.5/2.7
-
-
-
-
R2/R1 internal resistance values in
PGA mode (2)
Rnetwork
kΩ
-
-
-
-1%
-
-
PGA gain error PGA gain error
1%
0.2(3)
Ibias
OPAMP input bias current
-
µA
1. Data guaranteed by design.
2. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
R1 is the internal resistance between OPAMP inverting input and ground.
The PGA gain =1+R2/R1
3. Mostly TTa I/O leakage, when used in analog mode.
Doc ID 023353 Rev 5
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Electrical characteristics
STM32F302xx/STM32F303xx
6.3.22
Temperature sensor characteristics
Table 73. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
-
1
4.3
1.43
-
2
4.6
1.52
10
°C
mV/°C
V
Avg_Slope(1) Average slope
4.0
1.34
4
V25
Voltage at 25 °C
Startup time
(1)
tSTART
µs
ADC sampling time when reading the
temperature
(1)(2)
TS_temp
2.2
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
Table 74. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
temperature of 30 °C,
TS_CAL1
0x1FFF F7B8 - 0x1FFF F7B9
0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V
TS ADC raw data acquired at
temperature of 110 °C
TS_CAL2
VDDA= 3.3 V
6.3.23
V
monitoring characteristics
BAT
Table 75.
Symbol
V
monitoring characteristics
Parameter
BAT
Min
Typ
Max
Unit
R
Q
Er(1)
Resistor bridge for VBAT
Ratio on VBAT measurement
Error on Q
-
-
50
2
-
-
KΩ
-1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
(1)(2)
TS_vbat
2.2
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
118/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Package characteristics
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Doc ID 023353 Rev 5
119/133
Package characteristics
STM32F302xx/STM32F303xx
Figure 35. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢄꢏꢉꢇ MM
'!5'% 0,!.%
CCC
#
,
$
,ꢃ
$ꢃ
$ꢈ
ꢇꢃ
ꢆꢇ
ꢇꢄ
ꢆꢂ
ꢃꢄꢄ
ꢉꢂ
0). ꢃ
ꢃ
ꢉꢇ
)$%.4)&)#!4)/.
E
ꢃ,?-%?6ꢈ
1. Drawing is not to scale.
Table 76. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.2
0.063
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
0.05
1.35
0.002
0.0531
0.0067
0.0035
0.622
1.40
0.22
0.0551
0.0087
0.17
c
0.09
D
15.80
13.80
16.00
14.00
12.00
16.00
16.2
14.2
0.6299
0.5512
0.4724
0.6299
D1
D3
E
0.5433
15.80
16.2
0.622
0.6378
120/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Package characteristics
Table 76. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data (continued)
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
E1
E3
e
13.80
14.00
12.00
0.50
0.60
1.00
3.5°
14.2
0.5433
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.5591
L
0.45
0°
0.75
0.0177
0°
0.0295
L1
K
7°
7°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. Recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
1
26
1.2
25
12.3
16.7
ai14906b
1. Dimensions are in millimeters.
Doc ID 023353 Rev 5
121/133
Package characteristics
STM32F302xx/STM32F303xx
Figure 37. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢄꢏꢉꢇ MM
'!5'% 0,!.%
CCC
#
,
$
,ꢃ
$ꢃ
$ꢈ
ꢈꢈ
ꢀꢁ
ꢈꢉ
ꢀꢅ
B
ꢂꢀ
ꢃꢆ
ꢃꢂ
ꢃ
0). ꢃ
)$%.4)&)#!4)/.
E
ꢇ7?-%?6ꢉ
1. Drawing is not to scale.
Table 77. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
12.20
10.20
0.0630
0.0059
0.0571
0.0106
0.0079
0.4803
0.4016
0.05
1.350
0.17
0.0020
0.0531
0.0067
0.0035
0.4646
0.3858
1.40
0.22
0.0551
0.0087
c
0.09
D
11.80
9.80
12.00
10.00
7.50
0.4724
0.3937
0.2953
D1
D3
122/133
Doc ID 023353 Rev 5
STM32F302xx/STM32F303xx
Package characteristics
Table 77. LQFP64 – 10 x 10 mm low-profile quad flat package mechanical data (continued)
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
E
E1
E3
e
11.80
9.80
12.00
10.00
7.50
0.50
0.60
1.00
3.5°
12.20
10.20
0.4646
0.3858
0.4724
0.3937
0.2953
0.0197
0.0236
0.0394
3.5°
0.4803
0.4016
L
0.45
0°
0.75
0.0177
0°
0.0295
L1
K
7°
7°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 38. Recommended footprint
ꢀꢁ
ꢈꢈ
ꢄꢏꢈ
ꢄꢏꢇ
ꢀꢅ
ꢈꢉ
ꢃꢉꢏꢆ
ꢃꢄꢏꢈ
ꢃꢄꢏꢈ
ꢂꢀ
ꢃꢆ
ꢃꢏꢉ
ꢃ
ꢃꢂ
ꢆꢏꢁ
ꢃꢉꢏꢆ
AIꢃꢀꢅꢄꢅB
1. Dimensions are in millimeters.
Doc ID 023353 Rev 5
123/133
Package characteristics
STM32F302xx/STM32F303xx
Figure 39. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢄꢏꢉꢇ MM
'!5'% 0,!.%
CCC
#
$
,
$ꢃ
$ꢈ
,ꢃ
ꢈꢂ
ꢉꢇ
ꢈꢆ
ꢉꢀ
B
ꢀꢁ
ꢃꢈ
0). ꢃ
)$%.4)&)#!4)/.
ꢃ
ꢃꢉ
E
ꢇ"?-%?6ꢉ
1. Drawing is not to scale.
Table 78. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
9.20
7.20
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
0.05
1.35
0.17
0.09
8.80
6.80
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
1.40
0.22
0.0551
0.0087
c
D
9.00
7.00
5.50
9.00
7.00
5.50
0.50
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
D1
D3
E
8.80
6.80
9.20
7.20
0.3465
0.2677
0.3622
0.2835
E1
E3
e
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Package characteristics
Table 78. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data (continued)
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
L
L1
K
0.45
0.60
1.00
3.5°
0.75
0.0177
0.0236
0.0394
3.5°
0.0295
0°
7°
0°
7°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 40. Recommended footprint
ꢄꢏꢇꢄ
ꢃꢏꢉꢄ
ꢄꢏꢈꢄ
ꢈꢂ
ꢈꢆ
ꢉꢇ
ꢉꢀ
ꢄꢏꢉꢄ
ꢆꢏꢈꢄ
ꢅꢏꢆꢄ ꢇꢏꢁꢄ
ꢆꢏꢈꢄ
ꢀꢁ
ꢃ
ꢃꢈ
ꢃꢉ
ꢃꢏꢉꢄ
ꢇꢏꢁꢄ
ꢅꢏꢆꢄ
AIꢃꢀꢅꢃꢃD
1. Dimensions are in millimeters.
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Package characteristics
STM32F302xx/STM32F303xx
7.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 22: General operating conditions on page 58.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
●
●
●
●
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 79. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
ΘJA
55
41
°C/W
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
7.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
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Package characteristics
7.2.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F30xB/C at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 3 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 2 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW
IOmax
This gives: P
= 175 mW and P
= 61.6 mW:
IOmax
INTmax
P
= 175 + 61.6 = 236.6 mW
Dmax
Thus: P
= 236.6 mW
Dmax
Using the values obtained in Table 79 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45°C/W
= 82 °C + (45°C/W × 236.6 mW) = 82 °C + 10.65 °C = 92.65 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
= 115 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 9 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V= 70 mW
INTmax
= 9 × 8 mA × 0.4 V = 28.8 mW
IOmax
This gives: P
= 70 mW and P
= 28.8 mW:
IOmax
INTmax
P
= 70 + 28.8 = 98.8 mW
Dmax
Thus: P
= 98.8 mW
Dmax
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Package characteristics
Using the values obtained in Table 79 T
STM32F302xx/STM32F303xx
is calculated as follows:
Jmax
–
T
For LQFP100, 41°C/W
= 115 °C + (41°C/W × 98.8 mW) = 115 °C + 4.05 °C = 119.05 °C
Jmax
This is within the range of the suffix 7 version parts (–40 < T < 125 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering).
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Part numbering
8
Part numbering
Table 80. Ordering information scheme
Example:
STM32
F
303 R
B
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
302 = STM32F302xx
303 = STM32F303xx
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size
B = 128 Kbytes of Flash memory (medium density)
C = 256 Kbytes of Flash memory (high density)
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
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Revision history
STM32F302xx/STM32F303xx
9
Revision history
Table 81. Document revision history
Date
Revision
Changes
22-Jun-2012
1
Initial release
Modified Features on cover page.
Modified Table 2: STM32F301xx family device features and peripheral
counts
Added clock tree to Section 3.8: Clocks and startup
Added Table 5: STM32F30xB/C I2C implementation
Added Table 6: USART features
Added Table 7: STM32F30xB/C SPI/I2S implementation
Modified Table 8: Capacitive sensing GPIOs available on
STM32F302xx/STM32F303xx devices
Modified Figure 5, Figure 6 and Figure 7:
STM32F302xx/STM32F303xx LQFP100 pinout
Modified Table 11: STM32F302xx/STM32F303xx pin definitions
Modified Figure 11: Power supply scheme
Modified Table 19: Voltage characteristics
Modified Table 20: Current characteristics
Modified Table 23: Operating conditions at power-up / power-down
Added footnote to Table 29: Typical and maximum current consumption
from the VDDA supply
07-Sep-2012
2
Added footnote to Table 33 and Table 34: Typical current consumption
in Sleep mode, code running from Flash or RAM
Removed table “Switching output I/O current consumption” and table
“Peripheral current consumption”
Added note under Figure 17: Typical application with a 32.768 kHz
crystal
Updated Table 42: HSI oscillator characteristics
Updated Wakeup time from low-power mode and Table 37: Low-power
mode wakeup timings
Updated Table 45: Flash memory characteristics
Updated Table 50: Electrical sensitivities
Updated Table 51: I/O current injection susceptibility
Updated Table 52: I/O static characteristics
Updated Table 53: Output voltage characteristics
Updated Table 55: NRST pin characteristics
Updated Table 61: SPI characteristics
Updated Table 62: I2S characteristics
Corrected LQFP100 in Section 7.2.3: Selecting the product
temperature range
21-Sep-2012
3
Updated Table 61: SPI characteristics
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Table 81. Document revision history
Revision history
Date
Revision
Changes
Updated first page
Removed references to VDDSDx and VSSSD
Added reference to PM0214 in Section 1
Moved Temp. sensor calibartion values toTable 74 and VREF
calibration values to Table 27
Updated Table 2: STM32F30xB/C family device features and
peripheral counts on page 10
UpdatedSection 3.4: Embedded SRAM on page 14
Updated Section 3.2: Memory protection unit (MPU) on page 13
Updated Section 3.23: Universal serial bus (USB) on page 28
Modified Section 3.25: Touch sensing controller (TSC) on page 29
Updated heading of Table 6: USART features on page 27
Updated Table 11: STM32F302xx/STM32F303xx pin definitions on
page 36
Added notes to PC13, PC14 and PC15 in Table 11:
STM32F302xx/STM32F303xx pin definitions on page 36
Updated Figure 11: Power supply scheme on page 54
Modified Table 19: Voltage characteristics on page 56
Modified Table 20: Current characteristics on page 57
Modified Table 22: General operating conditions on page 58
Modified Figure 13: Typical VBAT current consumption (LSE and RTC
ON/LSEDRV[1:0] = ’00’) on page 66
Updated Section 6.3.14: I/O port characteristics on page 87
Updated Table 28: Typical and maximum current consumption from
VDD supply at VDD = 3.6V on page 62 and Table 29: Typical and
maximum current consumption from the VDDA supply on page 63
Updated Table 30: Typical and maximum VDD consumption in Stop
and Standby modes on page 65 and Table 31: Typical and maximum
VDDA consumption in Stop and Standby modes on page 65
Updated Table 32: Typical and maximum current consumption from
VBAT supply on page 66
05-Dec-2012
4
Added Figure 13: Typical VBAT current consumption (LSE and RTC
ON/LSEDRV[1:0] = ’00’)
Updated Table 33: Typical current consumption in Run mode, code
with data processing running from Flash on page 67 and Table 34:
Typical current consumption in Sleep mode, code running from Flash
or RAM on page 68
Added Table 36: Peripheral current consumption on page 71
Added Table 35: Switching output I/O current consumption on page 70
Updated Section 6.3.6: Wakeup time from low-power mode on page 73
Modified ESD absolute maximum ratings on page 84
Modified Table 53: Output voltage characteristics on page 90
Updated EMI characteristics on page 84
Updated Table 54: I/O AC characteristics on page 91
Updated Table 51: I/O current injection susceptibility on page 86
Updated Table 56: TIMx characteristics on page 93
Updated Section 7.2: Thermal characteristics on page 126
Added Table 67: Maximum ADC RAIN on page 106
Added Table 68: ADC accuracy - limited test conditions on page 107
Updated Table 69: ADC accuracy on page 109
Updated Table 70: DAC characteristics on page 112
Updated Table 72: Operational amplifier characteristics on page 116
Updated figures and tables in Section 7: Package characteristics
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Revision history
Table 81. Document revision history
STM32F302xx/STM32F303xx
Date
Revision
Changes
Updated Vhys and Ilkg in Table 52: I/O static characteristics.
Updated VIL(NRST), VIH(NRST), and VNF(NRST) in Table 55: NRST pin
characteristics.
08-Jan-2013
5
Updated Table 68: ADC accuracy - limited test conditions and Table 69:
ADC accuracy.
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