STM32F334C6Y6TR [STMICROELECTRONICS]
Arm®Cortex®-M4 32b MCUFPU,up to 64KB Flash,16KB SRAM, 2 ADCs,3 DACs,3 comp.,op-amp, 217ps 10-ch (HRTIM1);
| 型号： | STM32F334C6Y6TR |
| 厂家： | 
ST |
| 描述： | Arm®Cortex®-M4 32b MCUFPU,up to 64KB Flash,16KB SRAM, 2 ADCs,3 DACs,3 comp.,op-amp, 217ps 10-ch (HRTIM1) 静态存储器 |
| 文件： | 总125页 (文件大小：2606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F334x4 STM32F334x6
STM32F334x8
Arm®Cortex®-M4 32b MCU+FPU,up to 64KB Flash,16KB SRAM,
2 ADCs,3 DACs,3 comp.,op-amp, 217ps 10-ch (HRTIM1)
Datasheet - production data
Features
®
®
• Core: Arm Cortex -M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and
HW division DSP instruction
UFQFPN32 (5 x 5 mm)
LQFP32 (7 x 7 mm)
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
WLCSP49
(3.89x3.74 mm)
• Memories
– Up to 64 Kbytes of Flash memory
– Up to 12 Kbytes of SRAM with HW parity
check
• Three ultra-fast rail-to-rail analog comparators
with analog supply from 2 to 3.6 V
– Routine booster: 4 Kbytes of SRAM on
instruction and data bus with HW parity
check (CCM)
• One operational amplifiers that can be used in
PGA mode, all terminals accessible with
analog supply from 2.4 to 3.6 V
• CRC calculation unit
• Up to 18 capacitive sensing channels
supporting touchkeys, linear and rotary touch
sensors
• Reset and supply management
– Low-power modes: Sleep, Stop, Standby
• Up to 12 timers
– V
V
voltage range: 2.0 to 3.6 V
DD, DDA
– HRTIM: 6 x16-bit counters, 217 ps
resolution, 10 PWM, 5 fault inputs, 10 ext
event input, 1 synchro. input,1 synchro. out
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– V
supply for RTC and backup registers
– One 32-bit timer and one 16-bit timer with
up to 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
BAT
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– One 16-bit 6-channel advanced-control
timer, with up to 6 PWM channels,
– Internal 8 MHz RC (up to 64 MHz with PLL
option)
deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs,
1 OCN/PWM, deadtime generation,
emergency stop
– Internal 40 kHz oscillator
• Up to 51 fast I/O ports, all mappable on
external interrupt vectors, several 5 V-tolerant
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
• Interconnect matrix
– Two watchdog timers (independent,
window)
• 7-channel DMA controller
• Up to two ADC 0.20 µs (up to 21 channels) with
selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, single-ended /
differential mode, separate analog supply from
2.0 to 3.6 V
– SysTick timer: 24-bit downcounter
– Up to two 16-bit basic timers to drive DAC
• Calendar RTC with alarm, periodic wakeup
from Stop
• Temperature sensor
• Communication interfaces
• Up to three 12-bit DAC channels with analog
– CAN interface (2.0 B Active) and one SPI
supply from 2.4 V to 3.6 V
July 2018
DS9994 Rev 9
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This is information on a product in full production.
www.st.com
STM32F334x4 STM32F334x6 STM32F334x8
2
– One I C with 20 mA current sink to support
• 96-bit unique ID
• All packages ECOPACK 2 compliant
®
Fast mode plus, SMBus/PMBus
– Up to 3 USARTs, one with ISO/IEC 7816
interface, LIN, IrDA, modem control
• Debug mode: serial wire debug (SWD), JTAG
Table 1. Device summary
Reference
Part number
STM32F334Kx
STM32F334Cx
STM32F334Rx
STM32F334K4/K6/K8
STM32F334C4/C6/C8
STM32F334R6/R8
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STM32F334x4 STM32F334x6 STM32F334x8
Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Arm® Cortex®-M4 core with FPU with embedded Flash
memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1
3.2.2
3.2.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
3.4
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 15
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.1
3.4.2
3.4.3
3.4.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
3.6
3.7
3.8
3.9
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 20
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9.1
3.9.2
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.3
V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
BAT
3.10.4 OPAMP2 reference voltage (VOPAMP2) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13 Ultra-fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Contents
STM32F334x4 STM32F334x6 STM32F334x8
3.14.1 217 ps high-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14.2 Advanced timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14.3 General-purpose timers (TIM2, TIM3, TIM15, TIM16 and TIM17) . . . . . 25
3.14.4 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 26
3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2
3.16.1 Inter-integrated circuit interface (I C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16.2 Universal synchronous / asynchronous
receivers / transmitters (USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.4 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.1 Serial-wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31
4
5
6
Pinout and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Input voltage on a pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power-supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Measurement of the current consumption . . . . . . . . . . . . . . . . . . . . . . . 49
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.1
6.3.2
6.3.3
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 53
Characteristics of the embedded reset and power-control block . . . . . . 53
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Contents
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.16 High-resolution timer (HRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.17 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.18 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.19 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.22 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.23 Temperature sensor (TS) characteristics . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.24
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
BAT
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.7.1
7.7.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 120
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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5
List of tables
STM32F334x4 STM32F334x6 STM32F334x8
List of tables
Table 1.
Table 2.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32F334x4/6/8 family device features and peripheral counts. . . . . . . . . . . . . . . . . . . . 11
Table 3.
V
ranges for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDA
Table 4.
Table 5.
Table 6.
STM32F334x4/6/8 peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Comparison of I C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2
Table 7.
Table 8.
Table 9.
STM32F334x4/6/8 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32F334x4/6/8 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Capacitive sensing GPIOs available on STM32F334x4/6/8 devices . . . . . . . . . . . . . . . . . 30
No. of capacitive sensing channels available on STM32F334x4/6/8 devices. . . . . . . . . . . 31
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM32F334x4/6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM32F334x4/6/8 peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . 45
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 53
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Typical and maximum current consumption from V supply at V = 3.6V . . . . . . . . . . . 56
DD
DD
Typical and maximum current consumption from the V
supply . . . . . . . . . . . . . . . . . . 57
DDA
Typical and maximum V consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 57
DD
Typical and maximum V
consumption in Stop and Standby modes. . . . . . . . . . . . . . . 58
DDA
Typical and maximum current consumption from V
supply. . . . . . . . . . . . . . . . . . . . . . 58
BAT
Typical current consumption in Run mode, code with data processing
running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 61
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Wakeup time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
HRTIM1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
HRTIM output response to fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
HRTIM output response to external events 1 to 5 (Low-Latency mode). . . . . . . . . . . . . . . 83
HRTIM output response to external events 1 to 10 (Synchronous mode ). . . . . . . . . . . . . 83
HRTIM synchronization input / output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
IWDG min./max. timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
WWDG min./max. timeout value at 72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2
I C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Temperature sensor (TS) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Temperature sensor (TS) calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
BAT
LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
Table 79.
Table 80.
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 81.
Table 82.
Table 83.
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7
List of figures
STM32F334x4 STM32F334x6 STM32F334x8
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32F334x4/6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
WLCSP49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32F334x4/6/8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. Power-supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Scheme of the current-consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 14. Typical V
current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 59
BAT
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 71
Figure 20. TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 21. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 22. 5V- tolerant (FT and FTf) I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . 78
Figure 23. 5V-tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
(1)
Figure 27. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
(1)
Figure 28. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 29. ADC typical current consumption in single-ended and differential modes . . . . . . . . . . . . . 91
Figure 30. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 31. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 32. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 33. Maximum V
scaler startup time from power-down . . . . . . . . . . . . . . . . . . . . . . . . . 100
REFINT
Figure 34. OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 35. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 36. Recommended footprint for the LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 37. LQFP32 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 38. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 39. Recommended footprint for the LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 40. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 41. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 42. Recommended footprint for the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 43. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 44. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 45. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 46. WLCSP49 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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Figure 47. UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 48. UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 49. UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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9
Introduction
STM32F334x4 STM32F334x6 STM32F334x8
1
Introduction
This datasheet provides the ordering information and the mechanical device characteristics
of the STM32F334x4/6/8 microcontrollers.
This document must be read in conjunction with the STM32F334xx, reference manual
(RM0364) available from the STMicroelectronics website www.st.com.
®
For information on the Cortex -M4 core with FPU, refer to:
®(a)
®
•
Arm
Cortex -M4 Processor Technical Reference Manual available from the
www.arm.com website.
®
•
STM32F3xxx and STM32F4xxx Cortex -M4 programming manual (PM0214) available
from the www.st.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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Description
2
Description
®
®
The STM32F334x4/6/8 family incorporates the high-performance Arm Cortex -M4 32-bit
RISC core operating at up to 72 MHz frequency embedding a floating point unit (FPU),
high-speed embedded memories (up to 64 Kbytes of Flash memory, up to 12 Kbytes of
SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB
buses.
The STM32F334x4/6/8 microcontrollers offer two fast 12-bit ADCs (5 Msps), up to three
ultra-fast comparators, an operational amplifier, three DAC channels, a low-power RTC, one
high-resolution timer, one general-purpose 32-bit timer, one timer dedicated to motor
control, and four general-purpose 16-bit timers. They also feature standard and advanced
2
communication interfaces: one I C, one SPI, up to three USARTs and one CAN.
The STM32F334x4/6/8 family operates in the –40 to +85 °C and –40 to +105 °C
temperature ranges from 2.0 to 3.6 V power supply. A comprehensive set of power-saving
modes allow the design of low-power applications.
The STM32F334x4/6/8 family offers devices in 32, 48 and 64-pin packages.
Depending on the device chosen, different sets of peripherals are included.
Table 2. STM32F334x4/6/8 family device features and peripheral counts
Peripheral
STM32F334Kx
STM32F334Cx
STM32F334Rx
Flash memory (Kbyte)
16
32
64
16
32
12
64
16
32
64
SRAM on data bus (Kbyte)
Core coupled memory SRAM
on instruction bus (CCM
SRAM) (Kbyte)
4
High-resolution
timer
1 (16-bit / 10 channels)
1 (16-bit)
Advanced control
General purpose
Basic
4 (16-bit)
1 (32 bit)
2 (16-bit)
1
SysTick timer
Timers
Watchdog timers
(independent,
window)
2
26
20
PWM channels
(all)(1)
20
14
28
22
PWM channels
(except
complementary)
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46
Description
STM32F334x4 STM32F334x6 STM32F334x8
Table 2. STM32F334x4/6/8 family device features and peripheral counts (continued)
Peripheral
STM32F334Kx
STM32F334Cx
STM32F334Rx
SPI
1
1
I2C
Comm.
interfaces
USART
CAN
2
3
1
Normal I/Os (TC,
TTa)
10
20
26
GPIOs
5-Volt tolerant
I/Os (FT,FTf)
15
14
17
25
18
Capacitive sensing channels
DMA channels
17
7
12-bit ADCs
2
2
2
Number of channels
10
15
21
12-bit DAC channels
Ultra-fast analog comparator
Operational amplifiers
CPU frequency
3
2
3
1
72 MHz
Operating voltage
2.0 to 3.6 V
Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Junction temperature: - 40 to 125 °C
Operating temperature
Packages
LQFP32, UFQFPN32
LQFP48, WLCSP49
LQFP64
1. This total considers also the PWMs generated on the complementary output channels.
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Description
Figure 1. STM32F334x4/6/8 block diagram
@VDD33
POWER
TPIU
V
DD18
SWJTAG
FPU
V
V
=2 to 3.6V
JTRST
JTDI
DD33
SS
Flash 64KB
64 bits
VOLT. REG.
3.3V TO 1.8V
Ibus
JTCK-SWCLK
JTMS-SWDAT
JTDO-TRACESWO
as AF
CORTEX M4 CPU
@VDDA
Dbus
SRAM
12KB
Dbus
SUPPLY
F
= 72MHz
NVIC
POR
NRESET
VDDA
VSSA
max
SUPERVISION
System
bus
Reset
@VDDA
CCM SRAM
4KB
POR / PDR
Int
RC HS 8MHz
RC LS
PVD
GP DMA1
7 channels
@VDD33
OSC_IN
XTAL OSC
PLL
OSC_OUT
4-32MHz
Ind. WDG32K
AHBPCLK
Standby
interface
Temp sensor
APBP1CLK
APBP2CLK
HCLK
V
=
BAT
RESET&
1.65 to 3.6V
12bitADC1 IF
CLOCK
CTRL
V
REF+
V
REF-
FCLK
OSC32_IN
USARTCLK
I2CCLK
ADC1/ADC2
XTAL 32kHz
12bitADC2 IF
OSC32_OUT
Backup
RTC
ANTI-TAMP
reg (20B)
AWU
@VDDA
Backup interface
TIM2 (32-bit/PWM)
TIM3
PA[15:0]
GPIOPORTA
4 Channels, ETR
as AF
CRC
PB[15:0]
PC[15:0]
GPIOPORTB
GPIOPORTC
GPIOPORTD
GPIOPORTF
4 Channels, ETR
as AF
PD2
RX,TX, CTS, RTS,
SmartCard as AF
USART2
USART3
PF[1:0]
RX,TX, CTS, RTS,
SmartCard as AF
6 Groups of
Touch Sensing
Controller
4 Channels as AF
AHB2
APB2
AHB2
APB1
WinWATCHDOG
SCL,SDA,SMBA
as AF
I2C1
EXT.IT
WKUP
up to 16 lines
2 channels,
1 compl. channel,
TIM15
CAN_TX
CAN_RX
BRK as AF
1 channel,
1 compl. channel,
BRK as AF
BxCAN
TIM16
TIM17
1 channel,
1 compl. channel,
BRK as AF
12-bit DAC1
IF
4 channels,
3 compl. channel,
ETR, BRK as AF
DAC1_OUT1 as AF
DAC1_OUT2 as AF
channel 1
TIM6
TIM7
TIM1
12-bit DAC1
channel 2
IF
IF
5 fault inputs as AF
10 PWM outputs
10 ext. event inputs
1 synchro. input
HRTIM1
12-bit DAC2
channel 1
DAC2_OUT1 as AF
1 synchro. output
MOSI,MISO,
SPI1
SCK,NSS as AF
RX,TX, CTS, RTS,
SmartCard as AF
USART1
IF Op-amp2
@VDDA
SYSCFG CTL
INM, INP, OUT as AF
@VDDA
GP Comparator 6
GP Comparator 4
GP Comparator 2
INM, INP, OUT as AF
MSv31953V3
1. AF: alternate function on I/O pins.
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46
Functional overview
STM32F334x4 STM32F334x6 STM32F334x8
3
Functional overview
3.1
Arm® Cortex®-M4 core with FPU with embedded Flash
memory and SRAM
The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for
embedded systems. It has been developed to provide a low-cost platform that meets the
needs of MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm 32-bit Cortex-M4 RISC processor with FPU features exceptional code-efficiency,
delivering the high performance expected from an Arm core, with memory sizes usually
associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions that allows efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm core, the STM32F334x4/6/8 family is compatible with all Arm tools
and software.
Figure 1 shows the general block diagram of the STM32F334x4/6/8 family devices.
3.2
Memories
3.2.1
Embedded Flash memory
All STM32F334x4/6/8 devices feature up to 64 Kbytes of embedded Flash memory
available for storing programs and data. The Flash memory access time is adjusted to the
CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2
wait states above).
3.2.2
Embedded SRAM
The STM32F334x4/6/8 devices feature up to 12 Kbytes of embedded SRAM with hardware
parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait
states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz when running code from
CCM (core coupled memory) RAM.
The SRAM is organized as follows:
•
4 Kbytes of SRAM on instruction and data bus with parity check (core coupled memory
or CCM) and used to execute critical routines or to access data
•
12 Kbytes of SRAM with parity check mapped on the data bus
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3.2.3
Boot modes
At startup, BOOT0 pin and BOOT1 option bit are used to select one of the three boot
options:
•
•
•
Boot from user Flash memory
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART2 (PA2/PA3), I2C1 (PB6/PB7).
3.3
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps to compute a signature
of the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.4
Power management
3.4.1
Power supply schemes
•
V
, V = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
SS DD
provided externally through V pins.
DD
•
V
, V
= 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators
DDA
SSA
operational amplifiers, reset blocks, RCs and PLL.The minimum voltage to be applied
to V differs from one analog peripherals to another. See Table 3 below,
DDA
summarizing the V
ranges for analog peripherals. The V
voltage level must be
DDA
DDA
always greater or equal to the V voltage level and must be provided first.
DD
•
V
= 1.65 to 1.95 V (V
domain): power supply for digital core, SRAM and Flash
DD18
DD18
memory. V
is internally generated through an internal voltage regulator.
DD18
Table 3. V
ranges for analog peripherals
DDA
Analog peripheral
ADC/COMP
DAC/OPAMP
Min. VDDAsupply
Max. VDDAsupply
2 V
3.6 V
3.6 V
2.4 V
•
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
3.4.2
Power supply supervisor
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
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remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
•
The POR monitors only the V supply voltage. During the startup phase it is required
DD
that V
must arrive first and be greater than or equal to V
.
DDA
DD
•
The PDR monitors both the V and V
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V is higher than or
supply voltages, however the V
power
DD
DDA
DDA
DDA
equal to V
.
DD
The device features an embedded programmable voltage detector (PVD) that monitors the
power supply and compares it to the VPVD threshold. An interrupt can be generated
V
DD
when V drops below the V
threshold and/or when V is higher than the V
DD
PVD
DD PVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.4.3
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR), and power-down.
•
•
•
The MR mode is used in the nominal regulation mode (Run)
The LPR mode is used in Stop mode.
The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
3.4.4
Low-power modes
The STM32F334x4/6/8 supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm, COMPx,
2
I C or USARTx.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
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3.5
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F334x4/6/8 peripheral interconnect matrix
Interconnect
Interconnect source
Interconnect action
Timers synchronization or chaining
Conversion triggers
destination
TIMx
ADCx
DACx
TIMx
DMA
Memory to memory transfer trigger
Comparator output blanking
COMPx
TIMx
COMPx
ADCx
Timer input: ocrefclear input, input capture
Timer triggered by analog watchdog
TIM/HRTIM1
GPIO
RTCCLK
HSE/32
MC0
Clock source used as input channel for HSI and
LSI calibration
TIM16
CSS
CPU (hard fault)
RAM (parity error)
COMPx
TIM1
Timer break
TIM15, 16, 17
PVD
GPIO
TIMx
External trigger, timer break
Conversion external trigger
GPIO
ADCx
DACx
DACx
COMPx
Comparator inverting input
Conversion trigger
HRTIM1
DACx/ADCx
COMPx output is an input event or a fault input for
HRTIM1
COMPx
HRTIM1
OPAMP2
GPIO
HRTIM1
HRTIM1
GPIO
OPAMP2 output is an input event for HRTIM1
External fault/event/ Synchro inputs for HRTIM1
Synchro output for HRTIM1
HRTIM1
Note:
For more details about the interconnect actions, refer to the corresponding sections in the
RM0364 reference manual.
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3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected on reset as default CPU clock. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high-speed APB (APB2) and
the low-speed APB (APB1) domains. The maximum frequency of the AHB and the
high-speed APB domains is 72 MHz, while the maximum allowed frequency of the low-
speed APB domain is 36 MHz.
TIM1and HRTIM1 maximum frequency is 144 MHz.
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Figure 2. Clock tree
FLITFCLK
to Flash programming interface
HSI
to I2C1
SYSCLK
HSI
8 MHz
HSI RC
/2
HCLK
to AHB bus, core,
memory and DMA
PLLSRC
to cortex System timer
SW
/8
PLLMUL
FHCLK Cortex free
running clock
HSI
PLLCLK
AHB
prescaler
APB1
PLL
x2,x3,..
x16
PCLK1
to APB1 peripherals
prescaler
/1,2,..512
/1,2,4,8,16
HSE
SYSCLK
If (APB1 prescaler
=1) x1 else x2
CSS
to TIM 2, 3, 6, 7
/2,/3,...
/16
PCLK1
SYSCLK
HSI
OSC_OUT
OSC_IN
to USARTx (x = 1, 2, 3)
4-32 MHz
HSE OSC
LSE
APB2
prescaler
/1,2,4,8,16
PCLK2
to APB2 peripherals
to TIM 15,16,17
/32
LSE
RTCCLK
OSC32_IN
to RTC
LSE OSC
If (APB2 prescaler
=1) x1 else x2
32.768kHz
OSC32_OUT
RTCSEL[1:0]
LSI
IWDGCLK
to IWDG
LSI RC
40kHz
PLLNODIV
/2
MCOPRE
PLLCLK
TIM1/
HRTIM1
x2
HSI
LSI
/1,2,4,
...128
MCO
HSE
SYSCLK
ADC
to ADCx
(x = 1, 2)
Main clock
output
MCO
Prescaler
/1,2,4
ADC
Prescaler
/1,2,4,6,8,10,12,16,
32,64,128,256
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3.7
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed, following a specific
sequence to avoid spurious writing to the I/Os registers.
Fast I/O handling allows I/O toggling up to 36 MHz.
3.8
Direct memory access (DMA)
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-
memory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.
Each of the 7 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
high-resolution timer, DAC and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F334x4/6/8 devices embed a nested vectored interrupt controller (NVIC) able to
handle up to 60 interrupt channels that can be masked and 16 priority levels.
The NVIC benefits are the following:
•
•
•
•
•
•
•
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved on interrupt entry and restored on interrupt exit
with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.9.2
Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 27 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
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independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 51
GPIOs can be connected to the 16 external interrupt lines.
3.10
Fast analog-to-digital converter (ADC)
Two 5 MSPS fast analog-to-digital converters, with selectable resolution between 12 and 6
bit, are embedded in the STM32F334x4/6/8 family devices. The ADCs have up to 21
external channels. Some of the external channels are shared between ADC1 and ADC2,
performing conversions in single-shot or scan modes. The channels can be configured to be
either single-ended input or differential input. In scan mode, automatic conversion is
performed on a selected group of analog inputs.
The ADCs also have internal channels: temperature sensor connected to ADC1 channel 16,
V
/2 connected to ADC1 channel 17, voltage reference V
connected to both ADC1
BAT
REFINT
and ADC2 channel 18 and VOPAMP2 connected to ADC2 channel 17.
Additional logic functions embedded in the ADC interface allow:
•
•
•
Simultaneous sample and hold
Interleaved sample and hold
Single-shunt phase current reading techniques.
Three analog watchdogs are available per ADC. The ADC can be served by the DMA
controller.
The analog watchdog feature allows very precise monitoring of the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIM2, TIM3, TIM6, TIM15), the
advanced-control timer (TIM1) and the High-resolution timer (HRTIM1) can be internally
connected to the ADC start trigger and injection trigger, respectively, to allow the application
to synchronize A/D conversion and timers.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
that varies linearly with
SENSE
The temperature sensor is internally connected to the ADC1_IN16 input channel that is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.10.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC1_IN18 and ADC2_IN18
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input channels. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
3.10.3
V
battery voltage monitoring
BAT
This embedded hardware feature allows the application to measure the V
battery voltage
BAT
using the internal ADC channel ADC1_IN17. As the V
voltage may be higher than V
,
BAT
DDA
and thus outside the ADC input range, the V
pin is internally connected to a bridge
BAT
divider by 2. As a consequence, the converted digital value is half the V
voltage.
BAT
3.10.4
OPAMP2 reference voltage (VOPAMP2)
OPAMP2 reference voltage can be measured using ADC2 internal channel 17.
3.11
Digital-to-analog converter (DAC)
One 12-bit buffered DAC channel (DAC1_OUT1) and two 12-bit unbuffered DAC channels
(DAC1_OUT2 and DAC2_OUT1) can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
•
•
•
•
•
•
•
•
•
Three DAC output channels
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation (only on DAC1)
Triangular-wave generation (only on DAC1)
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
3.12
Operational amplifier (OPAMP)
The STM32F334x4/6/8 embeds an operational amplifier (OPAMP2) with external or internal
follower routing and PGA capability (or even amplifier and filter capability with external
components). When an operational amplifier is selected, an external ADC channel is used
to enable output measurement.
The operational amplifier features:
•
•
•
•
8 MHz GBP
0.5 mA output capability
Rail-to-rail input/output
In PGA mode, the gain can be programmed to 2, 4, 8 or 16.
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3.13
Ultra-fast comparators (COMP)
The STM32F334x4/6/8 devices embed three ultra-fast rail-to-rail comparators (COMP2/4/6)
that offer the features below:
•
•
Programmable internal or external reference voltage
Selectable output polarity.
The reference voltage can be one of the following:
•
•
•
External I/O
DAC output
Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 23: Embedded
internal reference voltage for values and parameters of the internal reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the
timers.
3.14
Timers and watchdogs
The STM32F334x4/6/8 includes advanced control timer, 5 general-purpose timers, basic
timer, two watchdog timers and a SysTick timer. The table below compares the features of
the advanced control, general purpose and basic timers.
Table 5. Timer feature comparison
DMA
request
generation channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
/1 /2 /4
(x2 x4 x8 x16
x32, with
DLL)
High-
resolution HRTIM1(1)
timer
16-bit
Up
Yes
10
Yes
Any integer
between 1
and 65536
Advanced
TIM1(1)
control
Up, Down,
Up/Down
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
Yes
Yes
Yes
4
4
4
2
1
0
Yes
No
No
1
Any integer
between 1
and 65536
General-
TIM2
Up, Down,
Up/Down
purpose
Any integer
between 1
and 65536
General-
TIM3
Up, Down,
Up/Down
purpose
Any integer
between 1
and 65536
General-
TIM15
Up
Up
Up
purpose
Any integer
between 1
and 65536
General-
purpose
TIM16,
TIM17
1
Any integer
between 1
and 65536
Basic
TIM6, TIM7
No
1. TIM1 can be clocked from the PLL x 2 running at 144 MHz .
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3.14.1
217 ps high-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
HRTIM1 timer is made of a digital kernel clocked at 144 MHz followed by delay lines. Delay
lines with closed loop control guarantee a 217 ps resolution whatever the voltage,
temperature or chip-to-chip manufacturing process deviation. The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, burst mode controller,
push-pull and resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
In debug mode, the HRTIM1 counters can be frozen and the PWM outputs enter safe state.
3.14.2
Advanced timer (TIM1)
The advanced-control timer can be seen as a three-phase PWM multiplexed on 6 channels.
They have complementary PWM outputs with programmable inserted dead-times. They can
also be seen as complete general-purpose timers. The 4 independent channels can be
used for:
•
•
•
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
Section 3.14.3) using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
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3.14.3
General-purpose timers (TIM2, TIM3, TIM15, TIM16 and TIM17)
There are up to three general-purpose timers embedded in the STM32F334x4/6/8 (see
Table 5 for differences) that can be synchronized. Each general-purpose timer can be used
to generate PWM outputs, or act as a simple time base.
•
TIM2 and TIM3
They are full-featured general-purpose timers:
–
–
TIM2 has a 32-bit auto-reload up/down counter and 32-bit prescaler
TIM3 has a 16-bit auto-reload up/down counter and 16-bit prescaler
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
TIM15, 16 and 17
•
They are three general-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
–
TIM15 has two channels and one complementary channel
TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.14.4
3.14.5
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
3.14.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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3.14.7
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
•
•
•
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
3.15
Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power from
either the V supply when present or the VBAT pin. The backup registers are five 32-bit
DD
registers used to store 20 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms with wakeup from Stop and Standby mode capability.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
•
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
Two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection.
Timestamp feature, which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
•
17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY
capability.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 40 kHz)
The high-speed external clock divided by 32.
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3.16
Communication interfaces
2
3.16.1
Inter-integrated circuit interface (I C)
2
The devices feature an I C bus interface that can operate in multimaster and slave mode. It
can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz)
modes.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,
1 with configurable mask). It also includes programmable analog and digital noise filters.
2
Table 6. Comparison of I C analog and digital filters
-
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
≥ 50 ns
1. Extra filtering capability vs.
standard requirements.
Benefits
Available in Stop mode
2. Stable length
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Variations depending on
temperature, voltage, process
Drawbacks
In addition, it provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. It also has a clock domain independent from the CPU clock,
allowing the I2C1 to wake up the MCU from Stop mode on address match.
2
The I C interface can be served by the DMA controller.
The features available in I2C1 are showed below in Table 7.
Table 7. STM32F334x4/6/8 I2C implementation
I2C features(1)
I2C1
7-bit addressing mode
X
X
X
X
X
X
X
X
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Independent clock
SMBus
Wakeup from STOP
1. X = supported.
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46
Functional overview
STM32F334x4 STM32F334x6 STM32F334x8
3.16.2
Universal synchronous / asynchronous
receivers / transmitters (USARTs)
The STM32F334x4/6/8 devices have three embedded universal synchronous
receivers/transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
USART1 provides hardware management of the CTS and RTS signals. It supports IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode and has LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
The features available in the USART interfaces are showed below in Table 8.
Table 8. USART features
USART2
USART modes/features(1)
USART1
USART3
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
-
-
Dual clock domain and wake up from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
-
-
-
-
X
1. X = supported.
3.16.3
Serial peripheral interface (SPI)
A SPI interface allows to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
The features available in SPI1 are showed below in Table 9.
Table 9. STM32F334x4/6/8 SPI implementation
SPI features(1)
SPI1
Hardware CRC calculation
Rx/Tx FIFO
X
X
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Functional overview
Table 9. STM32F334x4/6/8 SPI implementation (continued)
SPI features(1)
SPI1
NSS pulse mode
TI mode
X
X
1. X = supported.
3.16.4
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.17
Infrared transmitter
The STM32F334x4/6/8 devices provide an infrared transmitter solution. The solution is
based on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes is obtained by programming the two timers of the output compare channels (see
Figure 3).
Figure 3. Infrared transmitter
TIMER 16
OC
OC
(for envelop)
PB9/PA13
TIMER 17
(for carrier)
MSv30365V1
3.18
Touch sensing controller (TSC)
The STM32F334x4/6/8 devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 18 capacitive sensing channels
distributed over 6 analog I/Os group.
Capacitive sensing technology is able to detect the presence of a finger near an electrode
that is protected from direct touch by a dielectric (glass, plastic and others). The capacitive
DS9994 Rev 9
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46
Functional overview
STM32F334x4 STM32F334x6 STM32F334x8
variation introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the electrode capacitance and then transferring a part of the accumulated charges
into a sampling capacitor, until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 10. Capacitive sensing GPIOs available on STM32F334x4/6/8 devices
Group
Capacitive sensing group name
Pin name
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
PA0
PA1
1
PA2
PA3
PA4
PA5
2
3
4
5
6
PA6
PA7
PC5
PB0
PB1
PB2
PA9
PA10
PA13
PA14
PB3
PB4
PB6
PB7
PB11
PB12
PB13
PB14
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Functional overview
Table 11. No. of capacitive sensing channels available on STM32F334x4/6/8 devices
Number of capacitive sensing channels
Analog I/O group
STM32F334xRx
STM32F334xCx
STM32F334xKx
G1
G2
G3
G4
G5
G6
3
3
3
3
3
3
3
3
2
3
3
3
3
3
2
3
3
0
Total number of capacitive
sensing channels
18
17
14
3.19
Development support
3.19.1
Serial-wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
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46
Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
4
Pinout and pin descriptions
Figure 4. LQFP32 pinout
32 31 30 29 28 27 26 25
VDD
PF0/OSC_IN
PF1/OSC_OUT
NRST
1
2
3
4
5
6
24 PA14
23 PA13
22 PA12
21 PA11
20 PA10
19 PA9
18 PA8
17 VDD
LQFP32
VDDA/VREF+
PA0
PA1
7
8
PA2
9
10 11 12 13 14 15 16
MS31949V3
1. The above figure shows the package top view.
Figure 5. LQFP48 pinout
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
36
35
34
33
32
31
VBAT
PC13
VDD
VSS
PC14/OSC32_IN
PC15/OSC32_OUT
PF0/OSC_IN
PF1/OSC_OUT
NRST
PA13
PA12
PA11
PA10
LQFP48
7
8
30
29
28
27
26
25
PA9
PA8
VSSA/VREF-
VDDA/VREF+
PA0
9
PB15
PB14
PB13
PB12
10
11
12
PA1
PA2
13 14 15 16 17 18 19 20 21 22 23 24
MSv36901V2
1. The above figure shows the package top view.
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Pinout and pin descriptions
Figure 6. LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
VDD
VSS
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
1
2
3
4
5
6
VBAT
PC13
PC14/OSC32_IN
PC15/OSC32_OUT
PF0/OSC_IN
PF1/OSC_OUT
NRST
42
41
40
39
38
37
36
35
34
33
7
8
9
10
11
12
13
14
15
16
LQFP64
PC0
PC1
PC2
PC3
PC6
VSSA/VREF-
VDDA/VREF+
PA0
PB15
PB14
PB13
PB12
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MS31951V2
1. The above figure shows the package top view.
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46
Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
Figure 7. WLCSP49 ballout
6
2
4
5
7
3
1
BOOT0
PB7
PB6
PB5
PB9
PB8
PA15
VDD
PA13
VDD
VSS
PB3
PB4
PA14
VSS
A
B
C
PF1
OSC_OUT
PF0
OSC_IN
PA10
PC3
PA2
PA12
PA11
D
PA9
PB15
PC7
PA6
PA7
PC4
PA0
NRST
PA8
PB14
PB12
VSSA
VREF-
PB13
PB2
PC5
PB0
PA3
PA4
VDDA
VSS
E
F
VREF+
PA1
G
PB1
VDD
PB11
PB10
PA5
MSv44311V1
1. The above figure shows the package top view.
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Pinout and pin descriptions
Figure 8. UFQFPN32 pinout
32 31 30 29 28 27 26 25
VDD
1
2
3
24
23
22
21
20
19
PA14
PA13
PF0/OSC_IN
PF1/OSC_OUT
PA12
PA11
4
5
6
NRST
UFQFPN32
VDDA/VREF+
PA10
PA9
VSSA/VREF-
PA0
7
8
PA8
18
17
PA1
VDD
9
10 11 12 13 14 15 16
MSv44312V2
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46
Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
Definition
Table 12. Legend/abbreviations used in the pinout table
Name
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
FTf
TTa
TT
TC
B
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
3.3 V tolerant I/O directly connected to ADC
3.3 V tolerant I/O
I/O structure
Notes
Standard 3.3 V I/O
Dedicated BOOT0 pin
RST
Bi-directional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 13. STM32F334x4/6/8 pin definitions
Pin Number
Pin functions
Pin name
(function after
Alternate
functions
Additional functions
reset)
-
-
-
1
2
1
2
-
-
VBAT
S
-
Backup power supply
RTC_TAMP1/RTC_TS/
RTC_OUT/WKUP2
(1)
-
PC13
I/O
TC
TIM1_CH1N
(1)
-
-
-
-
3
4
5
6
3
4
5
6
-
PC14 / OSC32_IN
I/O
I/O
I/O
I/O
TC
TC
FT
FT
-
OSC32_IN
OSC32_OUT
OSC_IN
(1)
-
PC15 / OSC32_OUT
-
2
3
2
3
C7
C6
PF0 / OSC_IN
TIM1_CH3N
-
PF1 / OSC_OUT
OSC_OUT
Device reset input / internal reset output
(active low)
4
-
4
-
7
-
7
8
D7
-
NRST
PC0
I/O
I/O
RST
TTa
EVENTOUT,
ADC12_IN6
TIM1_CH1
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Pinout and pin descriptions
Pin functions
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Alternate
functions
Additional functions
EVENTOUT,
TIM1_CH2
-
-
-
-
-
9
-
-
PC1
PC2
I/O
I/O
TTa
TTa
ADC12_IN7
ADC12_IN8
EVENTOUT,
TIM1_CH3
-
-
10
EVENTOUT,
TIM1_CH4,
TIM1_BKIN2
-
-
11
12
C5
PC3
I/O
TTa
ADC12_IN9
6
-
-
-
8
-
E7
F7
E6
-
VSSA/VREF-
VREF+
S
S
S
S
-
-
-
-
Analog ground/Negative reference voltage
-
-
-
-
VDDA
5
7
5
6
9
13
14
VDDA/VREF+
Analog power supply/Positive reference voltage
TIM2_CH1/
TIM2_ETR,
TSC_G1_IO1,
USART2_CTS,
EVENTOUT
(2)
ADC1_IN1
,
10
D6
G7
PA0
PA1
I/O
I/O
TTa
TTa
RTC_TAMP2/WKUP1
TIM2_CH2,
TSC_G1_IO2,
USART2_RTS_DE,
TIM15_CH1N,
EVENTOUT
(2)
8
9
7
8
9
11
12
13
15
16
17
ADC1_IN2 , RTC_REFIN
TIM2_CH3,
TSC_G1_IO3,
USART2_TX,
COMP2_OUT,
TIM15_CH1,
EVENTOUT
(2)
D5
E5
PA2
PA3
I/O
I/O
TTa
TTa
ADC1_IN3 , COMP2_INM
TIM2_CH4,
TSC_G1_IO4,
USART2_RX,
TIM15_CH2,
EVENTOUT
(2)
10
ADC1_IN4
-
-
-
-
-
-
18
19
F6
VSS
VDD
S
S
-
-
-
-
-
-
G6
TIM3_CH2,
TSC_G2_IO1,
SPI1_NSS,
USART2_CK,
EVENTOUT
(2)
ADC2_IN1 , DAC1_OUT1,
(3)
11
12
10
11
14
15
20
21
F5
PA4
I/O
I/O
TTa
TTa
COMP2_INM, COMP4_INM,
COMP6_INM
TIM2_CH1/
TIM2_ETR,
TSC_G2_IO2,
SPI1_SCK,
EVENTOUT
(2)
ADC2_IN2 , DAC1_OUT2,
(3)
G5
PA5
OPAMP2_VINM
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Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
Pin functions
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Alternate
Additional functions
functions
TIM16_CH1,
TIM3_CH1,
TSC_G2_IO3,
SPI1_MISO,
TIM1_BKIN,
OPAMP2_DIG,
EVENTOUT
(2)
ADC2_IN3 , DAC2_OUT1,
(3)
13
14
12
16
17
22
E4
F4
PA6
I/O
I/O
TTa
TTa
OPAMP2_VOUT
TIM17_CH1,
TIM3_CH2,
TSC_G2_IO4,
SPI1_MOSI,
TIM1_CH1N,
EVENTOUT
(2)
ADC2_IN4 , COMP2_INP,
13
23
PA7
OPAMP2_VINP
EVENTOUT,
TIM1_ETR,
USART1_TX
(2)
-
-
-
-
-
-
24
25
G4
E3
PC4
PC5
I/O
I/O
TTa
TTa
ADC2_IN5
EVENTOUT,
TIM15_BKIN,
TSC_G3_IO1,
USART1_RX
ADC2_IN11, OPAMP2_VINM
TIM3_CH3,
TSC_G3_IO2,
TIM1_CH2N,
EVENTOUT
ADC1_IN11, COMP4_INP,
OPAMP2_VINP
15
14
15
18
19
26
27
F3
PB0
PB1
I/O
I/O
TTa
TTa
TIM3_CH4,
TSC_G3_IO3,
TIM1_CH3N,
COMP4_OUT,
HRTIM1_SCOUT,
EVENTOUT
-
G3
ADC1_IN12
TSC_G3_IO4,
HRTIM_SCIN,
EVENTOUT
-
-
-
-
20
21
28
29
F2
PB2
I/O
I/O
TTa
TT
ADC2_IN12, COMP4_INM
TIM2_CH3,
TSC_SYNC,
USART3_TX,
HRTIM1_FLT3,
EVENTOUT
G2
PB10
-
TIM2_CH4,
TSC_G6_IO1,
USART3_RX,
HRTIM1_FLT4,
EVENTOUT
-
-
22
30
G1
PB11
I/O
TTa
COMP6_INP
16
17
16
17
23
24
31
32
-
VSS
VDD
S
S
-
-
Digital ground
Digital power supply
TSC_G6_IO2,
B2
TIM1_BKIN,
USART3_CK,
HRTIM1_CHC1,
EVENTOUT
-
-
25
26
33
34
F1
E2
PB12
PB13
I/O
I/O
TTa
TTa
ADC2_IN13
TSC_G6_IO3,
TIM1_CH1N,
USART3_CTS,
HRTIM1_CHC2,
EVENTOUT
-
ADC1_IN13
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Pinout and pin descriptions
Pin functions
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Alternate
functions
Additional functions
TIM15_CH1,
TSC_G6_IO4,
TIM1_CH2N,
USART3_RTS_DE,
HRTIM1_CHD1,
EVENTOUT
-
-
27
35
E1
PB14
I/O
TTa
ADC2_IN14, OPAMP2_VINP
TIM15_CH2,
TIM15_CH1N,
TIM1_CH3N,
HRTIM1_CHD2,
EVENTOUT
ADC2_IN15, COMP6_INM,
RTC_REFIN
-
-
-
-
28
36
37
D3
PB15
PC6
I/O
I/O
TTa
FT
EVENTOUT,
TIM3_CH1,
HRTIM1_EEV10,
COMP6_OUT
-
-
-
EVENTOUT,
TIM3_CH2,
HRTIM1_FLT5
-
-
-
-
-
-
-
-
-
38
39
40
D4
PC7
PC8
PC9
I/O
I/O
I/O
FT
FT
FT
-
-
-
EVENTOUT,
TIM3_CH3,
HRTIM1_CHE1
-
-
EVENTOUT,
TIM3_CH4,
HRTIM1_CHE2
MCO, TIM1_CH1,
USART1_CK,
HRTIM1_CHA1,
EVENTOUT
18
19
18
19
29
30
41
42
D1
D2
PA8
PA9
I/O
I/O
FT
FT
-
-
TSC_G4_IO1,
TIM1_CH2,
USART1_TX,
TIM15_BKIN,
TIM2_CH3,
HRTIM1_CHA2,
EVENTOUT
TIM17_BKIN,
TSC_G4_IO2,
TIM1_CH3,
USART1_RX,
COMP6_OUT,
TIM2_CH4,
20
20
31
43
C4
PA10
I/O
FT
-
HRTIM1_CHB1,
EVENTOUT
TIM1_CH1N,
USART1_CTS,
CAN_RX,
21
22
21
22
32
33
44
45
C1
C3
PA11
PA12
I/O
I/O
FT
FT
TIM1_CH4,
-
-
TIM1_BKIN2,
HRTIM1_CHB2,
EVENTOUT
TIM16_CH1,
TIM1_CH2N,
USART1_RTS_DE,
COMP2_OUT,
CAN_TX,TIM1_ETR,
HRTIM1_FLT1,
EVENTOUT
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Pinout and pin descriptions
STM32F334x4 STM32F334x6 STM32F334x8
Pin functions
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Alternate
Additional functions
functions
JTMS/SWDAT,
TIM16_CH1N,
TSC_G4_IO3,
IR_OUT,
USART3_CTS,
EVENTOUT
23
23
34
46
C2
PA13
I/O
FT
-
-
-
-
-
35
36
47
48
B1
-
VSS
VDD
S
S
-
-
-
-
-
-
JTCK/SWCLK,
TSC_G4_IO4,
I2C1_SDA,
TIM1_BKIN,
USART2_TX,
EVENTOUT
24
24
37
49
A1
PA14
I/O
FTf
-
JTDI,
TIM2_CH1/TIM2_ET
R, TSC_SYNC,
I2C1_SCL,
25
25
38
50
A2
PA15
I/O
FTf
SPI1_NSS,
-
USART2_RX,
TIM1_BKIN,
HRTIM1_FLT2,
EVENTOUT
EVENTOUT,
USART3_TX
-
-
-
-
-
-
51
52
-
-
PC10
PC11
I/O
I/O
FT
FT
-
-
EVENTOUT,
HRTIM1_EEV2,
USART3_RX
EVENTOUT,
HRTIM1_EEV1,
USART3_CK
-
-
-
-
-
-
53
54
-
-
PC12
PD2
I/O
I/O
FT
FT
-
-
EVENTOUT,
TIM3_ETR
JTDO/TRACE
SWO, TIM2_CH2,
TSC_G5_IO1,
SPI1_SCK,
26
26
39
55
A3
PB3
I/O
FT
USART2_TX,
TIM3_ETR,
-
HRTIM1_SCOUT,
HRTIM1_EEV9,
EVENTOUT
NJTRST,
TIM16_CH1,
TIM3_CH1,
TSC_G5_IO2,
SPI1_MISO,
USART2_RX,
TIM17_BKIN,
HRTIM1_EEV7,
EVENTOUT
27
27
40
56
B3
PB4
I/O
FT
-
40/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Pinout and pin descriptions
Pin functions
Table 13. STM32F334x4/6/8 pin definitions (continued)
Pin Number
Pin name
(function after
reset)
Alternate
functions
Additional functions
TIM16_BKIN,
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI,
USART2_CK,
TIM17_CH1,
HRTIM1_EEV6,
EVENTOUT
28
29
28
41
42
57
B4
A4
PB5
PB6
I/O
I/O
FT
-
TIM16_CH1N,
TSC_G5_IO3,
I2C1_SCL,
USART1_TX,
HRTIM1_SCIN,
HRTIM1_EEV4,
EVENTOUT
29
58
FTf
-
TIM17_CH1N,
TSC_G5_IO4,
I2C1_SDA,
30
31
30
31
43
44
59
60
B5
A5
PB7
I/O
FTf
B
USART1_RX,
TIM3_CH4,
HRTIM1_EEV3,
EVENTOUT
-
-
BOOT0
I
-
TIM16_CH1,
TSC_SYNC,
I2C1_SCL,
USART3_RX,
CAN_RX,
TIM1_BKIN,
HRTIM1_EEV8,
EVENTOUT
-
-
-
-
45
46
61
62
B6
A6
PB8
PB9
I/O
I/O
FTf
FTf
-
-
TIM17_CH1,
I2C1_SDA, IR_OUT,
USART3_TX,
COMP2_OUT,
CAN_TX,
HRTIM1_EEV5,
EVENTOUT
32
1
32
1
47
48
63
64
B7
A7
VSS
VDD
S
S
-
-
-
-
-
-
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of
GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup
registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP
register description sections in the reference manual.
2. Fast ADC channel.
3. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.
DS9994 Rev 9
41/125
46
Table 14. Alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
TIM1
AF12
AF13
AF14
-
AF15
Port
TIM2/TIM15/
TIM16/TIM17/
EVENT
TIM1/TIM3/
TIM15/
TIM16
USART1/USA
RT2/USART3/
GPCOMP6
GPCOMP2/
GPCOMP4/
GPCOMP6
SPI1/
Infrared
TIM1/
Infrared
CAN/TIM1/
TIM15
TIM2/TIM3/TI
M17
HRTIM1/
TIM1
HRTIM1/
OPAMP2
SYS_AF
HRTIM1/TSC
I2C1/TIM1
EVENT
TIM2_CH1/TI
M2_ETR
PA0
-
-
-
-
TSC_G1_IO1
TSC_G1_IO2
-
-
-
-
-
-
USART2_CTS
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
USART2_RTS
_DE
PA1
TIM2_CH2
TIM15_CH1N
PA2
PA3
PA4
-
-
-
TIM2_CH3
TIM2_CH4
-
-
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
-
-
-
-
-
-
-
USART2_TX
USART2_RX
USART2_CK
COMP2_OUT
TIM15_CH1
TIM15_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
-
-
-
TIM3_CH2
SPI1_NSS
TIM2_CH1/TI
M2_ETR
PA5
-
-
TSC_G2_IO2
-
SPI1_SCK
-
-
-
-
-
-
-
-
-
EVENTOUT
PA6
PA7
PA8
PA9
PA10
PA11
-
TIM16_CH1
TIM3_CH1
TSC_G2_IO3
-
-
-
-
-
-
SPI1_MISO
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH1N
-
-
-
-
-
-
OPAMP2_DIG
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
TIM17_CH1
TIM3_CH2
TSC_G2_IO4
SPI1_MOSI
-
-
-
-
-
-
Port A
MCO
-
-
-
-
-
-
-
-
-
-
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
-
-
TIM15_BKIN
-
-
-
-
HRTIM1_CHA1
HRTIM1_CHA2
HRTIM1_CHB1
HRTIM1_CHB2
-
-
-
-
TSC_G4_IO1
TSC_G4_IO2
-
-
TIM2_CH3
TIM2_CH4
-
-
-
TIM17_BKIN
-
COMP6_OUT
-
-
-
CAN_RX
TIM1_CH4
TIM1_BKIN2
USART1_RTS
_DE
PA12
-
TIM16_CH1
-
-
-
-
TIM1_CH2N
COMP2_OUT
CAN_TX
-
TIM1_ETR
-
HRTIM1_FLT1
-
EVENTOUT
PA13
PA14
JTMS/SWDAT TIM16_CH1N
-
-
TSC_G4_IO3
TSC_G4_IO4
-
IR_OUT
-
-
USART3_CTS
USART2_TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
JTCK/SWCLK
JTDI
-
I2C1_SDA
TIM1_BKIN
TIM2_CH1/
TIM2_ETR
PA15
-
TSC_SYNC
I2C1_SCL
SPI1_NSS
-
USART2_RX
-
TIM1_BKIN
-
-
-
HRTIM1_FLT2
-
EVENTOUT
PB0
PB1
PB2
-
-
-
-
-
-
TIM3_CH3
TIM3_CH4
-
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
-
-
-
-
-
-
TIM1_CH2N
TIM1_CH3N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
COMP4_OUT
-
HRTIM1_SCOUT
HRTIM1_SCIN
JTDO/TRACE
SWO
HRTIM1_
SCOUT
PB3
TIM2_CH2
-
TSC_G5_IO1
-
SPI1_SCK
-
USART2_TX
-
-
TIM3_ETR
-
HRTIM1_EEV9
-
EVENTOUT
PB4
PB5
NJTRST
-
TIM16_CH1
TIM16_BKIN
TIM3_CH1
TIM3_CH2
TSC_G5_IO2
-
-
SPI1_MISO
SPI1_MOSI
-
-
USART2_RX
USART2_CK
-
-
-
-
TIM17_BKIN
TIM17_CH1
-
-
-
-
HRTIM1_EEV7
HRTIM1_EEV6
-
-
EVENTOUT
EVENTOUT
Port B
I2C1_SMBA
HRTIM1_
SCIN
PB6
-
TIM16_CH1N
-
TSC_G5_IO3
I2C1_SCL
-
-
USART1_TX
-
-
-
-
HRTIM1_EEV4
-
EVENTOUT
PB7
PB8
PB9
-
-
-
TIM17_CH1N
TIM16_CH1
TIM17_CH1
-
-
-
TSC_G5_IO4
I2C1_SDA
I2C1_SCL
I2C1_SDA
-
-
-
-
USART1_RX
USART3_RX
USART3_TX
-
-
TIM3_CH4
-
-
-
-
HRTIM1_EEV3
HRTIM1_EEV8
HRTIM1_EEV5
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
TSC_SYNC
-
-
-
CAN_RX
CAN_TX
-
-
TIM1_BKIN
-
IR_OUT
COMP2_OUT
Table 14. Alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
TIM1
AF12
AF13
AF14
-
AF15
Port
TIM2/TIM15/
TIM16/TIM17/
EVENT
TIM1/TIM3/
TIM15/
TIM16
USART1/USA
RT2/USART3/
GPCOMP6
GPCOMP2/
GPCOMP4/
GPCOMP6
SPI1/
Infrared
TIM1/
Infrared
CAN/TIM1/
TIM15
TIM2/TIM3/TI
M17
HRTIM1/
TIM1
HRTIM1/
OPAMP2
SYS_AF
HRTIM1/TSC
I2C1/TIM1
EVENT
PB10
-
-
-
-
TIM2_CH3
-
-
-
-
TSC_SYNC
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
-
-
-
-
-
-
-
-
-
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HRTIM1_FLT3
HRTIM1_FLT4
HRTIM1_CHC1
HRTIM1_CHC2
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PB11
PB12
PB13
TIM2_CH4
-
-
-
TIM1_BKIN
TIM1_CH1N
Port B
USART3_RTS
_DE
PB14
-
TIM15_CH1
-
TSC_G6_IO4
-
-
TIM1_CH2N
-
-
-
-
-
HRTIM1_CHD1
-
EVENTOUT
PB15
PC0
-
-
-
-
-
-
-
-
TIM15_CH2
EVENTOUT
-
TIM15_CH1N
TIM1_CH1
-
-
TIM1_CH3N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HRTIM1_CHD2
-
-
-
-
-
-
-
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC2
PC3
PC4
PC5
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TIM1_CH3
TIM1_CH4
TIM1_ETR
TIM15_BKIN
-
-
-
-
TIM1_BKIN2
-
-
-
-
USART1_TX
USART1_RX
TSC_G3_IO1
HRTIM1_
EEV10
PC6
-
EVENTOUT
TIM3_CH1
-
-
-
COMP6_OUT
-
-
-
-
-
-
-
-
PC7
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
TIM3_CH2
HRTIM1_FLT5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port C
PC8
EVENTOUT
TIM3_CH3
HRTIM1_CHE1
-
-
-
PC9
EVENTOUT
TIM3_CH4
HRTIM1_CHE2
-
-
-
PC10
PC11
PC12
PC13
PC14
PC15
PD2
EVENTOUT
-
-
-
-
USART3_TX
EVENTOUT
-
HRTIM1_EEV2
-
-
USART3_RX
EVENTOUT
-
HRTIM1_EEV1
-
-
USART3_CK
-
-
-
-
-
-
-
-
TIM1_CH1N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port D
Port F
EVENTOUT
TIM3_ETR
-
PF0
-
-
-
-
TIM1_CH3N
-
PF1
Memory mapping
STM32F334x4 STM32F334x6 STM32F334x8
5
Memory mapping
Figure 9. STM32F334x4/6/8 memory map
0x5000 03FF
AHB3
0xFFFF FFFF
0x5000 0000
Cortex-M4
with FPU
Internal
Reserved
7
0xE000 0000
6
0x4800 1800
0x4800 0000
Peripherals
AHB2
Reserved
AHB1
0x4002 43FF
0x4002 0000
0xC000 0000
Reserved
5
0x4001 6C00
0x4001 0000
APB2
Reserved
APB1
0xA000 0000
4
0x4000 A000
0x4000 0000
0x8000 0000
3
0x1FFF FFFF
0x1FFF F800
Option bytes
0x6000 0000
System memory
2
0x1FFF D800
0x1000 1000
Reserved
CCM RAM
Reserved
Peripherals
0x4000 0000
0x1000 0000
0x0801 0000
1
SRAM
CODE
0x2000 0000
Flash memory
0x0800 0000
0x0001 0000
0
Reserved
Flash, system
memory or SRAM,
depending on BOOT
configuration
0x0000 0000
Reserved
0x0000 0000
MSv33150V1
44/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Memory mapping
-
Table 15. STM32F334x4/6/8 peripheral register boundary addresses
Size
(bytes)
Bus
Boundary address
Peripheral
AHB3
0x5000 0000 - 0x5000 03FF
0x4800 1800 - 0x4FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 1000 - 0x4800 13FF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
0x4001 7400 - 0x4001 77FF
0x4001 4C00 - 0x4001 73FF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 0800 - 0x4001 2BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 9C00 - 0x4000 FFFF
1 K
~132 M
1 K
ADC1 - ADC2
-
AHB2
-
Reserved
GPIOF
1 K
Reserved
GPIOD
1 K
1 K
GPIOC
AHB2
-
1 K
GPIOB
1 K
GPIOA
~128 M
1 K
Reserved
TSC
3 K
Reserved
CRC
1 K
3 K
Reserved
Flash interface
Reserved
RCC
AHB1
1 K
3 K
1 K
3 K
Reserved
DMA1
1 K
-
32 K
1 K
Reserved
HRTIM1
Reserved
TIM17
APB2
12 K
1 K
1 K
TIM16
1 K
TIM15
1 K
Reserved
USART1
Reserved
SPI1
1 K
APB2
1 K
1 K
1 K
TIM1
9 K
Reserved
EXTI
1 K
1 K
SYSCFG + COMP + OPAMP
Reserved
-
25 K
DS9994 Rev 9
45/125
46
Memory mapping
STM32F334x4 STM32F334x6 STM32F334x8
Table 15. STM32F334x4/6/8 peripheral register boundary addresses (continued)
Size
Bus
Boundary address
Peripheral
(bytes)
0x4000 9800 - 0x4000 9BFF
0x4000 7800 - 0x4000 97FF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6800 - 0x4000 6FFF
0x4000 6400 - 0x4000 67FF
0x4000 5800 - 0x4000 63FF
0x4000 5400 - 0x4000 57FF
0x4000 4C00 - 0x4000 53FF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 3400 - 0x4000 43FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1800 - 0x4000 27FF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0800 - 0x4000 0FFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
0x2000 3000 - 3FFF FFFF
0x2000 0000 - 0x2000 2FFF
0x1FFF F800 - 0x1FFF FFFF
0x1FFF D800 - 0x1FFF F7FF
0x1000 2000 - 0x1FFF D7FF
0x1000 0000 - 0x1000 0FFF
0x0804 0000 - 0x0FFF FFFF
0x0800 0000 - 0x0800 FFFF
0x0004 0000 - 0x07FF FFFF
1 K
8 K
DAC2
Reserved
DAC1
1 K
1 K
PWR
2 K
Reserved
bxCAN
1 K
3 K
Reserved
I2C1
1 K
2 K
Reserved
USART3
USART2
Reserved
IWDG
1 K
APB1
1 K
2 K
1 K
1 K
WWDG
1 K
RTC
4 K
Reserved
TIM7
1 K
1 K
TIM6
2 K
Reserved
TIM3
1 K
1 K
TIM2
-
-
-
-
-
-
-
-
-
~512 M
12 K
2 K
Reserved
SRAM
Option bytes
System memory
Reserved
CCM RAM
Reserved
Main Flash memory
Reserved
8 K
~256 M
4 K
~128 M
64 K
~128 M
Main Flash memory, system
memory or SRAM depending
on BOOT configuration
-
0x0000 000 - 0x0000 FFFF
64 K
46/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V, V
3.3 V. They are given only as design guidelines and are not tested.
=
A
DD
DDA
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Input voltage on a pin
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19211V1
MS19210V1
DS9994 Rev 9
47/125
103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
6.1.6
Power-supply scheme
Figure 12. Power-supply scheme
V
BAT
Backup circuitry
(LSE, RTC,
Power
switch
1.65 - 3.6V
Wake-up logic
Backup registers)
OUT
IN
I/O
Logic
GPIOs
Kernel logic
(CPU,
digital
V
DD
& memories)
4 x V
DD
Regulator
4 x 100 nF
+ 1 x 4.7 μF
4 x V
SS
V
DDA
V
DDA
10 nF
+ 1 μF
Analog such as RCs, PLL,
comparators, OPAMP
V
V
ADC/
DAC
REF+
REF-
V
SSA
MS31954V1
Caution:
Each power-supply pair (V /V , V
/V
etc..) must be decoupled with filtering
DD SS
DDA SSA
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to or below the appropriate pins on the underside of the PCB, to ensure the good
functionality of the device.
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Electrical characteristics
6.1.7
Measurement of the current consumption
Figure 13. Scheme of the current-consumption measurement
I
DD_VBAT
V
BAT
I
DD
V
DD
I
DDA
V
DDA
MS19213V1
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STM32F334x4 STM32F334x6 STM32F334x8
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics,
Table 17: Current characteristics, and Table 18: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect the device reliability.
(1)
Table 16. Voltage characteristics
Symbol
Ratings
Min.
Max.
Unit
External main supply voltage (including VDDA, VBAT
VDD–VSS
-0.3
4.0
and VDD
)
VDD–VDDA
Allowed voltage difference for VDD > VDDA
Input voltage on FT and FTf pins
-
0.4
VSS −0.3
VDD + 4.0
V
Input voltage on TTa and TT pins
VSS −0.3
4.0
4.0
9
(2)
VIN
Input voltage on any other pin
VSS −0.3
Input voltage on Boot0 pin
0
-
|ΔVDDx
|
Variations between different VDD power pins
Variations between all the different ground pins(3)
50
50
mV
-
|VSSX −VSS
|
-
see Section 6.3.12: Electrical
sensitivity characteristics
VESD(HBM)
Electrostatic discharge voltage (human body model)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range. The following relationship must be respected between VDDA and VDD
VDDA must power on before or at the same time as VDD in the power up sequence.
:
V
DDA must be greater than or equal to VDD.
2. VIN maximum must always be respected. Refer to Table 17: Current characteristics for the maximum allowed injected
current values.
3. Include VREF- pin.
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Electrical characteristics
Table 17. Current characteristics
Symbol
Ratings
Max.
Unit
ΣIVDD
ΣIVSS
IVDD
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power line (source)(1)
Maximum current out of each VSS _x ground line (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on TT, FT, FTf and B pins(3)
140
-140
100
100
25
IVSS
IIO(PIN)
-25
80
mA
ΣIIO(PIN)
-80
-5 /+0
±5
IINJ(PIN)
Injected current on TC and RST pin(4)
Injected current on TTa pins(5)
±5
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(6)
±25
1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer to Table 16: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 16: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note 2.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 18. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
TSTG
TJ
–65 to +150
150
°C
°C
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STM32F334x4 STM32F334x6 STM32F334x8
6.3
Operating conditions
6.3.1
General operating conditions
Table 19. General operating conditions
Symbol
Parameter
Conditions
Min.
Max.
Unit
fHCLK
fPCLK1
fPCLK2
VDD
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
-
-
-
-
0
0
0
2
72
36
72
3.6
MHz
Core, SRAM and Flash memory
power supply
VDD18
-
1.65
2
1.95
3.6
V
V
V
Analog operating voltage
(OPAMP and DAC not used)
Must have a potential equal to
or higher than VDD
VDDA
Analog operating voltage
(OPAMP and DAC used)
2.4
3.6
VBAT
Backup operating voltage
I/O input voltage
-
1.65
–0.3
-0.3
–0.3
–0.3
0
3.6
TC I/O
V
DD+0.3
3.6
TT I/O
TTa I/O
VDDA+0.3
5.5
VIN
FT and FTf I/O(1)
BOOT0
5.5
LQFP64
-
444
364
333
540
414
85
mW
mW
mW
mW
mW
LQFP48
-
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix
7(2)
PD
LQFP32
-
UFQFPN32
-
WLCSP49
-
Maximum power dissipation
Low power dissipation(3)
Maximum power dissipation
Low power dissipation(3)
6 suffix version
7 suffix version
–40
–40
–40
–40
–40
–40
Ambient temperature for 6 suffix
version
°C
°C
°C
105
105
125
105
125
TA
TJ
Ambient temperature for 7 suffix
version
Junction temperature range
1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 81: Package thermal
characteristics).
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.7:
Thermal characteristics).
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6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 20 are derived from tests performed under the ambient
temperature condition summarized in Table 19.
Table 20. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min.
Max.
Unit
VDD rise time rate
0
20
0
∞
∞
∞
∞
tVDD
-
VDD fall time rate
µs/V
VDDA rise time rate
VDDA fall time rate
tVDDA
-
20
6.3.3
Characteristics of the embedded reset and power-control block
The parameters given in Table 21 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 19.
DD
Table 21. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Falling edge
Rising edge
Min. Typ. Max. Unit
1.8(2) 1.88 1.96
1.84 1.92 2.0
V
V
Power on/power down
reset threshold
(1)
VPOR/PDR
(1)
VPDRhyst
PDR hysteresis
-
-
-
40
-
mV
POR reset
temporization
(3)
tRSTTEMPO
1.5 2.5
4.5
ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD
.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 22. Programmable voltage detector characteristics
Symbol
Parameter
Conditions
Rising edge
Min.(1) Typ. Max.(1) Unit
2.1
2
2.18
2.08
2.26
2.16
2.37
2.27
2.48
2.38
2.58
2.48
2.69
2.59
2.79
2.69
2.9
VPVD0
PVD threshold 0
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.19 2.28
2.09 2.18
2.28 2.38
2.18 2.28
2.38 2.48
2.28 2.38
2.47 2.58
2.37 2.48
2.57 2.68
2.47 2.58
2.66 2.78
2.56 2.68
2.76 2.88
2.66 2.78
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
VPVD7
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
V
2.8
3
PVD threshold 7
PVD hysteresis
2.9
(2)
VPVDhyst
-
-
-
-
100
0.15
-
mV
µA
PVD current
consumption
IDD(PVD)
0.26
1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 23 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 19.
DD
Table 23. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
VREFINT
Internal reference voltage –40 °C < TA < +105 °C 1.20 1.23
ADC sampling time when
1.25
-
V
TS_vrefint
reading the internal
reference voltage
-
2.2
-
µs
Internal reference voltage
spread over the
temperature range
VRERINT
TCoeff
VDD = 31.8 V ±10 mV
-
-
-
-
-
10(1)
mV
Temperature coefficient
100(1) ppm/°C
1. Guaranteed by design, not tested in production.
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Table 24. Internal reference voltage calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 30 °C
VDDA= 3.3 V
VREFINT_CAL
0x1FFF F7BA - 0x1FFF F7BB
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Scheme of the current-
consumption measurement.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Note:
The total current consumption is the sum of the IDD and IDDA values.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f frequency (0 wait state from 0
HCLK
to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
•
•
•
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f
= f
and f
= f
PCLK1 HCLK/2
PCLK2
HCLK
When f
> 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HCLK
HSE (8 MHz) in bypass mode.
The parameters given in Table 25 to Table 29 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 19.
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STM32F334x4 STM32F334x6 STM32F334x8
Table 25. Typical and maximum current consumption from V supply at V = 3.6V
DD
DD
All peripherals enabled
All peripherals disabled
(1)
(1)
Symbol Parameter Conditions fHCLK
Max. @ TA
Max. @ TA
Unit
Typ.
Typ.
25 °C 85 °C 105 °C
25 °C 85 °C 105 °C
72 MHz 71.4
77.9
70.6
56.6
38.6
30.2
14.1
8.9
79.1
71.3
57.1
38.9
30.4
14.3
9.1
80.0
71.5
57.7
39.2
30.6
14.4
9.5
27.1 32.2
24.2 27.0
18.7 21.4
12.9 14.6
10.0 11.1
32.4
27.5
21.6
14.9
11.2
4.4
32.4
27.7
21.9
15.9
12.3
5.1
64 MHz 63.9
48 MHz 49.5
External
clock (HSE 32 MHz 34.0
bypass)
Supply
24 MHz 25.9
current in
Run mode,
executing
from Flash
8 MHz
1 MHz
9.3
3.5
3.3
0.7
4.0
0.9
1.0
1.2
64 MHz 61.6
48 MHz 48.1
32 MHz 33.3
24 MHz 25.7
68.1
54.6
37.8
29.8
12.2
77.8
70.5
56.5
37.7
28.8
13.2
7.6
68.8
54.8
37.9
29.8
12.3
78.7
70.7
56.9
37.9
29.0
13.3
7.8
70.1
55.1
38.0
30.0
12.8
78.9
70.9
57.4
38.0
29.2
13.8
8.0
24.1 27.0
18.6 21.6
12.7 14.4
10.0 11.1
27.1
21.7
14.9
11.2
4.2
27.2
21.9
16.0
12.3
5.0
Internal
clock (HSI)
8 MHz
9.7
3.4
3.8
IDD
mA
72 MHz 71.3
64 MHz 63.8
48 MHz 49.3
27.6 32.1
24.5 27.2
18.1 21.6
12.9 14.9
32.2
27.6
21.8
14.9
11.3
4.0
32.3
27.7
21.8
15.9
11.5
4.6
External
clock (HSE 32 MHz 33.9
bypass)
Supply
24 MHz 25.8
9.8
3.2
0.3
11.1
3.6
current in
Run mode,
executing
from RAM
8 MHz
1 MHz
9.0
3.2
0.4
0.8
1.2
64 MHz 61.3
48 MHz 48.0
32 MHz 33.1
24 MHz 25.6
66.9
52.4
35.6
28.5
11.6
58.7
52.7
40.6
28.8
23.2
11.5
7.4
67.3
52.6
35.8
28.7
11.6
61.1
54.5
41.7
29.2
23.7
11.7
7.7
67.8
53.1
36.6
28.8
11.7
61.9
54.8
41.8
29.5
23.9
11.9
7.9
24.1 26.9
19.1 21.6
12.6 14.8
27.0
21.6
14.9
11.3
4.1
27.1
22.1
15.9
11.5
4.7
Internal
clock (HSI)
9.8
3.0
7.0
6.3
4.6
3.0
2.4
0.6
0.3
5.4
4.3
2.9
1.3
0.5
11.1
3.1
7.3
6.7
5.1
3.3
2.5
0.9
0.3
6.5
4.7
3.1
1.7
0.7
8 MHz
9.7
72 MHz 55.5
64 MHz 49.8
48 MHz 38.5
8.4
8.5
7.0
7.8
5.6
5.9
External
clock (HSE 32 MHz 26.9
4.0
4.5
Supply
current in
Sleep
bypass)
24 MHz 19.1
3.2
3.8
8 MHz
1 MHz
7.1
3.0
1.2
2.1
IDD
mode,
mA
0.4
1.2
executing
from Flash
or RAM
64 MHz 47.7
48 MHz 35.0
32 MHz 23.7
24 MHz 18.5
52.4
40.4
27.7
23.8
9.6
52.6
40.6
28.3
24.0
9.7
52.8
40.8
28.8
24.2
9.7
6.8
7.5
5.2
5.7
Internal
clock (HSI)
3.2
4.4
2.2
2.7
8 MHz
7.5
1.1
2.0
1. Data based on characterization results, not tested in production unless otherwise specified.
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Electrical characteristics
Table 26. Typical and maximum current consumption from the V
supply
DDA
VDDA = 2.4 V
VDDA = 3.6 V
Conditions
(2)
(2)
Symbol Parameter
fHCLK
Max. @ TA
Max. @ TA
Unit
(1)
Typ.
Typ.
25 °C 85 °C 105 °C
25 °C 85 °C 105 °C
72 MHz 224
64 MHz 196
48 MHz 147
32 MHz 100
24 MHz 79
252
225
174
126
102
5
265
237
183
133
107
5
269
241
186
135
108
6
245
214
159
109
85
272
243
186
133
108
6
288
257
196
142
113
6
295
263
201
145
116
7
HSE
bypass
Supply
current in
Run/Sleep
mode,
code
8 MHz
1 MHz
3
3
4
IDDA
µA
5
5
6
3
5
6
6
executing
from Flash
or RAM
64 MHz 259
48 MHz 208
288
239
190
168
85
304
251
198
175
88
309
254
202
178
89
285
230
179
155
71
315
258
206
181
94
332
271
216
188
96
338
277
219
191
98
HSI clock 32 MHz 162
24 MHz 140
8 MHz
62
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
2. Data based on characterization results, not tested in production.
Table 27. Typical and maximum V consumption in Stop and Standby modes
DD
Typ. @VDD (VDD=VDDA
)
Max.(1)
Symbol Parameter
Conditions
Unit
TA = TA = TA =
25 °C 85 °C 105 °C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in run
mode, all
oscillators OFF
17.51 17.68 17.84 18.17 18.57 19.39 30.6 232.5 612.2
Supply
current in
Stop mode
Regulator in low-
power mode, all 6.44 6.51 6.60 6.73 6.96 7.20 20.0 246.4 585.0
oscillators OFF
IDD
µA
LSI ON and
IWDG ON
Supply
current in
Standby
mode
0.73 0.89 1.02 1.14 1.28 1.44
0.55 0.66 0.75 0.85 0.93 1.01
-
-
-
LSI OFF and
IWDG OFF
4.9
7.0
7.9
1. Data based on characterization results, not tested in production unless otherwise specified.
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Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
consumption in Stop and Standby modes
Table 28. Typical and maximum V
DDA
Typ. @VDD (VDD = VDDA
)
Max.(1)
Symbo
l
Uni
t
Parameter
Conditions
TA = TA = TA =
25 °C 85 °C 105 °C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in
run/low-power
mode, all
Supply
current in
Stop mode
1.67 1.79 1.91 2.04 2.19 2.35
2.5
5.9
6.2
oscillators OFF
LSI ON and
IWDG ON
Supply
current in
Standby
mode
2.06 2.24 2.41 2.60 2.80 3.04
1.54 1.68 1.78 1.92 2.06 2.22
-
-
-
LSI OFF and
IWDG OFF
2.6
3.0
3.8
IDDA
µA
Regulator in
run/low-power
mode, all
Supply
current in
Stop mode
0.97 0.99 1.03 1.07 1.14 1.22
-
-
-
oscillators OFF
LSI ON and
IWDG ON
Supply
current in
Standby
mode
1.36 1.44 1.52 1.62 1.76 1.91
0.86 0.88 0.91 0.95 1.03 1.09
-
-
-
-
-
-
LSI OFF and
IWDG OFF
1. Data based on characterization results, not tested in production.
Table 29. Typical and maximum current consumption from V
supply
BAT
Max.
@VBAT= 3.6V(2)
Typ.@VBAT
Para
meter
Conditions
Symbol
Unit
(1)
TA= TA=
TA=
1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V
25°C 85°C 105°C
LSE & RTC
ON; “Xtal
mode” lower
driving
capability;
LSEDRV[1:0]
= '00'
0.42 0.44 0.47 0.54 0.60 0.66 0.74 0.82
-
-
-
-
-
-
Backup
domain
supply
current
IDD_VBAT
µA
LSE & RTC
ON; “Xtal
mode” higher
driving
0.71 0.74 0.77 0.85 0.91 0.98 1.06 1.16
capability;
LSEDRV[1:0]
= '11'
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Data based on characterization results, not tested in production.
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Electrical characteristics
Figure 14. Typical V
current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’)
BAT
1.40
1.20
1.00
0.80
0.60
0.40
0.20
1.65 V
1.8 V
2 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
0.00
25°C
60°C
85°C
105°C
(
TA
°C)
MS34525V1
Typical current consumption
The MCU is placed under the following conditions:
•
•
•
V
= V
= 3.3 V
DDA
DD
All I/O pins available on each package are in analog input configuration
The Flash access time is adjusted to f frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash
prefetch is ON
HCLK
•
•
•
When the peripherals are enabled, f
= f
, f
= f
APB1
AHB/2 APB2 AHB
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8, 16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
•
Typical current consumption in Run mode, code with data processing running from
Flash
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STM32F334x4 STM32F334x6 STM32F334x8
Table 30. Typical current consumption in Run mode, code with data processing
running from Flash memory
Typ.
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals
enabled
Peripherals
disabled
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
70.6
60.3
46.0
31.3
25.0
16.2
8.4
25.2
22.6
17.3
12.0
9.3
Supply current in
Run mode from
VDD supply
6.5
IDD
mA
3.55
2.21
1.52
1.17
0.94
0.82
234.0
208.6
153.5
103.6
80.0
56.6
1.14
1.14
1.14
1.14
1.14
1.14
4 MHz
4.75
2.81
1.82
1.34
0.93
240.0
209.9
154.5
104.1
80.2
56.8
1.14
1.14
1.14
1.14
1.14
1.14
2 MHz
1 MHz
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
Running from HSE
crystal clock 8 MHz,
code executing from
Flash memory
Supply current in
Run mode from
VDDA supply
(1) (2)
IDDA
µA
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp and others, is not included. Refer to the tables of characteristics in the subsequent sections.
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Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ.
Symbol
Parameter
Conditions
fHCLK
Unit
Peripherals
enabled
Peripherals
disabled
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
51.8
46.4
35.0
23.7
18.0
12.2
6.2
6.3
5.7
4.40
3.13
2.49
1.85
0.99
0.88
0.80
0.76
0.74
0.72
236.7
207.8
152.9
103.2
79.8
56.6
1.14
1.14
1.14
1.14
1.14
1.14
Supply current in
Sleep mode from
VDD supply
IDD
mA
4 MHz
3.68
2.26
1.55
1.20
0.89
239.0
209.4
154.0
103.7
80.1
56.7
1.14
1.14
1.14
1.14
1.14
1.14
2 MHz
1 MHz
500 kHz
125 kHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
Running from HSE
crystal clock 8 MHz,
code executing from
Flash or RAM
Supply current in
Sleep mode from
VDDA supply
(1) (2)
IDDA
µA
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
1. VDDA supervisor is OFF.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp and others, is not included. Refer to the tables of characteristics in the subsequent sections.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
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For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins that must be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 33: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
where:
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
INT
EXT+CS
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The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Table 32. Switching output I/O current consumption
I/O toggling
Symbol
Parameter
Conditions(1)
Typ.
Unit
frequency (fSW
)
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
2 MHz
4 MHz
8 MHz
18 MHz
36 MHz
0.90
0.93
1.16
1.60
2.51
0.93
1.06
1.47
2.26
3.39
1.03
1.30
1.79
3.01
5.99
1.10
1.31
2.06
3.47
8.35
1.20
1.54
2.46
4.51
9.98
VDD = 3.3 V
Cext = 0 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
Cext = 10 pF
C = CINT + CEXT +CS
VDD = 3.3 V
Cext = 22 pF
C = CINT + CEXT +CS
I/O current
consumption
ISW
mA
VDD = 3.3 V
Cext = 33 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
Cext = 47 pF
C = CINT + CEXT+ CS
1. CS = 5 pF (estimated value).
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On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input configuration
All peripherals are disabled unless otherwise mentioned
The given value is calculated by measuring the current consumption:
–
–
With all peripherals clocked off
With only one peripheral clocked on
•
Ambient operating temperature at 25°C and V = V
= 3.3 V
DDA
DD
Table 33. Peripheral current consumption
Typical consumption(1)
Peripheral
Unit
IDD
BusMatrix (2)
DMA1
11.1
8.0
CRC
2.1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOF
8.7
8.4
8.4
2.6
1.7
TSC
4.7
ADC1&2
APB2-Bridge (3)
SYSCFG
TIM1
17.4
3.3
4.2
32.3
20.3
13.8
9.7
USART1
TIM15
µA/MHz
TIM16
TIM17
10.3
324.2
5.3
HRTIM
APB1-Bridge (3)
TIM2
43.4
34.0
9.7
TIM3
TIM6
TIM7
10.3
6.9
WWDG
USART2
USART3
18.8
19.1
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Table 33. Peripheral current consumption (continued)
Typical consumption(1)
Peripheral
Unit
IDD
I2C1
CAN
PWR
DAC
DAC2
SPI1
13.3
31.3
4.7
µA/MHz
15.4
8.6
8.2
1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp
and others, is not included. Refer to the tables of characteristics in the subsequent sections.
2. BusMatrix is automatically active when at least one master is ON (CPU or DMA1).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
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6.3.6
Wakeup time from low-power mode
The wakeup times given in Table 34 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep mode: the wakeup event is WFE.
WKUP1 (PA0) pin is used to wake up from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 19.
Table 34. Low-power mode wakeup timings
Typ. @VDD, VDD = VDDA
Symbol
Parameter
Conditions
Max. Unit
2.0 V
2.4 V
2.7 V
3 V
3.3 V
3.6 V
Regulator in
run mode
4.3
4.1
4.0
3.9
3.8
3.7
4.5
Wakeup from
Stop mode
tWUSTOP
Regulator in
low-power
mode
7.8
6.7
6.1
5.9
5.5
5.3
9
103
-
µs
Wakeup from LSI and
Standby mode IWDG OFF
(1)
tWUSTANDBY
74.4
64.3
60.0
56.9
54.3
51.1
CPU
clock
cycles
Wakeup from
-
tWUSLEEP
6
Sleep mode
1. Data based on characterization results, not tested in production.
(1)
Table 35. Wakeup time using USART
Symbol
Parameter
Conditions
Typ
Max
Unit
Stop mode with main
regulator in low
power mode
Wakeup time needed to calculate
the maximum USART baudrate
allowing to wake up from stop
mode when USART clock source is
HSI
-
-
13.125
3.125
tWUUSART
µs
Stop mode with main
regulator in run
mode
1. Guaranteed by design.
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 15.
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Table 36. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min.
Typ. Max.
Unit
User external clock source
frequency(1)
fHSE_ext
1
8
32
MHz
VHSEH
VHSEL
tw(HSEH)
OSC_IN input pin high-level voltage
OSC_IN input pin low-level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
-
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
15
-
-
-
-
tw(HSEL)
ns
tr(HSE)
tf(HSE)
20
1. Guaranteed by design, not tested in production.
Figure 15. High-speed external clock source AC timing diagram
t
w(HSEH)
V
HSEH
90%
10%
V
HSEL
t
t
t
t
r(HSE)
f(HSE)
w(HSEL)
T
HSE
MS19214V2
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 16.
Table 37. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high-level
voltage
VLSEH
VLSEL
0.7VDD
VSS
450
-
-
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low-level
voltage
-
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time(1)
OSC32_IN rise or fall time(1)
ns
tr(LSE)
tf(LSE)
50
1. Guaranteed by design, not tested in production.
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Figure 16. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
90%
10%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 38. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins to minimize output distortion and startup stabilization time. Refer to the
crystal resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 38. HSE oscillator characteristics
Symbol
Parameter
Conditions(1)
Min.(2) Typ. Max.(2) Unit
fOSC_IN Oscillator frequency
-
4
-
8
200
-
32
-
MHz
RF
Feedback resistor
-
kΩ
During startup(3)
-
8.5
V
DD= 3.3 V, Rm= 30Ω,
-
-
-
-
-
0.4
0.5
0.8
1
-
-
-
-
-
CL=10 pF@8 MHz
VDD= 3.3 V, Rm= 45Ω,
CL=10 pF@8 MHz
IDD
HSE current consumption
mA
VDD= 3.3 V, Rm= 30Ω,
CL=5 pF@32 MHz
VDD= 3.3 V, Rm= 30Ω,
CL=10 pF@32 MHz
V
DD= 3.3 V, Rm= 30Ω,
1.5
CL=20 pF@32 MHz
gm
Oscillator transconductance
Startup time
Startup
10
-
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
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For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 17. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
fHSE
Bias
controlled
gain
8 MHz
resonator
RF
(1)
OSC_OUT
REXT
CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins to minimize output distortion and startup stabilization time. Refer to the
crystal resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(1)
Min.(2) Typ. Max.(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
-
0.5
-
0.9
1
LSEDRV[1:0]=10
medium low driving
capability
IDD
LSE current consumption
µA
LSEDRV[1:0]=01
medium high-driving
capability
-
-
-
-
1.3
1.6
LSEDRV[1:0]=11
higher-driving capability
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Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz) (continued)
Symbol
Parameter
Conditions(1)
Min.(2) Typ. Max.(2) Unit
LSEDRV[1:0]=00
lower-driving capability
5
8
-
-
-
-
LSEDRV[1:0]=10
medium low-driving
capability
Oscillator
transconductance
gm
µA/V
LSEDRV[1:0]=01
medium high-driving
capability
15
-
-
LSEDRV[1:0]=11
higher-driving capability
25
-
-
-
-
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available at the ST website www.st.com.
Figure 18. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
fHSE
Bias
controlled
gain
8 MHz
resonator
RF
(1)
OSC_OUT
REXT
CL2
MS19876V1
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8
Internal clock source characteristics
The parameters given in Table 40 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19.
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High-speed internal (HSI) RC oscillator
(1)
Table 40. HSI oscillator characteristics
Symbol
fHSI
TRIM
DuCy(HSI) Duty cycle
Parameter
Frequency
HSI user trimming step
Conditions
Min.
Typ.
Max.
Unit
-
-
-
8
-
-
-
-
-
-
-
-
-
MHz
%
-
1(2)
55(2)
3.8(3)
2.3(3)
2(3)
2(3)
2(3)
1
-
45(2)
–2.8(3)
–1.9(3)
-1.9(3)
-1.3(3)
–1(3)
–1
%
TA = –40 to 105 °C
TA = –10 to 85 °C
TA = 0 to 85 °C
TA = 0 to 70 °C
TA = 0 to 55 °C
TA = 25 °C(4)
Accuracy of the HSI
ACCHSI
oscillator (factory
calibrated)
%
HSI oscillator startup
time
tsu(HSI)
-
-
1(2)
-
2(2)
µs
HSI oscillator power
consumption
IDDA(HSI)
-
80
100(2)
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
4. Factory calibrated, parts not soldered
Figure 19. HSI oscillator accuracy characterization results for soldered parts
4%
MAX
MIN
3%
2%
1%
0%
T [ºC]
A
-40
-20
0
20
40
60
80
100
120
-1%
-2%
-3%
-4%
MS30985V4
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Low-speed internal (LSI) RC oscillator
(1)
Table 41. LSI oscillator characteristics
Parameter Min.
Symbol
Typ.
Max.
Unit
fLSI
Frequency
30
-
40
-
50
85
kHz
µs
(2)
tsu(LSI)
LSI oscillator startup time
LSI oscillator power consumption
(2)
IDD(LSI)
-
0.75
1.2
µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19.
Table 42. PLL characteristics
Value
Symbol
Parameter
Unit
Min.
Typ.
Max.
PLL input clock(1)
1(2)
40(2)
16(2)
-
-
-
-
-
-
24(2)
60(2)
72
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
fPLL_OUT
tLOCK
MHz
µs
200(2)
300(2)
Jitter
Cycle-to-cycle jitter
-
ps
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
2. Guaranteed by design, not tested in production.
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6.3.10
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
Table 43. Flash memory characteristics
Symbol
Parameter
Conditions
Min.
Typ. Max.(1) Unit
tprog
16-bit programming time TA = –40 to +105 °C
40
20
20
-
53.5
60
40
40
10
12
µs
ms
ms
mA
mA
tERASE Page (2 KB) erase time TA = –40 to +105 °C
-
-
-
-
tME
Mass erase time
TA = –40 to +105 °C
Write mode
IDD
Supply current
Erase mode
-
1. Guaranteed by design, not tested in production.
Table 44. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions
Unit
Min.(1)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND
Endurance
10
kcycles
Years
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
10 kcycles(2) at TA = 55 °C
30
10
20
tRET
Data retention
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
The device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in “EMC design guide for ST microcontrollers” application note (AN1709).
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Symbol
STM32F334x4 STM32F334x6 STM32F334x8
Table 45. EMS characteristics
Parameter
Level/
Class
Conditions
VDD = 3.3 V, LQFP64, TA = +25°C,
fHCLK = 72 MHz
conforms to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
4A
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP64, TA = +25°C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It must be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see the “Software techniques for improving
microcontrollers EMC performance” application note (AN1015)).
Electromagnetic interference (EMI)
The electromagnetic field emitted by the device are monitored, while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard that specifies the test board and the pin loading.
Table 46. EMI characteristics
Max vs. [fHSE/fHCLK
8/72 MHz
]
Monitored
frequency band
Symbol Parameter
Conditions
Unit
0.1 to 30 MHz
5
9
VDD = 3.6 V, TA =25 °C,
LQFP64 package
compliant with IEC
61967-2
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
dBµV
-
SEMI
Peak level
31
4
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6.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 47. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
TA = +25 °C,
conforming to JESD22-
A114
VESD
Electrostatic discharge
voltage (human body model)
2
2000
(HBM)
V
Electrostatic discharge
voltage (charge device
model)
TA = +25 °C,
conforming to JESD22-
C101
VESD
II
250
(CDM)
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 48. Electrical sensitivities
Symbol
Parameter
Conditions
Class
II level A
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
6.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) must be avoided during normal product
DD
operation. However, to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
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The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator
frequency deviation). The test results are given in the table below.
Table 49. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
NA(Injection is not
possible)
Injected current on BOOT0
– 0
Injected current on PC0, PC1, PC2, PC3 (TTa pins) and PF1
pin (FT pin)
-0
+5
+5
IINJ
Injected current on PA0, PA1, PA2, PA3, PA4, PA5, PA6,
PA7, PC4, PC5, PB0, PB1, PB2, PB12, PB13, PB14, PB15
with induced leakage current on other pins from this group
less than -100 µA or more than +900 µA
mA
-5
Injection is not
possible
Injected current on PB11, other TT, FT, and FTf pins
Injected current on all other TC, TTa and RESET pins
– 5
– 5
+5
Note:
It is recommended to add a Schottky diode (pin to ground) to the analog pins that may
potentially inject negative currents.
6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 19. All I/Os are CMOS and TTL
compliant.
Table 50. I/O static characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
TT, TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
-
-
-
-
-
-
-
0.3 VDD+0.07 (1)
0.475 VDD-0.2 (1)
0.3 VDD–0.3 (1)
-
Low-level input
voltage
VIL
-
(2)
All I/Os except BOOT0
TTa and TT I/O
FT and FTf I/O
BOOT0
-
0.3 VDD
V
0.445 VDD+0.398 (1)
-
-
-
-
(1)
0.5 VDD+0.2
0.2 VDD+0.95 (1)
High-level input
voltage
VIH
(2)
All I/Os except BOOT0
0.7 VDD
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Table 50. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
TT, TC and TTa I/O
FT and FTf I/O
BOOT0
-
-
-
200 (1)
100 (1)
300 (1)
-
-
-
Schmitt trigger
hysteresis
Vhys
mV
TC, FT, TT, FTf and TTa
I/O in digital mode
-
-
±0.1
VSS ≤VIN ≤VDD
TTa I/O in digital mode
-
-
-
-
1
±0.2
10
VDD ≤VIN ≤VDDA
Input leakage
current (3)
TTa I/O in analog mode
Ilkg
µA
VSS ≤VIN ≤VDDA
FT and FTf I/O(4)
-
-
VDD ≤VIN ≤5 V
Weak pull-up
RPU
VIN = VSS
25
40
55
kΩ
equivalent resistor(5)
Weak pull-down
RPD
CIO
VIN = VDD
25
-
40
5
55
-
kΩ
equivalent resistor(5)
I/O pin capacitance
-
pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. If negative current is injected on adjacent pins. Refer to Table 49: I/O
current injection susceptibility.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 20 and Figure 21 for standard I/Os.
Figure 20. TC and TTa I/O input characteristics - CMOS port
VIL/VIH (V)
VIHmin 2.0
1.3
Area not determined
CMOS standard requirements VILmax = 0.3V
VDD (V)
DD
VILmax 0.7
0.6
2.0
2.7
3.0
3.3
3.6
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Figure 21. TC and TTa I/O input characteristics - TTL port
VIL/VIH (V)
TTL standard requirements VIHmin = 2V
VIHmin 2.0
1.3
Area not determined
VILmax 0.8
0.7
TTL standard requirements VILmax = 0.8V
VDD (V)
2.0
2.7
3.0
3.3
3.6
MS30256V2
Figure 22. 5V- tolerant (FT and FTf) I/O input characteristics - CMOS port
VIL/VIH (V)
2.0
Area not determined
1.0
0.5
VDD (V)
2.0
2.7
3.6
MS30257V3
Figure 23. 5V-tolerant (FT and FTf) I/O input characteristics - TTL port
VIL/VIH (V)
TTL standard requirements VIHmin = 2V
Area not determined
2.0
1.0
0.8
TTL standard requirements VILmax = 0.8V
0.5
VDD (V)
2.0
2.7
3.6
MS30258V2
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Output driving current
Electrical characteristics
The GPIOs (general-purpose input/output) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed V ).
V
OL/ OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣIVDD (see Table 17).
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣIVSS (see Table 17).
Output voltage levels
Unless otherwise specified, the parameters given in Table 47: ESD absolute maximum
ratings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 19. All I/Os (FT, TTa and TC unless otherwise
specified) are CMOS and TTL compliant.
Table 51. Output voltage characteristics
Symbol
Parameter
Conditions
Min.
Max.
0.4
-
Unit
VOL
Low-level output voltage for an I/O pin
High- level output voltage for an I/O pin
Low-level output voltage for an I/O pin
High-level output voltage for an I/O pin
CMOS port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
(1)
(3)
VOH
VDD–0.4
VOL
TTL port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
-
0.4
-
(1)
(3)
VOH
2.4
(1)(4)
VOL
Low-level output voltage for an I/O pin
High-level output voltage for an I/O pin
Low-level output voltage for an I/O pin
High-level output voltage for an I/O pin
-
1.3
-
V
I
IO = +20 mA
(3)(4)
2.7 V < VDD < 3.6 V
VOH
VDD–1.3
-
(1)(4)
VOL
0.4
-
I
IO = +6 mA
(3)(4)
2 V < VDD < 2.7 V
VOH
VDD–0.4
Low-level output voltage for an FTf I/O pin
in FM+ mode
IIO = +20 mA
2.7 V < VDD < 3.6 V
(1)(4)
VOLFM+
-
0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 17 and the sum of
IIO (I/O ports and control pins) must not exceed ΣIIO(PIN)
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 17 and the sum
of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN)
.
4. Data based on design simulation.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
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Table 66, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 19.
DD
(1)
Table 52. I/O AC characteristics
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
Min.
Max. Unit
MH
z
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
-
-
-
-
-
-
-
-
-
2(3)
125(3)
Output high to low level
fall time
x0
01
tf(IO)out
CL = 50 pF, VDD = 2 V to 3.6 V
ns
Output low to high level
tr(IO)out
125(3)
rise time
MH
z
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V
10(3)
Output high to low level
fall time
25
tf(IO)out
(3)
CL = 50 pF, VDD = 2 V to 3.6 V
ns
Output low to high level
25
tr(IO)out
(3)
rise time
MH
z
CL = 30 pF, VDD = 2.7 V to 3.6 V
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
50(3)
30(3)
20(3)
MH
z
MH
z
CL = 30 pF, VDD = 2.7 V to 3.6 V
Output high to low level
fall time
-
-
-
-
-
-
5(3)
8(3)
11
tf(IO)out
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
ns
5(3)
Output low to high level
rise time
tr(IO)out
8(3)
12(3)
MH
z
fmax(IO)out Maximum frequency(2)
-
-
-
2(4)
12(4)
FM+
Output high to low level
fall time
tf(IO)out
CL = 50 pF, VDD = 2 V to 3.6 V
configuration(4)
ns
Output low to high level
rise time
tr(IO)out
34(4)
Pulse width of external
-
tEXTIpw
signals detected by the
EXTI controller
-
10
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0364 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 24.
3. Guaranteed by design, not tested in production.
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4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the RM0364 reference manual for a description of FM+
I/O mode configuration.
Figure 24. I/O AC characteristics definition
90%
10%
50%
50%
90%
t
10%
t
EXTERNAL
OUTPUT
ON CL
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t ) ≤ (2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by CL specified in the table “ I/O AC characteristics”.
ai14131d
6.3.15
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 50).
PU
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 19.
Table 53. NRST pin characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
0.3VDD
(1)
VIL(NRST)
NRST Input low level voltage
-
-
-
+ 0.07(1)
V
0.445VDD
0.398(1)
+
(1)
VIH(NRST)
NRST Input high-level voltage
-
-
-
Vhys(NRST) NRST Schmitt trigger voltage hysteresis
-
-
25
200
-
55
mV
kΩ
ns
RPU
Weak pull-up equivalent resistor(2)
VIN = VSS
40
-
(1)
VF(NRST)
NRST Input filtered pulse
-
-
-
100(1)
(1)
VNF(NRST)
NRST Input not filtered pulse
500(1)
-
-
ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
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Figure 25. Recommended NRST pin protection
([WHUQDO
UHVHWꢅFLUFXLWꢆꢀꢇ
9''
538
1567ꢆꢈꢇ
,QWHUQDOꢅUHVHW
)LOWHU
ꢉꢊꢀꢅ)ꢆꢄꢇ
06ꢀꢁꢂꢃꢂ9ꢄ
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53. Otherwise the reset is not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
4. Place the external capacitor 0.1u F on NRST as close as possible to the chip.
6.3.16
High-resolution timer (HRTIM)
The parameters given in Table 54 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 19.
Table 54. HRTIM1 characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
fHRTIM=144MHz (1)
fHRTIM=128MHz (2)
-40
-10
128
6.9
-
-
-
-
105
105
144
7.8
°C
°C
Timer ambient
temperature range
TA
fHRTIM
tHRTIM
MHz
ns
HRTIM input clock for
DLL calibration
As per TA conditions
fHRTIM=144MHz (1), TA from -
40 to 105°C
fHRTIM=128MHz (2),TA from -10
to 105°C
-
-
217
244
-
-
ps
ps
tRES(HRTIM) Timer resolution time
ResHRTIM
tDTG
Timer resolution
-
-
-
-
-
-
-
-
-
-
-
16
16
bit
tHRTIM
ns
-
0.125
0.868
-
Dead time generator
clock period
fHRTIM=144MHz (1)
111.10
511
-
tDTG
µs
|tDTR| / |tDTF| Dead time range
fHRTIM=144MHz (1)
-
56.77
1/16
9
(absolute value)
max
-
fHRTIM=144MHz (1)
-
1/256
0.562
16
fHRTIM
MHz
tHRTIM
µs
Chopper stage clock
frequency
fCHPFRQ
256
1.77
Chopper first pulse
t1STPW
length
fHRTIM=144MHz (1)
0.111
1. Using HSE with 8MHz XTAL as clock source, configuring PLL to get PLLCLK=144MHz, and selecting PLLCLKx2 as
HRTIM clock source. (Refer to Reset and clock control section in RM0364.)
2. Using HSI (internal 8MHz RC oscillator), configuring PLL to get PLLCLK=128MHz, and selecting PLLCLKx2 as HRTIM
clock source. (Refer to Reset and clock control section in RM0364.
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(1)
Table 55. HRTIM output response to fault protection
Symbol
Parameter
Conditions
Min.
Typ. Max.(2)
Unit
Propagation delay from
HRTIM1_FLTx digital input to
HRTIM_CHxy output pin
Digital fault response
latency
tLAT(DF)
-
12
-
25
-
Minimum Fault pulse
width
tW(FLT)
-
12.5
-
ns
Propagation delay from comparator
COMPx_INP input pin to
HRTIM_CHxy output pin
Analog fault response
latency
tLAT(AF)
25
43
1. Refer to Fault paragraph in HRTIM section of RM0364.
2. Data based on characterization results, not tested in production.
(1)
Table 56. HRTIM output response to external events 1 to 5 (Low-Latency mode
)
Symbol
Parameter
Conditions
Min. Typ. Max.(2)
Unit
Propagation delay from
HRTIM1_EEVx digital input to
HRTIM_CHxy output pin (30pF
load)
Digital external event
response latency
tLAT(DEEV)
-
12.5
-
12
-
25
-
ns
ns
ns
Minimum external event
pulse width
tW(FLT)
-
Propagation delay from comparator
COMPx_INP input pin to
HRTIM_CHxy output pin (30pF
load)
Analog external event
response latency
tLAT(AEEV)
25
43
Jitter of the delay from
External event response HRTIM1_EEVx digital input or
(3)
(3)
TJIT(EEV)
-
-
-
-
0
1
tHRTIM
jitter
COMPx_INP input pin to
HRTIM_CHxy output pin
Jitter on output pulse
width in response to an
external event
TJIT(PW)
-
tHRTIM
1. EExFAST bit in HRTIM_EECR1 register is set (Low Latency mode). This functionality is available on external events
channels 1 to 5. Refer to Latency to external events paragraph in HRTIM section of RM0364.
2. Data based on characterization results, not tested in production.
3. THRTIM = 1 / fHRTIM with fHRTIM= 144 MHz or fHRTIM = 128 MHZ depending on the clock controller configuration. (Refer to
Reset and clock control section in RM0364.)
(1)
Table 57. HRTIM output response to external events 1 to 10 (Synchronous mode
)
Symbol
Parameter
Conditions
Min. Typ. Max.(2)
Unit
External event response
latency in HRTIM
TPROP(HRTIM)
HRTIM internal propagation delay (3)
6
-
-
7
tHRTIM
Propagation delay from HRTIM1_EEVx
digital input to HRTIM_CHxy output pin
(30pF load) (4)
Digital external event
response latency
tLAT(DEEV)
61
72
ns
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(1)
Table 57. HRTIM output response to external events 1 to 10 (Synchronous mode ) (continued)
Symbol
Parameter
Conditions
Min. Typ. Max.(2)
Unit
Propagation delay from COMPx_INP
input pin to HRTIM_CHxy output pin
(30pF load) (4)
Analog external event
response latency
tLAT(AEEV)
-
12.5
-
81
-
94
-
ns
Minimum external event
pulse width
tW(FLT)
-
ns
Jitter of the delay from HRTIM1_EEVx
digital input or COMPx_INP to
HRTIM_CHxy output pin
External event response
jitter
(5)
(5)
TJIT(EEV)
-
1
tHRTIM
Jitter on output pulse
width in response to an
external event
TJIT(PW)
-
-
-
0
tHRTIM
1. EExFAST bit in HRTIM_EECR1 or HRTIM_EECR2 register is cleared (synchronous mode). External event filtering is
disabled, i.e. EExF[3:0]=0000 in HRTIM_EECR2 register. Refer to Latency to external events paragraph in HRTIM section
of RM0364.
2. Data based on characterization results, not tested in production.
3. This parameter does not take into account latency introduced by GPIO or comparator. Refer to DEERL or SACRL
parameter for complete latency.
4. This parameter is given for fHRTIM = 144 MHz.
5. THRTIM = 1 / fHRTIM with fHRTIM= 144 MHz or fHRTIM = 128 MHZ depending on the clock controller configuration. (Refer to
Reset and clock control section in RM0364.)
(1)
Table 58. HRTIM synchronization input / output
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
Minimum pulse width on
tW(SYNCIN) SYNCIN inputs, including
HRTIM1_SCIN
-
2
-
-
-
-
tHRTIM
Response time to external
tLAT(DF)
-
-
1
tHRTIM
synchronization request
-
-
16
-
-
tHRTIM
ns
Pulse width on
tLAT(AF)
HRTIM1_SCOUT output
fHRTIM=144 MHz
111.1
1. Guaranteed by design, not tested in production.
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6.3.17
Timer characteristics
The parameters given in Table 59 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 59. TIMx
characteristics
Symbol
Parameter
Conditions
Min.
Max.
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 72 MHz
tres(TIM)
Timer resolution time
13.9
-
ns
fTIM1CLK = 144 MHz
6.95
-
fTIMxCLK/2
36
ns
-
0
0
-
MHz
MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 72 MHz
TIMx (except TIM2)
16
ResTIM
Timer resolution
bit
TIM2
-
-
32
1
65536
910
tTIMxCLK
µs
16-bit counter clock
period
tCOUNTER
fTIMxCLK = 72 MHz 0.0139
fTIM1CLK = 144 MHz 0.0069
455
µs
-
-
-
-
65536 × 65536 tTIMxCLK
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 72 MHz
fTIM1CLK = 144 MHz
59.65
s
s
29.825
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM15, TIM16 and TIM17 timers.
2. Guaranteed by design, not tested in production.
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
(1)
Table 60. IWDG min./max. timeout period at 40 kHz (LSI)
Min. timeout (ms)
RL[11:0] = 0x000
Max. timeout (ms)
RL[11:0] = 0xFFF
Prescaler divider PR[2:0] bits
/4
/8
0
1
2
3
4
5
7
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
/16
/32
/64
/128
/256
1638.4
3276.8
6553.6
13107.2
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
(1)
Table 61. WWDG min./max. timeout value at 72 MHz (PCLK)
Prescaler
WDGTB
Min. timeout value
Max. timeout value
1
2
4
8
0
1
2
3
0.05687
0.1137
0.2275
0.4551
3.6409
7.2817
14.564
29.127
1. Guaranteed by design, not tested in production.
6.3.18
Communication interfaces
I2C interface characteristics
2
2
The I C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 Kbit/s
Fast-mode (Fm): with a bit rate up to 400 Kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
2
The I C timings requirements are guaranteed by design when the I C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present. Only FTf I/O pins
support Fm+ low-level output current maximum requirement. Refer to Section 6.3.14: I/O
2
port characteristics for the I C I/O characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
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Electrical characteristics
2
(1)
Table 62. I C analog filter characteristics
Symbol
Parameter
Min.
Max.
Unit
Maximum pulse width of spikes that are
suppressed by the analog filter.
tAF
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with width below tAF(min.) are filtered.
3. Spikes with width above tAF(max.) are not filtered.
SPI characteristics
Unless otherwise specified, the parameters given in Table 53 for SPI are derived from tests
performed under ambient temperature, f frequency and V supply voltage conditions
PCLKx
DD
summarized in Table 19: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 63. SPI characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Master mode 2.7 < VDD < 3.6 V
Master mode 2 < VDD < 3.6 V
Slave mode 2 < VDD < 3.6 V
24
18
24
fSCK
1/tc(SCK)
SPI clock frequency
-
-
MHz
Slave mode transmitter/full
duplex
18(2)
2 < VDD < 3.6 V
Duty cycle of SPI clock
frequency
DuCy(SCK)
Slave mode
30
50
70
%
tsu(NSS) NSS setup time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
4*Tpclk
2*Tpclk
-
-
-
-
th(NSS)
NSS hold time
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2 Tpclk Tpclk+2
tsu(MI)
tsu(SI)
th(MI)
Master mode
0
3
-
-
-
-
Data input setup time
Data input hold time
Slave mode
Master mode
5
-
-
th(SI)
Slave mode
1
-
-
ns
ta(SO)
tdis(SO)
Data output access time
Data output disable time
Slave mode
10
10
-
-
40
17
20
27.5
5
Slave mode
-
Slave mode 2.7 < VDD < 3.6 V
Slave mode 2 < VDD < 3.6 V
Master mode
12
12
1.5
-
tv(SO)
Data output valid time
Data output hold time
-
tv(MO)
th(SO)
th(MO)
-
Slave mode
7.5
0
-
Master mode
-
-
1. Data based on characterization results, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Figure 26. SPI timing diagram - slave mode and CPHA = 0
(1)
Figure 27. SPI timing diagram - slave mode and CPHA = 1
NSS input
tSU(NSS)
th(NSS)
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(SO)
tdis(SO)
tv(SO)
ta(SO)
MISO
MSB OUT
MSB IN
BIT6 OUT
LSB OUT
OUTPUT
th(SI)
tsu(SI)
MOSI
INPUT
LSB IN
BIT 1 IN
ai14135b
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
88/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
(1)
Figure 28. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
6.3.19
ADC characteristics
Unless otherwise specified, the parameters showed from Table 64 to Table 67 are
guaranteed by design, with the conditions summarized in Table 19.
Table 64. ADC characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Analog supply voltage for
ADC
VDDA
-
2
-
3.6
V
Single ended mode,
5 MSPS
-
-
-
1011.3
214.7
54.7
1172.0
322.3
81.1
Single ended mode,
1 MSPS
Single ended mode,
200 KSPS
ADC current consumption
(Figure 29)
IDDA
µA
Differential mode, 5 MSPS
Differential mode, 1 MSPS
-
-
1061.5
246.6
1243.6
337.6
Differential mode,
200 KSPS
-
-
56.4
0
83.0
-
Negative reference
voltage
VREF-
-
V
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 64. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
fADC
ADC clock frequency
-
0.14
-
72
MHz
Resolution = 12 bits,
Fast Channel
0.01
0.012
0.014
0.0175
-
-
-
-
-
-
5.14
6
Resolution = 10 bits,
Fast Channel
(1)
fS
Sampling rate
Msps
Resolution = 8 bits,
Fast Channel
7.2
9
Resolution = 6 bits,
Fast Channel
fADC = 72 MHz
Resolution = 12 bits
5.14
MHz
(1)
fTRIG
External trigger frequency
Resolution = 12 bits
-
0
-
-
-
-
14
1/fADC
V
VAIN
Conversion voltage range
External input impedance
-
-
VDDA
100
(1)
RAIN
κΩ
Internal sample and hold
capacitor
(1)
CADC
-
-
5
-
pF
f
ADC = 72 MHz
1.56
112
µs
(1)
tCAL
Calibration time
-
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
µs
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
1.5
2
-
2.5
2
Trigger conversion latency
Regular and injected
channels without
-
(1)
tlatr
-
-
2.25
2.125
3.5
conversion abort
-
-
2.5
3
-
Trigger conversion latency
Injected channels aborting
a regular conversion
-
3
(1)
tlatrinj
-
-
-
3.25
3.125
8.35
601.5
-
fADC = 72 MHz
0.021
1.5
-
(1)
tS
Sampling time
-
-
1/fADC
tADCVRE
ADC Voltage Regulator
Start-up time
(
G_STUP
1)
-
-
-
-
10
µs
conver
sion
tSTAB Power-up time
1
cycle
90/125
DS9994 Rev 9
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Electrical characteristics
Table 64. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
fADC = 72 MHz
Resolution = 12 bits
0.19
-
8.52
µs
Total conversion time
(including sampling time)
(1)
tCONV
14 to 614 (tS for sampling + 12.5 for
successive approximation)
Resolution = 12 bits
1/fADC
(VSSA
VREF+)/2
+ 0.18
+
Common Mode Input
signal
(VSSA+VREF+)/ (VSSA
+
CMIR
ADC differential mode
V
2-0.18 VREF+)/2
1. Data guaranteed by design, not tested in production.
Figure 29. ADC typical current consumption in single-ended and differential modes
Clock frequency (MSPS)
MS34994V1
(1)
Table 65. Maximum ADC R
AIN
R
AIN max. (kΩ)
Sampling
cycle @
72 MHz
Sampling
time [ns] @
72 MHz
Resolution
Other
Fast channels(2) Slow channels
channels(3)
1.5
2.5
20.83
34.72
0.018
0.150
0.470
0.820
2.70
NA
NA
NA
0.022
0.180
0.470
1.50
4.5
62.50
0.220
0.560
1.80
6.80
18.0
68.0
7.5
104.17
270.83
854.17
2520.83
8354.17
12 bits
19.5
61.5
181.5
601.5
8.20
4.70
22.0
15.0
82.0
47.0
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
(1)
Table 65. Maximum ADC R
(continued)
RAIN max. (kΩ)
AIN
Sampling
cycle @
Sampling
time [ns] @
72 MHz
Resolution
Other
Fast channels(2) Slow channels
72 MHz
channels(3)
1.5
2.5
20.83
34.72
0.082
0.270
0.560
1.20
NA
0.082
0.390
0.82
NA
0.100
0.330
0.68
4.5
62.50
7.5
104.17
270.83
854.17
2520.83
8354.17
20.83
10 bits
19.5
61.5
181.5
601.5
1.5
3.30
2.70
2.20
10.0
8.2
6.8
33.0
27.0
22.0
100.0
0.150
0.390
0.820
1.50
82.0
68.0
NA
0.039
0.180
0.470
1.00
2.5
34.72
0.180
0.560
1.20
4.5
62.50
7.5
104.17
270.83
854.17
2520.83
8354.17
20.83
8 bits
19.5
61.5
181.5
601.5
1.5
3.90
3.30
2.70
12.00
39.00
100.00
0.270
0.560
1.200
2.20
12.00
33.00
100.00
0.100
0.390
0.820
1.80
8.20
27.00
82.00
0.150
0.330
0.820
1.50
2.5
34.72
4.5
62.50
7.5
104.17
270.83
854.17
2520.83
8354.17
6 bits
19.5
61.5
181.5
601.5
5.60
4.7
3.90
18.0
15.0
12.0
56.0
47.0
39.0
100.00
100.0
100.0
1. Data based on characterization results, not tested in production.
2. All fast channels, expect channel on PA6.
3. Channels available on PA6.
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DS9994 Rev 9
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Electrical characteristics
(1)(2)
Table 66. ADC accuracy - limited test conditions
Min.
Symbol Parameter
Conditions
Typ. Max.(3) Unit
(3)
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±4
±5.5
±3.5
±3.5
±2
±4.5
±6
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
±4
Differential
±4
±2
Single
ended
±1.5
±1.5
±1.5
±3
±2
Offset
error
±2
Differential
±2
±4
Single
ended
±5
±5.5
±3
Gain error
LSB
±3
Differential
Single
±3
±3.5
±1
±1
ADC clock freq. ≤ 72 MHz
ended
Differential
linearity
error
±1
±1
Sampling freq. ≤ 5 Msps
VDDA = 3.3 V
25°C
±1
±1
Differential
±1
±1
±1.5
±2
±2
Single
ended
Integral
linearity
error
±3
±1.5 ±1.5
Differential
±1.5
±2
-
Fast channel 5.1 Ms 10.8 10.8
Slow channel 4.8 Ms 10.8 10.8
Fast channel 5.1 Ms 11.2 11.3
Slow channel 4.8 Ms 11.2 11.3
Single
ended
Effective
-
ENOB(4) number of
bits
bit
-
Differential
-
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
66
66
69
69
67
67
70
70
-
Single
ended
Signal-to-
SINAD noise and
-
dB
(4)
distortion
ratio
-
Differential
-
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103
Electrical characteristics
Symbol Parameter
STM32F334x4 STM32F334x6 STM32F334x8
(1)(2)
Table 66. ADC accuracy - limited test conditions
(continued)
Min.
Conditions
Typ. Max.(3) Unit
(3)
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
66
66
69
69
-
67
67
-
-
Single
ended
Signal-to-
SNR(4)
noise ratio
70
-
ADC clock freq. ≤ 72 MHz
Sampling freq. ≤ 5 Msps
Differential
70
-
dB
VDDA = 3.3 V
-80
-78
-83
-81
-80
-77
-82
-80
Single
ended
25°C
Total
THD(4) harmonic
distortion
-
-
Differential
-
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins must be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
(1)(2)(3)
Table 67. ADC accuracy
Symbol Parameter
Conditions
Min.(4) Max.(4) Unit
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±6.5
±6.5
±4
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
Differential
±4.5
±3
Single
ended
±3
Offset error
Gain error
±2.5
±2.5
±6
Differential
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
LSB
Single
ended
2.0 V ≤ VDDA ≤ 3.6 V
±6
±3.5
±4
Differential
±1.5
±1.5
±1.5
±1.5
Single
ended
Differential
linearity
error
Differential
94/125
DS9994 Rev 9
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Electrical characteristics
Min.(4) Max.(4) Unit
(1)(2)(3)
Table 67. ADC accuracy
(continued)
Symbol Parameter
Conditions
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
Fast channel 5.1 Ms
Slow channel 4.8 Ms
-
-
±3
Single
ended
Integral
linearity
error
±3.5
EL
LSB
bits
-
±2
Differential
-
±2.5
10.4
10.4
10.8
10.8
64
63
67
67
64
64
67
67
-
-
Single
ended
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 5 Msps
Effective
number of
bits
-
ENOB
(5)
-
2.0 V ≤ VDDA ≤ 3.6 V
Differential
-
-
Single
ended
Signal-to-
SINAD noise and
-
(5)
distortion
ratio
-
-
Differential
-
Single
ended
-
Signal-to-
SNR(5)
dB
noise ratio
-
Differential
ADC clock freq. ≤ 72 MHz,
Sampling freq ≤ 5 Msps,
2.0 V ≤ VDDA ≤ 3.6 V
-
-75
-75
-79
-78
Single
ended
Total
THD(5) harmonic
distortion
-
-
Differential
-
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins must be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal.
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
(1)(2)
Table 68. ADC accuracy
at 1MSPS
Symbol
Parameter
Test conditions
Typ.
Max(3) Unit
Fast channel
Slow channel
Fast channel
Slow channel
Fast channel
Slow channel
Fast channel
Slow channel
Fast channel
Slow channel
±2.5
±3.5
±1
±5
±5
ET
Total unadjusted error
±2.5
±2.5
EO
EG
ED
EL
Offset error
±1.5
±2
ADC Freq. ≤ 72 MHz
Sampling Freq. ≤ 1MSPS
2.4 V ≤ VDDA = VREF+ ≤ 3.6 V
±3
Gain error
LSB
±4
±3
Single-ended mode
±0.7
±0.7
±1
± 2
±2
±3
±3
Differential linearity error
Integral linearity error
±1.2
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins must be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current
within the limits specified for IINJ(PIN) and ∑IINJ(PIN) in Section 6.3.14: I/O port characteristics does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
Figure 30. ADC accuracy characteristics
V
4096
DDA
1LSB
=
IDEAL
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
(2)
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
ET
(3)
7
6
5
4
3
2
1
EO=Offset Error: deviation between the first actual
(1)
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
ED
1LSBIDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
VSSA
MS34980V1
96/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Figure 31. Typical connection diagram using the ADC
VDD
Sample and hold ADC
converter
VT
0.6 V
(1)
RADC
RAIN
AINx
12-bit
converter
IL 1 μA
VT
VAIN
0.6 V
Cparasitic
CADC
MS19881V3
1. Refer to Table 64 for the values of RAIN
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC must be reduced.
General PCB design guidelines
Power supply decoupling must be performed as shown in Figure 12: Power-supply scheme.
The 10 nF capacitor must be ceramic (good quality) and it must be placed as close as
possible to the chip.
6.3.20
DAC electrical specifications
Table 69. DAC characteristics
Symbol
VDDA
Parameter
Conditions
Min. Typ.
Max.
Unit
Analog supply voltage
-
2.4
-
3.6
V
DAC output buffer ON (to VSSA
)
5
25
-
(1)
RLOAD
Resistive load
-
kΩ
DAC output buffer ON (to VDDA
DAC output buffer OFF
)
(1)
RO
Output impedance
Capacitive load
-
-
15
50
kΩ
(1)
CLOAD
DAC output buffer ON
-
pF
Corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VDDA = 3.6 V
0.2
-
VDDA – 0.2
V
and (0x155) and (0xEAB) at VDDA
2.4 V
=
(
VDAC_OUT Voltage on DAC_OUT
1)
output
-
-
0.5
-
-
mV
V
DAC output buffer OFF
VDDA– 1LSB
With no load, middle code (0x800)
on the input
-
-
-
-
380
480
µA
µA
DAC DC current
(3)
IDDA
consumption in quiescent
mode(2)
With no load, worst code (0xF1C) on
the input.
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Table 69. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min. Typ.
Max.
Unit
Given for a 10-bit input code
DAC1 channel 1
-
-
±0.5
LSB
Given for a 12-bit input code
DAC1 channel 1
-
-
-
-
±2
LSB
Differential non linearity
Difference between two
consecutive code-1LSB)
DNL(3)
Given for a 10-bit input code
-0.75/+0.25 LSB
DAC1 channel 2 & DAC2 channel 1
Given for a 12-bit input code
-
-
-
-
-3/+1
±1
LSB
LSB
DAC1 channel 2 & DAC2 channel 1
Integral non linearity
(difference between
Given for a 10-bit input code
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 4095)
INL(3)
Given for a 12-bit input code
-
-
±4
LSB
Offset error
-
-
-
-
-
-
-
-
-
±10
±3
mV
LSB
LSB
%
(difference between
measured value at Code
(0x800) and the ideal value
= VDDA/2)
Given for a 10-bit input code at
VDDA = 3.6 V
Offset(3)
Given for a 12-bit input code
Given for a 12-bit input code
±12
±0.5
Gain
Gain error
error(3)
Settling time (full scale: for
a 12-bit input code
tSETTLING transition between the
(3
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
-
-
3
-
4
1
µs
)
lowest and the highest input
codes when DAC_OUT
reaches final value ±1LSB
Max frequency for a correct
DAC_OUT change when
Update
MS/
s
small variation in the input CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
rate(3)
code (from code i to
i+1LSB)
DAC buffer ON
Output sink current
Iskink
100
-
-
-
µA
µs
Output level higher than 0.2 V
Wakeup time from off state
(3)
tWAKEUP
(Setting the ENx bit in the
DAC Control register)
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
6.5
10
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
No RLOAD, CLOAD = 50 pF
-
–67
–40
dB
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is
involved.
3. Data based on characterization results, not tested in production.
98/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
Figure 32. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
DAC_OUTx
12-bit
digital to
analog
converter
C
L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.21
Comparator characteristics
(1)
Table 70. Comparator characteristics
Symbol
VDDA
Parameter
Conditions
Min.
Typ.
Max.
Unit
Analog supply voltage
-
2
-
3.6
V
Comparator input voltage
range
VIN
-
0
-
VDDA
-
VBG
VSC
Scaler input voltage
Scaler offset voltage
-
-
-
-
VREFINIT
±5
-
-
±10
mV
First VREFINT scaler activation
after device power on
-
-
1(2)
s
VREFINT scaler startup time
from power down
tS_SC
Next activations
-
-
-
-
-
-
0.2
4
ms
VDDA < 2.7 V
tSTART
Comparator startup time
µs
VDDA < 2.7 V
10
V
DDA ≥ 2.7 V
-
-
-
-
25
28
32
35
28
30
35
40
Propagation delay for
200 mV step with 100 mV
overdrive
VDDA < 2.7 V
tD
ns
VDDA ≥ 2.7 V
Propagation delay for full
range step with 100 mV
overdrive
VDDA < 2.7 V
V
DDA ≥ 2.7 V
-
-
-
5
-
10
25
3
VOFFSET Comparator offset error
TVOFFSET Total offset variation
mV
VDDA < 2.7 V
Full temperature range
-
mV
µA
COMP current
IDD(COMP)
-
-
400
600
consumption
1. Guaranteed by design, not tested in production.
2. For more details and conditions see Figure 33: Maximum VREFINT scaler startup time from power-down.
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
Figure 33. Maximum VREFINT scaler startup time from power-down
6.3.22
Operational amplifier characteristics
(1)
Table 71. Operational amplifier characteristics
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDDA
CMIR
Analog supply voltage
-
-
2.4
0
-
-
3.6
V
V
Common mode input range
VDDA
25°C, No Load
on output.
-
-
-
-
-
-
-
-
4
6
Maximum
calibration range
All
voltage/Temp.
VIOFFSET
Input offset voltage
mV
25°C, No Load
on output.
1.6
3
After offset
calibration
All
voltage/Temp.
ΔVIOFFSET
Input offset voltage drift
Drive current
-
-
-
-
5
-
-
µV/°C
µA
ILOAD
500
No load,
quiescent mode
IDDOPAMP Consumption
-
690
1450
µA
CMRR
PSRR
GBW
SR
Common mode rejection ratio
-
-
73
-
90
117
8.2
4.7
-
-
-
dB
dB
Power supply rejection ratio
Bandwidth
DC
-
-
-
-
-
MHz
V/µs
kΩ
Slew rate
-
-
RLOAD
CLOAD
Resistive load
Capacitive load
4
-
-
-
50
pF
100/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
(1)
Table 71. Operational amplifier characteristics (continued)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Rload = min,
Input at VDDA
VDDA-100
-
.
VOHSAT
High saturation voltage(2)
Rload = 20K,
Input at VDDA
V
DDA-20
-
-
.
mV
R
load = min,
-
100
input at 0 V
VOLSAT
Low saturation voltage
Phase margin
Rload = 20K,
input at 0 V.
-
-
-
20
-
ϕm
-
62
°
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
tOFFTRIM
-
-
-
-
2
5
ms
CLOAD ≤50 pf,
RLOAD ≥ 4 kΩ,
Follower
tWAKEUP
Wakeup time from OFF state.
2.8
µs
configuration
tS_OPAM_VOUT ADC sampling time when reading the OPAMP output
400
-
2
-
-
-
-
-
-
-
-
-
ns
-
-
-
-
-
-
-
-
-
4
-
PGA gain
Non inverting gain value
-
8
-
16
-
Gain=2
Gain=4
Gain=8
Gain=16
5.4/5.4
16.2/5.4
37.8/5.4
40.5/2.7
R2/R1 internal resistance values in
PGA mode (3)
Rnetwork
kΩ
PGA gain
error
PGA gain error
-
-
-1%
-
-
-
1%
-
Ibias
OPAMP input bias current
0.2(4)
µA
PGA Gain = 2,
Cload = 50pF,
Rload = 4 KΩ
-
-
-
-
4
2
-
-
-
-
PGA Gain = 4,
Cload = 50pF,
Rload = 4 KΩ
PGA bandwidth for different non
inverting gain
PGA BW
MHz
PGA Gain = 8,
Cload = 50pF,
1
Rload = 4 KΩ
PGA Gain = 16,
Cload = 50pF,
0.5
Rload = 4 KΩ
DS9994 Rev 9
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103
Electrical characteristics
STM32F334x4 STM32F334x6 STM32F334x8
(1)
Table 71. Operational amplifier characteristics (continued)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
@ 1KHz, Output
loaded with
4 KΩ
-
109
-
nV
en
Voltage noise density
-----------
@ 10KHz,
Output loaded
with 4 KΩ
Hz
-
43
-
1. Guaranteed by design, not tested in production.
2. The saturation voltage can also be limited by the Iload
.
3. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
R1 is the internal resistance between OPAMP inverting input and ground.
The PGA gain =1+R2/R1
4. Mostly TTa I/O leakage, when used in analog mode.
Figure 34. OPAMP voltage noise versus frequency
102/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Electrical characteristics
6.3.23
Temperature sensor (TS) characteristics
Table 72. Temperature sensor (TS) characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
(1)
TL
VSENSE linearity with temperature
-
1
4.3
1.43
-
2
4.6
1.52
10
°C
mV/°C
V
Avg_Slope(1) Average slope
4.0
1.34
4
V25
Voltage at 25 °C
Startup time
(1)
tSTART
µs
ADC sampling time when reading the
temperature
(1)(2)
TS_temp
2.2
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
Table 73. Temperature sensor (TS) calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
temperature of 30 °C,
TS_CAL1
0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V
TS ADC raw data acquired at
temperature of 110 °C
TS_CAL2
0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V
6.3.24
V
monitoring characteristics
BAT
Table 74. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min.
Typ.
Max.
Unit
R
Q
-
-
50
2
-
-
KΩ
-
Ratio on VBAT measurement
Error on Q
Er(1)
-1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
(1)(2)
TS_vbat
2.2
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
DS9994 Rev 9
103/125
103
Package information
STM32F334x4 STM32F334x6 STM32F334x8
7
Package information
7.1
Package mechanical data
To meet the environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
®
®
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
104/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Package information
7.2
LQFP32 package information
LQFP32 is a 32-pin, 7 x 7mm low-profile quad flat package.
Figure 35. LQFP32 package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
K
D
D1
D3
L
L1
24
17
16
25
32
9
PIN 1
IDENTIFICATION
1
8
e
5V_ME_V2
1. Drawing is not to scale.
Table 75. LQFP32 mechanical data
Millimeters
Inches(1)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
-
1.600
0.150
1.450
-
-
-
0.0630
0.0059
0.0571
A1
A2
0.050
1.350
0.0020
0.0531
1.400
0.0551
DS9994 Rev 9
105/125
121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
Table 75. LQFP32 mechanical data (continued)
Millimeters
Typ.
Inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
b
c
0.300
0.090
8.800
6.800
-
0.370
-
0.450
0.200
9.200
7.200
-
0.0118
0.0146
-
0.0177
0.0079
0.3622
0.2835
-
0.0035
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3465
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
0.2677
-
8.800
6.800
-
9.200
7.200
-
0.3465
0.3622
0.2835
-
E1
E3
e
0.2677
-
-
-
-
-
L
0.450
-
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
0.0°
-
7.0°
0.100
7.0°
ccc
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. Recommended footprint for the LQFP32 package
0.80
1.20
24
17
25
16
0.50
0.30
7.30
6.10
9.70
7.30
32
9
8
1
1.20
6.10
9.70
5V_FP_V2
1. Drawing is not to scale.
2. Dimensions are expressed in millimeters.
106/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Device marking for LQFP32
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 37. LQFP32 marking example (package top view)
Product Identification(1)
STM32F
334K6T6
Y WW
Revision code
R
Pin 1
indentifier
MSv33098V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS9994 Rev 9
107/125
121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
7.3
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7mm low-profile quad flat package.
Figure 38. LQFP48 package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
36
25
37
24
b
48
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
Table 76. LQFP48 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
0.3543
0.2756
0.2165
D1
D3
108/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Package information
Table 76. LQFP48 package mechanical data (continued)
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
E
E1
E3
e
8.800
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
9.200
0.3465
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
0.3622
6.800
7.200
0.2677
0.2835
-
-
-
-
-
-
-
0.750
-
-
0.0295
-
L
0.450
0.0177
L1
k
-
0°
-
7°
0°
-
7°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 39. Recommended footprint for the LQFP48 package
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Drawing is not to scale.
2. Dimensions are in millimeters.
DS9994 Rev 9
109/125
121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
Device marking for LQFP48
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 40. LQFP48 marking example (package top view)
Product Identification(1)
STM32F
334C6T6
Y WW
Revision code
R
Pin 1
indentifier
MSv33099V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
110/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Package information
7.4
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 41. LQFP64 package outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
D1
D3
L
L1
33
48
32
49
64
b
17
16
1
PIN 1
e
IDENTIFICATION
5W_ME_V3
1. Drawing is not to scale.
Table 77. LQFP64 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
11.800
9.800
-
-
1.600
-
-
0.0630
-
0.150
0.0020
-
0.0059
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.270
0.0067
0.0106
c
0.200
0.0035
0.0079
D
12.000
10.000
12.000
10.000
0.500
-
-
-
-
-
-
-
-
-
-
0.4724
0.3937
0.4724
0.3937
0.0197
-
-
-
-
-
D1
E
E1
e
-
-
DS9994 Rev 9
111/125
121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
Table 77. LQFP64 package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
θ
L
0°
0.450
-
3.5°
7°
0.750
-
0°
0.0177
-
3.5°
7°
0.0295
-
0.600
1.000
0.0236
0.0394
L1
Number of pins
64
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. Recommended footprint for the LQFP64 package
48
33
0.3
0.5
49
32
12.7
10.3
10.3
7.8
17
64
1.2
16
1
12.7
ai14909c
1. Drawing is not to scale.
2. Dimensions are in millimeters.
112/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Device marking for LQFP64
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 43. LQFP64 marking example (package top view)
Revision code
Engineering Sample marking(1)
R
STM32F334
R6T6
Pin 1
indentifier
Y WW
MSv33100V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
7.5
WLCSP49 package information
Figure 44. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
package outline
bbb
Z
A1 BALL LOCATION
e1
A1
F
7
1
G
A
DETAIL A
e2 E
E
e
G
aaa
e
A2
D
D
A
TOP VIEW
BOTTOM VIEW
SIDE VIEW
A3
A2
BUMP
FRONT VIEW
A2
SEATING PLANE
DETAIL A
ROTATED 90
B01F_WLCSP49_ME_V1
1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3. Bump position designation per JESD 95-1, SPP-010.
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Package information
Table 78. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
b
-
-
0.23
0.36
0.025(2)
0.33
3.89
3.74
0.50
3.00
3.00
0.445(3)
0.370(4)
-
0.62
-
-
0.0244
-
-
-
0.009
0.014
0.001
0.013
0.153
0.147
0.020
0.118
0.118
0.017
0.015
-
-
-
-
-
-
-
-
-
-
0.30
0.36
3.91
3.76
-
0.012
0.014
0.154
0.148
-
D
3.87
0.152
E
3.72
0.146
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
F
-
-
-
-
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.10
0.05
0.05
0.004
0.004
0.004
0.002
0.002
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. A3 value is guaranteed by technology design value.
3. This value is calculated from over value D and e1.
4. This value is calculated from over value E and e2.
Figure 45. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
recommended footprint
Dpad
Dsm
B01F_WLCSP49_FP_V1
1. Dimensions are expressed in millimeters.
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Package information
STM32F334x4 STM32F334x6 STM32F334x8
Table 79. WLCSP - 49 ball, 3.89x3.74 mm, 0.5 mm pitch, wafer level chip scale,
recommended PCB design rules
Dimension
Recommended values
Pitch
Dpad
0.5 mm
0.290 mm
0.350 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.310 mm
0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 46. WLCSP49 marking example (package top view)
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
116/125
DS9994 Rev 9
STM32F334x4 STM32F334x6 STM32F334x8
Package information
7.6
UFQFPN32 package information
Figure 47. UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
package outline
D1
E1
e
L
Pin 1 identifier
e
b
BOTTOM VIEW
A1
A3
DETAIL A
FRONT VIEW
Pin 1 identifier
LASER MARKING AREA
A3
A1
A
E
SEATING
PLANE
e
b
DETAIL A
D
A09E_ME_V1
TOP VIEW
1. Drawing is not in scale.
DS9994 Rev 9
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121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
Table 80. UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A(2)
A1
A3
b
0.500
0
0.550
0.020
0.152
0.250
5.000
3.500
5.000
3.500
0.500
0.400
-
0.600
0.050
-
0.0197
0
0.0217
0.0008
0.0060
0.0098
0.1969
0.1378
0.1969
0.1378
0.0197
0.0157
-
0.0236
0.0020
-
-
-
0.180
4.900
3.400
4.900
3.400
-
0.280
5.100
3.600
5.100
3.600
-
0.0071
0.1929
0.1339
0.1929
0.1339
-
0.0110
0.2008
0.1417
0.2008
0.1417
-
D(3)
D1
E(3)
E1
e
L
0.300
-
0.500
0.080
0.0118
-
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. UFQFPN stands for Thermally Enhanced Ultrathin Fine pitch Quad Flat Package No lead.
3. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.
Figure 48. UFQFPN - 32 pin, 5 x 5 mm 0.5 mm pitch ultra thin fine pitch quad flat
recommended footprint
5.30
3.80
0.60
3.80
5.30
0.50
0.30
0.75
3.80
A09E_FP_V1
1. Dimensions are expressed in millimeters.
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Device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 49. UFQFPN32 marking example (package top view)
Product identification (1)
E334K6U
Y WW
Revision code
R
Pin 1 identifier
MSv44309V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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121
Package information
STM32F334x4 STM32F334x6 STM32F334x8
7.7
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in ° C,
A
Θ
is the package junction-to-ambient thermal resistance, in ° C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 81. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
55
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP32 - 7 × 7 mm / 0.8 mm pitch
Θ
60
°C/W
JA
Thermal resistance junction-ambient
UFQFN32 - 5 x 5 mm
37
Thermal resistance junction-ambient
WLCSP49 - 3.89 x 3.74 mm / 0.5 mm pitch
48.3
7.7.1
7.7.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available at the www.jedec.org website.
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 82: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and to a specific maximum junction temperature.
As applications do not commonly use the STM32F334x4/6/8 microcontroller at maximum
dissipation, it is useful to calculate the exact power consumption and junction temperature
to determine which temperature range is best suited to the application.
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DS9994 Rev 9
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Package information
The following examples show how to calculate the temperature range needed for a given
application.
Example: high-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
mode at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V = 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Thus: P
= 447 mW
Dmax
Using the values obtained in Table 81: Package thermal characteristics, T
is calculated
Jmax
as follows:
–
T
For LQFP64, 45 °C/W
= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 82: Ordering information scheme).
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Ordering information
STM32F334x4 STM32F334x6 STM32F334x8
8
Ordering information
Table 82. Ordering information scheme
STM32 334
Example:
F
C
8
T
6
xxx
Device family
®
STM32 = Arm -based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
334 = STM32F334xx, 2.0 to 3.6 V operating voltage
Pin count
K = 32 pins
C = 48 or 49 pins
R = 64 pins
Flash memory size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory
Package
T = LQFP
Y = WLCSP
U = UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
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Revision history
9
Revision history
Table 83. Document revision history
Date
Revision
Changes
19-Jun-2014
1
Initial release.
Updated:
– Table 54: TIMx characteristics
– Table 14: STM32F334x6/8 pin definitions
– Table 59: ADC characteristics
– Table 34: Peripheral current consumption
– Table 40: HSI oscillator characteristics
09-Dec-2014
2
– Table 17: HSI oscillator accuracy characterization results
for soldered parts
– Table 2: STM32F334x4/6/8 family device features and
peripheral counts
Updated:
– Figure 1: STM32F334x4/6/8 block diagram
– Table 38: HSE oscillator characteristics
– Table 43: Flash memory characteristics
2-Feb-2015
09-Jun-2015
3
4
Added Figure 15: High-speed external clock source AC timing
diagram
Updated:
– Title
– Section 3.14.1: 217 ps high-resolution timer (HRTIM1)
– Section 6.1.6: Power-supply scheme
– Table 19: General operating conditions
Updated:
Section Table 69.: DAC characteristics, Section Table 64.:
ADC characteristics,Table 53: NRST pin characteristics,
Figure 2: Clock tree, Table 13: STM32F334x4/6/8 pin
definitions, Table 71: Operational amplifier characteristics,
Figure 22: 5V- tolerant (FT and FTf) I/O input characteristics -
CMOS port, Table 23: Embedded internal reference voltage,
Table 39: LSE oscillator characteristics (fLSE = 32.768 kHz)
27-Sep-2016
5
Added Table 35: Wakeup time using USART.
Updated:
– Table 2: STM32F334x4/6/8 family device features and
peripheral counts
– Table 13: STM32F334x4/6/8 pin definitions
– Table 19: General operating conditions
– Table 81: Package thermal characteristics
– Table 82: Ordering information scheme
Added:
15-May-2017
6
– Figure 7: WLCSP49 ballout
– Section 7.5: WLCSP49 package information
DS9994 Rev 9
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124
Revision history
STM32F334x4 STM32F334x6 STM32F334x8
Table 83. Document revision history (continued)
Date
Revision
Changes
Updated:
– Footnotes of Table 25: Typical and maximum current
23-Nov--2017
19-Dec-2017
7
consumption from VDD supply at VDD = 3.6V
– Footnotes of Table 26: Typical and maximum current
consumption from the VDDA supply
Updated Table 1: Device summary: STM32F334R4 product
not covered by this datasheet
8
9
Updated:
– Table 2: STM32F334x4/6/8 family device features and
peripheral counts
– Table 13: STM32F334x4/6/8 pin definitions
– Table 19: General operating conditions
– Table 81: Package thermal characteristics
– Table 82: Ordering information scheme
Added:
16-Jul-2018
– Figure 8: UFQFPN32 pinout
– Section 7.6: UFQFPN32 package information
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DS9994 Rev 9
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS9994 Rev 9
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