STM32F412ZG [STMICROELECTRONICS]
ARM-Cortex-M4 32b MCUFPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces;
| 型号： | STM32F412ZG |
| 厂家： | 
ST |
| 描述： | ARM-Cortex-M4 32b MCUFPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces |
| 文件： | 总193页 (文件大小：2701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F412xE STM32F412xG
ARM®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash,
256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces
Datasheet - production data
Features
)%*$
• Dynamic Efficiency Line with BAM (Batch
Acquisition Mode)
®
®
UFBGA100
(7x7mm)
LQFP64 (10x10mm)
LQFP100 (14x14mm)
LQFP144 (20x20mm)
WLCSP64
(3.623x3.651mm)
• Core: ARM 32-bit Cortex -M4 CPU with
FPU, Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 100 MHz,
memory protection unit,
UFQFPN48
(7x7 mm)
UFBGA144
(10x10mm)
• Up to 17 timers: up to twelve 16-bit timers, two
32-bit timers up to 100 MHz each with up to
four IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input, two
watchdog timers (independent and window),
one SysTick timer
125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions
• Memories
– Up to 1 Mbyte of Flash memory
– 256 Kbyte of SRAM
– Flexible external static memory controller
with up to 16-bit data bus: SRAM, PSRAM,
NOR Flash memory
• Debug mode
– Serial wire debug (SWD) & JTAG
®
– Cortex -M4 Embedded Trace Macrocell™
• Up to 114 I/O ports with interrupt capability
– Dual mode Quad-SPI interface
– Up to 109 fast I/Os up to 100 MHz
– Up to 114 five V-tolerant I/Os
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
• Up to 17 communication interfaces
2
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
– Up to 4x I C interfaces (SMBus/PMBus)
– Up to 4 USARTs (2 x 12.5 Mbit/s,
2 x 6.25 Mbit/s), ISO 7816 interface, LIN,
IrDA, modem control)
– Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or
I2S audio protocol), out of which 2 muxed
full-duplex I2S interfaces
• Power consumption
– SDIO interface (SD/MMC/eMMC)
– Run: 112 µA/MHz (peripheral off)
– Advanced connectivity: USB 2.0 full-speed
device/host/OTG controller with PHY
– 2x CAN (2.0B Active)
– Stop (Flash in Stop mode, fast wakeup
time): 50 µA Typ @ 25 °C; 75 µA max
@25 °C
• True random number generator
– Stop (Flash in Deep power down mode,
slow wakeup time): down to 18 µA @
25 °C; 40 µA max @25 °C
• CRC calculation unit
• 96-bit unique ID
• RTC: subsecond accuracy, hardware calendar
– Standby: 2.4 µA @25 °C / 1.7 V without
RTC; 12 µA @85 °C @1.7 V
®
• All packages are ECOPACK 2
Table 1. Device summary
– V
supply for RTC: 1 µA @25 °C
BAT
Reference
Part number
• 1×12-bit, 2.4 MSPS ADC: up to 16 channels
STM32F412CE, STM32F412RE, STM32F412VE,
STM32F412ZE
• 2x digital filters for sigma delta modulator,
STM32F412xE
4x PDM interfaces, stereo microphone support
STM32F412CG, STM32F412RG, STM32F412VG,
STM32F412ZG
STM32F412xG
• General-purpose DMA: 16-stream DMA
May 2016
DocID028087 Rev 4
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This is information on a product in full production.
www.st.com
Contents
STM32F412xE/G
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . 19
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19
Batch Acquisition mode (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12 Quad-SPI memory interface (QUAD-SPI) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31
3.20 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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3.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 37
3.26 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.27 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 38
3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
3.31 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.32 Universal serial bus on-the-go full-speed (USB_OTG_FS) . . . . . . . . . . . 40
3.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.35 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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Contents
STM32F412xE/G
6.1.6
6.1.7
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Operating conditions at power-up/power-down (regulator ON) . . . . . . . 79
Operating conditions at power-up / power-down (regulator OFF) . . . . . 80
Embedded reset and power control block characteristics . . . . . . . . . . . 80
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 110
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 115
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.22
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
BAT
6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.24 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.26 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 159
6.3.27 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.1
7.2
7.3
WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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7.4
7.5
7.6
7.7
7.8
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.8.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Appendix A Recommendations when using the internal reset OFF . . . . . . . . 186
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
B.1
B.2
B.3
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 187
Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
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List of tables
STM32F412xE/G
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F412xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 31
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM32F412xE/G pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32F412xE/G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
STM32F412xE/G register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 78
VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 79
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 80
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DD
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- V = 1.7 V. . . 84
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - V = 3.6 V . . 85
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - V = 3.6 V. . . . . . . . . . . . . . . 86
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - V = 1.7 V. . . . . . . . . . . . . . . 87
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - V = 3.6 V. . . . . 88
DD
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Typical and maximum current consumption in Sleep mode - V = 3.6 V. . . . . . . . . . . . . 89
DD
Typical and maximum current consumption in Sleep mode - V = 1.7 V. . . . . . . . . . . . . 90
DD
Typical and maximum current consumptions in Stop mode - V = 1.7 V . . . . . . . . . . . . . 91
DD
Typical and maximum current consumption in Stop mode - V =3.6 V. . . . . . . . . . . . . . . 92
DD
Typical and maximum current consumption in Standby mode - V = 1.7 V . . . . . . . . . . . 92
DD
Typical and maximum current consumption in Standby mode - V = 3.6 V . . . . . . . . . . . 92
DD
Typical and maximum current consumptions in V
mode. . . . . . . . . . . . . . . . . . . . . . . . 93
BAT
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
(1)
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LSE
6/193
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List of tables
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Flash memory programming with V voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PP
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
EMS characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
EMI characteristics for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
SCL frequency (f
= 50 MHz, V = V
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 125
PCLK1
DD
DD_I2C
2
FMPI C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
2
I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ADC accuracy at f
ADC accuracy at f
ADC accuracy at f
= 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
= 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
ADC
ADC
ADC
ADC dynamic accuracy at f
ADC dynamic accuracy at f
= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 138
= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 138
ADC
ADC
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
BAT
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
Table 84.
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 148
Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
Table 85.
Table 86.
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 150
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 152
Table 87.
Table 88.
Table 89.
Table 90.
DocID028087 Rev 4
7/193
8
List of tables
STM32F412xE/G
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 157
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . 161
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
WLCSP64 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 163
Table 99.
Table 100. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 101. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 102. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 103. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 104. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 105. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 179
Table 106. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 107. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 182
Table 108. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 109. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 110. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
8/193
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32F412xE/G block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 25
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Startup in regulator OFF: slow V slope
DD
power-down reset risen after V
/V
stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 30
CAP_1 CAP_2
Figure 10. Startup in regulator OFF mode: fast V slope
DD
power-down reset risen before V
/V
stabilization. . . . . . . . . . . . . . . . . . . . . . . . 30
CAP_1 CAP_2
Figure 11. STM32F412xE/G WLCSP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. STM32F412xE/G UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 13. STM32F412xE/G LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 14. STM32F412xE/G LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 15. STM32F412xE/G LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16. STM32F412xE/G UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17. STM32F412xE/G UFBGA144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 18. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 19. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 20. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 23. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
EXT
Figure 24. Typical V
current consumption (LSE and RTC ON/LSE oscillator
BAT
“low power” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 25. Typical V current consumption (LSE and RTC ON/LSE oscillator
BAT
“high drive” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 26. Low-power mode wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 28. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 31. ACC
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
HSI
Figure 32. ACC versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LSI
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 35. FT/TC I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 36. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2
Figure 38. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2
Figure 39. FMPI C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
(1)
Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
(1)
Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
2
(1)
Figure 43. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
2
(1)
Figure 44. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
DocID028087 Rev 4
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11
List of figures
STM32F412xE/G
Figure 45. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 135
Figure 46. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 47. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 48. Power supply and reference decoupling (V
Figure 49. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 141
). . . . . . . . . . . . . . . . 142
REF+
DDA
connected to V
REF+
DDA
Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 146
Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 148
Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 54. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 55. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 57. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 58. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 59. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 61. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 62. WLCSP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 63. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 64. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 65. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 168
Figure 67. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 68. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 69. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 171
Figure 70. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 71. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 72. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 174
Figure 73. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 74. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 75. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 77. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 78. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 80. UFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 81. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 187
Figure 82. USB peripheral-only Full speed mode with direct connection
for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 83. USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 188
Figure 84. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 188
Figure 85. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 189
Figure 86. Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
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List of figures
Figure 87. Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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11
Introduction
STM32F412xE/G
1
Introduction
This datasheet provides the description of the STM32F412xE/G microcontrollers.
ꢀ
ꢀ
For information on the Cortex -M4 core, refer to the Cortex -M4 programming manual
(PM0214) available from www.st.com.
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Description
2
Description
®
®
The STM32F412XE/G devices are based on the high-performance ARM Cortex -M4 32-
®
bit RISC core operating at a frequency of up to 100 MHz. Their Cortex -M4 core features a
Floating point unit (FPU) single precision which supports all ARM single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F412XE/G belong to the STM32 Dynamic Efficiency™ product line (with
products combining power efficiency, performance and integration) while adding a new
innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power
consumption during data batching.
The STM32F412XE/G incorporate high-speed embedded memories (up to 1 Mbyte of Flash
memory, 256 Kbyte of SRAM), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer one 12-bit ADC, a low-power RTC, twelve general-purpose 16-bit timers,
two PWM timer for motor control and two general-purpose 32-bit timers.
They also feature standard and advanced communication interfaces.
2
2
•
•
•
Up to four I Cs, including one I C supporting Fast-Mode Plus
Five SPIs
2
2
Five I Ss out of which two are full duplex. To achieve audio class accuracy, the I S
peripherals can be clocked via a dedicate internal audio PLL or via an external clock to
allow synchronization.
•
•
•
•
Four USARTs
An SDIO/MMC interface
An USB 2.0 OTG full-speed interface
Two CANs.
In addition, the STM32F412xE/G embed advanced peripherals:
•
•
•
A flexible static memory control interface (FSMC)
A Quad-SPI memory interface
A digital filter for sigma modulator (DFSDM), two filters, up to four inputs, and support
of microphone MEMs.
The STM32F412xE/G are offered in 7 packages ranging from 48 to 144 pins. The set of
available peripherals depends on the selected package. Refer to Table 2: STM32F412xE/G
features and peripheral counts for the peripherals available for each part number.
The STM32F412xE/G operates in the – 40 to + 105 °C temperature range from a 1.7 (PDR
OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design
of low-power applications.
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42
Description
STM32F412xE/G
These features make the STM32F412xE/G microcontrollers suitable for a wide range of
applications:
•
•
•
•
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile phone sensor hub
Wearable devices
Connected objects
Wifi modules
Figure 4 shows the general block diagram of the devices.
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STM32F412xE/G
Description
Table 2. STM32F412xE/G features and peripheral counts
Peripherals
STM32F412xE
STM32F412xG
1024
Flash memory (Kbyte)
512
SRAM
System
(Kbyte)
256
FSMC memory controller
-
1
-
1
Quad-SPI memory
interface
-
1
-
1
General-
purpose
10
2
Timers
Advanced-
control
Basic
2
1
Random number generator
SPI/ I2S
I2C
5/5 (2 full duplex)
3
1
3
1
I2CFMP
USART
3
4
4
Comm.
interfaces
SDIO/MMC
1
1
USB/OTG FS
Dual power rail
1
No
1
No
Yes
Yes
CAN
2
Number of digital Filters for
Sigma-delta modulator
2
3
2
4
2
2
4
3
-
Number of channels
LCD parallel interface
Data bus size
-
8
16
8
16
GPIOs
36
50
81
16
114
36
10
50
81
16
114
1
12-bit ADC
Number of channels
10
Maximum CPU frequency
Operating voltage
100 MHz
1.7 to 3.6 V
Ambient temperatures: –40 to +85 °C/–40 to +105 °C
Junction temperature: –40 to + 125 °C
Operating temperatures
Package
UFBGA
100
UFBGA
144
LQFP64 UFBGA
UFBGA
144
UFQ
LQFP64
FPN48 WLCSP64
UFQ
FPN48
WLCSP
64
100
LQFP100 LQFP144
LQFP100 LQFP144
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42
Description
STM32F412xE/G
2.1
Compatibility with STM32F4 series
The STM32F412xE/G are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F412xE/G can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
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DocID028087 Rev 4
STM32F412xE/G
Description
Figure 2. Compatible board design for LQFP64 package
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42
Description
STM32F412xE/G
Figure 4. STM32F412xE/G block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 50 MHz.
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Functional overview
3
Functional overview
3.1
ARM® Cortex®-M4 with FPU core with embedded Flash and
SRAM
®
®
The ARM Cortex -M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
®
®
The ARM Cortex -M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an ARM core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F412xE/G devices are compatible with all ARM tools and software.
Figure 4 shows the general block diagram of the STM32F412xE/G.
®
®
Note:
Cortex -M4 with FPU is binary compatible with Cortex -M3.
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
®
®
®
standard ARM Cortex -M4 with FPU processors. It balances the inherent performance
®
advantage of the ARM Cortex -M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 125 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 100 MHz.
3.3
Batch Acquisition mode (BAM)
The Batch acquisition mode allows enhanced power efficiency during data batching. It
enables data acquisition through any communication peripherals directly to memory using
the DMA in reduced power consumption as well as data processing while the rest of the
system is in low-power mode (including the flash and ART). For example in an audio
system, a smart combination of PDM audio sample acquisition and processing from the
DFSDM directly to RAM (flash and ART™ stopped) with the DMA using BAM followed by
some very short processing from flash allows to drastically reduce the power consumption
of the application. A dedicated application note (AN4515) describes how to implement the
STM32F412xE/G BAM to allow the best power efficiency.
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42
Functional overview
STM32F412xE/G
3.4
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of
addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.5
Embedded Flash memory
The devices embed up to 1 Mbyte of Flash memory available for storing programs and data.
The Flash user area can be protected against reading by an entrusted code (Read
Protection, RDP) with different protection levels.
The flash user sectors can also be individually protected against write operation.
Furthermore the proprietary readout protection (PCROP) can also individually protect the
flash user sectors against D-bus read accesses.
(Additional information can be found in the product reference manual).
To optimize the power consumption the Flash memory can also be switched off in Run or in
Sleep mode (see Section 3.21: Low-power modes).
Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between
power saving and startup time.
Before disabling the Flash, the code must be executed from the internal RAM.
3.6
3.7
One-time programmable bytes
A one-time programmable area is available with16 OTP blocks of 32 bytes. Each block can
be individually locked
(Additional information can be found in the product reference manual)
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
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Functional overview
3.8
Embedded SRAM
All devices embed 256 Kbyte of system SRAM which can be accessed (read/write) at CPU
clock speed with 0 wait states
3.9
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 5. Multi-AHB matrix
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3.10
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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Functional overview
STM32F412xE/G
The DMA can be used with the main peripherals:
2
•
•
•
•
•
•
•
•
SPI and I S
2
2
I C and I CFMP
USART
General-purpose, basic and advanced-control timers TIMx
SD/SDIO/MMC/eMMC host interface
Quad-SPI
ADC
Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter.
3.11
Flexible static memory controller (FSMC)
The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It
features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR
Flash memory.
The main functions are:
•
•
•
8-,16-bit data bus width
Write FIFO
Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.12
Quad-SPI memory interface (QUAD-SPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode
through registers, external Flash status register polling mode and memory mapped mode.
Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or
32-bit mode. Code execution is also supported. The opcode and the frame format are fully
programmable. Communication can be performed either in single data rate or dual data
rate.
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Functional overview
3.13
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the
®
Cortex -M4 with FPU.
•
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.14
3.15
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 21 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB
buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the
low-speed APB domain is 50 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
2
performance. In this case, the I S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
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Functional overview
STM32F412xE/G
3.16
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
•
•
Boot from user Flash memory
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using one of the interface listed in the Table 3 or the USB OTG FS in device mode through
DFU (device firmware upgrade).
Table 3. Embedded bootloader interfaces
SPI3
SPI1
PA4/
PA5/
PA6/
PA7
SPI4
I2C
USART1 USART2 USART3 I2C1 I2C2 I2C3
PE11/ CAN2 USB
PE12/ PB5/ PA11
PE13/ PB13 /P12
PE14
PA15/
PC10/
PC11/
PC12
FMP1
PB14/
PB15
Package
PA9/
PA10
PD6/
PD5
PB11/
PB10
PB6/ PF0/ PA8/
PB7 PF1 PB4
UFQFPN48
WLCSP64
LQFP64
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
LQFP100
LQFP144
UFBGA100
UFBGA144
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
3.17
Power supply schemes
•
V
= 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
DD
(POR/PDR) disabled, provided externally through V pins. Requires the use of an
DD
external power supply supervisor connected to the V and NRST pins.
DD
•
V
, V
= 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
SSA DDA
and PLL. V
and V
must be connected to V and V , respectively, with
SSA DD SS
DDA
decoupling technique.
Note:
The V /V minimum value of 1.7 V is obtained with the use of an external power supply
DD DDA
supervisor (refer to Section 3.18.2: Internal reset OFF). Refer to Table 4: Regulator ON/OFF
and internal power supply supervisor availability to identify the packages supporting this
option.
•
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
•
V
can be connected either to VDD or an external independent power supply (3.0
DDUSB
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8 V, an independent power supply 3.3V can
be connected to V
. When the V
is connected to a separated power supply,
DDUSB
DDUSB
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Functional overview
it is independent from V or V
but it must be the last supply to be provided and the
DDA
DD
first to disappear.
The following conditions VDDUSB must be respected:
–
During power-on phase (V < V
), V
should be always lower than
DDUSB
DD
DD_MIN
V
DD
–
During power-down phase (V < V
), V
should be always lower than
DDUSB
DD
DD_MIN
V
DD
–
–
V
rising and falling time rate specifications must be respected.
DDUSB
In operating mode phase, V
could be lower or higher than VDD:
DDUSB
– If USB is used, the associated GPIOs powered by V
are operating
DDUSB
between V
and V
.
DDUSB_MIN
DDUSB_MAX
– If USB is not used, the associated GPIOs powered by V
are operating
DDUSB
between V
and V
.
DD_MIN
DD_MAX
Figure 6. V
connected to an external independent power supply
DDUSB
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Functional overview
STM32F412xE/G
3.18
Power supply supervisor
3.18.1
Internal reset ON
This feature is available for V operating voltage range 1.8 V to 3.6 V.
DD
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The device remains in reset mode when V is below a specified threshold, V
or
POR/PDR
DD
V
, without the need for an external reset circuit.
BOR
The device also features an embedded programmable voltage detector (PVD) that monitors
the V /V power supply and compares it to the V threshold. An interrupt can be
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is
DD DDA
PVD
DD DDA
higher than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.18.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor V and should set the device in reset
DD
mode when V is below 1.7 V. NRST should be connected to this external power supply
DD
supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset
OFF.
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Functional overview
(1)
Figure 7. Power supply supervisor interconnection with internal reset OFF
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1. The PRD_ON pin is available only on WLCSP64, UFBGA100, UFBGA144 and LQFP144 packages.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
•
•
•
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled.
The embedded programmable voltage detector (PVD) is disabled.
V
functionality is no more available and VBAT pin should be connected to V
.
BAT
DD
3.19
Voltage regulator
The regulator has three operating modes:
–
–
–
Main regulator mode (MR)
Low power regulator (LPR)
Power-down
3.19.1
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
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Functional overview
STM32F412xE/G
There are three power modes configured by software when the regulator is ON:
•
MR is used in the nominal regulation mode (With different voltage scaling in Run mode)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
•
•
LPR is used in the Stop mode
The LP regulator mode is configured by software when entering Stop mode.
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the 100 pins and 144 pins
packages.
All packages have the regulator ON feature.
3.19.2
Regulator OFF
This feature is available only on UFBGA100 and UFBGA144 packages, which feature the
BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator
OFF mode allows to supply externally a V voltage source through V
and V
12
CAP_1
CAP_2
pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
When the regulator is OFF, there is no more internal monitoring on V . An external power
12
supply supervisor should be used to monitor the V of the logic power domain. PA0 pin
12
should be used for this purpose, and act as power-on reset on V power domain.
12
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V logic power
domain which is not reset by the NRST pin.
12
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
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Functional overview
Figure 8. Regulator OFF
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The following conditions must be respected:
•
V
should always be higher than V
and V
to avoid current injection
CAP_2
DD
CAP_1
between power domains.
•
If the time for V and V
to reach V minimum value is faster than the time for
CAP_1
CAP_2
12
V
to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
DD
CAP_1
and V
reach V minimum value and until V reaches 1.7 V (see Figure 9).
12 DD
CAP_2
•
•
Otherwise, if the time for V
and V
to reach V minimum value is slower
CAP_2 12
CAP_1
than the time for V to reach 1.7 V, then PA0 could be asserted low externally (see
DD
Figure 10).
If V
and V
go below V minimum value and V is higher than 1.7 V, then a
CAP_2 12 DD
CAP_1
reset must be asserted on PA0 pin.
Note:
The minimum value of V depends on the maximum frequency targeted in the application.
12
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Functional overview
STM32F412xE/G
Figure 9. Startup in regulator OFF: slow V slope
DD
power-down reset risen after V
/V
stabilization
CAP_1 CAP_2
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1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast V slope
DD
power-down reset risen before V
/V
stabilization
CAP_1 CAP_2
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1. This figure is valid whatever the internal reset mode (ON or OFF).
30/193
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3.19.3
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal power supply supervisor availability
Power supply
supervisor ON
Power supply
supervisor OFF
Package
Regulator ON
Regulator OFF
UFQFPN48
WLCSP64
Yes
Yes
No
No
Yes
Yes
No
Yes
PDR_ON set to VDD PDR_ON set to VSS
LQFP64
LQFP100
LQFP144
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
No
Yes
UFBGA100
UFBGA144
BYPASS_REG set to BYPASS_REG set to
Yes
Yes
VSS
VDD
PDR_ON set to VDD PDR_ON set to VSS
Yes
Yes
BYPASS_REG set to BYPASS_REG set to
VSS VDD
3.20
Real-time clock (RTC) and backup registers
The backup domain includes:
•
•
The real-time clock (RTC)
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC features a reference clock detection, a more precise
second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC
provides a programmable alarm and programmable periodic interrupts with wakeup from
Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup registers are 32-bit registers used to store 80 byte of user application data
when V power is not present. Backup registers are not reset by a system, a power reset,
DD
or when the device wakes up from the Standby mode (see Section 3.21: Low-power
modes).
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Functional overview
STM32F412xE/G
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
The RTC and backup registers are supplied through a switch that is powered either from the
V
supply when present or from the V
pin.
DD
BAT
3.21
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
To further reduce the power consumption, the Flash memory can be switched off
before entering in Sleep mode. Note that this requires a code execution from the RAM.
•
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/
tamper/ time stamp events).
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on one of the WKUP pins, or an RTC alarm/ wakeup/ tamper/time stamp
event occurs.
Standby mode is not supported when the embedded voltage regulator is bypassed and
the 1.2 V domain is controlled by an external power.
3.22
VBAT operation
The VBAT pin allows to power the device V
domain from an external battery, an external
BAT
super-capacitor, or from V when no external battery and an external super-capacitor are
DD
present.
V
operation is activated when V is not present.
DD
BAT
The VBAT pin supplies the RTC and the backup registers.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from V
operation. When PDR_ON pin is not connected to V (internal
BAT
DD
Reset OFF), the V
functionality is no more available and VBAT pin should be connected
BAT
to V
.
DD
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Functional overview
3.23
Timers and watchdogs
The devices embed two advanced-control timer, ten general-purpose timers, two basic
timers, two watchdog timers and one SysTick timer.
All timer counters can be frozen in debug mode.
Table 5 compares the features of the advanced-control and general-purpose timers.
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Table 5. Timer feature comparison
Max.
Max.
DMA
request
generation channels
Capture/
compare
Timer
type
Counter Counter Prescaler
Complemen- interface timer
Timer
resolution
type
factor
tary output
clock
(MHz) (MHz)
clock
Any
Up,
integer
Advance TIM1,
d-control TIM8
16-bit
Down, between1
Up/down
Yes
Yes
Yes
No
4
4
4
2
1
2
1
0
Yes
100
50
100
100
100
100
100
100
100
100
and
65536
Any
integer
Down, between1
Up,
TIM2,
TIM5
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
No
No
No
No
No
No
No
Up/down
and
65536
Any
integer
Down, between1
Up,
TIM3,
TIM4
50
Up/down
and
65536
Any
integer
between1
and
TIM9
Up
100
100
50
65536
General
purpose
Any
integer
between1
and
TIM10,
TIM11
Up
Up
Up
Up
No
65536
Any
integer
between1
and
TIM12
No
65536
Any
integer
between1
and
TIM13,
TIM14
No
50
65536
Any
integer
between1
and
Basic
timers
TIM6,
TIM7
Yes
50
65536
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Functional overview
3.23.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator
multiplexed on 4 independent channels. They have complementary PWM outputs with
programmable inserted dead times. They can also be considered as complete general-
purpose timers. Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as a 16-bit PWM generator, they have full modulation capability
(0-100%).
The advanced-control timers can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.23.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F412xE/G
(see Table 5 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F412xE/G devices include 4 full-featured general-purpose timers: TIM2.
TIM3, TIM4 and TIM5. TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter plus a 16-bit prescaler. They all features four
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 15 input capture/output compare/PWMs
TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in
conjunction with the other general-purpose timers and TIM1 advanced-control timer via
the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM output.
TIM2. TIM3, TIM4 and TIM5 channels have independent DMA request generation.
They are capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13 and TIM14 feature one independent channel, whereas TIM9 and
TIM12 have two independent channels for input capture/output compare, PWM or one-
pulse mode output. They can be synchronized with TIM2. TIM3, TIM4 and TIM5 full-
featured general-purpose timers or used as simple time bases.
3.23.3
Basic timer (TIM6, TIM7)
TIM6 and TIM7 timers are basic 16-bit timers. They support independent DMA request
generation.
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3.23.4
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.23.5
3.23.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
3.24
Inter-integrated circuit interface (I2C)
2
The devices feature up to four I C bus interfaces which can operate in multimaster and
slave modes:
2
•
One I C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to
400 kHz) modes and Fast-mode plus (up to 1 MHz).
2
•
Three I C interfaces support the Standard mode (up to 100 KHz) and the Fast mode
(up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on
the complete solution, refer to the nearest STMicroelectronics sales office.
2
All I C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave)
and embed a hardware CRC generation/verification.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 6).
Table 6. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15 I2C peripheral clocks
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Functional overview
3.25
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6).
These four interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. USART1 and USART6 interfaces are able to
communicate at speeds of up to 12.5 Mbit/s. USART2 and USART3 interfaces
communicate at up to 6.25 bit/s.
All USART interfaces provide hardware management of the CTS and RTS signals, Smart
Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can
be served by the DMA controller.
Table 7. USART feature comparison
Max. baud
Max. baud
USART Standard Modem
SPI
master
Smartcard rate in Mbit/s rate in Mbit/s APB
(ISO 7816) (oversampling (oversampling mapping
LIN
irDA
name
features (RTS/CTS)
by 16)
by 8)
APB2
(max.
100 MHz)
USART1
USART2
USART3
USART6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
6.25
12.5
APB1
(max.
50 MHz)
3.12
3.12
6.25
6.25
6.25
12.5
APB1
(max.
50 MHz)
APB2
(max.
100 MHz)
3.26
Serial peripheral interface (SPI)
The devices feature five SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and
SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interfaces can be configured to operate in TI mode for communications in master
mode and slave mode.
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3.27
Inter-integrated sound (I2S)
2
Five standard I S interfaces (multiplexed with SPI1 to SPI5) are available. They can be
operated in master or slave mode, in simplex communication mode, and full duplex mode
2
for I2S2 and I2S3. All I S interfaces can be configured to operate with a 16-/32-bit resolution
as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz
2
are supported. When either or both of the I S interfaces is/are configured in master mode,
the master clock can be output to the external DAC/CODEC at 256 times the sampling
frequency.
2
All I Sx interfaces can be served by the DMA controller.
3.28
Audio PLL (PLLI2S)
2
The devices feature an additional dedicated PLL for audio I S applications. It allows to
2
achieve error-free I S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
Different sources can be selected for the I2S master clock of the APB1 and the I2S master
clock of the APB2. This gives the flexibility to work with two different audio sampling
frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI
clocks or an external clock provided through a pin (external PLL or Codec output)
2
The PLLI2S configuration can be modified to manage an I S sample rate change without
disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
3.29
Digital filter for sigma-delta modulators (DFSDM)
The device embeds one DFSDM with 2 digital filters modules and 4 external input serial
channels (transceivers) or alternately 2 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from microcontrollers
memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
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The DFSDM peripheral supports:
•
4 multiplexed input digital serial channels:
–
–
–
–
–
configurable SPI interface to connect various SD modulator(s)
configurable Manchester coded 1 wire interface support
PDM (Pulse Density Modulation) microphone input support
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
clock output for SD modulator(s): 0...20 MHz
•
•
alternative inputs from 4 internal digital parallel channels (up to 16 bit input resolution):
internal sources: device memory data streams (DMA)
–
2 digital filter modules with adjustable digital signal processing:
x
–
–
Sinc filter: filter order/type (1...5), oversampling ratio (up to 1...1024)
integrator: oversampling ratio (1...256)
•
•
•
•
up to 24-bit output data resolution, signed output data format
automatic data offset correction (offset stored in register by user)
continuous or single conversion
start-of-conversion triggered by
–
–
–
–
software trigger
internal timers
external events
start-of-conversion synchronously with first digital filter module (DFSDM1FLT0)
•
•
analog watchdog feature:
–
–
–
–
low value and high value data threshold registers
x
dedicated configurable Sinc digital filter (order = 1...3, oversampling ratio = 1...32
input from digital output data or from selected input digital serial channels
continuous monitoring independently from standard conversion
short circuit detector to detect saturated analog input values (bottom and top range):
–
–
up to 8-bit counter to detect 1...256 consecutive 0’s or 1’s on serial data stream
monitoring continuously each input serial channel
•
•
break signal generation on analog watchdog event or on short circuit detector event
extremes detector:
–
–
storage of minimum and maximum values of final conversion data
refreshed by software
•
•
DMA capability to read the final conversion data
interrupts: end of conversion, overrun, analog watchdog, short circuit input serial
channel clock absence
•
“regulator” or injected” conversions:
–
“regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority.
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Functional overview
STM32F412xE/G
3.30
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.31
3.32
Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 byte of SRAM are allocated for each CAN.
Universal serial bus on-the-go full-speed (USB_OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The Battery Charging Detection
(BCD) can detect and identify the type of port, it is connected to (standard USB or charger).
The type of charging is also detected: Dedicated Charging Port (DCP), Charging
Downstream Port (CDP) and Standard Downstream Port (SDP). Some packages provide a
dedicated USB power rail allowing a different supply for the USB and for the rest of the chip.
For instance the chip can be powered with the minimum specified supply and the USB
running at the level defined by the standard. The major features are:
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
•
•
Link Power Management (LPM)
Battery Charging Detection (BCD) supporting DCP, CDP and SDP
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Functional overview
3.33
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.34
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 100 MHz.
3.35
Analog-to-digital converter (ADC)
One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4 or TIM5 timer.
3.36
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the ADC_IN18 input channel which is used to convert the sensor output
voltage into a digital value. Refer to the reference manual for additional information.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.37
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
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Functional overview
STM32F412xE/G
3.38
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F412xE/G through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using any high-speed
channel available. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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Pinouts and pin description
4
Pinouts and pin description
Figure 11. STM32F412xE/G WLCSP64 pinout
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06ꢀꢈꢈꢅꢃ9ꢀ
1. The above figure shows the package top view.
DocID028087 Rev 4
43/193
67
Pinouts and pin description
STM32F412xE/G
Figure 13. STM32F412xE/G LQFP64 pinout
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06ꢀꢈꢈꢇꢊ9ꢀ
1. The above figure shows the package top view.
44/193
DocID028087 Rev 4
STM32F412xE/G
Pinouts and pin description
Figure 14. STM32F412xE/G LQFP100 pinout
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1. The above figure shows the package top view.
DocID028087 Rev 4
45/193
67
Pinouts and pin description
STM32F412xE/G
Figure 15. STM32F412xE/G LQFP144 pinout
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1. The above figure shows the package top view.
46/193
DocID028087 Rev 4
STM32F412xE/G
Pinouts and pin description
Figure 16. STM32F412xE/G UFBGA100 pinout
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06Yꢀꢁꢄꢂꢄ9ꢈ
1. The above figure shows the package top view.
DocID028087 Rev 4
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67
Pinouts and pin description
STM32F412xE/G
Figure 17. STM32F412xE/G UFBGA144 pinout
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1. The above figure shows the package top view.
Table 8. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
TC
B
Input/ output pin
5 V tolerant I/O
Standard 3.3 V I/O
I/O structure
Notes
Dedicated BOOT0 pin
NRST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Functions selected through GPIOx_AFR registers
Alternate
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
48/193
DocID028087 Rev 4
STM32F412xE/G
Pinouts and pin description
Table 9. STM32F412xE/G pin definition
Pin name
Pin Number
(function Pin
I/O
Additional
Alternate functions
functions
Notes
after
type structure
reset)(1)
TRACECLK,
SPI4_SCK/I2S4_CK,
-
-
-
-
-
-
-
1
B2 A3
1
2
3
PE2
PE3
PE4
I/O
I/O
I/O
FT
FT
FT
-
-
-
SPI5_SCK/I2S5_CK,
QUADSPI_BK1_IO2,
FSMC_A23, EVENTOUT
-
-
-
TRACED0, FSMC_A19,
EVENTOUT
-
2
A1 A2
B1 B2
TRACED1,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
DFSDM1_DATIN3,
-
3
FSMC_A20, EVENTOUT
TRACED2, TIM9_CH1,
SPI4_MISO, SPI5_MISO,
DFSDM1_CKIN3,
-
-
-
-
-
-
4
5
C2 B3
D2 B4
4
5
PE5
PE6
I/O
I/O
FT
FT
-
-
-
-
FSMC_A21, EVENTOUT
TRACED3, TIM9_CH2,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
FSMC_A22, EVENTOUT
1
2
1
2
B7
B8
6
7
E2 C2
C1 A1
6
7
VBAT
PC13
S
-
-
-
VBAT
(2)(3)
I/O
FT
EVENTOUT
TAMP_1
(2)(3)
(4)
PC14-
OSC32_IN
3
4
3
4
C8
C7
8
9
D1 B1
E1 C1
8
9
I/O
I/O
FT
FT
EVENTOUT
EVENTOUT
OSC32_IN
PC15-
OSC32_
OUT
OSC32_
OUT
(2)(4)
I2C2_SDA, FSMC_A0,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C3 10
C4 11
D4 12
E2 13
E3 14
PF0
PF1
PF2
PF3
PF4
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
-
-
-
-
-
-
-
-
-
-
I2C2_SCL, FSMC_A1,
EVENTOUT
I2C2_SMBA, FSMC_A2,
EVENTOUT
TIM5_CH1, FSMC_A3,
EVENTOUT
TIM5_CH2, FSMC_A4,
EVENTOUT
DocID028087 Rev 4
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67
Pinouts and pin description
STM32F412xE/G
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
TIM5_CH3, FSMC_A5,
EVENTOUT
-
-
-
-
-
E4 15
PF5
I/O
FT
-
-
-
-
-
-
-
-
10 F2 D2 16
11 G2 D3 17
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TRACED0, TIM10_CH1,
QUADSPI_BK1_IO3,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F3 18
F2 19
G3 20
PF6
PF7
PF8
I/O
I/O
I/O
I/O
FT
FT
FT
FT
-
-
-
-
-
-
-
-
TRACED1, TIM11_CH1,
QUADSPI_BK1_IO2,
EVENTOUT
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
-
-
-
-
-
-
G2 21
G1 22
PF9
TIM1_ETR, TIM5_CH4,
EVENTOUT
-
-
PF10
I/O
I/O
FT
FT
-
-
PH0 -
OSC_IN
(4)
5
5
D8 12 F1 D1 23
EVENTOUT
OSC_IN
PH1 -
OSC_OUT
(4)
6
7
-
6
7
8
E8 13 G1 E1 24
D7 14 H2 F1 25
D5 15 H1 H1 26
I/O
I/O
I/O
FT
RST
FT
EVENTOUT
-
OSC_OUT
NRST
NRST
PC0
-
-
ADC1_10,
WKUP2
EVENTOUT
ADC1_11,
WKUP3
-
-
9
F8 16 J2 H2 27
PC1
PC2
I/O
I/O
FT
FT
-
-
EVENTOUT
SPI2_MISO, I2S2ext_SD,
DFSDM1_CKOUT,
FSMC_NWE, EVENTOUT
10 E7 17 J3 H3 28
11 D6 18 K2 H4 29
ADC1_12
SPI2_MOSI/I2S2_SD,
FSMC_A0, EVENTOUT
-
-
PC3
VDD
I/O
S
FT
-
-
-
-
ADC1_13
-
-
19
-
-
-
-
30
31
-
-
-
-
-
-
-
-
-
-
VSSA/
VREF
8
-
12 G8 20
S
-
-
-
J1
J1
VSSA
S
50/193
DocID028087 Rev 4
STM32F412xE/G
Pinouts and pin description
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
-
-
-
-
K1 K1
-
-
VREF-
S
S
-
-
-
-
-
-
-
-
VDDA/
VREF+
9
13 F7
-
-
-
-
-
-
-
-
-
21 L1 L1 32
22 M1 M1 33
VREF+
VDDA
S
S
-
-
-
-
-
-
-
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
ADC1_0,
WKUP1
10 14 E6 23 L2 J2 34
PA0
PA1
PA2
I/O
I/O
FT
FT
-
-
EVENTOUT
TIM2_CH2, TIM5_CH2,
SPI4_MOSI/I2S4_SD,
USART2_RTS,
QUADSPI_BK1_IO3,
EVENTOUT
11 15 G7 24 M2 K2 35
ADC1_1
TIM2_CH3, TIM5_CH3,
TIM9_CH1, I2S2_CKIN,
USART2_TX, FSMC_D4,
EVENTOUT
12 16 H8 25 K3 L2 36
I/O
I/O
FT
FT
-
-
ADC1_2
ADC1_3
TIM2_CH4, TIM5_CH4,
TIM9_CH2, I2S2_MCK,
USART2_RX, FSMC_D5,
EVENTOUT
13 17 F6 26 L3 M2 37
PA3
-
-
-
18
-
-
-
27
-
-
G4 38
E3 H5
F4 39
VSS
S
I
-
FT
-
-
-
-
-
-
-
-
-
-
BYPASS_
REG
-
19 H7 28
-
VDD
S
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
DFSDM1_DATIN1,
FSMC_D6, EVENTOUT
14 20 G6 29 M3 J3 40
PA4
I/O
I/O
FT
FT
-
-
ADC1_4
ADC1_5
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
DFSDM1_CKIN1,
15 21 F5 30 K4 K3 41
PA5
FSMC_D7, EVENTOUT
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67
Pinouts and pin description
STM32F412xE/G
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
I2S2_MCK, TIM13_CH1,
QUADSPI_BK2_IO0,
16 22 H6 31 L4 L3 42
PA6
PA7
I/O
I/O
FT
FT
-
-
ADC1_6
ADC1_7
SDIO_CMD, EVENTOUT
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1,
17 23 E5 32 M4 M3 43
QUADSPI_BK2_IO1,
EVENTOUT
I2S1_MCK,
-
-
24 E4 33 K5 J4 44
PC4
PC5
I/O
I/O
FT
FT
-
-
QUADSPI_BK2_IO2,
FSMC_NE4, EVENTOUT
ADC1_14
ADC1_15
I2CFMP1_SMBA,
USART3_RX,
QUADSPI_BK2_IO3,
FSMC_NOE, EVENTOUT
25 G5 34 L5 K4 45
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
SPI5_SCK/I2S5_CK,
EVENTOUT
18 26 H5 35 M5 L4 46
PB0
I/O
FT
-
ADC1_8
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
SPI5_NSS/I2S5_WS,
DFSDM1_DATIN0,
QUADSPI_CLK,
EVENTOUT
19 27 F4 36 M6 M4 47
PB1
PB2
I/O
I/O
FT
FT
-
-
ADC1_9
BOOT1
DFSDM1_CKIN0,
QUADSPI_CLK,
EVENTOUT
20 28 G4 37 L6 J5 48
-
-
-
-
-
-
-
-
-
-
M5 49
L5 50
PF11
PF12
I/O
I/O
FT
FT
-
-
TIM8_ETR, EVENTOUT
-
-
TIM8_BKIN, FSMC_A6,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
51
VSS
VDD
S
S
-
-
-
-
-
-
-
-
G5 52
K5 53
I2CFMP1_SMBA,
FSMC_A7, EVENTOUT
-
-
-
-
-
PF13
I/O
FT
-
-
52/193
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STM32F412xE/G
Pinouts and pin description
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
I2CFMP1_SCL,
FSMC_A8, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M6 54
L6 55
K6 56
J6 57
PF14
PF15
PG0
PG1
I/O
I/O
I/O
I/O
FT
FT
FT
FT
-
-
-
-
-
-
-
-
I2CFMP1_SDA,
FSMC_A9, EVENTOUT
CAN1_RX, FSMC_A10,
EVENTOUT
CAN1_TX, FSMC_A11,
EVENTOUT
TIM1_ETR,
DFSDM1_DATIN2,
QUADSPI_BK2_IO0,
FSMC_D4/FSMC_DA4,
EVENTOUT
-
-
-
-
-
-
-
-
-
38 M7 M7 58
39 L7 L7 59
40 M8 K7 60
PE7
PE8
PE9
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
TIM1_CH1N,
DFSDM1_CKIN2,
QUADSPI_BK2_IO1,
FSMC_D5/FSMC_DA5,
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
QUADSPI_BK2_IO2,
FSMC_D6/FSMC_DA6,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
61
VSS
VDD
S
S
-
-
-
-
-
-
-
-
G6 62
TIM1_CH2N,
QUADSPI_BK2_IO3,
FSMC_D7/FSMC_DA7,
EVENTOUT
-
-
-
-
-
-
41 L8 J7 63
PE10
PE11
I/O
I/O
FT
FT
-
-
-
-
TIM1_CH2,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
FSMC_D8/FSMC_DA8,
EVENTOUT
42 M9 H8 64
TIM1_CH3N,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
FSMC_D9/FSMC_DA9,
EVENTOUT
-
-
-
43 L9 J8 65
PE12
I/O
FT
-
-
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67
Pinouts and pin description
STM32F412xE/G
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
TIM1_CH3, SPI4_MISO,
SPI5_MISO,
FSMC_D10/FSMC_DA10,
EVENTOUT
M1
0
-
-
-
44
K8 66
PE13
I/O
FT
-
-
TIM1_CH4,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
FSMC_D11/FSMC_DA11,
EVENTOUT
-
-
-
-
-
-
45 M11 L8 67
PE14
PE15
PB10
PB11
I/O
I/O
I/O
I/O
FT
FT
FT
FT
-
-
-
-
-
-
-
-
TIM1_BKIN,
FSMC_D12/FSMC_DA12,
EVENTOUT
M1
2
46
M8 68
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
I2S3_MCK, USART3_TX,
I2CFMP1_SCL, SDIO_D7,
EVENTOUT
21 29 H4 47 L10 M9 69
TIM2_CH4, I2C2_SDA,
I2S2_CKIN, USART3_RX,
EVENTOUT
M1
0
-
-
-
-
K9
70
22 30 H3 48 L11 H7 71
VCAP_1
VSS
S
S
-
-
-
-
-
-
-
-
23 31 H2 49 F12 H6
G1
-
24 32 H1 50
G7 72
VDD
S
-
-
-
-
2
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
SPI4_NSS/I2S4_WS,
SPI3_SCK/I2S3_CK,
USART3_CK, CAN2_RX,
DFSDM1_DATIN1,
25 33 G3 51 L12 M11 73
PB12
I/O
FT
-
-
FSMC_D13/FSMC_DA13,
EVENTOUT
TIM1_CH1N,
I2CFMP1_SMBA,
SPI2_SCK/I2S2_CK,
SPI4_SCK/I2S4_CK,
USART3_CTS, CAN2_TX,
DFSDM1_CKIN1,
EVENTOUT
M1
2
26 34 G2 52 K12
74
PB13
I/O
FT
-
-
54/193
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STM32F412xE/G
Pinouts and pin description
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
TIM1_CH2N,
TIM8_CH2N,
I2CFMP1_SDA,
SPI2_MISO, I2S2ext_SD,
USART3_RTS,
DFSDM1_DATIN2,
TIM12_CH1, FSMC_D0,
SDIO_D6, EVENTOUT
27 35 G1 53 K11 L11 75
PB14
PB15
I/O
I/O
FT
FT
-
-
-
-
RTC_50Hz, TIM1_CH3N,
TIM8_CH3N,
I2CFMP1_SCL,
28 36 F2 54 K10 L12 76
SPI2_MOSI/I2S2_SD,
DFSDM1_CKIN2,
TIM12_CH2, SDIO_CK,
EVENTOUT
USART3_TX, FSMC_D13/
FSMC_DA13, EVENTOUT
-
-
-
-
-
-
55
-
L9 77
PD8
PD9
I/O
I/O
FT
FT
-
-
-
-
USART3_RX,
FSMC_D14/FSMC_DA14,
EVENTOUT
56 K8 K9 78
57 J12 J9 79
USART3_CK,
FSMC_D15/FSMC_DA15,
EVENTOUT
-
-
-
-
-
-
PD10
PD11
I/O
I/O
FT
FT
-
-
-
-
I2CFMP1_SMBA,
USART3_CTS,
QUADSPI_BK1_IO0,
FSMC_A16, EVENTOUT
58 J11 H9 80
59 J10 L10 81
60 H12 K10 82
TIM4_CH1,
I2CFMP1_SCL,
USART3_RTS,
-
-
-
-
-
-
PD12
PD13
I/O
I/O
FT
FT
-
-
-
-
QUADSPI_BK1_IO1,
FSMC_A17, EVENTOUT
TIM4_CH2,
I2CFMP1_SDA,
QUADSPI_BK1_IO3,
FSMC_A18, EVENTOUT
-
-
-
-
-
-
-
-
-
-
G8 83
F8 84
VSS
VDD
S
S
-
-
-
-
-
-
-
-
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67
Pinouts and pin description
STM32F412xE/G
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
TIM4_CH3,
I2CFMP1_SCL,
FSMC_D0/FSMC_DA0,
EVENTOUT
-
-
-
-
-
-
61 H11 K11 85
PD14
PD15
I/O
I/O
FT
FT
-
-
-
-
TIM4_CH4,
I2CFMP1_SDA,
FSMC_D1/FSMC_DA1,
EVENTOUT
62 H10 K12 86
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J12 87
J11 88
J10 89
H12 90
PG2
PG3
PG4
PG5
I/O
I/O
I/O
I/O
FT
FT
FT
FT
-
-
-
-
FSMC_A12, EVENTOUT
FSMC_A13, EVENTOUT
FSMC_A14, EVENTOUT
FSMC_A15, EVENTOUT
-
-
-
-
QUADSPI_BK1_NCS,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H11 91
H10 92
G11 93
PG6
PG7
PG8
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
-
-
USART6_CK, EVENTOUT
USART6_RTS,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
94
-
VSS
VDD
S
S
S
-
-
-
-
F10
C11 95 VDDUSB
-
-
-
-
-
TIM3_CH1, TIM8_CH1,
I2CFMP1_SCL,
I2S2_MCK,
DFSDM1_CKIN3,
-
37 F1 63 E12 G12 96
PC6
I/O
FT
USART6_TX, FSMC_D1,
SDIO_D6, EVENTOUT
TIM3_CH2, TIM8_CH2,
I2CFMP1_SDA,
SPI2_SCK/I2S2_CK,
I2S3_MCK, USART6_RX,
DFSDM1_DATIN3,
-
-
38 E1 64 E11 F12 97
PC7
PC8
I/O
I/O
FT
FT
-
-
-
-
SDIO_D7, EVENTOUT
TIM3_CH3, TIM8_CH3,
USART6_CK,
QUADSPI_BK1_IO2,
SDIO_D0, EVENTOUT
39 F3 65 E10 F11 98
56/193
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STM32F412xE/G
Pinouts and pin description
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
MCO_2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S2_CKIN,
-
40 E2 66 D12 E11 99
PC9
I/O
FT
-
-
QUADSPI_BK1_IO0,
SDIO_D1, EVENTOUT
MCO_1, TIM1_CH1,
I2C3_SCL, USART1_CK,
USB_FS_SOF, SDIO_D1,
EVENTOUT
29 41 E3 67 D11 E12 100
30 42 D1 68 D10 D12 101
31 43 D2 69 C12 D11 102
PA8
PA9
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
TIM1_CH2, I2C3_SMBA,
USART1_TX,
USB_FS_VBUS,
SDIO_D2, EVENTOUT
TIM1_CH3,
SPI5_MOSI/I2S5_SD,
USART1_RX,
PA10
USB_FS_ID, EVENTOUT
TIM1_CH4, SPI4_MISO,
USART1_CTS,
32 44 D3 70 B12 C12 103
PA11
I/O
FT
-
USART6_TX, CAN1_RX,
USB_FS_DM,
-
EVENTOUT
TIM1_ETR, SPI5_MISO,
USART1_RTS,
USART6_RX, CAN1_TX,
USB_FS_DP, EVENTOUT
33 45 C1 71 A12 B12 104
34 46 C2 72 A11 A12 105
PA12
PA13
I/O
I/O
FT
FT
-
-
-
-
JTMS-SWDIO,
EVENTOUT
-
-
-
73 C11 G9 106 VCAP_2
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
35 47 B1 74 F11 G10 107
VSS
VDD
VDD
36 48
-
75 G11
-
-
-
-
A1
-
-
F9 108
JTCK-SWCLK,
EVENTOUT
37 49 B2 76 A10 A11 109
38 50 A2 77 A9 A10 110
PA14
I/O
FT
-
-
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART1_TX, EVENTOUT
PA15
I/O
FT
-
-
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67
Pinouts and pin description
STM32F412xE/G
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
SPI3_SCK/I2S3_CK,
USART3_TX,
QUADSPI_BK1_IO1,
SDIO_D2, EVENTOUT
-
-
51 C3 78 B11 B11 111
PC10
PC11
I/O
I/O
FT
FT
-
-
-
-
I2S3ext_SD, SPI3_MISO,
USART3_RX,
QUADSPI_BK2_NCS,
FSMC_D2, SDIO_D3,
EVENTOUT
52 B3 79 C10 B10 112
53 A3 80 B10 C10 113
SPI3_MOSI/I2S3_SD,
USART3_CK, FSMC_D3,
SDIO_CK, EVENTOUT
-
-
PC12
PD0
I/O
I/O
FT
FT
-
-
-
-
CAN1_RX,
FSMC_D2/FSMC_DA2,
EVENTOUT
-
-
-
-
81 C9 E10 114
82 B9 D10 115
CAN1_TX,
FSMC_D3/FSMC_DA3,
EVENTOUT
-
-
PD1
PD2
I/O
I/O
FT
FT
-
-
-
-
TIM3_ETR, FSMC_NWE,
SDIO_CMD, EVENTOUT
54 A4 83 C8 E9 116
TRACED1,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN0,
USART2_CTS,
-
-
-
84 B8 D9 117
PD3
I/O
FT
-
-
QUADSPI_CLK,
FSMC_CLK, EVENTOUT
DFSDM1_CKIN0,
USART2_RTS,
FSMC_NOE, EVENTOUT
-
-
-
-
-
-
85 B7 C9 118
86 A6 B9 119
PD4
PD5
I/O
I/O
FT
FT
-
-
-
-
USART2_TX,
FSMC_NWE, EVENTOUT
-
-
-
-
-
-
-
-
-
-
E7 120
F7 121
VSS
VDD
S
S
-
-
-
-
-
-
-
-
SPI3_MOSI/I2S3_SD,
DFSDM1_DATIN1,
USART2_RX,
-
-
-
87 B6 A8 122
PD6
I/O
FT
-
-
FSMC_NWAIT,
EVENTOUT
58/193
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STM32F412xE/G
Pinouts and pin description
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
DFSDM1_CKIN1,
USART2_CK,
FSMC_NE1, EVENTOUT
-
-
-
-
-
88 A5 A9 123
PD7
PG9
I/O
I/O
FT
FT
-
-
-
-
USART6_RX,
QUADSPI_BK2_IO2,
FSMC_NE2, EVENTOUT
-
-
-
E8 124
-
-
-
-
-
-
-
-
-
-
D8 125
C8 126
PG10
PG11
I/O
I/O
FT
FT
-
-
FSMC_NE3, EVENTOUT
CAN2_RX, EVENTOUT
-
-
USART6_RTS, CAN2_TX,
FSMC_NE4, EVENTOUT
-
-
-
-
-
-
-
-
-
-
B8 127
D7 128
PG12
PG13
I/O
I/O
FT
FT
-
-
-
-
TRACED2,
USART6_CTS,
FSMC_A24, EVENTOUT
TRACED3, USART6_TX,
QUADSPI_BK2_IO3,
-
-
-
-
-
C7 129
PG14
I/O
FT
-
-
FSMC_A25, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
130
VSS
VDD
S
S
-
-
-
-
-
-
-
-
F6 131
B7 132
USART6_CTS,
EVENTOUT
-
-
-
-
-
PG15
I/O
FT
-
-
JTDO-SWO, TIM2_CH2,
I2CFMP1_SDA,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
USART1_RX, I2C2_SDA,
EVENTOUT
39 55 A5 89 A8 A7 133
PB3
I/O
FT
-
-
JTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
I2S3ext_SD, I2C3_SDA,
SDIO_D0, EVENTOUT
40 56 B4 90 A7 A6 134
PB4
PB5
I/O
I/O
FT
FT
-
-
-
-
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
CAN2_RX, SDIO_D3,
EVENTOUT
41 57 C4 91 C5 B6 135
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67
Pinouts and pin description
STM32F412xE/G
Table 9. STM32F412xE/G pin definition (continued)
Pin Number
Pin name
(function Pin
I/O
Additional
functions
Notes
Alternate functions
after
type structure
reset)(1)
TIM4_CH1, I2C1_SCL,
USART1_TX, CAN2_TX,
QUADSPI_BK1_NCS,
SDIO_D0, EVENTOUT
42 58 B5 92 B5 C6 136
43 59 A6 93 B4 D6 137
PB6
PB7
I/O
FT
-
-
TIM4_CH2, I2C1_SDA,
USART1_RX, FSMC_NL,
EVENTOUT
I/O
I
FT
B
-
-
-
44 60 D4 94 A4 D5 138 BOOT0
-
VPP
TIM4_CH3, TIM10_CH1,
I2C1_SCL,
45 61 C5 95 A3 C5 139
PB8
I/O
FT
-
SPI5_MOSI/I2S5_SD,
CAN1_RX, I2C3_SDA,
SDIO_D4, EVENTOUT
-
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
46 62 B6 96 B3 B5 140
PB9
PE0
I/O
I/O
FT
FT
-
-
SPI2_NSS/I2S2_WS,
CAN1_TX, I2C2_SDA,
SDIO_D5, EVENTOUT
-
-
TIM4_ETR, FSMC_NBL0,
EVENTOUT
-
-
-
-
-
-
97 C3 A5 141
98 A2 A4 142
PE1
VSS
I/O
S
FT
-
-
-
-
FSMC_NBL1, EVENTOUT
-
-
-
47 63 A7 99
-
E6
-
-
-
-
-
C6
-
H3 E5 143 PDR_ON
F5 144 VDD
I
FT
10
0
48 64 A8
-
S
-
-
-
-
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F412xE/Greference manual.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
60/193
DocID028087 Rev 4
Table 10. STM32F412xE/G alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
I2C2/I2C3/
I2CFMP1/
USART3/ CAN1/CAN2
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
SPI1/I2S1/ SPI2/I2S2/SPI3
SPI2/I2S2/ /I2S3/SPI4/
SPI3/I2S3/ I2S4/SPI5/I2S5
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
DFSDM1/
QUADSPI/
FSMC
Port
TIM3/
TIM4/
TIM5
TIM1/
TIM2
SYS_AF
FSMC /SDIO SYS_AF
USART6/
CAN1
/TIM12/
TIM13/TIM14
/QUADSPI
I2CFMP1
SPI4/I2S4
/DFSDM1
/OTG1_FS
TIM2_CH1/
TIM2_ETR
PA0
-
-
TIM5_CH1
TIM5_CH2
TIM8_ETR
-
-
-
-
-
-
USART2_CTS
USART2_RTS
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
SPI4_MOSI/I
2S4_SD
QUADSPI_
BK1_IO3
PA1
TIM2_CH2
PA2
PA3
-
-
TIM2_CH3
TIM2_CH4
TIM5_CH3
TIM5_CH4
TIM9_CH1
TIM9_CH2
-
-
I2S2_CKIN
I2S2_MCK
-
-
USART2_TX
USART2_RX
-
-
-
-
-
-
FSMC_D4
FSMC_D5
EVENTOUT
EVENTOUT
SPI1_NSS/I2
S1_WS
SPI3_NSS/
I2S3_WS
DFSDM1_
DATIN1
PA4
PA5
-
-
-
-
-
USART2_CK
-
-
-
-
FSMC_D6
FSMC_D7
EVENTOUT
EVENTOUT
TIM2_CH1/
TIM2_ETR
SPI1_SCK/
I2S1_CK
DFSDM1_
CKIN1
-
-
TIM8_CH1N
-
-
-
TIM13_
CH1
QUADSPI_
BK2_IO0
PA6
-
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
-
TIM3_CH1
TIM8_BKIN
-
SPI1_MISO
I2S2_MCK
-
-
-
-
-
-
SDIO_CMD EVENTOUT
SPI1_MOSI/I
2S1_SD
TIM14_
CH1
QUADSPI_
BK2_IO1
PA7
-
TIM3_CH2
TIM8_CH1N
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
USB_FS_
SOF
PA8
MCO_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_SCL
-
-
-
-
-
-
-
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
USART1_RTS
-
-
SDIO_D1
I2C3_
SMBA
USB_FS_
VBUS
PA9
-
-
-
-
-
SDIO_D2
SPI5_MOSI/
I2S5_SD
PA10
PA11
PA12
PA13
PA14
PA15
-
-
-
-
-
-
-
USB_FS_ID
-
-
-
-
-
-
USART6_
TX
SPI4_MISO
CAN1_RX
USB_FS_DM
USART6_
RX
SPI5_MISO
CAN1_TX
USB_FS_DP
JTMS-
SWDIO
-
-
-
-
-
-
-
-
-
-
-
JTCK-
SWCLK
-
-
TIM2_CH1/
TIM2_ETR
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
JTDI
USART1_TX
Table 10. STM32F412xE/G alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
I2C2/I2C3/
I2CFMP1/
USART3/ CAN1/CAN2
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
SPI1/I2S1/ SPI2/I2S2/SPI3
SPI2/I2S2/ /I2S3/SPI4/
SPI3/I2S3/ I2S4/SPI5/I2S5
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
DFSDM1/
QUADSPI/
FSMC
Port
TIM3/
TIM4/
TIM5
TIM1/
TIM2
SYS_AF
FSMC /SDIO SYS_AF
USART6/
CAN1
/TIM12/
TIM13/TIM14
/QUADSPI
I2CFMP1
SPI4/I2S4
/DFSDM1
/OTG1_FS
SPI5_SCK/
I2S5_CK
PB0
-
-
-
TIM1_CH2N
TIM3_CH3
TIM3_CH4
-
TIM8_CH2N
TIM8_CH3N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
SPI5_NSS/
I2S5_WS
DFSDM1_
DATIN0
QUADSPI_
CLK
PB1
PB2
PB3
PB4
PB5
TIM1_CH3N
-
-
DFSDM1_
CKIN0
QUADSPI_
CLK
-
-
-
-
-
-
-
JTDO-
SWO
I2CFMP1_
SDA
SPI1_SCK/I2
S1_CK
SPI3_SCK/
I2S3_CK
TIM2_CH2
USART1_RX
I2C2_SDA
I2C3_SDA
CAN2_RX
-
I2S3ext_
SD
JTRST
-
-
-
TIM3_CH1
TIM3_CH2
-
-
-
SPI1_MISO
SPI3_MISO
SDIO_D0
SDIO_D3
SPI1_MOSI/I
2S1_SD
SPI3_MOSI/
I2S3_SD
I2C1_SMBA
-
QUADSPI_
BK1_NCS
PB6
-
-
TIM4_CH1
-
I2C1_SCL
-
-
-
USART1_TX
-
CAN2_TX
SDIO_D0
EVENTOUT
PB7
PB8
-
-
-
-
TIM4_CH2
TIM4_CH3
-
I2C1_SDA
I2C1_SCL
-
-
USART1_RX
-
-
-
-
-
FSMC_NL
SDIO_D4
EVENTOUT
EVENTOUT
SPI5_MOSI/I2S
5_SD
TIM10_CH1
CAN1_RX
I2C3_SDA
SPI2_NSS/
I2S2_WS
PB9
-
-
TIM4_CH4
TIM11_CH1
I2C1_SDA
-
-
CAN1_TX
I2C2_SDA
-
SDIO_D5
EVENTOUT
SPI2_SCK/
I2S2_CK
I2CFMP1_
SCL
PB10
PB11
-
-
TIM2_CH3
TIM2_CH4
-
-
-
-
I2C2_SCL
I2C2_SDA
I2S3_MCK
-
USART3_TX
USART3_RX
-
-
-
-
SDIO_D7
-
EVENTOUT
EVENTOUT
I2S2_CKIN
-
SPI2_NSS/
I2S2_WS
SPI4_NSS/
I2S4_WS
SPI3_SCK/
I2S3_CK
USART3_
CK
DFSDM1_
DATIN1
FSMC_D13/F
SMC_DA13
PB12
-
TIM1_BKIN
-
-
I2C2_SMBA
CAN2_RX
EVENTOUT
I2CFMP1_
SMBA
SPI2_SCK/
I2S2_CK
SPI4_SCK/
I2S4_CK
USART3_
CTS
DFSDM1_
CKIN1
PB13
PB14
PB15
-
-
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
-
-
-
-
-
CAN2_TX
TIM12_CH1
TIM12_CH2
-
EVENTOUT
EVENTOUT
EVENTOUT
I2CFMP1_
SDA
USART3_
RTS
DFSDM1_
DATIN2
TIM8_CH2N
TIM8_CH3N
SPI2_MISO
I2S2ext_SD
-
FSMC_D0
-
SDIO_D6
SDIO_CK
RTC_
50Hz
I2CFMP1_
SCL
SPI2_MOSI/I
2S2_SD
DFSDM1_
CKIN2
-
Table 10. STM32F412xE/G alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
I2C2/I2C3/
I2CFMP1/
USART3/ CAN1/CAN2
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
SPI1/I2S1/ SPI2/I2S2/SPI3
SPI2/I2S2/ /I2S3/SPI4/
SPI3/I2S3/ I2S4/SPI5/I2S5
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
DFSDM1/
QUADSPI/
FSMC
Port
TIM3/
TIM4/
TIM5
TIM1/
TIM2
SYS_AF
FSMC /SDIO SYS_AF
USART6/
CAN1
/TIM12/
TIM13/TIM14
/QUADSPI
I2CFMP1
SPI4/I2S4
/DFSDM1
/OTG1_FS
PC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
PC1
PC2
DFSDM1_
CKOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_MISO
I2S2ext_SD
-
-
-
-
-
-
-
-
-
FSMC_NWE EVENTOUT
SPI2_MOSI/I
2S2_SD
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
-
-
-
-
-
-
-
-
-
-
FSMC_A0
EVENTOUT
QUADSPI_
BK2_IO2
-
-
-
I2S1_MCK
-
-
FSMC_NE4 EVENTOUT
FSMC_NOE EVENTOUT
I2CFMP1_
SMBA
QUADSPI_
BK2_IO3
-
-
-
USART3_RX
I2CFMP1_
SCL
DFSDM1_
CKIN3
USART6_
TX
-
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
-
TIM8_CH1
TIM8_CH2
TIM8_CH3
TIM8_CH4
-
I2S2_MCK
-
FSMC_D1
SDIO_D6
SDIO_D7
SDIO_D0
SDIO_D1
SDIO_D2
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
I2CFMP1_
SDA
SPI2_SCK/
I2S2_CK
USART6_
RX
DFSDM1_
DATIN3
-
I2S3_MCK
-
USART6_
CK
QUADSPI_
BK1_IO2
-
-
-
-
-
-
-
-
-
QUADSPI_
BK1_IO0
MCO_2
-
I2C3_SDA
-
I2S2_CKIN
-
-
-
-
SPI3_SCK/
I2S3_CK
QUADSPI_
BK1_IO1
USART3_TX
QUADSPI_
BK2_NCS
PC11
PC12
-
-
-
-
-
-
-
-
-
-
I2S3ext_SD
-
SPI3_MISO
USART3_RX
USART3_CK
-
-
FSMC_D2
FSMC_D3
SDIO_D3
SDIO_CK
EVENTOUT
EVENTOUT
SPI3_MOSI/
I2S3_SD
-
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
Table 10. STM32F412xE/G alternate functions (continued)
AF0
SYS_AF
-
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
I2C2/I2C3/
I2CFMP1/
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
SPI1/I2S1/ SPI2/I2S2/SPI3
SPI2/I2S2/ /I2S3/SPI4/
SPI3/I2S3/ I2S4/SPI5/I2S5
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
USART3/ CAN1/CAN2
USART6/
CAN1
DFSDM1/
QUADSPI/
FSMC
Port
TIM3/
TIM4/
TIM5
TIM1/
TIM2
FSMC /SDIO SYS_AF
/TIM12/
TIM13/TIM14
/QUADSPI
I2CFMP1
SPI4/I2S4
/DFSDM1
/OTG1_FS
FSMC_D2/FS
EVENTOUT
MC_DA2
PD0
-
-
-
-
-
-
-
-
CAN1_RX
-
FSMC_D3/FS
EVENTOUT
MC_DA3
PD1
PD2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN1_TX
-
-
TIM3_ETR
-
FSMC_NWE
-
SDIO_CMD EVENTOUT
FSMC_CLK EVENTOUT
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN0
USART2_
CTS
QUADSPI_
CLK
PD3 TRACED1
DFSDM1_
CKIN0
USART2_
RTS
PD4
PD5
PD6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_NOE EVENTOUT
FSMC_NWE EVENTOUT
-
USART2_TX
USART2_RX
SPI3_MOSI/I
2S3_SD
DFSDM1_
DATIN1
FSMC_
EVENTOUT
NWAIT
DFSDM1_
CKIN1
PD7
PD8
-
-
-
-
-
-
-
-
-
-
-
-
USART2_CK
USART3_TX
-
-
-
-
-
-
FSMC_NE1 EVENTOUT
FSMC_D13/
EVENTOUT
FSMC_DA13
-
-
FSMC_D14/
EVENTOUT
FSMC_DA14
PD9
-
-
-
-
-
-
-
-
-
-
-
USART3_RX
USART3_CK
-
-
-
-
-
-
FSMC_D15/
EVENTOUT
FSMC_DA15
PD10
-
-
-
-
I2CFMP1_
SMBA
USART3_
CTS
QUADSPI_
BK1_IO0
PD11
PD12
PD13
PD14
PD15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A16
FSMC_A17
FSMC_A18
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
I2CFMP1_
SCL
USART3_
RTS
QUADSPI_
BK1_IO1
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
I2CFMP1_
SDA
QUADSPI_
BK1_IO3
-
-
-
-
-
-
-
-
-
I2CFMP1_
SCL
FSMC_D0/
FSMC_DA0
-
-
I2CFMP1_
SDA
FSMC_D1/
FSMC_DA1
Table 10. STM32F412xE/G alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
I2C2/I2C3/
I2CFMP1/
USART3/ CAN1/CAN2
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
SPI1/I2S1/ SPI2/I2S2/SPI3
SPI2/I2S2/ /I2S3/SPI4/
SPI3/I2S3/ I2S4/SPI5/I2S5
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
DFSDM1/
QUADSPI/
FSMC
Port
TIM3/
TIM4/
TIM5
TIM1/
TIM2
SYS_AF
FSMC /SDIO SYS_AF
USART6/
CAN1
/TIM12/
TIM13/TIM14
/QUADSPI
I2CFMP1
SPI4/I2S4
/DFSDM1
/OTG1_FS
PE0
-
-
-
-
TIM4_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_NBL0 EVENTOUT
FSMC_NBL1 EVENTOUT
PE1
PE2
TRACECL
K
SPI4_SCK/
I2S4_CK
SPI5_SCK/
I2S5_CK
QUADSPI_
BK1_IO2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A23
FSMC_A19
FSMC_A20
EVENTOUT
EVENTOUT
EVENTOUT
PE3 TRACED0
PE4 TRACED1
-
-
-
-
SPI4_NSS/
I2S4_WS
SPI5_NSS/
I2S5_WS
DFSDM1_
DATIN3
DFSDM1_
CKIN3
PE5 TRACED2
PE6 TRACED3
-
-
-
-
-
-
-
-
-
TIM9_CH1
-
-
-
-
-
-
-
-
SPI4_MISO
SPI5_MISO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A21
FSMC_A22
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
SPI4_MOSI/I
2S4_SD
SPI5_MOSI/
I2S5_SD
-
TIM9_CH2
-
-
-
-
-
-
-
DFSDM1_
DATIN2
QUADSPI_
BK2_IO0
FSMC_D4/
FSMC_DA4
PE7
PE8
-
-
-
-
-
-
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
-
-
-
-
-
-
-
-
-
-
DFSDM1_
CKIN2
QUADSPI_
BK2_IO1
FSMC_D5/
FSMC_DA5
DFSDM1_
CKOUT
QUADSPI_
BK2_IO2
FSMC_D6/
FSMC_DA6
PE9
QUADSPI_
BK2_IO3
FSMC_D7/
FSMC_DA7
PE10
PE11
PE12
-
SPI4_NSS/
I2S4_WS
SPI5_NSS/
I2S5_WS
FSMC_D8/
FSMC_DA8
SPI4_SCK/
I2S4_CK
SPI5_SCK/
I2S5_CK
FSMC_D9/
FSMC_DA9
-
-
FSMC_D10/
FSMC_DA10
PE13
PE14
PE15
-
-
-
TIM1_CH3
TIM1_CH4
TIM1_BKIN
-
-
-
-
-
-
-
-
-
SPI4_MISO
SPI5_MISO
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
SPI4_MOSI/I
2S4_SD
SPI5_MOSI/
I2S5_SD
FSMC_D11/
FSMC_DA11
-
-
FSMC_D12/
FSMC_DA12
-
-
Table 10. STM32F412xE/G alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
I2C2/I2C3/
I2CFMP1/
USART3/ CAN1/CAN2
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
SPI1/I2S1/ SPI2/I2S2/SPI3
SPI2/I2S2/ /I2S3/SPI4/
SPI3/I2S3/ I2S4/SPI5/I2S5
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
DFSDM1/
QUADSPI/
FSMC
Port
TIM3/
TIM4/
TIM5
TIM1/
TIM2
SYS_AF
FSMC /SDIO SYS_AF
USART6/
CAN1
/TIM12/
TIM13/TIM14
/QUADSPI
I2CFMP1
SPI4/I2S4
/DFSDM1
/OTG1_FS
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A0
FSMC_A1
FSMC_A2
FSMC_A3
FSMC_A4
FSMC_A5
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PF1
PF2
PF3
PF4
PF5
-
I2C2_SCL
-
I2C2_SMBA
TIM5_CH1
TIM5_CH2
TIM5_CH3
-
-
-
QUADSPI_
BK1_IO3
PF6 TRACED0
PF7 TRACED1
-
-
-
-
-
-
-
-
TIM10_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
QUADSPI_
BK1_IO2
TIM11_CH1
QUADSPI_
BK1_IO0
PF8
PF9
-
-
-
-
TIM13_CH1
TIM14_CH1
QUADSPI_
BK1_IO1
PF10
PF11
PF12
-
-
-
TIM1_ETR
TIM5_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
-
-
-
-
TIM8_ETR
TIM8_BKIN
-
FSMC_A6
I2CFMP1_
SMBA
PF13
PF14
PF15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A7
FSMC_A8
FSMC_A9
EVENTOUT
EVENTOUT
EVENTOUT
I2CFMP1_
SCL
I2CFMP1_
SDA
Table 10. STM32F412xE/G alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
I2C2/I2C3/
I2CFMP1/
USART3/ CAN1/CAN2
TIM8/
TIM9/
TIM10/
TIM11
I2C1/
I2C2/
I2C3/
SPI1/I2S1/ SPI2/I2S2/SPI3
SPI2/I2S2/ /I2S3/SPI4/
SPI3/I2S3/ I2S4/SPI5/I2S5
SPI3/I2S3/
USART1/
USART2/
USART3
DFSDM1/
DFSDM1/
QUADSPI/
FSMC
Port
TIM3/
TIM4/
TIM5
TIM1/
TIM2
SYS_AF
FSMC /SDIO SYS_AF
USART6/
CAN1
/TIM12/
TIM13/TIM14
/QUADSPI
I2CFMP1
SPI4/I2S4
/DFSDM1
/OTG1_FS
PG0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN1_RX
-
-
-
-
-
-
FSMC_A10
FSMC_A11
FSMC_A12
FSMC_A13
FSMC_A14
FSMC_A15
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
PG1
PG2
PG3
PG4
PG5
CAN1_TX
-
-
-
-
QUADSPI_
BK1_NCS
PG6
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
USART6_
CK
PG7
PG8
PG9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
USART6_
RTS
USART6_
RX
QUADSPI_
BK2_IO2
FSMC_NE2 EVENTOUT
FSMC_NE3 EVENTOUT
PG10
PG11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN2_RX
-
EVENTOUT
USART6_
RTS
PG12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN2_TX
-
-
-
-
-
FSMC_NE4 EVENTOUT
USART6_
CTS
PG13 TRACED2
PG14 TRACED3
FSMC_A24
FSMC_A25
-
EVENTOUT
EVENTOUT
EVENTOUT
USART6_
TX
QUADSPI_
BK2_IO3
USART6_
CTS
PG15
-
-
PH0
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
Memory mapping
STM32F412xE/G
5
Memory mapping
The memory map is shown in Figure 18.
Figure 18. Memory map
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68/193
DocID028087 Rev 4
STM32F412xE/G
Memory mapping
Table 11. STM32F412xE/G register boundary addresses
Bus
Boundary address
Peripheral
0xE010 0000 - 0xFFFF FFFF
0xE000 0000 - 0xE00F FFFF
0xA000 2000 - 0xDFFF FFFF
0xA000 1000 - 0xA000 1FFF
0xA000 0000 - 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
0x7000 0000 - 0x08FFF FFFF
0x6000 0000 - 0x6FFF FFFF
0x5006 0C00 - 0x5FFF FFFF
0x5006 0800 0x5006 0BFF
0x5004 000- 0x5006 07FF
0x5000 0000 - 0x5003 FFFF
0x4002 6800 - 0x4FFF FFFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
0x4002 5000 - 0x4002 4FFF
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
0x4002 3400 - 0x4002 37FF
0x4002 3000 - 0x4002 33FF
0x4002 2000 - 0x4002 2FFF
0x4002 1C00 - 0x4002 1FFF
0x4002 1800 - 0x4002 1BFF
0x4002 1400 - 0x4002 17FF
0x4002 1000 - 0x4002 13FF
0x4002 0C00 - 0x4002 0FFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
Reserved
®
Cortex -M4
Cortex-M4 internal peripherals
Reserved
QuadSPI control register
FSMC control register
QUADSPI
Reserved
FSMC
AHB3
AHB2
Reserved
RNG
Reserved
USB OTG FS
Reserved
DMA2
DMA1
Reserved
Flash interface register
RCC
Reserved
CRC
AHB1
Reserved
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
DocID028087 Rev 4
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71
Memory mapping
STM32F412xE/G
Table 11. STM32F412xE/G register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4001 6400- 0x4001 FFFF
0x4001 6000 - 0x4001 63FF
0x4001 5400 - 0x4001 5FFF
0x4001 5000 - 0x4001 53FF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2400 - 0x4001 2BFF
0x4001 2000 - 0x4001 23FF
0x4001 1800 - 0x4001 1FFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0800 - 0x4001 0FFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 7400 - 0x4000 FFFF
Reserved
DFSDM1
Reserved
SPI5/I2S5
TIM11
TIM10
TIM9
EXTI
SYSCFG
SPI4/I2S4
SPI1/I2S1
SDIO
APB2
Reserved
ADC1
Reserved
USART6
USART1
Reserved
TIM8
TIM1
Reserved
70/193
DocID028087 Rev 4
STM32F412xE/G
Memory mapping
Table 11. STM32F412xE/G register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800- 0x4000 6BFF
0x4000 6400- 0x4000 67FF
0x4000 6000- 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 4C00 - 0x4000 53FF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
PWR
Reserved
CAN2
CAN1
I2CFMP1
I2C3
I2C2
I2C1
Reserved
USART3
USART2
I2S3ext
SPI3 / I2S3
SPI2 / I2S2
I2S2ext
IWDG
APB1
WWDG
RTC & BKP Registers
Reserved
TIM14
TIM13
TIM12
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
DocID028087 Rev 4
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71
Electrical characteristics
STM32F412xE/G
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
1.7 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2 σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 19.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 20.
Figure 19. Pin loading conditions
Figure 20. Input voltage measurement
-#5 PIN
-#5 PIN
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72/193
DocID028087 Rev 4
STM32F412xE/G
Electrical characteristics
6.1.6
Power supply scheme
Figure 21. Power supply scheme
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1. To connect PDR_ON pin, refer to Section: Power supply supervisor.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VCAP_2 pad is only available on 100-pin and 144-pin packages.
4. VDDA=VDD and VSSA=VSS
.
5. VDDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and
associated DP/DM GPIOs. VDDUSB value does not depend on the VDD and VDDA values, but it must be the
last supply to be provided and the first to disappear.
Caution:
Each power supply pair (for example V /V , V
/V
) must be decoupled with filtering
DD SS
DDA SSA
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure good operation of
the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
DocID028087 Rev 4
73/193
161
Electrical characteristics
STM32F412xE/G
6.1.7
Current consumption measurement
Figure 22. Current consumption measurement scheme
,
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6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics,
Table 13: Current characteristics, and Table 14: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 12. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDDA, VDD
,
VDD–VSS
–0.3
4.0
(1)
VDDUSB and VBAT
)
Input voltage on FT and TC pins(2)
VSS–0.3 VDD+4.0
V
VIN
Input voltage on any other pin
V
SS–0.3
4.0
9.0
50
Input voltage for BOOT0
VSS
|ΔVDDx
|
Variations between different VDD power pins
Variations between all the different ground pins
-
-
mV
|VSSX −VSS
|
50
see Section 6.3.14:
Absolute maximum
ratings (electrical
sensitivity)
VESD(HBM)
Electrostatic discharge voltage (human body model)
1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 13 for the values of the maximum allowed
injected current.
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Symbol
Electrical characteristics
Table 13. Current characteristics
Ratings
Max.
Unit
ΣIVDD
Σ IVSS
Σ IVDDUSB
IVDD
Total current into sum of all VDD_x power lines (source)(1)
Total current out of sum of all VSS_x ground lines (sink)(1)
Total current into VDDUSB power lines (source)
160
-160
25
Maximum current into each VDD_x power line (source)(1)
Maximum current out of each VSS_x ground line (sink)(1)
Output current sunk by any I/O and control pin
100
-100
25
IVSS
IIO
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/O and control pins (2)
Total output current sunk by sum of all USB I/Os
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT and TC pins (4)
-25
mA
120
25
ΣIIO
-120
(3)
–5/+0
±25
IINJ(PIN)
Injected current on NRST and B pins (4)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply,
in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 14. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
125
Maximum junction temperature
°C
Maximum lead temperature during soldering
(WLCSP64, LQFP64/100/144, UFQFPN48,
UFBGA100/144)
TLEAD
see note (1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS
directive 2011/65/EU, July 2011).
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6.3
Operating conditions
6.3.1
General operating conditions
Table 15. General operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Power Scale3: Regulator ON,
0
-
64
VOS[1:0] bits in PWR_CR register = 0x01
Power Scale2: Regulator ON,
fHCLK
Internal AHB clock frequency
0
0
0
-
-
-
84
100
50
MHz
VOS[1:0] bits in PWR_CR register = 0x10
Power Scale1: Regulator ON,
VOS[1:0] bits in PWR_CR register = 0x11
Internal APB1 clock
frequency
fPCLK1
-
MHz
Internal APB2 clock
frequency
fPCLK2
VDD
-
-
0
-
-
100
3.6
MHz
V
Standard operating voltage
1.7(1)
Analog operating voltage
1.7(1)
-
-
2.4
3.6
(ADC limited to 1.2 M
samples)
(2)(3)
(4)
VDDA
Must be the same potential as VDD
V
Analog operating voltage
2.4
(ADC limited to 2.4 M
samples)
USB supply voltage
VDDUSB (supply voltage for PA11 and
PA12 pins)
USB not used
1.7
3.0
3.3
3.6
3.6
3.6
V
V
USB used(5)
-
-
VBAT
Backup operating voltage
-
1.65
VOS[1:0] bits in PWR_CR register = 0x01
Max frequency 64 MHz
1.08(6) 1.14 1.20(6)
1.20(6) 1.26 1.32(6)
1.26 1.32 1.38
Regulator ON: 1.2 V
VOS[1:0] bits in PWR_CR register = 0x10
Max frequency 84 MHz
V12
V
internal voltage on
VCAP_1/VCAP_2 pins
VOS[1:0] bits in PWR_CR register = 0x11
Max frequency 100 MHz
Max frequency 64 MHz
Max frequency 84 MHz
Max frequency 100 MHz
2 V ≤ VDD ≤ 3.6 V
VDD ≤ 2 V
1.10 1.14 1.20
1.20 1.26 1.32
1.26 1.32 1.38
Regulator OFF: 1.2 V
external voltage must be
supplied on
V12
V
V
VCAP_1/VCAP_2 pins
–0.3
–0.3
0
-
-
-
5.5
5.2
9
Input voltage on RST, FT and
TC pins(7)
VIN
Input voltage on BOOT0 pin
-
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Symbol
Electrical characteristics
Table 15. General operating conditions (continued)
Parameter
Conditions
Min
Typ
Max Unit
UFQFPN48
WLCSP64
LQFP64
-
-
-
-
-
-
-
-
625
392
425
Power dissipation at
PD
TA = 85°C for range 6 or
LQFP100
LQFP144
UFBGA100
UFBGA144
465
571
351
416
85
mW
TA = 105°C for range 7(8)
-
-
-
-
-
-
-
-
-
-
Maximum power dissipation
Low power dissipation(9)
Maximum power dissipation
Low power dissipation(9)
Range 6
–40
–40
–40
–40
–40
–40
Ambient temperature for
range 6
105
105
125
105
125
TA
TJ
Ambient temperature for
range 7
°C
Junction temperature range
Range 7
1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.18.2: Internal
reset OFF).
2. When the ADC is used, refer to Table 71: ADC characteristics.
3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
5. Only the DM (PA11) and DP (PA12) pads are supplied through VDDUSB. For application where the VBUS (PA9) is directly
connected to the chip, a minimum VDD supply of 2.7V is required.
(some application examples are shown in appendix B)
6. Guaranteed by test in production
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax
.
9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
.
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Table 16. Features depending on the operating power supply range
Maximum
Flash
Operating
power
supply
range
memory
access
frequency
Maximum Flash
memory access
frequency with
Possible
Flash
memory
operations
Clock output
frequency on
I/O pins(3)
ADC
operation
I/O operation
with no wait wait states (1)(2)
states
(fFlashmax
)
8-bit erase
and program
operations
only
Conversion
time up to
1.2 Msps
VDD =1.7 to
2.1 V(4)
100 MHz with 6 – No I/O
wait states compensation
16 MHz(5)
up to 30 MHz
up to 30 MHz
Conversion
time up to
1.2 Msps
16-bit erase
and program
operations
VDD = 2.1 to
2.4 V
100 MHz with 5 – No I/O
18 MHz
24 MHz
wait states
compensation
Conversion
time up to
2.4 Msps
– I/O
16-bit erase
and program
operations
VDD = 2.4 to
2.7 V
100 MHz with 4
wait states
compensation up to 50 MHz
works
– up to
100 MHz
when VDD
3.0 to 3.6 V
=
Conversion
time up to
2.4 Msps
– I/O
compensation
works
32-bit erase
and program
operations
VDD = 2.7 to
3.6 V(6)
100 MHz with 3
wait states
30 MHz
– up to
50 MHz
when VDD
=
2.7 to 3.0 V
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. Refer to Table 58: I/O AC characteristics for frequencies vs. external load.
4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.18.2: Internal
reset OFF).
5. Prefetch available over the complete VDD supply range.
6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of
D- and D+ pins will be degraded between 2.7 and 3 V.
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6.3.2
VCAP_1/VCAP_2 external capacitors
Stabilization for the main regulator is achieved by connecting the external capacitor C
to
EXT
the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT
capacitors are replaced by a single capacitor.
C
is specified in Table 17.
EXT
Figure 23. External capacitor C
EXT
&
(65
5ꢉ/HDN
06ꢈꢊꢃꢇꢇ9ꢄ
1. Legend: ESR is the equivalent series resistance.
(1)
Table 17. VCAP_1/VCAP_2 operating conditions
Parameter
Symbol
Conditions
Capacitance of external capacitor with the pins
VCAP_1 and VCAP_2 available
CEXT
2.2 µF
< 2 Ω
4.7 µF
< 1 Ω
ESR of external capacitor with the pins VCAP_1 and
VCAP_2 available
ESR
CEXT
ESR
Capacitance of external capacitor with a single VCAP
pin available
ESR of external capacitor with a single VCAP pin
available
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
6.3.3
Operating conditions at power-up/power-down (regulator ON)
Subject to general operating conditions for T .
A
Table 18. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
VDD fall time rate
Min
Max
Unit
20
20
∞
∞
tVDD
µs/V
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6.3.4
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T .
A
(1)
Table 19. Operating conditions at power-up / power-down (regulator OFF)
Symbol
Parameter
VDD rise time rate
DD fall time rate
Conditions
Power-up
Power-down
Min
Max
Unit
20
20
20
20
∞
∞
∞
∞
tVDD
V
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up
VCAP_1 and VCAP_2 fall time rate Power-down
tVCAP
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
Note:
This feature is only available for UFBGA100 and UFBGA144 packages.
6.3.5
Embedded reset and power control block characteristics
The parameters given in Table 20 are derived from tests performed under ambient
temperature and V supply voltage @ 3.3V.
DD
Table 20. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
-
2.09
1.98
2.23
2.13
2.39
2.29
2.54
2.44
2.70
2.59
2.86
2.65
2.96
2.85
3.07
2.95
-
2.14 2.19
2.04 2.08
2.30 2.37
2.19 2.25
2.45 2.51
2.35 2.39
2.60 2.65
2.51 2.56
V
2.76 2.82
Programmable voltage
detector level selection
VPVD
2.66 2.71
2.93 2.99
2.84 3.02
3.03 3.10
2.93 2.99
3.14 3.21
3.03 3.09
(2)
VPVDhyst
PVD hysteresis
100
-
mV
V
1.60(1)
1.64
Falling edge
1.68 1.76
1.72 1.80
Power-on/power-down
reset threshold
VPOR/PDR
Rising edge
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Table 20. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ Max Unit
(2)
VPDRhyst
PDR hysteresis
-
-
40
-
mV
Falling edge
2.13
2.23
2.44
2.53
2.75
2.85
-
2.19 2.24
2.29 2.33
2.50 2.56
2.59 2.63
2.83 2.88
2.92 2.97
Brownout level 1
threshold
VBOR1
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Brownout level 2
threshold
VBOR2
V
Brownout level 3
threshold
VBOR3
(2)
VBORhyst
BOR hysteresis
POR reset timing
-
-
100
1.5
-
mV
ms
TRSTTEMPO
0.5
3.0
(2)(3)
In-Rush current on
voltage regulator power-
on (POR or wakeup from
Standby)
(2)
IRUSH
-
-
160
-
200
5.4
mA
µC
In-Rush energy on
voltage regulator power-
on (POR or wakeup from IRUSH = 171 mA for 31 µs
Standby)
VDD = 1.7 V, TA = 105 °C,
(2)
ERUSH
-
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
3. The reset timing is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first
instruction is fetched by the user application code.
6.3.6
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 22: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
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Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in input mode with a static value at VDD or VSS (no load).
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted to both f frequency and VDD ranges
HCLK
(refer to Table 16: Features depending on the operating power supply range).
•
The voltage scaling is adjusted to f frequency as follows:
HCLK
–
–
–
Scale 3 for f
≤ 64 MHz
HCLK
Scale 2 for 64 MHz < f
Scale 1 for 84 MHz < f
≤ 84 MHz
≤ 100 MHz
HCLK
HCLK
•
•
•
The system clock is HCLK, f
= f
/2, and f
= f
.
PCLK1
HCLK
PCLK2
HCLK
External clock is 4 MHz and PLL is ON except if it is explicitly mentioned.
The maximum values are obtained for V = 3.6 V and a maximum ambient
DD
temperature (T ), and the typical values for T = 25 °C and V = 3.3 V unless
A
A
DD
otherwise specified.
Table 21. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA= 25 °C TA= 25 °C TA=85 °C TA=105 °C
100
84
64
50
25
20
16
28.1
22.7
15.7
12.3
6.5
30.24
24.05
16.99
13.36
7.44
31.27
24.54
17.47
13.82
7.82
32.21
25.11
18.03
14.36
8.30
External clock,
PLL ON,
all peripherals
enabled(2)(3)
5.6
6.16
6.66
7.20
HSI, PLL off, all
peripherals
3.9
4.70
5.31
6.08
enabled(2)(3)
1
0.6
0.78
1.33
1.98
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
14.0
11.3
7.9
15.48
12.23
8.84
7.06
4.18
3.44
2.51
16.08
12.75
9.31
7.53
4.61
3.98
3.13
16.83
13.41
10.01
8.19
External clock,
PLL ON, all
peripherals
disabled(3)
6.2
3.4
5.13
2.9
4.65
HSI, PLL off, all
peripherals
2.0
3.89
disabled(3)
1
0.5
0.64
1.21
1.90
1. Based on characterization, not tested in production unless otherwise specified
2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
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Electrical characteristics
Table 22. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA=
TA=
TA=
TA=
25 °C
25 °C
85 °C
105 °C
100
84
64
50
25
20
16
1
28.4
23.0
16.0
12.6
6.8
28.80(3)
24.09(3)
16.83(3)
13.46
7.63
30.84
25.20
17.77
13.98
8.14
32.39(3)
26.57(3)
19.12(3)
14.68
8.61
External clock,
PLL ON,
all peripherals enabled(2)
5.8
6.31
6.74
7.43
HSI, PLL OFF(4)
,
3.9
4.65
5.33
6.11
all peripherals enabled(2)
0.6
0.78
1.34
2.00
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
14.3
11.6
8.2
15.09(3)
12.28(3)
8.75(3)
7.21
16.22
13.36
9.68
17.90(3)
14.99(3)
11.21(3)
8.47
External clock,
PLL ON,
all peripherals disabled(2)
6.5
7.69
3.6
4.22
4.68
5.29
3.2
3.65
4.18
4.94
2.0
2.48
3.12
3.94
HSI, PLL OFF,
all peripherals disabled(2)
0.5
0.65
1.26
1.94
1. Based on characterization, not tested in production unless otherwise specified
2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
3. Tested in production
4. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered
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Table 23. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C
85 °C 105 °C
100
84
64
50
25
20
16
1
26.9
21.6
15.0
11.8
6.3
28.78
23.14
16.08
12.74
7.13
29.86
23.93
16.70
13.33
7.69
31.30
24.89
17.46
14.07
8.30
External clock,
PLL ON,
all peripherals enabled(2)(3)
5.5
6.09
6.64
7.30
3.9
4.20
4.78
4.49
HSI, PLL OFF,
all peripherals enabled(2)
0.9
0.98
1.50
2.20
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
12.7
10.3
7.2
13.82
11.20
7.87
14.71
11.97
8.57
15.76
12.96
9.41
External clock,
PLL ON(4)
all peripherals disabled(2)
5.7
6.33
7.02
7.87
3.2
3.77
4.38
5.13
2.9
3.31
3.93
4.69
2.1
2.25
2.83
3.56
HSI, PLL OFF, all
peripherals disabled(2)
0.7
0.83
1.42
2.12
1. Based on characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
4. Refer to Table 44 and RM0383 for the possible PLL VCO setting
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Table 24. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C
85 °C 105 °C
100
84
64
50
25
20
16
1
27.2
21.9
15.2
12.1
6.6
28.70(4) 30.14
31.98
25.37
17.87
14.46
8.77
23.60
16.45
13.12
7.59
24.31
17.03
13.67
8.12
External clock,
PLL ON(2)
,
all peripherals enabled(3)
5.7
6.51
7.07
7.77
4.0
4.32
4.88
5.69
HSI, PLL OFF, all
peripherals enabled(3)
0.8
1.14
1.67
2.38
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
13.0
10.5
7.5
14.06(4) 15.34
17.27
13.47
9.88
11.21
8.29
6.73
4.18
3.72
2.41
0.99
12.16
9.01
7.32
4.73
4.25
2.94
1.51
External clock, PLL ON(2)
all peripherals disabled(3)
6.0
8.27
3.5
5.57
3.1
5.10
2.1
3.75
HSI, PLL OFF, all
peripherals disabled(3)
0.7
2.30
1. Based on characterization, not tested in production unless otherwise specified.
2. Refer to Table 44 and RM0383 for the possible PLL VCO setting
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
4. Tested in production.
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Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C
85 °C 105 °C
100
84
64
50
25
20
16
1
36.3
31.1
22.3
18.3
10.1
8.6
38.95
33.22
23.97
19.77
11.39
9.60
41.19
34.81
25.10
20.65
12.16
10.25
7.51
42.95
36.10
26.23
21.73
13.11
11.06
8.38
External clock,
PLL ON(2)
,
all peripherals enabled(3)
6.3
6.85
HSI, PLL OFF, all
peripherals enabled(3)
1.1
1.39
1.82
2.61
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
22.1
19.7
14.5
12.2
7.0
23.95
20.79
15.88
13.38
8.05
25.80
22.52
17.21
14.59
8.89
27.50
24.12
18.54
15.79
10.16
8.52
External clock, PLL ON(2)
all peripherals disabled(3)
6.0
6.84
7.51
4.4
4.91
5.56
6.54
HSI, PLL OFF, all
peripherals disabled(3)
0.9
1.25
1.79
2.59
1. Based on characterization, not tested in production unless otherwise specified.
2. Refer to Table 44 and RM0383 for the possible PLL VCO setting
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
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Table 26. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C
85 °C 105 °C
100
84
64
50
25
20
16
1
35.9
29.4
22.4
18.6
10.3
8.9
38.55
31.59
24.02
20.07
11.62
9.85
40.77
33.12
25.15
21.08
12.39
10.59
8.04
42.52
34.42
26.28
22.05
13.34
11.32
8.80
External clock,
PLL ON,
all peripherals enabled(2)(3)
6.7
7.26
HSI, PLL OFF, all
peripherals enabled(2)(3)
1.1
1.44
1.99
2.66
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
21.7
18.0
14.6
12.5
7.2
23.55
19.16
15.93
13.63
8.25
25.48
20.93
17.32
14.90
9.26
27.07
22.39
18.59
16.07
10.26
8.84
External clock, PLL ON(3)
all peripherals disabled
6.3
7.15
7.99
4.9
5.37
6.20
7.03
HSI, PLL OFF, all
peripherals disabled(3)
1.0
1.30
1.91
2.65
1. Based on characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
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Table 27. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C
85 °C 105 °C
100
84
64
50
25
20
16
1
38.9
32.8
23.6
18.7
10.1
8.6
41.10
34.61
24.96
19.90
11.11
9.46
42.85
35.77
25.84
20.67
11.70
10.07
7.42
44.28
36.72
26.64
21.45
12.40
10.81
8.21
External clock,
PLL ON,
all peripherals enabled(2)
6.3
6.77
HSI, PLL OFF,
all peripherals enabled
1.1
1.35
1.84
2.59
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
24.7
21.4
15.8
12.6
7.0
26.11
22.22
16.80
13.51
7.85
27.59
23.53
17.90
14.52
8.57
28.84
24.66
18.99
15.54
9.39
External clock,
PLL ON(2)
all peripherals disabled
6.0
6.67
7.37
8.26
4.5
4.80
5.47
6.33
HSI, PLL OFF,
all peripherals disabled
0.9
1.25
1.81
2.58
1. Based on characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
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Table 28. Typical and maximum current consumption in Sleep mode - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C
85 °C 105 °C
100
84
64
50
25
20
16
17.7
14.3
10.0
7.9
18.48(3) 19.83
21.70
17.48
12.13
9.89
15.39
10.71
8.53
4.99
4.42
2.83
16.31
11.35
9.13
5.46
4.95
3.47
All peripherals enabled(2)
External clock,
PLL ON,
,
Flash deep power down
4.4
6.11
4.0
5.64
All peripherals enabled(2)
HSI, PLL OFF,
,
2.7
4.21
1
0.5
0.68
1.25
1.92
Flash deep power down
100
84
64
50
25
20
16
1
18.1
14.7
10.3
8.2
4.7
4.2
2.7
0.8
3.2
2.6
2.0
1.7
1.2
1.3
0.5
19.39
15.80
11.02
8.88
5.30
4.67
3.10
0.93
3.42
3.09
2.33
2.02
1.63
1.62
0.63
20.70
16.71
11.66
9.53
5.82
5.18
3.72
1.50
4.98
3.63
2.81
2.54
2.21
2.09
1.24
22.24
17.92
12.45
10.26
6.53
5.90
4.50
2.18
6.88
4.44
3.46
3.12
2.89
2.78
1.92
All peripherals enabled(2)
External clock,
PLL ON Flash ON
,
All peripherals enabled(2)
HSI, PLL ON, Flash ON
,
Supply current
in Sleep mode
IDD
mA
100
84
64
50
25
20
16
All peripherals disabled,
External clock,
PLL ON(2)
,
Flash deep power down
All peripherals disabled,
HSI, PLL OFF(2)
,
1
0.4
0.53
1.14
1.82
Flash deep power down
100
84
64
50
25
20
16
3.6
3.0
2.3
2.0
1.4
1.5
0.8
4.17
3.49
2.69
2.33
1.88
1.88
0.91
4.84
4.13
3.23
2.83
2.39
2.43
1.50
5.63
4.88
3.85
3.45
3.06
3.06
2.22
All peripherals disabled,
External clock,
PLL ON(2), Flash ON
All peripherals disabled,
HSI, PLL OFF(2)
Flash ON
,
1
0.7
0.78
1.37
2.09
1. Based on characterization, not tested in production unless otherwise specified.
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2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. Tested in production.
Table 29. Typical and maximum current consumption in Sleep mode - V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C
85 °C 105 °C
100
84
64
50
25
20
16
17.3
14.0
9.7
18.62
15.08
10.41
8.27
19.90
16.04
11.02
8.89
21.40
17.16
11.80
9.62
External clock,
PLL ON,
Flash deep power down,
7.6
all peripherals enabled(2)
4.2
4.79
5.35
6.00
3.7
4.11
4.67
5.31
HSI, PLL OFF(2)
,
2.4
2.81
3.45
4.20
Flash deep power down,
all peripherals enabled
1
0.5
0.67
1.27
1.91
Supply current
in Sleep mode
IDD
mA
100
84
64
50
25
20
16
17.8
14.4
10.0
7.9
19.08
15.49
10.76
8.58
20.35
16.42
11.43
9.19
21.90
17.59
12.18
9.94
External clock, PLL ON(2)
all peripherals enabled,
Flash ON
4.4
4.99
5.54
6.21
4.0
4.42
4.95
5.64
HSI, PLL OFF(2), all
peripherals enabled,
Flash ON
2.7
3.09
3.75
4.49
1
0.8
0.93
1.52
2.18
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Table 29. Typical and maximum current consumption in Sleep mode - V = 1.7 V (continued)
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
25 °C
25 °C
85 °C 105 °C
100
84
64
50
25
20
16
2.9
2.4
1.7
1.4
1.0
1.3
0.5
3.51
2.83
2.08
1.77
1.37
1.37
0.63
4.14
3.46
2.59
2.23
1.88
1.88
1.23
4.90
4.16
3.18
2.84
2.50
2.50
1.91
All peripherals disabled,
External clock,
PLL ON(2)
,
Flash deep power down
All peripherals disabled,
HSI, PLL OFF(2)
,
1
0.4
0.52
1.13
1.81
Supply current
in Sleep mode
Flash deep power down
IDD
mA
100
84
64
50
25
20
16
1
3.3
2.8
2.1
1.7
1.2
1.3
0.8
0.7
3.22
2.62
1.89
1.58
1.28
1.28
0.88
0.77
3.98
3.30
2.50
2.16
1.82
1.82
1.36
1.26
4.90
4.16
3.18
2.84
2.50
2.50
1.91
1.81
All peripherals disabled,
External clock, PLL ON(2)
Flash ON
,
All peripherals disabled,
HSI, PLL OFF(2), Flash ON
1. Based on characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
Table 30. Typical and maximum current consumptions in Stop mode - V = 1.7 V
DD
Typ(1)
Max(1)
Symbol
Conditions
Parameter
Unit
TA =
TA =
TA =
TA =
25 °C 25 °C 85 °C 105 °C
121.1 168.0 648.7 1213.0
50.8 104.7 667.4 1328.0
79.1 122.0 609.1 1181.0
Flash in Stop mode, all
oscillators OFF, no
independent watchdog
Main regulator usage
Low power regulator usage
Main regulator usage
IDD_STOP
µA
Flash in Deep power
down mode, all oscillators Low power regulator usage
22.4
18.5
74.7 631.9 1286.0
58.5 558.3 1145.0
OFF, no independent
Low power low voltage regulator
watchdog
usage
1. Based on characterization, not tested in production.
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Table 31. Typical and maximum current consumption in Stop mode - V =3.6 V
DD
Max(1)
Typ
Symbol
Conditions
Parameter
Unit
TA =
TA =
TA =
TA =
25 °C 25 °C 85 °C 105 °C
124.0 179.0(2) 907.2 1762.0(2)
52.8 104.9(2) 773.8 1559.0
87.6 123.0 698.5 1374.0
Flash in Stop mode, all
oscillators OFF, no
independent watchdog
Main regulator usage
Low power regulator usage
IDD_STOP
µA
Flash in Deep power
down mode, all oscillators
OFF, no independent
watchdog
Main regulator usage
Low power regulator usage
26.2
74.7 737.2 1515.0
Low power low voltage regulator usage 20.1 58.5(2) 629.1 1299.0(2)
1. Based on characterization, not tested in production.
2. Tested in production.
Table 32. Typical and maximum current consumption in Standby mode - V = 1.7 V
DD
Typ(1)
Max(2)
Symbol
Parameter
Conditions
Unit
TA =
TA = TA =
TA =
25 °C 25 °C 85 °C 105 °C
Low-speed oscillator (LSE in low drive
mode) and RTC ON
1.8
3.7
12.9
23.7
Supply current in
Standby mode
IDD_STBY
Low-speed oscillator (LSE in high drive
mode) and RTC ON
µA
2.6
1.1
4.5
3.0
13.7
13.1
24.5
25.0
RTC and LSE OFF
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Based on characterization, not tested in production unless otherwise specified.
Table 33. Typical and maximum current consumption in Standby mode - V = 3.6 V
DD
Typ(1)
Max(2)
Symbol
Parameter
Conditions
Unit
TA =
TA = TA =
TA =
25 °C 25 °C 85 °C 105 °C
Low-speed oscillator (LSE in low drive
mode) and RTC ON
3.7
5.4
16.0
28.4
Supply current in
Standby mode
IDD_STBY
Low-speed oscillator (LSE in high drive
mode) and RTC ON
µA
4.5
2.6
6.2
4.0
16.8
16.0
29.2
RTC and LSE OFF
30.0(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed by characterization, not tested in production unless otherwise specified.
3. Tested in production.
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Table 34. Typical and maximum current consumptions in V
mode
BAT
Typ
Max(2)
TA = TA =
85 °C 105 °C Unit
TA = 25 °C
Symbol Parameter
Conditions(1)
VBAT = VBAT= VBAT = VBAT
1.7 V 2.4 V 3.3 V 3.6 V
=
VBAT = 3.6 V
Low-speed oscillator (LSE in low-
drive mode) and RTC ON
0.74
0.87
1.04
1.11
3.0
5.0
Backup
I
DD_VBAT domain supply Low-speed oscillator (LSE in high-
µA
1.52
0.04
1.70
0.04
1.97
0.05
2.09
0.05
3.8
2.0
5.8
4.0
current
drive mode) and RTC ON
RTC and LSE OFF
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization, not tested in production.
Figure 24. Typical V
current consumption (LSE and RTC ON/LSE oscillator
“low power” mode selection)
BAT
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Electrical characteristics
Figure 25. Typical V
STM32F412xE/G
current consumption (LSE and RTC ON/LSE oscillator
BAT
“high drive” mode selection)
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I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 56: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 36: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
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pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
INT
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Table 35. Switching output I/O current consumption
I/O toggling
Symbol
Parameter
Conditions(1)
Typ
Unit
frequency (fSW
)
2 MHz
8 MHz
0.05
0.15
0.45
0.85
1.00
1.40
1.67
0.10
0.35
1.05
2.20
2.40
3.55
4.23
0.20
0.65
1.85
2.45
4.70
8.80
10.47
0.25
1.00
3.45
7.15
11.55
0.32
1.27
3.88
12.34
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
VDD = 3.3 V
C = CINT
8 MHz
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
VDD = 3.3 V
CEXT = 0 pF
C = CINT + CEXT + CS
I/O switching
current
IDDIO
mA
8 MHz
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
VDD = 3.3 V
CEXT =10 pF
C = CINT + CEXT + CS
8 MHz
VDD = 3.3 V
CEXT = 22 pF
25 MHz
50 MHz
60 MHz
2 MHz
C = CINT + CEXT + CS
VDD = 3.3 V
8 MHz
CEXT = 33 pF
25 MHz
50 MHz
C = CINT + CEXT + CS
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
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On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
•
•
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
The ART accelerator is ON.
Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.
HCLK is the system clock at 100 MHz. f = f /2, and f = f .
HCLK
PCLK1
HCLK
PCLK2
The given value is calculated by measuring the difference of current consumption
–
–
–
–
–
with all peripherals clocked off,
with only one peripheral clocked on,
scale 1 with f
scale 2 with f
scale 3 with f
= 100 MHz,
= 84 MHz,
= 64 MHz.
HCLK
HCLK
HCLK
•
Ambient operating temperature is 25 °C and V =3.3 V.
DD
Table 36. Peripheral current consumption
I
DD (Typ)
Peripheral
Unit
Scale 1
Scale 2
Scale 3
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
CRC
1.84
1.90
1.77
1.67
1.75
1.65
1.65
0.62
0.26
1.75
1.80
1.67
1.58
1.67
1.56
1.56
0.57
0.25
1.55
1.61
1.50
1.42
1.48
1.39
1.39
0.53
0.22
AHB1
µA/MHz
DMA1(1)
DMA2(1)
RNG
1,71N+2,98 1,62N+2,87 1,45N+2,58
1,78N+2,62 1,70N+2.53 1,52N+2.26
0.77
19.68
5.36
0.74
18.73
5.11
0.66
16.78
4.56
AHB2
AHB3
USB_OTG_FS
FSMC
QSPI
9.99
9.51
8.53
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Electrical characteristics
STM32F412xE/G
Table 36. Peripheral current consumption (continued)
DD (Typ)
I
Peripheral
Unit
Scale 1
Scale 2
Scale 3
AHB-APB1 bridge
TIM2
1.10
13.62
10.56
10.72
13.46
2.92
2.72
6.22
4.70
4.60
1.76
4.04
4.26
4.42
4.44
4.32
4.36
4.36
5.96
6.18
5.86
1.82
1.00
12.95
10.05
10.21
12.83
2.79
2.60
5.93
4.48
4.38
1.67
3.83
4.05
4.19
4.21
4.10
4.17
4.14
5.69
5.90
5.52
1.69
0.94
11.59
8.97
9.12
11.47
2.47
2.31
5.28
3.97
3.91
TIM3
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
WWDG
SPI2/I2S2
SPI3/I2S3
USART2
USART3
I2C1
1.47
APB1
µA/MHz
3.41
3.62
3.75
3.75
3.66
3.69
3.69
5.06
5.25
4.97
1.56
I2C2
I2C3
I2CFMP1
CAN1
CAN2
PWR
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Electrical characteristics
Table 36. Peripheral current consumption (continued)
DD (Typ)
I
Peripheral
Unit
Scale 1
Scale 2
Scale 3
AHB-APB2 bridge
TIM1
0.09
6.83
6.63
3.31
3.21
3.51
3.74
1.47
1.56
0.54
3.09
1.91
1.93
1.54
4.25
3.23
0.07
6.46
6.29
3.11
3.02
3.31
3.51
1.36
1.45
0.49
2.92
1.79
1.81
1.44
4.02
3.06
0.08
5.81
5.63
2.80
2.73
2.98
3.17
1.23
1.31
0.45
2.63
1.61
1.64
1.30
3.61
2.73
TIM8
USART1
USART6
ADC1
SDIO
APB2
SPI1
µA/MHz
SPI4
SYSCFG
TIM9
TIM10
TIM11
SPI5
DFSDM1
Bus Matrix
1. N is the number of stream enable (1...8).
6.3.7
Wakeup time from low-power modes
The wakeup times given in Table 37 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PA0/PC0/PC1) pins are used to wakeup from Standby, Stop and Sleep modes.
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Electrical characteristics
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Figure 26. Low-power mode wakeup
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All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
Table 37. Low-power mode wakeup timings(1)
Min(1)
Typ(1) Max(1)
Symbol
Parameter
Conditions
Unit
clk
cycles
tWUSLEEP
-
-
4
-
6
Wakeup from Sleep mode
Flash memory in Deep
power down mode
tWUSLEEPFDSM
-
50.0
µs
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STM32F412xE/G
Symbol
Electrical characteristics
Table 37. Low-power mode wakeup timings(1) (continued)
Min(1)
Typ(1) Max(1)
12.9 15.0
Parameter
Conditions
Unit
Main regulator
-
Main regulator, Flash
memory in Deep power
down mode
-
-
-
-
104.9 120.0
Wakeup from STOP mode
Code execution on Flash
Wakeup from Stop mode,
regulator in low power
mode(2)
tWUSTOP
20.8
112.9
4.9
28.0
130.0
7.0
Regulator in low power
mode, Flash memory in
Deep power down mode(2)
Main regulator with Flash in
Stop mode or Deep power
down
µs
Wakeup from STOP mode
code execution on RAM(3)
tWUSTOP
Wakeup from Stop mode,
regulator in low power mode
and Flash in Stop mode or
Deep power down(2)
-
12.8
20.0
Wakeup from Standby
mode
tWUSTDBY
-
-
-
-
316.8 400.0
11.0
From Flash_Stop mode
tWUFLASH
Wakeup of Flash
From Flash Deep power
down mode
50.0
1. Guaranteed by characterization, not tested in production.
2. The specification is valid for wakeup from regulator in low power mode or low power low voltage mode, since the timing
difference is negligible.
3. For the faster wakeup time for code execution on RAM, the Flash must be in STOP or DeepPower Down mode (see
reference manual RM0402).
6.3.8
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 56. However, the recommended clock input
waveform is shown in Figure 27.
The characteristics given in Table 38 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 15.
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Electrical characteristics
Symbol
STM32F412xE/G
Table 38. High-speed external user clock characteristics
Parameter
Conditions
Min
Typ
Max
Unit
External user clock source
frequency(1)
fHSE_ext
1
-
50
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
5
-
-
-
-
tw(HSE)
ns
tr(HSE)
tf(HSE)
10
Cin(HSE) OSC_IN input capacitance(1)
-
45
-
5
-
-
pF
%
DuCy(HSE) Duty cycle
55
±1
IL
OSC_IN Input leakage current
VSS ≤VIN ≤VDD
-
µA
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 56. However, the recommended clock input
waveform is shown in Figure 28.
The characteristics given in Table 39 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 15.
Table 39. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
0.7VDD
VSS
-
-
-
VDD
0.3VDD
-
V
VLSEL
tw(LSE)
OSC32_IN input pin low level voltage
OSC32_IN high or low time(1)
450
tf(LSE)
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
-
-
50
Cin(LSE)
OSC32_IN input capacitance(1)
-
30
-
5
-
-
pF
%
DuCy(LSE) Duty cycle
70
±1
IL
OSC32_IN Input leakage current
VSS ≤ VIN ≤ VDD
-
µA
1. Guaranteed by design, not tested in production.
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Electrical characteristics
Figure 27. High-speed external clock source AC timing diagram
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 40. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
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Electrical characteristics
Symbol
STM32F412xE/G
(1)
Table 40. HSE 4-26 MHz oscillator characteristics
Parameter
Conditions
Min
Typ Max Unit
fOSC_IN
RF
Oscillator frequency
Feedback resistor
4
-
-
26
-
MHz
200
kΩ
VDD=3.3 V,
ESR= 30 Ω,
-
-
450
530
-
-
CL=5 pF @25 MHz
IDD
HSE current consumption
HSE accuracy
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF @25 MHz
(2)
ACCHSE
-
-500
-
-
500
ppm
mA/V
ms
Gm_crit_max Maximum critical crystal gm
Startup
-
-
1
-
(3)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design, not tested in production.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 29). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 29. Typical application with an 8 MHz crystal
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Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 41. In
the application, the resonator and the load capacitors have to be placed as close as
104/193
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Electrical characteristics
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
The LSE high-power mode allows to cover a wider range of possible crystals but with a cost
of higher power consumption.
(1)
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
-
-
18.4
-
MΩ
Low-power mode
(default)
-
-
1
IDD
LSE current consumption
LSE accuracy
µA
High-drive mode
-
-
-
-
3
(2)
ACCLSE
-500
500
ppm
Startup, low-power
mode
-
-
0.56
Gm_crit_max Maximum critical crystal gm
µA/V
s
Startup, high-drive
mode
-
-
-
1.50
-
(3)
tSU(LSE)
startup time
VDD is stabilized
2
1. Guaranteed by design, not tested in production.
2. This parameter depends on the crystal used in the application. Refer to the application note AN2867.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is guaranteed by characterization and not tested in
production. It is measured for a standard crystal resonator and it can vary significantly with the crystal
manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
For information about the LSE high-power mode, refer to the reference manual RM0383.
Figure 30. Typical application with a 32.768 kHz crystal
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Electrical characteristics
STM32F412xE/G
6.3.9
Internal clock source characteristics
The parameters given in Table 42 and Table 43 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 15.
DD
High-speed internal (HSI) RC oscillator
L
(1)
Table 42. HSI oscillator characteristics
Symbol
Parameter
Frequency
HSI user trimming step(2)
Conditions
Min
Typ
Max Unit
fHSI
-
-
-
16
-
1
MHz
%
-
-
TA = –40 to 105 °C(3)
–8
–4
–1
-
-
-
4.5
4
%
ACCHSI
Accuracy of the HSI oscillator TA = –10 to 85 °C(3)
TA = 25 °C(4)
%
-
1
%
(2)
tsu(HSI)
HSI oscillator startup time
-
-
2.2
4
µs
HSI oscillator power
consumption
(2)
IDD(HSI)
-
60
80
µA
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production
3. Based on characterization, not tested in production
4. Factory calibrated, parts not soldered.
Figure 31. ACC
versus temperature
HSI
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1. Guaranteed by characterization, not tested in production.
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Electrical characteristics
Low-speed internal (LSI) RC oscillator
(1)
Table 43. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
17
-
32
15
47
40
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
(3)
IDD(LSI)
LSI oscillator power consumption
-
0.4
0.6
µA
1.
VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Figure 32. ACC versus temperature
LSI
-3ꢀꢂꢁꢀꢈ6ꢀ
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STM32F412xE/G
6.3.10
PLL characteristics
The parameters given in Table 44 and Table 45 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 15.
DD
Table 44. Main PLL characteristics
Symbol
Parameter
PLL input clock(1)
Conditions
Min
Typ
Max
Unit
fPLL_IN
-
-
0.95(2)
24
1
-
2.10
100
MHz
MHz
fPLL_OUT
PLL multiplier output clock
48 MHz PLL multiplier output
clock
fPLL48_OUT
fVCO_OUT
-
-
48
75
MHz
MHz
PLL VCO output
PLL lock time
-
100
75
100
-
-
-
432
200
300
-
VCO freq = 100 MHz
VCO freq = 432 MHz
tLOCK
µs
-
Cycle-to-cycle jitter
Period Jitter
RMS
25
peak
to
peak
-
-
-
150
15
-
-
-
System clock
100 MHz
RMS
Jitter(3)
ps
peak
to
200
peak
Cycle to cycle at 1 MHz
on 1000 samples.
Bit Time CAN jitter
-
330
-
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
(4)
IDD(PLL)
PLL power consumption on VDD
-
-
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLL power consumption on
VDDA
(4)
IDDA(PLL)
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of two PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization, not tested in production.
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Symbol
Electrical characteristics
Table 45. PLLI2S (audio PLL) characteristics
Parameter
PLLI2S input clock(1)
Conditions
Min
Typ
Max
Unit
fPLLI2S_IN
fPLLI2S_OUT
fVCO_OUT
-
0.95(2)
1
-
2.10
216
432
200
300
-
PLLI2S multiplier output clock
PLLI2S VCO output
-
-
-
MHz
100
75
100
-
-
VCO freq = 100 MHz
VCO freq = 432 MHz
-
tLOCK
PLLI2S lock time
µs
-
RMS
90
Cycle to cycle at
12.288 MHz on
48 kHz period,
N=432, R=5
peak
to
peak
-
280
90
-
Master I2S clock jitter
WS I2S clock jitter
Average frequency of
12.288 MHz
Jitter(3)
ps
-
-
-
-
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
400
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLI2S power consumption on
VDD
(4)
IDD(PLLI2S)
-
-
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLI2S power consumption on
VDDA
(4)
IDDA(PLLI2S)
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Guaranteed by characterization, not tested in production.
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Electrical characteristics
STM32F412xE/G
6.3.11
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 52: EMI characteristics for LQFP144). It is available only on the
main PLL.
Table 46. SSCG parameter constraints
Symbol
Parameter
Min
Typ
Max(1)
Unit
fMod
md
Modulation frequency
Peak modulation depth
-
0.25
-
-
-
-
10
2
kHz
%
MODEPER * INCSTEP
(Modulation period) * (Increment Step)
215-1
-
1. Guaranteed by design, not tested in production.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round[fPLL_IN ⁄ (4 × fMod)]
f
and f
must be expressed in Hz.
PLL_IN
Mod
As an example:
If f = 1 MHz, and f
= 1 kHz, the modulation depth (MODEPER) is given by
PLL_IN
MOD
equation 1:
MODEPER = round[106 ⁄ (4 × 103)] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]
f
must be expressed in MHz.
VCO_OUT
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN)
As a result:
mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak)
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Electrical characteristics
Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
nominal.
PLL_OUT
T
is the modulation period.
mode
md is the modulation depth.
Figure 33. PLL output clock waveforms in center spread mode
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6.3.12
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
The devices are shipped to customers with the Flash memory erased.
Table 47. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Write / Erase 8-bit mode, VDD = 1.7 V
Write / Erase 16-bit mode, VDD = 2.1 V
Write / Erase 32-bit mode, VDD = 3.3 V
-
-
-
5
8
-
-
-
IDD
Supply current
mA
12
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Table 48. Flash memory programming
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
Program/eraseparallelism
(PSIZE) = x 8/16/32
tprog
Word programming time
-
-
-
-
-
-
-
-
-
-
-
-
-
16
100(2) µs
800
Program/eraseparallelism
(PSIZE) = x 8
400
300
250
Program/eraseparallelism
(PSIZE) = x 16
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
600
500
ms
ms
s
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
1200 2400
Program/eraseparallelism
(PSIZE) = x 16
700
550
2
1400
1100
4
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
Program/eraseparallelism
(PSIZE) = x 16
1.3
1
2.6
2
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
16
11
8
32
Program/eraseparallelism
(PSIZE) = x 16
tME
Mass erase time
22
s
Program/eraseparallelism
(PSIZE) = x 32
16
32-bit program operation
16-bit program operation
8-bit program operation
2.7
2.1
1.7
-
-
-
3.6
3.6
3.6
V
V
V
Vprog
Programming voltage
1. Guaranteed by characterization, not tested in production.
2. The maximum programming time is measured after 100K erase operations.
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Table 49. Flash memory programming with V voltage
PP
Symbol
tprog
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Double word programming
-
-
16
230
490
875
6.9
-
100(2)
µs
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
-
-
TA = 0 to +40 °C
VDD = 3.3 V
-
ms
VPP = 8.5 V
-
-
tME
Vprog
VPP
Mass erase time
-
-
s
V
V
Programming voltage
VPP voltage range
-
-
2.7
7
3.6
9
-
Minimum current sunk on
the VPP pin
IPP
-
-
10
-
-
-
-
mA
Cumulative time during
which VPP is applied
(3)
tVPP
1
hour
1. Guaranteed by design, not tested in production.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
Table 50. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions
Unit
Min(1)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND Endurance
kcycles
Years
10
1 kcycle(2) at TA = 85 °C
30
10
20
tRET
Data retention 1 kcycle(2) at TA = 105 °C
10 kcycle(2) at TA = 55 °C
1. Guaranteed by characterization, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.13
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
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The test results are given in Table 52. They are based on the EMS levels and classes
defined in application note AN1709.
Table 51. EMS characteristics for LQFP144 package
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP144
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
TA = +25 °C, fHCLK = 100 MHz,
conforms to IEC 61000-4-2
2B
4B
V
DD = 3.3 V, LQFP144
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VEFTB
TA = +25 °C, fHCLK = 100 MHz,
conforms to IEC 61000-4-4
When the application is exposed to a noisy environment, it is recommended to avoid pin
exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,
PA2, on LQFP144 packages and PDR_ON on WLCSP49.
As a consequence, it is recommended to add a serial resistor (1 kΩ maximum) located as
close as possible to the MCU to the pins exposed to noise (connected to tracks longer than
50 mm on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
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Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with IEC61967-2
standard which specifies the test board and the pin loading.
Table 52. EMI characteristics for LQFP144
Max vs.
[fHSE/fCPU
]
Monitored
frequency band
Symbol
Parameter
Conditions
Unit
8/100 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
EMI Level
20
28
21
3.5
VDD = 3.6 V, TA = 25 °C, LQFP144
package, conforming to IEC 61967-2,
EEMBC, ART ON, all peripheral clocks
enabled, clock dithering disabled.
dBµV
-
SEMI
Peak level
6.3.14
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 53. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Electrostatic
Conditions
Class
Unit
value(1)
VESD(HBM) discharge voltage
(human body model)
TA = +25 °C conforming to JESD22-A114
2
2000
TA = +25 °C conforming to ANSI/ESD STM5.3.1,
UFBGA144, UFBGA100, LQFP100, LQFP64,
UFQFPN48
4
500
V
Electrostatic
VESD(CDM) discharge voltage
TA = +25 °C conforming to ANSI/ESD STM5.3.1,
3
3
400
250
(charge device model) WLCSP64
TA = +25 °C conforming to ANSI/ESD STM5.3.1,
LQFP144
1. Guaranteed by characterization, not tested in production.
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Electrical characteristics
Static latchup
STM32F412xE/G
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 54. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
6.3.15
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins
(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator
frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 55.
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Table 55. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0 pin
Injected current on NRST pin
–0
–0
NA
NA
Injected current on PB3, PB4, PB5, PB6,
PB7, PB8, PB9, PC13, PC14, PC15, PH1,
PDR_ON, PC0, PC1,PC2, PC3, PD1,
PD5, PD6, PD7, PE0, PE2, PE3, PE4,
PE5, PE6
IINJ
–0
NA
mA
Injected current on any other FT pin
Injected current on any other pins
–5
–5
NA
+5
1. NA = not applicable.
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.16
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the conditions summarized in Table 15. All I/Os are CMOS and TTL
compliant.
Table 56. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FT, TC and NRST I/O input low
level voltage
(1)
1.7 V≤VDD≤3.6 V
-
-
0.3VDD
1.75 V≤VDD ≤3.6 V,
-40 °C≤TA ≤105 °C
VIL
-
-
-
-
-
V
BOOT0 I/O input low level
voltage
0.1VDD+0.1(2)
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
FT, TC and NRST I/O input high
level voltage(5)
(1)
1.7 V≤VDD≤3.6 V
0.7VDD
-
-
1.75 V≤VDD ≤3.6 V,
-40 °C≤TA ≤105 °C
VIH
V
BOOT0 I/O input high level
voltage
0.17VDD+0.7(2)
-
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
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Table 56. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FT, TC and NRST I/O input
hysteresis
(2)(3)
1.7 V≤VDD≤3.6 V
10% VDD
-
-
1.75 V≤VDD ≤3.6 V,
-40 °C≤TA ≤105 °C
VHYS
V
BOOT0 I/O input hysteresis
I/O input leakage current (4)
0.1
-
-
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
VSS ≤VIN ≤VDD
VIN = 5 V
-
-
-
-
1
3
Ilkg
µA
I/O FT/TC input leakage current
(5)
All pins
except for
PA10
(OTG_FS_ID)
VIN = VSS
30
7
40
10
40
50
14
50
Weak pull-up
equivalent
resistor(6)
RPU
PA10
(OTG_FS_ID)
-
kΩ
All pins
except for
PA10
VIN = VDD
30
Weak pull-down
equivalent
RPD
(OTG_FS_ID)
resistor(7)
PA10
(OTG_FS_ID)
-
-
7
-
10
5
14
-
(8)
CIO
I/O pin capacitance
pF
1. Guaranteed by test in production.
2. Guaranteed by design, not tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 55: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 55: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization, not tested in production.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT and TC I/Os is shown in Figure 35.
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Figure 35. FT/TC I/O input characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA (with a relaxed V /V ) except PC13, PC14 and PC15 which can
OL OH
sink or source up to 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 13).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 13).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 15. All I/Os are CMOS and TTL compliant.
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Max Unit
Table 57. Output voltage characteristics
Symbol
Parameter
Conditions
Min
(1)
VOL
VOH
VOL
VOH
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port(2)
IIO = +8 mA
-
0.4
V
(3)
(1)
(3)
VDD–0.4
-
0.4
-
2.7 V ≤VDD ≤3.6 V
TTL port(2)
IIO =+8 mA
-
V
2.4
2.7 V ≤VDD ≤3.6 V
(1)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3(4)
IIO = +20 mA
V
V
V
(3)
VDD–1.3(4)
-
2.7 V ≤VDD ≤3.6 V
VOH
VOL
VOH
-
0.4(4)
(1)
IIO = +6 mA
(3)
VDD–0.4(4)
-
0.4(5)
-
1.8 V ≤VDD ≤3.6 V
(1)
VOL
-
IIO = +4 mA
VOH
VDD–0.4(5)
(3)
1.7 V ≤VDD ≤3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 13.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
4. Guaranteed by characterization results, not tested in production.
5. Guaranteed by design, not tested in production.
.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 36 and
Table 58, respectively.
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 15.
(1)(2)
Table 58. I/O AC characteristics
OSPEEDRy
[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.70 V
CL = 50 pF, VDD≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
4
2
fmax(IO)out Maximum frequency(3)
Output high to low level fall
MHz
8
00
4
tf(IO)out
/
CL = 50 pF, VDD = 1.7 V to
3.6 V
time and output low to high
level rise time
-
-
100
ns
tr(IO)out
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OSPEEDRy
Electrical characteristics
(1)(2)
Table 58. I/O AC characteristics
(continued)
[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.70 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 50 pF, VDD ≥2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥ 2.70 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD≥ 2.70 V
CL = 40 pF, VDD≥ 1.7 V
CL = 10 pF, VDD≥ 2.70 V
CL = 10 pF, VDD≥ 1.7 V
CL = 30 pF, VDD ≥ 2.70 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 30 pF, VDD ≥ 2.70 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD≥ 2.70 V
CL = 10 pF, VDD≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
12.5
MHz
50
fmax(IO)out Maximum frequency(3)
20
10
01
Output high to low level fall
time and output low to high
level rise time
20
ns
6
tf(IO)out
tr(IO)out
/
10
50(4)
25
fmax(IO)out Maximum frequency(3)
MHz
100(4)
50(4)
6
10
Output high to low level fall
time and output low to high
level rise time
10
ns
4
tf(IO)out
tr(IO)out
/
6
100(4)
MHz
Fmax(IO)out Maximum frequency(3)
50(4)
4
11
Output high to low level fall
time and output low to high
level rise time
6
tf(IO)out
tr(IO)out
/
ns
2.5
4
Pulse width of external signals
-
tEXTIpw detected by the EXTI
controller
-
10
-
-
ns
1. Guaranteed by characterization, not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 36.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
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STM32F412xE/G
Figure 36. I/O AC characteristics definition
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6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 56).
PU
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 15. Refer to Table 56: I/O static characteristics for the values of VIH and VIL for
NRST pin.
Table 59. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Weak pull-up equivalent
resistor(1)
RPU
VIN = VSS
30
40
50
kΩ
(2)
VF(NRST)
NRST Input filtered pulse
-
-
-
-
100
-
ns
ns
(2)
VNF(NRST)
NRST Input not filtered pulse
VDD > 2.7 V
300
Internal Reset
source
TNRST_OUT Generated reset pulse duration
20
-
-
µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design, not tested in production.
122/193
DocID028087 Rev 4
STM32F412xE/G
Electrical characteristics
Figure 37. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 59. Otherwise the reset is not taken into account by the device.
6.3.18
TIM timer characteristics
The parameters given in Table 60 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 60. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
tTIMxCLK
1
-
-
or 2 or 4, fTIMxCLK
100 MHz
=
11.9
ns
tTIMxCLK
ns
tres(TIM)
Timer resolution time
1
11.9
0
-
AHB/APBx prescaler>4,
fTIMxCLK = 100 MHz
-
fTIMxCLK/2
MHz
MHz
bit
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 100 MHz
0
50
ResTIM
Timer resolution
-
16/32
16-bit counter clock
period when internal clock
is selected
tCOUNTER
fTIMxCLK = 100 MHz
0.0119
780
µs
65536 ×
65536
tTIMxCLK
S
-
-
-
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 100 MHz
51.1
1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.
2. Guaranteed by design, not tested in production.
3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE
bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise
TIMxCLK >= 4x PCLKx.
DocID028087 Rev 4
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161
Electrical characteristics
STM32F412xE/G
6.3.19
Communications interfaces
I2C interface characteristics
2
2
The I C interface meets the requirements of the standard I C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and V is
DD
disabled, but is still present.
2
The I C characteristics are described in Table 61. Refer also to Section 6.3.16: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
The I C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400
2
kHz). The I C bus frequency can be increased up to 1 MHz. For more details about the
complete solution, contact your local ST sales representative.
2
Table 61. I C characteristics
Standard mode
Fast mode I2C(1)(2)
I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
250
0
-
1.3
0.6
100
0
-
µs
-
-
-
-
SDA data hold time
3450(3)
900(4)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
-
300
-
300
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
µs
Repeated Start condition
setup time
tsu(STO)
Stop condition setup time
µs
µs
Stop to Start condition time
(bus free)
tw(STO:STA)
Pulse width of the spikes
that are suppressed by the
analog filter for standard fast
mode
tSP
-
-
-
50
-
120(5)
400
ns
Capacitive load for each bus
line
Cb
400
pF
Guaranteed by design, not tested in production.
1.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode
clock.
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
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STM32F412xE/G
Electrical characteristics
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
5. The minimum width of the spikes filtered by the analog filter is above tSP (max)
2
Figure 38. I C bus AC waveforms and measurement circuit
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1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
(1)(2)
Table 62. SCL frequency (f
= 50 MHz, VDD = VDD_I2C = 3.3 V)
I2C_CCR value
PCLK1
fSCL (kHz)
RP = 4.7 kΩ
400
300
200
100
50
0x8019
0x8021
0x8032
0x0096
0x012C
0x02EE
20
1. RP = External pull-up resistance, fSCL = I2C speed
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external
components used to design the application.
DocID028087 Rev 4
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161
Electrical characteristics
STM32F412xE/G
FMPI2C characteristics
2
The following table presents FMPI C characteristics.
Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output
function characteristics (SDA and SCL).
2
(1)
Table 63. FMPI C characteristics
Standard mode Fast mode
Fast+ mode
Min Max
18
Parameter
Unit
Min
Max
Min
Max
fFMPI2CC
FMPI2CCLK frequency
2
-
8
-
-
tw(SCLL)
tw(SCLH)
tsu(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
0.25
0
-
1.3
0.6
0.10
0
-
-
0.5
0.26
0.05
0
-
-
-
-
-
-
-
-
tH(SDA)
SDA data hold time
Data, ACK valid time
-
tv(SDA,ACK)
-
3.45
-
0.9
-
0.45
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1.0
-
0.30
-
0.12
tf(SDA)
tf(SCL)
µs
SDA and SCL fall time
Start condition hold time
-
0.30
-
0.30
-
0.12
th(STA)
tsu(STA)
4
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
0.26
0.26
0.26
0.5
-
-
-
-
Repeated Start condition
setup time
4.7
4
tsu(STO)
Stop condition setup time
Stop to Start condition time
(bus free)
tw(STO:STA)
4.7
Pulse width of the spikes that
are suppressed by the
analog filter for standard and
fast mode
tSP
Cb
-
-
-
0.05
-
0.1
0.05
-
0.1
Capacitive load for each bus
Line
550(2)
400
400
pF
1. Based on characterization results, not tested in production.
2. Can be limited. Maximum supported value can be retrieved by referring to the following formulas:
tr(SDA/SCL) = 0.8473 x Rp x Cload
Rp(min) = (VDD -VOL(max)) / IOL(max)
126/193
DocID028087 Rev 4
STM32F412xE/G
Electrical characteristics
2
Figure 39. FMPI C timing diagram and measurement circuit
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DocID028087 Rev 4
127/193
161
Electrical characteristics
STM32F412xE/G
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 64 for the SPI interface are
derived from tests performed under the ambient temperature, f frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 15, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 64. SPI dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master full duplex/receiver mode,
2.7 V < VDD < 3.6 V
-
-
50
SPI1/4/5
Master transmitter mode
1.7 V < VDD < 3.6 V
SPI1/4/5
50
25
-
-
-
-
-
-
Master mode
1.7 V < VDD < 3.6 V
SPI1/2/3/4/5
Slave transmitter/full duplex mode
fSCK
SPI clock frequency
MHz
50
2.7 V < VDD < 3.6 V
SPI1//4/5
1/tc(SCK)
Slave transmitter/full duplex mode
1.7 V < VDD < 3.6 V
SPI1/4/5
35(2)
-
-
-
-
-
-
Slave receiver mode,
1.7 V < VDD < 3.6 V
50
SPI1/4/5
Slave mode,
1.7 V < VDD < 3.6 V
SPI2/3
25
70
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
%
tw(SCKH)
tw(SCKL)
TPCLK
+1.5
TPCLK
SCK high and low time Master mode, SPI presc = 2
TPCLK−1.5
ns
tsu(NSS)
th(NSS)
tsu(MI)
tsu(SI)
th(MI)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
3TPCLK
2TPCLK
4.5
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Data input setup time
Data input hold time
Slave mode
1.5
Master mode
5
th(SI)
Slave mode
0.5
128/193
DocID028087 Rev 4
STM32F412xE/G
Symbol
Electrical characteristics
(1)
Table 64. SPI dynamic characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
ta(SO
)
Data output access time Slave mode
Data output disable time Slave mode
7
5
-
-
21
12
ns
ns
tdis(SO)
Slave mode (after enable edge),
2.7 V < VDD < 3.6 V
-
-
7.5
7.5
-
9
14
-
ns
ns
ns
tv(SO)
Data output valid time
Data output hold time
Slave mode (after enable edge),
1.7 V < VDD < 3.6 V
Slave mode (after enable edge),
1.7 V < VDD < 3.6 V
th(SO)
5.5
tv(MO)
th(MO)
Data output valid time Master mode (after enable edge)
Master mode (after enable edge)
-
3
-
8
-
ns
ns
2
Data output hold time
1. Guaranteed by characterization, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI
communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%
Figure 40. SPI timing diagram - slave mode and CPHA = 0
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DocID028087 Rev 4
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161
Electrical characteristics
STM32F412xE/G
(1)
Figure 41. SPI timing diagram - slave mode and CPHA = 1
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Figure 42. SPI timing diagram - master mode
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130/193
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Electrical characteristics
I2S interface characteristics
2
Unless otherwise specified, the parameters given in Table 65 for the I S interface are
derived from tests performed under the ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 15, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
2
(1)
Table 65. I S dynamic characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
I2S clock frequency
-
256x8K 256xFs(2)
MHz
Master data: 32 bits
Slave data: 32 bits
-
-
64xFs
fCK
MHz
%
64xFs
DCK
I2S clock frequency duty cycle Slave receiver
30
-
70
tv(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
5
th(WS)
0
-
tsu(WS)
2
-
th(WS)
Slave mode
0.5
0
-
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
Data output valid time
2
-
ns
0
-
2.5
-
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
15
2.5
-
-
6
Data output hold time
th(SD_MT)
Master transmitter (after enable edge)
0
-
1. Guaranteed by characterization, not tested in production.
2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency).
Note:
Refer to the I2S section of RM0383 reference manual for more details on the sampling
frequency (F ).
S
f
, f , and D values reflect only the digital peripheral behavior. The values of these
CK
MCK CK
parameters might be slightly impacted by the source clock precision. D depends mainly
CK
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
maximum value is supported for each mode/condition.
S
DocID028087 Rev 4
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161
Electrical characteristics
STM32F412xE/G
2
(1)
Figure 43. I S slave timing diagram (Philips protocol)
t
c(CK)
CPOL = 0
CPOL = 1
WS input
t
t
t
t
w(CKL)
h(WS)
w(CKH)
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
transmit
(2)
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
(2)
LSB receive
Bitn receive
LSB receive
SD
receive
ai14881b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 44. I S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
CPOL = 1
WS output
t
w(CKH)
t
t
h(WS)
t
v(WS)
w(CKL)
t
t
v(SD_MT)
h(SD_MT)
(2)
SD
transmit
receive
LSB transmit
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
(2)
SD
LSB receive
Bitn receive
LSB receive
ai14884b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
132/193
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STM32F412xE/G
Electrical characteristics
QSPI interface characteristics
Unless otherwise specified, the parameters given in the following tables for QSPI are
derived from tests performed under the ambient temperature, f frequency and V
AHB
DD
supply voltage conditions summarized in Table 15, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C=20pF
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
Table 66. QSPI dynamic characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Write mode
1.71 V≤VDD≤3.6 V
-
-
80
Cload = 15 pF
fSCK
QSPI clock
frequency
MHz
Read mode
2.7 V<VDD<3.6 V
Cload = 15 pF
1/tc(SCK)
-
-
100
1.71 V≤VDD≤3.6 V
-
-
-
-
50
tw(CKH)
tw(CKL)
(T(CK) / 2)-1
T(CK) / 2)
T(CK) / 2
QSPI clock high
and low
-
(T(CK) / 2)+1
Data input setup
time
ts(IN)
-
-
-
-
0.5
3.5
-
-
-
-
-
Data input hold
time
ns
th(IN)
Data output valid
time
tv(OUT)
th(OUT)
1
-
1.5
-
Data output hold
time
0.5
1. Guaranteed by characterization results, not tested in production.
(1)
Table 67. QSPI dynamic characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Write mode
1.71 V≤VDD≤3.6 V
-
-
80
Cload = 15 pF
fSCK
QSPI clock
frequency
MHz
Read mode
2.7 V<VDD<3.6 V
Cload = 15 pF
1/tc(SCK)
-
-
-
-
80
50
1.71 V≤VDD≤3.6 V
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STM32F412xE/G
(1)
Table 67. QSPI dynamic characteristics in DDR mode (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tw(CKH)
tw(CKL)
(T(CK) / 2)-1
T(CK) / 2)
-
-
T(CK) / 2
QSPI clock high
and low
-
(T(CK) / 2)+1
Data input setup
time
ts(IN)
th(IN)
-
-
0
4
-
-
-
-
Data input hold
time
ns
2.7 V<VDD<3.6 V
1.71 V<VDD<3.6 V
-
-
8
8
10.5
13
Data output valid
time
tv(OUT)
Data output hold
time
th(OUT)
-
7.5
-
-
1. Guaranteed by characterization results, not tested in production.
USB OTG full speed (FS) characteristics
This interface is present in USB OTG FS controller.
Table 68. USB OTG FS startup time
Parameter
USB OTG FS transceiver startup time
Symbol
Max
Unit
µs
(1)
tSTARTUP
1
1. Guaranteed by design, not tested in production.
Table 69. USB OTG FS DC electrical characteristics
Symbol
VDD
Parameter
Conditions
Min.(1) Typ. Max.(1) Unit
USB OTG FS operating
voltage
3.0(2)
0.2
-
-
-
3.6
-
V
(3)
VDI
Differential input sensitivity
I(USB_FS_DP/DM)
Includes VDI range
Input
Differential common mode
range
(3)
levels
VCM
0.8
2.5
V
Single ended receiver
threshold
(3)
VSE
1.3
-
2.0
VOL Static output level low
VOH Static output level high
RL of 1.5 kΩto 3.6 V(4)
-
-
-
0.3
3.6
Output
levels
V
(4)
RL of 15 kΩto VSS
2.8
PA11, PA12
(USB_FS_DM/DP)
17
0.65
1.5
21
1.1
1.8
24
2.0
2.1
RPD
VIN = VDD
PA9 (OTG_FS_VBUS)
kΩ
PA11, PA12
(USB_FS_DM/DP)
VIN = VSS
VIN = VSS
RPU
PA9 (OTG_FS_VBUS)
0.25 0.37 0.55
1. All the voltages are measured from the local ground potential.
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2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Guaranteed by design, not tested in production.
RL is the load connected on the USB OTG FS drivers.
4.
When VBUS sensing feature is enabled, PA9 should be left at their default state (floating
input), not as alternate function. A typical 200 µA current consumption of the embedded
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 when the feature is enabled.
Note:
Figure 45. USB OTG FS timings: definition of data signal rise and fall time
Crossover
points
Differential
Data Lines
V
CR S
V
SS
t
t
r
f
ai14137
Table 70. USB OTG FS electrical characteristics(1)
Driver characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification -
Chapter 7 (version 2.0).
2.
CAN (controller area network) interface
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
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STM32F412xE/G
6.3.20
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 71 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 15.
Table 71. ADC characteristics
Conditions
Symbol
Parameter
Power supply
Min
Typ
Max
Unit
VDDA
1.7(1)
1.7(1)
0.6
-
-
3.6
VDDA
18
V
VDDA −VREF+ < 1.2 V
VREF+ Positive reference voltage
V
VDDA = 1.7(1) to 2.4 V
15
MHz
MHz
fADC
ADC clock frequency
VDDA = 2.4 to 3.6 V
0.6
30
-
36
fADC = 30 MHz,
-
-
1764
17
kHz
1/fADC
V
(2)
12-bit resolution
fTRIG
External trigger frequency
Conversion voltage range(3)
-
-
0 (VSSA or VREF-
tied to ground)
VAIN
-
-
VREF+
See Equation 1 for
(2)
RAIN
External input impedance
Sampling switch resistance
-
-
-
-
-
50
6
kΩ
kΩ
pF
details
(2)(4)
RADC
-
-
Internal sample and hold
capacitor
(2)
CADC
4
7
f
f
ADC = 30 MHz
-
-
-
0.100
3(5)
0.067
2(5)
16
µs
1/fADC
µs
Injection trigger conversion
latency
(2)
tlat
-
-
ADC = 30 MHz
-
-
-
Regular trigger conversion
latency
(2)
tlatr
-
-
1/fADC
µs
fADC = 30 MHz
0.100
-
(2)
tS
Sampling time
Power-up time
-
-
3
-
-
480
3
1/fADC
µs
(2)
tSTAB
2
fADC = 30 MHz
12-bit resolution
0.50
0.43
0.37
0.30
-
-
-
-
16.40
16.34
16.27
16.20
µs
µs
f
ADC = 30 MHz
10-bit resolution
ADC = 30 MHz
8-bit resolution
ADC = 30 MHz
6-bit resolution
Total conversion time (including
sampling time)
f
(2)
tCONV
µs
f
µs
9 to 492 (tS for sampling +n-bit resolution for successive
approximation)
1/fADC
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Symbol
Electrical characteristics
Table 71. ADC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
12-bit resolution
Single ADC
-
-
2
Msps
12-bit resolution
Sampling rate
-
-
3.75
Msps
Interleave Dual ADC
mode
(2)
fS
(fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
-
-
-
-
6
Msps
µA
Interleave Triple ADC
mode
ADC VREF DC current
consumption in conversion
mode
(2)
IVREF+
-
-
300
1.6
500
1.8
ADC VDDA DC current
consumption in conversion
mode
(2)
IVDDA
mA
1. VDDA minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
2. Guaranteed by characterization, not tested in production.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA
.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 71.
Equation 1: R
max formula
AIN
(k – 0.5)
RAIN = ---------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
(1)
Table 72. ADC accuracy at f
= 18 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(2)
Unit
ET
Total unadjusted error
±3
±4
f
ADC =18 MHz
EO
EG
ED
EL
Offset error
±2
±1
±1
±2
±3
±3
±2
±3
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA −VREF < 1.2 V
LSB
Gain error
Differential linearity error
Integral linearity error
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization, not tested in production.
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Electrical characteristics
Symbol
STM32F412xE/G
(1)
Table 73. ADC accuracy at f
= 30 MHz
ADC
Parameter
Test conditions
Typ
Max(2)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±2
±5
±2.5
±4
f
ADC = 30 MHz,
±1.5
±1.5
±1
RAIN < 10 kΩ,
Gain error
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA −VREF < 1.2 V
LSB
Differential linearity error
Integral linearity error
±2
±1.5
±3
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization, not tested in production.
(1)
Table 74. ADC accuracy at f
= 36 MHz
ADC
Symbol
Parameter
Test conditions
Typ
Max(2)
Unit
ET
Total unadjusted error
±4
±7
f
ADC =36 MHz,
EO
EG
ED
EL
Offset error
±2
±3
±2
±3
±3
±6
±3
±6
V
DDA = 2.4 to 3.6 V,
LSB
Gain error
VREF = 1.7 to 3.6 V
Differential linearity error
Integral linearity error
VDDA −VREF < 1.2 V
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization, not tested in production.
(1)
Table 75. ADC dynamic accuracy at f
Parameter
= 18 MHz - limited test conditions
ADC
Symbol
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to-noise and distortion ratio
Signal-to-noise ratio
10.3
64
64
-
10.4
64.2
65
-
-
bits
fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 kHz
Temperature = 25 °C
-
dB
THD
Total harmonic distortion
-72
-67
1. Guaranteed by characterization, not tested in production.
(1)
Table 76. ADC dynamic accuracy at f
= 36 MHz - limited test conditions
ADC
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to noise and distortion ratio
Signal-to noise ratio
10.6
66
64
-
10.8
67
-
-
bits
fADC = 36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 kHz
Temperature = 25 °C
68
-
dB
THD
Total harmonic distortion
-72
-70
1. Guaranteed by characterization, not tested in production.
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Electrical characteristics
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
Section 6.3.16 does not affect the ADC accuracy.
and ΣI
in
INJ(PIN)
INJ(PIN)
Figure 46. ADC accuracy characteristics
6
6
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1. See also Table 73.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
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STM32F412xE/G
Figure 47. Typical connection diagram using the ADC
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1. Refer to Table 71 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
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Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 48 or Figure 49,
depending on whether V is connected to V or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 48. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
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1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA
.
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161
Electrical characteristics
STM32F412xE/G
Figure 49. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
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1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA
.
6.3.21
Temperature sensor characteristics
Table 77. Temperature sensor characteristics
Symbol
Parameter
Min
Typ Max
Unit
(1)
TL
VSENSE linearity with temperature
-
-
1
2.5
0.76
6
2
°C
mV/°C
V
Avg_Slope(1) Average slope
-
(1)
V25
Voltage at 25 °C
Startup time
-
-
10
-
(2)
tSTART
-
µs
(2)
TS_temp
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
µs
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
Table 78. Temperature sensor calibration values
Parameter
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
Symbol
Memory address
0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL1
TS_CAL2
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6.3.22
V
monitoring characteristics
BAT
Table 79. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
50
4
-
-
KΩ
Ratio on VBAT measurement
Error on Q
Er(1)
–1
-
+1
%
ADC sampling time when reading the VBAT
1 mV accuracy
(2)(2)
TS_vbat
5
-
-
µs
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.23
Embedded reference voltage
The parameters given in Table 80 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 15.
DD
Table 80. Embedded internal reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Max
Unit
Typ
Internal reference voltage
–40 °C < TA < +105 °C 1.18 1.21
1.24
V
ADC sampling time when reading the
internal reference voltage
(1)
TS_vrefint
-
10
-
-
-
µs
Internal reference voltage spread over the
temperature range
(2)
VRERINT_s
VDD = 3V 10mV
3
5
mV
(2)
TCoeff
Temperature coefficient
Startup time
-
-
-
-
30
6
50
10
ppm/°C
µs
(2)
tSTART
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production
Table 81. Internal reference voltage calibration values
Symbol
Parameter
Memory address
Raw data acquired at temperature of
30 °C VDDA = 3.3 V
VREFIN_CAL
0x1FFF 7A2A - 0x1FFF 7A2B
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6.3.24
DFSDM characteristics
Unless otherwise specified, the parameters given in Table 82 for DFSDM are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
APB2
DD
conditions summarized in Table 15: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM).
(1)
Table 82. DFSDM characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDFSDMCLK DFSDM clock
-
-
-
fSYSCLK
MHz
fCKIN
(1/TCKIN
Input clock
frequency
20
SPI mode (SITP[1:0] = 01)
-
-
-
-
-
)
(fDFSDMCLK/4)
Output clock
frequency
fCKOUT
20
75
MHz
%
Output clock
DuCyCKOUT frequency
duty cycle
-
30
50
Input clock
twh(CKIN)
SPI mode (SITP[1:0] = 01),
(SPICKSEL[1:0] = 0)
high and low External clock mode
TCKIN/2-0.5 TCKIN/2
-
-
-
twl(CKIN)
time
SPI mode (SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
Data input
setup time
tsu
1
1
-
-
ns
SPI mode (SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
Data input
hold time
th
Manchester
data period
(recovered
Manchester mode (SITP[1:0]
= 10 or 11),
Internal clock mode
(CKOUT
DIV+1) ₓ
TDFSDMCLK
(2 ₓ CKOUTDIV)
ₓ TDFSDMCLK
TManchester
-
clock period) (SPICKSEL[1:0] ≠ 0)
1. Data based on characterization results, not tested in production.
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Figure 16: DFSDM timing diagram
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6.3.25
FSMC characteristics
Unless otherwise specified, the parameters given in Table 83 to Table 90 for the FSMC
interface are derived from tests performed under the ambient temperature, f frequency
HCLK
and V supply voltage conditions summarized in Table 14, with the following configuration:
DD
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitance load C = 30 pF
Measurement points are done at CMOS levels: 0.5.V
DD
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Electrical characteristics
STM32F412xE/G
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 50 through Figure 53 represent asynchronous waveforms and Table 83 through
Table 90 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
In all timing tables, the T
is the HCLK clock period.
HCLK
Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
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Electrical characteristics
Table 83. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
(1)(2)
read timings
Parameter
FSMC_NE low time
Symbol
Min
Max
Unit
tw(NE)
2THCLK – 1 2 THCLK + 0.5
tv(NOE_NE)
tw(NOE)
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
0
1
2THCLK - 1.5
2THCLK
FSMC_NOE high to FSMC_NE high hold
time
th(NE_NOE)
0
-
tv(A_NE)
th(A_NOE)
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NOE high
Data to FSMC_NEx high setup time
Data to FSMC_NOEx high setup time
Data hold time after FSMC_NOE high
Data hold time after FSMC_NEx high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
-
1.5
0
-
tv(BL_NE)
-
0.5
ns
th(BL_NOE)
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
0
-
THCLK - 1
-
THCLK - 1
-
0
0
-
-
-
0
-
THCLK + 0.5
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Table 84. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
(1)(2)
NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
7THCLK - 1 7THCLK + 0.5
tw(NOE)
FSMC_NWE low time
FSMC_NWAIT low time
5THCLK – 1.5
THCLK – 0.5
5THCLK
-
tw(NWAIT)
ns
FSMC_NWAIT valid before FSMC_NEx
high
tsu(NWAIT_NE)
5THCLK -1
-
-
FSMC_NEx hold time after FSMC_NWAIT
invalid
th(NE_NWAIT)
4THCLK + 1
1. CL = 30 pF.
2. Based on characterization, not tested in production.
DocID028087 Rev 4
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Electrical characteristics
STM32F412xE/G
Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
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1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
(1)(2)
Table 85. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
tw(NE)
Parameter
Min
Max
Unit
FSMC_NE low time
3 THCLK - 1 3 THCLK +0.5
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
THCLK + 0.5 THCLK + 0.5
THCLK – 1.5
THCLK+ 1
FSMC_NWE high to FSMC_NE high hold time THCLK - 1
-
FSMC_NEx low to FSMC_A valid
-
0.5
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
Data to FSMC_NEx low to Data valid
THCLK - 0.5
-
ns
-
1
THCLK - 1
-
-
THCLK + 2
th(Data_NWE) Data hold time after FSMC_NWE high
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
THCLK + 0.5
-
-
-
1
tw(NADV)
FSMC_NADV low time
THCLK+ 0.5
148/193
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STM32F412xE/G
Electrical characteristics
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
(1)(2)
NWAIT timings
Symbol
Parameter
FSMC_NE low time
FSMC_NWE low time
Min
Max
Unit
tw(NE)
8THCLK - 1
8THCLK + 0.5
tw(NWE)
6THCLK + 0.5 6THCLK + 1
ns
tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6THCLK + 0.5
-
-
FSMC_NEx hold time after FSMC_NWAIT
invalid
th(NE_NWAIT)
4THCLK + 1
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms
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Electrical characteristics
STM32F412xE/G
(1)(2)
Table 87. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
FSMC_NE low time
Min
Max
Unit
tw(NE)
tv(NOE_NE)
ttw(NOE)
3THCLK – 1 3THCLK + 0.5
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
2THCLK
2THCLK + 1
THCLK
THCLK – 1.5
FSMC_NOE high to FSMC_NE high hold
time
th(NE_NOE)
0
-
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
-
0.5
1
0
THCLK – 0.5 THCLK + 0.5
FSMC_AD(address) valid hold time after
FSMC_NADV high)
ns
th(AD_NADV)
0
-
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FSMC_NOE high
FSMC_BL time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
Data to FSMC_NEx high setup time
THCLK – 0.5
-
0
-
-
0.5
tsu(Data_NE)
THCLK - 2
-
-
tsu(Data_NOE) Data to FSMC_NOE high setup time
THCLK - 2
th(Data_NE)
th(Data_NOE)
Data hold time after FSMC_NEx high
Data hold time after FSMC_NOE high
0
0
-
-
1. CL = 30 pF.
2. Based on characterization, not tested in production.
(1)(2)
Table 88. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
8THCLK - 1
8THCLK + 0.5
tw(NOE)
FSMC_NWE low time
5THCLK
5THCLK + 0.5
-
ns
FSMC_NWAIT valid before FSMC_NEx
high
tsu(NWAIT_NE)
5THCLK - 1
FSMC_NEx hold time after
FSMC_NWAIT invalid
th(NE_NWAIT)
4THCLK + 1
-
1. CL = 30 pF.
2. Based on characterization, not tested in production.
150/193
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Electrical characteristics
Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms
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Electrical characteristics
STM32F412xE/G
(1)(2)
Table 89. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
FSMC_NE low time
Min
4THCLK - 1 4THCLK+0.5
THCLK THCLK + 1
2THCLK - 1 2THCLK + 0.5
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
th(NE_NWE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FSMC_NWE high to FSMC_NE high hold time THCLK - 1.5
-
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
-
2
1
0
THCLK – 0.5 THCLK+ 0.5
ns
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
th(AD_NADV)
THCLK
-
th(A_NWE)
th(BL_NWE)
Address hold time after FSMC_NWE high
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_NADV high to Data valid
THCLK- 1.5
-
THCLK
-
tv(BL_NE)
-
1.5
tv(Data_NADV)
th(Data_NWE)
1. CL = 30 pF.
-
THCLK + 2
-
Data hold time after FSMC_NWE high
THCLK + 0.5
2. Based on characterization, not tested in production.
(1)(2)
Table 90. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
FSMC_NWE low time
9THCLK - 1 9THCLK + 0.5
7THCLK - 1 7THCLK + 0.5
tw(NWE)
ns
tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6THCLK -1
-
-
FSMC_NEx hold time after FSMC_NWAIT
th(NE_NWAIT)
4THCLK + 1
invalid
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Synchronous waveforms and timings
Figure 54 through Figure 57 represent synchronous waveforms and Table 91 through
Table 94 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
•
•
•
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
152/193
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STM32F412xE/G
Electrical characteristics
In all timing tables, the T
is the HCLK clock period (with maximum
HCLK
FSMC_CLK = 90 MHz).
Figure 54. Synchronous multiplexed NOR/PSRAM read timings
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DocID028087 Rev 4
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Electrical characteristics
STM32F412xE/G
(1)(2)
Table 91. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
Min
Max
Unit
tw(CLK)
2THCLK - 0.5
-
-
1
-
td(CLKL-NExL)
td(CLKH_NExH)
FSMC_CLK high to FSMC_NEx high (x= 0…2) THCLK + 0.5
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
-
0
-
1
-
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
2
FSMC_CLK high to FSMC_Ax invalid
(x=16…25)
THCLK
-
FSMC_CLK low to FSMC_NOE low
-
1.5
-
ns
td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high
THCLK
td(CLKL-ADV)
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
-
2.5
-
0
FSMC_A/D[15:0] valid data before FSMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
1
2
-
-
FSMC_A/D[15:0] valid data after FSMC_CLK
high
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
2
2
-
-
1. CL = 30 pF.
2. Based on characterization, not tested in production.
154/193
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STM32F412xE/G
Electrical characteristics
Figure 55. Synchronous multiplexed PSRAM write timings
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DocID028087 Rev 4
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Electrical characteristics
STM32F412xE/G
(1)(2)
Table 92. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period, VDD range= 2.7 to 3.6 V
2THCLK - 0.5
-
1
-
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x= 0...2)
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2)
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
-
THCLK + 0.5
-
1
-
0
td(CLKL-AV)
td(CLKH-AIV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
-
2
-
THCLK
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
t(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high
td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid
td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low
td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low
-
1.5
-
ns
THCLK + 0.5
-
2.5
-
0
-
4
3
-
-
td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
THCLK
2
2
-
-
1. CL = 30 pF.
2. Based on characterization, not tested in production.
156/193
DocID028087 Rev 4
STM32F412xE/G
Electrical characteristics
Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings
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Table 93. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
2THCLK – 0.5
-
1
-
t(CLKL-NExL)
-
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2)
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
THCLK +0.5
-
1
-
0
td(CLKL-AV)
td(CLKH-AIV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
-
2
-
THCLK
-
ns
td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low
td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high
1.5
-
THCLK
FSMC_D[15:0] valid data before FSMC_CLK
high
tsu(DV-CLKH)
th(CLKH-DV)
1
-
FSMC_D[15:0] valid data after FSMC_CLK high
2
2
2
-
-
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
-
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161
Electrical characteristics
STM32F412xE/G
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 57. Synchronous non-multiplexed PSRAM write timings
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Electrical characteristics
(1)(2)
Table 94. Synchronous non-multiplexed PSRAM write timings
Symbol
tw(CLK)
Parameter
Min
Max
Unit
FSMC_CLK period
2THCLK – 0.5
-
1
-
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2)
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
-
THCLK + 0.5
-
1
-
0
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
-
2
-
td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x=16…25)
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high
td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low
td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low
THCLK
ns
-
1.5
-
THCLK + 0.5
-
-
4
3
-
td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high
THCLK
tsu(NWAIT-
FSMC_NWAIT valid before FSMC_CLK high
2
2
-
-
CLKH)
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
1. CL = 30 pF.
2. Based on characterization, not tested in production.
6.3.26
SD/SDIO MMC/eMMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 95 for the SDIO are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLK2
DD
conditions summarized in Table 15, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
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Electrical characteristics
STM32F412xE/G
Figure 58. SDIO high-speed mode
T
T
R
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T
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T
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(1)(2)
Table 95. Dynamic characteristics: SD / MMC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
0
-
-
-
50
8/3
-
MHz
-
-
fpp =50MHz
fpp =50MHz
9.5
8.5
10.5
9.5
ns
ns
ns
Clock high time
-
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =50MHz
fpp =50MHz
4
-
-
-
-
2.5
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =50MHz
fpp =50MHz
-
13
-
13.5
-
11
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Electrical characteristics
(1)(2)
Table 95. Dynamic characteristics: SD / MMC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D inputs (referenced to CK) in SD default mode
2.5
2.5
-
-
-
-
tISUD
tIHD
Input setup time SD
Input hold time SD
fpp =25MHz
fpp =25MHz
ns
CMD, D outputs (referenced to CK) in SD default mode
-
1.5
-
2
-
tOVD
tOHD
Output valid default time SD
Output hold default time SD
fpp =25 MHz
fpp =25 MHz
ns
0.5
1. Guaranteed by characterization results, not tested in production.
2. VDD = 2.7 to 3.6 V.
(1)(2)
Table 96. Dynamic characteristics: eMMC characteristics V = 1.7 V to 1.9 V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
0
-
-
-
50
8/3
-
MHz
-
fpp =50MHz
fpp =50MHz
9.5
8.5
10.5
9.5
ns
ns
ns
Clock high time
-
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =50MHz
fpp =50MHz
3.5
4
-
-
-
-
CMD, D outputs (referenced to CK) in eMMC mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =50MHz
fpp =50MHz
-
13.5
-
15
-
12
1. Guaranteed by characterization results, not tested in production.
2. CLOAD = 20 pF.
6.3.27
RTC characteristics
Table 97. RTC characteristics
Symbol
Parameter
Conditions
Min
Max
Any read/write operation
from/to an RTC register
-
fPCLK1/RTCCLK frequency ratio
4
-
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Package information
STM32F412xE/G
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
7.1
WLCSP64 package information
Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package outline
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1. Drawing is not to scale.
162/193
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Package information
Table 98. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
0.555
0.170
0.380
0.025
0.250
3.623
3.651
0.400
2.800
2.800
0.4115
0.4255
-
Max
Min
Typ
0.0219
0.0067
0.0150
0.0010
0.0098
0.1426
0.1437
0.0157
0.1102
0.1102
0.0162
0.0168
-
Max
A
A1
A2
A3(2)
b(3)
D
0.525
0.585
0.0207
0.0230
-
-
-
-
-
-
-
-
-
-
-
-
0.220
0.280
3.658
3.686
-
0.0087
0.0110
0.1440
0.1451
-
3.588
0.1413
E
3.616
0.1424
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
-
-
e2
-
-
F
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.100
0.100
0.100
0.050
0.050
0.0039
0.0039
0.0039
0.0020
0.0020
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 61. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale
recommended footprint
'SDG
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Table 99. WLCSP64 recommended PCB design rules (0.4 mm pitch)
Dimension
Recommended values
Pitch
Dpad
0.4 mm
0.225 mm
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Package information
STM32F412xE/G
Table 99. WLCSP64 recommended PCB design rules (0.4 mm pitch) (continued)
Dimension
Recommended values
0.290 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
Device marking for WLCSP64
The following figure gives an example of topside marking and pin 1 position identifier
location.
Figure 62. WLCSP64 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Package information
7.2
UFQFPN48 package information
Figure 63. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
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1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
Table 100. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
D
0.500
0.000
6.900
6.900
5.500
0.550
0.020
7.000
7.000
5.600
0.600
0.050
7.100
7.100
5.700
0.0197
0.0000
0.2717
0.2717
0.2165
0.0217
0.0008
0.2756
0.2756
0.2205
0.0236
0.0020
0.2795
0.2795
0.2244
E
D2
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Package information
STM32F412xE/G
Table 100. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
E2
L
5.500
5.600
0.400
0.152
0.250
0.500
-
5.700
0.500
-
0.2165
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.2244
0.0197
-
0.300
0.0118
T
-
-
b
0.200
0.300
-
0.0079
0.0118
-
e
-
-
-
-
ddd
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 64. UFQFPN48 recommended footprint
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1. Dimensions are in millimeters.
166/193
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Package information
Device marking for UFQFPN48
The following figure gives an example of topside marking and pin 1 position identifier
location.
Figure 65. UFQFPN48 marking example (package top view)
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qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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190
Package information
STM32F412xE/G
7.3
LQFP64 package information
Figure 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
6($7,1*ꢉ3/$1(
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1. Drawing is not to scale.
168/193
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Package information
Table 101. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
millimeters
inches(1)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
12.000
10.000
7.500
12.000
10.000
7.500
0.500
3.5°
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
3.5°
-
D1
D3
E
-
-
-
-
-
-
-
-
-
-
-
-
E1
E3
e
-
-
-
-
-
-
-
-
-
-
7°
-
-
7°
Κ
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID028087 Rev 4
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Package information
STM32F412xE/G
Figure 67. LQFP64 recommended footprint
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1. Dimensions are in millimeters.
Device marking for LQFP64
The following figure gives an example of topside marking and pin 1 position identifier
location.
Figure 68. LQFP64 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Package information
7.4
LQFP100 package information
Figure 69. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
3%!4).' 0,!.%
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1. Drawing is not to scale. Dimensions are in millimeters.
Table 102. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
0.050
1.350
0.170
0.090
15.800
13.800
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
0.6299
0.5512
D1
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Package information
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Table 102. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data (continued)
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
D3
E
-
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
-
16.200
14.200
-
-
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
-
0.6378
0.5591
-
15.800
0.6220
E1
E3
e
13.800
0.5433
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
-
0.0°
-
7.0°
0.080
7.0°
0.0031
ccc
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 70. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
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1. Dimensions are in millimeters.
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Package information
Device marking for LQFP100
The following figure gives an example of topside marking and pin 1 position identifier
location.
Figure 71. LQFP100 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Package information
STM32F412xE/G
7.5
LQFP144 package information
Figure 72. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline
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1. Drawing is not to scale.
174/193
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Package information
Table 103. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID028087 Rev 4
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190
Package information
STM32F412xE/G
Figure 73. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint
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1. Dimensions are expressed in millimeters.
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Package information
Device marking for LQFP144
The following figure gives an example of topside marking and pin 1 position identifier
location.
Figure 74. LQFP144 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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190
Package information
STM32F412xE/G
7.6
UFBGA100 package information
Figure 75. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline
= 6HDWLQJꢉSODQH
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1. Drawing is not to scale.
Table 104. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.250
7.000
5.500
7.000
5.500
0.500
0.750
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0098
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
0.0236
0.0043
0.0197
-
0.270
0.200
6.950
5.450
6.950
5.450
-
0.370
0.300
7.050
5.550
7.050
5.550
-
0.0106
0.0079
0.2736
0.2146
0.2736
0.2146
-
0.0146
0.0118
0.2776
0.2185
0.2776
0.2185
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
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STM32F412xE/G
Package information
Table 104. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.100
0.150
0.050
-
-
-
-
-
-
0.0039
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint
'SDG
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Table 105. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.280 mm
Between 0.100 mm and 0.125 mm
DocID028087 Rev 4
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190
Package information
STM32F412xE/G
Device marking for UFBGA100
The following figure gives an example of topside marking and ball 1 position identifier
location.
Figure 77. UFBGA100 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Package information
7.7
UFBGA144 package information
Figure 78. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline
& 6HDWLQJꢉSODQH
GGG =
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1. Drawing is not to scale.
Table 106. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
0.050
0.270
0.360
9.950
8.750
9.950
8.750
0.750
0.530
0.080
0.450
0.080
0.320
0.400
10.000
8.800
10.000
8.800
0.800
0.600
0.110
0.500
0.110
0.370
0.440
10.050
8.850
10.050
8.850
0.850
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2362
0.2756
0.2362
0.0197
0.0236
0.0043
0.0197
-
0.0106
0.0091
0.2736
0.2343
0.2736
0.2343
-
0.0146
0.0130
0.2776
0.2382
0.2776
0.2382
-
D
D1
E
E1
e
DocID028087 Rev 4
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190
Package information
STM32F412xE/G
Table 106. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
F
0.550
0.600
0.650
0.080
0.150
0.080
0.0177
0.0197
0.0217
0.0039
0.0059
0.0020
ddd
eee
fff
-
-
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array recommended footprint
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Table 107. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.80 mm
0.400 mm
0.550 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Note:
Non solder mask defined (NSMD) pads are recommended.
4 to 6 mils solder paste screen printing process.
Stencil opening is 0.400 mm.
Stencil thickness is between 0.100 mm and 0.125 mm.
Pad trace width is 0.120 mm.
182/193
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Package information
Device marking for UFBGA144
The following figure gives an example of topside marking and ball A1 position identifier
location.
Figure 80. UFBGA144 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID028087 Rev 4
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190
Package information
STM32F412xE/G
7.8
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 15: General operating conditions on page 76.
The maximum chip-junction temperature, T max., in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (PD max x Θ )
J
A
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
PD max is the sum of P
max and P max (PD max = P
max + P max),
INT I/O
INT
I/O
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 108. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm
35
43
47
48
57
51
32
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm
Thermal resistance junction-ambient
UFBGA144 - 10 x 10 mm / 0.8 mm pitch
Θ
°C/W
JA
Thermal resistance junction-ambient
UFBGA100 - 7 x 7 mm
Thermal resistance junction-ambient
WLCSP64 - 3.623 x 3.651 mm
Thermal resistance junction-ambient
UFQFPN48 - 7 x 7 mm
7.8.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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STM32F412xE/G
Part numbering
8
Part numbering
Table 109. Ordering information scheme
STM32 F 412 C E T
Example:
6
TR
Device family
®
STM32 = ARM -based 32-bit microcontroller
Product type
F = General-purpose
Device subfamily
412 = 412 line
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
Z = 144 pins
Flash memory size
E = 512 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
Package
H = UFBGA 7 x 7 mm
J = UFBGA 10 x 10 mm
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
DocID028087 Rev 4
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190
Recommendations when using the internal reset OFF
STM32F412xE/G
Appendix A Recommendations when using the internal
reset OFF
When the internal reset is OFF, the following integrated features are no longer supported:
•
•
•
•
The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled. By default BOR is OFF.
The embedded programmable voltage detector (PVD) is disabled.
V
functionality is no more available and VBAT pin should be connected to V
.
BAT
DD
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Application block diagrams
Appendix B Application block diagrams
B.1
USB OTG full speed (FS) interface solutions
Figure 81. USB controller configured as peripheral-only and used in Full speed mode
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1. External voltage regulator only needed when building a VBUS powered device.
Figure 82. USB peripheral-only Full speed mode with direct connection
for VBUS sense
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1. External voltage regulator only needed when building a VBUS powered device.
DocID028087 Rev 4
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190
Application block diagrams
STM32F412xE/G
Figure 83. USB peripheral-only Full speed mode, VBUS detection using GPIO
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1. External voltage regulator only needed when building a VBUS powered device.
Figure 84. USB controller configured as host-only and used in full speed mode
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1. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
188/193
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STM32F412xE/G
Application block diagrams
Figure 85. USB controller configured in dual mode and used in full speed mode
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1. External voltage regulator only needed when building a VBUS powered device.
2. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
3. The ID pin is required in dual role only.
B.2
Sensor Hub application example
Figure 86. Sensor Hub application example
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DocID028087 Rev 4
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190
Application block diagrams
STM32F412xE/G
B.3
Display application example
Figure 87. Display application example
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Note:
16 bit displays interfaces can be addressed with 100 and 144 pins packages.
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Revision history
Revision history
Table 110. Document revision history
Changes
Date
Revision
10-Nov-2015
1
Initial release.
Added
– Table 3: Embedded bootloader interfaces
– Figure 3: Compatible board design for LQFP144 package
– Figure 62: WLCSP64 marking example (package top view)
– Figure 77: UFBGA100 marking example (package top view)
Updated
– Section 3.17: Power supply schemes
– Section 3.23: Timers and watchdogs
– Section 3.32: Universal serial bus on-the-go full-speed (USB_OTG_FS)
– Figure 1: Compatible board design for LQFP100 package
– Figure 2: Compatible board design for LQFP64 package
– Figure 14: STM32F412xE/G LQFP100 pinout
– Figure 16: STM32F412xE/G UFBGA100 pinout
– Figure 17: STM32F412xE/G UFBGA144 pinout
– Figure 20: Input voltage measurement
01-Feb-2016
2
– Figure 80: UFBGA144 marking example (package top view)
– Table 2: STM32F412xE/G features and peripheral counts
– Table 9: STM32F412xE/G pin definition
– Table 12: Voltage characteristics
– Table 13: Current characteristics
– Table 15: General operating conditions
– Table 36: Peripheral current consumption
– Table 51: EMS characteristics for LQFP144 package
– Table 63: FMPI2C characteristics
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Revision history
STM32F412xE/G
Table 110. Document revision history
Changes
Date
Revision
Added:
– Figure 82: USB peripheral-only Full speed mode with direct connection for VBUS
sense
– Figure 83: USB peripheral-only Full speed mode, VBUS detection using GPIO
Updated:
– Figure 15: STM32F412xE/G LQFP144 pinout
– Section 6.3.6: Supply current characteristics
– Table 9: STM32F412xE/G pin definition
25-Mar-2016
3
– Table 10: STM32F412xE/G alternate functions
– Table 11: STM32F412xE/G register boundary addresses
– Table 15: General operating conditions
– Table 36: Peripheral current consumption
– Table 96: Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V
Updated:
– Section 3.23.2: General-purpose timers (TIMx)
– Table 21: Typical and maximum current consumption, code with data processing
(ART accelerator disabled) running from SRAM - VDD = 1.7 V
– Table 22: Typical and maximum current consumption, code with data processing
(ART accelerator disabled) running from SRAM - VDD = 3.6 V
– Table 23: Typical and maximum current consumption in run mode, code with data
processing (ART accelerator enabled except prefetch) running from Flash
memory- VDD = 1.7 V
– Table 24: Typical and maximum current consumption in run mode, code with data
processing (ART accelerator enabled except prefetch) running from Flash
memory - VDD = 3.6 V
27-May-2016
4
– Table 25: Typical and maximum current consumption in run mode, code with data
processing (ART accelerator disabled) running from Flash memory - VDD = 3.6 V
– Table 26: Typical and maximum current consumption in run mode, code with data
processing (ART accelerator disabled) running from Flash memory - VDD = 1.7 V
– Table 27: Typical and maximum current consumption in run mode, code with data
processing (ART accelerator enabled with prefetch) running from Flash memory -
VDD = 3.6 V
– Table 28: Typical and maximum current consumption in Sleep mode - VDD = 3.6 V
– Table 29: Typical and maximum current consumption in Sleep mode - VDD = 1.7 V
– Table 37: Low-power mode wakeup timings(1)
– Figure 38: I2C bus AC waveforms and measurement circuit
– Figure 39: FMPI2C timing diagram and measurement circuit
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