STM32F417VE_技术文档

STM32F415xx

STM32F417xx

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM,

crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

Datasheet - production data

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input

FBGA

• Debug mode

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

LQFP176 (24 × 24 mm)

– Serial wire debug (SWD) & JTAG

UFBGA176

interfaces

WLCSP90

(10 × 10 mm)

– Cortex-M4 Embedded Trace Macrocell™

• Up to 140 I/O ports with interrupt capability

– Up to 136 fast I/Os up to 84 MHz

– Up to 138 5 V-tolerant I/Os

Features

• Core: ARM 32-bit Cortex™-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 168 MHz,

memory protection unit, 210 DMIPS/

1.25 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

• Up to 15 communication interfaces

2

– Up to 3 × I C interfaces (SMBus/PMBus)

– Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO

7816 interface, LIN, IrDA, modem control)

– Up to 3 SPIs (42 Mbits/s), 2 with muxed

2

full-duplex I S to achieve audio class

accuracy via internal audio PLL or external

clock

• Memories

– Up to 1 Mbyte of Flash memory

– 2 × CAN interfaces (2.0B Active)

– SDIO interface

– Up to 192+4 Kbytes of SRAM including 64-

Kbyte of CCM (core coupled memory) data

RAM

– Flexible static memory controller

supporting Compact Flash, SRAM,

PSRAM, NOR and NAND memories

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

• LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 1.8 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

• 8- to 14-bit parallel camera interface up to

– 4-to-26 MHz crystal oscillator

54 Mbytes/s

– Internal 16 MHz factory-trimmed RC (1%

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

Low power

– Sleep, Stop and Standby modes

• Cryptographic acceleration: hardware

acceleration for AES 128, 192, 256, Triple

DES, HASH (MD5, SHA-1), and HMAC

• True random number generator

• CRC calculation unit

• 96-bit unique ID

•

– V

supply for RTC, 20×32 bit backup

BAT

• RTC: subsecond accuracy, hardware calendar

registers + optional 4 KB backup SRAM

• 3×12-bit, 2.4 MSPS A/D converters: up to 24

channels and 7.2 MSPS in triple interleaved

mode

Table 1. Device summary

Reference

Part number

• 2×12-bit D/A converters

STM32F415RG, STM32F415VG, STM32F415ZG,

STM32F415OG

STM32F415xx

• General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

STM32F417VG, STM32F417IG, STM32F417ZG,

STM32F417VE, STM32F417ZE, STM32F417IE

STM32F417xx

• Up to 17 timers: up to twelve 16-bit and two 32-

bit timers up to 168 MHz, each with up to 4

June 2013

DocID022063 Rev 4

1/186

This is information on a product in full production.

www.st.com

1

Contents

STM32F415xx, STM32F417xx

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1

2.2

Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

®

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

ARM Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . 19

Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 19

Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 20

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 22

2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 22

2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 22

2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 29

2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 29

2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.2.20

V

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

BAT

2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 33

2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 35

2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 35

2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 36

2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 36

2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.33 Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.34 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.35 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.36 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.37 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.38 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.39 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.40 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3

4

5

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.2

5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Operating conditions at power-up / power-down (regulator ON) . . . . . . 81

Operating conditions at power-up / power-down (regulator OFF) . . . . . 81

Embedded reset and power control block characteristics . . . . . . . . . . . 81

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

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5.3.11

PLL spread spectrum clock generation (SSCG) characteristics . . . . . 103

5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 109

5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

5.3.22

V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

BAT

5.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 156

5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 157

5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6

7

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

6.1

6.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

A.1

A.2

A.3

USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 172

USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 174

Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

8

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F415xx and STM32F417xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13

Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 29

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

STM32F41x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

STM32F41x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 80

VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 81

Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 81

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 82

Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 84

Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 88

Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 89

Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 89

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Typical and maximum current consumptions in V

mode. . . . . . . . . . . . . . . . . . . . . . . . 90

BAT

Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

LSE

HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Flash memory programming with V

PP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

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List of tables

STM32F415xx, STM32F417xx

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

Table 69.

Table 70.

Table 71.

Table 72.

Table 73.

Table 74.

Table 75.

Table 76.

Table 77.

Table 78.

Table 79.

Table 80.

Table 81.

Table 82.

Table 83.

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 116

Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 117

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

SCL frequency (f

= 42 MHz.,V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCLK1

DD

SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Ethernet DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Dynamic characteristics: Ehternet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 128

Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 129

Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 129

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

ADC accuracy at f

= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

ADC

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

BAT

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 139

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 140

Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 146

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Switching characteristics for PC Card/CF read and write cycles

in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Switching characteristics for PC Card/CF read and write cycles

Table 84.

in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 156

DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 160

LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 161

LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 163

LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 165

UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm

Table 85.

Table 86.

Table 87.

Table 88.

Table 89.

Table 90.

Table 91.

Table 92.

Table 93.

Table 94.

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 168

Table 95.

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Table 96.

Table 97.

Table 98.

Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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List of figures

STM32F415xx, STM32F417xx

List of figures

Figure 1.

Figure 2.

Compatible board design between STM32F10xx/STM32F4xx for LQFP64. . . . . . . . . . . . 15

Compatible board design STM32F10xx/STM32F2xx/STM32F4xx

for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx

for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Compatible board design between STM32F2xx and STM32F4xx

Figure 3.

Figure 4.

for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

STM32F41x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24

PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10. Startup in regulator OFF mode: slow V slope

DD

- power-down reset risen after V

/V

stabilization . . . . . . . . . . . . . . . . . . . . . . . . 28

CAP_1 CAP_2

Figure 11. Startup in regulator OFF mode: fast V slope

DD

- power-down reset risen before V

/V

stabilization . . . . . . . . . . . . . . . . . . . . . . 28

CAP_1 CAP_2

Figure 12. STM32F41x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 13. STM32F41x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. STM32F41x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 15. STM32F41x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 16. STM32F41x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17. STM32F41x WLCSP90 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 18. STM32F41x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 19. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 21. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 23. External capacitor C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

EXT

Figure 24. Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 86

Figure 25. Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 86

Figure 26. Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 87

Figure 27. Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 87

Figure 28. Typical V

Figure 29. Typical V

current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 90

current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 91

BAT

Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 34. ACC versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

LSI

Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 37. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 38. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

2

Figure 39. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 43. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

(1)

Figure 44. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 45. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 125

Figure 46. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 47. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 48. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 49. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 52. Power supply and reference decoupling (V

Figure 53. Power supply and reference decoupling (V

not connected to V

). . . . . . . . . . . . . 134

). . . . . . . . . . . . . . . . 134

REF+

DDA

connected to V

REF+

DDA

Figure 54. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 139

Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 140

Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 63. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 149

Figure 64. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . 149

Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 151

Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 152

Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 71. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 155

Figure 72. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 155

Figure 73. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 74. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 75. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . 160

Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 161

Figure 78. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 163

Figure 80. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 165

Figure 82. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm,

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 168

Figure 85. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 86. USB controller configured as peripheral-only and used

in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 87. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 172

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Figure 88. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 173

Figure 89. USB controller configured as peripheral, host, or dual-mode

and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 90. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 91. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 92. RMII with a 25 MHz crystal and PHY with PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

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Introduction

1

Introduction

This datasheet provides the description of the STM32F415xx and STM32F417xx lines of

microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please

refer to Section 2.1: Full compatibility throughout the family.

The STM32F415xx and STM32F417xx datasheet should be read in conjunction with the

STM32F4xx reference manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M4 core, please refer to the Cortex™-M4 programming

manual (PM0214) available from www.st.com.

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Description

STM32F415xx, STM32F417xx

2

Description

®

The STM32F415xx and STM32F417xx family is based on the high-performance ARM

Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4

core features a Floating point unit (FPU) single precision which supports all ARM single-

precision data-processing instructions and data types. It also implements a full set of DSP

instructions and a memory protection unit (MPU) which enhances application security. The

Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document.

The STM32F415xx and STM32F417xx family incorporates high-speed embedded

memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of

backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two

APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose

16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.

a true random number generator (RNG), and a cryptographic acceleration cell. They also

feature standard and advanced communication interfaces.

2

•

Up to three I Cs

2

Three SPIs, two I Ss full duplex. To achieve audio class accuracy, the I2S peripherals

can be clocked via a dedicated internal audio PLL or via an external clock to allow

synchronization.

•

Four USARTs plus two UARTs

An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the

ULPI),

•

Two CANs

An SDIO/MMC interface

Ethernet and the camera interface available on STM32F417xx devices only.

New advanced peripherals include an SDIO, an enhanced flexible static memory control

(FSMC) interface (for devices offered in packages of 100 pins and more), a camera

interface for CMOS sensors and a cryptographic acceleration cell. Refer to Table 2:

STM32F415xx and STM32F417xx: features and peripheral counts for the list of peripherals

available on each part number.

The STM32F415xx and STM32F417xx family operates in the –40 to +105 °C temperature

range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the

device operates in the 0 to 70 °C temperature range using an external power supply

supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving

mode allows the design of low-power applications.

The STM32F415xx and STM32F417xx family offers devices in various packages ranging

from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.

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Description

2.1

Full compatibility throughout the family

The STM32F415xx and STM32F417xx are part of the STM32F4 family. They are fully pin-

to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to

try different memory densities, peripherals, and performances (FPU, higher frequency) for a

greater degree of freedom during the development cycle.

The STM32F415xx and STM32F417xx devices maintain a close compatibility with the

whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The

STM32F415xx and STM32F417xx, however, are not drop-in replacements for the

STM32F10xxx devices: the two families do not have the same power scheme, and so their

power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F41x

family remains simple as only a few pins are impacted.

Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the

STM32F41x, STM32F2xxx, and STM32F10xxx families.

Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64

V

SS

V

SS

48

33

31

32

49

47

V

SS

V

SS

0 Ω resistor or soldering bridge

present for the STM32F10xx

configuration, not present in the

STM32F4xx configuration

64

17

1

16

ai18489

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Description

STM32F415xx, STM32F417xx

Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx

for LQFP100 package

V

SS

75

73

51

49

50

76

V

SS

V

SS

0 ΩΩ resistor or soldering bridge

present for the STM32F10xxx

configuration, not present in the

STM32F4xx configuration

99 (V

1

)

SS

100

19 20

26

25

V

SS

V

DD

SS

V

for STM32F10xx

for STM32F4xx

SS

Two 0 Ω resistors connected to:

V

DD

- V

for the STM32F10xx

for the STM32F4xx

SS

ai18488c

- V , V

or NC for the STM32F2xx

SS DD

Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx

for LQFP144 package

V_SS

108

73

71

72

109

106

V_SS

0 Ω resistor or soldering bridge

present for the STM32F10xx

configuration, not present in the

STM32F4xx configuration

Signal from

external power

supply

143 (PDR_ON)

1

30

31

144

37

supervisor

36

V_SS

V_DDV_SS

V_SSfor STM32F10xx

V_DDfor STM32F4xx

Two 0 Ω resistors connected to:

- V_SSfor the STM32F10xx

V_DD

V_SS

- V_SS, V_DDor NC for the STM32F2xx

- V_DDor signal from external power supply supervisor for the STM32F4xx

ai18487d

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Description

Figure 4. Compatible board design between STM32F2xx and STM32F4xx

for LQFP176 and BGA176 packages

132

133

89

88

Signal from external

power supply

supervisor

171 (PDR_ON)

176

1

45

44

V_DDV_SS

Two 0 Ω resistors connected to:

- V_SS, V_DDor NC for the STM32F2xx

- V_DDor signal from external power supply supervisor for the STM32F4xx

MS19919V3

DocID022063 Rev 4

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Description

STM32F415xx, STM32F417xx

2.2

Device overview

Figure 5. STM32F41x block diagram

External memory

controller (FSMC)

SRAM, PSRAM, NOR Flash,

PC Card (ATA), NAND Flash

CLK, NE [3:0], A[23:0],

D[31:0], OEN, WEN,

NBL[3:0], NL, NREG,

NWAIT/IORDY, CD

CCM data RAM 64 KB

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

AHB3

JTAG & SW

ETM

MPU

NVIC

NIORD, IOWR, INT[2:3]

INTN, NIIS16 as AF

TRACECLK

TRACED[3:0]

D-BUS

TDES, AES256

ARM Cortex-M4

168 MHz

FPU

I-BUS

HASH

RNG

Flash

up to

1 MB

S-BUS

DMA/

FIFO

Ethernet MAC

10/100

MII or RMII as AF

MDIO as AF

HSYNC, VSYNC

PUIXCLK, D[13:0]

Camera

interface

SRAM 112 KB

SRAM 16 KB

USB

OTG HS

DMA/

FIFO

DP, DM

ULPI:CK, D[7:0], DIR, STP, NXT

ID, VBUS, SOF

DP

DM

USB

OTG FS

8 Streams

FIFO

ID, VBUS, SOF

AHB2 168 MHz

DMA2

DMA1

AHB1 168 MHz

8 Streams

FIFO

Power managmt

VDD

Voltage

regulator

VDD = 1.8 to 3.6 V

VSS

3.3 to 1.2 V

VCAP1, VCPA2

@V_DD

@V_DDA

POR

reset

Supply

supervision

RC HS

PA[15:0]

PB[15:0]

PC[15:0]

GPIO PORT A

GPIO PORT B

GPIO PORT C

RC LS

P LL1&2

POR/PDR

Int

VDDA, VSSA

NRST

BOR

PVD

@V_DD

@V_DDA

PD[15:0]

PE[15:0]

GPIO PORT D

GPIO PORT E

GPIO PORT F

GPIO PORT G

GPIO PORT H

GPIO PORT I

OSC_IN

OSC_OUT

XTAL OSC

4- 16MHz

Reset &

IWDG

clock

M AN A G T

control

PF[15:0]

PG[15:0]

PWR

VBAT = 1.65 to 3.6 V

interface

@V_BAT

OSC32_IN

OSC32_OUT

PH[15:0]

PI[11:0]

XTAL 32 kHz

RTC

AWU

Backup register

RTC_AF1

4 KB BKPSRAM

4 channels, ETR as AF

4 channels

32b

TIM2

16b

TIM3

140 AF

EXT IT. WKUP

SDIO / MMC

16b

TIM4

DMA2

DMA1

32b

TIM5

D[7:0]

CMD, CK as AF

AHB/APB2 AHB/APB1

16b

2 channels as AF

1 channel as AF

TIM12

4 compl. channels (TIM1_CH1[1:4]N,

4 channels (TIM1_CH1[1:4]ETR,

BKIN as AF

16b

TIM1 / PWM

TIM8 / PWM

TIM13

4 compl. channels (TIM1_CH1[1:4]N,

4 channels (TIM1_CH1[1:4]ETR,

BKIN as AF

1 channel as AF

16b

TIM14

16b

RX, TX as AF

CTS, RTS as AF

smcard

USART2

irDA

2 channels as AF

16b

TIM9

TIM10

TIM11

RX, TX as AF

CTS, RTS as AF

smcard

USART3

irDA

1 channel as AF

RX, TX as AF

UART4

UART5

WWDG

smcard

RX, TX, CK,

CTS, RTS as AF

RX, TX, CK,

CTS, RTS as AF

MOSI, MISO,

SCK, NSS as AF

USART1

USART6

SPI1

MOSI/SD, MISO/SD_ext, SCK/CK

NSS/WS, MCK as AF

irDA

SP2/I2S2

SP3/I2S3

I2C1/SMBUS

I2C2/SMBUS

I2C3/SMBUS

bxCAN1

smcard

irDA

16b

MOSI/SD, MISO/SD_ext, SCK/CK

NSS/WS, MCK as AF

TIM6

TIM7

SCL, SDA, SMBA as AF

TX, RX

@V_DDA

VDDREF_ADC

@V_DDA

Temperature sensor

ADC1

8 analog inputs common

to the 3 ADCs

DAC1

DAC2

ITF

8 analog inputs common

to the ADC1 & 2

IF

ADC2

ADC3

TX, RX

bxCAN2

8 analog inputs for ADC3

DAC1_OUT

as AF

DAC2_OUT

as AF

ai18511d

1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to

APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration

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Description

in the RCC_DCKCFGR register.

2. The camera interface and ethernet are available only on STM32F417xx devices.

®

2.2.1

ARM Cortex™-M4F core with embedded Flash and SRAM

The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded

systems. It was developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced response to interrupts.

The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using

metalanguage development tools, while avoiding saturation.

The STM32F415xx and STM32F417xx family is compatible with all ARM tools and software.

Figure 5 shows the general block diagram of the STM32F41x family.

Cortex-M4F is binary compatible with Cortex-M3.

Note:

2.2.2

Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

®

standard ARM Cortex™-M4F processors. It balances the inherent performance advantage

of the ARM Cortex-M4F over Flash memory technologies, which normally requires the

processor to wait for the Flash memory at higher frequencies.

To release the processor full 210 DMIPS performance at this frequency, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 168 MHz.

2.2.3

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

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Description

STM32F415xx, STM32F417xx

2.2.4

Embedded Flash memory

The STM32F41x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for

storing programs and data.

2.2.5

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a software

signature during runtime, to be compared with a reference signature generated at link-time

and stored at a given memory location.

2.2.6

Embedded SRAM

All STM32F41x products embed:

•

Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)

data RAM

RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.

4 Kbytes of backup SRAM

•

This area is accessible only from the CPU. Its content is protected against possible

unwanted write accesses, and is retained in Standby or VBAT mode.

2.2.7

Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB

HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a

seamless and efficient operation even when several high-speed peripherals work

simultaneously.

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Description

Figure 6. Multi-AHB matrix

ARM

Cortex-M4

GP

DMA1

GP

DMA2

MAC

Ethernet

64-Kbyte

USB OTG

HS

CCM data RAM

S0

S1

S2

S3

S4

S5

S6

S7

ICODE

M0

Flash

memory

DCODE

M1

SRAM1

M2

M3

M4

M5

112 Kbyte

SRAM2

16 Kbyte

AHB1

APB1

APB2

peripherals

AHB2

peripherals

FSMC

M6

Static MemCtl

Bus matrix-S

ai18490c

2.2.8

DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8

streams each. They are able to manage memory-to-memory, peripheral-to-memory and

memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,

support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

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Description

STM32F415xx, STM32F417xx

The DMA can be used with the main peripherals:

2

•

SPI and I S

2

I C

USART

General-purpose, basic and advanced-control timers TIMx

DAC

SDIO

Cryptographic acceleration

Camera interface (DCMI)

ADC.

2.2.9

Flexible static memory controller (FSMC)

The FSMC is embedded in the STM32F415xx and STM32F417xx family. It has four Chip

Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM,

NOR Flash and NAND Flash.

Functionality overview:

•

Write FIFO

Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz.

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

2.2.10

Nested vectored interrupt controller (NVIC)

The STM32F415xx and STM32F417xx embed a nested vectored interrupt controller able to

manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16

interrupt lines of the Cortex™-M4F.

•

Closely coupled NVIC gives low-latency interrupt processing

Interrupt entry vector table address passed directly to the core

Allows early processing of interrupts

Processing of late arriving, higher-priority interrupts

Support tail chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

2.2.11

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

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Description

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected

to the 16 external interrupt lines.

2.2.12

Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full

temperature range. The application can then select as system clock either the RC oscillator

or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is

detected, the system automatically switches back to the internal RC oscillator and a

software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing

to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL

clock entry is available when necessary (for example if an indirectly used external oscillator

fails).

Several prescalers allow the configuration of the three AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB

buses is 168 MHz while the maximum frequency of the high-speed APB domains is

84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class

2

performance. In this case, the I S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

2.2.13

Boot modes

At startup, boot pins are used to select one out of three boot options:

•

Boot from user Flash

Boot from system memory

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB

OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).

2.2.14

Power supply schemes

•

V

= 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when

DD

enabled), provided externally through V pins.

DD

V

, V

= 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset

DDA

SSA

blocks, RCs and PLL. V

and V

must be connected to V and V , respectively.

DDA

SSA DD SS

V

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

backup registers (through power switch) when V is not present.

DD

Refer to Figure 21: Power supply scheme for more details.

V /V minimum value of 1.7 V is obtained when the device operates in reduced

DD DDA

Note:

temperature range, and with the use of an external power supply supervisor (refer to

Section : Internal reset OFF).

Refer to Table 2 in order to identify the packages supporting this option.

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Description

STM32F415xx, STM32F417xx

2.2.15

Power supply supervisor

Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by

holding PDR_ON high. On all other packages, the power supply supervisor is always

enabled.

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and

ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is

reached, the option byte loading process starts, either to confirm or modify default BOR

threshold levels, or to disable BOR permanently. Three BOR thresholds are available

through option bytes. The device remains in reset mode when V is below a specified

DD

threshold, V

or V

, without the need for an external reset circuit.

POR/PDR

BOR

The device also features an embedded programmable voltage detector (PVD) that monitors

the V /V power supply and compares it to the V threshold. An interrupt can be

DD DDA

PVD

generated when V /V

drops below the V

threshold and/or when V /V

is

DD DDA

PVD

DD DDA

higher than the V

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on

reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin.

An external power supply supervisor should monitor V and should maintain the device in

DD

reset mode as long as V is below a specified threshold. PDR_ON should be connected to

DD

this external power supply supervisor. Refer to Figure 7: Power supply supervisor

interconnection with internal reset OFF.

Figure 7. Power supply supervisor interconnection with internal reset OFF

V_DD

External V_DDpower supply supervisor

Ext. reset controller active when

V_DD< 1.7 V or 1.8 V ⁽¹⁾

PDR_ON

Application reset

signal (optional)

NRST

V_DD

MS31383V3

1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.

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Description

The V specified threshold, below which the device must be maintained under reset, is

DD

1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the

0 to 70 °C temperature range.

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no more supported:

•

The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled

The brownout reset (BOR) circuitry is disabled

The embedded programmable voltage detector (PVD) is disabled

V

functionality is no more available and V

pin should be connected to V

BAT DD

BAT

All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset

through the PDR_ON signal.

Figure 8. PDR_ON and NRST control with internal reset OFF

V

DD

PDR = 1.7 V or 1.8 V ⁽¹⁾

time

Reset by other source than

power supply supervisor

NRST

PDR_ON

time

MS19009V6

1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.

2.2.16

Voltage regulator

The regulator has four operating modes:

•

Regulator ON

–

Main regulator mode (MR)

Low power regulator (LPR)

Power-down

•

Regulator OFF

Regulator ON

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. On all other packages, the regulator is always enabled.

DocID022063 Rev 4

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Description

STM32F415xx, STM32F417xx

There are three power modes configured by software when regulator is ON:

•

MR is used in the nominal regulation mode (With different voltage scaling in Run)

In Main regulator mode (MR mode), different voltage scaling are provided to reach the

best compromise between maximum frequency and dynamic power consumption.

Refer to Table 14: General operating conditions.

•

LPR is used in the Stop modes

The LP regulator mode is configured by software when entering Stop mode.

Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator

output is in high impedance and the kernel circuitry is powered down, inducing zero

consumption. The contents of the registers and SRAM are lost)

Two external ceramic capacitors should be connected on V

& V

pin. Refer to

CAP_1

CAP_2

Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions.

All packages have regulator ON feature.

Regulator OFF

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is

disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply

externally a V voltage source through V

and V

pins.

12

CAP_1

CAP_2

Since the internal voltage scaling is not manage internally, the external voltage value must

be aligned with the targetted maximum frequency. Refer to Table 14: General operating

conditions.

The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling

capacitors.

Refer to Figure 21: Power supply scheme

When the regulator is OFF, there is no more internal monitoring on V . An external power

12

supply supervisor should be used to monitor the V of the logic power domain. PA0 pin

12

should be used for this purpose, and act as power-on reset on V power domain.

12

In regulator OFF mode the following features are no more supported:

•

PA0 cannot be used as a GPIO pin since it allows to reset a part of the V logic power

domain which is not reset by the NRST pin.

12

•

As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As

a consequence, PA0 and NRST pins must be managed separately if the debug

connection under reset or pre-reset is required.

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Description

Figure 9. Regulator OFF

V₁₂

External V_{CAP_1/2}power

Application reset

signal (optional)

supply supervisor

Ext. reset controller active

when V_{CAP_1/2}< Min V₁₂

V_DD

PA0

V_DD

NRST

BYPASS_REG

V₁₂

V_{CAP_1}

V_{CAP_2}

ai18498V4

The following conditions must be respected:

•

V

should always be higher than V

and V

to avoid current injection

CAP_2

DD

CAP_1

between power domains.

•

If the time for V and V

to reach V minimum value is faster than the time for

CAP_1

CAP_2

12

V

to reach 1.8 V, then PA0 should be kept low to cover both conditions: until V

DD

CAP_1

and V

reach V minimum value and until V reaches 1.8 V (see Figure 10).

12 DD

CAP_2

•

Otherwise, if the time for V

and V

to reach V minimum value is slower

CAP_2 12

CAP_1

than the time for V to reach 1.8 V, then PA0 could be asserted low externally (see

DD

Figure 11).

If V

and V

go below V minimum value and V is higher than 1.8 V, then

CAP_1

CAP_2 12 DD

a reset must be asserted on PA0 pin.

Note:

The minimum value of V depends on the maximum frequency targeted in the application

12

(see Table 14: General operating conditions).

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Description

STM32F415xx, STM32F417xx

Figure 10. Startup in regulator OFF mode: slow V slope

DD

- power-down reset risen after V

/V

stabilization

CAP_1 CAP_2

V_DD

PDR = 1.7 V or 1.8 V ⁽²⁾

V_{CAP_1}/V_{CAP_2}

V₁₂

Min V₁₂

time

NRST

ai18491e

time

1. This figure is valid both whatever the internal reset mode (onON or OFFoff).

2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges.

Figure 11. Startup in regulator OFF mode: fast V slope

DD

- power-down reset risen before V

/V

stabilization

CAP_1 CAP_2

V_DD

PDR = 1.7 V or 1.8 V ⁽²⁾

V_{CAP_1}/V_{CAP_2}

V₁₂

Min V₁₂

time

NRST

PA0 asserted externally

ai18492d

1. This figure is valid both whatever the internal reset mode (onON or offOFF).

2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges.

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Description

2.2.17

Regulator ON/OFF and internal reset ON/OFF availability

Table 3. Regulator ON/OFF and internal reset ON/OFF availability

Internal reset

OFF

Regulator ON

Regulator OFF Internal reset ON

LQFP64

Yes

No

LQFP100

Yes

No

LQFP144

LQFP176

Yes

PDR_ON

PDR_ON set to

V_DD

connected to an

external power

supply supervisor

Yes

WLCSP90

UFBGA176

BYPASS_REGset BYPASS_REGset

to V_SSto V_DD

2.2.18

Real-time clock (RTC), backup SRAM and backup registers

The backup domain of the STM32F415xx and STM32F417xx includes:

•

The real-time clock (RTC)

4 Kbytes of backup SRAM

20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain

the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-

coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are

performed automatically. The RTC provides a programmable alarm and programmable

periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is

also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power

RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC

has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz

output to compensate for any natural quartz deviation.

Two alarm registers are used to generate an alarm at a specific time and calendar fields can

be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit

programmable binary auto-reload downcounter with programmable resolution is available

and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a

time base of 1 second from a clock at 32.768 kHz.

The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data

which need to be retained in V

and standby mode. This memory area is disabled by

BAT

default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be

enabled by software.

The backup registers are 32-bit registers used to store 80 bytes of user application data

when V power is not present. Backup registers are not reset by a system, a power reset,

DD

or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power

modes).

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,

hours, day, and date.

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Description

STM32F415xx, STM32F417xx

Like backup SRAM, the RTC and backup registers are supplied through a switch that is

powered either from the V supply when present or from the V

pin.

DD

BAT

2.2.19

Low-power modes

The STM32F415xx and STM32F417xx support three low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of

SRAM and registers. All clocks in the V domain are stopped, the PLL, the HSI RC

12

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /

tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).

•

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire V domain is powered off. The PLL,

12

the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the

backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,

a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event

occurs.

The standby mode is not supported when the embedded voltage regulator is bypassed

and the V domain is controlled by an external power.

12

2.2.20

V

operation

BAT

The V

pin allows to power the device V

domain from an external battery, an external

BAT

supercapacitor, or from V when no external battery and an external supercapacitor are

DD

present.

V

operation is activated when V is not present.

DD

BAT

The V

pin supplies the RTC, the backup registers and the backup SRAM.

BAT

Note:

When the microcontroller is supplied from V , external interrupts and RTC alarm/events

BAT

do not exit it from V

operation.

BAT

When PDR_ON pin is not connected to V (internal reset OFF), the V

functionality is no

BAT

DD

more available and V

pin should be connected to V

.

BAT

DD

2.2.21

Timers and watchdogs

The STM32F415xx and STM32F417xx devices include two advanced-control timers, eight

general-purpose timers, two basic timers and two watchdog timers.

All timer counters can be frozen in debug mode.

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Description

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4. Timer feature comparison

DMA

request

generatio

n

Max

Counter

Timer resolutio

n

Capture/

compare

channels

Timer

type

Counter Prescaler

Complementar interface timer

type

factor

y output

clock

(MHz) (MHz)

clock

Up,

Down,

Up/dow

n

Anyinteger

between 1

and 65536

Advanced TIM1,

16-bit

32-bit

16-bit

Yes

4

Yes

84

42

168

84

-control

TIM8

Up,

Down,

Up/dow

n

Anyinteger

between 1

and 65536

TIM2,

TIM5

No

Up,

Down,

Up/dow

n

Anyinteger

between 1

and 65536

TIM3,

TIM4

84

Anyinteger

between 1

and 65536

TIM9

16-bit

Up

No

Yes

2

1

2

1

0

No

84

42

168

84

General

purpose

TIM10

,

TIM11

Anyinteger

between 1

and 65536

Anyinteger

between 1

and 65536

TIM12

TIM13

,

TIM14

Anyinteger

between 1

and 65536

84

Anyinteger

between 1

and 65536

TIM6,

TIM7

Basic

84

Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators

multiplexed on 6 channels. They have complementary PWM outputs with programmable

inserted dead times. They can also be considered as complete general-purpose timers.

Their 4 independent channels can be used for:

•

Input capture

Output compare

PWM generation (edge- or center-aligned modes)

One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose

TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-

100%).

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Description

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The advanced-control timer can work together with the TIMx timers via the Timer Link

feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F41x devices

(see Table 4 for differences).

•

TIM2, TIM3, TIM4, TIM5

The STM32F41x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,

and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload

up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-

bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent

channels for input capture/output compare, PWM or one-pulse mode output. This gives

up to 16 input capture/output compare/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the

other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the

Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are

capable of handling quadrature (incremental) encoder signals and the digital outputs

from 1 to 4 hall-effect sensors.

•

TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9

and TIM12 have two independent channels for input capture/output compare, PWM or

one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5

full-featured general-purpose timers. They can also be used as simple time bases.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be

used as a generic 16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free-running timer for application timeout

management. It is hardware- or software-configurable through the option bytes.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

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SysTick timer

Description

This timer is dedicated to real-time operating systems, but could also be used as a standard

downcounter. It features:

•

A 24-bit downcounter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source.

2.2.22

2.2.23

Inter-integrated circuit interface (I²C)

Up to three I²C bus interfaces can operate in multimaster and slave modes. They can

support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz) . They support

the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware

CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

Universal synchronous/asynchronous receiver transmitters (USART)

The STM32F415xx and STM32F417xx embed four universal synchronous/asynchronous

receiver transmitters (USART1, USART2, USART3 and USART6) and two universal

asynchronous receiver transmitters (UART4 and UART5).

These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to

communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at

up to 5.25 Mbit/s.

USART1, USART2, USART3 and USART6 also provide hardware management of the CTS

and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication

capability. All interfaces can be served by the DMA controller.

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Description

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Table 5. USART feature comparison

Max. baud rate Max. baud rate

Modem

(RTS/ LIN

CTS)

USART Standard

SPI

master

Smartcard

in Mbit/s in Mbit/s

APB

irDA

name

features

(ISO 7816) (oversampling (oversampling mapping

by 16)

by 8)

APB2

(max.

84 MHz)

USART1

USART2

USART3

UART4

X

-

X

-

X

-

5.25

10.5

APB1

(max.

42 MHz)

2.62

5.25

10.5

APB1

(max.

42 MHz)

APB1

(max.

42 MHz)

APB1

(max.

42 MHz)

UART5

-

APB2

(max.

USART6

X

84 MHz)

2.2.24

Serial peripheral interface (SPI)

The STM32F41x feature up to three SPIs in slave and master modes in full-duplex and

simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3

can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies

and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification

supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.

The SPI interface can be configured to operate in TI mode for communications in master

mode and slave mode.

2

2.2.25

Inter-integrated sound (I S)

2

Two standard I S interfaces (multiplexed with SPI2 and SPI3) are available. They can be

operated in master or slave mode, in full duplex and half-duplex communication modes, and

can be configured to operate with a 16-/32-bit resolution as an input or output channel.

Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of

2

the I S interfaces is/are configured in master mode, the master clock can be output to the

external DAC/CODEC at 256 times the sampling frequency.

2

All I Sx can be served by the DMA controller.

2.2.26

Audio PLL (PLLI2S)

2

The devices feature an additional dedicated PLL for audio I S application. It allows to

2

achieve error-free I S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

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Description

2

The PLLI2S configuration can be modified to manage an I S sample rate change without

disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 KHz to 192 KHz.

2

In addition to the audio PLL, a master clock input pin can be used to synchronize the I S

flow with an external PLL (or Codec output).

2.2.27

Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack

of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital

protocol Rev1.1.

2.2.28

Ethernet MAC interface with dedicated DMA and IEEE 1588 support

Peripheral available only on the STM32F417xx devices.

The STM32F417xx devices provide an IEEE-802.3-2002-compliant media access controller

(MAC) for ethernet LAN communications through an industry-standard medium-

independent interface (MII) or a reduced medium-independent interface (RMII). The

STM32F417xx requires an external physical interface device (PHY) to connect to the

physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F417xx MII

port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz

(MII) from the STM32F417xx.

The STM32F417xx includes the following features:

•

Supports 10 and 100 Mbit/s rates

Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM

and the descriptors (see the STM32F40x reference manual for details)

•

Tagged MAC frame support (VLAN support)

Half-duplex (CSMA/CD) and full-duplex operation

MAC control sublayer (control frames) support

32-bit CRC generation and removal

Several address filtering modes for physical and multicast address (multicast and

group addresses)

•

32-bit status code for each transmitted or received frame

Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the

receive FIFO are both 2 Kbytes.

•

Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008

(PTP V2) with the time stamp comparator connected to the TIM2 input

Triggers interrupt when system time becomes greater than target time

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Description

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2.2.29

Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1

Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as

extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 bytes of SRAM are allocated for each CAN.

2.2.30

Universal serial bus on-the-go full-speed (OTG_FS)

The STM32F415xx and STM32F417xx embed an USB OTG full-speed device/host/OTG

peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the

USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable

endpoint setting and supports suspend/resume. The USB OTG full-speed controller

requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE

oscillator. The major features are:

•

Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

4 bidirectional endpoints

8 host channels with periodic OUT support

HNP/SNP/IP inside (no need for any external resistor)

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

2.2.31

Universal serial bus on-the-go high-speed (OTG_HS)

The STM32F415xx and STM32F417xx devices embed a USB OTG high-speed (up to

480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and

high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and

features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using

the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG

1.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock

that is generated by a PLL connected to the HSE oscillator.

The major features are:

•

Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

6 bidirectional endpoints

12 host channels with periodic OUT support

Internal FS OTG PHY support

External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is

connected to the microcontroller ULPI port through 12 signals. It can be clocked using

the 60 MHz output.

•

Internal USB DMA

HNP/SNP/IP inside (no need for any external resistor)

for OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

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2.2.32

Digital camera interface (DCMI)

The camera interface is not available in STM32F415xx devices.

STM32F417xx products embed a camera interface that can connect with camera modules

and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The

camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:

•

Programmable polarity for the input pixel clock and synchronization signals

Parallel data communication can be 8-, 10-, 12- or 14-bit

Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2

progressive video, RGB 565 progressive video or compressed data (like JPEG)

•

Supports continuous mode or snapshot (a single frame) mode

Capability to automatically crop the image

2.2.33

Cryptographic acceleration

The STM32F415xx and STM32F417xx devices embed a cryptographic accelerator. This

cryptographic accelerator provides a set of hardware acceleration for the advanced

cryptographic algorithms usually needed to provide confidentiality, authentication, data

integrity and non repudiation when exchanging messages with a peer.

These algorithms consists of:

Encryption/Decryption

–

DES/TDES (data encryption standard/triple data encryption standard): ECB

(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,

128- or 192-bit key

–

AES (advanced encryption standard): ECB, CBC and CTR (counter mode)

chaining algorithms, 128, 192 or 256-bit key

Universal hash

–

SHA-1 (secure hash algorithm)

MD5

HMAC

The cryptographic accelerator supports DMA request generation.

2.2.34

2.2.35

Random number generator (RNG)

All STM32F415xx and STM32F417xx products embed an RNG that delivers 32-bit random

numbers generated by an integrated analog circuit.

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)

or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to

avoid spurious writing to the I/Os registers.

Fast I/O handling allowing maximum I/O toggling up to 84 MHz.

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Description

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2.2.36

Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16

external channels, performing conversions in the single-shot or scan mode. In scan mode,

automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

•

Simultaneous sample and hold

Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very

precise monitoring of the converted voltage of one, some or all selected channels. An

interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,

TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

2.2.37

Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The

conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally

connected to the ADC1_IN16 input channel which is used to convert the sensor output

voltage into a digital value.

As the offset of the temperature sensor varies from chip to chip due to process variation, the

internal temperature sensor is mainly suitable for applications that detect temperature

changes instead of absolute temperatures. If an accurate temperature reading is needed,

then an external temperature sensor part should be used.

2.2.38

Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two

analog voltage signal outputs.

This dual digital Interface supports the following features:

•

two DAC converters: one for each output channel

8-bit or 12-bit monotonic output

left or right data alignment in 12-bit mode

synchronized update capability

noise-wave generation

triangular-wave generation

dual DAC channel independent or simultaneous conversions

DMA capability for each channel

external triggers for conversion

input voltage reference V

REF+

Eight DAC trigger inputs are used in the device. The DAC channels are triggered through

the timer update outputs that are also connected to different DMA streams.

2.2.39

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

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Description

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could

be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to

switch between JTAG-DP and SW-DP.

2.2.40

Embedded Trace Macrocell™

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data

flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F41x through a small number of ETM pins to an external hardware trace port

analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or

any other high-speed channel. Real-time instruction and data flow activity can be recorded

and then formatted for display on the host computer that runs the debugger software. TPA

hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

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Pinouts and pin description

STM32F415xx, STM32F417xx

3

Pinouts and pin description

Figure 12. STM32F41x LQFP64 pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

VDD

VCAP_2

PA13

PA12

PA11

PA10

PA9

VBAT

PC13

PC14

1

2

3

4

5

6

7

8

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PC15

PH0

PH1

NRST

PC0

PA8

LQFP64

PC9

PC1

9

PC8

PC2

10

11

12

13

14

15

16

PC7

PC3

PC6

VSSA

VDDA

PA0_WKUP

PA1

PB15

PB14

PB13

PB12

PA2

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

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Pinouts and pin description

Figure 13. STM32F41x LQFP100 pinout

PE2

PE3

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD

VSS

2

PE4

3

VCAP_2

PA13

PA12

PA 11

PA10

PA9

PE5

PE6

4

5

VBAT

PC13

PC14

PC15

VSS

6

7

8

9

PA8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PC9

VDD

PH0

PC8

PC7

PH1

PC6

LQFP100

NRST

PC0

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PC1

PC2

PC3

VDD

VSSA

VREF+

VDDA

PA0

PD8

PB15

PB14

PB13

PB12

PA1

PA2

ai18495c

DocID022063 Rev 4

41/186

Pinouts and pin description

STM32F415xx, STM32F417xx

Figure 14. STM32F41x LQFP144 pinout

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14

PC15

PF0

1

108

107

106

105

104

103

102

101

100

99

V_DD

2

V_SS

3

V_{CAP_2}

PA13

PA12

PA11

PA10

PA9

4

5

6

7

8

9

PA8

10

11

12

13

14

15

16

PC9

PF1

98

PC8

PF2

97

PC7

PF3

96

PC6

PF4

95

V_DD

PF5

94

V_SS

93

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

V_DD

V_DD17

92

PF6

PF7

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

91

LQFP144

90

PF8

89

PF9

88

PF10

PH0

87

86

85

PH1

NRST

PC0

84

83

82

81

80

79

78

77

76

75

74

73

V_SS

PC1

PD13

PD12

PD11

PD10

PD9

PC2

PC3

V_DD

V_SSA

V_REF+

V_DDA

PA0

PA1

PA2

PD8

PB15

PB14

PB13

PB12

ai18496b

42/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Pinouts and pin description

Figure 15. STM32F41x LQFP176 pinout

PE2

PE3

PE4

PE5

PE6

V_BAT

PI8

PC13

PC14

PC15

PI9

1

2

3

4

5

6

7

8

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

PI1

PI0

PH15

PH14

PH13

V_DD

V_SS

V_{CAP_2}

PA13

PA12

PA11

PA10

PA9

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

PI10

PI11

V_SS

PA8

V_DD

PC9

PC8

PC7

PC6

V_DD

PF0

PF1

PF2

PF3

PF4

PF5

V_SS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

V_DD

LQFP176

V_DD

PF6

PF7

PF8

PF9

PF10

PH0

PH1

NRST

PC0

PC1

PC2

PC3

V_DDA

V_SSA

V_REF+

V_DDA

PA0

PA1

PA2

PH2

PH3

107

106

105

104

10V3

V_SS

102

V

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

V_DD

101

100

99

98

97

96

95

94

93

92

91

V_SS

PH12

90

89

MS19916V3

DocID022063 Rev 4

43/186

Pinouts and pin description

STM32F415xx, STM32F417xx

Figure 16. STM32F41x UFBGA176 ballout

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A

B

C

D

E

F

PE3

PE2

PE5

PI7

PE1

PE6

PI6

PE0

PB9

PI5

PB8

PB7

VDD

VSS

PB5

PB6

PG14

PG15

VDD

VSS

PG13

PG12

VDD

VSS

PB4

PG11

VDD

VSS

PB3

PG10

PG9

PD4

PD7

PD6

PD5

PD3

PC12

PD0

PA15

PC11

PI3

PA14

PC10

PI2

PA13

PA12

PA11

PA10

PA9

PE4

VBAT

PC13

PC14

PD1

PDR_ON

BOOT0

PI8

PI9

PI4

PD2

PH15

PH14

VCAP_2

VDD

PI1

PF0

VSS

PF2

PF3

PF6

PF9

PC0

PA1

PA2

PA3

PI10

VDD

PF1

PF4

PF5

PF8

PC1

PA0

PA6

PA7

PI11

PH2

PH3

PH4

PH5

PH13

VSS

VDD

PH12

PH11

PH8

PI0

PC15

VSS

PC9

PC8

PG8

PG7

PG4

PD15

PD14

PD11

PD9

PB14

PA8

G

H

J

PH0

PH1

PC7

VDD

PC6

NRST

PF7

VDD

PG6

PG3

PG2

PD13

PD10

PD8

K

L

PG5

VDD

BYPASS_

REG

PF10

PH10

PH9

M

N

P

R

VSSA

VREF-

VREF+

VDDA

PC2

PA4

PA5

PB1

PC3

PC4

PC5

PB0

PB2

PF13

PF12

PF11

PG1

PG0

VSS

VDD

PE8

PE7

VSS

VDD

PE9

VCAP_1

VDD

PH6

PE13

PE14

PE15

PH7

PD12

PB13

PB11

PF15

PF14

PE11

PB12

PB10

PE10

PE12

PB15

ai18497b

1. This figure shows the package top view.

44/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Pinouts and pin description

Figure 17. STM32F41x WLCSP90 ballout

10

9

8

7

6

5

4

3

2

1

PA14

A

B

VBAT

PC14

PC13 PDR_ON BOOT0

PB4

PD7

PD4

PC12

VDD

PI1

PC15

VSS

VDD

PB9

PB7

PB6

PB3

PD5

PD6

PD1

PD2

PA15

PI0

VCAP_2

PA11

C

PA0

PC11

PA12

BYPASS_

REG

PA13

VDD

D

PC2

PC0

PB5

VSS

PD0

VDD

PC10

VSS

PA10

PC9

PA9

PC8

PA8

PC7

PB8

VSS

PC3

E

PH1

VDDA

PA3

F

PH0

VDD

PB0

PE10

PE7

PE14 VCAP_1

PC6

PD14

PD12

PD15

PD11

PA1

PA5

G

H

NRST

PE13

PE12

PE15

PB10

PD10

VSSA

PA2

PA6

PA7

PB1

PB2

PE8

PE9

PD9

PD8

PB15

PB13

PE11

PB11

PB12

PB14

J

PA4

MS30402V1

1. This figure shows the package bump view.

Table 6. Legend/abbreviations used in the pinout table

Abbreviation Definition

Name

Unless otherwise specified in brackets below the pin name, the pin function during and after

reset is the same as the actual pin name

Pin name

S

I

Supply pin

Input only pin

Pin type

I/O

FT

TTa

B

Input / output pin

5 V tolerant I/O

3.3 V tolerant I/O directly connected to ADC

Dedicated BOOT0 pin

I/O structure

Notes

RST

Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Functions selected through GPIOx_AFR registers

Alternate

functions

Additional

functions

Functions directly selected/enabled through peripheral registers

DocID022063 Rev 4

45/186

Pinouts and pin description

Pin number

STM32F415xx, STM32F417xx

Table 7. STM32F41x pin and ball definitions

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

TRACECLK/ FSMC_A23 /

ETH_MII_TXD3 /

EVENTOUT

-

1

A2

1

PE2

I/O FT

TRACED0/FSMC_A19 /

EVENTOUT

-

2

3

2

3

A1

B1

2

3

PE3

PE4

I/O FT

TRACED1/FSMC_A20 /

DCMI_D4/ EVENTOUT

TRACED2 / FSMC_A21 /

TIM9_CH1 / DCMI_D6 /

EVENTOUT

-

4

B2

4

PE5

I/O FT

TRACED3 / FSMC_A22 /

TIM9_CH2 / DCMI_D7 /

EVENTOUT

-

1

-

A10

-

5

6

-

5

6

-

B3

C1

D2

5

6

7

PE6

V_BAT

PI8

I/O FT

S

RTC_TAMP1,

RTC_TAMP2,

RTC_TS

(2)(

3)

I/O FT

EVENTOUT

RTC_OUT,

RTC_TAMP1,

RTC_TS

(2)

(3)

2

3

4

A9

B10

B9

7

8

9

7

8

9

D1

E1

8

9

PC13

I/O FT

EVENTOUT

(2)(

3)

PC14/OSC32_IN

(PC14)

OSC32_IN⁽⁴⁾

PC15/

OSC32_OUT

(2)(

3)

F1 10

EVENTOUT

OSC32_OUT⁽⁴⁾

(PC15)

-

D3 11

E3 12

PI9

I/O FT

CAN1_RX / EVENTOUT

ETH_MII_RX_ER /

EVENTOUT

PI10

PI11

OTG_HS_ULPI_DIR /

EVENTOUT

-

E4 13

I/O FT

-

F2 14

F3 15

V_SS

V_DD

S

FSMC_A0 / I2C2_SDA /

EVENTOUT

-

10 E2 16

PF0

I/O FT

46/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Pinouts and pin description

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

FSMC_A1 / I2C2_SCL /

EVENTOUT

-

11 H3 17

12 H2 18

PF1

PF2

I/O FT

FSMC_A2 / I2C2_SMBA /

EVENTOUT

(4)

-

13 J2

14 J3

19

20

PF3

PF4

PF5

V_SS

V_DD

I/O FT

S

FSMC_A3/EVENTOUT

FSMC_A4/EVENTOUT

FSMC_A5/EVENTOUT

ADC3_IN9

ADC3_IN14

ADC3_IN15

15 K3 21

C9 10 16 G2 22

B8 11 17 G3 23

S

TIM10_CH1 /

FSMC_NIORD/

EVENTOUT

(4)

-

18 K2 24

19 K1 25

20 L3 26

PF6

PF7

PF8

I/O FT

ADC3_IN4

ADC3_IN5

ADC3_IN6

TIM11_CH1/FSMC_NREG

/ EVENTOUT

TIM13_CH1 /

FSMC_NIOWR/

EVENTOUT

TIM14_CH1 / FSMC_CD/

EVENTOUT

(4)

-

21 L2 27

22 L1 28

PF9

I/O FT

ADC3_IN7

ADC3_IN8

OSC_IN⁽⁴⁾

PF10

FSMC_INTR/ EVENTOUT

EVENTOUT

PH0/OSC_IN

(PH0)

5

F10 12 23 G1 29

F9 13 24 H1 30

PH1/OSC_OUT

(PH1)

6

7

I/O FT

EVENTOUT

OSC_OUT⁽⁴⁾

RS

G10 14 25 J1

E10 15 26 M2 32

16 27 M3 33

31

NRST

I/O

T

OTG_HS_ULPI_STP/

EVENTOUT

(4)

8

9

PC0

PC1

I/O FT

ADC123_IN10

ADC123_IN11

-

ETH_MDC/ EVENTOUT

SPI2_MISO /

OTG_HS_ULPI_DIR /

ETH_MII_TXD2

(4)

10 D10 17 28 M4 34

PC2

I/O FT

ADC123_IN12

/I2S2ext_SD/ EVENTOUT

DocID022063 Rev 4

47/186

Pinouts and pin description

STM32F415xx, STM32F417xx

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

SPI2_MOSI / I2S2_SD /

OTG_HS_ULPI_NXT /

ETH_MII_TX_CLK/

EVENTOUT

(4)

11 E9 18 29 M5 35

PC3

I/O FT

ADC123_IN13

-

19 30 G3 36

V_DD

S

12 H10 20 31 M1 37

V_SSA

-

N1

-

V_REF

–

21 32 P1 38

V_REF+

V_DDA

13 G9 22 33 R1 39

USART2_CTS/

UART4_TX/

ETH_MII_CRS /

TIM2_CH1_ETR/

TIM5_CH1 / TIM8_ETR/

EVENTOUT

ADC123_IN0/WKUP⁽⁴

PA0/WKUP

(PA0)

(5)

14 C10 23 34 N3 40

I/O FT

)

USART2_RTS /

UART4_RX/

ETH_RMII_REF_CLK /

ETH_MII_RX_CLK /

TIM5_CH2 / TIM2_CH2/

EVENTOUT

(4)

15 F8 24 35 N2 41

PA1

PA2

I/O FT

ADC123_IN1

ADC123_IN2

USART2_TX/TIM5_CH3 /

TIM9_CH1 / TIM2_CH3 /

ETH_MDIO/ EVENTOUT

16 J10 25 36 P2 42

ETH_MII_CRS/EVENTOU

T

-

F4 43

G4 44

PH2

PH3

I/O FT

ETH_MII_COL/EVENTOU

T

I2C2_SCL /

OTG_HS_ULPI_NXT/

EVENTOUT

-

H4 45

PH4

PH5

I/O FT

J4

46

I2C2_SDA/ EVENTOUT

48/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Pinouts and pin description

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

USART2_RX/TIM5_CH4 /

TIM9_CH2 / TIM2_CH4 /

OTG_HS_ULPI_D0 /

ETH_MII_COL/

(4)

17 H9 26 37 R2 47

PA3

I/O FT

ADC123_IN3

EVENTOUT

18 E5 27 38

D9

-

V_SS

BYPASS_REG

V_DD

S

L4 48

I

FT

19 E4 28 39 K4 49

20 J9 29 40 N4 50

S

SPI1_NSS / SPI3_NSS /

USART2_CK /

DCMI_HSYNC /

OTG_HS_SOF/ I2S3_WS/

EVENTOUT

ADC12_IN4

/DAC_OUT1

(4)

PA4

PA5

PA6

I/O TTa

I/O FT

SPI1_SCK/

OTG_HS_ULPI_CK /

TIM2_CH1_ETR/

ADC12_IN5/DAC_OU

T2

21 G8 30 41 P4 51

TIM8_CH1N/ EVENTOUT

SPI1_MISO /

TIM8_BKIN/TIM13_CH1 /

DCMI_PIXCLK /

TIM3_CH1 / TIM1_BKIN/

EVENTOUT

22 H8 31 42 P3 52

ADC12_IN6

ADC12_IN7

SPI1_MOSI/ TIM8_CH1N

/ TIM14_CH1/TIM3_CH2/

ETH_MII_RX_DV /

TIM1_CH1N /

(4)

23 J8 32 43 R3 53

PA7

I/O FT

ETH_RMII_CRS_DV/

EVENTOUT

ETH_RMII_RX_D0 /

ETH_MII_RX_D0/

EVENTOUT

(4)

24

25

-

33 44 N5 54

34 45 P5 55

PC4

PC5

I/O FT

ADC12_IN14

ADC12_IN15

ETH_RMII_RX_D1 /

ETH_MII_RX_D1/

EVENTOUT

TIM3_CH3 / TIM8_CH2N/

OTG_HS_ULPI_D1/

(4)

26 G7 35 46 R5 56

PB0

I/O FT

ADC12_IN8

ETH_MII_RXD2 /

TIM1_CH2N/ EVENTOUT

DocID022063 Rev 4

49/186

Pinouts and pin description

STM32F415xx, STM32F417xx

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

TIM3_CH4 / TIM8_CH3N/

OTG_HS_ULPI_D2/

ETH_MII_RXD3 /

TIM1_CH3N/ EVENTOUT

(4)

27 H7 36 47 R4 57

28 J7 37 48 M6 58

PB1

I/O FT

ADC12_IN9

PB2/BOOT1

(PB2)

EVENTOUT

-

49 R6 59

50 P6 60

51 M8 61

52 N8 62

53 N6 63

54 R7 64

55 P7 65

56 N7 66

57 M7 67

PF11

PF12

V_SS

I/O FT

S

DCMI_D12/ EVENTOUT

FSMC_A6/ EVENTOUT

V_DD

S

PF13

PF14

PF15

PG0

PG1

I/O FT

FSMC_A7/ EVENTOUT

FSMC_A8/ EVENTOUT

FSMC_A9/ EVENTOUT

FSMC_A10/ EVENTOUT

FSMC_A11/ EVENTOUT

FSMC_D4/TIM1_ETR/

EVENTOUT

-

G6 38 58 R8 68

H6 39 59 P8 69

J6 40 60 P9 70

PE7

PE8

PE9

I/O FT

FSMC_D5/ TIM1_CH1N/

EVENTOUT

FSMC_D6/TIM1_CH1/

EVENTOUT

-

61 M9 71

62 N9 72

V_SS

V_DD

S

FSMC_D7/TIM1_CH2N/

EVENTOUT

-

F6 41 63 R9 73

J5 42 64 P10 74

H5 43 65 R10 75

G5 44 66 N11 76

PE10

PE11

PE12

PE13

I/O FT

FSMC_D8/TIM1_CH2/

EVENTOUT

FSMC_D9/TIM1_CH3N/

EVENTOUT

FSMC_D10/TIM1_CH3/

EVENTOUT

50/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Pinouts and pin description

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

FSMC_D11/TIM1_CH4/

EVENTOUT

-

F5 45 67 P11 77

G4 46 68 R11 78

PE14

PE15

I/O FT

FSMC_D12/TIM1_BKIN/

EVENTOUT

SPI2_SCK / I2S2_CK /

I2C2_SCL/ USART3_TX /

OTG_HS_ULPI_D3 /

ETH_MII_RX_ER /

29 H4 47 69 R12 79

PB10

PB11

I/O FT

TIM2_CH3/ EVENTOUT

I2C2_SDA/USART3_RX/

OTG_HS_ULPI_D4 /

ETH_RMII_TX_EN/

ETH_MII_TX_EN /

TIM2_CH4/ EVENTOUT

30 J4 48 70 R13 80

31 F4 49 71 M10 81

V_{CAP_1}

V_DD

S

32

-

50 72 N10 82

I2C2_SMBA / TIM12_CH1

/ ETH_MII_RXD2/

EVENTOUT

-

M11 83

N12 84

M12 85

M13 86

PH6

PH7

PH8

PH9

I/O FT

I2C3_SCL /

ETH_MII_RXD3/

EVENTOUT

-

I2C3_SDA /

DCMI_HSYNC/

EVENTOUT

I2C3_SMBA /

TIM12_CH2/ DCMI_D0/

EVENTOUT

TIM5_CH1 / DCMI_D1/

EVENTOUT

-

L13 87

L12 88

K12 89

PH10

PH11

PH12

I/O FT

TIM5_CH2 / DCMI_D2/

EVENTOUT

TIM5_CH3 / DCMI_D3/

EVENTOUT

-

H12 90

J12 91

V_SS

V_DD

S

DocID022063 Rev 4

51/186

Pinouts and pin description

STM32F415xx, STM32F417xx

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

SPI2_NSS / I2S2_WS /

I2C2_SMBA/

USART3_CK/ TIM1_BKIN

/ CAN2_RX /

33 J3 51 73 P12 92

PB12

PB13

I/O FT

OTG_HS_ULPI_D5/

ETH_RMII_TXD0 /

ETH_MII_TXD0/

OTG_HS_ID/ EVENTOUT

SPI2_SCK / I2S2_CK /

USART3_CTS/

TIM1_CH1N /CAN2_TX /

OTG_HS_ULPI_D6 /

ETH_RMII_TXD1 /

ETH_MII_TXD1/

34 J1 52 74 P13 93

I/O FT

OTG_HS_VBUS

EVENTOUT

SPI2_MISO/ TIM1_CH2N

/ TIM12_CH1 /

OTG_HS_DM/

USART3_RTS /

TIM8_CH2N/I2S2ext_SD/

EVENTOUT

35 J2 53 75 R14 94

PB14

PB15

I/O FT

SPI2_MOSI / I2S2_SD/

TIM1_CH3N / TIM8_CH3N

/ TIM12_CH2 /

36 H1 54 76 R15 95

I/O FT

RTC_REFIN

OTG_HS_DP/

EVENTOUT

FSMC_D13 /

USART3_TX/ EVENTOUT

-

H2 55 77 P15 96

H3 56 78 P14 97

G3 57 79 N15 98

PD8

PD9

I/O FT

FSMC_D14 /

USART3_RX/ EVENTOUT

FSMC_D15 /

USART3_CK/ EVENTOUT

PD10

FSMC_CLE /

FSMC_A16/USART3_CT

S/ EVENTOUT

-

G1 58 80 N14 99

G2 59 81 N13 100

PD11

PD12

I/O FT

FSMC_ALE/

FSMC_A17/TIM4_CH1 /

USART3_RTS/

EVENTOUT

52/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Pinouts and pin description

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

FSMC_A18/TIM4_CH2/

EVENTOUT

-

60 82 M15 101

PD13

I/O FT

-

83

-

102

V_SS

V_DD

S

84 J13 103

FSMC_D0/TIM4_CH3/

EVENTOUT/ EVENTOUT

-

F2 61 85 M14 104

F1 62 86 L14 105

PD14

PD15

I/O FT

FSMC_D1/TIM4_CH4/

EVENTOUT

-

87 L15 106

88 K15 107

89 K14 108

90 K13 109

91 J15 110

PG2

PG3

PG4

PG5

PG6

I/O FT

FSMC_A12/ EVENTOUT

FSMC_A13/ EVENTOUT

FSMC_A14/ EVENTOUT

FSMC_A15/ EVENTOUT

FSMC_INT2/ EVENTOUT

FSMC_INT3

/USART6_CK/

EVENTOUT

-

92 J14 111

93 H14 112

PG7

PG8

I/O FT

USART6_RTS /

ETH_PPS_OUT/

EVENTOUT

-

94 G12 113

95 H13 114

V_SS

V_DD

S

I2S2_MCK /

TIM8_CH1/SDIO_D6 /

USART6_TX /

37 F3 63 96 H15 115

PC6

I/O FT

DCMI_D0/TIM3_CH1/

EVENTOUT

I2S3_MCK /

TIM8_CH2/SDIO_D7 /

USART6_RX /

DCMI_D1/TIM3_CH2/

EVENTOUT

38 E1 64 97 G15 116

39 E2 65 98 G14 117

PC7

PC8

I/O FT

TIM8_CH3/SDIO_D0

/TIM3_CH3/ USART6_CK

/ DCMI_D2/ EVENTOUT

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Pinouts and pin description

STM32F415xx, STM32F417xx

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

I2S_CKIN/ MCO2 /

TIM8_CH4/SDIO_D1 /

/I2C3_SDA / DCMI_D3 /

TIM3_CH4/ EVENTOUT

40 E3 66 99 F14 118

41 D1 67 100 F15 119

PC9

PA8

I/O FT

MCO1 / USART1_CK/

TIM1_CH1/ I2C3_SCL/

OTG_FS_SOF/

EVENTOUT

USART1_TX/ TIM1_CH2 /

I2C3_SMBA / DCMI_D0/

EVENTOUT

42 D2 68 101 E15 120

43 D3 69 102 D15 121

PA9

I/O FT

OTG_FS_VBUS

USART1_RX/ TIM1_CH3/

OTG_FS_ID/DCMI_D1/

EVENTOUT

PA10

USART1_CTS / CAN1_RX

/ TIM1_CH4 /

44 C1 70 103 C15 122

45 C2 71 104 B15 123

PA11

PA12

I/O FT

OTG_FS_DM/

EVENTOUT

USART1_RTS /

CAN1_TX/ TIM1_ETR/

OTG_FS_DP/

I/O FT

EVENTOUT

PA13

JTMS-SWDIO/

EVENTOUT

46 D4 72 105 A15 124

47 B1 73 106 F13 125

(JTMS-SWDIO)

V_{CAP_2}

V_SS

S

-

E7 74 107 F12 126

48 E6 75 108 G13 127

V_DD

TIM8_CH1N / CAN1_TX/

EVENTOUT

-

E12 128

E13 129

D13 130

PH13

PH14

PH15

I/O FT

TIM8_CH2N / DCMI_D4/

EVENTOUT

TIM8_CH3N / DCMI_D11/

EVENTOUT

TIM5_CH4 / SPI2_NSS /

I2S2_WS / DCMI_D13/

EVENTOUT

-

C3

-

E14 131

PI0

I/O FT

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STM32F415xx, STM32F417xx

Pinouts and pin description

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

SPI2_SCK / I2S2_CK /

DCMI_D8/ EVENTOUT

-

B2

-

D14 132

C14 133

PI1

PI2

I/O FT

TIM8_CH4 /SPI2_MISO /

DCMI_D9 / I2S2ext_SD/

EVENTOUT

TIM8_ETR / SPI2_MOSI /

I2S2_SD / DCMI_D10/

EVENTOUT

-

C13 134

PI3

I/O FT

-

D9 135

C9 136

V_SS

V_DD

S

PA14

JTCK-SWCLK/

EVENTOUT

49 A2 76 109 A14 137

I/O FT

(JTCK/SWCLK)

JTDI/ SPI3_NSS/

I2S3_WS/TIM2_CH1_ET

R / SPI1_NSS /

PA15

50 B3 77 110 A13 138

I/O FT

(JTDI)

EVENTOUT

SPI3_SCK / I2S3_CK/

UART4_TX/SDIO_D2 /

DCMI_D8 / USART3_TX/

EVENTOUT

51 D5 78 111 B14 139

52 C4 79 112 B13 140

53 A3 80 113 A12 141

PC10

PC11

PC12

I/O FT

UART4_RX/ SPI3_MISO /

SDIO_D3 /

DCMI_D4/USART3_RX /

I2S3ext_SD/ EVENTOUT

UART5_TX/SDIO_CK /

DCMI_D9 / SPI3_MOSI

/I2S3_SD / USART3_CK/

EVENTOUT

FSMC_D2/CAN1_RX/

EVENTOUT

-

D6 81 114 B12 142

C5 82 115 C12 143

PD0

PD1

I/O FT

FSMC_D3 / CAN1_TX/

EVENTOUT

TIM3_ETR/UART5_RX/

SDIO_CMD / DCMI_D11/

EVENTOUT

54 B4 83 116 D12 144

PD2

I/O FT

DocID022063 Rev 4

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Pinouts and pin description

STM32F415xx, STM32F417xx

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

FSMC_CLK/

USART2_CTS/

EVENTOUT

-

84 117 D11 145

PD3

I/O FT

FSMC_NOE/

USART2_RTS/

EVENTOUT

-

A4 85 118 D10 146

C6 86 119 C11 147

PD4

PD5

I/O FT

FSMC_NWE/USART2_TX

/ EVENTOUT

-

120 D8 148

121 C8 149

V_SS

V_DD

S

FSMC_NWAIT/

USART2_RX/ EVENTOUT

-

B5 87 122 B11 150

A5 88 123 A11 151

PD6

PD7

I/O FT

USART2_CK/FSMC_NE1/

FSMC_NCE2/

EVENTOUT

USART6_RX /

FSMC_NE2/FSMC_NCE3

/ EVENTOUT

-

124 C10 152

125 B10 153

PG9

I/O FT

FSMC_NCE4_1/

FSMC_NE3/ EVENTOUT

PG10

FSMC_NCE4_2 /

ETH_MII_TX_EN/

ETH _RMII_TX_EN/

EVENTOUT

-

126 B9 154

127 B8 155

PG11

PG12

I/O FT

FSMC_NE4 /

USART6_RTS/

EVENTOUT

FSMC_A24 /

USART6_CTS

/ETH_MII_TXD0/

ETH_RMII_TXD0/

EVENTOUT

-

128 A8 156

129 A7 157

PG13

PG14

I/O FT

FSMC_A25 / USART6_TX

/ETH_MII_TXD1/

ETH_RMII_TXD1/

EVENTOUT

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STM32F415xx, STM32F417xx

Pinouts and pin description

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

-

E8

F7

-

130 D7 158

V_SS

V_DD

S

131 C7 159

132 B7 160

USART6_CTS /

DCMI_D13/ EVENTOUT

-

PG15

I/O FT

JTDO/ TRACESWO/

SPI3_SCK / I2S3_CK /

TIM2_CH2 / SPI1_SCK/

EVENTOUT

PB3

55 B6 89 133 A10 161

56 A6 90 134 A9 162

I/O FT

(JTDO/

TRACESWO)

NJTRST/ SPI3_MISO /

TIM3_CH1 / SPI1_MISO /

I2S3ext_SD/ EVENTOUT

PB4

I/O FT

(NJTRST)

I2C1_SMBA/ CAN2_RX /

OTG_HS_ULPI_D7 /

ETH_PPS_OUT/TIM3_CH

2 / SPI1_MOSI/

SPI3_MOSI / DCMI_D10 /

I2S3_SD/ EVENTOUT

57 D7 91 135 A6 163

PB5

PB6

I2C1_SCL/ TIM4_CH1 /

CAN2_TX /

DCMI_D5/USART1_TX/

EVENTOUT

58 C7 92 136 B6 164

I/O FT

I2C1_SDA / FSMC_NL /

DCMI_VSYNC /

USART1_RX/ TIM4_CH2/

EVENTOUT

59 B7 93 137 B5 165

60 A7 94 138 D6 166

PB7

BOOT0

I

B

V_PP

TIM4_CH3/SDIO_D4/

TIM10_CH1 / DCMI_D6 /

ETH_MII_TXD3 /

I2C1_SCL/ CAN1_RX/

EVENTOUT

61 D8 95 139 A5 167

PB8

PB9

I/O FT

SPI2_NSS/ I2S2_WS /

TIM4_CH4/ TIM11_CH1/

SDIO_D5 / DCMI_D7 /

I2C1_SDA / CAN1_TX/

EVENTOUT

62 C8 96 140 B4 168

DocID022063 Rev 4

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Pinouts and pin description

STM32F415xx, STM32F417xx

Table 7. STM32F41x pin and ball definitions (continued)

Pin number

Pin name

Alternate functions

Additional functions

(function after

reset)⁽¹⁾

TIM4_ETR / FSMC_NBL0

/ DCMI_D2/ EVENTOUT

-

97 141 A4 169

98 142 A3 170

PE0

PE1

I/O FT

FSMC_NBL1 / DCMI_D3/

EVENTOUT

I/O FT

S

63

-

99

-

D5

-

V_SS

A8

143 C6 171

144 C5 172

PDR_ON

I

FT

10

0

64 A1

V_DD

PI4

S

TIM8_BKIN / DCMI_D5/

EVENTOUT

-

D4 173

C4 174

I/O FT

TIM8_CH1 /

DCMI_VSYNC/

EVENTOUT

PI5

TIM8_CH2 / DCMI_D6/

EVENTOUT

-

C3 175

C2 176

PI6

PI7

I/O FT

TIM8_CH3 / DCMI_D7/

EVENTOUT

1. Function availability depends on the chosen device.

2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (e.g. to drive an LED).

3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after

reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC

register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website:

www.st.com.

4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset

ON mode), then PA0 is used as an internal Reset (active low).

Table 8. FSMC pin definition

FSMC

WLCSP90

Pins⁽¹⁾

LQFP100⁽²⁾

(2)

NOR/PSRAM/

SRAM

CF

NOR/PSRAM Mux NAND 16 bit

PE2

PE3

A23

A19

A23

A19

Yes

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STM32F415xx, STM32F417xx

Pinouts and pin description

Table 8. FSMC pin definition (continued)

FSMC

WLCSP90

Pins⁽¹⁾

CF

LQFP100⁽²⁾

(2)

NOR/PSRAM/

SRAM

NOR/PSRAM Mux NAND 16 bit

PE4

PE5

PE6

A20

A21

A22

A0

A20

A21

A22

Yes

PF0

PF1

A0

A1

-

A1

-

PF2

A2

-

PF3

A3

-

PF4

A4

PF5

A5

-

PF6

NIORD

NREG

NIOWR

CD

-

PF7

-

PF8

-

PF9

-

PF10

PF12

PF13

PF14

PF15

PG0

PG1

PE7

INTR

A6

-

A6

A7

-

A7

-

A8

-

A9

-

A10

A11

D4

-

D4

D5

DA4

DA5

D4

D5

Yes

PE8

D5

PE9

D6

DA6

D6

PE10

PE11

PE12

PE13

PE14

PE15

PD8

PD9

PD10

PD11

D7

DA7

D7

D8

DA8

D8

D9

DA9

D9

D10

D11

D12

D13

D14

D15

D10

D11

D12

D13

D14

D15

A16

DA10

DA11

DA12

DA13

DA14

DA15

A16

D10

D11

D12

D13

D14

D15

CLE

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Pinouts and pin description

STM32F415xx, STM32F417xx

Table 8. FSMC pin definition (continued)

FSMC

WLCSP90

Pins⁽¹⁾

CF

LQFP100⁽²⁾

(2)

NOR/PSRAM/

SRAM

NOR/PSRAM Mux NAND 16 bit

PD12

PD13

A17

A18

D0

A17

A18

DA0

DA1

ALE

Yes

-

Yes

PD14

PD15

PG2

PG3

PG4

PG5

PG6

PG7

PD0

PD1

PD3

PD4

PD5

PD6

PD7

PG9

PG10

PG11

PG12

PG13

PG14

PB7

D0

D1

D0

D1

Yes

D1

Yes

A12

A13

A14

A15

-

INT2

INT3

D2

-

D2

D3

D2

D3

DA2

DA3

Yes

-

Yes

D3

CLK

NOE

NWE

NWAIT

NE1

NE2

NE3

CLK

NOE

NWE

NOE

NWE

NWAIT

NE1

NOE

NWE

Yes

NWAIT

NCE2

NCE3

Yes

NE2

-

NCE4_1

NCE4_2

NE3

-

NE4

A24

NE4

A24

-

A25

-

NADV

NBL0

NBL1

NADV

NBL0

NBL1

Yes

PE0

PE1

1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on

smaller packages are given in the dedicated package column.

2. Ports F and G are not available in devices delivered in 100-pin packages.

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DocID022063 Rev 4

Memory mapping

STM32F415xx, STM32F417xx

4

Memory mapping

The memory map is shown in Figure 18.

Figure 18. STM32F41x memory map

0xE010 0000 - 0xFFFF FFFF

Reserved

0xE000 0000 - 0xE00F FFFF

CORTEX-M4 internal peripherals

Reserved

AHB3

0xA000 1000 - 0xDFFF FFFF

0xA000 0FFF

0x6000 0000

0x5006 0C00 - 0x5FFF FFFF

Reserved

0x5006 0BFF

AHB2

0xFFFF FFFF

512-Mbyte

block 7

0x5000 0000

0x4008 0000 - 0x4FFF FFFF

0x4007 FFFF

Cortex-M4's

internal

peripherals

Reserved

0xE000 0000

0xDFFF FFFF

512-Mbyte

block 6

Not used

0xC000 0000

0xBFFF FFFF

AHB1

512-Mbyte

block 5

FSMC registers

0xA000 0000

0x9FFF FFFF

512-Mbyte

block 4

0x4002 000

0x4001 5800 - 0x4001 FFFF

0x4001 57FF

Reserved

FSMC bank 3

& bank4

0x8000 0000

0x7FFF FFFF

512-Mbyte

block 3

FSMC bank1

& bank2

0x6000 0000

0x5FFF FFFF

512-Mbyte

block 2

Peripherals

APB2

0x4000 0000

0x3FFF FFFF

512-Mbyte

block 1

SRAM

0x4001 0000

0x4000 7800 - 0x4000 FFFF

0x4000 7FFF

Reserved

0x2002 0000 - 0x3FFF FFFF

0x2001 C000 - 0x2001 FFFF

0x2000 0000

0x1FFF FFFF

Reserved

SRAM (16 KB aliased

by bit-banding)

512-Mbyte

block 0

Code

SRAM (112 KB aliased

by bit-banding)

0x2000 0000 - 0x2001 BFFF

0x0000 0000

Reserved

Option Bytes

Reserved

0x1FFF C008 - 0x1FFF FFFF

0x1FFF C000 - 0x1FFF C007

0x1FFF 7A10 - 0x1FFF 7FFF

System memory + OTP 0x1FFF 0000 - 0x1FFF 7A0F

0x1001 0000 - 0x1FFE FFFF

0x1000 0000 - 0x1000 FFFF

0x0810 0000 - 0x0FFF FFFF

Reserved

CCM data RAM

(64 KB data SRAM)

APB1

Reserved

Flash

0x0800 0000 - 0x080F FFFF

Reserved

0x0010 0000 - 0x07FF FFFF

Aliased to Flash, system

memory or SRAM depending

on the BOOT pins

0x0000 0000 - 0x000F FFFF

0x4000 0000

ai18513f

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Memory mapping

Table 10. STM32F41x register boundary addresses

Bus

Boundary address

Peripheral

0xE00F FFFF - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

0xA000 1000 - 0xDFFF FFFF

0xA000 0000 - 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

0x8000 0000 - 0x8FFF FFFF

0x7000 0000 - 0x7FFF FFFF

0x6000 0000 - 0x6FFF FFFF

0x5006 0C00- 0x5FFF FFFF

0x5006 0800 - 0x5006 0BFF

0x5006 0400 - 0x5006 07FF

0x5006 0000 - 0x5006 03FF

0x5005 0400 - 0x5005 FFFF

0x5005 0000 - 0x5005 03FF

0x5004 0000- 0x5004 FFFF

0x5000 0000 - 0x5003 FFFF

0x4008 0000- 0x4FFF FFFF

Reserved

Cortex-M4

Cortex-M4 internal peripherals

Reserved

FSMC control register

FSMC bank 4

FSMC bank 3

FSMC bank 2

FSMC bank 1

Reserved

AHB3

RNG

HASH

CRYP

AHB2

Reserved

DCMI

Reserved

USB OTG FS

Reserved

DocID022063 Rev 4

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Memory mapping

STM32F415xx, STM32F417xx

Table 10. STM32F41x register boundary addresses (continued)

Bus

Boundary address

Peripheral

0x4004 0000 - 0x4007 FFFF

0x4002 9400 - 0x4003 FFFF

0x4002 9000 - 0x4002 93FF

0x4002 8C00 - 0x4002 8FFF

0x4002 8800 - 0x4002 8BFF

0x4002 8400 - 0x4002 87FF

0x4002 8000 - 0x4002 83FF

0x4002 6800 - 0x4002 7FFF

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 5000 - 0x4002 5FFF

0x4002 4000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3400 - 0x4002 37FF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1C00 - 0x4002 1FFF

0x4002 1800 - 0x4002 1BFF

0x4002 1400 - 0x4002 17FF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

0x4001 5800- 0x4001 FFFF

USB OTG HS

Reserved

ETHERNET MAC

Reserved

DMA2

DMA1

Reserved

BKPSRAM

Flash interface register

RCC

AHB1

Reserved

CRC

Reserved

GPIOI

GPIOH

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

Reserved

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STM32F415xx, STM32F417xx

Memory mapping

Table 10. STM32F41x register boundary addresses (continued)

Bus

Boundary address

Peripheral

0x4001 4C00 - 0x4001 57FF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2400 - 0x4001 2BFF

0x4001 2000 - 0x4001 23FF

0x4001 1800 - 0x4001 1FFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0800 - 0x4001 0FFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 7800- 0x4000 FFFF

Reserved

TIM11

TIM10

TIM9

EXTI

SYSCFG

Reserved

SPI1

APB2

SDIO

Reserved

ADC1 - ADC2 - ADC3

Reserved

USART6

USART1

Reserved

TIM8

TIM1

Reserved

DocID022063 Rev 4

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Memory mapping

STM32F415xx, STM32F417xx

Table 10. STM32F41x register boundary addresses (continued)

Bus

Boundary address

Peripheral

0x4000 7800 - 0x4000 7FFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

Reserved

DAC

PWR

Reserved

CAN2

CAN1

Reserved

I2C3

I2C2

I2C1

UART5

UART4

USART3

USART2

I2S3ext

SPI3 / I2S3

SPI2 / I2S2

I2S2ext

IWDG

APB1

WWDG

RTC & BKP Registers

Reserved

TIM14

TIM13

TIM12

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

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STM32F415xx, STM32F417xx

Electrical characteristics

5

Electrical characteristics

5.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

5.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean±3Σ).

5.1.2

5.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the

A

DD

1.8 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean±2Σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

5.1.4

5.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 19.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 20.

Figure 19. Pin loading conditions

Figure 20. Pin input voltage

STM32F pin

V

OSC_OUT (Hi-Z when

using HSE or LSE)

IN

C =50 pF

OSC_OUT (Hi-Z when

using HSE or LSE)

MS19010V1

MS19011V1

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Electrical characteristics

STM32F415xx, STM32F417xx

5.1.6

Power supply scheme

Figure 21. Power supply scheme

VBAT

Backup circuitry

VBAT =

1.65 to 3.6V

(OSC32K,RTC,

Wakeup logic

Power

switch

Backup registers,

backup RAM)

OUT

IN

IO

Logic

GPIOs

VCAP_1

VCAP_2

Kernel logic

(CPU, digital

& RAM)

2 × 2.2 μF

VDD

1/2/...14/15

Voltage

regulator

15 × 100 nF

+ 1 × 4.7 μF

VSS

1/2/...14/15

Flash memory

BYPASS_REG

PDR_ON

VDDA

Reset

controller

VDD

VREF

VREF+

Analog:

RCs,

PLL,..

100 nF

+ 1 μF

100 nF

+ 1 μF

ADC

VREF-

VSSA

MS19911V2

1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These

capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the

PCB to ensure the good functionality of the device.

2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.16: Voltage regulator and Table 2.2.15:

Power supply supervisor.

3. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the

voltage regulator is OFF.

4. The 4.7 µF ceramic capacitor must be connected to one of the V_DDpin.

5. V_DDA=V_DDand V_SSA=V_SS

.

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Electrical characteristics

5.1.7

Current consumption measurement

Figure 22. Current consumption measurement scheme

I

_V

DD BAT

V

BAT

I

DD

V

DD

V

DDA

ai14126

5.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,

Table 12: Current characteristics, and Table 13: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Table 11. Voltage characteristics

Symbol

_DD–V_SS

Ratings

Min

Max

Unit

(1)

V

External main supply voltage (including V_DDA, V_DD

Input voltage on five-volt tolerant pin⁽²⁾

Input voltage on any other pin

)

–0.3

4.0

V_DD+4

4.0

V_SS–0.3

V

V_IN

|ΔV_DDx

V

_SS–0.3

|

Variations between different V_DDpower pins

Variations between all the different ground pins

-

50

mV

|V_SSX− V_SS

|

50

see Section 5.3.14:

Absolute maximum

ratings (electrical

sensitivity)

V_ESD(HBM)

Electrostatic discharge voltage (human body model)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. V_INmaximum value must always be respected. Refer to Table 12 for the values of the maximum allowed

injected current.

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Electrical characteristics

Symbol

STM32F415xx, STM32F417xx

Table 12. Current characteristics

Ratings

Max.

Unit

I_VDD

I_VSS

Total current into V_DDpower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on five-volt tolerant I/O⁽³⁾

Injected current on any other pin⁽⁴⁾

150

25

I_IO

25

mA

–5/+0

±5

(2)

I_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁵⁾

±25

(4)

ΣI_INJ(PIN)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC

characteristics.

3. Positive injection is not possible on these I/Os. A negative injection is induced by V_IN<V_SS. I_INJ(PIN)must

never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.

4. A positive injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS. I_INJ(PIN)must

never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.

5. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

Symbol

Ratings

Value

Unit

T_STG

T_J

Storage temperature range

–65 to +150

125

°C

Maximum junction temperature

5.3

Operating conditions

5.3.1

General operating conditions

Table 14. General operating conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOS bit in PWR_CR register = 0⁽¹⁾

VOS bit in PWR_CR register= 1

0

144

168

42

f_HCLK

Internal AHB clock frequency

MHz

f_PCLK1Internal APB1 clock frequency

f_PCLK2Internal APB2 clock frequency

84

V_DD

Standard operating voltage

1.8⁽²⁾

3.6

V

Analog operating voltage

(ADC limited to 1.2 M samples)

1.8⁽²⁾

2.4

Must be the same potential as

V_DD

(3)(4)

V_DDA

(5)

Analog operating voltage

(ADC limited to 1.4 M samples)

2.4

3.6

V_BAT

Backup operating voltage

1.65

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Electrical characteristics

Table 14. General operating conditions (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOS bit in PWR_CR register = 0⁽¹⁾

Max frequency 144MHz

1.08

1.14

1.20

V

Regulator ON:

1.2 V internal voltage on

V_{CAP_1}/V_{CAP_2}pins

VOS bit in PWR_CR register= 1

Max frequency 168MHz

1.20

1.10

1.26

1.14

1.32

1.20

V

V₁₂

Regulator OFF:

Max frequency 144MHz

1.2 V external voltage must be

supplied from external regulator

on V_{CAP_1}/V_{CAP_2}pins

Max frequency 168MHz

1.20

1.26

1.30

V

2 V ≤ V_DD≤ 3.6 V

V_DD≤ 2 V

–0.3

-

5.5

5.2

Input voltage on RST and FT

pins⁽⁶⁾

V_IN

V

V_DDA

0.3

+

Input voltage on TTa pins

Input voltage on B pin

–0.3

-

5.5

435

465

500

526

513

543

85

LQFP64

-

LQFP100

Power dissipation at T_A= 85 °C

for suffix 6 or T_A= 105 °C for

suffix 7⁽⁷⁾

LQFP144

-

P_D

mW

LQFP176

-

UFBGA176

-

WLCSP90

-

Maximum power dissipation

Low power dissipation⁽⁸⁾

Maximum power dissipation

Low power dissipation⁽⁸⁾

6 suffix version

7 suffix version

–40

Ambient temperature for 6 suffix

version

°C

105

125

105

125

TA

TJ

Ambient temperature for 7 suffix

version

Junction temperature range

1. The average expected gain in power consumption when VOS = 0 compared to VOS = 1 is around 10% for the whole

temperature range, when the system clock frequency is between 30 and 144 MHz.

2. V_DD/V_DDAminimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of

an external power supply supervisor (refer to Section : Internal reset OFF).

3. When the ADC is used, refer to Table 67: ADC characteristics.

4. If V_REF+pin is present, it must respect the following condition: V_DDA-V_REF+< 1.2 V.

5. It is recommended to power V_DDand V_DDAfrom the same source. A maximum difference of 300 mV between V_DDand

V

_DDAcan be tolerated during power-up and power-down operation.

6. To sustain a voltage higher than V_DD+0.3, the internal pull-up and pull-down resistors must be disabled.

7. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax

8. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax

.

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Electrical characteristics

STM32F415xx, STM32F417xx

Table 15. Limitations depending on the operating power supply range

Maximum

Flash

memory

access

frequency

with no wait

state

Maximum Flash

memory access

frequency

Operating

power

supply

range

Possible

Flash

memory

operations

Clock output

I/O operation Frequency on

I/O pins

ADC

operation

with wait

states^{(1) (2)}

(f_Flashmax

)

– Degraded

speed

performance

up to 30 MHz

– No I/O

compensation

8-bit erase

and program

operations

only

Conversion

time up to

1.2 Msps

V_DD=1.8 to

2.1 V⁽³⁾

160 MHz with 7

wait states

20 MHz⁽⁴⁾

– Degraded

speed

performance

Conversion

time up to

1.2 Msps

16-bit erase

and program

operations

V_DD= 2.1 to

2.4 V

168 MHz with 7

wait states

22 MHz

up to 30 MHz

up to 48 MHz

– No I/O

compensation

– Degraded

speed

performance

Conversion

time up to

2.4 Msps

16-bit erase

and program

operations

V_DD= 2.4 to

2.7 V

168 MHz with 6

wait states

24 MHz

– I/O

compensation

works

– up to

60 MHz

when V_DD

– Full-speed

operation

=

Conversion

time up to

2.4 Msps

32-bit erase

and program

operations

3.0 to 3.6 V

V_DD= 2.7 to

3.6 V⁽⁵⁾

168 MHz with 5

wait states

30 MHz

– I/O

compensation

works

– up to

48 MHz

when V_DD

=

2.7 to 3.0 V

1. It applies only when code executed from Flash memory access, when code executed from RAM, no

wait state is required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here

does not impact the execution speed from Flash memory since the ART accelerator allows to achieve

a performance equivalent to 0 wait state program execution.

3. V_DD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use

of an external power supply supervisor (refer to Section : Internal reset OFF).

4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.

5. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.

5.3.2

V

/V

external capacitor

CAP_1 CAP_2

Stabilization for the main regulator is achieved by connecting an external capacitor C

to

EXT

the V

/V

pins. C

is specified in Table 16.

EXT

CAP_1 CAP_2

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Electrical characteristics

Figure 23. External capacitor C

EXT

C

ESR

R _Leak

MS19044V2

1. Legend: ESR is the equivalent series resistance.

(1)

Table 16. V

/V

operating conditions

CAP_1 CAP_2

Symbol

Parameter

Conditions

CEXT

ESR

Capacitance of external capacitor

ESR of external capacitor

2.2 µF

< 2 Ω

1. When bypassing the voltage regulator, the two 2.2 µF V_CAPcapacitors are not required and should be

replaced by two 100 nF decoupling capacitors.

5.3.3

Operating conditions at power-up / power-down (regulator ON)

Subject to general operating conditions for T .

A

Table 17. Operating conditions at power-up / power-down (regulator ON)

Symbol

Parameter

V_DDrise time rate

V_DDfall time rate

Min

Max

Unit

20

∞

t_VDD

µs/V

5.3.4

Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for T .

A

(1)

Table 18. Operating conditions at power-up / power-down (regulator OFF)

Symbol

Parameter

Conditions

Power-up

Min

Max Unit

V_DDrise time rate

20

∞

t_VDD

V

_DDfall time rate

Power-down

Power-up

V_{CAP_1}and V_{CAP_2}rise time

rate

µs/V

20

∞

t_VCAP

V_{CAP_1}and V_{CAP_2}fall time

rate

Power-down

∞

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V_DDreach below

minimum value of V₁₂

.

5.3.5

Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 14.

DD

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Electrical characteristics

STM32F415xx, STM32F417xx

Table 19. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

PLS[2:0]=000 (rising

edge)

2.09

2.14 2.19

2.04 2.08

2.30 2.37

2.19 2.25

2.45 2.51

V

PLS[2:0]=000 (falling

edge)

1.98

2.23

2.13

2.39

2.29

PLS[2:0]=001 (rising

edge)

PLS[2:0]=001 (falling

edge)

PLS[2:0]=010 (rising

edge)

PLS[2:0]=010 (falling

edge)

2.35 2.39

2.60 2.65

2.51 2.56

V

PLS[2:0]=011 (rising edge) 2.54

PLS[2:0]=011 (falling

edge)

2.44

Programmable voltage

detector level selection

V_PVD

PLS[2:0]=100 (rising

2.70

2.76 2.82

2.66 2.71

2.93 2.99

V

edge)

PLS[2:0]=100 (falling

edge)

2.59

PLS[2:0]=101 (rising

edge)

2.86

PLS[2:0]=101 (falling

edge)

2.65

2.84 3.02

3.03 3.10

2.93 2.99

3.14 3.21

3.03 3.09

V

PLS[2:0]=110 (rising edge) 2.96

PLS[2:0]=110 (falling

edge)

2.85

PLS[2:0]=111 (rising edge) 3.07

PLS[2:0]=111 (falling

edge)

2.95

(1)

V_PVDhyst

PVD hysteresis

-

100

-

mV

V

Falling edge

Rising edge

1.60

1.64

-

1.68 1.76

1.72 1.80

Power-on/power-down

reset threshold

V_POR/PDR

V

(1)

V_PDRhyst

PDR hysteresis

40

-

mV

V

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

2.13

2.23

2.44

2.53

2.75

2.85

2.19 2.24

2.29 2.33

2.50 2.56

2.59 2.63

2.83 2.88

2.92 2.97

Brownout level 1

threshold

V_BOR1

V_BOR2

V_BOR3

V

Brownout level 2

threshold

V

Brownout level 3

threshold

V

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Electrical characteristics

Table 19. Embedded reset and power control block characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ Max Unit

(1)

V_BORhyst

BOR hysteresis

-

100

1.5

-

mV

ms

(1)(2)

T_RSTTEMPO

Reset temporization

0.5

3.0

InRush current on

voltage regulator

power-on (POR or

wakeup from Standby)

(1)

I_RUSH

-

160

-

200

mA

µC

InRush energy on

voltage regulator

power-on (POR or

wakeup from Standby)

V_DD= 1.8 V, T_A= 105 °C,

I_RUSH= 171 mA for 31 µs

E_RUSH

5.4

1. Guaranteed by design, not tested in production.

2. The reset temporization is measured from the power-on (POR reset or wakeup from V_BAT) to the instant

when first instruction is read by the user application code.

5.3.6

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 22: Current consumption

measurement scheme.

All Run mode current consumption measurements given in this section are performed using

a CoreMark-compliant code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

•

At startup, all I/O pins are configured as analog inputs by firmware.

All peripherals are disabled except if it is explicitly mentioned.

The Flash memory access time is adjusted to f

frequency (0 wait state from 0 to

HCLK

30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states

from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to

168 MHz).

•

When the peripherals are enabled HCLK is the system clock, f

= f

/4, and

PCLK1

HCLK

f

= f

/2, except is explicitly mentioned.

PCLK2

HCLK

The maximum values are obtained for V = 3.6 V and maximum ambient temperature

DD

(T ), and the typical values for T = 25 °C and V = 3.3 V unless otherwise specified.

A

DD

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Electrical characteristics

STM32F415xx, STM32F417xx

Table 20. Typical and maximum current consumption in Run mode, code with data processing

(1)

running from Flash memory (ART accelerator enabled) or RAM

Typ

Max⁽²⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A=

25 °C

85 °C 105 °C

168 MHz

144 MHz

120 MHz

90 MHz

60 MHz

30 MHz

25 MHz

16 MHz⁽⁶⁾

8 MHz

87

67

56

44

30

16

12

9

102

80

69

56

42

28

24

20

17

15

14

54

43

38

32

26

20

18

16

15

14

109

86

75

62

49

35

31

28

24

22

21

61

50

45

39

33

27

25

24

22

21

External clock⁽³⁾, all

peripherals enabled⁽⁴⁾⁽⁵⁾

5

4 MHz

3

2 MHz

2

Supply current in

Run mode

I_DD

mA

168 MHz

144 MHz

120 MHz

90 MHz

60 MHz

30 MHz

25 MHz

16 MHz⁽⁶⁾

8 MHz

40

31

26

20

14

8

External clock⁽³⁾, all

peripherals disabled⁽⁴⁾⁽⁵⁾

6

5

3

4 MHz

2

2 MHz

2

1. Code and data processing running from SRAM1 using boot pins.

2. Based on characterization, tested in production at V_DDmax and f_HCLKmax with peripherals enabled.

3. External clock is 4 MHz and PLL is on when f_HCLK> 25 MHz.

4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for

the analog part.

5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption

should be considered.

6. In this case HCLK = system clock/2.

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Electrical characteristics

Table 21. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator disabled)

Typ

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A= 25 °C T_A= 85 °C T_A= 105 °C

168 MHz

144 MHz

120 MHz

90 MHz

60 MHz

30 MHz

25 MHz

16 MHz

8 MHz

93

76

67

53

37

20

16

11

6

109

89

79

65

49

32

27

23

18

16

15

61

52

48

42

33

24

21

19

16

15

14

117

96

86

73

56

39

35

30

25

23

22

69

60

56

50

41

31

29

26

23

22

21

External clock⁽²⁾

all peripherals

enabled⁽³⁾⁽⁴⁾

,

4 MHz

4

2 MHz

3

Supply current

in Run mode

I_DD

mA

168 MHz

144 MHz

120 MHz

90 MHz

60 MHz

30 MHz

25 MHz

16 MHz

8 MHz

46

40

37

30

22

12

10

7

External clock⁽²⁾

all peripherals

disabled⁽³⁾⁽⁴⁾

,

4

4 MHz

3

2 MHz

2

1. Based on characterization, tested in production at V_DDmax and f_HCLKmax with peripherals enabled.

2. External clock is 4 MHz and PLL is on when f_HCLK> 25 MHz.

3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption

should be considered.

4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC

for the analog part.

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Electrical characteristics

STM32F415xx, STM32F417xx

Figure 24. Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF

50

45

40

35

-45°C

0°C

30

25

20

15

10

5

25°C

55°C

85°C

105°C

0

20

40

60

80

100

120

140

160

180

CPU Frequency (MHz

MS19974V1

Figure 25. Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator ON) or RAM, and peripherals ON

100

90

80

70

-45°C

0°C

60

50

40

30

20

10

0

25°C

55°C

85°C

105°C

0

20

40

60

80

100

120

140

160

180

CPU Frequency (MHz

MS19975V1

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Electrical characteristics

Figure 26. Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF

60

50

40

-45°C

0°C

30

25°C

55°C

20

10

0

85°C

105°C

0

20

40

60

80

100

120

140

160

180

CPU Frequency (MHz

MS19976V1

Figure 27. Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON

120

100

80

-45°C

0°C

60

25°C

55°C

40

20

0

85°C

105°C

0

20

40

60

80

100

120

140

160

180

CPU Frequency (MHz

MS19977V1

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Electrical characteristics

STM32F415xx, STM32F417xx

Table 22. Typical and maximum current consumption in Sleep mode

Typ

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Unit

T_A=

25 °C

85 °C

105 °C

168 MHz

144 MHz

120 MHz

90 MHz

60 MHz

30 MHz

25 MHz

16 MHz

8 MHz

59

46

38

30

20

11

8

77

61

53

44

34

24

21

18

16

15

14

27

22

20

19

17

16

15

14

13

84

67

60

51

41

31

28

25

23

22

21

35

29

28

26

24

23

22

21

External clock⁽²⁾

,

all peripherals enabled⁽³⁾

6

3

4 MHz

2

2 MHz

2

Supply current in

Sleep mode

I_DD

mA

168 MHz

144 MHz

120 MHz

90 MHz

60 MHz

30 MHz

25 MHz

16 MHz

8 MHz

12

9

8

7

5

External clock⁽²⁾, all

peripherals disabled

3

2

1

4 MHz

1

2 MHz

1

1. Based on characterization, tested in production at V_DDmax and f_HCLKmax with peripherals enabled.

2. External clock is 4 MHz and PLL is on when f_HCLK> 25 MHz.

3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only

while the ADC is ON (ADON bit is set in the ADC_CR2 register).

88/186

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STM32F415xx, STM32F417xx

Electrical characteristics

Table 23. Typical and maximum current consumptions in Stop mode

Typ

Max

Symbol

Parameter

Conditions

Unit

T_A=

25 °C 25 °C 85 °C 105 °C

Flash in Stop mode, low-speed and high-

speed internal RC oscillators and high-speed

oscillator OFF (no independent watchdog)

Supply

0.45

0.40

0.31

0.28

1.5

1.1

11.00 20.00

current in

Stop mode

with main

regulator in

Run mode

Flash in Deep power down mode, low-speed

and high-speed internal RC oscillators and

high-speed oscillator OFF (no independent

watchdog)

I_{DD_STOP}

mA

Flash in Stop mode, low-speed and high-

speed internal RC oscillators and high-speed

oscillator OFF (no independent watchdog)

Supply

8.00

15.00

current in

Stop mode

with main

regulator in

Low Power

mode

Flash in Deep power down mode, low-speed

and high-speed internal RC oscillators and

high-speed oscillator OFF (no independent

watchdog)

Table 24. Typical and maximum current consumptions in Standby mode

Typ

Max⁽¹⁾

T_A=

85 °C

T_A=

105 °C

T_A= 25 °C

Symbol

Parameter

Conditions

Unit

V_DD

1.8 V

=

V_DD

2.4 V

=

V_DD=

3.3 V

V_DD= 3.6 V

Backup SRAM ON, low-

speed oscillator and RTC ON

3.0

3.4

4.0

20

36

32

Backup SRAM OFF, low-

speed oscillator and RTC ON

2.4

1.7

2.7

2.6

1.9

3.3

3.0

2.2

16

12.5

9.8

Supply current

I_{DD_STBY}in Standby

mode

µA

Backup SRAM ON, RTC

OFF

24.8

19.2

Backup SRAM OFF, RTC

OFF

1. Based on characterization, not tested in production.

DocID022063 Rev 4

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Electrical characteristics

STM32F415xx, STM32F417xx

Table 25. Typical and maximum current consumptions in V

mode

Max⁽¹⁾

BAT

Typ

T_A=

85 °C

T_A=

105 °C

T_A= 25 °C

Symbol Parameter

Conditions

Unit

V_BAT

=

1.8 V

V_BAT

=

3.3 V

V_BAT

2.4 V

=

V_BAT= 3.6 V

Backup SRAM ON, low-speed

oscillator and RTC ON

1.29

0.62

1.42

0.73

1.68

0.96

6

3

11

5

Backup

I_{DD_VBA}domain

Backup SRAM OFF, low-speed

oscillator and RTC ON

µA

supply

current

T

Backup SRAM ON, RTC OFF

Backup SRAM OFF, RTC OFF

0.79

0.10

0.81

0.10

0.86

0.10

5

2

10

4

1. Based on characterization, not tested in production.

Figure 28. Typical V

current consumption (LSE and RTC ON/backup RAM OFF)

BAT

3.5

3

2.5

2

1.65V

1.8V

2V

2.4V

2.7V

3V

1.5

1

3.3V

3.6V

0.5

0

10

20

30

40

50

60

70

80

90

100

Te mpe r at ur e i n (° C)

MS19990V1

90/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Electrical characteristics

Figure 29. Typical V

current consumption (LSE and RTC ON/backup RAM ON)

BAT

6

5

4

3

2

1

0

1.65V

1.8V

2V

2.4V

2.7V

3V

3.3V

3.6V

0

10

20

30

40

50

60

70

80

90

100

Te mpe r at ur e i n (° C)

MS19991V1

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is

externally held low. The value of this current consumption can be simply computed by using

the pull-up/pull-down resistors values given in Table 47: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to

estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate

voltage level is externally applied. This current consumption is caused by the input Schmitt

trigger circuits used to discriminate the input value. Unless this specific configuration is

required by the application, this supply current consumption can be avoided by configuring

these I/Os in analog mode. This is notably the case of ADC input pins which should be

configured as analog inputs.

Caution:

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to

floating pins, they must either be configured in analog mode, or forced internally to a definite

digital value. This can be done either by using pull-up/down resistors or by configuring the

pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 27: Peripheral current consumption), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the MCU

DocID022063 Rev 4

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Electrical characteristics

STM32F415xx, STM32F417xx

supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

I_SW= V_DD× f_SW× C

where

I

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage

SW

V

DD

f

is the I/O switching frequency

SW

C is the total capacitance seen by the I/O pin: C = C + C

INT

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed

frequency.

92/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Electrical characteristics

Table 26. Switching output I/O current consumption

I/O toggling

frequency (f_SW

Symbol

Parameter

Conditions⁽¹⁾

Typ

Unit

)

2 MHz

0.02

8 MHz

25 MHz

50 MHz

60 MHz

2 MHz

0.14

0.51

0.86

1.30

0.10

0.38

1.18

2.47

2.86

0.17

0.66

1.70

2.65

3.48

0.23

0.95

3.20

4.69

8.06

0.30

1.22

3.90

8.82

V_DD= 3.3 V⁽²⁾

C = C_INT

8 MHz

V_DD= 3.3 V

C_EXT= 0 pF

25 MHz

50 MHz

60 MHz

2 MHz

C = C_INT+ C_EXT+ C_S

8 MHz

V_DD= 3.3 V

I/O switching

current

I_DDIO

mA

C_EXT= 10 pF

25 MHz

50 MHz

60 MHz

2 MHz

C = C_INT+ C_EXT+ C_S

8 MHz

V_DD= 3.3 V

C_EXT= 22 pF

25 MHz

50 MHz

60 MHz

2 MHz

C = C_INT+ C_EXT+ C_S

8 MHz

V_DD= 3.3 V

C_EXT= 33 pF

25 MHz

50 MHz

60 MHz

C = C_INT+ C_EXT+ C_S

(3)

-

1. C_Sis the PCB board capacitance including the pad pin. C_S= 7 pF (estimated value).

2. This test is performed by cutting the LQFP package pin (pad removal).

3. At 60 MHz, C maximum load is specified 30 pF.

DocID022063 Rev 4

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Electrical characteristics

STM32F415xx, STM32F417xx

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 27. The MCU is placed

under the following conditions:

•

At startup, all I/O pins are configured as analog pins by firmware.

All peripherals are disabled unless otherwise mentioned

The code is running from Flash memory and the Flash memory access time is equal to

5 wait states at 168 MHz.

•

The code is running from Flash memory and the Flash memory access time is equal to

4 wait states at 144 MHz, and the power scale mode is set to 2.

•

ART accelerator and Cache off.

The given value is calculated by measuring the difference of current consumption

–

with all peripherals clocked off

with one peripheral clocked on (with only the clock applied)

•

When the peripherals are enabled: HCLK is the system clock, f

= f

/4, and

PCLK1

HCLK

f

= f

/2.

PCLK2

HCLK

The typical values are obtained for V = 3.3 V and T = 25 °C, unless otherwise

DD

A

specified.

Table 27. Peripheral current consumption

Peripheral⁽¹⁾

168 MHz

144 MHz

Unit

GPIO A

GPIO B

GPIO C

GPIO D

GPIO E

GPIO F

GPIO G

GPIO H

GPIO I

0.49

0.45

0.47

0.45

0.44

0.45

0.44

4.57

0.07

0.11

6.15

6.24

0.36

0.33

0.34

0.35

0.33

0.34

0.33

3.55

0.06

0.08

4.75

4.8

AHB1

mA

OTG_HS + ULPI

CRC

BKPSRAM

DMA1

DMA2

ETH_MAC +

ETH_MAC_TX

ETH_MAC_RX

ETH_MAC_PTP

3.28

2.54

OTG_FS

DCMI

4.59

1.04

3.69

0.80

AHB2

mA

94/186

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STM32F415xx, STM32F417xx

Electrical characteristics

Table 27. Peripheral current consumption (continued)

Peripheral⁽¹⁾

168 MHz

144 MHz

Unit

RNG

0.29

1.71

0.23

1.31

AHB2

AHB3

HASH

mA

CRYPTO

FSMC

0.41

0.31

2.18

1.67

TIM2

0.80

0.61

TIM3

0.58

0.44

TIM4

0.62

0.48

TIM5

0.79

0.61

TIM6

0.15

0.11

TIM7

0.16

0.12

TIM12

0.33

0.26

TIM13

0.27

0.21

TIM14

0.27

0.21

PWR

0.04

0.03

0.13

USART2

USART3

UART4

UART5

I2C1

0.17

0.13

0.17

0.13

mA

APB1

0.17

0.13

0.17

0.13

I2C2

0.18

0.13

I2C3

0.18

0.13

SPI2/I2S2⁽²⁾

SPI3/I2S3⁽²⁾

CAN1

0.17/0.16

0.16/0.14

0.27

0.13/0.12

0.12/0.12

0.21

CAN2

0.26

0.20

DAC

0.14

0.10

DAC channel 1⁽³⁾

DAC channel 2⁽⁴⁾

0.91

0.89

0.91

0.89

DAC channel 1 and

2⁽³⁾⁽⁴⁾

1.69

0.04

1.68

0.04

WWDG

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Electrical characteristics

STM32F415xx, STM32F417xx

Table 27. Peripheral current consumption (continued)

Peripheral⁽¹⁾

168 MHz

144 MHz

Unit

SDIO

0.64

1.47

1.58

0.68

0.45

0.47

2.20

2.04

2.10

0.14

0.34

0.54

1.14

1.22

0.54

0.36

0.38

2.10

1.93

2.00

0.12

0.27

0.28

TIM1

TIM8

TIM9

TIM10

TIM11

ADC1⁽⁵⁾

ADC2⁽⁵⁾

ADC3⁽⁵⁾

SPI1

APB2

mA

USART1

USART6

1. HSE oscillator with 4 MHz crystal and PLL are ON.

2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I²S peripheral.

3. EN1 bit is set in DAC_CR register.

4. EN2 bit is set in DAC_CR register.

5. ADON bit set in ADC_CR2 register.

5.3.7

Wakeup time from low-power mode

The wakeup times given in Table 28 is measured on a wakeup phase with a 16 MHz HSI

RC oscillator. The clock source used to wake up the device depends from the current

operating mode:

•

Stop or Standby mode: the clock source is the RC oscillator

Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V supply

DD

voltage conditions summarized in Table 14.

Table 28. Low-power mode wakeup timings

Symbol

Parameter

Wakeup from Sleep mode

Min⁽¹⁾

Typ⁽¹⁾Max⁽¹⁾Unit

(2)

t_WUSLEEP

-

1

-

µs

Wakeup from Stop mode (regulator in Run mode)

13

17

Wakeup from Stop mode (regulator in low power mode)

40

(2)

t_WUSTOP

Wakeup from Stop mode (regulator in low power mode

and Flash memory in Deep power down mode)

-

110

375

-

(2)(3)

t_WUSTDBY

Wakeup from Standby mode

260

480

1. Based on characterization, not tested in production.

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.

3. t_WUSTDBYminimum and maximum values are given at 105 °C and –45 °C, respectively.

96/186

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STM32F415xx, STM32F417xx

Electrical characteristics

5.3.8

External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Table 29 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 14.

Table 29. High-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

External user clock source

frequency⁽¹⁾

f_{HSE_ext}

1

-

50

MHz

V_HSEH

V_HSEL

t_w(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

0.7V_DD

V_SS

-

V_DD

V

0.3V_DD

OSC_IN high or low time⁽¹⁾

OSC_IN rise or fall time⁽¹⁾

5

-

t_w(HSE)

ns

t_r(HSE)

t_f(HSE)

10

C_in(HSE)OSC_IN input capacitance⁽¹⁾

-

45

-

5

-

pF

%

DuCy_(HSE)Duty cycle

55

±1

I_L

OSC_IN Input leakage current

V_SS≤ V_IN≤ V_DD

-

µA

1. Guaranteed by design, not tested in production.

Low-speed external user clock generated from an external source

The characteristics given in Table 30 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 14.

Table 30. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User External clock source

frequency⁽¹⁾

f_{LSE_ext}

-

32.768

1000

kHz

OSC32_IN input pin high level

voltage

V_LSEH

0.7V_DD

V_SS

-

V_DD

0.3V_DD

-

V

V_LSEL

t_w(LSE)

OSC32_IN input pin low level voltage

OSC32_IN high or low time⁽¹⁾

450

t_f(LSE)

ns

t_r(LSE)

t_f(LSE)

OSC32_IN rise or fall time⁽¹⁾

OSC32_IN input capacitance⁽¹⁾

-

50

C_in(LSE)

-

30

-

5

-

pF

%

DuCy_(LSE)Duty cycle

70

±1

I_L

OSC32_IN Input leakage current

V_SS≤ V_IN≤ V_DD

-

µA

1. Guaranteed by design, not tested in production.

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Electrical characteristics

STM32F415xx, STM32F417xx

Figure 30. High-speed external clock source AC timing diagram

V

HSEH

90%

10%

V

HSEL

t

W(HSE)

t

W(HSE)

r(HSE)

f(HSE)

T

HSE

f

HSE_ext

External

I

L

OSC _I N

clock source

STM32F

ai17528

Figure 31. Low-speed external clock source AC timing diagram

V

LSEH

90%

10%

V

LSEL

t

W(LSE)

t

W(LSE)

r(LSE)

f(LSE)

T

LSE

f

LSE_ext

External

I

L

OSC32_IN

clock source

STM32F

ai17529

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 31. In

the application, the resonator and the load capacitors have to be placed as close as

possible to the oscillator pins in order to minimize output distortion and startup stabilization

time. Refer to the crystal resonator manufacturer for more details on the resonator

characteristics (frequency, package, accuracy).

98/186

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STM32F415xx, STM32F417xx

Symbol

Electrical characteristics

(1) (2)

Table 31. HSE 4-26 MHz oscillator characteristics

Parameter

Conditions

Min

Typ

Max Unit

f_{OSC_IN}Oscillator frequency

4

-

26

-

MHz

R_F

Feedback resistor

200

kΩ

V_DD=3.3 V,

ESR= 30 Ω,

C_L=5 pF@25 MHz

-

449

532

-

I_DD

HSE current consumption

µA

V_DD=3.3 V,

ESR= 30 Ω,

C_L=10 pF@25 MHz

g_m

Oscillator transconductance

Startup time

Startup

5

-

mA/V

ms

(3)

t_SU(HSE

V_DDis stabilized

2

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

For C and C , it is recommended to use high-quality external ceramic capacitors in the

L1

L2

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 32). C and C are usually the

L1

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of C and C . PCB and MCU pin capacitance must be included (10 pF

L1

L2

can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C .

C

L1

L2

Note:

For information on electing the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 32. Typical application with an 8 MHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC_IN

HSE

Bias

controlled

gain

8 MHz

resonator

R

F

STM32F

OSC_OUT

(1)

R

EXT

C

L2

ai17530

1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 32. In

the application, the resonator and the load capacitors have to be placed as close as

possible to the oscillator pins in order to minimize output distortion and startup stabilization

time. Refer to the crystal resonator manufacturer for more details on the resonator

characteristics (frequency, package, accuracy).

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Electrical characteristics

Symbol

STM32F415xx, STM32F417xx

(1)

Table 32. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Parameter

Conditions

Min

Typ

Max

Unit

R_F

I_DD

Feedback resistor

-

18.4

-

1

-

MΩ

µA

LSE current consumption

Oscillator Transconductance

startup time

-

g_m

2.8

-

µA/V

s

(2)

t_SU(LSE)

V_DDis stabilized

2

-

1. Guaranteed by design, not tested in production.

2. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary

significantly with the crystal manufacturer

Note:

For information on electing the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 33. Typical application with a 32.768 kHz crystal

Resonator with

integrated capacitors

C

L1

f

OSC32_IN

LSE

Bias

controlled

gain

32.768 kHz

resonator

R

F

STM32F

OSC32_OUT

C

L2

ai17531

5.3.9

Internal clock source characteristics

The parameters given in Table 33 and Table 34 are derived from tests performed under

ambient temperature and V supply voltage conditions summarized in Table 14.

DD

High-speed internal (HSI) RC oscillator

(1)

Table 33. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ

Max Unit

f_HSI

-

16

-

MHz

%

User-trimmed with the RCC_CR

register

-

1

T_A= –40 to

Accuracy of the HSI

oscillator

–8

4.5

%

105 °C⁽²⁾

ACC_HSI

Factory-

calibrated

T_A= –10 to 85 °C⁽²⁾–4

-

4

1

%

T_A= 25 °C

–1

-

HSI oscillator

startup time

(3)

t_su(HSI)

2.2

60

4

µs

HSI oscillator

power consumption

I_DD(HSI)

-

80

µA

100/186

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Electrical characteristics

1. V_DD= 3.3 V, T_A= –40 to 105 °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Low-speed internal (LSI) RC oscillator

(1)

Table 34. LSI oscillator characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(2)

f_LSI

Frequency

17

-

32

15

47

40

kHz

µs

(3)

t_su(LSI)

LSI oscillator startup time

(3)

I_DD(LSI)

LSI oscillator power consumption

-

0.4

0.6

µA

1.

V_DD= 3 V, T_A= –40 to 105 °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Figure 34. ACC versus temperature

LSI

50

40

30

20

10

0

max

avg

min

-10

-20

-30

-40

-45 -35 -25 -15

-5

5

15

25

35

45

55

65

75

85

95 105

Temperature(°C)

MS19013V1

5.3.10

PLL characteristics

The parameters given in Table 35 and Table 36 are derived from tests performed under

temperature and V supply voltage conditions summarized in Table 14.

DD

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Electrical characteristics

STM32F415xx, STM32F417xx

Table 35. Main PLL characteristics

Conditions

Symbol

f_{PLL_IN}

Parameter

PLL input clock⁽¹⁾

Min

Typ

Max

Unit

0.95⁽²⁾

24

1

-

2.10

168

MHz

f_{PLL_OUT}

PLL multiplier output clock

48 MHz PLL multiplier output

clock

f_{PLL48_OUT}

f_{VCO_OUT}

-

48

75

MHz

PLL VCO output

192

75

100

-

432

200

300

-

VCO freq = 192 MHz

VCO freq = 432 MHz

t_LOCK

PLL lock time

µs

-

RMS

25

peak

to

peak

Cycle-to-cycle jitter

Period Jitter

-

150

15

-

System clock

120 MHz

RMS

peak

to

200

Jitter⁽³⁾

ps

peak

Main clock output (MCO) for

RMII Ethernet

Cycle to cycle at 50 MHz

on 1000 samples

-

32

40

330

-

Main clock output (MCO) for MII Cycle to cycle at 25 MHz

Ethernet

on 1000 samples

Cycle to cycle at 1 MHz

on 1000 samples

Bit Time CAN jitter

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

(4)

I_DD(PLL)

PLL power consumption on VDD

mA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

PLL power consumption on

VDDA

(4)

I_DDA(PLL)

-

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between PLL and PLLI2S.

2. Guaranteed by design, not tested in production.

3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.

4. Based on characterization, not tested in production.

Table 36. PLLI2S (audio PLL) characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_{PLLI2S_IN}

f_{PLLI2S_OUT}

f_{VCO_OUT}

PLLI2S input clock⁽¹⁾

0.95⁽²⁾

-

1

-

2.10

216

432

200

300

MHz

PLLI2S multiplier output clock

PLLI2S VCO output

192

75

-

VCO freq = 192 MHz

VCO freq = 432 MHz

-

t_LOCK

PLLI2S lock time

µs

100

-

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Table 36. PLLI2S (audio PLL) characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ps

RMS

-

90

-

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

peak

to

peak

-

280

-

Master I²S clock jitter

Average frequency of

12.288 MHz

Jitter⁽³⁾

-

90

-

ps

N = 432, R = 5

on 1000 samples

Cycle to cycle at 48 KHz

on 1000 samples

WS I²S clock jitter

400

ps

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

PLLI2S power consumption on

V_DD

(4)

I_DD(PLLI2S)

-

mA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

PLLI2S power consumption on

V_DDA

(4)

I_DDA(PLLI2S)

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design, not tested in production.

3. Value given with main PLL running.

4. Based on characterization, not tested in production.

5.3.11

PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 43: EMI characteristics). It is available only on the main PLL.

Table 37. SSCG parameters constraint

Symbol

Parameter

Min

Typ

Max⁽¹⁾

Unit

f_Mod

md

Modulation frequency

Peak modulation depth

-

0.25

-

10

2

KHz

%

MODEPER * INCSTEP

2

¹⁵−1

-

1. Guaranteed by design, not tested in production.

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = round[f_{PLL_IN}⁄ (4 × f_Mod)]

f

and f

must be expressed in Hz.

PLL_IN

Mod

As an example:

If f = 1 MHz, and f

= 1 kHz, the modulation depth (MODEPER) is given by

MOD

PLL_IN

equation 1:

MODEPER = round[10⁶⁄ (4 × 10³)] = 250

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Electrical characteristics

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Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

INCSTEP = round[((2¹⁵– 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]

f

must be expressed in MHz.

VCO_OUT

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):

INCSTEP = round[((2¹⁵– 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is

obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage

quantized modulation depth is given by the following formula:

md_quantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((2¹⁵– 1) × PLLN)

As a result:

md_quantized% = (250 × 126 × 100 × 5) ⁄ ((2¹⁵– 1) × 240) = 2.002%(peak)

Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

nominal.

PLL_OUT

T

is the modulation period.

mode

md is the modulation depth.

Figure 35. PLL output clock waveforms in center spread mode

Frequency (PLL_OUT)

md

F0

md

Time

2 x tmode

tmode

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Figure 36. PLL output clock waveforms in down spread mode

Frequency (PLL_OUT)

F0

2 x md

Time

tmode

2 x tmode

ai17292

5.3.12

Memory characteristics

Flash memory

The characteristics are given at T = –40 to 105 °C unless otherwise specified.

A

The devices are shipped to customers with the Flash memory erased.

Table 38. Flash memory characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Write / Erase 8-bit mode, V_DD= 1.8 V

Write / Erase 16-bit mode, V_DD= 2.1 V

Write / Erase 32-bit mode, V_DD= 3.3 V

-

5

8

-

I_DD

Supply current

mA

12

Table 39. Flash memory programming

Symbol

Parameter

Conditions

Min⁽¹⁾Typ Max⁽¹⁾Unit

Program/eraseparallelism

(PSIZE) = x 8/16/32

t_prog

Word programming time

-

16

100⁽²⁾µs

800

Program/eraseparallelism

(PSIZE) = x 8

400

300

250

Program/eraseparallelism

(PSIZE) = x 16

t_ERASE16KBSector (16 KB) erase time

600

500

ms

Program/eraseparallelism

(PSIZE) = x 32

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Electrical characteristics

Symbol

STM32F415xx, STM32F417xx

Table 39. Flash memory programming (continued)

Parameter

Conditions

Min⁽¹⁾Typ Max⁽¹⁾Unit

Program/eraseparallelism

(PSIZE) = x 8

-

1200 2400

Program/eraseparallelism

(PSIZE) = x 16

t_ERASE64KBSector (64 KB) erase time

700

550

2

1400

1100

4

ms

Program/eraseparallelism

(PSIZE) = x 32

Program/eraseparallelism

(PSIZE) = x 8

Program/eraseparallelism

(PSIZE) = x 16

t_ERASE128KBSector (128 KB) erase time

1.3

1

2.6

2

s

Program/eraseparallelism

(PSIZE) = x 32

Program/eraseparallelism

(PSIZE) = x 8

16

11

8

32

Program/eraseparallelism

(PSIZE) = x 16

t_ME

Mass erase time

22

s

Program/eraseparallelism

(PSIZE) = x 32

16

32-bit program operation

16-bit program operation

8-bit program operation

2.7

2.1

1.8

-

3.6

V

V_prog

Programming voltage

1. Based on characterization, not tested in production.

2. The maximum programming time is measured after 100K erase operations.

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Symbol

Electrical characteristics

Table 40. Flash memory programming with V

PP

Parameter

Double word programming

Conditions

Min⁽¹⁾

Typ

Max⁽¹⁾Unit

t_prog

-

16

230

490

875

6.9

-

100⁽²⁾

µs

t_ERASE16KBSector (16 KB) erase time

t_ERASE64KBSector (64 KB) erase time

t_ERASE128KBSector (128 KB) erase time

-

T_A= 0 to +40 °C

V_DD= 3.3 V

-

ms

V_PP= 8.5 V

-

t_ME

V_prog

V_PP

Mass erase time

-

s

V

Programming voltage

V_PPvoltage range

2.7

7

3.6

9

-

Minimum current sunk on

the V_PPpin

I_PP

10

-

mA

Cumulative time during

which V_PPis applied

(3)

t_VPP

1

hour

1. Guaranteed by design, not tested in production.

2. The maximum programming time is measured after 100K erase operations.

3. V_PPshould only be connected during programming/erasing.

Table 41. Flash memory endurance and data retention

Value

Symbol

Parameter

Conditions

Unit

Min⁽¹⁾

T_A= –40 to +85 °C (6 suffix versions)

T_A= –40 to +105 °C (7 suffix versions)

N_ENDEndurance

kcycles

Years

10

1 kcycle⁽²⁾at T_A= 85 °C

30

10

20

t_RET

Data retention 1 kcycle⁽²⁾at T_A= 105 °C

10 kcycles⁽²⁾at T_A= 55 °C

1. Based on characterization, not tested in production.

2. Cycling performed over the whole temperature range.

5.3.13

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

the device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

•

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

•

FTB: A burst of fast transient voltage (positive and negative) is applied to V and V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant

with the IEC 61000-4-4 standard.

DD

SS

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Electrical characteristics

STM32F415xx, STM32F417xx

A device reset allows normal operations to be resumed.

The test results are given in Table 42. They are based on the EMS levels and classes

defined in application note AN1709.

Table 42. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD= 3.3 V, LQFP176, T_A= +25 °C,

f_HCLK= 168 MHz, conforms to

IEC 61000-4-2

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

V_FESD

2B

4A

Fast transient voltage burst limits to be

applied through 100 pF on V_DDand V_SS

pins to induce a functional disturbance

V_DD= 3.3 V, LQFP176, T_A=

+25 °C, f_HCLK= 168 MHz, conforms

to IEC 61000-4-2

V_EFTB

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

•

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,

?

executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2

standard which specifies the test board and the pin loading.

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Electrical characteristics

Max vs.

Table 43. EMI characteristics

Monitored

frequency band

[f_HSE/f_CPU

]

Symbol

Parameter

Conditions

Unit

25/168 MHz

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

0.1 to 30 MHz

32

25

29

4

V_DD= 3.3 V, T_A= 25 °C, LQFP176

package, conforming to SAE J1752/3

EEMBC, code running from Flash with

ART accelerator enabled

dBµV

-

dBµV

-

S_EMI

Peak level

19

16

18

3.5

V_DD= 3.3 V, T_A= 25 °C, LQFP176

package, conforming to SAE J1752/3

EEMBC, code running from Flash with

ART accelerator and PLL spread

spectrum enabled

30 to 130 MHz

130 MHz to 1GHz

SAE EMI level

5.3.14

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 44. ESD absolute maximum ratings

Maximum

Symbol

Ratings

Conditions

Class

Unit

value⁽¹⁾

Electrostatic discharge

V_ESD(HBM)voltage (human body

model)

T_A= +25 °C conforming to JESD22-A114

2

2000⁽²⁾

V

Electrostatic discharge

V_ESD(CDM)voltage (charge device

model)

T_A= +25 °C conforming to JESD22-C101

II

500

1. Based on characterization results, not tested in production.

2. On V_BATpin, V_ESD(HBM)is limited to 1000 V.

Static latchup

Two complementary static tests are required on six parts to assess the latchup

performance:

•

A supply overvoltage is applied to each power supply pin

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

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Electrical characteristics

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Table 45. Electrical sensitivities

Conditions

Symbol

Parameter

Static latch-up class

Class

LU

T_A= +105 °C conforming to JESD78A

II level A

5.3.15

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V or

SS

above V (for standard, 3 V-capable I/O pins) should be avoided during normal product

DD

operation. However, in order to give an indication of the robustness of the microcontroller in

cases when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of

5 uA/+0 uA range), or other functional failure (for example reset, oscillator frequency

deviation).

Negative induced leakage current is caused by negative injection and positive induced

leakage current by positive injection.

The test results are given in Table 46.

Table 46. I/O current injection susceptibility

Functional susceptibility

Symbol

Description

Unit

Negative

injection

Positive

injection

Injected current on all FT pins

Injected current on any other pin

–5

+0

+5

(1)

I_INJ

mA

1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject

negative currents.

5.3.16

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 47 are derived from tests

performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL

compliant.

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Table 47. I/O static characteristics

Conditions

Symbol

Parameter

Input low level voltage

Min

Typ

Max

Unit

V_IL

-

2.0

-

0.8

TTL ports

(1)

2.7 V ≤ V_DD≤ 3.6 V

V_IH

Input high level voltage

Input low level voltage

-

V_IL

-

0.3V_DD

V

CMOS ports

-

(1)

1.8 V ≤ V_DD≤ 3.6 V

V_IH

Input high level voltage

0.7V_DD

-

I/O Schmitt trigger voltage hysteresis⁽²⁾

200

V_hys

mV

µA

IO FT Schmitt trigger voltage

hysteresis⁽²⁾

(3)

5% V_DD

-

I/O input leakage current ⁽⁴⁾

V_SS≤ V_IN≤ V_DD

V_IN= 5 V

-

1

3

I_lkg

I/O FT input leakage current ⁽⁴⁾

All pins

except for

PA10 and

resistor⁽⁵⁾

PB12

30

8

40

11

40

50

15

50

15

Weak pull-up equivalent

R_PU

V_IN= V_SS

PA10 and

PB12

kΩ

All pins

except for

PA10 and

PB12

30

8

Weak pull-down

equivalent resistor

R_PD

V_IN= V_DD

PA10 and

PB12

11

5

(6)

C_IO

I/O pin capacitance

pF

1. Tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

6. Guaranteed by design, not tested in production.

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters.

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or

source up to 20 mA (with a relaxed V /V ) except PC13, PC14 and PC15 which can

OL OH

sink or source up to 3mA. When using the PC13 to PC15 GPIOs in output mode, the

speed should not exceed 2 MHz with a maximum load of 30 pF.

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In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 5.2. In particular:

•

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

I

(see Table 12).

VDD

•

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

I

(see Table 12).

VSS

Output voltage levels

Unless otherwise specified, the parameters given in Table 48 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 14. All I/Os are CMOS and TTL compliant.

(1)

Table 48. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(2)

V_OL

-

0.4

CMOS port

I_IO= +8 mA

V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(3)

2.7 V < V_DD< 3.6 V

V_OH

V_DD–0.4

-

0.4

-

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(2)

V_OL

-

2.4

-

TTL port

I_IO=+ 8mA

V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(3)

2.7 V < V_DD< 3.6 V

V_OH

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(2)(4)

V_OL

1.3

-

I_IO= +20 mA

2.7 V < V_DD< 3.6 V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(3)(4)

V_OH

V

_DD–1.3

-

V_DD–0.4

Output low level voltage for an I/O pin

when 8 pins are sunk at same time

(2)(4)

V_OL

0.4

-

I_IO= +6 mA

2 V < V_DD< 2.7 V

Output high level voltage for an I/O pin

when 8 pins are sourced at same time

(3)(4)

V_OH

1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited

amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed

should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current

source (e.g. to drive an LED).

2. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 12

and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

3. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in

Table 12 and the sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

4. Based on characterization data, not tested in production.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 37 and

Table 49, respectively.

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Unless otherwise specified, the parameters given in Table 49 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 14.

(1)(2)(3)

Table 49. I/O AC characteristics

OSPEEDRy

[1:0] bit

Symbol

Parameter

Conditions

Min

Typ

Max Unit

value⁽¹⁾

C_L= 50 pF, V_{DD >}2.70 V

C_L= 50 pF, V_{DD >}1.8 V

C_L= 10 pF, V_{DD >}2.70 V

C_L= 10 pF, V_{DD >}1.8 V

-

2

f_max(IO)outMaximum frequency⁽⁴⁾

MHz

TBD

00

Output high to low level fall

t_f(IO)out

time

-

TBD

ns

C_L= 50 pF, V_DD= 1.8 V to

3.6 V

Output low to high level rise

t_r(IO)out

time

TBD

C_L= 50 pF, V_{DD >}2.70 V

C_L= 50 pF, V_{DD >}1.8 V

C_L= 10 pF, V_{DD >}2.70 V

C_L= 10 pF, V_{DD >}1.8 V

C_L= 50 pF, V_DD< 2.7 V

C_L= 10 pF, V_DD> 2.7 V

C_L= 50 pF, V_DD< 2.7 V

C_L= 10 pF, V_DD> 2.7 V

C_L= 40 pF, V_{DD >}2.70 V

C_L= 40 pF, V_{DD >}1.8 V

C_L= 10 pF, V_{DD >}2.70 V

C_L= 10 pF, V_{DD >}1.8 V

-

25

12.5⁽⁵⁾

MHz

f_max(IO)outMaximum frequency⁽⁴⁾

50⁽⁵⁾

TBD

01

Output high to low level fall

t_f(IO)out

time

TBD

ns

TBD

Output low to high level rise

t_r(IO)out

time

TBD

50⁽⁵⁾

25

f_max(IO)outMaximum frequency⁽⁴⁾

MHz

100⁽⁵⁾

TBD

C_L= 50 pF,

10

-

Output high to low level fall

2.4 < V_DD< 2.7 V

t_f(IO)out

time

C_L= 10 pF, V_DD> 2.7 V

TBD

ns

C_L= 50 pF,

Output low to high level rise

2.4 < V_DD< 2.7 V

t_r(IO)out

time

C_L= 10 pF, V_DD> 2.7 V

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STM32F415xx, STM32F417xx

(1)(2)(3)

Table 49. I/O AC characteristics

(continued)

[1:0] bit

Symbol

Parameter

Conditions

Min

Typ

Max Unit

value⁽¹⁾

C_L= 30 pF, V_{DD >}2.70 V

C_L= 30 pF, V_{DD >}1.8 V

C_L= 10 pF, V_{DD >}2.70 V

C_L= 10 pF, V_{DD >}1.8 V

-

100⁽⁵⁾

50⁽⁵⁾

MHz

F_max(IO)ou

Maximum frequency⁽⁴⁾

200⁽⁵⁾

t

TBD

C_L= 20 pF,

11

-

Output high to low level fall

time

2.4 < V_DD< 2.7 V

t_f(IO)out

C_L= 10 pF, V_DD> 2.7 V

TBD

ns

C_L= 20 pF,

TBD

Output low to high level rise

time

2.4 < V_DD< 2.7 V

t_r(IO)out

C_L= 10 pF, V_DD> 2.7 V

TBD

Pulse width of external

-

t_EXTIpwsignals detected by the EXTI

controller

10

-

ns

1. Based on characterization data, not tested in production.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a

description of the GPIOx_SPEEDR GPIO port output speed register.

3. TBD stands for “to be defined”.

4. The maximum frequency is defined in Figure 37.

5. For maximum frequencies above 50 MHz, the compensation cell should be used.

Figure 37. I/O AC characteristics definition

90%

10%

50%

10%

90%

t

EXTERNAL

OUTPUT

ON 50pF

r(IO)out

T

Maximum frequency is achieved if (t + t ) ≤ 2/3)T and if the duty cycle is (45-55%)

r

f

when loaded by 50pF

ai14131

5.3.17

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, R (see Table 47).

PU

Unless otherwise specified, the parameters given in Table 50 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 14.

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Table 50. NRST pin characteristics

Symbol

Parameter

NRST Input low level voltage

Conditions

Min

Typ

Max

Unit

(1)

V_IL(NRST)

TTL ports

2.7 V ≤ V_DD

≤ 3.6 V

-

0.8

(1)

V_IH(NRST)

NRST Input high level voltage

NRST Input low level voltage

NRST Input high level voltage

2

-

V

(1)

V_IL(NRST)

CMOS ports

1.8 V ≤ V_DD

≤ 3.6 V

0.3V_DD

-

(1)

V_IH(NRST)

0.7V_DD

NRST Schmitt trigger voltage

hysteresis

V_hys(NRST)

R_PU

-

200

-

mV

Weak pull-up equivalent resistor⁽²⁾

V_IN= V_SS

30

-

40

-

50

100

-

kΩ

ns

(1)

V_F(NRST)

NRST Input filtered pulse

(1)

V_NF(NRST)

NRST Input not filtered pulse

V_DD> 2.7 V

300

-

Internal

Reset source

T_{NRST_OUT}Generated reset pulse duration

20

-

µs

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance must be minimum (~10% order).

Figure 38. Recommended NRST pin protection

V

DD

External

reset circuit

(1)

R

PU

(2)

Internal Reset

STM32Fxxx

NRST

Filter

0.1 μF

ai14132c

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 50. Otherwise the reset is not taken into account by the device.

5.3.18

TIM timer characteristics

The parameters given in Table 51 and Table 52 are guaranteed by design.

Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

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(1)

Table 51. Characteristics of TIMx connected to the APB1 domain

Symbol

Parameter

Conditions

Min

Max

Unit

AHB/APB1

1

-

t_TIMxCLK

prescaler distinct

from 1, f_TIMxCLK

84 MHz

=

11.9

-

ns

t_res(TIM)

Timer resolution time

AHB/APB1

prescaler = 1,

f_TIMxCLK= 42 MHz

1

-

t_TIMxCLK

ns

23.8

0

-

f_TIMxCLK/2

42

MHz

Timer external clock

frequency on CH1 to CH4

f_EXT

Res_TIM

Timer resolution

16/32

65536

bit

16-bit counter clock

period when internal clock

is selected

1

t_TIMxCLK

f

_TIMxCLK= 84 MHz

0.0119

1

780

µs

t_TIMxCLK

µs

APB1= 42 MHz

t_COUNTER

32-bit counter clock

period when internal clock

is selected

-

0.0119

51130563

-

65536 × 65536 t_TIMxCLK

51.1

t_{MAX_COUNT}Maximum possible count

s

1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers.

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(1)

Table 52. Characteristics of TIMx connected to the APB2 domain

Symbol

Parameter

Conditions

Min

Max

Unit

AHB/APB2

1

-

t_TIMxCLK

prescaler distinct

from 1, f_TIMxCLK

168 MHz

=

5.95

-

ns

t_res(TIM)

Timer resolution time

AHB/APB2

prescaler = 1,

f_TIMxCLK= 84 MHz

1

11.9

0

-

t_TIMxCLK

ns

-

f_TIMxCLK/2

84

Timer external clock

frequency on CH1 to

CH4

MHz

bit

f_EXT

0

f_TIMxCLK

=

Res_TIM

Timer resolution

-

16

168 MHz

16-bit counter clock

t_COUNTERperiod when internal

clock is selected

APB2 = 84 MHz

1

-

65536

32768

t_TIMxCLK

t_{MAX_COUNT}Maximum possible count

1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.

5.3.19

Communications interfaces

I²C interface characteristics

2

I

The STM32F415xx and STM32F417xx C interface meets the requirements of the

2

standard I C communication protocol with the following restrictions: the I/O pins SDA and

SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and V is disabled, but is still present.

DD

2

The I C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port

for more details on the input/output alternate function characteristics (SDA

characteristics

and SCL)

.

2

Table 53. I C characteristics

Standard mode I²C⁽¹⁾

Fast mode I²C⁽¹⁾⁽²⁾

Symbol

Parameter

Unit

Min

Max

Min

Max

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

SCL clock high time

SDA setup time

4.7

4.0

-

1.3

0.6

100

0

-

µs

-

250

0⁽³⁾

-

SDA data hold time

900⁽⁴⁾

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

SDA and SCL fall time

-

1000

300

20 + 0.1C_b

-

300

t_f(SDA)

t_f(SCL)

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2

Table 53. I C characteristics (continued)

Standard mode I²C⁽¹⁾Fast mode I²C⁽¹⁾⁽²⁾

Symbol

Parameter

Unit

Min

Max

Min

Max

t_h(STA)

t_su(STA)

Start condition hold time

4.0

-

0.6

-

µs

Repeated Start condition

setup time

4.7

4.0

4.7

-

0.6

1.3

-

t_su(STO)

Stop condition setup time

μs

Stop to Start condition time

(bus free)

t_w(STO:STA)

Capacitive load for each bus

line

C_b

-

400

-

400

pF

Guaranteed by design, not tested in production.

1.

2. f_PCLK1must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to

achieve fast mode I²C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I²C fast mode

clock.

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL

signal.

2

Figure 39. I C bus AC waveforms and measurement circuit

V

DD_I2C

STM32Fxx

R_P

R_S

SDA

SCL

I²C bus

S TAR T REPEATED

S TAR T

t

su(STA)

S D A

t

su(SDA)

r(SDA)

f(SDA)

t

w(STO:STA)

S TOP

t

h(STA)

t

w(SCLL)

h(SDA)

SCL

t

su(STO)

r(SCL)

t

w(SCLH)

f(SCL)

ai14979c

1. Rs= series protection resistor.

2. Rp = external pull-up resistor.

3. VDD_I2C is the I2C bus power supply.

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(1)(2)

Table 54. SCL frequency (f

= 42 MHz.,V_DD= 3.3 V)

PCLK1

I2C_CCR value

f_SCL(kHz)

R_P= 4.7 kΩ

400

0x8019

0x8021

0x8032

0x0096

0x012C

0x02EE

300

200

100

50

20

1. R_P= External pull-up resistance, f_SCL= I²C speed,

2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the

tolerance on the achieved speed 2%. These variations depend on the accuracy of the external

components used to design the application.

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests

performed under the ambient temperature, f

frequency and V supply voltage

PCLKx

DD

conditions summarized in Table 14 with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 V

DD

Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO).

(1)

Table 55. SPI dynamic characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Master mode, SPI1,

2.7V < V_DD< 3.6V

42

f_SCK

-

Slave mode, SPI1,

2.7V < V_DD< 3.6V

42

21

70

SPI clock frequency

MHz

Master mode, SPI1/2/3,

1.7V < V_DD< 3.6V

1/t_c(SCK)

-

Slave mode, SPI1/2/3,

1.7V < V_DD< 3.6V

Duty cycle of SPI clock

frequency

Duty(SCK)

Slave mode

30

50

%

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(1)

Table 55. SPI dynamic characteristics (continued)

Symbol

Parameter

Conditions

Min

T_PCLK-0.5 T_PCLKT_PCLK+0.5

_PCLK-2 T_PCLKT_PCLK+2

Typ

Max

Unit

Master mode, SPI presc = 2,

2.7V < V_DD< 3.6V

t_w(SCKH)

SCK high and low time

Master mode, SPI presc = 2,

1.7V < V_DD< 3.6V

t_w(SCKL)

T

t_su(NSS)

t_h(NSS)

t_su(MI)

t_su(SI)

t_h(MI)

NSS setup time

NSS hold time

Slave mode, SPI presc = 2

Master mode

4 x T_PCLK

-

2 x T_PCLK

6.5

2.5

4

-

Data input setup time

Slave mode

-

Master mode

-

Data input hold time

t_h(SI)

Slave mode

-

(2)

t_a(SO)

Data output access time

Slave mode, SPI presc = 2

0

4 x T_PCLK

Slave mode, SPI1,

2.7V < V_DD< 3.6V

0

-

7.5

16.5

13

(3)

t_dis(SO)

Data output disable time

Slave mode, SPI1/2/3

1.7V < V_DD< 3.6V

ns

Slave mode (after enable edge),

SPI1, 2.7V < V_DD< 3.6V

11

12

15.5

18

-

Slave mode (after enable edge),

SPI2/3, 2.7V < V_DD< 3.6V

-

16.5

19

t_v(SO)

t_h(SO)

Data output valid/hold time

Slave mode (after enable edge),

SPI1, 1.7V < V_DD< 3.6V

-

Slave mode (after enable edge),

SPI2/3, 1.7V < V_DD< 3.6V

-

20.5

2.5

4.5

-

Master mode (after enable edge),

SPI1 , 2.7V < V_DD< 3.6V

-

t_v(MO)

Data output valid time

Data output hold time

Master mode (after enable edge),

SPI1/2/3 , 1.7V < V_DD< 3.6V

-

t_h(MO)

Master mode (after enable edge)

0

-

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

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Figure 40. SPI timing diagram - slave mode and CPHA = 0

NSS input

t

c(SCK)

t

h(NSS)

SU(NSS)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

r(SCK)

f(SCK)

v(SO)

a(SO)

h(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134c

Figure 41. SPI timing diagram - slave mode and CPHA = 1

NSS input

t

h(NSS)

SU(NSS)

t

c(SCK)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

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Figure 42. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

INPUT

MSBIN

t

BIT6 IN

LSB IN

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTUT

t

v(MO)

h(MO)

ai14136

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I²S interface characteristics

2

Unless otherwise specified, the parameters given in Table 56 for the i S interface are

derived from tests performed under the ambient temperature, f

frequency and V

PCLKx

DD

supply voltage conditions summarized in Table 14, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 V

DD

Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (CK, SD, WS).

2

(1)

Table 56. I S dynamic characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

256 x

8K

(2)

f_MCK

I²S main clock output

-

256 x F_S

MHz

Master data: 32 bits

Slave data: 32 bits

-

64 x F_S

f_CK

I²S clock frequency

MHz

%

64 x F_S

D_CK

I²S clock frequency duty cycle Slave receiver

30

0

70

6

-

t_v(WS)

WS valid time

WS hold time

WS setup time

WS hold time

Master mode

Slave mode

t_h(WS)

0

t_su(WS)

1

-

t_h(WS)

Slave mode

0

-

t_{su(SD_MR)}

t_{su(SD_SR)}

t_{h(SD_MR)}

t_{h(SD_SR)}

Master receiver

Slave receiver

Master receiver

Slave receiver

7.5

2

-

Data input setup time

Data input hold time

-

ns

0

-

0

-

t_{v(SD_ST)}

t_{h(SD_ST)}

Slave transmitter (after enable edge)

-

27

Data output valid time

t_{v(SD_MT)}

Master transmitter (after enable edge)

-

20

-

t_{h(SD_MT)}Data output hold time

2.5

1. Data based on characterization results, not tested in production.

2. The maximum value of 256 x F_Sis 42 MHz (APB1 maximum frequency).

2

Note:

Refer to the I S section of RM0090 reference manual for more details on the sampling

frequency (F ). f

, f , and D values reflect only the digital peripheral behavior. The

S

MCK CK

CK

value of these parameters might be slightly impacted by the source clock accuracy. D

CK

depends mainly on the value of ODD bit. The digital contribution leads to a minimum value

of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV +

ODD). F maximum value is supported for each mode/condition.

S

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2

Figure 43. I S slave timing diagram (Philips protocol)

t

c(CK)

CPOL = 0

CPOL = 1

WS input

t

w(CKL)

h(WS)

w(CKH)

t

v(SD_ST)

h(SD_ST)

su(WS)

SD

transmit

(2)

LSB transmit

MSB transmit

MSB receive

Bitn transmit

LSB transmit

t

su(SD_SR)

h(SD_SR)

(2)

LSB receive

Bitn receive

LSB receive

SD

receive

ai14881b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

2

(1)

Figure 44. I S master timing diagram (Philips protocol)

t

r(CK)

f(CK)

t

c(CK)

CPOL = 0

CPOL = 1

WS output

t

w(CKH)

t

h(WS)

t

v(WS)

w(CKL)

t

v(SD_MT)

h(SD_MT)

(2)

SD

transmit

LSB transmit

MSB transmit

MSB receive

Bitn transmit

LSB transmit

t

h(SD_MR)

su(SD_MR)

(2)

SD

LSB receive

Bitn receive

LSB receive

receive

ai14884b

1. Based on characterization, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

USB OTG FS characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

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Symbol

Electrical characteristics

Table 57. USB OTG FS startup time

Parameter

Max

Unit

(1)

t_STARTUP

USB OTG FS transceiver startup time

1

µs

1. Guaranteed by design, not tested in production.

Table 58. USB OTG FS DC electrical characteristics

Symbol

Parameter

Conditions

Min.⁽¹⁾Typ. Max.⁽¹⁾Unit

USB OTG FS operating

voltage

V_DD

3.0⁽²⁾

0.2

-

3.6

-

V

I(USB_FS_DP/DM,

USB_HS_DP/DM)

(3)

V_DI

Differential input sensitivity

Input

levels

Differential common mode

range

(3)

V_CM

Includes V_DIrange

0.8

2.5

2.0

V

Single ended receiver

threshold

(3)

V_SE

1.3

V_OLStatic output level low

V_OHStatic output level high

R_Lof 1.5 kΩ to 3.6 V⁽⁴⁾

-

0.3

3.6

Output

levels

V

(4)

R_Lof 15 kΩ to V_SS

2.8

PA11, PA12, PB14, PB15

(USB_FS_DP/DM,

17

21

24

USB_HS_DP/DM)

R_PD

V_IN= V_DD

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

0.65

1.5

1.1

1.8

2.0

2.1

kΩ

PA12, PB15 (USB_FS_DP,

USB_HS_DP)

V_IN= V_SS

R_PU

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

V_IN= V_SS

0.25 0.37 0.55

1. All the voltages are measured from the local ground potential.

2. The STM32F415xx and STM32F417xx USB OTG FS functionality is ensured down to 2.7 V but not the full

USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V V_DDvoltage range.

3. Guaranteed by design, not tested in production.

R_Lis the load connected on the USB OTG FS drivers

4.

Figure 45. USB OTG FS timings: definition of data signal rise and fall time

Crossover

points

Differential

Data Lines

V

CR S

V

SS

t

r

f

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(1)

Table 59. USB OTG FS electrical characteristics

Driver characteristics

Conditions

Symbol

Parameter

Rise time⁽²⁾

Fall time⁽²⁾

Rise/ fall time matching

Output signal crossover voltage

Min

Max

Unit

t_r

t_f

C_L= 50 pF

t_r/t_f

4

20

ns

%

V

t_rfm

V_CRS

90

1.3

110

2.0

1. Guaranteed by design, not tested in production.

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

2.

USB HS characteristics

Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from

tests performed under the ambient temperature, f frequency summarized in Table 61

HCLK

and V supply voltage conditions summarized in Table 60, with the following configuration:

DD

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5V

.

DD

Refer to Section Section 5.3.16: I/O port characteristics for more details on the

input/outputcharacteristics.

Table 60. USB HS DC electrical characteristics

Symbol

Input level

Parameter

Min.⁽¹⁾

Max.⁽¹⁾

Unit

V_DD

USB OTG HS operating voltage

2.7

3.6

V

1. All the voltages are measured from the local ground potential.

(1)

Table 61. USB HS clock timing parameters

Parameter

Symbol

Min

Nominal

Max

Unit

f

_HCLKvalue to guarantee proper operation of

30

MHz

USB HS interface

Frequency (first transition)

8-bit ±10%

F_{START_8BIT}

F_STEADY

D_{START_8BIT}

D_STEADY

54

59.97

40

60

50

66

60.03

60

MHz

%

Frequency (steady state) ±500 ppm

Duty cycle (first transition)

8-bit ±10%

Duty cycle (steady state) ±500 ppm

49.975

50.025

%

Time to reach the steady state frequency and

duty cycle after the first transition

T_STEADY

-

1.4

ms

µs

Peripheral

T_{START_DEV}

-

5.6

-

Clock startup time after the

de-assertion of SuspendM

Host

T_{START_HOST}

PHY preparation time after the first transition

of the input clock

T_PREP

-

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1. Guaranteed by design, not tested in production.

Table 62. ULPI timing

Value⁽¹⁾

Parameter

Symbol

Unit

Min.

Max.

Control in (ULPI_DIR) setup time

Control in (ULPI_NXT) setup time

Control in (ULPI_DIR, ULPI_NXT) hold time

Data in setup time

-

2.0

1.5

-

t_SC

t_HC

t_SD

t_HD

t_DC

t_DD

0

-

2.0

-

ns

Data in hold time

0

-

Control out (ULPI_STP) setup time and hold time

Data out available from clock rising edge

1. V_DD= 2.7 V to 3.6 V and T_A= –40 to 85 °C.

9.2

10.7

-

Figure 46. ULPI timing diagram

Clock

t

HC

SC

Control In

(ULPI_DIR,

ULPI_NXT)

t

HD

SD

data In

(8-bit)

t

DC

Control out

(ULPI_STP)

t

DD

data out

(8-bit)

ai17361c

Ethernet characteristics

Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for

SMI, RMII and MII are derived from tests performed under the ambient temperature, f

HCLK

frequency summarized in Table 14 and VDD supply voltage conditions summarized in

Table 63, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5V

.

DD

Refer to Section 5.3.16: I/O port characteristics for more details on the input/output

characteristics.

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Electrical characteristics

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Table 63. Ethernet DC electrical characteristics

Symbol

Parameter

Min.⁽¹⁾

Max.⁽¹⁾

Unit

Input level

V_DD

Ethernet operating voltage

2.7

3.6

V

1. All the voltages are measured from the local ground potential.

Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface)

and Figure 47 shows the corresponding timing diagram.

Figure 47. Ethernet SMI timing diagram

tMDC

ETH_MDC

td(MDIO)

ETH_MDIO(O)

tsu(MDIO)

th(MDIO)

ETH_MDIO(I)

MS31384V1

(1)

Table 64. Dynamic characteristics: Ehternet MAC signals for SMI

Symbol

t_MDC

Parameter

Min

Typ

Max

Unit

MDC cycle time( 2.38 MHz)

Write data valid time

Read data setup time

Read data hold time

411

6

420

425

T_d(MDIO)

t_su(MDIO)

t_h(MDIO)

10

-

13

-

ns

12

0

-

1. Data based on characterization results, not tested in production.

Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the

corresponding timing diagram.

Figure 48. Ethernet RMII timing diagram

RMII_REF_CLK

t_d(TXEN)

t_d(TXD)

RMII_TX_EN

RMII_TXD[1:0]

t_su(RXD)

t_su(CRS)

t_ih(RXD)

t_ih(CRS)

RMII_RXD[1:0]

RMII_CRS_DV

ai15667

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Electrical characteristics

Table 65. Dynamic characteristics: Ethernet MAC signals for RMII

Symbol

Rating

Min

Typ

Max

Unit

t_su(RXD)

t_ih(RXD)

t_su(CRS)

t_ih(CRS)

t_d(TXEN)

t_d(TXD)

Receive data setup time

Receive data hold time

2

1

-

ns

-

Carrier sense set-up time

Carrier sense hold time

0.5

2

-

Transmit enable valid delay time

Transmit data valid delay time

8

9.5

10

11

11.5

8.5

Table 66 gives the list of Ethernet MAC signals for MII and Figure 48 shows the

corresponding timing diagram.

Figure 49. Ethernet MII timing diagram

MII_RX_CLK

t

su(RXD)

su(ER)

su(DV)

ih(RXD)

ih(ER)

ih(DV)

MII_RXD[3:0]

MII_RX_DV

MII_RX_ER

MII_TX_CLK

t

d(TXEN)

d(TXD)

MII_TX_EN

MII_TXD[3:0]

ai15668

(1)

Table 66. Dynamic characteristics: Ethernet MAC signals for MII

Symbol

Parameter

Min

Typ

Max

Unit

t_su(RXD)

t_ih(RXD)

t_su(DV)

t_ih(DV)

Receive data setup time

Receive data hold time

Data valid setup time

Data valid hold time

9

10

9

-

8

-

ns

t_su(ER)

t_ih(ER)

t_d(TXEN)

t_d(TXD)

Error setup time

6

-

Error hold time

8

-

Transmit enable valid delay time

Transmit data valid delay time

0

10

14

15

0

1. Data based on characterization results, not tested in production.

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Electrical characteristics

STM32F415xx, STM32F417xx

CAN (controller area network) interface

Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (CANTX and CANRX).

5.3.20

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 67 are derived from tests

performed under the ambient temperature, f

frequency and V

supply voltage

PCLK2

DDA

conditions summarized in Table 14.

Table 67. ADC characteristics

Conditions

Symbol

Parameter

Power supply

Min

Typ

Max

Unit

V_DDA

1.8⁽¹⁾

-

3.6

V

V_REF+Positive reference voltage

1.8^(1)(2)(3)

V_DDA

V_DDA= 1.8⁽¹⁾⁽³⁾to

2.4 V

0.6

-

15

18

36

MHz

kHz

f_ADC

ADC clock frequency

V_DDA= 2.4 to 3.6 V⁽³⁾

30

-

f_ADC= 30 MHz,

12-bit resolution

1764

17

(4)

f_TRIG

External trigger frequency

Conversion voltage range⁽⁵⁾

-

1/f_ADC

V

0 (V_SSAor V_REF-

tied to ground)

V_AIN

-

V_REF+

See Equation 1 for

(4)

R_AIN

External input impedance

Sampling switch resistance

-

50

6

κΩ

pF

details

(4)(6)

R_ADC

Internal sample and hold

capacitor

(4)

C_ADC

4

-

f_ADC= 30 MHz

-

0.100

3⁽⁷⁾

0.067

2⁽⁷⁾

16

µs

1/f_ADC

µs

Injection trigger conversion

latency

(4)

t_lat

-

Regular trigger conversion

latency

(4)

t_latr

-

1/f_ADC

µs

f

_ADC= 30 MHz

0.100

-

(4)

t_S

Sampling time

Power-up time

3

-

480

3

1/f_ADC

µs

(4)

t_STAB

2

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Electrical characteristics

Table 67. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_ADC= 30 MHz

12-bit resolution

0.50

-

16.40

µs

f_ADC= 30 MHz

10-bit resolution

0.43

0.37

0.30

-

16.34

16.27

16.20

µs

Total conversion time (including

sampling time)

f_ADC= 30 MHz

8-bit resolution

(4)

t_CONV

f_ADC= 30 MHz

6-bit resolution

µs

9 to 492 (t_Sfor sampling +n-bit resolution for successive

approximation)

1/f_ADC

Msps

12-bit resolution

-

2

Single ADC

12-bit resolution

Sampling rate

3.75

Msps

Interleave Dual ADC

mode

(4)

f_S

(f_ADC= 30 MHz, and

t_S= 3 ADC cycles)

12-bit resolution

-

6

Msps

µA

Interleave Triple ADC

mode

ADC V_REFDC current

consumption in conversion

mode

(4)

I_VREF+

300

1.6

500

1.8

ADC V_DDADC current

consumption in conversion

mode

(4)

I_VDDA

mA

1. V_DD/V_DDAminimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of

an external power supply supervisor (refer to Section : Internal reset OFF).

2. It is recommended to maintain the voltage difference between V_REF+and V_DDAbelow 1.8 V.

3. V_DDA-V_REF+< 1.2 V.

4. Based on characterization, not tested in production.

5. V_REF+is internally connected to V_DDAand V_REF-is internally connected to V_SSA

.

6. R_ADCmaximum value is given for V_DD=1.8 V, and minimum value for V_DD=3.3 V.

7. For external triggers, a delay of 1/f_PCLK2must be added to the latency specified in Table 67.

Equation 1: R

max formula

AIN

(k – 0.5)

R_AIN= -------------------------------------------------------------- – R_ADC

f_ADC× C_ADC× ln(2^{N + 2}

)

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of

sampling periods defined in the ADC_SMPR1 register.

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Electrical characteristics

STM32F415xx, STM32F417xx

a

(1)

Table 68. ADC accuracy at f

= 30 MHz

ADC

Symbol

Parameter

Test conditions

Typ

Max⁽²⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

±2

±5

±2.5

±3

±1.5

±1

f

_PCLK2= 60 MHz,

Gain error

f_ADC= 30 MHz, R_AIN< 10 kΩ,

LSB

V_DDA= 1.8⁽³⁾to 3.6 V

Differential linearity error

Integral linearity error

±2

±1.5

±3

1. Better performance could be achieved in restricted V_DD, frequency and temperature ranges.

2. Based on characterization, not tested in production.

3. V_DD/V_DDAminimum value of 1.7 V is obtained when the device operates in reduced temperature range,

and with the use of an external power supply supervisor (refer to Section : Internal reset OFF).

Note:

ADC accuracy vs. negative injection current: injecting a negative current on any analog

input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to

ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

Section 5.3.16 does not affect the ADC accuracy.

and ΣI

in

INJ(PIN)

Figure 50. ADC accuracy characteristics

V

DDA

4096

REF+

[1LSB

=

(or

depending on package)]

IDEAL

4096

E

G

4095

4094

4093

(2)

E

T

(3)

7

6

5

4

3

2

1

(1)

E

O

L

E

D

1L SB

IDEAL

7

0

V

1

2

3

456

4093 4094 4095 4096

V

DDA

SSA

ai14395c

1. See also Table 68.

2. Example of an actual transfer curve.

3. Ideal transfer curve.

4. End point correlation line.

5. E_T= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

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Electrical characteristics

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point

correlation line.

Figure 51. Typical connection diagram using the ADC

STM32F

V

DD

Sample and hold ADC

V

0.6 V

T

converter

(1)

C

(1)

R

AIN

ADC

AINx

12-bit

converter

V

T

V

AIN

0.6 V

C

(1)

ADC

parasitic

I

1 µA

L

ai17534

1. Refer to Table 67 for the values of R_AIN, R_ADCand C_ADC

.

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 5 pF). A high C_parasiticvalue downgrades conversion accuracy. To remedy this,

f_ADCshould be reduced.

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Electrical characteristics

STM32F415xx, STM32F417xx

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 52 or Figure 53,

depending on whether V is connected to V or not. The 10 nF capacitors should be

REF+

DDA

ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 52. Power supply and reference decoupling (V

not connected to V

)

DDA

REF+

STM32F

V

REF+

(See note 1)

1 µF // 10 nF

V

DDA

1 µF // 10 nF

/V

SSA REF-

(See note 1)

ai17535

1. V_REF+and V_REF–inputs are both available on UFBGA176. V_REF+is also available on LQFP100, LQFP144,

and LQFP176. When V_REF+and V_REF–are not available, they are internally connected to V_DDAand V_SSA

.

Figure 53. Power supply and reference decoupling (V

connected to V

)

DDA

REF+

STM32F

V

/V

REF+ DDA

(See note 1)

1 µF // 10 nF

V

/V

REF– SSA

(See note 1)

ai17536

1. V_REF+and V_REF–inputs are both available on UFBGA176. V_REF+is also available on LQFP100, LQFP144,

and LQFP176. When V_REF+and V_REF–are not available, they are internally connected to V_DDAand V_SSA

.

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Electrical characteristics

5.3.21

Temperature sensor characteristics

Table 69. Temperature sensor characteristics

Parameter

Symbol

Min

Typ Max

Unit

(1)

T_L

V_SENSElinearity with temperature

-

1

2.5

0.76

6

2

°C

mV/°C

V

Avg_Slope⁽¹⁾Average slope

(1)

V₂₅

Voltage at 25 °C

-

(2)

t_START

Startup time

-

10

-

µs

(3)(2)

T_{S_temp}

ADC sampling time when reading the temperature (1 °C accuracy)

10

-

µs

1. Based on characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

Table 70. Temperature sensor calibration values

Parameter

Symbol

Memory address

0x1FFF 7A2C - 0x1FFF 7A2D

TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V_DDA=3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V_DDA=3.3 V

5.3.22

V

monitoring characteristics

BAT

Table 71. V

monitoring characteristics

BAT

Symbol

Parameter

Resistor bridge for V_BAT

Min

Typ

Max

Unit

R

Q

-

50

2

-

KΩ

Ratio on V_BATmeasurement

Error on Q

Er⁽¹⁾

–1

-

+1

%

ADC sampling time when reading the V_BAT

1 mV accuracy

(2)(2)

T_{S_vbat}

5

-

µs

1. Guaranteed by design, not tested in production.

2. Shortest sampling time can be determined in the application by multiple iterations.

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Electrical characteristics

STM32F415xx, STM32F417xx

5.3.23

Embedded reference voltage

The parameters given in Table 72 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 14.

DD

Table 72. Embedded internal reference voltage

Symbol

V_REFINT

Parameter

Conditions

Min

Typ

Max

Unit

Internal reference voltage

–40 °C < T_A< +105 °C 1.18 1.21 1.24

V

ADC sampling time when reading the

internal reference voltage

(1)

T_{S_vrefint}

10

-

µs

Internal reference voltage spread over the

temperature range

(2)

V_{RERINT_s}

V_DD= 3 V

3

5

mV

(2)

T_Coeff

Temperature coefficient

Startup time

-

30

6

50

10

ppm/°C

µs

(2)

t_START

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

Table 73. Internal reference voltage calibration values

Parameter

Symbol

Memory address

V_{REFIN_CAL}

Raw data acquired at temperature of 30 °C, V_DDA=3.3 V

0x1FFF 7A2A - 0x1FFF 7A2B

5.3.24

DAC electrical characteristics

Table 74. DAC characteristics

Symbol

Parameter

Min Typ

Max

Unit

Comments

V_DDA

Analog supply voltage

1.8⁽¹⁾

-

3.6

V

V_REF+

V_SSA

Reference supply voltage

Ground

1.8⁽¹⁾

0

-

3.6

0

V

V_REF+≤ V_DDA

Resistive load with buffer

ON

(2)

R_LOAD

5

-

kΩ

When the buffer is OFF, the

Minimum resistive load between

DAC_OUT and V_SSto have a 1%

accuracy is 1.5 MΩ

Impedance output with

buffer OFF

(2)

R_O

-

15

kΩ

Maximum capacitive load at

pF DAC_OUT pin (when the buffer is

ON).

(2)

C_LOAD

Capacitive load

-

50

It gives the maximum output

excursion of the DAC.

DAC_OUT Lower DAC_OUT voltage

min⁽²⁾

with buffer ON

0.2

-

V

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V_REF+

3.6 V and (0x1C7) to (0xE38) at

V_REF+= 1.8 V

=

DAC_OUT Higher DAC_OUT voltage

max⁽²⁾

with buffer ON

V

_DDA– 0.2

V

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Electrical characteristics

Comments

Table 74. DAC characteristics (continued)

Symbol

Parameter

Min Typ

Max

Unit

DAC_OUT Lower DAC_OUT voltage

-

0.5

-

mV

min⁽²⁾

with buffer OFF

It gives the maximum output

excursion of the DAC.

DAC_OUT Higher DAC_OUT voltage

V

_REF+– 1LSB

V

max⁽²⁾

with buffer OFF

With no load, worst code (0x800)

at V_REF+= 3.6 V in terms of DC

consumption on the inputs

-

170

240

DAC DC V_REFcurrent

consumption in quiescent

mode (Standby mode)

(4)

I_VREF+

µA

With no load, worst code (0xF1C)

at V_REF+= 3.6 V in terms of DC

consumption on the inputs

-

50

75

With no load, middle code (0x800)

on the inputs

280

475

380

625

DAC DC VDDA current

consumption in quiescent

mode⁽³⁾

(4)

I_DDA

With no load, worst code (0xF1C)

µA at V_REF+= 3.6 V in terms of DC

consumption on the inputs

Given for the DAC in 10-bit

configuration.

-

±0.5

LSB

Differential non linearity

Difference between two

consecutive code-1LSB)

DNL⁽⁴⁾

Given for the DAC in 12-bit

configuration.

-

±2

±1

LSB

Integral non linearity

(difference between

Given for the DAC in 10-bit

configuration.

LSB

measured value at Code i

and the value at Code i on a

line drawn between Code 0

and last Code 1023)

INL⁽⁴⁾

Given for the DAC in 12-bit

configuration.

-

±4

LSB

Given for the DAC in 12-bit

configuration

-

±10

±3

mV

Offset error

(difference between

measured value at Code

(0x800) and the ideal value

= V_REF+/2)

Given for the DAC in 10-bit at

V_REF+= 3.6 V

Offset⁽⁴⁾

LSB

Given for the DAC in 12-bit at

LSB

±12

±0.5

V_REF+= 3.6 V

Gain

Given for the DAC in 12-bit

configuration

Gain error

%

µs

dB

error⁽⁴⁾

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±4LSB

C_LOAD≤ 50 pF,

R_LOAD≥ 5 kΩ

(4)

t_SETTLING

-

3

-

6

-

Total Harmonic Distortion

Buffer ON

C_LOAD≤ 50 pF,

R_LOAD≥ 5 kΩ

THD⁽⁴⁾

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Electrical characteristics

STM32F415xx, STM32F417xx

Comments

Table 74. DAC characteristics (continued)

Symbol

Parameter

Min Typ

Max

Unit

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

Update

rate⁽²⁾

C_LOAD≤ 50 pF,

R_LOAD≥ 5 kΩ

-

1

MS/s

C_LOAD≤ 50 pF, R_LOAD≥ 5 kΩ

input code between lowest and

highest possible ones.

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

(4)

t_WAKEUP

-

6.5

10

µs

Power supply rejection ratio

PSRR+ ⁽²⁾(to V_DDA) (static DC

measurement)

–67

–40

dB No R_LOAD, C_LOAD= 50 pF

1. V_DD/V_DDAminimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of

an external power supply supervisor (refer to Section : Internal reset OFF).

2. Guaranteed by design, not tested in production.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

4. Guaranteed by characterization, not tested in production.

Figure 54. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

R

LOAD

DACx_OUT

12-bit

digital to

analog

converter

C

LOAD

ai17157

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

loads directly without the use of an external operational amplifier. The buffer can be bypassed by

configuring the BOFFx bit in the DAC_CR register.

5.3.25

FSMC characteristics

Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC

interface are derived from tests performed under the ambient temperature, f

frequency

HCLK

and V supply voltage conditions summarized in Table 14, with the following configuration:

DD

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5V

DD

Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/output

characteristics.

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Electrical characteristics

Asynchronous waveforms and timings

Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through

Table 78 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

•

AddressSetupTime = 1

AddressHoldTime = 0x1

DataSetupTime = 0x1

BusTurnAroundDuration = 0x0

In all timing tables, the T_HCLKis the HCLK clock period.

Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

t

w(NE)

FSMC_NE

t

h(NE_NOE)

w(NOE)

v(NOE_NE)

FSMC_NOE

FSMC_NWE

t_{v(A_NE)}

t

h(A_NOE)

FSMC_A[25:0]

Address

t_{v(BL_NE)}

t

h(BL_NOE)

FSMC_NBL[1:0]

t

h(Data_NE)

t

su(Data_NOE)

h(Data_NOE)

t

su(Data_NE)

Data

FSMC_D[15:0]

FSMC_NADV⁽¹⁾

t

v(NADV_NE)

t

w(NADV)

ai14991c

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

(1)(2)

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

Symbol

Parameter

FSMC_NE low time

Min

2T_HCLK–0.5 2 T_HCLK+1

0.5

2T_HCLK–2 2T_HCLK+ 2

Max

Unit

t_w(NE)

t_{v(NOE_NE)}

t_w(NOE)

ns

FSMC_NEx low to FSMC_NOE low

FSMC_NOE low time

3

t_{h(NE_NOE)}

t_{v(A_NE)}

FSMC_NOE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

Address hold time after FSMC_NOE high

0

-

4.5

-

t_{h(A_NOE)}

4

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Electrical characteristics

STM32F415xx, STM32F417xx

(1)(2)

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

t_{v(BL_NE)}

t_{h(BL_NOE)}

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NOE high

Data to FSMC_NEx high setup time

Data to FSMC_NOEx high setup time

Data hold time after FSMC_NOE high

Data hold time after FSMC_NEx high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

-

1.5

ns

0

-

t_{su(Data_NE)}

t_{su(Data_NOE)}

t_{h(Data_NOE)}

t_{h(Data_NE)}

T_HCLK+4

-

T_HCLK+4

-

0

-

2

t_{v(NADV_NE)}

t_w(NADV)

-

T_HCLK

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

t

w(NE)

FSMC_NEx

FSMC_NOE

FSMC_NWE

t

h(NE_NWE)

v(NWE_NE)

w(NWE)

t

t_{v(A_NE)}

h(A_NWE)

FSMC_A[25:0]

Address

t_{v(BL_NE)}

t

h(BL_NWE)

FSMC_NBL[1:0]

NBL

t

v(Data_NE)

h(Data_NWE)

Data

FSMC_D[15:0]

FSMC_NADV⁽¹⁾

t

v(NADV_NE)

t

w(NADV)

ai14990

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

(1)(2)

Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

Symbol

Parameter

FSMC_NE low time

Min

Max

Unit

t_w(NE)

t_{v(NWE_NE)}

t_w(NWE)

3T_HCLK

3T_HCLK+ 4 ns

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low time

T_HCLK–0.5 T_HCLK+0.5 ns

T_HCLK–1

-

T_HCLK+2

ns

t_{h(NE_NWE)}

t_{v(A_NE)}

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

-

0

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Electrical characteristics

(1)(2)

Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

t_{h(A_NWE)}

t_{v(BL_NE)}

Address hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

FSMC_BL hold time after FSMC_NWE high

Data to FSMC_NEx low to Data valid

Data hold time after FSMC_NWE high

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

T_HCLK– 2

-

ns

-

1.5

t_{h(BL_NWE)}

t_{v(Data_NE)}

t_{h(Data_NWE)}

t_{v(NADV_NE)}

t_w(NADV)

T_HCLK– 1

-

T_HCLK+3

T_HCLK–1

-

2

T_HCLK+0.5 ns

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms

t

w(NE)

FSMC_NE

t

h(NE_NOE)

v(NOE_NE)

FSMC_NOE

t

w(NOE)

FSMC_NWE

t

t_{v(A_NE)}

h(A_NOE)

FSMC_A[25:16]

Address

t_{v(BL_NE)}

t

h(BL_NOE)

FSMC_NBL[1:0]

NBL

t

h(Data_NE)

t

su(Data_NE)

t

h(Data_NOE)

v(A_NE)

su(Data_NOE)

Address

Data

FSMC_AD[15:0]

FSMC_NADV

t

t_{h(AD_NADV)}

v(NADV_NE)

t

w(NADV)

ai14892b

(1)(2)

Table 77. Asynchronous multiplexed PSRAM/NOR read timings

Symbol

Parameter

FSMC_NE low time

Min

Max

3T_HCLK+1

Unit

t_w(NE)

3T_HCLK–1

ns

t_{v(NOE_NE)}FSMC_NEx low to FSMC_NOE low

t_w(NOE)FSMC_NOE low time

t_{h(NE_NOE)}FSMC_NOE high to FSMC_NE high hold time

2T_HCLK–0.5 2T_HCLK+0.5

T_HCLK–1

T_HCLK+1

0

-

t_{v(A_NE)}

FSMC_NEx low to FSMC_A valid

3

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STM32F415xx, STM32F417xx

(1)(2)

Table 77. Asynchronous multiplexed PSRAM/NOR read timings

(continued)

t_{v(NADV_NE)}FSMC_NEx low to FSMC_NADV low

1

2

ns

t_w(NADV)

t_{h(AD_NADV)}

t_{h(A_NOE)}

FSMC_NADV low time

T_HCLK– 2

T_HCLK+1

ns

FSMC_AD(adress) valid hold time after

FSMC_NADV high)

T_HCLK

-

Address hold time after FSMC_NOE high

T_HCLK–1

-

ns

t_{h(BL_NOE)}FSMC_BL time after FSMC_NOE high

t_{v(BL_NE)}FSMC_NEx low to FSMC_BL valid

0

-

2

-

t_{su(Data_NE)}Data to FSMC_NEx high setup time

t_{su(Data_NOE)}Data to FSMC_NOE high setup time

t_{h(Data_NE)}Data hold time after FSMC_NEx high

t_{h(Data_NOE)}Data hold time after FSMC_NOE high

T_HCLK+4

-

0

-

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms

t

w(NE)

FSMC_NEx

FSMC_NOE

t

h(NE_NWE)

v(NWE_NE)

w(NWE)

FSMC_NWE

t

t_{v(A_NE)}

h(A_NWE)

FSMC_A[25:16]

Address

t_{v(BL_NE)}

t

h(BL_NWE)

FSMC_NBL[1:0]

FSMC_AD[15:0]

NBL

t

h(Data_NWE)

t

v(A_NE)

v(Data_NADV)

Address

Data

t

t_{h(AD_NADV)}

v(NADV_NE)

t

w(NADV)

FSMC_NADV

ai14891B

(1)(2)

Table 78. Asynchronous multiplexed PSRAM/NOR write timings

Symbol

Parameter

FSMC_NE low time

Min

4T_HCLK–0.5 4T_HCLK+3

T_HCLK–0.5 T_HCLK-0.5

2T_HCLK–0.5 2T_HCLK+3

Max

Unit

t_w(NE)

t_{v(NWE_NE)}

t_w(NWE)

ns

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low tim e

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Electrical characteristics

(1)(2)

Table 78. Asynchronous multiplexed PSRAM/NOR write timings

t_{h(NE_NWE)}

t_{v(A_NE)}

t_{v(NADV_NE)}

t_w(NADV)

FSMC_NWE high to FSMC_NE high hold time

FSMC_NEx low to FSMC_A valid

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

T_HCLK

-

ns

-

1

0

2

T_HCLK– 2

T_HCLK+ 1

FSMC_AD(address) valid hold time after

FSMC_NADV high)

t_{h(AD_NADV)}

T_HCLK–2

-

ns

t_{h(A_NWE)}

t_{h(BL_NWE)}

t_{v(BL_NE)}

Address hold time after FSMC_NWE high

FSMC_BL hold time after FSMC_NWE high

FSMC_NEx low to FSMC_BL valid

T_HCLK

-

ns

T_HCLK–2

-

1.5

t_{v(Data_NADV)}FSMC_NADV high to Data valid

-

T_HCLK–0.5

-

t_{h(Data_NWE)}Data hold time after FSMC_NWE high

T_HCLK

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

Synchronous waveforms and timings

Figure 59 through Figure 62 represent synchronous waveforms and Table 80 through

Table 82 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

•

BurstAccessMode = FSMC_BurstAccessMode_Enable;

MemoryType = FSMC_MemoryType_CRAM;

WriteBurst = FSMC_WriteBurst_Enable;

CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual)

DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the T_HCLKis the HCLK clock period (with maximum

FSMC_CLK = 60 MHz).

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Electrical characteristics

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Figure 59. Synchronous multiplexed NOR/PSRAM read timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

Data latency = 0

d(CLKL-NExL)

t

d(CLKL-NExH)

FSMC_NEx

t

d(CLKL-NADVL)

d(CLKL-NADVH)

FSMC_NADV

t

d(CLKL-AIV)

d(CLKL-AV)

FSMC_A[25:16]

t

d(CLKL-NOEH)

d(CLKL-NOEL)

FSMC_NOE

t

h(CLKH-ADV)

d(CLKL-ADIV)

t

su(ADV-CLKH)

d(CLKL-ADV)

h(CLKH-ADV)

FSMC_AD[15:0]

AD[15:0]

t

D1

D2

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

t

h(CLKH-NWAITV)

su(NWAITV-CLKH)

ai14893g

(1)(2)

Max

Table 79. Synchronous multiplexed NOR/PSRAM read timings

Symbol

Parameter

Min

Unit

t_w(CLK)

FSMC_CLK period

2T_HCLK

-

0

-

ns

t_d(CLKL-NExL)FSMC_CLK low to FSMC_NEx low (x=0..2)

t_d(CLKL-NExH)FSMC_CLK low to FSMC_NEx high (x= 0…2)

t_{d(CLKL-NADVL)}FSMC_CLK low to FSMC_NADV low

t_{d(CLKL-NADVH)}FSMC_CLK low to FSMC_NADV high

-

2

-

2

-

2

-

t_d(CLKL-AV)

t_d(CLKL-AIV)

FSMC_CLK low to FSMC_Ax valid (x=16…25)

FSMC_CLK low to FSMC_Ax invalid (x=16…25)

0

-

0

-

t_d(CLKL-NOEL)FSMC_CLK low to FSMC_NOE low

t_d(CLKL-NOEH)FSMC_CLK low to FSMC_NOE high

0

-

2

-

t_d(CLKL-ADV)

FSMC_CLK low to FSMC_AD[15:0] valid

4.5

-

t_d(CLKL-ADIV)FSMC_CLK low to FSMC_AD[15:0] invalid

0

6

t_su(ADV-CLKH)FSMC_A/D[15:0] valid data before FSMC_CLK high

-

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(1)(2)

Table 79. Synchronous multiplexed NOR/PSRAM read timings

(continued)

ns

t_h(CLKH-ADV)FSMC_A/D[15:0] valid data after FSMC_CLK high

0

4

0

-

t_{su(NWAIT-CLKH)}FSMC_NWAIT valid before FSMC_CLK high

t_{h(CLKH-NWAIT)}FSMC_NWAIT valid after FSMC_CLK high

-

ns

-

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

Figure 60. Synchronous multiplexed PSRAM write timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

Data latency = 0

d(CLKL-NExL)

t

d(CLKL-NExH)

FSMC_NEx

t

d(CLKL-NADVL)

d(CLKL-NADVH)

FSMC_NADV

t

d(CLKL-AIV)

d(CLKL-AV)

FSMC_A[25:16]

FSMC_NWE

t

d(CLKL-NWEL)

d(CLKL-NWEH)

t

d(CLKL-ADIV)

t

d(CLKL-Data)

D1

t

d(CLKL-Data)

d(CLKL-ADV)

FSMC_AD[15:0]

AD[15:0]

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

FSMC_NBL

t

h(CLKH-NWAITV)

su(NWAITV-CLKH)

t

d(CLKL-NBLH)

ai14992g

(1)(2)

Table 80. Synchronous multiplexed PSRAM write timings

Symbol

Parameter

Min

Max

Unit

t_w(CLK)

FSMC_CLK period

2T_HCLK

-

1

-

ns

t_d(CLKL-NExL)FSMC_CLK low to FSMC_NEx low (x=0..2)

t_d(CLKL-NExH)FSMC_CLK low to FSMC_NEx high (x= 0…2)

t_{d(CLKL-NADVL)}FSMC_CLK low to FSMC_NADV low

t_{d(CLKL-NADVH)}FSMC_CLK low to FSMC_NADV high

-

1

-

0

-

0

-

t_d(CLKL-AV)

FSMC_CLK low to FSMC_Ax valid (x=16…25)

0

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Electrical characteristics

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(1)(2)

Table 80. Synchronous multiplexed PSRAM write timings

t_d(CLKL-AIV)

FSMC_CLK low to FSMC_Ax invalid (x=16…25)

8

-

ns

t_d(CLKL-NWEL)FSMC_CLK low to FSMC_NWE low

0.5

t_d(CLKL-NWEH)FSMC_CLK low to FSMC_NWE high

t_d(CLKL-ADIV)FSMC_CLK low to FSMC_AD[15:0] invalid

t_d(CLKL-DATA)FSMC_A/D[15:0] valid data after FSMC_CLK low

t_d(CLKL-NBLH)FSMC_CLK low to FSMC_NBL high

0

-

3

-

0

4

0

t_{su(NWAIT-CLKH)}FSMC_NWAIT valid before FSMC_CLK high

t_{h(CLKH-NWAIT)}FSMC_NWAIT valid after FSMC_CLK high

-

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

t

d(CLKL-NExH)

d(CLKL-NExL)

Data latency = 0

d(CLKL-NADVH)

FSMC_NEx

t

d(CLKL-NADVL)

FSMC_NADV

t

d(CLKL-AIV)

d(CLKL-AV)

FSMC_A[25:0]

t

d(CLKL-NOEL)

d(CLKL-NOEH)

FSMC_NOE

t

su(DV-CLKH)

h(CLKH-DV)

su(DV-CLKH)

t

h(CLKH-DV)

FSMC_D[15:0]

FSMC_NWAIT

D1

D2

h(CLKH-NWAITV)

t

su(NWAITV-CLKH)

(WAITCFG = 1b, WAITPOL + 0b)

t

h(CLKH-NWAITV)

su(NWAITV-CLKH)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

t

su(NWAITV-CLKH)

h(CLKH-NWAITV)

ai14894f

(1)(2)

Table 81. Synchronous non-multiplexed NOR/PSRAM read timings

Symbol

t_w(CLK)

t_d(CLKL-NExL)

Parameter

Min

Max

Unit

FSMC_CLK period

2T_HCLK–0.5

-

ns

FSMC_CLK low to FSMC_NEx low (x=0..2)

0.5

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Electrical characteristics

(1)(2)

Table 81. Synchronous non-multiplexed NOR/PSRAM read timings

(continued)

t_d(CLKL-NExH)

FSMC_CLK low to FSMC_NEx high (x= 0…2)

0

-

2

-

ns

t_{d(CLKL-NADVL)}FSMC_CLK low to FSMC_NADV low

t_{d(CLKL-NADVH)}FSMC_CLK low to FSMC_NADV high

3

t_d(CLKL-AV)

FSMC_CLK low to FSMC_Ax valid (x=16…25)

FSMC_CLK low to FSMC_Ax invalid (x=16…25)

FSMC_CLK low to FSMC_NOE low

-

2

0

-

t_d(CLKL-AIV)

t_d(CLKL-NOEL)

t_d(CLKL-NOEH)

t_su(DV-CLKH)

t_h(CLKH-DV)

-

0.5

-

FSMC_CLK low to FSMC_NOE high

1.5

6

FSMC_D[15:0] valid data before FSMC_CLK high

FSMC_D[15:0] valid data after FSMC_CLK high

-

3

-

t_{su(NWAIT-CLKH)}FSMC_NWAIT valid before FSMC_CLK high

t_{h(CLKH-NWAIT)}FSMC_NWAIT valid after FSMC_CLK high

4

-

0

-

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

Figure 62. Synchronous non-multiplexed PSRAM write timings

BUSTURN = 0

t

w(CLK)

FSMC_CLK

t

d(CLKL-NExL)

FSMC_NEx

d(CLKL-NExH)

Data latency = 0

d(CLKL-NADVH)

t

d(CLKL-NADVL)

FSMC_NADV

FSMC_A[25:0]

FSMC_NWE

t

d(CLKL-AIV)

d(CLKL-AV)

t

d(CLKL-NWEL)

d(CLKL-NWEH)

t

d(CLKL-Data)

FSMC_D[15:0]

D1

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

FSMC_NBL

t

d(CLKL-NBLH)

su(NWAITV-CLKH)

t

h(CLKH-NWAITV)

ai14993g

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(1)(2)

Table 82. Synchronous non-multiplexed PSRAM write timings

Symbol

t_w(CLK)

Parameter

Min

Max Unit

FSMC_CLK period

2T_HCLK

-

1

-

ns

t^d(CLKL-NExL)

FSMC_CLK low to FSMC_NEx low (x=0..2)

FSMC_CLK low to FSMC_NEx high (x= 0…2)

-

1

-

t_d(CLKL-NExH)

t_{d(CLKL-NADVL)}FSMC_CLK low to FSMC_NADV low

t_{d(CLKL-NADVH)}FSMC_CLK low to FSMC_NADV high

7

-

6

-

t_d(CLKL-AV)

t_d(CLKL-AIV)

FSMC_CLK low to FSMC_Ax valid (x=16…25)

FSMC_CLK low to FSMC_Ax invalid (x=16…25)

FSMC_CLK low to FSMC_NWE low

0

-

6

-

t_d(CLKL-NWEL)

t_d(CLKL-NWEH)

t_d(CLKL-Data)

t_d(CLKL-NBLH)

1

-

FSMC_CLK low to FSMC_NWE high

2

-

FSMC_D[15:0] valid data after FSMC_CLK low

FSMC_CLK low to FSMC_NBL high

3

-

3

4

0

t_{su(NWAIT-CLKH)}FSMC_NWAIT valid before FSMC_CLK high

t_{h(CLKH-NWAIT)}FSMC_NWAIT valid after FSMC_CLK high

-

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

PC Card/CompactFlash controller waveforms and timings

Figure 63 through Figure 68 represent synchronous waveforms, and Table 83 and Table 84

provide the corresponding timings. The results shown in this table are obtained with the

following FSMC configuration:

•

COM.FSMC_SetupTime = 0x04;

COM.FSMC_WaitSetupTime = 0x07;

COM.FSMC_HoldSetupTime = 0x04;

COM.FSMC_HiZSetupTime = 0x00;

ATT.FSMC_SetupTime = 0x04;

ATT.FSMC_WaitSetupTime = 0x07;

ATT.FSMC_HoldSetupTime = 0x04;

ATT.FSMC_HiZSetupTime = 0x00;

IO.FSMC_SetupTime = 0x04;

IO.FSMC_WaitSetupTime = 0x07;

IO.FSMC_HoldSetupTime = 0x04;

IO.FSMC_HiZSetupTime = 0x00;

TCLRSetupTime = 0;

TARSetupTime = 0.

In all timing tables, the T_HCLKis the HCLK clock period.

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Electrical characteristics

Figure 63. PC Card/CompactFlash controller waveforms for common memory read

access

FSMC_NCE4_2⁽¹⁾

FSMC_NCE4_1

t

h(NCEx-AI)

t

v(NCEx-A)

FSMC_A[10:0]

t

h(NCEx-NREG)

h(NCEx-NIORD)

t

d(NREG-NCEx)

d(NIORD-NCEx)

h(NCEx-NIOWR

)

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

FSMC_NWE

t

d(NCE4_1-NOE)

w(NOE)

FSMC_NOE

t

h(NOE-D)

su(D-NOE)

FSMC_D[15:0]

ai14895b

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

Figure 64. PC Card/CompactFlash controller waveforms for common memory write

access

FSMC_NCE4_1

FSMC_NCE4_2

FSMC_A[10:0]

High

t

h(NCE4_1-AI)

v(NCE4_1-A)

t

h(NCE4_1-NREG)

h(NCE4_1-NIORD)

h(NCE4_1-NIOWR)

t

d(NREG-NCE4_1)

d(NIORD-NCE4_1)

FSMC_NREG

FSMC_NIOWR

FSMC_NIORD

t

d(NCE4_1-NWE)

w(NWE)

d(NWE-NCE4_1)

FSMC_NWE

FSMC_NOE

MEMxHIZ =1

t

d(D-NWE)

t

v(NWE-D)

h(NWE-D)

FSMC_D[15:0]

ai14896b

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Electrical characteristics

STM32F415xx, STM32F417xx

Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read

access

FSMC_NCE4_1

t

h(NCE4_1-AI)

v(NCE4_1-A)

FSMC_NCE4_2

FSMC_A[10:0]

High

FSMC_NIOWR

FSMC_NIORD

t

h(NCE4_1-NREG)

d(NREG-NCE4_1)

FSMC_NREG

FSMC_NWE

t

d(NOE-NCE4_1)

d(NCE4_1-NOE)

w(NOE)

FSMC_NOE

t

su(D-NOE)

h(NOE-D)

FSMC_D[15:0]⁽¹⁾

ai14897b

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

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Electrical characteristics

Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write

access

FSMC_NCE4_1

High

FSMC_NCE4_2

FSMC_A[10:0]

t

h(NCE4_1-AI)

v(NCE4_1-A)

FSMC_NIOWR

FSMC_NIORD

t

d(NREG-NCE4_1)

h(NCE4_1-NREG)

FSMC_NREG

t

d(NCE4_1-NWE)

w(NWE)

FSMC_NWE

t

d(NWE-NCE4_1)

FSMC_NOE

t

v(NWE-D)

FSMC_D[7:0](1)

ai14898b

1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).

Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access

FSMC_NCE4_1

FSMC_NCE4_2

t

h(NCE4_1-AI)

v(NCEx-A)

FSMC_A[10:0]

FSMC_NREG

FSMC_NWE

FSMC_NOE

FSMC_NIOWR

t

w(NIORD)

t

d(NIORD-NCE4_1)

FSMC_NIORD

t

su(D-NIORD)

d(NIORD-D)

FSMC_D[15:0]

ai14899B

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Electrical characteristics

STM32F415xx, STM32F417xx

Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access

FSMC_NCE4_1

FSMC_NCE4_2

t

h(NCE4_1-AI)

v(NCEx-A)

FSMC_A[10:0]

FSMC_NREG

FSMC_NWE

FSMC_NOE

FSMC_NIORD

t

w(NIOWR)

d(NCE4_1-NIOWR)

FSMC_NIOWR

ATTxHIZ =1

t

h(NIOWR-D)

t

v(NIOWR-D)

FSMC_D[15:0]

ai14900c

Table 83. Switching characteristics for PC Card/CF read and write cycles

(1)(2)

in attribute/common space

Symbol

Parameter

Min

Max

Unit

t_v(NCEx-A)

FSMC_Ncex low to FSMC_Ay valid

FSMC_NCEx high to FSMC_Ax invalid

-

0

ns

t_{h(NCEx_AI)}

4

-

t_d(NREG-NCEx)FSMC_NCEx low to FSMC_NREG valid

t_h(NCEx-NREG)FSMC_NCEx high to FSMC_NREG invalid

t_d(NCEx-NWE)FSMC_NCEx low to FSMC_NWE low

t_d(NCEx-NOE)FSMC_NCEx low to FSMC_NOE low

-

3.5

T_HCLK+4

-

5T_HCLK+0.5

-

5T_HCLK+0.5

t_w(NOE)

FSMC_NOE low width

8T_HCLK–1

5T_HCLK+2.5

4.5

8T_HCLK+1

t_{d(NOE_NCEx)}FSMC_NOE high to FSMC_NCEx high

-

t_{su (D-NOE)}

t_h(N0E-D)

t_w(NWE)

FSMC_D[15:0] valid data before FSMC_NOE high

FSMC_N0E high to FSMC_D[15:0] invalid

FSMC_NWE low width

-

3

-

8T_HCLK–0.5

8T_HCLK+ 3

t_{d(NWE_NCEx)}FSMC_NWE high to FSMC_NCEx high

t_d(NCEx-NWE)FSMC_NCEx low to FSMC_NWE low

-

ns

5T_HCLK–1

-

5T_HCLK+ 1

ns

t_v(NWE-D)

FSMC_NWE low to FSMC_D[15:0] valid

-

0

-

t_h(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid

t_d(D-NWE) FSMC_D[15:0] valid before FSMC_NWE high

8T_HCLK–1

13T_HCLK–1

-

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

152/186

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STM32F415xx, STM32F417xx

Electrical characteristics

Table 84. Switching characteristics for PC Card/CF read and write cycles

(1)(2)

in I/O space

Parameter

FSMC_NIOWR low width

FSMC_NIOWR low to FSMC_D[15:0] valid

FSMC_NIOWR high to FSMC_D[15:0] invalid

Symbol

Min

Max

Unit

t_w(NIOWR)

t_v(NIOWR-D)

t_h(NIOWR-D)

8T_HCLK–1

-

ns

-

5T_HCLK– 1

8T_HCLK– 2

-

t_{d(NCE4_1-NIOWR)}FSMC_NCE4_1 low to FSMC_NIOWR valid

t_{h(NCEx-NIOWR)}FSMC_NCEx high to FSMC_NIOWR invalid

t_{d(NIORD-NCEx)}FSMC_NCEx low to FSMC_NIORD valid

t_{h(NCEx-NIORD)}FSMC_NCEx high to FSMC_NIORD) valid

-

5T_HCLK+ 2.5

5T_HCLK–1.5

-

5T_HCLK+ 2

5T_HCLK– 1.5

-

t_w(NIORD)

t_su(D-NIORD)

t_d(NIORD-D)

FSMC_NIORD low width

8T_HCLK–0.5

FSMC_D[15:0] valid before FSMC_NIORD high

FSMC_D[15:0] valid after FSMC_NIORD high

9

0

-

1. C_L= 30 pF.

2. Based on characterization, not tested in production.

NAND controller waveforms and timings

Figure 69 through Figure 72 represent synchronous waveforms, and Table 85 and Table 86

provide the corresponding timings. The results shown in this table are obtained with the

following FSMC configuration:

•

COM.FSMC_SetupTime = 0x01;

COM.FSMC_WaitSetupTime = 0x03;

COM.FSMC_HoldSetupTime = 0x02;

COM.FSMC_HiZSetupTime = 0x01;

ATT.FSMC_SetupTime = 0x01;

ATT.FSMC_WaitSetupTime = 0x03;

ATT.FSMC_HoldSetupTime = 0x02;

ATT.FSMC_HiZSetupTime = 0x01;

Bank = FSMC_Bank_NAND;

MemoryDataWidth = FSMC_MemoryDataWidth_16b;

ECC = FSMC_ECC_Enable;

ECCPageSize = FSMC_ECCPageSize_512Bytes;

TCLRSetupTime = 0;

TARSetupTime = 0.

In all timing tables, the T_HCLKis the HCLK clock period.

DocID022063 Rev 4

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Electrical characteristics

STM32F415xx, STM32F417xx

Figure 69. NAND controller waveforms for read access

FSMC_NCEx

ALE (FSMC_A17)

CLE (FSMC_A16)

FSMC_NWE

t_d(ALE-NOE)

t_h(NOE-ALE)

FSMC_NOE (NRE)

FSMC_D[15:0]

t

h(NOE-D)

su(D-NOE)

ai14901c

Figure 70. NAND controller waveforms for write access

FSMC_NCEx

ALE (FSMC_A17)

CLE (FSMC_A16)

t_d(ALE-NWE)

t_h(NWE-ALE)

FSMC_NWE

FSMC_NOE (NRE)

FSMC_D[15:0]

t_v(NWE-D)

t_h(NWE-D)

ai14902c

154/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Electrical characteristics

Figure 71. NAND controller waveforms for common memory read access

FSMC_NCEx

ALE (FSMC_A17)

CLE (FSMC_A16)

t_d(ALE-NOE)

t_h(NOE-ALE)

FSMC_NWE

FSMC_NOE

t_w(NOE)

t_su(D-NOE)

t_h(NOE-D)

FSMC_D[15:0]

ai14912c

Figure 72. NAND controller waveforms for common memory write access

FSMC_NCEx

ALE (FSMC_A17)

CLE (FSMC_A16)

t_d(ALE-NOE)

t_w(NWE)

t_h(NOE-ALE)

FSMC_NWE

FSMC_NOE

t_d(D-NWE)

t_v(NWE-D)

t_h(NWE-D)

FSMC_D[15:0]

ai14913c

(1)

Table 85. Switching characteristics for NAND Flash read cycles

Symbol

Parameter

Min

Max

Unit

4T_HCLK

0.5

–

t_w(N0E)

FSMC_NOE low width

4T_HCLK+ 3

ns

t_su(D-NOE)FSMC_D[15-0] valid data before FSMC_NOE high

t_h(NOE-D)FSMC_D[15-0] valid data after FSMC_NOE high

10

0

-

ns

-

t_d(ALE-NOE)FSMC_ALE valid before FSMC_NOE low

t_h(NOE-ALE)FSMC_NWE high to FSMC_ALE invalid

1. C_L= 30 pF.

-

3T_HCLK

-

3T_HCLK– 2

DocID022063 Rev 4

155/186

Electrical characteristics

STM32F415xx, STM32F417xx

(1)

Table 86. Switching characteristics for NAND Flash write cycles

Symbol

Parameter

FSMC_NWE low width

Min

Max

Unit

t_w(NWE)

t_v(NWE-D)

4T_HCLK–1

-

4T_HCLK+ 3

ns

FSMC_NWE low to FSMC_D[15-0] valid

FSMC_NWE high to FSMC_D[15-0] invalid

FSMC_D[15-0] valid before FSMC_NWE high

FSMC_ALE valid before FSMC_NWE low

FSMC_NWE high to FSMC_ALE invalid

0

t_h(NWE-D)

3T_HCLK–2

5T_HCLK–3

-

t_d(D-NWE)

-

t_d(ALE-NWE)

t_h(NWE-ALE)

1. C_L= 30 pF.

3T_HCLK

-

3T_HCLK–2

5.3.26

Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from

tests performed under the ambient temperature, f frequency and V supply voltage

HCLK

DD

summarized in Table 13, with the following configuration:

•

PCK polarity: falling

VSYNC and HSYNC polarity: high

Data format: 14 bits

Figure 73. DCMI timing diagram

1/DCMI_PIXCLK

Pixel clock

HSYNC

t_su(HSYNC)

t_h(HSYNC)

t_su(VSYNC)

t_h(HSYNC)

VSYNC

t_su(DATA)t_h(DATA)

DATA[0:13]

MS32414V1

(1)

Table 87. DCMI characteristics

Parameter

Symbol

Min

Max

Unit

Frequency ratio DCMI_PIXCLK/f_HCLK

-

0.4

DCMI_PIXCLK

D_pixel

Pixel clock input

-

54

70

MHz

%

Pixel clock input duty cycle

30

156/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Electrical characteristics

(1)

Table 87. DCMI characteristics (continued)

Symbol

t_su(DATA)

Parameter

Data input setup time

Min

2.5

1

Max

Unit

-

t_h(DATA)

Data hold time

t_su(HSYNC)

t_su(VSYNC)

,

ns

HSYNC/VSYNC input setup time

2

-

t_h(HSYNC)

,

HSYNC/VSYNC input hold time

0.5

t_h(VSYNC)

1. Data based on characterization results, not tested in production.

5.3.27

SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 88 are derived from tests

performed under ambient temperature, f frequency and V supply voltage conditions

PCLKx

DD

summarized in Table 14 with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5V

DD

Refer to Section 5.3.16: I/O port characteristics for more details on the input/output

characteristics.

Figure 74. SDIO high-speed mode

t

r

f

t

C

t

W(CKH)

W(CKL)

CK

t

OV

OH

D, CMD

(output)

t

ISU

IH

D, CMD

(input)

ai14887

DocID022063 Rev 4

157/186

Electrical characteristics

STM32F415xx, STM32F417xx

Figure 75. SD default mode

CK

t

OVD

OHD

D, CMD

(output)

ai14888

(1)

Table 88. Dynamic characteristics: SD / MMC characteristics

Symbol

f_PP

Parameter

Conditions

Min

Typ

Max

Unit

Clock frequency in data transfer mode

SDIO_CK/f_PCLK2frequency ratio

Clock low time

0

-

48

8/3

-

MHz

-

9

t_W(CKL)

t_W(CKH)

fpp = 48 MHz

8.5

8.3

ns

Clock high time

10

-

CMD, D inputs (referenced to CK) in MMC and SD HS mode

t_ISU

t_IH

Input setup time HS

Input hold time HS

fpp = 48 MHz

3

0

-

CMD, D outputs (referenced to CK) in MMC and SD HS mode

t_OV

t_OH

Output valid time HS

Output hold time HS

fpp = 48 MHz

-

4.5

-

6

-

1

CMD, D inputs (referenced to CK) in SD default mode

t_ISUD

t_IHD

Input setup time SD

Input hold time SD

fpp = 24 MHz

1.5

0.5

-

CMD, D outputs (referenced to CK) in SD default mode

t_OVD

t_OHD

Output valid default time SD

Output hold default time SD

fpp = 24 MHz

-

4.5

-

7

-

0.5

1. Data based on characterization results, not tested in production.

5.3.28

RTC characteristics

Table 89. RTC characteristics

Symbol

Parameter

Conditions

Min

Max

Any read/write operation

from/to an RTC register

-

f_PCLK1/RTCCLK frequency ratio

4

-

158/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Package characteristics

6

Package characteristics

6.1

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

DocID022063 Rev 4

159/186

Package characteristics

STM32F415xx, STM32F417xx

Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline

e1

A1 ball location

D

e

Detail A

E

e2

G

A2

A

F

Bump side

Wafer back side

Side view

Detail A

rotated by 90 °C

A1

eee

b

Seating plane

A0JW_ME

Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

0.520

0.165

0.350

0.240

4.178

3.964

0.570

0.190

0.380

0.270

4.218

3.969

0.400

3.600

3.200

0.312

0.385

0.620

0.215

0.410

0.300

4.258

4.004

0.0205

0.0065

0.0138

0.0094

0.1645

0.1561

0.0224

0.0075

0.015

0.0244

0.0085

0.0161

0.0118

0.1676

0.1576

0.0106

0.1661

0.1563

0.0157

0.1417

0.126

D

E

e

e1

e2

F

0.0123

0.0152

G

eee

0.050

0.0020

1. Values in inches are converted from mm and rounded to 4 decimal digits.

160/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Package characteristics

Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline

A

A2

A1

b

E

E1

e

D1

D

c

L1

L

ai14398b

1. Drawing is not to scale.

Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.050

1.350

0.170

0.090

0.0020

0.0531

0.0067

0.0035

1.400

0.220

0.0551

0.0087

c

D

12.000

10.000

12.000

10.000

0.500

3.5°

0.4724

0.3937

0.4724

0.3937

0.0197

3.5°

D1

E

E1

e

θ

0°

7°

0°

7°

L

0.450

0.600

1.000

0.750

0.0177

0.0236

0.0394

0.0295

L1

Number of pins

64

N

1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID022063 Rev 4

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Package characteristics

STM32F415xx, STM32F417xx

Figure 78. LQFP64 recommended footprint

48

33

0.3

49

32

0.5

12.7

10.3

64

17

1.2

1

16

7.8

12.7

ai14909

1. Drawing is not to scale.

2. Dimensions are in millimeters.

162/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Package characteristics

Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline

SEATING

PLANE

C

0.25 mm

GAUGE PLANE

ccc

C

L

D

L1

D1

D3

75

51

50

76

100

26

PIN 1

IDENTIFICATION

25

1

e

1L_ME_V4

1. Drawing is not to scale.

(1)

Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data

millimeters

Typ

inches

Typ

Symbol

Min

Max

Min

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

16.200

14.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

0.050

1.350

0.170

0.090

15.800

13.800

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

1.400

0.220

0.0551

0.0087

c

D

16.000

14.000

12.000

16.000

14.000

12.000

0.500

0.6299

0.5512

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

D1

D3

E

15.80v

13.800

16.200

14.200

0.6220

0.5433

0.6378

0.5591

E1

E3

e

L

0.450

0°

0.600

0.750

0.0177

0°

0.0295

L1

k

1.000

3.5°

7°

ccc

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID022063 Rev 4

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Package characteristics

STM32F415xx, STM32F417xx

Figure 80. LQFP100 recommended footprint

75

51

76

50

0.5

0.3

16.7 14.3

100

26

1.2

1

25

12.3

16.7

ai14906

1. Drawing is not to scale.

2. Dimensions are in millimeters.

164/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Package characteristics

Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline

Seating plane

C

A

A2 A1

c

b

0.25 mm

gage plane

ccc

C

k

D

D1

A1

L

D3

L1

108

73

72

109

E3 E1

E

144

37

Pin 1

identification

1

36

ME_1A

e

1. Drawing is not to scale.

Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

22.200

20.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.874

0.050

1.350

0.170

0.090

21.800

19.800

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

1.400

0.220

0.0551

0.0087

c

D

22.000

20.000

17.500

22.000

20.000

17.500

0.500

0.8661

0.7874

0.689

D1

D3

E

0.7953

21.800

19.800

22.200

20.200

0.8583

0.7795

0.8661

0.7874

0.6890

0.0197

0.0236

0.0394

0.8740

0.7953

E1

E3

e

L

0.450

0.600

0.750

0.0177

0.0295

L1

1.000

DocID022063 Rev 4

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Package characteristics

STM32F415xx, STM32F417xx

Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

k

0°

3.5°

7°

0°

3.5°

7°

ccc

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 82. LQFP144 recommended footprint

1.35

108

73

109

72

0.35

0.5

17.85

22.6

19.9

144

37

1

36

19.9

22.6

ai14905c

1. Drawing is not to scale.

2. Dimensions are in millimeters.

166/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Package characteristics

Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm,

package outline

C

Seating plane

A2

ddd

C

A

A1

A1 ball

A

A1 ball

E

identifier index area

e

F

A

F

D

e

B

R

15

1

TOP VIEW

BOTTOM VIEW

Øb (176 + 25 balls)

Ø eee M

Ø fff

C

A B

M

A0E7_ME_V4

1. Drawing is not to scale.

Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm

mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

0.460

0.050

0.530

0.080

0.600

0.110

0.0181

0.002

0.0209

0.0031

0.0236

0.0043

A1

A2

0.400

0.450

0.500

0.0157

0.0177

0.0197

b

D

0.230

9.900

0.280

10.000

0.650

0.330

10.100

0.0091

0.3898

0.0110

0.3937

0.0256

0.0177

0.0130

0.3976

E

e

F

0.425

0.450

0.475

0.080

0.150

0.080

0.0167

0.0187

0.0031

0.0059

0.0031

ddd

eee

fff

1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID022063 Rev 4

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Package characteristics

STM32F415xx, STM32F417xx

Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline

C Seating plane

A A2

0.25 mm

gauge plane

k

c

A1

ccc

C

A1

HD

D

L

L1

ZD

ZE

89

132

133

176

88

b

HE

E

45

Pin 1

1

44

identification

e

1T_ME

1. Drawing is not to scale.

Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

24.100

0.0630

0.050

1.350

0.170

0.090

23.900

0.0020

0.0531

0.0067

0.0035

0.9409

0.0060

0.0106

0.0079

0.9488

C

D

E

e

0.500

0.0197

HD

HE

L

25.900

0.450

26.100

0.750

1.0200

0.0177

1.0276

0.0295

L1

ZD

ZE

1.000

1.250

0.0394

0.0492

168/186

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STM32F415xx, STM32F417xx

Package characteristics

Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

ccc

k

0.080

7 °

0.0031

7 °

0 °

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 85. LQFP176 recommended footprint

1.2

176

133

132

0.5

1

0.3

44

45

89

88

1.2

21.8

26.7

1T_FP_V1

1. Dimensions are expressed in millimeters.

DocID022063 Rev 4

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Package characteristics

STM32F415xx, STM32F417xx

6.2

Thermal characteristics

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max x Θ )

J

A

D

JA

Where:

•

T max is the maximum ambient temperature in °C,

A

Θ

is the package junction-to-ambient thermal resistance, in °C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (V × I ) + Σ((V – V ) × I ),

OL OL DD OH OH

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 96. Package thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

46

43

Thermal resistance junction-ambient

LQFP100 - 14 × 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP144 - 20 × 20 mm / 0.5 mm pitch

40

Θ_JA

°C/W

Thermal resistance junction-ambient

LQFP176 - 24 × 24 mm / 0.5 mm pitch

38

Thermal resistance junction-ambient

UFBGA176 - 10× 10 mm / 0.65 mm pitch

39

Thermal resistance junction-ambient

WLCSP90 - 0.400 mm pitch

38.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

170/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Part numbering

7

Part numbering

Table 97. Ordering information scheme

STM32

Example:

F

415 R

E

T

6 xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

415 = STM32F41x, connectivity, cryptographic acceleration

417= STM32F41x, connectivity, camera interface, Ethernet

cryptographic acceleration, Ethernet,

Pin count

R = 64 pins

O = 90 pins

V = 100 pins

Z = 144 pins

I = 176 pins

Flash memory size

E = 512 Kbytes of Flash memory

G = 1024 Kbytes of Flash memory

Package

T = LQFP

H = UFBGA

Y = WLCSP

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

7 = Industrial temperature range, –40 to 105 °C.

Options

xxx = programmed parts

TR = tape and reel

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

DocID022063 Rev 4

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Application block diagrams

STM32F415xx, STM32F417xx

Appendix A Application block diagrams

A.1

USB OTG full speed (FS) interface solutions

Figure 86. USB controller configured as peripheral-only and used

in Full speed mode

V_DD

5V to V_DD

Volatge regulator

(1)

STM32F4xx

VBUS

DM

PA11//PB14

OSC_IN

DP

PA12/PB15

V

SS

OSC_OUT

MS19000V5

1. External voltage regulator only needed when building a V_BUSpowered device.

2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance

thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

Figure 87. USB controller configured as host-only and used in full speed mode

V_DD

EN

GPIO

Current limiter

5 V Pwr

(1)

power switch

Overcurrent

GPIO+IRQ

STM32F4xx

VBUS

DM

PA11//PB14

OSC_IN

DP

PA12/PB15

V_SS

OSC_OUT

MS19001V4

1. The current limiter is required only if the application has to support a V_BUSpowered device. A basic power

switch can be used if 5 V are available on the application board.

2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance

thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

172/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Application block diagrams

Figure 88. USB controller configured in dual mode and used in full speed mode

V_DD

5 V to V_DD

voltage regulator

(1)

V_DD

EN

GPIO

5 V Pwr

Current limiter

(2)

Overcurrent

power switch

GPIO+IRQ

STM32F4xx

VBUS

PA9/PB13

DM

PA11/PB14

OSC_IN

DP

(3)

PA12/PB15

PA10/PB12

ID

OSC_OUT

V

SS

MS19002V3

1. External voltage regulator only needed when building a V_BUSpowered device.

2. The current limiter is required only if the application has to support a V_BUSpowered device. A basic power

switch can be used if 5 V are available on the application board.

3. The ID pin is required in dual role only.

4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance

thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

DocID022063 Rev 4

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Application block diagrams

STM32F415xx, STM32F417xx

A.2

USB OTG high speed (HS) interface solutions

Figure 89. USB controller configured as peripheral, host, or dual-mode

and used in high speed mode

STM32F4xx

FS PHY

DP

not connected

DM

USB HS

OTG Ctrl

DP

ULPI_CLK

DM

ULPI_D[7:0]

(2)

ID

V_BUS

USB

connector

ULPI_DIR

ULPI_STP

ULPI

V_SS

ULPI_NXT

High speed

OTG PHY

XT1

PLL

24 or 26 MHz XT⁽¹⁾

MCO1 or MCO2

XI

MS19005V2

1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F41x

with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible

connection.

2. The ID pin is required in dual role only.

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STM32F415xx, STM32F417xx

Application block diagrams

A.3

Ethernet interface solutions

Figure 90. MII mode using a 25 MHz crystal

STM32

MII_TX_CLK

MII_TX_EN

MII_TXD[3:0]

MII_CRS

MCU

Ethernet

MAC 10/100

Ethernet

PHY 10/100

MII

MII_COL

= 15 pins

(1)

HCLK

MII_RX_CLK

MII_RXD[3:0]

MII_RX_DV

MII_RX_ER

MII + MDC

= 17 pins

IEEE1588 PTP

Timer

input

trigger

Timestamp

comparator

MDIO

MDC

TIM2

(2)

PPS_OUT

HCLK

MCO1/MCO2

PLL

XTAL

OSC

25 MHz

PHY_CLK 25 MHz

XT1

MS19968V1

1. f_HCLKmust be greater than 25 MHz.

2. Pulse per second when using IEEE1588 PTP optional signal.

Figure 91. RMII with a 50 MHz oscillator

STM32

Ethernet

PHY 10/100

MCU

RMII_TX_EN

Ethernet

MAC 10/100

RMII_TXD[1:0]

RMII_RXD[1:0]

RMII_CRX_DV

RMII_REF_CLK

RMII

= 7 pins

(1)

HCLK

RMII + MDC

= 9 pins

IEEE1588 PTP

MDIO

MDC

Timer

input

trigger

Timestamp

comparator

TIM2

/2 or /20

synchronous

2.5 or 25 MHz

50 MHz

HCLK

OSC

50 MHz

PLL

PHY_CLK 50 MHz XT1

50 MHz

MS19969V1

1. f_HCLKmust be greater than 25 MHz.

DocID022063 Rev 4

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Application block diagrams

STM32F415xx, STM32F417xx

Figure 92. RMII with a 25 MHz crystal and PHY with PLL

STM32F

Ethernet

PHY 10/100

MCU

RMII_TX_EN

Ethernet

MAC 10/100

RMII_TXD[1:0]

RMII_RXD[1:0]

RMII_CRX_DV

RMII_REF_CLK

RMII

(1)

HCLK

= 7 pins

REF_CLK

RMII + MDC

= 9 pins

IEEE1588 PTP

MDIO

MDC

Timer

input

trigger

Timestamp

comparator

TIM2

/2 or /20

synchronous

2.5 or 25 MHz

50 MHz

PLL

XT1

HCLK

MCO1/MCO2

XTAL

PLL

OSC

25 MHz

PHY_CLK 25 MHz

MS19970V1

1. f_HCLKmust be greater than 25 MHz.

2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block.

176/186

DocID022063 Rev 4

STM32F415xx, STM32F417xx

Revision history

8

Revision history

Table 98. Document revision history

Changes

Date

Revision

15-Sep-2011

1

Initial release.

Added WLCSP90 package on cover page.

Renamed USART4 and USART5 into UART4 and UART5,

respectively.

Updated number of USB OTG HS and FS in Table 2: STM32F415xx

and STM32F417xx: features and peripheral counts.

Updated Figure 3: Compatible board design between

STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package and

Figure 4: Compatible board design between STM32F2xx and

STM32F4xx for LQFP176 and BGA176 packages, and removed note

1 and 2.

Updated Section 2.2.9: Flexible static memory controller (FSMC).

Modified I/Os used to reprogram the Flash memory for CAN2 and

USB OTG FS in Section 2.2.13: Boot modes.

Updated note in Section 2.2.14: Power supply schemes.

PDR_ON no more available on LQFP100 package. Updated

Section 2.2.16: Voltage regulator. Updated condition to obtain a

minimum supply voltage of 1.7 V in the whole document.

Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for

UART4 and UART5 in Table 5: USART feature comparison.

Removed support of I2C for OTG PHY in Section 2.2.30: Universal

serial bus on-the-go full-speed (OTG_FS).

24-Jan-2012

2

Added Table 6: Legend/abbreviations used in the pinout table.

Table 7: STM32F41x pin and ball definitions: replaced V_SS_3, V_SS_4,

and V_SS_8 by V_SS; reformatted Table 7: STM32F41x pin and ball

definitions to better highlight I/O structure, and alternate functions

versus additional functions; signal corresponding to LQFP100 pin 99

changed from PDR_ON to V_SS; EVENTOUT added in the list of

alternate functions for all I/Os; ADC3_IN8 added as alternate function

for PF10; FSMC_CLE and FSMC_ALE added as alternate functions

for PD11 and PD12, respectively; PH10 alternate function

TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O

structure to TTa.

Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 7:

STM32F41x pin and ball definitions and Table 9: Alternate function

mapping.

Changed TCM data RAM to CCM data RAM in Figure 18: STM32F41x

memory map.

Added I_VDDand I_VSSmaximum values in Table 12: Current

characteristics.

Added Note 1 related to f_HCLK, updated Note 2 in Table 14: General

operating conditions, and added maximum power dissipation values.

Updated Table 15: Limitations depending on the operating power

supply range.

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Revision history

STM32F415xx, STM32F417xx

Table 98. Document revision history (continued)

Date

Revision

Changes

Added V in Table 19: Embedded reset and power control block

12

characteristics.

Updated Table 21: Typical and maximum current consumption in Run

mode, code with data processing running from Flash memory (ART

accelerator disabled) and Table 20: Typical and maximum current

consumption in Run mode, code with data processing running from

Flash memory (ART accelerator enabled) or RAM. Added Figure ,

Figure 25, Figure 26, and Figure 27.

Updated Table 22: Typical and maximum current consumption in Sleep

mode and removed Note 1.

Updated Table 23: Typical and maximum current consumptions in Stop

mode and Table 24: Typical and maximum current consumptions in

Standby mode, Table 25: Typical and maximum current consumptions

in VBAT mode, and Table 26: Switching output I/O current

consumption.

Section : On-chip peripheral current consumption: modified conditions,

and updated Table 27: Peripheral current consumption and Note 2.

Changed f_{HSE_ext}to 50 MHz and t_{r(HSE) f(HSE)}maximum value in

/t

Table 29: High-speed external user clock characteristics.

2

Added C_in(LSE)in Table 30: Low-speed external user clock

characteristics.

24-Jan-2012

(continued)

Updated maximum PLL input clock frequency, removed related note,

and deleted jitter for MCO for RMII Ethernet typical value in Table 35:

Main PLL characteristics. Updated maximum PLLI2S input clock

frequency and removed related note in Table 36: PLLI2S (audio PLL)

characteristics.

Updated Section : Flash memory to specify that the devices are

shipped to customers with the Flash memory erased. Updated

Table 38: Flash memory characteristics, and added t_MEin Table 39:

Flash memory programming.

Updated Table 42: EMS characteristics, and Table 43: EMI

characteristics.

Updated Table 56: I2S dynamic characteristics

Updated Figure 46: ULPI timing diagram and Table 62: ULPI timing.

Added t_COUNTERand t_{MAX_COUNT}in Table 51: Characteristics of TIMx

connected to the APB1 domain and Table 52: Characteristics of TIMx

connected to the APB2 domain. Updated Table 65: Dynamic

characteristics: Ethernet MAC signals for RMII.

Removed USB-IF certification in Section : USB OTG FS

characteristics.

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Revision history

Table 98. Document revision history (continued)

Revision Changes

Date

Updated Table 61: USB HS clock timing parameters

Updated Table 67: ADC characteristics.

Updated Table 68: ADC accuracy at fADC = 30 MHz.

Updated Note 1 in Table 74: DAC characteristics.

Section 5.3.25: FSMC characteristics: updated Table 75 toTable 86,

changed C_Lvalue to 30 pF, and modified FSMC configuration for

asynchronous timings and waveforms. Updated Figure 60:

Synchronous multiplexed PSRAM write timings.

Updated Table 96: Package thermal characteristics.

Appendix A.1: USB OTG full speed (FS) interface solutions: modified

Figure 86: USB controller configured as peripheral-only and used in

Full speed mode added Note 2, updated Figure 87: USB controller

configured as host-only and used in full speed mode and added

Note 2, changed Figure 88: USB controller configured in dual mode

and used in full speed mode and added Note 3.

2

24-Jan-2012

(continued)

Appendix A.2: USB OTG high speed (HS) interface solutions: removed

figures USB OTG HS device-only connection in FS mode and USB

OTG HS host-only connection in FS mode, and updated Figure 89:

USB controller configured as peripheral, host, or dual-mode and used

in high speed mode and added Note 2.

Added Appendix A.3: Ethernet interface solutions.

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Revision history

STM32F415xx, STM32F417xx

Table 98. Document revision history (continued)

Date

Revision

Changes

Updated Figure 5: STM32F41x block diagram and Figure 7: Power

supply supervisor interconnection with internal reset OFF

Added SDIO, added notes related to FSMC and SPI/I2S in Table 2:

STM32F415xx and STM32F417xx: features and peripheral counts.

Starting from Silicon revision Z, USB OTG full-speed interface is now

available for all STM32F415xx devices.

Added full information on WLCSP90 package together with

corresponding part numbers.

Changed number of AHB buses to 3.

Modified available Flash memory sizes in Section 2.2.4: Embedded

Flash memory.

Modified number of maskable interrupt channels in Section 2.2.10:

Nested vectored interrupt controller (NVIC).

Updated case of Regulator ON/internal reset ON, Regulator

ON/internal reset OFF, and Regulator OFF/internal reset ON in

Section 2.2.16: Voltage regulator.

Updated standby mode description in Section 2.2.19: Low-power

modes.

Added Note 1 below Figure 16: STM32F41x UFBGA176 ballout.

Added Note 1 below Figure 17: STM32F41x WLCSP90 ballout.

Updated Table 7: STM32F41x pin and ball definitions.

Added Table 8: FSMC pin definition.

31-May-2012

3

Removed OTG_HS_INTN alternate function in Table 7: STM32F41x

pin and ball definitions and Table 9: Alternate function mapping.

Removed I2S2_WS on PB6/AF5 in Table 9: Alternate function

mapping.

Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and

modified I2S3ext_SD on PC11 in Table 9: Alternate function mapping.

Added Table 10: STM32F41x register boundary addresses.

Updated Figure 18: STM32F41x memory map.

Updated V_DDAand V_REF+decoupling capacitor in Figure 21: Power

supply scheme.

Added power dissipation maximum value for WLCSP90 in Table 14:

General operating conditions.

Updated V_POR/PDRin Table 19: Embedded reset and power control

block characteristics.

Updated notes in Table 21: Typical and maximum current consumption

in Run mode, code with data processing running from Flash memory

(ART accelerator disabled), Table 20: Typical and maximum current

consumption in Run mode, code with data processing running from

Flash memory (ART accelerator enabled) or RAM, and Table 22:

Typical and maximum current consumption in Sleep mode.

Updated maximum current consumption at T_A= 25 °n Table 23:

Typical and maximum current consumptions in Stop mode.

180/186

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Revision history

Table 98. Document revision history (continued)

Revision Changes

Date

Removed f_{HSE_ext}typical value in Table 29: High-speed external user

clock characteristics. Updated Table 31: HSE 4-26 MHz oscillator

characteristics and Table 32: LSE oscillator characteristics (fLSE =

32.768 kHz).

Added f_{PLL48_OUT}maximum value in Table 35: Main PLL

characteristics.

Modified equation 1 and 2 in Section 5.3.11: PLL spread spectrum

clock generation (SSCG) characteristics.

Updated Table 38: Flash memory characteristics, Table 39: Flash

memory programming, and Table 40: Flash memory programming with

VPP.

Updated Section : Output driving current.

Table 53: I2C characteristics: Note 4 updated and applied to t_h(SDA)in

Fast mode, and removed note 4 related to t_h(SDA)minimum value.

3

31-May-2012

(continued)

Updated Table 67: ADC characteristics. Updated note concerning ADC

accuracy vs. negative injection current below Table 68: ADC accuracy

at fADC = 30 MHz.

Added WLCSP90 thermal resistance in Table 96: Package thermal

characteristics.

Updated Table 90: WLCSP90 - 0.400 mm pitch wafer level chip size

package mechanical data.

Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array

10 × 10 × 0.6 mm, package outline and Table 94: UFBGA176+25 -

ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data.

Added Figure 85: LQFP176 recommended footprint.

Removed 256 and 768 Kbyte Flash memory density from Table 97:

Ordering information scheme.

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Revision history

STM32F415xx, STM32F417xx

Table 98. Document revision history (continued)

Date

Revision

Changes

Modified Note 1 below Table 2: STM32F415xx and STM32F417xx:

features and peripheral counts.

Updated Figure 4 title.

Updated Note 3 below Figure 21: Power supply scheme.

Changed simplex mode into half-duplex mode in Section 2.2.25: Inter-

integrated sound (I2S).

Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and

DAC_OUT2, respectively.

Updated pin 36 signal in Figure 15: STM32F41x LQFP176 pinout.

Changed pin number from F8 to D4 for PA13 pin in Table 7:

STM32F41x pin and ball definitions.

Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5

pins in Table 9: Alternate function mapping.

Changed system memory into System memory + OTP in Figure 18:

STM32F41x memory map.

Added Note 1 below Table 16: VCAP_1/VCAP_2 operating conditions.

Updated I_DDAdescription in Table 74: DAC characteristics.

Removed PA9/PB13 connection to VBUS in Figure 86: USB controller

configured as peripheral-only and used in Full speed mode and

Figure 87: USB controller configured as host-only and used in full

speed mode.

Updated SPI throughput on front page and Section 2.2.24: Serial

peripheral interface (SPI)

Updated operating voltages in Table 2: STM32F415xx and

STM32F417xx: features and peripheral counts

04-Jun-2013

4

Updated note in Section 2.2.14: Power supply schemes

Updated Section 2.2.15: Power supply supervisor

Updated “Regulator ON” paragraph in Section 2.2.16: Voltage

regulator

Removed note in Section 2.2.19: Low-power modes

Corrected wrong reference manual in Section 2.2.28: Ethernet MAC

interface with dedicated DMA and IEEE 1588 support

Updated Table 15: Limitations depending on the operating power

supply range

Updated Table 24: Typical and maximum current consumptions in

Standby mode

Updated Table 25: Typical and maximum current consumptions in

VBAT mode

Updated Table 36: PLLI2S (audio PLL) characteristics

Updated Table 43: EMI characteristics

Updated Table 48: Output voltage characteristics

Updated Table 50: NRST pin characteristics

Updated Table 55: SPI dynamic characteristics

Updated Table 56: I2S dynamic characteristics

Deleted Table 59

Updated Table 62: ULPI timing

Updated Figure 47: Ethernet SMI timing diagram

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Revision history

Table 98. Document revision history (continued)

Revision Changes

Date

Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array

10 × 10 × 0.6 mm, package outline

Updated Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array

10 × 10 × 0.6 mm mechanical data

Updated Figure 5: STM32F41x block diagram

Updated Section 2: Description

Updated footnote ⁽³⁾in Table 2: STM32F415xx and STM32F417xx:

features and peripheral counts

Updated Figure 3: Compatible board design between

STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package

Updated Figure 4: Compatible board design between STM32F2xx and

STM32F4xx for LQFP176 and BGA176 packages

Updated Section 2.2.14: Power supply schemes

Updated Section 2.2.15: Power supply supervisor

Updated Section 2.2.16: Voltage regulator, including figures.

Updated Table 14: General operating conditions, including footnote ⁽²⁾

.

Updated Table 15: Limitations depending on the operating power

supply range, including footnote ⁽³⁾

.

Updated footnote ⁽¹⁾in Table 67: ADC characteristics.

Updated footnote ⁽³⁾in Table 68: ADC accuracy at fADC = 30 MHz.

Updated footnote ⁽¹⁾in Table 74: DAC characteristics.

Updated Figure 9: Regulator OFF.

Updated Figure 7: Power supply supervisor interconnection with

internal reset OFF.

4

04-Jun-2013

(continued)

Added Section 2.2.17: Regulator ON/OFF and internal reset ON/OFF

availability.

Updated footnote ⁽²⁾of Figure 21: Power supply scheme.

Replaced respectively “I2S3S_WS" by "I2S3_WS”, “I2S3S_CK” by

“I2S3_CK” and “FSMC_BLN1” by “FSMC_NBL1” in Table 9: Alternate

function mapping.

Added “EVENTOUT” as alternate function “AF15” for pin PC13, PC14,

PC15, PH0, PH1, PI8 in Table 9: Alternate function mapping

Replaced “DCMI_12” by “DCMI_D12” in Table 7: STM32F41x pin and

ball definitions.

Removed the following sentence from Section : I2C interface

characteristics: ”Unless otherwise specified, the parameters

given in Table 53 are derived from tests performed under the

ambient temperature, f

frequency and V supply voltage

PCLK1

DD

conditions summarized in Table 14.”.

In Table 7: STM32F41x pin and ball definitions on page 46:

– For pin PC13, replaced “RTC_AF1” by “RTC_OUT, RTC_TAMP1,

RTC_TS”

– for pin PI8, replaced “RTC_AF2” by “RTC_TAMP1, RTC_TAMP2,

RTC_TS”.

– for pin PB15, added RTC_REFIN in Alternate functions column.

In Table 9: Alternate function mapping on page 61, for port

PB15, replaced “RTC_50Hz” by “RTC_REFIN”.

DocID022063 Rev 4

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Revision history

STM32F415xx, STM32F417xx

Table 98. Document revision history (continued)

Date

Revision

Changes

Updated Figure 6: Multi-AHB matrix.

Updated Figure 7: Power supply supervisor interconnection with

internal reset OFF

Changed 1.2 V to V in Section : Regulator OFF

12

Updated LQFP176 pin 48.

Updated Section 1: Introduction.

Updated Section 2: Description.

Updated operating voltage in Table 2: STM32F415xx and

STM32F417xx: features and peripheral counts.

Updated Note 1.

Updated Section 2.2.15: Power supply supervisor.

Updated Section 2.2.16: Voltage regulator.

Updated Figure 9: Regulator OFF.

Updated Table 3: Regulator ON/OFF and internal reset ON/OFF

availability.

Updated Section 2.2.19: Low-power modes.

Updated Section 2.2.20: VBAT operation.

Updated Section 2.2.22: Inter-integrated circuit interface (I²C) .

Updated pin 48 in Figure 15: STM32F41x LQFP176 pinout.

Updated Table 6: Legend/abbreviations used in the pinout table.

Updated Table 7: STM32F41x pin and ball definitions.

Updated Table 14: General operating conditions.

4

Updated Table 15: Limitations depending on the operating power

supply range.

04-Jun-2013

(continued)

Updated Section 5.3.7: Wakeup time from low-power mode.

Updated Table 33: HSI oscillator characteristics.

Updated Section 5.3.15: I/O current injection characteristics.

Updated Table 47: I/O static characteristics.

Updated Table 50: NRST pin characteristics.

Updated Table 53: I2C characteristics.

Updated Figure 39: I2C bus AC waveforms and measurement circuit.

Updated Section 5.3.19: Communications interfaces.

Updated Table 67: ADC characteristics.

Added Table 70: Temperature sensor calibration values.

Added Table 73: Internal reference voltage calibration values.

Updated Section 5.3.25: FSMC characteristics.

Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO)

characteristics.

Updated Table 23: Typical and maximum current consumptions in Stop

mode.

Updated Section : SPI interface characteristics included Table 55.

Updated Section : I2S interface characteristics included Table 56.

Updated Table 64: Dynamic characteristics: Ehternet MAC signals for

SMI.

Updated Table 66: Dynamic characteristics: Ethernet MAC signals for

MII.

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Revision history

Table 98. Document revision history (continued)

Revision Changes

Date

Updated Table 64: Dynamic characteristics: Ehternet MAC signals for

SMI.

Updated Table 66: Dynamic characteristics: Ethernet MAC signals for

MII.

Updated Table 79: Synchronous multiplexed NOR/PSRAM read

timings.

Updated Table 80: Synchronous multiplexed PSRAM write timings.

Updated Table 81: Synchronous non-multiplexed NOR/PSRAM read

timings.

4

04-Jun-2013

(continued)

Updated Table 82: Synchronous non-multiplexed PSRAM write

timings.

Updated Section 5.3.26: Camera interface (DCMI) timing specifications

including Table 87: DCMI characteristics and addition of Figure 73:

DCMI timing diagram.

Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO)

characteristics including Table 88.

Updated Chapter Figure 9.

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STM32F415xx, STM32F417xx

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型号：	STM32F417VE
厂家：	ST
描述：	ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM ARM的Cortex- M4 32B MCUFPU ， 210DMIPS ，高达1MB闪存/ 1924KB内存闪存
文件：	总186页 (文件大小：5450K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM32F417VE [STMICROELECTRONICS]

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