STM32G071RB [STMICROELECTRONICS]
Arm Cortex-M0 32-bit MCU, up to 128 KB Flash, 36 KB RAM;
| 型号： | STM32G071RB |
| 厂家： | 
ST |
| 描述： | Arm Cortex-M0 32-bit MCU, up to 128 KB Flash, 36 KB RAM |
| 文件： | 总133页 (文件大小：2185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32G071x8/xB
Arm® Cortex®-M0+ 32-bit MCU, up to 128 KB Flash, 36 KB RAM,
4x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V
Datasheet - production data
Features
®
®
• Core: Arm 32-bit Cortex -M0+ CPU,
frequency up to 64 MHz
LQFP32
7 mm
LQFP48
7 mm
LQFP64
10 10 mm
UFQFPN28
4 × 4 mm
UFQFPN32
5 × 5 mm
UFQFPN48
7 × 7 mm
• -40°C to 85°C/105°C/125°C operating
WLCSP25
2.3 × 2.5 mm
UFBGA64
5 mm
7
×
5
×
temperature
7
×
• Memories
×
– Up to 128 Kbytes of Flash memory with
protection and securable area
• Communication interfaces
– 36 Kbytes of SRAM (32 Kbytes with HW
parity check)
2
– Two I C-bus interfaces supporting Fast-
mode Plus (1 Mbit/s) with extra current
sink, one supporting SMBus/PMBus and
wakeup from Stop mode
• CRC calculation unit
• Reset and power management
– Four USARTs with master/slave
synchronous SPI; two supporting ISO7816
interface, LIN, IrDA capability, auto baud
rate detection and wakeup feature
– One low-power UART
– Two SPIs (32 Mbit/s) with 4- to 16-bit
programmable bitframe, one multiplexed
– Voltage range: 1.7 V to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable Brownout reset (BOR)
– Programmable voltage detector (PVD)
– Low-power modes:
Sleep, Stop, Standby, Shutdown
– V
supply for RTC and backup registers
2
BAT
with I S interface
• Clock management
– HDMI CEC interface, wakeup on header
• USB Type-C™ Power Delivery controller
• Development support: serial wire debug (SWD)
• 96-bit unique ID
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator with calibration
– Internal 16 MHz RC with PLL option (±1 %)
– Internal 32 kHz RC oscillator (±5 %)
®
• All packages ECOPACK 2 compliant
• Up to 60 fast I/Os
– All mappable on external interrupt vectors
– Multiple 5 V-tolerant I/Os
Table 1. Device summary
Reference
Part number
• 7-channel DMA controller with flexible mapping
STM32G071C8, STM32G071G8,
STM32G071K8, STM32G071R8
• 12-bit, 0.4 µs ADC (up to 16 ext. channels)
– Up to 16-bit with hardware oversampling
– Conversion range: 0 to 3.6V
STM32G071x8
STM32G071RB, STM32G071CB,
STM32G071KB, STM32G071GB,
STM32G071EB
STM32G071xB
• Two 12-bit DACs, low-power sample-and-hold
• Two fast low-power analog comparators, with
programmable input and output, rail-to-rail
• 14 timers (two 128 MHz capable): 16-bit for
advanced motor control, one 32-bit and five 16-
bit general-purpose, two basic 16-bit, two low-
power 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup
from Stop/Standby/Shutdown
March 2020
DS12232 Rev 3
1/133
This is information on a product in full production.
www.st.com
Contents
STM32G071x8/xB
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
3.2
3.3
Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1
Securable area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
3.5
3.6
3.7
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 16
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8
3.9
Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 24
3.13.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 24
3.14 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REFINT
3.14.3
V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
BAT
3.15 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.16 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Contents
3.17 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 29
3.18.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.4 Low-power timers (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 30
3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Universal synchronous/asynchronous receiver transmitter (USART) . . . 32
3.22 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 33
3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24 USB Type-C™ Power Delivery controller . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.25 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.25.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4
5
Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 36
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 56
Embedded reset and power control block characteristics . . . . . . . . . . . 56
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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5
Contents
STM32G071x8/xB
5.3.6
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.7
5.3.8
5.3.9
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.18 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.22
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
BAT
5.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.3.24 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . . 99
5.3.25 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.9.1
6.9.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 129
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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Contents
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
DS12232 Rev 3
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5
List of tables
STM32G071x8/xB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32G071x8/xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 12
Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 15
Interconnect of STM32G071x8/xB peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2
I C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Terms and symbols used in Table 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port A alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Port B alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56
Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Current consumption in Run and Low-power run modes
at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typical current consumption in Run and Low-power run modes,
Table 26.
depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 61
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LSE
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6/133
DS12232 Rev 3
STM32G071x8/xB
List of tables
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Maximum ADC R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
AIN
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
BAT
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Minimum I2CCLK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2
I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UCPD operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Recommended PCB design rules for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . 111
LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
WLCSP25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Recommended PCB pad design rules for WLCSP25 package . . . . . . . . . . . . . . . . . . . . 127
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
DS12232 Rev 3
7/133
7
List of figures
STM32G071x8/xB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM32G071RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM32G071RxI UFBGA64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STM32G071CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STM32G071CxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STM32G071KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STM32G071KxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STM32G071GxU UFQFPN28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 10. STM32G071Ex WLCSP25 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 15.
V
vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
REFINT
Figure 16. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 17. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 20. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 21. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
(1)
Figure 22. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 24. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 26. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 27. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 28. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 29. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2
Figure 30. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2
Figure 31. I S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 32. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 33. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 34. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 35. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 36. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 37. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 38. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 39. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 40. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 41. UFQFPN48 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 42. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 43. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 44. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 45. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 46. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 47. UFQFPN32 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 48. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8/133
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List of figures
Figure 49. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 50. UFQFPN28 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 51. Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 52. UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 53. WLCSP25 chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 54. Recommended PCB pad design for WLCSP25 package. . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 55. WLCSP25 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
DS12232 Rev 3
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9
Introduction
STM32G071x8/xB
1
Introduction
This document provides information on STM32G071x8/xB microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering codes.
Information on memory mapping and control registers is object of reference manual.
®(a)
®
Information on Arm
Cortex -M0+ core is available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
10/133
DS12232 Rev 3
STM32G071x8/xB
Description
2
Description
The STM32G071x8/xB mainstream microcontrollers are based on high-performance
®
®
Arm Cortex -M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high
level of integration, they are suitable for a wide range of applications in consumer, industrial
and appliance domains and ready for the Internet of Things (IoT) solutions.
The devices incorporate a memory protection unit (MPU), high-speed embedded memories
(up to 128 Kbytes of Flash program memory with read protection, write protection,
proprietary code protection, and securable area, and 36 Kbytes of SRAM), DMA and an
extensive range of system functions, enhanced I/Os and peripherals. The devices offer
2
2
standard communication interfaces (two I Cs, two SPIs / one I S, one HDMI CEC, and four
USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two
channels, two fast comparators, an internal voltage reference buffer, a low-power RTC, an
advanced control PWM timer running at up to double the CPU frequency, five general-
purpose 16-bit timers with one running at up to double the CPU frequency, a 32-bit general-
purpose timer, two basic timers, two low-power 16-bit timers, two watchdog timers, and a
SysTick timer. The STM32G071x8/xB devices provide a fully integrated USB Type-C Power
Delivery controller.
The devices operate within ambient temperatures from -40 to 125°C. They can operate with
supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a
comprehensive set of power-saving modes, low-power timers and low-power UART, allows
the design of low-power applications.
VBAT direct battery input allows keeping RTC and backup registers powered.
The devices come in packages with 28 to 64 pins.
DS12232 Rev 3
11/133
35
Description
STM32G071x8/xB
Table 2. STM32G071x8/xB family device features and peripheral counts
STM32G071_
Peripheral
_G8 _GB
xxN xxN
_K8 _KB
xxN xxN
_EB _G8 _GB
_K8 _KB
64 128
_C8 _CB _R8 _RB
64 128 64 128
Flash memory (Kbyte)
SRAM (Kbyte)
Advanced control
General-purpose
Basic
128
64
128
64
128
64 128
32 (with parity) or 36 (without parity)
1 (16-bit) high frequency
4 (16-bit) + 1 (16-bit) high frequency + 1 (32-bit)
2 (16-bit)
Low-power
SysTick
2 (16-bit)
1
2
Watchdog
SPI [I2S](1)
I2C
2 [1]
2
USART
4
LPUART
1
(2)
(2)
UCPD
2
2
CEC
1
Yes
2
RTC
Tamper pins
Random number
generator
No
No
AES
GPIOs
23
26
30
44
4
60
5
Wakeup pins
4
3
4
3
10 ext.
+ 2 int.
9 ext.
+ 2 int.
11 ext.
+ 2 int.
10 ext.
+ 2 int.
14 ext.
+ 3 int.
16 ext.
+ 3 int.
12-bit ADC channels
12-bit DAC channels
2
Internal voltage reference
buffer
No
Yes
Analog comparators
Max. CPU frequency
Operating voltage
2
64 MHz
1.7 to 3.6 V
Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Junction: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C
Operating temperature(3)
Number of pins
25
28
32
48
64
1. The numbers in brackets denote the count of SPI interfaces configurable as I2S interface.
2. One port with only one CC line available (supporting limited number of use cases).
3. Depends on order code. Refer to Section 7: Ordering information for details.
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STM32G071x8/xB
Description
Figure 1. Block diagram
POWER
DMAMUX
SWCLK
SWDIO
SWD
Voltage
regulator
VCORE
DMA
VDDIO1
VDDA
VDD
VDD/VDDA
VSS/VSSA
CPU
Flash memory
CORTEX-M0+
fmax = 64 MHz
I/F
SUPPLY
SUPERVISION
up to 128 KB
POR
Reset
Int
POR/BOR
T sensor
PVD
SRAM
36 KB
NRST
Parity
NVIC
IOPORT
HSI16
RC 16 MHz
PLL
PLLPCLK
PLLQCLK
PLLRCLK
LSI
GPIOs
Port A
PAx
XTAL OSC
4-48 MHz
RC 32 kHz
OSC_IN
OSC_OUT
PBx
Port B
Port C
Port D
Port F
HSE
IWDG
CRC
PCx
PDx
I/F
VDD
VBAT
LSE
RCC
Reset & clock control
Low-voltage
detector
PFx
LSE
OSC32_IN
OSC32_OUT
XTAL32 kHz
System and
peripheral
clocks
RTC, TAMP
Backup regs
RTC_OUT
RTC_REFIN
RTC_TS
EXTI
I/F
from peripherals
TAMP_IN
AHB-to-APB
VREF+
VREFBUF
4 channels
TIM1
TIM2 (32-bit)
TIM3
BKIN, BKIN2, ETR
COMP1
COMP2
IN+, IN-,
OUT
4 channels
ETR
SYSCFG
4 channels
ETR
DAC_OUT1
DAC_OUT2
DAC
ADC
I/F
I/F
TIM14
1 channel
TIM6
TIM7
2 channels
BKIN
TIM15
16x IN
1 channel
BKIN
TIM16 & 17
MOSI/SD
MISO/MCK
SCK/CK
PWRCTRL
WWDG
ETR, IN, OUT
LPTIM1 & 2
SPI1/I2S
NSS/WS
IR_OUT
IRTIM
MOSI, MISO
SCK, NSS
SPI2
DBGMCU
RX, TX
USART1 & 2
CTS, RTS, CK
CC, DBCC
FRSTX
UCPD1 & 2
RX, TX
USART3 & 4
CTS, RTS, CK
HDMI-CEC
CEC
RX, TX,
LPUART
CTS, RTS
SCL, SDA
I2C1
I2C2
SMBA, SMBUS
SCL, SDA
Power domain of analog blocks :
VBAT
VDD
VDDA
VDDIO1
MSv42182V2
DS12232 Rev 3
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35
Functional overview
STM32G071x8/xB
3
Functional overview
3.1
Arm® Cortex®-M0+ core with MPU
The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of
embedded applications. It offers significant benefits to developers, including:
•
•
•
•
•
•
a simple architecture, easy to learn and program
ultra-low power, energy-efficient operation
excellent code density
deterministic, high-performance interrupt handling
upward compatibility with Cortex-M processor family
platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a
2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy
efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern
32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to embedded Arm core, the STM32G071x8/xB devices are compatible with Arm tools
and software.
The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)
described in Section 3.13.1.
3.2
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3
Embedded Flash memory
STM32G071x8/xB devices feature up to 128 Kbytes of embedded Flash memory available
for storing code and data.
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Functional overview
Flexible protections can be configured thanks to option bytes:
•
Readout protection (RDP) to protect the whole memory. Three levels are available:
–
–
Level 0: no readout protection
Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
–
Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in
RAM and bootloader selection are disabled. This selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
Debug, boot from RAM or boot
User execution
Protection
level
from system memory (loader)
Area
Read
Write
Erase
Read
Write
Erase
1
2
1
2
1
2
1
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
N/A
Yes
N/A
Yes
N/A
No
No
N/A
No
No
N/A
No
User
memory
System
memory
No
No
N/A
Yes
N/A
No
N/A
Yes
N/A
N/A(1)
N/A
Yes
No
Yes
No
N/A(1)
Option
bytes
Yes
Yes
Backup
registers
N/A
N/A
N/A
1. Erased upon RDP change from Level 1 to Level 0.
•
•
Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU as instruction code, while all other accesses
(DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional
option bit (PCROP_RDP) determines whether the PCROP area is erased or not when
the RDP protection is changed from Level 1 to Level 0.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•
•
•
single error detection and correction
double error detection
readout of the ECC fail address from the ECC register
3.3.1
Securable area
A part of the Flash memory can be hidden from the application once the code it contains is
executed. As soon as the write-once SEC_PROT bit is set, the securable memory cannot be
accessed until the system resets. The securable area generally contains the secure boot
code to execute only once at boot. This helps to isolate secret code from untrusted
application code.
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Functional overview
STM32G071x8/xB
3.4
Embedded SRAM
STM32G071x8/xB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity
check allows memory data errors to be detected, which contributes to increasing functional
safety of applications.
When the parity protection is not required because the application is not safety-critical, the
parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.
The memory can be read/write-accessed at CPU clock speed, with 0 wait states.
3.5
Boot modes
At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
•
•
•
boot from User Flash memory
boot from System memory
boot from embedded SRAM
The boot pin is shared with a standard GPIO and can be enabled through the boot selector
option bit. The boot loader is located in System memory. It manages the Flash memory
2
reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I C-
bus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or
PB12/PB13/PB14/PB15.
3.6
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
3.7
Power supply management
3.7.1
Power supply schemes
The STM32G071x8/xB devices require a 1.7 V to 3.6 V operating supply voltage (V ).
DD
Several different power supplies are provided to specific peripherals:
•
V
= 1.7 (1.6) to 3.6 V
DD
V
is the external power supply for the internal regulator and the system analog such
DD
as reset, power management and internal clocks. It is provided externally through
VDD/VDDA pin.
The minimum voltage of 1.7 V corresponds to power-on reset release threshold
V
(max). Once this threshold is crossed and power-on reset is released, the
POR
functionality is guaranteed down to power-down reset threshold V
(min).
PDR
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Functional overview
•
V
V
= 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V
DDA
DDA
is the analog power supply for the A/D converter, D/A converter, voltage
voltage level is identical to V voltage as it is
reference buffer and comparators. V
DDA
DD
provided externally through VDD/VDDA pin.
•
•
V
V
= V
DD
DDIO1
is the power supply for the I/Os. V
voltage level is identical to V voltage
DD
DDIO1
DDIO1
as it is provided externally through VDD/VDDA pin.
V
= 1.55 V to 3.6 V. V is the power supply (through a power switch) for RTC,
BAT
BAT
TAMP, low-speed external 32.768 kHz oscillator and backup registers when V is not
DD
present. V
is provided externally through VBAT pin. When this pin is not available
BAT
on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.
V is the analog peripheral input reference voltage, or the output of the internal
REF+
•
voltage reference buffer (when enabled). When V
< 2 V, V
must be equal to
DDA
REF+
V
. When V
≥ 2 V, V
must be between 2 V and V
. It can be grounded
DDA
DDA
REF+
DDA
when the analog peripherals using V
are not active.
REF+
The internal voltage reference buffer supports two output voltages, which is configured
with VRS bit of the VREFBUF_CSR register:
–
–
V
V
V
around 2.048 V (requiring V
equal to or higher than 2.4 V)
DDA
REF+
REF+
around 2.5 V (requiring V
equal to or higher than 2.8 V)
DDA
is delivered through VREF+ pin. On packages without VREF+ pin, V
is
REF+
REF+
internally connected with V , and the internal voltage reference buffer must be kept
DD
disabled (refer to datasheets for package pinout description).
•
V
CORE
An embedded linear voltage regulator is used to supply the V
internal digital
CORE
power. V
is the power supply for digital peripherals, SRAM and Flash memory.
CORE
The Flash memory is also supplied with V
.
DD
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Functional overview
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Figure 2. Power supply overview
VDDA domain
VREF+
VREF+
A/D converter
VDDA
VSSA
Comparators
D/A converter
Voltage reference buffer
VDDIO1 domain
I/O ring
VDDIO1
VDD domain
Reset block
Temp. sensor
PLL, HSI
VCORE domain
Core
Standby circuitry
VSS
VDD
(Wakeup, IWDG)
SRAM
VSS/VSSA
VDD/VDDA
Digital
peripherals
VCORE
Voltage
regulator
Low-voltage
detector
Flash memory
RTC domain
BKP registers
VBAT
LSE crystal 32.768 kHz osc
RCC BDCR register
RTC and TAMP
MSv39736V3
3.7.2
Power supply supervisor
The device has an integrated power-on/power-down (POR/PDR) reset active in all power
modes except Shutdown and ensuring proper operation upon power-on and power-down. It
maintains the device in reset when the supply voltage is below V
threshold, without
POR/PDR
the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It
can be enabled and configured through option bytes, by selecting one of four thresholds for
rising V and other four for falling V
.
DD
DD
The device also features an embedded programmable voltage detector (PVD) that monitors
the V power supply and compares it to V threshold. It allows generating an interrupt
DD
PVD
when V level crosses the V
threshold, selectively while falling, while rising, or while
DD
PVD
falling and rising. The interrupt service routine can then generate a warning message and/or
put the MCU into a safe state. The PVD is enabled by software.
3.7.3
Voltage regulator
Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device.
The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power
sleep and Stop modes.
In Standby and Shutdown modes, both regulators are powered down and their outputs set in
high-impedance state, such as to bring their current consumption close to zero. However,
SRAM data retention is possible in Standby mode, in which case the LPR remains active
and it only supplies the SRAM.
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Functional overview
3.7.4
Low-power modes
By default, the microcontroller is in Run mode after system or power reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Low-power run mode
This mode is achieved with V
supplied by the low-power regulator to minimize the
CORE
regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
•
•
Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Low-
power run mode.
Stop 0 and Stop 1 modes
In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the V
domain are stopped.
CORE
The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,
so as to get clock for processing the wakeup event. The main regulator remains active
in Stop 0 mode while it is turned off in Stop 1 mode.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption, with POR/PDR
always active in this mode. The main regulator is switched off to power down V
CORE
domain. The low-power regulator is either switched off or kept active. In the latter case,
it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC
oscillator and the HSE crystal oscillator are also powered down. The RTC can remain
active (Standby mode with RTC, Standby mode without RTC).
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode.
Upon entering Standby mode, register contents are lost except for registers in the RTC
domain and standby circuitry. The SRAM contents can be retained through register
setting.
The device exits Standby mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE
(CSS on LSE).
•
Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off to power down the V
domain. The PLL, as well as the
CORE
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Functional overview
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HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The
RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode. Therefore, switching to RTC domain is not supported.
SRAM and register contents are lost except for registers in the RTC domain.
The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper).
3.7.5
3.7.6
Reset mode
During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce
power consumption. In addition, when the reset source is internal, the built-in pull-up
resistor on NRST pin is deactivated.
VBAT operation
The V
power domain, consuming very little energy, includes RTC, and LSE oscillator and
BAT
backup registers.
In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for
example, an external battery or an external supercapacitor. Two anti-tamper detection pins
are available.
The RTC domain can also be supplied from VDD/VDDA pin.
By means of a built-in switch, an internal voltage supervisor allows automatic switching of
RTC domain powering between V and voltage from VBAT pin to ensure that the supply
DD
voltage of the RTC domain (V
) remains within valid operating conditions. If both voltages
BAT
are valid, the RTC domain is supplied from VDD/VDDA pin.
An internal circuit for charging the battery on VBAT pin can be activated if the V voltage is
DD
within a valid range.
Note:
External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT
mode, as in that mode the V is not within a valid range.
DD
3.8
Interconnect of peripherals
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
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Functional overview
Table 4. Interconnect of STM32G071x8/xB peripherals
Interconnect
Interconnect source
Interconnect action
destination
TIMx
Timer synchronization or chaining
Conversion triggers
Y
Y
Y
Y
-
-
ADCx
DACx
TIMx
DMA
Memory-to-memory transfer trigger
Comparator output blanking
Y
Y
Y
Y
-
-
COMPx
Timer input channel, trigger, break
from analog signals comparison
TIM1,2,3
Y
Y
Y
Y
-
COMPx
Low-power timer triggered by analog
signals comparison
LPTIMERx
Y
ADCx
RTC
TIM1
Timer triggered by analog watchdog
Timer input channel from RTC events
Y
Y
Y
Y
-
-
TIM16
Low-power timer triggered by RTC
alarms or tampers
LPTIMERx
Y
Y
Y
Y
Y
-
All clocks sources (internal
and external)
Clock source used as input channel for
RC measurement and trimming
TIM14,16,17
CSS
RAM (parity error)
Flash memory (ECC error)
COMPx
TIM1,15,16,17
Timer break
Y
Y
-
PVD
CPU (hard fault)
TIM1,15,16,17
TIMx
Timer break
Y
Y
Y
-
-
-
External trigger
External trigger
Y
Y
LPTIMERx
Y
GPIO
ADC
Conversion external trigger
Y
Y
-
DACx
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Functional overview
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3.9
Clocks and startup
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•
•
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock source: three different sources can deliver SYSCLK system clock:
–
4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It
can supply clock to system PLL. The HSE can also be configured in bypass mode
for an external clock.
–
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or
HSI16 clocks.
•
Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
–
32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
–
32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
•
•
Peripheral clock sources: several peripherals (I2S, USARTs, I2Cs, LPTIMs, ADC)
have their own clock independent of the system clock.
Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt. The CCS feature can be
enabled by software.
•
Clock output:
–
MCO (microcontroller clock output) provides one of the internal clocks for
external use by the application
–
LSCO (low speed clock output) provides LSI or LSE in all low-power modes
(except in VBAT operation).
Several prescalers allow the application to configure AHB and APB domain clock
frequencies, 64 MHz at maximum.
3.10
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of
the GPIO pins are shared with special digital or analog functions.
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Functional overview
Through a specific sequence, this special function configuration of I/Os can be locked, such
as to avoid spurious writing to I/O control registers.
3.11
Direct memory access controller (DMA)
The direct memory access (DMA) controller is a bus master and system peripheral with
single-AHB architecture.
With 7 channels, it performs data transfers between memory-mapped peripherals and/or
memories, to offload the CPU.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The unit includes an arbiter for handling the priority between DMA requests.
Main features of the DMA controller:
•
•
Single-AHB master
Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
•
•
Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
All DMA channels independently configurable:
–
–
–
Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
Priority between the requests is programmable by software (four levels per
channel: very high, high, medium, low) and by hardware in case of equality (such
as request to channel 1 has priority over request to channel 2).
Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
–
–
Support of transfers from/to peripherals to/from memory with circular buffer
management
16
Programmable number of data to be transferred: 0 to 2 - 1
•
Generation of an interrupt request per channel. Each interrupt request originates from
any of the three DMA events: transfer complete, half transfer, or transfer error.
3.12
3.13
DMA request multiplexer (DMAMUX)
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controller. Each channel selects a unique DMA request line,
unconditionally or synchronously with events from its DMAMUX synchronization inputs.
DMAMUX may also be used as a DMA request generator from programmable events on its
input trigger signals.
Interrupts and events
The device flexibly manages events causing interrupts of linear program execution, called
exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)
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Functional overview
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and an extended interrupt/event controller (EXTI) are the assets contributing to handling the
exceptions. Exceptions include core-internal events such as, for example, a division by zero
and, core-external events such as logical level changes on physical lines. Exceptions result
in interrupting the program flow, executing an interrupt service routine (ISR) then resuming
the original program flow.
The processor context (contents of program pointer and status registers) is stacked upon
program interrupt and unstacked upon program resume, by hardware. This avoids context
stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving
time, code and power. The ability to abandon and restart load-multiple and store-multiple
operations significantly increases the device’s responsiveness in processing exceptions.
3.13.1
Nested vectored interrupt controller (NVIC)
The configurable nested vectored interrupt controller is tightly coupled with the core. It
handles physical line events associated with a non-maskable interrupt (NMI) and maskable
interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.
The tight coupling of the processor core with NVIC significantly reduces the latency between
interrupt events and start of corresponding interrupt service routines (ISRs). The ISR
vectors are listed in a vector table, stored in the NVIC at a base address. The vector
address of an ISR to execute is hardware-built from the vector table base address and the
ISR order number used as offset.
If a higher-priority interrupt event happens while a lower-priority interrupt event occurring
just before is waiting for being served, the later-arriving higher-priority interrupt event is
served first. Another optimization is called tail-chaining. Upon a return from a higher-priority
ISR then start of a pending lower-priority ISR, the unnecessary processor context
unstacking and stacking is skipped. This reduces latency and contributes to power
efficiency.
Features of the NVIC:
•
•
•
•
•
•
•
•
Low-latency interrupt processing
4 priority levels
Handling of a non-maskable interrupt (NMI)
Handling of 32 maskable interrupt lines
Handling of 10 Cortex-M0+ exceptions
Later-arriving higher-priority interrupt processed first
Tail-chaining
Interrupt vector retrieval by hardware
3.13.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller adds flexibility in handling physical line events and
allows identifying wake-up events at processor wakeup from Stop mode.
The EXTI controller has a number of channels, of which some with rising, falling or rising,
and falling edge detector capability. Any GPIO and a few peripheral signals can be
connected to these channels.
The channels can be independently masked.
The EXTI controller can capture pulses shorter than the internal clock period.
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Functional overview
A register in the EXTI controller latches every event even in Stop mode, which allows the
software to identify the origin of the processor's wake-up from Stop mode or, to identify the
GPIO and the edge event having caused an interrupt.
3.14
Analog-to-digital converter (ADC)
A native 12-bit analog-to-digital converter is embedded into STM32G071x8/xB devices. It
can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16
external channels and 3 internal channels (temperature sensor, voltage reference, V
BAT
monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that
the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate in the whole V supply
DD
range.
The ADC features a hardware oversampler up to 256 samples, improving the resolution to
16 bits (refer to AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions with timers.
3.14.1
Temperature sensor
The temperature sensor (TS) generates a voltage V that varies linearly with temperature.
TS
The temperature sensor is internally connected to an ADC input to convert the sensor
output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor may
vary from part to part due to process variation, the uncalibrated internal temperature sensor
is suitable only for relative temperature measurements.
To improve the accuracy of the temperature sensor, each part is individually factory-
calibrated by ST. The resulting calibration data are stored in the part’s engineering bytes,
accessible in read-only mode.
Table 5. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
TS_CAL1
0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
TS_CAL2
0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
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Functional overview
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3.14.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC and comparators. V
is internally connected to an ADC input. The V
REFINT
REFINT
voltage is individually precisely measured for each part by ST during production test and
stored in the part’s engineering bytes. It is accessible in read-only mode.
Table 6. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
V
temperature of 30 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
0x1FFF 75AA - 0x1FFF 75AB
REFINT
3.14.3
V
battery voltage monitoring
BAT
This embedded hardware feature allows the application to measure the V
battery voltage
BAT
using an internal ADC input. As the V
voltage may be higher than V
and thus outside
BAT
DDA
the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a
consequence, the converted digital value is one third the V
voltage.
BAT
3.15
Digital-to-analog converter (DAC)
The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available
on the channel output. The architecture of either channel is based on integrated resistor
string and an inverting amplifier. The digital circuitry is common for both channels.
Features of the DAC:
•
•
•
•
•
•
•
•
•
•
•
•
Two DAC output channels
8-bit or 12-bit output mode
Buffer offset calibration (factory and user trimming)
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Independent or simultaneous conversion for DAC channels
DMA capability for either DAC channel
Triggering with timer events, synchronized with DMA
Triggering with external events
Sample-and-hold low-power mode, with internal or external capacitor
26/133
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STM32G071x8/xB
Functional overview
3.16
Voltage reference buffer (VREFBUF)
When enabled, an embedded buffer provides the internal reference voltage to analog
blocks (for example ADC) and to VREF+ pin for external components.
The internal voltage reference buffer supports two voltages:
•
•
2.048 V
2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is disabled.
On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to
common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.
3.17
Comparators (COMP)
Two embedded rail-to-rail analog comparators have programmable reference voltage
(internal or external), hysteresis, speed (low for low-power) and output polarity.
The reference voltage can be one of the following:
•
•
•
external, from an I/O
internal, from DAC
internal reference voltage (V
) or its submultiple (1/4, 1/2, 3/4)
REFINT
The comparators can wake up the device from Stop mode, generate interrupts, breaks or
triggers for the timers and can be also combined into a window comparator.
3.18
Timers and watchdogs
The device includes an advanced-control timer, six general-purpose timers, two basic
timers, two low-power timers, two watchdog timers and a SysTick timer. Table 7 compares
features of the advanced-control, general-purpose and basic timers.
Table 7. Timer feature comparison
Maximum
operating
frequency
DMA
request
generation channels
Capture/
compare mentary
Comple-
Counter
resolution
Counter
type
Prescaler
factor
Timer type
Timer
outputs
Advanced-
control
Up, down,
up/down
Integer from
1 to 216
TIM1
16-bit
128 MHz
Yes
4
3
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35
Functional overview
STM32G071x8/xB
Table 7. Timer feature comparison (continued)
Maximum
operating
frequency
DMA
request
generation channels
Capture/
compare mentary
Comple-
Counter
resolution
Counter
type
Prescaler
factor
Timer type
Timer
outputs
Up, down,
up/down
Integer from
1 to 216
TIM2
TIM3
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
64 MHz
64 MHz
64 MHz
128 MHz
64 MHz
64 MHz
64 MHz
Yes
Yes
No
4
4
-
Up, down,
up/down
Integer from
1 to 216
-
-
Integer from
1 to 216
TIM14
TIM15
Up
Up
Up
Up
Up
1
General-
purpose
Integer from
1 to 216
Yes
Yes
Yes
No
2
1
1
-
TIM16
TIM17
Integer from
1 to 216
1
TIM6
TIM7
Integer from
1 to 216
Basic
-
LPTIM1
LPTIM2
2n where
n=0 to 7
Low-power
N/A
-
3.18.1
Advanced-control timer (TIM1)
The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
•
•
•
•
input capture
output compare
PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
one-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled, so as to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.18.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
28/133
DS12232 Rev 3
STM32G071x8/xB
Functional overview
3.18.2
General-purpose timers (TIM2, 3, 14, 15, 16, 17)
There are six synchronizable general-purpose timers embedded in the device (refer to
Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs
or act as a simple timebase.
•
TIM2, TIM3
These are full-featured general-purpose timers:
–
–
TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler
TIM3 with 16-bit auto-reload up/downcounter and 16-bit prescaler
They have four independent channels for input capture/output compare, PWM or one-
pulse mode output. They can operate together or in combination with other general-
purpose timers via the Timer Link feature for synchronization or event chaining. They
can generate independent DMA request and support quadrature encoders. Their
counters can be frozen in debug mode.
•
•
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one
channel for input capture/output compare, PWM output or one-pulse mode output. Its
counter can be frozen in debug mode.
TIM15, TIM16, TIM17
These are general-purpose timers featuring:
–
–
–
16-bit auto-reload upcounter and 16-bit prescaler
2 channels and 1 complementary channel for TIM15
1 channel and 1 complementary channel for TIM16 and TIM17
All channels can be used for input capture/output compare, PWM or one-pulse mode
output. The timers can operate together via the Timer Link feature for synchronization
or event chaining. They can generate independent DMA request. Their counters can
be frozen in debug mode.
3.18.3
3.18.4
Basic timers (TIM6 and TIM7)
These timers are mainly used for triggering DAC conversions. They can also be used as
generic 16-bit timebases.
Low-power timers (LPTIM1 and LPTIM2)
These timers have an independent clock. When fed with LSE, LSI or external clock, they
keep running in Stop mode and they can wake up the system from it.
DS12232 Rev 3
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35
Functional overview
STM32G071x8/xB
Features of LPTIM1 and LPTIM2:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output (pulse, PWM)
Continuous/one-shot mode
Selectable software/hardware input trigger
Selectable clock source:
–
–
Internal: LSE, LSI, HSI16 or APB clocks
External: over LPTIM input (working even with no internal clock source running,
used by pulse counter application)
•
•
Programmable digital glitch filter
Encoder mode
3.18.5
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).
Independent of the main clock, it can operate in Stop and Standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management. It is hardware- or software-configurable through the
option bytes. Its counter can be frozen in debug mode.
3.18.6
3.18.7
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked by the
system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug
mode.
SysTick timer
This timer is dedicated to real-time operating systems, but it can also be used as a standard
down counter.
Features of SysTick timer:
•
•
•
•
24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
3.19
Real-time clock (RTC), tamper (TAMP) and backup registers
The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of
the silicon die.
The ways of powering the RTC domain are described in Section 3.7.6.
The RTC is an independent BCD timer/counter.
30/133
DS12232 Rev 3
STM32G071x8/xB
Functional overview
Features of the RTC:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
Programmable alarm
On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with
a master clock
•
•
Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be
used to improve the calendar precision
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
•
•
Two anti-tamper detection pins with programmable filter
Timestamp feature to save a calendar snapshot, triggered by an event on the
timestamp pin or a tamper event, or by switching to VBAT mode
•
•
17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable
resolution and period
Multiple clock sources and references:
–
–
–
–
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32
When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When
clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes
except for the Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wake the device up from the low-power modes.
The backup registers allow keeping 20 bytes of user application data in the event of V
DD
failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by
the system reset, power reset, and upon the device’s wakeup from Standby or Shutdown
modes.
3.20
Inter-integrated circuit interface (I2C)
The device embeds two I2C peripherals. Refer to Table 8 for the features.
2
The I C-bus interface handles communication between the microcontroller and the serial
2
2
I C-bus. It controls all I C-bus-specific sequencing, protocol, arbitration and timing.
DS12232 Rev 3
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35
Functional overview
STM32G071x8/xB
Features of the I2C peripheral:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Clock stretching
•
SMBus specification rev 3.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
–
–
–
–
Command and data acknowledge control
Address resolution protocol (ARP) support
Host and Device support
SMBus alert
Timeouts and idle condition detection
•
•
PMBus rev 1.3 standard compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent of the PCLK reprogramming
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
2
Table 8. I C implementation
I2C features(1)
I2C1
I2C2
Standard mode (up to 100 kbit/s)
X
X
X
X
X
X
X
X
X
X
X
-
Fast mode (up to 400 kbit/s)
Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os
Programmable analog and digital noise filters
SMBus/PMBus hardware support
Independent clock
-
Wakeup from Stop mode on address match
1. X: supported
-
3.21
Universal synchronous/asynchronous receiver transmitter
(USART)
The device embeds universal synchronous/asynchronous receivers/transmitters (USART1,
USART2, USART3, USART4) that communicate at speeds of up to 8 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
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DS12232 Rev 3
STM32G071x8/xB
Functional overview
half-duplex communication mode. Some can also support SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have
a clock domain independent of the CPU clock, which allows them to wake up the MCU from
Stop mode. The wakeup events from Stop mode are programmable and can be:
•
•
•
start bit detection
any received data frame
a specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 9. USART implementation
USART1
USART2
USART3
USART4
USART modes/features(1)
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
-
-
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
-
-
-
-
X
1. X: supported
3.22
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one LPUART. The peripheral supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent of the CPU clock, and can wakeup the
system from Stop mode. The Stop mode wakeup events are programmable and can be:
•
•
•
start bit detection
any received data frame
a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
DS12232 Rev 3
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35
Functional overview
STM32G071x8/xB
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.23
Serial peripheral interface (SPI)
The device contains two SPIs running at up to 32 Mbits/s in master and slave modes. It
supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight
master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI
peripherals support NSS pulse mode, TI mode and hardware CRC calculation.
The SPI peripherals can be served by the DMA controller.
2
The I S interface mode of the SPI peripheral (if supported, see the following table) supports
four different audio standards can operate as master or slave, in half-duplex communication
mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, it can output a clock for an external audio component at 256 times the sampling
frequency.
Table 10. SPI/I2S implementation
SPI features(1)
SPI1
SPI2
Hardware CRC calculation
X
X
X
X
X
X
X
X
-
Rx/Tx FIFO
NSS pulse mode
I2S mode
TI mode
X
1. X = supported.
3.24
USB Type-C™ Power Delivery controller
The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev.
1.2 and USB Power Delivery Rev. 3.0 specifications.
The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
•
•
•
•
USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
“Dead battery” support
USB Power Delivery message transmission and reception
FRS (fast role swap) support
34/133
DS12232 Rev 3
STM32G071x8/xB
Functional overview
The digital controller handles notably:
•
•
•
USB Type-C level detection with de-bounce, generating interrupts
FRS detection, generating an interrupt
byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
•
•
•
•
•
USB Power Delivery timing dividers (including a clock pre-scaler)
CRC generation/checking
4b5b encode/decode
ordered sets (with a programmable ordered set mask at receive)
frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.25
Development support
3.25.1
Serial wire debug port (SW-DP)
An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.
DS12232 Rev 3
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35
Pinouts, pin description and alternate functions
STM32G071x8/xB
4
Pinouts, pin description and alternate functions
The devices housed in packages with 48 or more pins provide 2-port USB-C Power
Delivery. The devices housed in 32-pin packages come in two variants - “GP” with a single-
port limited USB-C Power Delivery and “PD” with 2-port USB-C Power Delivery.
Figure 3. STM32G071RxT LQFP64 pinout
Top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC11
PC12
PC13
PC8
PA15
PA14-BOOT0
PA13
PA12 [PA10]
PA11 [PA9]
PA10
PD9
PD8
PC7
PC6
PA9
PA8
PB15
PB14
PC14-OSC32_IN
PC15-OSC32_OUT
VBAT
VREF+
VDD/VDDA
VSS/VSSA
PF0-OSC_IN
PF1-OSC_OUT
PF2-NRST
PC0
LQFP64
PC1
PC2
PC3
PB13
MSv39710V3
36/133
DS12232 Rev 3
STM32G071x8/xB
Pinouts, pin description and alternate functions
Figure 4. STM32G071RxI UFBGA64 pinout
1
2
3
4
5
6
7
8
PC11
PC10
PC12
PC13
VREF+
PB7
PB8
PB9
VBAT
PC0
PA3
PA2
PA1
PB6
PB3
PB4
PB5
PA7
PA6
PA5
PA4
PD6
PD5
PD4
PD3
PC7
PB0
PB1
PC4
PD2
PD1
PA15
PA10
PA9
PD0
PC9
PC8
A
B
C
D
E
F
PC15-
OSC32
_OUT
PA12
[PA10]
PC14-
OSC32
_IN
PA14-
BOOT0
PA11
[PA9]
VDD/
VDDA
PA13
PC6
PD9
PD8
VSS/
VSSA
PF2-
NRST
PF0-
OSC_I
N
PC1
PC2
PA0
PB14
PB10
PC5
PB15
PB12
PB2
PA8
PF1-
OSC_
OUT
PB13
PB11
G
H
PC3
MSv47971V1
Figure 5. STM32G071CxT LQFP48 pinout
Top view
1
36
35
34
33
32
31
30
29
28
27
26
25
PC13
PA14-BOOT0
PA13
PA12 [PA10]
PA11 [PA9]
PA10
PC7
PC6
PA9
PA8
2
PC14-OSC32_IN
PC15-OSC32_OUT
VBAT
3
4
5
VREF+
6
VDD/VDDA
VSS/VSSA
PF0-OSC_IN
PF1-OSC_OUT
PF2-NRST
PA0
LQFP48
7
8
9
10
11
12
PB15
PB14
PB13
PA1
MSv39711V3
DS12232 Rev 3
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Pinouts, pin description and alternate functions
STM32G071x8/xB
Figure 6. STM32G071CxU UFQFPN48 pinout
Top view
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
PC13
PA14-BOOT0
PA13
PA12 [PA10]
PA11 [PA9]
PA10
PC7
PC6
PA9
PA8
PB15
PB14
PC14-OSC32_IN
PC15-OSC32_OUT
VBAT
VREF+
VDD/VDDA
VSS/VSSA
PF0-OSC_IN
PF1-OSC_OUT
PF2-NRST
PA0
UFQFPN48
10
11
12
Exposed pad
PA1
PB13
VSS
MSv39714V3
Figure 7. STM32G071KxT LQFP32 pinout
Top view
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PB9
PA13
PC14-OSC32_IN
PC15-OSC32_OUT
VDD/VDDA
VSS/VSSA
PF2-NRST
PA0
PA12 [PA10]
PA11 [PA9]
PA10
LQFP32
PC6
PA9
PA8
GP version
PA1
PB2
(_KxT)
MSv39712V3
Top view
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PB9
PC14-OSC32_IN
PC15-OSC32_OUT
VDD/VDDA
VSS/VSSA
PA13
PA12 [PA10]
PA11 [PA9]
PA10
LQFP32
PC6
PF2-NRST
PA9
PD version
(_KxTxN)
PA0
PA8
PA1
PB15
MSv42120V1
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DS12232 Rev 3
STM32G071x8/xB
Pinouts, pin description and alternate functions
Figure 8. STM32G071KxU UFQFPN32 pinout
Top view
PB9
PC14-OSC32_IN
PC15-OSC32_OUT
VDD/VDDA
VSS/VSSA
PA13
PA12 [PA10]
PA11 [PA9]
PA10
PC6
PA9
PA8
PB2
FQFPN
PF2-NRST
GP version
PA0
PA1
(_KxU)
VSS
MSv39715V3
Top view
PB9
PC14-OSC32_IN
PC15-OSC32_OUT
VDD/VDDA
VSS/VSSA
PA13
PA12 [PA10]
PA11 [PA9]
PA10
PC6
PA9
PA8
PB15
FQFPN
PF2-NRST
PD version
(_KxUxN)
PA0
PA1
VSS
MSv42121V1
DS12232 Rev 3
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47
Pinouts, pin description and alternate functions
STM32G071x8/xB
Figure 9. STM32G071GxU UFQFPN28 pinout
Top view
1
2
3
4
5
6
7
21
20
19
18
17
16
15
PC14-OSC32_IN
PC15-OSC32_OUT
VDD/VDDA
VSS/VSSA
PF2-NRST
PA0
PA14-BOOT0
PA13
PA12 [PA10]
PA11 [PA9]
PC6
PA8
PB1
UFQFPN28
GP version
PA1
(_GxU)
MSv39713V4
Top view
1
2
3
4
5
6
7
21
20
19
18
17
16
15
PC14-OSC32_IN
PC15-OSC32_OUT
VDD/VDDA
VSS/VSSA
PF2-NRST
PA0
PA14-BOOT0
PA13
PA12 [PA10]
PA11 [PA9]
PC6
PA8
PB15
UFQFPN28
PD version
(_GxUxN)
PA1
MSv42122V2
Figure 10. STM32G071Ex WLCSP25 pinout
1
2
3
4
5
Top view
PC14-
OSC32
_IN
PA14-
PA15
PB5
PB6
PA3
PA4
PA5
PB7
PB8
PA0
PA1
PA2
A
B
C
D
E
BOOT0
PC15-
OSC32
_OUT
PA12
[PA10]
PA13
PA6
PA7
PB0
PA11
[PA9]
VDD/
VDDA
VSS/
VSSA
PA8
PB1
PF2 -
NRST
MSv47938V2
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Pinouts, pin description and alternate functions
Table 11. Terms and symbols used in Table 12
Symbol Definition
Column
Terminal name corresponds to its by-default function at reset, unless otherwise specified in
parenthesis under the pin name.
Pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
TT
RST
Input / output pin
5 V tolerant I/O
3.6 V tolerant I/O
Bidirectional reset pin with embedded weak pull-up resistor
Options for TT or FT I/Os
I/O, Fm+ capable
I/O structure
_f
_a
_c
_d
I/O, with analog switch function
I/O, USB Type-C PD capable
I/O, USB Type-C PD Dead Battery function
Note
Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Functions selected through GPIOx_AFR registers
Alternate
functions
Pin
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
Table 12. Pin assignment and description
Pin Number
Pin name
Alternate
functions
Additional
functions
(function
upon reset)
USART3_RX, USART4_RX,
TIM1_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A1
B2
C2
1
2
3
PC11
PC12
PC13
I/O
I/O
I/O
FT
FT
FT
-
-
-
LPTIM1_IN1,
UCPD1_FRSTX,
TIM14_CH1
-
TAMP_IN1,RTC_TS,
RTC_OUT1,WKUP2
(1)(2)
1
TIM1_BKIN
DS12232 Rev 3
41/133
47
Pinouts, pin description and alternate functions
STM32G071x8/xB
Table 12. Pin assignment and description (continued)
Pin Number
Pin name
Alternate
functions
Additional
functions
(function
upon reset)
PC14-
OSC32_IN
(PC14)
(1)(2)
(1)(2)
(1)(2)
-
-
-
-
-
2
-
C1
-
4
-
I/O
I/O
FT
FT
FT
TIM1_BKIN2
TIM1_BKIN2
OSC32_IN
OSC32_IN,OSC_IN
OSC32_OUT
PC14-
OSC32_IN
(PC14)
A5
B5
1
2
1
2
2
3
2
3
PC15-
OSC32_OUT I/O
(PC15)
OSC32_EN, OSC_EN,
TIM15_BKIN
3
B1
5
-
-
-
-
-
-
-
-
-
4
5
6
7
D3
D2
D1
E1
6
7
8
9
VBAT
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VREF+
VREF_OUT
C5
D5
3
4
3
4
4
5
4
5
VDD/VDDA
VSS/VSSA
-
-
PF0-OSC_IN
(PF0)
-
-
-
-
-
-
-
-
-
-
8
9
F1 10
G1 11
I/O
I/O
FT
FT
-
-
TIM14_CH1
OSC_IN
PF1-
OSC_OUT
(PF1)
OSC_EN, TIM15_CH1N
MCO
OSC_OUT
E5
-
5
-
5
-
6
-
6
-
10 E2 12 PF2 - NRST I/O
FT
FT
-
-
NRST
-
LPTIM1_IN1,
LPUART1_RX, LPTIM2_IN1
-
-
-
-
E3 13
F2 14
G2 15
H1 16
PC0
PC1
PC2
PC3
I/O
I/O
I/O
I/O
LPTIM1_OUT,
LPUART1_TX, TIM15_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FT
FT
FT
-
-
-
-
-
-
LPTIM1_IN2, SPI2_MISO,
TIM15_CH2
LPTIM1_ETR, SPI2_MOSI,
LPTIM2_ETR
SPI2_SCK, USART2_CTS,
TIM2_CH1_ETR,
USART4_TX, LPTIM1_OUT,
UCPD2_FRSTX,
COMP1_INM,ADC_IN0,
TAMP_IN2,WKUP1
C4
6
6
7
7
11 H2 17
PA0
I/O
FT_a
-
COMP1_OUT
42/133
DS12232 Rev 3
STM32G071x8/xB
Pin Number
Pinouts, pin description and alternate functions
Table 12. Pin assignment and description (continued)
Pin name
Alternate
functions
Additional
functions
(function
upon reset)
SPI1_SCK/I2S1_CK,
USART2_RTS_DE_CK,
TIM2_CH2, USART4_RX,
TIM15_CH1N, I2C1_SMBA,
EVENTOUT
D4
E4
C3
-
7
8
9
-
7
8
9
-
8
9
8
9
12 H3 18
PA1
PA2
PA3
PA4
PA4
PA5
PA6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT_a
FT_a
FT_a
TT_a
TT_a
TT_a
FT_a
-
-
-
-
-
-
-
COMP1_INP, ADC_IN1
SPI1_MOSI/I2S1_SD,
USART2_TX, TIM2_CH3,
UCPD1_FRSTX,
TIM15_CH1, LPUART1_TX,
COMP2_OUT
COMP2_INM,ADC_IN2,
WKUP4,LSCO
13 G3 19
SPI2_MISO, USART2_RX,
TIM2_CH4,
UCPD2_FRSTX,
TIM15_CH2, LPUART1_RX,
EVENTOUT
10 10 14 F3 20
COMP2_INP, ADC_IN3
SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
LPTIM2_OUT,
ADC_IN4, DAC_OUT1,
RTC_OUT2
-
-
15 H4 21
UCPD2_FRSTX,
EVENTOUT
SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
LPTIM2_OUT,
ADC_IN4, DAC_OUT1,
TAMP_IN1,RTC_TS,
RTC_OUT1,WKUP2
D3 10 10 11 11
-
-
-
UCPD2_FRSTX,
EVENTOUT
SPI1_SCK/I2S1_CK, CEC,
TIM2_CH1_ETR,
USART3_TX, LPTIM2_ETR, ADC_IN5, DAC_OUT2
E3 11 11 12 12 16 G4 22
C2 12 12 13 13 17 F4 23
D2 13 13 14 14 18 E4 24
UCPD1_FRSTX,
EVENTOUT
SPI1_MISO/I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
USART3_CTS, TIM16_CH1,
LPUART1_CTS,
ADC_IN6
ADC_IN7
COMP1_OUT
SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM1_CH1N,
TIM14_CH1, TIM17_CH1,
UCPD1_FRSTX,
PA7
PC4
I/O
I/O
FT_a
FT_a
-
-
COMP2_OUT
USART3_TX, USART1_TX,
TIM2_CH1_ETR
COMP1_INM,
ADC_IN17
-
-
-
-
-
-
H5 25
DS12232 Rev 3
43/133
47
Pinouts, pin description and alternate functions
STM32G071x8/xB
Table 12. Pin assignment and description (continued)
Pin Number
Pin name
Alternate
functions
Additional
functions
(function
upon reset)
USART3_RX, USART1_RX,
TIM2_CH2
COMP1_INP,
ADC_IN18, WKUP5
-
-
-
-
-
-
-
H6 26
PC5
PB0
I/O
I/O
FT_a
FT_a
-
-
SPI1_NSS/I2S1_WS,
TIM3_CH3, TIM1_CH2N,
USART3_RX, LPTIM1_OUT,
UCPD1_FRSTX,
E2 14
15 15 19 F5 27
ADC_IN8
COMP1_OUT
SPI1_NSS/I2S1_WS,
TIM3_CH3, TIM1_CH2N,
USART3_RX, LPTIM1_OUT,
UCPD1_FRSTX,
UCPD1_DBCC2,
ADC_IN8
(3)
-
-
14
-
-
-
-
-
PB0
PB1
I/O FT_da
COMP1_OUT
TIM14_CH1, TIM3_CH4,
TIM1_CH3N,
USART3_RTS_DE_CK,
LPTIM2_IN1,
LPUART1_RTS_DE,
EVENTOUT
E1 15
-
16 16 20 G5 28
I/O
I/O
FT_a
FT_a
-
COMP1_INM, ADC_IN9
SPI2_MISO, USART3_TX,
LPTIM1_OUT, EVENTOUT
-
-
-
-
-
-
17
-
-
-
21 H7 29
22 G6 30
PB2
-
-
COMP1_INP, ADC_IN10
ADC_IN11
CEC, LPUART1_RX,
TIM2_CH3, USART3_TX,
SPI2_SCK, I2C2_SCL,
COMP1_OUT
PB10
I/O FT_fa
I/O FT_fa
SPI2_MOSI, LPUART1_TX,
TIM2_CH4, USART3_RX,
I2C2_SDA, COMP2_OUT
-
-
-
-
-
-
-
-
-
-
23 H8 31
24 G7 32
PB11
PB12
-
-
ADC_IN15
ADC_IN16
SPI2_NSS,
LPUART1_RTS_DE,
TIM1_BKIN, TIM15_BKIN,
UCPD2_FRSTX,
I/O
I/O
FT_a
FT_f
EVENTOUT
SPI2_SCK, LPUART1_CTS,
TIM1_CH1N,
-
-
-
-
-
25 G8 33
PB13
-
USART3_CTS,
-
TIM15_CH1N, I2C2_SCL,
EVENTOUT
44/133
DS12232 Rev 3
STM32G071x8/xB
Pin Number
Pinouts, pin description and alternate functions
Table 12. Pin assignment and description (continued)
Pin name
Alternate
functions
Additional
functions
(function
upon reset)
SPI2_MISO,
UCPD1_FRSTX,
TIM1_CH2N,
-
-
-
-
-
-
-
-
26 F6 34
PB14
I/O
FT_f
-
-
USART3_RTS_DE_CK,
TIM15_CH1, I2C2_SDA,
EVENTOUT
SPI2_MOSI, TIM1_CH3N,
TIM15_CH1N, TIM15_CH2,
EVENTOUT
UCPD1_CC2,
RTC_REFIN,
(3)
(3)
15
17 27 F7 35
PB15
PA8
I/O
I/O
FT_c
FT_c
MCO, SPI2_NSS,
TIM1_CH1, LPTIM2_OUT,
EVENTOUT
D1 16 16 18 18 28 F8 36
UCPD1_CC1
MCO, USART1_TX,
TIM1_CH2, SPI2_MISO,
TIM15_BKIN, I2C1_SCL,
EVENTOUT
(3)
-
-
-
19 19 29 E6 37
20 20 30 E7 38
PA9
I/O FT_fd
UCPD1_DBCC1
UCPD1_FRSTX,
TIM3_CH1, TIM2_CH3
-
-
-
17
-
-
17
-
PC6
PC6
PC7
I/O
I/O
I/O
FT
FT_d
FT
-
-
UCPD1_FRSTX,
TIM3_CH1, TIM2_CH3
(3)
-
-
-
-
-
-
-
UCPD1_DBCC1
-
UCPD2_FRSTX,
TIM3_CH2, TIM2_CH4
-
31 E5 39
-
-
USART3_TX,
SPI1_SCK/I2S1_CK,
LPTIM1_OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E8 40
D8 41
PD8
PD9
I/O
I/O
FT
FT
-
USART3_RX,
SPI1_NSS/I2S1_WS,
TIM1_BKIN2
-
-
SPI2_MOSI, USART1_RX,
TIM1_CH3, TIM17_BKIN,
I2C1_SDA, EVENTOUT
(3)
21 21 32 D6 42
PA10
I/O FT_fd
UCPD1_DBCC2
SPI1_MISO/I2S1_MCK,
USART1_CTS, TIM1_CH4,
TIM1_BKIN2, I2C2_SCL,
COMP1_OUT
PA11
C1 18 18 22 22 33 C8 43
I/O
I/O
FT_f
FT_f
-
-
-
-
[PA9](4)
SPI1_MOSI/I2S1_SD,
USART1_RTS_DE_CK,
TIM1_ETR, I2S_CKIN,
I2C2_SDA, COMP2_OUT
PA12
B1 19 19 23 23 34 B8 44
[PA10](4)
DS12232 Rev 3
45/133
47
Pinouts, pin description and alternate functions
STM32G071x8/xB
Table 12. Pin assignment and description (continued)
Pin Number
Pin name
Alternate
functions
Additional
functions
(function
upon reset)
SWDIO, IR_OUT,
EVENTOUT
(5)
(5)
B2 20 20 24 24 35 D7 45
PA13
I/O
FT
FT
-
SWCLK, USART2_TX,
EVENTOUT
A2 21 21 25 25 36 C7 46 PA14-BOOT0 I/O
BOOT0
SPI1_NSS/I2S1_WS,
USART2_RX,
TIM2_CH1_ETR,
A1 22
-
26
-
37 C6 47
PA15
I/O
FT
-
-
-
USART4_RTS_DE_CK,
USART3_RTS_DE_CK,
EVENTOUT
UCPD2_FRSTX,
TIM3_CH3, TIM1_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A8 48
B7 49
PC8
PC9
PD0
PD1
PD2
PD3
PD4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
-
I2S_CKIN, TIM3_CH4,
TIM1_CH2
-
-
-
EVENTOUT, SPI2_NSS,
TIM16_CH1
(3)
22
23
24
25
-
26 38 A7 50
27 39 B6 51
28 40 A6 52
29 41 D5 53
FT_c
FT_d
FT_c
FT_d
FT
UCPD2_CC1
UCPD2_DBCC1
UCPD2_CC2
UCPD2_DBCC2
-
EVENTOUT, SPI2_SCK,
TIM17_CH1
(3)
(3)
(3)
USART3_RTS_DE_CK,
TIM3_ETR, TIM1_CH1N
USART2_CTS, SPI2_MISO,
TIM1_CH2N
USART2_RTS_DE_CK,
SPI2_MOSI, TIM1_CH3N
-
-
-
-
C5 54
B5 55
-
-
USART2_TX,
SPI1_MISO/I2S1_MCK,
TIM1_BKIN
-
-
-
-
-
-
-
-
PD5
PD6
I/O
I/O
FT
FT
-
-
USART2_RX,
SPI1_MOSI/I2S1_SD,
LPTIM2_OUT
-
-
-
-
A5 56
-
-
-
SPI1_SCK/I2S1_CK,
TIM1_CH2, TIM2_CH2,
USART1_RTS_DE_CK,
EVENTOUT
-
-
23
24
-
-
27
28
42 B4 57
43 C4 58
PB3
PB4
I/O
I/O
FT_a
FT_a
COMP2_INM
COMP2_INP
SPI1_MISO/I2S1_MCK,
TIM3_CH1, USART1_CTS,
TIM17_BKIN, EVENTOUT
46/133
DS12232 Rev 3
STM32G071x8/xB
Pin Number
Pinouts, pin description and alternate functions
Table 12. Pin assignment and description (continued)
Pin name
Alternate
functions
Additional
functions
(function
upon reset)
SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM16_BKIN,
LPTIM1_IN1, I2C1_SMBA,
COMP2_OUT
A3 25
-
29
-
44 D4 59
PB5
PB6
I/O
FT
-
-
WKUP6
USART1_TX, TIM1_CH3,
TIM16_CH1N, SPI2_MISO,
LPTIM1_ETR, I2C1_SCL,
EVENTOUT
B3 26 26 30 30 45 A4 60
A4 27 27 31 31 46 A3 61
B4 28 28 32 32 47 B3 62
I/O FT_fa
I/O FT_fa
COMP2_INP
USART1_RX, SPI2_MOSI,
TIM17_CH1N,
USART4_CTS,
LPTIM1_IN2, I2C1_SDA,
EVENTOUT
PB7
PB8
-
-
COMP2_INM, PVD_IN
CEC, SPI2_SCK,
TIM16_CH1, USART3_TX,
TIM15_BKIN, I2C1_SCL,
EVENTOUT
I/O
FT_f
-
IR_OUT, UCPD2_FRSTX,
TIM17_CH1, USART3_RX,
SPI2_NSS, I2C1_SDA,
EVENTOUT
-
-
-
-
-
-
1
-
1
-
48 C3 63
PB9
I/O
I/O
FT_f
FT
-
-
-
-
USART3_TX, USART4_TX,
TIM1_CH3
-
A2 64
PC10
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to
the RTC domain and RTC register descriptions in the RM0444 reference manual.
3. Upon reset, a pull-down resistor might be present on PB15, PA8, PD0, or PD2, depending on the voltage level on PB0,
PA9, PC6, PA10, PD1, and PD3. In order to disable this resistor, strobe the UCPDx_STROBE bit of the SYSCFG_CFGR1
register during start-up sequence.
4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.
5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the
internal pull-down on PA14 pin are activated.
DS12232 Rev 3
47/133
47
Table 13. Port A alternate function mapping
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PA0
SPI2_SCK
USART2_CTS
TIM2_CH1_ETR
-
USART4_TX
LPTIM1_OUT
UCPD2_FRSTX
COMP1_OUT
SPI1_SCK/
I2S1_CK
USART2_RTS
_DE_CK
PA1
TIM2_CH2
-
USART4_RX
TIM15_CH1N
I2C1_SMBA
EVENTOUT
SPI1_MOSI/
I2S1_SD
PA2
PA3
PA4
USART2_TX
USART2_RX
SPI2_MOSI
TIM2_CH3
TIM2_CH4
-
-
-
-
UCPD1_FRSTX
UCPD2_FRSTX
TIM14_CH1
TIM15_CH1
TIM15_CH2
LPTIM2_OUT
LPUART1_TX
LPUART1_RX
UCPD2_FRSTX
COMP2_OUT
EVENTOUT
EVENTOUT
SPI2_MISO
SPI1_NSS/
I2S1_WS
SPI1_SCK/
I2S1_CK
PA5
PA6
PA7
CEC
TIM2_CH1_ETR
TIM1_BKIN
-
-
USART3_TX
USART3_CTS
TIM14_CH1
LPTIM2_ETR
TIM16_CH1
TIM17_CH1
UCPD1_FRSTX
LPUART1_CTS
UCPD1_FRSTX
EVENTOUT
COMP1_OUT
COMP2_OUT
SPI1_MISO/
I2S1_MCK
TIM3_CH1
TIM3_CH2
SPI1_MOSI/
I2S1_SD
TIM1_CH1N
-
-
-
-
PA8
PA9
MCO
MCO
SPI2_NSS
USART1_TX
USART1_RX
TIM1_CH1
TIM1_CH2
TIM1_CH3
-
LPTIM2_OUT
TIM15_BKIN
TIM17_BKIN
-
EVENTOUT
EVENTOUT
EVENTOUT
SPI2_MISO
-
I2C1_SCL
I2C1_SDA
PA10
SPI2_MOSI
SPI1_MISO/
I2S1_MCK
PA11
PA12
USART1_CTS
TIM1_CH4
TIM1_ETR
-
-
-
-
TIM1_BKIN2
I2S_CKIN
I2C2_SCL
I2C2_SDA
COMP1_OUT
COMP2_OUT
SPI1_MOSI/
I2S1_SD
USART1_RTS
_DE_CK
PA13
PA14
SWDIO
SWCLK
IR_OUT
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
USART2_TX
SPI1_NSS/
I2S1_WS
USART4_RTS
_DE_CK
USART3_RTS
_DE_CK
PA15
USART2_RX
TIM2_CH1_ETR
-
-
EVENTOUT
Table 14. Port B alternate function mapping
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1_NSS/
I2S1_WS
PB0
TIM3_CH3
TIM1_CH2N
-
USART3_RX
LPTIM1_OUT
UCPD1_FRSTX
COMP1_OUT
USART3_RTS
_DE_CK
LPUART1_RTS
_DE
PB1
PB2
PB3
TIM14_CH1
-
TIM3_CH4
SPI2_MISO
TIM1_CH2
TIM1_CH3N
-
-
-
-
LPTIM2_IN1
EVENTOUT
EVENTOUT
EVENTOUT
USART3_TX
LPTIM1_OUT
-
-
-
SPI1_SCK/
I2S1_CK
USART1_RTS
_DE_CK
TIM2_CH2
SPI1_MISO/
I2S1_MCK
PB4
PB5
TIM3_CH1
TIM3_CH2
-
-
-
USART1_CTS
-
TIM17_BKIN
LPTIM1_IN1
-
EVENTOUT
SPI1_MOSI/
I2S1_SD
TIM16_BKIN
I2C1_SMBA
COMP2_OUT
PB6
PB7
USART1_TX
USART1_RX
CEC
TIM1_CH3
SPI2_MOSI
TIM16_CH1N
TIM17_CH1N
TIM16_CH1
TIM17_CH1
TIM2_CH3
-
-
-
-
-
-
SPI2_MISO
USART4_CTS
USART3_TX
USART3_RX
USART3_TX
USART3_RX
LPTIM1_ETR
LPTIM1_IN2
TIM15_BKIN
SPI2_NSS
SPI2_SCK
-
I2C1_SCL
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
COMP1_OUT
COMP2_OUT
PB8
SPI2_SCK
PB9
IR_OUT
UCPD2_FRSTX
LPUART1_RX
LPUART1_TX
PB10
PB11
CEC
SPI2_MOSI
TIM2_CH4
LPUART1_RTS
_DE
PB12
PB13
PB14
PB15
SPI2_NSS
SPI2_SCK
SPI2_MISO
SPI2_MOSI
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
-
-
-
-
-
TIM15_BKIN
TIM15_CH1N
TIM15_CH1
TIM15_CH2
UCPD2_FRSTX
I2C2_SCL
I2C2_SDA
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
LPUART1_CTS
USART3_CTS
USART3_RTS
_DE_CK
UCPD1_FRSTX
-
TIM15_CH1N
Table 15. Port C alternate function mapping
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PC0
PC1
LPTIM1_IN1
LPTIM1_OUT
LPTIM1_IN2
LPTIM1_ETR
USART3_TX
USART3_RX
UCPD1_FRSTX
UCPD2_FRSTX
UCPD2_FRSTX
I2S_CKIN
LPUART1_RX
LPUART1_TX
SPI2_MISO
SPI2_MOSI
USART1_TX
USART1_RX
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
USART4_TX
USART4_RX
UCPD1_FRSTX
-
LPTIM2_IN1
TIM15_CH1
TIM15_CH2
LPTIM2_ETR
TIM2_CH1_ETR
TIM2_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC2
PC3
PC4
PC5
PC6
TIM2_CH3
PC7
TIM2_CH4
PC8
TIM1_CH1
PC9
TIM1_CH2
PC10
PC11
PC12
PC13
PC14
PC15
USART3_TX
USART3_RX
LPTIM1_IN1
-
TIM1_CH3
TIM1_CH4
TIM14_CH1
TIM1_BKIN
TIM1_BKIN2
TIM15_BKIN
-
-
OSC32_EN
OSC_EN
*
Table 16. Port D alternate function mapping
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PD0
PD1
EVENTOUT
EVENTOUT
SPI2_NSS
SPI2_SCK
TIM16_CH1
TIM17_CH1
-
-
-
-
-
-
-
-
-
-
USART3_RTS
_DE_CK
PD2
PD3
PD4
TIM3_ETR
SPI2_MISO
SPI2_MOSI
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_CTS
USART2_RTS
_DE_CK
SPI1_MISO/
I2S1_MCK
PD5
PD6
PD8
PD9
USART2_TX
USART2_RX
USART3_TX
USART3_RX
TIM1_BKIN
LPTIM2_OUT
LPTIM1_OUT
TIM1_BKIN2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI1_MOSI/
I2S1_SD
SPI1_SCK/
I2S1_CK
SPI1_NSS/
I2S1_WS
Table 17. Port F alternate function mapping
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PF0
PF1
PF2
-
-
-
-
TIM14_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OSC_EN
MCO
TIM15_CH1N
-
Electrical characteristics
STM32G071x8/xB
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
Parameter values defined at temperatures or in temperature ranges out of the ordering
information scope are to be ignored.
Packages used for characterizing certain electrical parameters may differ from the
commercial packages as per the ordering information.
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T (max) (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
52/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
5.1.6
Power supply scheme
Figure 13. Power supply scheme
VBAT
Backup circuitry
(LSE, RTC and
backup registers)
1.55 V to 3.6 V
Power
switch
VDD
VCORE
VDD/VDDA
GPIOs
VDD
Regulator
VDDIO1
OUT
IN
Kernel logic
(CPU, digital and
memories)
IO
logic
1 x 100 nF
+ 1 x 4.7 μF
VSS
VDDA
VREF
VREF+
1 μF
ADC
DAC
COMPs
VREFBUF
VREF+
VREF-
100 nF
VSSA
VSS/VSSA
MSv47900V1
Caution:
Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
5.1.7
Current consumption measurement
Figure 14. Current consumption measurement scheme
IDDVBAT
VBAT
VBAT
IDD
VDD/VDDA
VDD
(VDDA
)
MSv47901V1
DS12232 Rev 3
53/133
106
Electrical characteristics
STM32G071x8/xB
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
All voltages are defined with respect to V
.
SS
Table 18. Voltage characteristics
Ratings Min
External supply voltage
Symbol
Max
Unit
VDD
VBAT
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
4.0
External supply voltage on VBAT pin
External voltage on VREF+ pin
Input voltage on FT_xx pins except FT_c
Input voltage on FT_c pins
4.0
Min(VDD + 0.4, 4.0)
VDD + 4.0(2)
5.5
VREF+
V
(1)
VIN
Input voltage on any other pin
4.0
1. Refer to Table 19 for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
Table 19. Current characteristics
Symbol
Ratings
Max
Unit
IVDD/VDDA Current into VDD/VDDA power pin (source)(1)
IVSS/VSSA Current out of VSS/VSSA ground pin (sink)(1)
Output current sunk by any I/O and control pin except FT_f
100
100
15
IIO(PIN)
Output current sunk by any FT_f pin
20
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins
Total output current sourced by sum of all I/Os and control pins
Injected current on a FT_xx pin
15
mA
80
∑IIO(PIN)
80
-5 / NA(3)
-5 / 0
25
(2)
IINJ(PIN)
Injected current on a TT_a pin(4)
∑|IINJ(PIN)
|
Total injected current (sum of all I/Os and control pins)(5)
1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power
supplies, in the permitted range.
2. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. On these I/Os, any current injection disturbs the analog performances of the device.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
54/133
DS12232 Rev 3
STM32G071x8/xB
Symbol
Electrical characteristics
Table 20. Thermal characteristics
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
Maximum junction temperature
–65 to +150
150
°C
°C
5.3
Operating conditions
5.3.1
General operating conditions
Table 21. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK Internal AHB clock frequency
fPCLK Internal APB clock frequency
-
-
-
0
0
64
64
MHz
V
VDD
Standard operating voltage
1.7(1)
3.6
For ADC and COMP
operation
1.62
3.6
VDDA Analog supply voltage
V
For DAC operation
For VREFBUF operation
-
1.8
2.4
3.6
3.6
VBAT
Backup operating voltage
I/O input voltage
1.55
-0.3
-0.3
-0.3
-40
-40
-40
-40
-40
-40
3.6
V
V
All except TT_xx and FT_c
TT_xx
Min(VDD + 3.6, 5.5)(2)
VIN
VDD + 0.3
5.0(2)
85
FT_c
Suffix 6(4)
TA
Ambient temperature(3)
Junction temperature
Suffix 7(4)
105
°C
°C
Suffix 3(4)
125
Suffix 6(4)
105
TJ
Suffix 7(4)
125
Suffix 3(4)
130
1. When RESET is released functionality is guaranteed down to VPDR min.
2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.
3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided
that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.9: Thermal characteristics.
4. Temperature range digit in the order code. See Section 7: Ordering information.
DS12232 Rev 3
55/133
106
Electrical characteristics
STM32G071x8/xB
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
Table 22. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rising
-
∞
∞
∞
µs/V
tVDD
VDD slew rate
VDD falling; ULPEN = 0
VDD falling; ULPEN = 1
10
100
ms/V
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature conditions summarized in Table 21: General operating conditions.
Table 23. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions(1) Min
Typ
Max Unit
(2)
tRSTTEMPO
POR temporization when VDD crosses VPOR
Power-on reset threshold
VDD rising
-
250
400
μs
V
(2)
VPOR
-
-
1.62 1.66 1.70
1.60 1.64 1.69
2.05 2.10 2.18
1.95 2.00 2.08
2.20 2.31 2.38
2.10 2.21 2.28
2.50 2.62 2.68
2.40 2.52 2.58
2.80 2.91 3.00
2.70 2.81 2.90
2.05 2.15 2.22
1.95 2.05 2.12
2.20 2.30 2.37
2.10 2.20 2.27
2.35 2.46 2.54
2.25 2.36 2.44
2.50 2.62 2.70
2.40 2.52 2.60
2.65 2.74 2.87
2.55 2.64 2.77
(2)
VPDR
Power-down reset threshold
V
V
DD rising
VDD falling
DD rising
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
Brownout reset threshold 1
Brownout reset threshold 2
Brownout reset threshold 3
Brownout reset threshold 4
Programmable voltage detector threshold 0
PVD threshold 1
V
V
V
V
V
V
V
V
V
V
VDD falling
VDD rising
VDD falling
V
DD rising
VDD falling
DD rising
VDD falling
DD rising
VDD falling
DD rising
VDD falling
DD rising
VDD falling
DD rising
VDD falling
V
V
V
PVD threshold 2
V
PVD threshold 3
V
PVD threshold 4
56/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
Table 23. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions(1) Min
DD rising
VDD falling
DD rising
Typ
Max Unit
V
2.80 2.91 3.03
2.70 2.81 2.93
2.90 3.01 3.14
2.80 2.91 3.04
VPVD5
PVD threshold 5
PVD threshold 6
V
V
V
VPVD6
VDD falling
Hysteresis in
continuous
mode
-
-
20
30
-
-
Vhyst_POR_PDR
Hysteresis of VPOR and VPDR
mV
Hysteresis in
other mode
Vhyst_BOR_PVD
Hysteresis of VBORx and VPVDx
BOR and PVD consumption
-
-
-
-
100
1.1
-
mV
µA
(2)
IDD(BOR_PVD)
1.6
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
2. Guaranteed by design.
5.3.4
Embedded voltage reference
The parameters given in Table 24 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 24. Embedded internal voltage reference
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference voltage
-40°C < TJ < 130°C
1.182 1.212 1.232
V
ADC sampling time when reading
the internal reference voltage
(1)
tS_vrefint
-
-
-
4(2)
-
8
-
µs
µs
Start time of reference voltage
buffer when ADC is enable
tstart_vrefint
-
-
-
12(2)
20(2)
VREFINT buffer consumption from
VDD when converted by ADC
IDD(VREFINTBUF)
12.5
µA
mV
Internal reference voltage spread
over the temperature range
∆VREFINT
V
DD = 3 V
5
7.5(2)
50(2)
TCoeff_vrefint
ACoeff
Temperature coefficient
Long term stability
Voltage coefficient
-
-
-
30
ppm/°C
ppm
1000 hours, T = 25 °C
3.0 V < VDD < 3.6 V
300 1000(2)
VDDCoeff
-
250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
-
VREFINT
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
DS12232 Rev 3
57/133
106
Electrical characteristics
STM32G071x8/xB
Figure 15. V
vs. temperature
REFINT
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40
°C
-20
0
20
40
60
80
100
120
Mean
Min
Max
MSv40169V1
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the f
frequency (refer to the table “Number of wait states according
HCLK
to CPU clock (HCLK) frequency” available in the RM0444 reference manual).
•
•
When the peripherals are enabled f
= f
PCLK
HCLK
PCLK
For Flash memory and shared peripherals f
= f
= f
HCLK HCLKS
Unless otherwise stated, values given in Table 25 through Table 33 are derived from tests
performed under ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
58/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
Table 25. Current consumption in Run and Low-power run modes
at different die temperatures
Conditions
Typ
Max(1)
Symbol
Parameter
Unit
Fetch
25° 85° 125° 25° 85° 130°
General
fHCLK
from(2)
C
C
C
C
C
C
64 MHz
56 MHz
48 MHz
32 MHz
24 MHz
16 MHz
64 MHz
56 MHz
48 MHz
32 MHz
24 MHz
16 MHz
16 MHz
8 MHz
6.3
6.4
6.8
6.7
7.0
7.7
5.5
5.0
3.5
2.8
1.8
6.0
5.3
4.7
3.3
2.6
1.7
1.4
0.8
0.3
1.4
0.7
0.4
0.3
5.7
5.1
3.6
2.9
1.9
6.2
5.5
4.8
3.4
2.7
1.7
1.5
0.9
0.3
1.4
0.8
0.5
0.3
5.9
5.4
3.8
3.1
2.1
6.4
5.7
5.0
3.5
2.9
1.9
1.7
1.0
0.5
1.6
1.0
0.6
0.5
5.9
5.2
4.0
3.1
2.1
6.3
5.6
5.0
3.5
2.8
1.9
1.7
1.2
0.5
1.6
1.1
0.7
0.5
6.3
5.7
4.3
3.6
2.5
6.6
5.8
5.2
3.8
3.1
2.1
2.0
1.3
0.8
1.8
1.2
0.9
0.8
6.8
6.3
4.7
4.0
3.0
7.0
6.2
5.6
4.1
3.4
2.7
2.6
1.8
1.4
2.2
1.6
1.5
1.2
Flash
memory
Range 1;
PLL enabled;
fHCLK = fHSE_bypass
(≤16 MHz),
fHCLK = fPLLRCLK
(>16 MHz);
(3)
Supply
current in
Run mode
SRAM
IDD(Run)
mA
Flash
memory
Range 2;
PLL enabled;
fHCLK = fHSE_bypass
(≤16 MHz),
2 MHz
16 MHz
8 MHz
fHCLK = fPLLRCLK
(>16 MHz);
SRAM
(3)
4 MHz
2 MHz
2 MHz
220 255 420 530 795 1255
105 155 320 505 770 1200
1 MHz
Flash
memory
500 kHz
125 kHz
32 kHz
2 MHz
67
26
17
105 265 465 700 1110
PLL disabled;
fHCLK = fHSE
66
56
230 450 520 1045
220 375 475 1035
Supply
current in bypass (> 32 kHz),
Low-power fHCLK = fLSE
IDD(LPRun)
µA
199 231 380 485 700 1220
run mode bypass (= 32 kHz);
(3)
1 MHz
95
61
24
15
140 290 430 660 1140
500 kHz
125 kHz
32 kHz
SRAM
95
59
55
240 365 625 1100
225 335 440 970
220 325 355 940
1. Based on characterization results, not tested in production.
2. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM.
3. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled, cache enabled,
prefetch disabled for code and data fetch from Flash and enabled from SRAM
DS12232 Rev 3
59/133
106
Electrical characteristics
STM32G071x8/xB
Table 26. Typical current consumption in Run and Low-power run modes,
depending on code executed
Conditions
Typ
Typ
Symbol
Parameter
Unit
Unit
Fetch
General
Code
25 °C
25 °C
from(1)
Reduced code(3)
Coremark
6.4
6.2
5.9
4.6
4.6
6.2
6.2
6.0
6.2
4.8
1.5
1.5
1.5
1.1
1.1
1.5
1.4
1.4
1.5
1.1
380
395
405
385
400
250
245
240
250
230
100
97
Flash
memory
Dhrystone 2.1
Fibonacci
92
71
Range 1;
While(1) loop
Reduced code(3)
Coremark
71
fHCLK = fPLLRCLK
=
64 MHz;
96
(2)
97
Dhrystone 2.1
Fibonacci
SRAM
93
96
Supply
current in
Run mode
While(1) loop
Reduced code(3)
Coremark
75
IDD(Run)
mA
uA/MHz
94
94
Flash
memory
Dhrystone 2.1
Fibonacci
91
69
Range 2;
fHCLK = fHSI16
16 MHz,
=
While(1) loop
Reduced code(3)
Coremark
69
91
PLL disabled,
(2)
88
Dhrystone 2.1
Fibonacci
SRAM
84
91
While(1) loop
Reduced code(3)
Coremark
69
190
198
203
193
200
125
123
120
125
115
Flash
memory
Dhrystone 2.1
Fibonacci
Supply
fHCLK = fHSI16/8 =
While(1) loop
Reduced code(3)
Coremark
current in 2 MHz;
IDD(LPRun)
uA
uA/MHz
Low-power PLL disabled,
(2)
run mode
Dhrystone 2.1
Fibonacci
SRAM
While(1) loop
1. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM.
2. = 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM
3. Reduced code used for characterization results provided in Table 25.
V
DD
60/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
Table 27. Current consumption in Sleep and Low-power sleep modes
Conditions Typ
Max(1)
Symbol
Parameter
Unit
Voltage
scaling
25° 85° 125° 25° 85° 130°
General
fHCLK
C
C
C
C
C
C
64 MHz 1.8 1.9 2.1 1.8 2.1 2.9
56 MHz 1.6 1.7 1.9 1.7 1.9 2.8
48 MHz 1.4 1.5 1.7 1.6 1.7 2.7
32 MHz 1.0 1.1 1.3 1.2 1.3 2.3
24 MHz 0.8 0.9 1.1 1.0 1.1 1.9
16 MHz 0.5 0.6 0.8 0.6 0.7 1.7
16 MHz 0.4 0.5 0.7 0.5 0.6 1.4
Flash memory enabled;
fHCLK = fHSE bypass
(≤16 MHz; PLL
Range 1
Supply
current in disabled),
IDD(Sleep)
mA
Sleep
mode
fHCLK = fPLLRCLK
(>16 MHz; PLL
enabled);
All peripherals disabled
Range 2 8 MHz 0.3 0.3 0.5 0.3 0.5 1.2
2 MHz 0.1 0.2 0.4 0.2 0.4 1.1
2 MHz
1 MHz
60
33
99 265 150 360 1110
75 240 130 330 1010
Flash memory disabled;
PLL disabled;
Supply
current in
Low-power
sleep mode
IDD(LPSleep)
fHCLK = fHSE bypass (> 32 kHz), 500 kHz 25
64 230 125 250 870 µA
55 220 110 235 715
53 215 110 225 645
fHCLK = fLSE bypass (= 32 kHz);
All peripherals disabled
125 kHz 16
32 kHz 14
1. Based on characterization results, not tested in production.
Table 28. Current consumption in Stop 0 mode
Conditions
Typ
Max(1)
Symbol
Parameter
Unit
HSI kernel
VDD
25°C
85°C 125°C 25°C
85°C 130°C
1.8 V
2.4 V
3 V
275
280
280
285
95
305
310
315
315
140
145
145
150
430
435
435
440
270
275
280
285
330
330
350
375
120
125
125
130
425
450
490
500
180
220
240
250
750
850
950
1020
490
610
720
840
Enabled
Supply
current in
Stop 0
3.6 V
1.8 V
2.4 V
3 V
IDD(Stop 0)
µA
mode
100
100
105
Disabled
3.6 V
1. Based on characterization results, not tested in production.
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
Table 29. Current consumption in Stop 1 mode
Conditions
Typ
Max(1)
Symbol
Parameter
Unit
Flash
memory
RTC(2)
VDD
25°C 85°C 125°C 25°C 85°C 130°C
1.8 V
2.4 V
3 V
3.2
3.3
3.4
3.8
3.4
3.7
4.0
4.4
6.9
7.3
7.3
7.8
32
32
33
33
32
32
33
34
36
36
37
38
150
150
155
155
150
155
155
160
155
160
160
160
8
100
120
135
140
100
120
140
145
100
110
120
135
480
535
620
705
480
540
630
720
575
600
645
665
10
15
18
9
Disabled
Enabled
3.6 V
1.8 V
2.4 V
3 V
Not
powered
Supply
current in
Stop 1
11
16
20
12
14
18
23
IDD(Stop 1)
µA
mode
3.6 V
1.8 V
2.4 V
3 V
Powered Disabled
3.6 V
1. Based on characterization results, not tested in production.
2. Clocked by LSI
Table 30. Current consumption in Standby mode
Conditions Typ
General
Max(1)
Symbol
Parameter
Unit
VDD
25°C 85°C 125°C 25°C 85°C 130°C
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
0.07
0.13
0.20
0.34
0.35
0.49
0.66
0.90
0.26
0.37
0.49
0.69
0.70
0.89
1.10
1.30
1.7
2.1
2.5
3.0
2.0
2.4
2.9
3.5
1.9
2.3
2.7
3.3
1.6
2.0
2.4
2.9
6.7
8.1
0.7
0.8
0.9
1.0
0.8
1.0
1.3
2.2
0.8
1.0
1.4
2.1
-
9
12
14
16
10
12
15
18
10
12
15
18
-
34
38
46
55
35
40
47
56
34
39
45
52
-
RTC disabled
10.0
12.0
7.0
8.4
RTC enabled,
clocked by LSI;
10.5
12.5
6.8
Supply current
in Standby
mode(2)
IDD(Standby)
µA
8.3
IWDG enabled,
clocked by LSI
10.3
12.3
6.6
8.0
-
-
-
ULPEN = 0
9.8
-
-
-
11.8
-
-
-
62/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
Table 30. Current consumption in Standby mode (continued)
Conditions Typ
Max(1)
General 25°C 85°C 125°C 25°C 85°C 130°C
Symbol
Parameter
Unit
VDD
1.8 V
2.4 V
3.0 V
3.6 V
0.49
0.57
0.67
0.77
3.0
3.1
3.2
3.3
14.8
14.9
15.0
15.0
0.6
1.1
1.5
1.9
16
17
17
18
58
63
67
71
Extra supply
current to
SRAM retention
enabled
∆IDD(SRAM)
µA
retain SRAM
content(3)
1. Based on characterization results, not tested in production.
2. Without SRAM retention and with ULPEN bit set
3. To be added to IDD(Standby) as appropriate
Table 31. Current consumption in Shutdown mode
Conditions
Typ
Max(1)
Symbol
Parameter
Unit
RTC
VDD
25 °C 85 °C 125 °C 25 °C 85 °C 130 °C
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
17
23
515
600
730
940
710
890
4500
5150
250
450
3000 32600
3500 33600
Disabled
33
6450 1075 4250 37400
7700 1250 5300 43600
Supply current
in Shutdown
mode
53
IDD(Shutdown)
nA
205
300
420
565
4700
900
4500 27300
Enabled, clocked
by LSE bypass at
32.768 kHz
5500 1550 5500 34800
1150 6800 2475 6000 40900
1450 8100 3250 7000 48500
1. Based on characterization results, not tested in production.
Table 32. Current consumption in VBAT mode
Conditions
Typ
Symbol
Parameter
Unit
RTC
VDD
25°C
85°C
125°C
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
165
260
365
505
290
370
470
600
1
170
355
475
655
390
480
600
815
80
620
970
Enabled, clocked by
LSE bypass at
32.768 kHz
1200
2070
960
Enabled, clocked by
LSE crystal at
32.768 kHz
1150
1650
2250
660
Supply current in
VBAT mode
IDD(VBAT)
nA
2
90
750
Disabled
2
105
200
1200
1700
6
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 51: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 33: Current consumption of peripherals, the I/Os used by an application also
contribute to the current consumption. When an I/O pin switches, it uses the current from
the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive
load (internal or external) connected to the pin:
ISW = VDDIO1 × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the I/O supply voltage
DDIO1
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
+ C
S
INT
EXT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
64/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
•
•
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
–
–
when the peripheral is clocked on
when the peripheral is clocked off
•
•
Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in the
following table. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 33. Current consumption of peripherals
Consumption in µA/MHz
Peripheral
Bus
Low-power run
and sleep
Range 1
Range 2
IOPORT Bus
IOPORT
IOPORT
IOPORT
IOPORT
IOPORT
IOPORT
AHB
1.0
3.4
3.1
2.9
1.8
0.7
3.2
15.0
4.7
0.5
4.1
46.5
0.2
0.4
0.4
0.4
7.3
4.7
3.6
0.7
0.7
1.5
4.0
2.3
0.7
2.8
2.6
2.5
1.5
0.6
2.2
12.5
3.8
0.4
3.5
47.5
0.2
0.3
0.4
0.3
6.1
3.8
3.0
0.6
0.7
1.2
3.3
2.0
0.5
3.0
2.5
3.0
1.5
1.0
2.8
14.0
4.5
0.5
4.0
48.0
0.1
0.5
0.3
0.5
6.5
5.0
2.5
0.5
1.0
1.5
3.0
2.0
GPIOA
GPIOB
GPIOC
GPIOD
GPIOF
Bus matrix
All AHB Peripherals
DMA1/DMAMUX
CRC
AHB
AHB
AHB
FLASH
AHB
All APB peripherals
AHB to APB bridge(1)
PWR
APB
APB
APB
SYSCFG/VREFBUF/COMP
WWDG
APB
APB
TIM1
APB
TIM2
APB
TIM3
APB
TIM6
APB
TIM7
APB
TIM14
APB
TIM15
APB
TIM16
APB
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
Table 33. Current consumption of peripherals (continued)
Consumption in µA/MHz
Peripheral
Bus
Low-power run
and sleep
Range 1
Range 2
TIM17
LPTIM1
LPTIM2
I2C1
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
0.7
3.2
3.1
3.8
0.7
1.5
7.2
7.2
2.0
2.0
4.3
0.4
4.0
4.0
2.0
2.2
0.7
2.7
2.5
3.1
0.6
1.2
6.0
6.0
1.7
1.7
3.5
0.3
7.7
7.7
1.7
1.8
0.5
3.0
3.0
3.5
I2C2
1.0
SPI2
1.0
USART1
USART2
USART3
USART4
LPUART1
CEC
6.5
6.0
2.0
2.0
4.0
0.5
UCPD1
UCPD2
ADC
NA(2)
NA(2)
2.0
DAC
2.0
1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.
2. UCPDx are always clocked by HSI16.
5.3.6
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 34 are the latency between the event and the execution of
the first user instruction.
(1)
Table 34. Low-power mode wakeup times
Symbol
Parameter
Conditions
Typ Max
Unit
Wakeup time from
tWUSLEEP Sleep to Run
mode
-
11
11
11
14
CPU
cycles
Transiting to Low-power-run-mode execution in Flash
memory not powered in Low-power sleep mode;
Wakeup time from
tWULPSLEEP Low-power sleep
mode
HCLK = HSI16 / 8 = 2 MHz
66/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
(1)
Table 34. Low-power mode wakeup times (continued)
Conditions
Symbol
Parameter
Typ Max
Unit
Transiting to Run-mode execution in Flash memory not
powered in Stop 0 mode;
5.6
2
6
HCLK = HSI16 = 16 MHz;
Regulator in Range 1 or Range 2
Wakeup time from
Stop 0
tWUSTOP0
µs
Transiting to Run-mode execution in SRAM or in Flash
memory powered in Stop 0 mode;
2.4
HCLK = HSI16 = 16 MHz;
Regulator in Range 1 or Range 2
Transiting to Run-mode execution in Flash memory not
powered in Stop 1 mode;
9.0
5
11.2
7.5
HCLK = HSI16 = 16 MHz;
Regulator in Range 1 or Range 2
Transiting to Run-mode execution in SRAM or in Flash
memory powered in Stop 1 mode;
HCLK = HSI16 = 16 MHz;
Regulator in Range 1 or Range 2
Wakeup time from
Stop 1
tWUSTOP1
µs
Transiting to Low-power-run-mode execution in Flash
memory not powered in Stop 1 mode;
22
25.3
HCLK = HSI16/8 = 2 MHz;
Regulator in low-power mode (LPR = 1 in PWR_CR1)
Transiting to Low-power-run-mode execution in SRAM or
in Flash memory powered in Stop 1 mode;
18
23.5
30
HCLK = HSI16 / 8 = 2 MHz;
Regulator in low-power mode (LPR = 1 in PWR_CR1)
Transiting to Run mode;
HCLK = HSI16 = 16 MHz;
Regulator in Range 1
Wakeup time from
Standby mode
tWUSTBY
14.5
µs
Transiting to Run mode;
HCLK = HSI16 = 16 MHz;
Regulator in Range 1
Wakeup time from
Shutdown mode
tWUSHDN
258
5
340
7
µs
µs
Wakeup time from
Transiting to Run mode;
tWULPRUN Low-power run
HSISYS = HSI16/8 = 2 MHz
mode(2)
1. Based on characterization results, not tested in production.
2. Time until REGLPF flag is cleared in PWR_SR2.
(1)
Table 35. Regulator mode transition times
Symbol
Parameter
Conditions
Typ
20
Max
40
Unit
Transition times between regulator
Range 1 and Range 2(2)
tVOST
HSISYS = HSI16
µs
1. Based on characterization results, not tested in production.
2. Time until VOSF flag is cleared in PWR_SR2.
DS12232 Rev 3
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106
Electrical characteristics
Symbol
STM32G071x8/xB
(1)
Table 36. Wakeup time using LPUART
Parameter Conditions
Typ
Max
1.7
Unit
Stop mode 0
-
-
Wakeup time needed to calculate the maximum
tWULPUART LPUART baud rate allowing to wakeup up from Stop
mode when LPUART clock source is HSI16
µs
Stop mode 1
8.5
1. Guaranteed by design.
5.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. See
Figure 16 for recommended clock input waveform.
(1)
Table 37. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Voltage scaling
Range 1
-
8
48
fHSE_ext User external clock source frequency
MHz
Voltage scaling
Range 2
-
8
26
VHSEH OSC_IN input pin high level voltage
VHSEL OSC_IN input pin low level voltage
-
-
0.7 VDDIO1
VSS
-
-
VDDIO1
V
0.3 VDDIO1
Voltage scaling
Range 1
7
-
-
-
-
tw(HSEH)
OSC_IN high or low time
tw(HSEL)
ns
Voltage scaling
Range 2
18
1. Guaranteed by design.
Figure 16. High-speed external clock source AC timing diagram
t
w(HSEH)
V
HSEH
90%
10%
V
HSEL
t
t
t
t
r(HSE)
f(HSE)
w(HSEL)
T
HSE
MS19214V2
68/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. See
Figure 17 for recommended clock input waveform.
(1)
Table 38. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
-
-
-
32.768
1000
VDDIO1
kHz
0.7 VDDIO1
VSS
-
-
V
0.3 VDDIO1
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
-
250
-
-
ns
1. Guaranteed by design.
Figure 17. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
90%
10%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
(1)
Table 39. HSE oscillator characteristics
Symbol
Parameter
Oscillator frequency
Feedback resistor
Conditions(2)
Min
Typ
Max
Unit
fOSC_IN
RF
-
-
4
-
8
48
-
MHz
200
kΩ
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Electrical characteristics
STM32G071x8/xB
(1)
Table 39. HSE oscillator characteristics (continued)
Symbol
Parameter
Conditions(2)
During startup(3)
DD = 3 V,
Min
Typ
Max
Unit
-
-
5.5
V
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
-
-
-
-
0.44
0.45
0.68
0.94
1.77
-
-
-
-
-
VDD = 3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
VDD = 3 V,
IDD(HSE)
HSE current consumption
mA
Rm = 30 Ω,
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 20 pF@48 MHz
Maximum critical crystal
transconductance
Gm
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 18). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
70/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
Figure 18. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
fHSE
Bias
controlled
gain
8 MHz
resonator
RF
(1)
OSC_OUT
REXT
CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 40. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
(1)
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(2)
Min
Typ
Max Unit
LSEDRV[1:0] = 00
Low drive capability
-
250
-
LSEDRV[1:0] = 01
Medium low drive capability
-
-
-
-
-
-
315
-
IDD(LSE) LSE current consumption
nA
LSEDRV[1:0] = 10
Medium high drive capability
500
-
LSEDRV[1:0] = 11
High drive capability
630
-
LSEDRV[1:0] = 00
Low drive capability
-
-
-
0.5
LSEDRV[1:0] = 01
Medium low drive capability
0.75
µA/V
1.7
Maximum critical crystal
Gmcritmax
gm
LSEDRV[1:0] = 10
Medium high drive capability
LSEDRV[1:0] = 11
High drive capability
-
-
-
2.7
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
-
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 19. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
5.3.8
Internal clock source characteristics
The parameters given in Table 41 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
(1)
Table 41. HSI16 oscillator characteristics
Symbol
Parameter
HSI16 Frequency
Conditions
Min
Typ
Max
Unit
fHSI16
VDD=3.0 V, TA=30 °C
TA= 0 to 85 °C
15.88
-1
-
-
-
16.08
1
MHz
%
HSI16 oscillator frequency drift over
temperature
∆
Temp(HSI16)
TA= -40 to 125 °C
-2
1.5
%
%
HSI16 oscillator frequency drift over
VDD
∆
VDD=1.62 V to 3.6 V
-0.1
-8
-
0.05
-4
VDD(HSI16)
From code 127 to 128
From code 63 to 64
-6
-5.8
-3.8
-1.8
TRIM
HSI16 frequency user trimming step From code 191 to 192
%
For all other code
increments
0.2
0.3
0.4
(2)
DHSI16
Duty Cycle
-
-
45
-
-
55
%
(2)
tsu(HSI16)
HSI16 oscillator start-up time
0.8
1.2
μs
72/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
(1)
Table 41. HSI16 oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(2)
tstab(HSI16)
HSI16 oscillator stabilization time
HSI16 oscillator power consumption
-
-
-
-
3
5
μs
(2)
IDD(HSI16)
155
190
μA
1. Based on characterization results, not tested in production.
2. Guaranteed by design.
Figure 20. HSI16 frequency vs. temperature
MHz
16.4
+2%
+1.5%
+1%
16.3
16.2
16.1
16
15.9
15.8
15.7
15.6
-1%
-1.5%
-2%
-40
-20
0
20
40
mean
60
80
100
120 °C
min
max
MSv39299V1
Low-speed internal (LSI) RC oscillator
(1)
Table 42. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
VDD = 3.0 V, TA = 30 °C
31.04
29.5
-
-
32.96
34
fLSI
LSI frequency
kHz
VDD = 1.62 V to 3.6 V, TA = -40 to
125 °C
(2)
tSU(LSI)
LSI oscillator start-up time
-
-
-
80
130
180
μs
μs
(2)
tSTAB(LSI)
LSI oscillator stabilization time 5% of final frequency
125
LSI oscillator power
consumption
(2)
IDD(LSI)
-
-
110
180
nA
1. Based on characterization results, not tested in production.
2. Guaranteed by design.
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
5.3.9
PLL characteristics
The parameters given in Table 43 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 21: General operating conditions.
DD
(1)
Table 43. PLL characteristics
Symbol
Parameter
Conditions
Min
2.66
45
Typ Max Unit
fPLL_IN
PLL input clock frequency(2)
PLL input clock duty cycle
-
-
-
-
16
55
MHz
%
DPLL_IN
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
-
3.09
3.09
12
12
12
12
96
96
-
-
-
122
40
128
33
64
16
344
128
40
-
fPLL_P_OUT PLL multiplier output clock P
fPLL_Q_OUT PLL multiplier output clock Q
fPLL_R_OUT PLL multiplier output clock R
fVCO_OUT PLL VCO output
MHz
MHz
MHz
-
-
-
-
-
MHz
μs
-
tLOCK
Jitter
PLL lock time
15
50
40
RMS cycle-to-cycle jitter
RMS period jitter
-
System clock 56 MHz
±ps
-
-
VCO freq = 96 MHz
VCO freq = 192 MHz
VCO freq = 344 MHz
-
200 260
300 380
520 650
PLL power consumption
on VDD
IDD(PLL)
-
μA
(1)
-
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the two PLLs.
5.3.10
Flash memory characteristics
(1)
Table 44. Flash memory characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
tprog
64-bit programming time
-
85
2.7
125
4.6
µs
Normal programming
Fast programming
Normal programming
Fast programming
-
tprog_row
Row (32 double word) programming time
1.7
2.8
21.8
13.7
22.0
1.4
36.6
22.4
40.0
2.4
ms
tprog_page Page (2 Kbyte) programming time
tERASE Page (2 Kbyte) erase time
tprog_bank Bank (128 Kbyte(2)) programming time
tME Mass erase time
Normal programming
Fast programming
-
s
0.9
1.4
22.1
40.1
ms
74/133
DS12232 Rev 3
STM32G071x8/xB
Symbol
Electrical characteristics
(1)
Table 44. Flash memory characteristics (continued)
Parameter Conditions
Programming
Typ
Max
Unit
3
3
3
-
-
-
IDD(FlashA) Average consumption from VDD
Page erase
Mass erase
mA
Programming, 2 µs peak
duration
7
7
-
-
IDD(FlashP) Maximum current (peak)
1. Guaranteed by design.
mA
Erase, 41 µs peak duration
2. Values provided also apply to devices with less Flash memory than one 128 Kbyte bank
Table 45. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Conditions
Min(1)
Unit
NEND
TA = -40 to +105 °C
10
30
15
7
kcycles
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
1 kcycle(2) at TA = 125 °C
10 kcycles(2) at TA = 55 °C
10 kcycles(2) at TA = 85 °C
10 kcycles(2) at TA = 105 °C
tRET
Data retention
Years
30
15
10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
5.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 46. They are based on the EMS levels and classes
defined in application note AN1709.
DS12232 Rev 3
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106
Electrical characteristics
Symbol
STM32G071x8/xB
Table 46. EMS characteristics
Parameter
Level/
Class
Conditions
VDD = 3.3 V, TA = +25 °C,
fHCLK = 64 MHz, LQFP64,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
5A
Fast transient voltage burst limits to be applied
VDD = 3.3 V, TA = +25 °C,
through 100 pF on VDD and VSS pins to induce a fHCLK = 64 MHz, LQFP64,
functional disturbance conforming to IEC 61000-4-4
VEFTB
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
corrupted program counter
unexpected reset
critical data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
76/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
Max vs.
Table 47. EMI characteristics
[fHSE/fHCLK
]
Monitored
frequency band
Symbol
Parameter
Conditions
Unit
8 MHz / 64 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI level
7
-1
8
VDD = 3.6 V, TA = 25 °C,
Peak level LQFP64 package
compliant with IEC 61967-2
dBµV
-
SEMI
7
2.5
5.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 48. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge voltage
(human body model)
TA = +25 °C, conforming to
ANSI/ESDA/JEDEC JS-001
VESD(HBM)
VESD(CDM)
2
2000
V
Electrostatic discharge voltage
(charge device model)
TA = +25 °C, conforming to
ANSI/ESDA/JEDEC JS-002
C2a
500
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current is injected to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 49. Electrical sensitivity
Symbol
Parameter
Conditions
Class
II Level A
LU
Static latch-up class
TA = +125 °C conforming to JESD78
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
5.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V
(for standard, 3.3 V-capable I/O pins) should be avoided during normal
DDIO1
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter: ADC error above a certain limit
(higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional
limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
(1)
Table 50. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
All except PA4, PA5, PA6, PB0,
PB3, and PC0
-5
N/A
mA
Injected current on
pin
IINJ
PA4, PA5
-5
0
0
mA
mA
PA6, PB0, PB3, and PC0
N/A
1. Based on characterization results, not tested in production.
78/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
5.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 51. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.3 x VDDIO1
(2)
All
except 1.62 V < VDDIO1 < 3.6 V
FT_c
-
-
0.39 x VDDIO1
- 0.06 (3)
I/O input low level
voltage
(1)
VIL
V
2 V < VDDIO1 < 2.7 V
FT_c
-
-
-
-
0.3 x VDDIO1
0.25 x VDDIO1
1.62 V < VDDIO1 < 2.7 V
(
0.7 x VDDIO1
-
-
2)
All
except 1.62 V < VDDIO1 < 3.6 V
FT_c
I/O input high level
voltage
(1)
VIH
0.49 x VDDIO1
+ 0.26(3)
V
-
-
-
FT_c
1.62 V < VDDIO1 < 3.6 V
0.7 x VDDIO1
5
TT_xx,
(3)
Vhys
I/O input hysteresis FT_xx, 1.62 V < VDDIO1 < 3.6 V
NRST
-
200
-
mV
0 < VIN ≤ VDDIO1
-
-
-
-
±70
FT_xx
except
FT_c
and
VDDIO1 ≤ VIN ≤ VDDIO1+1 V
600(4)
VDDIO1 +1 V < VIN
5.5 V(3)
≤
-
-
150(4)
FT_d
0 < VIN ≤ VDDIO1
VDDIO1 < VIN ≤ 5 V
0 < VIN ≤ VDDIO1
-
-
-
-
-
-
-
-
-
-
2000
3000(4)
4500
FT_c
FT_d
Input leakage
current(3)
Ilkg
nA
VDDIO1 < VIN ≤ 5.5 V
0 < VIN ≤ VDDIO1
9000(4)
±150
TT_a
V
DDIO1 < VIN
≤
-
-
2000(4)
55
VDDIO1 + 0.3 V
Weak pull-up
RPU
equivalent resistor
VIN = VSS
25
40
kΩ
(5)
Weak pull-down
RPD
CIO
VIN = VDDIO1
25
-
40
5
55
-
kΩ
equivalent resistor(5)
I/O pin capacitance
-
pF
1. Refer to Figure 21: I/O input characteristics.
2. Tested in production.
3. Guaranteed by design.
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 21.
Figure 21. I/O input characteristics
3
2.5
Minimum required
logic level 1 zone
TTL standard requirement
2
VIN (V)
1.5
Undefined input range
1
TTL standard requirement
0.5
Minimum required
logic level 0 zone
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VDDIO (V)
Device characteristics
Test thresholds
MSv47925V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±6 mA, and up to
±15 mA with relaxed V /V
.
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum
DDIO1,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 18: Voltage characteristics).
VDD
•
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating I
(see Table 18:
SS
VSS
Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
80/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
(1)
Table 52. Output voltage characteristics
Symbol
Parameter
Conditions
CMOS port(2)
Min
Max
Unit
VOL
Output low level voltage for an I/O pin
-
0.4
|IIO| = 2 mA for FT_c I/Os
= 6 mA for other I/Os
VDDIO1 ≥ 2.7 V
VOH
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
VDDIO1 - 0.4
-
0.4
-
(3)
VOL
TTL port(2)
|IIO| = 2 mA for FT_c I/Os
= 6 mA for other I/Os
VDDIO1 ≥ 2.7 V
-
(3)
VOH
2.4
(3)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
All I/Os except FT_c
|IIO| = 15 mA
VDDIO1 ≥ 2.7 V
-
1.3
-
V
(3)
VOH
VDDIO1 - 1.3
-
(3)
VOL
|IIO| = 1 mA for FT_c I/Os
= 3 mA for other I/Os
VDDIO1 ≥ 1.62 V
0.4
-
(3)
VOH
VDDIO1 - 0.45
|IIO| = 20 mA
VDDIO1 ≥ 2.7 V
-
-
0.4
0.4
VOLFM+ Output low level voltage for an FT I/O
(3)
pin in FM+ mode (FT I/O with _f option)
|IIO| = 9 mA
VDDIO1 ≥ 1.62 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and
Table 53, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
(1)(2)
Table 53. I/O AC characteristics
Speed Symbol
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
2
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
-
-
-
-
-
-
0.35
3
Fmax Maximum frequency
MHz
0.45
100
225
75
00
Tr/Tf Output rise and fall time
ns
150
DS12232 Rev 3
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106
Electrical characteristics
Speed Symbol
STM32G071x8/xB
(1)(2)
Table 53. I/O AC characteristics
(continued)
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
-
10
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V
C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
15
2.5
30
60
15
30
30
15
60
30
11
22
4
Fmax Maximum frequency
Tr/Tf Output rise and fall time
Fmax Maximum frequency
Tr/Tf Output rise and fall time
Fmax Maximum frequency
MHz
01
ns
MHz
ns
10
8
60
30
80(3)
40
5.5
11
2.5
5
MHz
ns
11
Tr/Tf Output rise and fall time
Fmax Maximum frequency
1
MHz
ns
Fm+
C=50 pF, 1.6 V ≤ VDDIO1 ≤ 3.6 V
Tf
Output fall time(4)
5
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0444 reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.
4. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.
82/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
(1)
Figure 22. I/O AC characteristics definition
10%
90%
50%
50%
10%
90%
t
t
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 53: I/O AC characteristics.
5.3.15
NRST input characteristics
The NRST input driver uses CMOS technology. It is connected to a permanent
pull-up resistor, R
.
PU
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 21: General operating conditions.
(1)
Table 54. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST input low level
voltage
VIL(NRST)
VIH(NRST)
Vhys(NRST)
RPU
-
-
-
0.3 x VDDIO1
V
NRST input high level
voltage
-
0.7 x VDDIO1
-
200
40
-
-
-
NRST Schmitt trigger
voltage hysteresis
-
-
25
-
mV
kΩ
ns
Weak pull-up
VIN = VSS
55
70
-
equivalent resistor(2)
NRST input filtered
pulse
VF(NRST)
VNF(NRST)
-
NRST input not filtered
pulse
1.7 V ≤ VDD ≤ 3.6 V
350
-
ns
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
Figure 23. Recommended NRST pin protection
External
reset circuit(1)
VDD
RPU
NRST(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 54: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.16
Analog switch booster
(1)
Table 55. Analog switch booster characteristics
Symbol
Parameter
Supply voltage
Min
Typ
Max
Unit
VDD
1.62 V
-
-
-
3.6
V
tSU(BOOST)
Booster startup time
240
µs
Booster consumption for
1.62 V ≤ VDD ≤ 2.0 V
-
-
-
-
-
-
250
500
900
Booster consumption for
2.0 V ≤ VDD ≤ 2.7 V
IDD(BOOST)
µA
Booster consumption for
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.
5.3.17
Analog-to-digital converter characteristics
Unless otherwise specified, the parameters given in Table 56 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK
DDA
conditions summarized in Table 21: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
(1)
Table 56. ADC characteristics
Symbol
Parameter
Conditions(2)
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
1.62
2
-
-
3.6
V
VDDA ≥ 2 V
VDDA < 2 V
VDDA
Positive reference
voltage
VREF+
V
VDDA
84/133
DS12232 Rev 3
STM32G071x8/xB
Symbol
Electrical characteristics
(1)
Table 56. ADC characteristics
(continued)
Parameter
Conditions(2)
Min
Typ
Max
Unit
Range 1
Range 2
12 bits
10 bits
8 bits
0.14
-
-
-
-
-
-
-
-
35
16
fADC
ADC clock frequency
MHz
0.14
-
-
-
-
-
-
2.50
2.92
3.50
4.38
2.33
fADC/15
fs
Sampling rate
MSps
MHz
6 bits
fADC = 35 MHz; 12 bits
12 bits
External trigger
frequency
fTRIG
Conversion voltage
range
(3)
VAIN
-
-
-
-
VSSA
-
-
VREF+
V
External input
impedance
RAIN
CADC
tSTAB
-
-
50
-
kΩ
pF
Internal sample and
hold capacitor
5
2
Conversion
cycle
ADC power-up time
Calibration time
f
ADC = 35 MHz
-
2.35
82
-
µs
tCAL
1/fADC
1/fADC
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
2
3
6.5
12.5
3.5
-
Trigger conversion
latency
tLATR
1/fPCLK
0.043
1.5
4.59
160.5
4.59
µs
fADC = 35 MHz;
VDDA > 2V
-
1/fADC
µs
ts
Sampling time
0.1
-
fADC = 35 MHz;
VDDA < 2V
3.5
160.5
1/fADC
ADC voltage regulator
start-up time
-
-
-
-
20
tADCVREG_STUP
µs
fADC = 35 MHz
Resolution = 12 bits
0.40
4.95
µs
Total conversion time
(including sampling
time)
tCONV
ts + 12.5 cycles for successive
approximation
Resolution = 12 bits
1/fADC
= 14 to 173
Laps of time allowed
between two
conversions without
rearm
-
-
-
100
µs
t
IDLE
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
(1)
Table 56. ADC characteristics
Conditions(2)
(continued)
Symbol
Parameter
Min
Typ
Max
Unit
fs = 2.5 MSps
-
-
-
-
-
-
410
164
17
-
-
-
-
-
-
ADC consumption
from VDDA
IDDA(ADC)
fs = 1 MSps
fs = 10 kSps
fs = 2.5 MSps
fs = 1 MSps
fs = 10 kSps
µA
65
ADC consumption
from VREF+
IDDV(ADC)
26
µA
0.26
1. Guaranteed by design
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
3. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate
functions for further details.
Table 57. Maximum ADC R
.
AIN
(1)(2)
Sampling time at 35 MHz
[ns]
Max. RAIN
Resolution
Sampling cycle at 35 MHz
(Ω)
1.5(3)
3.5
43
100
214
357
557
1129
2271
4586
43
50
680
7.5
2200
4700
8200
15000
33000
50000
68
12.5
19.5
39.5
79.5
160.5
1.5(3)
3.5
12 bits
100
214
357
557
1129
2271
4586
820
7.5
3300
5600
10000
22000
39000
50000
12.5
19.5
39.5
79.5
160.5
10 bits
86/133
DS12232 Rev 3
STM32G071x8/xB
Resolution
Electrical characteristics
Table 57. Maximum ADC R
. (continued)
AIN
(1)(2)
Sampling time at 35 MHz
[ns]
Max. RAIN
Sampling cycle at 35 MHz
(Ω)
1.5(3)
3.5
43
100
214
357
557
1129
2271
4586
43
82
1500
7.5
3900
12.5
19.5
39.5
79.5
160.5
1.5(3)
3.5
6800
8 bits
12000
27000
50000
50000
390
100
214
357
557
1129
2271
4586
2200
7.5
5600
12.5
19.5
39.5
79.5
160.5
10000
15000
33000
50000
50000
6 bits
1. Guaranteed by design.
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
3. Only allowed with VDDA > 2 V
(1)(2)(3)
Table 58. ADC accuracy
Symbol
Parameter
Conditions(4)
Min
Typ
Max
Unit
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
-
3
4
TA = 25 °C
2 V < VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
Total
unadjusted
error
-
-
3
3
6.5
7.5
ET
LSB
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
(1)(2)(3)
Table 58. ADC accuracy
Conditions(4)
DDA = VREF+ = 3 V;
(continued)
Symbol
Parameter
Min
Typ
Max
Unit
V
fADC = 35 MHz; fs ≤ 2.5 MSps;
-
1.5
2
TA = 25 °C
2 V < VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
-
-
1.5
1.5
4.5
5.5
EO
Offset error
LSB
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = 25 °C
-
-
3
3
3.5
5
2 V < VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
EG
ED
EL
Gain error
LSB
LSB
LSB
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
-
3
6.5
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = 25 °C
-
-
1.2
1.2
1.5
1.5
2 V < VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
Differential
linearity error TA = entire range
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
-
1.2
1.5
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
-
-
2.5
2.5
3
3
TA = 25 °C
2 V < VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
Integral
linearity error TA = entire range
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
-
2.5
3.5
88/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
(1)(2)(3)
Table 58. ADC accuracy
Conditions(4)
DDA = VREF+ = 3 V;
(continued)
Symbol
Parameter
Min
Typ
Max
Unit
V
fADC = 35 MHz; fs ≤ 2.5 MSps;
10.1
10.2
-
TA = 25 °C
2 V < VDDA=VREF+ < 3.6 V;
Effective
number of bits TA = entire range
fADC = 35 MHz; fs ≤ 2.5 MSps;
9.6
9.5
10.2
10.2
-
-
ENOB
bit
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = 25 °C
62.5
59.5
63
63
-
-
2 V < VDDA=VREF+ < 3.6 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = entire range
Signal-to-noise
and distortion
ratio
dB
dB
dB
SINAD
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
59
63
-
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
TA = 25 °C
63
60
64
64
-
-
2 V < VDDA=VREF+ < 3.6 V;
Signal-to-noise fADC = 35 MHz; fs ≤ 2.5 MSps;
SNR
ratio
TA = entire range
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
60
64
-
VDDA = VREF+ = 3 V;
fADC = 35 MHz; fs ≤ 2.5 MSps;
-
-
-74
-74
-73
-70
TA = 25 °C
2 V < VDDA=VREF+ < 3.6 V;
Total harmonic fADC = 35 MHz; fs ≤ 2.5 MSps;
THD
distortion
TA = entire range
1.65 V < VDDA=VREF+ < 3.6 V;
TA = entire range
Range 1: fADC = 35 MHz; fs ≤ 2.2 MSps;
Range 2: fADC = 16 MHz; fs ≤ 1.1 MSps;
-
-74
-70
1. Based on characterization results, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on
another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive
negative current.
4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled
when VDDA ≥ 2.4 V.
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
Figure 24. ADC accuracy characteristics
EG
Code
4095
(1) Example of an actual transfer curve
(2) Ideal transfer curve
4094
(3) End point correlation line
4093
ET
total unadjusted error: maximum deviation
between the actual and ideal transfer curves.
(2)
ET
EO
offset error: maximum deviation between the
(3)
7
6
first actual transition and the first ideal one.
(1)
EG gain error: deviation between the last ideal
transition and the last actual one.
5
EL
EO
ED
differential linearity error: maximum deviation
between actual steps and the ideal ones.
4
3
2
1
ED
EL integral linearity error: maximum deviation between
any actual transition and the end point correlation line.
1 LSB ideal
0
1
2
3
4
5
6
7
4093 4094 4095
(VAIN / VREF+)*4095
MSv19880V3
Figure 25. Typical connection diagram using the ADC
VDDA
VT
Sample and hold ADC converter
(1)
RAIN
RADC
AINx
12-bit
converter
(2)
(3)
Cparasitic
CADC
VT
Ilkg
VAIN
MS33900V5
1. Refer to Table 56: ADC characteristics for the values of RAIN and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 51: I/O static characteristics for the value of the pad capacitance). A high
C
parasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 51: I/O static characteristics for the values of Ilkg.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 13: Power supply
scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
90/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
5.3.18
Digital-to-analog converter characteristics
(1)
Table 59. DAC characteristics
Conditions
Symbol
Parameter
Min
1.71
1.80
1.71
1.80
Typ
Max
Unit
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
-
-
-
-
Analog supply voltage for
DAC ON
VDDA
3.6
V
Other modes
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
VREF+
Positive reference voltage
VDDA
V
Other modes
connected to VSSA
DAC output
5
25
9.6
-
-
-
-
RL
Resistive load
kΩ
kΩ
buffer ON
connected to VDDA
-
11.7
-
RO
Output Impedance
DAC output buffer OFF
13.8
2
Output impedance sample VDD = 2.7 V
and hold mode, output
RBON
kΩ
kΩ
VDD = 2.0 V
-
-
-
-
-
-
3.5
buffer ON
Output impedance sample VDD = 2.7 V
and hold mode, output
16.5
18.0
RBOFF
VDD = 2.0 V
buffer OFF
CL
DAC output buffer ON
Sample and hold mode
-
-
-
50
1
pF
µF
Capacitive load
CSH
0.1
VREF+
– 0.2
DAC output buffer ON
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
DAC output buffer OFF
±0.5 LSB
0
-
-
VREF+
3
1.7
Normal mode
DAC output
buffer ON
CL ≤ 50 pF,
RL ≥ 5 kΩ
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
±1 LSB
-
1.6
2.9
±2 LSB
±4 LSB
±8 LSB
-
1.55
1.48
1.4
2.85
2.8
tSETTLING highest input codes when
DAC_OUT reaches final
µs
-
-
2.75
value ±0.5LSB, ±1 LSB,
±2 LSB, ±4 LSB, ±8 LSB)
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF
-
-
-
-
2
2.5
7.5
5
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Wakeup time from off state
4.2
2
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
(2)
tWAKEUP
µs
Normal mode DAC output buffer
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL = 5 kΩ, DC
PSRR
VDDA supply rejection ratio
-80
-28
dB
DS12232 Rev 3
91/133
106
Electrical characteristics
STM32G071x8/xB
(1)
Table 59. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Minimum time between two DAC_MCR:MODEx[2:0] = 000 or
consecutive writes into the 001
1
-
-
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
variation of the input code
(1 LSB)
CL ≤ 50 pF; RL ≥ 5 kΩ
TW_to_W
µs
DAC_MCR:MODEx[2:0] = 010 or
011
CL ≤ 10 pF
1.4
-
-
DAC output buffer
ON, CSH = 100 nF
-
-
0.7
3.5
18
DAC_OUT
pin connected
ms
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
DAC output buffer
OFF, CSH = 100 nF
10.5
tSAMP
DAC_OUT
pin not
connected
(internal
connection
only)
DAC output buffer
OFF
-
2
3.5
µs
Sample and hold mode,
DAC_OUT pin connected
(3)
Ileak
Output leakage current
-
-
-
nA
Internal sample and hold
capacitor
CIint
-
5.2
7
8.8
pF
µs
tTRIM
Middle code offset trim time DAC output buffer ON
50
-
-
-
-
-
VREF+ = 3.6 V
1500
750
Middle code offset for 1 trim
code step
Voffset
µV
µA
VREF+ = 1.8 V
-
No load, middle
code (0x800)
-
-
-
315
450
500
670
DAC output
buffer ON
No load, worst code
(0xF1C)
DAC consumption from
VDDA
IDDA(DAC)
DAC output
buffer OFF
No load, middle
code (0x800)
-
0.2
315 ₓ
670 ₓ
Sample and hold mode, CSH
100 nF
=
-
Ton/(Ton+ Ton/(Ton+
Toff)(4) Toff)(4)
92/133
DS12232 Rev 3
STM32G071x8/xB
Symbol
Electrical characteristics
(1)
Table 59. DAC characteristics (continued)
Parameter Conditions Min
No load, middle
Typ
Max
Unit
-
-
-
185
240
code (0x800)
DAC output
buffer ON
No load, worst code
(0xF1C)
340
400
DAC output
buffer OFF
No load, middle
code (0x800)
155
205
DAC consumption from
VREF+
IDDV(DAC)
µA
185 ₓ
400 ₓ
Sample and hold mode, buffer ON,
CSH = 100 nF, worst case
-
-
Ton/(Ton+ Ton/(Ton+
Toff)(4)
Toff)(4)
155 ₓ
205 ₓ
Sample and hold mode, buffer OFF,
CSH = 100 nF, worst case
Ton/(Ton+ Ton/(Ton+
Toff)(4) Toff)(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 51: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0444 reference manual for more details.
Figure 26. 12-bit buffered / non-buffered DAC
Buffered / non-buffered DAC
Buffer(1)
RLOAD
DAC_OUTx
12-bit
digital-to-analog
converter
CLOAD
MSv47959V1
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DS12232 Rev 3
93/133
106
Electrical characteristics
STM32G071x8/xB
.
(1)
Table 60. DAC accuracy
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
DAC output buffer ON
-
-
-
±2
±2
Differential non
linearity (2)
DNL
-
DAC output buffer OFF
10 bits
-
monotonicity
guaranteed
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±4
±4
Integral non
linearity(3)
INL
DAC output buffer OFF
CL ≤ 50 pF, no RL
VREF+ = 3.6 V
VREF+ = 1.8 V
±12
±25
±8
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
LSB
Offset error at
code 0x800(3)
Offset
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset error at
code 0x001(4)
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset1
±5
VREF+ = 3.6 V
VREF+ = 1.8 V
±5
Offset Error at
OffsetCal code 0x800
after calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±7
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±0.5
±0.5
±30
±12
Gain
Gain error(5)
%
DAC output buffer OFF
CL ≤ 50 pF, no RL
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Total
TUE
unadjusted
error
LSB
LSB
DAC output buffer OFF
CL ≤ 50 pF, no RL
Total
unadjusted
error after
calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
TUECal
-
-
±23
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
1 kHz, BW 500 kHz
-
-
71.2
71.6
-
-
Signal-to-noise
ratio
SNR
THD
dB
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
BW 500 kHz
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
-
-
-78
-79
-
-
Total harmonic
distortion
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
94/133
DS12232 Rev 3
STM32G071x8/xB
Electrical characteristics
(1)
Table 60. DAC accuracy (continued)
Conditions Min
DAC output buffer ON
Symbol
Parameter
Typ
Max
Unit
-
-
-
-
70.4
-
Signal-to-noise
and distortion
ratio
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
71
-
-
-
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
11.4
11.5
Effective
number of bits
ENOB
bits
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
5.3.19
Voltage reference buffer characteristics
(1)
Table 61. VREFBUF characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRS = 0
2.4
2.8
-
-
-
-
3.6
3.6
2.4
2.8
Normal mode
VRS = 1
VRS = 0
Analog supply
voltage
VDDA
1.65
Degraded mode(2)
Normal mode
VRS = 1
1.65
V
VRS = 0
VRS = 1
VRS = 0
VRS = 1
2.046(3)
2.498(3)
VDDA-150 mV
VDDA-150 mV
2.048 2.049(3)
2.5
2.502(3)
VREFBUF_ Voltage
reference output
OUT
-
-
VDDA
Degraded mode(2)
VDDA
Trim step
resolution
TRIM
CL
-
-
-
-
-
±0.05
1
±0.1
1.5
%
Load capacitor
0.5
µF
Equivalent
Serial Resistor
of Cload
esr
-
-
-
-
-
-
-
-
2
4
Ω
Static load
current
Iload
mA
I
load = 500 µA
-
-
-
200
100
50
1000
500
Iline_reg
Iload_reg
Line regulation 2.8 V ≤ VDDA ≤ 3.6 V
ppm/V
Iload = 4 mA
Load regulation 500 μA ≤ Iload ≤4 mA Normal mode
500
ppm/mA
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106
Electrical characteristics
STM32G071x8/xB
(1)
Table 61. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Temperature
TCoeff_vrefbuf coefficient of
-40 °C < TJ < +125 °C
-
-
50
ppm/ °C
VREFBUF(4)
DC
40
25
-
60
40
-
Power supply
PSRR
dB
µs
rejection
100 kHz
-
CL = 0.5 µF(5)
CL = 1.1 µF(5)
CL = 1.5 µF(5)
300
500
650
350
650
800
tSTART
Start-up time
-
-
Control of
maximum DC
current drive on
VREFBUF_OUT
during start-up
phase (6)
IINRUSH
-
-
8
-
mA
µA
Iload = 0 µA
-
-
-
16
18
35
25
30
50
VREFBUF
consumption
from VDDA
IDDA(VREFB
Iload = 500 µA
UF)
Iload = 4 mA
1. Guaranteed by design.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA
drop voltage).
-
3. Guaranteed by test in production.
4. The temperature coefficient at VREF+ output is the sum of TCoeff_vrefint and TCoeff_vrefbuf
.
5. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
6. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
5.3.20
Comparator characteristics
(1)
Table 62. COMP characteristics
Symbol
VDDA
VIN
Parameter
Conditions
Min Typ Max Unit
Analog supply
voltage
-
1.62
0
-
-
3.6
V
V
Comparator
input voltage range
-
VDDA
(2)
VBG
Scaler input voltage
Scaler offset voltage
Scaler static
-
VREFINT
±5
V
VSC
-
-
-
±10
mV
nA
BRG_EN=0 (bridge disable)
200 300
0.8
100 200
IDDA(SCALER) consumption from
VDDA
BRG_EN=1 (bridge enable)
-
-
-
1
µA
µs
tSTART_SCALER Scaler startup time
96/133
DS12232 Rev 3
STM32G071x8/xB
Symbol
Electrical characteristics
Min Typ Max Unit
(1)
Table 62. COMP characteristics (continued)
Parameter Conditions
Comparator startup
time to reach
propagation delay
specification
High-speed mode
-
-
-
-
5
tSTART
µs
Medium-speed mode
15
200 mV step;
100 mV
overdrive
High-speed mode
Medium-speed mode
-
-
-
-
30
0.3
-
50
0.6
70
ns
µs
ns
µs
tD
Propagation delay
>200 mV step; High-speed mode
100 mV
Medium-speed mode
overdrive
-
1.2
Comparator offset
error
Voffset
Full common mode range
-
±5
±20
mV
No hysteresis
-
-
-
-
-
0
-
-
Low hysteresis
Medium hysteresis
High hysteresis
10
20
30
5
Comparator
hysteresis
Vhys
mV
-
-
Static
7.5
Medium-speed
mode;
No deglitcher
With 50 kHz and ±100 mV
overdrive square signal
-
-
-
-
-
6
7
8
-
10
-
Static
Comparator
consumption from
VDDA
Medium-speed
mode;
With deglitcher
IDDA(COMP)
µA
With 50 kHz and ±100 mV
overdrive square signal
Static
250 400
High-speed
mode
With 50 kHz and ±100 mV
overdrive square signal
250
-
1. Guaranteed by design.
2. Refer to Table 24: Embedded internal voltage reference.
5.3.21
Temperature sensor characteristics
Table 63. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VTS linearity with temperature
-
±1
2.5
±2
2.7
°C
mV/°C
V
Avg_Slope(2) Average slope
2.3
V30
Voltage at 30°C (±5 °C)(3)
0.742
0.76
0.785
Sensor Buffer Start-up time in continuous mode(4)
Start-up time when entering in continuous mode(4)
-
-
8
15
µs
µs
(1)
tSTART(TS_BUF)
(1)
tSTART
70
120
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Electrical characteristics
STM32G071x8/xB
Table 63. TS characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
(1)
tS_temp
ADC sampling time when reading the temperature
5
-
-
µs
Temperature sensor consumption from VDD, when
selected by ADC
(1)
IDD(TS)
-
4.7
7
µA
1. Guaranteed by design.
2. Based on characterization results, not tested in production.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
5.3.22
V
monitoring characteristics
BAT
Table 64. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
39
3
-
-
-
kΩ
-
Ratio on VBAT measurement
Error on Q
Er(1)
-10
12
10
-
%
µs
(1)
tS_vbat
ADC sampling time when reading the VBAT
-
1. Guaranteed by design.
Table 65. V
charging characteristics
BAT
Symbol
Parameter
Conditions
VBRS = 0
VBRS = 1
Min
Typ
5
Max
Unit
Battery
charging
resistor
-
-
-
-
RBC
kΩ
1.5
5.3.23
Timer characteristics
The parameters given in the following tables are guaranteed by design. Refer to
Section 5.3.14: I/O port characteristics for details on the input/output alternate function
characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 66. TIMx characteristics
Symbol
tres(TIM)
Parameter
Conditions
Min
Max
Unit
-
fTIMxCLK = 64 MHz
-
1
-
tTIMxCLK
ns
Timer resolution time
15.625
-
fTIMxCLK/2
40
0
0
-
Timer external clock frequency
on CH1 to CH4
fEXT
MHz
bit
fTIMxCLK = 64 MHz
TIMx (except TIM2)
TIM2
16
ResTIM
Timer resolution
-
32
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STM32G071x8/xB
Symbol
Electrical characteristics
(1)
Table 66. TIMx characteristics (continued)
Parameter
Conditions
Min
Max
Unit
-
fTIMxCLK = 64 MHz
-
1
65536
1024
tTIMxCLK
µs
tTIMxCLK
s
tCOUNTER
16-bit counter clock period
0.015625
-
-
65536 × 65536
67.10
Maximum possible count with
32-bit counter
tMAX_COUNT
fTIMxCLK = 64 MHz
1. TIMx, is used as a general term in which x stands for 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17.
(1)
Table 67. IWDG min/max timeout period at 32 kHz LSI clock
Prescaler divider PR[2:0] bits
Min timeout RL[11:0]= 0x000
Max timeout RL[11:0]= 0xFFF
Unit
/4
/8
0
0.125
0.250
0.500
1.0
512
1024
2048
4096
8192
16384
32768
1
/16
/32
/64
/128
/256
2
3
4
ms
2.0
5
4.0
6 or 7
8.0
1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an
uncertainty of one RC period.
5.3.24
Characteristics of communication interfaces
I2C-bus interface characteristics
2
2
The I C-bus interface meets timing requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The timings are guaranteed by design as long as the I2C peripheral is properly configured
(refer to the reference manual RM0444) and when the I2CCLK frequency is greater than the
minimum shown in the following table.
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Electrical characteristics
STM32G071x8/xB
Table 68. Minimum I2CCLK frequency
Condition
Symbol
Parameter
Typ
Unit
Standard-mode
2
Analog filter enabled
9
9
DNF = 0
Analog filter disabled
DNF = 1
Fast-mode
Minimum I2CCLK
frequency for correct
operation of I2C
peripheral
fI2CCLK(min)
MHz
Analog filter enabled
DNF = 0
18
16
Fast-mode Plus
Analog filter disabled
DNF = 1
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
is disabled, but is still present. Only FT_f I/O pins
DDIO1
support Fm+ low-level output current maximum requirement. Refer to Section 5.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its
characteristics:
(1)
Table 69. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Limiting duration of spikes suppressed
by the filter(2)
tAF
50
260
ns
1. Based on characterization results, not tested in production.
2. Spikes shorter than the limiting duration are suppressed.
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 70 for SPI are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 21: General operating conditions. The additional general conditions
are:
•
•
•
OSPEEDRy[1:0] set to 11 (output speed)
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
100/133
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STM32G071x8/xB
Electrical characteristics
(1)
Table 70. SPI characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Master mode
1.65 < VDD < 3.6 V
Range 1
32
Master transmitter
1.65 < VDD < 3.6 V
Range 1
32
32
32
Slave receiver
1.65 < VDD < 3.6 V
Range 1
fSCK
1/tc(SCK)
SPI clock frequency
-
-
MHz
Slave transmitter/full duplex
2.7 < VDD < 3.6 V
Range 1
Slave transmitter/full duplex
1.65 < VDD < 3.6 V
Range 1
23
8
1.65 < VDD < 3.6 V
Range 2
tsu(NSS) NSS setup time
th(NSS) NSS hold time
Slave mode, SPI prescaler = 2
Slave mode, SPI prescaler = 2
4 ₓ TPCLK
2 ₓ TPCLK
-
-
-
-
ns
ns
TPCLK
- 1.5
TPCLK
+ 1.5
tw(SCKH) SCK high time
tw(SCKL) SCK low time
Master mode
TPCLK
ns
ns
ns
ns
ns
ns
TPCLK
- 1.5
TPCLK
+ 1.5
Master mode
TPCLK
Master data input setup
tsu(MI)
tsu(SI)
th(MI)
th(SI)
-
-
-
-
1
1
5
1
-
-
-
-
-
-
-
-
time
Slave data input setup
time
Master data input hold
time
Slave data input hold
time
ta(SO) Data output access time Slave mode
tdis(SO) Data output disable time Slave mode
9
9
-
-
34
16
ns
ns
2.7 < VDD < 3.6 V
Range 1
-
-
-
9
9
14
21
24
Slave data output valid
time
1.65 < VDD < 3.6 V
Range 1
tv(SO)
ns
ns
1.65 < VDD < 3.6 V
Voltage Range 2
11
Master data output valid
time
tv(MO)
-
-
3
5
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Electrical characteristics
STM32G071x8/xB
(1)
Table 70. SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Slave data output hold
time
th(SO)
-
5
-
-
ns
Master data output hold
time
th(MO)
-
1
-
-
ns
1. Based on characterization results, not tested in production.
Figure 27. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
Figure 28. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
102/133
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STM32G071x8/xB
Electrical characteristics
Figure 29. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
t
su(MI)
f(SCK)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD
.
2
(1)
Table 71. I S characteristics
Conditions
Symbol
Parameter
Min
Max
Unit
fMCK= 256 x Fs; (Fs = audio sampling
frequency)
fMCK
I2S main clock output
2.048
49.152
MHz
Fsmin = 8 kHz; Fsmax = 192 kHz;
Master data
Slave data
-
-
64xFs
64xFs
fCK
I2S clock frequency
MHz
%
I2S clock frequency duty
cycle
DCK
Slave receiver
30
70
DS12232 Rev 3
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106
Electrical characteristics
STM32G071x8/xB
2
(1)
Table 71. I S characteristics (continued)
Conditions
Symbol
Parameter
WS valid time
Min
Max
Unit
tv(WS)
th(WS)
tsu(WS)
Master mode
Master mode
Slave mode
-
8
-
WS hold time
WS setup time
WS hold time
2
4
-
th(WS)
Slave mode
2
4
-
-
-
-
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
5
4.5
2
ns
after enable edge; 2.7 < VDD < 3.6V
after enable edge; 1.65 < VDD < 3.6V
16
23
Data output valid time -
slave transmitter
tv(SD_ST)
-
Data output valid time -
master transmitter
tv(SD_MT)
th(SD_ST)
th(SD_MT)
after enable edge
after enable edge
after enable edge
-
5.5
Data output hold time -
slave transmitter
8
1
-
-
Data output hold time -
master transmitter
1. Based on characterization results, not tested in production.
2
Figure 30. I S slave timing diagram (Philips protocol)
tc(CK)
CPOL = 0
CPOL = 1
WS input
th(WS)
tw(CKH)
tw(CKL)
tv(SD_ST)
th(SD_ST)
tsu(WS)
LSB transmit(2)
tsu(SD_SR)
MSB transmit
MSB receive
Bitn transmit
th(SD_SR)
SDtransmit
SDreceive
LSB receive(2)
Bitn receive
LSB receive
MSv39721V1
1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
104/133
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STM32G071x8/xB
Electrical characteristics
2
Figure 31. I S master timing diagram (Philips protocol)
90%
10%
tf(CK)
tr(CK)
tc(CK)
CPOL = 0
CPOL = 1
WS output
SDtransmit
tw(CKH)
tv(WS)
th(WS)
tw(CKL)
tv(SD_MT)
th(SD_MT)
LSB transmit(2)
tsu(SD_MR)
MSB transmit
MSB receive
Bitn transmit
th(SD_MR)
LSB transmit
SDreceive
LSB receive(2)
Bitn receive
LSB receive
MSv39720V1
1. Based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
USART characteristics
Unless otherwise specified, the parameters given in Table 72 for USART are derived from
tests performed under the ambient temperature, f
frequency and supply voltage
PCLKx
conditions summarized in Table 21: General operating conditions. The additional general
conditions are:
•
•
•
OSPEEDRy[1:0] set to 10 (output speed)
capacitive load C = 30 pF
measurement points at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, and RX for USART).
Table 72. USART characteristics
Symbol
Parameter
Conditions
Master mode
Slave mode
Min
Typ
Max
Unit
-
-
-
-
8
fCK
USART clock frequency
MHz
21
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Electrical characteristics
STM32G071x8/xB
Table 72. USART characteristics
Symbol
Parameter
Conditions
Slave mode
Min
Typ
Max
Unit
tsu(NSS)
th(NSS)
tw(CKH)
tw(CKL)
NSS setup time
NSS hold time
CK high time
CK low time
tker + 2
2
-
-
-
-
Slave mode
1 / fCK / 2
- 1
1 / fCK / 2
+ 1
Master mode
1 / fCK / 2
Master mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
t
ker + 2
-
-
-
-
tsu(RX)
th(RX)
tv(TX)
th(TX)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
4
1
ns
-
-
0.5
-
-
-
0.5
10
-
1
19
-
-
0
7
-
-
5.3.25
UCPD characteristics
UCPD1 and UCPD2 controllers comply with USB Type-C Rev.1.2 and USB Power Delivery
Rev. 3.0 specifications.
Table 73. UCPD operating conditions
Symbol
Parameter
Conditions
Sink mode only
Sink and source mode
Min
Typ
Max
Unit
3.0
3.3
3.3
3.6
V
V
UCPD operating supply
voltage
VDD
3.135
3.465
106/133
DS12232 Rev 3
STM32G071x8/xB
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 32. LQFP64 package outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
D1
D3
L
L1
33
48
32
49
64
b
17
16
1
PIN 1
e
IDENTIFICATION
5W_ME_V3
1. Drawing is not to scale.
Table 74. LQFP64 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
-
-
-
1.600
0.150
1.450
-
-
0.0630
0.0059
0.0571
A1
A2
0.050
1.350
0.0020
0.0531
-
1.400
0.0551
DS12232 Rev 3
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128
Package information
STM32G071x8/xB
Table 74. LQFP64 package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
b
c
0.170
0.220
-
0.270
0.0067
0.0087
-
0.0106
0.090
0.200
0.0035
0.0079
D
-
12.000
10.000
7.500
12.000
10.000
7.500
0.500
3.5°
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
3.5°
-
D1
D3
E
-
-
-
-
-
-
-
-
-
-
-
-
E1
E3
e
-
-
-
-
-
-
-
-
-
-
7°
-
-
7°
K
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 33. Recommended footprint for LQFP64 package
48
33
0.3
0.5
49
32
12.7
10.3
10.3
7.8
17
64
1.2
16
1
12.7
ai14909c
1. Dimensions are expressed in millimeters.
108/133
DS12232 Rev 3
STM32G071x8/xB
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 34. LQFP64 package marking example
Revision code
R
Product identification (1)
STM32G071
RBT6
Date code
Y WW
Pin 1 identifier
MSv47902V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12232 Rev 3
109/133
128
Package information
STM32G071x8/xB
6.2
UFBGA64 package information
UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-low-profile fine-pitch ball grid array
package.
Figure 35. UFBGA64 package outline
Z Seating plane
ddd Z
A4
A3 A2
A1
A
E1
X
A1 ball
A1 ball
E
identifier index area
e
F
A
F
D1
D
e
Y
H
8
1
Øb (64 balls)
Øeee M Z Y X
Øfff M Z
BOTTOM VIEW
TOP VIEW
A019_ME_V1
1. Drawing is not to scale.
Table 75. UFBGA64 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
A4
b
0.460
0.050
0.400
0.080
0.270
0.170
4.850
3.450
4.850
3.450
-
0.530
0.080
0.450
0.130
0.320
0.280
5.000
3.500
5.000
3.500
0.500
0.750
0.600
0.110
0.500
0.180
0.370
0.330
5.150
3.550
5.150
3.550
-
0.0181
0.0020
0.0157
0.0031
0.0106
0.0067
0.1909
0.1358
0.1909
0.1358
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.1969
0.1378
0.1969
0.1378
0.0197
0.0295
0.0236
0.0043
0.0197
0.0071
0.0146
0.0130
0.2028
0.1398
0.2028
0.1398
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
110/133
DS12232 Rev 3
STM32G071x8/xB
Symbol
Package information
Table 75. UFBGA64 package mechanical data (continued)
millimeters
Typ
inches(1)
Min
Max
Min
Typ
Max
A
0.460
0.530
0.600
0.080
0.150
0.050
0.0181
0.0209
0.0236
0.0031
0.0059
0.0020
ddd
eee
fff
-
-
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. Recommended footprint for UFBGA64 package
Dpad
Dsm
A019_FP_V2
Table 76. Recommended PCB design rules for UFBGA64 package
Dimension
Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the solder mask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.280 mm
Between 0.100 mm and 0.125 mm
0.100 mm
DS12232 Rev 3
111/133
128
Package information
STM32G071x8/xB
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 37. UFBGA64 package marking example
(1)
Product identification
G071R8I6
Standard ST logo
Date code
Y WW
Revision code
Ball A1 identifier
R
MSv47972V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
112/133
DS12232 Rev 3
STM32G071x8/xB
Package information
6.3
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Figure 38. LQFP48 package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
36
25
37
24
b
48
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
Table 77. LQFP48 mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
0.3543
0.2756
0.2165
D1
D3
DS12232 Rev 3
113/133
128
Package information
STM32G071x8/xB
Table 77. LQFP48 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E
E1
E3
e
8.800
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
9.200
0.3465
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
0.3622
6.800
7.200
0.2677
0.2835
-
-
-
-
-
-
0.750
-
-
-
0.0295
-
L
0.450
0.0177
L1
k
-
0°
-
-
0°
-
7°
7°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 39. Recommended footprint for LQFP48 package
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
114/133
DS12232 Rev 3
STM32G071x8/xB
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 40. LQFP48 package marking example
Product identification (1)
STM32G071
CBT6
Date code
Y WW
Revision code
Pin 1 identifier
R
MSv47904V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12232 Rev 3
115/133
128
Package information
STM32G071x8/xB
6.4
UFQFPN48 package information
UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package
Figure 41. UFQFPN48 package outline
Pin 1 identifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500x45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
Table 78. UFQFPN48 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.550
0.020
7.000
7.000
5.600
5.600
0.600
0.050
7.100
7.100
5.700
5.700
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
E
D2
E2
116/133
DS12232 Rev 3
STM32G071x8/xB
Package information
Table 78. UFQFPN48 package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
L
T
0.300
0.400
0.152
0.250
0.500
-
0.500
-
0.0118
0.0157
0.0060
0.0098
0.0197
-
0.0197
-
-
-
b
0.200
0.300
-
0.0079
0.0118
-
e
-
-
-
-
ddd
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. Recommended footprint for UFQFPN48 package
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
DS12232 Rev 3
117/133
128
Package information
STM32G071x8/xB
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 43. UFQFPN48 package marking example
Product identification (1)
STM32G
071CBU6
Date code
YWW
Revision code
Pin 1 identifier
R
MSv47906V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
118/133
DS12232 Rev 3
STM32G071x8/xB
Package information
6.5
LQFP32 package information
LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.
Figure 44. LQFP32 package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
K
D
D1
D3
L
L1
24
17
16
25
32
9
PIN 1
IDENTIFICATION
1
8
e
5V_ME_V2
1. Drawing is not to scale.
Table 79. LQFP32 mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
-
1.600
0.150
1.450
-
-
-
0.0630
0.0059
0.0571
A1
A2
0.050
1.350
0.0020
0.0531
1.400
0.0551
DS12232 Rev 3
119/133
128
Package information
STM32G071x8/xB
Table 79. LQFP32 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
b
c
0.300
0.370
-
0.450
0.200
9.200
7.200
-
0.0118
0.0146
-
0.0177
0.0079
0.3622
0.2835
-
0.090
0.0035
D
8.800
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3465
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
6.800
0.2677
-
-
8.800
9.200
7.200
-
0.3465
0.3622
0.2835
-
E1
E3
e
6.800
0.2677
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0°
-
-
0°
-
7°
7°
ccc
-
0.100
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 45. Recommended footprint for LQFP32 package
0.80
1.20
24
17
25
16
0.50
0.30
7.30
6.10
9.70
7.30
32
9
8
1
1.20
6.10
9.70
5V_FP_V2
1. Dimensions are expressed in millimeters.
120/133
DS12232 Rev 3
STM32G071x8/xB
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 46. LQFP32 package marking example
Product identification (1)
STM32G
071KBT6
Date code
Y WW
Pin 1 identifier
Revision code
R
MSv47908V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12232 Rev 3
121/133
128
Package information
STM32G071x8/xB
6.6
UFQFPN32 package information
UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package.
Figure 47. UFQFPN32 package outline
D
A
ddd C
SEATINGPLANE
A1
A3
e
C
D1
b
e
b
E2
E1
E
1
L
32
D2
L
PIN 1 Identifier
A0B8_ME_V3
1. Drawing is not to scale.
2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.
Table 80. UFQFPN32 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A3
b
0.500
-
0.550
-
0.600
0.050
-
0.0197
-
0.0217
-
0.0236
0.0020
-
-
0.152
0.230
5.000
3.500
3.500
5.000
3.500
3.500
0.500
0.400
-
-
0.0060
0.0091
0.1969
0.1378
0.1378
0.1969
0.1378
0.1378
0.0197
0.0157
-
0.180
4.900
3.400
3.400
4.900
3.400
3.400
-
0.280
5.100
3.600
3.600
5.100
3.600
3.600
-
0.0071
0.1929
0.1339
0.1339
0.1929
0.1339
0.1339
-
0.0110
0.2008
0.1417
0.1417
0.2008
0.1417
0.1417
-
D
D1
D2
E
E1
E2
e
L
0.300
-
0.500
0.080
0.0118
-
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
122/133
DS12232 Rev 3
STM32G071x8/xB
Package information
Figure 48. Recommended footprint for UFQFPN32 package
5.30
3.80
0.60
25
32
1
24
3.45
3.80
5.30
3.45
0.50
8
17
0.30
16
9
0.75
3.80
A0B8_FP_V2
1. Dimensions are expressed in millimeters
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 49. UFQFPN32 package marking example
Product identification (1)
G071KB6
Date code
Revision code
Y
WW R
Pin 1 identifier
MSv47910V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12232 Rev 3
123/133
128
Package information
STM32G071x8/xB
6.7
UFQFPN28 package information
UFQFPN is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 50. UFQFPN28 package outline
Detail Y
D
E
D
D1
E1
Detail Z
A0B0_ME_V5
1. Drawing is not to scale.
(1)
Table 81. UFQFPN28 package mechanical data
millimeters
Typ
inches
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
-
0.550
0.000
4.000
3.000
4.000
3.000
0.400
0.350
0.152
0.250
0.500
0.600
0.050
4.100
3.100
4.100
3.100
0.500
0.450
-
0.0197
-
0.0217
0.0000
0.1575
0.1181
0.1575
0.1181
0.0157
0.0138
0.0060
0.0098
0.0197
0.0236
0.0020
0.1614
0.1220
0.1614
0.1220
0.0197
0.0177
-
3.900
2.900
3.900
2.900
0.300
0.250
-
0.1535
0.1142
0.1535
0.1142
0.0118
0.0098
-
D1
E
E1
L
L1
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
1. Values in inches are converted from mm and rounded to 4 decimal digits.
124/133
DS12232 Rev 3
STM32G071x8/xB
Package information
Figure 51. Recommended footprint for UFQFPN28 package
ꢀꢁꢀꢂ
ꢂꢁꢅꢂ
ꢀꢁꢃꢂ
ꢄꢁꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢃꢂ
ꢂꢁꢀꢂ
ꢂꢁꢅꢅ
ꢂꢁꢅꢂ
ꢂꢁꢅꢂ
!ꢂ"ꢂ?&0?6ꢃ
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 52. UFQFPN28 package marking example
Product identification (1)
G071GB
Revision code
R
Date code
Y
WW
Pin 1 identifier
MSv47912V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12232 Rev 3
125/133
128
Package information
STM32G071x8/xB
6.8
WLCSP25 package information
Figure 53. WLCSP25 chip-scale package outline
F
bbb Z
e1
A1
A1 ball location
5
4
3
2
1
G
e
A
B
C
DETAIL A
e2
E
D
E
aaa
e
A
A2
D
(4X)
BOTTOM VIEW
TOP VIEW
SIDE VIEW
A3
A2
BUMP
A1
eee
Z
b
FRONT VIEW
Z
b (25x)
M
ccc
Z X Y
Z
M
ddd
DETAIL A
ROTATED 90
A06J_WLCSP25_ME_V1
1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
Table 82. WLCSP25 mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A(2)
A1
A2
A3
b
-
-
0.59
-
-
0.023
-
0.18
0.38
0.025(3)
0.25
2.30
2.48
0.40
1.60
-
-
0.007
0.015
0.001
0.010
0.091
0.098
0.016
0.063
-
-
-
-
-
-
-
-
-
0.22
2.28
2.46
-
0.28
2.32
2.50
-
0.009
0.090
0.097
-
0.011
0.091
0.098
-
D
E
e
e1
-
-
-
-
126/133
DS12232 Rev 3
STM32G071x8/xB
Package information
Table 82. WLCSP25 mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
e2
-
-
-
-
-
-
-
-
1.60
-
-
-
-
-
-
-
-
-
0.063
-
F(4)
G(4)
aaa
bbb
ccc
ddd
eee
0.350
-
0.014
-
0.440
-
0.017
-
-
-
-
-
-
0.10
0.10
0.10
0.05
0.05
-
-
-
-
-
0.004
0.004
0.004
0.002
0.002
1. Values in inches are converted from mm and rounded to 3 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
values and tolerances of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place
Figure 54. Recommended PCB pad design for WLCSP25 package
Dpad
Dsm
MS18965V2
Table 83. Recommended PCB pad design rules for WLCSP25 package
Dimension
Recommended value (mm)
Pitch
0.4
225
Dpad
Dsm
0.290 typ.(1)
Stencil opening
0.250
Stencil thickness
0.100
1. Depends on the solder mask registration tolerance
DS12232 Rev 3
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128
Package information
STM32G071x8/xB
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks that identify the parts throughout supply chain
operations, are not indicated below.
Figure 55. WLCSP25 package marking example
Ball A1 identifier
Product identification (1)
G0786
Date code
Revision code
YWW
R
MSv47937V2
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
128/133
DS12232 Rev 3
STM32G071x8/xB
6.9
Thermal characteristics
The operating junction temperature T must never exceed the maximum given in
J
Table 21: General operating conditions.
The maximum junction temperature in °C that the device can reach if respecting the
operating conditions, is:
T (max) = T (max) + P (max) x Θ
JA
J
A
D
where:
•
•
•
T (max) is the maximum operating ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P = P
+ P
,
I/O
D
INT
INT
–
–
P
P
P
is power dissipation contribution from product of I and V
DD DD
is power dissipation contribution from output ports where:
I/O
I/O
= Σ (V × I ) + Σ ((V
– V ) × I ),
OH OH
OL
OL
DDIO1
taking into account the actual V / I and V / I of the I/Os at low and high
OL OL
OH OH
level in the application.
Table 84. Package thermal characteristics
Symbol
Parameter
Package
Value
Unit
LQFP64 10 × 10 mm
UFBGA64 5 × 5 mm
LQFP48 7 × 7 mm
65
74
75
30
76
34
44
70
UFQFPN48 7 × 7 mm
LQFP32 7 × 7 mm
Thermal resistance
junction-ambient
Θ
°C/W
JA
UFQFPN32 5 × 5 mm
UFQFPN28 4 × 4 mm
WLCSP25 2.3 × 2.5 mm
6.9.1
6.9.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (still air). Available from www.jedec.org.
Selecting the product temperature range
The temperature range is specified in the ordering information scheme shown in Section 7:
Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and to a specific maximum junction temperature.
As applications do not commonly use microcontrollers at their maximum power
consumption, it is useful to calculate the exact power consumption and junction temperature
to determine which temperature range best suits the application.
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130
STM32G071x8/xB
The following example shows how to calculate the temperature range needed for a given
application.
Example:
Assuming the following worst application conditions:
•
•
•
•
ambient temperature T = 50 °C (measured according to JESD51-2)
A
I
= 50 mA; V = 3.6 V
DD
DD
20 I/Os simultaneously used as output at low level with I = 8 mA (V = 0.4 V), and
OL
OL
8 I/Os simultaneously used as output at low level with I = 20 mA (V = 1.3 V),
OL
OL
the power consumption from power supply P
is:
INT
P
= 50 mA × 3.6 V= 118 mW,
INT
the power loss through I/Os P is
IO
P
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW,
IO
and the total power P to dissipate is:
D
P
180 mW + 272 mW = 452 mW
D =
For product in LQFP48 with Θ = 75°C/W, the junction temperature stabilizes at:
JA
T = 50°C + (75°C/W × 452 mW) = 50 °C + 33.9 °C = 83.9°C
J
As a conclusion, product version with suffix 6 (maximum allowed T = 105° C) is sufficient
J
for this application.
If the same application was used in a hot environment with maximum T greater than 71°C,
A
the junction temperature would exceed 105°C and the product version allowing higher
maximum T would have to be ordered.
J
130/133
DS12232 Rev 3
STM32G071x8/xB
Ordering information
7
Ordering information
Example
STM32
G
071
K
8
T
6
xyy
Device family
®
STM32 = Arm based 32-bit microcontroller
Product type
G = general-purpose
Device subfamily
071 = STM32G071
Pin count
E = 25
G = 28
K = 32
C = 48
R = 64
Flash memory size
8 = 64 Kbytes
B = 128 Kbytes
Package type
I = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = -40 to 85°C (105°C junction)
7 = -40 to 105°C (125°C junction)
3 = -40 to 125°C (130°C junction)
Options
xTR = tape and reel packing; x = N (PD product version) or blank
x˽˽ = tray packing; x = N (PD product version) or blank
other = 3-character ID incl. custom Flash code and packing information; x = N for PD product version
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
DS12232 Rev 3
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131
Revision history
STM32G071x8/xB
8
Revision history
Table 85. Document revision history
Date
Revision
Changes
8-Nov-2018
1
Initial release.
Table 19: IINJ(PIN) parameter definition modified;
Table 21: VIN parameter definition modified;
Table 51: FT_d type added to Ilkg parameter
specification, note attached to Ilkg values, and TT_xx
modified to TT_a;
28-Nov-2018
2
Table 56: “single ended mode” removed from IDDV(ADC)
parameter definition;
Table 84: UFBGA64 5x5 mm package ΘJA corrected
Cover page updated;
Section 2: Description updated;
Section 3.3.1: Securable area added;
Section 3.7.1: Power supply schemes: corrected
minimum VDD and VDDA values;
Section 3.14.1: Temperature sensor: “engineering
bytes” replaced “System memory”;
Section 3.20: Inter-integrated circuit interface (I2C):
SMBus and PMBus feature points;
Section 3.21: Universal synchronous/asynchronous
receiver transmitter (USART): max. speed corrected;
Table 12: Note 3 inserted and note 4 modified;
Table 18 updated;
06-Mar-2020
3
Table 19: Note 2 removed;
Table 21: Redefined VIN for I/Os of other than TT_xx
and FT_c type;
Table 49: LU class modified from “II” to “II Level A”;
Table 52: I/O current condition for relaxed VOL/VOH
corrected from 18 mA to 15 mA; section Output driving
current corrected accordingly;
Table 56: major update;
Section 3.12: DMA request multiplexer (DMAMUX)
added;
Figures with package marking examples corrected.
132/133
DS12232 Rev 3
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
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