STM32G431C8U3TR [STMICROELECTRONICS]
Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz /213 DMIPS, up to 128 KB Flash, 32 KB SRAM, rich analog, math accelerator;
| 型号： | STM32G431C8U3TR |
| 厂家： | 
ST |
| 描述： | Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz /213 DMIPS, up to 128 KB Flash, 32 KB SRAM, rich analog, math accelerator 静态存储器 |
| 文件： | 总197页 (文件大小：2587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32G431x6 STM32G431x8
STM32G431xB
Arm® Cortex®-M4 32-bit MCU+FPU, 170 MHz /213 DMIPS,
up to 128 KB Flash, 32 KB SRAM, rich analog, math accelerator
Datasheet - production data
Features
FBGA
®
®
• Core: Arm 32-bit Cortex -M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 170 MHz
with 213 DMIPS, MPU, DSP instructions
LQFP32 (7 x 7 mm)
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
LQFP80 (12 x 12 mm)
LQFP100 (14 x 14 mm)
UFBGA64
(5 x 5 mm)
UFQFPN32 (5 x 5 mm)
UFQFPN48 (7 x 7 mm)
WLCSP49
(Pitch 0.4)
• Operating conditions:
– V , V
voltage range:
• Interconnect matrix
DD
DDA
1.71 V to 3.6 V
• 12-channel DMA controller
• Mathematical hardware accelerators
• 2 x ADCs 0.25 µs (up to 23 channels).
– CORDIC for trigonometric functions
acceleration
Resolution up to 16-bit with hardware
oversampling, 0 to 3.6 V conversion range
– FMAC: filter mathematical accelerator
• 4 x 12-bit DAC channels
• Memories
– 2 x buffered external channels 1 MSPS
– 128 Kbytes of Flash memory with ECC
support, proprietary code readout
protection (PCROP), securable memory
area, 1 Kbyte OTP
– 2 x unbuffered internal channels 15 MSPS
• 4 x ultra-fast rail-to-rail analog comparators
• 3 x operational amplifiers that can be used in
PGA mode, all terminals accessible
– 22 Kbytes of SRAM, with hardware parity
check implemented on the first 16 Kbytes
• Internal voltage reference buffer (VREFBUF)
supporting three output voltages (2.048 V,
2.5 V, 2.9 V)
– Routine booster: 10 Kbytes of SRAM on
instruction and data bus, with hardware
parity check (CCM SRAM)
• 14 timers:
• Reset and supply management
– 1 x 32-bit timer and 2 x 16-bit timers with up
to four IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– Power-on/power-down reset
(POR/PDR/BOR)
– 2 x 16-bit 8-channel advanced motor
control timers, with up to 8 x PWM
channels, dead time generation and
emergency stop
– Programmable voltage detector (PVD)
– Low-power modes: sleep, stop, standby
and shutdown
– V
supply for RTC and backup registers
BAT
– 1 x 16-bit timer with 2 x IC/OCs, one
OCN/PWM, dead time generation and
emergency stop
• Clock management
– 4 to 48 MHz crystal oscillator
– 32 kHz oscillator with calibration
– Internal 16 MHz RC with PLL option (± 1%)
– Internal 32 kHz RC oscillator (± 5%)
– 2 x 16-bit timers with IC/OC/OCN/PWM,
dead time generation and emergency stop
– 2 x watchdog timers (independent, window)
– 1 x SysTick timer: 24-bit downcounter
– 2 x 16-bit basic timers
• Up to 86 fast I/Os
– All mappable on external interrupt vectors
– 1 x low-power timer
– Several I/Os with 5 V tolerant capability
November 2020
DS12589 Rev 3
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This is information on a product in full production.
www.st.com
STM32G431x6 STM32G431x8 STM32G431xB
• Calendar RTC with alarm, periodic wakeup
– 1 x SAI (serial audio interface)
from stop/standby
– USB 2.0 full-speed interface with LPM and
BCD support
• Communication interfaces
– IRTIM (infrared interface)
– 1 x FDCAN controller supporting flexible
data rate
– USB Type-C™ /USB power delivery
controller (UCPD)
2
– 3 x I C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus,
wakeup from stop
• True random number generator (RNG)
• CRC calculation unit, 96-bit unique ID
– 4 x USART/UARTs (ISO 7816 interface,
LIN, IrDA, modem control)
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
– 1 x LPUART
– 3 x SPIs, 4 to 16 programmable bit frames,
2
2 x with multiplexed half duplex I S
interface
Table 1. Device summary
Part number
Reference
STM32G431x6
STM32G431x8
STM32G431xB
STM32G431C6, STM32G431K6, STM32G431R6, STM32G431V6, STM32G431M6
STM32G431C8, STM32G431K8, STM32G431R8, STM32G431V8, STM32G431M8
STM32G431CB, STM32G431KB, STM32G431RB, STM32G431VB, STM32G431MB
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Adaptive real-time memory accelerator (ART accelerator) . . . . . . . . . . . 17
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21
3.11 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.11.6
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16 DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 28
3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 28
3.18 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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STM32G431x6 STM32G431x8 STM32G431xB
3.18.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.22 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.24.1 Advanced motor control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . 33
3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 36
3.26 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.27 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.28 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Universal synchronous/asynchronous receiver transmitter (USART) . . . 39
3.30 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 40
3.31 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.32 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.32.1 SAI peripheral supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.33 Controller area network (FDCAN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.34 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.35 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 42
3.36 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1
UFQFPN32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
LQFP32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
WLCSP49 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
UFBGA64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LQFP80 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.10 Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.11 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 72
Embedded reset and power control block characteristics . . . . . . . . . . . 72
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3.7
5.3.8
5.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 117
5.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.3.18 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 118
5.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 133
5.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.3.24
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
BAT
5.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 150
5.3.27 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 192
7
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32G431x6/x8/xB features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32G431x6/x8/xB peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SAI implementation for the features implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32G431x6/x8/xB pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 72
Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . . 76
Current consumption in Run and Low-power run modes,
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 80
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Typical current consumption in Run and Low-power run modes, with different codes
running from CCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Current consumption in Sleep and Low-power sleep mode Flash ON . . . . . . . . . . . . . . . . 84
Current consumption in low-power sleep modes, Flash in power-down. . . . . . . . . . . . . . . 85
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LSE
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DS12589 Rev 3
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9
List of tables
STM32G431x6 STM32G431x8 STM32G431xB
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
I/O (except FT_c) AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
I/O FT_c AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ADC accuracy (Multiple ADCs operation) - limited test conditions 1 . . . . . . . . . . . . . . . . 129
ADC accuracy (Multiple ADCs operation) - limited test conditions 2 . . . . . . . . . . . . . . . . 130
ADC accuracy (Multiple ADCs operation) - limited test conditions 3 . . . . . . . . . . . . . . . . 131
DAC 1MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
DAC 1MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DAC 15MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
DAC 15MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
BAT
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
WWDG min/max timeout value at 170 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
USART electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
UFQFPN32 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
LQFP32 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
UFQFPN48 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
LQFP48 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
WLCSP49 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
WLCSP49 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
8/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
List of tables
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
LQFP64 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
UFBGA64 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 182
LQFP80 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
LQPF100 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 100. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 101. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DS12589 Rev 3
9/197
9
List of figures
STM32G431x6 STM32G431x8 STM32G431xB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32G431x6/x8/xB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STM32G431x6/x8/xB UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STM32G431x6/x8/xB LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STM32G431x6/x8/xB UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32G431x6/x8/xB LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32G431x6/x8/xB WLCSP49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10. STM32G431x6/x8/xB LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 11. STM32G431x6/x8/xB UFBGA64 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. STM32G431x6/x8/xB LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. STM32G431x6/x8/xB LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 14. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 15. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 17. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 18. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 20. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 23. HSI16 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 24. HSI48 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 25. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
(1)
Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 28. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 30. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 31. VREFOUT_TEMP in case VRS = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 32. VREFOUT_TEMP in case VRS = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 33. VREFOUT_TEMP in case VRS = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 34. OPAMP noise density @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 35. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 36. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 37. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 38. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 39. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 40. UFQFPN32 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 41. UFQFPN32 - recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 42. UFQFPN32 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 43. LQFP32 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 44. LQFP32 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 45. LQFP32 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 46. UFQFPN48 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 47. UFQFPN48 - recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 48. UFQFPN48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
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List of figures
Figure 49. LQFP48 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 50. LQFP48 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 51. LQFP48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 52. WLCSP49 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 53. WLCSP49 - recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 54. WLCSP49 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 55. LQFP64 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 56. LQFP64 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 57. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 58. UFBGA64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 59. UFBGA64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 60. UFBGA64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 61. LQFP80 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 62. LQFP80 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 63. LQFP80 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 64. LQFP100 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 65. LQFP100 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 66. LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
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11
Introduction
STM32G431x6 STM32G431x8 STM32G431xB
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32G431x6/x8/xB microcontrollers.
This document should be read in conjunction with the reference manual RM0440
®
“STM32G4 Series advanced Arm 32-bit MCUs”. The reference manual is available from
the STMicroelectronics website www.st.com.
®(a)
®
®
For information on the Arm
Cortex -M4 core, refer to the Cortex -M4 technical
reference manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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Description
2
Description
®
®
The STM32G431x6/x8/xB devices are based on the high-performance Arm Cortex -M4
32-bit RISC core. They operate at a frequency of up to 170 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all
the Arm single-precision data-processing instructions and all the data types. It also
implements a full set of DSP (digital signal processing) instructions and a memory protection
unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (128 Kbytes of Flash memory, and 32 Kbytes
of SRAM), an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The devices also embed several protection mechanisms for embedded Flash memory and
SRAM: readout protection, write protection, securable memory area and proprietary code
readout protection.
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC for trigonometric functions and FMAC unit for filter functions).
They offer two fast 12-bit ADCs (5 Msps), four comparators, three operational amplifiers,
four DAC channels (2 external and 2 internal), an internal voltage reference buffer, a low-
power RTC, one general-purpose 32-bit timers, two 16-bit PWM timers dedicated to motor
control, seven general-purpose 16-bit timers, and one 16-bit low-power timer.
They also feature standard and advanced communication interfaces such as:
- Three I2Cs
- Three SPIs multiplexed with two half duplex I2Ss
- Three USARTs, one UART and one low-power UART.
- One FDCAN
- One SAI
- USB device
- UCPD
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported including an analog independent supply
input for ADC, DAC, OPAMPs and comparators. A V
the registers.
input allows backup of the RTC and
BAT
The STM32G431x6/x8/xB family offers 9 packages from 32-pin to 100-pin.
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43
Description
STM32G431x6 STM32G431x8 STM32G431xB
Table 2. STM32G431x6/x8/xB features and peripheral counts
Peripheral
STM32G431Kx STM32G431Cx STM32G431Rx STM32G431Mx STM32G431Vx
32 64 128 32
64 128 32 64 128 32 64 128 32 64 128
KB KB KB KB KB KB KB KB KB KB KB
Flash memory
SRAM
KB KB KB
KB
32 (16 + 6 + 10) KB
2 (16-bit)
Advanced
motor control
General
purpose
5 (16-bit)
1 (32-bit)
Basic
2 (16-bit)
1 (16-bit)
1
Low power
SysTick timer
Timers
Watchdog
timers
2
(independent,
window)
PWM channels
(all)
23
23
32
25
36
25
36
25
36
25
PWM channels
(except
complementary)
SPI(I2S)(1)
I2C
3 (2)
3
USART
UART
2
3
0
1
Comm.
interfaces
LPUART
FDCANs
USB device
UCPD
1
1
Yes
Yes
Yes
Yes
SAI
RTC
Tamper pins
1
2
2
3
Random number generator
Yes
No
AES
CORDIC
FMAC
Yes
Yes
52
86
5
26
2
38 in LQFP48
66
4
GPIOs
42 in UFQFPN48
41 in WLCSP49
3
Wakeup pins
4
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Description
Table 2. STM32G431x6/x8/xB features and peripheral counts (continued)
Peripheral
STM32G431Kx STM32G431Cx STM32G431Rx STM32G431Mx STM32G431Vx
2
12-bit ADCs
Number of channels
17 in LQFP48
18 in UFQFPN48
18 in WLCSP49
11
23
2
23
23
12-bit DAC
Number of channels
4 (2 external + 2 internal)
Internal voltage reference
buffer
Yes
Analog comparator
Operational amplifiers
Max. CPU frequency
Operating voltage
4
3
170 MHz
1.71 V to 3.6 V
Operating temperature
Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
LQFP48/
LQFP64/
LQFP32/
UFQFPN32
Packages
UFQFPN48/
WLCSP49
LQFP80
LQFP100
UFBGA64
1. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
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43
Description
STM32G431x6 STM32G431x8 STM32G431xB
Figure 1. STM32G431x6/x8/xB block diagram
JTRST, JTDI,
JTCK/SWCLK
JTAG & SW
ETM
MPU
NVIC
FPU
JTDO/SWD, JTDO
TRACECK
TRACED(3:0)
Arm®
Cortex-M4
170MHz
D-BUS
I-BUS
FLASH 128 KB
S-BUS
CCM SRAM 10 KB
GP-DMA2
GP-DMA1
6 Chan
6 Chan
@VDDA
CH1
SRAM2 6 KB
SRAM1 16 KB
DAC1
OUT1/OUT2
CH2
DMAMUX
AHB2
CH1
CH2
DAC3
RNG
@VDDA
SAR ADC1
SAR ADC2
RNB1
analog
Ain ADC
IF
POWER MNGT
VOLT. REG.
3.3V TO 1.2V
CORDIC
FMAC
VDD = 1.71 to 3.6V
VSS
VDD12
PA(15:0)
PB(15:0)
@VDD
SUPPLY
GPIO PORT A
@VDD
GPIO PORT B
SUPERVISION
LSI
PLL
POR
Reset
Int
PC(15:0)
POR / BOR
GPIO PORT C
PD(15:0)
GPIO PORT D
VDD, VSS,
VDDA, VSSA,
RESET
HSI
HSI48
PVD, PWM
PE(15:0)
GPIO PORT E
PF(10:9,2:0)
GPIO PORT F
PG(10:10)
XTAL OSC
4-48MHz
GPIO PORT G
OSC_IN
OSC_OUT
RESET&
IWDG
FS, SCK, SD,
MCLK as AF
CLOCKCTRL
Standby Interface
@VBAT
VBAT = 1.55 to 3.6V
SAI1
OSC32_IN
OSC_OUT
peripheralclocks
and system
XTAL 32kHz
140 AFP
EXT IT. WKUP
RTC AWU
BKPREG
RTC_OUT
RTC_TS
RTC_TAMPx
CRC
4 PWM,4PWM,
ETR,BKIN as F
16b PWM
RTC Interface
TIMER1
TIMER8
4 PWM,4PWM,
ETR,BKIN as F
16b PWM
16b
AHB/APB2 AHB/APB1
TIMER2
4 CH, ETR as AF
4 CH, ETR as AF
CH as AF
CH as AF
TIMER15
TIMER3&4
16b
16b
TIMER16
PWRCTRL
WinWATCHDOG
LP timer1
LP_UART1
I2C1&2&3
RX, TX as AF
CH as AF16b
TIMER17
SCL, SDA, SMBAL as AF
RX, TX, SCK,
CTS, RTS as AF
RX, TX, CTS,
RTS as AF
Smcard
USART2&3
UART4
RX, TX, SCK,CTS,
RTS as AF
16b trigg
Smcard
irDA
irDA
TIMER6
TIMER7
USART1
16b trigg
MOSI, MISO
SCK, NSS as AF
irDA
SPI 1
I2S half
duplex
MOSI, MISO, SCK
NSS, as AF
SPI2&3
CRS
RX,TX as AF
CAN1
SysCfg
COMP
@VDDA
USBPD
USB
Device
D+
D-
OPAMP
1,2,3
Vref_Buf
1,2,3,4
CC1
CC2
MSv62521V2
1. AF: alternate function on I/O pins.
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Functional overview
3
Functional overview
3.1
Arm® Cortex®-M4 core with FPU
®
®
The Arm Cortex -M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
the MCU implementation, with a reduced pin count and with low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
®
®
The Arm Cortex -M4 with FPU 32-bit RISC processor features an exceptional code-
efficiency, delivering the expected high-performance from an Arm core in a memory size
usually associated with 8-bit and 16-bit devices.
The processor supports a set of DSP instructions which allows an efficient signal processing
and a complex algorithm execution. Its single precision FPU speeds up the software
development by using metalanguage development tools to avoid saturation.
With its embedded Arm core, the STM32G431x6/x8/xB family is compatible with all Arm
tools and software.
Figure 1 shows the general block diagram of the STM32G431x6/x8/xB devices.
3.2
3.3
Adaptive real-time memory accelerator (ART accelerator)
The ART accelerator is a memory accelerator that is optimized for the STM32 industry-
®
®
standard Arm Cortex -M4 processors. It balances the inherent performance advantage of
®
®
the Arm Cortex -M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 8 protected areas, which can be
divided in up into 8 subareas each. The protection area sizes range between 32 bytes and
the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.4
Embedded Flash memory
The STM32G431x6/x8/xB devices feature 128 kbytes of embedded Flash memory which is
available for storing programs and data.
Flexible protections can be configured thanks to the option bytes:
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43
Functional overview
STM32G431x6 STM32G431x8 STM32G431xB
• Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
– Level 0: no readout protection
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
•
•
Write protection (WRP): the protected area is protected against erasing and
programming.
Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An
additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not
when the RDP protection is changed from Level 1 to Level 0.
•
Securable memory area: a part of Flash memory can be configured by option bytes to
be securable. After reset this securable memory area is not secured and it behaves like
the remainder of main Flash memory (execute, read, write access). When secured, any
access to this securable memory area generates corresponding read/write error.
Purpose of the Securable memory area is to protect sensitive code and data (secure
keys storage) which can be executed only once at boot, and never again unless a new
reset occurs.
The Flash memory embeds the error correction code (ECC) feature supporting:
•
•
•
•
Single error detection and correction
Double error detection
The address of the ECC fail can be read in the ECC register
1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The
OTP area is available in Bank 1 only. The OTP data cannot be erased and can be
written only once.
3.5
Embedded SRAM
STM32G431x6/x8/xB devices feature 32 Kbytes of embedded SRAM. This SRAM is split
into three blocks:
•
16 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the
SRAM1 through the System Bus (or through the I-Code/D-Code buses when boot from
SRAM1 is selected or when physical remap is selected by SYSCFG_MEMRMP
register). Whole SRAM1 supports hardware parity check.
•
•
6 Kbytes mapped at address 0x2000 4000 (SRAM2). The CM4 can access the SRAM2
through the System bus. SRAM2 can be kept in stop and standby modes.
10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU
through I-Code/D-Code bus for maximum performance.
It is also aliased at 0x2000 5800 address to be accessed by all masters (CPU, DMA1,
DMA2) through SBUS contiguously to SRAM1 and SRAM2. The CCM SRAM supports
hardware parity check and can be write-protected with 1-Kbyte granularity.
•
The memory can be accessed in read/write at max CPU clock speed with 0 wait states.
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Functional overview
3.6
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM,AHB and APB peripherals). It also ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 2. Multi-AHB bus matrix
Cortex®-M4
with FPU
DMA1
DMA2
ICode
FLASH
128 KB
DCode
SRAM1
CCM
SRAM
SRAM2
AHB1
peripherals
AHB2
peripherals
BusMatrix-S
MS47544V1
3.7
Boot modes
At startup, a BOOT0 pin (or nBOOT0 option bit)and an nBOOT1 option bit are used to select
one of three boot options:
•
•
•
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit
depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade).
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Functional overview
STM32G431x6 STM32G431x8 STM32G431xB
3.8
CORDIC
The CORDIC provides hardware acceleration of certain mathematical functions, notably
trigonometric, commonly used in motor control, metering, signal processing and many other
applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
Cordic features
•
•
•
•
24-bit CORDIC rotation engine
Circular and Hyperbolic modes
Rotation and Vectoring modes
Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,
Natural logarithm
•
•
•
•
•
•
Programmable precision up to 20-bit
Fast convergence: 4 bits per clock cycle
Supports 16-bit and 32-bit fixed point input and output formats
Low latency AHB slave interface
Results can be read as soon as ready without polling or interrupt
DMA read and write channels
3.9
Filter mathematical accelerator (FMAC)
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
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FMAC features
Functional overview
•
•
•
•
•
16 x 16-bit multiplier
24+2-bit accumulator with addition and subtraction
16-bit input and output data
256 x 16-bit local memory
Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
•
•
•
•
•
Input and output sample buffers can be circular
Buffer “watermark” feature reduces overhead in interrupt mode
Filter functions: FIR, IIR (direct form 1)
AHB slave interface
DMA read and write data channels
3.10
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
3.11
Power supply management
3.11.1
Power supply schemes
The STM32G431x6/x8/xB devices require a 1.71 V to 3.6 V V operating voltage supply.
DD
Several independent supplies, can be provided for specific peripherals:
•
V
= 1.71 V to 3.6 V
DD
V
is the external power supply for the I/Os, the internal regulator and the system
DD
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
•
V
= 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum V
DDA
DDA
voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation).
is the external analog power supply for A/D converters, D/A converters, voltage
V
DDA
reference buffer, operational amplifiers and comparators. The V
voltage level is
DDA
independent from the V voltage and should preferably be connected to V when
DD
DD
these peripherals are not used.
•
V
= 1.55 V to 3.6 V
BAT
V
is the power supply for RTC, external clock 32 kHz oscillator and backup registers
BAT
(through power switch) when V is not present.
DD
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43
Functional overview
STM32G431x6 STM32G431x8 STM32G431xB
•
VREF-, VREF+
V
is the input reference voltage for ADCs and DACs. It is also the output of the
REF+
internal voltage reference buffer when enabled.
When V
When V
< 2 V V
must be equal to V
.
DDA
DDA
DDA
REF+
REF+
≥ 2 V V
must be between 2 V and V
.
DDA
The internal voltage reference buffer supports three output voltages, which are
configured with VRS bits in the VREFBUF_CSR register:
–
–
–
V
V
V
V
= 2.048 V
= 2.5 V
REF+
REF+
REF+
= 2.9 V
is double bonded with V
.
SSA
REF-
3.11.2
Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after power-
on and during power down. The device remains in reset mode when the monitored supply
voltage V is below a specified threshold, without the need for an external reset circuit.
DD
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the V power supply and compares it to the VPVD threshold. An
DD
interrupt can be generated when V drops below the VPVD threshold and/or when V is
DD
DD
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a peripheral voltage monitor which compares the
independent supply voltages V
, with a fixed threshold in order to ensure that the
DDA
peripheral is in its functional supply range.
3.11.3
Voltage regulator
Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep
modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby
and Shutdown modes, both regulators are powered down and their outputs set in high-
impedance state, such as to bring their current consumption close to zero.
The device supports dynamic voltage scaling to optimize its power consumption in Run
mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator (MR) operates in the following ranges:
•
•
•
Range 1 boost mode with the CPU running at up to 170 MHz.
Range 1 normal mode with CPU running at up to 150 MHz.
Range 2 with a maximum CPU frequency of 26 MHz.
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Functional overview
3.11.4
Low-power modes
By default, the microcontroller is in Run mode after system or power Reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to
operate and can wake up the CPU when an interrupt/event occurs.
•
Low-power run mode: This mode is achieved with VCORE supplied by the low-power
regulator to minimize the regulator's operating current. The code can be executed from
SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with
independent clock can be clocked by HSI16.
•
•
Stop mode: In Stop mode, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the VCORE domain are
stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable
the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.
Standby mode: The Standby mode is used to achieve the lowest power consumption
with brown-out reset, BOR. The internal regulator is switched off to power down the
VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal
oscillator are also powered down. The RTC can remain active (Standby mode with
RTC, Standby mode without RTC). The BOR always remains active in Standby mode.
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM
and register contents are lost except for registers in the RTC domain and standby
circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG
reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC
event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on
LSE (CSS on LSE).
•
Shutdown mode: The Shutdown mode allows to achieve the lowest power
consumption. The internal regulator is switched off to power down the VCORE domain.
The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are
also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown
mode without RTC). The BOR is not available in Shutdown mode. No power voltage
monitoring is possible in this mode. Therefore, switching to RTC domain is not
supported. SRAM and register contents are lost except for registers in the RTC
domain. The device exits Shutdown mode upon external reset event (NRST pin),
IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or
RTC event (alarm, periodic wakeup, timestamp, tamper).
3.11.5
3.11.6
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
V
operation
BAT
The V
pin allows to power the device V
domain from an external battery, an external
BAT
BAT
supercapacitor, or from V when there is no external battery and when an external
DD
supercapacitor is present. The V
pin supplies the RTC with LSE and the backup
BAT
registers. Three anti-tamper detection pins are available in V
mode.
BAT
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The V
operation is automatically activated when V is not present. An internal V
DD BAT
BAT
battery charging circuit is embedded and can be activated when V is present.
DD
Note:
When the microcontroller is supplied from V
, neither external interrupts nor RTC
BAT
alarm/events exit the microcontroller from the V
operation.
BAT
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3.12
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
Table 3. STM32G431x6/x8/xB peripherals interconnect matrix
Interconnect
destination
Interconnect source
Interconnect action
TIMx
Timers synchronization or chaining
Conversion triggers
Y
Y
Y
Y
Y
Y
-
-
ADCx
DACx
TIMx
DMA
Memory to memory transfer trigger
Comparator output blanking
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
COMPx
IRTIM
TIM16/TIM17
COMPx
ADCx
Infrared interface output generation
TIM1, 8
TIM2, 3, 4
Timer input channel, trigger, break
from analog signals comparison
Y
Y
Y
-
Low-power timer triggered by
analog signals comparison
LPTIMER1
TIM1, 8
TIM16
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Timer triggered by analog watchdog
Timer input channel from RTC
events
-
RTC
Low-power timer triggered by RTC
alarms or tampers
LPTIMER1
Y
Y
Y
Y
All clocks sources (internal
and external)
Clock source used as input channel
for RC measurement and trimming
TIM15, 16, 17
TIM2
Y
Y
Y
Y
Y
-
-
-
USB
Timer triggered by USB SOF
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
COMPx
TIM1, 8
TIM15, 16, 17
Timer break
Y
Y
Y
-
PVD
TIMx
External trigger
External trigger
Y
Y
Y
Y
Y
Y
-
-
LPTIMER1
GPIO
ADCx
DACx
Conversion external trigger
Y
Y
Y
-
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3.13
Clocks and startup
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•
•
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock source: three different sources can deliver SYSCLK system clock:
–
4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).
It can supply clock to system PLL. The HSE can also be configured in bypass
mode for an external clock.
–
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
System PLL with maximum output frequency of 170 MHz. It can be fed with HSE
or HSI16 clocks.
•
•
RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can
be used to drive the USB or the RNG peripherals.
Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
–
32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
–
32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
•
•
Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI,
RNG) have their own clock independent of the system clock.
Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt.
•
Clock-out capability:
–
MCO: microcontroller clock output: it outputs one of the internal clocks for external
use by the application
–
LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes.
Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 170 MHz.
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3.14
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.15
Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 4: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 12 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports:
•
12 independently configurable channels (requests)
–
Each channel is connected to a dedicated hardware DMA request, a software
trigger is also supported on each channel. This configuration is done by software.
•
•
Priorities between requests from channels of one DMA are both software
programmable (4 levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•
•
Support for circular buffer management
3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
•
•
•
•
Memory-to-memory transfer
Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
Access to Flash, SRAM, APB and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536.
Table 4. DMA implementation
DMA features
DMA1
6
DMA2
6
Number of regular channels
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3.16
DMA request router (DMAMux)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in figures or described in the text. The DMA request generator
produces DMA requests following events on DMA request trigger inputs.
3.17
Interrupts and events
3.17.1
Nested vectored interrupt controller (NVIC)
The STM32G431x6/x8/xB devices embed a nested vectored interrupt controller which is
able to manage 16 priority levels, and to handle up to 71 maskable interrupt channels plus
®
the 16 interrupt lines of the Cortex -M4.
The NVIC benefits are the following:
•
•
•
•
•
•
•
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.17.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 39 edge detector lines used to generate
interrupt/event requests and to wake-up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 86 GPIOs can
be connected to the 16 external interrupt lines.
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3.18
Analog-to-digital converter (ADC)
The device embeds two successive approximation analog-to-digital converters with the
following features:
•
•
12-bit native resolution, with built-in calibration
4 Msps maximum conversion rate with full resolution
–
–
Down to 41.67 ns sampling time
Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit
resolution)
•
One external reference pin is available on all packages, allowing the input voltage
range to be independent from the power supply
•
•
Single-ended and differential mode inputs
Low-power design
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–
Dual clock domain architecture: ADC speed independent from CPU frequency
•
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
–
–
–
–
–
Results stored into a data register or in RAM with DMA controller support
Data pre-processing: left/right alignment and per channel offset compensation
Built-in oversampling unit for enhanced SNR
Channel-wise programmable sampling time
Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
–
–
Flexible sample time control
Hardware gain and offset compensation
3.18.1
Temperature sensor
The temperature sensor (TS) generates a voltage V that varies linearly with temperature.
TS
The temperature sensor is internally connected to the ADC1_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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Table 5. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
TS_CAL1
TS_CAL2
0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.18.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN18
input channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 6. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT
temperature of 30 °C (± 5 °C),
0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.18.3
VBAT battery voltage monitoring
This embedded hardware enables the application to measure the V
battery voltage using
BAT
the internal ADC1_IN17 channel. As the V
voltage may be higher than the V
, and
BAT
DDA
thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
3. As a consequence, the converted digital value is one third of the V
voltage.
BAT
3.19
Digital to analog converter (DAC)
Four 12 bit DAC channels (2 external buffered and 2 internal unbuffered) can be used to
convert digital signals into analog voltage signal outputs. The chosen design structure is
composed of integrated resistor strings and an amplifier in inverting configuration.
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This digital interface supports the following features:
Up to two DAC output channels
8-bit or 12-bit output mode
•
•
•
•
•
•
•
•
•
•
•
•
•
Buffer offset calibration (factory and user trimming)
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Saw tooth wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Sample and hold low-power mode, with internal or external capacitor
Up to 1 Msps for external output and 15 Msps for internal output
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.20
Voltage reference buffer (VREFBUF)
The STM32G431x6/x8/xB devices embed a voltage reference buffer which can be used as
voltage reference for ADC, DACs and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports three voltages:
•
•
•
2.048 V
2.5 V
2.9 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with V
on some packages. In these packages the
DDA
internal voltage reference buffer is not available.
Figure 3. Voltage reference buffer
VREFBUF
Bandgap
VDDA DAC, ADC
+
-
VREF+
Low frequency
cut-off capacitor
100 nF
MSv40197V1
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3.21
Comparators (COMP)
The STM32G431x6/x8/xB devices embed four rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis.
The reference voltage can be one of the following:
•
•
•
External I/O
DAC output channels
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers.
3.22
Operational amplifier (OPAMP)
The STM32G431x6/x8/xB devices embed three operational amplifiers with external or
internal follower routing and PGA capability.
The operational amplifier features:
•
•
•
13 MHz bandwidth
Rail-to-rail input/output
PGA with a non-inverting gain ranging of 2, 4, 8, 16, 32 or 64 or inverting gain ranging
of -1, -3, -7, -15, -31 or -63
3.23
3.24
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
Timers and watchdogs
The STM32G431x6/x8/xB devices include two advanced motor control timers, up to six
general-purpose timers, two basic timers, one low-power timer, two watchdog timers and a
SysTick timer. The table below compares the features of the advanced motor control,
general purpose and basic timers.
Table 7. Timer feature comparison
DMA
request
generation channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
Advanced
motor
control
Up,
Any integer
TIM1, TIM8
TIM2
16-bit
32-bit
16-bit
down, between 1 and
Up/down
Yes
Yes
Yes
4
4
4
4
65536
Up,
Any integer
General-
purpose
down, between 1 and
Up/down
No
No
65536
Up,
Any integer
General-
purpose
TIM3, TIM4
down, between 1 and
Up/down 65536
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Table 7. Timer feature comparison (continued)
DMA
request
generation channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
Any integer
between 1 and
65536
General-
purpose
TIM15
16-bit
16-bit
16-bit
Up
Up
Up
Yes
Yes
Yes
2
1
0
1
1
Any integer
between 1 and
65536
General-
purpose
TIM16, TIM17
TIM6, TIM7
Any integer
between 1 and
65536
Basic
No
3.24.1
Advanced motor control timer (TIM1, TIM8)
The advanced motor control timers can each be seen as a four-phase
PWM multiplexed on 8 channels. They have complementary PWM outputs with
programmable inserted dead-times. They can also be seen as complete general-purpose
timers.
The 4 independent channels can be used for:
•
•
•
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
•
One-pulse mode output
In debug mode, the advanced motor control timer counter can be frozen and the PWM
outputs disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.24.2) using the same architecture, so the advanced motor control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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3.24.2
General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16,
TIM17)
There are up to six synchronizable general-purpose timers embedded in the
STM32G431x6/x8/xB devices (see Table 7 for differences). Each general-purpose timer can
be used to generate PWM outputs, or act as a simple time base.
•
TIM2, TIM3, and TIM4
They are full-featured general-purpose timers:
–
–
TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler
TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature 4 independent channels for input capture/output compare, PWM
or one-pulse mode output. They can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
TIM15, 16 and 17
•
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
–
TIM15 has 2 channels and 1 complementary channel
TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.24.3
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
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3.24.4
Low-power timer (LPTIM1)
The devices embed a low-power timer. This timer has an independent clock and are running
in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the system
from Stop mode.
LPTIM1 is active in Stop mode.
This low-power timer supports the following features:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous/ one shot mode
Selectable software/hardware input trigger
Selectable clock source
–
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•
•
Programmable digital glitch filter
Encoder mode
3.24.5
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.24.6
3.24.7
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
•
•
•
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
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3.25
Real-time clock (RTC) and backup registers
The RTC supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC is supplied through a switch that takes power either from the V supply when
DD
present or from the VBAT pin.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in V
mode and in all low-power modes when it is clocked by the
BAT
LSE. When clocked by the LSI, the RTC is not functional in V
all low-power modes except Shutdown mode.
mode, but is functional in
BAT
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.
3.26
Tamper and backup registers (TAMP)
•
16 32-bit backup registers, retained in all low-power modes and also in V
mode.
BAT
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. They are not reset by a system or power reset, or when the device
wakes up from Standby or Shutdown mode.
•
Up to three tamper pins for external tamper detection events. The external tamper pins
can be configured for edge detection, edge and level, level detection with filtering.
•
•
•
•
Five internal tampers events.
Any tamper detection can generate a RTC timestamp event.
Any tamper detection erases the backup registers.
Any tamper detection can generate an interrupt and wake-up the device from all low-
power modes.
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Functional overview
3.27
Infrared transmitter
The STM32G431x6/x8/xB devices provide an infrared transmitter solution. The solution is
based on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
Figure 4. Infrared transmitter
TIM17_CH1
IR_OUT
IRTIM
TIM16_CH1
MS30474V2
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Functional overview
STM32G431x6 STM32G431x8 STM32G431xB
3.28
Inter-integrated circuit interface (I2C)
The device embeds three I2Cs. Refer to Table 8: I2C implementation for the features
implementation.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power system management protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 8. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
Standard-mode (up to 100 kbit/s)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Programmable analog and digital noise filters
SMBus/PMBus hardware support
Independent clock
Wakeup from Stop mode on address match
1. X: supported
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Functional overview
3.29
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32G431x6/x8/xB devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3) and one universal asynchronous receiver
transmitters (UART4).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4) to wake up the MCU from Stop mode. The wakeup from Stop mode can be done
on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
All USART interfaces can be served by the DMA controller.
Table 9. USART/UART/LPUART features
USART modes/features(1)
USART1 USART2 USART3 UART4 LPUART1
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
-
Smartcard mode
-
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
X
X
-
-
Dual clock domain
X
X
-
Wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
-
X (4 modes)
-
X
X
X
X
X
LPUART/USART data length
7, 8 and 9 bits
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Functional overview
STM32G431x6 STM32G431x8 STM32G431xB
Table 9. USART/UART/LPUART features (continued)
USART modes/features(1)
USART1 USART2 USART3 UART4 LPUART1
Tx/Rx FIFO
X
8
Tx/Rx FIFO size
1. X = supported.
3.30
Low-power universal asynchronous receiver transmitter
(LPUART)
The STM32G431x6/x8/xB devices embed one Low-Power UART. The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half-
duplex single-wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default. It has a clock domain independent
from the CPU clock, and can wakeup the system from Stop mode. The wake up from Stop
mode can be done on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.31
Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to 75 Mbits/s in master and up to 41 Mbits/s in
slave, half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and hardware CRC calculation.
2
Two standard I S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio
standards can operate as master or slave at half-duplex communication modes. They can
be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and
synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can
be set by 8-bit programmable linear prescaler. When operating in master mode it can output
a clock for an external audio component at 256 times the sampling frequency.
All SPI interfaces can be served by the DMA controller.
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STM32G431x6 STM32G431x8 STM32G431xB
Functional overview
3.32
Serial audio interfaces (SAI)
The device embeds 1 SAI. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
3.32.1
SAI peripheral supports
•
Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•
•
•
•
8-word integrated FIFOs for each audio sub-block.
Synchronous or asynchronous mode between the audio sub-blocks.
Master or slave configuration independent for both audio sub-blocks.
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•
•
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
•
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
•
•
•
•
•
•
•
•
Number of bits by frame may be configurable.
Frame synchronization active level configurable (offset, bit length, level).
First active bit position in the slot is configurable.
LSB first or MSB first for data transfer.
Mute mode.
Stereo/Mono audio frame capability.
Communication clock strobing edge configurable (SCK).
Error flags with associated interrupts if enabled respectively.
–
–
–
–
Overrun and underrun detection.
Anticipated frame synchronization signal detection in slave mode.
Late frame synchronization signal detection in slave mode.
Codec not ready for the AC’97 mode in reception.
•
•
Interruption sources when enabled:
–
–
Errors.
FIFO requests.
DMA interface with 2 dedicated channels to handle access to the dedicated integrated
FIFO of each SAI audio sub-block.
Table 10. SAI implementation for the features implementation
SAI features
Support(1)
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
X
X
X
Mute mode
Stereo/Mono audio frame capability
16 slots
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Functional overview
STM32G431x6 STM32G431x8 STM32G431xB
Table 10. SAI implementation for the features implementation (continued)
SAI features
Support(1)
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
X
X (8 word)
X
FIFO size
SPDIF
1. X: supported.
3.33
3.34
Controller area network (FDCAN1)
The controller area network (CAN) subsystem consists of one CAN module and message
RAM memory.
The CAN module (FDCAN) is compliant with ISO 11898-1 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 1-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers.
Universal serial bus (USB)
The STM32G431x6/x8/xB devices embed a full-speed USB device peripheral compliant
with the USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume
support. It requires a precise 48 MHz clock which can be generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator
in automatic trimming mode. The synchronization for this oscillator can be taken from the
USB data stream itself (SOF signalization) which allows crystal less operation.
3.35
USB Type-C™ / USB Power Delivery controller (UCPD)
The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB
Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
•
•
•
•
USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
“Dead battery” support
USB Power Delivery message transmission and reception
FRS (fast role swap) support
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STM32G431x6 STM32G431x8 STM32G431xB
Functional overview
The digital controller handles notably:
•
•
•
USB Type-C level detection with de-bounce, generating interrupts
FRS detection, generating an interrupt
Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
•
•
•
•
•
USB Power Delivery timing dividers (including a clock pre-scaler)
CRC generation/checking
4b5b encode/decode
Ordered sets (with a programmable ordered set mask at receive)
Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.36
Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.37
Development support
3.37.1
Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.37.2
Embedded trace macrocell™
The Arm embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32G431x6/x8/xB devices through a small number of ETM pins to an external hardware
trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded trace macrocell operates with third party debugger software tools.
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Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
4
Pinouts and pin description
4.1
UFQFPN32 pinout description
Figure 5. STM32G431x6/x8/xB UFQFPN32 pinout
32 31 30 29 28 27 26 25
VDD
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PA0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PA14
PA13
PA12
PA11
PA10
PA9
UFQFPN32
PA1
Exposed pad
PA2
PA8
PA3
VDD
9
10 11 12 13 14 15 16
MSv47174V1
1. The above figure shows the package top view.
4.2
LQFP32 pinout description
Figure 6. STM32G431x6/x8/xB LQFP32 pinout
VDD
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PA0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PA14
PA13
PA12
PA11
PA10
PA9
LQFP32
PA1
PA2
PA8
PA3
VDD
MSv47175V1
1. The above figure shows the package top view
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Pinouts and pin description
4.3
UFQFPN48 pinout description
Figure 7. STM32G431x6/x8/xB UFQFPN48 pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
PA13
VDD
PA12
PA11
PA10
PA9
2
PC14-OSC32_IN
PC15-OSC32_OUT
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PA0
3
4
5
6
UFQFPN48
7
PA8
8
PC6
PA1
9
PB15
PB14
PB13
PB12
PA2
10
11
12
PA3
Exposed pad
PA4
VSS
MSv47172V1
1. The above figure shows the package top view.
2. VSS pads are connected to the exposed pad.
4.4
LQFP48 pinout description
Figure 8. STM32G431x6/x8/xB LQFP48 pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
2
PC14 - OSC32_IN
PC15 - OSC32_OUT
PF0 - OSC_IN
PF1 - OSC_OUT
PG10 - NRST
PA0
3
PA12
PA11
PA10
PA9
4
5
6
LQFP48
7
PA8
8
PB15
PB14
PB13
PB12
PB11
PA1
9
PA2
10
11
12
PA3
PA4
MSv42659V2
1. The above figure shows the package top view.
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Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
4.5
WLCSP49 ballout description
Figure 9. STM32G431x6/x8/xB WLCSP49 ballout
1
2
3
4
5
6
7
A
B
C
D
E
F
PA15
PC11
PB3
PB5
PB7
VSS
VDD
PB8-
BOOT0
PA12
PA11
PC6
PA13
PA10
PA8
PA14
PA9
PB4
PB6
PB9
VBAT
PG10-
NRST
PC14-
OSC32_IN
PC13
PA7
PA4
PA5
PB0
PC15-
OSC32_O
UT
PB14
PB11
VREF+
VDDA
PC4
PB1
PA1
PF1-
OSC_OUT
PF0-
OSC_IN
PB15
PB12
VDD
PB13
PB10
VSS
PB2
PA2
PA6
PA0
PA3
G
VSSA
MSv47176V2
1. The above figure shows the package top view.
4.6
LQFP64 pinout description
Figure 10. STM32G431x6/x8/xB LQFP64 pinout
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
VSS
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PC0
LQFP64
PC1
PC2
PC3
PA0
PA1
PA2
VSS
VDD
9
10
11
12
13
14
15
16
PC6
PB15
PB14
PB13
PB12
PB11
MSv42658V2
1. The above figure shows the package top view.
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Pinouts and pin description
4.7
UFBGA64 ballout description
Figure 11. STM32G431x6/x8/xB UFBGA64 ballout
1
2
3
4
5
6
7
8
A
B
C
D
E
F
VDD
PB9
VSS
PB7
PB8-BOOT0
PC1
PB6
PB5
PB4
PA4
PB3
PD2
PC12
PC11
PA14
PA10
PA8
PA15
VSS
PA13
PA9
VDD
PA12
PA11
PC9
PC13
PC14-
OSC32_IN
VBAT
PG10-NRST
PC0
PC10
PC4
PC15-
OSC32_OUT
PC2
PF0-OSC_IN
PF1-OSC_OUT
PC3
PA1
PA5
PB0
PC7
PC6
PA0
PA2
PC5
VSSA
PB1
PC8
PB15
VSS
PB14
PB12
VSS
G
H
PA6
VREF+
PB13
PA3
VDD
PA7
PB2
VDDA
PB10
PB11
VDD
MSv47177V3
1. The above figure shows the package top view.
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Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
4.8
LQFP80 pinout description
Figure 12. STM32G431x6/x8/xB LQFP80 pinout
VBAT
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PA12
PA11
PA10
PA9
PC13
2
PC14-OSC32_IN
3
PC15-OSC32_OUT
4
PF0-OSC_IN
5
PA8
PF1-OSC_OUT
PG10-NRST
PC0
6
PC9
7
PC8
8
PC7
PC1
9
PC6
PC2
10
11
12
13
14
15
16
17
18
19
20
VDD
VSS
PD10
PD9
LQFP80
PC3
PA0
PA1
PA2
PD8
VSS
PB15
PB14
PB13
PB12
PB11
VDD
VDD
PA3
PA4
PA5
PA6
MSv60826V1
1. The above figure shows the package top view.
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Pinouts and pin description
4.9
LQFP100 pinout description
Figure 13. STM32G431x6/x8/xB LQFP100 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD
VSS
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD
VSS
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC14-OSC32_IN
PC15-OSC32_OUT
9
PF9
PF10
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PC0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100
PC1
PC2
PC3
PF2
PA0
PA1
PA2
VSS
PD8
PB15
PB14
PB13
PB12
VDD
PA3
MSv42661V3
1. The above figure shows the package top view.
DS12589 Rev 3
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Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
4.10
Pin definition
Table 11. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
TT
B
Input / output pin
5 V tolerant I/O
3.6 V tolerant I/O
Dedicated BOOT0 pin
NRST
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
I/O, with Analog switch function supplied by VDDA
I/O, USB Type-C PD capable
I/O, USB Type-C PD Dead Battery function
I/O, Fm+ capable
I/O structure
_a(1)
_c
_d
_f(2)
_u(3)
I/O, with USB function
Notes
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 12 are: FT_a, FT_fa, TT_a.
2. The related I/O structures in Table 12 are: FT_f, FT_fa.
3. The related I/O structures in Table 12 are FT_u.
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Pinouts and pin description
(1)
Table 12. STM32G431x6/x8/xB pin definition
Pin Number
Pin name
(function
after reset)
Additional
Alternate function
functions
TRACECK, TIM3_CH1,
SAI1_CK1,
SAI1_MCLK_A,
-
-
-
-
-
-
-
-
1
PE2
I/O
FT
-
-
EVENTOUT
TRACED0, TIM3_CH2,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
3
PE3
PE4
I/O
I/O
FT
FT
-
-
SAI1_SD_B,
EVENTOUT
-
-
TRACED1, TIM3_CH3,
SAI1_D2, SAI1_FS_A,
EVENTOUT
TRACED2, TIM3_CH4,
SAI1_CK2,
-
-
-
-
-
-
-
-
4
PE5
I/O
FT
-
-
SAI1_SCK_A,
EVENTOUT
TRACED3,
SAI1_D1,
SAI1_SD_A,
EVENTOUT
WKUP3,
RTC_TAMP3
-
-
-
-
-
-
-
-
-
-
-
-
5
6
7
PE6
VBAT
PC13
I/O
S
FT
-
-
-
1
2
1
2
B7
C5
1
2
C2
B1
1
2
-
-
TIM1_BKIN,
TIM1_CH1N,
TIM8_CH4N,
EVENTOUT
WKUP2,
RTC_TAMP1,
RTC_TS,
(2)
(3)
I/O
FT
RTC_OUT1
(2)
(3)
PC14-
OSC32_IN
-
-
-
-
3
4
3
4
C7
D7
3
4
C1
D1
3
4
8
9
I/O
I/O
FT
FT
EVENTOUT
EVENTOUT
OSC32_IN
(2)
(3)
PC15-
OSC32_OUT
OSC32_OUT
TIM15_CH1,
SPI2_SCK,
SAI1_FS_B,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
11
PF9
I/O
I/O
FT
FT
-
-
-
-
-
TIM15_CH2,
SPI2_SCK,
SAI1_D3,
PF10
EVENTOUT
I2C2_SDA,
SPI2_NSS/
I2S2_WS, TIM1_CH3N,
EVENTOUT
ADC1_IN10,
OSC_IN
2
2
5
5
E7
5
E1
5
12 PF0-OSC_IN I/O FT_fa
SPI2_SCK/
I2S2_CK,
EVENTOUT
ADC2_IN10,
COMP3_INM,
OSC_OUT
PF1-
OSC_OUT
3
4
3
4
6
7
6
7
E6
C6
6
7
F1
D2
6
7
13
14
I/O FT_a
-
-
MCO,
EVENTOUT
PG10-NRST I/O
DS12589 Rev 3
FT
NRST
51/197
66
Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
Alternate function
functions
LPTIM1_IN1,
TIM1_CH1,
LPUART1_RX,
EVENTOUT
ADC12_IN6,
COMP3_INM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8
9
E2
C3
8
9
15
16
PC0
PC1
PC2
I/O FT_a
I/O TT_a
I/O FT_a
-
-
-
LPTIM1_OUT,
TIM1_CH2,
LPUART1_TX,
SAI1_SD_A,
EVENTOUT
ADC12_IN7,
COMP3_INP
LPTIM1_IN2,
TIM1_CH3,
COMP3_OUT,
EVENTOUT
10 D3 10 17
ADC12_IN8
LPTIM1_ETR,
TIM1_CH4,
SAI1_D1,
TIM1_BKIN2,
SAI1_SD_A,
EVENTOUT
-
-
-
-
-
-
11 G1 11 18
PC3
I/O FT_a
-
ADC12_IN9
I2C2_SMBA,
EVENTOUT
-
-
-
-
-
-
-
19
PF2
PA0
I/O
FT
-
-
-
TIM2_CH1,
USART2_CTS,
COMP1_OUT,
ADC12_IN1,
COMP1_INM,
COMP3_INP,
RTC_TAMP2,
WKUP1
5
5
8
8
F7 12 F2 12 20
I/O TT_a
I/O TT_a
TIM8_BKIN, TIM8_ETR,
TIM2_ETR, EVENTOUT
RTC_REFIN,
TIM2_CH2,
USART2_RTS_DE,
TIM15_CH1N,
EVENTOUT
ADC12_IN2,
COMP1_INP,
OPAMP1_VINP,
OPAMP3_VINP
6
7
6
7
9
9
D6 13 E3 13 21
PA1
PA2
-
-
TIM2_CH3,
USART2_TX,
COMP2_OUT,
TIM15_CH1,
LPUART1_TX,
UCPD1_FRSTX,
EVENTOUT
ADC1_IN3,
COMP2_INM,
OPAMP1_VOUT,
WKUP4/
10 10 F6 14 F3 14 22
I/O TT_a
LSCO
-
-
-
-
-
-
-
-
-
-
15 G2 15 23
16 H1 16 24
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM2_CH4, SAI1_CK1,
USART2_RX,
ADC1_IN4,
COMP2_INP,
TIM15_CH2,
8
8
11 11 G7 17 H2 17 25
PA3
I/O TT_a
-
LPUART1_RX,
SAI1_MCLK_A,
EVENTOUT
OPAMP1_VINM/
OPAMP1_VINP
52/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Pinouts and pin description
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
functions
Alternate function
TIM3_CH2, SPI1_NSS,
SPI3_NSS/
I2S3_WS,USART2_CK,
SAI1_FS_B,
ADC2_IN17,
DAC1_OUT1,
COMP1_INM
9
9
12 12 E5 18 D4 18 26
PA4
PA5
I/O TT_a
I/O TT_a
-
-
EVENTOUT
TIM2_CH1, TIM2_ETR,
SPI1_SCK,
ADC2_IN13,
DAC1_OUT2,
COMP2_INM,
OPAMP2_VINM
10 10 13 13 F5 19 E4 19 27
UCPD1_FRSTX,
EVENTOUT
TIM16_CH1,
TIM3_CH1, TIM8_BKIN,
SPI1_MISO,
ADC2_IN3,
OPAMP2_VOUT
11 11 14 14 G6 20 G3 20 28
PA6
PA7
I/O TT_a
-
TIM1_BKIN,
COMP1_OUT,
LPUART1_CTS,
EVENTOUT
TIM17_CH1,
TIM3_CH2,
ADC2_IN4,
COMP2_INP,
OPAMP1_VINP,
OPAMP2_VINP
TIM8_CH1N,
SPI1_MOSI,
TIM1_CH1N,
COMP2_OUT,
UCPD1_FRSTX,
EVENTOUT
12 12 15 15 D5 21 H3 21 29
I/O TT_a
-
TIM1_ETR, I2C2_SCL,
USART1_TX,
-
-
-
-
16
-
-
-
D4 22 D5 22 30
PC4
PC5
I/O FT_fa
I/O TT_a
-
-
ADC2_IN5
EVENTOUT
TIM15_BKIN, SAI1_D3,
TIM1_CH4N,
ADC2_IN11,
OPAMP1_VINM,
OPAMP2_VINM,
WKUP5
-
23 F4 23 31
USART1_RX,
EVENTOUT
TIM3_CH3,
TIM8_CH2N,
TIM1_CH2N,
UCPD1_FRSTX,
EVENTOUT
ADC1_IN15,
COMP4_INP,
OPAMP2_VINP,
OPAMP3_VINP
13 13 17 16 G5 24 E5 24 32
PB0
I/O TT_a
-
TIM3_CH4,
TIM8_CH3N,
TIM1_CH3N,
ADC1_IN12,
COMP1_INP,
OPAMP3_VOUT
-
-
-
-
18 17 E4 25 F5 25 33
PB1
PB2
I/O TT_a
I/O TT_a
-
-
COMP4_OUT,
LPUART1_RTS_DE,
EVENTOUT
RTC_OUT2,
LPTIM1_OUT,
I2C3_SMBA,
EVENTOUT
ADC2_IN12,
COMP4_INM,
OPAMP3_VINM
19 18 F4 26 H4 26 34
DS12589 Rev 3
53/197
66
Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
Alternate function
functions
14 14
-
19 G4 27 G4 27 35
VSSA
VREF+
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20 20 F3 28 G5 28 36
21 21 G3 29 H5 29 37
VREFBUF_OUT
-
VDDA
15 15
-
-
-
-
-
-
-
VDDA/VREF+
VREFBUF_OUT
TIM1_ETR,
SAI1_SD_B,
EVENTOUT
-
-
-
-
-
-
-
30 38
PE7
I/O TT_a
I/O FT_a
-
COMP4_INP
TIM1_CH1N,
SAI1_SCK_B,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
31 39
32 40
33 41
PE8
PE9
-
-
-
COMP4_INM
TIM1_CH1,SAI1_FS_B,
EVENTOUT
I/O
I/O
FT
FT
-
-
TIM1_CH2N,
SAI1_MCLK_B,
EVENTOUT
PE10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
34 42
35 43
36 44
PE11
PE12
PE13
I/O
I/O
I/O
FT
FT
FT
-
-
-
TIM1_CH2, EVENTOUT
-
-
-
TIM1_CH3N,
EVENTOUT
TIM1_CH3, EVENTOUT
TIM1_CH4,
TIM1_BKIN2,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
37 45
38 46
PE14
PE15
I/O
I/O
FT
FT
-
-
-
-
TIM1_BKIN,
TIM1_CH4N,
USART3_RX,
EVENTOUT
TIM2_CH3,
USART3_TX,
LPUART1_RX,
TIM1_BKIN,
SAI1_SCK_A,
EVENTOUT
-
-
22 22 F2 30 H6 39 47
PB10
I/O TT_a
-
OPAMP3_VINM
16 16
-
23 G2 31 G7 40 48
VSS
VDD
S
S
-
-
-
-
-
-
-
-
17 17 23 24 G1 32 H8 41 49
TIM2_CH4,
USART3_RX,
LPUART1_TX,
EVENTOUT
-
-
24 25 E3 33 H7 42 50
PB11
I/O FT_a
-
ADC12_IN14
54/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Pinouts and pin description
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
functions
Alternate function
I2C2_SMBA,
SPI2_NSS/
I2S2_WS, TIM1_BKIN,
USART3_CK,
LPUART1_RTS_DE,
EVENTOUT
-
-
-
-
-
-
25 26 F1 34 G8 43 51
26 27 E2 35 G6 44 52
27 28 D3 36 F8 45 53
PB12
PB13
PB14
I/O FT_a
I/O TT_a
I/O TT_a
-
-
-
ADC1_IN11
SPI2_SCK/I2S2_CK,
TIM1_CH1N,
USART3_CTS,
LPUART1_CTS,
EVENTOUT
OPAMP3_VINP
TIM15_CH1,
SPI2_MISO,
TIM1_CH2N,
ADC1_IN5,
OPAMP2_VINP
USART3_RTS_DE,
COMP4_OUT,
EVENTOUT
RTC_REFIN,
TIM15_CH2,
TIM15_CH1N,
COMP3_OUT,
TIM1_CH3N,
SPI2_MOSI/
I2S2_SD,
-
-
28 29 E1 37 F7 46 54
PB15
I/O FT_a
I/O FT_a
-
ADC2_IN15
EVENTOUT
USART3_TX,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
47 55
48 56
49 57
PD8
PD9
-
-
-
-
-
-
-
-
USART3_RX,
EVENTOUT
I/O
I/O
FT
FT
USART3_CK,
EVENTOUT
PD10
PD11
USART3_CTS,
EVENTOUT
-
-
58
59
I/O FT_a
TIM4_CH1,
USART3_RTS_DE,
EVENTOUT
-
-
-
-
-
-
-
PD12
I/O
I/O
FT
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
60
61
PD13
PD14
-
-
TIM4_CH2, EVENTOUT
I/O TT_a
TIM4_CH3, EVENTOUT OPAMP2_VINP
TIM4_CH4, SPI2_NSS,
-
-
-
-
-
-
-
-
62
PD15
I/O
FT
-
-
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50 63
51 64
VSS
VDD
S
S
-
-
-
-
-
-
-
-
DS12589 Rev 3
55/197
66
Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
Alternate function
functions
TIM3_CH1, TIM8_CH1,
I2S2_MCK, EVENTOUT
-
-
-
-
-
-
29
-
-
-
-
D1 38 E8 52 65
PC6
PC7
PC8
I/O
I/O
FT
FT
-
-
-
-
-
-
TIM3_CH2, TIM8_CH2,
I2S3_MCK, EVENTOUT
-
-
39 E7 53 66
40 F6 54 67
TIM3_CH3, TIM8_CH3,
I2C3_SCL, EVENTOUT
-
I/O FT_f
I/O FT_f
TIM3_CH4, TIM8_CH4,
I2SCKIN, TIM8_BKIN2,
I2C3_SDA, EVENTOUT
-
-
-
-
-
41 D8 55 68
PC9
-
-
MCO, I2C3_SCL,
I2C2_SDA, I2S2_MCK,
TIM1_CH1,
18 18 30 30 D2 42 E6 56 69
PA8
I/O FT_f
-
USART1_CK,
-
TIM4_ETR, SAI1_CK2,
SAI1_SCK_A,
EVENTOUT
I2C3_SMBA,I2C2_SCL,
I2S3_MCK, TIM1_CH2,
USART1_TX,
TIM15_BKIN,
TIM2_CH3,SAI1_FS_A,
EVENTOUT
19 19 31 31 C3 43 D7 57 70
PA9
I/O FT_fd
-
-
UCPD1_DBCC1
UCPD1_DBCC2
TIM17_BKIN,
USB_CRS_SYNC,
I2C2_SMBA,
FT_d
SPI2_MISO,TIM1_CH3,
USART1_RX,
20 20 32 32 C2 44 D6 58 71
PA10
I/O
a
TIM2_CH4, TIM8_BKIN,
SAI1_D1, SAI1_SD_A,
EVENTOUT
SPI2_MOSI/
I2S2_SD,
TIM1_CH1N,
USART1_CTS,
COMP1_OUT,
FDCAN1_RX,
TIM4_CH1,
21 21 33 33 C1 45 C8 59 72
PA11
I/O FT_u
-
USB_DM
TIM1_CH4,
TIM1_BKIN2,
EVENTOUT
56/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Pinouts and pin description
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
functions
Alternate function
TIM16_CH1,
I2SCKIN,
TIM1_CH2N,
USART1_RTS_DE,
COMP2_OUT,
FDCAN1_TX,
TIM4_CH2,
22 22 34 34 B1 46 B8 60 73
PA12
I/O FT_u
-
USB_DP
TIM1_ETR,
EVENTOUT
-
-
-
-
-
35
-
-
47 B7 61 74
48 A8 62 75
VSS
VDD
S
S
-
-
-
-
-
-
-
-
35 36
SWDIO-JTMS,
TIM16_CH1N,
I2C1_SCL,
IR_OUT,
(4)
(4)
(4)
23 23 36 37 B2 49 C7 63 76
24 24 37 38 B3 50 C6 64 77
25 25 38 39 A1 51 A7 65 78
PA13
PA14
PA15
I/O FT_f
I/O FT_f
I/O FT_f
-
-
-
USART3_CTS,
TIM4_CH3,
SAI1_SD_B,
EVENTOUT
SWCLK-JTCK,
LPTIM1_OUT,
I2C1_SDA,
TIM8_CH2,
TIM1_BKIN,
USART2_TX,
SAI1_FS_B,
EVENTOUT
JTDI,
TIM2_CH1, TIM8_CH1,
I2C1_SCL, SPI1_NSS,
SPI3_NSS/
I2S3_WS,USART2_RX,
UART4_RTS_DE,
TIM1_BKIN, TIM2_ETR,
EVENTOUT
TIM8_CH1N,
UART4_TX,
SPI3_SCK/
I2S3_CK,
USART3_TX,
EVENTOUT
-
-
-
-
39
40
-
-
-
52 C5 66 79
PC10
PC11
I/O
FT
-
-
-
-
TIM8_CH2N,
UART4_RX,
SPI3_MISO,
A2 53 B6 67 80
I/O FT_f
USART3_RX,
I2C3_SDA, EVENTOUT
DS12589 Rev 3
57/197
66
Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
Alternate function
functions
TIM8_CH3N,
SPI3_MOSI/
I2S3_SD,
USART3_CK,
UCPD1_FRSTX,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
54 A6 68 81
PC12
PD0
I/O
I/O
FT
FT
-
-
-
-
TIM8_CH4N,
FDCAN1_RX,
EVENTOUT
-
-
-
-
69 82
70 83
TIM8_CH4,
TIM8_BKIN2,
FDCAN1_TX,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD1
PD2
PD3
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
TIM3_ETR, TIM8_BKIN,
EVENTOUT
55 B5 71 84
TIM2_CH1/
TIM2_ETR,
USART2_CTS,
EVENTOUT
-
-
-
85
TIM2_CH2,
USART2_RTS_DE,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
86
87
PD4
PD5
I/O
I/O
FT
FT
-
-
-
-
USART2_TX,
EVENTOUT
TIM2_CH4,
SAI1_D1, USART2_RX,
SAI1_SD_A,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88
89
PD6
PD7
I/O
I/O
FT
FT
-
-
-
-
EVENTOUT
TIM2_CH3,
USART2_CK,
EVENTOUT
JTDO-TRACESWO,
TIM2_CH2, TIM4_ETR,
USB_CRS_SYNC,
TIM8_CH1N,
SPI1_SCK, SPI3_SCK/
I2S3_CK,
(4)
26 26 41 40 A3 56 A5 72 90
PB3
I/O
FT
-
USART2_TX,
TIM3_ETR,
SAI1_SCK_B,
EVENTOUT
58/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Pinouts and pin description
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
functions
Alternate function
JTRST,
TIM16_CH1,
TIM3_CH1,
TIM8_CH2N,
SPI1_MISO,
SPI3_MISO,
USART2_RX,
TIM17_BKIN,
SAI1_MCLK_B,
EVENTOUT
(4)
(5)
27 27 42 41 B4 57 C4 73 91
PB4
I/O FT_c
UCPD1_CC2
TIM16_BKIN,
TIM3_CH2,
TIM8_CH3N,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/
I2S3_SD,
28 28 43 42 A43 58 B4 74 92
PB5
I/O FT_f
-
-
USART2_CK,
I2C3_SDA,TIM17_CH1,
LPTIM1_IN1,
SAI1_SD_B,
EVENTOUT
TIM16_CH1N,
TIM4_CH1, TIM8_CH1,
TIM8_ETR,
USART1_TX,
COMP4_OUT,
TIM8_BKIN2,
LPTIM1_ETR,
SAI1_FS_B,
(5)
29 29 44 43 C4 59 A4 75 93
30 30 45 44 A5 60 A3 76 94
31 31 46 45 B5 61 B3 77 95
PB6
I/O FT_c
UCPD1_CC1
EVENTOUT
TIM17_CH1N,
TIM4_CH2, I2C1_SDA,
TIM8_BKIN,
USART1_RX,
COMP3_OUT,
TIM3_CH4,
LPTIM1_IN2,
UART4_CTS,
EVENTOUT
PB7
I/O FT_f
-
PVD_IN
TIM16_CH1,
TIM4_CH3, SAI1_CK1,
I2C1_SCL,
USART3_RX,
COMP1_OUT,
(6)
PB8-BOOT0 I/O FT_f
-
FDCAN1_RX,
TIM8_CH2, TIM1_BKIN,
SAI1_MCLK_A,
EVENTOUT
DS12589 Rev 3
59/197
66
Pinouts and pin description
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 12. STM32G431x6/x8/xB pin definition (continued)
Pin Number
Pin name
(function
after reset)
Additional
Alternate function
functions
TIM17_CH1,
TIM4_CH4,
SAI1_D2, I2C1_SDA,
IR_OUT, USART3_TX,
COMP2_OUT,
-
-
47 46 B6 62 A2 78 96
PB9
I/O FT_f
-
-
FDCAN1_TX,
TIM8_CH3,
TIM1_CH3N,
SAI1_FS_A,
EVENTOUT
TIM4_ETR,
TIM16_CH1,
USART1_TX,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
97
98
PE0
PE1
I/O
I/O
FT
FT
-
-
-
-
TIM17_CH1,
USART1_RX,
EVENTOUT
-
-
32 32
47 A6 63 B2 79 99
VSS
VDD
S
S
-
-
-
-
-
-
-
-
1
1
48 48 A7 64 A1 80 100
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
3. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the reference manual RM0440 "STM32G4 Series advanced Arm®-based 32-bit
MCUs".
4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4
pins and the internal pull-down on PA14 pin are activated.
5. After reset, a pull-down resistor (Rd = 5.1kΩ from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1,
UCPD1_CC2). The pull-down on PB6 (UCPD1_CC1) is activated by high level on PA9 (UCPD1_DBCC1). The pull-down on
PB4 (UCPD1_CC2) is activated by high level on PA10 (UCPD1_DBCC2). This pull-down control (dead battery support on
UCPD peripheral) can be disabled by setting bit UCPD1_DBDIS=1 in the PWR_CR3 register. PB4, PB6 have UCPD_CC
functionality which implements an internal pull-down resistor (5.1kΩ) which is controlled by the voltage on the
UCPD_DBCC pin (PA10, PA9). A high level on the UCPD_DBCC pin activates the pull-down on the UCPD_CC pin. The
pull-down effect on the CC lines can be removed by using the bit UCPD1_DBDIS =1 (USB Type-C and power delivery dead
battery disable) in the PWR_CR3 register.
6. It is recommended to set PB8 in another mode than analog mode after startup to limit consumption if the pin is left
unconnected.
60/197
DS12589 Rev 3
4.11
Alternate functions
Table 13. Alternate function
AF0
SYS_AF
-
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/
I2S2/3/
UART4
/TIM8/Infra
red
I2C3/4
/UART4/
LPUART1/
GPCOMP1/
2/3
I2C3/SAI1/
USB/TIM8/
15/
SPI2/3/
I2S2/3/
TIM1/8/
Infrared
Port
LPTIM1/TI I2C3/TIM1/
M2/5/15/1
6/17
I2C1/2/3/
TIM1/8/16/
17
LPTIM1/TI
M1/8/FDCA
N1
UART4/SAI
1/TIM2/15/ EVENT
UCPD1
USART1/2/
3
TIM1/8/15/ TIM2/3/4/8/
FDCAN1 17
LPUART1/
SAI1/TIM1
SAI1/
OPAMP2
2/3/4/8/15/
GPCOMP1
GPCOMP3
TIM2_
CH1
USART2_
CTS
COMP1_
OUT
EVENT
OUT
PA0
PA1
PA2
PA3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_BKIN TIM8_ETR
-
-
-
-
-
-
-
-
-
TIM2_ETR
RTC_
REFIN
TIM2_
CH2
USART2_
RTS_DE
TIM15_
-
EVENT
-
-
-
CH1N
OUT
TIM2_
CH3
USART2_
TX
COMP2_
OUT
TIM15_
-
LPUART1_
TX
UCPD1_
FRSTX
EVENT
OUT
-
-
-
CH1
TIM2_
CH4
USART2_
RX
TIM15_
-
LPUART1_
RX
SAI1_
MCLK_A
EVENT
OUT
SAI1_CK1
-
-
-
-
CH2
SPI3_NSS/
I2S3_WS
USART2_
CK
EVENT
OUT
PA4
-
-
TIM3_CH2
-
-
-
SPI1_NSS
SPI1_SCK
-
-
-
-
-
SAI1_FS_B
-
TIM2_
CH1
UCPD1_
FRSTX
EVENT
OUT
PA5
PA6
PA7
PA8
PA9
PA10
-
TIM2_ETR
TIM3_CH1
TIM3_CH2
I2C3_SCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM16_
CH1
COMP1_
OUT
LPUART1_
CTS
EVENT
OUT
-
TIM8_BKIN SPI1_MISO TIM1_BKIN
-
-
TIM17_
CH1
TIM8_
CH1N
TIM1_
CH1N
COMP2_
OUT
UCPD1_
FRSTX
EVENT
OUT
-
SPI1_MOSI
-
-
USART1_
CK
SAI1_
SCK_A
EVENT
OUT
MCO
-
-
I2C2_SDA
I2C2_SCL
I2S2_MCK TIM1_CH1
I2S3_MCK TIM1_CH2
SPI2_MISO TIM1_CH3
-
-
-
TIM4_ETR
TIM2_CH3
SAI1_CK2
-
I2C3_
SMBA
USART1_
TX
TIM15_
BKIN
EVENT
OUT
-
-
SAI1_FS_A
TIM17_
BKIN
USB_
CRS_SYNC
I2C2_
SMBA
USART1_
RX
SAI1_SD_ EVENT
-
-
TIM2_CH4 TIM8_BKIN
TIM4_CH1 TIM1_CH4
TIM4_CH2 TIM1_ETR
SAI1_D1
A
OUT
SPI2_MOSI
/I2S2_SD
TIM1_
CH1N
USART1_
CTS
COMP1_
OUT
FDCAN1_R
X
TIM1_
BKIN2
EVENT
OUT
PA11
-
-
-
-
-
-
-
-
-
TIM16_
CH1
TIM1_
CH2N
USART1_
RTS_DE
COMP2_
OUT
FDCAN1_T
X
EVENT
OUT
PA12
PA13
PA14
-
-
-
-
-
-
-
I2SCKIN
IR_OUT
-
-
-
-
-
-
SWDIO-
JTMS
TIM16_
CH1N
USART3_
CTS
SAI1_SD_
B
EVENT
OUT
I2C1_SCL
I2C1_SDA
-
-
-
-
-
TIM4_CH3
-
-
-
SWCLK-
JTCK
LPTIM1_
OUT
USART2_
TX
EVENT
OUT
TIM8_CH2 TIM1_BKIN
SAI1_FS_B
TIM2_
CH1
SPI3_NSS/
SPI1_NSS
USART2_
RX
UART4_
RTS_DE
EVENT
OUT
PA15
JTDI
TIM8_CH1
-
I2C1_SCL
TIM1_BKIN
-
-
-
-
TIM2_ETR
I2S3_WS
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/
I2S2/3/
UART4
/TIM8/Infra
red
I2C3/4
/UART4/
LPUART1/
GPCOMP1/
2/3
I2C3/SAI1/
USB/TIM8/
15/
SPI2/3/
I2S2/3/
TIM1/8/
Infrared
Port
LPTIM1/TI I2C3/TIM1/
I2C1/2/3/
TIM1/8/16/
17
LPTIM1/TI
M1/8/FDCA
N1
UART4/SAI
1/TIM2/15/ EVENT
UCPD1
USART1/2/
3
TIM1/8/15/ TIM2/3/4/8/
LPUART1/
SAI1/TIM1
SAI1/
OPAMP2
SYS_AF
M2/5/15/1
6/17
2/3/4/8/15/
GPCOMP1
FDCAN1
17
GPCOMP3
TIM8_
CH2N
TIM1_
CH2N
UCPD1_FR EVENT
PB0
-
-
-
TIM3_CH3
TIM3_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
STX
OUT
TIM8_
CH3N
TIM1_
CH3N
COMP4_
OUT
LPUART1_
RTS_DE
EVENT
OUT
PB1
PB2
-
-
LPTIM1_
OUT
I2C3_
SMBA
EVENT
OUT
RTC_OUT2
-
-
-
-
-
-
JTDO-
TRACESWO
TIM2_
CH2
USB_CRS_
SYNC
TIM8_
CH1N
SPI3_SCK/
I2S3_CK
USART2_
TX
SAI1_SCK EVENT
PB3
PB4
PB5
TIM4_ETR
TIM3_CH1
TIM3_CH2
SPI1_SCK
-
-
-
-
TIM3_ETR
-
-
-
-
-
_B
OUT
TIM16_
CH1
TIM8_
CH2N
USART2_
RX
TIM17_
BKIN
SAI1_
MCLK_B
EVENT
OUT
JTRST
-
-
SPI1_MISO SPI3_MISO
-
TIM16_
BKIN
TIM8_
CH3N
I2C1_
SMBA
SPI3_MOSI USART2_
/I2S3_SD
TIM17_
CH1
LPTIM1_
IN1
SAI1_SD_
B
EVENT
OUT
SPI1_MOSI
I2C3_SDA
-
CK
TIM16_
CH1N
USART1_
TX
COMP4_
OUT
TIM8_
BKIN2
LPTIM1_
ETR
EVENT
OUT
PB6
PB7
-
-
-
-
-
-
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
-
-
TIM8_CH1 TIM8_ETR
-
-
-
-
-
-
-
-
-
SAI1_FS_B
TIM17_
CH1N
USART1_
RX
COMP3_
OUT
LPTIM1_
IN2
UART4_
CTS
EVENT
OUT
-
I2C1_SDA TIM8_BKIN
-
TIM3_CH4
-
TIM16_
CH1
USART3_
RX
COMP1_
OUT
FDCAN1_R
X
SAI1_
MCLK_A
EVENT
OUT
PB8
SAI1_CK1
I2C1_SCL
-
-
-
-
-
TIM8_CH2
-
-
-
-
TIM1_BKIN
TIM17_
CH1
USART3_
TX
COMP2_
OUT
FDCAN1_T
X
TIM1_
CH3N
EVENT
OUT
PB9
SAI1_D2
I2C1_SDA
IR_OUT
TIM8_CH3
SAI1_FS_A
TIM2_
CH3
USART3_
TX
LPUART1_
RX
SAI1_
SCK_A
EVENT
OUT
PB10
PB11
-
-
-
-
-
-
-
-
-
-
TIM1_BKIN
-
TIM2_
CH4
USART3_
RX
LPUART1_
TX
EVENT
OUT
-
-
-
I2C2_
SMBA
SPI2_NSS/
I2S2_WS
USART3_
CK
LPUART1_
RTS_DE
EVENT
OUT
PB12
-
-
-
-
-
TIM1_BKIN
-
-
-
-
-
SPI2_SCK/
I2S2_CK
TIM1_
CH1N
USART3_
CTS
LPUART1_
CTS
EVENT
OUT
PB13
PB14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM15_
CH1
TIM1_
CH2N
USART3_
RTS_DE
COMP4_
OUT
EVENT
OUT
SPI2_MISO
TIM15_
CH2
TIM15_
CH1N
COMP3_
OUT
TIM1_
CH3N
SPI2_MOSI
/I2S2_SD
EVENT
OUT
PB15 RTC_REFIN
-
-
-
-
-
-
-
-
-
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/
I2S2/3/
UART4
/TIM8/Infra
red
I2C3/4
/UART4/
LPUART1/
GPCOMP1/
2/3
I2C3/SAI1/
USB/TIM8/
15/
SPI2/3/
I2S2/3/
TIM1/8/
Infrared
Port
LPTIM1/TI I2C3/TIM1/
I2C1/2/3/
TIM1/8/16/
17
LPTIM1/TI
M1/8/FDCA
N1
UART4/SAI
1/TIM2/15/ EVENT
UCPD1
USART1/2/
3
TIM1/8/15/ TIM2/3/4/8/
LPUART1/
SAI1/TIM1
SAI1/
OPAMP2
SYS_AF
M2/5/15/1
6/17
2/3/4/8/15/
GPCOMP1
FDCAN1
17
GPCOMP3
LPTIM1_
IN1
LPUART1_
RX
EVENT
-
PC0
-
-
-
-
-
-
-
-
-
-
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OUT
LPTIM1_
OUT
LPUART1_
TX
SAI1_SD_
A
EVENT
-
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
-
-
OUT
LPTIM1_
IN2
COMP3_
OUT
EVENT
-
-
-
-
-
OUT
LPTIM1_
ETR
TIM1_
BKIN2
SAI1_SD_
A
EVENT
-
SAI1_D1
-
-
-
OUT
USART1_
TX
EVENT
-
-
-
-
-
-
-
-
I2C2_SCL
-
-
-
-
-
-
-
-
-
-
OUT
TIM15_
BKIN
TIM1_
CH4N
USART1_
RX
EVENT
-
SAI1_D3
-
-
OUT
TIM8_
CH1
EVENT
-
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
-
-
-
-
-
I2S2_MCK
I2S3_MCK
-
-
-
-
-
-
OUT
TIM8_
CH2
EVENT
-
-
-
OUT
TIM8_
CH3
EVENT
-
-
I2C3_SCL
I2C3_SDA
OUT
TIM8_
CH4
TIM8_
BKIN2
EVENT
-
I2SCKIN
OUT
TIM8_
CH1N
SPI3_SCK/
I2S3_CK
USART3_
TX
EVENT
OUT
PC10
PC11
PC12
-
-
-
-
-
-
-
-
-
-
-
-
UART4_TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_
CH2N
USART3_
RX
EVENT
-
UART4_RX SPI3_MISO
I2C3_SDA
-
OUT
TIM8_
CH3N
SPI3_MOSI USART3_
/I2S3_SD
UCPD1_
FRSTX
EVENT
OUT
-
CK
TIM1_
CH1N
TIM8_
CH4N
EVENT
OUT
PC13
PC14
PC15
-
-
-
-
-
-
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/
I2S2/3/
UART4
/TIM8/Infra
red
I2C3/4
/UART4/
LPUART1/
GPCOMP1/
2/3
I2C3/SAI1/
USB/TIM8/
15/
SPI2/3/
I2S2/3/
TIM1/8/
Infrared
Port
LPTIM1/TI I2C3/TIM1/
I2C1/2/3/
TIM1/8/16/
17
LPTIM1/TI
M1/8/FDCA
N1
UART4/SAI
1/TIM2/15/ EVENT
UCPD1
USART1/2/
3
TIM1/8/15/ TIM2/3/4/8/
LPUART1/
SAI1/TIM1
SAI1/
OPAMP2
SYS_AF
M2/5/15/1
6/17
2/3/4/8/15/
GPCOMP1
FDCAN1
17
GPCOMP3
TIM8_
CH4N
FDCAN1_R
X
EVENT
-
PD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OUT
TIM8_
BKIN2
FDCAN1_T
X
EVENT
-
PD1
PD2
-
TIM8_CH4
TIM8_BKIN
OUT
EVENT
-
TIM3_ETR
-
-
OUT
TIM2_CH1/
TIM2_ETR
USART2_
CTS
EVENT
OUT
PD3
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_
RTS_DE
EVENT
-
PD4
PD5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM2_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OUT
USART2_
TX
EVENT
-
-
-
-
OUT
USART2_
RX
SAI1_SD_
A
EVENT
-
PD6
TIM2_CH4
SAI1_D1
-
OUT
USART2_
CK
EVENT
-
PD7
TIM2_CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OUT
USART3_
TX
EVENT
-
PD8
-
-
OUT
USART3_
RX
EVENT
-
PD9
-
-
OUT
USART3_
CK
EVENT
-
PD10
PD11
PD12
PD13
PD14
PD15
-
-
OUT
USART3_
CTS
EVENT
-
-
-
OUT
USART3_
RTS_DE
EVENT
-
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
OUT
EVENT
-
-
-
-
-
OUT
EVENT
-
-
OUT
EVENT
-
SPI2_NSS
OUT
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/
I2S2/3/
UART4
/TIM8/Infra
red
I2C3/4
/UART4/
LPUART1/
GPCOMP1/
2/3
I2C3/SAI1/
USB/TIM8/
15/
SPI2/3/
I2S2/3/
TIM1/8/
Infrared
Port
LPTIM1/TI I2C3/TIM1/
I2C1/2/3/
TIM1/8/16/
17
LPTIM1/TI
M1/8/FDCA
N1
UART4/SAI
1/TIM2/15/ EVENT
UCPD1
USART1/2/
3
TIM1/8/15/ TIM2/3/4/8/
LPUART1/
SAI1/TIM1
SAI1/
OPAMP2
SYS_AF
M2/5/15/1
6/17
2/3/4/8/15/
GPCOMP1
FDCAN1
17
GPCOMP3
TIM16_
CH1
USART1_
TX
EVENT
-
PE0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM4_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OUT
TIM17_
CH1
USART1_
RX
EVENT
-
PE1
PE2
-
-
OUT
TIM3_
CH1
SAI1_
MCLK_A
EVENT
-
TRACECK
SAI1_CK1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OUT
TIM3_
CH2
SAI1_
SD_B
EVENT
-
PE3
TRACED0
-
OUT
TIM3_
CH3
SAI1_
FS_A
EVENT
-
PE4
TRACED1
SAI1_D2
OUT
TIM3_
CH4
SAI1_
SCK_A
EVENT
-
PE5
TRACED2
SAI1_CK2
OUT
SAI1_
SD_A
EVENT
-
PE6
TRACED3
-
SAI1_D1
OUT
TIM1_
ETR
SAI1_
SD_B
EVENT
-
PE7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OUT
TIM1_
CH1N
SAI1_
SCK_B
EVENT
-
PE8
OUT
TIM1_
CH1
SAI1_
FS_B
EVENT
-
PE9
OUT
TIM1_
CH2N
SAI1_
MCLK_B
EVENT
-
PE10
PE11
PE12
PE13
PE14
PE15
OUT
TIM1_
CH2
EVENT
-
-
-
-
-
-
OUT
TIM1_
CH3N
EVENT
-
OUT
TIM1_
CH3
EVENT
-
OUT
TIM1_
CH4
TIM1_
BKIN2
EVENT
-
OUT
TIM1_
BKIN
TIM1_
CH4N
USART3_
RX
EVENT
-
OUT
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SPI1/2/3/
I2S2/3/
UART4
/TIM8/Infra
red
I2C3/4
/UART4/
LPUART1/
GPCOMP1/
2/3
I2C3/SAI1/
USB/TIM8/
15/
SPI2/3/
I2S2/3/
TIM1/8/
Infrared
Port
LPTIM1/TI I2C3/TIM1/
I2C1/2/3/
TIM1/8/16/
17
LPTIM1/TI
M1/8/FDCA
N1
UART4/SAI
1/TIM2/15/ EVENT
UCPD1
USART1/2/
3
TIM1/8/15/ TIM2/3/4/8/
LPUART1/
SAI1/TIM1
SAI1/
OPAMP2
SYS_AF
M2/5/15/1
6/17
2/3/4/8/15/
GPCOMP1
FDCAN1
17
GPCOMP3
I2C2_
SDA
SPI2_NSS/
I2S2_WS
TIM1_
CH3N
EVENT
-
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OUT
SPI2_SCK/
I2S2_CK
EVENT
-
PF1
PF2
-
-
-
-
-
-
-
OUT
I2C2_
SMBA
EVENT
-
-
-
-
OUT
EVENT
-
PF9
TIM15_CH1
TIM15_CH2
-
-
SPI2_SCK
SPI2_SCK
SAI1_FS_B
SAI1_D3
OUT
EVENT
-
PF10
OUT
EVENT
OUT
PG10
MCO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 14.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 15.
Figure 14. Pin loading conditions
Figure 15. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
MS19211V1
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
5.1.6
Power supply scheme
Figure 16. Power supply scheme
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
VDD
VCORE
n x VDD
Regulator
VDDIO
OUT
Kernel logic
(CPU, Digital
& Memories)
IO
logic
n x 100 nF
+1 x 4.7 μF
GPIOs
IN
n x VSS
Reset block
VDDA
VDDA
Temp. sensor
PLL, HSI16, HSI48
VREF+
VREF+
VREF
ADCs/
Standby circuitry
(Wakeup logic,
IWDG)
DACs/
10 nF
+1 μF
OPAMPs/
COMPs/
VREFBUF
VREF-
100 nF +1 μF
VSSA
MS60206V1
Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
68/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
5.1.7
Current consumption measurement
Figure 17. Current consumption measurement
IDD_VBAT
VBAT
IDD
VDD
IDDA
VDDA
MS60200V1
The I
parameters given in Table 21 to Table 24 represent the total MCU consumption
DD_ALL
including the current supplying V , V
and V
.
DD
DDA
BAT
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
(1)
Table 14. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
VDD - VSS
-0.3
4.0
VDDA, VBAT and VREF+
)
min (VDD, VDDA
)
Input voltage on FT_xxx pins except FT_c pins
VSS-0.3
+ 4.0(3)(4)
V
(2)
Input voltage on FT_c pins
Input voltage on TT_xx pins
Input voltage on any other pins
VSS-0.3
VSS-0.3
VSS-0.3
5.5
4.0
4.0
VIN
Variations between different VDDX power pins of
the same domain
|∆VDDx
|
-
50
mV
V
|VSSx-VSS
|
Variations between all the different ground pins(5)
-
-
50
V
REF+-VDDA Allowed voltage difference for VREF+ > VDDA
0.4
1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supply, in the permitted range.
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
2. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 15. Current characteristics
Symbol
Ratings
Max
Unit
∑IVDD
∑IVSS
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
150
150
100
100
20
IVDD(PIN) Maximum current into each VDD power pin (source)(1)
IVSS(PIN)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin except FT_f
Output current sunk by any FT_f pin
IIO(PIN)
20
mA
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT_xxx, TT_xx, NRST pins
20
100
100
-5/0(4)
±25
∑IIO(PIN)
(3)
IINJ(PIN)
∑|IINJ(PIN)
|
Total injected current (sum of all I/Os and control pins)(5)
1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14:
Voltage characteristics for the minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
Table 16. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
70/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
5.3
Operating conditions
5.3.1
General operating conditions
Table 17. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
Internal AHB clock frequency
-
-
-
0
0
0
170
170
170
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
MHz
VDD
Standard operating voltage
Analog supply voltage
-
1.71(1)
3.6
V
V
ADC or COMP used
DAC 1 MSPS or DAC 15 MSPS
OPAMP used
1.62
1.71
2.0
3.6
3.6
VDDA
VREFBUF used
2.4
3.6
ADC, DAC, OPAMP, COMP,
VREFBUF not used
0
VBAT
Backup operating voltage
I/O input voltage
-
TT_xx I/O
1.55
-0.3
-0.3
3.6
DD+0.3
5
V
V
V
FT_c I/O
VIN
MIN(MIN(VDD
VDDA)+3.6 V,
5.5 V)(2)(3)
,
All I/O except TT_xx and FT_c
-0.3
See Section 6.10: Thermal characteristics for application
appropriate thermal resistance and package.
PD
Power dissipation
mW
Power dissipation is then calculated according ambient
temperature (TA) and maximum junction temperature (TJ) and
selected thermal resistance.
Maximum power dissipation
Low-power dissipation(4)
Maximum power dissipation
Low-power dissipation(4)
Suffix 6 version
-40
-40
-40
-40
-40
-40
85
Ambient temperature for the
suffix 6 version
105
125
130
105
130
TA
°C
°C
Ambient temperature for the
suffix 3 version
TJ
Junction temperature range
Suffix 3 version
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6.10:
Thermal characteristics).
DS12589 Rev 3
71/197
160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 18 are derived from tests performed under the ambient
temperature condition summarized in Table 17.
Table 18. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
VDD fall time rate
VDDA rise time rate
VDDA fall time rate
0
10
0
∞
∞
∞
∞
tVDD
-
µs/V
tVDDA
-
µs/V
10
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 19 are derived from tests performed under the ambient
temperature conditions summarized in Table 17: General operating conditions.
Table 19. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Reset temporization after
BOR0 is detected
(2)
tRSTTEMPO
VDD rising
-
250
400
μs
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.62
1.6
1.66
1.64
2.1
1.7
(2)
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
V
V
V
V
V
V
V
V
V
1.69
2.14
2.04
2.35
2.24
2.66
2.57
2.95
2.86
2.19
2.1
2.06
1.96
2.26
2.16
2.56
2.47
2.85
2.76
2.1
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
2
2.31
2.20
2.61
2.52
2.90
2.81
2.15
2.05
2.31
2.20
2.46
2.36
2.61
2.52
Programmable voltage
detector threshold 0
2
2.26
2.15
2.41
2.31
2.56
2.47
2.36
2.25
2.51
2.41
2.66
2.57
PVD threshold 1
PVD threshold 2
PVD threshold 3
72/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
Table 19. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.69
2.59
2.85
2.75
2.92
2.84
2.74
2.64
2.91
2.81
2.98
2.90
2.79
2.69
2.96
2.86
3.04
2.96
VPVD4
PVD threshold 4
V
VPVD5
PVD threshold 5
PVD threshold 6
V
V
VPVD6
Hysteresis in
continuous
mode
-
20
-
Vhyst_BORH0 Hysteresis voltage of BORH0
mV
Hysteresis in
other mode
-
-
-
30
100
1.1
-
-
Hysteresis voltage of BORH
Vhyst_BOR_PVD
-
-
mV
µA
(except BORH0) and PVD
IDD
BOR(3) (except BOR0) and
1.6
(BOR_PVD)(2) PVD consumption from VDD
Rising edge
Falling edge
Rising edge
Falling edge
-
1.61
1.6
1.78
1.77
-
1.65
1.64
1.82
1.81
10
1.69
1.68
1.86
1.85
-
VDDA peripheral voltage
VPVM1
V
V
monitoring (COMP/ADC)
VDDA peripheral voltage
VPVM2
monitoring (OPAMP/DAC)
Vhyst_PVM1
Vhyst_PVM2
IDD
PVM1 hysteresis
PVM2 hysteresis
mV
mV
-
-
10
-
PVM1 and PVM2
consumption from VDD
(PVM1/PVM2)
-
-
2
-
µA
(2)
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
5.3.4
Embedded voltage reference
The parameters given in Table 20 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 17: General operating
conditions.
Table 20. Embedded internal voltage reference
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference
voltage
VREFINT
–40 °C < TA < +130 °C 1.182 1.212 1.232
V
ADC sampling time
when reading the
internal reference
voltage
(1)
tS_vrefint
-
-
-
4(2)
-
8
-
µs
µs
Start time of reference
voltage buffer when
ADC is enable
tstart_vrefint
-
-
-
12(2)
20(2)
7.5(2)
VREFINT buffer
consumption from VDD
DD(VREFINTBUF) when converted by
ADC
12.5
µA
mV
I
Internal reference
voltage spread over
ꢀVREFINT
VDD = 3 V
5
the temperature range
Average temperature
coefficient
TCoeff
ACoeff
–40°C < TA < +130°C
1000 hours, T = 25°C
3.0 V < VDD < 3.6 V
-
-
-
30
50(2) ppm/°C
Long term stability
300 1000(2)
ppm
Average voltage
coefficient
VDDCoeff
250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
-
VREFINT
1. The shortest sampling time is determined in the application by multiple iterations.
2. Guaranteed by design.
74/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
Figure 18. V
versus temperature
REFINT
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
°C
-40
-20
0
20
Mean
40
60
80
100
120
Min
Max
MSv40169V2
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in Figure 17: Current consumption
measurement.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the f
frequency (refer to the table “number of wait states according
HCLK
to CPU clock (HCLK) frequency” available in the reference manual RM0440
®
"STM32G4 Series advanced Arm -based 32-bit MCUs").
•
•
When the peripherals are enabled f
= f
PCLK HCLK
The voltage scaling Range 1 is adjusted to f
frequency as follows:
HCLK
–
–
Voltage Range 1 Boost mode for 150 MHz < f
≤ 170 MHz
≤ 150 MHz
HCLK
Voltage Range 1 Normal mode for 26 MHz < f
HCLK
The parameters given in Table 21 to Table 24 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 17: General
operating conditions.
DS12589 Rev 3
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160
Table 21. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
Condition
Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 3.20 3.35 3.60 4.15
16 MHz 2.05 2.15 2.50 3.05
5.05 3.90 4.90 7.40
11.0
15.0
14.0
13.0
13.0
12.0
12.0
12.0
3.95 2.70 3.70 6.10 9.30
3.05 1.70 2.60 5.10 8.30
2.60 1.10 2.10 3.60 7.60
2.35 0.840 1.90 3.40 7.40
2.25 0.710 1.70 3.20 7.30
2.15 0.590 1.60 3.10 1.00
8 MHz
1.10 1.25 1.60 2.10
Range 2 4 MHz 0.635 0.755 1.15 1.65
2 MHz 0.400 0.525 0.910 1.45
1 MHz 0.280 0.415 0.800 1.35
100 KHz 0.170 0.305 0.690 1.20
Range 1
fHCLK = fHSE up to
48 MHz included,
Supply current bypass mode PLL
Boost
mode
170 MHz 25.5 26.0 27.0 27.5
29.0 28.0 29.0 33.0 38.0
44.0
IDD (Run)
mA
in Run mode
ON above 48 MHz
all peripherals
disable
150 MHz 21.0 21.5 22.0 23.0
120 MHz 17.0 17.5 18.0 18.5
80 MHz 11.5 11.5 12.5 13.0
24.0 23.0 24.0 28.0 32.0
20.0 19.0 20.0 24.0 28.0
14.0 13.0 14.0 18.0 22.0
13.0 12.0 13.0 17.0 21.0
38.0
33.0
27.0
26.0
25.0
23.0
20.0
19.0
18.0
72 MHz 10.5 10.5 11.0
Range 1 64 MHz 9.30 9.50 10.0
12.0
11.0
12.0
9.30 8.10 9.40 13.0 17.0
7.10 5.80 7.10 11.0 15.0
11.0 12.0 15.0 20.0
48 MHz 6.95 7.15 7.45 8.15
32 MHz 4.70 4.90 5.25 5.95
24 MHz 3.60 3.80 4.20 4.85
16 MHz 2.45 2.65 3.10 3.75
6.00 4.60 5.90 9.20 14.0
4.90 3.40 4.70 8.00 13.0
Table 21. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) (continued)
Condition
Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
1 MHz
350
255
525
410
300
990 1600 2650 970 2200 3900 6700 11000
860 1500 2550 830 2100 3800 6600 11000
750 1400 2450 690 1900 3700 6500 11000
725 1350 2400 670 1800 3700 6500 11000
fHCLK = fHSE
all peripherals disable
250 KHz 145
Supply current
62.5 KHz 99.5 270
IDD (LPRun) in Low-power
run mode
μA
2 MHz
1 MHz
865 1050 1500 2150 3200 1600 2800 4500 7600 12000
820
965 1400 2050 3100 1500 2700 4400 7400 12000
875 1300 1950 3000 1400 2600 4400 7400 12000
860 1300 1900 2950 1300 2600 4400 7400 12000
fHCLK = fHSI / HPRE
all peripherals disable
250 KHz 725
62.5 KHz 685
Table 22. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1
Condition
Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 2.85 3.00 3.30 3.85
16 MHz 1.80 1.95 2.30 2.85
8 MHz 0.995 1.15 1.50 2.05
4.75 3.50 4.40 6.90
11.0
15.0
14.0
13.0
13.0
12.0
12.0
12.0
3.75 2.50 3.40 5.90 9.00
2.95 1.50 2.50 4.00 7.80
2.55 1.10 2.10 3.50 7.40
2.35 0.800 1.80 3.30 7.00
2.25 0.690 1.70 3.20 6.90
2.15 0.590 1.60 3.10 6.70
Range 2 4 MHz 0.580 0.725 1.10 1.65
2 MHz 0.370 0.510 0.900 1.45
1 MHz 0.270 0.405 0.790 1.35
100 KHz 0.170 0.310 0.695 1.25
Range 1
fHCLK = fHSE
up to 48 MHz
Supply current included, bypass
Boost
mode
170 MHz 23.0 23.5 24.0 25.0
26.5 24.0 26.0 30.0 35.0
41.0
IDD (Run)
mA
in Run mode
mode PLL ON
above 48 MHz all
peripherals disable
150 MHz 19.0 19.5 20.0 20.5
120 MHz 15.5 15.5 16.0 17.0
22.0 20.0 21.0 25.0 29.0
18.0 16.0 18.0 21.0 25.0
35.0
31.0
26.0
25.0
24.0
22.0
20.0
19.0
18.0
80 MHz 10.5 10.5 11.0
72 MHz 9.35 9.55 10.0
12.0
11.0
13.0
12.0
11.0
11.0 13.0 16.0 20.0
11.0 12.0 15.0 19.0
9.10 11.0 14.0 18.0
Range 1 64 MHz 8.35 8.55 9.15 9.85
48 MHz 6.25 6.45 6.75 7.45
32 MHz 4.25 4.45 4.80 5.50
24 MHz 3.25 3.45 3.85 4.55
16 MHz 2.25 2.40 2.85 3.55
8.65 7.10 8.40 12.0 16.0
6.65 5.20 6.50 9.80 14.0
5.65 4.20 5.40 8.70 13.0
4.70 3.00 4.40 7.40 12.0
Table 22. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 (continued)
Condition
Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
1 MHz
350
210
495
370
275
965 1600 2650 900 2100 3900 6700 12000
845 1500 2550 780 2000 3800 6600 11000
755 1400 2450 680 1900 3700 6800 12000
725 1350 2400 630 1800 3600 6400 11000
fHCLK = fHSE
all peripherals disable
250 KHz 115
Supply current
62.5 KHz 98.0 255
IDD (LPRun) in Low-power
run mode
μA
2 MHz
1 MHz
850 1000 1500 2100 3150 1500 2700 4500 7500 12000
770
900 1400 2000 3050 1500 2700 4500 7600 13000
840 1300 1950 3000 1400 2600 4400 7300 12000
830 1300 1900 2950 1400 2600 4400 7300 12000
fHCLK = fHSI / HPRE
all peripherals disable
250 KHz 720
62.5 KHz 665
Table 23. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF)
TYP
TYP
Conditions
Single Bank
Mode
Single Bank
Mode
Symbol
Parameter
Code
Unit
Unit
-
Voltage scaling
25°C
25°C
Pseudo-dhrystone
Coremark
3.20
3.15
3.20
3.60
3.00
21.0
21.0
21.0
23.5
20.0
25.5
25.0
26.0
28.5
24.5
865
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
123
121
123
138
115
140
140
140
157
133
150
147
153
168
144
433
428
438
453
435
Range2
fHCLK=26MHz
Dhrystone2.1
Fibonacci
µA/MHz
While(1)
Pseudo-dhrystone
Coremark
fHCLK= fHSE up to 48
MHZ included, bypass
mode PLL ON above
48 MHz all peripherals
disable
IDD
(Run)
Supply current
in Run mode
Range 1
fHCLK= 150 MHz
Dhrystone2.1
Fibonacci
µA/MHz
µA/MHz
µA/MHz
While(1)
Pseudo-dhrystone
Coremark
Range 1
Boost mode
Dhrystone2.1
Fibonacci
fHCLK= 170 MHz
While(1)
Pseudo-dhrystone
Coremark
855
µA
Supply current SYSCLK source is HSI
IDD
(LPRun)
in Low-power
run
fHCLK = 2 MHz
all peripherals disable
Dhrystone2.1
Fibonacci
875
µA
905
µA
While(1)
870
µA
Table 24. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1
Conditions
TYP 25°C
TYP 25°C
Single
bank
mode
Symbol
Parameter
Code
Unit
Unit
Single bank
mode
-
Voltage scaling
Pseudo-dhrystone
Coremark
2.85
2.95
2.85
2.85
3.05
19.0
19.5
19.0
20.5
18.5
23.0
24.0
23.0
24.5
22.0
850
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
110
113
110
110
117
127
130
127
137
123
135
141
135
144
129
425
435
420
428
410
Range2
fHCLK=26 MHz
Dhrystone2.1
Fibonacci
µA/MHz
While(1)
Pseudo-dhrystone
Coremark
fHCLK = fHSE up to 48 MHZ
Supply current in included, bypass mode
Range 1
fHCLK= 150 MHz
IDD (Run)
Dhrystone2.1
Fibonacci
µA/MHz
µA/MHz
µA/MHz
Run mode
PLL ON above 48 MHz all
peripherals disable
While(1)
Pseudo-dhrystone
Coremark
Range 1
Boost mode
fHCLK= 170 MHz
Dhrystone2.1
Fibonacci
While(1)
Pseudo-dhrystone
Coremark
870
µA
SYSCLK source is HSI
fHCLK = 2 MHz
all peripherals disable
IDD
Supply current in
Low-power run
Dhrystone2.1
Fibonacci
840
µA
(LPRun)
855
µA
While(1)
820
µA
Table 25. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM2
Conditions
TYP 25°C
TYP 25°C
Single
bank
mode
Symbol
Parameter
Code
Unit
Unit
Single bank
mode
-
Voltage scaling
Pseudo-dhrystone
Coremark
2.40
2.50
2.40
2.35
2.25
15.5
16.5
15.5
15.5
14.5
19.0
20.0
19.0
19.0
18.0
835
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
92
96
Range2
fHCLK=26 MHz
Dhrystone2.1
Fibonacci
92
µA/MHz
90
While(1)
87
Pseudo-dhrystone
Coremark
103
110
103
103
97
fHCLK = fHSE up to 48 MHZ
Supply current in included, bypass mode
Range 1
IDD (Run)
Dhrystone2.1
Fibonacci
µA/MHz
µA/MHz
µA/MHz
Run mode
PLL ON above 48 MHz all fHCLK= 150 MHz
peripherals disable
While(1)
Pseudo-dhrystone
Coremark
112
118
112
112
106
418
413
415
415
408
Range 1
Boost mode
Dhrystone2.1
Fibonacci
fHCLK= 170 MHz
While(1)
Pseudo-dhrystone
Coremark
825
µA
SYSCLK source is HSI
fHCLK = 2 MHz
all peripherals disable
IDD
Supply current in
Low-power run
Dhrystone2.1
Fibonacci
830
µA
(LPRun)
830
µA
While(1)
815
µA
Table 26. Typical current consumption in Run and Low-power run modes, with different codes
running from CCM
Conditions
TYP 25°C
TYP 25°C
Single
bank
mode
Symbol
Parameter
Code
Unit
Unit
Single bank
mode
-
Voltage scaling
Pseudo-dhrystone
Coremark
2.65
2.80
2.65
3.25
3.25
17.5
19.0
17.5
21.5
21.5
21.5
23.0
21.5
26.0
26.0
845
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
102
108
102
125
125
117
127
117
143
143
126
135
126
153
153
423
413
410
443
445
Range2
fHCLK=26 MHz
Dhrystone2.1
Fibonacci
µA/MHz
While(1)
Pseudo-dhrystone
Coremark
fHCLK = fHSE up to 48 MHZ
Supply current in included, bypass mode
Range 1
IDD (Run)
Dhrystone2.1
Fibonacci
µA/MHz
µA/MHz
µA/MHz
Run mode
PLL ON above 48 MHz all fHCLK= 150 MHz
peripherals disable
While(1)
Pseudo-dhrystone
Coremark
Range 1
Boost mode
Dhrystone2.1
Fibonacci
f
HCLK= 170 MHz
While(1)
Pseudo-dhrystone
Coremark
825
µA
SYSCLK source is HSI
fHCLK = 2 MHz
all peripherals disable
IDD
Supply current in
Low-power run
Dhrystone2.1
Fibonacci
820
µA
(LPRun)
885
µA
While(1)
890
µA
Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON
Condition Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz 1.05 1.15 1.45 2.00
16 MHz 0.690 0.810 1.15 1.70
8 MHz 0.425 0.545 0.920 1.45
2.90 1.70 2.70 5.20 8.30
2.60 1.30 2.30 3.80 8.00
2.35 0.930 2.00 3.50 7.70
2.25 0.760 1.80 3.30 7.60
2.20 0.670 1.70 3.20 7.50
2.15 0.620 1.60 3.10 7.50
2.15 0.580 1.60 3.10 7.40
13.0
13.0
13.0
12.0
12.0
12.0
12.0
Range 2 4 MHz 0.300 0.400 0.815 1.35
2 MHz 0.230 0.355 0.755 1.30
1 MHz 0.200 0.320 0.725 1.25
100 KHz 0.165 0.285 0.690 1.25
Range 1
fHCLK = fHSE
Boost
mode
170 MHz 7.40 7.65 8.30 9.10
10.5 8.60 11.0 14.0 19.0
25.0
up to 48 MHz
Supply current included, bypass
in Sleep mode mode PLL ON
above 48 MHz all
IDD (Sleep)
mA
150 MHz 6.10 6.30 6.90 7.60
120 MHz 4.95 5.15 5.70 6.40
80 MHz 3.45 3.65 4.15 4.85
72 MHz 3.15 3.35 3.85 4.55
8.80 7.10 8.40 12.0 16.0
22.0
21.0
19.0
19.0
18.0
18.0
17.0
17.0
16.0
peripherals disable
7.60 5.90 7.20 11.0
15.0
6.00 4.40 5.70 9.00 13.0
5.70 4.10 5.30 8.60 13.0
5.40 3.70 5.00 8.30 13.0
4.40 3.10 4.40 7.60 12.0
3.80 2.50 3.80 7.10 12.0
Range 1 64 MHz 2.85 3.00 3.55 4.25
48 MHz 2.10 2.30 2.55 3.25
32 MHz 1.50 1.65 2.00 2.70
24 MHz 1.15 1.35 1.75 2.40
16 MHz 0.850 1.05 1.45 2.15
3.55 2.20 3.40 6.70
3.25 1.80 3.10 6.30
11.0
11.0
Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON (continued)
Condition Typ Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
1 MHz
180
135
335
300
265
810 1450 2500 1600 2900 4600 7700 13000
770 1400 2450 1200 2400 4100 7100 12000
740 1350 2400 670 2000 3600 6300 11000
730 1350 2400 660 1900 3600 6300 11000
fHCLK = fHSE
all peripherals disable
250 KHz 115
Supply current
in Low-power
sleep mode
62.5 KHz 89.5 255
IDD
(LPSleep)
μA
2 MHz
1 MHz
730
675
875 1350 1950 3000 1400 2600 4300 7200 12000
830 1300 1950 3000 1400 2600 4300 7200 12000
820 1300 1950 3000 1400 2600 4300 7200 12000
850 1300 1950 3000 1400 2600 4300 7200 12000
fHCLK = fHSI / HPRE
all peripherals disable
250 KHz 655
62.5 KHz 680
Table 28. Current consumption in low-power sleep modes, Flash in power-down
Condition Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
1 MHz
175
125
290
280
240
245
805 1450 2500 750 2000 3700 6400 11000
765 1400 2450 700 2000 3700 6400 11000
735 1350 2400 670 1900 3700 6400 11000
725 1350 2400 660 1900 3700 6400 11000
fHCLK = fHSE
all peripherals
disable
-
250 KHz 105
62.5 KHz 105
Supply current
in low-power
sleep mode
IDD
(LPSleep)
μA
2 MHz
1 MHz
670
655
830 1350 1950 3000 1400 2600 4300 7200 12000
825 1300 1950 3000 1400 2600 4300 7200 12000
825 1300 1900 2950 1400 2600 4300 7100 12000
840 1300 1900 2950 1200 2200 3700 6200 11000
fHCLK = fHSI
all peripherals
disable
-
250 KHz 635
62.5 KHz 640
Table 29. Current consumption in Stop 1 mode
TYP
Conditions
-
MAX(1)
85°C
Symbol
Parameter
Unit
VDD
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
58.5
58.5
59.0
59.5
59.0
59.5
59.5
60.5
58.5
59.0
60.0
62.0
58.5
59.0
59.5
61.0
175
175
175
180
175
175
175
180
175
175
180
180
150
150
150
150
550
550
555
560
550
555
555
560
550
555
555
565
445
445
445
450
1050
1050
1050
1100
1050
1050
1050
1100
1050
1050
1050
1100
890
1900
1950
1950
1950
1950
1950
1950
1950
1900
1950
1950
1950
-
390
1200
3300
5900
11000
Supply current
in Stop 1 mode, RTC disabled
RTC disabled
390
1300
3300
5900
11000
IDD
(Stop 1)
390
1300
3300
6000
11000
390
1300
3300
6000
11000
390
1300
3300
5900
11000
390
1300
3300
5900
11000
RTC clocked by LSI
400
1300
3300
6000
11000
400
1300
3400
6000
11000
µA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IDD
(Stop 1
Supply current RTC clocked by LSE
in Stop 1 mode, bypassed at 32768
with RTC) RTC enabled Hz
RTC clocked by LSE
quartz in low drive
mode at 32768 Hz
890
-
890
-
895
-
Wakeup clock is HSI
= 16 MHz,
3.0 V
1.39
-
-
-
-
-
-
-
-
-
-
-
Supply current
IDD
(Stop 1
with RTC)
during wakeup
from
Wakeup clock is
HSI = 4 MHz,
mA
3.0 V
0.93
-
-
-
-
-
-
-
Stop 1 mode
(HPRE divider=4),
voltage Range 2
1. Guaranteed by characterization results, unless otherwise specified.
Table 30. Current consumption in Stop 0 mode
TYP
Conditions
VDD
MAX(1)
85°C
Symbol
Parameter
Unit
-
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
1.8 V
2.4 V
3 V
150
150
155
155
280
280
280
285
680
680
685
685
1200
1200
1200
1200
2100
2100
2150
2150
510
510
510
510
1400
1400
1400
1500
3600
3600
3600
3600
6400
6400
6400
6500
11000
11000
11000
12000
Supply current
in Stop 0 mode, -
RTC disabled
IDD(Stop 0)
µA
3.6 V
1. Guaranteed by characterization results, unless otherwise specified.
Table 31. Current consumption in Standby mode
Conditions
-
TYP
MAX(1)
Symbol
Parameter
Unit
VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V 92.0
2.4 V 100
205
870
2250 5600 200 900 2900 7000 18000
240
1000 2600 6450 220 1000 3300 8000 21000
1200 3050 7400 250 1100 3800 9100 23000
1550 3800 9200 330 1400 4400 11000 27000
No independent
watchdog
3 V
120
280
Supply current in Standby
mode (backup registers
retained),
3.6 V 175
1.8 V 275
2.4 V 335
385
IDD
(Standby)
nA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC disabled
With independent
watchdog
3 V
400
3.6 V 510
Table 31. Current consumption in Standby mode (continued)
Conditions
-
TYP
MAX(1)
Symbol
Parameter
Unit
VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V 490
2.4 V 630
605
765
955
1300 2650 5950 600 1300 3300 7300 18000
1550 3100 6950 770 1500 3800 8400 21000
1850 3700 8050 940 1700 4400 9700 24000
RTC clocked by
LSI, no
independent
watchdog
3 V
785
3.6 V 1000 1200 2350 4600 9950 1300 2200 5200 12000 27000
nA
1.8 V 530
2.4 V 685
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked by
LSI, with
-
-
independent
watchdog
3 V
860
Supply current in Standby
mode (backup registers
retained),
IDD
(Standby with
RTC)
3.6 V 1100
1.8 V 360
2.4 V 480
-
470
625
1100 2450 5750
1400 3000 6800
RTC enabled
RTC clocked by
LSE bypassed at
32768 Hz
3 V
3.6 V 2550 3400 5250 8000 13500
825
1100 2200 4200 8700
nA
1.8 V 355
2.4 V 455
490
605
775
990
2150 4800
RTC clocked by
LSE quartz(2) in low
drive mode
1200 2550 5550
1450 3100 6400
3 V
595
3.6 V 810
1.8 V 218
2.4 V 220
1200 2050 3900 7750
530
525
530
545
1680 3500 6900
1700 3500 7050
1650 3500 7100
1700 3600 6800
Supply current to be added in
Standby mode when SRAM2
is retained
IDD
(SRAM2)(3)
-
nA
3 V
215
3.6 V 220
Table 31. Current consumption in Standby mode (continued)
Conditions
-
TYP
VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
3 V 2.0
MAX(1)
Symbol
Parameter
Unit
IDD (wakeup Supply current during wakeup Wakeup clock is
from Standby) from Standby mode
HSI16 = 16 MHz(4)
-
-
-
-
-
-
-
-
-
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IIDD_ALL(Standby
+ RTC) + IDD_ALL(SRAM2).
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings.
Table 32. Current consumption in Shutdown mode
Conditions
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
VDD
25°C
55°C
85°C
105°C
125°C
25°C
55°C
105°C 125°C
Supply current
in Shutdown
mode (backup
registers
1.8 V
2.4 V
3 V
14.0
22.0
35.0
94.0
120
150
570
670
805
1600
1900
2200
4350
4950
5750
120
130
160
380
440
520
1900
2200
2500
5500
6200
7000
15000
17000
19000
IDD
(Shutdown)
-
nA
retained) RTC
disabled
3.6 V
74.0
245
1100
2900
7350
210
640
3000
8200
22000
Table 32. Current consumption in Shutdown mode (continued)
Conditions
VDD
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
25°C
55°C
85°C
105°C
125°C
25°C
55°C
105°C 125°C
RTC
clocked by
LSE
bypassed
at 32768
Hz
1.8 V
2.4 V
3 V
280
400
745
355
500
985
800
1050
1850
1800
2250
3400
4500
5350
7100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Supply current
in Shutdown
mode (backup
registers
retained) RTC
enabled
IDD
3.6 V
2450
3250
4850
7100
11500
-
-
-
-
-
nA
(Shutdownwith
RTC)
RTC
1.8 V
2.4 V
3 V
275
375
515
375
495
640
775
950
1650
2050
2550
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
clocked by
LSE
quartz(2) in
low drive
mode
1200
3.6 V
710
925
1750
3300
-
-
-
-
-
-
Supply current
during wakeup
from Shutdown HSI16 =
Wakeup
clock is
IDD(wakeup
from
Shutdown)
3 V
0.24
-
-
-
-
-
-
-
-
-
mA
mode
16 MHz(3)
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings.
Table 33. Current consumption in VBAT mode
Conditions
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
VBAT
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
1.8 V
2.4 V
3 V
4.00
5.00
6.00
15.0
270
385
725
21.0
24.0
28.0
54.0
275
400
865
105
120
140
240
330
490
1150
280
310
360
615
475
690
1550
685
765
865
1500
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC
disabled
3.6 V
1.8 V
2.4 V
3 V
RTC
enabled and
clocked by
LSE
-
Backup domain
supply current
IDD(VBAT)
nA
-
bypassed at
32768 Hz
3.6 V
2500
3050
3900
4700
-
-
-
-
-
-
1.8 V
2.4 V
3 V
265
355
480
675
315
415
545
870
415
530
670
865
1000
1150
1250
1700
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC
enabled and
clocked by
LSE
710
1050
1500
quartz(2)
3.6 V
1100
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 53: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC, OPAMP, COMP input pins
which should be configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This is done either by using pull-up/down resistors or by configuring the pins in
output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 35: Low-power mode wakeup timings), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
ISW = VDDIOx × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the I/O supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
C
S
INT
EXT +
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 34. The MCU is placed
under the following conditions:
•
•
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
–
–
when the peripheral is clocked on
when the peripheral is clocked off
•
•
Ambient operating temperature and supply voltage conditions summarized in Table 14:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in
Table 34. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 34. Peripheral current consumption
Range 1
Boost Mode
Low-power
run and sleep
BUS
Peripheral
Range 1 Range 2
Unit
AHB
Bus Matrix
5.31
3.21
3.10
7.48
1.61
3.70
6.10
0.31
5.00
2.95
2.86
6.97
1.50
3.47
5.66
0.32
4.07
2.45
2.37
5.74
1.24
2.86
4.64
0.26
4.97
2.68
2.59
6.43
1.34
3.27
5.33
0.38
µA/MHz
DMA1
DMA2
DMAMUX
CORDIC
FMAC
AHB1
µA/MHz
FLASH
SRAM1
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
Table 34. Peripheral current consumption (continued)
Range 1
Boost Mode
Low-power
run and sleep
BUS
Peripheral
Range 1 Range 2
Unit
CRC
1.11
1.00
0.55
0.56
0.35
0.59
0.46
0.38
0.32
0.70
6.72
0.61
5.57
5.67
3.63
1.06
79.97
0.47
10.84
9.32
8.60
2.88
2.72
0.65
3.72
0.77
4.96
5.33
3.45
1.51
3.86
1.47
1.05
0.91
0.50
0.51
0.33
0.55
0.43
0.36
0.31
0.66
6.27
0.59
5.17
5.30
3.37
1.00
74.54
0.37
10.04
8.65
8.00
2.69
2.53
0.62
3.49
0.74
4.63
4.98
3.23
1.40
3.62
1.36
0.86
0.73
0.41
0.42
0.26
0.45
0.36
0.29
0.26
0.55
5.17
0.46
4.40
NA
0.90
0.93
0.54
0.43
0.26
0.41
0.31
0.26
0.25
0.55
5.95
0.56
4.99
NA
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
AHB2
CCMSRAM
µA/MHz
µA/MHz
µA/MHz
SRAM2
ADC12 AHB clock domain
ADC12 independent clock domain
DAC1
DAC3
RNG clock domain
NA
Na
RNG independent clock domain
NA
NA
AHB
ALL AHB peripherals
57.83
0.32
8.21
7.10
6.61
2.22
2.09
0.50
2.92
0.60
3.82
4.09
2.65
1.17
2.97
1.12
66.98
0.08
9.31
8.02
7.53
2.66
2.41
0.57
3.73
0.71
4.33
4.67
2.95
1.38
3.49
1.18
AHB to APB1 bridge
TIM2
TIM3
TIM4
TIM6
TIM7
CRS
APB1
RTC
WWDG
SPI2
SPI3
I2S2 clock domain
I2S2 independent clock domain
I2S3 clock domain
I2S3 independent clock domain
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DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
Table 34. Peripheral current consumption (continued)
Range 1
Boost Mode
Low-power
run and sleep
BUS
Peripheral
Range 1 Range 2
Unit
USART2 clock domain
3.57
7.93
3.50
7.69
3.30
6.53
1.69
3.95
1.69
4.04
0.57
1.19
9.52
4.82
1.26
1.68
2.48
1.52
4.38
2.42
3.36
7.36
3.29
7.14
3.10
6.06
1.60
3.68
1.60
3.76
0.55
1.10
8.90
4.48
1.19
1.59
2.30
1.45
4.05
2.29
2.76
6.10
2.68
5.94
2.54
5.02
1.31
3.05
1.31
3.11
0.44
5.28
7.32
3.70
0.96
1.30
1.92
1.17
3.38
1.87
3.22
6.84
3.12
6.71
2.91
5.61
1.53
3.47
1.53
3.58
0.51
NA
USART2 independent clock domain
USART3 clock domain
USART3 independent clock domain
UART4 clock domain
UART4 independent clock domain
I2C1 clock domain
I2C1 independent clock domain
I2C2 clock domain
I2C2 independent clock domain
USB clock domain
USB independent clock domain
FDCAN clock domain
8.29
4.37
1.04
1.53
2.19
1.43
3.68
2.15
APB1
µA/MHz
FDCAN independent clock domain
PWR
I2C3 clock domain
I2C3 independent clock domain
LPTIM1 clock domain
LPTIM1 independent clock domain
LPUART1 clock domain
LPUART1 independent clock
domain
4.65
4.30
3.59
4.14
ALL APB1 on
138.92
0.43
129.50
0.36
105.42
0.30
120.34
0.19
3.24
NA
AHB to APB2 bridge
UCPD clock domain
UCPD independent clock domain
3.67
3.42
2.82
1.28
1.20
5.73
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
Table 34. Peripheral current consumption (continued)
Range 1
Boost Mode
Low-power
run and sleep
BUS
Peripheral
Range 1 Range 2
Unit
SYSCFG/VREFBUF/COMP
1.94
12.00
2.47
1.81
11.16
2.32
1.49
9.20
1.92
8.93
2.18
5.38
1.92
4.61
3.20
3.33
2.36
2.35
52.90
179.05
1.82
10.41
2.18
TIM1
SPI1
TIM8
11.65
2.84
10.83
2.65
10.17
2.48
USART1 clock domain
USART1 independent clock domain
SPI4
7.01
6.53
6.17
2.47
2.32
2.18
APB2
µA/MHz
TIM15
6.00
5.57
5.26
TIM16
4.18
3.89
3.57
TIM17
4.37
4.06
3.76
SAI1 clock domain
SAI1 independent clock domain
ALL APB2 on
3.08
2.88
2.79
3.07
2.84
2.63
62.79
250.00
58.41
210.44
53.64
225.00
ALL peripherals
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Electrical characteristics
5.3.6
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 35 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
(1)
Table 35. Low-power mode wakeup timings
Symbol
tWUSLEEP
Parameter
Conditions
Typ
Max
Unit
Wakeup time from Sleep
mode to Run mode
-
11
12
Nb of
CPU
Wakeup time from Low-
cycles
tWULPSLEEP power sleep mode to Low-
power run mode
-
10
11
Range 1
Range 2
Range 1
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
5.8
18.4
2.8
6
19.1
3
Wake up time from Stop 0
mode to Run mode in Flash
tWUSTOP0
Wake up time from Stop 0
mode to Run mode in
SRAM1
Range 2
Wakeup clock HSI16 = 16 MHz
2.9
3
Range 1
Range 2
Range 1
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
9.5
21.9
6.6
9.8
22.7
6.9
Wake up time from Stop 1
mode to Run in Flash
Wake up time from Stop 1
mode to Run mode in
SRAM1
Range 2
Wakeup clock HSI16 = 16 MHz
6.4
6.6
tWUSTOP1
Wake up time from Stop 1
27.1(2)
mode to Low-power run
mode in Flash
26.1
Regulator in
low-power
Wakeup clock
HSI16 = 16 MHz,
with HPRE = 8
µs
mode (LPR=1
in PWR_CR1)
Wake up time from Stop 1
mode to Low-power run
mode in SRAM1
15(2)
14.4
Wakeup time from Standby
tWUSTBY
Range 1
Range 1
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
29.7
29.7
33.8
33.5
mode to Run mode
tWUSTBY
Wakeup time from Standby
with SRAM2 to Run mode
SRAM2
Wakeup time from
tWUSHDN Shutdown mode to Run
mode
274.6(2)
Range 1
Wakeup clock HSI16 = 16 MHz
267.9
5
Wakeup time from Low-
Wakeup clock HSI16 = 16 MHz
HPRE = 8
tWULPRUN
power run mode to Run
7
mode(3)
1. Guaranteed by characterization results.
2. Characterization results for temperature range from 0°C to 125°C
3. Time until REGLPF flag is cleared in PWR_SR2.
DS12589 Rev 3
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160
Electrical characteristics
Symbol
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 36. Regulator modes transition times
Parameter
Conditions
Typ
Max Unit
Regulator transition time from Range
2 to Range 1 or
Wakeup clock HSI16 = 16 MHz
HPRE = 8
tVOST
20
40
μs
Range 1 to Range 2(2)
1. Guaranteed by characterization results.
2. Time until VOSF flag is cleared in PWR_SR2.
(1)
Table 37. Wakeup time using USART/LPUART
Symbol
Parameter
Conditions
Stop 0 mode
Typ
Max
Unit
Wakeup time needed to calculate the
maximum USART/LPUART baudrate
allowing to wakeup up from stop mode
when USART/LPUART clock source is
HSI16
-
1.7
tWUUSART
μs
tWULPUART
Stop 1 mode
-
8.5
1. Guaranteed by design.
5.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. However,
the recommended clock input waveform is shown in Figure 19: High-speed external clock
source AC timing diagram.
(1)
Table 38. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Voltage scaling
Range 1
-
8
48
User external clock
source frequency
fHSE_ext
MHz
Voltage scaling
Range 2
-
0.7 VDD
VSS
7
8
-
26
OSC_IN input pin high
level voltage
VHSEH
VHSEL
-
-
VDD
V
OSC_IN input pin low
level voltage
-
0.3 VDD
Voltage scaling
Range 1
-
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
ns
Voltage scaling
Range 2
18
-
1. Guaranteed by design.
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Electrical characteristics
Figure 19. High-speed external clock source AC timing diagram
t
w(HSEH)
V
HSEH
90%
10%
V
HSEL
t
t
t
t
r(HSE)
f(HSE)
w(HSEL)
T
HSE
MS19214V2
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. However,
the recommended clock input waveform is shown in Figure 20.
(1)
Table 39. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
-
-
32.768
1000
kHz
OSC32_IN input pin high
level voltage
VLSEH
VLSEL
tw(LSEH)
-
-
-
0.7 VDD
VSS
-
-
-
VDD
0.3 VDD
-
V
OSC32_IN input pin low level
voltage
OSC32_IN high or low time
250
ns
tw(LSEL)
1. Guaranteed by design.
Figure 20. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
90%
10%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 40. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
(1)
Table 40. HSE oscillator characteristics
Symbol
fOSC_IN Oscillator frequency
RF Feedback resistor
Parameter
Conditions(2)
Min
Typ
Max
Unit
-
4
-
8
200
-
48
-
MHz
-
kΩ
During startup(3)
-
5.5
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
-
-
-
-
0.44
0.45
0.68
0.94
1.77
-
-
-
-
-
VDD = 3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
VDD = 3 V,
IDD(HSE) HSE current consumption
mA
Rm = 30 Ω,
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 20 pF@48 MHz
Maximum critical crystal
transconductance
Gm
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
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DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 21. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
fHSE
Bias
controlled
gain
8 MHz
resonator
RF
(1)
OSC_OUT
REXT
CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 41. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
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Symbol
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)
Parameter
Conditions(2)
Min
Typ
Max Unit
LSEDRV[1:0] = 00
Low drive capability
-
250
-
LSEDRV[1:0] = 01
Medium low drive capability
-
-
-
-
-
-
315
-
IDD(LSE) LSE current consumption
nA
LSEDRV[1:0] = 10
Medium high drive capability
500
-
LSEDRV[1:0] = 11
High drive capability
630
-
LSEDRV[1:0] = 00
Low drive capability
-
-
-
0.5
LSEDRV[1:0] = 01
Medium low drive capability
0.75
µA/V
1.7
Maximum critical crystal
Gmcritmax
gm
LSEDRV[1:0] = 10
Medium high drive capability
LSEDRV[1:0] = 11
High drive capability
-
-
-
2.7
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
-
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
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Electrical characteristics
5.3.8
Internal clock source characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 17: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
(1)
Table 42. HSI16 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI16
HSI16 Frequency
VDD=3.0 V, TA=30 °C
15.88
-
16.08 MHz
Trimming code is not a
multiple of 64
0.2
-4
0.3
-6
0.4
%
TRIM
HSI16 user trimming step
Trimming code is a
multiple of 64
-8
DuCy(HSI16)(2) Duty Cycle
-
45
-1
-2
-
-
-
55
1
%
%
TA= 0 to 85 °C
TA= -40 to 125 °C
HSI16 oscillator frequency
drift over temperature
ꢀTemp(HSI16)
1.5
%
%
HSI16 oscillator frequency
drift over VDD
ꢀVDD(HSI16)
tsu(HSI16)(2)
tstab(HSI16)(2)
IDD(HSI16)(2)
VDD=1.62 V to 3.6 V
-0.1
-
0.05
1.2
5
HSI16 oscillator start-up
time
-
-
-
-
-
-
0.8
3
μs
μs
μA
HSI16 oscillator
stabilization time
HSI16 oscillator power
consumption
155
190
1. Guaranteed by characterization results.
2. Guaranteed by design.
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STM32G431x6 STM32G431x8 STM32G431xB
Figure 23. HSI16 frequency versus temperature
MHz
16.4
+2 %
+1.5 %
+1 %
16.3
16.2
16.1
16
15.9
15.8
15.7
-1 %
-1.5 %
-2 %
15.6
-40
-20
0
20
40
60
80
100
120 °C
Mean
min
max
MSv39299V2
High-speed internal 48 MHz (HSI48) RC oscillator
(1)
Table 43. HSI48 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI48
TRIM
HSI48 Frequency
VDD=3.0V, TA=30°C
-
-
-
48
-
MHz
%
HSI48 user trimming step
0.11(2) 0.18(2)
USER TRIM HSI48 user trimming
COVERAGE coverage
±32 steps
-
±3(3)
45(2)
-
±3.5(3)
-
%
%
DuCy(HSI48) Duty Cycle
-
-
55(2)
±3(3)
VDD = 3.0 V to 3.6 V,
TA = –15 to 85 °C
Accuracy of the HSI48
ACCHSI48_REL oscillator over temperature
(factory calibrated)
%
VDD = 1.65 V to 3.6 V,
TA = –40 to 125 °C
-
-
±4.5(3)
VDD = 3 V to 3.6 V
-
-
0.025(3) 0.05(3)
HSI48 oscillator frequency
DVDD(HSI48)
%
0.05(3)
0.1(3)
drift with VDD
VDD = 1.65 V to 3.6 V
HSI48 oscillator start-up
tsu(HSI48)
time
-
-
-
-
2.5(2)
6(2)
μs
HSI48 oscillator power
consumption
IDD(HSI48)
340(2)
380(2) μA
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Electrical characteristics
(1)
Table 43. HSI48 oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Next transition jitter
Accumulated jitter on 28
cycles(4)
NT jitter
-
-
+/-0.15(2)
-
-
ns
ns
Paired transition jitter
Accumulated jitter on 56
cycles(4)
PT jitter
-
-
+/-0.25(2)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.
Figure 24. HSI48 frequency versus temperature
%
6
4
2
0
-2
-4
-6
-50
-30
-10
10
30
50
70
90
110
130
°C
Avg
min
max
MSv40989V1
Low-speed internal (LSI) RC oscillator
(1)
Table 44. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
DD = 3.0 V,
31.04
-
32.96
34
TA = 30 °C
fLSI
LSI Frequency
kHz
VDD = 1.62 to 3.6 V,
29.5
-
-
TA = -40 to 125 °C
LSI oscillator start-up
time
tSU(LSI)(2)
-
80
130
μs
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STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 44. LSI oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LSI oscillator stabilization
time
tSTAB(LSI)(2)
5% of final frequency
-
125
180
μs
LSI oscillator power
consumption
IDD(LSI)(2)
-
-
110
180
nA
1. Guaranteed by characterization results.
2. Guaranteed by design.
5.3.9
PLL characteristics
The parameters given in Table 45 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 17: General operating conditions.
DD
(1)
Table 45. PLL characteristics
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ Max Unit
PLL input clock(2)
-
-
2.66
45
-
-
16
55
MHz
%
PLL input clock duty cycle
Voltage scaling Range 1
Boost mode
2.0645
-
170
fPLL_P_OUT PLL multiplier output clock P
Voltage scaling Range 1 2.0645
Voltage scaling Range 2 2.0645
-
-
150
26
Voltage scaling Range 1
Boost mode
8
-
170
fPLL_Q_OUT PLL multiplier output clock Q
Voltage scaling Range 1
Voltage scaling Range 2
8
8
-
-
150
26
MHz
Voltage scaling Range 1
Boost mode
8
-
170
fPLL_R_OUT PLL multiplier output clock R
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
-
8
8
96
96
-
-
-
150
26
-
344
128
40
fVCO_OUT PLL VCO output
-
tLOCK
Jitter
PLL lock time
15
28.6
21.4
200
300
520
μs
RMS cycle-to-cycle jitter
RMS period jitter
-
-
System clock 150 MHz
±ps
-
-
VCO freq = 96 MHz
VCO freq = 192 MHz
VCO freq = 344 MHz
-
260
380
650
PLL power consumption on
VDD
I
DD(PLL)
-
μA
(1)
-
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock
values.
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Electrical characteristics
5.3.10
Flash memory characteristics
(1)
Table 46. Flash memory characteristics
Symbol
Parameter
Conditions
Typ
Max Unit
tprog
64-bit programming time
-
81.7
2.61
83.35
2.7
µs
Normal programming
Fast programming
Normal programming
Fast programming
One row (32 double
word) programming time
tprog_row
1.91
1.95
21.34
15.6
20.91
15.29
One page (2 Kbytes)
programming time
ms
tprog_page
Page (2 Kbytes) erase
time
tERASE
-
22.02
24.47
Normal programming
Fast programming
-
1.34
0.98
1.49
One bank (128 Kbyte)
programming time
tprog_bank
tME
s
1.09
Mass erase time
22.13
24.6
ms
Write mode
Erase mode
Write mode
Erase mode
3.5
-
-
-
-
Average consumption
from VDD
3.5
IDD
mA
7 (for 6 µs)
7 (for 67 µs)
Maximum current (peak)
1. Guaranteed by design.
Table 47. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Conditions
Min(1)
Unit
NEND
TA = -40 to +105 °C
10
30
15
7
kcycles
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
1 kcycle(2) at TA = 125 °C
10 kcycles(2) at TA = 55 °C
10 kcycles(2) at TA = 85 °C
10 kcycles(2) at TA = 105 °C
tRET
Data retention
Years
30
15
10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
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STM32G431x6 STM32G431x8 STM32G431xB
5.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709.
Table 48. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, TA = +25 °C,
fHCLK = 170 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
2B
5A
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 170 MHz,
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
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Electrical characteristics
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 49. EMI characteristics
Max vs. [fHSE/fHCLK
8 MHz / 170 MHz
]
Monitored
frequency band
Symbol
Parameter
Conditions
Unit
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
3
-2
25
18
4
VDD = 3.6 V, TA = 25 °C,
Peak level LQFP100 package
compliant with IEC 61967-2
dBµV
-
SEMI
5.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 50. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge
voltage (human body model) ANSI/ESDA/JEDEC JS-001
TA = +25 °C, conforming to
VESD(HBM)
2
2000
V
V
Electrostatic discharge TA = +25 °C, conforming to
voltage (charge device model) ANSI/ESDA/JEDEC JS- 002
VESD(CDM)
C1
250
1. Guaranteed by characterization results.
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Electrical characteristics
Static latch-up
STM32G431x6 STM32G431x8 STM32G431xB
Two complementary static tests are required on three parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.
Table 51. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +125 °C conforming to JESD78E
Class II level A
5.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 52.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 52. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
All except TT_a, PF2
-5
-0
-5
NA
NA
0
(1)
IINJ
Injected current on pin
PF2
mA
TT_a pins
1. Guaranteed by characterization.
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5.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under the conditions summarized in Table 17: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 53. I/O static characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
0.3xVDD
All except
FT_c
1.62 V<VDD<3.6 V
-
-
0.39xVDD-0.06(3)
I/O input
low level
voltage
(1)(2)
VIL
V
0.3xVDD
FT_c
1.62 V<VDD<3.6 V
-
-
0.25xVDD
0.7xVDD
0.49xVDD +0.26(3)
0.7xVDD
-
-
-
-
-
-
All except
FT_c
I/O input
high level
voltage
1.62 V<VDD<3.6 V
1.62 V<VDD<3.6 V
(1)(2)
(3)
VIH
V
FT_c
TT_xx,
FT_xxx,
NRST
Input
hysteresis
VHYS
1.62 V<VDD<3.6 V
-
200
-
mV
0 < VIN ≤ VDD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±100
650(4)
200(4)
2000
FT_xx
except
FT_c
V
DD ≤ VIN ≤ VDD+1 V
VDD+1 V < VIN ≤ 5.5 V
0 ≤ VIN ≤ VDDMAX
FT_c
V
DD ≤ VIN <0.5 V
3000
Input
0 ≤ VIN ≤ VDD
±150
Ileak
leakage
nA
current(3)
FT_u, PC3
VDD ≤ VIN ≤ VDD+ 1 V
±2500
±250
V
DD ≤ VIN ≤ 5.5 V
0 ≤ VIN ≤ VDD
±4500
±9000
±150
FT_d
VDD + 1V ≤ VIN ≤ 5.5 V
0 ≤ VIN ≤ VDD
TT_xx
VDD ≤ VIN ≤ 3.6 V
2000
Weak pull-
up
RPU
VIN = VSS
25
40
55
equivalent
resistor(5)
kΩ
Weak pull-
down
RPD
VIN = VDD
25
-
40
5
55
-
equivalent
resistor(5)
I/O pin
capacitance capacitance
I/O pin
CIO
-
pF
1. Refer to Figure 25: I/O input characteristics
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STM32G431x6 STM32G431x8 STM32G431xB
2. Data based on characterization results, not tested in production
3. Guaranteed by design.
4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
Note:
For more information about GPIO properties, refer to the application note AN4899 "STM32
GPIO configuration for hardware settings and low-power consumption" available from the
ST website www.st.com.
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 25 for standard I/Os, and in Figure 25 for
5 V tolerant I/Os.
Figure 25. I/O input characteristics
TTL requirement Vih min = 2V
TTL requirement Vil max = 0.8V
MSv37613V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed V /V ).
OL OH
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In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 14: Voltage characteristics).
VDD
•
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating ΣI
(see
SS
VSS
Table 14: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 17: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
(1)(2)
Table 54. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
(3)
VOL
Output low level voltage for an I/O pin CMOS port
-
0.4
|IIO| = 2 mA for FT_c
(3)
I/Os = 8 mA for other I/Os VDD
≥ 2.7 V
VOH
Output high level voltage for an I/O pin
VDD-0.4
-
0.4
-
(3)
VOL
Output low level voltage for an I/O pin TTL port
|IIO| = 2 mA for FT_c
-
(3)
I/Os = 8 mA for other I/Os
VDD ≥ 2.7 V
VOH
Output high level voltage for an I/O pin
2.4
(3)
VOL
Output low level voltage for an I/O pin All I/Os except FT_c
|IIO| = 20 mA
-
1.3
-
V
(3)
VOH
Output high level voltage for an I/O pin
VDD-1.3
-
VDD ≥ 2.7 V
(3)
VOL
Output low level voltage for an I/O pin |IIO| = 1 mA for FT_c
I/Os = 4 mA for other I/Os
0.4
-
(3)
VOH
Output high level voltage for an I/O pin
VDD-0.45
VDD ≥ 1.62 V
|IIO| = 20 mA
VDD ≥ 2.7 V
-
-
0.4
0.4
Output low level voltage for an FT I/O
pin in FM+ mode (FT I/O with “f”
option)
VOLFM+
(3)
|IIO| = 10 mA
VDD ≥ 1.62 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 14:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and
Table 55, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 17: General
operating conditions.
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Electrical characteristics
Speed Symbol
STM32G431x6 STM32G431x8 STM32G431xB
(1) (2)
Table 55. I/O (except FT_c) AC characteristics
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
1
Maximum
frequency
Fmax
MHz
10
1.5
25
00
52
Output rise and
fall time
Tr/Tf
ns
MHz
ns
17
37
25
10
Maximum
frequency
Fmax
50
15
01
9
16
Output rise and
fall time
Tr/Tf
4.5
9
50
25
Maximum
frequency
Fmax
MHz
100(3)
37.5
5.8
11
10
Output rise and
fall time
Tr/Tf
ns
2.5
5
120(3)
50
Maximum
frequency
Fmax
MHz
180(3)
75
11
3.3
6
Output rise and
fall time(4)
Tr/Tf
ns
1.7
3.3
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Electrical characteristics
(1) (2)
Table 55. I/O (except FT_c) AC characteristics
(continued)
Speed Symbol
Parameter
Conditions
Min
Max
Unit
Maximum
frequency
Fmax(5)
-
1
5
MHz
FM+
C=50 pF, 1.6 V≤VDD≤3.6 V
Output high to
low level fall
time
Tr/TF(4)
-
ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm®-
based 32-bit MCUs" for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. This value represented the I/O capability but maximum system frequency is 170 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
5. The maximum frequency is defined with the following conditions:
- (Tr+ Tf) ≤ 2/3 T.
- 45%<Duty cycle<55%
(1) (2)
Table 56. I/O FT_c AC characteristics
Speed Symbol
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.6 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
-
-
-
2
1
Maximum
frequency
Fmax
MHz
0
Output H/L to
170
Tr/Tf L/H level fall
time
ns
MHz
ns
C=50 pF, 1.6 V≤VDD≤2.7 V
-
330
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.6 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
-
-
-
10
5
Maximum
Fmax
frequency
1
Output H/L to
Tr/Tf L/H level fall
time
35
C=50 pF, 1.6 V≤VDD≤2.7 V
-
65
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm®-
based 32-bit MCUs" for a description of GPIO Port configuration register.
2. Guaranteed by design.
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STM32G431x6 STM32G431x8 STM32G431xB
(1)
Figure 26. I/O AC characteristics definition
10%
90%
50%
50%
10%
90%
t
t
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 55: I/O (except FT_c) AC characteristics.
5.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 17: General operating conditions.
(1)
Table 57. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST input low level
voltage
VIL(NRST)
-
-
-
0.3ₓVDD
V
NRST input high level
voltage
VIH(NRST)
Vhys(NRST)
RPU
-
0.7ₓVDD
-
200
40
-
-
-
NRST Schmitt trigger
voltage hysteresis
-
-
25
-
mV
kΩ
ns
Weak pull-up equivalent
resistor(2)
VIN = VSS
-
55
70
-
NRST input filtered
pulse
VF(NRST)
VNF(NRST)
NRST input not filtered
pulse
1.71 V ≤ VDD
≤ 3.6 V
350
-
ns
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
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Figure 27. Recommended NRST pin protection
External
reset circuit(1)
VDD
RPU
NRST(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 57: NRST pin characteristics. Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.16
Extended interrupt and event controller input (EXTI) characteristics
The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
(1)
Table 58. EXTI input characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pulse length to event
controller
PLEC
-
20
-
-
ns
1. Guaranteed by design.
5.3.17
Analog switches booster
(1)
Table 59. Analog switches booster characteristics
Symbol
Parameter
Supply voltage
Min
Typ
Max
Unit
VDD
1.62
-
-
-
3.6
V
tSU(BOOST)
Booster startup time
240
µs
Booster consumption for
-
-
-
-
-
-
250
500
900
1.62 V ≤ VDD ≤ 2.0 V
Booster consumption for
IDD(BOOST)
µA
2.0 V ≤ VDD ≤ 2.7 V
Booster consumption for
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.
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5.3.18
Analog-to-digital converter characteristics
Unless otherwise specified, the parameters given in Table 60 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK
DDA
conditions summarized in Table 17: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
(1) (2)
Table 60. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage
VDDA
-
1.62
2
-
3.6
V
Positive
reference
voltage
V
DDA ≥ 2 V
-
VDDA
V
V
VREF+
VDDA < 2 V
VDDA
Negative
reference
voltage
VREF-
-
VSSA
V
Input common
mode
(VREF++VREF-)/2 (VREF+
+
(VREF+ + VREF-)/2
+ 0.18
VCMIN
Differential
V
- 0.18
0.14
-
VREF-)/2
Range 1, single
ADC operation
-
-
60
26
Range 2
Range 1, all ADCs
operation, single
ended mode
0.14
0.14
-
-
-
52
42
56
VDDA ≥ 2.7 V
ADC clock
frequency
fADC
MHz
Range 1, all ADCs
operation, single
ended mode
VDDA ≥ 1.62 V
Range 1, all ADCs
operation,
differential mode
VDDA ≥ 1.62 V
0.14
For given
Sampling rate,
continuous mode sampling time
cycles (ts)
resolution and
fADC / (sampling time [cycles] +
resolution [bits] + 0.5)
fs
0.001
Msps
Considering trigger
conversion latency
time (tLATR or
-
-
External trigger
period
tLATRINJ
)
TTRIG
1ms
-
Resolution =
12 bits,
fADC=60 MHz
tconv + [tLATR or
-
tLATRINJ
]
Conversion
voltage range
(3)
VAIN
-
0
-
VREF+
V
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Electrical characteristics
(1) (2)
Table 60. ADC characteristics
(continued)
Typ
Symbol
Parameter
Conditions
Min
Max
Unit
External input
impedance
(4)
RAIN
-
-
-
50
kΩ
Internal sample
and hold
capacitor
CADC
-
-
-
5
1
-
pF
conversi
on cycle
tSTAB
Power-up time
Calibration time
f
ADC = 60 MHz
-
1.93
µs
tCAL
116
1/fADC
Trigger
conversion
latency Regular
and injected
channels without
conversion abort
CKMODE = 00
CKMODE = 01
CKMODE = 10
1.5
2
-
2.5
2.0
-
-
tLATR
1/fADC
-
2.25
CKMODE = 11
-
-
2.125
Trigger
CKMODE = 00
CKMODE = 01
CKMODE = 10
2.5
3
-
3.5
3.0
conversion
latency Injected
channels
-
-
tLATRINJ
1/fADC
-
3.25
aborting a
regular
conversion
CKMODE = 11
-
-
3.125
f
ADC = 60 MHz
-
0.0416
2.5
-
-
10.675
640.5
µs
ts
Sampling time
1/fADC
tADCVREG_S ADC voltage
regulator start-up
-
-
-
-
20
µs
TUP
time
fADC = 60 MHz
Resolution =
12 bits
Total conversion
time
(including
0.25
10.883
µs
tCONV
sampling time)
-
ts[cycles] + resolution [bits] +0.5 = 15 to 653
1/fADC
fs = 4 Msps
fs = 1 Msps
fs = 10 ksps
fs = 4 Msps
fs = 1 Msps
-
-
-
-
-
590
160
16
730
220
50
ADC
consumption
from the VDDA
supply
IDDA(ADC)
µA
µA
µA
ADC
110
30
140
40
consumption
from the VREF+
single ended
mode
IDDV_S(ADC
)
fs = 10 ksps
-
0.6
2
fs = 4 Msps
fs = 1 Msps
fs = 10 ksps
-
-
-
220
60
270
70
3
ADC
IDDV_D(ADC consumption
)
from the VREF+
differential mode
1.3
1. Guaranteed by design
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2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disabled when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
4. The maximum value of RAIN can be found in Table 61: Maximum ADC RAIN.
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Electrical characteristics
The maximum value of R
can be found in Table 61: Maximum ADC RAIN.
AIN
(1)(2)
Table 61. Maximum ADC R
AIN
RAIN max (Ω)
Fast channels(3) Slow channels(4)
Sampling cycle
@60 MHz
Sampling time
[ns]
Resolution
2.5
6.5
41.67
108.33
208.33
408.33
791.67
1541.67
4125
100
330
N/A
100
12.5
24.5
47.5
92.5
247.5
640.5
2.5
680
470
1500
2200
4700
12000
39000
120
1200
1800
3900
10000
33000
N/A
12 bits
10675
41.67
6.5
108.33
208.33
408.33
791.67
1541.67
4125
390
180
12.5
24.5
47.5
92.5
247.5
640.5
2.5
820
560
1500
2200
5600
12000
47000
180
1200
1800
4700
10000
39000
N/A
10 bits
8 bits
6 bits
10675
41.67
6.5
108.33
208.33
408.33
791.67
1541.67
4125
470
270
12.5
24.5
47.5
92.5
247.5
640.5
2.5
1000
1800
2700
6800
15000
50000
220
680
1500
2200
5600
12000
50000
N/A
10675
41.67
6.5
108.33
208.33
408.33
791.67
1541.67
4125
560
330
12.5
24.5
47.5
92.5
247.5
640.5
1200
2700
3900
8200
18000
50000
1000
2200
3300
6800
15000
50000
10675
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1. Guaranteed by design.
2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disabled when VDDA ≥ 2.4 V.
3. Fast channels are: ADCx_IN1 to ADCx_IN5.
4. Slow channels are: all ADC inputs except the fast channels.
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Electrical characteristics
(1)(2)(3)
Table 62. ADC accuracy - limited test conditions 1
(4)
Symbol Parameter
Conditions
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.9 6.9
5.5 6.9
4.6 5.6
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
Differential
4
5.6
4
2.5
1.9
Single
ended
4
Offset error
Gain error
1.8 2.8
1.1 2.8
4.6 6.6
4.5 6.6
3.6 4.6
3.3 4.6
1.1 1.9
1.3 1.9
1.3 1.6
1.4 1.6
2.3 3.4
2.4 3.4
2.1 3.2
2.2 3.2
Differential
Single
ended
LSB
Differential
Single
ended
Differential
linearity
error
Single ADC operation ADC clock
frequency ≤ 60 MHz,
Differential
V
= VREF+ = 3 V, TA =
DDA
25 °C
Continuous mode, sampling
rate:
Fast channels@4Msps
Slow channels@2Msps
Single
ended
Integral
linearity
error
Differential
Fast channel (max speed) 10.4 10.6
Slow channel (max speed) 10.4 10.6
Fast channel (max speed) 10.8 10.9
Slow channel (max speed) 10.8 10.9
Fast channel (max speed) 64.4 65.6
Slow channel (max speed) 64.4 65.6
Fast channel (max speed) 66.8 67.5
Slow channel (max speed) 66.8 67.5
Fast channel (max speed) 65 66.9
Slow channel (max speed) 65 66.9
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Effective
ENOB number of
bits
bits
Differential
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Differential
dB
Single
ended
Signal-to-
SNR
Fast channel (max speed) 67
Slow channel (max speed) 67
69
69
noise ratio
Differential
-
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STM32G431x6 STM32G431x8 STM32G431xB
(1)(2)(3)
Table 62. ADC accuracy - limited test conditions 1
(continued)
(4)
Symbol Parameter
Conditions
Min Typ Max Unit
Single ADC operation ADC clock
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-73 -72
-73 -72
-73 -72
Single
ended
frequency ≤ 60 MHz,
= VREF+ = 3 V, TA =
V
DDA
Total
25 °C
THD
harmonic
distortion
dB
Continuous mode, sampling
rate:
Fast channels@4Msps
Slow channels@2Msps
Differential
Slow channel (max speed)
-
-73 -72
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disabled when VDDA ≥ 2.4 V. No oversampling.
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Electrical characteristics
(1)(2)(3)
Table 63. ADC accuracy - limited test conditions 2
Sym-
bol
(4)
Parameter
Conditions
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
5.9
5.5
4.6
4
8.4
8
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
-
6.6
6
Differential
-
-
2.5
1.9
1.8
1.1
4.6
4.5
3.6
3.3
1.1
1.3
1.3
1.4
2.3
2.4
2.1
2.2
10.6
10.6
6
Single
ended
-
6.9
3.3
3.3
8.1
8.1
4.6
4.6
1.8
1.8
1.6
1.6
4.4
4.4
4.1
3.7
-
Offset error
Gain error
-
Differential
-
-
Single
ended
-
LSB
-
Differential
-
-
Single
ended
Differential
linearity
error
-
Single ADC operation
ADC clock frequency
-
Differential
≤ 60 MHz, 2 V ≤ V
DDA
-
Continuous mode, sampling
rate:
Fast channels@4Msps
Slow channels@2Msps
-
Single
ended
Integral
linearity
error
-
-
Differential
-
10
10
Single
ended
Effective
ENOB number of
bits
-
bits
Fast channel (max speed) 10.7 10.9
Slow channel (max speed) 10.7 10.9
-
Differential
-
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
62
62
65
65
64
64
65.6
65.6
67.5
67.5
66.9
66.9
69
-
Single
ended
Signal-to-
noise and
distortion
ratio
-
SINAD
-
Differential
-
dB
-
Single
ended
-
Signal-to-
SNR
noise ratio
Fast channel (max speed) 66.5
Slow channel (max speed) 66.5
-
Differential
69
-
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STM32G431x6 STM32G431x8 STM32G431xB
(1)(2)(3)
Table 63. ADC accuracy - limited test conditions 2
(continued)
Sym-
(4)
Parameter
bol
Conditions
Min Typ Max Unit
Single ADC operation
ADC clock frequency
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-73
-73
-73
-65
-67
-70
Single
ended
≤ 60 MHz, 2 V ≤ V
Total
THD harmonic
distortion
DDA
Continuous mode, sampling
rate:
Fast channels@4Msps
Slow channels@2Msps
dB
Differential
Slow channel (max speed)
-
-73
-71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
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(1)(2)(3)
Table 64. ADC accuracy - limited test conditions 3
Sym-
bol
(4)
Parameter
Conditions
Min
Typ Max Unit
Fast channel (max speed)
-
5.9
5.5
7.9
7.5
7.6
5.5
5.5
5.5
3.5
3
Single
ended
Total
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
ET
EO
EG
ED
EL
unadjusted
error
-
4.6
Differential
-
4
-
2.5
Single
ended
-
-
1.9
Offset error
Gain error
1.8
Differential
-
1.1
-
4.6
7.1
7
Single
ended
-
4.5
LSB
-
3.6
4.1
4.8
1.9
1.9
1.6
1.6
4.4
4.4
3.7
3.7
-
Differential
-
3.3
-
1.1
Single
ended
Single ADC operation
ADC clock frequency ≤
60 MHz,
Differential
linearity
error
-
1.3
-
1.3
Differential
1.62 V ≤ V
≤ 3.6 V,
= V
REF+
DDA
-
1.4
-
2.3
Continuous mode,
sampling rate:
Fast channels@4Msps
Slow channels@2Msps
Single
ended
Integral
linearity
error
-
2.4
-
2.1
Differential
-
2.2
10
10
10.6
10.6
62
62
65
65
63
63
66
66
10.6
10.6
10.9
10.9
65.6
65.6
67.5
67.5
66.9
66.9
69
Single
ended
Effective
-
ENOB number of
bits
bits
-
Differential
-
-
Single
ended
Signal-to-
-
noise and
distortion
SINAD
-
ratio
Differential
-
dB
-
Single
ended
-
Signal-to-
SNR
noise ratio
-
Differential
69
-
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
(1)(2)(3)
Table 64. ADC accuracy - limited test conditions 3
(continued)
Sym-
(4)
Parameter
bol
Conditions
Min
Typ Max Unit
Single ADC operation
ADC clock frequency ≤
60 MHz,
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-73
-73
-73
-67
-67
-71
Single
ended
Fast channel (max speed)
1.62 V ≤ V
≤ 3.6 V,
= V
REF+
Total
THD harmonic
distortion
DDA
dB
Continuous mode,
sampling rate:
Fast channels@4Msps
Slow channels@2Msps
Differential
Slow channel (max speed)
-
-73
-71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
128/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1)(2)(3)
Table 65. ADC accuracy (Multiple ADCs operation) - limited test conditions 1
(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Single ended
Differential
-
-
-
-
-
-
-
-
-
-
-
-
-
4.5
4.1
-
-
-
-
-
-
-
-
-
-
-
-
-
Totalunadjusted
error
ET
Single ended
Differential
1.3
EO
EG
Offset error
Gain error
0.4
Single ended
Differential
3.9
LSB
3.4
Multiple ADC operation
ADC clock frequency:
single ended ≤ 52 MHz,
differential ≤ 56 MHz,
Single ended
Differential
1.5
Differential
linearity error
ED
1.2
V
25°C,
= VREF= 3.3 V,
Single ended
Differential
1.7
DDA
Integral linearity
error
EL
2.1
Continuous mode,
sampling time:
Fast channels: 2.5 cycles
Slow channels: 6.5 cycles
LQFP100 package
Single ended
Differential
10.7
10.9
66.3
Effective
number of bits
ENOB
bits
dB
dB
Signal-to-noise
and distortion
ratio
Single ended
SINAD
Differential
-
67.2
-
Single ended
Differential
-
-
-
-
67.3
68.6
-73.5
-73
-
-
-
-
Signal-to-noise
ratio
SNR
THD
Single ended
Differential
Total harmonic
distortion
1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
(1)(2)(3)
Table 66. ADC accuracy (Multiple ADCs operation) - limited test conditions 2
(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Single ended
Differential
-
-
-
-
-
-
-
-
-
-
-
-
-
7.1
4.6
-
-
-
-
-
-
-
-
-
-
-
-
-
Totalunadjusted
error
ET
Single ended
Differential
4.2
EO
EG
Offset error
Gain error
2.8
Single ended
Differential
6.8
LSB
4.3
Multiple ADC operation
ADC clock frequency:
single ended ≤ 52 MHz,
differential ≤ 56 MHz,
Single ended
Differential
1.5
Differential
linearity error
ED
1.7
V
DDA ≥ 2.7 V, VREF≥ 1.62 V,
Single ended
Differential
3.1
Integral linearity
error
EL
-40 to 125°C,
Continuous mode,
sampling time:
Fast channels: 2.5 cycles
Slow channels: 6.5 cycles
LQFP100 package
2.4
Single ended
Differential
10.2
10.6
62.9
Effective
number of bits
ENOB
bits
dB
dB
Signal-to-noise
and distortion
ratio
Single ended
SINAD
Differential
-
65.3
-
Single ended
Differential
-
-
-
-
63.6
66.3
-
-
-
-
Signal-to-noise
ratio
SNR
THD
Single ended
Differential
-70.9
-71.8
Total harmonic
distortion
1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
130/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1)(2)(3)
Table 67. ADC accuracy (Multiple ADCs operation) - limited test conditions 3
(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Single ended
Differential
-
-
-
-
-
-
-
-
-
-
-
-
-
7.4
4.6
4
-
-
-
-
-
-
-
-
-
-
-
-
-
Totalunadjusted
error
ET
Single ended
Differential
EO
EG
Offset error
Gain error
2.8
7.2
4.3
1.8
1.7
3.1
2.4
10.1
10.6
62.6
Single ended
Differential
LSB
Multiple ADC operation
ADC clock frequency:
single ended ≤ 42 MHz,
differential ≤ 56 MHz,
Single ended
Differential
Differential
linearity error
ED
V
= VREF≥ 1.62 V,
Single ended
Differential
DDA
Integral linearity
error
EL
-40 to 125°C,
Continuous mode,
sampling time:
Fast channels: 2.5 cycles
Slow channels: 6.5 cycles
LQFP100 package
Single ended
Differential
Effective
number of bits
ENOB
bits
dB
dB
Signal-to-noise
and distortion
ratio
Single ended
SINAD
Differential
-
65.3
-
Single ended
Differential
-
-
-
-
63.2
66.3
-
-
-
-
Signal-to-noise
ratio
SNR
THD
Single ended
Differential
-70.6
-71.8
Total harmonic
distortion
1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
Figure 28. ADC accuracy characteristics
ADC code
4095
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4094
4093
(2)
ET
= total unajusted error: maximum deviation
between the actual and ideal transfer curves.
ET
(3)
EO
= offset error: maximum deviation between the
first actual transition and the first ideal one.
7
6
(1)
EG
ED
EL
= gain error: deviation between the last
ideal transition and the last actual one.
5
EO
EL
= differential linearity error: maximum deviation
between actual steps and the ideal ones.
4
3
2
1
ED
= integral linearity error: maximum deviation
between any actual transition and the end
point correlation line.
1 LSB IDEAL
0
Vin/VREF*4096
1
2
3
4
5
6
7
4093 4094 4095 4096
MS60205V1
Figure 29. Typical connection diagram using the ADC
VDDA
Sample and hold ADC converter
(1)
RAIN
RADC
AINx
12-bit
converter
(2)
(3)
Cparasitic
CADC
Ilkg
VAIN
MS33900V6
1. Refer to Table 60: ADC characteristics for the values of RAIN and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 53: I/O static characteristics for the value of the pad capacitance). A high
C
parasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 53: I/O static characteristics for the values of Ilkg
.
General PCB design guidelines
Power supply decoupling must be performed as shown in Figure 16: Power supply scheme.
The decoupling capacitor on V
close as possible to the chip.
must be ceramic (good quality) and it must be placed as
DDA
132/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
5.3.19
Digital-to-Analog converter characteristics
(1)
Table 68. DAC 1MSPS characteristics
Conditions
Symbol
Parameter
Min
1.71
1.80
1.71
1.80
Typ
Max
Unit
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
-
-
-
-
Analog supply voltage for
DAC ON
VDDA
3.6
Other modes
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
V
VREF+
Positive reference voltage
Negative reference voltage
VDDA
Other modes
-
VREF-
VSSA
connected to VSSA
DAC output
5
25
9.6
-
-
-
-
RL
Resistive load
kΩ
kΩ
buffer ON
connected to VDDA
-
11.7
-
RO
Output Impedance
DAC output buffer OFF
13.8
2
Output impedance sample VDD = 2.7 V
and hold mode, output
RBON
kΩ
kΩ
VDD = 2.0 V
-
-
-
-
-
-
3.5
buffer ON
Output impedance sample VDD = 2.7 V
and hold mode, output
16.5
18.0
RBOFF
VDD = 2.0 V
buffer OFF
CL
DAC output buffer ON
Sample and hold mode
-
-
-
50
1
pF
µF
Capacitive load
CSH
0.1
VREF+
– 0.2
DAC output buffer ON
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
DAC output buffer OFF
±0.5 LSB
0
-
-
VREF+
3
1.7
Normal mode
DAC output
buffer ON
CL ≤ 50 pF,
RL ≥ 5 kΩ
±1 LSB
-
1.6
2.9
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value)
±2 LSB
±4 LSB
±8 LSB
-
1.55
1.48
1.4
2.85
2.8
tSETTLING
µs
-
-
2.75
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF
-
-
-
-
2
2.5
7.5
5
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Wakeup time from off state
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
4.2
2
(2)
tWAKEUP
µs
Normal mode DAC output buffer
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL = 5 kΩ, DC
PSRR
VDDA supply rejection ratio
-80
-28
dB
DS12589 Rev 3
133/197
160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 68. DAC 1MSPS characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Minimal time between two
consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
variation of the input code
(1 LSB)
TW_to_W
-
-
µs
DAC_MCR:MODEx[2:0] =
000 or 001
DAC_MCR:MODEx[2:0] =
010 or 011
CL ≤ 50 pF, RL ≥ 5 kΩ
CL ≤ 10 pF
1
1.4
-
DAC output buffer
0.7
3.5
18
ON, CSH = 100 nF
DAC_OUT
ms
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
pin connected
DAC output buffer
OFF, CSH = 100 nF
-
10.5
tSAMP
DAC_OUT
pin not
connected
(internal
connection
only)
DAC output buffer
OFF
-
2
3.5
µs
Sample and hold mode,
DAC_OUT pin connected
(3)
Ileak
Output leakage current
-
-
-
nA
Internal sample and hold
capacitor
CIint
-
5.2
7
8.8
pF
µs
tTRIM
Middle code offset trim time DAC output buffer ON
50
-
-
-
-
-
VREF+ = 3.6 V
1500
750
Middle code offset for 1 trim
code step
Voffset
µV
µA
VREF+ = 1.8 V
-
No load, middle
code (0x800)
-
-
-
315
450
500
670
DAC output
buffer ON
No load, worst code
(0xF1C)
DAC consumption from
VDDA
DAC output
buffer OFF
No load, middle
code (0x800)
I
DDA(DAC)
-
0.2
315 ₓ
670 ₓ
Sample and hold mode, CSH
100 nF
=
Ton/(Ton Ton/(Ton
+Toff) +Toff)
-
(4)
(4)
134/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1)
Table 68. DAC 1MSPS characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
No load, middle
code (0x800)
-
185
240
DAC output
buffer ON
No load, worst code
(0xF1C)
-
-
340
400
DAC output
buffer OFF
No load, middle
code (0x800)
155
205
DAC consumption from
VREF+
IDDV(DAC)
µA
185 ₓ
Ton/(Ton Ton/(Ton
400 ₓ
Sample and hold mode, buffer ON,
CSH = 100 nF, worst case
-
-
+Toff)
+Toff)
(4)
(4)
155 ₓ
205 ₓ
Sample and hold mode, buffer OFF,
CSH = 100 nF, worst case
Ton/(Ton Ton/(Ton
+Toff) +Toff)
(4)
(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 53: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to the reference manual RM0440 "STM32G4
Series advanced Arm®-based 32-bit MCUs" for more details.
Figure 30. 12-bit buffered / non-buffered DAC
Buffered/non-buffered DAC
Buffer(1)
RLOAD
12-bit
DACx_OUT
digital to
analog
converter
CLOAD
ai17157d
1. The DAC integrates an output buffer to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx
bit in the DAC_CR register.
DS12589 Rev 3
135/197
160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
.
(1)
Table 69. DAC 1MSPS accuracy
Conditions
DAC output buffer ON
Symbol
Parameter
Min
Typ
Max
Unit
-
-
-
±2
±2
Differential non
linearity (2)
DNL
-
DAC output buffer OFF
10 bits
-
monotonicity
Guaranteed
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±4
±4
Integral non
linearity(3)
INL
DAC output buffer OFF
CL ≤ 50 pF, no RL
VREF+ = 3.6 V
VREF+ = 1.8 V
±12
±25
±8
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
LSB
Offset error at
code 0x800(3)
Offset
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset error at
code 0x001(4)
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset1
±5
VREF+ = 3.6 V
VREF+ = 1.8 V
±5
Offset Error at
OffsetCal code 0x800
after calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±7
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±0.5
±0.5
±30
±12
Gain
Gain error(5)
%
DAC output buffer OFF
CL ≤ 50 pF, no RL
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Total
TUE
unadjusted
error
LSB
LSB
DAC output buffer OFF
CL ≤ 50 pF, no RL
Total
unadjusted
error after
calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
TUECal
-
-
±23
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
1 kHz, BW 500 kHz
-
-
71.2
71.6
-
-
Signal-to-noise
ratio
SNR
THD
dB
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
BW 500 kHz
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
-
-
-78
-79
-
-
Total harmonic
distortion
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
136/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1)
Table 69. DAC 1MSPS accuracy (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
-
70.4
-
Signal-to-noise
and distortion
ratio
SINAD
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
-
-
-
71
-
-
-
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
11.4
11.5
Effective
number of bits
ENOB
bits
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
(1)
Table 70. DAC 15MSPS characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage for
DAC ON
VDDA
-
1.71
1.71
-
-
3.6
V
VREF+
VREF-
VDAC_OUT
Positive reference voltage
Negative reference voltage
-
-
VDDA
VSSA
Voltage on DAC_OUT
output
-
0
-
VREF+
V
10%-90%
5%-95%
1%-99%
32lsb
-
-
-
-
-
-
-
-
-
-
16
21
33
40
64
24
32
49
57
93
22
29
46
53
87
32
43
67
75
125
VDDA>2,7V
With One comparator
on DAC output
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value)
1lsb
tSETTLING
ns
10%-90%
5%-95%
1%-99%
32lsb
VDDA>2,7V
With One comparator
and OPAMP on DAC
output
1lsb
DS12589 Rev 3
137/197
160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 70. DAC 15MSPS characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
10%-90%
5%-95%
1%-99%
32lsb
-
-
-
-
-
-
-
-
-
-
16
21
33
40
64
24
32
49
57
93
88
116
181
196
332
128
170
265
284
483
VDDA<2,7V
With One comparator
on DAC output
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value)
1lsb
tSETTLING
ns
10%-90%
5%-95%
1%-99%
32lsb
VDDA<2,7V
With One comparator
and OPAMP on DAC
output
1lsb
Wakeup time from off state
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
(2)
tWAKEUP
Normal mode CL ≤ 10 pF
-
1.4
3.5
µs
V
DD > 2.7 V
65
40
85
85
-
-
PSRR
VDDA supply rejection ratio
dB
VDD <2.7 V
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
tSAMP
-
-
-
0.7
-
µs
Internal sample and hold
capacitor
CIint
-
-
4
5
-
pF
Voltage decay rate in
Sample and hold mode,
during hold phase
CSH = 4 pF
T = 55°C
dV/dt (hold
phase)
50
mV/ms
DAC consumption from
VDDA
IDDA(DAC)
No load, middle code (0x800)
No load, middle code (0x800)(3)
-
-
-
0.2
µA
DAC consumption from
VREF+
IDDV(DAC)
720
955
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Worst case consumption is at code 0x800.
138/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1)
Table 71. DAC 15MSPS accuracy
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DNL
INL
Differential non linearity (2)
Integral non linearity(3)
Total unadjusted error
-
-2
-5
-5
-
-
-
2
5
5
CL ≤ 50 pF, no RL
CL ≤ 50 pF, no RL
LSB
TUE
Spike amplitude on DAC voltage when
DAC output value is decreasing
DCS
Dynamic code spike
-
0
4
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095.
Offset error is included.
DS12589 Rev 3
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Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
5.3.20
Voltage reference buffer characteristics
(1)
Table 72. VREFBUF characteristics
Symbol
Parameter
Conditions
VRS = 00
Min
Typ
Max
Unit
2.4
2.8
-
3.6
3.6
Normal mode
VRS = 01
VRS = 10
VRS= 00
-
3.135
-
3.6
Analog supply
voltage
VDDA
1.65
-
2.4
Degraded mode(2) VRS = 01
1.65
-
2.8
VRS= 10
1.65
-
3.135
2.052
2.504
2.904
VDDA
VDDA
VDDA
V
VRS= 00
2.044
2.048
Normal mode
VRS= 01
VRS = 10
VRS= 00
2.496
2.5
2.896
2.9
VREFBUF_ Voltage reference
output
OUT
VDDA -250 mV
VDDA -250 mV
VDDA -250 mV
-
-
-
Degraded mode(2) VRS = 01
VRS = 10
Voltage reference
See
VREFOUT_ output spread over
Figure 31,
Figure 32,
Figure 33
VDDA = 3V
-
-
mV
the temperature
range
TEMP
Trim step
resolution
TRIM
CL
-
-
-
-
0.5
-
±0.05
±0.1
1.5
2
%
µF
Ω
Load capacitor
1
-
Equivalent Serial
Resistor of Cload
esr
Iload
Static load current
Line regulation
-
-
-
-
6.5
mA
(3)
Iline_reg
-
500 μA ≤
1000
2000
ppm/V
Normal
mode
ppm/m
A
Iload_reg
Load regulation
-
50
500
I
load ≤4 mA
-40 °C < TJ < +125 °C
0 °C < TJ < +50 °C
-
-
-
-
Tcoeff_vr
efint +
50(4)
Temperature
coefficient
TCoeff
ppm/ °C
dB
DC
40
25
-
55
40
-
Power supply
rejection
PSRR
100 kHz
-
CL = 0.5 µF(5)
CL = 1.1 µF(5)
CL = 1.5 µF(5)
300
500
650
350
650
800
tSTART
Start-up time
-
µs
-
140/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1)
Table 72. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Control of
maximum DC
current drive on
VREFBUF_
IINRUSH
-
-
8
-
mA
OUT during start-
up phase (6)
Iload = 0 µA
load = 500 µA
-
-
-
-
16
18
35
45
25
30
50
80
VREFBUF
consumption from
VDDA
I
IDDA(VREF
BUF)
µA
Iload = 4 mA
Iload = 6.5 mA
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (VDDA - drop
voltage).
3. Line regulation is given for overall supply variation, in normal mode.
4. Tcoeff_vrefint refer to Tcoeff parameter in the embedded voltage reference section.
5. The capacitive load must include a 100 nF low ESR capacitor in order to cut-off the high frequency noise.
6. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V], [2.8 V to 3.6 V] and [3.135 V to 3.6 V] respectively for VRS=0,1 and 2.
Figure 31. V
in case VRS = 00
REFOUT_TEMP
V
2.06
2.055
2.05
2.045
2.04
2.035
2.03
2.025
-40
-20
0
20
Mean
40
60
80
100
120 °C
Min
Max
MSv62522V1
DS12589 Rev 3
141/197
160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
Figure 32. V
in case VRS = 01
REFOUT_TEMP
V
2.51
2.505
2.5
2.495
2.49
2.485
2.48
2.475
-40
-20
0
20
40
60
80
100
120 °C
Mean
Min
Max
MSv62523V1
Figure 33. V
in case VRS = 10
REFOUT_TEMP
V
2.91
2.905
2.9
2.895
2.89
2.885
2.88
2.875
2.87
-40
-20
0
20
Mean
40
60
80
100
120 °C
Min
Max
MSv62524V1
142/197
DS12589 Rev 3
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Electrical characteristics
5.3.21
Comparator characteristics
(1)
Table 73. COMP characteristics
Symbol
VDDA
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
-
1.62
-
3.6
Comparator input voltage
range
VIN
-
0
-
VDDA
V
(2)
VBG
Scaler input voltage
Scaler offset voltage
-
-
VREFINT
±5
(3)
VSC
-
-
-
-
±10
300
1
mV
nA
µA
µs
BRG_EN=0 (bridge disable)
200
Scaler static consumption from
VDDA
I
DDA(SCALER)
BRG_EN=1 (bridge enable)
-
0.8
tSTART_SCALER Scaler startup time
Comparator startup time to
100
200
tSTART
reach propagation delay
specification
-
-
-
5
µs
VDDA < 2.7 V
-
-
-
35
31
ns
ns
Propagation delay for 200 mV 50pF load on
(4)
tD
step with 100 mV overdrive
output
VDDA ≥2.7 V
16.7
Full VDDA voltage range, full
temperature range
(3)
Voffset
Comparator offset error
-9
-6/+2
3
mV
HYST[2:0] = 0
HYST[2:0] =1
HYST[2:0] = 2
HYST[2:0] = 3
HYST[2:0] = 4
HYST[2:0] = 5
HYST[2:0] = 6
HYST[2:0] = 7
Static
-
0
9
-
4
16
32
47
63
79
95
110
720
7
18
27
36
45
54
63
450
11
15
19
23
26
-
Vhys
Comparator hysteresis
mV
Comparator consumption from
VDDA
IDDA(COMP)
µA
With 50 kHz ±100 mV overdrive
square signal
-
450
-
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 20: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Typical value (3V) is an average for all comparators propagation delay.
DS12589 Rev 3
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Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
5.3.22
Operational amplifiers characteristics
(1) (2)
Table 74. OPAMP characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VDDA
CMIR
Analog supply voltage
-
2
3.3
3.6
V
V
Common mode input
range
-
0
-
VDDA
25 °C, No Load on output.
All voltage/temperature.
-
-
-
-
±1.5
±3
VIOFFSET
Input offset voltage
mV
Input offset voltage
drift
ꢀVIOFFSET
-
-
-
-
±10
1.1
-
μV/°C
Offset trim step at low
common input voltage
TRIMOFFSE
TP
1.2
(0.1 ₓ VDDA
)
mV
Offset trim step at high
common input voltage
TRIMOFFSE
TN
-
-
1.3
1.65
(0.9 ₓ VDDA
)
ILOAD
ILOAD_PGA
CLOAD
Drive current
-
-
-
-
-
-
-
-
-
-
500
270
50
-
µA
Drive current in PGA
mode
Capacitive load
-
pF
dB
Common mode
rejection ratio
CMRR
60
Power supply rejection CLOAD ≤ 50 pf,
PSRR
GBW
-
80
13
-
-
dB
ratio
RLOAD ≥ 4 kΩ DC Vcom=VDDA/2
Gain Bandwidth
Product
100mV ≤ Output dynamic range ≤ VDDA -
100mV
7
MHz
Slew rate
(from 10 and 90% of
output voltage)
Normal mode
2.5
18
6.5
45
-
-
SR(3)
V/µs
dB
High-speed mode
100mV ≤ Output dynamic range ≤ VDDA
100mV
-
65
75
95
95
-
-
AO
Open loop gain
200mV ≤ Output dynamic range ≤ VDDA -
200mV
-
-
High saturation
voltage
Iload = max or Rload = min Input at VDDA
.
VDDA
- 100
(3)
VOHSAT
Follower mode
mV
I
load = max or Rload = min Input at 0.
(3)
VOLSAT
Low saturation voltage
-
-
100
Follower mode
φm
Phase margin
Gain margin
Follower mode, Vcom=VDDA/2
Follower mode, Vcom=VDDA/2
-
-
65
10
-
-
°
GM
dB
144/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1) (2)
Table 74. OPAMP characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
follower
Normal mode
-
3
6
configuration
Wake up time from
OFF state.
tWAKEUP
µs
CLOAD ≤ 50 pf,
RLOAD
≥
High-speed mode
20 kΩ
-
3
6
follower
configuration
OPAMP input bias
current
Ibias
See lleak parameter in Table 53: I/O static characteristics for given pin.
PGA Gain = 2 0.1 ≤ Out
V
DDA < 2.2
-2
-1
-
-
2
1
dynamic range ≤ VDDA
-
VDDA ≥ 2.2
0.1
PGA Gain=4, 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
-1
-1
-1
-2
-2
-
-
-
-
-
1
1
1
2
2
PGA Gain=8 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
Non inverting gain
value(4)
%
PGA Gain=16, 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
PGA Gain=32 200mV ≤ Output ≤ VDDA
200mV
-
PGA Gain=64 200mV ≤ Output dynamic
range ≤ VDDA - 200mV
PGA gain
PGA Gain = -1
V
DDA < 2.2
-2
-1
-
-
2
1
100mV ≤ Output dynamic
range ≤ VDDA - 100mV
VDDA ≥ 2.2
PGA Gain=-3, 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
-1
-1
-1
-2
-5
-
-
-
-
-
1
1
1
2
2
PGA Gain=-7 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
Inverting gain value
%
PGA Gain=-15, 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
PGA Gain=-31 200mV ≤ Output ≤ VDDA
200mV
-
PGA Gain=-63 200mV ≤ Output dynamic
range ≤ VDDA - 200mV
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
(1) (2)
Table 74. OPAMP characteristics
Parameter Conditions
(continued)
Min
Symbol
Typ
Max Unit
PGA Gain = 2
PGA Gain = 4
PGA Gain = 8
PGA Gain = 16
PGA Gain = 32
PGA Gain = 64
PGA Gain = -1
PGA Gain = -3
PGA Gain = -7
-
-
-
-
-
-
-
-
-
-
-
-
10/10
30/10
-
-
-
-
-
R2/R1 internal
resistance values in
non-inverting PGA
mode(5)
70/10
150/10
310/10
630/10
10/10
-
kΩ/k
Ω
Rnetwork
-
30/10
-
-
-
-
-
R2/R1 internal
70/10
resistance values in
inverting PGA mode(5)
PGA Gain = -15
PGA Gain = -31
PGA Gain = -63
150/10
310/10
630/10
Resistance variation
(R1 or R2)
Delta R
-
-15
-
+15
%
Gain = 2
-
GBW/2
GBW/4
GBW/8
GBW/16
GBW/32
GBW/64
GBW/2
GBW/4
GBW/8
GBW/16
GBW/32
GBW/64
250
-
Gain = 4
-
-
PGA bandwidth for
different non inverting
gain
Gain = 8
-
-
MHz
Gain = 16
Gain = 32
Gain = 64
Gain = -1
Gain = -3
Gain = -7
Gain = -15
Gain = -31
Gain = -63
-
-
-
-
-
-
PGA BW
-
-
-
-
-
-
PGA bandwidth for
different inverting gain
MHz
-
-
-
-
-
-
-
at 1 kHz, Output loaded with 4 kΩ
at 10 kHz, Output loaded with 4 kΩ
-
nV/√
Hz
eN
Voltage noise density
-
90
-
Normal mode
No load,
-
-
1.3
2.2
2.6
-
OPAMP consumption
from VDDA
IDDA(OPAMP)
mA
ns
follower mode
High-speed mode
VDDA < 2V
1.4
ADC sampling time
TS_OPAMP_VO when reading the
300
-
OPAMP output.
OPAINTOEN=1
UT
VDDA ≥ 2V
200
-
-
OPAMP consumption Normal mode
-
-
0.45
0.5
0.7
0.8
I
DDA(OPAMPI
no load,
follower mode
from VDDA
.
mA
NT)
High-speed mode
OPAINTOEN=1
146/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
1. Guaranteed by design, unless otherwise specified.
2. Data guaranteed on normal and high speed mode unless otherwise specified.
3. Guaranteed by characterization results.
4. Valid also for inverting gain configuration with external bias.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
Figure 34. OPAMP noise density @ 25°C
MSv62525V1
DS12589 Rev 3
147/197
160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
5.3.23
Temperature sensor characteristics
Table 75. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VTS linearity with temperature
-
±1
2.5
±2
2.7
°C
mV/°C
V
Avg_Slope(1) Average slope
2.3
V30
Voltage at 30°C (±5 °C)(2)
0.742
0.76
0.785
(1)
tSTART-RUN
Start-up time in Run mode (start-up of buffer)
-
-
8
15
µs
µs
Start-up time when entering in continuous
mode
(3)
tSTART_CONT
70
120
ADC sampling time when reading the
temperature
(1)
tS_temp
5
-
-
-
µs
Temperature sensor consumption from VDD,
when selected by ADC
IDD(TS)(1)
4.7
7
µA
1. Guaranteed by design.
2. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer
to Table 5: Temperature sensor calibration values.
3. Continuous mode means RUN mode or Temperature Sensor ON.
5.3.24
V
monitoring characteristics
BAT
(1)
Table 76. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
3x39
-
-
kΩ
-
Ratio on VBAT measurement
Error on Q
3
-
Er(2)
-10
12
10
-
%
µs
(2)
tS_vbat
ADC sampling time when reading the V
-
BAT
1. 1.55 V < VBAT < 3.6 V.
2. Guaranteed by design.
Table 77. V
charging characteristics
BAT
Symbol
Parameter Conditions
Min
Typ
5
Max
Unit
VBRS = 0
VBRS = 1
-
-
-
-
Battery
charging
resistor
RBC
kΩ
1.5
148/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
5.3.25
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
(2)
Table 78. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
-
1
5.88
0
-
tTIMxCLK
ns
tres(TIM)
Timer resolution time
fTIMxCLK = 170 MHz
-
-
Timer external clock
frequency on CH1 to
CH4
f
TIMxCLK/2
MHz
fEXT
fTIMxCLK = 170 MHz
0
85
MHz
bit
TIMx (except TIM2)
-
-
16
32
ResTIM
Timer resolution
TIM2
-
1
65536
385.5
tTIMxCLK
µs
16-bit counter clock
period
tCOUNTER
fTIMxCLK = 170 MHz 0.00588
Maximum possible
tMAX_COUNT count with 32-bit
counter
-
-
-
65536 × 65536
25.26
tTIMxCLK
fTIMxCLK = 170 MHz
s
-
0
0
fTIMxCLK/4
42.5
MHz
MHz
Encoder frequency on
fENC
TI1 and TI2 input pins
fTIMxCLK = 170MHz
Index pulsewidth on
tW(INDEX)
-
-
2
-
Tck
ETR input
Min pulsewidth
on TI1 and TI2 inputs
in all encoder modes
except directional
2
-
Tck
tW(TI1, TI2)
clock x1
Min pulsewidth
on TI1 and TI2 inputs
in directional clock x1
-
3
-
Tck
1. TIMx, is used as a general term in which x stands for 1,2,3,4,6,7,8,15,16, or 17.
2. Guaranteed by design.
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
(1)(2)
Table 79. IWDG min/max timeout period at 32 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
0
0.125
0.250
0.500
1.0
512
1024
2048
4096
8192
16384
32768
/8
1
/16
2
/32
3
4
ms
/64
2.0
/128
/256
5
4.0
6 or 7
8.0
1. Guaranteed by design.
2. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
(1)
Table 80. WWDG min/max timeout value at 170 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0241
0.0482
0.0964
0.1928
1.542
3.084
6.168
12.336
ms
1. Guaranteed by design.
5.3.26
Communication interfaces characteristics
I2C interface characteristics
2
The I2C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
®
configured (refer to reference manual RM0440 "STM32G4 Series advanced Arm -based
32-bit MCUs") and when the I2CCLK frequency is greater than the minimum shown in the
table below.
150/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
Table 81. Minimum I2CCLK frequency in all I2C modes
Symbol
Parameter
Condition
Min
Unit
Standard mode
Fast-mode
2
Analog Filtre ON
DNF=0
8
9
Analog Filtre OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
MHz
Analog Filtre ON
DNF=0
17
16
Fast-mode
Plus
Analog Filtre OFF
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but is still present.
DDIOx
•
The 20mA output drive requirement in Fast-mode Plus is supported partially. This limits
the maximum load Cload supported in Fm+, which is given by these formulas:
–
–
t (SDA/SCL)=0.8473 x R x C
r p load
R (min)= (V - V (max)) / I (max)
p
DD
OL
OL
Where Rp is the I2C lines pull-up. Refer to Section 5.3.14: I/O port characteristics for the
I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 82 below for the analog
filter characteristics:
(1)
Table 82. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes that
are suppressed by the analog filter
tAF
50(2)
90(3)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI characteristics
Unless otherwise specified, the parameters given in Table 83 for SPI are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 17: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
DS12589 Rev 3
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Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 83. SPI characteristics
Conditions
Symbol
Parameter
Min
Typ
Max(2) Unit
Master mode
2.7 V < VDD < 3.6 V
Voltage Range V1
75
Master mode
1.71 V < VDD < 3.6 V
Voltage Range V1
50
50
Master transmitter mode
1.71 V < VDD < 3.6 V
Voltage Range V1
Slave receiver mode
1.71 V < VDD < 3.6 V
Voltage Range V1
fSCK
1/tc(SCK)
SPI clock frequency
-
-
MHz
50
41
27
13
Slave mode transmitter/full duplex
2.7 V < VDD < 3.6 V
Voltage Range V1
Slave mode transmitter/full duplex
1.71 V < VDD < 3.6 V
Voltage Range V1
1.71 V < VDD < 3.6 V
Voltage Range V2
tsu(NSS) NSS setup time
th(NSS) NSS hold time
tw(SCKH)
Slave mode
Slave mode
4*Tpclk
2*Tpclk
-
-
-
-
-
-
SCK high and low time Master mode, SPI prescaler = 2
Tpclk-1
Tpclk
Tpclk+1
ns
ns
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
Master mode
Data input setup time
4
3
4
1
9
9
-
-
-
-
-
-
-
-
Slave mode
Master mode
Data input hold time
-
ns
th(SI)
Slave mode
-
ta(SO) Data output access time Slave mode
tdis(SO) Data output disable time Slave mode
34
16
ns
ns
152/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1)
Table 83. SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max(2) Unit
Slave mode
2.7 V < VDD < 3.6 V
Voltage Range V1
-
9
12
Slave mode
tv(SO)
1.71 V < VDD < 3.6 V
Voltage Range V1
-
-
9
18
Data output valid time
Slave mode
1.71 V < VDD < 3.6 V
Voltage Range V2
ns
22
13
tv(MO)
th(SO)
th(MO)
Master mode
-
3.5
4.5
Slave mode 1.71 V < VDD < 3.6 V
Slave mode Range V2
Master mode
6
9
2
-
-
-
-
-
-
Data output hold time
1. Guaranteed by characterization results.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into
SCK low or high-phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
Figure 35. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
Figure 36. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
Last bit OUT
MOSI input
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 37. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
I2S characteristics
Electrical characteristics
Unless otherwise specified, the parameters given in Table 84 for I2S are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 17: General operating conditions, with the following
configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30pF
Measurement points are done at CMOS levels: 0.5 V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
(1)
Table 84. I2S characteristics
Uni
t
Symbol
fMCLK
fCK
Parameter
Conditions
Min
Max
I2S Main clock
output
256x8
K
256
MH
z
-
*Fs(2)
Master data
Slave data
-
-
64xFs
64xFs
MH
z
I2S clock frequency
I2S clock frequency
duty cycle
DCK
Slave receiver
30
70
%
tv(WS)
WS valid time
WS hold time
WS setup time
Master mode
Master mode
Slave mode
-
3
2
4
3
4
4
2
-
6
-
th(WS)
-
tsu(WS)
Slave mode
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
-
Data input setup
time
-
-
ns
Data input hold time
-
2.7 V ≤ VDD ≤ 3.6 V
1.65 V ≤ VDD ≤ 3.6 V
15
22
3
-
Slave transmitter (after
enable edge)
tv(SD_ST)
Data output valid
time
-
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
-
7
1
Data output hold
time
-
1. Guaranteed by characterization results, not tested in production.
2. 256xFs maximum is 49.152 MHz.
®
Note:
Refer to the reference manual RM0440 "STM32G4 Series advanced Arm -based 32-bit
MCUs" I2S section for more details about the sampling frequency (Fs), f
, f , D
MCK CK
CK
values reflect only the digital peripheral behavior, source clock precision might slightly
change the values D depends mainly on ODD bit value. Digital contribution leads to a min
CK
of (I2SDIV/(2*I2SDIV+ODD) and a max (I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max
supported for each mode/condition.
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
SAI characteristics
Unless otherwise specified, the parameters given in Table 85 for SAI are derived from tests
performed under the ambient temperature, f frequency and V supply voltage condi-
PCLKx
DD
tions summarized inTable 17: General operating conditions, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,FS).
156/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Electrical characteristics
(1)
Table 85. SAI characteristics
Symbol
Parameter
Conditions
Min
Max Unit
fMCLK
SAI Main clock output
-
-
50
33
MHz
Master transmitter
2.7 V ≤ VDD ≤ 3.6 V
-
Voltage Range 1
Master transmitter
1.71 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
-
-
22
22
45
Master receiver
Voltage Range 1
Slave transmitter
2.7 V ≤ VDD ≤ 3.6 V
Voltage Range 1
fCK
SAI clock frequency(2)
MHz
Slave transmitter
1.71 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
29
Slave receiver
Voltage Range 1
-
-
-
-
50
13
15
22
Slave transmitter
Voltage Range 2
Master mode
2.7 V ≤ VDD ≤ 3.6 V
tv(FS)
FS valid time
ns
Master mode
1.71 V ≤ VDD ≤ 3.6 V
th(FS)
tsu(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
10
2
-
-
-
-
-
-
-
ns
ns
ns
th(FS)
Slave mode
1
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
2.5
1
Data input setup time
Data input hold time
ns
ns
5
1
Slave transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
-
-
11
17
Slave transmitter (after enable edge)
1.71 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time
ns
ns
Slave transmitter (after enable edge)
voltage range V2
-
20
-
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge)
10
DS12589 Rev 3
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160
Electrical characteristics
Symbol
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 85. SAI characteristics (continued)
Parameter
Conditions
Min
Max Unit
Master transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
-
14
ns
21
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
1.71 V ≤ VDD ≤ 3.6 V
-
th(SD_A_MT) Data output hold time Master transmitter (after enable edge)
10
-
ns
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
Figure 38. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 39. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
CAN (controller area network) interface
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCANx_TX and FDCANx_RX).
158/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
USB characteristics
Electrical characteristics
The device USB interface is fully compliant with the USB specification version 2.0 and is
USB-IF certified (for Full-speed device operation).
(1)
Table 86. USB electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
USB transceiver operating voltage
3.0(2)
-15
-
3.6
85
V
tCrystal_less USB crystal less operation temperature
-
°C
RPUI
Embedded USB_DP pull-up value during idle
Embedded USB_PD pull-up value during reception
Output driver impedance(4)
Driving high and low
900
1400
28
1250
2300
36
1500
3200
44
ꢁ
ꢁ
RPUR
(3)
ZsDRV
1. TA = -40 to 125 °C unless otherwise specified.
2. The device USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics, which are degraded in
the 2.7-to-3.0 V voltage range.
3. Guarantee by design.
4. No external termination series resistors are required on USB_PD (D+) and USB_DM (D-); the matching impedance is
already included in the embedded driver.
USART interface characteristics
Unless otherwise specified, the parameters given in Table 87 for USART are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 87, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30 pF
Measurement points are done at CMOS levels: 0.5 V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
(1)
Table 87. USART electrical characteristics
Symbol
Parameter
Conditions
Master mode
Min
Typ
Max
Unit
-
-
-
-
-
21
22
-
fCK
USART clock frequency
MHz
Slave mode
Slave mode
Slave mode
-
tker + 2
2
tsu(NSS)
th(NSS)
NSS setup time
NSS hold time
ns
-
tw(CKH)
tw(CKL)
CK high and low time
Data input setup time
Master mode
1/fck/2-1
1/fck/2 1/fck/2+1 ns
Master mode
Slave mode
Master mode
Slave mode
tker + 2
-
-
-
-
-
-
-
-
tsu(RX)
th(RX)
2
1
ns
Data input hold time
0.5
DS12589 Rev 3
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160
Electrical characteristics
STM32G431x6 STM32G431x8 STM32G431xB
(1)
Table 87. USART electrical characteristics (continued)
Symbol
Parameter
Conditions
Master mode
Min
Typ
Max
Unit
-
-
0.5
10
-
1.5
22
-
tv(TX)
Data output valid time
Slave mode
Master mode
Slave mode
ns
0
7
th(RX)
Data output hold time
-
-
1. Based on characterization, not tested in production.
5.3.27
UCPD characteristics
UCPD1 controller complies with USB Type-C Rev.1.2 and USB Power Delivery Rev. 3.0
specifications.
Table 88. UCPD characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Sink mode only
3.0
3.3
3.3
3.6
V
V
VDD
UCPD operating supply voltage
Sink and source mode
3.135
3.465
160/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1
UFQFPN32 package information
UFQFPN32 is a 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package.
Figure 40. UFQFPN32 - outline
D
A
ddd C
A1
A3
e
C
SEATINGPLANE
D1
b
e
b
E2
E1
E
1
L
32
D2
L
PIN 1 Identifier
A0B8_ME_V3
1. Drawing is not to scale.
2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.
DS12589 Rev 3
161/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
Table 89. UFQFPN32 - mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.500
-
0.550
-
0.600
0.050
-
0.0197
-
0.0217
-
0.0236
0.0020
-
-
0.152
0.230
5.000
3.500
3.500
5.000
3.500
3.500
0.500
0.400
-
-
0.0060
0.0091
0.1969
0.1378
0.1378
0.1969
0.1378
0.1378
0.0197
0.0157
-
0.180
4.900
3.400
3.400
4.900
3.400
3.400
-
0.280
5.100
3.600
3.600
5.100
3.600
3.600
-
0.0071
0.1929
0.1339
0.1339
0.1929
0.1339
0.1339
-
0.0110
0.2008
0.1417
0.1417
0.2008
0.1417
0.1417
-
D
D1
D2
E
E1
E2
e
L
0.300
-
0.500
0.080
0.0118
-
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 41. UFQFPN32 - recommended footprint
5.30
3.80
0.60
25
32
1
24
3.45
3.80
5.30
3.45
0.50
8
17
0.30
16
9
0.75
3.80
A0B8_FP_V2
1. Dimensions are expressed in millimeters.
162/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
UFQFPN32 device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 42. UFQFPN32 top view example
Product
(1)
identification
32G431KBU6
Revision code
Date code
R
WW
Y
Pin 1
identification
MSv62537V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12589 Rev 3
163/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
6.2
LQFP32 package information
LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.
Figure 43. LQFP32 - outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
K
D
D1
D3
17
L
L1
24
16
25
32
9
PIN 1
IDENTIFICATION
1
8
e
5V_ME_V2
1. Drawing is not to scale.
164/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
inches(1)
Table 90. LQFP32 - mechanical data
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.300
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.450
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
-
-
-
1.400
0.370
-
0.0551
0.0146
-
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 44. LQFP32 - recommended footprint
0.80
1.20
24
17
25
16
0.50
0.30
7.30
6.10
9.70
7.30
32
9
8
1
1.20
6.10
9.70
5V_FP_V2
1. Dimensions are expressed in millimeters.
DS12589 Rev 3
165/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
LQFP32 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 45. LQFP32 top view example
Product
identification
(1)
STM32G
431KBT6
Date code
Y
WW
Pin 1
identification
Revision code
R
MSv62532V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
166/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
6.3
UFQFPN48 package information
UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 46. UFQFPN48 - outline
Pin 1 identifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500x45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DS12589 Rev 3
167/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
Table 91. UFQFPN48 - mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 47. UFQFPN48 - recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
168/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
UFQFPN48 device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 48. UFQFPN48 top view example
Product
identification
(1)
STM32G
431CBU6
Date code
Y
WW
Pin 1
identification
Revision code
R
MSv62529V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12589 Rev 3
169/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
6.4
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Figure 49. LQFP48 - outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
36
25
37
24
b
48
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
170/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
inches(1)
Table 92. LQFP48 - mechanical data
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS12589 Rev 3
171/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
Figure 50. LQFP48 - recommended footprint
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
172/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
LQFP48 device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 51. LQFP48 top view example
Product
identification
(1)
STM32G431
CBT6
Date code
Y
WW
Pin 1
identification
Revision code
R
MSv62526V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12589 Rev 3
173/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
6.5
WLCSP49 package information
WLCSP49 is a 49-ball, 3.15 x 3.13 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 52. WLCSP49 - outline
A1 ORIENTATION REFERENCE
F
bbb Z
G
e1
D
A1
DETAIL A
E
e2
e
A
e
aaa
A2
(4x)
BOTTOM VIEW
TOP VIEW
SIDE VIEW
BUMP
A2
A3
A1
eeeZ
b
FRONT VIEW
Z
b(49x)
ccc
ddd
Z
Z
X Y
SEATING PLANE
DETAIL A
ROTATED 90
B03Q_WLCSP49_DIE468_ME_V1
1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
174/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
inches(1)
Table 93. WLCSP49 - mechanical data
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
A(2)
A1
-
-
0.59
-
-
0.023
-
0.18
0.38
0.025
0.25
3.15
3.13
0.40
2.40
2.40
0.375
0.365
0.10
0.10
0.10
0.05
0.05
-
-
0.007
0.015
0.001
0.010
0.124
0.123
0.016
0.094
0.094
0.015
0.014
0.004
0.004
0.004
0.002
0.002
-
A2
-
-
-
-
A3(3)
b(4)
D
-
-
-
-
0.22
0.28
0.009
0.011
3.13
3.17
0.123
0.125
E
3.11
3.15
0.122
0.124
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
F(5)
G(5)
aaa
bbb
ccc
ddd
eee
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capabili-
ty.
4. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
5. Calculated dimensions are rounded to the 3rd decimal place
DS12589 Rev 3
175/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
Figure 53. WLCSP49 - recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
1. Dimensions are expressed in millimeters.
Table 94. WLCSP49 recommended PCB design rules
Recommended values
Dimension
Pitch
0.4 mm
Dpad
0,225 mm
Dsm
0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
176/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
WLCSP49 device marking
Package information
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 54. WLCSP49 top view example
Ball 1
identification
Product
identification
(1)
G431CB6
Date code
Revision code
Y
WW
R
MSv62539V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12589 Rev 3
177/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
6.6
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 55. LQFP64 - outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
L1
D1
D3
33
48
32
49
64
b
17
16
e
1
PIN 1
IDENTIFICATION
5W_ME_V3
1. Drawing is not to scale.
Table 95. LQFP64 - mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
-
-
-
-
12.000
10.000
7.500
12.000
10.000
-
-
-
-
-
-
-
-
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
-
-
-
-
-
D1
D3
E
E1
178/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
Table 95. LQFP64 - mechanical data (continued)
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
E3
e
-
7.500
0.500
3.5°
-
-
0.2953
0.0197
3.5°
-
-
-
7°
-
-
7°
K
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 56. LQFP64 - recommended footprint
48
33
0.3
0.5
49
32
12.7
10.3
10.3
7.8
17
64
1.2
16
1
12.7
ai14909c
1. Dimensions are expressed in millimeters.
DS12589 Rev 3
179/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
LQFP64 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 57. LQFP64 top view example
Product
identification
(1)
STM32G431
RBT6
Date code
Y
WW
Pin 1
identification
Revision code
R
MSv62530V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
180/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
6.7
UFBGA64 package information
UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package.
Figure 58. UFBGA64 outline
Z Seating plane
ddd Z
A4
A3 A2
A1
A
E1
X
A1 ball
A1 ball
E
identifier index area
e
F
A
F
D1
D
e
Y
H
8
1
Øb (64 balls)
Øeee M Z Y X
Øfff M Z
BOTTOM VIEW
TOP VIEW
A019_ME_V1
1. Drawing is not to scale.
Table 96. UFBGA64 – Mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
A3
A4
b
0.460
0.050
0.400
0.080
0.270
0.170
4.850
3.450
4.850
3.450
-
0.530
0.080
0.450
0.130
0.320
0.280
5.000
3.500
5.000
3.500
0.500
0.750
0.600
0.110
0.500
0.180
0.370
0.330
5.150
3.550
5.150
3.550
-
0.0181
0.0020
0.0157
0.0031
0.0106
0.0067
0.1909
0.1358
0.1909
0.1358
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.1969
0.1378
0.1969
0.1378
0.0197
0.0295
0.0236
0.0043
0.0197
0.0071
0.0146
0.0130
0.2028
0.1398
0.2028
0.1398
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
DS12589 Rev 3
181/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
Table 96. UFBGA64 – Mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
0.460
0.530
0.600
0.080
0.150
0.050
0.0181
0.0209
0.0236
0.0031
0.0059
0.0020
ddd
eee
fff
-
-
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 59. UFBGA64 recommended footprint
Dpad
Dsm
A019_FP_V2
Table 97. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the solder mask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.280 mm
Between 0.100 mm and 0.125 mm
0.100 mm
182/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
UFBGA64 device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 60. UFBGA64 top view example
Product
G431RBI6
(1)
identification
Date code
WW
Y
Revision code
R
Pin 1
identification
MSv62538V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12589 Rev 3
183/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
6.8
LQFP80 package information
LQFP80 is a 80-pin, 12 x 12 mm low-profile quad flat package.
Figure 61. LQFP80 - outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
L
k
D
L1
D1
D3
60
41
61
40
80
21
PIN 1
IDENTIFICATION
1
20
e
9X_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
Table 98. LQFP80 - mechanical data
Millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.050
1.350
0.170
0.090
-
0.0020
0.0531
0.0067
0.0035
-
1.400
0.220
-
0.0551
0.0087
-
c
184/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
Table 98. LQFP80 - mechanical data (continued)
Millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
D
D1
D2
E
-
14.000
12.000
9.500
14.000
12.000
9.500
0.500
0.600
1.000
-
-
-
0.5512
0.4724
0.3740
0.5512
0.4724
0.3740
0.0197
0.0236
0.0394
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E1
E3
e
-
-
-
-
-
-
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
ccc
k
-
-
-
-
0.080
7.0°
0.0031
7.0°
0.0°
-
0.0°
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 62. LQFP80 - recommended footprint
80
61
1
0.5
60
20
41
1.2
21
40
9.8
14.7
9X_FP
1. Dimensions are expressed in millimeters.
DS12589 Rev 3
185/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
LQFP80 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 63. LQFP80 top view example
Product
identification
(1)
STM32G431
MBT6
Revision code
R
Date code
Y WW
Pin 1
identification
MSv62536V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
186/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Package information
6.9
LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 64. LQFP100 - outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
75
C
D
D1
D3
L
L1
51
50
76
100
26
PIN 1
IDENTIFICATION
25
1
e
1L_ME_V5
1. Drawing is not to scale.
Table 99. LQPF100 - mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
0.6299
0.5512
0.4724
D1
D3
DS12589 Rev 3
187/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
Table 99. LQPF100 - mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E
E1
E3
e
15.800
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
16.200
0.6220
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.6378
13.800
14.200
0.5433
0.5591
-
-
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
-
0.0°
-
7.0°
0.080
7.0°
0.0031
ccc
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 65. LQFP100 - recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
188/197
DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
LQFP100 device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 66. LQFP100 top view example
Product
identification
(1)
STM32G431
VBT6
Revision code
R
Date code
Y WW
Pin 1
identification
MSv62534V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12589 Rev 3
189/197
193
Package information
STM32G431x6 STM32G431x8 STM32G431xB
6.10
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ ((V
– V ) × I ),
I/O
OL
OL
DDIOx OH OH
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 100. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm
48.9
49.7
50.8
58.4
58.4
44.2
28.6
36.7
59
Thermal resistance junction-ambient
LQFP80 - 12 × 12 mm
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
Thermal resistance junction-ambient
LQFP32 - 7 × 7 mm
ΘJA
°C/W
Thermal resistance junction-ambient
UFBGA64 - 5 × 5 mm
Thermal resistance junction-ambient
UFQFPN48 - 7 × 7 mm
Thermal resistance junction-ambient
UFQFPN32 - 5 × 5 mm
Thermal resistance junction-ambient
WLCSP49 - pitch 0.4
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Package information
Table 100. Package thermal characteristics (continued)
Symbol
Parameter
Value
Unit
Thermal resistance junction-case
LQFP100 - 14 × 14 mm
10.3
Thermal resistance junction-case
LQFP80 - 12 × 12 mm
10.3
10.1
11.9
Thermal resistance junction-case
LQFP64 - 10 × 10 mm
Thermal resistance junction-case
LQFP48 - 7 × 7 mm
Thermal resistance junction-case
LQFP32 - 7 × 7 mm
11.9
ΘJC
°C/W
Thermal resistance junction-case
UFBGA64 - 5 × 5 mm
14.78
Thermal resistance junction-case
UFQFPN48 - 7 × 7 mm
3.1(1)
9.4
3.4(1)
14.2
Thermal resistance junction-case
UFQFPN32 - 5 × 5 mm
Thermal resistance junction-case
WLCSP49 - pitch 0.4
2.33
25.7
25.1
24.7
27.7
27.7
22.5
15.7
18.6
38.12
Thermal resistance junction-board
LQFP100 - 14 × 14 mm
Thermal resistance junction-board
LQFP80 - 12 × 12 mm
Thermal resistance junction-board
LQFP64 - 10 × 10 mm
Thermal resistance junction-board
LQFP48 - 7 × 7 mm
Thermal resistance junction-board
ΘJB
°C/W
LQFP32 - 7 × 7 mm
Thermal resistance junction-board
UFBGA64 - 5 × 5 mm
Thermal resistance junction-board
UFQFPN48 - 7 × 7 mm
Thermal resistance junction-board
UFQFPN32 - 5 × 5 mm
Thermal resistance junction-board
WLCSP49 - pitch 0.4
1. Thermal resistance junction-case where the case is the bottom thermal pad on the UFQFPN package.
6.10.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
DS12589 Rev 3
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Package information
STM32G431x6 STM32G431x8 STM32G431xB
6.10.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 7: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32G431xB at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
50 mA × 3.5 V= 175 mW
INTmax =
20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax =
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
175 272 = 447 mW
+
Dmax =
Using the values obtained in T
is calculated as follows:
Jmax
–
T
For LQFP100, 42 °C/W
= 82 °C + (42 °C/W × 447 mW) = 82 °C + 18.774 °C = 100.774 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Section 7:
J
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 7: Ordering information).
Note:
With this given P
we can find the TAmax allowed for a given device temperature range
Dmax
(order code suffix 6 or 7).
Suffix 6: T
Suffix 3: T
= T
= T
- (42°C/W × 447 mW) = 105-18.774 = 86.226 °C
Amax
Amax
Jmax
Jmax
- (42°C/W × 447 mW) = 130-18.774 = 111.226 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
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DS12589 Rev 3
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Package information
Assuming the following application conditions:
Maximum ambient temperature T
= 100 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
20 mA × 3.5 V= 70 mW
INTmax =
× 8 mA × 0.4 V = 64 mW
IOmax = 20
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
70 64 = 134 mW
Dmax =
+
Thus: P
= 134 mW
Dmax
Using the values obtained in T
is calculated as follows:
Jmax
–
T
For LQFP100, 42 °C/W
= 100 °C + (42 °C/W × 134 mW) = 100 °C + 5.628 °C = 105.628 °C
Jmax
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 7: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
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Ordering information
STM32G431x6 STM32G431x8 STM32G431xB
7
Ordering information
Table 101. Ordering information scheme
STM32 G 431
Example:
V
B
T
6
xxx
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
G = General-purpose
Sub-family
431 = STM32G431x6/x8/xB
Pin count
K = 32 pins
C = 48/49 pins
R = 64 pins
M = 80 pins
V = 100 pins
Code size
6 = 32 Kbyte
8 = 64 Kbyte
B = 128 Kbyte
Package
I = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, - 40 to 85 °C (105 °C junction)
3 = Industrial temperature range, - 40 to 125 °C (130 °C junction)
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, contact the nearest ST sales office.
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DS12589 Rev 3
STM32G431x6 STM32G431x8 STM32G431xB
Revision history
8
Revision history
Table 102. Document revision history
Date
Revision
Changes
10-May-2019
1
Initial release.
Updated:
– Section 2: Description and Table 2: STM32G431x6/x8/xB features
and peripheral counts removing “-40 to 105°C (+ 125°C junction)”.
– Figure 1: STM32G431x6/x8/xB block diagram with 170 MHz.
– Section 3.5: Embedded SRAM.
– Section 3.20: Voltage reference buffer (VREFBUF).
– Table 3: STM32G431x6/x8/xB peripherals interconnect matrix.
– Table 17: General operating conditions.
– Table 34: Peripheral current consumption.
– Table 60: ADC characteristics.
28-Oct-2019
2
– Table 83: SPI characteristics.
– Table 100: Package thermal characteristics.
– Table 101: Ordering information scheme.
– Section 6: Package information.
Added:
– Table 65: ADC accuracy (Multiple ADCs operation) - limited test
conditions 1.
– Table 66: ADC accuracy (Multiple ADCs operation) - limited test
conditions 2.
– Table 67: ADC accuracy (Multiple ADCs operation) - limited test
conditions 3..
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Revision history
STM32G431x6 STM32G431x8 STM32G431xB
Table 102. Document revision history (continued)
Date
Revision
Changes
Updated:
– Table 2: STM32G431x6/x8/xB features and peripheral counts
timer PWM channel number.
– Section 3.5: Embedded SRAM.
– Table 12: STM32G431x6/x8/xB pin definition.
– Figure 11: STM32G431x6/x8/xB UFBGA64 ballout.
– Table 21, Table 22, Table 27, Table 28, Table 29, Table 30,
Table 31 Table 32 max current consumptions.
– Table 35: Low-power mode wakeup timings adding note.
– Table 70: DAC 15MSPS characteristics TSAMP, .dV/dt (hold phase)
and IDDA(DAC) characteristics.
20-Nov-2020
3
– Table 73: COMP characteristics IDDA(COMP).
– Table 74: OPAMP characteristics PSRR.
– Table 76: VBAT monitoring characteristics.
– Table 100: Package thermal characteristics.
– Internal voltage reference buffer (VREFBUF) at 2.9 V.
Removed:
– Current consumption in Run and Low-power run modes, code with
data processing running from Flash in single Bank, ART disable
table.
– Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ART disable table.
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DS12589 Rev 3
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS12589 Rev 3
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