STM32G474VET6XXX [STMICROELECTRONICS]
Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer;
| 型号： | STM32G474VET6XXX |
| 厂家： | 
ST |
| 描述： | Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer 静态存储器 |
| 文件： | 总236页 (文件大小：3039K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32G474xB STM32G474xC
STM32G474xE
Arm® Cortex®-M4 32-bit MCU+FPU, 170 MHz / 213 DMIPS,
128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer
Datasheet - production data
Features
®
®
• Core: Arm 32-bit Cortex -M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 170 MHz
with 213 DMIPS, MPU, DSP instructions
LQFP48 (7 x 7 mm)
WLCSP81
(4.02 x 4.27 mm)
UFQFPN48
(7 x 7 mm)
LQFP64 (10 x 10 mm)
LQFP80 (12 x 12 mm)
LQFP100 (14 x 14 mm)
LQFP128 (14 x 14 mm)
• Operating conditions:
– V , V
voltage range:
DD
DDA
UFBGA121
(6 x 6 mm)
TFBGA100
(8 x 8 mm)
1.71 V to 3.6 V
• Mathematical hardware accelerators
– CORDIC for trigonometric functions
acceleration
– Internal 32 kHz RC oscillator (± 5%)
• Up to 107 fast I/Os
– FMAC: filter mathematical accelerator
– All mappable on external interrupt vectors
• Memories
– Several I/Os with 5 V tolerant capability
– 512 Kbytes of Flash memory with ECC
support, two banks read-while-write,
proprietary code readout protection
(PCROP), securable memory area, 1 Kbyte
OTP
• Interconnect matrix
• 16-channel DMA controller
• 5 x 12-bit ADCs 0.25 µs, up to 42 channels.
Resolution up to 16-bit with hardware
– 96 Kbytes of SRAM, with hardware parity
check implemented on the first 32 Kbytes
oversampling, 0 to 3.6 V conversion range
• 7 x 12-bit DAC channels
– Routine booster: 32 Kbytes of SRAM on
instruction and data bus, with hardware
parity check (CCM SRAM)
– 3 x buffered external channels 1 MSPS
– 4 x unbuffered internal channels 15 MSPS
– External memory interface for static
memories FSMC supporting SRAM,
PSRAM, NOR and NAND memories
• 7 x ultra-fast rail-to-rail analog comparators
• 6 x operational amplifiers that can be used in
PGA mode, all terminals accessible
– Quad-SPI memory interface
• Internal voltage reference buffer (VREFBUF)
supporting three output voltages (2.048 V,
2.5 V, 2.95 V)
• Reset and supply management
– Power-on/power-down reset
(POR/PDR/BOR)
• 17 timers:
– Programmable voltage detector (PVD)
– HRTIM (Hi-Resolution and complex
waveform builder): 6 x16-bit counters,
184 ps resolution, 12 PWM
– Low-power modes: sleep, stop, standby
and shutdown
– V
supply for RTC and backup registers
BAT
– 2 x 32-bit timer and 2 x 16-bit timers with
up to four IC/OC/PWM or pulse counter
and quadrature (incremental) encoder input
• Clock management
– 4 to 48 MHz crystal oscillator
– 32 kHz oscillator with calibration
– Internal 16 MHz RC with PLL option (± 1%)
– 3 x 16-bit 8-channel advanced motor
control timers, with up to 8 x PWM
October 2020
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This is information on a product in full production.
www.st.com
STM32G474xB STM32G474xC STM32G474xE
channels, dead time generation and
emergency stop
– 5 x USART/UARTs (ISO 7816 interface,
LIN, IrDA, modem control)
– 1 x 16-bit timer with 2 x IC/OCs, one
OCN/PWM, dead time generation and
emergency stop
– 1 x LPUART
– 4 x SPIs, 4 to 16 programmable bit frames,
2
2 x with multiplexed half duplex I S
– 2 x 16-bit timers with IC/OC/OCN/PWM,
dead time generation and emergency stop
interface
– 1 x SAI (serial audio interface)
– 2 x watchdog timers (independent, window)
– 1 x SysTick timer: 24-bit downcounter
– 2 x 16-bit basic timers
– USB 2.0 full-speed interface with LPM and
BCD support
– IRTIM (infrared interface)
– 1 x low-power timer
– USB Type-C™ /USB power delivery
controller (UCPD)
• Calendar RTC with alarm, periodic wakeup
from stop/standby
• True random number generator (RNG)
• CRC calculation unit, 96-bit unique ID
• Communication interfaces
– 3 x FDCAN controller supporting flexible
data rate
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
2
– 4 x I C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus,
wakeup from stop
Table 1. Device summary
Reference
Part number
STM32G474CB, STM32G474MB, STM32G474RB,
STM32G474VB, STM32G474QB, STM32G474PB
STM32G474xB
STM32G474xC
STM32G474xE
STM32G474CC, STM32G474MC, STM32G474RC,
STM32G474VC, STM32G474QC, STM32G474PC
STM32G474CE, STM32G474ME, STM32G474RE,
STM32G474VE, STM32G474QE, STM32G474PE
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Adaptive real-time memory accelerator (ART accelerator) . . . . . . . . . . . 18
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 23
3.11 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.11.6
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16 DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 31
3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 31
3.18 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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3.18.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.18.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.18.4 Operational amplifier internal output (OPAMPxINT): . . . . . . . . . . . . . . . 33
3.19 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.21 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.1 High-resolution timer (HRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24.2 Advanced motor control timer (TIM1, TIM8, TIM20) . . . . . . . . . . . . . . . 36
3.24.3 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.24.4 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.24.5 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.24.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.24.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.24.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 39
3.26 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.28 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.29 Universal synchronous/asynchronous receiver transmitter (USART) . . . 42
3.30 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 43
3.31 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.32 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.33 Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 45
3.34 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.35 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 45
3.36 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.37 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 46
3.38 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.39 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.39.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.39.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LQFP80 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LQFP128 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
WLCSP81 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
UFBGA121 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.10 Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.11 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 86
Embedded reset and power control block characteristics . . . . . . . . . . . 86
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.3.7
5.3.8
5.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.16 High-resolution timer (HRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 137
5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.3.19 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 139
5.3.20 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 154
5.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 161
5.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.3.23 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.3.25
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
BAT
5.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.3.27 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 171
5.3.28 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.3.29 QUADSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
5.3.30 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
LQFP128 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
UFBGA121 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
6.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
6.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 231
7
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
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List of tables
STM32G474xB STM32G474xC STM32G474xE
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32G474xB/xC/xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM32G474xB/xC/xE peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SAI implementation for the features implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STM32G474xB/xC/xE pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 86
Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . . 90
Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) . . . . 92
Current consumption in Run and Low-power run modes,
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 96
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical current consumption in Run and Low-power run modes, with different codes
running from CCMSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Current consumption in Sleep and Low-power sleep mode Flash ON . . . . . . . . . . . . . . . 101
Current consumption in low-power sleep modes, Flash in power-down. . . . . . . . . . . . . . 102
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
8/236
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List of tables
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LSE
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
I/O (except FT_c) AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
I/O FT_c AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
HRTIM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
HRTIM output response to fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
HRTIM output response to external events 1 to 5
(Low-Latency mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
HRTIM output response to external events 1 to 10 (Synchronous mode ). . . . . . . . . . . . 137
HRTIM synchronization input / output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
ADC accuracy (Multiple ADCs operation) - limited test conditions 1 . . . . . . . . . . . . . . . . 150
ADC accuracy (Multiple ADCs operation) - limited test conditions 2 . . . . . . . . . . . . . . . . 151
ADC accuracy (Multiple ADCs operation) - limited test conditions 3 . . . . . . . . . . . . . . . . 152
DAC 1MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
DAC 1MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
DAC 15MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DAC 15MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
BAT
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
WWDG min/max timeout value at 170 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
DS12288 Rev 5
9/236
10
List of tables
STM32G474xB STM32G474xC STM32G474xE
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
USART electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 183
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 183
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 184
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 185
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 186
Table 100. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 101. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 188
Table 102. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 103. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 104. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 105. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 106. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 107. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 108. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 109. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 110. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 111. WLCSP81 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 112. WLCSP81 - recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 113. UFQFPN48 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 114. LQFP48 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 115. LQFP64 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 116. LQFP80 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 117. TFBGA100 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 118. TFBGA100 - recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 119. LQPF100 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 120. LQFP128 - mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 121. UFBGA121 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 122. UFBGA121 - recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 123. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 124. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 125. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32G474xB/xC/xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STM32G474xB/xC/xE UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32G474xB/xC/xE LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32G474xB/xC/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32G474xB/xC/xE LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32G474xB/xC/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. STM32G474xB/xC/xE LQFP128 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. STM32G474xB/xC/xE WLCSP81 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 12. STM32G474xB/xC/xE TFBGA100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 13. STM32G474xB/xC/xE UFBGA121 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 14. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 15. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 16. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 17. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 18. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 20. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 23. HSI16 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 24. HSI48 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 25. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
(1)
Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 28. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 30. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 31. VREFOUT_TEMP in case VRS = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 32. VREFOUT_TEMP in case VRS = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 33. VREFOUT_TEMP in case VRS = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 34. OPAMP noise density @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 35. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 36. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 37. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 38. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 39. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 40. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 182
Figure 41. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 184
Figure 42. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 43. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 44. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 45. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 46. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 47. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 48. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
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List of figures
STM32G474xB STM32G474xC STM32G474xE
Figure 49. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 50. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 196
Figure 51. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 197
Figure 52. Quad SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 53. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 54. WLCSP81 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 55. WLCSP81 - recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 56. UFQFPN48 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 57. UFQFPN48 - recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 58. UFQFPN48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 59. LQFP48 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 60. LQFP48 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 61. LQFP48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 62. LQFP64 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 63. LQFP64 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 64. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 65. LQFP80 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 66. LQFP80 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 67. LQFP80 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 68. TFBGA100 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 69. TFBGA100 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 70. TFBGA100 - 8 x 8 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 219
Figure 71. LQFP100 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 72. LQFP100 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 73. LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 74. LQFP128 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 75. LQFP128 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 76. LQFP128 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 77. UFBGA121 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 78. UFBGA121 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32G474xB/xC/xE microcontrollers.
This document should be read in conjunction with the reference manual RM0440
®
“STM32G4 Series advanced Arm 32-bit MCUs”. The reference manual is available from
the STMicroelectronics website www.st.com.
®(a)
®
®
For information on the Arm
Cortex -M4 core, refer to the Cortex -M4 technical
reference manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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48
Description
STM32G474xB STM32G474xC STM32G474xE
2
Description
®
®
The STM32G474xB/xC/xE devices are based on the high-performance Arm Cortex -M4
32-bit RISC core. They operate at a frequency of up to 170 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all
the Arm single-precision data-processing instructions and all the data types. It also
implements a full set of DSP (digital signal processing) instructions and a memory protection
unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (512 Kbytes of Flash memory, and 128 Kbytes
of SRAM), a flexible external memory controller (FSMC) for static memories (for devices
with packages of 100 pins and more), a Quad SPI Flash memory interface, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
The devices also embed several protection mechanisms for embedded Flash memory and
SRAM: readout protection, write protection, securable memory area and proprietary code
readout protection.
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC for trigonometric functions and FMAC unit for filter functions).
They offer five fast 12-bit ADCs (5 Msps), seven comparators, six operational amplifiers,
seven DAC channels (3 external and 4 internal), an internal voltage reference buffer, a low-
power RTC, two general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor
control, seven general-purpose 16-bit timers, and one 16-bit low-power timer, and high
resolution timer with 184 ps resolution.
They also feature standard and advanced communication interfaces such as:
•
•
•
•
•
•
•
Four I2Cs
Four SPIs multiplexed with two half duplex I2Ss
Three USARTs, two UARTs and one low-power UART.
Three FDCANs
One SAI
USB device
UCPD
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported including an analog independent supply
input for ADC, DAC, OPAMPs and comparators. A V
the registers.
input allows backup of the RTC and
BAT
The STM32G474xB/xC/xE family offers 9 packages from 48-pin to 128-pin.
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Description
Table 2. STM32G474xB/xC/xE features and peripheral counts
Peripheral
128 256 512 128 256 512 128 256 512 128 256 512 128 256 512 128 256 512
Flash memory
KB
KB
KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB KB
SRAM
128 (80 + 16+ 32) KB
External memory controller for
static memories (FSMC)
No
No
No
Yes(1)
Yes(2)
Yes
QUADSPI
1
3 (16-bit)
1
Advanced motor
control
HRTIM
5 (16-bit)
2 (32-bit)
General purpose
Timers
Basic
2 (16-bit)
1 (16-bit)
1
Low power
SysTick timer
Watchdog timers
(independent,
window)
2
SPI(I2S)(3)
I2C
3 (2)
4 (2)
4
3
USART
UART
0
2
Comm.
interfaces
LPUART
FDCANs
USB device
UCPD
1
3
Yes
Yes
Yes
Yes
SAI
RTC
Tamper pins
2
3
Random number generator
Yes
Yes
Yes
CORDIC
FMAC
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48
Description
STM32G474xB STM32G474xC STM32G474xE
Table 2. STM32G474xB/xC/xE features and peripheral counts (continued)
Peripheral
38 in
LQFP48
42 in
UFQFPN48
3
67 in
WLCSP81
66 in
LQFP80
4
GPIOs
52
4
86
5
102
5
107
5
Wakeup pins
5
4
20 in
LQFP48
21 in
42 in
WLCSP81
41 in
12-bit ADCs
Number of channels
26
42
42
42
UFQFPN48
LQFP80
12-bit DAC
Number of channels
7 (3 external + 4 internal)
Internal voltage reference
buffer
Yes
PWM channels (all)
33
28
41
30
42
32
48
33
48
33
48
33
PWM channels
(except complementary)
Analog comparator
Operational amplifiers
Max. CPU frequency
Operating voltage
7
6
170 MHz
1.71 V to 3.6 V
Ambient operating temperature: -40 to 85 °C /-40 to 125 °C
Operating temperature
LQFP48/
UFQFPN48
WLCSP81
LQFP80
LQFP100/
TFBGA100
Packages
LQFP64
UFBGA121 LQFP128
1. For the LQFP100 package, only FMC bank1 and NAND bank are available. Bank1 can only support a multiplexed
NOR/PSRAM memory using the NE1 chip select.
2. For the UFBGA121 package, only FMC bank1/bank4 and NAND bank are available. Bank1/Bank4 can only support a
multiplexed NOR/PSRAM memory using the NE1/NE4 chip select.
3. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
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Description
Figure 1. STM32G474xB/xC/xE block diagram
CLK, E(3:0), A(23:0)
JTRST, JTDI,
JTCK/SWCLK
D(31:0), OEN, WEN,
FSMC
JTAG & SW
ETM
MPU
NVIC
FPU
BL(3:0), L, WAIT/IORDY,
IORD, IOWD,IS16 as AF
JTDO/SWD, JTDO
TRACECK
TRACED(3:0)
QUADSPI
CLK, NCS, BK1_IO[3:0]
ARM®
CORTEX-M4
170MHz
D-BUS
I-BUS
S-BUS
FLASH 2 x 256 KB
CCM SRAM 32 KB
@VDDA
CH1
DAC1
DAC2
DAC3
OUT1/OUT2
OUT1
GP-DMA2
GP-DMA1
8 Chan
8 Chan
CH2
SRAM2 16 KB
CH1
SRAM1 80 KB
AHB2
CH1
CH2
DMAMUX
CH1
CH2
RNG
@VDDA
SAR ADC1
SAR ADC2
DAC4
RNB1
analog
IF
Ain ADC
POWER MNGT
VOLT. REG.
3.3V TO 1.2V
CORDIC
FMAC
VDD = 1.71 to 3.6V
VSS
SAR ADC3
SAR ADC4
SAR ADC5
VDD12
IF
@VDD
SUPPLY
SUPERVISION
@VDD
PA(15:0)
PB(15:0)
PC(15:0)
GPIO PORT A
LSI
PLL
POR
Reset
Int
POR / BOR
GPIO PORT B
VDD, VSS,
VDDA, VSSA,
RESET
HSI
PVD, PWM
GPIO PORT C
HSI48
PD(15:0)
PE(15:0)
PF(15:0)
GPIO PORT D
GPIO PORT E
XTAL OSC
4-48MHz
OSC_IN
OSC_OUT
GPIO PORT F
PG(10:0)
GPIO PORT G
RESET&
IWDG
FS, SCK, SD,
MCLK as AF
CLOCKCTRL
Standby Interface
@VBAT
VBAT = 1.55 to 3.6V
SAI1
6 Fault inputs as AF
10 ext. event inputs
1 synchro. input
1 synchro. Output
12 PWM outputs
OSC32_IN
OSC_OUT
peripheralclocks
and system
XTAL 32kHz
16b PWM
HRTimer
RTC AWU
BKPREG
RTC_OUT
RTC_TS
RTC_TAMPx
CRC
EXT IT. WKUP
107 AF
RTC Interface
4 PWM,4PWM,
ETR,BKIN as F
4 PWM,4PWM,
ETR,BKIN as F
16b PWM
TIMER1
TIMER8
AHB/APB2 AHB/APB1
16b PWM
TIMER2&5
TIMER3&4
4 CH, ETR as AF
4 CH, ETR as AF
16b
CH as AF
CH as AF
TIMER15
PWRCTRL
WinWATCHDOG
LP timer1
16b
16b
TIMER16
LP_UART1
RX, TX as AF
CH as AF16b
TIMER17
SCL, SDA, SMBAL as AF
I2C1&2&3&4
4 PWM,4PWM,
ETR,BKIN as F
16b PWM
TIMER20
RX, TX, SCK,
CTS, RTS as AF
RX, TX, CTS,
RTS as AF
Smcard
USART2&3
UART4&5
SPI2&3
RX, TX, SCK,CTS,
16b trigg
irDA
TIMER6
TIMER7
USART 1
RTS as AF
16b trigg
MOSI, MISO
SCK, NSS as AF
irDA
SPI 1
I2S half
duplex
MOSI, MISO, SCK
NSS, as AF
CRS
MOSI, MISO
SCK, NSS as AF
SPI 4
RX,TX as AF
CAN1 & 2 & 3
SysCfg
@VDDA
OPAMP
UCPD
USB
Device
D+
D-
COMP
Vref_Buf
1,2,3,4,5,6,7 1,2,3,4,5,6
CC1
CC2
MSv42693V4
1. AF: alternate function on I/O pins.
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Functional overview
STM32G474xB STM32G474xC STM32G474xE
3
Functional overview
3.1
Arm® Cortex®-M4 core with FPU
®
®
The Arm Cortex -M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
the MCU implementation, with a reduced pin count and with low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
®
®
The Arm Cortex -M4 with FPU 32-bit RISC processor features an exceptional code-
efficiency, delivering the expected high-performance from an Arm core in a memory size
usually associated with 8-bit and 16-bit devices.
The processor supports a set of DSP instructions which allows an efficient signal processing
and a complex algorithm execution. Its single precision FPU speeds up the software
development by using metalanguage development tools to avoid saturation.
With its embedded Arm core, the STM32G474xB/xC/xE family is compatible with all Arm
tools and software.
Figure 1 shows the general block diagram of the STM32G474xB/xC/xE devices.
3.2
3.3
Adaptive real-time memory accelerator (ART accelerator)
The ART accelerator is a memory accelerator that is optimized for the STM32 industry-
®
®
standard Arm Cortex -M4 processors. It balances the inherent performance advantage of
®
®
the Arm Cortex -M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 8 protected areas, which can be
divided in up into 8 subareas each. The protection area sizes range between 32 bytes and
the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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Functional overview
3.4
Embedded Flash memory
The STM32G474xB/xC/xE devices feature 512 kbytes of embedded Flash memory which is
available for storing programs and data.
The Flash interface features:
–
–
Single or dual bank operating modes
Read-while-write (RWW) in dual bank mode
This feature allows to perform a read operation from one bank while an erase or program
operation is performed to the other bank. The dual bank boot is also supported.
Flexible protections can be configured thanks to the option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
– Level 0: no readout protection
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
•
•
Write protection (WRP): the protected area is protected against erasing and
programming.
Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An
additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not
when the RDP protection is changed from Level 1 to Level 0.
•
Securable memory area: a part of Flash memory can be configured by option bytes to
be securable. After reset this securable memory area is not secured and it behaves like
the remainder of main Flash memory (execute, read, write access). When secured, any
access to this securable memory area generates corresponding read/write error.
Purpose of the Securable memory area is to protect sensitive code and data (secure
keys storage) which can be executed only once at boot, and never again unless a new
reset occurs.
The Flash memory embeds the error correction code (ECC) feature supporting:
•
•
•
•
Single error detection and correction
Double error detection
The address of the ECC fail can be read in the ECC register
1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The
OTP area is available in Bank 1 only. The OTP data cannot be erased and can be
written only once.
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Functional overview
STM32G474xB STM32G474xC STM32G474xE
3.5
Embedded SRAM
STM32G474xB/xC/xE devices feature 128 Kbytes of embedded SRAM. This SRAM is split
into three blocks:
•
80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the
SRAM1 through the System Bus (or through the I-Code/D-Code buses when boot from
SRAM1 is selected or when physical remap is selected by SYSCFG_MEMRMP
register). The first 32 Kbyte of SRAM1 support hardware parity check.
•
•
16 Kbytes mapped at address 0x2001 4000 (SRAM2). The CM4 can access the
SRAM2 through the System bus. SRAM2 can be retained in standby modes.
32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU
through I-Code/D-Code bus for maximum performance.
It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1,
DMA2) through SBUS contiguously to SRAM1 and SRAM2. The CCM SRAM supports
hardware parity check and can be write-protected with 1 Kbyte granularity.
•
The memory can be accessed in read/write at max CPU clock speed with 0 wait states.
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Functional overview
3.6
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, FSMC, QUADSPI, AHB and APB peripherals). It also ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
Figure 2. Multi-AHB bus matrix
Cortex®-M4
with FPU
DMA1
DMA2
ICode
FLASH
512 KB
DCode
SRAM1
CCM
SRAM
SRAM2
AHB1
peripherals
AHB2
peripherals
FSMC
QUADSPI
BusMatrix-S
MSv42663V1
3.7
Boot modes
At startup, a BOOT0 pin (or nBOOT0 option bit) and an nBOOT1 option bit are used to
select one of three boot options:
•
•
•
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit
depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade).
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3.8
CORDIC
The CORDIC provides hardware acceleration of certain mathematical functions, notably
trigonometric, commonly used in motor control, metering, signal processing and many other
applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
Cordic features
•
•
•
•
24-bit CORDIC rotation engine
Circular and Hyperbolic modes
Rotation and Vectoring modes
Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,
Natural logarithm
•
•
•
•
•
•
Programmable precision up to 20-bit
Fast convergence: 4 bits per clock cycle
Supports 16-bit and 32-bit fixed point input and output formats
Low latency AHB slave interface
Results can be read as soon as ready without polling or interrupt
DMA read and write channels
3.9
Filter mathematical accelerator (FMAC)
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
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Functional overview
•
•
•
•
•
16 x 16-bit multiplier
24+2-bit accumulator with addition and subtraction
16-bit input and output data
256 x 16-bit local memory
Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
•
•
•
•
•
Input and output sample buffers can be circular
Buffer “watermark” feature reduces overhead in interrupt mode
Filter functions: FIR, IIR (direct form 1)
AHB slave interface
DMA read and write data channels
3.10
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
3.11
Power supply management
3.11.1
Power supply schemes
The STM32G474xB/xC/xE devices require a 1.71 V to 3.6 V V operating voltage supply.
DD
Several independent supplies, can be provided for specific peripherals:
•
V
= 1.71 V to 3.6 V
DD
V
is the external power supply for the I/Os, the internal regulator and the system
DD
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
•
V
= 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum V
DDA
DDA
voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation).
is the external analog power supply for A/D converters, D/A converters, voltage
V
DDA
reference buffer, operational amplifiers and comparators. The V
voltage level is
DDA
independent from the V voltage and should preferably be connected to V when
DD
DD
these peripherals are not used.
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•
•
V
V
= 1.55 V to 3.6 V
BAT
BAT
is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when V is not present.
DD
VREF-, VREF+
V
is the input reference voltage for ADCs and DACs. It is also the output of the
REF+
internal voltage reference buffer when enabled.
When V
When V
< 2 V V
must be equal to V
.
DDA
DDA
DDA
REF+
REF+
≥ 2 V V
must be between 2 V and V
.
DDA
The internal voltage reference buffer supports three output voltages, which are
configured with VRS bits in the VREFBUF_CSR register:
–
–
–
V
V
V
V
= 2.048 V
= 2.5 V
REF+
REF+
REF+
= 2.95 V
is double bonded with V
.
SSA
REF-
3.11.2
Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after power-
on and during power down. The device remains in reset mode when the monitored supply
voltage V is below a specified threshold, without the need for an external reset circuit.
DD
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the V power supply and compares it to the VPVD threshold. An
DD
interrupt can be generated when V drops below the VPVD threshold and/or when V is
DD
DD
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a peripheral voltage monitor which compares the
independent supply voltages V
, with a fixed threshold in order to ensure that the
DDA
peripheral is in its functional supply range.
3.11.3
Voltage regulator
Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep
modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby
and Shutdown modes, both regulators are powered down and their outputs set in high-
impedance state, such as to bring their current consumption close to zero.
The device supports dynamic voltage scaling to optimize its power consumption in Run
mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator (MR) operates in the following ranges:
•
•
•
Range 1 boost mode with the CPU running at up to 170 MHz.
Range 1 normal mode with CPU running at up to 150 MHz.
Range 2 with a maximum CPU frequency of 26 MHz.
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3.11.4
Low-power modes
By default, the microcontroller is in Run mode after system or power Reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to
operate and can wake up the CPU when an interrupt/event occurs.
•
Low-power run mode: This mode is achieved with VCORE supplied by the low-power
regulator to minimize the regulator's operating current. The code can be executed from
SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with
independent clock can be clocked by HSI16.
•
•
Low-power sleep mode: This mode is entered from the low-power run mode. Only the
CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the
system reverts to the Low power run mode.
Stop mode: In Stop mode, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the VCORE domain are
stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable
the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.
•
Standby mode: The Standby mode is used to achieve the lowest power consumption
with brown-out reset, BOR. The internal regulator is switched off to power down the
VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal
oscillator are also powered down. The RTC can remain active (Standby mode with
RTC, Standby mode without RTC). The BOR always remains active in Standby mode.
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM
and register contents are lost except for registers in the RTC domain and standby
circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG
reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC
event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on
LSE (CSS on LSE).
•
Shutdown mode: The Shutdown mode allows to achieve the lowest power
consumption. The internal regulator is switched off to power down the VCORE domain.
The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are
also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown
mode without RTC). The BOR is not available in Shutdown mode. No power voltage
monitoring is possible in this mode. Therefore, switching to RTC domain is not
supported. SRAM and register contents are lost except for registers in the RTC
domain. The device exits Shutdown mode upon external reset event (NRST pin),
IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or
RTC event (alarm, periodic wakeup, timestamp, tamper).
3.11.5
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
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3.11.6
V
operation
BAT
The V
pin allows to power the device V
domain from an external battery, an external
BAT
BAT
supercapacitor, or from V when there is no external battery and when an external
DD
supercapacitor is present. The V
pin supplies the RTC with LSE and the backup
BAT
registers. Three anti-tamper detection pins are available in V
mode.
BAT
The V
operation is automatically activated when V is not present. An internal V
DD BAT
BAT
battery charging circuit is embedded and can be activated when V is present.
DD
Note:
When the microcontroller is supplied from V
, neither external interrupts nor RTC
BAT
alarm/events exit the microcontroller from the V
operation.
BAT
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3.12
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
Table 3. STM32G474xB/xC/xE peripherals interconnect matrix
Interconnect
destination
Interconnect source
Interconnect action
TIMx
Timers synchronization or chaining
Conversion triggers
Y
Y
Y
Y
Y
Y
Y
Y
-
-
ADCx
DACx
TIMx
DMA
Memory to memory transfer trigger
Comparator output blanking
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
COMPx
IRTIM
TIM16/TIM17
Infrared interface output generation
TIM1, 8, 20
TIM2, 3, 4, 5
Timer input channel, trigger, break from
analog signals comparison
Y
Y
Y
Y
Y
Y
Y
Y
-
Low-power timer triggered by analog
signals comparison
COMPx
LPTIMER1
Y
COMPx Output is an input event or a
fault input for HRTIM
HRTIM
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
TIM1, 8, 20
HRTIM
Timer triggered by analog watchdog
ADCx
RTC
HRTIM external event source can be
ADCx analog watchdog
-
TIM16
Timer input channel from RTC events
-
Low-power timer triggered by RTC
alarms or tampers
LPTIMER1
Y
All clocks sources (internal and TIM5,
Clock source used as input channel for
Y
Y
Y
Y
Y
-
Y
-
-
-
external)
TIM15, 16, 17 RC measurement and trimming
USB
TIM2
Timer triggered by USB SOF
CSS
RAM (parity error)
Flash memory (ECC error)
COMPx
TIM1,8, 20
TIM15,16,17
HRTIM
Timer break
Y
Y
Y
Y
-
HRTIM SYSFLT
PVD
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Table 3. STM32G474xB/xC/xE peripherals interconnect matrix (continued)
Interconnect
destination
Interconnect source
Interconnect action
TIM1,8,20
TIM15/16/17
HRTIM
Timer break
CPU (hard fault)
Y
Y
Y
Y
-
HRTIM SYSFLT
External trigger
External trigger
TIMx
Y
Y
Y
Y
Y
Y
Y
Y
-
LPTIMER1
Y
External fault/event/Synchro inputs for
HRTIM
GPIO
HRTIM
Y
Y
Y
Y
Y
Y
Y
Y
-
-
ADCx
DACx
Conversion external trigger
DACx/ADCx
GPIO
Conversion trigger
Y
Y
Y
Y
-
-
HRTIM
Synchro output for HRTIM
Y
Y
Y
Y
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3.13
Clocks and startup
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•
•
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock source: three different sources can deliver SYSCLK system clock:
–
4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).
It can supply clock to system PLL. The HSE can also be configured in bypass
mode for an external clock.
–
–
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
System PLL with maximum output frequency of 170 MHz. It can be fed with HSE
or HSI16 clocks.
•
•
RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can
be used to drive the USB or the RNG peripherals.
Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
–
32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
–
32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
•
•
Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI,
RNG) have their own clock independent of the system clock.
Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt.
•
Clock-out capability:
–
MCO: microcontroller clock output: it outputs one of the internal clocks for external
use by the application
–
LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes.
Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 170 MHz.
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3.14
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.15
Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 4: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 16 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports:
•
16 independently configurable channels (requests)
–
Each channel is connected to a dedicated hardware DMA request, a software
trigger is also supported on each channel. This configuration is done by software.
•
•
Priorities between requests from channels of one DMA are both software
programmable (4 levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•
•
Support for circular buffer management
3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
•
•
•
•
Memory-to-memory transfer
Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
Access to Flash, SRAM, APB and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536.
Table 4. DMA implementation
DMA features
DMA1
8
DMA2
8
Number of regular channels
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Functional overview
3.16
DMA request router (DMAMux)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in figures or described in the text. The DMA request generator
produces DMA requests following events on DMA request trigger inputs.
3.17
Interrupts and events
3.17.1
Nested vectored interrupt controller (NVIC)
The STM32G474xB/xC/xE devices embed a nested vectored interrupt controller which is
able to manage 16 priority levels, and to handle up to 102 maskable interrupt channels plus
®
the 16 interrupt lines of the Cortex -M4.
The NVIC benefits are the following:
•
•
•
•
•
•
•
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.17.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 44 edge detector lines used to generate
interrupt/event requests and to wake-up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 107 GPIOs can
be connected to the 16 external interrupt lines.
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3.18
Analog-to-digital converter (ADC)
The device embeds five successive approximation analog-to-digital converters with the
following features:
•
•
12-bit native resolution, with built-in calibration
4 Msps maximum conversion rate with full resolution
–
–
Down to 41.67 ns sampling time
Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit
resolution)
•
One external reference pin is available on all packages, allowing the input voltage
range to be independent from the power supply
•
•
Single-ended and differential mode inputs
Low-power design
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–
Dual clock domain architecture: ADC speed independent from CPU frequency
•
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
–
–
–
–
–
Results stored into a data register or in RAM with DMA controller support
Data pre-processing: left/right alignment and per channel offset compensation
Built-in oversampling unit for enhanced SNR
Channel-wise programmable sampling time
Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
–
–
Flexible sample time control
Hardware gain and offset compensation
3.18.1
Temperature sensor
The temperature sensor (TS) generates a voltage V that varies linearly with temperature.
TS
The temperature sensor is internally connected to the ADCs input channels which is used to
convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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Table 5. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
TS_CAL1
0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
TS_CAL2
0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.18.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADCx_IN18,
x = 1,3,4,5 input channel. The precise voltage of VREFINT is individually measured for each
part by ST during production test and stored in the system memory area. It is accessible in
read-only mode.
Table 6. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT
temperature of 30 °C (± 5 °C),
0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.18.3
3.18.4
3.19
VBAT battery voltage monitoring
This embedded hardware enables the application to measure the V
the internal ADC1_IN17 channel. As the V
thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
3. As a consequence, the converted digital value is one third of the V
battery voltage using
BAT
voltage may be higher than the V
, and
BAT
DDA
voltage.
BAT
Operational amplifier internal output (OPAMPxINT):
The OPAMPx (x = 1...6) output OPAMPxINT can be sampled using an ADCx (x = 1...5)
internal input channel. In this case, the I/O on which the OPAMPx output is mapped can be
used as GPIO.
Digital to analog converter (DAC)
Seven 12 bit DAC channels (3 external buffered and 4 internal unbuffered) can be used to
convert digital signals into analog voltage signal outputs. The chosen design structure is
composed of integrated resistor strings and an amplifier in inverting configuration.
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This digital interface supports the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Up to two DAC output channels
8-bit or 12-bit output mode
Buffer offset calibration (factory and user trimming)
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Saw tooth wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Sample and hold low-power mode, with internal or external capacitor
Up to 1 Msps for external output and 15 Msps for internal output
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.20
Voltage reference buffer (VREFBUF)
The STM32G474xB/xC/xE devices embed a voltage reference buffer which can be used as
voltage reference for ADC, DACs and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports three voltages:
•
•
•
2.048 V
2.5 V
2.9 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with V
on some packages. In these packages the
DDA
internal voltage reference buffer is not available.
Figure 3. Voltage reference buffer
VREFBUF
Bandgap
VDDA DAC, ADC
+
-
VREF+
Low frequency
cut-off capacitor
100 nF
MSv40197V1
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3.21
Comparators (COMP)
The STM32G474xB/xC/xE devices embed seven rail-to-rail comparators with
programmable reference voltage (internal or external), hysteresis.
The reference voltage can be one of the following:
•
•
•
External I/O
DAC output channels
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers.
3.22
Operational amplifier (OPAMP)
The STM32G474xB/xC/xE devices embed six operational amplifiers with external or internal
follower routing and PGA capability.
The operational amplifier features:
•
•
•
13 MHz bandwidth
Rail-to-rail input/output
PGA with a non-inverting gain ranging of 2, 4, 8, 16, 32 or 64 or inverting gain ranging
of -1, -3, -7, -15, -31 or -63
3.23
3.24
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
Timers and watchdogs
The STM32G474xB/xC/xE devices include One High Resolution time, three advanced
motor control timers, up to nine general-purpose timers, two basic timers, one low-power
timer, two watchdog timers and a SysTick timer. The table below compares the features of
the advanced motor control, general purpose and basic timers.
Table 7. Timer feature comparison
DMA
request
generation channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
High
resolution
timer
/1 /2 /4
(x2 x4 x8 x16
x32, with DLL)
HRTIM
16-bit
16-bit
32-bit
Up
Yes
Yes
Yes
12
4
Yes
4
Advanced
motor
control
Up,
Any integer
down, between 1 and
TIM1, TIM8,
TIM20
Up/down
65536
Up,
Any integer
down, between 1 and
Up/down 65536
General-
purpose
TIM2, TIM5
4
No
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Table 7. Timer feature comparison (continued)
DMA
request
generation channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
Up,
Any integer
General-
purpose
TIM3, TIM4
TIM15
16-bit
16-bit
16-bit
16-bit
down, between 1 and
Up/down
Yes
Yes
Yes
Yes
4
2
1
0
No
1
65536
Any integer
between 1 and
65536
General-
purpose
Up
Any integer
between 1 and
65536
General-
purpose
TIM16, TIM17
TIM6, TIM7
Up
Up
1
Any integer
between 1 and
65536
Basic
No
3.24.1
High-resolution timer (HRTIM)
The high-resolution timer (HRTIM) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 7 timers, 1 master and 6 slaves, totaling 12 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 6 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
HRTIM timer is made of a digital kernel clocked at 170 MHz followed by delay lines. Delay
lines with closed loop control guarantee a 184 ps resolution whatever the voltage,
temperature or chip-to-chip manufacturing process deviation. The high-resolution is
available on the 12 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, burst mode controller,
push-pull and resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
In debug mode, the HRTIM counters can be frozen and the PWM outputs enter safe state.
3.24.2
Advanced motor control timer (TIM1, TIM8, TIM20)
The advanced motor control timers can each be seen as a four-phase
PWM multiplexed on 8 channels. They have complementary PWM outputs with
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Functional overview
programmable inserted dead-times. They can also be seen as complete general-purpose
timers.
The 4 independent channels can be used for:
•
•
•
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
•
One-pulse mode output
In debug mode, the advanced motor control timer counter can be frozen and the PWM
outputs disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.24.3) using the same architecture, so the advanced motor control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
3.24.3
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32G474xB/xC/xE devices (see Table 7 for differences). Each general-purpose timer
can be used to generate PWM outputs, or act as a simple time base.
•
TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers:
–
–
TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler
TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature 4 independent channels for input capture/output compare, PWM
or one-pulse mode output. They can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
TIM15, 16 and 17
•
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
–
TIM15 has 2 channels and 1 complementary channel
TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.24.4
Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
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STM32G474xB STM32G474xC STM32G474xE
3.24.5
Low-power timer (LPTIM1)
The devices embed a low-power timer. This timer has an independent clock and are running
in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the system
from Stop mode.
LPTIM1 is active in Stop mode.
This low-power timer supports the following features:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous/ one shot mode
Selectable software/hardware input trigger
Selectable clock source
–
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•
•
Programmable digital glitch filter
Encoder mode
3.24.6
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.24.7
3.24.8
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
•
•
•
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
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3.25
Real-time clock (RTC) and backup registers
The RTC supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC is supplied through a switch that takes power either from the V supply when
DD
present or from the VBAT pin.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in V
mode and in all low-power modes when it is clocked by the
BAT
LSE. When clocked by the LSI, the RTC is not functional in V
all low-power modes except Shutdown mode.
mode, but is functional in
BAT
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.
3.26
Tamper and backup registers (TAMP)
•
32 32-bit backup registers, retained in all low-power modes and also in V
mode.
BAT
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. They are not reset by a system or power reset, or when the device
wakes up from Standby or Shutdown mode.
•
Up to three tamper pins for external tamper detection events. The external tamper pins
can be configured for edge detection, edge and level, level detection with filtering.
•
•
•
•
Five internal tampers events.
Any tamper detection can generate a RTC timestamp event.
Any tamper detection erases the backup registers.
Any tamper detection can generate an interrupt and wake-up the device from all low-
power modes.
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STM32G474xB STM32G474xC STM32G474xE
3.27
Infrared transmitter
The STM32G474xB/xC/xE devices provide an infrared transmitter solution. The solution is
based on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
Figure 4. Infrared transmitter
TIM17_CH1
IR_OUT
IRTIM
TIM16_CH1
MS30474V2
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Functional overview
3.28
Inter-integrated circuit interface (I2C)
The device embeds four I2Cs. Refer to Table 8: I2C implementation for the features
implementation.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System management bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (packet error checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power system management protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 8. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 kbit/s)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Programmable analog and digital noise filters
SMBus/PMBus hardware support
Independent clock
Wakeup from Stop mode on address match
1. X: supported
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Functional overview
STM32G474xB STM32G474xC STM32G474xE
3.29
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32G474xB/xC/xE devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver
transmitters (UART4, USART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
All USART have a clock domain independent from the CPU clock, allowing the U(S)ARTx
(x=1,2,3,4,5) to wake up the MCU from Stop mode. The wakeup from Stop mode can be
done on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
All USART interfaces can be served by the DMA controller.
Table 9. USART/UART/LPUART features
USART modes/features(1)
USART1 USART2 USART3 UART4 UART5 LPUART1
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
-
X
X
X
-
X
X
X
Smartcard mode
X
-
-
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
X
X
-
Dual clock domain
X
X
X
-
Wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
X
X
X
X (4 modes)
X
-
-
X
X
X
X
X
LPUART/USART data length
7, 8 and 9 bits
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Table 9. USART/UART/LPUART features (continued)
USART modes/features(1)
USART1 USART2 USART3 UART4 UART5 LPUART1
Tx/Rx FIFO
X
8
Tx/Rx FIFO size
1. X = supported.
3.30
Low-power universal asynchronous receiver transmitter
(LPUART)
The STM32G474xB/xC/xE devices embed one Low-Power UART. The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half-
duplex single-wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default. It has a clock domain independent
from the CPU clock, and can wakeup the system from Stop mode. The wake up from Stop
mode can be done on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.31
Serial peripheral interface (SPI)
Four SPI interfaces allow communication up to 75 Mbits/s in master and up to 41 Mbits/s in
slave, half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and hardware CRC calculation.
2
Two standard I S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio
standards can operate as master or slave at half-duplex communication modes. They can
be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and
synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can
be set by 8-bit programmable linear prescaler. When operating in master mode it can output
a clock for an external audio component at 256 times the sampling frequency.
All SPI interfaces can be served by the DMA controller.
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Functional overview
STM32G474xB STM32G474xC STM32G474xE
3.32
Serial audio interfaces (SAI)
The device embeds 1 SAI. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
SAI peripheral supports:
•
Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•
•
•
•
8-word integrated FIFOs for each audio sub-block.
Synchronous or asynchronous mode between the audio sub-blocks.
Master or slave configuration independent for both audio sub-blocks.
Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•
•
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
•
Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
•
•
•
•
•
•
•
•
Number of bits by frame may be configurable.
Frame synchronization active level configurable (offset, bit length, level).
First active bit position in the slot is configurable.
LSB first or MSB first for data transfer.
Mute mode.
Stereo/Mono audio frame capability.
Communication clock strobing edge configurable (SCK).
Error flags with associated interrupts if enabled respectively.
–
–
–
–
Overrun and underrun detection.
Anticipated frame synchronization signal detection in slave mode.
Late frame synchronization signal detection in slave mode.
Codec not ready for the AC’97 mode in reception.
•
•
Interruption sources when enabled:
–
–
Errors.
FIFO requests.
DMA interface with 2 dedicated channels to handle access to the dedicated integrated
FIFO of each SAI audio sub-block.
Table 10. SAI implementation for the features implementation
SAI features
Support(1)
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97
X
X
X
X
Mute mode
Stereo/Mono audio frame capability
16 slots
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Functional overview
Table 10. SAI implementation for the features implementation (continued)
SAI features
Support(1)
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
X
X (8 word)
X
FIFO size
SPDIF
1. X: supported.
3.33
Controller area network (FDCAN1, FDCAN2, FDCAN3)
The controller area network (CAN) subsystem consists of three CAN modules and a shared
message RAM memory.
The three CAN modules (FDCAN1, FDCAN2 and FDCAN3) are compliant with ISO 11898-1
(CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification
version 1.0.
A 3-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers. This message RAM is shared between the three
FDCAN modules.
3.34
Universal serial bus (USB)
The STM32G474xB/xC/xE devices embed a full-speed USB device peripheral compliant
with the USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume
support. It requires a precise 48 MHz clock which can be generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator
in automatic trimming mode. The synchronization for this oscillator can be taken from the
USB data stream itself (SOF signalization) which allows crystal less operation.
3.35
USB Type-C™ / USB Power Delivery controller (UCPD)
The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB
Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
•
•
•
•
USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
“Dead battery” support
USB Power Delivery message transmission and reception
FRS (fast role swap) support
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STM32G474xB STM32G474xC STM32G474xE
The digital controller handles notably:
•
•
•
USB Type-C level detection with de-bounce, generating interrupts
FRS detection, generating an interrupt
Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
•
•
•
•
•
USB Power Delivery timing dividers (including a clock pre-scaler)
CRC generation/checking
4b5b encode/decode
Ordered sets (with a programmable ordered set mask at receive)
Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.36
3.37
Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
Flexible static memory controller (FSMC)
The Flexible static memory controller (FSMC) includes two memory controllers:
•
•
The NOR/PSRAM memory controller
The NAND/memory controller
This memory controller is also named Flexible memory controller (FMC).
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
–
–
–
–
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Ferroelectric RAM (FRAM)
•
•
•
•
•
8-,16- bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.
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LCD parallel interface
Functional overview
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.38
Quad SPI memory interface (QUADSPI)
The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
•
•
Indirect mode: all the operations are performed using the QUADSPI registers
Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory.
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
quad SPI flash memories are accessed simultaneously.
The Quad SPI interface supports:
•
•
Indirect mode: all the operations are performed using the QUADSPI registers
Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory
•
•
•
•
Three functional modes: indirect, status-polling, and memory-mapped
SDR and DDR support
Fully programmable opcode for both indirect and memory mapped mode
Fully programmable frame format for both indirect and memory mapped mode
–
Each of the 5 following phases can be configured independently (enable, length,
single/dual/quad communication)
–
–
–
–
–
Instruction phase
Address phase
Alternate bytes phase
Dummy cycles phase
Data phase
•
•
•
•
•
•
Integrated FIFO for reception and transmission
8, 16, and 32-bit data accesses are allowed
DMA channel for indirect mode operations
Programmable masking for external flash flag management
Timeout management
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
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STM32G474xB STM32G474xC STM32G474xE
3.39
Development support
3.39.1
Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.39.2
Embedded trace macrocell™
The Arm embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32G474xB/xC/xE devices through a small number of ETM pins to an external hardware
trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded trace macrocell operates with third party debugger software tools.
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Pinouts and pin description
4
Pinouts and pin description
4.1
UFQFPN48 pinout description
Figure 5. STM32G474xB/xC/xE UFQFPN48 pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
PA13
VDD
PA12
PA11
PA10
PA9
2
PC14-OSC32_IN
PC15-OSC32_OUT
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PA0
3
4
5
6
UFQFPN48
7
PA8
8
PC6
PA1
9
PB15
PB14
PB13
PB12
PA2
10
11
12
PA3
Exposed pad
PA4
VSS
MS60210V1
1. The above figure shows the package top view.
2. VSS pads are connected to the exposed pad.
DS12288 Rev 5
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Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
4.2
LQFP48 pinout description
Figure 6. STM32G474xB/xC/xE LQFP48 pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
2
PC14 - OSC32_IN
PC15 - OSC32_OUT
PF0 - OSC_IN
PF1 - OSC_OUT
PG10 - NRST
PA0
3
PA12
PA11
PA10
PA9
4
5
6
LQFP48
7
PA8
8
PB15
PB14
PB13
PB12
PB11
PA1
9
PA2
10
11
12
PA3
PA4
MSv42659V2
1. The above figure shows the package top view.
4.3
LQFP64 pinout description
Figure 7. STM32G474xB/xC/xE LQFP64 pinout
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
VSS
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PC0
LQFP64
PC1
PC2
PC3
PA0
PA1
PA2
VSS
VDD
9
10
11
12
13
14
15
16
PC6
PB15
PB14
PB13
PB12
PB11
MSv42658V2
1. The above figure shows the package top view.
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Pinouts and pin description
4.4
LQFP80 pinout description
Figure 8. STM32G474xB/xC/xE LQFP80 pinout
VBAT
1
60
59
PA12
PA11
PA10
PA9
PC13
2
PC14-OSC32_IN
3
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PC15-OSC32_OUT
4
PF0-OSC_IN
5
PA8
PF1-OSC_OUT
PG10-NRST
PC0
6
PC9
7
PC8
8
PC7
PC1
9
PC6
PC2
10
11
12
13
14
15
16
17
18
19
20
VDD
VSS
PD10
PD9
LQFP80
PC3
PA0
PA1
PA2
PD8
VSS
PB15
PB14
PB13
PB12
PB11
VDD
VDD
PA3
PA4
PA5
PA6
MSv60826V1
1. The above figure shows the package top view.
DS12288 Rev 5
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Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
4.5
LQFP100 pinout description
Figure 9. STM32G474xB/xC/xE LQFP100 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD
VSS
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD
VSS
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC14-OSC32_IN
PC15-OSC32_OUT
9
PF9
PF10
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PC0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100
PC1
PC2
PC3
PF2
PA0
PA1
PA2
VSS
PD8
PB15
PB14
PB13
PB12
VDD
PA3
MSv42661V3
1. The above figure shows the package top view.
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DS12288 Rev 5
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Pinouts and pin description
4.6
LQFP128 pinout description
Figure 10. STM32G474xB/xC/xE LQFP128 pinout
PE2
1
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PA13
VDD
VSS
PA12
PA11
PA10
PA9
PE3
2
PE4
PE5
3
4
PE6
5
VBAT
6
PC13
7
PC14-OSC32_IN
8
PA8
PC15-OSC32_OUT
9
PC9
PF3
PF4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PC8
PG4
PG3
PG2
PG1
PG0
PC7
VSS
VDD
PF5
PF7
PF8
LQFP128
PF9
PC6
PF10
VDD
VSS
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PC0
PC1
PC2
PC3
PF2
PA0
PD8
PA1
PB15
PB14
PB13
PB12
PB11
PA2
VSS
VDD
PA3
MSv42664V3
1. The above figure shows the package top view.
DS12288 Rev 5
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Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
4.7
WLCSP81 pinout description
Figure 11. STM32G474xB/xC/xE WLCSP81 pinout
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VDD
VSS
PA12
PA8
VDD
VSS
PD8
PB13
VDD
PA15
PA13
PA11
PC9
PC12
PC10
PA14
PA10
PC6
PD1
PB3
PD2
PC8
PC7
PE12
PE9
PE8
PE7
VDDA
PB5
PB6
PB4
PA4
PB9
VSS
VDD
VBAT
PD0
PB8-BOOT0
PB7
PC13
PC1
PC14-
OSC32_IN
PC11
PA9
PC15-
OSC32_OUT
PA0
PG10-NRST
PC0
PD11
PD10
PB14
PB11
VSS
PB15
PE15
PE13
PE11
PE10
PC4
PB0
PB1
VSSA
VREF+
PA1
PF0-OSC_IN
PF1-
OSC_OUT
PD9
PA5
PC2
G
H
J
PB12
PB10
PE14
PA6
PA2
PC3
VSS
VDD
PC5
PA3
PB2
PA7
MSv48046V1
1. The above figure shows the package top view.
4.8
TFBGA100 pinout description
Figure 12. STM32G474xB/xC/xE TFBGA100 pinout
1
2
3
PB8-BOOT0
PE1
4
5
6
7
8
9
10
A
B
C
D
E
F
PE4
PE5
PB9
PE3
PE6
VSS
PB6
PB7
PE0
PC13
PF10
PC1
PA0
PB3
PD6
PD7
PD3
VSS
VSS
VSS
PE12
PE9
PE11
PE10
PD5
PD4
PD1
PC12
PA14
PA11
PA9
PB5
PD2
PD0
PA15
PA12
PA10
PC9
PC14-
OSC32_IN
PE2
PB4
PC11
VDD
VSS
VDD
PD10
PE15
PE14
PE13
PC10
PA13
PC8
PC15-
OSC32_OUT
VBAT
PF9
VDD
VSS
VDD
PE7
PF1-
OSC_OUT
PF0-OSC_IN
PC2
PA8
PC0
PA1
PA4
PA6
PC4
PG10-NRST
PF2
PD14
PD9
PC6
PC7
G
H
J
PC3
PD13
PB14
PB13
PB15
PD15
PD11
PD12
PD8
PA2
PA3
PB0
PB2
VSSA
PE8
PB11
PB10
PB12
PA5
PC5
VDDA
VREF+
K
PA7
PB1
MS48951V1
1. The above figure shows the package top view.
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Pinouts and pin description
4.9
UFBGA121 pinout description
Figure 13. STM32G474xB/xC/xE UFBGA121 pinout
1
2
3
4
PB9
PE0
PE1
PF4
5
PB6
6
7
8
9
10
11
A
B
C
D
E
F
PE4
PE5
PC13
PE2
PE3
VBAT
VDD
VSS
PE6
PF3
PF5
PF9
PC2
PA1
PA2
PA7
PC4
PB3
PD7
PB4
PD6
PD5
PD15
PF15
PF14
PF13
VSS
VDD
PD4
PD3
PD2
PC12
PA8
PG2
PD11
PE10
PE9
PE8
PE7
VDD
VSS
PC11
PA9
PD1
PA15
PA14
VSS
PF6
PB5
PD0
PA13
VDD
PA11
PG3
PC7
PB7
PC10
PA10
PC8
PC14-
OSC32_IN
PC15-
OSC32_OUT
PB8-BOOT0
PF8
PA12
PG4
VDD
PF0-OSC_IN
PC1
VSS
PF7
PC9
PF1-
OSC_OUT
PF10
PA0
PC5
PB0
PB2
VREF+
PG10-NRST
PB1
PG1
PD12
PB15
PE13
PE12
PE11
PG0
PD13
PD8
PC6
G
H
J
PC0
PF2
VSS
PA5
PA6
PD14
PD9
VDD
PD10
PB13
VDD
PB11
PC3
PF12
VDD
PF11
PB12
PE14
PE15
PB14
VSS
K
L
PA3
VSSA
VDDA
PA4
PB10
MS52876V1
1. The above figure shows the package top view.
DS12288 Rev 5
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Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
4.10
Pin definition
Table 11. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
TT
B
Input / output pin
5 V tolerant I/O
3.6 V tolerant I/O
Dedicated BOOT0 pin
NRST
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
I/O, with Analog switch function supplied by VDDA
I/O, USB Type-C PD capable
I/O, USB Type-C PD Dead Battery function
I/O, Fm+ capable
I/O structure
_a(1)
_c
_d
_f(2)
_u(3)
I/O, with USB function
Notes
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 12 are: FT_a, FT_fa, TT_a.
2. The related I/O structures in Table 12 are: FT_f, FT_fa.
3. The related I/O structures in Table 12 are FT_u.
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Pinouts and pin description
Table 12. STM32G474xB/xC/xE pin definition
Pin Number
Alternate
functions
Additional
functions
TRACECK,
TIM3_CH1,
SAI1_CK1,
SPI4_SCK,
TIM20_CH1,
FMC_A23,
-
-
-
-
-
C3
1
A2
1
PE2
I/O
FT
-
-
SAI1_MCLK_A,
EVENTOUT
TRACED0,
TIM3_CH2,
SPI4_NSS,
TIM20_CH2,
FMC_A19,
-
-
-
-
-
-
-
-
-
-
B2
A1
2
3
B2
A1
2
3
PE3
PE4
I/O
I/O
FT
FT
-
-
-
-
SAI1_SD_B,
EVENTOUT
TRACED1,
TIM3_CH3, SAI1_D2,
SPI4_NSS,
TIM20_CH1N,
FMC_A20,
SAI1_FS_A,
EVENTOUT
TRACED2,
TIM3_CH4,
SAI1_CK2,
SPI4_MISO,
TIM20_CH2N,
FMC_A21,
SAI1_SCK_A,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
B1
C2
4
5
B1
C3
4
5
PE5
PE6
I/O
I/O
FT
FT
-
-
TRACED3, SAI1_D1,
SPI4_MOSI,
TIM20_CH3N,
FMC_A22,
SAI1_SD_A,
WKUP3,
RTC_TAMP3
-
-
EVENTOUT
B9
B8
1
2
1
2
1
2
1
2
D3
D4
6
7
C2
C1
6
7
VBAT
PC13
PC14-
S
-
-
-
TIM1_BKIN,
TIM1_CH1N,
TIM8_CH4N,
EVENTOUT
WKUP2,
RTC_TAMP1,
RTC_TS,
(2)
(3)
I/O
FT
RTC_OUT1
(2)
(3)
C9
D9
3
4
3
4
3
4
3
4
C1
D1
8
9
D1
D2
8
9
OSC32_I I/O
N
FT
FT
EVENTOUT
EVENTOUT
OSC32_IN
PC15-
OSC32_ I/O
OUT
(2)
(3)
OSC32_OUT
DS12288 Rev 5
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Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM20_CH4,
I2C3_SCL,
FMC_A3,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D3
D4
10
11
PF3
PF4
I/O
I/O
FT_f
FT_f
-
-
-
-
EVENTOUT
COMP1_OUT,
TIM20_CH1N,
I2C3_SDA, FMC_A4,
EVENTOUT
F1
A9
-
-
-
-
-
-
-
-
D2
D5
-
-
E2
E1
12
13
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM20_CH2N,
FMC_A5,
-
-
-
-
-
-
-
E3
14
PF5
I/O
FT
-
-
EVENTOUT
TIM20_BKIN,
TIM5_CH2,
QUADSPI1_BK1_IO2
, FMC_A1,
-
-
-
-
-
-
-
E4
15
PF7
I/O
FT
-
-
SAI1_MCLK_B,
EVENTOUT
TIM20_BKIN2,
TIM5_CH3,
QUADSPI1_BK1_IO0
, FMC_A24,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E5
F3
F4
16
17
PF8
PF9
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
SAI1_SCK_B,
EVENTOUT
TIM20_BKIN,
TIM15_CH1,
SPI2_SCK,
TIM5_CH4,
QUADSPI1_BK1_IO1
, FMC_A25,
E3
E4
10
11
SAI1_FS_B,
EVENTOUT
TIM20_BKIN2,
TIM15_CH2,
SPI2_SCK,
QUADSPI1_CLK,
FMC_A0, SAI1_D3,
EVENTOUT
18
19
PF10
I2C2_SDA,
SPI2_NSS/I2S2_WS,
TIM1_CH3N,
PF0-
OSC_IN
ADC1_IN10,
OSC_IN
E9
F9
5
6
5
6
5
6
5
6
E1
E2
12
13
F1
F2
I/O FT_fa
-
-
EVENTOUT
PF1-
ADC2_IN10,
COMP3_INM,
OSC_OUT
SPI2_SCK/I2S2_CK,
EVENTOUT
20 OSC_OU I/O FT_a
T
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Pinouts and pin description
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
PG10-
NRST
D8
E8
7
-
7
-
7
8
7
8
F3
F2
14
15
F5
21
22
I/O
FT
-
-
MCO, EVENTOUT
NRST
LPTIM1_IN1,
TIM1_CH1,
LPUART1_RX,
EVENTOUT
ADC12_IN6,
COMP3_INM
G2
PC0
I/O FT_a
LPTIM1_OUT,
TIM1_CH2,
LPUART1_TX,
QUADSPI1_BK2_IO0
, SAI1_SD_A,
ADC12_IN7,
COMP3_INP
C8
F8
-
-
-
-
9
9
F4
F1
16
17
G1
G3
23
24
PC1
I/O TT_a
-
-
EVENTOUT
LPTIM1_IN2,
TIM1_CH3,
COMP3_OUT,
TIM20_CH2,
10 10
PC2
I/O FT_a
ADC12_IN8
ADC12_IN9,
QUADSPI1_BK2_IO1
, EVENTOUT
LPTIM1_ETR,
TIM1_CH4, SAI1_D1,
TIM1_BKIN2,
QUADSPI1_BK2_IO2 OPAMP5_VINP
, SAI1_SD_A,
G9
-
-
-
-
11 11
G1
G3
18
19
H1
H2
25
26
PC3
PF2
I/O TT_a
-
-
EVENTOUT
TIM20_CH3,
I2C2_SMBA,
FMC_A2,
-
-
-
I/O
FT
-
EVENTOUT
TIM2_CH1,
TIM5_CH1,
ADC12_IN1,
USART2_CTS,
COMP1_INM,
COMP1_OUT,
COMP3_INP,
TIM8_BKIN,
RTC_TAMP2,W
TIM8_ETR,
D7
E7
8
9
8
9
12 12
G4
G2
20
21
G4
H3
27
28
PA0
PA1
I/O TT_a
-
-
KUP1
TIM2_ETR,
EVENTOUT
RTC_REFIN,
ADC12_IN2,
TIM2_CH2,
TIM5_CH2,
COMP1_INP,
13 13
I/O TT_a
OPAMP1_VINP,
USART2_RTS_DE,
OPAMP3_VINP,
TIM15_CH1N,
OPAMP6_VINM
EVENTOUT
DS12288 Rev 5
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Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM2_CH3,
TIM5_CH3,
USART2_TX,
COMP2_OUT,
TIM15_CH1,
ADC1_IN3,
COMP2_INM,
OPAMP1_VOUT
, WKUP4/LSCO
G8 10
10
14 14
H1
22
J3
29
PA2
I/O FT_a
-
QUADSPI1_BK1_NC
S, LPUART1_TX,
UCPD1_FRSTX,
EVENTOUT
H9
J9
-
-
-
-
15 15
16 16
D6
D7
23
24
J2
J1
30
31
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM2_CH4,
TIM5_CH4,
SAI1_CK1,
ADC1_IN4,
COMP2_INP,
OPAMP1_VINM/
OPAMP
1_VINP,
OPAMP5_VINM
USART2_RX,
TIM15_CH2,
QUADSPI1_CLK,
LPUART1_RX,
SAI1_MCLK_A,
EVENTOUT
H8
11
11
17 17
H3
25
K1
32
PA3
I/O TT_a
-
TIM3_CH2,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
SAI1_FS_B,
ADC2_IN17,
DAC1_OUT1,
COMP1_INM
D6
F7
12
13
12
13
18 18
H2
J1
26
27
L1
33
34
PA4
PA5
I/O TT_a
-
-
EVENTOUT
TIM2_CH1,
TIM2_ETR,
SPI1_SCK,
UCPD1_FRSTX,
EVENTOUT
ADC2_IN13,
DAC1_OUT2,
COMP2_INM,
OPAMP2_VINM
19 19
K2
I/O TT_a
TIM16_CH1,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO,
TIM1_BKIN,
COMP1_OUT,
QUADSPI1_BK1_IO3
, LPUART1_CTS,
EVENTOUT
ADC2_IN3,
DAC2_OUT1,
OPAMP2_VOUT
G7 14
14
20 20
J2
28
L2
35
PA6
I/O TT_a
-
TIM17_CH1,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI,
TIM1_CH1N,
ADC2_IN4,
COMP2_INP,
OPAMP1_VINP,
OPAMP2_VINP
J8
15
15
21 21
K1
29
K3
36
PA7
I/O TT_a
-
COMP2_OUT,
QUADSPI1_BK1_IO2
, UCPD1_FRSTX,
EVENTOUT
60/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Pinouts and pin description
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM1_ETR,
I2C2_SCL,
E6
H7
16
-
-
22 22
K2
J3
30
31
L3
37
38
PC4
PC5
I/O FT_fa
-
-
USART1_TX,
QUADSPI1_BK2_IO3
, EVENTOUT
ADC2_IN5
TIM15_BKIN,
SAI1_D3,
TIM1_CH4N,
USART1_RX,
HRTIM1_EEV10,
EVENTOUT
ADC2_IN11,
OPAMP1_VINM,
OPAMP2_VINM,
WKUP5
-
23 23
H4
I/O TT_a
TIM3_CH3,
TIM8_CH2N,
TIM1_CH2N,
ADC3_IN12/AD
C1_IN15,
F6
17
16
24 24
H4
32
J4
39
PB0
I/O TT_a
-
QUADSPI1_BK1_IO1
, HRTIM1_FLT5,
UCPD1_FRSTX,
EVENTOUT
COMP4_INP,
OPAMP2_VINP,
OPAMP3_VINP
TIM3_CH4,
TIM8_CH3N,
TIM1_CH3N,
ADC3_IN1/ADC
1_IN12,
COMP1_INP,
OPAMP3_VOUT
,
COMP4_OUT,
QUADSPI1_BK1_IO0
,
LPUART1_RTS_DE,
HRTIM1_SCOUT,
EVENTOUT
G6 18
17
25 25
K3
33
G5
40
PB1
I/O TT_a
-
OPAMP6_VINM
RTC_OUT2,
LPTIM1_OUT,
TIM5_CH1,
TIM20_CH1,
I2C3_SMBA,
ADC2_IN12,
COMP4_INM,
OPAMP3_VINM
J7
19
18
26 26
J4
34
K4
41
PB2
I/O TT_a
-
QUADSPI1_BK2_IO1
, HRTIM1_SCIN,
EVENTOUT
H6
J6
-
-
20
-
19
20
-
27 27
28 28
K4
K5
-
35
36
-
K5
L4
-
42
43
44
45
46
47
VSSA
VREF+
VREF+
VDDA
VSS
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VREFBUF_OUT
-
-
VREFBUF_OUT
J5
H9
J1
21
-
21
-
29 29
J5
E5
F5
37
-
L5
K6
L6
-
-
-
-
-
-
-
-
-
-
VDD
TIM20_ETR,
FMC_NE4,
EVENTOUT
-
-
-
-
-
-
-
J5
48
PF11
I/O
FT
-
-
DS12288 Rev 5
61/236
79
Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM20_CH1,
FMC_A6,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H5
J6
49
50
PF12
PF13
I/O
I/O
FT
FT
-
-
-
-
TIM20_CH2,
I2C4_SMBA,
FMC_A7,
EVENTOUT
TIM20_CH3,
I2C4_SCL, FMC_A8,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H6
G6
L7
51
52
53
PF14
PF15
PE7
I/O
I/O
FT_f
FT_f
-
-
-
-
-
TIM20_CH4,
I2C4_SDA, FMC_A9,
EVENTOUT
TIM1_ETR, FMC_D4,
SAI1_SD_B,
ADC3_IN4,
COMP4_INP
H5
30
G5
38
I/O TT_a
I/O FT_a
EVENTOUT
TIM5_CH3,
TIM1_CH1N,
FMC_D5,
SAI1_SCK_B,
EVENTOUT
ADC345_IN6,
COMP4_INM
G5
F5
J4
-
-
-
-
-
-
-
-
-
31
32
33
H5
H6
K6
39
40
41
K7
J7
54
55
56
PE8
PE9
-
-
-
TIM5_CH4,
TIM1_CH1, FMC_D6,
SAI1_FS_B,
I/O FT_a
I/O FT_a
ADC3_IN2
EVENTOUT
TIM1_CH2N,
QUADSPI1_CLK,
FMC_D7,
H7
PE10
ADC345_IN14
SAI1_MCLK_B,
EVENTOUT
TIM1_CH2,
SPI4_NSS,
H4
E5
G4
-
-
-
-
-
-
-
-
-
34
35
36
J6
G6
K7
42
43
44
L8
K8
J8
57
58
59
PE11
PE12
PE13
I/O FT_a
I/O FT_a
I/O FT_a
-
-
-
QUADSPI1_BK1_NC ADC345_IN15
S, FMC_D8,
EVENTOUT
TIM1_CH3N,
SPI4_SCK,
QUADSPI1_BK1_IO0 ADC345_IN16
, FMC_D9,
EVENTOUT
TIM1_CH3,
SPI4_MISO,
QUADSPI1_BK1_IO1
, FMC_D10,
ADC3_IN3
EVENTOUT
62/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Pinouts and pin description
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM1_CH4,
SPI4_MOSI,
TIM1_BKIN2,
QUADSPI1_BK1_IO2
, FMC_D11,
J3
F4
-
-
-
-
-
-
37
38
J7
45
46
K9
L9
60
61
PE14
PE15
I/O FT_a
-
-
ADC4_IN1
ADC4_IN2
EVENTOUT
TIM1_BKIN,
TIM1_CH4N,
USART3_RX,
QUADSPI1_BK1_IO3
, FMC_D12,
H7
I/O FT_a
EVENTOUT
TIM2_CH3,
USART3_TX,
LPUART1_RX,
QUADSPI1_CLK,
TIM1_BKIN,
HRTIM1_FLT3,
SAI1_SCK_A,
EVENTOUT
COMP5_INM,
OPAMP3_VINM,
OPAMP4_VINM
H3
22
22
30 39
J8
47
L10
62
PB10
I/O TT_a
-
J2
J1
-
23
24
31 40
32 41
E6
F7
48 K10
63
64
VSS
VDD
S
S
-
-
-
-
-
-
-
-
23
49
K11
TIM2_CH4,
USART3_RX,
LPUART1_TX,
ADC12_IN14,
COMP6_INP,
H2
24
25
33 42
H8
50
L11
65
PB11
I/O TT_a
-
QUADSPI1_BK1_NC OPAMP4_VINP,
S, HRTIM1_FLT4,
EVENTOUT
OPAMP6_VOUT
TIM5_ETR,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
TIM1_BKIN,
USART3_CK,
LPUART1_RTS_DE,
FDCAN2_RX,
ADC4_IN3/ADC
1_IN11,
COMP7_INM,
OPAMP4_VOUT
,
G3 25
26
34 43
K8
51
J9
66
PB12
I/O TT_a
-
OPAMP6_VINP
HRTIM1_CHC1,
EVENTOUT
SPI2_SCK/I2S2_CK,
TIM1_CH1N,
USART3_CTS,
LPUART1_CTS,
FDCAN2_TX,
ADC3_IN5,
COMP5_INP,
OPAMP3_VINP,
OPAMP4_VINP,
OPAMP6_VINP
H1
26
27
35 44
J9
52
J11
67
PB13
I/O TT_a
-
HRTIM1_CHC2,
EVENTOUT
DS12288 Rev 5
63/236
79
Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM15_CH1,
SPI2_MISO,
TIM1_CH2N,
ADC4_IN4/ADC
1_IN5,
G2 27
28
36 45
H9
53
J10
68
PB14
I/O TT_a
-
USART3_RTS_DE,
COMP4_OUT,
HRTIM1_CHD1,
EVENTOUT
COMP7_INP,
OPAMP2_VINP,
OPAMP5_VINP
RTC_REFIN,
TIM15_CH2,
TIM15_CH1N,
COMP3_OUT,
TIM1_CH3N,
ADC4_IN5/ADC
2_IN15,
COMP6_INM,
E4
28
29
37 46
K9
54
55
H8
H9
69
70
PB15
I/O TT_a
-
SPI2_MOSI/I2S2_SD OPAMP5_VINM
, HRTIM1_CHD2,
EVENTOUT
USART3_TX,
FMC_D13,
EVENTOUT
ADC4_IN12/AD
C5_IN12,
OPAMP4_VINM
G1
F3
F2
-
-
-
-
-
-
-
-
-
47 K10
PD8
PD9
I/O TT_a
I/O TT_a
I/O FT_a
-
-
-
USART3_RX,
FMC_D14,
EVENTOUT
ADC4_IN13/AD
C5_IN13,
OPAMP6_VINP
48
49
G8
G7
56 H10 71
USART3_CK,
FMC_D15,
EVENTOUT
ADC345_IN7,
COMP6_INM
57 H11
72
73
PD10
TIM5_ETR,
I2C4_SMBA,
USART3_CTS,
FMC_A16,
ADC345_IN8,
COMP6_INP,
OPAMP4_VINP
E2
-
-
-
-
-
-
-
-
H10
J10
58
G7
PD11
PD12
I/O TT_a
I/O TT_a
-
-
EVENTOUT
TIM4_CH1,
USART3_RTS_DE,
FMC_A17,
ADC345_IN9,
COMP5_INP,
OPAMP5_VINP
-
59
60
G8
G9
74
75
EVENTOUT
TIM4_CH2,
FMC_A18,
EVENTOUT
ADC345_IN10,
COMP5_INM
-
-
-
-
-
-
-
-
-
-
G9
F8
PD13
PD14
I/O FT_a
I/O TT_a
-
-
TIM4_CH3,
FMC_D0,
ADC345_IN11,
COMP7_INP,
61 G10 76
EVENTOUT
OPAMP2_VINP
TIM4_CH4,
SPI2_NSS,
FMC_D1,
-
-
-
-
-
G10
62
63
F6
-
77
78
PD15
I/O FT_a
-
COMP7_INM
EVENTOUT
B1
E1
-
-
-
-
-
-
50
51
E7
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
64 G11 79
64/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Pinouts and pin description
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM3_CH1,
HRTIM1_EEV10,
TIM8_CH1,
I2S2_MCK,
COMP6_OUT,
I2C4_SCL,
E3
29
-
38 52
F9
65
F10
80
PC6
I/O
FT_f
-
-
HRTIM1_CHF1,
EVENTOUT
TIM3_CH2,
HRTIM1_FLT5,
TIM8_CH2,
I2S3_MCK,
COMP5_OUT,
I2C4_SDA,
D5
-
-
39 53 F10
66
F11
81
PC7
I/O
FT_f
-
-
HRTIM1_CHF2,
EVENTOUT
TIM20_CH1N,
FMC_A10,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F9
F8
82
83
PG0
PG1
I/O
I/O
FT
FT
-
-
-
-
TIM20_CH2N,
FMC_A11,
EVENTOUT
TIM20_CH3N,
SPI1_SCK,
FMC_A12,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F7
84
85
PG2
PG3
I/O
I/O
FT
-
-
-
-
EVENTOUT
TIM20_BKIN,
I2C4_SCL,
SPI1_MISO,
TIM20_CH4N,
FMC_A13,
E11
FT_f
EVENTOUT
TIM20_BKIN2,
I2C4_SDA,
SPI1_MOSI,
FMC_A14,
-
-
-
-
-
-
-
-
-
E10
E9
86
87
PG4
PC8
I/O
I/O
FT_f
FT_f
-
-
-
-
EVENTOUT
TIM3_CH3,
HRTIM1_CHE1,
TIM8_CH3,
TIM20_CH3,
COMP7_OUT,
I2C3_SCL,
C5
40 54
E8
67
EVENTOUT
DS12288 Rev 5
65/236
79
Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM3_CH4,
HRTIM1_CHE2,
TIM8_CH4, I2SCKIN,
TIM8_BKIN2,
D2
-
-
41 55
E9
68
E8
88
PC9
I/O
FT_f
-
-
I2C3_SDA,
EVENTOUT
MCO, I2C3_SCL,
I2C2_SDA,
I2S2_MCK,
TIM1_CH1,
USART1_CK,
COMP7_OUT,
TIM4_ETR,
ADC5_IN1,
OPAMP5_VOUT
D1
30
30
42 56 E10
69
E7
89
PA8
I/O FT_a
-
FDCAN3_RX,
SAI1_CK2,
HRTIM1_CHA1,
SAI1_SCK_A,
EVENTOUT
I2C3_SMBA,
I2C2_SCL,
I2S3_MCK,
TIM1_CH2,
USART1_TX,
OMP5_OUT,
TIM15_BKIN,
TIM2_CH3,
FT_fd
ADC5_IN2,
UCPD1_DBCC1
D4
31
31
43 57 D10
70
D8
90
PA9
I/O
a
-
HRTIM1_CHA2,
SAI1_FS_A,
EVENTOUT
TIM17_BKIN,
USB_CRS_SYNC,
I2C2_SMBA,
SPI2_MISO,
TIM1_CH3,
USART1_RX,
COMP6_OUT,
TIM2_CH4,
FT_fd
D3
32
32
44 58
D9
71
D9
91
PA10
I/O
a
-
UCPD1_DBCC2
TIM8_BKIN,
SAI1_D1,
HRTIM1_CHB1,
SAI1_SD_A,
EVENTOUT
66/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Pinouts and pin description
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
SPI2_MOSI/I2S2_SD
, TIM1_CH1N,
USART1_CTS,
COMP1_OUT,
FDCAN1_RX,
TIM4_CH1,
C2
33
33
45 59 C10
72 D11
92
PA11
I/O FT_u
-
USB_DM
TIM1_CH4,
TIM1_BKIN2,
HRTIM1_CHB2,
EVENTOUT
TIM16_CH1,
I2SCKIN,
TIM1_CH2N,
USART1_RTS_DE,
COMP2_OUT,
FDCAN1_TX,
TIM4_CH2,
C1
34
34
46 60
C9
73 D10 93
PA12
I/O FT_u
-
USB_DP
TIM1_ETR,
HRTIM1_FLT1,
EVENTOUT
A8
A1
-
35
36
47 61
48 62
F6
-
74 C10 94
VSS
VDD
S
S
-
-
-
-
-
-
-
-
35
75 C11
95
SWDIO-JTMS,
TIM16_CH1N,
I2C4_SCL,
I2C1_SCL, IR_OUT,
USART3_CTS,
TIM4_CH3,
(4)
B2
36
37
49 63
D8
76
B11
96
PA13
I/O
FT_f
-
SAI1_SD_B,
EVENTOUT
TIM5_ETR,
TIM4_CH4,
SAI1_SD_B,
I2C2_SCL,
TIM5_CH1,
-
-
-
-
-
-
-
A11
97
PF6
I/O
FT_f
-
-
USART3_RTS,
QUADSPI1_BK1_IO3
, EVENTOUT
SWCLK-JTCK,
LPTIM1_OUT,
I2C4_SMBA,
I2C1_SDA,
(4)
C3
37
38
50 64 B10
77 B10
98
PA14
I/O
FT_f
TIM8_CH2,
-
TIM1_BKIN,
USART2_TX,
SAI1_FS_B,
EVENTOUT
DS12288 Rev 5
67/236
79
Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
JTDI, TIM2_CH1,
TIM8_CH1,
I2C1_SCL,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_RX,
UART4_RTS_DE,
TIM1_BKIN,
(4)
A2
38
39
51 65
B9
78 A10
99
PA15
I/O
FT_f
-
FDCAN3_TX,
HRTIM1_FLT2,
TIM2_ETR,
EVENTOUT
TIM8_CH1N,
UART4_TX,
SPI3_SCK/I2S3_CK,
USART3_TX,
B3
C4
39
40
-
-
52 66
C8
C7
79
80
C9 100
PC10
PC11
I/O
I/O
FT
-
-
-
-
HRTIM1_FLT6,
EVENTOUT
HRTIM1_EEV2,
TIM8_CH2N,
UART4_RX,
SPI3_MISO,
USART3_RX,
I2C3_SDA,
53 67
C8 101
FT_f
EVENTOUT
TIM5_CH2,
HRTIM1_EEV1,
TIM8_CH3N,
UART5_TX,
A3
-
-
54 68 A10
81
D7 102
PC12
I/O
FT
-
-
SPI3_MOSI/I2S3_SD
, USART3_CK,
UCPD1_FRSTX,
EVENTOUT
TIM20_ETR,
SPI1_NSS,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
103
104
PG5
PG6
I/O
I/O
FT
FT
-
-
LPUART1_CTS,
FMC_A15,
EVENTOUT
-
-
TIM20_BKIN,
I2C3_SMBA,
LPUART1_RTS_DE,
FMC_INT,
EVENTOUT
SAI1_CK1,
I2C3_SCL,
LPUART1_TX,
FMC_INT,
-
-
-
-
-
-
-
-
105
PG7
I/O
FT_f
-
-
SAI1_MCLK_A,
EVENTOUT
68/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Pinouts and pin description
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
I2C3_SDA,
LPUART1_RX,
FMC_NE3,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
106
107
108
109
PG8
PG9
PD0
PD1
I/O
I/O
I/O
I/O
FT_f
FT
-
-
-
-
-
-
-
-
EVENTOUT
SPI3_SCK,
USART1_TX,
FMC_NCE/FMC_NE
2, TIM15_CH1N,
EVENTOUT
-
-
-
-
-
TIM8_CH4N,
FDCAN1_RX,
FMC_D2,
B4
A4
69
70
B8
A9
82
83
B9
A9
FT
EVENTOUT
TIM8_CH4,
TIM8_BKIN2,
FDCAN1_TX,
FMC_D3,
FT
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
B8
A8
110
111
VSS
VDD
S
S
-
-
-
-
-
-
-
-
A1
TIM3_ETR,
TIM8_BKIN,
UART5_RX,
EVENTOUT
B5
-
-
55 71
B7
84
C7
112
PD2
I/O
FT
-
-
TIM2_CH1/
TIM2_ETR,
USART2_CTS,
QUADSPI1_BK2_NC
S, FMC_CLK,
EVENTOUT
-
-
-
-
-
C6
85
B7
113
PD3
I/O
FT
-
-
TIM2_CH2,
USART2_RTS_DE,
QUADSPI1_BK2_IO0
, FMC_NOE,
-
-
-
-
-
-
-
-
-
-
A8
A7
86
87
A7
E6
114
115
PD4
PD5
I/O
I/O
FT
FT
-
-
-
-
EVENTOUT
USART2_TX,
QUADSPI1_BK2_IO1
, FMC_NWE,
EVENTOUT
TIM2_CH4, SAI1_D1,
USART2_RX,
QUADSPI1_BK2_IO2
, FMC_NWAIT,
SAI1_SD_A,
-
-
-
-
-
A6
88
D6
116
PD6
I/O
FT
-
-
EVENTOUT
DS12288 Rev 5
69/236
79
Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM2_CH3,
USART2_CK,
QUADSPI1_BK2_IO3
,
-
-
-
-
-
B6
89
B6
117
PD7
I/O
FT
-
-
FMC_NCE/FMC_NE
1, EVENTOUT
JTDO-TRACESWO,
TIM2_CH2,
TIM4_ETR,
UCPD1_CRS_SYNC,
TIM8_CH1N,
SPI1_SCK,
SPI3_SCK/I2S3_CK,
USART2_TX,
(4)
A5
41
40
56 72
A5
90
A6
118
PB3
I/O
FT
-
TIM3_ETR,
FDCAN3_RX,
HRTIM1_SCOUT,
HRTIM1_EEV9,
SAI1_SCK_B,
EVENTOUT
JTRST, TIM16_CH1,
TIM3_CH1,
TIM8_CH2N,
SPI1_MISO,
SPI3_MISO,
(4)
(5)
USART2_RX,
UART5_RTS_DE,
TIM17_BKIN,
FDCAN3_TX,
HRTIM1_EEV7,
SAI1_MCLK_B,
EVENTOUT
C6
42
41
57 73
C5
91
C6
119
PB4
I/O FT_c
UCPD1_CC2
TIM16_BKIN,
TIM3_CH2,
TIM8_CH3N,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD
, USART2_CK,
I2C3_SDA,
A6
43
42
58 74
B5
92
B5
120
PB5
I/O
FT_f
-
-
FDCAN2_RX,
TIM17_CH1,
LPTIM1_IN1,
SAI1_SD_B,
HRTIM1_EEV6,
UART5_CTS,
EVENTOUT
70/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Pinouts and pin description
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM16_CH1N,
TIM4_CH1,
TIM8_CH1,
TIM8_ETR,
USART1_TX,
COMP4_OUT,
FDCAN2_TX,
TIM8_BKIN2,
LPTIM1_ETR,
HRTIM1_SCIN,
HRTIM1_EEV4,
SAI1_FS_B,
EVENTOUT
-
B6
44
43
59 75
A4
93
A5
121
PB6
I/O FT_c
UCPD1_CC1
(5)
TIM17_CH1N,
TIM4_CH2,
I2C4_SDA,
I2C1_SDA,
TIM8_BKIN,
USART1_RX,
COMP3_OUT,
TIM3_CH4,
LPTIM1_IN2,
FMC_NL,
HRTIM1_EEV3,
UART4_CTS,
EVENTOUT
C7
B7
A7
45
46
47
44
45
46
60 76
61 77
62 78
B4
A3
A2
94
95
96
C5 122
PB7
I/O
I/O
I/O
FT_f
FT_f
FT_f
-
PVD_IN
TIM16_CH1,
TIM4_CH3,
SAI1_CK1,
I2C1_SCL,
USART3_RX,
COMP1_OUT,
FDCAN1_RX,
TIM8_CH2,
TIM1_BKIN,
HRTIM1_EEV8,
SAI1_MCLK_A,
EVENTOUT
PB8-
BOOT0
(6)
D5 123
-
TIM17_CH1,
TIM4_CH4,
SAI1_D2,
I2C1_SDA,
IR_OUT,
USART3_TX,
COMP2_OUT,
FDCAN1_TX,
TIM8_CH3,
TIM1_CH3N,
HRTIM1_EEV5,
SAI1_FS_A,
EVENTOUT
A4
124
PB9
-
-
DS12288 Rev 5
71/236
79
Pinouts and pin description
STM32G474xB STM32G474xC STM32G474xE
Table 12. STM32G474xB/xC/xE pin definition (continued)
Pin Number
Alternate
functions
Additional
functions
TIM4_ETR,
TIM20_CH4N,
TIM16_CH1,
TIM20_ETR,
USART1_TX,
FMC_NBL0,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
C4
B3
97
B4
125
PE0
PE1
I/O
I/O
FT
FT
-
-
-
-
TIM17_CH1,
TIM20_CH4,
USART1_RX,
FMC_NBL1,
EVENTOUT
98
99
C4 126
-
-
47
48
63 79
64 80
-
-
B3
127
128
VSS
VDD
S
S
-
-
-
-
-
-
-
-
A9
48
100 A3
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
3. After a backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the reference manual RM0440 "STM32G4 Series advanced Arm®-based 32-bit
MCUs".
4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4
pins and the internal pull-down on PA14 pin are activated.
5. After reset, a pull-down resistor (Rd = 5.1kΩ from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1,
UCPD1_CC2). The pull-down on PB6 (UCPD1_CC1) is activated by high level on PA9 (UCPD1_DBCC1). The pull-down
on PB4 (UCPD1_CC2) is activated by high level on PA10 (UCPD1_DBCC2). This pull-down control (dead battery support
on UCPD peripheral) can be disabled by setting bit UCPD1_DBDIS=1 in the PWR_CR3 register. PB4, PB6 have
UCPD_CC functionality which implements an internal pull-down resistor (5.1kΩ) which is controlled by the voltage on the
UCPD_DBCC pin (PA10, PA9). A high level on the UCPD_DBCC pin activates the pull-down on the UCPD_CC pin. The
pull-down effect on the CC lines can be removed by using the bit UCPD1_DBDIS =1 (USB Type-C and power delivery dead
battery disable) in the PWR_CR3 register.
6. It is recommended to set PB8 in another mode than analog mode after startup to limit consumption if the pin is left
unconnected.
72/236
DS12288 Rev 5
4.11
Alternate functions
Table 13. Alternate function
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
QUADSPI1
/SPI1/2/3/4/
I2S2/3/I2C4/
UART4/5/
TIM8/
QUADSPI1/
I2C3/4/SAI1/US
B/HRTIM1/
TIM8/20/15/
COMP3
I2C3/4/UAR
USART1/2/3 T4/5/LPUA
/FDCAN/CO RT1/COMP
I2C1/3/
TIM1/2/3/4/5/8/
20/15/
QUADSPI1/
SPI2/3/I2S2
/3/TIM1/5/8/
20/Infrared
FDCAN/T
IM1/8/15/
FDCAN1/
2
UART4/5/
SAI1/TIM
2/15/
Port
LPTIM1/
TIM2/5/
15/16/17
I2C1/2/3/
4/TIM1/8/
16/17
QUADSPI1/
LPTIM1/ FMC/LPUART1 SAI1SAI1/HR
I2C4/
SYS_AF
TIM2/3/4/8/1 TIM1/8/F /SAI1/HRTIM1/ TIM1/OPAMP
EVENT
MP7/5/6
1/2/7/4/5/6/
3
7
DCAN1/3
TIM1
2
COMP1
UCPD1
Infrared
USART2_
CTS
COMP1
_OUT
TIM8_
BKIN
TIM2_
ETR
EVENT
OUT
PA0
PA1
-
TIM2_CH1
TIM2_CH2
TIM2_CH3
TIM2_CH4
-
TIM5_CH1
TIM5_CH2
TIM5_CH3
TIM5_CH4
TIM3_CH2
TIM2_ETR
TIM3_CH1
TIM3_CH2
I2C3_SCL
I2C3_SMBA
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC_
REFIN
USART2_
RTS_DE
TIM15_
CH1N
EVENT
OUT
-
-
-
-
-
USART2_
TX
COMP2
_OUT
TIM15_
CH1
QUADSPI1_
BK1_NCS
UCPD1_ EVENT
FRSTX
PA2
-
-
-
LPUART1_TX
OUT
USART2_
RX
TIM15_
CH2
QUADSPI1_
CLK
SAI1_MCLK_
A
EVENT
OUT
PA3
-
SAI1_CK1
-
-
-
-
LPUART1_RX
-
SPI3_NSS/
I2S3_WS
USART2_
CK
EVENT
OUT
PA4
-
-
-
-
-
-
-
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
I2S2_MCK
I2S3_MCK
SPI2_MISO
-
-
-
-
-
-
-
-
-
SAI1_FS_B
-
UCPD1_ EVENT
FRSTX
PA5
-
TIM2_CH1
TIM16_CH1
TIM17_CH1
-
-
-
-
-
-
-
-
OUT
TIM8_
BKIN
COMP1
_OUT
QUADSPI1_
BK1_IO3
LPUART1_
CTS
EVENT
OUT
PA6
-
TIM1_BKIN
-
TIM8_
CH1N
TIM1_
CH1N
COMP2_
OUT
QUADSPI1_
BK1_IO2
UCPD1_ EVENT
FRSTX OUT
PA7
-
-
I2C2_
SDA
USART1_
CK
COMP7
_OUT
FDCAN3
_RX
HRTIM1_
CHA1
SAI1_SC EVENT
K_A OUT
PA8
MCO
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM4_ETR
TIM2_CH3
TIM2_CH4
TIM4_CH1
TIM4_CH2
TIM4_CH3
-
SAI1_CK2
I2C2_
SCL
USART1_
TX
COMP5
_OUT
TIM15_
BKIN
HRTIM1_
CHA2
SAI1_FS EVENT
_A OUT
PA9
-
-
-
-
-
-
-
USB_
CRS_SYNC
I2C2_
SMBA
USART1_
RX
COMP6
_OUT
TIM8_
BKIN
HRTIM1_
CHB1
SAI1_SD EVENT
_A
PA10
PA11
PA12
PA13
PA14
TIM17_BKIN
-
-
SAI1_D1
OUT
SPI2_MOSI/
I2S2_SD
TIM1_
CH1N
USART1_
CTS
COMP1
_OUT
FDCAN1
_RX
TIM1_
CH4
HRTIM1_
CHB2
EVENT
OUT
-
-
-
-
TIM1_BKIN2
-
TIM1_
CH2N
USART1_
RTS_DE
COMP2
_OUT
FDCAN1
_TX
TIM1_
ETR
HRTIM1_
FLT1
EVENT
OUT
TIM16_CH1
TIM16_CH1N
LPTIM1_OUT
-
-
I2SCKIN
IR_OUT
-
-
-
-
-
-
SWDIO-
JTMS
I2C1_
SCL
USART3_
CTS
EVENT
OUT
-
I2C4_SCL
I2C4_SMBA
-
-
-
-
-
-
-
SAI1_SD_B
SAI1_FS_B
SWCLK-
JTCK
I2C1_
SDA
TIM1_
BKIN
USART2_
TX
EVENT
OUT
-
TIM8_CH2
FDCAN3
_
TX
I2C1_
SCL
SPI3_NSS/
I2S3_WS
USART2_
RX
UART4
_RTS_DE
TIM1_
BKIN
HRTIM1_
FLT2
TIM2_
ETR
EVENT
OUT
PA15
JTDI
TIM2_CH1
TIM8_CH1
-
SPI1_NSS
-
-
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
QUADSPI1
/SPI1/2/3/4/
I2S2/3/I2C4/
UART4/5/
TIM8/
QUADSPI1/
I2C3/4/SAI1/US
B/HRTIM1/
TIM8/20/15/
COMP3
I2C3/4/UAR
USART1/2/3 T4/5/LPUA
/FDCAN/CO RT1/COMP
I2C1/3/
TIM1/2/3/4/5/8/
20/15/
QUADSPI1/
SPI2/3/I2S2
/3/TIM1/5/8/
20/Infrared
FDCAN/T
IM1/8/15/
FDCAN1/
2
UART4/5/
SAI1/TIM
2/15/
Port
LPTIM1/
TIM2/5/
15/16/17
I2C1/2/3/
4/TIM1/8/
16/17
QUADSPI1/
LPTIM1/ FMC/LPUART1 SAI1SAI1/HR
I2C4/
SYS_AF
TIM2/3/4/8/1 TIM1/8/F /SAI1/HRTIM1/ TIM1/OPAMP
EVENT
MP7/5/6
1/2/7/4/5/6/
3
7
DCAN1/3
TIM1
2
COMP1
UCPD1
Infrared
TIM8_
CH2N
TIM1_
CH2N
QUADSPI1_
BK1_IO1
HRTIM1_
FLT5
UCPD1_ EVENT
PB0
-
-
TIM3_CH3
TIM3_CH4
TIM5_CH1
TIM4_ETR
TIM3_CH1
TIM3_CH2
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FRSTX
OUT
TIM8_
CH3N
TIM1_
CH3N
COMP4_
OUT
QUADSPI1_
BK1_IO0
LPUART1_
RTS_DE
HRTIM1_
SCOUT
EVENT
OUT
PB1
PB2
-
-
-
-
-
I2C3_
SMBA
QUADSPI1_
BK2_IO1
HRTIM1_
SCIN
EVENT
OUT
RTC_OUT2
LPTIM1_OUT
TIM2_CH2
TIM16_CH1
TIM16_BKIN
TIM16_CH1N
TIM17_CH1N
TIM16_CH1
TIM17_CH1
TIM2_CH3
TIM2_CH4
-
TIM20_CH1
-
-
-
-
-
-
JTDO-
TRACESWO
USB_CRS_
SYNC
TIM8_
CH1N
SPI3_SCK/
I2S3_CK
USART2_
TX
FDCAN3
_RX
HRTIM1_
SCOUT
HRTIM1_
EEV9
SAI1_
SCK_B
EVENT
OUT
PB3
SPI1_SCK
TIM3_ETR
TIM17_BKIN
TIM17_CH1
TIM8_BKIN2
TIM3_CH4
TIM8_CH2
TIM8_CH3
TIM8_
CH2N
USART2_
RX
UART5_
RTS_DE
FDCAN3
_TX
HRTIM1_
EEV7
SAI1_
MCLK_B
EVENT
OUT
PB4
JTRST
-
SPI1_MISO
SPI3_MISO
-
I2C1_
SMBA
SPI3_MOSI
/I2S3_SD
USART2_
CK
FDCAN2
_RX
LPTIM1_
IN1
HRTIM1_
EEV6
UART5_ EVENT
CTS OUT
PB5
-
TIM8_CH3N
SPI1_MOSI
I2C3_SDA
SAI1_SD_B
USART1_
TX
COMP4_
OUT
FDCAN2
_TX
LPTIM1_
ETR
HRTIM1_
EEV4
SAI1_FS EVENT
_B OUT
PB6
-
-
-
TIM8_CH1
TIM8_ETR
HRTIM1_SCIN
I2C1_
SDA
USART1_
RX
COMP3_
OUT
LPTIM1_
IN2
HRTIM1_
EEV3
UART4_ EVENT
PB7
-
I2C4_SDA
TIM8_BKIN
-
-
FMC_NL
CTS
OUT
I2C1_
SCL
USART3_
RX
COMP1_
OUT
FDCAN1
_RX
HRTIM1_
EEV8
SAI1_
MCLK_A
EVENT
OUT
PB8
-
SAI1_CK1
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_BKIN
I2C1_
SDA
USART3_
TX
COMP2_
OUT
FDCAN1
_TX
HRTIM1_
EEV5
SAI1_FS EVENT
_A OUT
PB9
-
SAI1_D2
IR_OUT
TIM1_CH3N
USART3_
TX
LPUART1_
RX
QUADSPI1_
CLK
HRTIM1_
FLT3
SAI1_SC EVENT
PB10
PB11
PB12
PB13
PB14
PB15
-
-
-
-
-
-
-
TIM1_BKIN
K_A
OUT
USART3_
RX
LPUART1_
TX
QUADSPI1_
BK1_NCS
HRTIM1_
FLT4
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
I2C2_
SMBA
SPI2_NSS/
I2S2_WS
USART3_
CK
LPUART1_
RTS_DE
FDCAN2
_RX
HRTIM1_
CHC1
EVENT
OUT
-
TIM5_ETR
-
-
TIM1_BKIN
-
-
-
-
-
-
-
-
SPI2_SCK/
I2S2_CK
TIM1_
CH1N
USART3_
CTS
LPUART1_
CTS
FDCAN2
_TX
HRTIM1_
CHC2
EVENT
OUT
-
-
-
-
-
TIM1_
CH2N
USART3_
RTS_DE
COMP4_
OUT
HRTIM1_
CHD1
EVENT
OUT
-
TIM15_CH1
TIM15_CH2
-
-
SPI2_MISO
-
-
TIM1_
CH3N
SPI2_MOSI/
I2S2_SD
HRTIM1_
CHD2
EVENT
OUT
RTC_REFIN
TIM15_CH1N
COMP3_OUT
-
-
-
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
QUADSPI1
/SPI1/2/3/4/
I2S2/3/I2C4/
UART4/5/
TIM8/
QUADSPI1/
I2C3/4/SAI1/US
B/HRTIM1/
TIM8/20/15/
COMP3
I2C3/4/UAR
USART1/2/3 T4/5/LPUA
/FDCAN/CO RT1/COMP
I2C1/3/
TIM1/2/3/4/5/8/
20/15/
QUADSPI1/
SPI2/3/I2S2
/3/TIM1/5/8/
20/Infrared
FDCAN/T
IM1/8/15/
FDCAN1/
2
UART4/5/
SAI1/TIM
2/15/
Port
LPTIM1/
TIM2/5/
15/16/17
I2C1/2/3/
4/TIM1/8/
16/17
QUADSPI1/
LPTIM1/ FMC/LPUART1 SAI1SAI1/HR
I2C4/
SYS_AF
TIM2/3/4/8/1 TIM1/8/F /SAI1/HRTIM1/ TIM1/OPAMP
EVENT
MP7/5/6
1/2/7/4/5/6/
3
7
DCAN1/3
TIM1
2
COMP1
UCPD1
Infrared
LPUART1_
RX
EVENT
OUT
PC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LPTIM1_IN1
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
TIM15_BKIN
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LPUART1_
TX
QUADSPI1_
BK2_IO0
EVENT
OUT
PC1
PC2
LPTIM1_OUT
-
-
-
SAI1_SD_A
QUADSPI1_
BK2_IO1
EVENT
OUT
LPTIM1_IN2
COMP3_OUT
-
TIM20_CH2
-
-
TIM1_
BKIN2
QUADSPI1_
BK2_IO2
EVENT
OUT
PC3
LPTIM1_ETR
SAI1_D1
-
-
SAI1_SD_A
-
I2C2_
SCL
USART1_
TX
QUADSPI1_
BK2_IO3
EVENT
OUT
PC4
-
-
-
-
-
TIM1_
CH4N
USART1_
RX
HRTIM1_
EEV10
EVENT
OUT
PC5
-
SAI1_D3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_
CH1
COMP6_
OUT
HRTIM1_
CHF1
EVENT
OUT
PC6
-
HRTIM1_EEV10
-
I2S2_MCK
I2S3_MCK
TIM20_CH3
I2C4_SCL
TIM8_
CH2
COMP5_
OUT
HRTIM1_
CHF2
EVENT
OUT
PC7
-
HRTIM1_FLT5
-
I2C4_SDA
TIM8_
CH3
COMP7_
OUT
EVENT
OUT
PC8
-
HRTIM1_CHE1
-
I2C3_SCL
-
-
TIM8_
CH4
TIM8_
BKIN2
EVENT
OUT
PC9
-
HRTIM1_CHE2
I2SCKIN
-
I2C3_SDA
TIM8_
CH1N
SPI3_SCK/
I2S3_CK
USART3_
TX
HRTIM1_
FLT6
EVENT
OUT
PC10
PC11
PC12
PC13
PC14
PC15
-
-
UART4_TX
-
TIM8_
CH2N
USART3_
RX
EVENT
OUT
-
-
HRTIM1_EEV2
UART4_RX
SPI3_MISO
I2C3_SDA
-
-
-
-
-
TIM8_
CH3N
SPI3_MOSI
/I2S3_SD
USART3_
CK
UCPD1_ EVENT
TIM5_CH2
-
HRTIM1_EEV1
UART5_TX
-
-
-
-
FRSTX
OUT
TIM1_
CH1N
TIM8_
CH4N
EVENT
OUT
-
-
-
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
-
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
QUADSPI1
/SPI1/2/3/4/
I2S2/3/I2C4/
UART4/5/
TIM8/
QUADSPI1/
I2C3/4/SAI1/US
B/HRTIM1/
TIM8/20/15/
COMP3
I2C3/4/UAR
USART1/2/3 T4/5/LPUA
/FDCAN/CO RT1/COMP
I2C1/3/
TIM1/2/3/4/5/8/
20/15/
QUADSPI1/
SPI2/3/I2S2
/3/TIM1/5/8/
20/Infrared
FDCAN/T
IM1/8/15/
FDCAN1/
2
UART4/5/
SAI1/TIM
2/15/
Port
LPTIM1/
TIM2/5/
15/16/17
I2C1/2/3/
4/TIM1/8/
16/17
QUADSPI1/
LPTIM1/ FMC/LPUART1 SAI1SAI1/HR
I2C4/
SYS_AF
TIM2/3/4/8/1 TIM1/8/F /SAI1/HRTIM1/ TIM1/OPAMP
EVENT
MP7/5/6
1/2/7/4/5/6/
3
7
DCAN1/3
TIM1
2
COMP1
UCPD1
Infrared
TIM8_
CH4N
FDCAN1
_RX
EVENT
OUT
PD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D2
FMC_D3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_
CH4
TIM8_
BKIN2
FDCAN1
_TX
EVENT
OUT
PD1
PD2
-
-
-
-
-
TIM8_
BKIN
EVENT
OUT
-
TIM3_ETR
-
UART5_RX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM2_CH1/
TIM2_ETR
USART2_
CTS
QUADSPI1
_BK2_NCS
EVENT
OUT
PD3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_CLK
FMC_NOE
FMC_NWE
FMC_NWAIT
-
USART2_
RTS_DE
QUADSPI1_
BK2_IO0
EVENT
OUT
PD4
-
TIM2_CH2
-
-
-
USART2_
TX
QUADSPI1_
BK2_IO1
EVENT
OUT
PD5
-
-
-
-
-
USART2_
RX
QUADSPI1_
BK2_IO2
EVENT
OUT
PD6
-
TIM2_CH4
SAI1_D1
-
SAI1_SD_A
USART2_
CK
QUADSPI1_
BK2_IO3
FMC_NCE/
FMC_NE1
EVENT
OUT
PD7
-
TIM2_CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_
TX
EVENT
OUT
PD8
-
-
-
-
-
-
-
-
-
-
-
FMC_D13
FMC_D14
FMC_D15
FMC_A16
FMC_A17
FMC_A18
FMC_D0
FMC_D1
USART3_
RX
EVENT
OUT
PD9
-
-
-
USART3_
CK
EVENT
OUT
PD10
PD11
PD12
PD13
PD14
PD15
-
-
-
I2C4_
SMBA
USART3_
CTS
EVENT
OUT
TIM5_ETR
-
-
USART3_
RTS_DE
EVENT
OUT
-
-
-
-
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
-
-
-
-
EVENT
OUT
-
-
-
-
EVENT
OUT
-
EVENT
OUT
SPI2_NSS
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
QUADSPI1
/SPI1/2/3/4/
I2S2/3/I2C4/
UART4/5/
TIM8/
QUADSPI1/
I2C3/4/SAI1/US
B/HRTIM1/
TIM8/20/15/
COMP3
I2C3/4/UAR
USART1/2/3 T4/5/LPUA
/FDCAN/CO RT1/COMP
I2C1/3/
TIM1/2/3/4/5/8/
20/15/
QUADSPI1/
SPI2/3/I2S2
/3/TIM1/5/8/
20/Infrared
FDCAN/T
IM1/8/15/
FDCAN1/
2
UART4/5/
SAI1/TIM
2/15/
Port
LPTIM1/
TIM2/5/
15/16/17
I2C1/2/3/
4/TIM1/8/
16/17
QUADSPI1/
LPTIM1/ FMC/LPUART1 SAI1SAI1/HR
I2C4/
SYS_AF
TIM2/3/4/8/1 TIM1/8/F /SAI1/HRTIM1/ TIM1/OPAMP
EVENT
MP7/5/6
1/2/7/4/5/6/
3
7
DCAN1/3
TIM1
2
COMP1
UCPD1
Infrared
TIM16_
CH1
USART1_
TX
FDCAN1
_RXFD
EVENT
OUT
PE0
-
-
TIM4_ETR
-
TIM20_CH4N
-
TIM20_ETR
TIM20_CH4
TIM20_CH1
TIM20_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NBL0
FMC_NBL1
FMC_A23
FMC_A19
FMC_A20
FMC_A21
FMC_A22
FMC_D4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM17_
CH1
USART1_
RX
EVENT
OUT
PE1
PE2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI1_MCLK_
A
EVENT
OUT
TRACECK
-
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
-
SAI1_CK1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI4_SCK
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PE3
TRACED0
-
-
SPI4_NSS
SAI1_SD_B
SAI1_FS_A
SAI1_SCK_A
SAI1_SD_A
SAI1_SD_B
SAI1_SCK_B
SAI1_FS_B
TIM20_
CH1N
EVENT
OUT
PE4
TRACED1
-
SAI1_D2
SPI4_NSS
TIM20_
CH2N
EVENT
OUT
PE5
TRACED2
-
SAI1_CK2
SPI4_MISO
TIM20_
CH3N
EVENT
OUT
PE6
TRACED3
-
SAI1_D1
SPI4_MOSI
EVENT
OUT
PE7
-
-
-
-
-
-
-
-
-
-
TIM1_ETR
TIM1_CH1N
TIM1_CH1
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
TIM1_CH4
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PE8
TIM5_CH3
-
FMC_D5
EVENT
OUT
PE9
TIM5_CH4
-
FMC_D6
QUADSPI1_
CLK
SAI1_MCLK_
B
EVENT
OUT
PE10
PE11
PE12
PE13
PE14
PE15
-
-
-
-
-
-
-
FMC_D7
QUADSPI1_
BK1_NCS
EVENT
OUT
SPI4_NSS
SPI4_SCK
SPI4_MISO
SPI4_MOSI
-
FMC_D8
-
-
-
-
-
QUADSPI1_
BK1_IO0
EVENT
OUT
FMC_D9
QUADSPI1_
BK1_IO1
EVENT
OUT
FMC_D10
FMC_D11
FMC_D12
TIM1_
BKIN2
QUADSPI1_
BK1_IO2
EVENT
OUT
TIM1_
CH4N
USART3_
RX
QUADSPI1_
BK1_IO3
EVENT
OUT
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
QUADSPI1
/SPI1/2/3/4/
I2S2/3/I2C4/
UART4/5/
TIM8/
QUADSPI1/
I2C3/4/SAI1/US
B/HRTIM1/
TIM8/20/15/
COMP3
I2C3/4/UAR
USART1/2/3 T4/5/LPUA
/FDCAN/CO RT1/COMP
I2C1/3/
TIM1/2/3/4/5/8/
20/15/
QUADSPI1/
SPI2/3/I2S2
/3/TIM1/5/8/
20/Infrared
FDCAN/T
IM1/8/15/
FDCAN1/
2
UART4/5/
SAI1/TIM
2/15/
Port
LPTIM1/
TIM2/5/
15/16/17
I2C1/2/3/
4/TIM1/8/
16/17
QUADSPI1/
LPTIM1/ FMC/LPUART1 SAI1SAI1/HR
I2C4/
SYS_AF
TIM2/3/4/8/1 TIM1/8/F /SAI1/HRTIM1/ TIM1/OPAMP
EVENT
MP7/5/6
1/2/7/4/5/6/
3
7
DCAN1/3
TIM1
2
COMP1
UCPD1
Infrared
I2C2_
SDA
SPI2_NSS/
I2S2_WS
TIM1_
CH3N
EVENT
OUT
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_SCK/
I2S2_CK
EVENT
OUT
PF1
PF2
-
-
-
-
-
-
I2C2_
SMBA
EVENT
OUT
-
TIM20_CH3
TIM20_CH4
COMP1_OUT
TIM20_CH2N
TIM4_CH4
TIM20_BKIN
TIM20_BKIN2
TIM20_BKIN
TIM20_BKIN2
TIM20_ETR
TIM20_CH1
TIM20_CH2
TIM20_CH3
TIM20_CH4
-
-
-
FMC_A2
FMC_A3
FMC_A4
FMC_A5
-
I2C3_
SCL
EVENT
OUT
PF3
-
-
-
-
I2C3_
SDA
EVENT
OUT
PF4
-
TIM20_CH1N
-
-
EVENT
OUT
PF5
-
-
-
-
-
I2C2_
SCL
USART3_
RTS
QUADSPI1_
BK1_IO3
EVENT
OUT
PF6
TIM5_ETR
SAI1_SD_B
-
TIM5_CH1
QUADSPI1_
BK1_IO2
SAI1_MCLK_
B
EVENT
OUT
PF7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM5_CH2
-
-
-
-
-
-
-
-
-
FMC_A1
FMC_A24
FMC_A25
FMC_A0
FMC_NE4
FMC_A6
FMC_A7
FMC_A8
FMC_A9
QUADSPI1_
BK1_IO0
EVENT
OUT
PF8
-
-
TIM5_CH3
SAI1_SCK_B
QUADSPI1_
BK1_IO1
EVENT
OUT
PF9
TIM15_CH1
SPI2_SCK
TIM5_CH4
SAI1_FS_B
QUADSPI1_
CLK
EVENT
OUT
PF10
PF11
PF12
PF13
PF14
PF15
TIM15_CH2
SPI2_SCK
-
-
-
-
-
-
SAI1_D3
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
I2C4_
SMBA
EVENT
OUT
I2C4_
SCL
EVENT
OUT
I2C4_
SDA
EVENT
OUT
Table 13. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
QUADSPI1
/SPI1/2/3/4/
I2S2/3/I2C4/
UART4/5/
TIM8/
QUADSPI1/
I2C3/4/SAI1/US
B/HRTIM1/
TIM8/20/15/
COMP3
I2C3/4/UAR
USART1/2/3 T4/5/LPUA
/FDCAN/CO RT1/COMP
I2C1/3/
TIM1/2/3/4/5/8/
20/15/
QUADSPI1/
SPI2/3/I2S2
/3/TIM1/5/8/
20/Infrared
FDCAN/T
IM1/8/15/
FDCAN1/
2
UART4/5/
SAI1/TIM
2/15/
Port
LPTIM1/
TIM2/5/
15/16/17
I2C1/2/3/
4/TIM1/8/
16/17
QUADSPI1/
LPTIM1/ FMC/LPUART1 SAI1SAI1/HR
I2C4/
SYS_AF
TIM2/3/4/8/1 TIM1/8/F /SAI1/HRTIM1/ TIM1/OPAMP
EVENT
MP7/5/6
1/2/7/4/5/6/
3
7
DCAN1/3
TIM1
2
COMP1
UCPD1
Infrared
EVENT
OUT
PG0
-
-
-
-
-
-
-
-
-
-
-
-
TIM20_CH1N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
FMC_A11
FMC_A12
FMC_A13
FMC_A14
FMC_A15
FMC_INT
FMC_INT
FMC_NE3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
-
TIM20_CH2N
-
-
-
EVENT
OUT
-
TIM20_CH3N
-
SPI1_SCK
-
I2C4_
SCL
TIM20_
CH4N
EVENT
OUT
-
TIM20_BKIN
-
SPI1_MISO
-
I2C4_
SDA
EVENT
OUT
-
TIM20_BKIN2
-
SPI1_MOSI
-
-
LPUART1_
CTS
EVENT
OUT
-
TIM20_ETR
-
-
SPI1_NSS
-
-
I2C3_
SMBA
LPUART1_
RTS_DE
EVENT
OUT
-
TIM20_BKIN
-
-
-
-
-
-
-
-
I2C3_
SCL
LPUART1_
TX
SAI1_MCLK_
A
EVENT
OUT
-
-
-
-
-
SAI1_CK1
-
-
I2C3_
SDA
LPUART1_
RX
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
FMC_NCE/
FMC_NE2
TIM15_
CH1N
EVENT
OUT
-
-
SPI3_SCK
-
USART1_TX
-
-
-
EVENT
OUT
MCO
-
-
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
5.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 14.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 15.
Figure 14. Pin loading conditions
Figure 15. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
MS19211V1
80/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
5.1.6
Power supply scheme
Figure 16. Power supply scheme
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
VDD
VCORE
n x VDD
Regulator
VDDIO
OUT
Kernel logic
IO
logic
n x 100 nF
+1 x 4.7 μF
(CPU, Digital
GPIOs
& Memories)
IN
n x VSS
Reset block
Temp. sensor
PLL, HSI16, HSI48
VDDA
VDDA
VREF+
VREF
ADCs/
VREF+
Standby circuitry
(Wakeup logic,
IWDG)
DACs/
10 nF
+1 μF
OPAMPs/
VREF-
COMPs/
100 nF +1 μF
VREFBUF
VSSA
MS60206V1
Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.1.7
Current consumption measurement
Figure 17. Current consumption measurement
IDD_VBAT
VBAT
IDD
VDD
IDDA
VDDA
MS60200V1
The I
parameters given in Table 21 to Table 25 represent the total MCU consumption
DD_ALL
including the current supplying V , V
and V
.
DD
DDA
BAT
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
(1)
Table 14. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
VDD - VSS
-0.3
4.0
VDDA, VBAT and VREF+
)
min (VDD, VDDA
)
Input voltage on FT_xxx pins except FT_c pins
VSS-0.3
+ 4.0(3)(4)
V
(2)
Input voltage on FT_c pins
Input voltage on TT_xx pins
Input voltage on any other pins
VSS-0.3
VSS-0.3
VSS-0.3
5.5
4.0
4.0
VIN
Variations between different VDDX power pins of
the same domain
|∆VDDx
|
-
50
mV
V
|VSSx-VSS
|
Variations between all the different ground pins(5)
-
-
50
V
REF+-VDDA Allowed voltage difference for VREF+ > VDDA
0.4
1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supply, in the permitted range.
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Electrical characteristics
2. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 15. Current characteristics
Symbol
Ratings
Max
Unit
∑IVDD
∑IVSS
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
150
150
100
100
20
IVDD(PIN) Maximum current into each VDD power pin (source)(1)
IVSS(PIN)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin except FT_f
Output current sunk by any FT_f pin
IIO(PIN)
20
mA
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT_xxx, TT_xx, NRST pins
20
100
100
-5/0(4)
±25
∑IIO(PIN)
(3)
IINJ(PIN)
∑|IINJ(PIN)
|
Total injected current (sum of all I/Os and control pins)(5)
1. All main power (VDD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14:
Voltage characteristics for the minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
Table 16. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.3
Operating conditions
5.3.1
General operating conditions
Table 17. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
Internal AHB clock frequency
-
-
-
0
0
0
170
170
170
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
MHz
VDD
Standard operating voltage
Analog supply voltage
-
1.71(1)
1.62
1.8
3.6
V
V
ADC
3.6
3.6
3.6
DAC 1 MSPS or DAC 15 MSPS
or OPAMP
VDDA
COMP used
1.8
2.4
VREFBUF used
ADC, DAC, OPAMP, COMP,
VREFBUF not used
0
VBAT
Backup operating voltage
I/O input voltage
-
1.55
-0.3
-0.3
3.6
VDD+0.3
5
V
V
TT_xx
FT_c
VIN
MIN(MIN(VDD
VDDA)+3.6 V,
5.5 V)(2)(3)
,
All I/O except TT_xx and FT_c
-0.3
See Section 6.10: Thermal characteristics for application
appropriate thermal resistance and package.
PD
Power dissipation
mW
mW
Power dissipation is then calculated according ambient
temperature (TA) and maximum junction temperature (TJ) and
selected thermal resistance.
See Section 6.10: Thermal characteristics for application
appropriate thermal resistance and package. Power dissipation
is then calculated according to ambient temperature (TA),
maximum junction temperature (TJ) and selected thermal
resistance.
PD
Power dissipation
Maximum power dissipation
Low-power dissipation(4)
Maximum power dissipation
Low-power dissipation(4)
Suffix 6 version
-40
-40
-40
-40
-40
-40
85
Ambient temperature for the
suffix 6 version
105
125
130
105
130
TA
°C
°C
Ambient temperature for the
suffix 3 version
TJ
Junction temperature range
Suffix 3 version
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA)+3.6 V and 5.5V.
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Electrical characteristics
3. For operation with voltage higher than Min (VDD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6.10:
Thermal characteristics).
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 18 are derived from tests performed under the ambient
temperature condition summarized in Table 17.
Table 18. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
VDD fall time rate
VDDA rise time rate
VDDA fall time rate
0
10
0
∞
∞
∞
∞
tVDD
-
µs/V
tVDDA
-
µs/V
10
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 19 are derived from tests performed under the ambient
temperature conditions summarized in Table 17: General operating conditions.
Table 19. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Reset temporization after
BOR0 is detected
(2)
tRSTTEMPO
VDD rising
-
250
400
μs
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.62
1.6
1.66
1.64
2.1
1.7
(2)
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
V
V
V
V
V
V
V
V
V
1.69
2.14
2.04
2.35
2.24
2.66
2.57
2.95
2.86
2.19
2.1
2.06
1.96
2.26
2.16
2.56
2.47
2.85
2.76
2.1
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
2
2.31
2.20
2.61
2.52
2.90
2.81
2.15
2.05
2.31
2.20
2.46
2.36
2.61
2.52
Programmable voltage
detector threshold 0
2
2.26
2.15
2.41
2.31
2.56
2.47
2.36
2.25
2.51
2.41
2.66
2.57
PVD threshold 1
PVD threshold 2
PVD threshold 3
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Table 19. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.69
2.59
2.85
2.75
2.92
2.84
2.74
2.64
2.91
2.81
2.98
2.90
2.79
2.69
2.96
2.86
3.04
2.96
VPVD4
PVD threshold 4
V
VPVD5
PVD threshold 5
PVD threshold 6
V
V
VPVD6
Hysteresis in
continuous
mode
-
20
-
Vhyst_BORH0 Hysteresis voltage of BORH0
mV
Hysteresis in
other mode
-
-
-
30
100
1.1
-
-
Hysteresis voltage of BORH
Vhyst_BOR_PVD
-
-
mV
µA
(except BORH0) and PVD
IDD
BOR(3) (except BOR0) and
1.6
(BOR_PVD)(2) PVD consumption from VDD
Rising edge
Falling edge
Rising edge
Falling edge
-
1.61
1.6
1.78
1.77
-
1.65
1.64
1.82
1.81
10
1.69
1.68
1.86
1.85
-
VDDA peripheral voltage
VPVM1
V
V
monitoring (COMP/ADC)
VDDA peripheral voltage
VPVM2
monitoring (OPAMP/DAC)
Vhyst_PVM1
Vhyst_PVM2
IDD
PVM1 hysteresis
PVM2 hysteresis
mV
mV
-
-
10
-
PVM1 and PVM2
consumption from VDD
(PVM1/PVM2)
-
-
2
-
µA
(2)
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.3.4
Embedded voltage reference
The parameters given in Table 20 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 17: General operating
conditions.
Table 20. Embedded internal voltage reference
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference
voltage
VREFINT
–40 °C < TA < +130 °C 1.182 1.212 1.232
V
ADC sampling time
when reading the
internal reference
voltage
(1)
tS_vrefint
-
-
-
4(2)
-
8
-
µs
µs
Start time of reference
voltage buffer when
ADC is enable
tstart_vrefint
-
-
-
12(2)
20(2)
7.5(2)
VREFINT buffer
consumption from VDD
DD(VREFINTBUF) when converted by
ADC
12.5
µA
mV
I
Internal reference
voltage spread over
ꢀVREFINT
VDD = 3 V
5
the temperature range
Average temperature
coefficient
TCoeff
ACoeff
–40°C < TA < +130°C
1000 hours, T = 25°C
3.0 V < VDD < 3.6 V
-
-
-
30
50(2) ppm/°C
Long term stability
300 1000(2)
ppm
Average voltage
coefficient
VDDCoeff
250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
-
VREFINT
1. The shortest sampling time is determined in the application by multiple iterations.
2. Guaranteed by design.
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Figure 18. V
Electrical characteristics
versus temperature
REFINT
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
°C
-40
-20
0
20
Mean
40
60
80
100
120
Min
Max
MSv40169V2
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
The current consumption is measured as described in Figure 17: Current consumption
measurement.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the f
frequency (refer to the table “number of wait states according
HCLK
to CPU clock (HCLK) frequency” available in the reference manual RM0440
®
"STM32G4 Series advanced Arm -based 32-bit MCUs").
•
•
When the peripherals are enabled f
= f
PCLK HCLK
The voltage scaling Range 1 is adjusted to f
frequency as follows:
HCLK
–
–
Voltage Range 1 Boost mode for 150 MHz < f
≤ 170 MHz
≤ 150 MHz
HCLK
Voltage Range 1 Normal mode for 26 MHz < f
HCLK
The parameters given in Table 21 to Table 25 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 17: General
operating conditions.
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Table 21. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
Condition
Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz
16 MHz
8 MHz
3.65
2.30
1.25
3.85 4.45
2.55 3.1
1.50 2.05
5.1
3.8
2.8
2.3
2
6.45 4.40 6.60 11.0
16.0
22.0
21.0
19.0
19.0
19.0
18.0
18.0
5.15 3.00 5.00 9.00 14.9
4.1
3.6
2.00
3.6
7.70 13.0
Range 2 4 MHz
2 MHz
0.75 0.955 1.5
1.40 3.00 7.00 12.0
0.47
0.34
0.22
0.69 1.25
0.55 1.1
3.35 0.990 2.60 6.70 12.0
3.2 0.830 2.50 6.50 12.0
1 MHz
1.9
100 KHz
0.43 0.98 1.75
3.1 0.690 2.30 6.30
11.0
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
ON above 48
MHz all
Range 1
Boost
mode
170 MHz 29.50 29.5
31
32
34.5 31.0 35.0 42.0 48.0
56.0
Supply current
in Run mode
IDD (Run)
mA
150 MHz 24.50
120 MHz 19.50
26
20
27
28
30
23.5 21.0 23.0 32.0 38.0
17 15.0 17.0 25.0 30.0
26.0 28.0 34.0 44.0
47.0
43.0
37.0
36.0
34.0
32.0
29.0
28.0
26.0
peripherals
disable
20.5 21.5
80 MHz 13.00 13.5
14
13
15.5
14
72 MHz 12.00
Range 1 64 MHz 10.50
12
11
15.5 13.0 16.0 23.0 29.0
14.5 12.0 14.0 21.0 27.0
11.5
9
12.5
9.7
48 MHz
32 MHz
24 MHz
16 MHz
7.90
5.40
4.10
2.80
8.2
11.5
9.10 13.0 19.0 25.0
5.65
4.35
3.1
6.4
5.1
3.8
7.2
8.85 6.50 9.60 15.0 21.0
5.95
4.7
7.6
6.3
5.20 8.00 14.0 20.0
4.30 6.40 12.0 18.0
Table 21. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) (continued)
Condition
Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
455
280
160
130
920
780
725
720
725 1350 2250 3800 1200 3200 8100 14000 22000
545 1200 2100 3600 1100 3000 7900 14000 22000
435 1100 2000 3500 840 2800 7700 14000 22000
405 1050 1950 3500 810 2700 7600 14000 22000
1200 1850 2750 4250 1900 3800 8700 15000 22000
1100 1700 2650 4150 1700 3700 8600 14000 22000
980 1600 2500 4050 1600 3600 8400 14000 22000
955 1600 2500 4000 1500 3500 8400 14000 22000
SYSCLK source is HSE
in bypass mode
all peripherals disable
1 MHz
250 KHz
62.5 KHz
2 MHz
Supply current
IDD (LPRun) in Low-power
run mode
µA
1 MHz
SYSCLK source is HSI16
all peripherals disable
250 KHz
62.5 KHz
Table 22. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF)
Conditions
TYP
MAX(1)
Symbol
Parameter
fHCLK
Unit
Voltage
-
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
scaling
26 MHz
16 MHz
8 MHz
3.70
2.35
1.25
0.75
0.47
0.34
0.22
3.9
2.55
1.5
4.45
3.1
5.15
3.85
2.8
6.45
5.15
4.15
3.6
4.40
3.00
2.00
1.40
6.60
5.00
3.60
3.00
11.0
9.00
7.70
7.00
6.70
6.50
6.30
16.0
14.0
13.0
12.0
12.0
12.0
11.0
22.0
21.0
19.0
19.0
19.0
18.0
18.0
2.05
1.5
Range 2
4 MHz
0.97
0.7
2.3
2 MHz
1.25
1.1
2.05
1.9
3.35 0.990 2.60
1 MHz
0.56
3.2
3.1
0.830 2.50
0.690 2.30
fHCLK = fHSE
up to 48MHz
included,
bypass mode
PLL ON
above 48
MHz all
peripherals
disable
100 KHz
0.44 0.975
1.8
Range 1
Boost mode
170 MHz 29.50
30
31
32
34.5
31.0
35.0
42.0
48.0
56.0
Supply
current in
Run mode
IDD
(Run)
mA
150 MHz 24.50
120 MHz 19.50
24.5
20
25.5
20.5
14.5
13
26.5
22
28.5
23.5
17
26.0
21.0
15.0
13.0
12.0
9.10
6.50
5.20
4.30
28.0
23.0
17.0
16.0
14.0
13.0
9.60
8.00
6.40
34.0
32.0
25.0
23.0
21.0
19.0
15.0
14.0
12.0
44.0
38.0
30.0
29.0
27.0
25.0
21.0
20.0
18.0
47.0
43.0
37.0
36.0
34.0
32.0
29.0
28.0
26.0
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
13.00
12.00
10.50
7.95
13.5
12.5
11
15.5
14
15.5
14.5
11.5
8.9
Range 1
11.5
9
13
8.3
10
5.40
5.7
6.45
5.1
7.25
6
4.10
4.4
7.65
6.35
2.85
3.15
3.8
4.75
Table 22. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch OFF) (continued)
Conditions
TYP
MAX(1)
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
450
270
185
130
970
800
680
695
725
575
460
430
1350 2250 3800 1200 3200 8100 14000 22000
SYSCLK source is HSE
in bypass mode
1 MHz
1200 2150 3650
1050 2000 3550
1050 2000 3500
1100
840
810
3000 7900 14000 22000
2800 7700 14000 22000
2700 7600 14000 22000
250 KHz
62.5 KHz
2 MHz
all peripherals disable
Supply
IDD
(LPRun)
current in
Low-power
run mode
µA
1200 1850 2750 4300 1900 3800 8700 15000 22000
1100 1700 2650 4150 1700 3700 8600 14000 22000
1 MHz
SYSCLK source is HSI16
all peripherals disable
250 KHz
62.5 KHz
990
965
1600 2550 4050 1600 3600 8400 14000 22000
1600 2500 4050 1500 3500 8400 14000 22000
1. Guaranteed by characterization results, unless otherwise specified.
Table 23. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1
Conditions
TYP
MAX(1)
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz
16 MHz
8 MHz
3.35
2.15
1.15
0.69
0.43
0.30
0.19
3.55
2.35
4.1
2.9
1.9
1.4
4.95
3.7
6.45
5.25
4.2
4.00
3.10
1.90
1.30
6.20
4.70
3.50
2.90
11.0
8.70
7.50
6.90
6.60
6.40
6.30
15.0
14.0
13.0
12.0
12.0
12.0
11.0
22.0
20.0
19.0
19.0
18.0
18.0
18.0
1.35
2.7
Range 2
4 MHz
0.855
2.2
3.7
2 MHz
0.595 1.15
0.47
0.355 0.89
1.95
1.8
3.45 0.960 2.60
1 MHz
1
3.3
3.2
0.810 2.40
0.680 2.30
100 KHz
1.7
fHCLK = fHSE
up to 48MHz
included,
bypass mode
PLL ON
Range 1
Boost
mode
170 MHz
150 MHz
26.00
21.50
26.5
22
27.5
22.5
28.5
23.5
30.5
25.5
28.0
23.0
32.0
25.0
39.0
31.0
45.0 53.0(2)
Supply
IDD(Run) current in
Run mode
mA
above 48
MHz all
41.0
46.0(2)
peripherals
disable
120 MHz
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
17.50
11.50
10.50
9.45
17.5
12
18.5
12.5
11.5
10.5
8.2
19.5
13.5
12.5
11.5
9.25
6.9
21.5
15.5
14.5
13.5
11
19.0
13.0
12.0
11.0
8.10
6.00
4.80
4.00
21.0
15.0
14.0
13.0
12.0
8.90
7.50
6.10
30.0
23.0
21.0
20.0
17.0
15.0
13.0
12.0
36.0
29.0
27.0
26.0
23.0
21.0
19.0
18.0
41.0
35.0
34.0
33.0
31.0
29.0
27.0
26.0
11
Range 1
9.7
7.5
5.15
4
7.25
4.90
5.85
4.7
8.7
3.75
5.7
7.5
2.60
2.85
3.5
4.5
6.3
Table 23. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 (continued)
Conditions
TYP
MAX(1)
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
365
240
135
105
835
775
640
640
570
425
315
285
1200 2150 3850 1200 3100 7900 14000 22000
SYSCLK source is HSE
in bypass mode
1 MHz
1050 2000 3650
960
840
780
2900 7700 14000 22000
2800 7600 13000 22000
2700 7600 13000 22000
250 KHz
62.5 KHz
2 MHz
945
915
1850 3550
1850 3550
all peripherals disable
Supply
IDD
(LPRun)
current in
Low-power
run mode
µA
1050 1650 2600 4300 1800 3700 8600 14000 22000
1 MHz
940
860
830
1550 2500 4150 1700 3600 8500 14000 22000
1450 2400 4100 1500 3500 8400 14000 22000
1450 2350 4050 1600 3500 8400 14000 22000
SYSCLK source is HSI16
all peripherals disable
250 KHz
62.5 KHz
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
Table 24. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF)
TYP
TYP
TYP
TYP
Conditions
Single Bank
Mode
Dual Bank
Mode
SingleBank Dual Bank
Symbol Parameter
Code
Unit
Unit
Mode
25°C
Mode
25°C
-
Voltage scaling
25°C
25°C
Reduced
code(1)
3.65
3.7
140
142
Coremark
Dhrystone2.1
Fibonacci
3.65
3.65
4.55
2.90
3.7
3.7
4.2
3
140
140
175
112
142
142
162
115
Range2
fHCLK=26MHz
mA
µA/MHz
While(1)
Reduced
code(1)
24.5
24.5
163
163
fHCLK=fHSE
up to 48 MHZ
included, bypass
mode PLL ON
above 48 MHz all
peripherals
Coremark
Dhrystone2.1
Fibonacci
24
24
24.5
28
160
163
150
130
160
163
187
133
Supply
IDD
Range 1
fHCLK= 150 MHz
current in
(Run)
mA
µA/MHz
24.5
22.5
19.5
Run mode
disable
While(1)
20
Reduced
code(1)
29.5
29.5
174
174
Coremark
Dhrystone2.1
Fibonacci
29
29.5
38
29
29.5
35
171
174
224
138
171
174
206
141
Range 1
Boost mode
fHCLK= 170 MHz
mA
µA/MHz
While(1)
23.5
24
Table 24. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) (continued)
TYP
TYP
TYP
TYP
Conditions
Single Bank
Mode
Dual Bank
Mode
SingleBank Dual Bank
Symbol Parameter
Code
Unit
Unit
Mode
25°C
Mode
25°C
-
Voltage scaling
25°C
25°C
Reduced
code(1)
920
970
460
485
Supply
current in
(LPRun) Low-power
run
Coremark
Dhrystone2.1
Fibonacci
905
915
985
915
950
875
453
458
525
465
493
458
475
438
SYSCLK source is HSI16
fHCLK = 2 MHz
all peripherals disable
IDD
µA
µA/MHz
1,050
930
While(1)
1. Reduced code used for characterization results provided in Table 21, Table 23.
Table 25. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1
Conditions
TYP
TYP
Symbol
Parameter
Code
Unit
Unit
Voltage
scaling
-
25°C
25°C
Reduced code(1)
Coremark
3.25
3.35
125
129
127
127
131
143
150
143
150
133
153
159
153
162
144
478
445
458
440
453
Range2
fHCLK=26 M
Hz
Dhrystone2.1
Fibonacci
µA/MHz
3.30
mA
3.30
While(1)
3.40
Reduced code(1)
Coremark
21.50
22.50
21.50
22.50
20.00
26.00
27.00
26.00
27.50
24.50
955
fHCLK = fHSE up to 48 MHZ
Range 1
Supply current in included, bypass mode
IDD (Run)
f
HCLK= 150
Dhrystone2.1
Fibonacci
µA/MHz
µA/MHz
µA/MHz
mA
mA
µA
Run mode
PLL ON above 48 MHz all
peripherals disable
MHz
While(1)
Reduced code(1)
Coremark
Range 1
Boost mode
Dhrystone2.1
Fibonacci
fHCLK
=
170 MHz
While(1)
Reduced code(1)
Coremark
890
IDD
Supply current in fHCLK = fHSE = 2 MHz
Low-power run all peripherals disable
Dhrystone2.1
Fibonacci
915
(LPRun)
880
While(1)
905
1. Reduced code used for characterization results provided in Table 21, Table 23.
Table 26. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM2
Conditions
TYP
TYP
Single
bank
mode
Symbol
Parameter
fHCLK
Unit
Unit
Voltage
scaling
Single bank
mode
-
Reduced code(1)
Coremark
2.65
2.80
2.65
2.60
2.45
17.50
18.00
17.50
17.00
16
102
108
102
100
94
Range2
fHCLK=26 M
Hz
Dhrystone2.1
Fibonacci
µA/MHz
mA
While(1)
Reduced code(1)
117
120
117
113
107
124
129
124
121
115
445
415
413
415
408
fHCLK = fHSE up to 48 MHZ
Coremark
Range 1
fHCLK= 150
MHz
Supply current in included, bypass mode
IDD (Run)
Dhrystone2.1
Fibonacci
µA/MHz
µA/MHz
µA/MHz
mA
mA
µA
Run mode
PLL ON above 48 MHz all
peripherals disable
While(1)
Reduced code(1)
21.00
22.00
21.00
20.50
19.50
890
Range 1
Boost mode
Coremark
Dhrystone2.1
Fibonacci
fHCLK
=
170 MHz
While(1)
Reduced code(1)
Coremark
830
SYSCLK source is HSI16
FHCLK = 2MHz
IDD
Supply current in
Low-power run
Dhrystone2.1
Fibonacci
825
(LPRun)
all peripherals disable
830
While(1)
815
1. Reduced code used for characterization results provided in Table 21, Table 23.
Table 27. Typical current consumption in Run and Low-power run modes, with different codes
running from CCMSRAM
Conditions
TYP
TYP
Single
bank
mode
Symbol
Parameter
fHCLK
Unit
Unit
Voltage
scaling
Single bank
mode
-
Reduced code(1)
Coremark
2.75
2.85
106
110
106
113
100
120
123
120
127
113
129
132
129
138
121
450
425
435
425
405
Range2
fHCLK=26 M
Hz
Dhrystone2.1
Fibonacci
µA/MHz
2.75
mA
2.95
While(1)
2.60
Reduced code(1)
Coremark
18.00
18.50
18.00
19.00
17.00
22.00
22.50
22.00
23.50
20.50
900
fHCLK = fHSE up to 48 MHZ
Range 1
fHCLK= 150
MHz
Supply current in included, bypass mode
IDD (Run)
Dhrystone2.1
Fibonacci
µA/MHz
µA/MHz
µA/MHz
mA
mA
µA
Run mode
PLL ON above 48 MHz all
peripherals disable
While(1)
Reduced code(1)
Coremark
Range 1
Boost mode
Dhrystone2.1
Fibonacci
fHCLK
=
170 MHz
While(1)
Reduced code(1)
Coremark
850
SYSCLK source is HSI16
FHCLK = 2MHz
IDD
Supply current in
Low-power run
Dhrystone2.1
Fibonacci
870
(LPRun)
all peripherals disable
850
While(1)
810
1. Reduced code used for characterization results provided in Table 21, Table 23.
Table 28. Current consumption in Sleep and Low-power sleep mode Flash ON
Condition Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
26 MHz
16 MHz
8 MHz
0.98
0.67
0.44
0.33
0.27
0.24
0.21
1.1
1.75
2.4
3.75 1.90 3.50 7.60 13.0
3.5 1.50 3.00 7.10 12.0
19.0
19.0
19.0
18.0
18.0
18.0
18.0
0.835 1.45 2.15
0.605 1.25
0.5 1.1
2
3.35 1.10 2.70 6.70 12.0
3.25 0.860 2.50 6.50 12.0
3.2 0.760 2.40 6.40 11.0
3.15 0.720 2.30 6.40 11.0
3.1 0.670 2.30 6.30 11.0
Range 2 4 MHz
2 MHz
1.9
0.445 1.05 1.85
0.415 1.05 1.8
0.385 0.995 1.8
1 MHz
100 KHz
Range 1
f
HCLK = fHSE
Boost
mode
170 MHz
up to 48 MHz
6.60
6.95
7.8
8.9
10.5 8.00 12.0 18.0 24.0
9.25 6.40 9.50 15.0 21.0
33.0
Supply current included, bypass
in sleep mode mode PLL ON
above 48 MHz all
IDD (Sleep)
mA
150 MHz
120 MHz
80 MHz
72 MHz
5.50
4.50
3.15
2.85
2.60
1.90
1.40
1.10
0.83
5.8
4.75
3.45
3.15
2.9
6.55 7.55
29.0
28.0
26.0
26.0
26.0
25.0
25.0
25.0
24.0
peripherals disable
5.5
4.2
3.9
3.65
3
6.55
5.15
4.9
4.6
3.65
3.2
3
8.2
6.8
5.40 8.20 14.0 20.0
4.50 6.60 12.0 18.0
6.55 4.20 6.30 12.0 18.0
Range 1 64 MHz
48 MHz
6.3
5.3
3.50 6.00 12.0 18.0
3.20 5.30 11.0 17.0
2.2
32 MHz
1.65
1.35
1.1
2.4
2.1
4.85 2.70 4.80 11.0 17.0
4.65 2.30 4.50 9.80 16.0
4.35 1.90 4.10 9.40 16.0
24 MHz
16 MHz
1.85 2.75
Table 28. Current consumption in Sleep and Low-power sleep mode Flash ON (continued)
Condition Typ Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
205
165
145
140
700
710
670
685
430 1150 2050 3600 1600 2900 7800 14000 22000
400 1100 2000 3550 1100 2900 7700 14000 22000
370 1100 2000 3550 820 2800 7700 13000 22000
365 1050 2000 3550 810 2800 7700 13000 22000
925 1650 2550 4100 1600 3600 8400 14000 22000
925 1600 2550 4100 1600 3600 8400 14000 22000
910 1600 2500 4050 1600 3600 8400 14000 22000
910 1600 2500 4050 1600 3600 8400 14000 22000
SYSCLK source is HSE
in bypass mode
1 MHz
μA
250 KHz
62.5 KHz
2 MHz
all peripherals disable
Supply current
in Low-power
sleep mode
IDD
(LPSleep)
1 MHz
SYSCLK source is HSI16
all peripherals disable
μA
250 KHz
62.5 KHz
Table 29. Current consumption in low-power sleep modes, Flash in power-down
Condition Typ
Max
Symbol
Parameter
fHCLK
Unit
Voltage
scaling
-
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
2 MHz
210
150
120
110
675
695
640
690
385 1150 2050 3550 910 2900 7800 14000 22000
360 1100 2000 3550 860 2900 7700 14000 22000
330 1050 2000 3500 820 2700 7600 13000 21000
330 1050 1950 3500 810 2700 7600 13000 21000
900 1600 2500 4050 1600 3600 8500 14000 22000
890 1600 2500 4050 1600 3600 8400 14000 22000
885 1600 2500 4050 1600 3600 8500 14000 22000
880 1600 2500 4050 1400 3000 7000 12000 19000
SYSCLK source is HSE
in bypass mode
all peripherals disable
1 MHz
250 KHz
62.5 KHz
2 MHz
Supply current
in low-power
sleep mode
IDD
(LPSleep)
μA
1 MHz
SYSCLK source is HSI16
all peripherals disable
250 KHz
62.5 KHz
Table 30. Current consumption in Stop 1 mode
TYP
Conditions
-
MAX(1)
85°C
Symbol
Parameter
Unit
VDD
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
80
80
250
250
255
255
255
255
255
830
835
840
845
830
835
835
1550
1600
1600
1600
1550
1600
1600
2850
2850
2900
2900
2850
2850
2850
630
640
640
640
640
640
640
2100
2100
2200
2200
2100
2200
2200
5900
5900
6000
6000
5900
5900
6000
11000 18000
11000 18000
11000 18000
11000 18000
11000 18000
11000 18000
11000 18000
18000
Supplycurrent
in Stop 1
(Stop 1) mode, RTC
disabled
IDD
RTC disabled
80.5
81.5
80.5
81
RTC clocked by LSI
81.5
3.6 V
82
255
845
1600
2900
650
2200
6000
11000
(2)
µA
1.8 V
2.4 V
3.0 V
3.6 V
1.8 V
2.4 V
3.0 V
3.6 V
80
80.5
81.5
83
255
255
255
260
220
220
220
220
830
830
835
845
655
660
660
660
1550
1600
1600
1600
1300
1300
1300
1300
2850
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IDD
(Stop 1
with
Supplycurrent
in Stop 1
mode, RTC
enabled
2850
RTC clocked by LSE
bypassed at 32768 Hz
RTC)
2900
2900
83.5
84
-
-
-
-
RTC clocked by LSE
quartz in low drive mode
at 32768 Hz
84.5
87
Wakeup clock is HSI6,
voltage Range 1
3.0 V
1.73
-
-
-
-
-
-
-
-
-
Supplycurrent
duringwakeup
from
IDD
(wakeu
p from
Stop 1
Wakeup clock is
HSI6 = 4 MHz,
(HPRE = 4),
mA
3.0 V
1.29
-
-
-
-
-
-
-
-
-
Stop 1 mode
voltage Range 2
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production
Table 31. Current consumption in Stop 0 mode
TYP
Conditions
VDD
MAX(1)
85°C
Symbol
Parameter
Unit
-
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
1.8 V
2.4 V
3 V
190
190
190
380
380
380
980
985
985
1750
1750
1750
3100
3100
3100
790
790
800
2400
2400
2400
6500
6400
6500
11000 19000
11000 19000
Supply current
in Stop 0 mode,
IDD(Stop 0)
-
µA
12000 19000
12000
RTC disabled
3.6 V
190
380
985
1750
3100
800
2500
6500
12000
(2)
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
Table 32. Current consumption in Standby mode
Conditions TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V
2.4 V
3 V
100
110
130
275
325
385
1350 3450 8450
200 1100 4100 9700 27000
1600 4100 10000 220 1200 4800 12000 31000
1900 4850 12000 240 1400 5500 13000 35000
40000
No
independent
watchdog
Supply current in Standby
mode (backup registers
retained),
3.6 V
180
530
2400 6050 14500 360 1700 6300 15000
IDD
(Standby)
(2)
nA
1.8 V
2.4 V
3 V
300
365
435
545
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC disabled
With
independent
watchdog
3.6 V
Table 32. Current consumption in Standby mode (continued)
Conditions TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 V
2.4 V
3 V
540
700
885
1100
580
760
960
1200
410
545
830
2200
370
495
655
875
300
305
305
310
725
920
1800 3850 8850
660 1500 4600 11000 27000
RTCclocked
by LSI, no
independent
watchdog
2150 4650 10500 860 1900 5300 12000 31000
1150 2650 5550 12500 1100 2200 6300 14000 36000
1450 3350 7000 15500 1400 2700 7400 16000 41000
3.6 V
1.8 V
2.4 V
3 V
nA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTCclocked
by LSI, with
independent
watchdog
-
-
Supply current in Standby
mode (backup registers
retained),
IDD
(Standby with
RTC)
3.6 V
1.8 V
2.4 V
3 V
-
580
750
1600 3650 8600
1950 4450 10500
RTC enabled
RTCclocked
by LSE
bypassed at
32768 Hz
1150 2750 5800 13000
3050 5550 9550 18000
3.6 V
1.8 V
2.4 V
3 V
nA
570
715
915
1350 3150 7100
1650 3800 8350
2100 4550 9850
RTCclocked
by LSE
quartz(3) in
low drive
mode
3.6 V
1.8 V
2.4 V
3 V
1350 2800 5750 12000
825
875
865
870
2950 6300 12550
2900 6400 12500
2950 6150 12500
3000 6450 13000
Supply current to be added in
Standby mode when SRAM2
is retained
IDD
(SRAM2)(4)
-
nA
3.6 V
Table 32. Current consumption in Standby mode (continued)
Conditions TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD
25°C
55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
Wakeup
IDD (wakeup Supply current during wakeup clock is
3 V
mA
2.46
-
-
-
-
-
-
-
-
-
from Standby) from Standby mode
HSI16 =
16 MHz(5)
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
4. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is:
IIDD_ALL(Standby + RTC) + IDD_ALL(SRAM2).
5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 36: Low-power mode wakeup timings.
Table 33. Current consumption in Shutdown mode
Conditions
VDD
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
25°C
55°C
85°C
105°C
125°C
25°C
55°C
105°C 125°C
Supply current
in Shutdown
mode (backup
registers
retained) RTC
disabled
1.8 V
2.4 V
3 V
19
28
43
87
140
180
230
360
885
2500
2950
3600
4700
6600
7800
9300
12000
78.0
94.0
130
190
490
570
680
870
3100
3600
4100
4900
8100
9300
24000
27000
1050
1300
1750
IDD
(Shutdown)
-
nA
11000 31000
13000 35000
3.6 V
Table 33. Current consumption in Shutdown mode (continued)
Conditions
VDD
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
25°C
55°C
85°C
105°C
125°C
25°C
55°C
105°C 125°C
RTC
clocked by
LSE
bypassed
at 32768
Hz
1.8 V
2.4 V
3 V
330
460
745
2100
285
410
565
780
445
605
1150
1450
2200
4900
1050
1300
1750
2400
2700
3350
4550
8150
2500
3050
3750
4850
6800
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8150
Supply current
in Shutdown
mode (backup
registers
retained) RTC
enabled
1000
2850
450
10500
IDD
3.6 V
1.8 V
2.4 V
3 V
15500
nA
(Shutdownwith
RTC)
RTC
-
-
-
-
clocked by
LSE
585
quartz(2) in
low drive
mode
770
3.6 V
1200
Supply current
during wakeup
from Shutdown HSI16 =
Wakeup
clock is
IDD(wakeup
from
Shutdown)
3 V
mA
1.6
-
-
-
-
-
-
-
-
-
mode
16 MHz(3)
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 36: Low-power mode wakeup timings.
Table 34. Current consumption in V
mode
BAT
Conditions
TYP
MAX(1)
85°C
Symbol
Parameter
Unit
-
V
25°C
55°C
85°C
105°C 125°C
25°C
55°C
105°C 125°C
BAT
1.8 V
2.4 V
3 V
4
5
17
20
92
105
125
260
350
500
1050
3400
455
650
910
1250
245
280
600
690
805
1650
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC
disabled
6
24
330
3.6 V
1.8 V
2.4 V
3 V
16
54
675
RTC
310
435
720
2150
270
385
525
710
315
440
815
2600
345
455
600
995
470
enabled and
clocked by
LSE
bypassed at
32768 Hz
665
-
Backup domain
supply current
IDD(V
)
nA
BAT
1350
4050
715
-
3.6 V
1.8 V
2.4 V
3 V
-
835
910
1000
1900
RTC
enabled and
clocked by
LSE
910
1150
1700
quartz(2)
3.6 V
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
STM32G474xB STM32G474xC STM32G474xE
IO system current consumption
Electrical characteristics
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC, OPAMP, COMP input pins
which should be configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This is done either by using pull-up/down resistors or by configuring the pins in
output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 36: Low-power mode wakeup timings), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
ISW = VDDIOx × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the I/O supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
C
S
INT
EXT +
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 35. The MCU is placed
under the following conditions:
•
•
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
–
–
when the peripheral is clocked on
when the peripheral is clocked off
•
•
Ambient operating temperature and supply voltage conditions summarized in Table 14:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in
Table 35. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 35. Peripheral current consumption
Range 1 Range 1
Low-power
run and
sleep
Bus
Peripheral
Boost
mode
Normal Range 2
mode
Unit
Bus Matrix
6.12
0.26
0.39
10.21
3.51
1.28
0.74
2.83
3.11
6.71
0.58
6.46
4.59
5.69
0.25
0.37
9.52
3.27
1.19
0.68
2.64
2.90
6.26
0.54
6.01
4.29
4.70
0.22
0.32
7.87
2.69
0.98
0.57
2.17
2.39
5.17
0.44
4.95
3.57
6.11
0.03
0.03
10.28
3.51
0.78
0.63
2.75
2.43
6.68
0.54
6.15
3.83
AHB1 to APB1 bridge
AHB1 to APB2 bridge
FSMC
-
µA/MHz
QUADSPI
CORDIC
CRC
DMA 1
DMA 2
AHB1
µA/MHz
DMAMUX
SRAM1
FLASH
FMAC
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
Table 35. Peripheral current consumption (continued)
Range 1 Range 1
Low-power
run and
sleep
Bus
Peripheral
Boost
mode
Normal Range 2
Unit
mode
ADC1/ADC2
6.24
8.21
4.70
2.51
4.62
4.31
0.09
0.10
0.10
0.06
0.23
0.07
0.25
0.39
0.29
2.09
5.80
7.64
4.38
2.34
4.31
4.01
0.08
0.09
0.09
0.06
0.22
0.07
0.24
0.37
0.27
1.95
4.77
6.29
3.63
1.93
3.57
3.32
0.07
0.07
0.08
0.03
0.18
0.05
0.20
0.29
0.23
NA
5.88
8.14
4.40
2.14
4.15
3.90
0.14
0.03
0.03
0.05
0.10
0.02
0.24
0.28
0.22
NA
ADC3/ADC4/ADC5
DAC1
DAC2
DAC3
DAC4
GPIOA
GPIOB
AHB2
µA/MHz
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
SRAM2
CCM SRAM
RNG
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
Table 35. Peripheral current consumption (continued)
Range 1 Range 1
Low-power
run and
sleep
Bus
Peripheral
Boost Normal Range 2
mode mode
Unit
CRS
0.74
22.20
1.29
1.29
1.25
1.25
1.11
1.91
0.71
2.64
4.05
4.08
7.97
6.37
6.43
8.28
1.22
1.28
2.51
2.79
2.75
2.71
0.46
2.46
0.42
0.68
0.57
17.10
0.99
0.99
0.96
0.96
0.85
1.47
0.53
2.07
3.11
3.13
6.16
4.92
4.97
6.38
0.94
0.98
1.92
2.14
2.12
2.08
NA
0.51
21.15
1.28
1.28
1.56
1.97
1.42
2.03
0.53
3.26
4.16
4.49
8.29
6.81
6.50
8.11
1.45
1.56
3.14
3.34
3.11
2.47
NA
FDCAN1/FDCAN2/FDCAN3
I2C1
20.68
1.20
1.20
1.17
1.16
1.03
1.78
0.65
2.46
3.77
3.81
7.42
5.93
5.98
7.71
1.13
1.18
2.33
2.60
2.56
2.52
0.43
2.28
0.39
I2C2
I2C3
I2C4
LPTIM1
LPUART1
PWR
RTC
SPI2/I2S2
SPI3/I2S3
TIM2
APB1
µA/MHz
TIM3
TIM4
TIM5
TIM6
TIM7
UART4
UART5
USART2
USART3
USB
UCPD
1.89
0.31
NA
WWDG
0.42
112/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
Table 35. Peripheral current consumption (continued)
Range 1 Range 1
Low-power
run and
sleep
Bus
Peripheral
Boost
mode
Normal Range 2
Unit
mode
HRTIM
SAI1
69.98
2.67
1.99
1.99
10.85
10.67
4.81
3.71
3.66
10.71
2.49
1.63
65.11
2.48
1.86
1.86
10.13
9.96
4.48
3.45
3.41
9.99
2.31
1.52
53.68
2.05
1.54
1.54
8.40
8.25
3.71
2.88
2.83
8.29
1.91
1.25
60.95
2.64
2.02
2.02
9.93
9.82
4.57
3.45
3.81
10.00
2.49
0.91
SPI1
SPI4
TIM1
TIM8
APB2
µA/MHz
TIM15
TIM16
TIM17
TIM20
USART1
SYSCFG/COMP/OPAMP/VREFBUF
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
Table 35. Peripheral current consumption (continued)
Range 1 Range 1
Low-power
run and
sleep
Bus
Peripheral
Boost Normal Range 2
mode mode
Unit
ADC1/
ADC2
independent clock domain
independent clock domain
0.72
0.67
0.67
0.53
0.50
0.63
0.22
ADC3/
ADC4/
ADC5
0.62
FDCAN1/
FDCAN2/
FDCAN3
independent clock domain
11.62
10.84
8.95
10.24
I2C1
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
independent clock domain
4.03
3.78
2.72
3.95
1.49
1.52
4.00
4.43
0.54
0.83
1.10
3.36
6.60
6.60
7.62
7.37
7.98
369.00
3.76
3.52
2.55
3.67
1.40
1.43
3.71
4.13
0.51
0.87
1.17
3.14
6.17
6.16
7.12
6.86
7.44
316.04
3.12
2.93
2.11
3.04
1.15
1.16
3.08
3.45
0.44
NA
4.15
3.23
2.65
2.81
1.63
2.15
3.57
4.02
0.75
NA
I2C2
I2C3
I2C4
I2S2
Independent
clock domain
I2S3
µA/MHz
LPTIM1
LPUART1
QUADSPI
RNG
USB
NA
NA
SAI1
2.58
5.14
5.12
5.89
5.70
6.17
266.18
3.25
6.02
6.12
6.90
6.72
8.21
325.00
UART4
UART5
USART1
USART2
USART3
-
All
µA/MHz
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
5.3.6
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 36 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
(1)
Table 36. Low-power mode wakeup timings
Symbol
tWUSLEEP
Parameter
Conditions
Typ
Max
Unit
Wakeup time from Sleep
mode to Run mode
-
11
12
Nb of
CPU
Wakeup time from Low-
cycles
tWULPSLEEP power sleep mode to Low-
power run mode
-
10
11
Range 1
Range 2
Range 1
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
5.8
18.4
2.8
6
19.1
3
Wake up time from Stop 0
mode to Run mode in Flash
tWUSTOP0
Wake up time from Stop 0
mode to Run mode in
SRAM1
Range 2
Wakeup clock HSI16 = 16 MHz
2.9
3
Range 1
Range 2
Range 1
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
9.5
21.9
6.6
9.8
22.7
6.9
Wake up time from Stop 1
mode to Run in Flash
Wake up time from Stop 1
mode to Run mode in
SRAM1
Range 2
Wakeup clock HSI16 = 16 MHz
6.4
6.6
tWUSTOP1
Wake up time from Stop 1
27.1(2)
mode to Low-power run
mode in Flash
26.1
Regulator in
low-power
Wakeup clock
HSI16 = 16 MHz,
with HPRE = 8
µs
mode (LPR=1
in PWR_CR1)
Wake up time from Stop 1
mode to Low-power run
mode in SRAM1
15(2)
14.4
Wakeup time from Standby
tWUSTBY
Range 1
Range 1
Wakeup clock HSI16 = 16 MHz
Wakeup clock HSI16 = 16 MHz
29.7
29.7
33.8
33.5
mode to Run mode
tWUSTBY
Wakeup time from Standby
with SRAM2 to Run mode
SRAM2
Wakeup time from
tWUSHDN Shutdown mode to Run
mode
274.6(2)
Range 1
Wakeup clock HSI16 = 16 MHz
267.9
5
Wakeup time from Low-
Wakeup clock HSI16 = 16 MHz
with HPRE = 8
tWULPRUN
power run mode to Run
7
mode(3)
1. Guaranteed by characterization results.
2. Characterization results for temperature range from 0°C to 125°C
3. Time until REGLPF flag is cleared in PWR_SR2.
DS12288 Rev 5
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200
Electrical characteristics
Symbol
STM32G474xB STM32G474xC STM32G474xE
(1)
Table 37. Regulator modes transition times
Parameter
Conditions
Typ
Max Unit
Regulator transition time from Range
2 to Range 1 or
Wakeup clock HSI16 = 16 MHz
with HPRE = 8
tVOST
20
40
μs
Range 1 to Range 2(2)
1. Guaranteed by characterization results.
2. Time until VOSF flag is cleared in PWR_SR2.
(1)
Table 38. Wakeup time using USART/LPUART
Symbol
Parameter
Conditions
Stop 0 mode
Typ
Max
Unit
Wakeup time needed to calculate the
maximum USART/LPUART baudrate
allowing to wakeup up from stop mode
when USART/LPUART clock source is
HSI16
-
1.7
tWUUSART
μs
tWULPUART
Stop 1 mode
-
8.5
1. Guaranteed by design.
5.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. However,
the recommended clock input waveform is shown in Figure 19: High-speed external clock
source AC timing diagram.
(1)
Table 39. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Voltage scaling
Range 1
-
8
48
User external clock
source frequency
fHSE_ext
MHz
Voltage scaling
Range 2
-
0.7 VDD
VSS
7
8
-
26
OSC_IN input pin high
level voltage
VHSEH
VHSEL
-
-
VDD
V
OSC_IN input pin low
level voltage
-
0.3 VDD
Voltage scaling
Range 1
-
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
ns
Voltage scaling
Range 2
18
-
1. Guaranteed by design.
116/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
Figure 19. High-speed external clock source AC timing diagram
t
w(HSEH)
V
HSEH
90%
10%
V
HSEL
t
t
t
t
r(HSE)
f(HSE)
w(HSEL)
T
HSE
MS19214V2
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.14. However,
the recommended clock input waveform is shown in Figure 20.
(1)
Table 40. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
-
-
32.768
1000
kHz
OSC32_IN input pin high
level voltage
VLSEH
VLSEL
tw(LSEH)
-
-
-
0.7 VDD
VSS
-
-
-
VDD
0.3 VDD
-
V
OSC32_IN input pin low level
voltage
OSC32_IN high or low time
250
ns
tw(LSEL)
1. Guaranteed by design.
Figure 20. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
90%
10%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 41. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
(1)
Table 41. HSE oscillator characteristics
Symbol
fOSC_IN Oscillator frequency
RF Feedback resistor
Parameter
Conditions(2)
Min
Typ
Max
Unit
-
4
-
8
200
-
48
-
MHz
-
kΩ
During startup(3)
-
5.5
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
-
-
-
-
0.44
0.45
0.68
0.94
1.77
-
-
-
-
-
VDD = 3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
VDD = 3 V,
IDD(HSE) HSE current consumption
mA
Rm = 30 Ω,
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 20 pF@48 MHz
Maximum critical crystal
transconductance
Gm
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
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Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 21. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
fHSE
Bias
controlled
gain
8 MHz
resonator
RF
(1)
OSC_OUT
REXT
CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 42. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
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Symbol
STM32G474xB STM32G474xC STM32G474xE
(1)
Table 42. LSE oscillator characteristics (fLSE = 32.768 kHz)
Parameter
Conditions(2)
Min
Typ
Max Unit
LSEDRV[1:0] = 00
Low drive capability
-
250
-
LSEDRV[1:0] = 01
Medium low drive capability
-
-
-
-
-
-
315
-
IDD(LSE) LSE current consumption
nA
LSEDRV[1:0] = 10
Medium high drive capability
500
-
LSEDRV[1:0] = 11
High drive capability
630
-
LSEDRV[1:0] = 00
Low drive capability
-
-
-
0.5
LSEDRV[1:0] = 01
Medium low drive capability
0.75
µA/V
1.7
Maximum critical crystal
Gmcritmax
gm
LSEDRV[1:0] = 10
Medium high drive capability
LSEDRV[1:0] = 11
High drive capability
-
-
-
2.7
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
-
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
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5.3.8
Internal clock source characteristics
The parameters given in Table 43 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 17: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
(1)
Table 43. HSI16 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI16
HSI16 Frequency
VDD=3.0 V, TA=30 °C
15.88
-
16.08 MHz
Trimming code is not a
multiple of 64
0.2
-4
0.3
-6
0.4
%
TRIM
HSI16 user trimming step
Trimming code is a
multiple of 64
-8
DuCy(HSI16)(2) Duty Cycle
-
45
-1
-2
-
-
-
55
1
%
%
TA= 0 to 85 °C
TA= -40 to 125 °C
HSI16 oscillator frequency
drift over temperature
ꢀTemp(HSI16)
1.5
%
%
HSI16 oscillator frequency
drift over VDD
ꢀVDD(HSI16)
tsu(HSI16)(2)
tstab(HSI16)(2)
IDD(HSI16)(2)
VDD=1.62 V to 3.6 V
-0.1
-
0.05
1.2
5
HSI16 oscillator start-up
time
-
-
-
-
-
-
0.8
3
μs
μs
μA
HSI16 oscillator
stabilization time
HSI16 oscillator power
consumption
155
190
1. Guaranteed by characterization results.
2. Guaranteed by design.
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STM32G474xB STM32G474xC STM32G474xE
Figure 23. HSI16 frequency versus temperature
MHz
16.4
+2 %
+1.5 %
+1 %
16.3
16.2
16.1
16
15.9
15.8
15.7
-1 %
-1.5 %
-2 %
15.6
-40
-20
0
20
40
60
80
100
120 °C
Mean
min
max
MSv39299V2
High-speed internal 48 MHz (HSI48) RC oscillator
(1)
Table 44. HSI48 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI48
TRIM
HSI48 Frequency
VDD=3.0V, TA=30°C
-
-
-
48
-
MHz
%
HSI48 user trimming step
0.11(2) 0.18(2)
USER TRIM HSI48 user trimming
COVERAGE coverage
±32 steps
-
±3(3)
45(2)
-
±3.5(3)
-
%
%
DuCy(HSI48) Duty Cycle
-
-
55(2)
±3(3)
VDD = 3.0 V to 3.6 V,
TA = –15 to 85 °C
Accuracy of the HSI48
ACCHSI48_REL oscillator over temperature
(factory calibrated)
%
VDD = 1.65 V to 3.6 V,
TA = –40 to 125 °C
-
-
±4.5(3)
VDD = 3 V to 3.6 V
-
-
0.025(3) 0.05(3)
HSI48 oscillator frequency
DVDD(HSI48)
%
0.05(3)
0.1(3)
drift with VDD
VDD = 1.65 V to 3.6 V
HSI48 oscillator start-up
tsu(HSI48)
time
-
-
-
-
2.5(2)
6(2)
μs
HSI48 oscillator power
consumption
IDD(HSI48)
340(2)
380(2) μA
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(1)
Table 44. HSI48 oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Next transition jitter
Accumulated jitter on 28
cycles(4)
NT jitter
-
-
+/-0.15(2)
-
-
ns
ns
Paired transition jitter
Accumulated jitter on 56
cycles(4)
PT jitter
-
-
+/-0.25(2)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.
Figure 24. HSI48 frequency versus temperature
%
6
4
2
0
-2
-4
-6
-50
-30
-10
10
30
50
70
90
110
130
°C
Avg
min
max
MSv40989V1
Low-speed internal (LSI) RC oscillator
(1)
Table 45. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
DD = 3.0 V,
31.04
-
32.96
34
TA = 30 °C
fLSI
LSI Frequency
kHz
VDD = 1.62 to 3.6 V,
29.5
-
-
TA = -40 to 125 °C
LSI oscillator start-up
time
tSU(LSI)(2)
-
80
130
μs
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STM32G474xB STM32G474xC STM32G474xE
(1)
Table 45. LSI oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LSI oscillator stabilization
time
tSTAB(LSI)(2)
5% of final frequency
-
125
180
μs
LSI oscillator power
consumption
IDD(LSI)(2)
-
-
110
180
nA
1. Guaranteed by characterization results.
2. Guaranteed by design.
5.3.9
PLL characteristics
The parameters given in Table 46 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 17: General operating conditions.
DD
(1)
Table 46. PLL characteristics
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ Max Unit
PLL input clock(2)
-
-
2.66
45
-
-
16
55
MHz
%
PLL input clock duty cycle
Voltage scaling Range 1
Boost mode
2.0645
-
170
fPLL_P_OUT PLL multiplier output clock P
Voltage scaling Range 1 2.0645
Voltage scaling Range 2 2.0645
-
-
150
26
Voltage scaling Range 1
Boost mode
8
-
170
fPLL_Q_OUT PLL multiplier output clock Q
Voltage scaling Range 1
Voltage scaling Range 2
8
8
-
-
150
26
MHz
Voltage scaling Range 1
Boost mode
8
-
170
fPLL_R_OUT PLL multiplier output clock R
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
-
8
8
96
96
-
-
-
150
26
-
344
128
40
fVCO_OUT PLL VCO output
-
tLOCK
Jitter
PLL lock time
15
28.6
21.4
200
300
520
μs
RMS cycle-to-cycle jitter
RMS period jitter
-
-
System clock 150 MHz
±ps
-
-
VCO freq = 96 MHz
VCO freq = 192 MHz
VCO freq = 344 MHz
-
260
380
650
PLL power consumption on
VDD
I
DD(PLL)
-
μA
(1)
-
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock
values.
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Electrical characteristics
5.3.10
Flash memory characteristics
(1)
Table 47. Flash memory characteristics
Symbol
Parameter
Conditions
Typ
Max Unit
tprog
64-bit programming time
-
81.7
2.61
83.35
2.7
µs
Normal programming
Fast programming
Normal programming
Fast programming
One row (32 double
word) programming time
tprog_row
1.91
1.95
21.34
15.6
20.91
15.29
One page (2 Kbytes)
programming time
ms
tprog_page
tERASE
tprog_bank
tME
Page (2 Kbytes) erase
time
-
22.02
24.47
Normal programming
Fast programming
2.68
1.96
2.73
2
One bank (256 Kbyte)
programming time
s
Mass erase time
(one or two banks)
-
22.13
24.6
ms
Write mode
Erase mode
Write mode
Erase mode
3.5
-
-
-
-
Average consumption
from VDD
3.5
IDD
mA
7 (for 6 µs)
7 (for 67 µs)
Maximum current (peak)
1. Guaranteed by design.
Table 48. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Conditions
Min(1)
Unit
NEND
TA = -40 to +105 °C
10
30
15
7
kcycles
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
1 kcycle(2) at TA = 125 °C
10 kcycles(2) at TA = 55 °C
10 kcycles(2) at TA = 85 °C
10 kcycles(2) at TA = 105 °C
tRET
Data retention
Years
30
15
10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 49. They are based on the EMS levels and classes
defined in application note AN1709.
Table 49. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, TA = +25 °C,
fHCLK = 170 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
3B
5A
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 170 MHz,
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
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To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 50. EMI characteristics
Max vs. [fHSE/fHCLK
8 MHz / 170 MHz
]
Monitored
frequency band
Symbol
Parameter
Conditions
Unit
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
4
0
VDD = 3.6 V, TA = 25 °C,
Peak level LQFP128 package
compliant with IEC 61967-2
dBµV
-
SEMI
16
11
3.5
5.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 51. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge
voltage (human body model) ANSI/ESDA/JEDEC JS-001
TA = +25 °C, conforming to
VESD(HBM)
2
2000
V
LQFP100 and
LQFP128
C1
250
500
TA = +25 °C, conforming to
Electrostatic discharge
voltage (charge device model)
002
VESD(CDM)
ANSI/ESDA/JEDEC JS-
V
Other
packages
C2a
1. Guaranteed by characterization results.
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Electrical characteristics
Static latch-up
STM32G474xB STM32G474xC STM32G474xE
Two complementary static tests are required on three parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.
Table 52. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +125 °C conforming to JESD78E
Class II level A
5.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 53.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 53. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
All except TT_a, PF10, PB8-BOOT0, PC10
PF10, PB8-BOOT0, PC10
TT_a pins
-5
-0
-5
NA
NA
0
(1)
IINJ
Injected current on pin
mA
1. Guaranteed by characterization.
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5.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 17: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 54. I/O static characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
0.3xVDD
All except
FT_c
1.62 V<VDD<3.6 V
-
-
0.39xVDD-0.06(3)
I/O input
low level
voltage
(1)(2)
VIL
V
0.3xVDD
FT_c
1.62 V<VDD<3.6 V
-
-
0.25xVDD
0.7xVDD
0.49xVDD +0.26(3)
0.7xVDD
-
-
-
-
-
-
All except
FT_c
I/O input
high level
voltage
1.62 V<VDD<3.6 V
1.62 V<VDD<3.6 V
(1)(2)
(3)
VIH
V
FT_c
TT_xx,
FT_xxx,
NRST
Input
hysteresis
VHYS
1.62 V<VDD<3.6 V
-
200
-
mV
0 < VIN ≤ VDD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±100
650(4)
200(4)
2000
FT_xx
except
FT_c
V
DD ≤ VIN ≤ VDD+1 V
VDD+1 V < VIN ≤ 5.5 V
0 ≤ VIN ≤ VDDMAX
FT_c
V
DD ≤ VIN <0.5 V
3000
Input
0 ≤ VIN ≤ VDD
±150
Ileak
leakage
nA
current(3)
FT_u, PC3
VDD ≤ VIN ≤ VDD+ 1 V
±2500
±250
V
DD ≤ VIN ≤ 5.5 V
0 ≤ VIN ≤ VDD
±4500
±9000
±150
FT_d
VDD + 1V ≤ VIN ≤ 5.5 V
0 ≤ VIN ≤ VDD
TT_xx
VDD ≤ VIN ≤ 3.6 V
2000
Weak pull-
up
RPU
VIN = VSS
25
40
55
equivalent
resistor(5)
kΩ
Weak pull-
down
RPD
VIN = VDD
25
-
40
5
55
-
equivalent
resistor(5)
I/O pin
capacitance capacitance
I/O pin
CIO
-
pF
1. Refer to Figure 25: I/O input characteristics
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STM32G474xB STM32G474xC STM32G474xE
2. Data based on characterization results, not tested in production
3. Guaranteed by design.
4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 25 for standard I/Os, and in Figure 25 for
5 V tolerant I/Os.
Figure 25. I/O input characteristics
TTL requirement Vih min = 2V
TTL requirement Vil max = 0.8V
MSv37613V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 14: Voltage characteristics).
VDD
•
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating ΣI
(see
SS
VSS
Table 14: Voltage characteristics).
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Electrical characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 17: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
(1)(2)
Table 55. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
(3)
VOL
Output low level voltage for an I/O pin CMOS port
-
0.4
|IIO| = 2 mA for FT_c
(3)
I/Os = 8 mA for other I/Os VDD
≥ 2.7 V
VOH
Output high level voltage for an I/O pin
VDD-0.4
-
0.4
-
(3)
VOL
Output low level voltage for an I/O pin TTL port
|IIO| = 2 mA for FT_c
-
(3)
I/Os = 8 mA for other I/Os
VDD ≥ 2.7 V
VOH
Output high level voltage for an I/O pin
2.4
(3)
VOL
Output low level voltage for an I/O pin All I/Os except FT_c
|IIO| = 20 mA
-
1.3
-
V
(3)
VOH
Output high level voltage for an I/O pin
VDD-1.3
-
VDD ≥ 2.7 V
(3)
VOL
Output low level voltage for an I/O pin |IIO| = 1 mA for FT_c
I/Os = 4 mA for other I/Os
0.4
-
(3)
VOH
Output high level voltage for an I/O pin
VDD-0.45
VDD ≥ 1.62 V
|IIO| = 20 mA
VDD ≥ 2.7 V
-
-
0.4
0.4
Output low level voltage for an FT I/O
pin in FM+ mode (FT I/O with “f”
option)
VOLFM+
(3)
|IIO| = 10 mA
VDD ≥ 1.62 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 14:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and
Table 56, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 17: General
operating conditions.
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Electrical characteristics
Speed Symbol
STM32G474xB STM32G474xC STM32G474xE
(1) (2)
Table 56. I/O (except FT_c) AC characteristics
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
1
Maximum
frequency
Fmax
MHz
10
1.5
25
00
52
Output rise and
fall time
Tr/Tf
ns
MHz
ns
17
37
25
10
Maximum
frequency
Fmax
50
15
01
9
16
Output rise and
fall time
Tr/Tf
4.5
9
50
25
Maximum
frequency
Fmax
MHz
100(3)
37.5
5.8
11
10
Output rise and
fall time
Tr/Tf
ns
2.5
5
120(3)
50
Maximum
frequency
Fmax
MHz
180(3)
75
11
3.3
6
Output rise and
fall time(4)
Tr/Tf
ns
1.7
3.3
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Electrical characteristics
(1) (2)
Table 56. I/O (except FT_c) AC characteristics
(continued)
Speed Symbol
Parameter
Conditions
Min
Max
Unit
Maximum
frequency
Fmax(5)
-
1
5
MHz
FM+
C=50 pF, 1.6 V≤VDD≤3.6 V
Output high to
low level fall
time
Tr/TF(4)
-
ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm®-
based 32-bit MCUs" for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. This value represented the I/O capability but maximum system frequency is 170 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
5. The maximum frequency is defined with the following conditions:
- (Tr+ Tf) ≤ 2/3 T.
- 45%<Duty cycle<55%
(1) (2)
Table 57. I/O FT_c AC characteristics
Speed Symbol
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.6 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
-
-
-
2
1
Maximum
frequency
Fmax
MHz
0
Output H/L to
170
Tr/Tf L/H level fall
time
ns
MHz
ns
C=50 pF, 1.6 V≤VDD≤2.7 V
-
330
C=50 pF, 2.7 V≤VDD≤3.6 V
C=50 pF, 1.6 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤VDD≤3.6 V
-
-
-
10
5
Maximum
Fmax
frequency
1
Output H/L to
Tr/Tf L/H level fall
time
35
C=50 pF, 1.6 V≤VDD≤2.7 V
-
65
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the
SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm®-
based 32-bit MCUs" for a description of GPIO Port configuration register.
2. Guaranteed by design.
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STM32G474xB STM32G474xC STM32G474xE
(1)
Figure 26. I/O AC characteristics definition
10%
90%
50%
50%
10%
90%
t
t
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 56: I/O (except FT_c) AC characteristics.
5.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 17: General operating conditions.
(1)
Table 58. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST input low level
voltage
VIL(NRST)
-
-
-
0.3ₓVDD
V
NRST input high level
voltage
VIH(NRST)
Vhys(NRST)
RPU
-
0.7ₓVDD
-
200
40
-
-
-
NRST Schmitt trigger
voltage hysteresis
-
-
25
-
mV
kΩ
ns
Weak pull-up equivalent
resistor(2)
VIN = VSS
-
55
70
-
NRST input filtered
pulse
VF(NRST)
VNF(NRST)
NRST input not filtered
pulse
1.71 V ≤ VDD
≤ 3.6 V
350
-
ns
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
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Figure 27. Recommended NRST pin protection
External
reset circuit(1)
VDD
RPU
NRST(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 58: NRST pin characteristics. Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.16
High-resolution timer (HRTIM)
The parameters given in Table 59 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 17.
(1)
Table 59. HRTIM characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Timer ambient
temperature range
TA
fHRTIM=170 MHz
-40
-
125
°C
fHRTIM
tHRTIM
-
-
-
170
-
MHz
ns
HRTIM input clock
for DLL calibration
As per TA conditions
5.88
high-resolution
step size
fHRTIM=170 MHz,
TA from -40 to 105°C
tRES(HRTIM)
-
184
-
ps
ResHRTIM Timer resolution
Dead time
-
-
-
-
-
16
16
bit
0.125
tHRTIM
tDTG
generator clock
period
fHRTIM=170 MHz
0.735
-
94.1
ns
-
-
-
-
-
-
-
-
511
48.09
1/16
tDTG
µs
|tDTR| / |tDTF| Dead time range
(absolute value)
fHRTIM=170 MHz
-
max
-
fHRTIM=170 MHz
-
1/256
0.664
16
fHRTIM
MHz
tHRTIM
µs
Chopper stage
fCHPFRQ
clock frequency
10.625
256
Chopper first
t1STPW
pulse length
fHRTIM=170 MHz
0.094
1.506
1. Data based on characterization results, not tested in production.
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Electrical characteristics
Symbol
STM32G474xB STM32G474xC STM32G474xE
(1)
Table 60. HRTIM output response to fault protection
Parameter
Conditions
Min. Typ. Max.(2) Unit
Propagation delay from
HRTIM1_FLTx digital input to
HRTIM_CHxy output pin
Digital fault response
latency
tLAT(DF)
tW(FLT)
tLAT(AF)
-
7
-
9
-
20
-
Minimum Fault pulse
width
-
ns
Propagation delay from
comparator COMPx_INP input
pin to HRTIM_CHxy output pin
Analog fault response
latency
16
31
1. Refer to Fault paragraph in HRTIM section of RM0440.
2. Data based on characterization results, not tested in production.
Table 61. HRTIM output response to external events 1 to 5
(1)
(Low-Latency mode
)
Symbol
Parameter
Conditions
Min Typ(2) Max(2)
Unit
Propagation delay from
Digital external event HRTIM1_EEVx digital input to
tLAT(DEEV)
-
7
-
12
-
23
-
response latency
HRTIM_CHxy output pin (30pF
load)
Minimum external
event pulse width
tW(EEV)
-
ns
Propagation delay from
Analog external event comparator COMPx_INP input
tLAT(AEEV)
19
31
response latency
pin to HRTIM_CHxy output pin
(30pF load)
1. EExFAST bit in HRTIM_EECR1 register is set (Low Latency mode). This functionality is available on
external events channels 1 to 5. Refer to Latency to external events paragraph in HRTIM section of
RM0440.
2. Data based on characterization results, not tested in production.
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Electrical characteristics
(1)
Table 62. HRTIM output response to external events 1 to 10 (Synchronous mode
)
Symbol
Parameter
Conditions
Min. Typ. Max.(2)
Unit
Propagation delay from HRTIM1_EEVx
digital input to HRTIM_CHxy output pin
(30pF load) (3)
Digital external event
response latency
tLAT(DEEV)
-
56
66
ns
Propagation delay from COMPx_INP
input pin to HRTIM_CHxy output pin
(30pF load) (3)
Analog external event
response latency
tLAT(AEEV)
-
7
-
62
-
76
-
ns
ns
Minimum external event
pulse width
tW(EEV)
-
Jitter of the delay from HRTIM1_EEVx
digital input or COMPx_INP to
HRTIM_CHxy output pin
External event response
jitter
(4)
TJIT(EEV)
-
1
tHRTIM
1. EExFAST bit in HRTIM_EECR1 or HRTIM_EECR2 register is cleared (synchronous mode). External event filtering is
disabled, i.e. EExF[3:0]=0000 in HRTIM_EECR2 register. Refer to Latency to external events paragraph in HRTIM section
of RM0440.
2. Data based on characterization results, not tested in production.
3. This parameter is given for fHRTIM = 170 MHz.
4. THRTIM = 1 / fHRTIM with fHRTIM= 170 MHz.
(1)
Table 63. HRTIM synchronization input / output
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
Minimum pulse width on
tW(SYNCIN) SYNCIN inputs, including
HRTIM_SCIN
-
2
-
-
-
-
tHRTIM
Response time to external
tRES(ESR)
-
-
3
tHRTIM
synchronization request
-
-
16
-
-
tHRTIM
ns
Pulse width on
tW(SYNCOUT)
HRTIM_SCOUT output
fHRTIM=170 MHz
94.1
1. Guaranteed by design, not tested in production.
5.3.17
Extended interrupt and event controller input (EXTI) characteristics
The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
(1)
Table 64. EXTI input characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pulse length to event
controller
PLEC
-
20
-
-
ns
1. Guaranteed by design.
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.3.18
Analog switches booster
(1)
Table 65. Analog switches booster characteristics
Symbol
Parameter
Supply voltage
Min
Typ
Max
Unit
VDD
1.62
-
-
-
3.6
V
tSU(BOOST)
Booster startup time
240
µs
Booster consumption for
-
-
-
-
-
-
250
500
900
1.62 V ≤ VDD ≤ 2.0 V
Booster consumption for
IDD(BOOST)
µA
2.0 V ≤ VDD ≤ 2.7 V
Booster consumption for
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.
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Electrical characteristics
5.3.19
Analog-to-digital converter characteristics
Unless otherwise specified, the parameters given in Table 66 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK
DDA
conditions summarized in Table 17: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
(1) (2)
Table 66. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage
VDDA
-
1.62
2
-
3.6
V
Positive
reference
voltage
V
DDA ≥ 2 V
-
VDDA
V
V
VREF+
VDDA < 2 V
VDDA
Negative
reference
voltage
VREF-
-
VSSA
V
Input common
mode
(VREF++VREF-)/2 (VREF+
+
(VREF+ + VREF-)/2
+ 0.18
VCMIN
Differential
V
- 0.18
0.14
-
VREF-)/2
Range 1, single
ADC operation
-
-
60
26
Range 2
Range 1, all ADCs
operation, single
ended mode
0.14
0.14
-
-
-
52
42
56
VDDA ≥ 2.7 V
ADC clock
frequency
fADC
MHz
Range 1, all ADCs
operation, single
ended mode
VDDA ≥ 1.62 V
Range 1, all ADCs
operation,
differential mode
VDDA ≥ 1.62 V
0.14
For given
Sampling rate,
continuous mode sampling time
cycles (ts)
resolution and
fADC / (sampling time [cycles] +
resolution [bits] + 0.5)
fs
0.001
Msps
Considering trigger
conversion latency
time (tLATR or
-
-
External trigger
period
tLATRINJ
)
TTRIG
1ms
-
Resolution =
12 bits,
fADC=60 MHz
tconv + [tLATR or
-
tLATRINJ
]
Conversion
voltage range
(3)
VAIN
-
0
-
VREF+
V
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STM32G474xB STM32G474xC STM32G474xE
(1) (2)
Table 66. ADC characteristics
(continued)
Typ
Symbol
Parameter
Conditions
Min
Max
Unit
External input
impedance
(4)
RAIN
-
-
-
50
kΩ
Internal sample
and hold
capacitor
CADC
-
-
-
5
1
-
pF
conversi
on cycle
tSTAB
Power-up time
Calibration time
f
ADC = 60 MHz
-
1.93
µs
tCAL
116
1/fADC
Trigger
conversion
latency Regular
and injected
channels without
conversion abort
CKMODE = 00
CKMODE = 01
CKMODE = 10
1.5
2
-
2.5
2.0
-
-
tLATR
1/fADC
-
2.25
CKMODE = 11
-
-
2.125
Trigger
CKMODE = 00
CKMODE = 01
CKMODE = 10
2.5
3
-
3.5
3.0
conversion
latency Injected
channels
-
-
tLATRINJ
1/fADC
-
3.25
aborting a
regular
conversion
CKMODE = 11
-
-
3.125
f
ADC = 60 MHz
-
0.0416
2.5
-
-
10.675
640.5
µs
ts
Sampling time
1/fADC
tADCVREG_S ADC voltage
regulator start-up
-
-
-
-
20
µs
TUP
time
fADC = 60 MHz
Resolution =
12 bits
Total conversion
time
(including
0.25
10.883
µs
tCONV
sampling time)
-
ts[cycles] + resolution [bits] +0.5 = 15 to 653
1/fADC
fs = 4 Msps
fs = 1 Msps
fs = 10 ksps
fs = 4 Msps
fs = 1 Msps
-
-
-
-
-
590
160
16
730
220
50
ADC
consumption
from the VDDA
supply
IDDA(ADC)
µA
µA
µA
ADC
110
30
140
40
consumption
from the VREF+
single ended
mode
IDDV_S(ADC
)
fs = 10 ksps
-
0.6
2
fs = 4 Msps
fs = 1 Msps
fs = 10 ksps
-
-
-
220
60
270
70
3
ADC
IDDV_D(ADC consumption
)
from the VREF+
differential mode
1.3
1. Guaranteed by design
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2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disabled when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
4. The maximum value of RAIN can be found in Table 67: Maximum ADC RAIN.
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STM32G474xB STM32G474xC STM32G474xE
The maximum value of R
can be found in Table 67: Maximum ADC RAIN.
AIN
(1)(2)
Table 67. Maximum ADC R
AIN
RAIN max (Ω)
Fast channels(3) Slow channels(4)
Sampling cycle
@60 MHz
Sampling time
[ns]
Resolution
2.5
6.5
41.67
108.33
208.33
408.33
791.67
1541.67
4125
100
330
N/A
100
12.5
24.5
47.5
92.5
247.5
640.5
2.5
680
470
1500
2200
4700
12000
39000
120
1200
1800
3900
10000
33000
N/A
12 bits
10 bits
8 bits
10675
41.67
6.5
108.33
208.33
408.33
791.67
1541.67
4125
390
180
12.5
24.5
47.5
92.5
247.5
640.5
2.5
820
560
1500
2200
5600
12000
47000
180
1200
1800
4700
10000
39000
N/A
10675
41.67
6.5
108.33
208.33
408.33
791.67
1541.67
4125
470
270
12.5
24.5
47.5
92.5
247.5
640.5
2.5
1000
1800
2700
6800
15000
50000
220
680
1500
2200
5600
12000
50000
N/A
10675
41.67
6.5
108.33
208.33
408.33
791.67
1541.67
4125
560
330
12.5
24.5
47.5
92.5
247.5
640.5
1200
2700
3900
8200
18000
50000
1000
2200
3300
6800
15000
50000
6 bits
10675
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Electrical characteristics
1. Guaranteed by design.
2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4V). It is disabled when VDDA ≥ 2.4 V.
3. Fast channels are: ADCx_IN1 to ADCx_IN5.
4. Slow channels are: all ADC inputs except the fast channels.
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STM32G474xB STM32G474xC STM32G474xE
(1)(2)(3)
Table 68. ADC accuracy - limited test conditions 1
(4)
Symbol Parameter
Conditions
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.9 6.9
5.5 6.9
4.6 5.6
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
Differential
4
5.6
4
2.5
1.9
Single
ended
4
Offset error
Gain error
1.8 2.8
1.1 2.8
4.6 6.6
4.5 6.6
3.6 4.6
3.3 4.6
1.1 1.9
1.3 1.9
1.3 1.6
1.4 1.6
2.3 3.4
2.4 3.4
2.1 3.2
2.2 3.2
Differential
Single
ended
LSB
Differential
Single
ended
Differential
linearity
error
Single ADC operation ADC clock
frequency ≤ 60 MHz,
Differential
V
= VREF+ = 3 V, TA =
DDA
25 °C
Continuous mode, sampling
rate:
Fast channels@4Msps
Slow channels@2Msps
Single
ended
Integral
linearity
error
Differential
Fast channel (max speed) 10.4 10.6
Slow channel (max speed) 10.4 10.6
Fast channel (max speed) 10.8 10.9
Slow channel (max speed) 10.8 10.9
Fast channel (max speed) 64.4 65.6
Slow channel (max speed) 64.4 65.6
Fast channel (max speed) 66.8 67.5
Slow channel (max speed) 66.8 67.5
Fast channel (max speed) 65 66.9
Slow channel (max speed) 65 66.9
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Effective
ENOB number of
bits
bits
Differential
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Differential
dB
Single
ended
Signal-to-
SNR
Fast channel (max speed) 67
Slow channel (max speed) 67
69
69
noise ratio
Differential
-
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(1)(2)(3)
Table 68. ADC accuracy - limited test conditions 1
(continued)
(4)
Symbol Parameter
Conditions
Min Typ Max Unit
Single ADC operation ADC clock
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-73 -72
-73 -72
-73 -72
Single
ended
frequency ≤ 60 MHz,
= VREF+ = 3 V, TA =
V
DDA
Total
25 °C
THD
harmonic
distortion
dB
Continuous mode, sampling
rate:
Fast channels@4Msps
Slow channels@2Msps
Differential
Slow channel (max speed)
-
-73 -72
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disabled when VDDA ≥ 2.4 V. No oversampling.
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)(2)(3)
Table 69. ADC accuracy - limited test conditions 2
Sym-
bol
(4)
Parameter
Conditions
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
5.9
5.5
4.6
4
8.4
8
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
-
6.6
6
Differential
-
-
2.5
1.9
1.8
1.1
4.6
4.5
3.6
3.3
1.1
1.3
1.3
1.4
2.3
2.4
2.1
2.2
10.6
10.6
6
Single
ended
-
6.9
3.3
3.3
8.1
8.1
4.6
4.6
1.8
1.8
1.6
1.6
4.4
4.4
4.1
3.7
-
Offset error
Gain error
-
Differential
-
-
Single
ended
-
LSB
-
Differential
-
-
Single
ended
Differential
linearity
error
-
Single ADC operation
ADC clock frequency
-
Differential
≤ 60 MHz, 2 V ≤ V
DDA
-
Continuous mode, sampling
rate:
Fast channels@4Msps
Slow channels@2Msps
-
Single
ended
Integral
linearity
error
-
-
Differential
-
10
10
Single
ended
Effective
ENOB number of
bits
-
bits
Fast channel (max speed) 10.7 10.9
Slow channel (max speed) 10.7 10.9
-
Differential
-
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
62
62
65
65
64
64
65.6
65.6
67.5
67.5
66.9
66.9
69
-
Single
ended
Signal-to-
noise and
distortion
ratio
-
SINAD
-
Differential
-
dB
-
Single
ended
-
Signal-to-
SNR
noise ratio
Fast channel (max speed) 66.5
Slow channel (max speed) 66.5
-
Differential
69
-
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Electrical characteristics
(1)(2)(3)
Table 69. ADC accuracy - limited test conditions 2
(continued)
Sym-
bol
(4)
Parameter
Conditions
Min Typ Max Unit
Single ADC operation
ADC clock frequency
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-73
-73
-73
-65
-67
-70
Single
ended
≤ 60 MHz, 2 V ≤ V
Total
DDA
THD harmonic
distortion
Continuous mode, sampling
rate:
Fast channels@4Msps
Slow channels@2Msps
dB
Differential
Slow channel (max speed)
-
-73
-71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)(2)(3)
Table 70. ADC accuracy - limited test conditions 3
Sym-
bol
(4)
Parameter
Conditions
Min
Typ Max Unit
Fast channel (max speed)
-
5.9
5.5
7.9
7.5
7.6
5.5
5.5
5.5
3.5
3
Single
ended
Total
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
ET
EO
EG
ED
EL
unadjusted
error
-
4.6
Differential
-
4
-
2.5
Single
ended
-
-
1.9
Offset error
Gain error
1.8
Differential
-
1.1
-
4.6
7.1
7
Single
ended
-
4.5
LSB
-
3.6
4.1
4.8
1.9
1.9
1.6
1.6
4.4
4.4
3.7
3.7
-
Differential
-
3.3
-
1.1
Single
ended
Single ADC operation
ADC clock frequency ≤
60 MHz,
Differential
linearity
error
-
1.3
-
1.3
Differential
1.62 V ≤ V
≤ 3.6 V,
= V
REF+
DDA
-
1.4
-
2.3
Continuous mode,
sampling rate:
Fast channels@4Msps
Slow channels@2Msps
Single
ended
Integral
linearity
error
-
2.4
-
2.1
Differential
-
2.2
10
10
10.6
10.6
62
62
65
65
63
63
66
66
10.6
10.6
10.9
10.9
65.6
65.6
67.5
67.5
66.9
66.9
69
Single
ended
Effective
-
ENOB number of
bits
bits
-
Differential
-
-
Single
ended
Signal-to-
-
noise and
distortion
SINAD
-
ratio
Differential
-
dB
-
Single
ended
-
Signal-to-
SNR
noise ratio
-
Differential
69
-
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Electrical characteristics
(continued)
(1)(2)(3)
Table 70. ADC accuracy - limited test conditions 3
Sym-
bol
(4)
Parameter
Conditions
Min
Typ Max Unit
Single ADC operation
ADC clock frequency ≤
60 MHz,
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-73
-73
-73
-67
-67
-71
Single
ended
1.62 V ≤ V
≤ 3.6 V,
= V
REF+
Total
DDA
THD harmonic
distortion
dB
Continuous mode,
sampling rate:
Fast channels@4Msps
Slow channels@2Msps
Differential
Slow channel (max speed)
-
-73
-71
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)(2)(3)
Table 71. ADC accuracy (Multiple ADCs operation) - limited test conditions 1
(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Single ended
Differential
-
-
-
-
-
-
-
-
-
-
-
-
-
4.5
4.1
-
-
-
-
-
-
-
-
-
-
-
-
-
Totalunadjusted
error
ET
Single ended
Differential
1.3
EO
EG
Offset error
Gain error
0.4
Single ended
Differential
3.9
LSB
3.4
Multiple ADC operation
ADC clock frequency:
single ended ≤ 52 MHz,
differential ≤ 56 MHz,
Single ended
Differential
1.5
Differential
linearity error
ED
1.2
V
25°C,
= VREF= 3.3 V,
Single ended
Differential
1.7
DDA
Integral linearity
error
EL
2.1
Continuous mode,
sampling time:
Fast channels: 2.5 cycles
Slow channels: 6.5 cycles
LQFP100 package
Single ended
Differential
10.7
10.9
66.3
Effective
number of bits
ENOB
bits
dB
dB
Signal-to-noise
and distortion
ratio
Single ended
SINAD
Differential
-
67.2
-
Single ended
Differential
-
-
-
-
67.3
68.6
-73.5
-73
-
-
-
-
Signal-to-noise
ratio
SNR
THD
Single ended
Differential
Total harmonic
distortion
1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
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Electrical characteristics
(1)(2)(3)
Table 72. ADC accuracy (Multiple ADCs operation) - limited test conditions 2
(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Single ended
Differential
-
-
-
-
-
-
-
-
-
-
-
-
-
7.1
4.6
-
-
-
-
-
-
-
-
-
-
-
-
-
Totalunadjusted
error
ET
Single ended
Differential
4.2
EO
EG
Offset error
Gain error
2.8
Single ended
Differential
6.8
LSB
4.3
Multiple ADC operation
ADC clock frequency:
single ended ≤ 52 MHz,
differential ≤ 56 MHz,
Single ended
Differential
1.5
Differential
linearity error
ED
1.7
V
DDA ≥ 2.7 V, VREF≥ 1.62 V,
Single ended
Differential
3.1
Integral linearity
error
EL
-40 to 125°C,
Continuous mode,
sampling time:
Fast channels: 2.5 cycles
Slow channels: 6.5 cycles
LQFP100 package
2.4
Single ended
Differential
10.2
10.6
62.9
Effective
number of bits
ENOB
bits
dB
dB
Signal-to-noise
and distortion
ratio
Single ended
SINAD
Differential
-
65.3
-
Single ended
Differential
-
-
-
-
63.6
66.3
-
-
-
-
Signal-to-noise
ratio
SNR
THD
Single ended
Differential
-70.9
-71.8
Total harmonic
distortion
1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)(2)(3)
Table 73. ADC accuracy (Multiple ADCs operation) - limited test conditions 3
(4)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Single ended
Differential
-
-
-
-
-
-
-
-
-
-
-
-
-
7.4
4.6
4
-
-
-
-
-
-
-
-
-
-
-
-
-
Totalunadjusted
error
ET
Single ended
Differential
EO
EG
Offset error
Gain error
2.8
7.2
4.3
1.8
1.7
3.1
2.4
10.1
10.6
62.6
Single ended
Differential
LSB
Multiple ADC operation
ADC clock frequency:
single ended ≤ 42 MHz,
differential ≤ 56 MHz,
Single ended
Differential
Differential
linearity error
ED
V
= VREF≥ 1.62 V,
Single ended
Differential
DDA
Integral linearity
error
EL
-40 to 125°C,
Continuous mode,
sampling time:
Fast channels: 2.5 cycles
Slow channels: 6.5 cycles
LQFP100 package
Single ended
Differential
Effective
number of bits
ENOB
bits
dB
dB
Signal-to-noise
and distortion
ratio
Single ended
SINAD
Differential
-
65.3
-
Single ended
Differential
-
-
-
-
63.2
66.3
-
-
-
-
Signal-to-noise
ratio
SNR
THD
Single ended
Differential
-70.6
-71.8
Total harmonic
distortion
1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided
as this significantly reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enabled when V
< 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA
V
< 2.4 V). It is disabled when V
≥ 2.4 V. No oversampling.
DDA
DDA
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Electrical characteristics
Figure 28. ADC accuracy characteristics
ADC code
4095
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4094
4093
(2)
ET
= total unajusted error: maximum deviation
between the actual and ideal transfer curves.
ET
(3)
EO
= offset error: maximum deviation between the
first actual transition and the first ideal one.
7
(1)
6
5
4
3
2
1
EG
ED
EL
= gain error: deviation between the last
ideal transition and the last actual one.
EO
EL
= differential linearity error: maximum deviation
between actual steps and the ideal ones.
ED
= integral linearity error: maximum deviation
between any actual transition and the end
point correlation line.
1 LSB IDEAL
0
Vin/VREF*4096
1
2
3
4
5
6
7
4093 4094 4095 4096
MS60205V1
Figure 29. Typical connection diagram using the ADC
VDDA
Sample and hold ADC converter
(1)
RAIN
RADC
AINx
12-bit
converter
(2)
(3)
Cparasitic
CADC
Ilkg
VAIN
MS33900V6
1. Refer to Table 66: ADC characteristics for the values of RAIN and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 54: I/O static characteristics for the value of the pad capacitance). A high
C
parasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 54: I/O static characteristics for the values of Ilkg
.
General PCB design guidelines
Power supply decoupling must be performed as shown in Figure 16: Power supply scheme.
The decoupling capacitor on V
close as possible to the chip.
must be ceramic (good quality) and it must be placed as
DDA
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.3.20
Digital-to-Analog converter characteristics
(1)
Table 74. DAC 1MSPS characteristics
Symbol
Parameter
Conditions
Min
1.71
1.80
1.71
1.80
Typ
Max
Unit
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
-
-
-
-
Analog supply voltage for
DAC ON
VDDA
3.6
Other modes
DAC output buffer OFF, DAC_OUT
pin not connected (internal
connection only)
V
VREF+
Positive reference voltage
Negative reference voltage
VDDA
Other modes
-
VREF-
VSSA
connected to VSSA
DAC output
5
25
9.6
-
-
-
-
RL
Resistive load
kΩ
kΩ
buffer ON
connected to VDDA
-
11.7
-
RO
Output Impedance
DAC output buffer OFF
13.8
2
Output impedance sample VDD = 2.7 V
and hold mode, output
RBON
kΩ
kΩ
VDD = 2.0 V
-
-
-
-
-
-
3.5
buffer ON
Output impedance sample VDD = 2.7 V
and hold mode, output
16.5
18.0
RBOFF
VDD = 2.0 V
buffer OFF
CL
DAC output buffer ON
Sample and hold mode
-
-
-
50
1
pF
µF
Capacitive load
CSH
0.1
VREF+
– 0.2
DAC output buffer ON
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
DAC output buffer OFF
±0.5 LSB
0
-
-
VREF+
3
1.7
Normal mode
DAC output
buffer ON
CL ≤ 50 pF,
RL ≥ 5 kΩ
±1 LSB
-
1.6
2.9
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value)
±2 LSB
±4 LSB
±8 LSB
-
1.55
1.48
1.4
2.85
2.8
tSETTLING
µs
-
-
2.75
Normal mode DAC output buffer
OFF, ±1LSB, CL = 10 pF
-
-
-
-
2
2.5
7.5
5
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Wakeup time from off state
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
4.2
2
(2)
tWAKEUP
µs
Normal mode DAC output buffer
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
CL ≤ 50 pF, RL = 5 kΩ, DC
PSRR
VDDA supply rejection ratio
-80
-28
dB
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
(1)
Table 74. DAC 1MSPS characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Minimal time between two
consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC_OUT for a small
variation of the input code
(1 LSB)
TW_to_W
-
-
µs
DAC_MCR:MODEx[2:0] =
000 or 001
DAC_MCR:MODEx[2:0] =
010 or 011
CL ≤ 50 pF, RL ≥ 5 kΩ
CL ≤ 10 pF
1
1.4
-
DAC output buffer
0.7
3.5
18
ON, CSH = 100 nF
DAC_OUT
ms
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
pin connected
DAC output buffer
OFF, CSH = 100 nF
-
10.5
tSAMP
DAC_OUT
pin not
connected
(internal
connection
only)
DAC output buffer
OFF
-
2
3.5
µs
Sample and hold mode,
DAC_OUT pin connected
(3)
Ileak
Output leakage current
-
-
-
nA
Internal sample and hold
capacitor
CIint
-
5.2
7
8.8
pF
µs
tTRIM
Middle code offset trim time DAC output buffer ON
50
-
-
-
-
-
VREF+ = 3.6 V
1500
750
Middle code offset for 1 trim
code step
Voffset
µV
µA
VREF+ = 1.8 V
-
No load, middle
code (0x800)
-
-
-
315
450
500
670
DAC output
buffer ON
No load, worst code
(0xF1C)
DAC consumption from
VDDA
DAC output
buffer OFF
No load, middle
code (0x800)
I
DDA(DAC)
-
0.2
315 ₓ
670 ₓ
Sample and hold mode, CSH
100 nF
=
Ton/(Ton Ton/(Ton
+Toff) +Toff)
-
(4)
(4)
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)
Table 74. DAC 1MSPS characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
No load, middle
code (0x800)
-
185
240
DAC output
buffer ON
No load, worst code
(0xF1C)
-
-
340
400
DAC output
buffer OFF
No load, middle
code (0x800)
155
205
DAC consumption from
VREF+
IDDV(DAC)
µA
185 ₓ
Ton/(Ton Ton/(Ton
400 ₓ
Sample and hold mode, buffer ON,
CSH = 100 nF, worst case
-
-
+Toff)
+Toff)
(4)
(4)
155 ₓ
205 ₓ
Sample and hold mode, buffer OFF,
CSH = 100 nF, worst case
Ton/(Ton Ton/(Ton
+Toff) +Toff)
(4)
(4)
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 54: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to the reference manual RM0440 "STM32G4
Series advanced Arm®-based 32-bit MCUs" for more details.
Figure 30. 12-bit buffered / non-buffered DAC
Buffered/non-buffered DAC
Buffer(1)
RLOAD
12-bit
DACx_OUT
digital to
analog
converter
CLOAD
ai17157d
1. The DAC integrates an output buffer to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx
bit in the DAC_CR register.
156/236
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Electrical characteristics
.
(1)
Table 75. DAC 1MSPS accuracy
Conditions
DAC output buffer ON
Symbol
Parameter
Min
Typ
Max
Unit
-
-
-
±2
±2
Differential non
linearity (2)
DNL
-
DAC output buffer OFF
10 bits
-
monotonicity
Guaranteed
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±4
±4
Integral non
linearity(3)
INL
DAC output buffer OFF
CL ≤ 50 pF, no RL
VREF+ = 3.6 V
VREF+ = 1.8 V
±12
±25
±8
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
LSB
Offset error at
code 0x800(3)
Offset
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset error at
code 0x001(4)
DAC output buffer OFF
CL ≤ 50 pF, no RL
Offset1
±5
VREF+ = 3.6 V
VREF+ = 1.8 V
±5
Offset Error at
OffsetCal code 0x800
after calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±7
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
±0.5
±0.5
±30
±12
Gain
Gain error(5)
%
DAC output buffer OFF
CL ≤ 50 pF, no RL
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
Total
TUE
unadjusted
error
LSB
LSB
DAC output buffer OFF
CL ≤ 50 pF, no RL
Total
unadjusted
error after
calibration
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
TUECal
-
-
±23
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
1 kHz, BW 500 kHz
-
-
71.2
71.6
-
-
Signal-to-noise
ratio
SNR
THD
dB
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
BW 500 kHz
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
-
-
-78
-79
-
-
Total harmonic
distortion
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)
Table 75. DAC 1MSPS accuracy (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
-
70.4
-
Signal-to-noise
and distortion
ratio
SINAD
dB
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
-
-
-
71
-
-
-
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
11.4
11.5
Effective
number of bits
ENOB
bits
DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
(1)
Table 76. DAC 15MSPS characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage for
DAC ON
VDDA
-
1.71
1.71
-
-
3.6
V
VREF+
VREF-
VDAC_OUT
Positive reference voltage
Negative reference voltage
-
-
VDDA
VSSA
Voltage on DAC_OUT
output
-
0
-
VREF+
V
10%-90%
5%-95%
1%-99%
32lsb
-
-
-
-
-
-
-
-
-
-
16
21
33
40
64
24
32
49
57
93
22
29
46
53
87
32
43
67
75
125
VDDA>2,7V
With One comparator
on DAC output
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value)
1lsb
tSETTLING
ns
10%-90%
5%-95%
1%-99%
32lsb
VDDA>2,7V
With One comparator
and OPAMP on DAC
output
1lsb
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
(1)
Table 76. DAC 15MSPS characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
10%-90%
5%-95%
1%-99%
32lsb
-
-
-
-
-
-
-
-
-
-
16
21
33
40
64
24
32
49
57
93
88
116
181
196
332
128
170
265
284
483
VDDA<2,7V
With One comparator
on DAC output
Settling time (full scale: for
a 12-bit code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value)
1lsb
tSETTLING
ns
10%-90%
5%-95%
1%-99%
32lsb
VDDA<2,7V
With One comparator
and OPAMP on DAC
output
1lsb
Wakeup time from off state
(setting the ENx bit in the
DAC Control register) until
final value ±1 LSB
(2)
tWAKEUP
Normal mode CL ≤ 10 pF
-
1.4
3.5
µs
V
DD > 2.7 V
65
40
85
85
-
-
PSRR
VDDA supply rejection ratio
dB
VDD <2.7 V
Sampling time in sample
and hold mode (code
transition between the
lowest input code and the
highest input code when
DACOUT reaches final
value ±1LSB)
tSAMP
-
-
-
0.7
-
µs
Internal sample and hold
capacitor
CIint
-
-
4
5
-
pF
Voltage decay rate in
Sample and hold mode,
during hold phase
CSH = 4 pF
T = 55°C
dV/dt (hold
phase)
50
mV/ms
DAC consumption from
VDDA
IDDA(DAC)
No load, middle code (0x800)
No load, middle code (0x800)(3)
-
-
-
0.2
µA
DAC consumption from
VREF+
IDDV(DAC)
720
955
1. Guaranteed by design.
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Worst case consumption is at code 0x800.
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
.
(1)
Table 77. DAC 15MSPS accuracy
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DNL
INL
Differential non linearity (2)
Integral non linearity(3)
Total unadjusted error
-
-2
-5
-5
-
-
-
2
5
5
CL ≤ 50 pF, no RL
LSB
TUE
CL ≤ 50 pF, no RL
Spike amplitude on DAC voltage when
DAC output value is decreasing
DCS
Dynamic code spike
-
0
4
1. Guaranteed by design.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095.
Offset error is included.
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STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
5.3.21
Voltage reference buffer characteristics
(1)
Table 78. VREFBUF characteristics
Conditions Min
VRS = 00 2.4
Symbol
Parameter
Typ
Max
Unit
-
3.6
3.6
Normal mode
VRS = 01
VRS = 10
VRS= 00
2.8
3.135
-
-
3.6
Analog supply
voltage
VDDA
1.65
-
2.4
Degraded mode(2) VRS = 01
1.65
-
2.8
VRS= 10
1.65
-
3.135
2.052
2.504
2.904
VDDA
VDDA
VDDA
V
VRS= 00
2.044
2.048
Normal mode(3)
VRS= 01
VRS = 10
VRS= 00
2.496
2.5
2.896
2.9
VREFBUF_ Voltage reference
output
OUT
VDDA -250 mV
VDDA -250 mV
VDDA -250 mV
-
-
-
Degraded mode(2) VRS = 01
VRS = 10
Voltage reference
See
VREFOUT_ output spread over
Figure 31,
Figure 32,
Figure 33
VDDA = 3V
-
-
mV
(3)
the temperature
range
TEMP
Trim step
resolution
TRIM
CL
-
-
-
-
0.5
-
±0.05
±0.1
1.5
2
%
µF
Ω
Load capacitor
1
-
Equivalent Serial
Resistor of Cload
esr
Iload
Static load current
Line regulation
-
-
-
-
6.5
mA
(4)
Iline_reg
-
500 μA ≤
1000
2000
ppm/V
Normal
mode
ppm/m
A
Iload_reg
Load regulation
-
50
500
I
load ≤4 mA
-40 °C < TJ < +125 °C
0 °C < TJ < +50 °C
-
-
-
-
Tcoeff_vr
efint +
50(5)
Temperature
coefficient
TCoeff
ppm/ °C
dB
DC
40
25
-
55
40
-
Power supply
rejection
PSRR
100 kHz
-
CL = 0.5 µF(6)
CL = 1.1 µF(6)
CL = 1.5 µF(6)
300
500
650
350
650
800
tSTART
Start-up time
-
µs
-
DS12288 Rev 5
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)
Table 78. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Control of
maximum DC
current drive on
VREFBUF_
IINRUSH
-
-
8
-
mA
OUT during start-
up phase (7)
Iload = 0 µA
load = 500 µA
-
-
-
-
16
18
35
45
25
30
50
80
VREFBUF
consumption from
VDDA
I
IDDA(VREF
BUF)
µA
Iload = 4 mA
Iload = 6.5 mA
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (VDDA - drop
voltage).
3. Guaranteed by characterization results.
4. Line regulation is given for overall supply variation, in normal mode.
5. Tcoeff_vrefint refer to Tcoeff parameter in the embedded voltage reference section.
6. The capacitive load must include a 100 nF low ESR capacitor in order to cut-off the high frequency noise.
7. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V], [2.8 V to 3.6 V] and [3.135 V to 3.6 V] respectively for VRS=0,1 and 2.
Figure 31. V
in case VRS = 00
REFOUT_TEMP
V
2.06
2.055
2.05
2.045
2.04
2.035
2.03
2.025
-40
-20
0
20
Mean
40
60
80
100
120 °C
Min
Max
MSv62522V1
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Figure 32. V
Electrical characteristics
in case VRS = 01
REFOUT_TEMP
V
2.51
2.505
2.5
2.495
2.49
2.485
2.48
2.475
-40
-20
0
20
40
60
80
100
120 °C
Mean
Min
Max
MSv62523V1
Figure 33. V
in case VRS = 10
REFOUT_TEMP
V
2.91
2.905
2.9
2.895
2.89
2.885
2.88
2.875
2.87
-40
-20
0
20
Mean
40
60
80
100
120 °C
Min
Max
MSv62524V1
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.3.22
Comparator characteristics
(1)
Table 79. COMP characteristics
Parameter Conditions
Symbol
VDDA
Min
Typ
Max
Unit
Analog supply voltage
-
-
1.62
-
3.6
Comparator input voltage
range
VIN
0
-
VDDA
V
(2)
VBG
Scaler input voltage
Scaler offset voltage
-
VREFINT
±5
(3)
VSC
-
-
-
-
-
±10
300
1
mV
nA
µA
µs
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
200
Scaler static consumption from
VDDA
I
DDA(SCALER)
0.8
tSTART_SCALER Scaler startup time
Comparator startup time to
100
200
tSTART
reach propagation delay
-
-
-
5
µs
specification
Propagation delay (From
COMP input pin to COMP
output pin) for 200 mV step
with 100 mV overdrive
VDDA < 2.7 V
50pF load on
-
-
-
35
31
ns
ns
(4)
tD
output
VDDA ≥2.7 V
16.7
Full VDDA voltage range, full
temperature range
(3)
Voffset
Comparator offset error
Comparator hysteresis
-9
-6/+2
3
mV
HYST[2:0] = 0
HYST[2:0] =1
HYST[2:0] = 2
HYST[2:0] = 3
HYST[2:0] = 4
HYST[2:0] = 5
HYST[2:0] = 6
HYST[2:0] = 7
Static
-
0
9
-
4
16
32
47
63
79
95
110
720
7
18
27
36
45
54
63
450
11
15
19
23
26
-
Vhys
mV
Comparator consumption from
VDDA
IDDA(COMP)
µA
With 50 kHz ±100 mV overdrive
square signal
-
450
-
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 20: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Typical value (3V) is an average for all comparators propagation delay.
164/236
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STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
5.3.23
Operational amplifiers characteristics
(1) (2)
Table 80. OPAMP characteristics
Conditions
Symbol
Parameter
Min
Typ
Max Unit
VDDA
CMIR
Analog supply voltage
-
-
2
3.3
3.6
V
V
Common mode input
range
0
-
VDDA
25 °C, No Load on output.
All voltage/temperature.
-
-
-
-
±1.5
±3
(3)
VIOFFSET
Input offset voltage
mV
Input offset voltage
drift
ꢀVIOFFSET
-
-
-
-
±10
1.1
-
μV/°C
Offset trim step at low
common input voltage
TRIMOFFSE
TP
1.2
(0.1 ₓ VDDA
)
mV
Offset trim step at high
common input voltage
TRIMOFFSE
TN
-
-
1.3
1.65
(0.9 ₓ VDDA
)
ILOAD
ILOAD_PGA
CLOAD
Drive current
-
-
-
-
-
-
-
-
-
-
500
270
50
-
µA
Drive current in PGA
mode
Capacitive load
-
pF
dB
Common mode
rejection ratio
CMRR
60
Power supply rejection CLOAD ≤ 50 pf,
PSRR
GBW
-
80
13
-
-
dB
ratio
RLOAD ≥ 4 kΩ DC Vcom=VDDA/2
Gain Bandwidth
Product
100mV ≤ Output dynamic range ≤ VDDA -
100mV
7
MHz
Slew rate
(from 10 and 90% of
output voltage)
Normal mode
2.5
18
6.5
45
-
-
SR(3)
V/µs
dB
High-speed mode
100mV ≤ Output dynamic range ≤ VDDA
100mV
-
65
75
95
95
-
-
AO
Open loop gain
200mV ≤ Output dynamic range ≤ VDDA -
200mV
-
-
High saturation
voltage
Iload = max or Rload = min Input at VDDA
.
VDDA
- 100
(3)
VOHSAT
Follower mode
mV
I
load = max or Rload = min Input at 0.
(3)
VOLSAT
Low saturation voltage
-
-
100
Follower mode
φm
Phase margin
Gain margin
Follower mode, Vcom=VDDA/2
Follower mode, Vcom=VDDA/2
-
-
65
10
-
-
°
GM
dB
DS12288 Rev 5
165/236
200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1) (2)
Table 80. OPAMP characteristics
Parameter Conditions
(continued)
Symbol
Min
Typ
Max Unit
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
follower
Normal mode
-
3
6
configuration
Wake up time from
OFF state.
(3)
tWAKEUP
µs
CLOAD ≤ 50 pf,
RLOAD
≥
High-speed mode
20 kΩ
-
3
6
follower
configuration
OPAMP input bias
current
Ibias
See lleak parameter in Table 54: I/O static characteristics for given pin.
PGA Gain = 2 0.1 ≤ Out
V
DDA < 2.2
-2
-1
-
-
2
1
dynamic range ≤ VDDA
-
VDDA ≥ 2.2
0.1
PGA Gain=4, 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
-1
-1
-1
-2
-2
-
-
-
-
-
1
1
1
2
2
PGA Gain=8 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
Non inverting gain
value(4)
%
PGA Gain=16, 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
PGA Gain=32 200mV ≤ Output ≤ VDDA
200mV
-
PGA Gain=64 200mV ≤ Output dynamic
range ≤ VDDA - 200mV
PGA gain
PGA Gain = -1
V
DDA < 2.2
-2
-1
-
-
2
1
100mV ≤ Output dynamic
range ≤ VDDA - 100mV
VDDA ≥ 2.2
PGA Gain=-3, 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
-1
-1
-1
-2
-5
-
-
-
-
-
1
1
1
2
2
PGA Gain=-7 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
Inverting gain value
%
PGA Gain=-15, 100mV ≤ Output dynamic
range ≤ VDDA - 100mV
PGA Gain=-31 200mV ≤ Output ≤ VDDA
200mV
-
PGA Gain=-63 200mV ≤ Output dynamic
range ≤ VDDA - 200mV
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
(1) (2)
Table 80. OPAMP characteristics
(continued)
Min
Symbol
Parameter
Conditions
Typ
Max Unit
PGA Gain = 2
PGA Gain = 4
PGA Gain = 8
PGA Gain = 16
PGA Gain = 32
PGA Gain = 64
PGA Gain = -1
PGA Gain = -3
PGA Gain = -7
-
-
-
-
-
-
-
-
-
-
-
-
10/10
30/10
-
-
-
-
-
R2/R1 internal
resistance values in
non-inverting PGA
mode(5)
70/10
150/10
310/10
630/10
10/10
-
kΩ/k
Ω
Rnetwork
-
30/10
-
-
-
-
-
R2/R1 internal
70/10
resistance values in
inverting PGA mode(5)
PGA Gain = -15
PGA Gain = -31
PGA Gain = -63
150/10
310/10
630/10
Resistance variation
(R1 or R2)
Delta R
-
-15
-
+15
%
Gain = 2
-
GBW/2
GBW/4
GBW/8
GBW/16
GBW/32
GBW/64
GBW/2
GBW/4
GBW/8
GBW/16
GBW/32
GBW/64
250
-
Gain = 4
-
-
PGA bandwidth for
different non inverting
gain
Gain = 8
-
-
MHz
Gain = 16
Gain = 32
Gain = 64
Gain = -1
Gain = -3
Gain = -7
Gain = -15
Gain = -31
Gain = -63
-
-
-
-
-
-
PGA BW
-
-
-
-
-
-
PGA bandwidth for
different inverting gain
MHz
-
-
-
-
-
-
-
at 1 kHz, Output loaded with 4 kΩ
at 10 kHz, Output loaded with 4 kΩ
-
nV/√
Hz
eN
Voltage noise density
-
90
-
Normal mode
No load,
-
-
1.3
2.2
2.6
-
OPAMP consumption
from VDDA
IDDA(OPAMP)
mA
ns
follower mode
High-speed mode
VDDA < 2V
1.4
ADC sampling time
TS_OPAMP_VO when reading the
300
-
OPAMP output.
OPAINTOEN=1
UT
VDDA ≥ 2V
200
-
-
OPAMP consumption Normal mode
-
-
0.45
0.5
0.7
0.8
I
DDA(OPAMPI
no load,
follower mode
from VDDA
.
mA
NT)
High-speed mode
OPAINTOEN=1
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
1. Guaranteed by design, unless otherwise specified.
2. Data guaranteed on normal and high speed mode unless otherwise specified.
3. Guaranteed by characterization results.
4. Valid also for inverting gain configuration with external bias.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
Figure 34. OPAMP noise density @ 25°C
MSv62525V1
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STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
5.3.24
Temperature sensor characteristics
Table 81. TS characteristics
Parameter
VTS linearity with temperature
Symbol
Min
Typ
Max
Unit
(1)
TL
-
±1
2.5
±2
2.7
°C
mV/°C
V
Avg_Slope(1) Average slope
2.3
V30
Voltage at 30°C (±5 °C)(2)
0.742
0.76
0.785
(1)
tSTART-RUN
Start-up time in Run mode (start-up of buffer)
-
-
8
15
µs
µs
Start-up time when entering in continuous
mode
(3)
tSTART_CONT
70
120
ADC sampling time when reading the
temperature
(1)
tS_temp
5
-
-
-
µs
Temperature sensor consumption from VDD,
when selected by ADC
IDD(TS)(1)
4.7
7
µA
1. Guaranteed by design.
2. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer
to Table 5: Temperature sensor calibration values.
3. Continuous mode means RUN mode or Temperature Sensor ON.
5.3.25
V
monitoring characteristics
BAT
Table 82. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
39
3
-
-
-
kΩ
-
Ratio on VBAT measurement
Error on Q
Er(1)
-10
12
10
-
%
µs
(1)
tS_vbat
ADC sampling time when reading the V
-
BAT
1. Guaranteed by design.
Table 83. V
charging characteristics
BAT
Symbol
Parameter Conditions
Min
Typ
5
Max
Unit
VBRS = 0
VBRS = 1
-
-
-
-
Battery
charging
resistor
RBC
kΩ
1.5
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
5.3.26
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
(2)
Table 84. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
-
1
5.88
0
-
tTIMxCLK
ns
tres(TIM)
Timer resolution time
fTIMxCLK = 170 MHz
-
-
Timer external clock
frequency on CH1 to
CH4
f
TIMxCLK/2
MHz
fEXT
fTIMxCLK = 170 MHz
0
-
85
16
MHz
TIMx (except TIM2
and TIM5)
ResTIM
Timer resolution
bit
TIM2 and TIM5
-
-
32
1
65536
385.5
tTIMxCLK
µs
16-bit counter clock
period
tCOUNTER
fTIMxCLK = 170 MHz 0.00588
Maximum possible
tMAX_COUNT count with 32-bit
counter
-
-
-
65536 × 65536
25.26
tTIMxCLK
fTIMxCLK = 170 MHz
s
-
TIMxCLK = 170MHz
0
0
fTIMxCLK/4
42.5
MHz
MHz
Encoder frequency on
fENC
TI1 and TI2 input pins
f
Index pulsewidth on
tW(INDEX)
-
2
-
Tck
ETR input
Min pulsewidth
on TI1 and TI2 inputs
in all encoder modes
except directional
-
2
-
Tck
tW(TI1, TI2)
clock x1
Min pulsewidth
on TI1 and TI2 inputs
in directional clock x1
-
3
-
Tck
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16, 17 or 20.
2. Guaranteed by design.
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Prescaler divider PR[2:0] bits
Electrical characteristics
(1)(2)
Table 85. IWDG min/max timeout period at 32 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Unit
/4
0
0.125
0.250
0.500
1.0
512
1024
2048
4096
8192
16384
32768
/8
1
/16
2
/32
3
4
ms
/64
2.0
/128
/256
5
4.0
6 or 7
8.0
1. Guaranteed by design.
2. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
(1)
Table 86. WWDG min/max timeout value at 170 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0241
0.0482
0.0964
0.1928
1.542
3.084
6.168
12.336
ms
1. Guaranteed by design.
5.3.27
Communication interfaces characteristics
I2C interface characteristics
2
The I2C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
®
configured (refer to reference manual RM0440 "STM32G4 Series advanced Arm -based
32-bit MCUs") and when the I2CCLK frequency is greater than the minimum shown in the
table below.
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Electrical characteristics
Symbol
STM32G474xB STM32G474xC STM32G474xE
Table 87. Minimum I2CCLK frequency in all I2C modes
Parameter
Condition
Min
Unit
Standard mode
Fast-mode
2
Analog Filtre ON
DNF=0
8
9
Analog Filtre OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
MHz
Analog Filtre ON
DNF=0
17
16
Fast-mode
Plus
Analog Filtre OFF
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but is still present.
DDIOx
•
The 20mA output drive requirement in Fast-mode Plus is supported partially. This limits
the maximum load Cload supported in Fm+, which is given by these formulas:
–
–
t (SDA/SCL)=0.8473 x R x C
r p load
R (min)= (V - V (max)) / I (max)
p
DD
OL
OL
Where Rp is the I2C lines pull-up. Refer to Section 5.3.14: I/O port characteristics for the
I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 88 below for the analog
filter characteristics:
(1)
Table 88. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes that
are suppressed by the analog filter
tAF
50(2)
90(3)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI characteristics
Unless otherwise specified, the parameters given in Table 89 for SPI are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 17: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
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Electrical characteristics
(1)
Table 89. SPI characteristics
Conditions
Symbol
Parameter
Min
Typ
Max(2) Unit
Master mode
2.7 V < VDD < 3.6 V
Voltage Range V1
75
Master mode
1.71 V < VDD < 3.6 V
Voltage Range V1
50
50
Master transmitter mode
1.71 V < VDD < 3.6 V
Voltage Range V1
Slave receiver mode
1.71 V < VDD < 3.6 V
Voltage Range V1
fSCK
1/tc(SCK)
SPI clock frequency
-
-
MHz
50
41
27
13
Slave mode transmitter/full duplex
2.7 V < VDD < 3.6 V
Voltage Range V1
Slave mode transmitter/full duplex
1.71 V < VDD < 3.6 V
Voltage Range V1
1.71 V < VDD < 3.6 V
Voltage Range V2
tsu(NSS) NSS setup time
th(NSS) NSS hold time
tw(SCKH)
Slave mode
Slave mode
4*Tpclk
2*Tpclk
-
-
-
-
-
-
SCK high and low time Master mode, SPI prescaler = 2
Tpclk-1
Tpclk
Tpclk+1
ns
ns
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
Master mode
Data input setup time
4
3
4
1
9
9
-
-
-
-
-
-
-
-
Slave mode
Master mode
Data input hold time
-
ns
th(SI)
Slave mode
-
ta(SO) Data output access time Slave mode
tdis(SO) Data output disable time Slave mode
34
16
ns
ns
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)
Table 89. SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max(2) Unit
Slave mode
2.7 V < VDD < 3.6 V
Voltage Range V1
-
9
12
Slave mode
tv(SO)
1.71 V < VDD < 3.6 V
Voltage Range V1
-
-
9
18
Data output valid time
Slave mode
1.71 V < VDD < 3.6 V
Voltage Range V2
ns
22
13
tv(MO)
th(SO)
th(MO)
Master mode
-
3.5
4.5
Slave mode 1.71 V < VDD < 3.6 V
Slave mode Range V2
Master mode
6
9
2
-
-
-
-
-
-
Data output hold time
1. Guaranteed by characterization results.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into
SCK low or high-phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
Figure 35. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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Electrical characteristics
Figure 36. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 37. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
I2S characteristics
Unless otherwise specified, the parameters given in Table 90 for I2S are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 17: General operating conditions, with the following
configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30pF
Measurement points are done at CMOS levels: 0.5 V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
(1)
Table 90. I2S characteristics
Uni
t
Symbol
fMCLK
fCK
Parameter
Conditions
Min
Max
I2S Main clock
output
256x8
K
256
MH
z
-
*Fs(2)
Master data
Slave data
-
-
64xFs
64xFs
MH
z
I2S clock frequency
I2S clock frequency
duty cycle
DCK
Slave receiver
30
70
%
tv(WS)
WS valid time
WS hold time
WS setup time
Master mode
Master mode
Slave mode
-
3
2
4
3
4
4
2
-
6
-
th(WS)
-
tsu(WS)
Slave mode
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
-
Data input setup
time
-
-
ns
Data input hold time
-
2.7 V ≤ VDD ≤ 3.6 V
1.65 V ≤ VDD ≤ 3.6 V
15
22
3
-
Slave transmitter (after
enable edge)
tv(SD_ST)
Data output valid
time
-
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
-
7
1
Data output hold
time
-
1. Guaranteed by characterization results, not tested in production.
2. 256xFs maximum is 49.152 MHz.
®
Note:
Refer to the reference manual RM0440 "STM32G4 Series advanced Arm -based 32-bit
MCUs" I2S section for more details about the sampling frequency (Fs), f
, f , D
MCK CK
CK
values reflect only the digital peripheral behavior, source clock precision might slightly
change the values D depends mainly on ODD bit value. Digital contribution leads to a min
CK
of (I2SDIV/(2*I2SDIV+ODD) and a max (I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max
supported for each mode/condition.
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SAI characteristics
Electrical characteristics
Unless otherwise specified, the parameters given in Table 91 for SAI are derived from tests
performed under the ambient temperature, f frequency and V supply voltage condi-
PCLKx
DD
tions summarized inTable 17: General operating conditions, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,FS).
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)
Table 91. SAI characteristics
Conditions
Symbol
Parameter
Min
Max Unit
fMCLK
SAI Main clock output
-
-
50
33
MHz
Master transmitter
2.7 V ≤ VDD ≤ 3.6 V
-
Voltage Range 1
Master transmitter
1.71 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
-
-
22
22
45
Master receiver
Voltage Range 1
Slave transmitter
2.7 V ≤ VDD ≤ 3.6 V
Voltage Range 1
fCK
SAI clock frequency(2)
MHz
Slave transmitter
1.71 V ≤ VDD ≤ 3.6 V
Voltage Range 1
-
29
Slave receiver
Voltage Range 1
-
-
-
-
50
13
15
22
Slave transmitter
Voltage Range 2
Master mode
2.7 V ≤ VDD ≤ 3.6 V
tv(FS)
FS valid time
ns
Master mode
1.71 V ≤ VDD ≤ 3.6 V
th(FS)
tsu(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
10
2
-
-
-
-
-
-
-
ns
ns
ns
th(FS)
Slave mode
1
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
2.5
1
Data input setup time
Data input hold time
ns
ns
5
1
Slave transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
-
-
11
17
Slave transmitter (after enable edge)
1.71 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time
ns
ns
Slave transmitter (after enable edge)
voltage range V2
-
20
-
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge)
10
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Electrical characteristics
(1)
Table 91. SAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max Unit
Master transmitter (after enable edge)
2.7 V ≤ VDD ≤ 3.6 V
-
14
ns
21
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
1.71 V ≤ VDD ≤ 3.6 V
-
th(SD_A_MT) Data output hold time Master transmitter (after enable edge)
10
-
ns
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
Figure 38. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 39. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
CAN (controller area network) interface
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCANx_TX and FDCANx_RX).
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
USB characteristics
The device USB interface is fully compliant with the USB specification version 2.0 and is
USB-IF certified (for Full-speed device operation).
(1)
Table 92. USB electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
USB transceiver operating voltage
3.0(2)
-15
-
3.6
85
V
tCrystal_less USB crystal less operation temperature
-
°C
RPUI
Embedded USB_DP pull-up value during idle
Embedded USB_PD pull-up value during reception
Output driver impedance(4)
Driving high and low
900
1400
28
1250
2300
36
1500
3200
44
ꢁ
ꢁ
RPUR
(3)
ZsDRV
1. TA = -40 to 125 °C unless otherwise specified.
2. The device USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics, which are degraded in
the 2.7-to-3.0 V voltage range.
3. Guarantee by design.
4. No external termination series resistors are required on USB_PD (D+) and USB_DM (D-); the matching impedance is
already included in the embedded driver.
USART interface characteristics
Unless otherwise specified, the parameters given in Table 93 for USART are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 93, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30 pF
Measurement points are done at CMOS levels: 0.5 V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
(1)
Table 93. USART electrical characteristics
Symbol
Parameter
Conditions
Master mode
Min
Typ
Max
Unit
-
-
-
-
-
21
22
-
fCK
USART clock frequency
MHz
Slave mode
Slave mode
Slave mode
-
tker + 2
2
tsu(NSS)
th(NSS)
NSS setup time
NSS hold time
ns
-
tw(CKH)
tw(CKL)
CK high and low time
Data input setup time
Master mode
1/fck/2-1
1/fck/2 1/fck/2+1 ns
Master mode
Slave mode
Master mode
Slave mode
tker + 2
-
-
-
-
-
-
-
-
tsu(RX)
th(RX)
2
1
ns
Data input hold time
0.5
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Electrical characteristics
(1)
Table 93. USART electrical characteristics (continued)
Symbol
Parameter
Conditions
Master mode
Min
Typ
Max
Unit
-
-
0.5
10
-
1.5
22
-
tv(TX)
Data output valid time
Slave mode
Master mode
Slave mode
ns
0
7
th(RX)
Data output hold time
-
-
1. Based on characterization, not tested in production.
5.3.28
FSMC characteristics
Unless otherwise specified, the parameters given in Table 94 to Table 107 for the FMC
interface are derived from tests performed under the ambient temperature, f frequency
HCLK
and V supply voltage conditions summarized in Table 17, with the following configuration:
DD
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 x V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 40 through Figure 43 represent asynchronous waveforms and Table 94 through
Table 101 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
•
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataHoldTime = 0x1
ByteLaneSetup = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
In all timing tables, the THCLK is the HCLK clock period.
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
Figure 40. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
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Electrical characteristics
(1)(2)
Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
3 THCLK– 0.5
3THCLK+ 1
FMC_NEx low to FMC_NOE low
FMC_NOE low time
0
1
2 THCLK– 0.5
2 THCLK+ 1
th(NE_NOE)
tv(A_NE)
th(A_NOE)
tsu(Data_NE)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
Address hold time after FMC_NOE high
Data to FMC_NEx high setup time
THCLK
-
-
2
2 THCLK– 1
-
ns
THCLK + 20
-
tsu(Data_NOE) Data to FMC_NOEx high setup time
20
0
0
-
-
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
Data hold time after FMC_NOE high
Data hold time after FMC_NEx high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
-
1.5
-
THCLK+ 8
1. CL = 30 pF.
2. Guaranteed by characterization results.
Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
-
8 THCLK + 1
tw(NOE)
FMC_NWE low time
FMC_NWAIT low time
7 THCLK - 1 7 THCLK + 0.5
ns
tw(NWAIT)
THCLK
-
-
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
5 THCLK + 17
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 THCLK + 17
1. CL = 30 pF.
2. Guaranteed by characterization results.
DS12288 Rev 5
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
Figure 41. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
(1)(2)
Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
3 THCLK - 0.5
3 THCLK + 1
tv(NWE_NE) FMC_NEx low to FMC_NWE low
tw(NWE) FMC_NWE low time
th(NE_NWE) FMC_NWE high to FMC_NE high hold time
tv(A_NE) FMC_NEx low to FMC_A valid
th(A_NWE) Address hold time after FMC_NWE high
tv(BL_NE) FMC_NEx low to FMC_BL valid
THCLK - 0.5
THCLK + 1
THCLK -2
THCLK + 1
THCLK - 0.5
-
-
0
THCLK - 1
-
ns
-
0
th(BL_NWE) FMC_BL hold time after FMC_NWE high
tv(Data_NE) Data to FMC_NEx low to Data valid
th(Data_NWE) Data hold time after FMC_NWE high
tv(NADV_NE) FMC_NEx low to FMC_NADV low
THCLK + 0.5
-
THCLK + 2
-
-
THCLK + 6
-
-
1.5
tw(NADV)
FMC_NADV low time
THCLK + 0.5
1. CL = 30 pF.
2. Guaranteed by characterization results.
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Electrical characteristics
Table 97. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
(1)(2)
timings
Symbol
Parameter
FMC_NE low time
FMC_NWE low time
Min
Max
Unit
tw(NE)
9 THCLK - 1 9 THCLK + 1
6 THCLK - 1 6 THCLK + 1
tw(NWE)
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
7 THCLK + 17
-
-
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 7 THCLK + 17
1. CL = 30 pF.
2. Guaranteed by characterization results.
Figure 42. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
DS12288 Rev 5
185/236
200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)(2)
Table 98. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
3 THCLK - 0.5 3 THCLK + 1
tv(NOE_NE) FMC_NEx low to FMC_NOE low
tw(NOE) FMC_NOE low time
th(NE_NOE) FMC_NOE high to FMC_NE high hold time
tv(A_NE) FMC_NEx low to FMC_A valid
tv(NADV_NE) FMC_NEx low to FMC_NADV low
0
1
2 THCLK - 0.5 2 THCLK + 0.5
THCLK
-
-
2
1.5
0.5
tw(NADV)
FMC_NADV low time
THCLK
THCLK + 1.5
FMC_AD(address) valid hold time after
FMC_NADV high
ns
th(AD_NADV)
THCLK - 0.3
-
Addresshold
until next
read
th(A_NOE) Address hold time after FMC_NOE high
-
operation
tsu(Data_NE) Data to FMC_NEx high setup time
tsu(Data_NOE) Data to FMC_NOE high setup time
th(Data_NE) Data hold time after FMC_NEx high
th(Data_NOE) Data hold time after FMC_NOE high
THCLK + 20
-
-
-
-
20
0
0
1. CL = 30 pF.
2. Guaranteed by characterization results.
(1)(2)
Table 99. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
FMC_NE low time
FMC_NWE low time
Min
Max
Unit
tw(NE)
8 THCLK - 1
8 THCLK + 1
tw(NOE)
7 THCLK - 1 7 THCLK + 0.5
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
5 THCLK + 17
-
-
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 THCLK + 17
1. CL = 30 pF.
2. Guaranteed by characterization results.
186/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
Figure 43. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FMC_ NEx
FMC_NOE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
FMC_NWE
t
t
h(A_NWE)
v(A_NE)
FMC_ A[25:16]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_ NBL[1:0]
NBL
v(Data_NADV)
Data
t
t
h(Data_NWE)
t
v(A_NE)
Address
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
DS12288 Rev 5
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200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)(2)
Table 100. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
3 THCLK - 0.5 3 THCLK + 1
tv(NWE_NE) FMC_NEx low to FMC_NWE low
tw(NWE) FMC_NWE low time
th(NE_NWE) FMC_NWE high to FMC_NE high hold time
tv(A_NE) FMC_NEx low to FMC_A valid
tv(NADV_NE) FMC_NEx low to FMC_NADV low
THCLK - 0.5
THCLK - 2
THCLK - 0.5
-
THCLK + 1
THCLK + 1
-
0
1.5
0
tw(NADV)
FMC_NADV low time
THCLK + 0.5
THCLK + 1.5
FMC_AD(address) valid hold time after
FMC_NADV high
ns
th(AD_NADV)
T
HCLK - 3
-
Address hold
until next
write
th(A_NWE) Address hold time after FMC_NWE high
th(BL_NWE) FMC_BL hold time after FMC_NWE high
-
operation
THCLK - 0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0
tv(Data_NADV) FMC_NADV high to Data valid
-
THCLK + 2
-
th(Data_NWE) Data hold time after FMC_NWE high
THCLK + 6
1. CL = 30 pF.
2. Guaranteed by characterization results.
(1)(2)
Table 101. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
FMC_NE low time
FMC_NWE low time
Min
Max
Unit
tw(NE)
9 THCLK - 1
9 THCLK + 1
tw(NWE)
6 THCLK - 1 6 THCLK + 0.5
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
7 THCLK + 17
-
-
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 5 THCLK + 17
1. CL = 30 pF.
2. Guaranteed by characterization results.
188/236
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STM32G474xB STM32G474xC STM32G474xE
Synchronous waveforms and timings
Electrical characteristics
Figure 44 through Figure 47 represent synchronous waveforms and Table 102
through Table 105 provide the corresponding timings. The results shown in these
tables are obtained with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period.
•
For 2.7 V ≤ V ≤ 3.6 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 54 MHz
for CLKDIV = 0x0 at CL = 30 pF (on FMC_CLK).
DD
•
For 1.71 V ≤ V ≤ 2.7 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and
32 MHz for CLKDIV = 0x0 at CL= 20 pF (on FMC_CLK).
DD
Figure 44. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
MS32757V1
DS12288 Rev 5
189/236
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)(2)(3)
Table 102. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max Unit
tw(CLK)
FMC_CLK period
R*THCLK - 0.5
-
1.5
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
R*THCLK/2 + 1
-
2.5
-
3.5
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
4
R*THCLK/2 + 1
-
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low
-
2
-
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
R*THCLK/2 + 1
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
-
0
3
-
2
-
4
-
1.5
4
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
190/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
Figure 45. Synchronous multiplexed PSRAM write timings
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DS12288 Rev 5
191/236
200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
(1)(2)(3)
Table 103. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
R*THCLK - 0.5
-
1.5
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
R*THCLK/2 + 1
-
2.5
-
3.5
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
4
-
R*THCLK/2 + 1
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
-
2
-
ns
R*THCLK/2 + 1
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
-
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
0
-
3
-
1
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
R*THCLK/2 + 1.5
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1.5
4
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
192/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
Figure 46. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
MS32759V1
(1)(2)(3)
Table 104. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max Unit
tw(CLK)
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0..2)
R*THCLK - 0.5
-
1.5
-
td(CLKL-NExL)
-
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
R*THCLK/2 + 1
-
2.5
-
3.5
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
-
4
-
ns
R*THCLK/2+- 1
-
2
-
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high
R*THCLK/2 + 1
2
4
-
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1.5
4
-
ns
-
DS12288 Rev 5
193/236
200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
Figure 47. Synchronous non-multiplexed PSRAM write timings
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194/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Electrical characteristics
(1)(2)(3)
Table 105. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
R*THCLK - 0.5
-
1.5
-
td(CLKL-NExL)
td(CLKH-NExH)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
-
R*THCLK/2 + 1
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
2.5
-
3.5
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
4
-
R*THCLK/2 + 1
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
-
2
-
R*THCLK/2 + 1
td(CLKL-Data)
td(CLKL-NBLL)
FMC_D[15:0] valid data after FMC_CLK low
FMC_CLK low to FMC_NBL low
-
3
-
1
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
R*THCLK/2 + 1.5
-
1.5
4
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
NAND controller waveforms and timings
Figure 48 through Figure 51 represent synchronous waveforms, and Table 106 and
Table 107 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x01
COM.FMC_WaitSetupTime = 0x03
COM.FMC_HoldSetupTime = 0x02
COM.FMC_HiZSetupTime = 0x01
ATT.FMC_SetupTime = 0x01
ATT.FMC_WaitSetupTime = 0x03
ATT.FMC_HoldSetupTime = 0x02
ATT.FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
In all timing tables, the THCLK is the HCLK clock period.
DS12288 Rev 5
195/236
200
Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
Figure 48. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
th(NOE-ALE)
td(NCE-NOE)
FMC_NOE (NRE)
FMC_D[15:0]
tsu(D-NOE)
th(NOE-D)
MSv38003V1
Figure 49. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NWE-ALE)
td(NCE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
th(NWE-D)
tv(NWE-D)
MSv38004V1
Figure 50. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NOE-ALE)
td(NCE-NOE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MSv38005V1
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Electrical characteristics
Figure 51. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE)
tw(NWE)
th(NOE-ALE)
FMC_NWE
FMC_NOE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FMC_D[15:0]
MSv38006V1
(1)(2)
Table 106. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
FMC_NOE low width
Min
Max
Unit
Tw(N0E)
Tsu(D-NOE)
Th(NOE-D)
4 THCLK - 1
4 THCLK
FMC_D[15-0] valid data before FMC_NOE high
FMC_D[15-0] valid data after FMC_NOE high
19
-
0
-
ns
Td(NCE-NOE) FMC_NCE valid before FMC_NOE low
Th(NOE-ALE) FMC_NOE high to FMC_ALE invalid
-
3 THCLK
-
3 THCLK
1. CL = 30 pF.
2. Guaranteed by characterization results.
(1)(2)
Table 107. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
FMC_NWE low width
Min
Max
Unit
Tw(NWE)
Tv(NWE-D)
Th(NWE-D)
Td(D-NWE)
4 THCLK -1
0
4 THCLK
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
FMC_D[15-0] valid before FMC_NWE high
-
3 THCLK - 1
5 THCLK
-
-
ns
-
Td(NCE_NWE) FMC_NCE valid before FMC_NWE low
3 THCLK
-
Th(NWE-ALE)
FMC_NWE high to FMC_ALE invalid
3 THCLK
1. CL = 30 pF.
2. Guaranteed by characterization results.
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STM32G474xB STM32G474xC STM32G474xE
5.3.29
QUADSPI characteristics
Unless otherwise specified, the parameters given in Table 108 and Table 109 for Quad SPI
are derived from tests performed under the ambient temperature, f
frequency and V
AHB
DD
supply voltage conditions summarized in Table 17: General operating conditions, with the
following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 15 or 20 pF
Measurement points are done at CMOS levels: 0.5 ₓ V
DD
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
Table 108. Quad SPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71 < VDD< 3.6 V,
CLOAD = 15 pF
-
-
50
Voltage Range 1
Quad SPI clock
frequency
F(QCK)
MHz
1.71 < VDD< 3.6 V,
CLOAD = 20 pF
-
-
110
Voltage Range 2
tw(CKH) Quad SPI clock high
and low time
t(CK)/2-0.5
t(CK)/2-1
-
-
-
-
t(CK)/2+1
t(CK)/2+0.5
PRESCALER [7:0]
n =0,1, 3, 5...
tw(CKL)
Even division
tw(CKH) Quad SPI clock high
and low time
(n/2)*t(CK)/(n+1) - 0.5
(n/2+1)*t(CK)/(n+1) - 1
(n/2)*t(CK)/(n+1) + 1
(n/2+1)*t(CK)/(n+1) +0.5
PRESCALER [7:0]
n =2,4, 6, 8...
tw(CKL)
Odd division
ns
ts(IN)
Data input setup time 1.71 < VDD< 3.6 V
1
5
-
-
-
-
th(IN) Data input hold time 1.71 < VDD< 3.6 V
Data output valid
tv(OUT)
1.71 < VDD< 3.6 V
-
1
-
1.5
-
time
th(OUT) Data output hold time 1.71 < VDD< 3.6 V
1. Guaranteed by characterization results.
0.5
(1)
Table 109. QUADSPI characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71 < VDD< 3.6 V,
CLOAD = 15 pF
-
-
50
70
Voltage Range 1
Quad SPI clock
frequency
F(QCK)
MHz
1.71 < VDD< 3.6 V,
CLOAD = 20 pF
-
-
Voltage Range 2
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(1)
Table 109. QUADSPI characteristics in DDR mode (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tw(CKH) Quad SPI clock high
and low time
t(CK)/2
-
t(CK)/2+1
PRESCALER [7:0]
n =0,1, 3, 5 ...
tw(CKL)
t(CK)/2-1
-
-
-
t(CK)/2
Even division
tw(CKH) Quad SPI clock high and
low time
(n/2)*t(CK)/(n+1)
(n/2)*t(CK)/(n+1) + 1
(n/2+1)*t(CK)/(n+1)
PRESCALER [7:0]
n =2,4, 6, 8...
tw(CKL)
(n/2+1)*t(CK)/(n+1) - 1
Odd division
Data input setup time on
rising edge
tsr(IN)
1.71 < VDD< 3.6 V
1.71 < VDD< 3.6 V
1.71 < VDD< 3.6 V
1.71 < VDD< 3.6 V
1
1
6
5
-
-
Data input setup time on
falling edge
tsf(IN)
thr(IN)
thf(IN)
-
-
-
Data input hold time on
rising edge
-
Data input hold time on
falling edge
-
-
1.71 < VDD< 3.6 V
DHHC = 0
7.5
8
ns
Data output valid time on
rising edge
tvr(OUT)
-
-
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2
+1
Thclk/2+1.5
1.71 < VDD< 3.6 V
DHHC = 0
7
10
tvf(OUT) Data output valid time
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2
+1
Thclk/2+2
1.71 < VDD< 3.6 V
DHHC = 0
2
-
-
-
-
-
-
-
-
Data output hold time on
rising edge
thr(OUT)
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2+ 0.5
3
1.71 < VDD< 3.6 V
DHHC = 0
Data output hold time on
falling edge
thf(OUT)
1.71 < VDD< 3.6 V
DHHC = 1
Thclk/2+0.5
1. Guaranteed by characterization results.
Figure 52. Quad SPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
Figure 53. Quad SPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
5.3.30
UCPD characteristics
UCPD1 controller complies with USB Type-C Rev.1.2 and USB Power Delivery Rev. 3.0
specifications.
Table 110. UCPD characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Sink mode only
3.0
3.3
3.3
3.6
V
V
VDD
UCPD operating supply voltage
Sink and source mode
3.135
3.465
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Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1
WLCSP81 package information
WLCSP81 is a 81-ball, 4.02x4.27 mm, 0.4 mm pitch wafer level chip scale package.
Figure 54. WLCSP81 - outline
DETAIL A
bbb Z
A1 BALL
LOCATION
F
D
A1
e1
A
G
e2
E
e
J
A
A2
9
1
eee
(4X)
BOTTOM VIEW
TOP VIEW
SIDE VIEW
A2
A3
BUMP
b
A1
FRONT VIEW
eee
Z
z
b(81x)
ccc M
X
Y
Z
Z
SEATING PLANE
M
ddd
DETAIL A
ROTATED 90
B068_WLCSP81_DIE469_ME_V1
1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
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Package information
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Table 111. WLCSP81 - mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A(2)
A1
A2
A3
b
-
-
0.18
0.38
0.025
0.25
4.02
4.27
0.40
3.20
3.20
0.410
0.535
-
0.59
-
-
0.023
-
-
-
0.007
0.015
0.001
0.010
0.158
0.168
0.016
0.126
0.126
0.016
0.021
-
-
-
-
-
-
-
-
-
-
0.22
0.28
4.04
4.29
-
0.009
0.011
0.159
0.169
-
D
4.00
0.157
E
4.25
0.167
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
-
-
e2
-
-
F(3)
G(3)
aaa
bbb
ccc
ddd
eee
-
-
-
-
0.10
0.10
0.10
0.05
0.05
0.004
0.004
0.004
0.002
0.002
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 3 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Calculated dimensions are rounded to the 3rd decimal place
Figure 55. WLCSP81 - recommended footprint
Dpad
Dsm
B068_WLCSP81_DIE469_FP_V1
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Package information
Table 112. WLCSP81 - recommended PCB design rules
Dimension Recommended values
Pitch
Dpad
Dsm
0.4 mm
0,225 mm
0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
DS12288 Rev 5
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Package information
STM32G474xB STM32G474xC STM32G474xE
6.2
UFQFPN48 package information
UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 56. UFQFPN48 - outline
Pin 1 identifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500x45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
204/236
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Package information
inches(1)
Table 113. UFQFPN48 - mechanical data
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 57. UFQFPN48 - recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
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Package information
STM32G474xB STM32G474xC STM32G474xE
UFQFPN48 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 58. UFQFPN48 top view example
Product
(1)
identification
STM32G474
CEU6
Date code
Y WW
Revision code
Pin 1
identification
B
MS51944V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
206/236
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Package information
6.3
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Figure 59. LQFP48 - outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
36
25
37
24
b
48
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
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Package information
STM32G474xB STM32G474xC STM32G474xE
Table 114. LQFP48 - mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
208/236
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Package information
Figure 60. LQFP48 - recommended footprint
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
DS12288 Rev 5
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Package information
STM32G474xB STM32G474xC STM32G474xE
LQFP48 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 61. LQFP48 top view example
Product
(1)
identification
STM32G474
CET6
Date code
Y WW
Revision code
Pin 1
identification
B
MS51943V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
1.
210/236
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Package information
6.4
LQFP64 package information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 62. LQFP64 - outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
D1
D3
L
L1
33
48
32
49
64
b
17
16
1
PIN 1
e
IDENTIFICATION
5W_ME_V3
1. Drawing is not to scale.
Table 115. LQFP64 - mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
-
-
-
-
12.000
10.000
7.500
12.000
10.000
-
-
-
-
-
-
-
-
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
-
-
-
-
-
D1
D3
E
E1
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Package information
STM32G474xB STM32G474xC STM32G474xE
Table 115. LQFP64 - mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E3
e
-
7.500
0.500
3.5°
-
-
0.2953
0.0197
3.5°
-
-
-
7°
-
-
7°
K
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 63. LQFP64 - recommended footprint
48
33
0.3
0.5
49
32
12.7
10.3
10.3
7.8
17
64
1.2
16
1
12.7
ai14909c
1. Dimensions are expressed in millimeters.
212/236
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LQFP64 device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 64. LQFP64 top view example
Product
(1)
identification
STM32G474
RET6
Date code
Y WW
Revision code
Pin 1
identification
B
MS51941V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12288 Rev 5
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232
Package information
STM32G474xB STM32G474xC STM32G474xE
6.5
LQFP80 package information
LQFP80 is a 80-pin, 12 x 12 mm low-profile quad flat package.
Figure 65. LQFP80 - outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
L
k
D
L1
D1
D3
60
41
61
40
80
21
PIN 1
IDENTIFICATION
1
20
e
9X_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
Table 116. LQFP80 - mechanical data
Millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.050
1.350
0.170
0.090
-
0.0020
0.0531
0.0067
0.0035
-
1.400
0.220
-
0.0551
0.0087
-
c
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Package information
inches(1)
Table 116. LQFP80 - mechanical data (continued)
Millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
D
D1
D2
E
-
14.000
12.000
9.500
14.000
12.000
9.500
0.500
0.600
1.000
-
-
-
0.5512
0.4724
0.3740
0.5512
0.4724
0.3740
0.0197
0.0236
0.0394
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E1
E3
e
-
-
-
-
-
-
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
ccc
k
-
-
-
-
0.080
7.0°
0.0031
7.0°
0.0°
-
0.0°
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 66. LQFP80 - recommended footprint
80
61
1
0.5
60
20
41
1.2
21
40
9.8
14.7
9X_FP
1. Dimensions are expressed in millimeters.
DS12288 Rev 5
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232
Package information
STM32G474xB STM32G474xC STM32G474xE
LQFP80 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 67. LQFP80 top view example
Product
identification
(1)
STM32G474
MET6
Revision code
Z
Date code
Y WW
Pin 1
identification
MS51945V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
216/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Package information
6.6
TFBGA100 package information
TFBGA is a 100-ball, 8 x 8 mm, 0.8 mm pitch fine pitch ball grid array package.
Figure 68. TFBGA100 - outline
SEATING
PLANE
C
A1 ball
index
area
A1 ball
identifier
D1
D
e
F
A
B
C
D
E
F
G
H
J
A
K
10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
TOP VIEW
b(100 BALLS)
eee
fff
C
C
A B
A08Q_ME_V1
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232
Package information
STM32G474xB STM32G474xC STM32G474xE
Table 117. TFBGA100 - mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
A2
b
-
-
1.100
-
-
0.0433
0.150
-
-
0.0059
-
-
-
0.760
0.400
8.000
7.200
8.000
7.200
0.800
0.400
0.400
-
-
-
0.0299
0.0157
0.3150
0.2835
0.3150
0.2835
0.0315
0.0157
0.0157
-
-
0.350
0.450
0.0138
0.0177
D
7.850
8.150
0.3091
0.3209
D1
E
-
-
-
-
7.850
8.150
0.3091
0.3209
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
-
G
-
-
ddd
eee
fff
0.100
0.150
0.080
0.0039
0.0059
0.0031
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 69. TFBGA100 - recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 118. TFBGA100 - recommended PCB design rules
Dimension
Recommended values
Pitch
Dpad
0.8
0.400 mm
0.470 mm typ. (depends on the soldermask
registration tolerance)
Dsm
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Package information
Table 118. TFBGA100 - recommended PCB design rules (continued)
Dimension Recommended values
Stencil opening
Stencil thickness
Pad trace width
0.400 mm
Between 0.100 mm and 0.125 mm
0.120 mm
TFBGA100 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 70. TFBGA100 - 8 x 8 mm, low-profile quad flat package top view example
Product
identification
(1)
STM32G474
VEH6
Revision code
A
Date code
Y WW
Pin 1
identification
MS51946V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12288 Rev 5
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232
Package information
STM32G474xB STM32G474xC STM32G474xE
6.7
LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 71. LQFP100 - outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
75
C
D
D1
D3
L
L1
51
50
76
100
26
PIN 1
IDENTIFICATION
25
e
1
1L_ME_V5
1. Drawing is not to scale.
Table 119. LQPF100 - mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
0.6299
0.5512
0.4724
D1
D3
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Package information
Table 119. LQPF100 - mechanical data (continued)
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
E
E1
E3
e
15.800
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
16.200
0.6220
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.6378
13.800
14.200
0.5433
0.5591
-
-
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
-
0.0°
-
7.0°
0.080
7.0°
0.0031
ccc
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 72. LQFP100 - recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
DS12288 Rev 5
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232
Package information
STM32G474xB STM32G474xC STM32G474xE
LQFP100 device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 73. LQFP100 top view example
Product
identification
(1)
STM32G474
VET6
Revision code
R
Date code
Y WW
Pin 1
identification
MS51942V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
222/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Package information
6.8
LQFP128 package information
LQFP128 is a 128-pin, 14 x 14 mm low-profile quad flat package.
Figure 74. LQFP128 - outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
L
k
D
L1
D1
D3
96
65
64
97
128
33
PIN 1
IDENTIFICATION
1
32
e
TC_ME_V1
1. Drawing is not to scale.
Table 120. LQFP128 - mechanical data
Millimeters
Inches(1)
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
-
-
1.600
0.150
1.450
0.230
-
-
0.0630
0.0059
0.0571
0.0091
0.050
1.350
0.130
-
0.0020
0.0531
0.0051
-
1.400
0.180
0.0551
0.0071
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Package information
Symbol
STM32G474xB STM32G474xC STM32G474xE
Table 120. LQFP128 - mechanical data (continued)
Millimeters
Typ.
Inches(1)
Min.
Max.
Min.
Typ.
Max.
c
D
0.090
-
0.200
0.0035
-
0.0079
15.800
16.000
14.000
12.400
16.000
14.000
12.400
0.400
0.600
1.000
3.5°
16.200
0.6220
0.6299
0.5512
0.4882
0.6299
0.5512
0.4882
0.0157
0.0236
0.0394
3.5°
0.6378
D1
D3
E
13.800
14.200
0.5433
0.5591
-
-
-
-
15.800
16.200
0.6220
0.6378
E1
E3
e
13.800
14.200
0.5433
0.5591
-
-
-
-
-
-
0.750
-
-
-
0.0295
-
L
0.450
0.0177
L1
k
-
0°
-
-
0°
-
7°
7°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 75. LQFP128 - recommended footprint
16
14
12.4
96
65
64
97
14
12.4
16
0.18
128
33
1
32
0.4
TC_LQFP128_FP_V1
Dimensions are expressed in millimeters.
224/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
LQFP128 device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 76. LQFP128 top view example
Product
identification
(1)
STM32G474
QET6
Revision code
B
Date code
Y WW
Pin 1
identification
MS51947V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12288 Rev 5
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232
Package information
STM32G474xB STM32G474xC STM32G474xE
6.9
UFBGA121 package information
UFBGA121 is a 121 balls, 6 x 6 mm, 0.5 mm pitch, fine pitch, square ball grid array
package.
Figure 77. UFBGA121 - outline
SEATING
PLANE
C
A2
A4
A
A1
SIDE VIEW
E
E1
F
e
A
F
L
K
J
H
G
F
E
D
C
B
A
D1
D
e
1
2
3
4
5
6
7
8
9 10 11
b (121 BALLS)
A1 INDEX CORNER AREA
eee
fff
C
C
A
B
BOTTOM VIEW
B0CU_UFBGA121_ME_V1
1. Drawing is not to scale.
2. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
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Package information
inches(1)
Table 121. UFBGA121 - mechanical data
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
A(2)
A1
A2
A4
b(3)
D
-
-
0.60
0.11
-
-
-
0.0236
-
-
-
-
0.0043
-
0.13
0.32
0.29
6.00
5.00
6.00
5.00
0.50
0.50
-
-
0.0051
0.0126
0.0114
0.2362
0.1969
0.2362
0.1969
0.0197
0.0197
-
-
-
-
-
-
0.24
0.34
6.15
-
0.0094
0.0134
5.85
0.2303
0.2421
D1
E
-
-
-
5.85
6.15
-
0.2303
0.2421
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
-
ddd
eee(4)
fff(5)
0.08
0.15
0.05
0.0031
0.0059
0.0020
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. - UFBGA stands for Ultra-Thin Profile Fine Pitch Ball Grid Array.
- Ultra Thin profile: 0.50 < A ≤ 0.65mm / Fine pitch: e < 1.00mm pitch.
- The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A Max = A1 Typ + A2 Typ + A4 Typ + √ (A1²+A2²+A4² tolerance values)
3. The typical balls diameters before mounting is 0.20 mm
4. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect
to datum A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this
tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datumC of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each
ball must lie simultaneously in both tolerance zones.
DS12288 Rev 5
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232
Package information
STM32G474xB STM32G474xC STM32G474xE
Figure 78. UFBGA121 - recommended footprint
Dpad
Dsm
Table 122. UFBGA121 - recommended PCB design rules
Dimension
Recommended values
Pitch
Dpad
Dsm
0.5 mm
0,225 mm
0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
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DS12288 Rev 5
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Package information
6.10
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ ((V
– V ) × I ),
I/O
OL
OL
DDIOx OH OH
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 123. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP128 - 14 × 14 mm
43.0
46.2
46.8
47.9
55.2
30.8
TBD
26.8
45
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm
Thermal resistance junction-ambient
LQFP80 - 12 × 12 mm
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
ΘJA
°C/W
Thermal resistance junction-ambient
TFBGA100 - 8 × 8 mm
Thermal resistance junction-ambient
UFBGA121 - 6 × 6 mm
Thermal resistance junction-ambient
UFQFPN48 - 7 × 7 mm
Thermal resistance junction-ambient
WLCSP81 - 4.02 X 4.27 mm
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Package information
STM32G474xB STM32G474xC STM32G474xE
Table 123. Package thermal characteristics (continued)
Symbol
Parameter
Value
Unit
Thermal resistance junction-case
LQFP128 - 14 × 14 mm
7.0
Thermal resistance junction-case
LQFP100 - 14 × 14 mm
8.3
8.2
8.0
9.6
13
Thermal resistance junction-case
LQFP80 - 12 × 12 mm
Thermal resistance junction-case
LQFP64 - 10 × 10 mm
Thermal resistance junction-case
LQFP48 - 7 × 7 mm
ΘJC
°C/W
Thermal resistance junction-case
TFBGA100 - 8 × 8 mm
Thermal resistance junction-ambient
UFBGA121 - 6 × 6 mm
TBD
Thermal resistance junction-case
UFQFPN48 - 7 × 7 mm
2(1)
7.5
Thermal resistance junction-case
WLCSP81 - 4.02 X 4.27 mm
1.46
19.9
22.9
22.3
21.8
24.3
13.42
TBD
11
Thermal resistance junction-board
LQFP128 - 14 × 14 mm
Thermal resistance junction-board
LQFP100 - 14 × 14 mm
Thermal resistance junction-board
LQFP80 - 12 × 12 mm
Thermal resistance junction-board
LQFP64 - 10 × 10 mm
Thermal resistance junction-board
LQFP48 - 7 × 7 mm
ΘJB
°C/W
Thermal resistance junction-board
TFBGA100 - 8 × 8 mm
Thermal resistance junction-ambient
UFBGA121 - 6 × 6 mm
Thermal resistance junction-board
UFQFPN48 - 7 × 7 mm
Thermal resistance junction-board
WLCSP81 - 4.02 X 4.27 mm
27.45
1. Thermal resistance junction-case where the case is the bottom thermal pad on the UFQFPN package.
6.10.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
230/236
DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Package information
6.10.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 7: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32G474xE at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
50 mA × 3.5 V= 175 mW
INTmax =
20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax =
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
175 272 = 447 mW
+
Dmax =
Using the values obtained in T
is calculated as follows:
Jmax
–
T
For LQFP100, 42 °C/W
= 82 °C + (42 °C/W × 447 mW) = 82 °C + 18.774 °C = 100.774 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Section 7:
J
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 7: Ordering information).
Note:
With this given P
we can find the TAmax allowed for a given device temperature range
Dmax
(order code suffix 6 or 7).
Suffix 6: T
Suffix 3: T
= T
= T
- (42°C/W × 447 mW) = 105-18.774 = 86.226 °C
Amax
Amax
Jmax
Jmax
- (42°C/W × 447 mW) = 130-18.774 = 111.226 °C
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
DS12288 Rev 5
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232
Package information
STM32G474xB STM32G474xC STM32G474xE
Assuming the following application conditions:
Maximum ambient temperature T = 100 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
20 mA × 3.5 V= 70 mW
INTmax =
× 8 mA × 0.4 V = 64 mW
IOmax = 20
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
70 64 = 134 mW
Dmax =
+
Thus: P
= 134 mW
Dmax
Using the values obtained in T
is calculated as follows:
Jmax
–
T
For LQFP100, 42 °C/W
= 100 °C + (42 °C/W × 134 mW) = 100 °C + 5.628 °C = 105.628 °C
Jmax
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 7: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
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Ordering information
7
Ordering information
Table 124. Ordering information
STM32 G 474
Example:
V
E
T
6
x
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
G = General-purpose
Sub-family
474 = STM32G474xB/xC/xE
Pin count
C = 48 pins
R = 64 pins
M = 80 pins, 81 pins
V = 100 pins
P = 121 pins
Q = 128 pins
Code size
B = 128 Kbyte
C = 256 Kbyte
E = 512 Kbyte
Package
H = TFBGA
I = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, - 40 to 85 °C (105 °C junction)
3 = Industrial temperature range, - 40 to 125 °C (130 °C junction)
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, contact the nearest ST sales office.
DS12288 Rev 5
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233
Revision history
STM32G474xB STM32G474xC STM32G474xE
8
Revision history
Table 125. Document revision history
Changes
Date
Revision
15-May-2019
1
Initial release.
Updated:
– Section 2: Description, Section 3.5: Embedded SRAM,
– Table 2: STM32G474xB/xC/xE features and peripheral counts, Table 17: General
operating conditions, Table 35: Peripheral current consumption, Table 66: ADC
characteristics, Table 67: Maximum ADC RAIN, Table 89: SPI characteristics,
Table 123: Package thermal characteristics, Table 124: Ordering information
01-Oct-2019
2
Added: Table 71: ADC accuracy (Multiple ADCs operation) - limited test conditions 1,
Table 73: ADC accuracy (Multiple ADCs operation) - limited test conditions 3,
Table 73: ADC accuracy (Multiple ADCs operation) - limited test conditions 3
Updated:
– Section 2: Description,
– Table 2: STM32G474xB/xC/xE features and peripheral counts,
– Table 12: STM32G474xB/xC/xE pin definition
– Table 124: Ordering information
– Added:
24-Apr-2020
3
– Section 4.9: UFBGA121 pinout description,
– Section 6.9: UFBGA121 package information:
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DS12288 Rev 5
STM32G474xB STM32G474xC STM32G474xE
Revision history
Table 125. Document revision history (continued)
Changes
Date
Revision
Updated:
– Table 2: STM32G474xB/xC/xE features and peripheral counts,
– Table 36: Low-power mode wakeup timings
– Section 3.5: Embedded SRAM
Deleted:
03-Jun-2020
4
– Table 23: Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single bank, ART disable
– Table 24: Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART disable
– Table 27: Typical current consumption in Run and Low-power run modes, with
different codes running from Flash, ART disable
Updated:
– Table 1: Device summary
– Section 3.18: Analog-to-digital converter (ADC)
– Table 2: STM32G474xB/xC/xE features and peripheral counts
– Table 21: Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch
OFF)
– Table 22: Current consumption in Run and Low-power run modes, code with data
processing running from Flash in dual bank, ART enable (Cache ON Prefetch
OFF)
– Table 23: Current consumption in Run and Low-power run modes, code with data
processing running from SRAM1
– Table 28: Current consumption in Sleep and Low-power sleep mode Flash ON
– Table 29: Current consumption in low-power sleep modes, Flash in power-down
– Table 30: Current consumption in Stop 1 mode
– Table 31: Current consumption in Stop 0 mode
– Table 32: Current consumption in Standby mode
– Table 51: ESD absolute maximum ratings
– Table 76: DAC 15MSPS characteristics
– Table 79: COMP characteristics
23-Oct-2020
5
– Table 80: OPAMP characteristics
– Table 84: TIMx characteristics
– Table 89: SPI characteristics
– Table 90: I2S characteristics
– Table 109: QUADSPI characteristics in DDR mode
– Table 121: UFBGA121 - mechanical data
– Table 122: UFBGA121 - recommended PCB design rules
– Table 123: Package thermal characteristics
– Table 124: Ordering information
– Figure 77: UFBGA121 - outline
– Figure 78: UFBGA121 - recommended footprint
Added:
– Figure 75: LQFP128 - recommended footprint
DS12288 Rev 5
235/236
235
STM32G474xB STM32G474xC STM32G474xE
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236/236
DS12288 Rev 5
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