STM32H723VGI6TR [STMICROELECTRONICS]
32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces;
| 型号： | STM32H723VGI6TR |
| 厂家： | 
ST |
| 描述： | 32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces |
| 文件： | 总227页 (文件大小：3021K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32H723VE STM32H723VG
STM32H723ZE STM32H723ZG
32-bit Arm Cortex -M7 550 MHz MCU, up to 1 MB Flash memory,
®
®
564 KB RAM, 35 comms peripherals and analog interfaces
Datasheet - production data
Features
Core
®
®
• 32-bit Arm Cortex -M7 CPU with DP-FPU, L1
cache: 32-Kbyte data cache and 32-Kbyte
instruction cache allowing 0-wait state
LQFP144
(20x20 mm)
LQFP100
(14x14 mm)
FBGA
FBGA
execution from embedded Flash memory and
external memories, frequency up to 550 MHz,
MPU, 1177 DMIPS/2.14 DMIPS/MHz
TFBGA100
(8x8 mm)
UFBGA144
(7x7 mm)
(Dhrystone 2.1), and DSP instructions
Memories
Clock, reset and supply management
• 1.62 V to 3.6 V application supply and I/O
• POR, PDR, PVD and BOR
• Up to 1 Mbyte of embedded Flash memory with
ECC
• SRAM: total 564 Kbytes all with ECC, including
128 Kbytes of data TCM RAM for critical real-
time data + 432 Kbytes of system RAM (up to
256 Kbytes can remap on instruction TCM
RAM for critical real time instructions) +
4 Kbytes of backup SRAM (available in the
lowest-power modes)
• Dedicated USB power
• Embedded LDO regulator
• Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-50 MHz HSE,
• Flexible external memory controller with up to
16-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
32.768 kHz LSE
Low power
• Sleep, Stop and Standby modes
• 2 x Octo-SPI interface with XiP
• 2 x SD/SDIO/MMC interface
• Bootloader
• V
supply for RTC, 32×32-bit backup
registers
BAT
Analog
Graphics
• 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to
18 channels and 7.2 MSPS in double-
interleaved mode
• Chrom-ART Accelerator graphical hardware
accelerator enabling enhanced graphical user
interface to reduce CPU load
• 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12
• LCD-TFT controller supporting up to XGA
channels
resolution
• 2 x comparators
• 2 x operational amplifier GBW = 8 MHz
• 2× 12-bit D/A converters
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• SWPMI single-wire protocol master I/F
Digital filters for sigma delta modulator
(DFSDM)
• MDIO slave interface
• 8 channels/4 filters
Mathematical acceleration
4 DMA controllers to offload the CPU
• 1 × MDMA with linked list support
• CORDIC for trigonometric functions
acceleration
• FMAC: Filter mathematical accelerator
Digital temperature sensor
True random number generator
CRC calculation unit
• 2 × dual-port DMAs with FIFO
• 1 × basic DMA with request router capabilities
24 timers
• Seventeen 16-bit (including 5 x low power
16-bit timer available in stop mode) and four
32-bit timers, each with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
RTC with sub-second accuracy and
hardware calendar
• 2x watchdogs, 1x SysTick timer
ROP, PC-ROP, tamper detection
96-bit unique ID
Debug mode
• SWD and JTAG interfaces
• 2-Kbyte embedded trace buffer
All packages are ECOPACK2 compliant
Up to 114 I/O ports with interrupt
capability
Up to 35 communication interfaces
• Up to 5 × I2C FM+ interfaces
(SMBus/PMBus™)
• Up to 5 USARTs/5 UARTs (ISO7816 interface,
LIN, IrDA, modem control) and 1 x LPUART
• Up to 6 SPIs with 4 with muxed duplex I2S for
audio class accuracy via internal audio PLL or
external clock and up to 5 x SPI (from 5 x
USART when configured in synchronous
mode)
• 2x SAI (serial audio interface)
• 1× FD/TT-CAN and 2xFD-CAN
• 8- to 14-bit camera interface
• 16-bit parallel slave synchronous interface
• SPDIF-IN interface
• HDMI-CEC
• Ethernet MAC interface with DMA controller
• USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip FS PHY and ULPI for external
HS PHY
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
3.2
3.3
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.1
3.3.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Error code correction (ECC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.4
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CORDIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.6
3.7
Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FMAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.1
3.7.2
3.7.3
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8
3.9
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9.1
3.9.2
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.11 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.12 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.13 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 31
3.15 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 31
3.16 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 31
3.17 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18 Octo-SPI memory interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 32
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3.19 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.20 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.21 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.23 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.25 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.26 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 36
3.27 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 PSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.30 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.31 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.31.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.31.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.31.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.31.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 43
3.31.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.31.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.31.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.32 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 44
3.33 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.34 Universal synchronous/asynchronous receiver transmitter (USART) . . . 45
3.35 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 46
3.36 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 47
3.37 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.38 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.39 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 48
3.40 Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . 49
3.41 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 49
3.42 Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 49
3.43 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 50
3.44 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 50
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3.45 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.46 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pinouts, pin descriptions and alternate functions . . . . . . . . . . . . . . . . 53
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4
5
6
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 93
Embedded reset and power control block characteristics . . . . . . . . . . . 94
Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . . 95
Embedded USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . 96
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical and maximum current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
I/O system current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
6.3.8
6.3.9
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 105
High-speed external user clock generated from an external source . . . . . . . . .105
Low-speed external user clock generated from an external source . . . . . . . . . .106
High-speed external clock generated from a crystal/ceramic resonator. . . . . . .107
Low-speed external clock generated from a crystal/ceramic resonator . . . . . . .108
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 109
48 MHz high-speed internal RC oscillator (HSI48). . . . . . . . . . . . . . . . . . . . . . .109
64 MHz high-speed internal RC oscillator (HSI). . . . . . . . . . . . . . . . . . . . . . . . .110
4 MHz low-power internal RC oscillator (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . .111
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Low-speed internal (LSI) RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.11
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . .117
Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . .117
Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 118
Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Static latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Functional susceptibility to I/O current injection . . . . . . . . . . . . . . . . . . . . . . . . .119
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
General input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Output driving current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Output voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Output buffer timing characteristics (HSLV option disabled) . . . . . . . . . . . . . . .124
Output buffer timing characteristics (HSLV option enabled). . . . . . . . . . . . . . . .126
Analog switch between ports Pxy_C and Pxy . . . . . . . . . . . . . . . . . . . . . . . . . .127
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.18 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Asynchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Synchronous waveforms and timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
NAND controller waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
SDRAM waveforms and timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6.3.19 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.20 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.21 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
6.3.22 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.23 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.24 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.25 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 175
6.3.26 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 176
6.3.27 Temperature and V
monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
BAT
6.3.28 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3.29 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3.30 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 178
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6.3.31 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 181
6.3.32 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 184
6.3.33 Parallel synchronous slave interface (PSSI) characteristics . . . . . . . . 185
6.3.34 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 186
6.3.35 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
6.3.36 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
6.3.37 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
USART interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
SPI interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
I2S Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
MDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . . . . . . . .200
USB OTG_FS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
USB OTG_HS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Ethernet interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1
7.2
7.3
7.4
7.5
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Device marking for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Device marking for TFBGA100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Device marking for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Device marking for UFBGA144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.5.1
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
DS13313 Rev 2
7/227
7
List of tables
STM32H723xE/G
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
STM32H723xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System versus domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STM32H723 pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
STM32H723 pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Supply voltage and maximum temperature configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 92
VCAP operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 93
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical and maximum current consumption in Run mode,
code with data processing running from ITCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical and maximum current consumption in Run mode,
code with data processing running from Flash memory, cache OFF. . . . . . . . . . . . . . . . 100
Typical consumption in Run mode and corresponding performance
Table 21.
Table 22.
Table 23.
versus code position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Typical current consumption in Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Typical current consumption in Stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical current consumption in Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 102
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
PLL1 characteristics (wide VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
PLL1 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PLL2 and PLL3 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . 114
PLL2 and PLL3 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . 115
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
8/227
DS13313 Rev 2
STM32H723xE/G
List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Output voltage characteristics for all I/Os except PC13, PC14 and PC15 . . . . . . . . . . . . 122
Output voltage characteristics for PC13, PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . 123
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Pxy_C and Pxy analog switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 130
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 130
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 132
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 132
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 134
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 135
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 141
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . 153
Delay Block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Minimum sampling time vs RAIN (16-bit ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16-bit ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Minimum sampling time vs RAIN (12-bit ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12-bit ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
BAT
BAT
Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
DS13313 Rev 2
9/227
10
List of tables
STM32H723xE/G
Table 97.
Table 98.
Table 99.
DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 101. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 103. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 104. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 105. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 106. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 107. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
2
Table 108. I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 109. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 110. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 111. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 200
Table 112. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V. . . . . . . . . . . . . . . 201
Table 113. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 114. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 115. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 116. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 117. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 118. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 119. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 120. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 121. TFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 122. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 215
Table 123. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 124. UFBGA144 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 125. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 221
Table 126. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 127. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
10/227
DS13313 Rev 2
STM32H723xE/G
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32H723xE/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32H723xE/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 10. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 12. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
EXT
Figure 13. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 14. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 15. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 17. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 18. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 19. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 129
Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 131
Figure 21. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 22. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 23. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 24. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 25. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 26. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 27. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 28. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 145
Figure 29. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 146
Figure 30. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 31. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 32. OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 33. OCTOSPI DTR mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 34. OCTOSPI Hyperbus clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 35. OCTOSPI Hyperbus read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 36. OCTOSPI Hyperbus write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 37. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 38. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 39. Power supply and reference decoupling (V
Figure 40. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 163
). . . . . . . . . . . . . . . . 163
REF+
DDA
connected to V
REF+
DDA
Figure 41. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 42. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 43. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 44. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 45. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 46. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 47. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 48. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
DS13313 Rev 2
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12
List of figures
STM32H723xE/G
(1)
Figure 49. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
(1)
Figure 50. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
2
(1)
Figure 51. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
2
(1)
Figure 52. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 53. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 54. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 55. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 56. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 57. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 58. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 59. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 60. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 61. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 62. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 63. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 64. SWD timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 65. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 66. LQFP100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 67. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 68. TFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 69. TFBGA100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 70. TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 71. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 72. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 73. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 74. UFBGA144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 75. UFBGA144 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 76. UFBGA144 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12/227
DS13313 Rev 2
STM32H723xE/G
Introduction
1
Introduction
This document provides information on STM32H723xE/G microcontrollers, such as
description, functional overview, pin assignment and definition, packaging, and ordering
information.
This document should be read in conjunction with the STM32H723xE/G reference manual
(RM0468), available from the STMicroelectronics website www.st.com.
®(a)
®
®
For information on the Arm
Cortex -M7 core, refer to the Cortex -M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS13313 Rev 2
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52
Description
STM32H723xE/G
2
Description
®
®
STM32H723xE/G devices are based on the high-performance Arm Cortex -M7 32-bit
RISC core operating at up to 550 MHz. The Cortex® -M7 core features a floating point unit
®
(FPU) which supports Arm double-precision (IEEE 754 compliant) and single-precision
data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of
instruction cache and 32 Kbytes of data cache. STM32H723xE/G devices support a full set
of DSP instructions and a memory protection unit (MPU) to enhance application security.
STM32H723xE/G devices incorporate high-speed embedded memories with up to 1 Mbyte
of Flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared
between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI,
128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive
range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit
multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external
memory access. To improve application robustness, all memories feature error code
correction (one error correction, two error detections).
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC co-processor for trigonometric functions and FMAC unit for filter functions). All the
devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low power
comparators, a low-power RTC, 4 general-purpose 32-bit timers, 12 general-purpose 16-bit
timers including two PWM timers for motor control, five low-power timers, a true random
number generator (RNG). The devices support four digital filters for external sigma-delta
modulators (DFSDM). They also feature standard and advanced communication interfaces.
•
Standard peripherals
2
–
–
–
Five I Cs
Five USARTs, five UARTs and one LPUART
2
2
Six SPIs, four I Ss in Half-duplex mode. To achieve audio class accuracy, the I S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization. (Note that the five USARTs also provide SPI slave
capability.)
–
–
–
–
–
–
–
–
–
–
Two SAI serial audio interfaces
One SPDIFRX interface with four inputs
One SWPMI (Single Wire Protocol Master Interface)
Management Data Input/Output (MDIO) slaves
Two SDMMC interfaces
A USB OTG high-speed interface with full-speed capability (with the ULPI)
Two FDCANs plus one TT-FDCAN interface
An Ethernet interface
Chrom-ART Accelerator
HDMI-CEC
14/227
DS13313 Rev 2
STM32H723xE/G
Description
•
Advanced peripherals including
–
A flexible memory control (FMC) interface
Two Octo-SPI memory interfaces
A camera interface for CMOS sensors
An LCD-TFT display controller
–
–
–
Refer to Table 1: STM32H723xE/G features and peripheral counts for the list of peripherals
available on each part number.
STM32H723xE/G devices operate in the –40 to +85 °C ambient temperature range from a
1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an
external power supervisor (see Section 3.7.2: Power supply supervisor) and connecting the
PDR_ON pin to V . Otherwise the supply voltage must stay above 1.71 V with the
SS
embedded power voltage detector enabled.
Dedicated supply inputs for USB are available to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H723xE/G devices are offered in several packages ranging from 100 to 144
pins/balls. The set of included peripherals changes with the device chosen.
These features make STM32H723xE/G microcontrollers suitable for a wide range of
applications:
•
•
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile applications, Internet of Things
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
DS13313 Rev 2
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52
Description
STM32H723xE/G
Figure 1. STM32H723xE/G block diagram
D[7:0],DP, DM, STP,
D123DIR,NXT,ULPI:CK
D0DIR, , D[7:0], DIR,
MII / RMII
MDIO
as AF
To APB1-2
peripherals
CMD, CKas AF ID, VBUS
AHB1
(275MHz)
D-TCM
64KB
D-TCM
64KB
PHY
OTG_HS
I-TCM 64KB
ETHER
MAC
DMA1 DMA2
8 Stream 8 Stream
SDMMC2
FIFO
Shared AXI
I-TCM 192KB
128 KB AXI
SRAM
AXI/AHB12 (275MHz)
AHBP
DMA/
FIFO
DMA/
FIFO
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWDIO, JTDO
Arm CPU
Cortex-M7
550 MHz
FIFOs
FIFOs
JTAG/SW
ETM
AXIM
1 MB FLASH
FMC
TRACECLK
TRACED[3:0]
32-bit AHB BUS-MATRIX
I-Cache
32KB
D-Cache
32KB
DMA
Mux1
FMC_signal
AHBS
SRAM1 SRAM2
16 KB 16 KB
OCTOSPI1
signals
16 Streams
FIFO
MDMA
RNG
CORDIC
FMAC
ADC1
Up to 20 analog inputs Most
are common to ADC1 & 2
ADC2
CHROM-ART
(DMA2D)
FIFO
FIFO
AHB/APB
32b
16b
16b
32b
32b
32b
TIM2
TIM3
CH[4;1], ETR as AF
CH[4;1], ETR as AF
CH[4;1], ETR as AF
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
LCD-TFT
OCTOSPI2
signals
TIM4
WWDG
AHB/APB
DLYBOS1-2
TIM5
CH[4;1], ETR as AF
DLYBSD1
TIM23
CH[4;1], ETR as AF
CH[4;1], ETR as AF
CH[2;1] as AF
TIM6
TIM7
16b
16b
D[7:0], D123DIR, D0DIR,
CMD, CKas AF
TIM24
FIFO
SDMMC1
AXI/AHB34 (275MHz)
AHB2 (275MHz)
16b
TIM12
SWPMI
DLYBSD2
DCMI
TIM13
CH1 as AF
CH1 as AF
16b
16b
TIM14
HSYNC, VSYNC, PIXCLK, D[13:0]
PDCK, DE, RDY, D[15:0]
AHB/APB
PSSI
USART2
USART3
UART4
UART5
UART7
UART8
SPI2/I2S2
SPI3/I2S3
RX, TX, CK, CTS, RTS, DE as A
RX, TX, CK, CTS, RTS, DE as A
RX, TX, CTS, RTS, DE as AF
RX, TX, CTS, RTS, DE as AF
CKOUT, DATIN[7:0], CKIN[7:0]
DFSDM
SAI1
SD_[A;B], SCK_[A;B], FS_[A;B],
MCLK_[A;B], D[3:1], CK[2:1] as AF
RX, TX, CTS, RTS, DE as AF
RX, TX, CTS, RTS, DE as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS as AF
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
MOSI, MISO, SCK, NSS as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI1/I2S1
UART9
DMA
I2C5/SMBUS
USBCR
Mux2
RX, TX, CTS, RTS, DE as AF
AHB4
DAP
BDMA
USART10
RX, TX, CK, CTS, RTS, DE as AF
RX, TX, CK, CTS, RTS, DE as AF
RX, TX, CK, CTS, RTS, DE as AF
MDC, MDIO as AF
MDIOS
USART6
USART1
TX, RX, RXFD_MODE,
RAM
I/F
32-bit AHB BUS-MATRIX
16 KB SRAM
TT-FDCAN1
FDCAN2
TXFD_MODE as AF
TX, RX, RXFD_MODE,
TXFD_MODE as AF
CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2
as AF
TX, RX, RXFD_MODE,
TIM1/PWM
16b
FDCAN3
TXFD_MODE as AF
HSEM
CRC
CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2
as AF
4 KB BKP
SPDIFRX1
HDMI-CEC
DAC
IN[1:4] as AF
TIM8/PWM
16b
RAM
CEC as AF
Up to 17 analog inputs
Some common to ADC1 and 2
ADC3
OUT1, OUT2 as AF
PA..H[15:0]
PJ,PK[11:0]
GPIO PORTA.. H
LPTIM1
IN1, IN2, ETR, OUT as AF
16b
GPIO PORTJ,K
RCC
Reset &
control
OPAMP1
OPAMP2
VINM, VINP, VOUT as AF
VINM, VINP, VOUT as AF
@VDD
SD_[A;B], SCK_[A;B], FS_[A;B],
MCLK_[A;B], D[3:1], CK[2:1] as AF
SAI4
VCORE
BBgen + POWER MNGT
VDD
VSS
VCAP, VDDLDO
COMPx_INP, COMPx_INM,
Voltage
regulator
3.3 to 1.2V
COMP1&2
COMPx_OUT as AF
LPTIM5
16b
OUT as AF
OUT as AF
AHB/APB
VREF
SYSCFG
EXTI WKUP
IWDG
VBAT
LPTIM4
16b
@VSW
OSC32_IN
OSC32_OUT
LPTIM3
16b
XTAL 32 kHz
OUT as AF
RTC
Backup registers
SCL, SDA, SMBA as AF
I2C4
@VDD
TS, TAMP1, TAMP3,
OUT, REFIN
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI6/I2S6
AWU
HSI
HSI RC
Temperature
sensor
RX, TX, CK, CTS, RTS as AF
LPUART1
HSI48
HSI48 RC
CSI RC
LSI RC
CSI
LSI
LPTIM2
16b
IN1, IN2, ETR, OUT as AF
@VDD
OSC_IN
OSC_OUT
XTAL OSC
4- 48 MHz
PLL1+PLL2+PLL3
@VDD
SUPPLY SUPERVISION
POR/PDR/BOR
POR
reset
Int
VDDA, VSSA
NRESET
WKUP[1;2;4;6]
PVD
MSv52561V3
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DS13313 Rev 2
STM32H723xE/G
Description
Table 1. STM32H723xE/G features and peripheral counts
STM32H723 STM32H723 STM32H723 STM32H723
Peripherals
VGH/VEH
VGT/VET
ZGT/ZET
ZGI/ZEI
Flash memory (Kbytes)(1)
SRAM mapped onto AXI bus
1024 / 512
1024 / 512
1024 / 512
1024 / 512
128
16
16
16
192
64
128
4
SRAM1 (D2 domain)
SRAM2 (D2 domain)
SRAM4 (D3 domain)
SRAM (Kbytes)
RAM shared between ITCM and AXI (Kbytes)
ITCM RAM (instruction)
TCM RAM (Kbytes)
DTCM RAM (data)
Backup SRAM (Kbytes)
Interface
1
NOR Flash
memory/RAM
controller
-
-
yes
yes
yes
yes
Multiplexed I/O
FMC
NOR Flash
memory
yes
yes
16-bit NAND
yes
-
yes
-
yes
yes
yes
yes
Flash memory
16-bit SDRAM
controller
GPIO
80
80
112
2
114
2
Octo-SPI interface
OTFDEC
CORDIC
FMAC
2(2)
2(2)
no
yes
yes
General purpose 32 bits
General purpose 16 bits
2
2
2
2
10
10
10
10
Advanced control
(PWM)
2
2
2
2
Timers
Basic
2
5
1
2
5
1
2
5
1
2
5
1
Low-power
RTC
Window watchdog /
2
4
2
4
2
4
2
4
independent watchdog
Wakeup pins
DS13313 Rev 2
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52
Description
STM32H723xE/G
Table 1. STM32H723xE/G features and peripheral counts (continued)
STM32H723 STM32H723 STM32H723 STM32H723
Peripherals
VGH/VEH
VGT/VET
ZGT/ZET
ZGI/ZEI
Tamper pins
2
2
2
2
Random number generator
Cryptographic accelerator
yes
no
SPI / I2S
5/4
5
5/4
5
6/4
5
6/4
5
I2C
USART/UART/
LPUART
5/5/1
2/1(3)
5/5/1
2/1(3)
5/5/1
2/1
5/5/1
2/1
SAI/PDM
SPDIFRX
1
1
1
1
2
Communication
interfaces
HDMI-CEC
SWPMI
MDIO
SDMMC
FDCAN/TT-FDCAN
USB [OTG_HS(ULPI)/FS(PHY)]
Ethernet [MII/RMII]
2/1
2/1
2/1
2/1
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
1 [1/1]
Camera interface/PSSI
LCD-TFT
yes
yes
yes
yes
yes
Chrom-ART Accelerator (DMA2D)
yes
2
Number of ADCs
Number of direct
channelsADC1/ADC2
2/2
3/2
9/8
0
0
2/2
4/3
16-bit ADCs
12-bit ADCs
Number of fast channels
ADC1/ADC2
3/2
4/3
Number of slow channels
ADC1/ADC2
11/10
12/11
12/11
Number of ADCs
1
Number of direct channels
Number of fast channels
Number of slow channels
Present in IC
2
6
9
2
2
0
2
6
4
2
6
9
yes
2
Number of channels
Comparators
12-bit DAC
DFSDM
2
Operational amplifiers
Present in IC
2
yes
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Description
Table 1. STM32H723xE/G features and peripheral counts (continued)
STM32H723 STM32H723 STM32H723 STM32H723
Peripherals
VGH/VEH
VGT/VET
ZGT/ZET
ZGI/ZEI
Maximum CPU frequency
USB separate supply pad
USB internal regulator
LDO
550 MHz
yes
-
-
-
yes
-
yes
-
yes
SMPS step-down converter
-
-
-
-
1.62 to
3.6 V
1.71 to
3.6 V
Operating voltage
1.62 to 3.6 V
Ambient temperature
Junction temperature
-40°C to +85°C
-40°C to +125°C
Operating
temperatures
Package
TFBGA100
LQFP100
LQFP144
UFBGA144
1. STM32H723xGy products have 1024 Kbytes of Flash memory, whereas STM32H723xEy products have 512 Kbytes
2. The two Octo-SPI/Quad-SPI interfaces are available only in Muxed mode.
3. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7: STM32H723 pin
and ball descriptions.
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52
Functional overview
STM32H723xE/G
3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
®
®
The Arm Cortex -M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
®
The Cortex -M7 processor is a highly efficient high-performance featuring:
•
•
•
•
•
•
Six-stage dual-issue pipeline
Dynamic branch prediction
Harvard architecture with L1 caches (32 Kbytes of I-cache and 32 Kbytes of D-cache)
64-bit AXI interface
64-bit ITCM interface
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
•
AXI Bus interface to optimize Burst transfers
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H723xE/G family.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
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Functional overview
3.3
Memories
3.3.1
Embedded Flash memory
The STM32H723xE/G devices embed up to 1 Mbyte of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•
•
one Flash word (8 words, 32 bytes or 256 bits)
10 ECC bits (single-error correction and double-error detection).
The Flash memory is organized as follows:
•
up to 1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes
(4 K Flash memory words)
•
128 Kbytes of system Flash memory from which the device can boot
2 Kbytes (64 Flash words) of user option bytes for user configuration
•
3.3.2
Embedded SRAM
All devices feature:
•
•
•
•
•
from 128 to 320 Kbytes of AXI-SRAM mapped onto the AXI bus on D1 domain
SRAM1 mapped on D2 domain: 16 Kbytes
SRAM2 mapped on D2 domain: 16 Kbytes
SRAM4 mapped on D3 domain: 16 Kbytes
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses, and
can be retained in Standby or V
mode.
BAT
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the
Cortex®-M7CPU(AHBSAHBP):
–
64 to 256 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
–
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs. As reflected
above, 192 Kbyte of RAM can be used either for AXI SRAM or ITCM, with a 64Kbyte
granularity.
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52
Functional overview
STM32H723xE/G
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•
•
7 ECC bits are added per 32-bit word.
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
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Functional overview
3.4
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
•
•
All Flash address space
All RAM address space: ITCM, DTCM RAMs and SRAMs
The System memory bootloader
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, FDCAN, USB-DFU). Refer to
application note AN2606 “STM32 microcontroller System memory Boot mode” for details.
3.5
CORDIC co-processor (CORDIC)
The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
CORDIC features
•
•
•
•
24-bit CORDIC rotation engine
Circular and Hyperbolic modes
Rotation and Vectoring modes
Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,
Natural logarithm
•
•
•
•
•
•
Programmable precision up to 20-bit
Fast convergence: 4 bits per clock cycle
Supports 16-bit and 32-bit fixed point input and output formats
Low latency AHB slave interface
Results can be read as soon as ready without polling or interrupt
DMA read and write channels
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52
Functional overview
STM32H723xE/G
3.6
Filter mathematical accelerator (FMAC)
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
FMAC features
•
•
•
•
•
16 x 16-bit multiplier
24+2-bit accumulator with addition and subtraction
16-bit input and output data
256 x 16-bit local memory
Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
•
•
•
•
•
Input and output sample buffers can be circular
Buffer “watermark” feature reduces overhead in interrupt mode
Filter functions: FIR, IIR (direct form 1)
AHB slave interface
DMA read and write data channels
3.7
Power supply management
3.7.1
Power supply scheme
STM32H723xE/G power supply voltages are the following:
•
V
pins.
= 1.62 to 3.6 V: external power supply for I/Os, provided externally through V
DD
DD
•
•
V
= 1.62 to 3.6 V: supply voltage for the internal regulator supplying V
DDLDO
CORE
V
= 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
DDA
OPAMP.
•
V
: allows the support of a VDD supply different from 3.3 V while powering the
DD33USB
USB transceiver with 3.3V on V
.
DD33USB
•
•
V
V
= 1.2 to 3.6 V: power supply for the V
domain when V is not present.
BAT
SW DD
: V
supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
CAP
CORE
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register. The
domain is split into the following power domains that can be independently
V
CORE
switch off.
®
–
–
–
D1 domain containing some peripherals and the Cortex -M7 core
D2 domain containing a large part of the peripherals
D3 domain containing some peripherals and the system control
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Functional overview
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
•
When V is below 1 V, other power supplies (V
, V
) must remain below
DD33USB
DD
DDA
V
+ 300 mV.
DD
•
When V is above 1 V, all power supplies are independent.
DD
During the power-down phase, V can temporarily become lower than other supplies only
DD
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
Figure 2. Power-up/power-down sequence
V
3.6
(1)
VDDX
VDD
VBOR0
1
0.3
Power-on
Operating mode
VDDX < VDD + 300 mV
Power-down
time
Invalid supply area
VDDX independent from VDD
MSv47490V1
1. VDDx refers to any power supply among VDDA, VDD33USB
.
3.7.2
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors V power supply and compares it to a fixed threshold.
DD
The devices remain in Reset mode when V is below this threshold,
DD
•
Power-down reset (PDR)
The PDR supervisor monitors V power supply. A reset is generated when V drops
DD
DD
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
Brownout reset (BOR)
•
The BOR supervisor monitors V power supply. Three BOR thresholds (from 2.1 to
DD
2.7 V) can be configured through option bytes. A reset is generated when V drops
DD
below this threshold.
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52
Functional overview
STM32H723xE/G
3.7.3
Voltage regulator
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
•
•
Run mode (VOS0 to VOS3)
–
–
–
–
Scale 0: boosted performance
Scale 1: high performance
Scale 2: medium performance and consumption
Scale 3: optimized performance and low-power consumption
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled. The
peripheral functionality is disabled but wakeup from Stop mode is possible through
GPIO or asynchronous interrupt.
3.8
Low-power strategy
There are several ways to reduce power consumption on STM32H723xE/G:
•
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
•
Save power when the CPU is idle, by selecting among the available low-power modes
according to the user application needs. This allows the best compromise between
short startup time and low power consumption to be achieved, according to the
available wakeup sources.
The devices feature several low-power modes:
•
•
•
•
•
•
CSleep (CPU clock stopped)
CStop (CPU sub-system clock stopped)
DStop (Domain bus matrix clock stopped)
Stop (System clock stopped)
DStandby (Domain powered down)
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
®
the Cortex -Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
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Functional overview
D3 domain power mode
Table 2. System versus domain low-power mode
System power mode
D1 domain power mode
D2 domain power mode
Run
Stop
DRun/DStop/DStandby
DStop/DStandby
DStandby
DRun/DStop/DStandby
DStop/DStandby
DStandby
DRun
DStop
Standby
DStandby
3.9
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), thus the system frequency can be changed without modifying the
baudrate.
3.9.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
Internal oscillators:
–
–
–
–
64 MHz HSI clock
48 MHz RC oscillator
4 MHz CSI clock
32 kHz LSI clock
•
External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
–
LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
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52
Functional overview
STM32H723xE/G
3.9.2
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
•
•
•
•
•
•
•
•
Power-on reset (pwr_por_rst)
Brownout reset
Low level on NRST pin (external reset)
Window watchdog
Independent watchdog
Software reset
Low-power mode security reset
Exit from Standby
3.10
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.11
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
the interconnection of bus masters with bus slaves (see Figure 3).
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DS13313 Rev 2
Figure 3. STM32H723xE/G bus matrix
AHBS
ITCM
CPU
64 Kbyte
Cortex-M7
D$
OR
ITCM
192 Kbyte
I$
Ethernet
MAC
DMA1
DMA2
SDMMC2 USBHS1
32KB 32KB
DTCM
128 Kbyte
SDMMC1 MDMA
DMA2D
LTDC
D1-to-D2 AHB
AXI SRAM
192K byte
SRAM1 16
Kbyte
SRAM2 16
Kbyte
Flash A
Up to 1 Mbyte
AHB1
AHB2
AXI SRAM
128 Kbyte
OCTOSPI1
OCTOSPI2
FMC
APB1
APB2
APB3
AHB3
64-bit AXI bus matrix
32-bit AHB bus matrix
D1 domain
D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D3 AHB
32-bit AHB bus matrix
BDMA
D3 domain
Legend
AHB4
APB4
TCM AHB
32-bit bus
64-bit bus
Bus multiplexer
AXI
APB
SRAM4
16 Kbyte
Master interface
Slave interface
Backup
SRAM
4 Kbyte
MSv65313V1
Functional overview
STM32H723xE/G
3.12
DMA controllers
The devices feature four DMA instances and a DMA request router to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
®
access Cortex -M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
•
•
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
A DMA request multiplexer (DMAMUX)
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing
managing the DMA requests with a high flexibility, maximizing the number of DMA
requests that run concurrently, as well as generating DMA requests from peripheral
output trigger or DMA event.
3.13
Chrom-ART Accelerator (DMA2D)
The Chrom-Art Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation.
It can perform the following operations:
•
•
•
•
•
•
•
•
Filling a part or the whole of a destination image with a specific color
Copying a part or the whole of a source image into a part or the whole of a destination
image
Copying a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
Blending a part and/or two complete source images with different pixel format and copy
the result into a part or the whole of a destination image with a different color format.
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel
with indexed or direct color mode, including block based YCbCr to handle JPEG
decoder output.
•
The DMA2D has its own dedicated memories for CLUTs (color look-up tables).
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automated and are running independently from the CPU or the
DMAs.
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Functional overview
3.14
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 140 maskable interrupt channels plus the 16 interrupt lines
®
of the Cortex -M7 with FPU core.
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.15
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 80 independent event/interrupt lines split as 26 configurable events
and 54 direct events.
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.16
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
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Functional overview
STM32H723xE/G
3.17
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
–
–
–
–
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
•
•
•
•
•
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
3.18
Octo-SPI memory interface (OCTOSPI)
The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal
SPI memories. The STM32H723xE/G embeds two separate Octo-SPI interfaces.
Each OCTOSPI instance supports single/dual/quad/octal SPI formats. multiplexing of
single/dual/quad/octal SPI over the same bus can be achieved using the integrated Octo-
SPI I/O manager (OCTOSPIM).
The OCTOSPI can operate in any of the three following modes:
•
•
Indirect mode: all the operations are performed using the OCTOSPI registers
Status-polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory supporting both read and write operations.
The OCTOSPI supports two frame formats supported by most external serial memories
such as serial PSRAMs, serial NAND and serial NOR Flash memories, Hyper RAMs and
Hyper Flash memories.
Multi chip package (MCP) combining any of the above mentioned memory types can also
be supported.
•
The classical frame format with the command, address, alternate byte, dummy cycles
and data phase
•
The HyperBus™ frame format.
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3.19
Analog-to-digital converters (ADCs)
STM32H723xE/G devices embed three analog-to-digital converters, two of 16-bit resolution,
and the third of 12-bit resolution. The 16-bit resolution ADCs can be configured as 16, 14,
12, 10 or 8 bits. The 12-bit resolution ADC can be configured to 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
•
simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing automatic transfer of ADC
converted values to a destination location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some, or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs can be triggered by any of the TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, TIM23, TIM24, and LPTIM1 timers.
3.20
Temperature sensor
STM32H723xE/G devices embed a temperature sensor that generates a voltage (V ) that
TS
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN17. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 to +125°C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.21
Digital temperature sensor (DTS)
STM32H723xE/G devices embed a sensor that converts the temperature into a square
wave the frequency of which is proportional to the temperature. The PCLK or the LSE clock
can be used as the reference clock for the measurements. A formula given in the product
reference manual allows calculation of the temperature according to the measured
frequency stored in the DTS_DR register.
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STM32H723xE/G
3.22
VBAT operation
The V
power domain contains the RTC, the backup registers and the backup SRAM.
BAT
To optimize battery duration, this power domain is supplied by V when available or by the
DD
voltage applied on VBAT pin (when V supply is not present). V
power is switched
DD
BAT
when the PDR detects that V dropped below the PDR level.
DD
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by V , in which case, the V mode is not functional.
DD
BAT
V
operation is activated when V is not present.
DD
BAT
The V
pin supplies the RTC, the backup registers and the backup SRAM.
BAT
Note:
When the microcontroller is supplied from V
, external interrupts and RTC alarm/events
BAT
do not exit it from V
operation.
BAT
When PDR_ON pin is connected to V (Internal Reset OFF), the V
functionality is no
BAT
SS
more available and V
pin should be connected to VDD.
BAT
3.23
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
•
•
•
•
•
•
•
•
•
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel including DMA underrun error detection
external triggers for conversion
input voltage reference V
or internal VREFBUF reference.
REF+
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
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3.24
Ultra-low-power comparators (COMP)
STM32H723xE/G devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•
•
•
An external I/O
A DAC output channel
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.25
Operational amplifiers (OPAMP)
STM32H723xE/G devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•
•
•
•
•
One positive input connected to DAC
Output connected to internal ADC
Low input bias current down to 1 nA
Low input offset voltage down to 1.5 mV
Gain bandwidth up to 7.3 MHz
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
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STM32H723xE/G
3.26
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
8 multiplexed input digital serial channels:
–
–
–
–
–
configurable SPI interface to connect various SD modulator(s)
configurable Manchester coded 1 wire interface support
PDM (Pulse Density Modulation) microphone input support
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
clock output for SD modulator(s): 0..20 MHz
•
•
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
internal sources: ADC data or memory data streams (DMA)
–
4 digital filter modules with adjustable digital signal processing:
x
–
–
Sinc filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
integrator: oversampling ratio (1..256)
•
•
•
•
up to 24-bit output data resolution, signed output data format
automatic data offset correction (offset stored in register by user)
continuous or single conversion
start-of-conversion triggered by:
–
–
–
–
software trigger
internal timers
external events
start-of-conversion synchronously with first digital filter module (DFSDM0)
•
analog watchdog feature:
–
–
–
–
low value and high value data threshold registers
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
input from final output data or from selected input digital serial channels
continuous monitoring independently from standard conversion
•
•
short circuit detector to detect saturated analog input values (bottom and top range):
–
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
monitoring continuously each input serial channel
break signal generation on analog watchdog event or on short circuit detector event
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Functional overview
•
extremes detector:
storage of minimum and maximum values of final conversion data
refreshed by software
DMA capability to read the final conversion data
–
–
•
•
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
•
Pulse skipper feature to support beamforming applications (delay-line like behavior).
Table 3. DFSDM implementation
DFSDM features
Number of filters
DFSDM1
4
Number of input
transceivers/channels
8
Internal ADC parallel input
Number of external triggers
X
16
Regular channel information in
identification register
X
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STM32H723xE/G
3.27
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
•
•
•
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
•
Supports Continuous mode or Snapshot (a single frame) mode
Capability to automatically crop the image
3.28
PSSI
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
allows the transmitter to send a data valid signal to indicate when the data is valid, and the
receiver to output a flow control signal to indicate when it is ready to sample the data.
The main PSSI features are:
•
•
•
•
Slave mode operation
8- or 16-bit parallel data input or output
8-word (32-byte) FIFO
Data enable (DE) alternate function input and Ready (RDY) alternate function output.
When enabled, these signals can either allow the transmitter to indicate when the data is
valid or, the receiver to indicate when it is ready to sample the data, or both.
The PSSI shares most of its circuitry with the digital camera interface (DCMI). It therefore
cannot be used simultaneously with the DCMI.
3.29
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024 x 768) resolution with the following features:
•
•
•
•
•
•
•
•
2 display layers with dedicated FIFO (64x64-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events
AXI master interface with burst of 16 words
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Functional overview
3.30
True random number generator (RNG)
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG can be used to construct a Non-deterministic Random Bit Generator (NDRBG), as
a NIST SP 800-90B compliant entropy source.
The RNG true random number generator has been tested using German BSI statistical tests
of AIS-31 (T0 to T8), and NIST SP800-90B statistical test suite.
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STM32H723xE/G
3.31
Timers and watchdogs
The devices include two advanced-control timers, twelve general-purpose timers, two basic
timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Max
Max
DMA
request
generation channels
Capture/ Comple-
compare mentary
timer
clock
Timer
type
Counter Counter Prescaler
interface
clock
Timer
resolution
type
factor
output
(MHz)
(MHz)
(1)
Any
Up,
integer
Advanced TIM1,
16-bit
Down, between1
Up/down
Yes
Yes
Yes
No
4
4
4
2
1
2
1
Yes
137.5
137.5
137.5
137.5
137.5
137.5
137.5
275
275
275
275
275
275
275
-control
TIM8
and
65536
Any
integer
Down, between1
TIM2,
TIM5,
TIM23,
TIM24
Up,
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
No
No
No
No
1
Up/down
and
65536
Any
integer
Down, between1
Up,
TIM3,
TIM4
Up/down
and
65536
Any
integer
between1
and
TIM12
Up
65536
General
purpose
Any
integer
between1
and
TIM13,
TIM14
Up
Up
Up
No
65536
Any
integer
between1
and
TIM15
Yes
Yes
65536
Any
integer
between1
and
TIM16,
TIM17
1
65536
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Functional overview
Table 4. Timer feature comparison (continued)
Max
Max
DMA
request
generation channels
Capture/ Comple-
compare mentary
timer
clock
Timer
Timer
type
Counter Counter Prescaler
interface
clock
resolution
type
factor
output
(MHz)
(MHz)
(1)
Any
integer
between1
and
TIM6,
Basic
16-bit
Up
Yes
No
0
0
No
137.5
137.5
275
275
TIM7
65536
LPTIM1,
Low-
power
timer
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
1, 2, 4, 8,
16, 32,
64, 128
16-bit
Up
No
1. The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
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STM32H723xE/G
3.31.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (Edge- or Center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.31.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H723xE/G
devices (see Table 4: Timer feature comparison for differences).
•
TIM2, TIM3, TIM4, TIM5, TIM23, TIM24
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4, TIM5,
TIM23 and TIM24. TIM2, TIM5, TIM23 and TIM24 are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit
auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent
channels for input capture/output compare, PWM or One-pulse mode output. This
gives up to 24 input capture/output compare/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5, TIM23 and TIM24 general-purpose timers can work together,
or with the other general-purpose timers and the advanced-control timers TIM1 and
TIM8 via the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5, TIM23, and TIM24 all have independent DMA request
generation. They are capable of handling quadrature (incremental) encoder signals
and the digital outputs from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5,
TIM23, and TIM24 full-featured general-purpose timers or used as simple time bases.
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Functional overview
3.31.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.31.4
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
•
•
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / One-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
•
Programmable digital glitch filter
Encoder mode
3.31.5
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
A window option allows the device to be reset when a reload operation is made too early
after the previous reload.
3.31.6
3.31.7
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
•
•
•
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
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Functional overview
STM32H723xE/G
3.32
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
•
Three anti-tamper detection pins with programmable filter.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in V
mode and in all low-power modes when it is clocked by the
BAT
LSE. When clocked by the LSI, the RTC is not functional in V
all low-power modes.
mode, but is functional in
BAT
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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Functional overview
3.33
Inter-integrated circuit interface (I2C)
2
STM32H723xE/G devices embed five I C interfaces.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and Master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power System Management Protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
3.34
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H723xE/G devices have five embedded universal synchronous receiver transmitters
(USART1, USART2, USART3, USART6, and USART10) and five universal asynchronous
receiver transmitters (UART4, UART5, UART7, UART8, and UART9). Refer to Table 5:
USART features for a summary of USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3, USART6, and USART10 also provide Smartcard mode (ISO
7816 compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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Functional overview
STM32H723xE/G
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 5. USART features
USART modes/features(1)
USART1/2/3/6/10
UART4/5/7/8/9
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode (Master/Slave)
Smartcard mode
-
Single-wire Half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
X
X
Dual clock domain and wakeup from low power mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
X
Tx/Rx FIFO size
16
1. X = supported.
3.35
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
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Functional overview
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.36
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI2S6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-
duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
2
Four standard I S interfaces (multiplexed with SPI1, SPI2, SPI3 and SPI6) are available.
They can be operated in Master or Slave mode, in Simplex communication modes, and can
be configured to operate as a 16-/32-bit resolution input or output channel (except SPI2S6
which is limited to 16 bits). Audio sampling frequencies from 8 kHz up to 192 kHz are
2
supported. When either or both of the I S interfaces is/are configured in Master mode, the
master clock can be output to the external DAC/CODEC at 256 times the sampling
2
frequency. All I S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA
capability.
3.37
Serial audio interfaces (SAI)
The devices embed 2 SAIs (SAI1, and SAI4) that allow designing many stereo or mono
audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF
output is available when the audio block is configured as a transmitter. To bring this level of
flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each
block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
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52
Functional overview
STM32H723xE/G
3.38
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
•
•
•
•
•
•
•
•
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.39
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
•
•
•
Full-duplex communication mode
automatic SWP bus state management (active, suspend, resume)
configurable bitrate up to 2 Mbit/s
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
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Functional overview
3.40
Management data input/output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
•
Configurable slave (port) address
Independently maskable interrupts/events:
–
–
–
MDIO Register write
MDIO Register read
MDIO protocol error
•
Able to operate in and wake up from Stop mode
3.41
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.42
Controller area network (FDCAN1, FDCAN2, FDCAN3)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
All CAN modules (FDCAN1, FDCAN2, and FDCAN3) are compliant with ISO 11898-1 (CAN
protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the three modules - FDCAN1 FDCAN2 and FDCAN3.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for FDCAN1, FDCAN2 and FDCAN3 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
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Functional overview
STM32H723xE/G
3.43
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral
that supports both full-speed and high-speed operations. It integrates the transceivers for
full-speed operation (12 Mbit/s) and a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG_HS interface in HS mode, an external
PHY device connected to the ULPI is required.
The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It features software-configurable endpoint setting and supports
suspend/resume. The USB OTG_HS controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
•
•
•
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Battery Charging Specification Revision 1.2 support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•
•
•
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.44
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
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Functional overview
The devices include the following features:
•
•
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
•
•
•
•
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
•
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
3.45
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.46
Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
•
•
•
•
•
•
•
•
•
Breakpoint debugging
Code execution tracing
Software instrumentation
JTAG debug port
Serial-wire debug port
Trigger input and output
Serial-wire trace port
Trace port
®
Arm CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools. The trace port performs data capture for logging and analysis.
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52
Memory mapping
STM32H723xE/G
4
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
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Pinouts, pin descriptions and alternate functions
5
Pinouts, pin descriptions and alternate functions
Figure 4. TFBGA100 pinout
1
2
3
PE2
PE3
PE4
PE5
PE6
PC3_C
PA4
PA5
PA6
PA7
4
5
PB7
PB6
PB5
BOOT0
VSS
VDD
PB2
PE7
6
7
8
9
10
PC14-
OSC32_IN
A
B
C
D
E
F
PC13
VBAT
VSS
VDD
PC2_C
PC1
PB9
PB8
PE1
PE0
VSS
VDD
PC4
PC5
PB0
PB1
PB4
PB3
PA15
PC11
PC12
PD0
PA14
PC10
PA9
PA13
PA12
PA11
PA10
PC7
PC15-
OSC32_OUT
PD5
PD2
PH0-OSC_IN
PD6
PD3
PH1-
OSC_OUT
PD7
PD4
PA8
NRST
PC0
VSS
VCAP
PDR_ON
PE14
PE15
PB10
PB11
PD1
PC9
PC8
PD11
PD10
PD9
PD8
VDD33USB
PE10
PE11
PE12
PE13
VCAP
PD15
PD14
PB13
PB12
PC6
G
H
J
VSSA
VDDA
VSS
PA0
PB15
PB14
PD13
PD12
PA1
PA2
PE8
K
VDD
PA3
PE9
MSv52520V1.
1. The above figure shows the package top view.
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85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Figure 5. LQFP100 pinout
PE2
PE3
1
2
75
VDD
VSS
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE4
PE5
PE6
VBAT
PC13
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
VDD
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC6
LQFP100
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
PC2_C
PC3_C
VSSA
VREF+
VDDA
PA0
PD8
PB15
PB14
PB13
PB12
PA1
PA2
PA3
MSv52521V1.
1. The above figure shows the package top view.
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Pinouts, pin descriptions and alternate functions
Figure 6. LQFP144 pinout
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
VDD
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
9
PA8
PC9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
LQFP144
PG4
PG3
PG2
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0
PD8
PB15
PB14
PB13
PB12
PA1
PA2
MSv52522V1.
1. The above figure shows the package top view.
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85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Figure 7. UFBGA144 ballout
1
2
3
4
5
6
7
8
9
10
11
PA14
PC10
VDD33USB
PA10
PC9
12
A
B
C
D
E
F
PC13
PE3
PE4
VBAT
VSS
PF3
PF7
PF9
PC1
PA0
PA1
PA2
PA3
PE2
PE5
PF0
VDD
PF4
PF6
PF8
PC2
PA4
PA5
PA6
PA7
PE1
PE6
PF1
PF2
PF5
VDD
VSS
PC3
PC4
PC5
PB0
PB1
PE0
PB4
PB5
PB6
PB7
VSS
VDD
VDD
VSS
PG1
PG0
PF15
PF14
PB3
PD6
PD7
PD5
PD4
PD3
PD2
VDD
VCAP
PD11
PD10
PD9
PD8
PB10
PA15
PC11
PC12
PD1
PA13
PA12
PA11
PA9
PC14-
OSC32_IN
PB9
PG15
PG14
PG13
VSS
VDD
VDD
VCAP
PE10
PE9
PG12
PG11
PG10
PG9
PC15-
OSC32_OUT
PB8
PH0-OSC_IN
BOOT0
PDR_ON
VDD
PH1-
OSC_OUT
PD0
PA8
NRST
PF10
VDD
VSS
VDD
VSS
PC8
PC7
G
H
J
VDD
PG8
PC6
PC0
VSS
PE11
PE12
PE13
PE14
PE15
PG7
PG6
PG5
PG2
PD15
PB15
PB13
VSSA
VREF-
VREF+
VDDA
PB2
PG4
PG3
K
L
PF13
PF12
PF11
PD13
PD12
PB11
PD14
PB14
PB12
PE8
M
PE7
MSv52523V1.
1. The above figure shows the package top view.
Table 6. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
ANA
FT
TT
B
Input / output pin
Analog-only Input
5 V tolerant I/O
3.3 V tolerant I/O
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
RST
I/O structure
Option for TT and FT I/Os
_f
I2C FM+ option
_a
_u
_h
analog option (supplied by VDDA)
USB option (supplied by VDD33USB
)
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Notes
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Pinouts, pin descriptions and alternate functions
Definition
Table 6. Legend/abbreviations used in the pinout table (continued)
Name
Abbreviation
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 7. STM32H723 pin and ball descriptions
Pin number
Pin name (function
Additional
functions
Alternate functions
after reset)
TRACECLK, SAI1_CK1,
USART10_RX, SPI4_SCK,
SAI1_MCLK_A, SAI4_MCLK_A,
OCTOSPIM_P1_IO2, SAI4_CK1,
ETH_MII_TXD3, FMC_A23,
EVENTOUT
A3
B3
C3
1
2
3
1
2
3
A3
A2
B2
PE2
PE3
PE4
I/O FT_h
I/O FT_h
I/O FT_h
-
-
-
-
-
-
TRACED0, TIM15_BKIN, SAI1_SD_B,
SAI4_SD_B, USART10_TX, FMC_A19,
EVENTOUT
TRACED1, SAI1_D2,
DFSDM1_DATIN3, TIM15_CH1N,
SPI4_NSS, SAI1_FS_A, SAI4_FS_A,
SAI4_D2, FMC_A20,
DCMI_D4/PSSI_D4, LCD_B0,
EVENTOUT
TRACED2, SAI1_CK2,
DFSDM1_CKIN3, TIM15_CH1,
SPI4_MISO, SAI1_SCK_A,
SAI4_SCK_A, SAI4_CK2, FMC_A21,
DCMI_D6/PSSI_D6, LCD_G0,
EVENTOUT
D3
E3
4
5
4
5
B3
B4
PE5
PE6
I/O FT_h
-
-
-
TRACED3, TIM1_BKIN2, SAI1_D1,
TIM15_CH2, SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1, SAI4_MCLK_B,
TIM1_BKIN2_COMP12, FMC_A22,
DCMI_D7/PSSI_D7, LCD_G1,
EVENTOUT
I/O FT_h
-
-
B2
A2
6
7
6
7
C2
A1
VBAT
PC13
S
-
-
-
-
RTC_TAMP1/
RTC_TS,
I/O
FT
EVENTOUT
WKUP4
A1
B1
8
9
8
9
B1
C1
PC14-OSC32_IN
I/O
I/O
FT
FT
-
-
EVENTOUT
EVENTOUT
OSC32_IN
PC15-OSC32_OUT
OSC32_OUT
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85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
I2C2_SDA(boot), I2C5_SDA,
OCTOSPIM_P2_IO0, FMC_A0,
TIM23_CH1, EVENTOUT
-
-
-
-
-
-
10
11
12
C3
C4
D4
PF0
PF1
PF2
I/O FT_fh
I/O FT_fh
I/O FT_h
-
-
-
-
-
I2C2_SCL(boot), I2C5_SCL,
OCTOSPIM_P2_IO1, FMC_A1,
TIM23_CH2, EVENTOUT
I2C2_SMBA, I2C5_SMBA,
OCTOSPIM_P2_IO2, FMC_A2,
TIM23_CH3, EVENTOUT
-
OCTOSPIM_P2_IO3, FMC_A3,
TIM23_CH4, EVENTOUT
-
-
-
-
-
-
13
14
15
E2
E3
E4
PF3
PF4
PF5
I/O FT_ha
I/O FT_ha
I/O FT_ha
-
-
-
ADC3_INP5
OCTOSPIM_P2_CLK, FMC_A4,
EVENTOUT
ADC3_INN5,
ADC3_INP9
OCTOSPIM_P2_NCLK, FMC_A5,
EVENTOUT
ADC3_INP4
-
-
10
11
16
17
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM16_CH1, FDCAN3_RX, SPI5_NSS,
SAI1_SD_B, UART7_RX, SAI4_SD_B,
OCTOSPIM_P1_IO3, TIM23_CH1,
EVENTOUT
ADC3_INN4,
ADC3_INP8
-
-
-
-
18
19
F3
F2
PF6
PF7
I/O FT_ha
I/O FT_ha
-
-
TIM17_CH1, FDCAN3_TX, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
SAI4_MCLK_B, OCTOSPIM_P1_IO2,
TIM23_CH2, EVENTOUT
ADC3_INP3
TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE,
SAI4_SCK_B, TIM13_CH1,
OCTOSPIM_P1_IO0, TIM23_CH3,
EVENTOUT
ADC3_INN3,
ADC3_INP7
-
-
-
-
20
21
G3
G2
PF8
PF9
I/O FT_ha
-
-
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS, SAI4_FS_B,
TIM14_CH1, OCTOSPIM_P1_IO1,
TIM23_CH4, EVENTOUT
I/O FT_ha
I/O FT_ha
ADC3_INP2
TIM16_BKIN, SAI1_D3, PSSI_D15,
OCTOSPIM_P1_CLK, SAI4_D3,
DCMI_D11/PSSI_D11, LCD_DE,
EVENTOUT
ADC3_INN2,
ADC3_INP6
-
-
22
23
G1
D1
PF10
-
-
C1
12
PH0-OSC_IN
I/O
FT
EVENTOUT
OSC_IN
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Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
D1
E1
13
14
24
25
E1
F1
PH1-OSC_OUT
NRST
I/O
FT
-
-
EVENTOUT
-
OSC_OUT
-
I/O RST
FMC_D12/FMC_AD12,
DFSDM1_CKIN0, DFSDM1_DATIN4,
SAI4_FS_B, FMC_A25,
OTG_HS_ULPI_STP, LCD_G2,
FMC_SDNWE, LCD_R5, EVENTOUT
F1
F2
15
16
26
27
H1
H2
PC0
PC1
I/O FT_ha
-
-
ADC123_INP10
TRACED0, SAI4_D1, SAI1_D1,
DFSDM1_DATIN0, DFSDM1_CKIN4, ADC123_INN10,
SPI2_MOSI/I2S2_SDO, SAI1_SD_A, ADC123_INP11,
SAI4_SD_A, SDMMC2_CK,
OCTOSPIM_P1_IO4, ETH_MDC,
MDIOS_MDC, LCD_G5, EVENTOUT
I/O FT_ha
RTC_TAMP3,
WKUP6
PWR_DEEPSLEEP, DFSDM1_CKIN1,
OCTOSPIM_P1_IO5,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OCTOSPIM_P1_IO2,
ADC123_INN11,
ADC123_INP12
-
-
-
H3
PC2
PC2_C
PC3
I/O FT_a
-
-
-
-
OTG_HS_ULPI_DIR, ETH_MII_TXD2,
FMC_SDNE0, EVENTOUT
AN
TT_a
A
ADC3_INN1,
ADC3_INP0
E2
17
28
-
-
PWR_SLEEP, DFSDM1_DATIN1,
OCTOSPIM_P1_IO6,
SPI2_MOSI/I2S2_SDO,
OCTOSPIM_P1_IO0,
OTG_HS_ULPI_NXT,
ADC12_INN12,
ADC12_INP13
-
-
-
H4
I/O FT_a
ETH_MII_TX_CLK, FMC_SDCKE0,
EVENTOUT
AN
TT_a
A
F3
18
29
-
PC3_C
-
ADC3_INP1
-
G1
-
-
30
31
-
-
VDD
VSSA
VREF-
VREF+
VDDA
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
19
-
J1
K1
L1
M1
-
20
21
32
33
H1
DS13313 Rev 2
59/227
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
TIM2_CH1/TIM2_ETR, TIM5_CH1,
TIM8_ETR, TIM15_BKIN,
SPI6_NSS/I2S6_WS,
USART2_CTS/USART2_NSS,
UART4_TX, SDMMC2_CMD,
SAI4_SD_B, ETH_MII_CRS,
FMC_A19, EVENTOUT
ADC1_INP16,
WKUP1
G2
22
34
J2
PA0
PA1
I/O FT_ha
-
TIM2_CH2, TIM5_CH2, LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS/USART2_DE,
UART4_RX, OCTOSPIM_P1_IO3,
SAI4_MCLK_B,
ADC1_INN16,
ADC1_INP17
H2
23
35
K2
I/O FT_ha
-
ETH_MII_RX_CLK/ETH_RMII_REF_C
LK, OCTOSPIM_P1_DQS, LCD_R2,
EVENTOUT
TIM2_CH3, TIM5_CH3, LPTIM4_OUT,
TIM15_CH1, OCTOSPIM_P1_IO0,
USART2_TX(boot), SAI4_SCK_B,
ETH_MDIO, MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC12_INP14,
WKUP2
J2
24
25
36
37
L2
PA2
PA3
I/O FT_ha
-
-
TIM2_CH4, TIM5_CH4, LPTIM5_OUT,
TIM15_CH2, I2S6_MCK,
OCTOSPIM_P1_IO2,
K2
M2
I/O FT_ha
USART2_RX(boot), LCD_B2,
OTG_HS_ULPI_D0, ETH_MII_COL,
OCTOSPIM_P1_CLK, LCD_B5,
EVENTOUT
ADC12_INP15
-
-
26
27
38
39
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
D1PWREN, TIM5_ETR,
SPI1_NSS(boot)/I2S1_WS,
SPI3_NSS/I2S3_WS, USART2_CK,
SPI6_NSS/I2S6_WS,
ADC12_INP18,
DAC1_OUT1
G3
H3
28
29
40
41
J3
PA4
PA5
I/O TT_ha
-
-
FMC_D8/FMC_AD8,
DCMI_HSYNC/PSSI_DE,
LCD_VSYNC, EVENTOUT
D2PWREN, TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK(boot)/I2S1_CK,
SPI6_SCK/I2S6_CK,
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
K3
I/O TT_ha
OTG_HS_ULPI_CK,
FMC_D9/FMC_AD9, PSSI_D14,
LCD_R4, EVENTOUT
60/227
DS13313 Rev 2
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
TIM1_BKIN, TIM3_CH1, TIM8_BKIN,
SPI1_MISO(boot)/I2S1_SDI,
OCTOSPIM_P1_IO3,
SPI6_MISO/I2S6_SDI, TIM13_CH1,
TIM8_BKIN_COMP12, MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK/PSSI_PDCK, LCD_G2,
EVENTOUT
J3
30
42
L3
PA6
PA7
I/O FT_ha
-
ADC12_INP3
TIM1_CH1N, TIM3_CH2, TIM8_CH1N,
SPI1_MOSI(boot)/I2S1_SDO,
SPI6_MOSI/I2S6_SDO, TIM14_CH1,
OCTOSPIM_P1_IO2,
ADC12_INN3,
ADC12_INP7,
K3
31
43
M3
I/O TT_ha
-
ETH_MII_RX_DV/ETH_RMII_CRS_DV, OPAMP1_VINM
FMC_SDNWE, LCD_VSYNC,
EVENTOUT
PWR_DEEPSLEEP, FMC_A22,
DFSDM1_CKIN2, I2S1_MCK,
SPDIFRX1_IN3, SDMMC2_CKIN,
ETH_MII_RXD0/ETH_RMII_RXD0,
FMC_SDNE0, LCD_R7, EVENTOUT
ADC12_INP4,
OPAMP1_VOUT,
COMP1_INM
G4
H4
32
33
44
45
J4
PC4
PC5
I/O TT_ha
I/O TT_ha
-
-
PWR_SLEEP, SAI4_D3, SAI1_D3,
DFSDM1_DATIN2, PSSI_D15,
SPDIFRX1_IN4,OCTOSPIM_P1_DQS,
ETH_MII_RXD1/ETH_RMII_RXD1,
FMC_SDCKE0, COMP1_OUT,
LCD_DE, EVENTOUT
ADC12_INN4,
ADC12_INP8,
OPAMP1_VINM
K4
TIM1_CH2N, TIM3_CH3, TIM8_CH2N,
OCTOSPIM_P1_IO1,
DFSDM1_CKOUT, UART4_CTS,
LCD_R3, OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1, EVENTOUT
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP1_INP
J4
34
35
46
47
L4
PB0
PB1
I/O TT_ha
I/O FT_ha
-
-
TIM1_CH3N, TIM3_CH4, TIM8_CH3N,
OCTOSPIM_P1_IO0,
DFSDM1_DATIN1, LCD_R6,
OTG_HS_ULPI_D2, ETH_MII_RXD3,
LCD_G0, EVENTOUT
ADC12_INP5,
COMP1_INM
K4
M4
RTC_OUT, SAI4_D1, SAI1_D1,
DFSDM1_CKIN1, SAI1_SD_A,
SPI3_MOSI/I2S3_SDO, SAI4_SD_A,
OCTOSPIM_P1_CLK,
G5
36
48
J5
PB2
I/O FT_ha
-
COMP1_INP
OCTOSPIM_P1_DQS, ETH_TX_ER,
TIM23_ETR, EVENTOUT
DS13313 Rev 2
61/227
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
SPI5_MOSI, OCTOSPIM_P1_NCLK,
SAI4_SD_B, FMC_NRAS,
DCMI_D12/PSSI_D12, TIM24_CH1,
EVENTOUT
-
-
-
-
49
50
M5
L5
PF11
PF12
I/O FT_ha
I/O FT_ha
-
-
ADC1_INP2
OCTOSPIM_P2_DQS, FMC_A6,
TIM24_CH2, EVENTOUT
ADC1_INN2,
ADC1_INP6
-
-
-
-
51
52
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
DFSDM1_DATIN6, I2C4_SMBA,
FMC_A7, TIM24_CH3, EVENTOUT
-
-
53
K5
PF13
I/O FT_ha
-
ADC2_INP2
DFSDM1_CKIN6, I2C4_SCL, FMC_A8,
TIM24_CH4, EVENTOUT
ADC2_INN2,
ADC2_INP6
-
-
-
-
-
-
54
55
56
M6
L6
PF14
PF15
PG0
I/O FT_fha
I/O FT_fh
I/O FT_h
-
-
-
I2C4_SDA, FMC_A9, EVENTOUT
-
-
OCTOSPIM_P2_IO4, UART9_RX,
FMC_A10, EVENTOUT
K6
OCTOSPIM_P2_IO5, UART9_TX,
FMC_A11, EVENTOUT
-
-
57
58
J6
PG1
PE7
I/O TT_h
I/O TT_ha
-
-
OPAMP2_VINM
TIM1_ETR, DFSDM1_DATIN2,
UART7_RX, OCTOSPIM_P1_IO4,
FMC_D4/FMC_AD4, EVENTOUT
OPAMP2_VOUT,
COMP2_INM
H5
37
M7
TIM1_CH1N, DFSDM1_CKIN2,
UART7_TX, OCTOSPIM_P1_IO5,
FMC_D5/FMC_AD5, COMP2_OUT,
EVENTOUT
J5
38
39
59
60
L7
K7
PE8
PE9
I/O TT_ha
I/O TT_ha
-
-
OPAMP2_VINM
TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS/UART7_DE,
OCTOSPIM_P1_IO6,
OPAMP2_VINP,
COMP2_INP
K5
FMC_D6/FMC_AD6, EVENTOUT
-
-
-
-
61
62
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM1_CH2N, DFSDM1_DATIN4,
UART7_CTS, OCTOSPIM_P1_IO7,
FMC_D7/FMC_AD7, EVENTOUT
G6
40
63
J7
PE10
I/O FT_ha
-
COMP2_INM
TIM1_CH2, DFSDM1_CKIN4,
SPI4_NSS(boot), SAI4_SD_B,
OCTOSPIM_P1_NCS,
H6
41
64
H8
PE11
I/O FT_ha
-
COMP2_INP
FMC_D8/FMC_AD8, LCD_G3,
EVENTOUT
62/227
DS13313 Rev 2
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
TIM1_CH3N, DFSDM1_DATIN5,
SPI4_SCK(boot), SAI4_SCK_B,
FMC_D9/FMC_AD9, COMP1_OUT,
LCD_B4, EVENTOUT
J6
42
65
J8
PE12
I/O FT_h
-
-
TIM1_CH3, DFSDM1_CKIN5,
SPI4_MISO(boot), SAI4_FS_B,
FMC_D10/FMC_AD10, COMP2_OUT,
LCD_DE, EVENTOUT
K6
G7
H7
43
44
45
66
67
68
K8
L8
PE13
PE14
PE15
I/O FT_h
I/O FT_h
I/O FT_h
-
-
-
-
-
-
TIM1_CH4, SPI4_MOSI(boot),
SAI4_MCLK_B, FMC_D11/FMC_AD11,
LCD_CLK, EVENTOUT
TIM1_BKIN, USART10_CK,
FMC_D12/FMC_AD12,
TIM1_BKIN_COMP12, LCD_R7,
EVENTOUT
M8
TIM2_CH3, LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7, USART3_TX(boot),
OCTOSPIM_P1_NCS,
OTG_HS_ULPI_D3, ETH_MII_RX_ER,
LCD_G4, EVENTOUT
J7
46
47
69
M9
PB10
PB11
I/O FT_fh
-
-
-
-
TIM2_CH4, LPTIM2_ETR, I2C2_SDA,
DFSDM1_CKIN7, USART3_RX(boot),
OTG_HS_ULPI_D4,
K7
70 M10
I/O FT_f
ETH_MII_TX_EN/ETH_RMII_TX_EN,
LCD_G5, EVENTOUT
F8
-
48
49
50
71
-
H7
VCAP
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
72
VDD
TIM1_BKIN, OCTOSPIM_P1_NCLK,
I2C2_SMBA, SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1, USART3_CK,
FDCAN2_RX, OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII_TXD0,
OCTOSPIM_P1_IO0,
K8
51
73 M11
PB12
I/O FT_h
-
-
TIM1_BKIN_COMP12, UART5_RX,
EVENTOUT
DS13313 Rev 2
63/227
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
TIM1_CH1N, LPTIM2_OUT,
OCTOSPIM_P1_IO2,
SPI2_SCK/I2S2_CK, DFSDM1_CKIN1,
USART3_CTS/USART3_NSS,
FDCAN2_TX, OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII_TXD1,
SDMMC1_D0, DCMI_D2/PSSI_D2,
UART5_TX, EVENTOUT
J8
52
74 M12
PB13
I/O FT_h
-
-
TIM1_CH2N, TIM12_CH1,
TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
H10 53
75 L11
PB14
PB15
I/O FT_h
-
-
-
-
USART3_RTS/USART3_DE,
UART4_RTS/UART4_DE,
SDMMC2_D0, FMC_D10/FMC_AD10,
LCD_CLK, EVENTOUT
RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
USART1_RX, SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2, UART4_CTS,
SDMMC2_D1, FMC_D11/FMC_AD11,
LCD_G7, EVENTOUT
G10 54
76 L12
I/O FT_h
DFSDM1_CKIN3, USART3_TX(boot),
SPDIFRX1_IN2,
FMC_D13/FMC_AD13, EVENTOUT
K9
J9
55
56
57
77
78
79
L9
K9
J9
PD8
PD9
I/O FT_h
I/O FT_h
I/O FT_h
-
-
-
-
-
-
DFSDM1_DATIN3, USART3_RX(boot),
FMC_D14/FMC_AD14, EVENTOUT
DFSDM1_CKOUT, USART3_CK,
FMC_D15/FMC_AD15, LCD_B3,
EVENTOUT
H9
PD10
LPTIM2_IN2, I2C4_SMBA,
USART3_CTS/USART3_NSS,
OCTOSPIM_P1_IO0, SAI4_SD_A,
FMC_A16/FMC_CLE, EVENTOUT
G9
58
80
H9
PD11
PD12
I/O FT_h
I/O FT_fh
-
-
-
-
LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1,
I2C4_SCL, FDCAN3_RX,
USART3_RTS/USART3_DE,
OCTOSPIM_P1_IO1, SAI4_FS_A,
FMC_A17/FMC_ALE,
K10 59
81 L10
DCMI_D12/PSSI_D12, EVENTOUT
64/227
DS13313 Rev 2
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
LPTIM1_OUT, TIM4_CH2, I2C4_SDA,
FDCAN3_TX, OCTOSPIM_P1_IO3,
SAI4_SCK_A,
J10 60
82 K10
PD13
I/O FT_fh
-
-
UART9_RTS/UART9_DE, FMC_A18,
DCMI_D13/PSSI_D13, EVENTOUT
-
-
-
-
83
84
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM4_CH3, UART8_CTS, UART9_RX,
FMC_D0/FMC_AD0, EVENTOUT
H8
G8
61
62
85 K11
86 K12
87 J12
PD14
PD15
I/O FT_h
I/O FT_h
-
-
-
-
TIM4_CH4, UART8_RTS/UART8_DE,
UART9_TX, FMC_D1/FMC_AD1,
EVENTOUT
TIM8_BKIN, TIM8_BKIN_COMP12,
FMC_A12, TIM24_ETR, EVENTOUT
-
-
-
-
-
-
-
-
PG2
PG3
PG4
PG5
I/O FT_h
I/O FT_h
I/O FT_h
I/O FT_h
-
-
-
-
-
-
-
-
TIM8_BKIN2, TIM8_BKIN2_COMP12,
FMC_A13, TIM23_ETR, EVENTOUT
88
J11
TIM1_BKIN2, TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0, EVENTOUT
89 J10
90 H12
TIM1_ETR, FMC_A15/FMC_BA1,
EVENTOUT
TIM17_BKIN, OCTOSPIM_P1_NCS,
FMC_NE3, DCMI_D12/PSSI_D12,
LCD_R7, EVENTOUT
-
-
-
-
91 H11
92 H10
PG6
PG7
I/O FT_h
I/O FT_h
-
-
-
-
SAI1_MCLK_A, USART6_CK,
OCTOSPIM_P2_DQS, FMC_INT,
DCMI_D13/PSSI_D13, LCD_CLK,
EVENTOUT
TIM8_ETR, SPI6_NSS/I2S6_WS,
USART6_RTS/USART6_DE,
SPDIFRX1_IN3, ETH_PPS_OUT,
FMC_SDCLK, LCD_G7, EVENTOUT
-
-
93 G11
PG8
I/O FT_h
-
-
-
-
-
94
-
VSS
S
S
-
-
-
-
-
-
-
-
F6
95 C11
VDD33USB
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3, I2S2_MCK,
USART6_TX, SDMMC1_D0DIR,
FMC_NWAIT, SDMMC2_D6,
SDMMC1_D6, DCMI_D0/PSSI_D0,
LCD_HSYNC, EVENTOUT
F10 63
96 G12
PC6
I/O FT_h
-
SWPMI_IO
DS13313 Rev 2
65/227
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
DBTRGIO, TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3, I2S3_MCK,
USART6_RX, SDMMC1_D123DIR,
FMC_NE1, SDMMC2_D7, SWPMI_TX,
SDMMC1_D7, DCMI_D1/PSSI_D1,
LCD_G6, EVENTOUT
E10 64
97 F12
PC7
PC8
I/O FT_h
-
-
-
TRACED1, TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS/UART5_DE,
FMC_NE2/FMC_NCE, FMC_INT,
SWPMI_RX, SDMMC1_D0,
DCMI_D2/PSSI_D2, EVENTOUT
F9
E9
65
66
98 F11
I/O FT_h
-
-
MCO2, TIM3_CH4, TIM8_CH4,
I2C3_SDA(boot), I2S_CKIN,
I2C5_SDA, UART5_CTS,
OCTOSPIM_P1_IO0, LCD_G3,
SWPMI_SUSPEND, SDMMC1_D1,
DCMI_D3/PSSI_D3, LCD_B2,
EVENTOUT
99 E11
PC9
I/O FT_fh
-
MCO1, TIM1_CH1, TIM8_BKIN2,
I2C3_SCL(boot), I2C5_SCL,
D9
C9
67 100 E12
PA8
PA9
I/O FT_fh
I/O FT_u
-
-
USART1_CK, OTG_HS_SOF,
UART7_RX, TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6, EVENTOUT
-
TIM1_CH2, LPUART1_TX,
I2C3_SMBA, SPI2_SCK/I2S2_CK,
I2C5_SMBA, USART1_TX(boot),
ETH_TX_ER, DCMI_D0/PSSI_D0,
LCD_R5, EVENTOUT
68 101 D12
OTG_HS_VBUS
TIM1_CH3, LPUART1_RX,
USART1_RX(boot), OTG_HS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1/PSSI_D1, LCD_B1,
EVENTOUT
D10 69 102 D11
PA10
PA11
I/O FT_u
I/O FT_u
-
-
-
TIM1_CH4, LPUART1_CTS,
SPI2_NSS/I2S2_WS, UART4_RX,
USART1_CTS/USART1_NSS,
FDCAN1_RX, LCD_R4, EVENTOUT
OTG_HS_DM
(boot)
C10 70 103 C12
TIM1_ETR,
LPUART1_RTS/LPUART1_DE,
SPI2_SCK/I2S2_CK, UART4_TX,
USART1_RTS/USART1_DE,
SAI4_FS_B, FDCAN1_TX,
OTG_HS_DP
(boot)
B10 71 104 B12
PA12
I/O FT_u
-
TIM1_BKIN2, LCD_R5, EVENTOUT
66/227
DS13313 Rev 2
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
A10 72 105 A12 PA13(JTMS/SWDIO) I/O
FT
-
-
-
-
-
-
JTMS/SWDIO, EVENTOUT
-
-
-
-
-
E7
-
73 106 G9
VCAP
VSS
S
S
S
-
74 107
75 108
-
-
-
-
-
VDD
-
-
A9
76 109 A11 PA14(JTCK/SWCLK) I/O
FT
JTCK/SWCLK, EVENTOUT
JTDI, TIM2_CH1/TIM2_ETR, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS/I2S6_WS,
UART4_RTS/UART4_DE, LCD_R3,
UART7_TX, LCD_B6, EVENTOUT
A8
B9
B8
C8
77 110 A10
PA15(JTDI)
I/O
FT
-
-
-
-
-
-
-
-
DFSDM1_CKIN5, I2C5_SDA,
SPI3_SCK(boot)/I2S3_CK,
USART3_TX, UART4_TX,
OCTOSPIM_P1_IO1, LCD_B1,
SWPMI_RX, SDMMC1_D2,
DCMI_D8/PSSI_D8, LCD_R2,
EVENTOUT
78
111 B11
PC10
I/O FT_fh
I/O FT_fh
I/O FT_h
DFSDM1_DATIN5, I2C5_SCL,
SPI3_MISO(boot)/I2S3_SDI,
USART3_RX, UART4_RX,
OCTOSPIM_P1_NCS, SDMMC1_D3,
DCMI_D4/PSSI_D4, LCD_B4,
EVENTOUT
79 112 B10
PC11
TRACED3, FMC_D6/FMC_AD6,
TIM15_CH1, I2C5_SMBA,
SPI6_SCK/I2S6_CK,
SPI3_MOSI(boot)/I2S3_SDO,
USART3_CK, UART5_TX,
SDMMC1_CK, DCMI_D9/PSSI_D9,
LCD_R6, EVENTOUT
80 113 C10
PC12
DFSDM1_CKIN6, UART4_RX,
FDCAN1_RX(boot), UART9_CTS,
FMC_D2/FMC_AD2, LCD_B1,
EVENTOUT
D8
E8
81 114 E10
82 115 D10
PD0
PD1
I/O FT_h
I/O FT_h
-
-
-
-
DFSDM1_DATIN6, UART4_TX,
FDCAN1_TX(boot),
FMC_D3/FMC_AD3, EVENTOUT
DS13313 Rev 2
67/227
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
TRACED2, FMC_D7/FMC_AD7,
TIM3_ETR, TIM15_BKIN, UART5_RX,
LCD_B7, SDMMC1_CMD,
DCMI_D11/PSSI_D11, LCD_B2,
EVENTOUT
B7
C7
83 116 E9
PD2
PD3
I/O FT_h
I/O FT_h
-
-
-
-
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_NSS,
FMC_CLK, DCMI_D5/PSSI_D5,
LCD_G7, EVENTOUT
84 117 D9
USART2_RTS/USART2_DE,
OCTOSPIM_P1_IO4, FMC_NOE,
EVENTOUT
D7
B6
85 118 C9
86 119 B9
PD4
PD5
I/O FT_h
I/O FT_h
-
-
-
-
USART2_TX, OCTOSPIM_P1_IO5,
FMC_NWE, EVENTOUT
-
-
-
-
120
121
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
SAI4_D1, SAI1_D1, DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO, SAI1_SD_A,
USART2_RX, SAI4_SD_A,
OCTOSPIM_P1_IO6, SDMMC2_CK,
FMC_NWAIT, DCMI_D10/PSSI_D10,
LCD_B2, EVENTOUT
C6
D6
87 122 A8
PD6
PD7
I/O FT_h
-
-
-
-
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1, USART2_CK,
SPDIFRX1_IN1, OCTOSPIM_P1_IO7,
SDMMC2_CMD, FMC_NE1,
EVENTOUT
88 123 A9
I/O FT_h
FDCAN3_TX, SPI1_MISO/I2S1_SDI,
USART6_RX, SPDIFRX1_IN4,
-
-
-
-
124 E8
PG9
I/O FT_h
I/O FT_h
-
-
OCTOSPIM_P1_IO6, SAI4_FS_B,
SDMMC2_D0, FMC_NE2/FMC_NCE,
DCMI_VSYNC/PSSI_RDY, EVENTOUT
-
-
FDCAN3_RX, OCTOSPIM_P2_IO6,
SPI1_NSS/I2S1_WS, LCD_G3,
SAI4_SD_B, SDMMC2_D1, FMC_NE3,
DCMI_D2/PSSI_D2, LCD_B2,
EVENTOUT
125 D8
PG10
68/227
DS13313 Rev 2
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
LPTIM1_IN2, USART10_RX,
SPI1_SCK/I2S1_CK, SPDIFRX1_IN1,
OCTOSPIM_P2_IO7, SDMMC2_D2,
ETH_MII_TX_EN/ETH_RMII_TX_EN,
DCMI_D3/PSSI_D3, LCD_B3,
EVENTOUT
-
-
-
-
126 C8
PG11
PG12
I/O FT_h
-
-
-
-
LPTIM1_IN1, OCTOSPIM_P2_NCS,
USART10_TX, SPI6_MISO/I2S6_SDI,
USART6_RTS/USART6_DE,
SPDIFRX1_IN2, LCD_B4,
SDMMC2_D3,
127 B8
I/O FT_h
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_NE4, TIM23_CH1, LCD_B1,
EVENTOUT
TRACED0, LPTIM1_OUT,
USART10_CTS/USART10_NSS,
SPI6_SCK/I2S6_CK,
USART6_CTS/USART6_NSS,
SDMMC2_D6,
-
-
128 D7
PG13
I/O FT_h
-
-
ETH_MII_TXD0/ETH_RMII_TXD0,
FMC_A24, TIM23_CH2, LCD_R0,
EVENTOUT
TRACED1, LPTIM1_ETR,
USART10_RTS/USART10_DE,
SPI6_MOSI/I2S6_SDO, USART6_TX,
OCTOSPIM_P1_IO7, SDMMC2_D7,
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_A25, TIM23_CH3, LCD_B0,
EVENTOUT
-
-
129 C7
PG14
I/O FT_h
-
-
-
-
-
-
130
131
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
USART6_CTS/USART6_NSS,
OCTOSPIM_P2_DQS, USART10_CK,
FMC_NCAS, DCMI_D13/PSSI_D13,
EVENTOUT
-
-
132 B7
PG15
I/O FT_h
-
-
JTDO/TRACESWO, TIM2_CH2,
SPI1_SCK/I2S1_CK,
PB3
SPI3_SCK/I2S3_CK,
A7
89 133 A7
I/O FT_h
-
-
(JTDO/TRACESWO)
SPI6_SCK/I2S6_CK, SDMMC2_D2,
CRS_SYNC, UART7_RX, TIM24_ETR,
EVENTOUT
DS13313 Rev 2
69/227
85
Pinouts, pin descriptions and alternate functions
STM32H723xE/G
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
NJTRST, TIM16_BKIN, TIM3_CH1,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO/I2S6_SDI, SDMMC2_D3,
UART7_TX, EVENTOUT
A6
C5
90 134 A6
PB4(NJTRST)
I/O FT_h
-
-
-
TIM17_BKIN, TIM3_CH2, LCD_B5,
I2C1_SMBA, SPI1_MOSI/I2S1_SDO,
I2C4_SMBA, SPI3_MOSI/I2S3_SDO,
SPI6_MOSI/I2S6_SDO, FDCAN2_RX,
OTG_HS_ULPI_D7, ETH_PPS_OUT,
FMC_SDCKE1, DCMI_D10/PSSI_D10,
UART5_RX, EVENTOUT
91 135 B6
PB5
I/O FT_h
-
-
TIM16_CH1N, TIM4_CH1,
I2C1_SCL(boot), CEC, I2C4_SCL,
USART1_TX, LPUART1_TX,
FDCAN2_TX, OCTOSPIM_P1_NCS,
DFSDM1_DATIN5, FMC_SDNE1,
DCMI_D5/PSSI_D5, UART5_TX,
EVENTOUT
B5
92 136 C6
PB6
I/O FT_fh
-
TIM17_CH1N, TIM4_CH2, I2C1_SDA,
I2C4_SDA, USART1_RX,
A5
D5
93 137 D6
94 138 D5
PB7
I/O FT_fa
-
-
LPUART1_RX, DFSDM1_CKIN5,
FMC_NL, DCMI_VSYNC/PSSI_RDY,
EVENTOUT
PVD_IN
VPP
BOOT0
I
B
-
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7, I2C1_SCL,
I2C4_SCL, SDMMC1_CKIN,
UART4_RX, FDCAN1_RX,
SDMMC2_D4, ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6/PSSI_D6,
LCD_B6, EVENTOUT
B4
95 139 C5
PB8
I/O FT_fh
-
-
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7, I2C1_SDA(boot),
SPI2_NSS/I2S2_WS, I2C4_SDA,
SDMMC1_CDIR, UART4_TX,
FDCAN1_TX, SDMMC2_D5,
I2C4_SMBA, SDMMC1_D5,
DCMI_D7/PSSI_D7, LCD_B7,
EVENTOUT
A4
96 140 B5
PB9
I/O FT_fh
-
-
70/227
DS13313 Rev 2
STM32H723xE/G
Pinouts, pin descriptions and alternate functions
Table 7. STM32H723 pin and ball descriptions (continued)
Pin number
Pin name (function
after reset)
Additional
functions
Alternate functions
LPTIM1_ETR, TIM4_ETR,
LPTIM2_ETR, UART8_RX,
SAI4_MCLK_A, FMC_NBL0,
DCMI_D2/PSSI_D2, LCD_R0,
EVENTOUT
D4
C4
97 141 A5
PE0
PE1
I/O FT_h
I/O FT_h
-
-
-
-
LPTIM1_IN2, UART8_TX, FMC_NBL1,
DCMI_D3/PSSI_D3, LCD_R6,
EVENTOUT
98 142 A4
-
F7
-
99
-
-
-
VSS
PDR_ON
VDD
VSS
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
143 E5
100 144
-
C2
E6
J1
E4
E5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D2
E6
E7
G4
G8
G10
H5
H6
D3
F4
VSS
VSS
VSS
VSS
VSS
-
VSS
-
VSS
D2
F5
K1
F4
-
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
F5
F6
F7
-
F8
-
F9
-
F10
G5
G6
G7
-
-
-
DS13313 Rev 2
71/227
85
Table 8. STM32H723 pin alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
USART2
_CTS/
USART2
_NSS
TIM2_CH
1/TIM2_ TIM5_CH1
ETR
SPI6_
NSS/I2S
6_WS
TIM8_
ETR
TIM15_
BKIN
UART4_ SDMMC2_ SAI4_SD_
ETH_MII_
CRS
EVENT
OUT
PA0
-
-
-
-
FMC_A19
-
-
-
TX
CMD
B
USART2
_RTS/
USART2
_DE
ETH_MII_
RX_CLK/
OCTOSPI
M_P1_
DQS
TIM2_CH
TIM5_CH2
2
LPTIM3_
OUT
TIM15_
CH1N
UART4_
RX
OCTOSPI
M_P1_IO3 MCLK_B ETH_RMII_
REF_CLK
SAI4_
LCD_ EVENT
R2 OUT
PA1
-
-
TIM2_CH
TIM5_CH3
3
LPTIM4_
OUT
TIM15_
CH1
OCTOSPI USART2 SAI4_SCK
MDIOS_
MDIO
LCD_R EVENT
OUT
PA2
PA3
-
-
-
-
ETH_MDIO
-
-
M_P1_IO0
_TX
_B
1
OCTOSPI
M_P1_
CLK
TIM2_CH
TIM5_CH4
4
LPTIM5_
OUT
TIM15_
CH2
I2S6_
MCK
OCTOSPI USART2
M_P1_IO2 _RX
OTG_HS_
ULPI_D0
ETH_MII_
COL
LCD_B EVENT
OUT
-
LCD_B2
5
SPI1_
NSS/
I2S1_WS
DCMI_
HSYNC/
PSSI_DE
D1PWR
EN
TIM5_
ETR
SPI3_NSS USART2 SPI6_NSS
FMC_D8/
FMC_AD8
LCD_ EVENT
VSYNC OUT
PA4
PA5
-
-
-
-
-
-
-
-
-
/I2S3_WS
_CK
/I2S6_WS
TIM2_CH
1/TIM2_
ETR
SPI1_
SCK/
I2S1_CK
D2PWR
EN
TIM8_CH
1N
SPI6_SCK
/I2S6_CK
OTG_HS_
ULPI_CK
FMC_D9/ PSSI_D1 LCD_R EVENT
-
-
-
FMC_AD9
4
4
OUT
DCMI_
SPI1_
MISO/
I2S1_SDI
SPI6_
MISO/I2S6
_SDI
TIM8_
BKIN_
COMP12
TIM1_
BKIN_
COMP12
TIM1_
BKIN
TIM8_
BKIN
OCTOSPI
M_P1_IO3
TIM13_CH
1
MDIOS_
MDC
PIXCLK/ LCD_G EVENT
PSSI_
PDCK
PA6
PA7
-
-
TIM3_CH1
-
-
-
-
2
OUT
ETH_MII_
RX_DV/
SPI1_
MOSI/I2S
1_SDO
SPI6_
MOSI/I2S6
_SDO
TIM1_CH
1N
TIM8_CH
1N
TIM14_CH OCTOSPI
FMC_SDN
WE
LCD_ EVENT
VSYNC OUT
TIM3_CH2
-
-
1
M_P1_IO2 ETH_RMII_
CRS_DV
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
TIM8_
BKIN2_
COMP12
TIM1_CH
1
TIM8_
BKIN2
I2C3_
SCL
USART1
_CK
OTG_HS_
SOF
LCD_R EVENT
OUT
PA8
MCO1
-
-
-
-
I2C5_SCL
-
-
-
-
-
-
UART7_RX
LCD_B3
6
SPI2_
SCK/
I2S2_CK
DCMI_
D0/PSSI
_D0
TIM1_CH
2
LPUART
1_TX
I2C3_
SMBA
I2C5_
SMBA
USART1
_TX
ETH_TX_
ER
LCD_R EVENT
OUT
PA9
-
-
-
-
5
DCMI_
D1/PSSI
_D1
TIM1_CH
3
LPUART
1_RX
USART1
_RX
OTG_HS_
ID
MDIOS_
MDIO
LCD_B EVENT
OUT
PA10
-
-
-
-
LCD_B4
1
USART1
_CTS/
USART1
_NSS
SPI2_
NSS/
I2S2_WS
TIM1_CH
4
LPUART
1_CTS
UART4_
RX
FDCAN1_
RX
LCD_R EVENT
OUT
PA11
PA12
-
-
-
-
-
-
-
-
-
-
-
-
4
LPUART
1_RTS/
LPUART
1_DE
USART1
_RTS/
USART1
_DE
SPI2_
SCK/
I2S2_CK
TIM1_
ETR
UART4_
TX
SAI4_FS_ FDCAN1_
TIM1_
BKIN2
LCD_R EVENT
-
B
TX
5
OUT
JTMS/
SWDIO
EVENT
OUT
PA13
PA14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
JTCK/
SWCLK
EVENT
OUT
UART4_
RTS/
UART4_
DE
TIM2_
CH1/TIM2
_ETR
SPI1_
NSS/
I2S1_WS
SPI6_
NSS/
I2S6_WS
SPI3_NSS
/I2S3_WS
LCD_B EVENT
OUT
PA15
JTDI
-
-
CEC
LCD_R3
-
UART7_TX
-
-
6
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
OCTO
SPIM_P1
_IO1
TIM1_CH
2N
TIM8_CH
2N
DFSDM1_
CKOUT
UART4_
CTS
OTG_HS_
ULPI_D1
ETH_MII_
RXD2
LCD_G EVENT
OUT
PB0
-
-
TIM3_CH3
TIM3_CH4
SAI1_D1
-
-
-
-
-
-
LCD_R3
-
-
-
-
-
-
-
1
OCTO
SPIM_P1
_IO0
TIM1_CH
3N
TIM8_CH
3N
DFSDM1_
DATIN1
OTG_HS_
ULPI_D2
ETH_MII_
RXD3
LCD_G EVENT
PB1
PB2
-
LCD_R6
OCTO
0
OUT
SPI3_
MOSI/I2S
3_SDO
OCTO
SPIM_P1_ SPIM_P1_
RTC_
OUT
DFSDM1
_CKIN1
SAI1_SD_
A
SAI4_SD_
A
ETH_TX_
ER
TIM23_
ETR
EVENT
OUT
SAI4_D1
-
-
-
-
CLK
DQS
JTDO/
SPI1_
SCK/
I2S1_CK
TIM2_CH
2
SPI3_SCK
/I2S3_CK
SPI6_SCK SDMMC2_
/I2S6_CK
CRS_
SYNC
TIM24_ EVENT
PB3 TRACE
SWO
-
-
-
UART7_RX
UART7_TX
-
-
D2
ETR
OUT
SPI1_
MISO/
SPI3_
MISO/
SPI2_
NSS/
SPI6_
MISO/
NJT
PB4
TIM16_
BKIN
SDMMC2_
D3
EVENT
OUT
TIM3_CH1
-
-
RST
I2S1_SDI I2S3_SDI I2S2_WS I2S6_SDI
SPI1_
MOSI/I2S
1_SDO
SPI3_
MOSI/I2S MOSI/I2S6
3_SDO _SDO
SPI6_
DCMI_
D10/PSS
I_D10
TIM17_
BKIN
I2C1_
SMBA
I2C4_
SMBA
FDCAN2_ OTG_HS_ ETH_PPS_ FMC_SDC
UART5 EVENT
_RX OUT
PB5
PB6
-
-
TIM3_CH2 LCD_B5
RX
ULPI_D7
OUT
KE1
OCTO
SPIM_P1_
NCS
DCMI_
D5/PSSI
_D5
TIM16_
CH1N
I2C1_
SCL
USART1 LPUART1 FDCAN2_
DFSDM1_ FMC_SDN
UART5 EVENT
TIM4_CH1
TIM4_CH2
-
-
CEC
-
I2C4_SCL
I2C4_SDA
I2C4_SCL
_TX
_TX
TX
-
DATIN5
E1
_TX
OUT
DCMI_
VSYNC/
PSSI_
RDY
TIM17_
CH1N
I2C1_
SDA
USART1 LPUART1
_RX _RX
DFSDM1_
CKIN5
EVENT
OUT
PB7
-
-
FMC_NL
-
DCMI_
D6/PSSI
_D6
TIM16_C
H1
DFSDM1
_CKIN7
I2C1_
SCL
SDMMC1 UART4_
_CKIN RX
FDCAN1_ SDMMC2_ ETH_MII_ SDMMC1_
LCD_B EVENT
OUT
PB8
PB9
-
-
TIM4_CH3
TIM4_CH4
-
RX
D4
TXD3
D4
6
SPI2_
NSS/I2S I2C4_SDA
2_WS
DCMI_
D7/PSSI
_D7
TIM17_
CH1
DFSDM1
_DATIN7
I2C1_
SDA
SDMMC1 UART4_
FDCAN1_ SDMMC2_
TX D5
I2C4_
SMBA
SDMMC1_
D5
LCD_B EVENT
OUT
_CDIR
TX
7
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
SPI2_
SCK/
I2S2_CK
OCTO
SPIM_P1_
NCS
TIM2_CH
3
LPTIM2_
IN1
I2C2_
SCL
DFSDM1_ USART3
DATIN7 _TX
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER
LCD_G EVENT
OUT
PB10
-
-
-
-
-
-
-
-
-
4
ETH_MII_
TX_EN/
TIM2_CH
4
LPTIM2_
ETR
I2C2_
SDA
DFSDM1_ USART3
CKIN7 _RX
OTG_HS_
ULPI_D4 ETH_RMII_
TX_EN
LCD_G EVENT
OUT
PB11
PB12
PB13
-
-
-
5
ETH_MII_
TXD0/
OCTO
SPIM_P1
_NCLK
SPI2_
NSS/
I2S2_WS
TIM1_
BKIN_
COMP12
TIM1_BKI
N
I2C2_SM
BA
DFSDM1_ USART3
FDCAN2_ OTG_HS_
OCTOSPI
UART5 EVENT
_RX OUT
-
-
-
-
-
-
-
DATIN1
_CK
RX
ULPI_D5 ETH_RMII_ M_P1_IO0
TXD0
USART3
_CTS/
USART3
_NSS
ETH_MII_
TXD1/
OCTO
SPIM_P1
_IO2
SPI2_
SCK/
I2S2_CK
DCMI_
D2/PSSI
_D2
TIM1_CH
1N
LPTIM2_
OUT
DFSDM1_
CKIN1
FDCAN2_ OTG_HS_
SDMMC1_
D0
UART5 EVENT
_TX OUT
TX
ULPI_D6 ETH_RMII_
TXD1
USART3
_RTS/
USART3
_DE
SPI2_
MISO/
I2S2_SDI
UART4_
RTS/UAR
T4_DE
FMC_D10/
FMC_
AD10
TIM1_CH TIM12_CH TIM8_CH USART1
2N 2N _TX
DFSDM1_
DATIN2
SDMMC2_
D0
LCD_C EVENT
LK OUT
PB14
PB15
-
-
-
-
-
-
1
SPI2_
MOSI/I2S
2_SDO
FMC_D11/
FMC_AD1
1
RTC_
REFIN
TIM1_CH TIM12_CH TIM8_CH USART1
3N 3N _RX
DFSDM1_
CKIN2
UART4_ SDMMC2_
CTS D1
LCD_G EVENT
OUT
-
2
7
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
FMC_D12
/FMC_AD
12
DFSDM1
_CKIN0
DFSDM1_
DATIN4
SAI4_FS_
B
OTG_HS_
ULPI_STP
FMC_SDN
WE
LCD_R EVENT
OUT
PC0
-
-
-
-
-
-
-
-
FMC_A25
LCD_G2
-
-
-
-
5
SPI2_
MOSI/I2S
2_SDO
OCTO
SPIM_P1_ ETH_MDC
IO4
TRACE
D0
DFSDM1 DFSDM1
_DATIN0 _CKIN4
SAI1_SD_
A
SAI4_SD_ SDMMC2_
MDIOS_
MDC
LCD_G EVENT
PC1
PC2
PC3
SAI4_D1
SAI1_D1
A
CK
5
OUT
PWR_
DEEP
SLEEP
OCTO
SPIM_P1 MISO/I2S
_IO5
SPI2_
DFSDM1
_CKIN1
DFSDM1_
CKOUT
OCTOSPI OTG_HS_
M_P1_IO2 ULPI_DIR
ETH_MII_ FMC_SDN
TXD2 E0
EVENT
OUT
-
-
-
-
-
-
2_SDI
OCTO
SPIM_P1 MOSI/I2S
_IO6
SPI2_
PWR_
SLEEP
DFSDM1
_DATIN1
OCTOSPI OTG_HS_
M_P1_IO0 ULPI_NXT
ETH_MII_ FMC_SDC
EVENT
OUT
-
-
-
-
-
-
TX_CLK
KE0
2_SDO
ETH_MII_
PWR_
DEEP
SLEEP
DFSDM1
_CKIN2
I2S1_
MCK
SPDIFRX1 SDMMC2_ RXD0/ETH FMC_SDN
LCD_R EVENT
OUT
PC4
FMC_A22
-
-
-
-
-
_IN3
CKIN
_RMII_RXD
0
E0
7
OCTOSPI ETH_MII_R
M_P1_DQ XD1/ETH_
PWR_
SLEEP
DFSDM1 PSSI_D1
_DATIN2
SPDIFRX1
_IN4
FMC_SDC COMP1_ LCD_D EVENT
PC5
PC6
PC7
SAI4_D3
SAI1_D3
TIM3_CH1
TIM3_CH2
-
-
-
5
KE0
OUT
E
OUT
S
RMII_RXD1
DCMI_
D0/PSSI
_D0
TIM8_CH DFSDM1
_CKIN3
I2S2_
MCK
USART6 SDMMC1_
_TX D0DIR
FMC_
NWAIT
SDMMC2_
D6
SDMMC1_
D6
LCD_H EVENT
SYNC OUT
-
-
-
-
1
DCMI_
D1/PSSI
_D1
DB
TRGIO
TIM8_CH DFSDM1
I2S3_
MCK
USART6 SDMMC1_
SDMMC2_
D7
SDMMC1_
D7
LCD_G EVENT
-
-
FMC_NE1
SWPMI_TX
2
_DATIN3
-
_RX
D123DIR
6
OUT
UART5_
RTS/
UART5_
DE
FMC_NE2
/FMC_
NCE
DCMI_
D2/PSSI
_D2
TRACE
D1
TIM8_CH
3
USART6
_CK
SDMMC1_
D0
EVENT
OUT
PC8
-
TIM3_CH3
-
FMC_INT SWPMI_RX
-
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
OCTO
SPIM_P1_
IO0
DCMI_D
3/PSSI_
D3
TIM8_CH
4
I2C3_
SDA
I2S_
CKIN
UART5_C
TS
SWPMI_
SUSPEND
SDMMC1_
D1
LCD_B EVENT
OUT
PC9
MCO2
-
-
-
TIM3_CH4
I2C5_SDA
-
LCD_G3
2
OCTO
SPIM_P1_
IO1
DCMI_D
8/PSSI_
D8
DFSDM1
_CKIN5
I2C5_
SDA
SPI3_SCK USART3
/I2S3_CK
UART4_
TX
SDMMC1_
D2
LCD_R EVENT
OUT
PC10
PC11
PC12
-
-
-
-
-
-
LCD_B1
SWPMI_RX
_TX
2
SPI3_
MISO/
I2S3_SDI
OCTO
SPIM_P1_
NCS
DCMI_
D4/PSSI
_D4
DFSDM1
_DATIN5
I2C5_
SCL
USART3
_RX
UART4_
RX
SDMMC1_
D3
LCD_B EVENT
OUT
-
-
-
-
4
SPI6_
SCK/
I2S6_CK I2S3_SDO
SPI3_
MOSI/
DCMI_
D9/PSSI
_D9
TRACE FMC_D6/ TIM15_CH
D3
I2C5_
SMBA
USART3
_CK
UART5_
TX
SDMMC1_
CK
LCD_R EVENT
-
-
FMC_AD6
1
6
OUT
EVENT
OUT
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
EVENT
OUT
-
-
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
DFSDM1
_CKIN6
UART4_
RX
FDCAN1_
RX
UART9_
CTS
FMC_D2/
FMC_AD2
LCD_B EVENT
PD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
OUT
DFSDM1
_DATIN6
UART4_
TX
FDCAN1_
TX
FMC_D3/
FMC_AD3
EVENT
OUT
PD1
PD2
-
-
-
DCMI_
D11/PSSI
_D11
TRACE FMC_D7/
D2
TIM3_
ETR
TIM15_
BKIN
UART5_
RX
SDMMC1_
CMD
LCD_B EVENT
OUT
-
-
-
-
-
LCD_B7
-
-
FMC_AD7
2
USART2
_CTS/
USART2
_NSS
SPI2_
SCK/
I2S2_CK
DCMI_
DFSDM1
_CKOUT
LCD_G EVENT
PD3
PD4
-
-
-
-
-
-
-
-
FMC_CLK D5/PSSI
_D5
7
OUT
USART2
_RTS/
USART2
_DE
OCTOSPI
M_P1_IO4
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NOE
FMC_NWE
-
-
-
USART2
_TX
OCTOSPI
M_P1_IO5
EVENT
OUT
PD5
PD6
-
-
-
-
-
-
-
-
SPI3_
MOSI/I2S
3_SDO
OCTO
SPIM_P1_
IO6
DCMI_D
10/PSSI_
D10
DFSDM1 DFSDM1
_CKIN4 _DATIN1
SAI1_SD_ USART2 SAI4_SD_
SDMMC2_
CK
FMC_
NWAIT
LCD_B EVENT
SAI4_D1
SAI1_D1
A
_RX
A
2
OUT
SPI1_
MOSI/I2S
1_SDO
OCTO
SPIM_P1_
IO7
DFSDM1
-
DFSDM1_ USART2
SPDIFRX1
_IN1
SDMMC2_
CMD
EVENT
OUT
PD7
PD8
-
-
-
-
-
-
-
FMC_NE1
-
-
-
_DATIN4
CKIN1
_CK
FMC_D13/
FMC_
AD13
DFSDM1
-
USART3
_TX
SPDIFRX1
_IN2
EVENT
OUT
-
-
-
-
-
-
_CKIN3
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
FMC_D14/
FMC_AD1
4
DFSDM1
_DATIN3
USART3
_RX
EVENT
OUT
PD9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D15/
FMC_AD1
5
DFSDM1
_CKOUT
USART3
_CK
LCD_B EVENT
PD10
PD11
3
OUT
USART3
_CTS/
USART3
_NSS
LPTIM2_I I2C4_SM
OCTOSPI SAI4_SD_
M_P1_IO0
FMC_A16/
FMC_CLE
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N2
BA
A
USART3
_RTS/
USART3
_DE
OCTO
SPIM_P1_
IO1
DCMI_
D12/PSS
I_D12
LPTIM1_
IN1
LPTIM2_
IN1
I2C4_
SCL
FDCAN3
_RX
SAI4_FS_
A
FMC_A17/
FMC_ALE
EVENT
OUT
PD12
TIM4_CH1
-
DCMI_
D13/
PSSI_
D13
OCTO
SPIM_P1_
IO3
UART9_
RTS/
UART9_DE
LPTIM1_
OUT
I2C4_
SDA
FDCAN3
_TX
SAI4_
SCK_A
EVENT
OUT
PD13
PD14
PD15
-
-
-
TIM4_CH2
TIM4_CH3
TIM4_CH4
-
-
-
-
-
-
-
-
-
FMC_A18
-
-
-
UART8_
CTS
FMC_D0/
FMC_AD0
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
UART9_RX
UART9_TX
-
UART8_
RTS/
UART8_
DE
FMC_D1/
FMC_AD1
EVENT
OUT
-
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
DCMI_
D2/PSSI
_D2
LPTIM1_
ETR
TIM4_
ETR
LPTIM2_
ETR
UART8_
RX
SAI4_
MCLK_A
FMC_NBL
0
LCD_R EVENT
OUT
PE0
-
-
-
-
-
-
-
-
-
-
-
-
-
0
DCMI_
D3/
PSSI_D3
LPTIM1_
IN2
UART8_
TX
FMC_NBL
1
LCD_R EVENT
PE1
-
-
-
-
6
OUT
TRACE
CLK
SAI1_
CK1
USART1
0_RX
SPI4_
SCK
SAI1_
MCLK_A
SAI4_
MCLK_A M_P1_IO2
OCTOSPI
ETH_MII_
TXD3
EVENT
OUT
PE2
PE3
-
-
-
-
-
-
SAI4_CK1
-
FMC_A23
FMC_A19
-
-
TRACE
D0
TIM15_
BKIN
SAI1_SD_
B
SAI4_SD_
USART10_
TX
EVENT
OUT
-
-
-
-
-
B
DCMI_
FMC_A20 D4/PSSI
_D4
TRACE
D1
DFSDM1 TIM15_ SPI4_NS SAI1_FS_
SAI4_FS_
LCD_B EVENT
OUT
PE4
PE5
PE6
PE7
PE8
-
-
SAI1_D2
-
-
-
-
SAI4_D2
-
_DATIN3
CH1N
S
A
A
0
DCMI_
FMC_A21 D6/PSSI
_D6
TRACE
D2
DFSDM1 TIM15_
SPI4_
MISO
SAI1_SCK
_A
SAI4_SCK
LCD_G EVENT
OUT
SAI1_CK2
-
SAI4_CK2
SAI4_
-
_CKIN3
CH1
_A
0
DCMI_
FMC_A22 D7/PSSI
_D7
TRACE
D3
TIM1_
BKIN2
TIM15_
CH2
SPI4_
MOSI
SAI1_SD_
A
SAI4_SD_
SAI4_D1
A
TIM1_BKIN
LCD_G EVENT
SAI1_D1
-
MCLK_B 2_COMP12
1
OUT
OCTO
SPIM_P1_
IO4
TIM1_ET
R
DFSDM1
_DATIN2
UART7_
RX
FMC_D4/
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_AD4
OCTO
SPIM_P1_
IO5
TIM1_CH
1N
DFSDM1
_CKIN2
UART7_
TX
FMC_D5/ COMP2_
EVENT
OUT
-
-
FMC_AD5
OUT
UART7_
RTS/
UART7_
DE
OCTO
SPIM_P1_
IO6
TIM1_CH
1
DFSDM1
_CKOUT
FMC_D6/
FMC_AD6
EVENT
OUT
PE9
-
-
-
-
-
-
-
-
-
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
OCTO
SPIM_P1_
IO7
TIM1_CH
2N
DFSDM1
_DATIN4
UART7_
CTS
FMC_D7/
FMC_AD7
EVENT
OUT
PE10
-
-
-
-
-
-
-
-
-
-
-
OCTO
SPIM_P1_
NCS
TIM1_CH
2
DFSDM1
_CKIN4
SPI4_
NSS
SAI4_SD_
B
FMC_D8/
FMC_AD8
LCD_G EVENT
OUT
PE11
PE12
PE13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
TIM1_CH
3N
DFSDM1
_DATIN5
SPI4_
SCK
SAI4_SCK
_B
FMC_D9/ COMP1_ LCD_B EVENT
FMC_AD9
-
-
OUT
4
OUT
FMC_D10/
FMC_
AD10
TIM1_CH
3
DFSDM1
_CKIN5
SPI4_
MISO
SAI4_FS_
B
COMP2_
OUT
LCD_ EVENT
DE OUT
FMC_D11/
FMC_
AD11
TIM1_CH
4
SPI4_
MOSI
SAI4_
MCLK_B
LCD_ EVENT
CLK OUT
PE14
PE15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D12/
FMC_
AD12
TIM1_
BKIN_
COMP12
TIM1_
BKIN
USART10_
CK
LCD_ EVENT
R7 OUT
-
-
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
OCTO
SPIM_P2_
IO0
I2C2_
SDA
TIM23_
CH1
EVENT
OUT
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C5_SDA
I2C5_SCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A0
FMC_A1
FMC_A2
FMC_A3
FMC_A4
FMC_A5
-
-
-
-
-
-
-
-
-
OCTO
SPIM_P2_
IO1
I2C2_
SCL
TIM23_
CH2
EVENT
OUT
PF1
PF2
PF3
PF4
PF5
PF6
PF7
OCTO
SPIM_P2_
IO2
I2C2_
SMBA
I2C5_
SMBA
TIM23_
CH3
EVENT
OUT
OCTO
SPIM_P2_
IO3
TIM23_
CH4
EVENT
OUT
-
-
-
-
-
-
-
-
OCTO
SPIM_P2_
CLK
EVENT
OUT
-
-
OCTO
SPIM_P2_
NCLK
EVENT
OUT
OCTO
SPIM_P1_
IO3
TIM16_
CH1
FDCAN3_
RX
SPI5_
NSS
SAI1_SD_ UART7_ SAI4_SD_
TIM23_
CH1
EVENT
OUT
-
-
B
RX
B
OCTO
SPIM_P1_
IO2
TIM17_
CH1
FDCAN3_
TX
SPI5_
SCK
SAI1_
MCLK_B
UART7_
TX
SAI4_
MCLK_B
TIM23_
CH2
EVENT
OUT
-
UART7_
RTS/
UART7_
DE
OCTO
SPIM_P1_
IO0
TIM16_
CH1N
SPI5_
MISO
SAI1_SCK
_B
SAI4_SCK TIM13_CH
_B
TIM23_
CH3
EVENT
OUT
PF8
PF9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
OCTO
SPIM_P1_
IO1
TIM17_
CH1N
SPI5_
MOSI
SAI1_FS_ UART7_ SAI4_FS_ TIM14_CH
CTS
TIM23_
CH4
EVENT
OUT
B
B
1
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
OCTO
SPIM_P1_ SAI4_D3
CLK
DCMI_
D11/PSSI
_D11
TIM16_BK
IN
PSSI_
D15
LCD_D EVENT
OUT
PF10
-
-
-
SAI1_D3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E
OCTO
SAI4_SD_
SPIM_P1_
B
DCMI_
D12/PSS
I_D12
SPI5_
MOSI
FMC_
NRAS
TIM24_ EVENT
CH1 OUT
PF11
PF12
-
-
-
-
-
-
NCLK
OCTO
SPIM_P2_
DQS
TIM24_ EVENT
CH2 OUT
-
-
FMC_A6
-
DFSDM1
_DATIN6
I2C4_
SMBA
TIM24_ EVENT
CH3 OUT
PF13
PF14
PF15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A7
FMC_A8
FMC_A9
-
-
-
DFSDM1
_CKIN6
I2C4_
SCL
TIM24_ EVENT
CH4
OUT
I2C4_
SDA
EVENT
OUT
-
-
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
SAI4/
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
SDMMC2/ 8/UART7/9/
TIM8
USART10
OCTO
SPIM_P2_
IO4
EVENT
OUT
PG0
-
-
-
-
-
-
-
-
-
-
-
UART9_RX FMC_A10
UART9_TX FMC_A11
-
-
-
OCTO
SPIM_P2_
IO5
EVENT
OUT
PG1
PG2
PG3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_
BKIN
TIM8_BKIN
FMC_A12
_COMP12
TIM24_ EVENT
-
-
ETR
OUT
TIM8_
TIM8_
BKIN2
TIM23_
ETR
EVENT
OUT
BKIN2_
FMC_A13
-
COMP12
TIM1_
BKIN2_
COMP12
TIM1_BKI
N2
FMC_A14/
FMC_BA0
EVENT
OUT
PG4
PG5
PG6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_
ETR
FMC_A15/
FMC_BA1
EVENT
OUT
-
-
-
OCTO
SPIM_P1_
NCS
DCMI_D
TIM17_
BKIN
LCD_R EVENT
OUT
FMC_NE3 12/PSSI_
D12
7
OCTO
SPIM_P2_
DQS
DCMI_D
FMC_INT 13/PSSI_
D13
SAI1_
MCLK_A
USART6
_CK
LCD_ EVENT
CLK OUT
PG7
PG8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART6
_RTS/
USART6
_DE
SPI6_
NSS/I2S
6_WS
TIM8_
ETR
SPDIFRX1
_IN3
ETH_PPS_
OUT
FMC_
-
LCD_G EVENT
-
-
-
SDCLK
7
-
OUT
DCMI_
SPI1_
MISO/I2S
1_SDI
OCTO
SPIM_P1_
IO6
FDCAN3_
TX
USART6 SPDIFRX1
_RX _IN4
SAI4_FS_ SDMMC2_ FMC_NE2/ VSYNC/
EVENT
OUT
PG9
-
-
-
-
B
D0
FMC_NCE
PSSI_
RDY
Table 8. STM32H723 pin alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
CEC/
DCMI/
PSSI/
CRS/
FMC/
LCD/
DFSDM1/
ETH/I2C4/
LCD/MDIO
S/OCTOSP
IM_P1/
FDCAN1/2
/FMC/
LCD/
DFSDM1
/LCD/
DFSDM1/I SDMMC1
CEC/
LPUART1/
SAI4/
SDMMC1/
SPDIFRX1 SPIM_P1/
/SPI6/ 2/SAI4/
UART4/5/ SDMMC2/
FMC/LCD/
MDIOS/
OCTOSPI
M_P1/
SDMMC1/
TIM1x/
DFSDM1
2C4/5/
OCTO
SPIM_P1/
SAI1/
SPI3/
I2S3/
/SPI2/I2S
2/SPI3/
I2S3/
COMP/
DCMI/
PSSI/
LCD/
TIM1x/
TIM23
FMC/
LPTIM1/
SAI4/TIM1
6/17/TIM1 TIM3/4/5/1
x/TIM2x
FDCAN3/
PDM_
SAI1/
FDCAN3/
SPI1/I2S
1/SPI2/
I2S2/SPI
3/I2S3/
LPTIM2/ /I2C1/2/3/
3/4/5/ 4/5/
LPUART LPTIM2/
1/OCTO OCTO
SPIM_P1 SPIM_P1
OCTO
SPIM_P1/
OTG1_FS/ SDMMC2/
OTG1_HS/ SWPMI1/
SAI4/
SDMMC2/ 8/UART7/9/
TIM8 USART10
Port
OCTO
LCD/
TIM24/
UART5
SYS
SPI6/
UART7/
USART1/
2/3/6
2/15
TIM1x/TIM
SPI4/5/6
8
SPDIFRX1
/TIM13/14
TIM8
/2/TIM8
/TIM15/
USART1/
10
UART4
OCTO
SPIM_P2
_IO6
SPI1_
NSS/I2S
1_WS
DCMI_
FMC_NE3 D2/PSSI
_D2
FDCAN3_
RX
SAI4_SD_ SDMMC2_
LCD_B EVENT
OUT
PG10
-
-
-
-
-
-
-
-
-
LCD_G3
B
D1
2
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
SPI1_
SCK/I2S
1_CK
OCTO
SPIM_P2_
IO7
DCMI_
D3/PSSI
_D3
LPTIM1_
IN2
USART1
0_RX
SPDIFRX1
_IN1
SDMMC2_
D2
LCD_B EVENT
OUT
PG11
PG12
PG13
PG14
PG15
-
-
-
-
-
-
-
3
USART6
_RTS/
USART6
_DE
ETH_MII_
SDMMC2_ TXD1/ETH
OCTO
SPIM_P2
_NCS
SPI6_
MISO/I2S
6_SDI
LPTIM1_
IN1
USART1
0_TX
SPDIFRX1
_IN2
TIM23_
CH1
LCD_B EVENT
OUT
-
-
-
-
-
LCD_B4
FMC_NE4
FMC_A24
FMC_A25
D3
_RMII_TXD
1
1
USART1
0_CTS/
USART1
0_NSS
USART6
_CTS/
USART6
_NSS
ETH_MII_
SDMMC2_ TXD0/ETH
SPI6_
SCK/I2S
6_CK
TRACE LPTIM1_
D0 OUT
TIM23_
CH2
LCD_R EVENT
OUT
-
-
-
-
-
-
-
D6
_RMII_TXD
0
0
USART1
0_RTS/
USART1
0_DE
ETH_MII_
SDMMC2_ TXD1/ETH
SPI6_
MOSI/I2S
6_SDO
OCTO
SPIM_P1_
IO7
TRACE LPTIM1_
D1
USART6
_TX
TIM23_
CH3
LCD_B EVENT
ETR
D7
_RMII_TXD
1
0
OUT
USART6
_CTS/
USART6
_NSS
OCTO
SPIM_P2_
DQS
DCMI_D
13/PSSI_
D13
USART10_ FMC_NCA
EVENT
OUT
-
-
-
-
-
-
CK
S
EVENT
OUT
PH0
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
Electrical characteristics
STM32H723xE/G
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at T = 25 °C and T = T (given by the
J
J
Jmax
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
J
DD
1.7 V ≤ V
tested.
≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8. Pin loading conditions
Figure 9. Pin input voltage
MCU pin
MCU pin
V
C =50 pF
IN
MS19011V2
MS19010V2
86/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
6.1.6
Power supply scheme
Figure 10. Power supply scheme
VCAP
Core domain (VCORE
)
LDO
voltage
regulator
VDDLDO
VSS
D3 domain
(System
logic,
D1 domain
(CPU, peripherals,
RAM)
D2 domain
(peripherals,
RAM)
EXTI,
IO
logic
IOs
Peripherals,
RAM)
Flash
VSS
VDD domain
HSI, CSI,
VDD
Power
switch
HSI48,
HSE, PLLs
VBAT
charging
Backup domain
Backup
regulator
VSW
VBKP
VBAT
Power switch
LSI, LSE, RTC,
Wakeup logic,
backup
Backup
RAM
BKUP
IOs
IO
logic
registers, Reset
VSS
VSS
VDD33USB
VDDA
USB
FS IOs
Analog domain
REF_BUF
ADC, DAC
VREF+
OPAMP,
Comparator
VREF+
VREF-
VREF-
VSSA
1. Refer to application note AN5419 “Getting started with STM32H723/733, STM32H725/735 and
STM32H730 Value Line hardware development“ for the possible power scheme and connected capacitors.
DS13313 Rev 2
87/227
208
Electrical characteristics
STM32H723xE/G
6.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
LDO ON
IDD_VBAT
VBAT
IDD
VDD
VDDLDO
VDDA
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 9: Voltage characteristics,
Table 10: Current characteristics, and Table 11: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
Table 9. Voltage characteristics
Symbols
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
(1)
VDDX - VSS
−0.3
4.0
V
VDDLDO, VDDA, VDD33USB, VBAT
)
Min(VDD, VDDA
,
Input voltage on FT_xxx pins
VSS−0.3
V
DD33USB, VBAT
)
V
+4.0(3)(4)
(2)
VIN
Input voltage on TT_xx pins
Input voltage on BOOT0 pin
Input voltage on any other pins
V
SS−0.3
4.0
9.0
4.0
V
V
V
VSS
VSS-0.3
-
Variations between different VDDX power
pins of the same domain
|ꢀVDDX
|
50
50
mV
mV
Variations between all the different ground
pins
|VSSx-VSS
|
-
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
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DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 10. Current characteristics
Ratings
Symbols
Max
Unit
ΣIVDD
ΣIVSS
IVDD
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin, except Px_C
Output current sunk by Px_C pins
620
620
100
100
20
IVSS
IIO
1
mA
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
140
140
ΣI(PIN)
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
(3)(4)
IINJ(PIN)
Injected current on PA4, PA5
−0/0
ΣIINJ(PIN)
Total injected current (sum of all I/Os and control pins)(5)
±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 9: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 11. Thermal characteristics
Symbol
Ratings
Storage temperature range
Value
Unit
TSTG
− 65 to +150
°C
Maximum junction
temperature
TJ
Industrial temperature range 6
125
DS13313 Rev 2
89/227
208
Electrical characteristics
STM32H723xE/G
6.3
Operating conditions
6.3.1
General operating conditions
Table 12. General operating conditions
Operating
conditions
Symbol
Parameter
Min
Typ
Max
Unit
-
VDD
Standard operating voltage
-
1.62(1)
1.62(1)
3.6
3.6
Supply voltage for the internal
regulator
VDDLDO
VDDLDO ≤ VDD
-
USB used
3.0
0
-
-
-
-
-
-
3.6
3.6
Standard operating voltage, USB
domain
VDD33USB
USB not used
ADC or COMP used
DAC used
1.62
1.8
2.0
1.8
OPAMP used
VREFBUF used
VDDA
Analog operating voltage
3.6
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
0
-
V
TT_xx I/O
BOOT0
−0.3
-
-
VDD+0.3
9
0
Min(VDD
VDDA
VDD33USB
+3.6V <
5.5V(2)
,
VIN
I/O Input voltage
,
All I/O except BOOT0
and TT_xx
−0.3
-
)
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
0.95
1.05
1.15
1.30
0.98
1.08
1.18
1.33
1.0
1.05
1.15
1.26
1.40
1.08
1.18
1.28
1.40
1.10
1.21
1.36
1.03
1.13
1.23
1.38
Internal regulator ON (LDO)(3)
VCORE
V
Regulator OFF: external VCORE
voltage must be supplied from
external regulator on VCAP pins
90/227
DS13313 Rev 2
STM32H723xE/G
Symbol
Electrical characteristics
Table 12. General operating conditions (continued)
Operating
conditions
Parameter
Min
Typ
Max
Unit
VOS3
-
-
-
-
-
-
-
-
170
300
400
520
VOS2
VOS1
VOS0
fCPU
Arm® Cortex®-M7 clock frequency
VOS0 and
CPU_FREQ_BOOST
-
-
550
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85
150
200
275
85
fACLK
fHCLK
fPCLK
AXI clock frequency
AHB clock frequency
APB clock frequency
MHz
150
200
275
42.5(4)
75
100
137.5
Ambient temperature for
temperature range 3
Maximum power
dissipation
−40
−40
−40
125
85
Maximum power
dissipation
(5)
TA
°C
Ambient temperature for
temperature range 6
Low-power
105
dissipation(6)
1. When RESET is released, the functionality is guaranteed down to VPDRmax or down to the specified VDDmin when the PDR
is OFF. The PDR can only be switched OFF though the PDR_ON pin that not available in all packages.
2. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table.
3. At startup, the external VCORE voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO).
4. This value corresponds to the maximum APB clock frequency when at least one peripheral is enabled.
5. The device junction temperature must be kept below maximum TJ indicated in Table 13: Supply voltage and maximum
temperature configuration and the maximum temperature.
6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5:
Thermal characteristics).
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
Table 13. Supply voltage and maximum temperature configuration
Power scale
VCORE source
Max. TJ (°C)
Min. VDD(V)
Min. VDDLDO (V)
LDO
External (Bypass)
LDO
1.7
1.62
1.62
-
1.7
VOS0
105
-
1.62
VOS1
125
125
External (Bypass)
LDO
-
1.62
-
1.62
VOS2 or VOS3
External (bypass)
-
2
125
105
125
2
LDO
SVOS4/SVOS5
1.62
1.62
1.62
-
External (Bypass)
6.3.2
VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
to
EXT
the VCAP pin. C
VCAP pins.
is specified in Table 14. Two external capacitors can be connected to
EXT
Figure 12. External capacitor C
EXT
C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
(1)
Table 14. VCAP operating conditions
Parameter
Symbol
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF(2)(3)
< 100 mΩ
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
3. If a third VCAP pin is available on the package, it must be connected to the other VCAP pins but no
additional capacitor is required.
92/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
6.3.3
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 15. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
Min
Max
Unit
0
10
0
∞
∞
∞
∞
∞
∞
tVDD
VDD fall time rate
VDDA rise time rate
tVDDA
µs/V
V
DDA fall time rate
VDDUSB rise time rate
DDUSB fall time rate
10
0
tVDDUSB
V
10
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
6.3.4
Embedded reset and power control block characteristics
The parameters given in Table 16 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 12: General operating
DD
conditions.
Table 16. Reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset temporization
after BOR0 released
(1)
tRSTTEMPO
-
-
377
550
µs
Rising edge(1)
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge in Run mode
1.62
1.58
2.04
1.95
2.34
2.25
2.63
2.54
1.90
1.81
2.05
1.96
2.19
2.10
2.35
2.25
2.49
2.39
2.64
2.55
2.78
2.69
1.67
1.62
2.10
2.00
2.41
2.31
2.70
2.61
1.96
1.86
2.10
2.01
2.26
2.15
2.41
2.31
2.56
2.45
2.71
2.61
2.86
2.76
1.71
1.68
2.15
2.06
2.47
2.37
2.78
2.68
2.01
1.91
2.16
2.06
2.32
2.21
2.47
2.37
2.62
2.51
2.78
2.68
2.94
2.83
Power-on/power-downreset
threshold
VPOR/PDR
VBOR1
VBOR2
VBOR3
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
Programmable Voltage
Detector threshold 0
Programmable Voltage
Detector threshold 1
V
Programmable Voltage
Detector threshold 2
Programmable Voltage
Detector threshold 3
Programmable Voltage
Detector threshold 4
Programmable Voltage
Detector threshold 5
Programmable Voltage
Detector threshold 6
VPVD6
Hysteresis voltage for
Power-on/power-downreset
VPOR/PDR
Hysteresis in Run mode
-
-
-
43.00
100
-
-
-
mV
µA
Vhyst_BOR_PVD Hysteresis voltage for BOR
Hysteresis in Run mode
-
BOR and PVD consumption
from VDD
(1)
IDD_BOR_PVD
0.630
POR and PVD consumption
from VDD
IDD_POR_PVD
-
0.8
-
1.200
94/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Table 16. Reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.66
1.56
2.06
1.96
2.42
2.35
2.74
2.64
1.71
1.61
2.12
2.02
2.50
2.42
2.83
2.72
1.76
1.66
2.19
2.08
2.58
2.49
2.91
2.80
Analog voltage detector for
VDDA threshold 0
VAVM_0
Analog voltage detector for
VDDA threshold 1
VAVM_1
VAVM_2
VAVM_3
V
Analog voltage detector for
VDDA threshold 2
Analog voltage detector for
VDDA threshold 3
Hysteresis of VDDA voltage
detector
Vhyst_VDDA
IDD_PVM
-
-
-
-
100
-
mV
µA
µA
PVM consumption from
VDD(1)
-
-
-
0.25
2.5
Voltage detector
consumption on VDDA
IDD_VDDA
Resistor bridge
(1)
1. Guaranteed by design.
6.3.5
Embedded reference voltage characteristics
The parameters given in Table 17 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 12: General operating
DD
conditions.
Table 17. Embedded reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference voltages
-40°C < TJ < TJmax
1.180
1.216
1.255
V
ADC sampling time when
reading the internal reference
voltage
(1)(2)
tS_vrefint
-
-
4.3
9
-
-
-
-
(3)
VBAT sampling time when
reading the internal VBAT
reference voltage
µs
(2)
tS_vbat
Start time of reference voltage
buffer when ADC is enable
(2)
tstart_vrefint
-
-
-
4.4
23
Reference Buffer
consumption for ADC
(2)
Irefbuf
VDD = 3.3 V
9
13.5
µA
Internal reference voltage
spread over the temperature
range
(2)
ΔVREFINT
-40°C < TJ < TJmax
-
5
15
mV
Average temperature
coefficient
Average temperature
coefficient
(2)
Tcoeff
-
-
20
10
70
ppm/°C
ppm/V
(2)
VDDcoeff
Average Voltage coefficient
3.0 V < VDD < 3.6 V
1370
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
Table 17. Embedded reference voltage (continued)
Symbol
Parameter
Conditions
Min
Typ
25
Max
Unit
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
-
-
-
-
-
-
-
-
-
%
50
VREFINT
75
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
3. Guaranteed by design. and tested in production at 3.3 V.
Table 18. Internal reference voltage calibration values
Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1 E860 - 1FF1 E861
Symbol
6.3.6
Embedded USB regulator characteristics
The parameters given in Table 19 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 12: General operating
DD
conditions.
Table 19. USB regulator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VREGOUTV33V
Regulated output voltage
-
3
-
3.6
V
Output current load sinked by
USB block
IOUT
-
-
-
-
-
20
mA
us
TWKUP
Wakeup time
120
170
6.3.7
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
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DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode.
All peripherals are disabled except when explicitly mentioned.
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (f
) frequency and V
range” available in the reference manual).
rcc_c_ck
CORE
•
When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in the below tables are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 12: General operating
conditions.
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
Table 20. Typical and maximum current consumption in Run mode,
(1)
code with data processing running from ITCM
Max(2)
TJ =
frcc_c_ck
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TJ =
TJ =
TJ =
25 °C
85 °C
105 °C
125 °C
550
520
520
480
450
400
400
300
300
280
216
200
170
168
144
60
145
135
135
125
115
105
90.5
69.5
63
170
160
160
150
150
130
110
84
260
260
260
250
240
230
170
150
130
120
110
110
80
330
320
320
310
300
290
220
200
170
160
150
140
110
110
110
90
-
VOS0(3)
-
-
-
VOS0
VOS1
VOS2
-
-
280
260
220
210
200
200
160
160
150
140
130
-
All
peripherals
disabled
74
58
69
45.5
42
56
53
Supply
current in
Run mode
32.5
32
40
IDD
mA
40
79
VOS3
28
36
75
13.5
6.9
21
61
25
14
54
83
550
520
520
400
400
300
300
280
170
215
205
205
160
135
105
95
250
240
240
190
160
130
110
100
58
360
350
350
300
230
200
170
160
110
430
420
420
370
290
250
210
210
140
VOS0
(3)
-
-
VOS0
VOS1
-
All
peripherals
enabled
360
330
280
270
190
VOS2
VOS3
88
49
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. Guaranteed by characterization results, unless otherwise specified.
3. CPU_FREQ_BOOST is enabled.
98/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Table 21. Typical and maximum current consumption in Run mode, code with data processing
(1)
running from Flash memory, cache ON
Max(2)
frcc_c_ck
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TJ =
TJ =
TJ =
TJ =
25 °C
85 °C
105 °C
125 °C
550
520
520
400
400
300
300
280
216
200
180
170
168
144
60
145
140
140
110
92
170
170
170
140
110
86
270
260
260
230
180
150
130
120
-
330
320
320
290
220
200
170
160
-
-
VOS0(3)
-
-
VOS0
VOS1
-
290
260
220
210
-
71
64
75
All
59
70
peripherals
disabled
VOS2
VOS3
46.5
42.5
36
-
53
110
83
140
120
110
-
200
160
160
-
43
33.5
33
41
81
Supply
current in Run
mode
IDD
-
-
mA
29
-
-
-
-
14
-
-
-
-
25
6.85
220
210
210
160
140
105
96
-
-
-
-
550
520
520
400
400
300
300
280
170
250
240
240
190
160
130
110
110
59
360
350
350
300
240
200
170
160
110
430
420
420
370
290
250
210
210
140
-
VOS0
(3)
-
-
VOS0
VOS1
-
All
peripherals
enabled
360
330
280
270
190
VOS2
VOS3
89
50
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. Guaranteed by characterization results, unless otherwise specified.
3. CPU_FREQ_BOOST is enabled.
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
Table 22. Typical and maximum current consumption in Run mode,
(1)
code with data processing running from Flash memory, cache OFF
frcc_c_ck
(MHz)
Typ
Symbol
Parameter
Conditions
Unit
550
520
520
400
400
300
300
280
170
550
520
520
400
400
300
300
280
170
99
95
VOS0(2)
VOS0
95
76.5
66.5
51.5
47.5
43.5
24.5
170
165
165
130
115
87
All peripherals
disabled
VOS1
VOS2
VOS3
Supply current
in Run mode
IDD
mA
VOS0(2)
VOS0
VOS1
All peripherals
enabled
79
VOS2
VOS3
73.5
41
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this
case.
2. CPU_FREQ_BOOST is enabled.
100/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Table 23. Typical consumption in Run mode and corresponding performance
versus code position
Conditions
frcc_c_c k
(MHz)
IDD/
Coremark
Symbol Parameter
Coremark
Typ
Unit
Unit
Peripheral
Code
ITCM
550
550
2777
2777
145
145
52.2
52.2
FLASH
All
peripherals
disabled,
cache ON
AXI
SRAM
550
2777
145
52.2
SRAM 1
SRAM 4
FLASH
550
550
550
2777
2777
923
150
145
99
54.0
52.2
Supply
current in
Run mode
µA/
Core-
mark
IDD
mA
107.3
All
AXI
SRAM
550
1271
105
82.6
peripherals
disabled
SRAM 1
SRAM 4
550
550
790
723
96.5
89.5
122.2
123.8
cache OFF
Table 24. Typical current consumption in Autonomous mode
frcc_c_c k
Symbol
Parameter
Conditions
Typ
Unit
(MHz)
Run, D1Stop,
VOS3
64
3.6
D2Stop
Run,
Supply current in
Autonous mode
IDD
mA
D1Standby, VOS3
D2Standby
64
2.6
Table 25. Typical current consumption in Sleep mode
Max(1)
frcc_c_ck
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
TJ =
TJ =
TJ =
TJ =
25 °C 85 °C 105 °C 125 °C
550
520
520
400
400
300
300
170
170
36
-
-
-
-
VOS0
(2)
33.5
33.5
27
60
60
52
39
34
28
21
17
170
170
160
110
110
85
240
240
230
170
160
130
120
96
-
-
VOS0
-
Supply
current in
Sleep mode
All
IDD(Sleep)
peripherals
disabled
22.5
18.5
16.5
9.7
240
240
190
190
150
mA
VOS1
VOS2
VOS3
78
8.5
61
1. Guaranteed by characterization results.
2. CPU_FREQ_BOOST is enabled.
DS13313 Rev 2
101/227
208
Electrical characteristics
STM32H723xE/G
Table 26. Typical current consumption in Stop mode
Max(1)
Symbol Parameter
Conditions
Typ
Unit
TJ =
TJ =
TJ =
TJ =
25 °C 85 °C 105 °C 125 °C
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
0.52
0.81
1.15
0.535
0.96
1.45
3.7
6.1
8.6
3.7
6.2
8.8
26
39
51
26
39
51
44
64
82
44
64
83
72
110
130
72
Flash memory in low
power mode
Supply
current in
IDD(Stop) Stop and
DStop
mA
Flash memory in
normal mode
modes
110
130
1. Guaranteed by characterization results.
Table 27. Typical current consumption in Standby mode
Conditions
Typ(1)
Max at 3.6 V(2)
Symbol Parameter
RTC
TJ = TJ = TJ =
3.3 V 25 ° 85 ° 105 ° 125 °
TJ =
Unit
Backup
SRAM
1.65
V
and
2.4 V
3 V
LSE(3)
C
C
C
C
OFF
ON
OFF
OFF
ON
2.2
3.5
2.2
3.5
2.35
3.7
2.5
4
2.8
4.3
-
-
-
-
-
-
Supply
current in
Standby
mode,
-
-
IDD
µA
(Standby)
OFF
ON
2.4
2.85
4.35
3.25 4.5
4.75 8.3
15
39
30
75
64
140
IWDG OFF
ON
3.8
1. These values are given for PDR OFF. When the PDR is ON, the typical current consumption is increased
(refer to Table 16: Reset and power control block characteristics.
2. Guaranteed by characterization results.
3. The LSE is in Low-drive mode.
Table 28. Typical and maximum current consumption in V
mode
BAT
Max at 3.6 V(1)(2)
Conditions
Typ
Sym-
bol
Para-
meter
RTC
TJ = TJ =
105 ° 125 °
Back-up
SRAM
TJ = 2 TJ =
5 °C 85 °C
and
1.2 V
2 V
3 V
3.3 V
LSE(3)
C
C
OFF
ON
OFF
OFF
ON
0.008
1.5
0.01
1.7
0.025
1.9
0.05
1.9
0.8
3.2
0.3
3.1
28
-
7.4
53
-
18
91
-
Supply
current in
VBAT
4
-
IDD
(VBAT)
OFF
ON
0.4
0.5
0.75
2.8
mode
ON
1.8
2.1
-
-
-
-
1. Guaranteed by characterization results.
2. The LDO regulator is used before switching to VBAT mode.
3. The LSE is in Low-drive mode.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
102/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption, the I/Os used by an application
also contribute to the current consumption. When an I/O pin switches, it uses the current
from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the
capacitive load (internal or external) connected to the pin:
ISW = VDDx × fSW × CL
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the MCU supply voltage
DDx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
EXT
L
INT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS13313 Rev 2
103/227
208
Electrical characteristics
STM32H723xE/G
6.3.8
Wakeup time from low-power modes
The wakeup times given in Table 29 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
Table 29. Low-power mode wakeup timings
Max(1)
Typ(1)
Symbol
Parameter
Conditions
Unit
(2)
CPU
clock
cycles
(3)
tWUSLEEP
Wakeup from Sleep
-
14.00
15.00
SVOS3, HSI, Flash memory in Normal mode
SVOS3, HSI, Flash memory in low-power mode
SVOS4, HSI, Flash memory in Normal mode
SVOS4, HSI, Flash memory in low-power mode
SVOS5, HSI, Flash memory in Normal mode
SVOS5, HSI, Flash memory in low-power mode
SVOS3, CSI, Flash memory in Normal mode
SVOS3, CSI, Flash memory in low power mode
SVOS4, CSI, Flash memory in Normal mode
SVOS4, CSI, Flash memory in low-power mode
SVOS5, CSI, Flash memory in Normal mode
SVOS5, CSI, Flash memory in low-power mode
4.6
6.2
12.4
15.5
23.3
39.1
39.1
30.0
40.6
41.0
51.5
67.3
67.2
17.4
21.1
31.8
52.6
52.7
41.6
55.0
55.4
68.8
89.5
89.5
Wakeup from Stop
mode
(3)
tWUSTOP
µs
Wakeup from
Standby mode
(3)
tWUSTDBY
-
400.0
504.3
1. Guaranteed by characterization results.
2. The maximum values have been measured at -40 °C, in worst conditions.
3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
104/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
6.3.9
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 50: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 13.
(1)
Table 30. High-speed external user clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fHSE_ext
User external clock source frequency
4
25
50
MHz
VSW
(VHSEH−VHSEL)
OSC_IN amplitude
0.7VDD
-
VDD
V
VDC
OSC_IN input voltage
VSS
7
-
-
0.3VSS
-
tW(HSE)
OSC_IN high or low time
ns
1. Guaranteed by design.
Figure 13. High-speed external clock source AC timing diagram
V
HSEH
90%
10 %
HSEL
V
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
I
L
OSC _I N
clock source
STM32
ai17528b
DS13313 Rev 2
105/227
208
Electrical characteristics
STM32H723xE/G
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 50: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 14.
(1)
Table 31. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
-
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
-
-
-
0.7 VDD
VSS
-
-
-
VDD
0.3 VDD
-
V
OSC32_IN input pin low level
voltage
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
250
ns
1. Guaranteed by design.
Figure 14. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
t
W(LSE)
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
I
L
OSC32_IN
clock source
STM32
ai17529b
106/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 32. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 32. 4-50 MHz HSE oscillator characteristics
Operating
Symbol
Parameter
Min
Typ
Max
Unit
conditions(2)
F
Oscillator frequency
Feedback resistor
-
4
-
-
200
-
50
-
MHz
RF
-
kΩ
During startup(3)
-
4
V
DD=3 V, Rm=30 Ω
-
-
-
-
-
0.35
0.40
0.45
0.65
0.95
-
-
-
-
-
CL=10 pF at 4 MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 8 MHz
HSE current
consumption
IDD(HSE)
mA
VDD=3 V, Rm=30 Ω
CL=10 pF at 16 MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 48 MHz
Maximum critical crystal
gm
Gmcritmax
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU
Start-up time
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 15). C and C are usually
L1
L2
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . The PCB and MCU pin capacitance must be included
L1
L2
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing C and C .
L1
L2
Note:
For information on selecting the crystal, refer to application note AN2867 “Oscillator design
guide for ST microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
STM32H723xE/G
Figure 15. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
OSC_OUT
(1)
STM32
R
EXT
C
L2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 33. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 33. Low-speed external user clock characteristics
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
-
32.768
-
kHz
LSEDRV[1:0] = 00,
Low drive capability
-
-
-
-
-
-
-
290
390
550
900
-
-
-
LSEDRV[1:0] = 01,
Medium Low drive capability
LSE current
consumption
IDD
nA
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
LSEDRV[1:0] = 00,
Low drive capability
0.5
0.75
1.7
LSEDRV[1:0] = 01,
Medium Low drive capability
-
Maximum critical crystal
gm
Gmcritmax
µA/V
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
-
-
2.7
-
(3)
tSU
Startup time
VDD is stabilized
2
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
108/227
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Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 16. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC32_IN
Bias
controlled
gain
32.768 kHz
resonator
RF
OSC32_OUT
STM32
CL2
ai17531c
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
6.3.10
Internal clock source characteristics
The parameters given in Table 34 to Table 36 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 12: General
DD
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 34. HSI48 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD=3.3 V,
TJ=30 °C
fHSI48
HSI48 frequency
47.5(1)
-
48
48.5(1) MHz
TRIM(2)
USER trimming step
USER TRIMMING coverage
Duty Cycle
-
± 32 steps
-
0.175 0.250
%
%
%
%
USER TRIM
±4.70
45
±5.6
-
COVERAGE(3)
DuCy(HSI48)(2)
-
-
55
3.5
Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
ACCHSI48_REL(3)(4)
TJ=-40 to 125 °C
–4.5
V
DD=3 to 3.6 V
-
-
-
-
0.025
0.05
2.1
0.05
0.1
HSI48 oscillator frequency drift with
VDD(6) (the reference is 3.3 V)
∆
VDD(HSI48)(2)(5)
%
VDD=1.62 V to 3.6 V
(2)
tsu(HSI48)
HSI48 oscillator start-up time
-
-
4.0
µs
(2)
IDD(HSI48)
HSI48 oscillator power consumption
350
400
µA
Next transition jitter
NT jitter(2)
PT jitter(2)
-
-
-
-
± 0.15
± 0.25
-
-
ns
ns
Accumulated jitter on 28 cycles(7)
Paired transition jitter
Accumulated jitter on 56 cycles(7)
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. ꢀfHSI = ACCHSI48_REL + ꢀVDD
.
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Electrical characteristics
STM32H723xE/G
5. ꢀfHSI = ACCHSI48_REL + ꢀVDD
.
6. These values are obtained by using the formula: (Freq(3.6 V) - Freq(3.0 V)) / Freq(3.0 V) or (Freq(3.6 V) - Freq(1.62 V)) /
Freq(1.62 V).
7. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
(1)
Table 35. HSI oscillator characteristics
Symbol
Parameter
HSI frequency
Conditions
Min
Typ
Max
Unit
fHSI
VDD=3.3 V, TJ=30 °C
63.7(2)
64
64.3(2)
MHz
Trimming is not a multiple
of 32
-
0.24
−1.8
−0.8
0.32
Trimming is 128, 256 and
384
−5.2
−1.4
-
-
Trimming is 64, 192, 320
and 448
TRIM
HSI user trimming step
%
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
−0.6
−0.25
-
DuCy(HSI) Duty cycle
HSI oscillator frequency drift over
-
45
-
-
55
%
%
ΔVDD (HSI)
VDD=1.62 to 3.6 V
−0.12
0.03
VDD (the reference is 3.3 V)
HSI oscillator frequency drift over
TJ=-20 to 105 °C
−1(3)
−2(3)
-
-
1(3)
1(3)
ΔTEMP(HSI) temperature (the reference is
%
TJ=−40 to TJmax °C
64 MHz)
tsu(HSI)
tstab(HSI) HSI oscillator stabilization time
DD(HSI) HSI oscillator power consumption
HSI oscillator start-up time
-
-
-
-
-
1.4
4
2
8
at 1% of target frequency
at 5% of target frequency
-
µs
-
4
I
300
400
µA
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.
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Electrical characteristics
4 MHz low-power internal RC oscillator (CSI)
(1)
Table 36. CSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCSI
CSI frequency
CSI trimming step
Duty cycle
VDD=3.3 V, TJ=30 °C
3.96(2)
4
4.04(2) MHz
Trimming is not a
multiple of 16
-
0.40
0.75
Trimming is a multiple
of 32
−4.75 −2.75
0.75
%
TRIM
Other trimming values
not multiple of 16
(excluding multiple of
32)
−0.43
0.00
0.75
DuCy(CSI)
-
45
-
-
-
55
%
%
TJ = 0 to 85 °C
TJ = −40 to 125 °C
−3.7(3)
−11(3)
4.5(3)
7.5(3)
CSI oscillator frequency drift over
temperature
ꢀ
TEMP (CSI)
CSI oscillator frequency drift over
VDD
ꢀVDD (CSI)
tsu(CSI)
VDD = 1.62 to 3.6 V
−0.06
-
1
0.06
2
%
µs
CSI oscillator startup time
-
-
-
-
-
-
CSI oscillator stabilization time
tstab(CSI)
IDD(CSI)
-
4
cycle
µA
(to reach ± 3% of fCSI
)
CSI oscillator power consumption
23
30
1. Guaranteed by design, unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.
Low-speed internal (LSI) RC oscillator
Table 37. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V, TJ = 25 °C
31.4(1)
32
32.6(1)
TJ = –40 to 110 °C,
VDD = 1.62 to 3.6 V
29.76(2)
-
33.6(2)
fLSI
LSI frequency
kHz
TJ = –40 to 125 °C,
VDD = 1.62 to 3.6 V
29.4(2)
-
33.6(2)
130
(3)
tsu(LSI)
LSI oscillator startup time
-
-
-
-
-
-
80
µs
LSI oscillator stabilization time
(5% of final value)
(3)
tstab(LSI)
120
130
170
(3)
IDD(LSI)
LSI oscillator power consumption
280
nA
1. Guaranteed by test in production.
2. Guaranteed by characterization results.
3. Guaranteed by design.
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STM32H723xE/G
6.3.11
PLL characteristics
The parameters given in Table 38, Table 41 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 12: General operating
DD
conditions.
(1)
Table 38. PLL1 characteristics (wide VCO frequency range)
Symbol
fPLL_IN
Parameter
PLL input clock
PLL input clock duty cycle
Conditions
Min
Typ
Max
Unit
-
2
-
-
16
MHz
%
-
10
90
VOS0
VOS1
VOS2
VOS3
-
1.5
1.5
1.5
1.5
192
15
-
550(2)
400(2)
300(2)
170(2)
836(3)
150(3)
-
fPLL_P_OUT PLL multiplier output clock P
-
MHz
µs
-
fVCO_OUT
PLL VCO output
PLL lock time
-
Normal mode
50
tLOCK
Sigma-delta mode (CKIN ≥
25
-
65
51
170
8 MHz)
fVCO_OUT
= 192 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
fVCO_OUT
= 400 MHz
-
19
Cycle-to-cycle jitter(4)
fVCO_OUT
= 560 MHz
-
10
fPLL_OUT
=
fVCO_OUT
fVCO_OUT/100 = 800 MHz
-
9
fVCO_OUT
= 192 MHz
-
38
fVCO_OUT
= 560 MHz
Period jitter
-
8
fVCO_OUT
= 800 MHz
Jitter
-
7
ps
fVCO_OUT
= 192 MHz
-
0.15
0.14
0.16
0.17
0.08
0.06
Normal mode
fVCO_OUT
(CKIN = 2 MHz) = 400 MHz
-
fVCO_OUT
= 832 MHz
-
Long term jitter
fVCO_OUT
= 192 MHz
-
Sigma-delta
fVCO_OUT
mode (CKIN =
= 500 MHz
16 MHz)
-
fVCO_OUT
= 836 MHz
-
112/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
(1)
Table 38. PLL1 characteristics (wide VCO frequency range) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
VCORE
VDDA
530
1190
260
557
1285
286
670
6300
513
fVCO_OUT
560 MHz
=
IDD(PLL)
PLL power consumption
µA
fVCO_OUT
192 MHz
=
VCORE
309
377
5700
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation.
3. Guaranteed by characterization results.
4. Integer mode only.
(1)
Table 39. PLL1 characteristics (medium VCO frequency range)
Symbol
Parameter
PLL input clock
Conditions
Min
Typ
Max Unit
-
1
-
-
-
-
-
-
-
2
MHz
%
fPLL_IN
PLL input clock duty cycle
-
VOS0
10
90
1.17
1.17
1.17
1.17
150
-
210
210
VOS1
fPLL_OUT
PLL multiplier output clock P, Q, R
VOS2
210 MHz
200
VOS3
fVCO_OUT
tLOCK
PLL VCO output
PLL lock time
-
420
Normal mode
Sigma-delta mode
fVCO_OUT
60(2) 100(2)
µs
forbidden
145
=
-
-
-
-
-
-
-
-
-
-
-
-
-
-
150 MHz
fVCO_OUT
300 MHz
=
91
64
Cycle-to-cycle jitter(3)
-
±ps
fVCO_OUT
400 MHz
=
fVCO_OUT
420 MHz
=
Jitter
63
fVCO_OUT
=
55
150 MHz
fPLL_OUT
50 MHz
=
Period jitter
±-ps
%
fVCO_OUT
=
30
400 MHz
fVCO_OUT
400 MHz
=
Long term jitter
Normal mode
±0.3
VDD
VCORE
VDD
-
-
-
-
440
530
180
200
1150
fVCO_OUT
420 MHz
=
-
500
-
I(PLL)
PLL power consumption on VDD
µA
fVCO_OUT
150 MHz
=
VCORE
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Electrical characteristics
STM32H723xE/G
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
(1)
Table 40. PLL2 and PLL3 characteristics (wide VCO frequency range)
Symbol
Parameter
PLL input clock
Conditions
Min
Typ
Max
Unit
-
-
2
-
-
16
MHz
%
fPLL_IN
PLL input clock duty cycle
10
90
VOS0
VOS1
VOS2
VOS3
-
1.5
1.5
1.5
1.5
192
-
-
550(2)
400(2)
300(2)
170(2)
960(3)
150(3)
-
PLL multiplier output clock P,
Q, R
fPLL_OUT
-
MHz
-
fVCO_OUT PLL VCO output
-
Normal mode
50
tLOCK
PLL lock time
µs
Sigma-delta mode (fPLL_IN
-
58
166(3)
≥ 8 MHz)
fVCO_OUT = 192 MHz
-
-
-
-
134
134
76
-
-
-
-
f
f
VCO_OUT = 200 MHz
VCO_OUT = 400 MHz
Cycle-to-cycle jitter(4)
±ps
fVCO_OUT = 800 MHz
Normal
39
mode
(fPLL_IN
2 MHz)
fVCO_OUT
560 MHz
=
-
-
-
-
±0.2
±0.8
±0.2
±0.8
-
-
-
-
=
Normal
mode
(fPLL_IN
Jitter
fVCO_OUT
560 MHz
=
=
16 MHz)
Long term jitter
%
Sigma-delta
mode
(fPLL_IN
fVCO_OUT
560 MHz
=
=
2 MHz)
Sigma-delta
mode
(fPLL_IN
fVCO_OUT
560 MHz
=
=
16 MHz)
VDD
VCORE
VDD
-
-
-
-
590
720
180
280
1500
fVCO_OUT
836 MHz
=
-
600
-
(3)
IDD(PLL)
PLL power consumption
µA
fVCO_OUT
192 MHz
=
VCORE
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation.
114/227
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Electrical characteristics
3. Guaranteed by characterization results.
4. Integer mode only.
(1)
Table 41. PLL2 and PLL3 characteristics (medium VCO frequency range)
Symbol
Parameter
PLL input clock
Conditions
Min
Typ
Max
Unit
-
1
-
2
90
MHz
fPLL_IN
PLL input clock duty cycle
-
VOS0
10
-
%
1.17
1.17
1.17
1.17
150
-
-
210
210
210
200
420
100(2)
MHz
VOS1
-
-
-
-
-
PLL multiplier output clock
P, Q, R
fPLL_OUT
VOS2
-
VOS3
-
fVCO_OUT PLL VCO output
-
-
60
Normal mode
Sigma-delta mode
fVCO_OUT = 150 MHz
tLOCK
PLL lock time
µs
forbidden
145
91
-
-
-
-
-
-
-
-
f
VCO_OUT = 200 MHz
VCO_OUT = 400 MHz
Cycle-to-cycle jitter(3)
±ps
f
64
fVCO_OUT = 420 MHz
63
Jitter
fPLL_OUT
50 MHz
=
fVCO_OUT
150 MHz
=
-
-
-
55
30
-
-
-
Period jitter
±ps
%
fVCO_OUT = 400 MHz
fVCO_OUT
=
Long term jitter
Normal mode
±0.3
400 MHz
VDD
-
-
-
-
440
530
180
200
1150
fVCO_OUT
420 MHz
=
VCORE
VDD
-
500
-
PLL power consumption on
VDD
IDD(PLL)
µA
fVCO_OUT
150 MHz
=
VCORE
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
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STM32H723xE/G
6.3.12
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 125 °C unless otherwise specified.
J
The devices are shipped to customers with the Flash memory erased.
Table 42. Flash memory characteristics
Symbol
Parameter
Conditions
Write / Erase 8-bit mode
Min
Typ
Max
Unit
-
-
-
-
6.5
11.5
20
-
-
-
-
Write / Erase 16-bit mode
Write / Erase 32-bit mode
Write / Erase 64-bit mode
IDD
Supply current
mA
35
Table 43. Flash memory programming
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
Program/erase parallelism x 8
-
-
-
-
-
-
-
-
-
-
-
290
180
130
100
2
580(2)
360
µs
260
Word (266 bits) programming
time
tprog
200
4
tERASE
Sector (128 Kbytes) erase time Program/erase parallelism x 16
Program/erase parallelism x 32
1.8
3.6
Program/erase parallelism x 8
3
8
6
5
26
16
12
10
s
Program/erase parallelism x 16
Mass erase time (1 Mbyte)
tME
Program/erase parallelism x 32
Program/erase parallelism x 64
Program parallelism x 8
Program parallelism x 16
Programming voltage
1.62
1.8
-
-
3.6
3.6
Vprog
V
Program parallelism x 32
Program parallelism x 64
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
Table 44. Flash memory endurance and data retention
Parameter Conditions
Min(1)
TJ = –40 to +125 °C
Symbol
Unit
NEND
Endurance
kcycles
Years
10
30
20
Data retention
1 kcycle at TA = 85 °C
10 kcycles at TA = 55 °C
tRET
116/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
1. Guaranteed by characterization results.
6.3.13
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709 “EMC design guide for STM8, STM32 and Legacy
MCUs ”.
Table 45. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, TA = 25 °C,
LQFP176, conforming to
IEC 61000-4-2
Voltage limits to be applied on any I/O pin to induce
a functional disturbance
VFESD
3B
5A
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
VDD = 3.3 V, TA = 25 °C,
LQFP176, conforming to
IEC 61000-4-4
VFTB
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015 “Software
techniques for improving microcontrollers EMC performance”).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 46. EMI characteristics
Max vs.
Monitored
frequency band
[fHSE/fCPU
]
Symbol Parameter
Conditions
Unit
8/550 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
14
20
27
17
4
dBµV
-
VDD = 3.6 V, TA = 25 °C, LQFP176 package,
conforming to IEC61967-2
SEMI
Peak level
6.3.14
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 47. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Packages
Class
Unit
value(1)
Electrostatic discharge
voltage (human body model) ANSI/ESDA/JEDEC JS-001
TA = 25 °C conforming to
VESD(HBM)
All packages
2
2000
All LQFP
packages
C1
250
500
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-002
All BGA and
WLCSP packages
C2a
1. Guaranteed by characterization results.
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Electrical characteristics
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 48. Electrical sensitivities
Symbol
Parameter
Conditions
Conforming to JESD78,
TJ = TJMax
Class
LU
Static latchup class
II level A
6.3.15
I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
DD
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 49. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
PA12, PE8
5
0
0
PC4, PE12, PF15, PH0
NA
IINJ
mA
PA0, PA0_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PE7, PG1, PH4, PH5, BOOT0
0
5
0
All other I/Os
NA
1. Guaranteed by characterization results.
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6.3.16
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 12: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Note:
For information on GPIO configuration, refer to application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption” available from the ST
website www.st.com.
Table 50. I/O static characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I/O input low level voltage
except BOOT0
(1)
-
-
0.3VDD
I/O input low level voltage
except BOOT0
0.4VDD−0.1
VIL
1.62 V<VDD<3.6 V
-
-
-
V
(2)
BOOT0 I/O input low level
voltage
0.19VDD+0.1
-
(2)
I/O input high level voltage
except BOOT0
(1)
0.7VDD
-
-
-
-
-
I/O input high level voltage
except BOOT0
0.47VDD
+
+
VIH
1.62 V<VDD<3.6 V
-
-
V
0.25(2)
BOOT0 I/O input high level
voltage
0.17VDD
0.6(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis
-
250
(2)
VHYS
1.62 V< VDD <3.6 V
mV
BOOT0 I/O input hysteresis
-
-
200
-
-
(8)
0< VIN ≤ Max(VDDXXX
)
+/-250
FT_xx Input leakage current(2)
Max(VDDXXX) < VIN ≤ 5.5 V
-
-
-
-
-
-
1500
(4)(5)(8)
(8)
0< VIN ≤ Max(VDDXXX
)
+/- 350
5000(6)
(3)
FT_u IO
Ileak
Max(VDDXXX) < VIN ≤ 5.5 V
nA
(4)(5)(8)
(8)
TT_xx Input leakage current
0< VIN ≤ Max(VDDXXX
0< VIN ≤ VDD
)
-
-
-
-
+/-250
15
VPP (BOOT0 alternate
function)
VDD < VIN ≤ 9 V
35
Weak pull-up equivalent
resistor(7)
RPU
VIN=VSS
30
40
50
kΩ
Weak pull-down equivalent
resistor(7)
(8)
RPD
CIO
VIN=VDD
30
-
40
5
50
-
I/O pin capacitance
-
pF
1. Compliant with CMOS requirements.
2. Guaranteed by design.
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Electrical characteristics
3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max)
.
4. All FT_xx IO except FT_lu, FT_u and PC3.
5. VIN must be less than Max(VDDXXX) + 3.6 V.
6. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
7. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
8. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 17.
Figure 17. V /V for all I/Os except BOOT0
IL IH
3
2.5
2
TLL requirement: VIHmin = 2 V
1.5
1
TLL requirement: VILmin = 0.8 V
0.5
0
2.8
1.6
1.8
2
2.2
2.4
2.6
3
3.2
3.4
3.6
MSv46121V3
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 10).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 10).
VSS
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STM32H723xE/G
Output voltage levels
Unless otherwise specified, the parameters given in Table 51: Output voltage characteristics
for all I/Os except PC13, PC14 and PC15 and Table 52: Output voltage characteristics for
PC13, PC14 and PC15 are derived from tests performed under ambient temperature and
V
supply voltage conditions summarized in Table 12: General operating conditions. All
DD
I/Os are CMOS and TTL compliant.
(1)
Table 51. Output voltage characteristics for all I/Os except PC13, PC14 and PC15
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO = 8 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO = −8 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO = 8 mA
(3)
VOL
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO = −8 mA
(3)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
V
I
IO = 20 mA
2.7 V≤ VDD ≤3.6 V
IO = −20 mA
2.7 V≤ VDD ≤3.6 V
IO = 4 mA
1.62 V≤ VDD ≤3.6 V
IO = −4 mA
(3)
VOL
Output low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
1.3
-
I
(3)
VOH
VDD−1.3
I
(3)
VOL
-
0.4
-
I
(3)
VOH
VDD−-0.4
1.62 V≤VDD<3.6 V
IIO = 20 mA
-
-
0.4
0.4
2.3 V≤ VDD≤3.6 V
Output low level voltage for an FTf
I/O pin in FM+ mode
(3)
VOLFM+
IIO = 10 mA
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 9:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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(1)
Table 52. Output voltage characteristics for PC13, PC14 and PC15
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO = 3 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO = −3 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO = 3 mA
(3)
VOL
-
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO = −3 mA
(2)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
IIO = 1.5 mA
(2)
VOL
Output low level voltage
Output high level voltage
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO = −1.5 mA
(2)
VOH
VDD−0.4
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 9:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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STM32H723xE/G
Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
(1)
Table 53. Output timing characteristics (HSLV OFF)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
3
12
(2)
Fmax
Maximum frequency
MHz
3
16
4
00
16.6
33.3
13.3
25
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
ns
MHz
ns
10
20
60
15
80
(2)
Fmax
Maximum frequency
15
110
20
01
5.2
10
Output high to low level
fall time and output low
to high level rise time
4.2
7.5
2.8
5.2
tr/tf(3)
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Speed Symbol
Electrical characteristics
(1)
Table 53. Output timing characteristics (HSLV OFF) (continued)
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V(4)
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 2.7 V≤VDD≤3.6 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=10 pF, 2.7 V≤VDD≤3.6 V(4)
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
C=50 pF, 2.7 V≤VDD≤3.6 V(4)
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 2.7 V≤VDD≤3.6 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=10 pF, 2.7 V≤VDD≤3.6 V(4)
C=10 pF, 1.62 V≤VDD≤2.7 Vv
C=50 pF, 2.7 V≤VDD≤3.6 Vv
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 2.7 V≤VDD≤3.6 Vv
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=10 pF, 2.7 V≤VDD≤3.6 V(4)
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
C=50 pF, 2.7 V≤VDD≤3.6 V(4)
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 2.7 V≤VDD≤3.6 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=10 pF, 2.7 V≤VDD≤3.6 V(4)
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85
35
110
40
(2)
Fmax
Maximum frequency
MHz
166
100
3.8
6.9
2.8
5.2
1.8
3.3
100
50
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
ns
MHz
ns
133
66
(2)
Fmax
Maximum frequency
220
85
11
3.3
6.6
2.4
4.5
1.5
2.7
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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STM32H723xE/G
Output buffer timing characteristics (HSLV option enabled)
(1)
Table 54. Output timing characteristics (HSLV ON)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
10
10
11
(2)
Fmax
Maximum frequency
MHz
00
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
9
ns
MHz
ns
6.6
50
58
66
6.6
4.8
3
(2)
Fmax
Maximum frequency
01
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
55
80
133
5.8
4
(2)
Fmax
Maximum frequency
MHz
ns
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
2.4
60
90
175
5.3
3.6
1.9
(2)
Fmax
Maximum frequency
MHz
ns
11
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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Analog switch between ports Pxy_C and Pxy
PA0_C, PA1_C, PC2_C and PC3_C can be connected internally to PA0, PA1, PC2 and
PC3, respectively (refer to SYSCFG_PMCR register in RM0468 reference manual). The
switch is controlled by V
voltage level. It is defined through BOOSTVDDSEL bit of
DDSWITCH
SYSCFG_PMCR. If the switch is closed the switch characteristics are given in the table
below.
Table 55. Pxy_C and Pxy analog switch characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Switch control boosted
-
-
-
-
-
-
-
-
-
-
-
-
315
315
335
390
445
550
V
V
V
V
> 2.7 V
> 2.4 V
> 2.0 V
> 1.8 V
> 1.62 V
DDSWITCH
DDSWITCH
DDSWITCH
DDSWITCH
Switch
impedance
Ω
Switch control
not boosted
V
DDSWITCH
6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 50: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 12: General operating conditions.
Table 56. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Weak pull-up equivalent
resistor(1)
(2)
RPU
VIN = VSS
30
40
50
㏀
(2)
VF(NRST)
NRST Input filtered pulse
1.71 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
-
-
50
-
350
ns
(2)
VNF(NRST)
NRST Input not filtered pulse
1.62 V < VDD < 3.6 V 1000
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Guaranteed by design.
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STM32H723xE/G
Figure 18. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 50. Otherwise the reset is not taken into account by the device.
6.3.18
FMC characteristics
Unless otherwise specified, the parameters given in Table 57 to Table 70 for the FMC
interface are derived from tests performed under the ambient temperature, f
frequency
HCLK
and V supply voltage conditions summarized in Table 12: General operating conditions,
DD
with the following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS0.
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics.
Asynchronous waveforms and timings
Figure 19 through Figure 21 represent asynchronous waveforms and Table 57 through
Table 64 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
Capacitive load C = 30 pF
L
In all timing tables, the T
is the f
clock period.
KERCK
mc_ker_ck
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Figure 19. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Electrical characteristics
STM32H723xE/G
(1)
Table 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
3Tfmc_ker_ck–1
0
3Tfmc_ker_ck+1
0.5
2Tfmc_ker_ck –1
2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high
hold time
th(NE_NOE)
tv(A_NE)
Tfmc_ker_ck
-
-
0.5
-
FMC_NEx low to FMC_A valid
Address hold time after
FMC_NOE high
th(A_NOE)
2Tfmc_ker_ck
Data to FMC_NEx high setup
time
ns
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
Tfmc_ker_ck+14
-
-
-
-
Data to FMC_NOEx high setup
time
13
0
Data hold time after FMC_NOE
high
Data hold time after FMC_NEx
high
0
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV) FMC_NADV low time
-
-
4
Tfmc_ker_ck+1
1. Guaranteed by characterization results.
Table 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tw(NOE)
tw(NWAIT)
FMC_NE low time
FMC_NOE low time
FMC_NWAIT low time
7Tfmc_ker_ck–1
5Tfmc_ker_ck–1
Tfmc_ker_ck– 0.5
7Tfmc_ker_ck+1
5Tfmc_ker_ck +1
-
ns
FMC_NWAIT valid before FMC_NEx
high
tsu(NWAIT_NE)
th(NE_NWAIT)
4Tfmc_ker_ck +9
3Tfmc_ker_ck+12
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle.
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Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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STM32H723xE/G
(1)
Table 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
3Tfmc_ker_ck –1
Tfmc_ker_ck–1
3Tfmc_ker_ck + 1
Tfmc_ker_ck
Tfmc_ker_ck –0.5
Tfmc_ker_ck+0.5
FMC_NWE high to FMC_NE high
hold time
th(NE_NWE)
tv(A_NE)
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Tfmc_ker_ck
-
1
FMC_NEx low to FMC_A valid
-
Address hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
-
-
ns
FMC_NEx low to FMC_BL valid
0.5
-
FMC_BL hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
Data to FMC_NEx low to Data valid
-
Tfmc_ker_ck+ 2
th(Data_NWE) Data hold time after FMC_NWE high
Tfmc_ker_ck
-
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
-
5
Tfmc_ker_ck+ 1
1. Guaranteed by characterization results.
Table 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
6Tfmc_ker_ck –1
8Tfmc_ker_ck+1
6Tfmc_ker_ck+1
tw(NWE)
FMC_NWE low time
FMC_NWAIT valid before FMC_NEx
high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
5Tfmc_ker_ck+13
4Tfmc_ker_ck+12
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle.
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Figure 21. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
DS13313 Rev 2
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STM32H723xE/G
(1)
Table 61. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
4Tfmc_ker_ck –1
4Tfmc_ker_ck +1
2Tfmc_ker_ck
+0.5
tv(NOE_NE)
ttw(NOE)
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2Tfmc_ker_ck
Tfmc_ker_ck –1
Tfmc_ker_ck
Tfmc_ker_ck+1
-
FMC_NOE high to FMC_NE high hold
time
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
0.5
4.0
0
Tfmc_ker_ck –0.5
Tfmc_ker_ck +1
ns
FMC_AD(address) valid hold time
after FMC_NADV high)
th(AD_NADV)
th(A_NOE)
Tfmc_ker_ckk –4
Tfmc_ker_ck –0.5
-
-
Address hold time after FMC_NOE
high
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NE)
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
Tfmc_ker_ck +14
-
-
13
0
-
th(Data_NOE)
0
-
1. Guaranteed by characterization results.
(1)
Table 62. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
5Tfmc_ker_ck –1
8Tfmc_ker_ck +1
5Tfmc_ker_ck +1
tw(NOE)
FMC_NWE low time
FMC_NWAIT valid before
FMC_NEx high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
4Tfmc_ker_ck +9
3Tfmc_ker_ck +12
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
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Table 63. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
4Tfmc_ker_ck –1
Tfmc_ker_ck –1
4Tfmc_ker_ck
Tfmc_ker_ck +0.5
2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5
FMC_NWE high to FMC_NE high hold
time
th(NE_NWE)
Tfmc_ker_ck –0.5
-
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
1
5.0
0
Tfmc_ker_ck –0.5
Tfmc_ker_ck + 1
ns
FMC_AD(adress) valid hold time after
FMC_NADV high)
th(AD_NADV)
th(A_NWE)
Tfmc_ker_ck –4.5
-
-
-
Address hold time after FMC_NWE
high
T
fmc_ker_ck – 0.5
fmc_ker_ck – 0.5
FMC_BL hold time after FMC_NWE
high
th(BL_NWE)
T
tv(BL_NE)
FMC_NEx low to FMC_BL valid
FMC_NADV high to Data valid
-
0.5
tv(Data_NADV)
th(Data_NWE)
-
Tfmc_ker_ck +2
-
Data hold time after FMC_NWE high
Tfmc_ker_ck
1. Guaranteed by characterization results.
(1)(2)
Table 64. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9Tfmc_ker_ck –1
9Tfmc_ker_ck
tw(NWE)
FMC_NWE low time
7Tfmc_ker_ck –0.5
7Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_NEx
high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
5Tfmc_ker_ck +9
4Tfmc_ker_ck +12
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle.
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STM32H723xE/G
Synchronous waveforms and timings
Figure 22 through Figure 25 represent synchronous waveforms and Table 65 through
Table 68 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash, DataLatency = 0 for PSRAM, C = 30 pF
L
In all the timing tables, the Tfmc_ker_ck is the f
FMC_CLK maximum values:
clock period, with the following
mc_ker_ck
•
•
•
For 2.7 V<V <3.6 V: maximum FMC_CLK = 137 MHz at C = 20 pF
DD L
For 1.8 V<V <1.9 V: maximum FMC_CLK = 100 MHz at C = 20 pF
DD
L
For 1.62 V<V <1.8 V: maximumFMC_CLK = 88 MHz at C = 15 pF
DD
L
Figure 22. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
MS32757V1
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(1)
Table 65. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –0.5
-
3
td(CLKL-NExL)
td(CLKH_NExH)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
-
Tfmc_ker_ck+1.5
-
1.62 V <VDD < 3.6 V
FMC_CLK low to
5.5
2
td(CLKL-NADVL)
-
FMC_NADV low
2.7 V <VDD < 3.6 V
1.62 V <VDD < 3.6 V
FMC_CLK low to
-
td(CLKL-NADVH)
1
FMC_NADV high
2.7 V <VDD < 3.6 V
-
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
-
3
Tfmc_ker_ck
-
ns
-
2.5
FMC_CLK high to FMC_NOE high
Tfmc_ker_ck +1
-
3
-
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
FMC_A/D[15:0] valid data before FMC_CLK high
FMC_A/D[15:0] valid data after FMC_CLK high
-
0
3
0
-
-
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
3
-
-
CLKH)
th(CLKH-NWAIT)
2.5
1. Guaranteed by characterization results.
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STM32H723xE/G
Figure 23. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
FMC_A[25:16]
t
d(CLKH-NWEH)
d(CLKL-NWEL)
FMC_NWE
t
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
d(CLKL-Data)
d(CLKL-ADV)
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKH-NBLH)
FMC_NBL
MS32758V1
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Electrical characteristics
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Table 66. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period, VDD = 2.7 to 3.6 V
2Tfmc_ker_ck –0.5
-
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x =0..2)
3
FMC_CLK high to FMC_NEx high
(x = 0…2)
td(CLKH-NExH)
Tfmc_ker_ck +1.5
-
1.62 V <VDD < 3.6 V
FMC_CLK low to
5.5
td(CLKL-NADVL)
-
FMC_NADV low
2.7 V <VDD < 3.6 V
2.0
1.62 V <VDD < 3.6 V
FMC_CLK low to
-
td(CLKL-NADVH)
1
FMC_NADV high
2.7 V <VDD < 3.6 V
-
3
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NWEL)
t(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_Ax valid (x =16…25)
FMC_CLK high to FMC_Ax invalid (x =16…25)
FMC_CLK low to FMC_NWE low
-
Tfmc_ker_ck
-
ns
-
2.5
-
FMC_CLK high to FMC_NWE high
Tfmc_ker_ck +1
FMC_CLK low to to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
2.5
-
0
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low
-
3.5
2
td(CLKL-NBLL)
td(CLKH-NBLH)
tsu(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
-
Tfmc_ker_ck +0.5
-
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
3
-
2.5
-
1. Guaranteed by characterization results.
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STM32H723xE/G
Figure 24. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
MS32759V1
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(1)
Table 67. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –0.5
-
t(CLKL-NExL)
td(CLKH-NExH)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
-
3
Tfmc_ker_ck+1.5
-
1.62 V <VDD < 3.6 V
FMC_CLK low to
5.5
td(CLKL-NADVL)
-
FMC_NADV low
2.7 V <VDD < 3.6 V
2.0
1.62 V <VDD < 3.6 V
FMC_CLK low to
-
td(CLKL-NADVH)
1
FMC_NADV high
2.7 V <VDD < 3.6 V
-
3
-
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK ow to FMC_NOE low
-
ns
Tfmc_ker_ck
-
2.5
-
FMC_CLK high to FMC_NOE high
Tfmc_ker_ck+1
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high
3
0
-
th(CLKH-DV)
t(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_D[15:0] valid data after FMC_CLK high
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
-
3
-
2.5
-
1. Guaranteed by characterization results.
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STM32H723xE/G
Figure 25. Synchronous non-multiplexed PSRAM write timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKL-NExL)
FMC_NEx
d(CLKH-NExH)
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
FMC_NWE
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
td(CLKH-NWEH)
d(CLKL-NWEL)
t
t
d(CLKL-Data)
d(CLKL-Data)
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FMC_NBL
t
t
d(CLKH-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
MS32760V1
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Table 68. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
t(CLK)
FMC_CLK period
2Tfmc_ker_ck –0.5
-
3
td(CLKL-NExL)
t(CLKH-NExH)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
-
Tfmc_ker_ck+1.5
-
1.62 V <VDD < 3.6 V
FMC_CLK low to
5.5
2
td(CLKL-NADVL)
-
FMC_NADV low
2.7 V <VDD < 3.6 V
1.62 V <VDD < 3.6 V
FMC_CLK low to
-
td(CLKL-NADVH)
1
FMC_NADV high
2.7 V <VDD < 3.6 V
-
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NWE low
-
3
ns
Tfmc_ker_ck
-
td(CLKL-NWEL)
td(CLKH-NWEH)
td(CLKL-Data)
td(CLKL-NBLL)
td(CLKH-NBLH)
-
2.5
-
FMC_CLK high to FMC_NWE high
Tfmc_ker_ck+1
FMC_D[15:0] valid data after FMC_CLK low
FMC_CLK low to FMC_NBL low
-
3.5
2
-
FMC_CLK high to FMC_NBL high
Tfmc_ker_ck+0.5
-
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
3
-
-
CLKH)
th(CLKH-NWAIT)
2.5
1. Guaranteed by characterization results.
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
NAND controller waveforms and timings
Figure 26 through Figure 29 represent synchronous waveforms, and Table 69 and Table 70
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration and a capacitive load (C ) of 30 pF:
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x01
COM.FMC_WaitSetupTime = 0x03
COM.FMC_HoldSetupTime = 0x02
COM.FMC_HiZSetupTime = 0x01
ATT.FMC_SetupTime = 0x01
ATT.FMC_WaitSetupTime = 0x03
ATT.FMC_HoldSetupTime = 0x02
ATT.FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 26. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
t
th(NOE-ALE)
d(ALE-NOE)
FMC_NOE (NRE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
MS32767V1
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Electrical characteristics
Figure 27. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NWE-ALE)
d(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NWE-D)
v(NWE-D)
MS32768V1
Figure 28. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NOE-ALE)
d(ALE-NOE)
FMC_NWE
FMC_NOE
t
w(NOE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
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Electrical characteristics
STM32H723xE/G
Figure 29. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
t
d(ALE-NOE)
w(NWE)
h(NOE-ALE)
FMC_NWE
FMC_N OE
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FMC_D[15:0]
MS32770V1
(1)
Table 69. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
Min
Max
4Tfmc_ker_ck+0.5
Unit
tw(N0E)
FMC_NOE low width
4Tfmc_ker_ck – 0.5
FMC_D[15-0] valid data before
FMC_NOE high
tsu(D-NOE)
th(NOE-D)
11
0
-
FMC_D[15-0] valid data after
FMC_NOE high
ns
-
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid
1. Guaranteed by characterization results.
-
3Tfmc_ker_ck +0.5
-
4Tfmc_ker_ck –1
(1)
Table 70. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
Min
Max
Unit
tw(NWE)
FMC_NWE low width
4Tfmc_ker_ck – 0.5
4Tfmc_ker_ck +0.5
FMC_NWE low to FMC_D[15-0]
valid
tv(NWE-D)
th(NWE-D)
0
-
FMC_NWE high to FMC_D[15-0]
invalid
2Tfmc_ker_ck +1.5
5Tfmc_ker_ck – 5
-
-
ns
FMC_D[15-0] valid before
FMC_NWE high
td(D-NWE)
-
FMC_ALE valid before FMC_NWE
low
td(ALE-NWE)
th(NWE-ALE)
3Tfmc_ker_ck +0.5
-
FMC_NWE high to FMC_ALE
invalid
2Tfmc_ker_ck – 0.5
1. Guaranteed by characterization results.
146/227
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Electrical characteristics
SDRAM waveforms and timings
In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
•
•
•
For 2.7 V<V <3.6 V: maximum FMC_CLK = 95 MHz at 20 pF
DD
For 1.8 V<V <1.9 V: maximum FMC_CLK = 90 MHz at 20 pF
DD
For 1.62 V< <1.8 V: maximum FMC_CLK = 85 MHz at 15 pF
DD
Figure 30. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR)
th(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
th(SDCLKL_NCAS)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
td(SDCLKL_NCAS)
FMC_SDNWE
FMC_D[31:0]
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Data1 Data2 Datai
Datan
MS32751V2
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
(1)
Table 71. SDRAM read timings
Symbol
Parameter
Min
Max
Unit
2Tfmc_ker_ck
0.5
–
2Tfmc_ker_ck
+0.5
tw(SDCLK)
FMC_SDCLK period
tsu(SDCLKH _Data)
th(SDCLKH_Data)
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
3
1.5
-
-
-
td(SDCLKL_Add)
2.0
td(SDCLKL- SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
1.5(2)
ns
0
-
1
-
0
-
-
2.0
-
0.5
1. Guaranteed by characterization results.
2. Using PC2_C I/O adds 4.5 ns to this timing.
(1)
Table 72. LPSDR SDRAM read timings
Symbol
Parameter
Min
Max
Unit
2Tfmc_ker_ck
0.5
–
tW(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck+0.5
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
3
2.5
-
-
-
td(SDCLKL_Add)
2
td(SDCLKL_SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
1.5(2)(3)
ns
0
-
1
-
-
0
-
2
-
0.5
1. Guaranteed by characterization results.
2. Using PC2 I/O adds 4 ns to this timing.
3. Using PC2_C I/O adds 16.5 ns to this timing.
148/227
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Electrical characteristics
Figure 31. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
th(SDCLKL_NCAS)
th(SDCLKL_NWE)
td(SDCLKL_NCAS)
td(SDCLKL_NWE)
td(SDCLKL_Data)
Data1
Data2
Datai
Datan
FMC_D[31:0]
td(SDCLKL_NBL)
FMC_NBL[3:0]
th(SDCLKL_Data)
MS32752V2
(1)
Table 73. SDRAM Write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5
td(SDCLKL _Data
th(SDCLKL _Data)
td(SDCLKL_Add)
)
-
0.5
-
2
-
2
td(SDCLKL_SDNWE)
th(SDCLKL_SDNWE)
td(SDCLKL_ SDNE)
th(SDCLKL-_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
td(SDCLKL_SDNCAS)
-
2
0
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
-
1.5(2)
0
-
1
-
-
0
-
2
-
0.5
1. Guaranteed by characterization results.
2. Using PC2_C I/O adds 4.5 ns to this timing.
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Electrical characteristics
STM32H723xE/G
(1)
Table 74. LPSDR SDRAM Write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5
td(SDCLKL _Data
)
-
0
-
2
th(SDCLKL _Data)
td(SDCLKL_Add)
-
2.5
td(SDCLKL-SDNWE)
th(SDCLKL-SDNWE)
td(SDCLKL- SDNE)
th(SDCLKL- SDNE)
td(SDCLKL-SDNRAS)
th(SDCLKL-SDNRAS)
td(SDCLKL-SDNCAS)
td(SDCLKL-SDNCAS)
-
2
0
-
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
1.5(2)(3)
0
-
-
1
-
0
-
2
-
0.5
1. Guaranteed by characterization results.
2. Using PC2 I/O adds 4 ns to this timing.
3. Using PC2_C I/O adds 16.5 ns to this timing.
6.3.19
Octo-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 75 and Table 77 for OCTOSPI
are derived from tests performed under the ambient temperature, f frequency and V
HCLK
DD
supply voltage conditions summarized in Table 12: General operating conditions, with the
following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.5 V
DD
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)(2)
Table 75. OCTOSPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71 V < VDD < 3.6 V,
VOS0,
-
-
92
CLOAD = 15 pF
1.71 V < VDD < 3.6 V,
VOS0, CLOAD =20 pF
F(CLK)
OCTOSPI clock frequency
-
-
-
-
90
MHz
2.7 V < VDD < 3.6 V,
VOS0,
140
CLOAD = 20 pF
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Electrical characteristics
(1)(2)
Table 75. OCTOSPI characteristics in SDR mode
(continued)
Typ
Symbol
Parameter
Conditions
Min
Max
Unit
tw(CKH)
t(CK)/2
-
-
t(CK)/2+1
t(CK)/2
OCTOSPI clock high and low PRESCALER[7:0] = n
time, even division = 0,1,3,5
tw(CKL)
tw(CKH)
t(CK)/2–1
(n/2)*t(CK)
/
(n/2)*t(CK)
(n+1)+1
/
-
-
(n+1)
OCTOSPI clock high and low PRESCALER[7:0] = n
time, odd division
= 2,4,6,8
(n/2+1)*t(CK)
/
(n/2+1)*t(CK)
/(n+1)
tw(CKL)
ns
(n+1)–1
(3)
ts(IN)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
-
-
-
-
3.0
1.5
-
-
-
-
(3)
th(IN)
-
tv(OUT)
th(OUT)
0.5
-
1(4)
-
0
1. All values apply to Octal and Quad-SPI mode.
2. Guaranteed by characterization results.
3. Delay block bypassed.
4. Using PC2 or PC3 I/O in the data bus adds 4 ns to this timing value.
Figure 32. OCTOSPI SDR read/write timing diagram
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
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Electrical characteristics
STM32H723xE/G
(1)(2)
Table 76. OCTOSPI characteristics in DTR mode (no DQS)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71 V < VDD < 3.6 V,
VOS0, CLOAD = 15 pF
-
-
-
-
90(4)
1.71 V < VDD < 3.6 V,
VOS0, CLOAD = 20 pF
(3)
FCK
OCTOSPI clock frequency
-
-
87(4)
110
MHz
2.7 V < VDD < 3.6 V,
VOS0, CLOAD = 20 pF
tw(CKH)
tw(CKL)
t(CK)/2
-
-
t(CK)/2+1
t(CK)/2
OCTOSPI clock high and
low time, even division
PRESCALER[7:0] = n
= 0,1,3,5
t(CK)/2–1
(n/2)*t(CK)
/
(n/2)*t(CK)
(n+1)+1
/
tw(CKH)
-
-
-
(n+1)
OCTOSPI clock high and
low time, odd division
PRESCALER[7:0] = n
= 2,4,6,8
(n/2+1)*t(CK)/(
n+1) – 1
(n/2+1)*
tw(CKL)
t
(CK)/(n+1)
tsr(IN)
Data input setup time
Data input hold time
-
3.0
-
(5)
tsf(IN)
ns
thr(IN)
-
1.50
-
-
(5)
thf(IN)
DHQC = 0
-
-
6
7(6)
tvr(OUT)
tvf(OUT)
Data output valid time
Data output hold time
DHQC = 1,
Prescaler = 1,2 ...
tpclk/4+ tpclk/4+1.25
(6)
1
DHQC = 0
4.5
-
-
-
-
thr(OUT)
thf(OUT)
DHQC = 1,
Prescaler = 1,2 ...
t
pclk/4
1. All values apply to Octal and Quad-SPI mode.
2. Guaranteed by characterization results.
3. DHQC must be set to reach the mentioned frequency.
4. Using PC2 or PC3 I/O in the data bus decreases the frequency to 47 MHz.
5. Delay block bypassed.
6. Using PC2 or PC3 I/O in the data bus adds 4 ns to this timing value.
Figure 33. OCTOSPI DTR mode timing diagram
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
tsr(IN)thr(IN)
D5
tsf(IN) thf(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv36879V1
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Electrical characteristics
(1)
Table 77. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2,7 V < VDD < 3.6 V,
VOS0, CLOAD = 20 pF
-
-
100
(2)(3)
FCK
OCTOSPI clock frequency
MHz
1.71 V < VDD < 3.6 V,
VOS0, CLOAD = 20 pF
-
-
100(4)
tw(CKH)
tw(CKL)
t(CK)/2
-
-
t(CK)/2+1
t(CK)/2
OCTOSPI clock high and
low time, even division
PRESCALER[7:0] = n =
0,1,3,5
ns
ns
t(CK)/2–1
(n/2)*t(CK)
/
(n/2)*t(CK)
(n+1)+1
/
tw(CKH)
tw(CKL)
-
-
(n+1)
OCTOSPI clock high and
low time, odd division
PRESCALER[7:0] = n =
2,4,6,8
(n/2+1)*t(CK)/(
n+1)–1
(n/2+1)*t(CK)
/
(n+1)
tv(CK)
th(CK)
Clock valid time
Clock hold time
-
-
-
-
-
t(CK)+1
-
t(CK)/2
CK,CK crossing level on CK
rising edge
VODr(CK)
VODf(CK)
VDD = 1.8 V
VDD = 1.8 V
922
-
-
1229
1277
mV
CK,CK crossing level on CK
falling edge
1000
tw(CS)
tv(DQ)
tv(DS)
th(DS)
Chip select high time
Data input vallid time
-
-
-
-
3*t(CK)
-
-
-
-
-
-
-
-
0
0
0
Data strobe input valid time
Data strobe input hold time
Data strobe output valid
time
tv(RWDS)
-
-
-
3 x t(CK)
tsr(DQ)
tsf(DQ)
thr(DQ)
thf(DQ)
Rising edge
Falling edge
Rising edge
Falling edge
DHQC = 0
0
0
1
1
-
-
-
-
Data input setup time
Data input hold time
-
-
-
-
-
ns
6
7(5)
Data output valid time rising
edge
tvr(OUT)
tvf(OUT)
thr(OUT)
thf(OUT)
DHQC = 1,
Prescaler = 1,2...
tpclk/4+ tpclk/4+1.25
-
-
(5)
1
DHQC = 0
5.5
6(5)
Data output valid time
falling edge
DHQC = 1,
Prescaler = 1,2...
tpclk/4+ tpclk/4+0.75
0.5
-
(5)
DHQC = 0
4.5
-
-
-
-
-
-
-
-
Data output hold time rising
edge
DHQC = 1,
Prescaler = 1,2...
t
pclk/4
4.5
DHQC = 0
Data output hold time falling
edge
DHQC = 1,
Prescaler = 1,2...
tpclk/4
1. Guaranteed by characterization results.
DS13313 Rev 2
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2. Maximum frequency values are given for a RWDS to DQ skew of maximum +/-1.0 ns.
3. Activating DHQC is mandatory to reach this frequency
4. Using PC2 or PC3 I/O on data bus decreases the frequency to 47 MHz.
5. Using PC2 or PC3 I/O on the data bus adds 4 ns to this timing value.
Figure 34. OCTOSPI Hyperbus clock timing diagram
tr(CK)
tw(CKH)
tw(CKL)
t(CK)
tf(CK)
VOD(CK)
CK
MSv47732V2
Figure 35. OCTOSPI Hyperbus read timing diagram
tw(CS)
CS#
th(CK)
tv(CK)
tACC= Initial Access
CK
tv(RWDS)
tv(DS)
th(DS)
RWDS
tv(OUT)
th(OUT)
tv(DQ)
ts(DQ)
th(DQ)
Latency Count
Dn
Dn
Dn+1
A
Dn+1
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
A
B
B
Command-Address
Memory drives DQ[7:0] and RWDS
MSv47733V2
Host drives DQ[7:0] and Memory drives RWDS
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Electrical characteristics
Figure 36. OCTOSPI Hyperbus write timing diagram
tw(CS)
CS#
CK
Read Write Recovery
tv(CK)
Access Latency
th(CK)
th(OUT)
tv(OUT)
tv(RWDS)
High = 2x Latency Count
Low = 1x Latency Count
RWDS
Latency Count
th(OUT)
th(OUT)
tv(OUT)
tv(OUT)
Dn
A
Dn
B
Dn+1
A
Dn+1
B
47:40 39:32 31:24 23:16 15:8
7:0
DQ[7:0]
Command-Address
Host drives DQ[7:0] and RWDS
Host drives DQ[7:0] and Memory drives RWDS
MSv47734V2
6.3.20
Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 78 for Delay Block are derived
from tests performed under the ambient temperature, f frequency and VDD supply
rcc_c_ck
voltage summarized in Table 12: General operating conditions, with the following
configuration:
Table 78. Delay Block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tinit
t∆
Initial delay
Unit Delay
-
-
900
28
1300
33
1900
41
ps
-
6.3.21
16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 79, Table 80 and Table 81 are
derived from tests performed under the ambient temperature, f frequency and V
PCLK2
DDA
supply voltage conditions summarized in Table 12: General operating conditions.
(1)(2)
Table 79. 16-bit ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage for ADC
ON
V
-
1.62
1.62
-
-
3.6
DDA
V
V
≥ 2 V
V
DDA
Positive
reference
voltage
DDA
V
V
REF+
V
< 2 V
DDA
DDA
Negative
reference
voltage
V
-
V
SSA
REF-
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
(1)(2)
Table 79. 16-bit ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BOOST = 11
BOOST = 10
BOOST = 01
BOOST = 00
0.12
0.12
0.12
-
-
-
-
-
50
25
ADC clock
frequency
f
1.62 V ≤ VDDA ≤ 3.6 V
MHz
ADC
12.5
6.25
Resolution = 16 bits,
>2.5 V
f
f
= 36 MHz
SMP = 1.5
-
-
3.60
ADC
V
DDA
T
= 90 °C
J
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 16 bits,
= 37 MHz
= 50 MHz
= 50 MHz
= 50 MHz
= 50 MHz
= 49 MHz
= 50 MHz
= 50 MHz
= 50 MHz
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 1.5
SMP = 1.5
SMP = 1.5
SMP = 1.5
SMP = 1.5
SMP = 1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.35
5.00
5.50
7.10
8.30
4.90
5.50
6.70
8.30
ADC
ADC
ADC
ADC
ADC
f
f
f
f
T = 125 °C
J
Sampling rate
for Direct
channels
f
ADC
ADC
ADC
ADC
f
f
f
T = 140 °C
J
f
f
= 32 MHz
SMP = 2.5
-
-
2.90
ADC
V
>2.5 V
DDA
T
= 90 °C
J
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 16 bits
resolution = 14 bits
resolution = 12 bits
resolution = 10 bits
resolution = 8 bits
resolution = 12 bits
resolution = 10 bits
resolution = 8 bits
= 31 MHz
= 33 MHz
= 39 MHz
= 48 MHz
= 50 MHz
= 37 MHz
= 46 MHz
= 50 MHz
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.80
3.30
4.30
6.00
7.10
4.10
5.70
7.10
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
f
f
f
f
f
f
f
(3)
f
MSps
s
Sampling rate
for Fast
channels
T = 125 °C
J
T
= 140 °C
= 90 °C
J
T
J
Sampling rate
for Slow
channels,
T = 125 °C
J
f
= 10 MHz
SMP = 1.5
1.00
ADC
BOOST = 0,
f
= 10 MHz
ADC
T
= 140 °C
J
External trigger
period
1/
t
Resolution = 16 bits
-
-
-
10
TRIG
f
ADC
Conversion
voltage range
(4)
AIN
V
-
-
0
V
REF+
V
Common mode
input voltage
V
/2
V
/
V
/2
REF
+ 10%
REF
− 10%
REF
2
V
V
CMIV
156/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
(1)(2)
Table 79. 16-bit ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resolution = 16 bits, T = 125 °C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
170
435
J
Resolution = 14 bits, T = 125 °C
J
External input
impedance
(5)
R
Resolution = 12 bits, T =125 °C
1,150
5,650
26,500
Ω
AIN
J
Resolution = 10 bits, T = 125 °C
J
Resolution = 8 bits, T = 125 °C
J
Internal sample
and hold
capacitor
C
-
-
-
4
5
-
-
10
-
pF
us
ADC
t
ADC LDO
startup time
ADCVREG
_STUP
-
conver
sion
cycle
ADC Power-up
time
t
LDO already started
1
STAB
Offset and
linearity
calibration time
t
-
-
16,5010
1,280
1/f
1/f
CAL
ADC
ADC
t
Offsetcalibration
time
OFF_
CAL
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
1.5
2
-
2.5
2.5
2.5
2.25
3.5
3.5
3.5
Trigger
conversion
latency regular
and injected
channelswithout
conversion abort
-
t
1/f
1/f
LATR
ADC
-
-
-
2.5
-
-
Trigger
conversion
latency regular
injected
3
-
t
LATRINJ
ADC
-
-
channels
aborting a
regular
conversion
CKMODE = 11
-
-
-
-
3.25
t
Sampling time
1.5
810.5
1/f
1/f
S
ADC
ADC
Total conversion
time (including
sampling time)
ts + 0.5
+ N/2
t
Resolution = N bits
-
-
CONV
DS13313 Rev 2
157/227
208
Electrical characteristics
STM32H723xE/G
(1)(2)
Table 79. 16-bit ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ADC
consumption on
Resolution = 16 bits, f
Resolution = 14 bits, f
= 25 MHz
-
-
-
-
-
-
1,440
1,350
-
-
ADC
ADC
= 30 MHz
= 40 MHz
V
,
DDA
BOOST=11,
Differential
mode
Resolution = 12 bits, f
-
-
-
990
-
ADC
ADC
consumption on
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
1,080
810
-
-
V
,
DDA
BOOST=10,
Differential
mode,
Resolution = 12 bits
-
-
-
585
-
f
= 25 MHz
ADC
I
_
D
DDA
(ADC)
ADC
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
630
432
-
-
consumption on
V
,
DDA
BOOST=01,
Differential
mode,
Resolution = 12 bits
-
-
-
315
-
f
= 12.5 MHz
ADC
ADC
consumption on
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
360
270
-
-
V
DDA,
BOOST=00,
Differential
mode,
Resolution = 12 bits
-
-
-
225
-
f
= 6.25 MHz
ADC
ADC
consumption on
Resolution = 16 bits, f
=25 MHz
-
-
-
-
-
-
720
675
-
-
ADC
Resolution = 14 bits, f
Resolution = 12 bits, f
=30 MHz
=40 MHz
V
,
ADC
DDA
BOOST=11,
Single-ended
mode
µA
-
-
-
495
-
ADC
ADC
consumption on
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
540
405
-
-
V
,
DDA
BOOST=10,
Singl-ended
mode,
Resolution = 12 bits
-
-
-
292.5
-
f
= 25 MHz
ADC
I
_
DDA SE
(ADC)
ADC
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
315
216
-
-
consumption on
V
,
DDA
BOOST=01,
Single-ended
mode,
Resolution = 12 bits
-
-
-
157.5
-
f
= 12.5 MHz
ADC
ADC
consumption on
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
180
135
-
-
V
DDA
BOOST=00,
Single-ended
mode
Resolution = 12 bits
-
-
-
112.5
-
f
=6.25 MHz
ADC
f
=50 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
220
180
120
80
-
-
-
-
-
ADC
f
=25 MHz
ADC
ADC
consumption on
I
DD
f
f
=12.5 MHz
=6.25 MHz
ADC
ADC
(ADC)
V
DD
f
=3.125 MHz
ADC
1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
158/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
3. These values are valid for TFBGA100, UFBGA169 and UFBGA176+25 packages and one ADC. The values for other
packages and multiple ADCs may be different.
4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA
.
5. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit
resolutions.
(1)(2)
Table 80. Minimum sampling time vs R
(16-bit ADC)
AIN
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
16 bits
47
47
7.37E-08
6.29E-08
6.84E-08
7.80E-08
9.86E-08
1.32E-07
5.32E-08
5.74E-08
6.58E-08
8.37E-08
1.11E-07
1.56E-07
2.16E-07
3.01E-07
4.34E-08
4.68E-08
5.35E-08
6.68E-08
8.80E-08
1.24E-07
1.69E-07
2.38E-07
3.45E-07
5.15E-07
7.42E-07
1.10E-06
1.14E-07
9.74E-08
1.02E-07
1.12E-07
1.32E-07
1.61E-07
8.00E-08
8.50E-08
9.31E-08
1.10E-07
1.34E-07
1.78E-07
2.39E-07
3.29E-07
6.51E-08
6.89E-08
7.55E-08
8.77E-08
1.08E-07
1.43E-07
1.89E-07
2.60E-07
3.66E-07
5.35E-07
7.75E-07
1.14E-06
1.72E-07
1.55E-07
1.58E-07
1.62E-07
1.80E-07
2.01E-07
1.29E-07
1.32E-07
1.40E-07
1.51E-07
1.73E-07
2.14E-07
2.68E-07
3.54E-07
1.08E-07
1.11E-07
1.16E-07
1.26E-07
1.40E-07
1.71E-07
2.13E-07
2.80E-07
3.84E-07
5.48E-07
7.78E-07
1.14E-06
68
14 bits
100
150
220
47
68
100
150
220
330
470
680
47
12 bits
68
100
150
220
330
470
680
1000
1500
2200
3300
10 bits
DS13313 Rev 2
159/227
208
Electrical characteristics
STM32H723xE/G
(1)(2)
Table 80. Minimum sampling time vs R
(16-bit ADC)
(continued)
AIN
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
47
68
3.32E-08
3.59E-08
4.10E-08
5.06E-08
6.61E-08
9.17E-08
1.24E-07
1.74E-07
2.53E-07
3.73E-07
5.39E-07
8.02E-07
1.13E-06
1.62E-06
2.36E-06
3.50E-06
5.10E-08
5.35E-08
5.83E-08
6.76E-08
8.22E-08
1.08E-07
1.40E-07
1.91E-07
2.70E-07
3.93E-07
5.67E-07
8.36E-07
1.18E-06
1.69E-06
2.47E-06
3.69E-06
8.61E-08
8.83E-08
9.22E-08
9.95E-08
1.11E-07
1.32E-07
1.63E-07
2.12E-07
2.85E-07
4.05E-07
5.75E-07
8.38E-07
1.18E-06
1.68E-06
2.45E-06
3.65E-06
100
150
220
330
470
680
8 bits
1000
1500
2200
3300
4700
6800
10000
15000
1. Guaranteed by design.
2. Data valid at up to 130 °C, with a 47 pF PCB capacitor, and VDDA=1.6 V.
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to PA6, PB1, PC4, PF11, PF13 for ADCx_INPx, and to PA7, PB0, PC5, PF12, PF14 for
ADCx_INNx.
5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.
160/227
DS13313 Rev 2
STM32H723xE/G
Symbol
Electrical characteristics
(1)(2)
Table 81. 16-bit ADC accuracy
Conditions(3)
Parameter
Min
Typ
Max
Unit
Single ended
Direct
-
-
-
-
-
+10/–20
±15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
channel
Differential
Single ended
Fast channel
+10/–20
±15
ET
Total undadjusted error
Differential
Single ended
Slow
±10
channel
Differential
±10
EO
EG
Offset error
Gain error
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±10
-
±15
LSB
Single ended
+3/–1
+4.5/–1
±11
ED
Differential linearity error
Integral linearity error
Effective number of bits
Differential
Single ended
Direct
channel
Differential
Single ended
Differential
±7
±13
EL
Fast channel
±7
Single ended
Differential
±10
Slow
channel
±6
Single ended
12.2
13.2
75.2
81.2
77.0
81.0
87
ENOB
SINAD
SNR
Bits
dB
Differential
Single ended
Differential
Signal-to-noise and
distortion ratio
Single ended
Differential
Signal-to-noise ratio
Single ended
Differential
THD
Total harmonic distortion
90
1. Guaranteed by characterization results for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V, BOOST=11 and 16-bit mode.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
affect the ADC accuracy.
and ΣI
does not
INJ(PIN)
INJ(PIN)
DS13313 Rev 2
161/227
208
Electrical characteristics
STM32H723xE/G
Figure 37. ADC accuracy characteristics (12-bit resolution)
V
V
DDA
4096
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
E
G
4095
4094
4093
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
E
O
L
E
D
1L SB
IDEAL
7
0
V
1
2
3
456
4093 4094 4095 4096
V
DDA
SSA
ai14395c
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 38. Typical connection diagram using the ADC
STM32
V
DD
Sample and hold ADC
V
T
converter
0.6 V
(1)
AIN
(1)
R
R
ADC
AINx
12-bit
converter
V
0.6 V
T
V
AIN
C
(1)
ADC
C
parasitic
I
1 μA
L
ai17534b
1. Refer to Table 79 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
162/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 39 or Figure 40,
depending on whether V is connected to V or not. The 100 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 39. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM32
(1)
VREF+
1 μF // 100 nF
VDDA
1 μF // 100 nF
(1)
VSSA/VREF+
MSv50648V1
1. When VREF+ and VREF- inputs are not available, they are internally connected to VDDA and VSSA
respectively.
,
Figure 40. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32
(1)
VREF+/VDDA
1 μF // 100 nF
(1)
VREF-/VSSA
MSv50649V1
1. When VREF+ and VREF- inputs are not available, they are internally connected to VDDA and VSSA
respectively.
,
DS13313 Rev 2
163/227
208
Electrical characteristics
STM32H723xE/G
6.3.22
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 82, Table 83 and Table 84 are
derived from tests performed under the ambient temperature and V
supply voltage
DDA
conditions summarized in Table 12: General operating conditions. In Table 82, Table 83 and
Table 84, f refers to f
.
adc_ker_ck
ADC
(1)(2)
Table 82. 12-bit ADC characteristics
Sym-
bol
Parameter
Conditions
Min
Typ
Max
Unit
Analog
power
supply for
ADC ON
V
-
1.62
-
3.6
DDA
Positive
reference
voltage
V
V
REF+
(3)
V
≥ V
1.62
-
-
V
DDA
REF+
DDA
-
Negative
reference
voltage
V
-
V
SSA
REF-
ADC clock
frequency
f
1,62 V ≤ V
≤ 3.6 V
1.5
-
-
-
-
-
75
5
MHz
ADC
DDA
f
= 75
MHz
ADC
Continuous
2.4 V ≤ V
1.6V ≤ V
2.4 V ≤ V
1.6 V ≤ V
≤ 3.6 V
≤ 3.6 V
≤ 3.6 V
≤ 3.6 V
-
-
-
-
DDA
DDA
DDA
DDA
and
Discontinuous
f
= 60
MHz
(5)
ADC
4
mode
Resolution
= 12 bits
SMP
= 2.5
–40 °C ≤ T ≤ 130 °C
J
f
= 50
ADC
3.33
2.53
(6)
MHz
Single mode
f
= 38
ADC
(6)
MHz
Continuous
and
f
= 75
MHz
ADC
1.6V ≤ V
≤ 3.6V
-
-
5.77
DDA
Discontinuous
(5)
mode
Resolution
= 10 bits
SMP
–40 °C ≤ T ≤ 130 °C
J
f
= 58 = 2.5
ADC
2.4 V ≤ V
1.6V ≤ V
≤ 3.6 V
≤ 3.6V
-
-
-
-
4.46
3.23
(6)
DDA
DDA
MHz
Single mode
Sampling
rate for
Direct
f
= 42
ADC
(6)
MHz
(4)
f
MSPS
S
Continuous
and
channels
f
= 75
MHz
ADC
1.6V ≤ V
≤ 3.6V
-
-
6.82
DDA
Discontinuous
(5)
mode
Resolution
= 8 bits
SMP
= 67 = 2.5
MHz
–40 °C ≤ T ≤ 130 °C
J
f
ADC
2.4 V ≤ V
1.6V ≤ V
≤ 3.6 V
≤ 3.6V
-
-
-
-
6.09
4.36
(6)
DDA
DDA
Single mode
f
= 48
ADC
(6)
MHz
Continuous
and
f
= 75
MHz
ADC
1.6V ≤ V
≤ 3.6V
-
-
8.33
DDA
Discontinuous
(5)
mode
Resolution
= 6 bits
SMP
= 75 = 2.5
–40 °C ≤ T ≤ 130 °C
J
f
ADC
2.4 V ≤ V
1.6V ≤ V
≤ 3.6 V
≤ 3.6V
-
-
-
-
8.33
6.11
(6)
DDA
DDA
MHz
Single mode
f
= 55
ADC
(6)
MHz
164/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
(1)(2)
Table 82. 12-bit ADC characteristics
(continued)
Sym-
Parameter
bol
Conditions
Min
Typ
Max
Unit
f
= 65
MHz
ADC
Continuous
and
2.4 V ≤ V
1.6V ≤ V
2.4 V ≤ V
1.6V ≤ V
≤ 3.6 V
≤ 3.6V
≤ 3.6 V
≤ 3.6V
-
-
-
-
-
-
-
-
4.33
3.87
2.13
1.73
DDA
DDA
DDA
DDA
Discontinuous
f
= 58
MHz
(5)
ADC
mode
Resolution
= 12 bits
SMP
= 2.5
–40 °C ≤ T ≤ 130 °C
J
f
= 32
ADC
(6)
MHz
Single mode
f
=
ADC
(6)
26 MHz
Continuous
and
f
= 75
MHz
ADC
1.6V ≤ V
≤ 3.6V
-
-
5.77
DDA
Discontinuous
(5)
mode
Resolution
= 10 bits
SMP
–40 °C ≤ T ≤ 130 °C
J
f
= 36 = 2.5
ADC
2.4 V ≤ V
1.6V ≤ V
≤ 3.6 V
≤ 3.6V
-
-
-
-
2.77
2.31
(6)
DDA
DDA
MHz
Single mode
Sampling
rate for fast
channels
f
= 30
ADC
(6)
MHz
Continuous
and
(VIN[0:5])
f
= 75
MHz
ADC
1.6V ≤ V
≤ 3.6V
-
-
6.82
DDA
Discontinuous
(5)
mode
(4)
f
S
Resolution
= 8 bits
SMP
=44 = 2.5
MHz
(conti-
nued)
–40 °C ≤ T ≤ 130 °C
MSPS
J
f
ADC
2.4 V ≤ V
1.6V ≤ V
≤ 3.6 V
≤ 3.6V
-
-
-
-
4.00
3.18
(6)
DDA
DDA
Single mode
f
= 35
ADC
(6)
MHz
Continuous
and
f
= 75
MHz
ADC
1.6V ≤ V
≤ 3.6V
-
-
8.33
DDA
Discontinuous
(5)
mode
Resolution
= 6 bits
SMP
= 56 = 2.5
MHz
–40 °C ≤ T ≤ 130 °C
J
f
ADC
2.4 V ≤ V
1.6V ≤ V
≤ 3.6 V
≤ 3.6V
-
-
-
-
-
-
-
-
-
-
-
-
6.22
4.66
1.00
1.28
1.63
2.08
(6)
DDA
DDA
Single mode
f
= 42
ADC
(6)
MHz
Resolution
= 12 bits
Resolution
= 10 bits
Sampling
rate for slow
channels
f
= 15 SMP
ADC
-
-
–40 °C ≤ T ≤ 130 °C
(6)
J
MHz
= 2.5
Resolution
= 8 bits
Resolution
= 6 bits
External
trigger
period
t
Resolution = 12 bits
-
-
-
15
1/f
ADC
TRIG
Conversion
voltage
range
V
-
-
0
V
REF+
AIN
V
Common
mode input
voltage
V
REF
/2−
10%
V
V
/2
REF
+ 10%
REF
/2
V
CMIV
Resolution = 12 bits, T = 125 °C
-
-
-
-
-
-
-
-
220
J
External
input
Resolution = 10 bits, T = 125 °C
J
2100
R
AIN
(7)
Ω
Resolution = 8 bits, T = 125 °C
J
12000
80000
impedance
Resolution = 6 bits, T = 125 °C
J
DS13313 Rev 2
165/227
208
Electrical characteristics
STM32H723xE/G
(1)(2)
Table 82. 12-bit ADC characteristics
(continued)
Sym-
bol
Parameter
Conditions
Min
Typ
Max
Unit
Internal
sample and
hold
C
-
-
5
-
pF
ADC
capacitor
t
ADCV
ADC LDO
startup time
-
-
1
5
-
10
-
µs
REG_
STUP
con-
version
cycle
ADC power-
up time
t
LDO already started
STAB
Offset
calibration
time
t
OFF_
CAL
-
135
-
-
Trigger
conversion
latency for
regular and
injected
CKMODE = 00
CKMODE = 01
CKMODE = 10
1.5
2
-
2.5
2.5
2.5
-
-
-
t
LATR
channels
without
aborting the
conversion
CKMODE = 11
-
-
2.25
Trigger
conversion
latency for
regular and
injected
CKMODE = 00
CKMODE = 01
CKMODE = 10
2.5
3
-
3.5
3.5
3.5
-
-
1/f
ADC
-
t
LATR
INJ
channels
when a
regular
conversion
is aborted
CKMODE = 11
-
-
-
3.25
Sampling
time
t
-
2.5
640.5
S
Total
conversion
time
(including
sampling
time)
t
+
S
t
N-bits resolution
0.5 +
-
-
CONV
N
ADC
consumption
f = 5 MSPS
-
-
430
133
-
-
S
f
= 1 MSPS
I
on V
and
,
S
DDA_
D(ADC)
DDA
V
REF
Differential
mode
f
f
= 0.1 MSPS
-
51
-
S
µA
ADC
consumption
f = 5 MSPS
-
-
350
122
-
-
S
I
DDA_
SE
f
= 1 MSPS
on V
and
,
S
DDA
V
REF
(ADC)
Single-
ended mode
= 0.1 MSPS
-
-
47
-
-
S
ADC
consumption
I
µA/
MHz
DD
(ADC)
-
2.4
on V per
DD
f
ADC
1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA
4. Guaranteed by characterization for BGA and CSP packages. The values for LQFP packages may be different.
.
166/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
5. The conversion of the first element in the group is excluded.
6. fADC value corresponds to the maximum frequency that can be reached considering a 2.5 sampling period. For other SMPy
sampling periods, the maximum frequency is fADC value * SMPy / 2.5 with a limitation to 75 MHz.
7. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. It is otherwise specified.
(1)(2)
Table 83. Minimum sampling time vs R
(12-bit ADC)
AIN
Minimum sampling time (s)
Direct channels(3) Fast channels(4) Slow channels(5)
Resolution
RAIN (Ω)
47
68
5.55E-08
5.76E-08
6.17E-08
7.02E-08
8.59E-08
1.11E-07
1.46E-07
1.98E-07
4.90E-08
5.07E-08
5.41E-08
6.18E-08
7.51E-08
9.46E-08
1.22E-07
1.63E-07
2.27E-07
3.27E-07
4.53E-07
6.56E-07
7.04E-08
7.22E-08
7.65E-08
8.45E-08
1.00E-07
1.26E-07
1.61E-07
2.17E-07
6.06E-08
6.27E-08
6.67E-08
7.50E-08
8.70E-08
1.07E-07
1.34E-07
1.77E-07
2.42E-07
3.40E-07
4.86E-07
6.93E-07
1.03E-07
1.05E-07
1.07E-07
1.13E-07
1.22E-07
1.41E-07
1.69E-07
2.25E-07
8.77E-08
8.95E-08
9.22E-08
9.59E-08
1.04E-07
1.17E-07
1.42E-07
1.86E-07
2.43E-07
3.35E-07
4.73E-07
6.72E-07
100
150
220
330
470
680
47
12 bits
68
100
150
220
330
470
680
1000
1500
2200
3300
10 bits
DS13313 Rev 2
167/227
208
Electrical characteristics
STM32H723xE/G
(1)(2)
Table 83. Minimum sampling time vs R
(12-bit ADC)
(continued)
AIN
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct channels(3)
Fast channels(4) Slow channels(5)
47
68
4.35E-08
4.47E-08
4.72E-08
5.33E-08
6.26E-08
7.84E-08
9.80E-08
1.28E-07
1.76E-07
2.49E-07
3.50E-07
5.09E-07
7.00E-07
9.84E-07
1.43E-06
2.10E-06
3.79E-08
3.88E-08
4.09E-08
4.48E-08
5.07E-08
6.04E-08
7.37E-08
9.31E-08
1.23E-07
1.71E-07
2.39E-07
3.43E-07
4.72E-07
6.65E-07
9.54E-07
1.40E-06
5.31E-08
5.48E-08
5.79E-08
6.35E-08
7.26E-08
8.80E-08
1.07E-07
1.39E-07
1.88E-07
2.66E-07
3.63E-07
5.27E-07
7.28E-07
1.03E-06
1.48E-06
2.18E-06
4.58E-08
4.69E-08
4.89E-08
5.25E-08
5.81E-08
6.79E-08
8.10E-08
1.01E-07
1.32E-07
1.82E-07
2.50E-07
3.57E-07
4.92E-07
6.89E-07
9.88E-07
1.45E-06
7.36E-08
7.47E-08
7.63E-08
7.88E-08
8.47E-08
9.48E-08
1.14E-07
1.43E-07
1.90E-07
2.64E-07
3.63E-07
5.24E-07
7.09E-07
1.00E-06
1.44E-06
2.11E-06
5.74E-08
5.81E-08
5.93E-08
6.14E-08
6.58E-08
7.46E-08
8.60E-08
1.04E-07
1.34E-07
1.82E-07
2.49E-07
3.49E-07
4.81E-07
6.68E-07
9.54E-07
1.39E-06
100
150
220
330
470
680
8 bits
1000
1500
2200
3300
4700
6800
10000
15000
47
68
100
150
220
330
470
680
6 bits
1000
1500
2200
3300
4700
6800
10000
15000
1. Guaranteed by design.
2. Data valid up to 130 °C, with a 22 pF PCB capacitor and VDDA = 1.62 V.
168/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to ADCx_INx[0:5].
5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.
(1)(2)
Table 84. 12-bit ADC accuracy
Symbol
Parameter
Conditions
Min
Typ Max Unit
Single
ended
-
-
-
-
-
3.5
2.5
3.5
2.5
3.5
5
3
5
3
5
Direct channel
Differential
Single
ended
Total
unadjusted
error
ET
Fast channel
Slow channel
Differential
Single
ended
Differential
-
-
2.5
3
EO
EG
Offset error
Gain error
-
-
+/-2
+/-5
TBD
-
-
-
-
(3)
±LSB
+/- +1.5/-
0.75
Single ended
Differential
Differential
linearity
error
1
ED
+1.25
/-1
+/-0.5
Single
ended
-
-
-
-
-
+/-1 +/-2.5
+/-1 +/-2
+/-1 +/-2.5
+/-1 +/-2
+/-1 +/-2.5
Direct channel
Differential
Single
ended
Integral
linearity
error
EL
Fast channel
Slow channel
Differential
Single
ended
Differential
-
-
+/-1
11.2
+/-2
-
Effective
number of
bits
Single ended
ENOB
SINAD
bits
Differential
-
-
11.5
68.9
-
-
Signal-to-
noise and
distortion
ratio
Single ended
Differential
-
71.1
-
Single ended
Differential
-
-
-
69.1
71.4
-79.6
-
-
-
Signal-to-
noise ratio
dB
SNR
THD
Total
harmonic
distortion
Single ended
Differential
-
-81.8
-
DS13313 Rev 2
169/227
208
Electrical characteristics
STM32H723xE/G
1. Guaranteed by characterization for BGA packages. The maximum values are preliminary data. The values for LQFP
packages may be different.
2. ADC DC accuracy values are measured after internal calibration in Continuous and Discontinuous mode.
3. TBD stands for “to be defined”.
6.3.23
DAC characteristics
(1)
Table 85. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
-
1.8
3.3
-
3.6
VREF+
Positive reference voltage
1.80
VDDA
V
Negative reference
voltage
VREF-
-
-
5
VSSA
-
-
-
connected
to VSSA
-
-
DAC output buffer
ON
RL
Resistive Load
connected
to VDDA
kΩ
25
RO
Output Impedance
DAC output buffer OFF
10.3
-
13
-
16
Output impedance
sample and hold mode,
output buffer ON
VDD = 2.7 V
1.6
DAC output buffer
ON
RBON
kΩ
kΩ
VDD = 2.0 V
VDD = 2.7 V
VDD = 2.0 V
-
-
-
-
-
-
2.6
Output impedance
sample and hold mode,
output buffer OFF
17.8
18.7
DAC output buffer
OFF
RBOFF
CL
DAC output buffer OFF
Sample and Hold mode
-
-
-
50
1
pF
µF
Capacitive Load
CSH
0.1
VDDA
−0.2
DAC output buffer ON
DAC output buffer OFF
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
0
-
-
VREF+
3
±0.5 LSB
2.05
1.97
1.67
1.66
1.65
Settling time (full scale:
for a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
±1 LSB
±2 LSB
±4 LSB
±8 LSB
-
2.87
2.84
2.78
2.7
Normal mode, DAC
output buffer ON,
CL ≤ 50 pF,
-
tSETTLING
µs
RL ≥ 5 ㏀
-
-
Normal mode, DAC output buffer
OFF, ±1LSB CL=10 pF
-
-
1.7
5
2
Wakeup time from off
state (setting the ENx bit
in the DAC Control
register) until the final
value of ±1LSB is reached
Normal mode, DAC output buffer
7.5
ON, CL ≤ 50 pF, RL = 5 ㏀
(2)
tWAKEUP
µs
Normal mode, DAC output buffer
2
5
OFF, CL ≤ 10 pF
DC VDDA supply rejection Normal mode, DAC output buffer
PSRR
-
−80
−28
dB
ratio
ON, CL ≤ 50 pF, RL = 5 ㏀
170/227
DS13313 Rev 2
STM32H723xE/G
Symbol
Electrical characteristics
(1)
Table 85. DAC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
Sampling time in Sample
and Hold mode
MODE<2:0>_V12=100/101
(BUFFER ON)
-
0.7
2.6
ms
CL=100 nF
MODE<2:0>_V12=110
(BUFFER OFF)
-
-
11.5
18.7
0.6
(code transition between
the lowest input code and
the highest input code
when DAC_OUT reaches
the ±1LSB final value)
tSAMP
MODE<2:0>_V12=111
(INTERNAL BUFFER OFF)
0.3
(3)
µs
Ileak
CIint
Output leakage current
-
-
nA
pF
Internal sample and hold
capacitor
1.8
50
2.2
2.6
-
Middle code offset trim
time
Minimum time to verify the each
code
tTRIM
-
µs
VREF+ = 3.6 V
VREF+ = 1.8 V
-
-
850
425
-
-
Middle code offset for 1
trim code step
Voffset
µV
No load,
middlecode
(0x800)
-
-
360
490
-
-
DAC output buffer
ON
No load,
worst code
(0xF1C)
DAC quiescent
consumption from VDDA
IDDA(DAC)
No load,
DAC output buffer
OFF
middle/
worst code
(0x800)
-
20
-
360*TON
/
Sample and Hold mode,
CSH=100 nF
-
-
-
(TON+TOFF
)
-
-
-
(4)
No load,
middlecode
(0x800)
170
170
µA
DAC output buffer
ON
No load,
worst code
(0xF1C)
No load,
middle/
worst code
(0x800)
DAC consumption from
VREF+
DAC output buffer
OFF
I
DDV(DAC)
-
160
-
170*TON
/
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code)
-
-
(TON+TOFF
)
)
-
-
(4)
160*TON
/
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code)
(TON+TOFF
(4)
1. Guaranteed by design unless otherwise specified.
DS13313 Rev 2
171/227
208
Electrical characteristics
STM32H723xE/G
2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. Refer to Table 50: I/O static characteristics.
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
(1)
Table 86. DAC accuracy
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON
DAC output buffer OFF
10 bits
−2
−2
-
-
-
-
2
2
-
Differential non
linearity(2)
DNL
-
LSB
-
Monotonicity
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀
−4
-
4
INL
Integral non linearity(3)
LSB
DAC output buffer OFF,
−4
-
-
4
CL ≤ 50 pF, no RL
DAC output
buffer ON,
CL ≤ 50 pF,
RL ≥ 5 ㏀
V
REF+ = 3.6 V
-
±12
Offset error at code
0x800 (3)
VREF+ = 1.8 V
-
-
-
-
±25
±8
Offset
LSB
DAC output buffer OFF,
CL ≤ 50 pF, no RL
Offset error at code
0x001(4)
DAC output buffer OFF,
Offset1
-
-
-
-
±5
±5
LSB
LSB
CL ≤ 50 pF, no RL
DAC output
VREF+ = 3.6 V
Offset error at code
0x800 after factory
calibration
buffer ON,
OffsetCal
CL ≤ 50 pF,
RL ≥ 5 ㏀
VREF+ = 1.8 V
-
-
±7
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀
-
-
-
-
-
-
±1
±1
Gain
Gain error(5)
%
DAC output buffer OFF,
CL ≤ 50 pF, no RL
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀
±30
±12
±23
-
TUE
Total unadjusted error
DAC output buffer OFF, CL
50 pF, no RL
≤
LSB
Total unadjusted error DAC output buffer ON, CL ≤ 50 pF,
TUECal
-
-
-
after calibration
RL ≥ 5 ㏀
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
67.8
SNR
Signal-to-noise ratio(6)
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL,1 kHz, BW =
500 KHz
-
67.8
-
172/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
(1)
Table 86. DAC accuracy (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
-
−78.6
-
Total harmonic
distortion(6)
THD
dB
DAC output buffer OFF,
-
-
-
-
-
−78.6
67.5
67.5
10.9
10.9
-
-
-
-
-
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
Signal-to-noise and
distortion ratio(6)
SINAD
ENOB
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON,
CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
Effective number of
bits
bits
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
1. Guaranteed by characterization results.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5dBFS with Fsampling=1 MHz.
Figure 41. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
DAC_OUTx
12-bit
digital to
analog
converter
C
L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DS13313 Rev 2
173/227
208
Electrical characteristics
STM32H723xE/G
6.3.24
Voltage reference buffer characteristics
(1)
Table 87. VREFBUF characteristics
Conditions
Symbol
Parameter
Min
2.8
Typ
Max
3.6
Unit
VSCALE = 000
3.3
VSCALE = 001
Normal mode,
2.4
-
-
-
-
-
-
-
3.6
VDDA = 3.3 V
VSCALE = 010
VSCALE = 011
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
2.1
3.6
1.8
3.6
VDDA
Analog supply voltage
1.62
1.62
1.62
1.62
2.80
2.40
2.10
1.80
Degraded mode(2)
VSCALE = 000 2.4980 2.5000 2.5035
VSCALE = 001 2.0460 2.0490 2.0520
VSCALE = 010 1.8010 1.8040 1.8060
VSCALE = 011 1.4995 1.5015 1.5040
V
Normal mode at 30 °C,
Iload = 100 µA
VDDA
150 mV
−
Voltage Reference
Buffer Output, at 30 °C,
Iload= 100 µA
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
-
-
-
-
VDDA
VDDA
VDDA
VDDA
VREFBUF
_OUT
VDDA
150 mV
−
Degraded mode(2)
VDDA
150 mV
−
VDDA
150 mV
−
TRIM
CL
Trim step resolution
Load capacitor
-
-
-
-
-
±0.05
1
±0.1
1.50
%
0.5
µF
Equivalent Serial
Resistor of CL
esr
-
-
-
-
-
-
2
Ω
ILOAD
Static load current
-
-
-
-
4
-
mA
I
load = 500 µA
Iload = 4 mA
200
100
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
ppm/V
-
ppm/
mA
Iload_reg
Load regulation
500 µA ≤ ILOAD ≤ 4 mA Normal mode
−40 °C < TJ < +130 °C
-
-
50
-
-
Tcoeff
VREFINT
+ 100
ppm/
°C
Tcoeff
Temperature coefficient
DC
-
-
-
-
60
40
-
-
PSRR
Power supply rejection
dB
100KHz
174/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
(1)
Table 87. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
CL=0.5 µF
Min
Typ
300
500
650
Max
Unit
-
-
-
-
-
-
-
-
-
tSTART
Start-up time
CL=1 µF
µs
CL=1.5 µF
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
IINRUSH
-
-
8
-
mA
µA
ILOAD = 0 µA
-
-
-
-
-
-
15
16
32
25
30
50
VREFBUF
consumption from
VDDA
IDDA
ILOAD = 500 µA
(VREFBUF)
I
LOAD = 4 mA
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
6.3.25
Analog temperature sensor characteristics
Table 88. Temperature sensor characteristics
Symbol
Parameter
Min Typ Max Unit
(1)
TL
VSENSE linearity with temperature
-
-
-
3
°C
mV/°C
V
Avg_Slope(2) Average slope
2
-
(3)
V30
Voltage at 30°C ± 5 °C
-
0.62
-
25.2
-
tstart_run
Startup time in Run mode (buffer startup)
ADC sampling time when reading the temperature
Sensor consumption
-
-
-
µs
(1)
tS_temp
9
-
(1)
Isens
0.18 0.31
3.8 6.5
µA
(1)
Isensbuf
Sensor buffer consumption
-
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 89. Temperature sensor calibration values
Symbol
Parameter
Memory address
Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V
TS_CAL1
0x1FF1 E820 -0x1FF1 E821
Temperature sensor raw data acquired value at
110 °C, VDDA=3.3 V
TS_CAL2
0x1FF1 E840 - 0x1FF1 E841
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
6.3.26
Digital temperature sensor characteristics
(1)
Table 90. Digital temperature sensor characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
(2)
fDTS
Output Clock frequency
-
500
750
1150 kHz
Hz/°
(2)
TLC
Temperature linearity coefficient
VOS2
1660
2100
-
2750
C
TJ = −40°C to
−13
4
30°C
TTOTAL_ERROR
Temperature offset
measurement, all VOS
°C
(2)
TJ = 30°C to
Tjmax
−7
0
-
-
2
VOS2
0
Additional error due to supply
variation
TVDD_CORE
°C
1
VOS0, VOS1,
VOS3
−1
-
-
tTRIM
Calibration time
-
-
-
2
ms
116.00 μs
70.0 μA
Wake-up time from off state until
DTS ready bit is set
tWAKE_UP
-
67
DTS consumption on
VDD_CORE
IDDCORE_DTS
-
8.5
30
1. Guaranteed by design, unless otherwise specified.
2. Guaranteed by characterization results.
6.3.27
Temperature and V
monitoring
BAT
Table 91. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
26
4
-
KΩ
-
Ratio on VBAT measurement
Error on Q
-
-
Er(1)
–10
-
+10
%
µs
(1)
tS_vbat
ADC sampling time when reading VBAT input
High supply monitoring
9
-
-
-
-
-
VBAThigh
VBATlow
3.55
1.36
V
Low supply monitoring
-
1. Guaranteed by design.
Table 92. V
charging characteristics
BAT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBRS in PWR_CR3= 0
VBRS in PWR_CR3= 1
-
5
-
-
RBC
Battery charging resistor
KΩ
1.5
176/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Table 93. Temperature monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
TEMPhigh
TEMPlow
High temperature monitoring
Low temperature monitoring
-
-
117
-
-
°C
–25
6.3.28
Voltage booster for analog switch
(1)
Table 94. Voltage booster for analog switch characteristics
Symbol
VDD
Parameter
Supply voltage
Condition
Min Typ Max Unit
-
1.62 2.6 3.6
V
Booster startup time
-
-
-
-
-
-
-
50
µs
tSU(BOOST)
1.62 V ≤ VDD ≤ 2.7 V
2.7 V < VDD < 3.6 V
125
250
Booster consumption
µA
IDD(BOOST)
1. Guaranteed by characterization results.
6.3.29
Comparator characteristics
(1)
Table 95. COMP characteristics
Conditions
Symbol
VDDA
Parameter
Min
Typ
Max
Unit
Analog supply voltage
-
-
1.62
3.3
3.6
Comparator input voltage
range
VIN
0
-
VDDA
V
(2)
VBG
VSC
Scaler input voltage
Scaler offset voltage
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±5
0.2
0.8
140
2
±10
0.3
1
mV
µA
µs
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
Scaler static consumption
from VDDA
IDDA(SCALER)
tSTART_SCALER Scaler startup time
250
5
High-speed mode
Medium mode
Comparator startup time to
reach propagation delay
specification
tSTART
5
20
80
80
0.9
7
µs
Ultra-low-power mode
High-speed mode
Medium mode
15
50
0.5
2.5
50
0.5
2.5
±5
ns
µs
Propagation delay for
200 mV step with 100 mV
overdrive
Ultra-low-power mode
High-speed mode
Medium mode
(3)
tD
120
1.2
7
ns
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
µs
Ultra-low-power mode
Full common mode range
Voffset
Comparator offset error
±20
mV
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
(1)
Table 95. COMP characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
No hysteresis
Low hysteresis
-
4
0
-
10
20
30
400
22
37
52
600
Vhys
Comparator hysteresis
mV
Medium hysteresis
High hysteresis
Static
8
16
-
Ultra-low-
power mode
With 50 kHz
±100 mV overdrive
square signal
nA
µA
-
-
-
-
-
800
5
-
Static
7
Comparator consumption
from VDDA
With 50 kHz
±100 mV overdrive
square signal
IDDA(COMP)
Medium mode
6
-
100
-
Static
70
75
High-speed
mode
With 50 kHz
±100 mV overdrive
square signal
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 17: Embedded reference voltage.
3. Guaranteed by characterization results.
6.3.30
Operational amplifier characteristics
(1)
Table 96. Operational amplifier characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
Range
VDDA
CMIR
-
2
3.3
3.6
V
Common Mode Input
Range
-
0
-
-
VDDA
±1.5
±2.5
-
25°C, no load on output
-
-
VIOFFSET
Input offset voltage
mV
All voltages and
temperature, no load
-
ΔVIOFFSET
Input offset voltage drift
-
-
±3.0
μV/°C
Offset trim step at low
common input voltage
TRIMOFFSETP
-
-
-
1.1
1.1
1.5
1.5
TRIMLPOFFSETP
(0.1*VDDA
)
mV
Offset trim step at high
common input voltage
TRIMOFFSETN
-
TRIMLPOFFSETN
(0.9*VDDA
)
ILOAD
Drive current
-
-
-
-
-
-
500
270
μA
ILOAD_PGA
Drive current in PGA mode
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DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
(1)
Table 96. Operational amplifier characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CLOAD
Capacitive load
-
-
-
50
pF
Common mode rejection
ratio
CMRR
PSRR
-
-
80
66
-
-
dB
dB
CLOAD ≤ 50pf /
RLOAD ≥ 4 kꢁ(2) at 1 kHz,
Vcom=VDDA/2
Power supply rejection
ratio
50
4
Gain bandwidth for high
supply range
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
GBW
SR
7.3
12.3
MHz
V/µs
dB
Normal mode
-
-
3
-
-
Slew rate (from 10% and
90% of output voltage)
High-speed mode
24
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
AO
Open loop gain
59
90
129
φm
Phase margin
Gain margin
-
-
-
-
55
12
-
-
°
GM
dB
I
load=max or RLOAD=min,
Input at VDDA
VDDA
−100 mV
VOHSAT
High saturation voltage
Low saturation voltage
-
-
-
mV
Iload=max or RLOAD=min,
Input at 0 V
VOLSAT
-
-
100
CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kꢁ,
mode
0.8
0.9
3.2
2.8
follower
configuration
Wake up time from OFF
state
tWAKEUP
µs
CLOAD ≤ 50pf,
RLOAD ≥ 4 kꢁ,
follower
High
speed
mode
-
configuration
PGA gain = 2
−1
−2
-
-
-
-
-
-
-
-
-
-
-
-
1
2
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16
Non inverting gain error
value
−2.5
−3
2.5
3
−1
1
−1
1
PGA gain
Inverting gain error value
%
−2
2
−3
3
−1
1
−3
3
External non-inverting gain
error value
−3.5
−4
3.5
4
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
(1)
Table 96. Operational amplifier characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PGA Gain=2
PGA Gain=4
-
-
-
-
-
-
-
-
10/10
30/10
70/10
150/10
10/10
30/10
70/10
150/10
-
-
-
-
-
-
-
-
R2/R1 internal resistance
values in non-inverting
PGA mode(3)
PGA Gain=8
PGA Gain=16
PGA Gain = -1
PGA Gain = -3
PGA Gain = -7
PGA Gain = -15
kꢁ/
kꢁ
Rnetwork
R2/R1 internal resistance
values in inverting PGA
mode(3)
Resistance variation (R1
or R2)
Delta R
-
−15
-
15
%
Gain=2
Gain=4
-
-
-
-
-
-
-
-
GBW/2
GBW/4
GBW/8
GBW/16
5.00
-
-
-
-
-
-
-
-
PGA bandwidth for
different non inverting gain
MHz
Gain=8
Gain=16
Gain = -1
Gain = -3
Gain = -7
Gain = -15
PGA BW
3.00
PGA bandwidth for
different inverting gain
MHz
1.50
0.80
at
1 KHz
-
-
-
140
55
-
-
output loaded
with 4 kꢁ
nV/√
Hz
en
Voltage noise density
at
10 KHz
Normal
mode
570
1000
no Load,
quiescent mode,
follower
OPAMP consumption from
VDDA
IDDA(OPAMP)
µA
High-
speed
mode
-
610
1200
1. Guaranteed by design, unless otherwise specified.
2. RLOAD is the resistive load connected to VSSA or to VDDA
.
3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
180/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
6.3.31
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 97 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 12: General operating conditions.
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS0
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).
Table 97. DFSDM measured timing
Symbol
fDFSDMCLK
Parameter
Conditions
Min
Typ
Max
Unit
DFSDM
clock
1.62 < VDD < 3.6 V
-
-
fSYSCLK
SPI mode
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0)
-
-
20
fCKIN
(1/TCKIN
Input clock
frequency
MHz
)
SPI mode
(SITP[1:0] = 0,1),
Internal clock mode
(SPICKSEL[1:0] # 0)
-
-
-
-
20
20
55
Output clock
frequency
fCKOUT
1.62 < VDD < 3.6 V
Even
division,
CKOUTDIV
45
50
Output clock
frequency
duty cycle
= n, 1, 3, 5..
1.62 < VDD
DuCyCKOUT
%
< 3.6 V
Odd
division,
CKOUTDIV
= n, 2, 4, 6..
(((n/2+1)/(n+1)) (((n/2+1)/(n+1)) (((n/2+1)/(n+1))
*100)−5 *100) *100)+5
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
Table 97. DFSDM measured timing (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI mode
Input clock
high and low
time
twh(CKIN)
twl(CKIN)
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0)
TCKIN/2−0.5
TCKIN/2
-
SPI mode
Data input
setup time
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0)
tsu
2
1
-
-
-
-
-
ns
SPI mode
Data input
hold time
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0)
th
Manchester
data period
(recovered
clock period)
Manchester mode
(SITP[1:0] = 2,3),
Internal clock mode
(SPICKSEL[1:0] # 0)
(CKOUTDIV+1)
* TDFSDMCLK
(2*CKOUTDIV)
* TDFSDMCLK
TManchester
182/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Figure 42. Channel transceiver timing diagrams
(SPICKSEL=0)
SITP = 00
tr
tf
twl
twh
tsu
th
tsu
th
SITP = 01
SPICKSEL=3
SPICKSEL=2
SPICKSEL=1
tr
tf
twl
twh
tsu
th
SITP = 0
SITP = 1
tsu
th
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V2
DS13313 Rev 2
183/227
208
Electrical characteristics
STM32H723xE/G
6.3.32
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 98 for DCMI are derived from
tests performed under the ambient temperature, f
frequency and VDD supply voltage
HCLK
summarized in Table 12: General operating conditions, with the following configuration:
•
•
•
•
•
•
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS0
DD
(1)
Table 98. DCMI characteristics
Parameter
Symbol
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
Pixel Clock input
-
-
0.4
110
70
-
-
DCMI_PIXCLK
Dpixel
MHz
%
Pixel Clock input duty cycle
Data input setup time
30
2
t
su(DATA)
th(DATA)
Data hold time
1
-
tsu(HSYNC),
tsu(VSYNC)
ns
DCMI_HSYNC/ DCMI_VSYNC input setup time
DCMI_HSYNC/ DCMI_VSYNC input hold time
2
1
-
-
th(HSYNC),
th(VSYNC)
1. Guaranteed by characterization results.
Figure 43. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
th(HSYNC)
tsu(HSYNC)
th(HSYNC)
tsu(VSYNC)
tsu(DATA) th(DATA)
MS32414V2
184/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
6.3.33
Parallel synchronous slave interface (PSSI) characteristics
Unless otherwise specified, the parameters given in Table 99 and Table 100 for PSSI are
derived from tests performed under the ambient temperature, f
frequency and VDD
HCLK
supply voltage summarized in Table 12: General operating conditions.
(1)
Table 99. PSSI transmit characteristics
Symbol
Parameter
Min
Max
Unit
Frequency ratio
PSSI_PDCK/fHCLK
-
-
0.4
-
-
-
50
35(2)
70
PSSI_PDCK
PSSI Clock input
MHz
%
Dpixel
tov(DATA)
-
PSSI Clock input duty cycle
Data output valid time
-
30
-
10
(2)
14
-
toh(DATA)
tov((DE)
Data output hold time
DE output valid time
DE output hold time
RDY input setup time
RDY input hold time
4.5
-
-
10
-
ns
t
oh(DE)
4
tsu(RDY)
th(RDY)
0
-
0
-
1. Guaranteed by characterization results.
2. This value is obtained by using PA9, PA10 or PH4 I/O.
(1)
Table 100. PSSI receive characteristics
Symbol
Parameter
Min
Max
Unit
Frequency ratio
PSSI_PDCK/fHCLK
-
-
0.4
-
PSSI_PDCK
Dpixel
PSSI Clock input
PSSI Clock input duty cycle
Data input setup time
Data input hold time
DE input setup time
DE input hold time
-
110
MHz
%
30
1.5
0.5
2
70
-
tsu(DATA)
th(DATA)
tsu((DE)
-
-
ns
th(DE)
1
-
tov(RDY)
toh(RDY)
RDY output valid time
RDY output hold time
-
15
-
5.5
1. Guaranteed by characterization results.
DS13313 Rev 2
185/227
208
Electrical characteristics
STM32H723xE/G
6.3.34
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 101 for LCD-TFT are derived
from tests performed under the ambient temperature, f
frequency and VDD supply
HCLK
voltage summarized in Table 12: General operating conditions, with the following
configuration:
•
•
•
•
•
•
•
•
•
•
LCD_CLK polarity: high
LCD_DE polarity: low
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5VDD
IO Compensation cell activated.
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS0
(1)
Table 101. LTDC characteristics
Symbol
Parameter
2.7<VD <3.6 V, 20 pF
Min
Max
Unit
150
133
D
LTDC clock
output
frequency
fCLK
2.7<VD <3.6 V
D
-
MHz
%
1.62<VD <3.6 V
D
90/76.5(2)
DCLK
LTDC clock output duty cycle
45
55
tw(CLKH),
tw(CLKL)
Clock High time, low time
tw(CLK)//2−0.5
tw(CLK)/2+0.5
2.7<VD <3.6 V
2.0
D
tv(DATA)
th(DATA)
Data output valid time
-
1.62<VD <3.6 V
D
2.5/6.5(2)
Data output hold time
0
-
-
ns
tv(HSYNC),
tv(VSYNC),
tv(DE)
2.7<VD <3.6 V
1.5
D
HSYNC/VSYNC/DE output
valid time
1.62<VD <3.6 V
-
2.0
D
th(HSYNC),
HSYNC/VSYNC/DE output hold time
0
-
th(VSYNC)
,
th(DE)
1. Guaranteed by characterization results.
2. This value is valid when PA[9], PA[10], PA[11], PA[12], PA[15], PB[11], PH[4], PJ[8], PJ[9], PJ[10], PJ[11], PK[0], PK[1] or
PK[2] is used.
186/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Figure 44. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC)
tv(HSYNC)
LCD_HSYNC
th(DE)
tv(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
Pixel Pixel
1
Pixel
N
2
th(DATA)
Active width
HSYNCHorizontal
width back porch
Horizontal
back porch
One line
MS32749V1
Figure 45. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC)
tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
M lines data
VSYNC Vertical
width back porch
Active width
One frame
Vertical
back porch
MS32750V1
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
6.3.35
Timer characteristics
The parameters given in Table 102 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 102. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK
=
tTIMxCLK
1
-
275 MHz
tres(TIM)
Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK
=
tTIMxCLK
1
-
137.5 MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK/2
16/32
0
-
MHz
bit
f
TIMxCLK = 240 MHz
ResTIM
Timer resolution
Maximum possible count
with 32-bit counter
65536 ×
65536
tMAX_COUNT
tTIMxCLK
-
-
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 275 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
rcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2
F
.
6.3.36
Low-power timer characteristics
The parameters given in Table 103 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 103. LPTIMx characteristics
Symbol
tres(TIM)
Parameter
Timer resolution time
Min
1
Max
-
Unit
tTIMxCLK
fLPTIMxCLK
Timer kernel clock
0
137.5
MHz
Timer external clock frequency on Input1 and
Input2
fEXT
fLPTIMxCLK/2
0
ResTIM
Timer resolution
-
-
16
bit
tMAX_COUNT
tTIMxCLK
Maximum possible count
65536
1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.
2. Guaranteed by design.
188/227
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STM32H723xE/G
Electrical characteristics
6.3.37
Communication interfaces
I2C interface characteristics
2
The I C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
2
The I C timings requirements are guaranteed by design when the I C peripheral is properly
configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
2
Table 104. Minimum i2c_ker_ck frequency in all I C modes
Symbol
Parameter
Condition
Min
Unit
Standard-mode
Fast-mode
-
2
Analog Filtre ON
DNF=0
8
9
MHz
Analog Filtre OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
Analog Filtre ON
DNF=0
17
16
Fast-mode Plus
Analog Filtre OFF
DNF=1
-
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but still present.
DD
•
The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load C
supported in Fm+, which is given by these formulas:
Load
t
=0.8473xR
C
r(SDA/SCL)
P * Load
R
= (V -V
)/I
P(min)
DD OL(max) OL(max)
Where R is the I2C lines pull-up. Refer to Section 6.3.16: I/O port characteristics for
P
2
the I C I/Os characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
2
(1)
Table 105. I C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes
that are suppressed by analog
filter
tAF
50(2)
80(3)
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
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STM32H723xE/G
3. Spikes with widths above tAF(max) are not filtered.
USART interface characteristics
Unless otherwise specified, the parameters given in Table 106 for USART are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 12: General operating conditions, with the following
configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
(1)
Table 106. USART characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode,
1.62 V < VDD < 3.6 V
17.0
-
-
Slave receiver mode,
1.62 V < VDD < 3.6 V
45.0
27.0
37.0
fCK
USART clock frequency
MHz
Slave transmitter mode,
1.62 V < VDD < 3.6 V
-
-
Slave transmitter mode,
2.5 V < VDD < 3.6 V
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
tker+1
2
-
-
-
-
,
CK high and low time
Data input setup time
Master mode
1/fCK/2-2
1/fCK/2
1/fCK/2+2
tw(SCKL)
Master mode
Slave mode
Master mode
Slave mode
16
1.0
0
-
-
-
-
-
-
-
-
tsu(RX)
th(RX)
Data input hold time
Data output valid time
Data output hold time
ns
2.0
Slave mode, ,
1.62 V < VDD < 3.6 V
-
-
12.0
12.0
18
tv(TX)
Slave mode, ,
2.5 V < VDD < 3.6 V
13.5
Master mode
Slave mode
Master mode
-
0.5
1
-
9
0
-
-
th(TX)
-
1. Guaranteed by characterization results.
190/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Figure 46. USART timing diagram in Master mode
High
NSS input
tc(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tsu(RX)
tr(SCK)/tf(SCK)
LSB IN
tw(SCKL)
MSB IN
th(RX)
RX
BIT6 IN
INPUT
TX
OUTPUT
BIT1 OUT
th(TX)
LSB OUT
MSB OUT
tv(TX)
MSv65386V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 47. USART timing diagram in Slave mode
NSS
input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(TX)
tw(SCKL)
tv(TX)
th(TX)
tf(SCK)
Last bit OUT
tdis(TX)
TX output
RX input
First bit OUT
th(RX)
Next bits OUT
tsu(RX)
First bit IN
Next bits IN
Last bit IN
MSv65387V1
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 107 for SPI are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 12: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)(2)
Table 107. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode,
2.7 V < VDD < 3.6 V, SPI1, 2, 3
125
Master mode,
1.62 V < VDD < 3.6 V, SPI1, 2,
3
80/66(3)
68.5
Master mode,
1.62 V < VDD < 3.6 V, SPI4, 5,
6
Slave receiver mode,
1.62 V < VDD < 3.6 V, SPI1, 2,
3
fSCK
SPI clock frequency
-
-
MHz
100
Slave receiver mode,
1.62 V < VDD < 3.6 V, SPI4, 5,
6
68.5
Slave mode transmitter/full
duplex, 2.7 V < VDD < 3.6 V
45
Slave mode transmitter/full
duplex, 1.62 V < VDD < 3.6 V
42.5/31(4)
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
2
1
-
-
-
-
-
,
SCK high and low time
Master mode
tSCK/2-1(5) tSCK/2(5) tSCK/2+1(5)
tw(SCKL)
192/227
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Electrical characteristics
(1)(2)
Table 107. SPI characteristics
(continued)
Min
Symbol
Parameter
Conditions
Typ
Max
Unit
tsu(MI)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
Slave mode,
2.5
1
-
-
-
-
Data input setup time
tsu(SI)
th(MI)
3
-
-
Data input hold time
th(SI)
1.5
9
-
-
ta(SO)
tdis(SO)
Data output access time
Data output disable time
13
1
27
5
0
ns
-
-
-
7.5
7.5
1
11
2.7 V < VDD < 3.6 V
tv(SO)
Slave mode,
1.62 V < VDD < 3.6 V
Data output valid time
12/16(4)
1.5/5.5(6)
Master mode,
1.62 V < VDD < 3.6 V
tv(MO)
th(SO)
th(MO)
Slave mode
7
-
-
-
-
Data output hold time
Master mode
0.5
1. Guaranteed by characterization results.
2. The values given in the above table might be degraded when PC3_C/PC2_C I/Os are used (not available on all packages).
3. This value is obtained by using PA9 or PA12 I/O.
4. This value is obtained by using PC2 or PJ11 I/O.
5. tSCK = tker_ck * baud rate prescaler.
6. This value is obtained by using PC3 or PJ10 I/O.
Figure 48. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
DS13313 Rev 2
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STM32H723xE/G
(1)
Figure 49. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
(1)
Figure 50. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
194/227
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STM32H723xE/G
Electrical characteristics
I2S Interface characteristics
2
Unless otherwise specified, the parameters given in Table 108 for I S are derived from tests
performed under the ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 12: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
2
(1)
Table 108. I S dynamic characteristics
Parameter Conditions
Symbol
Min
Max
Unit
-
-
-
50
Master transmitter
I2S main clock output Master receiver
Slave transmitter
50/40(2)
fMCK
-
50/40(2)
MHz
-
41.5/31(3)
Slave receiver
-
50
tv(WS)
th(WS)
WS valid time
Master mode
WS hold time
-
2/6(4)
1
-
-
-
-
-
-
-
tsu(WS)
WS setup time
Slave mode
WS hold time
3
th(WS)
1
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Data input setup time
2.5
1
Slave receiver
Master receiver
Data input hold time
3
ns
Slave receiver
1.5
Slave transmitter (after enable
edge)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
-
12/16(3)
Data output valid time
Data output hold time
Master transmitter (after
enable edge)
-
2/6(5)
Slave transmitter (after enable
edge)
6.5
0.5
-
-
Master transmitter (after
enable edge)
1. Guaranteed by characterization results.
2. This value is obtained when PA9 or PA12 are used.
3. This value is obtained when PC2 is used.
4. This value is obtained when PA11 or PA15 are used.
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STM32H723xE/G
5. This value is obtained when PC3 is used.
2
(1)
Figure 51. I S slave timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 52. I S master timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
196/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
SAI characteristics
Unless otherwise specified, the parameters given in Table 109 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 12: General operating conditions, with the following
configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
IO Compensation cell activated.
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS0
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
(1)
Table 109. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
SAI Main clock output
-
-
-
-
-
-
-
-
50
45
Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V
Master transmitter, 1.62 V ≤ VDD ≤ 3.6 V
Master receiver, 1.62 V ≤ VDD ≤ 3.6 V
Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V
Slave transmitter, 1.62 V ≤ VDD ≤ 3.6 V
Slave receiver, 1.62 V ≤ VDD ≤ 3.6 V
32
32
MHz
fCK
SAI clock frequency(2)
47.5
41.5
50
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Electrical characteristics
STM32H723xE/G
(1)
Table 109. SAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode, 2.7 V ≤ VDD ≤ 3.6 V
-
-
11
tv(FS)
tsu(FS)
th(FS)
FS valid time
Master mode, 1.62 V ≤ VDD ≤ 3.6 V
Slave mode
15.5
FS setup time
FS hold time
2.5
6
-
-
-
-
-
-
-
Master mode
Slave mode
0.5
3
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Data input setup time
Data input hold time
3.5
3.5
0
Master receiver
Slave receiver
ns
Slave transmitter (after enable edge),
-
10.5
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST)
th(SD_B_ST)
tv(SD_A_MT)
th(SD_A_MT)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave transmitter (after enable edge),
-
6.5
-
12
-
1.62 V ≤ VDD ≤ 3.6 V
Slave transmitter (after enable edge)
Master transmitter (after enable edge),
10.5
2.7 V ≤ VDD ≤ 3.6 V
Master transmitter (after enable edge),
-
14.5
-
1.62 V ≤ VDD ≤ 3.6 V
Master transmitter (after enable edge)
6
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
Figure 53. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
198/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Figure 54. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
MDIO characteristics
Unless otherwise specified, the parameters given in Table 110 for the MDIO are derived
from tests performed under the ambient temperature, f frequency and VDD supply
PCLKx
voltage conditions summarized in Table 12: General operating conditions, with the following
configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
I/O Compensation cell activated.
Measurement points are done at CMOS levels: 0.5V
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS0
Table 110. MDIO Slave timing parameters
Symbol
Parameter
Min
Typ
Max
Unit
FMDC
td(MDIO)
tsu(MDIO)
th(MDIO)
Management Data Clock
-
-
10
-
30
18
-
MHz
Management Data Iput/output output valid time
Management Data Iput/output setup time
Management Data Iput/output hold time
8
1
1
ns
-
-
DS13313 Rev 2
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Electrical characteristics
STM32H723xE/G
Figure 55. MDIO Slave timing diagram
tMDC)
td(MDIO)
tsu(MDIO)
th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 111 and Table 112 for SDIO are
derived from tests performed under the ambient temperature, f frequency and VDD
PCLKx
supply voltage summarized in Table 12: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
(1)(2)
Table 111. Dynamics characteristics: SD / MMC characteristics, V =2.7 to 3.6 V
DD
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Clock frequency in data transfer
mode
fPP
-
-
0
-
120 MHz
-
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
8/3
-
tW(CKL)
tW(CKH)
8.5
8.5
9.5
9.5
-
-
fPP =52MHz
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
-
2.5
0.5
1.5
-
-
-
-
-
-
ns
ns
(3)
tIDW
Input valid window (variable window)
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode
tOV
tOH
Output valid time HS
Output hold time HS
-
-
-
5.5
-
6
-
4.5
200/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
(1)(2)
Table 111. Dynamics characteristics: SD / MMC characteristics, V =2.7 to 3.6 V
DD
Symbol
Parameter
Conditions
Min
Typ
Max Unit
CMD, D inputs (referenced to CK) in SD default mode
Input setup time SD
Input hold time SD
-
-
1.5
0.5
-
tISUD
tIHD
ns
-
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time SD
Output hold default time SD
-
-
-
1
-
1
ns
0
-
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
(1)(2)
Table 112. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock frequency in data transfer
mode
fPP
-
-
0
-
85
MHz
-
-
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
8/3
tW(CKL)
tW(CKH)
8.5
8.5
9.5
9.5
-
-
fPP =52 MHz
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
1.5
1.5
-
-
-
-
Input valid window (variable
window)
(3)
tIDW
-
3.5
-
-
CMD, D outputs (referenced to CK) in eMMC mode
tOVD
tOHD
Output valid time HS
Output hold time HS
-
-
-
6
-
6.5
-
5.5
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
Figure 56. SDIO high-speed mode
Figure 57. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
Figure 58. DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
202/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
USB OTG_FS characteristics
Unless otherwise specified, the parameters given in Table 114 for ULPI are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
summarized in Table 12: General operating conditions, with the following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Table 113. USB OTG_FS electrical characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VDD33US
USB transceiver operating voltage
-
3.0(1)
-
3.6
V
B
Embedded USB_DP pull-up value
during idle
RPUI
RPUR
ZDRV
-
-
900
1400
28
1250
2300
36
1600
3200
44
Embedded USB_DP pull-up value
during reception
ꢁ
Driver high
and low
Output driver impedance(2)
1. The USB functionality is ensured down to 2.7 V. However, not all USB electrical characteristics are
degraded in the 2.7 to 3.0 V voltage range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
USB OTG_HS characteristics
Unless otherwise specified, the parameters given in Table 114 for ULPI are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
summarized in Table 12: General operating conditions, with the following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
(1)
Table 114. Dynamics characteristics: USB ULPI
Symbol
Parameter
Condition
Min Typ Max Unit
Control in (ULPI_DIR , ULPI_NXT)
setup time
tSC
-
5.5
0
-
-
-
-
Control in (ULPI_DIR, ULPI_NXT) hold
time
tHC
-
tSD
tHD
Data in setup time
Data in hold time
-
-
2.5
0
-
-
-
-
ns
2.7 V < VDD < 3.6 V,
CL = 20 pF
-
-
6.0
6.0
8.0
12
t
DC/tDD
Control/Datal output delay
1.71 V < VDD < 3.6 V
, CL = 15 pF
1. Guaranteed by characterization results.
Figure 59. ULPI timing diagram
Clock
t
t
HC
SC
Control In
(ULPI_DIR,
ULPI_NXT)
t
t
HD
SD
data In
(8-bit)
t
t
DC
DC
Control out
(ULPI_STP)
t
DD
data out
(8-bit)
ai17361c
204/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Ethernet interface characteristics
Unless otherwise specified, the parameters given in Table 115, Table 116 and Table 117 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
f
frequency and V supply voltage conditions summarized in Table 12: General
rcc_c_ck
DD
operating conditions, with the following configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics:
(1)
Table 115. Dynamics characteristics: Ethernet MAC signals for SMI
Symbol
Parameter
Min
Typ
Max
Unit
tMDC
MDC cycle time( 2.5 MHz)
Write data valid time
Read data setup time
Read data hold time
400
0.5
12.5
0
400
403
Td(MDIO)
tsu(MDIO)
th(MDIO)
1.5
4
-
ns
-
-
-
1. Guaranteed by characterization results.
Figure 60. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
ETH_MDIO(I)
tsu(MDIO)
th(MDIO)
MS31384V1
DS13313 Rev 2
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208
Electrical characteristics
STM32H723xE/G
(1)
Table 116. Dynamics characteristics: Ethernet MAC signals for RMII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(CRS)
tih(CRS)
td(TXEN)
td(TXD)
Receive data setup time
Receive data hold time
2
2
-
-
-
-
-
Carrier sense setup time
Carrier sense hold time
1.5
1.5
8
-
ns
-
-
Transmit enable valid delay time
Transmit data valid delay time
0
8
10.5
9.5
7
1. Guaranteed by characterization results.
Figure 61. Ethernet RMII timing diagram
RMII_REF_CLK
t
t
d(TXEN)
d(TXD)
RMII_TX_EN
RMII_TXD[1:0]
t
t
t
t
su(RXD)
su(CRS)
ih(RXD)
ih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
(1)
Table 117. Dynamics characteristics: Ethernet MAC signals for MII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(DV)
tih(DV)
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
2.0
2.0
1.5
1.5
1.5
0.5
9.0
8.5
-
-
-
-
-
-
-
-
ns
tsu(ER)
tih(ER)
td(TXEN)
td(TXD)
Error setup time
-
-
Error hold time
-
-
Transmit enable valid delay time
Transmit data valid delay time
11
10
19
19
1. Guaranteed by characterization results.
206/227
DS13313 Rev 2
STM32H723xE/G
Electrical characteristics
Figure 62. Ethernet MII timing diagram
MII_RX_CLK
t
t
t
t
t
t
su(RXD)
su(ER)
su(DV)
ih(RXD)
ih(ER)
ih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
t
t
d(TXEN)
d(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 118 and Table 119 for JTAG/SWD
are derived from tests performed under the ambient temperature, f frequency and
rcc_c_ck
V
supply voltage summarized in Table 12: General operating conditions, with the
DD
following configuration:
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS0
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics:
Table 118. Dynamics JTAG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7V <VDD< 3.6 V
-
-
-
-
37
TCK clock frequency
1/tc(TCK)
tisu(TMS)
tih(TMS)
tisu(TDI)
tih(TDI)
1.62 <VDD< 3.6 V
27.5
MHz
TMS input setup time
TMS input hold time
TDI input setup time
TDI input hold time
-
2.5
1
-
-
-
-
-
-
1.5
1
-
-
-
-
-
-
-
-
-
-
2.7V <VDD< 3.6 V
1.62 <VDD< 3.6 V
-
-
8
8
-
13.5
18
-
tov(TDO)
toh(TDO)
TDO output valid time
TDO output hold time
-
7
DS13313 Rev 2
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208
Electrical characteristics
Symbol
STM32H723xE/G
Table 119. Dynamics SWD characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7V <VDD< 3.6 V
-
-
-
-
71
52.5
-
SWCLK clock frequency
MHz
1/tc(SWCLK)
tisu(SWDIO)
tih(SWDIO)
1.62 <VDD< 3.6 V
SWDIO input setup time
SWDIO input hold time
-
2.5
1
-
-
-
-
-
-
-
2.7V <VDD< 3.6 V
1.62 <VDD< 3.6 V
-
8.5
14
tov(SWDIO)
SWDIO output valid time
SWDIO output hold time
-
8.5
-
19
-
-
-
toh(SWDIO)
-
8
Figure 63. JTAG timing diagram
tc(TCK)
TCK
TDI/TMS
TDO
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL)
tw(TCKH)
tov(TDO)
toh(TDO)
MSv40458V1
Figure 64. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL)
tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
208/227
DS13313 Rev 2
STM32H723xE/G
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com. ECOPACK
is an ST trademark.
7.1
LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 65. LQFP100 package outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
75
C
D
D1
D3
L
L1
51
50
76
100
26
PIN 1
IDENTIFICATION
25
1
e
1L_ME_V5
1. Drawing is not to scale.
DS13313 Rev 2
209/227
225
Package information
STM32H723xE/G
Table 120. LQPF100 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
-
0.0630
0.0059
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
1.400
0.220
-
0.0551
0.0087
-
0.0571
0.0106
0.0079
0.6378
0.5591
-
c
D
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
15.800
13.800
-
16.200
14.200
-
0.6220
0.5433
-
0.6378
0.5591
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0.0°
-
7.0°
0.0°
7.0°
ccc
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
210/227
DS13313 Rev 2
STM32H723xE/G
Package information
Figure 66. LQFP100 package recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
DS13313 Rev 2
211/227
225
Package information
STM32H723xE/G
Device marking for LQFP100
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 67. LQFP100 marking example (package top view)
Product identification(1)
STM32H723
VGT6
Revision code
R
Date code
WW
Y
Pin 1
indentifier
MSv53061V3
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
212/227
DS13313 Rev 2
STM32H723xE/G
Package information
7.2
TFBGA100 package information
TFBGA100 is a 100-ball, 8 x 8 mm, 0.8 mm pitch, thin fine-pitch ball grid array package.
Figure 68. TFBGA100 package outline
SEATING
PLANE
C
A1 ball
index
area
A1 ball
identifier
D1
D
e
F
A
B
C
D
E
F
G
H
J
A
K
10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
TOP VIEW
b(100 BALLS)
eee
fff
C
C
A B
A08Q_ME_V1
1. Drawing is not to scale.
DS13313 Rev 2
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225
Package information
STM32H723xE/G
Table 121. TFBGA100 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.100
-
-
-
-
0.0433
-
0.150
-
0.0059
-
0.760
0.400
8.000
7.200
8.000
7.200
0.800
0.400
0.400
-
-
-
0.0299
0.0157
0.3150
0.2835
0.3150
0.2835
0.0315
0.0157
0.0157
-
-
0.350
0.450
8.150
0.0138
0.0177
D
7.850
0.3091
0.3209
D1
E
-
-
-
7.850
8.150
0.3091
0.3209
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
-
G
-
-
ddd
eee
fff
0.100
0.150
0.080
0.0039
0.0059
0.0031
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 69. TFBGA100 package recommended footprint
Dpad
Dsm
A08Q_FP_V1
1. Dimensions are expressed in millimeters.
214/227
DS13313 Rev 2
STM32H723xE/G
Package information
Table 122. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.8
0.400 mm
0.470 mm typ (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
0.400 mm
Stencil thickness
Pad trace width
Between 0.100 mm and 0.125 mm
0.120 mm
Device marking for TFBGA100
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 70. TFBGA100 marking example (package top view)
Product
identification(1)
STM32H723
Revision code
VGH6
R
Date code
Ball
A1identifier
Y WW
MSv53063V2
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS13313 Rev 2
215/227
225
Package information
STM32H723xE/G
7.3
LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 71. LQFP144 package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
108
73
109
72
37
144
1
36
PIN 1
IDENTIFICATION
e
1A_ME_V4
1. Drawing is not to scale.
216/227
DS13313 Rev 2
STM32H723xE/G
Package information
Table 123. LQFP144 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS13313 Rev 2
217/227
225
Package information
STM32H723xE/G
Figure 72. LQFP144 package recommended footprint
1.35
108
73
109
72
0.35
0.5
19.9
17.85
22.6
144
37
1
36
19.9
22.6
ai14905e
1. Dimensions are expressed in millimeters.
218/227
DS13313 Rev 2
STM32H723xE/G
Package information
Device marking for LQFP144
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 73. LQFP144 marking example (package top view)
Product
ES32H723ZGT6
identification(1)
Revision code
R
Date code
Y WW
Pin 1 identifier
MSv53065V2
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS13313 Rev 2
219/227
225
Package information
STM32H723xE/G
7.4
UFBGA144 package information
UFBGA144 is a 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 74. UFBGA144 package outline
Z Seating plane
ddd Z
A4
A2
A
A3
A1
A
E1
X
A1 ball
A1 ball
E
identifier index area
e
F
F
D1
D
e
Y
M
12
1
Øb (144 balls)
Øeee M Z Y X
Øfff M Z
BOTTOM VIEW
TOP VIEW
A0AS_ME_V2
1. Drawing is not to scale.
Table 124. UFBGA144 package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.280
7.000
5.500
7.000
5.500
0.500
0.750
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
0.0236
0.0043
0.0197
-
0.270
0.230
6.950
5.450
6.950
5.450
-
0.370
0.320
7.050
5.550
7.050
5.550
-
0.0106
0.0091
0.2736
0.2146
0.2736
0.2146
-
0.0146
0.0126
0.2776
0.2185
0.2776
0.2185
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
220/227
DS13313 Rev 2
STM32H723xE/G
Package information
Table 124. UFBGA144 package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.100
0.150
0.050
-
-
-
-
-
-
0.0039
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 75. UFBGA144 package recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 125. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.50 mm
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.280 mm
Between 0.100 mm and 0.125 mm
0.120 mm
DS13313 Rev 2
221/227
225
Package information
STM32H723xE/G
Device marking for UFBGA144
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 76. UFBGA144 marking example (package top view
STM32H
Product identification(1)
723ZGI6
Revision code
Date code
Y
WW
R
Ball A1
identifier
MSv53067V2
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
222/227
DS13313 Rev 2
STM32H723xE/G
Package information
7.5
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 126. Thermal characteristics
Parameter
Symbol
Definition
Value
Unit
Thermal resistance junction-ambient
43.8
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
43.2
44.8
TBD
19.8
24.8
24.4
TBD
7.3
TFBGA100 - 8 x 8 mm /0.8 mm pitch
Thermal resistance
junction-ambient
ΘJA
ΘJB
ΘJC
°C/W
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
UFBGA144 - 7 x 7 mm /0.5 mm pitch
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
TFBGA100 - 8 x 8 mm /0.8 mm pitch
Thermal resistance
junction-board
°C/W
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
UFBGA144 - 7 x 7 mm /0.5 mm pitch
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
13.2
7.4
TFBGA100 - 8 x 8 mm /0.8 mm pitch
Thermal resistance
junction-case
°C/W
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
TBD
UFBGA144 - 7 x 7 mm /0.5 mm pitch
DS13313 Rev 2
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225
Package information
STM32H723xE/G
7.5.1
Reference documents
•
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
•
For information on thermal management, refer to application note “Thermal
management guidelines for STM32 applications” (AN5036) available from www.st.com.
224/227
DS13313 Rev 2
STM32H723xE/G
Ordering information
8
Ordering information
Example:
STM32 H
723
V
G
T
6
TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
723 = STM32H723
Pin count
V = 100 pins
Z = 144 pins
Flash memory size
E = 512 Kbytes
G = 1024 Kbytes
Package
T = LQFP ECOPACK2
I = UFBGA pitch 0.5 mm ECOPACK2
H = TFBGA ECOPACK2
Temperature range
6 = Industrial temperature range –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
DS13313 Rev 2
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225
Revision history
STM32H723xE/G
9
Revision history
Table 127. Document revision history
Date
Revision
Changes
10-Jul-2020
1
Initial release.
Renamed Section 3.30 into True random number
generator (RNG).
Replaced VDDIOx by VDD in Section 6: Electrical
characteristics.
Updated IIO in Table 10: Current characteristics.
Updated Table 24: Typical current consumption in
Autonomous mode, Table 27: Typical current
consumption in Standby mode and Table 28: Typical and
maximum current consumption in VBAT mode.
03-Sep-2020
2
Added Section 6.3.15: I/O current injection
characteristics.
Removed reference to PI8 in Table 51: Output voltage
characteristics for all I/Os except PC13, PC14 and PC15
and Table 52: Output voltage characteristics for PC13,
PC14 and PC15.
Added Section 6.3.15: I/O current injection
characteristics.
Added Section : Analog switch between ports Pxy_C
and Pxy.
226/227
DS13313 Rev 2
STM32H723xE/G
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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DS13313 Rev 2
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