STM32H747BIY6TR [STMICROELECTRONICS]
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI;型号: | STM32H747BIY6TR |
厂家: | ST |
描述: | Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI |
文件: | 总252页 (文件大小:3452K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STM32H747xI/G
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to
2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
Datasheet - production data
Features
FBGA
Dual core
®
®
• 32-bit Arm Cortex -M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
LQFP176
(24x24 mm)
LQFP208
UFBGA169
(7 × 7 mm)
TFBGA240+25
(14x14 mm)
WLCSP156
(4.96x4.64 mm)
(28x28 mm)
Reset and power management
®
®
• 3 separate power domains which can be
• 32-bit Arm 32-bit Cortex -M4 core with FPU,
Adaptive real-time accelerator (ART
independently clock-gated or switched off:
Accelerator™) for internal Flash memory and
external memories, frequency up to 240 MHz,
MPU, 300 DMIPS/1.25 DMIPS /MHz
– D1: high-performance capabilities
– D2: communication peripherals and timers
– D3: reset/clock control/power management
(Dhrystone 2.1), and DSP instructions
• 1.62 to 3.6 V application supply and I/Os
• POR, PDR, PVD and BOR
Memories
• Up to 2 Mbytes of Flash memory with read-
• Dedicated USB power embedding a 3.3 V
while-write support
internal regulator to supply the internal PHYs
• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
• Embedded regulator (LDO) to supply the digital
circuitry
• High power-efficiency SMPS step-down
converter regulator to directly supply V
and/or external circuitry
CORE
• Dual mode Quad-SPI memory interface
• Voltage scaling in Run and Stop mode (6
running up to 133 MHz
configurable ranges)
• Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
• Backup regulator (~0.9 V)
• Voltage reference for analog peripheral/V
REF+
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 125 MHz in
Synchronous mode
• 1.2 to 3.6 V V
supply
BAT
• Low-power modes: Sleep, Stop, Standby and
supporting battery charging
• CRC calculation unit
V
BAT
Security
Low-power consumption
• ROP, PC-ROP, active tamper
• V
battery operating mode with charging
capability
BAT
General-purpose input/outputs
• CPU and domain power state monitoring pins
• Up to 168 I/O ports with interrupt capability
• 2.95 µAin Standby mode (Backup SRAM OFF,
RTC/LSE ON)
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STM32H747xI/G
• 2× operational amplifiers (7.3 MHz bandwidth)
Clock management
• 1× digital filters for sigma delta modulator
• Internal oscillators: 64 MHz HSI, 48 MHz
(DFSDM) with 8 channels/4 filters
HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-48 MHz HSE,
Graphics
32.768 kHz LSE
• LCD-TFT controller up to XGA resolution
• 3× PLLs (1 for the system clock, 2 for kernel
• MIPI DSI host including an MIPI D-PHY to
clocks) with Fractional mode
interface with low-pin count large displays
Interconnect matrix
• Chrom-ART graphical hardware Accelerator™
(DMA2D) to reduce CPU load
•
•
3 bus matrices (1 AXI and 2 AHB)
Bridges (5× AHB2-APB, 2× AXI2-AHB)
• Hardware JPEG Codec
4 DMA controllers to unload the CPU
Up to 22 timers and watchdogs
• 1× high-speed master direct memory access
• 1× high-resolution timer (2.1 ns max
controller (MDMA) with linked list support
resolution)
• 2× dual-port DMAs with FIFO
• 2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
• 1× basic DMA with request router capabilities
Up to 35 communication peripherals
• 2× 16-bit advanced motor control timers (up to
240 MHz)
• 4× I2Cs FM+ interfaces (SMBus/PMBus)
• 10× 16-bit general-purpose timers (up to
• 4× USARTs/4x UARTs (ISO7816 interface,
240 MHz)
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
• 5× 16-bit low-power timers (up to 240 MHz)
• 4× watchdogs (independent and window)
• 2× SysTick timers
• 6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
• 4x SAIs (serial audio interface)
• SPDIFRX interface
• RTC with sub-second accuracy and hardware
calendar
• SWPMI single-wire protocol master I/F
• MDIO Slave interface
Debug mode
• SWD & JTAG interfaces
• 4-Kbyte Embedded Trace Buffer
• 2× SD/SDIO/MMC interfaces (up to 125 MHz)
• 2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
True random number generators (3
oscillators each)
• 2× USB OTG interfaces (1FS, 1HS/FS) crystal-
less solution with LPM and BCD
96-bit unique ID
• Ethernet MAC interface with DMA controller
• HDMI-CEC
All packages are ECOPACK®2 compliant
Table 1. Device summary
• 8- to 14-bit camera interface (up to 80 MHz)
11 analog peripherals
Reference
Part number
• 3× ADCs with 16-bit max. resolution (up to 36
STM32H747 STM32H747AI, STM32H747BI,
xI
STM32H747II, STM32H747XI, STM32H747ZI
channels, up to 3.6 MSPS)
STM32H747 STM32H747AG, STM32H747BG,
• 1× temperature sensor
xG
STM32H747IG, STM32H747XG
• 2× 12-bit D/A converters (1 MHz)
• 2× ultra-low-power comparators
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Dual Arm® Cortex® cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
®
®
3.1.1
3.1.2
Arm Cortex -M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
®
®
Arm Cortex -M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
3.3
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.1
3.3.2
3.3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ART™ accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.1
3.5.2
3.5.3
3.5.4
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage regulator (SMPS step-down converter and LDO) . . . . . . . . . . . 18
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6
3.7
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.1
3.7.2
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8
3.9
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 24
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 24
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
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3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 28
3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.26 DSI Host (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.27 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.28 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.29 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.29.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.29.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.29.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.29.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 36
3.29.6 Independent watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.29.7 Window watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.29.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.30 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 37
3.31 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.32 Universal synchronous/asynchronous receiver transmitter (USART) . . . 38
3.33 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 39
3.34 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 40
3.35 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.36 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.37 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 41
3.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 42
3.39 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 42
3.40 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 42
3.41 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 43
3.42 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 43
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3.43 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.44 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4
5
6
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 105
Embedded reset and power control block characteristics . . . . . . . . . . 106
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 128
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.12 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.13 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.14 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.15 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.16 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 144
6.3.17 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.18 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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6.3.19 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.20 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.21 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.3.22 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3.23 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.24 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.3.25 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 190
6.3.26 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.3.27 Temperature and V
monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
BAT
6.3.28 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3.29 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.30 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.3.31 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 196
6.3.32 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 199
6.3.33 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 200
6.3.34 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.35 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
7.1
7.2
7.3
7.4
7.5
7.6
WLCSP156 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
7.6.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
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List of tables
List of tables
Table 1.
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32H747xI/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STM32H747xI/G pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Port I alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 103
VCAP operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Characteristics of SMPS step-down converter external components. . . . . . . . . . . . . . . . 104
SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 105
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 105
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
(ART accelerator ON), LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4,
ART accelerator ON, SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache ON,
ART accelerator ON, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache OFF,
Table 32.
Table 33.
Table 34.
ART accelerator OFF, LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, LDO regulator ON . . . . . . . . . . . . . . . 111
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, SMPS regulator. . . . . . . . . . . . . . . . . 112
Typical and maximum current consumption in Run mode, code with data processing
Table 35.
Table 36.
Table 37.
DS12930 Rev 1
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4
List of tables
STM32H747xI/G
running from Flash memory, only Arm Cortex-M7 running, cache ON,
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache OFF,
Table 38.
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Typical and maximum current consumption batch acquisition mode,
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,
Table 39.
Table 40.
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Typical and maximum current consumption in Run mode, code with data processing
running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,
Table 41.
SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 115
Typical and maximum current consumption in Stop, SMPS regulator . . . . . . . . . . . . . . . 116
Typical and maximum current consumption in Sleep mode, LDO regulator . . . . . . . . . . 117
Typical and maximum current consumption in Sleep mode, SMPS regulator . . . . . . . . . 117
Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 118
Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
PLL characteristics (wide VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MIPI D-PHY AC characteristics LP mode and HS/LP
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 141
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 148
Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 149
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 155
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 155
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 157
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
2/242
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List of tables
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 157
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 159
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 160
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 166
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 171
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
QUADSPI characteristics in DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Delay Block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 100. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 101. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 103. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 104. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 105. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 106. V
Table 107. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
BAT
BAT
Table 108. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 109. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 110. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 111. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 112. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 113. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 114. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 115. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 116. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 117. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 118. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 119. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
2
Table 120. I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 121. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 122. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 123. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 214
Table 124. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V. . . . . . . . . . . . . . . 215
Table 125. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 126. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 127. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 128. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 129. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 130. Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 131. WLCSP156 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
DS12930 Rev 1
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List of tables
STM32H747xI/G
Table 132. WLCSP156 bump recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 133. UFBGA169 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 134. LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 135. LQFP208 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 136. TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 137. TFBGA240+25 recommended PCB design rules (0.8 mm pitch). . . . . . . . . . . . . . . . . . . 237
Table 138. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 139. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
4/242
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32H747xI/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TFBGA240+25 ball assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ART™ accelerator schematic and environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32H747xI/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
WLCSP156 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 10. TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 15. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
EXT
Figure 16. External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C. . . . . . . . . . 119
Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . 119
Figure 19. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = 30 °C. . . . . 120
Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 121
Figure 21. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 22. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 23. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 24. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 25. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 26. MIPI D-PHY HS/LP data lane transition timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 27. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 29. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 154
Figure 30. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 156
Figure 31. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 32. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 33. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 34. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 35. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 36. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 37. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 38. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 170
Figure 39. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 171
Figure 40. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 41. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 42. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 43. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 44. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 45. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 46. Power supply and reference decoupling (V
Figure 47. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 185
). . . . . . . . . . . . . . . . 185
REF+
DDA
connected to V
REF+
DDA
Figure 48. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
DS12930 Rev 1
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2
List of figures
STM32H747xI/G
Figure 49. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 50. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 51. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 52. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 53. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 54. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 55. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
(1)
Figure 56. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
(1)
Figure 57. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
2
(1)
Figure 58. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
2
(1)
Figure 59. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 60. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 61. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 62. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 63. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 64. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 65. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 66. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 67. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 68. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 69. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 70. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 71. SWD timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 72. WLCSP156 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 73. WLCSP156 bump recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 74. WLCSP156 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 75. UFBGA169 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 76. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 77. LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 78. LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 79. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 80. LQFP208 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 81. LQFP208 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 82. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 83. TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 84. TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 85. TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
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STM32H747xI/G
Introduction
1
Introduction
This document provides information on STM32H747xI/G microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering information.
This document should be read in conjunction with the STM32H747xI/G reference manual
(RM0399), available from the STMicroelectronics website www.st.com.
®(a)
®
®
®
For information on the Arm
Cortex -M7 core and Arm Cortex -M4 core, please refer to
®
the Cortex -M7 Technical Reference Manual, available from the http://www.arm.com
website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12930 Rev 1
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46
Description
STM32H747xI/G
2
Description
®
®
STM32H747xI/G devices are based on the high-performance Arm Cortex -M7 and
®
®
Cortex -M4 32-bit RISC cores. The Cortex -M7 core operates at up to 480 MHz and the
Cortex -M4 core at up to 240 MHz. Both cores feature a floating point unit (FPU) which
supports Arm single- and double-precision (Cortex -M7 core) operations and conversions
(IEEE 754 compliant), including a full set of DSP instructions and a memory protection unit
(MPU) to enhance application security.
®
®
®
STM32H747xI/G devices incorporate high-speed embedded memories with a dual-bank
Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM,
up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive
range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit
multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external
memory access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG). The devices support
four digital filters for external sigma-delta modulators (DFSDM). They also feature standard
and advanced communication interfaces.
•
Standard peripherals
2
–
–
–
Four I Cs
Four USARTs, four UARTs and one LPUART
2
2
Six SPIs, three I Ss in Half-duplex mode. To achieve audio class accuracy, the I S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
–
–
–
–
–
–
Four SAI serial audio interfaces
One SPDIFRX interface
One SWPMI (Single Wire Protocol Master Interface)
Management Data Input/Output (MDIO) slaves
Two SDMMC interfaces
A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
–
–
–
–
One FDCAN plus one TT-FDCAN interface
An Ethernet interface
™
Chrom-ART Accelerator
HDMI-CEC
•
Advanced peripherals including
–
–
–
–
–
–
A flexible memory control (FMC) interface
A Quad-SPI Flash memory interface
A camera interface for CMOS sensors
An LCD-TFT display controller
A JPEG hardware compressor/decompressor
A DSI Host interface.
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DS12930 Rev 1
STM32H747xI/G
Description
Refer to Table 1: STM32H747xI/G features and peripheral counts for the list of peripherals
available on each part number.
STM32H747xI/G devices operate in the –40 to +85 °C temperature range from a 1.62 to
3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
V
. Otherwise the supply voltage must stay above 1.71 V with the embedded power
SS
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages to
allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H747xI/G devices are offered in 5 packages ranging from 156 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H747xI/G microcontrollers suitable for a wide range of
applications:
•
•
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile applications, Internet of Things
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
DS12930 Rev 1
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46
Description
STM32H747xI/G
Table 1. STM32H747xI/G features and peripheral counts
Peripherals
Flash memory in Kbytes
SRAM
2 x 512 Kbytes
2 x 1 Mbyte
mapped onto
512
AXI bus
SRAM1
(D2 domain)
128
128
32
SRAM in Kbytes
SRAM2
(D2 domain)
SRAM3
(D2 domain)
SRAM4
(D3 domain)
64
ITCM RAM
(instruction)
64
TCM RAM in
Kbytes
DTCM RAM
(data)
128
Backup SRAM (Kbytes)
4
FMC
General-purpose input/outputs
Quad-SPI
Yes
99
112
119
148
168
112
119
148
168
Yes
Yes
Ethernet
High-
resolution
1
10
2
General-
purpose
Timers
Advanced-
control (PWM)
Basic
2
5
Low-power
Wakeup pins
Tamper pins
4
2
4
2
6
3
6
3
Random number generator
Yes
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DS12930 Rev 1
STM32H747xI/G
Description
Table 1. STM32H747xI/G features and peripheral counts (continued)
Peripherals
SPI / I2S
6/3(1)
4
I2C
USART/UART
/LPUART
4/4
/1
SAI
4
4 inputs
Yes
SPDIFRX
SWPMI
MDIO
Communication
interfaces
Yes
SDMMC
2
FDCAN/TT-
FDCAN
1/1
USB OTG_FS
USB OTG_HS
Yes
Yes
Yes
Yes
Yes
Yes
Ethernet and camera interface
LCD-TFT
MIPI-DSI Host
JPEG Codec
Chrom-ART Accelerator™
(DMA2D)
Yes
GPIOs
Up to 168
3
16-bit ADCs
Number of Direct channels
Number of Fast channels
Number of Slow channels
2
9
4
9
2
7
2
9
4
9
2
9
21
2
9
21
17
23
14
17
23
12-bit DAC
Yes
2
Number of channels
Comparators
Operational amplifiers
DFSDM
2
2
Yes
Maximum CPU frequency
480 MHz
DS12930 Rev 1
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46
Description
STM32H747xI/G
Table 1. STM32H747xI/G features and peripheral counts (continued)
Peripherals
Operating voltage
1.62 to 3.6 V(2)
Ambient temperatures: –40 up to +85 °C(3)
Operating temperatures
Package
Junction temperature: –40 to + 125 °C
UFBGA LQFP LQFP TFBGA WLCSP UFBG LQFP LQFP TFBGA
169
176
208
240+25
156
A169 176
208
240+25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
3. The product junction temperature must be kept within the –40 to +125 °C range.
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STM32H747xI/G
Description
Figure 1. STM32H747xI/G block diagram
DP, DM, STP,
SDMMC_
MII / RMII
MDIO
as AF
NXT,ULPI:CK DP, DM, ID,
To APB1-2
peripherals
D[7:0],
, D[7:0], DIR,
ID, VBUS
VBUS
CMD, CK as AF
AHB1
(200MHz)
PHY
PHY
ETHER
I-
TCM
4KB
D-
TCM
64KB
D-
OTG_HS OTG_FS
DMA1 DMA2
8 Stream 8 Stream
SDMMC2
FIFO
ARM
Cortex
M4
D- S-
Bus Bus Bus
MAC
DMA
TCM
64KB
DMA/
FIFO
DMA/
FIFO
I-
FIFOs
FIFOs
AXI/AHB12 (200MHz)
AHBP
JTDO/SWD, JTDO
JTRST, JTDI,
JTCK/SWCLK
Up to 1 MB
FLASH
Up to 1 MB
FLASH
Arm
Cortex
M7
JTAG/SW
ETM
32-bit AHB BUS-MATRIX
AXIM
TRACECK
TRACED[3:0]
DMA
Mux1
I-Cache
16KB
D-Cache
16KB
SRAM1 SRAM2 SRAM3
128 KB 128 KB 32 KB
512 KB AXI
SRAM
AHBS
RNG
ADC1
FMC
16 Streams
FIFO
Up to 20 analog inputs
common to ADC1 & 2
MDMA
ADC2
FMC_signals
Quad-SPI
CLK, CS,D[7:0]
CHROM-ART
(DMA2D)
AHB/APB
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE,
LCD_CLK
FIFO
TIM2
TIM3
TIM4
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels
32b
16b
16b
LCD-TFT FIFO
WWDG1 JPEG
TIM6
D
S
I
DSI_D0_P, DSI_D0_N
DSI_D1_P, DSI_D1_N
DSI_CK_P, DSI_CK_N
16b
16b
AXI/AHB34 (200MHz)
TIM7
AHB/APB
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
SWPMI
TIM5
TIM12
TIM13
TIM14
32b
16b
16b
16b
FIFO
SDMMC1
2 channels as AF
1 channel as AF
ART
(instruction cache)
1 channel as AF
AHB ART (200MHz)
smcard
RX, TX, SCK, CTS,
RTS as AF
AHB2 (200MHz)
USART2
Delay block
DCMI
irDA
smcard
RX, TX, SCK
CTS, RTS as AF
USART3
HSYNC, VSYNC, PUIXCLK, D[13:0]
irDA
AHB/APB
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
UART4
UART5
RX, TX as AF
RX, TX as AF
HRTIM1
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
DFSDM1
UART7
RX, TX as AF
RX, TX as AF
SAI3
SAI2
SAI1
SD, SCK, FS, MCLK as AF
UART8
MOSI, MISO, SCK, NSS/SDO,
SDI, CK, WS, MCK, as AF
SPI2/I2S2
SPI3/I2S3
SD, SCK, FS, MCLK as AF
MOSI, MISO, SCK, NSS/SDO,
SDI, CK, WS, MCK, as AF
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
SCL, SDA, SMBAL as AF
I2C1/SMBUS
I2C2/SMBUS
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS as AF
DMA
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
SCL, SDA, SMBAL as AF
Mux2
AHB4
BDMA
DAP
I2C3/SMBUS
MDIOS
SCL, SDA, SMBAL as AF
MDC, MDIO
TX, RX
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
IWDG1
IWDG2
RAM
I/F
MOSI, MISO, SCK, NSS as AF
32-bit AHB BUS-MATRIX
64 KB SRAM
FDCAN1
FDCAN2
MOSI, MISO, SCK, NSS/
SDO, SDI, CK, WS, MCK, as AF
TX, RX
SPI/I2S1
smcard
CRS
RX, TX, SCK, CTS, RTS as AF
USART6
irDA
smcard
4 KB BKP
SPDIFRX1
HDMI-CEC
DAC1&2
IN[1:4] as AF
RX, TX, SCK, CTS, RTS as AF
USART1
irDA
RAM
CEC as AF
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR, BKIN as
AF
TIM1/PWM
TIM8/PWM
16b
16b
DAC1_OUT, DAC2_OUT as AF
HSEM
CRC
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
LPTIM1
WWDG2
16b
OPAMPx_VINM
Up to 17 analog inputs
common to ADC1 and 2
OPAMP1&2
@VDD33
OPAMPx_VINP
ADC3
OPAMPx_VOUT as AF
VDD = 1.62 to 3.6V
VDDUSB33 = 3.0 to 3.6V
VDDDSI = 1.8 to 3.6V
VSS
Tem. sensor
VDDREF_ADC
PA..J[15:0]
VDD12
@VSW
RCC
Reset &
control
Voltage regulator
3.3 to 1.2V
GPIO PORTA.. J
GPIO PORTK
VCAP
SMPS step-down
converter
PK[7:0]
VDDMMC33 = 1.8 to 3.6 V
VDDSMPS, VSSSMPS
VLXSMPS, VFBSMPS
AHB/APB
SD, SCK, FS, MCLK,
PDM_DI/CK[4:1] as AF
SAI4
OSC32_IN
OSC32_OUT
XTAL 32 kHz
COMPx_INP, COMPx_INM,
COMP1&2
LPTIM5
COMPx_OUT as AF
RTC
RTC_TS
@VDD
Backup registers
RTC_TAMP[1:3]
RTC_OUT
LPTIM5_OUT as AF
LPTIM4_OUT as AF
VREF
AWU
CSI
4 MHz CSI
RTC_REFIN
LPTIM4
LPTIM3
SYSCFG
48 MHz HSI48 RC
RC48
LPTIM3_OUT as AF
SCL, SDA, SMBAL as AF
VBAT = 1.2 to 3.6 V
64 MHz HSI RC
32 KHz LSI RC
HSI
LSI
EXTI WKUP
@VDD
I2C4
SPI6
OSC_IN
OSC_OUT
XTAL OSC
4- 48 MHz
MISO, MOSI, SCK, NSS as AF
PLL1+PLL2+PLL3
IWDG1
IWDG2
RX, TX, CK, CTS, RTS as AF
LPTIM2_OUT as AF
LPUART1
LPTIM2
@VDD
SUPPLY SUPERVISION
POR/PDR/BOR
POR
reset
Int
VDDA, VSSA
NRESET
WKUP[5:0]
PVD
MSv43739V12
DS12930 Rev 1
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46
Description
STM32H747xI/G
Compatibility throughout the family
STM32H747xI/G devices are not pin-to-pin compatible with STM32H7x3 devices (single
core line):
•
The TFBGA240+25 ballout is compatible with STM32H7x3 devices, except for a few
I/O balls as shown in Figure 2.
•
LQFP208 and LQFP176 pinouts, as well as UFBGA176+25 ballout are not compatible
with STM32H7x3 devices.
Figure 2. TFBGA240+25 ball assignment differences
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PA15
15
16
17
VCAP
A
B
C
D
E
F
VSS
PI6
PI5
PI4
PB5
VDDLDO
PK5
PG10
PG9
PD5
PD4
PC10
PI1
PI0
VSS
VBAT
VSS
PI7
PE2
PE3
PC13
PI10
PF1
PI14
VSS
PF7
PF10
PC2
PA2
PH4
PA6
PA5
PA4
PE1
PE0
PB9
PI8
PB6
PB7
PB8
PE6
VDD
VDD
VDD
PF4
VDD
VDD
VDD
PA0
PI15
PA7
PB1
PB0
VSS
PB3
PB4
PK6
PK7
PK4
PK3
PG11
PG12
PG13
VDD
PJ15
VSS
PD6
PD7
PJ12
VDD
PD3
PC12
PD2
PC11
VSS
PD0
PC8
PC7
VDD
VDD
VDD
VDD
VDD
VDD
PJ8
PA14
PI3
PI2
PA13
PA9
PA8
PG8
PG6
PG3
PK1
PH15
VSS
PH13
PA12
PG7
VSS
PG2
PH14
VDDLDO
VCAP
PC14-
OSC32_
IN
PC15-
OSC32_
OUT
PE5
PE4
PG15
VDD
PG14
BOOT0
PJ14
PJ13
PA10
PC9
PC6
PG5
PG4
PK0
PDR
_ON
PI9
PD1
PA11
VDD33
USB
PI11
PF0
PF3
PF5
PF8
PF9
PC3
PA1
PH5
VSS
PC4
PC5
VDD5
USB
G
H
J
PF2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PI12
PI13
PK2
PH1-
OSC_
OUT
PH0-
OSC_
IN
VSS
DSI
VSSDSI
K
L
NRST
VDDA
VREF+
VREF-
VSSA
PF6
PC0
PC1
PH2
PH3
PJ11
PJ10
PJ9
M
N
P
R
T
PJ0
PJ1
PB2
PJ2
PJ3
VDD
PF13
PF12
PF11
PJ4
VDD
PF14
VSS
PG0
PG1
PE10
PE9
VDD
PE11
PE12
PE13
PE14
VDD
PB10
PE15
PH6
VDD
PB11
PJ7
PJ6
VSS
PD14
PD12
PD10
PD8
PH10
PH9
PH8
PH7
PH11
PH12
PB12
PB13
PD15
PD11
PB15
PB14
PC2_C PC3_C
PF15
PE8
PJ5
PD13
PD9
PA0_C
VSS
PA1_C
PA3
VSS
VDDLDO
U
PE7
VCAP
VSS
STM32H7x7
STM32H7x3
VLX
SMPS
VDD
PI9
PI9
VSSDSI DSI_D1P DSI_D1N
NC
NC
VSS
NC
NC
VSS
SMPS
VFB
VSSDSI DSI_CKP DSI_CKN
NC
NC
VSS
VSS
NC
NC
NC
NC
SMPS
PF2
VSSDSI DSI_D0P DSI_D0N
PF2
SMPS
VDDCAP
PJ6
VSS
PJ6
VSS
PD14
NC
DSI
PD15
PD14
PD15
VDDDSI
VDD
MSv48802V2
1. The balls highlighted in gray correspond to different signals on STM32H747xI/G and STM32H7x3 devices.
10/242
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Functional overview
3
Functional overview
®
®
3.1
Dual Arm Cortex cores
®
®
The dual-core MIPI-DSI STM32H747xI/G devices embed two Arm cores, a Cortex -M7
®
®
and a Cortex -M4. The Cortex -M4 offers optimal performance for real-time applications
while the Cortex -M7 core can execute high-performance tasks in parallel.
®
The two cores belong to separate power domains. This allows designing gradual high-
power efficiency solutions in combination with the low-power modes already available on all
STM32 microcontrollers.
®
®
3.1.1
Arm Cortex -M7 with FPU
®
®
The Arm Cortex -M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
®
The Cortex -M7 processor is a highly efficient high-performance featuring:
•
•
•
•
•
•
Six-stage dual-issue pipeline
Dynamic branch prediction
Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
64-bit AXI interface
64-bit ITCM interface
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
•
AXI Bus interface to optimize Burst transfers
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H747xI/G family.
®
®
Note:
Cortex -M7 with FPU core is binary compatible with the Cortex -M4 core.
DS12930 Rev 1
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46
Functional overview
®
STM32H747xI/G
®
3.1.2
Arm Cortex -M4 with FPU
®
®
The Arm Cortex -M4 processor is a high-performance embedded processor which
supports DSP instructions. It was developed to provide an optimized power consumption
MCU, while delivering outstanding computational performance and low interrupt latency.
®
®
The Arm Cortex -M4 processor is a highly efficient MCU featuring:
•
•
•
•
•
3-stage pipeline with branch prediction
Harvard architecture
32-bit System (S-BUS) interface
32-bit I-BUS interface
32-bit D-BUS interface
®
®
The Arm Cortex -M4 processor also features a dedicated hardware adaptive real-time
™
accelerator (ART Accelerator ). This is an instruction cache memory composed of sixty-
four 256-bit lines, a 256-bit cache buffer connected to the 64-bit AXI interface and a 32-bit
interface for non-cacheable accesses.
3.2
Memory protection unit (MPU)
The devices feature two memory protection units. Each MPU manages the CPU access
rights and the attributes of the system resources. It has to be programmed and enabled
before use. Its main purposes are to prevent an untrusted user program to accidentally
corrupt data used by the OS and/or by a privileged task, but also to protect data processes
or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
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Functional overview
3.3
Memories
3.3.1
Embedded Flash memory
The STM32H747xI/G devices embed up to 2 Mbytes of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•
•
One Flash word (8 words, 32 bytes or 256 bits)
10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
•
A user Flash memory block of 512 Kbytes (STM32H7xxxG) or 1-Mbyte (STM32H7xxxI)
containing eight user sectors of 128 Kbytes (4 K Flash memory words)
•
128 Kbytes of System Flash memory from which the device can boot
2 Kbytes (64 Flash words) of user option bytes for user configuration
•
3.3.2
Embedded SRAM
All devices feature around 1 Mbyte of RAM with hardware ECC. The RAM is divided as
follows:
•
•
•
•
•
•
512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
SRAM1 mapped on D2 domain: 128 Kbytes
SRAM2 mapped on D2 domain: 128 Kbytes
SRAM3 mapped on D2 domain: 32 Kbytes
SRAM4 mapped on D3 domain: 64 Kbytes
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or V
mode.
BAT
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
®
®
from the Arm Cortex -M7 CPU or the MDMA (even in Sleep mode) through a specific
®
AHB slave of the Cortex -M7(AHBS):
–
–
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
®
real-times routines by the Cortex -M7.
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
®
load/store operations) thanks to the Cortex -M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
DS12930 Rev 1
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46
Functional overview
STM32H747xI/G
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•
•
7 ECC bits are added per 32-bit word.
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
™
3.3.3
ART accelerator
™
The ART (adaptive real-time) accelerator block speeds up instruction fetch accesses of
®
the Cortex -M4 core from D1-domain internal memories (Flash memory bank 1, Flash
memory bank 2, AXI SRAM) and from D1-domain external memories attached via Quad-
SPI controller and Flexible memory controller (FMC).
™
The ART accelerator is a 256-bit cache line using 64-bit WRAP4 accesses from the 64-bit
AXI D1 domain. The acceleration is achieved by loading selected code into an embedded
®
cache and making it instantly available to Cortex -M4 core, thus avoiding latency due to
memory wait states.
Figure 3. shows the block schematic and the environment of the ART accelerator.
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Functional overview
™
Figure 3. ART accelerator schematic and environment
AHB from D2 domain
D1 domain
ART accelerator
Non-cacheable
access path
Cacheable
access path
AHB switch
control
Detect of
instruction
fetch
write to cacheable page
Cache
Cache buffer
1 x 256-bit
cache cache
hit miss
non-
Cache
cacheable
access
manager
Cache memory
64 x 256-bit
cache
refill
AHB access
AXI access
Flash bank 1
Flash bank 2
AXI SRAM
QSPI
Legend
Control
32-bit bus
64-bit bus
Bus multiplexer
Master interface
Slave interface
FMC
AXI AHB
64-bit AXI bus matrix
MSv39757V2
3.4
Boot modes
By default, the boot codes are executed simultaneously by both cores. However, by
programming the appropriate Flash user option byte, it is possible to boot from one core
while clock-gating the other core.
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
•
All Flash address space
Flash memory and SRAMs (except for ITCM /DTCM RAMs which cannot be accessed
®
by the Cortex -M4 core)
DS12930 Rev 1
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46
Functional overview
STM32H747xI/G
The bootloader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5
Power supply management
3.5.1
Power supply scheme
STM32H747xI/G power supply voltages are the following:
•
V
pins.
= 1.62 to 3.6 V: external power supply for I/Os, provided externally through V
DD
DD
•
•
V
= 1.62 to 3.6 V: supply voltage for the internal regulator supplying V
DDLDO
CORE
V
= 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
DDA
OPAMP.
•
V
V
:
DD33USB and DD50USB
V
can be supplied through the USB cable to generate the V
via the
DD33USB
DD50USB
USB internal regulator. This allows supporting a V supply different from 3.3 V.
DD
The USB regulator can be bypassed to supply directly V
if V = 3.3 V.
DD
DD33USB
•
•
V
= 1.2 to 3.6 V: power supply for the V
domain when V is not present.
BAT
SW DD
V
: V
supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
CAP
CORE
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The V domain is split into the
CORE
following power domains that can be independently switch off.
®
–
D1 domain containing some peripherals and the Cortex -M7 core.
®
–
D2 domain containing a large part of the peripherals and the Cortex -M4 core.
D3 domain containing some peripherals and the system control.
= 1.62 V to 3.6 V: SMPS step-down converter power supply
–
•
V
V
V
V
DDSMPS
DDSMPS
LXSMPS
FBSMPS
must be kept at the same voltage level as V
.
DD
•
•
= SMPS step-down converter output coupled to an inductor.
= V , 1.8 V or 2.5 V external SMPS step-down converter feedback
CORE
voltage sense input.
•
•
•
V
V
V
= 1.62 to 3.6 V: supply voltage for the DSI internal regulator
DDDSI
= 1.15 to 1.3 V: optional supply voltage for the DSI PHY (DSI regulator off)
DD12DSI
: DSI regulator supply output
CAPDSI
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 4):
•
When V is below 1 V, other power supplies (V
, V
, V
, V
)
DDDSI
DD
DDA
DD33USB
DD50USB
must remain below V + 300 mV.
DD
•
When V is above 1 V, all power supplies are independent (except for V
,
DD
DDSMPS
which must remain at the same level as V ).
DD
During the power-down phase, V can temporarily become lower than other supplies only
DD
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
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DS12930 Rev 1
STM32H747xI/G
Functional overview
Figure 4. Power-up/power-down sequence
V
3.6
(1)
VDDX
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB and VDDDSI
Operating mode
Power-down
time
VDDX < VDD + 300 mV
VDDX independent from VDD
MSv47490V1
.
2. VDD and VDDSMPS must be wired together into order to follow the same voltage sequence.
3.5.2
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors V power supply and compares it to a fixed threshold.
DD
The devices remain in Reset mode when V is below this threshold,
DD
•
Power-down reset (PDR)
The PDR supervisor monitors V power supply. A reset is generated when V drops
DD
DD
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
Brownout reset (BOR)
•
The BOR supervisor monitors V power supply. Three BOR thresholds (from 2.1 to
DD
2.7 V) can be configured through option bytes. A reset is generated when V drops
DD
below this threshold.
DS12930 Rev 1
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46
Functional overview
STM32H747xI/G
3.5.3
Voltage regulator (SMPS step-down converter and LDO)
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
•
Run mode (VOS0 to VOS3)
–
–
–
–
Scale 0: boosted performance (available only with LDO regulator)
Scale 1: high performance
Scale 2: medium performance and consumption
Scale 3: optimized performance and low-power consumption
Note:
For STM32H7x7xIT3 sales types (industrial temperature range) the voltage regulator output
can be set only to VOS2 or VOS3 in Run mode (VOS1 is not available for industrial
temperature range).
•
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
3.5.4
SMPS step-down converter
The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear
switching regulator that provides lower power consumption than a conventional voltage
regulator (LDO).
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Functional overview
The SMPS step-down converter can be used for the following purposes:
•
Direct supply of the V
domain
CORE
–
the SMPS step-down converter operating modes follow the device system
operating modes (Run, Stop, Standby).
–
the SMPS step-down converter output voltage are set according to the selected
VOS and SVOS bits (voltage scaling)
•
Delivery of an intermediate voltage level to supply the internal voltage regulator (LDO)
–
SMPS step-down converter operating modes
When the SDEXTHP bit is equal to 0 in the PWR_CR3 register, the SMPS step-
down converter follows the device system operating modes (Run, Stop and
Standby).
When the SDEXTHP bit is equal to 1 in PWR_CR3, the SMPS step-down
converter is forced to High-performance mode and does not follow the device
system operating modes (Run, Stop and Standby).
–
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the
selected SD level
•
Delivery of an external supply
–
The SMPS step-down converter is forced to High-performance mode (provided
SDEXTHP bit is equal to 1 in PWR_CR3)
–
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the
selected SD level
3.6
Low-power strategy
There are several ways to reduce power consumption on STM32H747xI/G:
•
Select the SMPS step-down converter as V
enhance power efficiency.
supply voltage source, as it allows to
CORE
•
•
Select the adequate voltage scaling
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode, and by individually clock gating the peripherals that are not used.
•
Save power consumption when one or both CPUs are idle, by selecting among the
available low-power mode according to the user application needs. This allows
achieving the best compromise between short startup time, low-power consumption, as
well as available wakeup sources.
The devices feature several low-power modes:
•
•
•
•
•
•
CSleep (CPU clock stopped)
CStop (CPU sub-system clock stopped)
DStop (Domain bus matrix clock stopped)
Stop (System clock stopped)
DStandby (Domain powered down)
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
®
the Cortex -Mx core is set after returning from an interrupt service routine.
DS12930 Rev 1
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46
Functional overview
STM32H747xI/G
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode. For instance
D1 or D2 domain enters DStop/DStandby mode when the CPU of the domain is in CStop
mode AND the other CPU has no peripheral allocated in that domain, or if it is in CStop
mode too. D3 domain can enter DStop/DStandby mode if both core subsystems do not have
active peripherals in D3 domain, and D3 is not forced in Run mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
®
The clock system can be re-initialize by a master CPU (either the Cortex -M4 or -M7) after
exiting Stop mode while the slave CPU is held in low-power mode. Once the master CPU
has re-initialized the system, the slave CPU can receive a wakeup interrupt and proceed
with the interrupt service routine.
Table 2. System vs domain low-power mode
D1 domain power
mode
D2 domain power
mode
D3 domain power
mode
System power mode
Run
Stop
DRun/DStop/DStandby DRun/DStop/DStandby
DRun
DStop
DStop/DStandby
DStandby
DStop/DStandby
DStandby
Standby
DStandby
3.7
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
Internal oscillators:
–
–
–
–
64 MHz HSI clock
48 MHz RC oscillator
4 MHz CSI clock
32 kHz LSI clock
•
External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
–
LSE clock: 32.768 kHz
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The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
3.7.2
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
•
•
•
•
•
•
•
•
•
•
Power-on reset (pwr_por_rst)
Brownout reset
Low level on NRST pin (external reset)
Independent watchdog 1 (from D1 domain)
Independent watchdog 2 (from D2 domain)
Window watchdog 1 (from D1 domain)
Window watchdog 2 (from D2 domain)
Software reset
Low-power mode security reset
Exit from Standby
3.8
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 5).
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Figure 5. STM32H747xI/G bus matrix
AHBS
7
CPU
ITCM
CPU
Cortex-M7
D$
64 Kbyte
Cortex-M4
I$
DTCM
Ethernet
SDMMC2 USBHS1 USBHS2
DMA1
DMA2
16KB 16KB
128 Kbyte
MAC
ART
SDMMC1 MDMA
DMA2D
LTDC
D1-to-D2 AHB
APB3
SRAM1 128
Kbyte
4
SRAM2 128
Kbyte
AHB3
SRAM3
32 Kbyte
Flash A
5
Up to 1 Mbyte
AHB1
AHB2
APB1
APB2
Flash B
Up to 1 Mbyte
AXI SRAM
512 Kbyte
QSPI
FMC
1
64-bit AXI bus matrix
D1 domain
2
32-bit AHB bus matrix
D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
BDMA
D1-to-D3 AHB
Legend
6
3
AHB4
APB4
TCM AHB
32-bit bus
AXI
APB
SRAM4
64 Kbyte
Master interface
Slave interface
64-bit bus
Backup
SRAM
Bus multiplexer
32-bit AHB bus matrix
4 Kbyte
D3 domain
MSv39740V3
STM32H747xI/G
Functional overview
3.10
DMA controllers
The devices feature four DMA instances to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
®
access Cortex -M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•
•
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
•
•
•
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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Functional overview
STM32H747xI/G
3.12
Nested vectored interrupt controller (NVIC)
®
®
Both Cortex -M7 (CPU1) and Cortex -M4 (CPU2) cores have their own nested vector
interrupt controller (respectively NVIC1 and NVIC2). Each NVIC instance is able to manage
16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt
®
lines of the Cortex -M7 with FPU core.
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processors, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events (including two interrupt lines for inter-core management).
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
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Functional overview
3.15
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
–
–
–
–
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
•
•
•
•
•
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
3.16
Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
•
•
•
Direct mode through registers
External Flash status register polling mode
Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17
Analog-to-digital converters (ADCs)
The STM32H747xI/G devices embed three analog-to-digital converters, which resolution
can be configured to 16, 14, 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
•
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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Functional overview
STM32H747xI/G
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18
Temperature sensor
STM32H747xI/G devices embed a temperature sensor that generates a voltage (V ) that
TS
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 up to +125 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.19
VBAT operation
The V
power domain contains the RTC, the backup registers and the backup SRAM.
BAT
To optimize battery duration, this power domain is supplied by V when available or by the
DD
voltage applied on VBAT pin (when V supply is not present). V
power is switched
DD
BAT
when the PDR detects that V dropped below the PDR level.
DD
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by V , in which case, the V mode is not functional.
DD
BAT
V
operation is activated when V is not present.
DD
BAT
The V
pin supplies the RTC, the backup registers and the backup SRAM.
BAT
Note:
When the microcontroller is supplied from V
, external interrupts and RTC alarm/events
BAT
do not exit it from V
operation.
BAT
When PDR_ON pin is connected to V (Internal Reset OFF), the V
functionality is no
BAT
SS
more available and V
pin should be connected to VDD.
BAT
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Functional overview
3.20
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
•
•
•
•
•
•
•
•
•
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel including DMA underrun error detection
external triggers for conversion
input voltage reference V
or internal VREFBUF reference.
REF+
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21
Ultra-low-power comparators (COMP)
STM32H747xI/G devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•
•
•
An external I/O
A DAC output channel
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22
Operational amplifiers (OPAMP)
STM32H747xI/G devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•
•
•
•
•
One positive input connected to DAC
Output connected to internal ADC
Low input bias current down to 1 nA
Low input offset voltage down to 1.5 mV
Gain bandwidth up to 7.3 MHz
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Functional overview
STM32H747xI/G
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
8 multiplexed input digital serial channels:
–
–
–
–
–
configurable SPI interface to connect various SD modulator(s)
configurable Manchester coded 1 wire interface support
PDM (Pulse Density Modulation) microphone input support
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
clock output for SD modulator(s): 0..20 MHz
•
•
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
internal sources: ADC data or memory data streams (DMA)
–
4 digital filter modules with adjustable digital signal processing:
x
–
–
Sinc filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
integrator: oversampling ratio (1..256)
•
•
•
•
up to 24-bit output data resolution, signed output data format
automatic data offset correction (offset stored in register by user)
continuous or single conversion
start-of-conversion triggered by:
–
–
–
–
software trigger
internal timers
external events
start-of-conversion synchronously with first digital filter module (DFSDM0)
•
analog watchdog feature:
–
–
–
–
low value and high value data threshold registers
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
input from final output data or from selected input digital serial channels
continuous monitoring independently from standard conversion
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Functional overview
•
short circuit detector to detect saturated analog input values (bottom and top range):
–
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
monitoring continuously each input serial channel
•
•
break signal generation on analog watchdog event or on short circuit detector event
extremes detector:
–
–
storage of minimum and maximum values of final conversion data
refreshed by software
•
•
DMA capability to read the final conversion data
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Table 3. DFSDM implementation
DFSDM features
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
Number of external triggers
X
16
Regular channel information in
identification register
X
3.24
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
•
•
•
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
•
Supports Continuous mode or Snapshot (a single frame) mode
Capability to automatically crop the image
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Functional overview
STM32H747xI/G
3.25
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
•
•
•
•
•
•
•
•
2 display layers with dedicated FIFO (64x64-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events
AXI master interface with burst of 16 words
3.26
DSI Host (DSI)
®
The DSI Host is a dedicated peripheral for interfacing with MIPI DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC, a generic APB
interface that can be used to transmit information to the display, and Video mode pattern
generator:
•
LTDC interface
It is used to transmit information in Video mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
This interface can also be used to transmit information in full bandwidth in the Adapted
Command mode (DBI).
•
•
APB slave interface
The APB slave interface allows transmitting generic information in Command mode
though a proprietary register interface. It can operate concurrently with the LTDC
interface either in Video or Adapted Command mode.
The Video mode pattern generator allows transmitting horizontal/vertical color bar and
D-PHY BER testing pattern without any kind of stimuli.
The DSI Host main features are the following:
®
•
•
•
Compliance with MIPI Alliance standards
®
Interface with MIPI D-PHY
®
Support for all commands defined in the MIPI Alliance specification for DCS:
–
–
Transmission of all Command mode packets through the APB interface
Transmission of commands in low-power and high-speed during Video mode
•
•
•
•
•
•
•
Support for up to two D-PHY data lanes
Bidirectional communication and Escape mode support through data lane 0
Support for non-continuous clock in D-PHY clock lane for additional power saving
Support for Ultra Low-Power mode with PLL disabled
ECC and Checksum capabilities
Support for End of Transmission Packet (EoTp)
Fault recovery schemes
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Functional overview
•
•
3D transmission support
Configurable selection of system interfaces
–
–
–
–
AMBA APB for control and optional support for Generic and DCS commands
Video mode interface through LTDC
Adapted Command mode interface through LTDC
Independently programmable Virtual Channel ID in Video, Adapted Command or
APB Slave mode
•
Video mode interfaces features
–
LTDC interface color coding mappings into 24-bit interface:
16-bit RGB, configurations 1, 2, and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
–
–
Programmable polarity of all LTDC interface signals
Extended resolutions beyond the DPI standard maximum resolution of 800x480
pixels; the maximum resolution is limited by the available DSI physical link
bandwidth:
Number of lanes: 2
Maximum speed per lane: 1 Gbps
•
•
Adapted interface features
–
Support for sending large amounts of data through the memory_write_start (WMS)
and memory_write_continue (WMC) DCS commands
–
LTDC interface color coding mappings into 24-bit interface:
16-bit RGB, configurations 1, 2, and 3
18-bit RGB, configurations 1 and 2
24-bit RGB
Video mode pattern generator
–
–
Vertical and horizontal color bar generation without LTDC stimuli
BER pattern without LTDC stimuli
3.27
JPEG Codec (JPEG)
The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 10918-
1 specification. It provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
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Functional overview
STM32H747xI/G
The JPEG codec main features are as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit/channel pixel depths
Single clock per pixel encoding and decoding
Support for JPEG header generation and parsing
Up to four programmable quantization tables
Fully programmable Huffman tables (two AC and two DC)
Fully programmable minimum coded unit (MCU)
Encode/decode support (non simultaneous)
Single clock Huffman coding and decoding
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
Support for single greyscale component
Ability to enable/disable header processing
Fully synchronous design
Configuration for High-speed decode mode
3.28
3.29
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten general-
purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Max
Max
DMA
request
generation channels
Capture/ Comple-
compare mentary
timer
clock
Timer
type
Counter Counter Prescaler
interface
clock
Timer
resolution
type
factor
output
(MHz)
(MHz)
(1)
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
High-
resolution HRTIM1
timer
16-bit
Up
Yes
Yes
10
4
Yes
480
120
480
240
Any
integer
Down, between1
Up,
Advanced TIM1,
-control
16-bit
Yes
TIM8
Up/down
and
65536
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Functional overview
Table 4. Timer feature comparison (continued)
Max
Max
DMA
request
generation channels
Capture/ Comple-
compare mentary
timer
clock
Timer
Timer
type
Counter Counter Prescaler
interface
clock
resolution
type
factor
output
(MHz)
(MHz)
(1)
Any
Up,
integer
TIM2,
TIM5
32-bit
Down, between1
Up/down
Yes
Yes
No
4
4
2
1
2
1
0
0
No
120
120
120
120
120
120
120
120
240
240
240
240
240
240
240
240
and
65536
Any
integer
Down, between1
Up,
TIM3,
TIM4
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
No
No
No
1
Up/down
and
65536
Any
integer
between1
and
TIM12
Up
65536
General
purpose
Any
integer
between1
and
TIM13,
TIM14
Up
Up
Up
Up
Up
No
65536
Any
integer
between1
and
TIM15
Yes
Yes
Yes
No
65536
Any
integer
between1
and
TIM16,
TIM17
1
65536
Any
integer
between1
and
TIM6,
Basic
No
No
TIM7
65536
LPTIM1,
Low-
power
timer
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
1, 2, 4, 8,
16, 32, 64,
128
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
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Functional overview
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3.29.1
High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, Burst mode
controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
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Functional overview
3.29.2
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (Edge- or Center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.29.3
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H747xI/G
devices (see Table 4 for differences).
•
TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
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Functional overview
STM32H747xI/G
3.29.4
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.29.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
•
•
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / One-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
•
Programmable digital glitch filter
Encoder mode
3.29.6
Independent watchdogs
There are two independent watchdogs, one per domain. Each independent watchdog is
based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32
kHz internal RC and as it operates independently from the main clock, it can operate in Stop
and Standby modes. It can be used either as a watchdog to reset the device when a
problem occurs, or as a free-running timer for application timeout management. It is
hardware- or software-configurable through the option bytes.
3.29.7
3.29.8
Window watchdogs
There are two window watchdogs, one per domain. Each window watchdog is based on a 7-
bit downcounter that can be set as free-running. It can be used as a watchdog to reset the
device or each respective domain (configurable in the RCC register), when a problem
occurs. It is clocked from the main clock. It has an early warning interrupt capability and the
counter can be frozen in Debug mode.
SysTick timer
The devices feature two SysTick timers, one per CPU. These timers are dedicated to real-
time operating systems, but could also be used as a standard downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
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Functional overview
3.30
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
•
Three anti-tamper detection pins with programmable filter.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in V
mode and in all low-power modes when it is clocked by the
BAT
LSE. When clocked by the LSI, the RTC is not functional in V
all low-power modes.
mode, but is functional in
BAT
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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Functional overview
STM32H747xI/G
3.31
Inter-integrated circuit interface (I2C)
2
STM32H747xI/G devices embed four I C interfaces.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and Master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power System Management Protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
3.32
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H747xI/G devices have four embedded universal synchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7 and UART8). Refer to Table 5 for a summary of
USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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Functional overview
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 5. USART features
USART modes/features(1)
USART1/2/3/6
UART4/5/7/8
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode (Master/Slave)
Smartcard mode
-
Single-wire Half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
X
X
Dual clock domain and wakeup from low power mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
X
Tx/Rx FIFO size
16
1. X = supported.
3.33
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
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Functional overview
STM32H747xI/G
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.34
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-
duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
2
Three standard I S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in Simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
2
I S interfaces is/are configured in Master mode, the master clock can be output to the
2
external DAC/CODEC at 256 times the sampling frequency. All I S interfaces support 16x 8-
bit embedded Rx and Tx FIFOs with DMA capability.
3.35
Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
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Functional overview
3.36
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
•
•
•
•
•
•
•
•
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.37
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
•
•
•
Full-duplex communication mode
automatic SWP bus state management (active, suspend, resume)
configurable bitrate up to 2 Mbit/s
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
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Functional overview
STM32H747xI/G
3.38
Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
•
Configurable slave (port) address
Independently maskable interrupts/events:
–
–
–
MDIO Register write
MDIO Register read
MDIO protocol error
•
Able to operate in and wake up from Stop mode
3.39
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.40
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
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Functional overview
3.41
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1
features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using
the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
•
•
•
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
9 bidirectional endpoints (including EP0)
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Battery Charging Specification Revision 1.2 support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
•
•
•
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.42
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
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Functional overview
STM32H747xI/G
The devices include the following features:
•
•
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
•
•
•
•
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
•
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
3.43
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.44
Debug infrastructure
The devices offer a comprehensive set of debug and trace features on both cores to support
software development and system integration.
•
•
•
•
•
•
•
•
•
Breakpoint debugging
Code execution tracing
Software instrumentation
JTAG debug port
Serial-wire debug port
Trigger input and output
Serial-wire trace port
Trace port
®
Arm CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools. The debug infrastructure allows debugging one core at a time, or
both cores in parallel.
The trace port performs data capture for logging and analysis.
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Functional overview
A 4-Kbyte embedded trace FIFO (ETF) allows recording data and sending them to any com
port. In Trace mode, the trace is transferred by DMA to system RAM or to a high-speed
interface (such as SPI or USB). It can even be monitored by a software running on one of
the cores. Unlike hardware FIFO mode, this mode is invasive since it uses system
resources which are shared by the processors.
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46
Memory mapping
STM32H747xI/G
4
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
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Pin descriptions
5
Pin descriptions
Figure 6. WLCSP156 ballout
13
12
11
10
9
8
7
6
5
4
PD0
3
2
VDDLDO
VCAP
PA10
PC9
1
DNC(1)
VDDLDO
PE4
VCAP
VDD
PE5
VSS
PB8
PE0
VSS
PE3
PF0
PF5
PC1
PA5
PA3
PA4
PC5
PB2
VDD
VSS
PB9
PE2
PC13
PF1
PA6
PB1
PA7
PB0
VSS
VDD
PB4
PB5
PB7
PE1
PE6
PF11
PF12
PF13
PF15
PF14
PG0
PG1
PG15
PB3
VDD
VSS
PD6
PD7
PD2
PD1
PE11
PB10
PE12
PE13
PE15
PE14
PD4
PA15
VDD
PA13
PA8
VSS
PA12
PA11
PC8
A
B
C
D
E
F
VBAT
PD3
PC12
VSS
PC14-
OSC32_IN
PC15-
OSC32_OUT
PB6
BOOT0
PDR_ON
PD5
PC11
PC10
PA14
PC6
VSS
SMPS
VLX
VDD
PA9
VDD
SMPS
VFB
SMPS
VDD50
USB
VDD33
USB
PC7
VDD
SMPS
PF3
PF2
PF4
PG4
VSS
PG8
PG5
DSI_
D1P
DSI_
CKP
DSI_
D0P
DSI_
D1N
DSI_
CKN
DSI_
D0N
VCAP
DSI
G
H
J
VDD
VSS
PC0
PE10
PE7
PD8
PG3
PG2
PH1-
OSC_OUT
PH0-
OSC_IN
NRST
VDDA
PA2
PB13
PB12
PB11
VSS
PD14
PD11
PD9
VSSDSI
PD15
PD13
PD10
PB14
VSSA
PC2_C
PA0
VREF+
PC3_C
PA1
PE8
K
L
PE9
VDD
PD12
PB15
VSS
VSS
VDDLDO
VDD
VSS
M
VSS
VDD
PC4
VDD
VCAP
VSS
MSv43741V5
1. The DNC ball must neither be connected to GND nor to VDD
2. The above figure shows the package top view.
.
DS12930 Rev 1
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95
Pin descriptions
STM32H747xI/G
Figure 7. UFBGA169 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
C
D
E
F
VSS
PE2
VDD
PE6
VCAP
PB5
PB3
VSS
PD7
VDD
PD3
PA14
VSS
PA10
VDDLDO
PDR_
ON
VBAT
VSS
PE1
PE0
PE5
BOOT0
PB7
PB4
PG15
PB9
VDD
PG9
PD6
PD5
VSS
PD1
PA15
PD0
PA13
PC10
PA9
VDD
VSS
PA11
VDD
VDDLDO
VCAP
PA12
PC14_
OSC32_
IN
PE3
PE4
PC15_
OSC32_
OUT
VSS
PB8
PG10
PG11
PG13
PG12
PG2
PD4
PC12
PC11
PG8
PA8
VLX
SMPS
VDD
PC13
PB6
PG14
PF2
PD2
PC7
PC9
PC6
PG6
VSS
VDD
SMPS
VSS
SMPS
VFB
SMPS
VDD50_ VDD33_
USB USB
PF1
PG7
PG3
PE13
PE12
PE15
PE8
PC8
PF0
PF6
G
H
J
PF4
PF3
PF5
PF9
PC1
PF7
PF8
PG5
PG4
VSSDSI VSSDSI
VSS
DSI
DSI_
D1P
DSI_
D1N
VDD
VSS
PF10
PC0
PA7
PC4
PA6
PB0
NRST
PA5
PB1
PD14
PD13
PB10
VDD
VSS
PD15
PD12
PD11
PB12
PB13
PH1_
OSCOUT OSCIN
PH0_
VSS
DSI
DSI_
CKP
DSI_
CKN
PF12
PF11
PG0
VSS
PE9
PG1
VSS
DSI
DSI_
D0P
DSI_
D0N
K
L
PC2_C
PC3_C
VDDA
VDD
PC5
PE7
PA0
VSSA_
VREF-
VCAP
DSI
PB2
PE10
PF15
PE11
VDD
PB15
PB14
VSS
PA1
PA2
PA4
VDD
DSI
M
N
VREF+
VSS
PF13
PF14
PE14
PB11
PD9
PD8
PA3
VCAP VDDLDO
PD10
MSv43740V4
1. The above figure shows the package top view.
48/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Figure 8. LQFP176 pinout
1
2
3
4
5
6
7
8
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PE2
PE3
PA13
PA12
PE4
PA11
PE5
PA10
PE6
PA9
VSS
PA8
VDD
VDD
VBAT
PC9
9
PC13
PC8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PC14-OSC32_IN
PC15-OSC32_OUT
VSS
PC7
PC6
VDD33USB
VDD50USB
VSS
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPs
PF0
PG8
PG7
PG6
PG5
PF1
PG4
PF2
VDD
PF3
VSS
176-pins
PF4
PG3
PF5
PG2
VSS
VSSDSI
VDD12DSI
DSI_CKN
DSI_CKP
VSSDSI
DSI_D0N
DSI_D0P
VDD12DSI
VCAPDSI
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
VDD
98
97
96
95
94
93
92
91
PD15
PD14
PD13
PD12
PD11
PC2_C
PC3_C
VSSA
VREF+
VDDA
PA0
VSS
VDD
PA1
PD10
PD9
90
PA2
89
VDD
PD8
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
MSv43745V4
1. The above figure shows the package top view.
DS12930 Rev 1
49/242
95
Pin descriptions
STM32H747xI/G
Figure 9. LQFP208 pinout
1
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
PE2
PH13
2
PE3
PE4
VDD
3
VDDLDO
VSS
4
PE5
5
PE6
VCAP
PA13
6
VSS
7
VDD
PA12
8
VBAT
PA11
9
PI8
PA10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PC13
PA9
PC14-OSC32_IN
PC15-OSC32_OUT
PI9
PA8
PC9
PC8
PI10
PC7
PI11
PC6
VSS
VDD33USB
VDD50USB
VSS
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
PF0
PG8
PG7
PG6
PG5
PF1
PG4
PF2
VDD
208-pins
PF3
VSS
PF4
PG3
PF5
PG2
VSS
VSSDSI
DSI_D1N
DSI_D1P
VDD12DSI
DSI_CKN
DSI_CKP
VSSDSI
DSI_D0N
DSI_D0P
VDD12DSI
VCAPDSI
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VSSA
VREF+
VDDA
PA0
VDD
PD15
PD14
VDD
VSS
PD13
PA1
PD12
PA2
PD11
PH2
VSS
VDD
VDD
VSS
PD10
PH3
PD9
PH4
PD8
MSv43749V4
1. The above figure shows the package top view.
50/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Figure 10. TFBGA240+25 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PA15
15
16
17
VDD
LDO
VCAP
A
B
C
D
E
F
VSS
PI6
PI5
PI4
PB5
PK5
PG10
PG9
PD5
PD4
PC10
PI1
PI0
VSS
VBAT
VSS
PI7
PE2
PE3
PC13
PI10
PF1
PI14
VSS
PF7
PF10
PC2
PA2
PE1
PE0
PB9
PI8
PB6
PB7
PB8
PE6
VDD
VDD
VDD
PF4
VDD
VDD
VDD
PA0
PI15
PA7
PB1
PB0
VSS
PB3
PB4
PK6
PK7
PK4
PK3
PG11
PG12
PG13
PJ15
VSS
PD6
PD7
PJ12
VDD
PD3
PC12
PD2
PC11
VSS
PD0
PC8
PC7
VDD
VDD
VDD
VDD
VDD
VDD
PJ8
PA14
PI3
PI2
PA13
PA9
PA8
PG8
PG6
PG3
PK1
PH15
VSS
PH13
PA12
PG7
VSS
PG2
PH14
PC15-
OSC32_
OUT
PC14-
OSC32
_IN
VDD
LDO
VCAP
PA11
PE5
PE4
PG15
VDD
PG14
PJ14
PJ13
PA10
PC9
PC6
PG5
PG4
PK0
VLX
SMPS
PDR
_ON
PI9
BOOT0 VDD
PD1
VDD
SMPS SMPS
VSS
VDD
33USB
PI11
PF0
PF3
PF5
PF8
PF9
PC3
PA1
PH5
VSS
PC4
PC5
VFB
PF2
VDD50
USB
G
H
J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SMPS
PI12
PI13
PK2
PH1-
OSC_
OUT
PH0-
OSC
_IN
VSS
DSI
VSSDSI
DSI_
D1P
DSI_
D1N
K
L
NRST
PF6
PJ11 VSSDSI
PJ10 VSSDSI
DSI_
CKP
DSI_
CKN
VDDA
PC0
DSI_
D0N
DSI_
D0P
M
N
P
R
T
VREF+ PC1
PJ9
VSSDSI
PJ6
VCAP
DSI
VREF-
VSSA
PH2
PH3
PJ0
PJ1
PB2
PJ2
PJ3
VDD
PF13
PF12
PF11
PJ4
VDD
PF14
VSS
PG0
PG1
PE10
PE9
VDD
PE11
PE12
PE13
PE14
VDD
PB10
PE15
PH6
VDD
PB11
PJ5
PJ7
VSS
PD14
PD12
PD10
PD8
VDD
DSI
PH4
PH10
PH9
PH8
PH7
PH11
PH12
PB12
PB13
PD15
PD11
PB15
PB14
PC2_C PC3_C PA6
PF15
PE8
PD13
PD9
PA0_C PA1_C
VSS PA3
PA5
PA4
VSS
VDD
LDO
VCAP
U
PE7
VSS
MSv43743V4
1. The above figure shows the package top view.
DS12930 Rev 1
51/242
95
Pin descriptions
STM32H747xI/G
Table 6. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
ANA
FT
TT
B
Input / output pin
Analog-only Input
5 V tolerant I/O
3.3 V tolerant I/O
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
RST
I/O structure
Option for TT and FT I/Os
_f
I2C FM+ option
_a
_u
_h
analog option (supplied by VDDA)
USB option (supplied by VDD33USB
)
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
functions
Functions directly selected/enabled through peripheral registers
52/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
FT_
h
SAI4_MCLK_A,
QUADSPI_BK1_IO2,
SAI4_CK1,
D9
A2
1
1
C3
PE2
I/O
-
-
ETH_MII_TXD3,
FMC_A23, EVENTOUT
TRACED0,
TIM15_BKIN,
SAI1_SD_B,
FT_
h
D10
B12
C3
D3
2
3
2
3
D3
D2
PE3
PE4
I/O
I/O
-
-
-
-
SAI4_SD_B, FMC_A19,
EVENTOUT
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
FT_
h
SPI4_NSS, SAI1_FS_A,
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1,
SPI4_MISO,
SAI1_SCK_A,
SAI4_SCK_A,
FT_
h
C11
E4
4
4
D1
PE5
I/O
-
-
SAI4_CK2, FMC_A21,
DCMI_D6, LCD_G0,
EVENTOUT
TRACED3,
TIM1_BKIN2, SAI1_D1,
TIM15_CH2,
SPI4_MOSI,
FT_
h
SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
E8
C2
5
5
E5
PE6
I/O
-
-
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
-
-
A1
A9
B1
6
7
8
6
7
8
A1
-
VSS
VDD
VBAT
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
B13
B1
DS12930 Rev 1
53/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
D11
-
-
-
-
B2
E4
VSS
PI8
S
-
-
-
-
-
RTC_TAMP2/
WKUP3
-
-
9
I/O FT
I/O FT
EVENTOUT
RTC_TAMP1/
RTC_TS/WKUP2
E9
E3
C1
9
10
E3
C2
PC13
-
-
EVENTOUT
EVENTOUT
PC14-
C13
10
11
12
OSC32_IN
I/O FT
I/O FT
OSC32_IN
(OSC32_IN)(1)
PC15-
OSC32_OUT(
C12
D2
11
-
C1
E2
-
-
EVENTOUT
OSC32_OUT
OSC32_OUT)
(1)
UART4_RX,
FDCAN1_RX,
FMC_D30,
LCD_VSYNC,
EVENTOUT
FT_
-
-
13
PI9
I/O
h
-
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER,
FMC_D31,
FT_
-
-
-
-
-
-
14
15
F3
F4
PI10
PI11
I/O
h
-
-
-
LCD_HSYNC,
EVENTOUT
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
I/O FT
WKUP4
-
B4
E2
F2
E1
F1
F3
12
13
14
15
16
17
16
17
18
19
20
21
A17
E6
F2
VSS
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D13
D12
E12
E13
E11
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
E1
F1
G2
I2C2_SDA, FMC_A0,
EVENTOUT
E10
F9
F4
F5
F6
18
19
20
22
23
24
G4
G3
G1
PF0
PF1
PF2
I/O FT_f
I/O FT_f
I/O FT
-
-
-
-
-
-
I2C2_SCL, FMC_A1,
EVENTOUT
I2C2_SMBA, FMC_A2,
EVENTOUT
F12
54/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
LCD_HSYNC,
EVENTOUT
-
-
-
-
H1
H2
H3
H4
J5
PI12
PI13
PI14
PF3
PF4
PF5
I/O FT
I/O FT
-
-
-
-
-
-
-
LCD_VSYNC,
EVENTOUT
-
-
-
-
-
FT_
-
-
-
-
I/O
h
LCD_CLK, EVENTOUT
FMC_A3, EVENTOUT
FMC_A4, EVENTOUT
FMC_A5, EVENTOUT
-
FT_
I/O
F13
F11
F10
G2
G1
G3
21
22
23
25
26
27
ADC3_INP5
ha
FT_
I/O
ADC3_INN5,
ADC3_INP9
ha
FT_
I/O
J4
ADC3_INP4
ha
G12
G13
-
24
25
28
29
C10
E9
VSS
VDD
S
S
-
-
-
-
-
-
H1
TIM16_CH1, SPI5_NSS,
SAI1_SD_B,
FT_
I/O
UART7_RX,
SAI4_SD_B,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_INN4,
ADC3_INP8
-
-
G4
G5
26
27
30
31
K2
K3
PF6
PF7
-
-
ha
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_TX,
SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
FT_
I/O
ADC3_INP3
ha
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
FT_
I/O
UART7_RTS/UART7_
DE, SAI4_SCK_B,
TIM13_CH1,
ADC3_INN3,
ADC3_INP7
-
G6
28
32
K4
PF8
-
ha
QUADSPI_BK1_IO0,
EVENTOUT
DS12930 Rev 1
55/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM17_CH1N,
SPI5_MOSI,
SAI1_FS_B,
FT_
ha
UART7_CTS,
SAI4_FS_B,
TIM14_CH1,
-
H3
29
33
L4
PF9
I/O
I/O
-
ADC3_INP2
QUADSPI_BK1_IO1,
EVENTOUT
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK,
SAI4_D3, DCMI_D11,
LCD_DE, EVENTOUT
FT_
ha
ADC3_INN2,
ADC3_INP6
-
H4
J2
30
31
34
35
L3
J2
PF10
-
-
PH0-
OSC_IN(PH0)
H12
I/O FT
EVENTOUT
OSC_IN
PH1-
H13
H11
J1
32
33
36
37
J1
OSC_OUT(P I/O FT
H1)
-
-
EVENTOUT
-
OSC_OUT
-
H5
K1
NRST
PC0
I/O RST
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B,
FT_
G11
J4
34
38
L2
I/O
a
-
ADC123_INP10
OTG_HS_ULPI_STP,
FMC_SDNWE,LCD_R5,
EVENTOUT
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO, ADC123_INN10,
FT_
I/O
SAI1_SD_A,
SAI4_SD_A,
SDMMC2_CK,SAI4_D1,
ETH_MDC,
ADC123_INP11,
RTC_TAMP3/
WKUP5
G10
J3
35
39
M2
PC1
-
ha
MDIOS_MDC,
EVENTOUT
FT_
C1DSLEEP,
DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
ADC123_INN11,
ADC123_INP12
-
-
-
-
M3(2)
PC2
I/O
a
-
-
AN TT_
ADC3_INN1,
ADC3_INP0
K13(3) K1(3) 36(3) 40(3) R1(1)
PC2_C
A
a
EVENTOUT
56/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
FT_
a
C1SLEEP,
DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
ADC12_INN12,
ADC12_INP13
-
-
-
-
M4(1)
PC3
I/O
-
-
AN TT_
K12(3) K2(3) 37(3) 41(3) R2(1)
PC3_C
ADC3_INP1
A
a
EVENTOUT
-
-
M2
C12
-
-
-
-
-
E11
C13
P1
VDD
VSS
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J13
-
38
-
42
-
VSSA
VREF-
VREF+
VDDA
L1
N1
J12
J11
M1
L2
39
40
43
44
M1
L1
FT_
a
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
USART2_CTS/USART2
_NSS, UART4_TX,
SDMMC2_CMD,
SAI2_SD_B,
ADC1_INP16,
WKUP0
L13
K3
41
45
N5(1)
T1(1)
N4(1)
PA0
PA0_C
PA1
I/O
-
-
-
AN TT_
ADC12_INN1,
ADC12_INP0
-
-
-
-
A
a
ETH_MII_CRS,
EVENTOUT
FT_
ha
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT,
ADC1_INN16,
ADC1_INP17
L12
L3
42
46
I/O
TIM15_CH1N,
USART2_RTS/USART2
_DE, UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH
_RMII_REF_CLK,
LCD_R2, EVENTOUT
AN TT_
-
-
-
-
T2(1)
PA1_C
-
ADC12_INP1
A
a
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
FT_
a
USART2_TX,
SAI2_SCK_B,
ADC12_INP14,
WKUP1
K11
M3
43
47
N3
PA2
I/O
-
ETH_MDIO,
MDIOS_MDIO,LCD_R1,
EVENTOUT
DS12930 Rev 1
57/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
FT_
ha
-
-
-
48
N2
PH2
I/O
-
ADC3_INP13
ETH_MII_CRS,
FMC_SDCKE0,
LCD_R0, EVENTOUT
-
-
-
44
49
50
F5
VDD
VSS
S
S
-
-
-
-
-
-
-
-
N1
45
C16
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
FT_
ha
ADC3_INN13,
ADC3_INP14
-
-
-
51
P2
PH3
I/O
-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
FT_f
a
ADC3_INN14,
ADC3_INP15
-
-
-
-
-
-
52
53
P3
P4
PH4
PH5
I/O
I/O
-
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
FT_f
a
ADC3_INN15,
ADC3_INP16
EVENTOUT
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
FT_
ha
J10
N2
46
54
U2
PA3
I/O
-
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL,
ADC12_INP15
LCD_B5, EVENTOUT
L11
-
-
47
48
55
56
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
M12
G5
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
TT_
a
ADC12_INP18,
DAC1_OUT1
K10
N3
49
57
U3
PA4
I/O
-
SPI6_NSS,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
58/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
SPI6_SCK,
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
TT_
ha
H10
J5
50
58
T3
PA5
I/O
-
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO,
FT_
a
TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
G9
M4
51
59
R3
PA6
I/O
-
ADC12_INP3
TIM1_BKIN_COMP12,
DCMI_PIXCLK,
LCD_G2, EVENTOUT
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI,
ADC12_INN3,
ADC12_INP7,
OPAMP1_VINM
TT_
a
J9
K4
52
60
R5
PA7
I/O
-
TIM14_CH1,
ETH_MII_RX_DV/ETH_
RMII_CRS_DV,
FMC_SDNWE,
EVENTOUT
C2DSLEEP,
DFSDM1_CKIN2,
I2S1_MCK,
ADC12_INP4,
OPAMP1_VOUT,
COMP1_INM
TT_
a
SPDIFRX1_IN3,
ETH_MII_RXD0/ETH_R
MII_RXD0,
M11
L4
53
61
T4
PC4
I/O
-
FMC_SDNE0,
EVENTOUT
DS12930 Rev 1
59/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
C2SLEEP, SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
SAI4_D3,
ETH_MII_RXD1/ETH_R
MII_RXD1,
ADC12_INN4,
ADC12_INP8,
OPAMP1_VINM
TT_
a
L10
K5
54
62
U4
PC5
I/O
-
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
-
-
-
-
-
-
G13
R4
VDD
VSS
S
S
-
-
-
-
-
-
-
-
H2
-
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
DFSDM1_CKOUT,
ADC12_INN5,
ADC12_INP9,
FT_
a
K9
N4
55
63
U5
PB0
I/O
-
UART4_CTS, LCD_R3, OPAMP1_VINP,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
COMP1_INP
LCD_G1, EVENTOUT
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
TT_
u
DFSDM1_DATIN1,
LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
ADC12_INP5,
COMP1_INM
H9
H6
56
64
T5
PB1
I/O
I/O
-
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A,
FT_
ha
M10
L5
57
65
66
R6
P5
PB2
PI15
-
-
COMP1_INP
QUADSPI_CLK,
SAI4_D1, EVENTOUT
LCD_G2, LCD_R0,
EVENTOUT
-
-
-
I/O FT
-
LCD_R7, LCD_R1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
N6
P6
T6
PJ0
PJ1
PJ2
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
LCD_R2, EVENTOUT
DSI_TE, LCD_R3,
EVENTOUT
60/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
-
-
-
-
-
U6
U7
PJ3
PJ4
I/O FT
I/O FT
-
-
LCD_R4, EVENTOUT
LCD_R5, EVENTOUT
-
-
-
-
-
SPI5_MOSI,
SAI2_SD_B,
FMC_SDNRAS,
FT_
F8
K6
58
67
T7
PF11
I/O
a
-
ADC1_INP2
DCMI_D12, EVENTOUT
FT_
I/O
ADC1_INN2,
ADC1_INP6
G8
J6
59
68
R7
PF12
-
FMC_A6, EVENTOUT
ha
L9
-
-
-
-
-
-
J3
VSS
VDD
S
S
-
-
-
-
-
-
M9
H5
DFSDM1_DATIN6,
I2C4_SMBA, FMC_A7,
EVENTOUT
FT_
I/O
H8
K8
M5
N5
60
61
69
70
P7
P8
PF13
PF14
-
-
ADC2_INP2
ha
DFSDM1_CKIN6,
I2C4_SCL, FMC_A8,
EVENTOUT
FT_f
ADC2_INN2,
ADC2_INP6
I/O
ha
FT_f
I2C4_SDA, FMC_A9,
EVENTOUT
J8
L8
M7
L6
62
63
71
72
R9
T8
PF15
PG0
I/O
h
-
-
-
-
FT_
I/O
h
FMC_A10, EVENTOUT
-
-
M9
-
64
65
73
74
J16
VSS
VDD
S
S
-
-
-
-
-
-
H13
TT_
M8
J7
66
75
U8
U9
PG1
I/O
h
-
FMC_A11, EVENTOUT OPAMP2_VINM
TIM1_ETR,
DFSDM1_DATIN2,
TT_
I/O
UART7_RX,
QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4,
EVENTOUT
OPAMP2_VOUT,
COMP2_INM
H7
K7
67
76
PE7
-
ha
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_TX,
QUADSPI_BK2_IO1,
FMC_D5/FMC_DA5,
COMP2_OUT,
TT_
I/O
J7
L8
68
77
T9
PE8
-
OPAMP2_VINM
ha
EVENTOUT
DS12930 Rev 1
61/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_CH1,
DFSDM1_CKOUT,
UART7_RTS/UART7_
DE,
QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6,
EVENTOUT
TT_
ha
OPAMP2_VINP,
COMP2_INP
K7
N6
69
78
P9
PE9
I/O
-
L7
M6
-
70
71
79
80
J17
J13
VSS
VDD
S
S
-
-
-
-
-
-
-
-
M7
TIM1_CH2N,
DFSDM1_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
FT_
ha
G7
G6
L7
72
73
81
82
N9
PE10
PE11
I/O
I/O
-
-
COMP2_INM
COMP2_INP
TIM1_CH2,
DFSDM1_CKIN4,
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
FT_
ha
N7
P10
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
FT_
h
J6
J8
74
75
83
84
R10
T10
PE12
PE13
I/O
I/O
-
-
SAI2_SCK_B,
-
-
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO,
FT_
h
K6
H8
SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
-
-
H2
-
-
-
-
-
T12
K13
VSS
VDD
S
S
-
-
-
-
-
-
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
FT_
h
M6
M8
76
85
U10
PE14
I/O
-
-
62/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_BKIN,
COMP_TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12,
LCD_R7, EVENTOUT
FT_
h
L6
K8
K9
77
78
86
87
R11
P11
PE15
PB10
I/O
-
-
-
-
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
USART3_TX,
H6
I/O FT_f
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
K5
N8
79
88
P12
PB11
I/O FT_f
-
-
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_
RMII_TX_EN, DSI_TE,
LCD_G5, EVENTOUT
M5
L5
L4
M4
-
N9
80
81
82
-
89
90
91
-
U11
-
VCAP
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N10
U12
L13
R12
VDDLDO
VDD
-
-
-
-
-
-
PJ5
I/O FT
LCD_R6, EVENTOUT
TIM12_CH1,
I2C2_SMBA,SPI5_SCK,
ETH_MII_RXD2,
FMC_SDNE1,
DCMI_D8, EVENTOUT
-
-
-
-
-
-
92
93
T11
PH6
PH7
I/O FT
-
-
-
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FT_f
U13
I/O
a
FMC_SDCKE1,
DCMI_D9, EVENTOUT
DS12930 Rev 1
63/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM5_ETR, I2C3_SDA,
FMC_D16,
FT_f
ha
-
-
-
94
T13
PH8
I/O
-
-
DCMI_HSYNC,
LCD_R2, EVENTOUT
-
E13
L9
-
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
M4
M13
TIM12_CH2,
I2C3_SMBA, FMC_D17,
DCMI_D0, LCD_R3,
EVENTOUT
FT_
h
-
-
-
-
-
-
95
96
R13
P13
PH9
I/O
I/O
-
-
-
-
TIM5_CH1,
I2C4_SMBA, FMC_D18,
DCMI_D1, LCD_R4,
EVENTOUT
FT_
h
PH10
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2,
LCD_R5, EVENTOUT
FT_f
h
-
-
-
-
-
-
97
98
P14
R14
PH11
PH12
I/O
I/O
-
-
-
-
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3,
LCD_R6, EVENTOUT
FT_f
h
-
D1
-
83
84
99
N16
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
M4
100
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FT_
u
FDCAN2_RX,
J5
L10
85
101 T14
PB12
I/O
-
-
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_R
MII_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX,
EVENTOUT
64/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
FT_
u
USART3_CTS/USART3
_NSS, FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_R
MII_TXD1, UART5_TX,
EVENTOUT
H5
M10
86
102 U14
PB13
I/O
-
OTG_HS_VBUS
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3
_DE, UART4_RTS/
UART4_DE,
FT_
u
M3
N11
87
103 U15
PB14
I/O
-
-
SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
FT_
u
M2
M11
88
104 T15
PB15
I/O
-
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2,
UART4_CTS,
-
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
DFSDM1_CKIN3,
SAI3_SCK_B,
FT_
h
USART3_TX,
G5
N12
89
105 U16
PD8
I/O
-
-
SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
DS12930 Rev 1
65/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
DFSDM1_DATIN3,
SAI3_SD_B,
FT_
h
USART3_RX,
K4
L3
M12
90
106 T17
PD9
I/O
I/O
-
-
-
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
DFSDM1_CKOUT,
SAI3_FS_B,
USART3_CK,
FT_
h
N13
91
107 T16
PD10
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
-
L11
L13
92
93
108 N12
109 U17
VDD
VSS
S
S
-
-
-
-
-
-
-
-
M1
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3
_NSS,
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
FT_
h
J4
K10
94
110 R15
PD11
I/O
-
-
LPTIM1_IN1,
TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/
FT_f
h
L2
J10
95
96
111
R16
PD12
PD13
I/O
I/O
-
-
-
-
USART3_DE,
QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A,
FT_f
h
K3
J9
112 R17
FMC_A18, EVENTOUT
L1
-
-
-
-
-
113
114
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
N11
TIM4_CH3,
SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0,
EVENTOUT
FT_
h
H4
H9
97
115
P16
PD14
I/O
-
-
66/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM4_CH4,
SAI3_MCLK_A,
UART8_RTS/
FT_
h
J3
H10
98
116
P15
PD15
I/O
-
-
UART8_DE,
FMC_D1/FMC_DA1,
EVENTOUT
TIM8_CH2, LCD_R7,
EVENTOUT
-
-
-
-
-
-
-
-
N15
N14
PJ6
PJ7
I/O FT
I/O FT
-
-
-
-
TRGIN, TIM8_CH2N,
LCD_G0, EVENTOUT
K2
-
-
-
-
-
-
N10
R8
VDD
VSS
S
S
-
-
-
-
-
-
-
-
C12
TIM1_CH3N,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N13
M14
L14
K14
PJ8
PJ9
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
TIM8_CH1, UART8_TX,
LCD_G1, EVENTOUT
-
-
-
-
TIM1_CH3,
TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
TIM1_CH2N,
TIM8_CH2, SPI5_MOSI,
LCD_G3, EVENTOUT
PJ10
PJ11
TIM1_CH2,
TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
-
M13
-
99
-
117
-
N8
P17
U1
VDD
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDDDSI
VSS
S
-
100
101
102
118
S
K1
-
L12
-
119 N17
120
VCAPDSI
VDD12DSI
DSI_D0P
DSI_D0N
VSSDSI
DSI_CKP
DSI_CKN
S
-
S
J2
J1
H3
H2
H1
K12 103
K13 104
G12 105
121 M16
122 M17
123 K15
I/O TT
I/O TT
S
J12
J13
106
107
124
125
L16
L17
I/O TT
I/O TT
DS12930 Rev 1
67/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
-
-
108
126
127 K16
128 K17
-
VDD12DSI
DSI_D1P
DSI_D1N
VSSDSI
S
-
-
-
-
-
-
-
-
-
-
-
-
-
G2
G1
-
H12
H13
-
-
I/O TT
I/O TT
G13 109
129
L15
S
-
TIM1_CH1N,
-
-
-
-
-
-
-
J14
PK0
PK1
I/O FT
I/O FT
-
-
TIM8_CH3, SPI5_SCK,
LCD_G5, EVENTOUT
-
-
TIM1_CH1,
TIM8_CH3N,
SPI5_NSS, LCD_G6,
EVENTOUT
-
-
J15
TIM1_BKIN,
TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
-
-
-
H17
PK2
I/O FT
-
-
TIM8_BKIN,
TIM8_BKIN_COMP12,
FMC_A12, EVENTOUT
FT_
G3
G4
H7
G8
110
111
130 H16
131 H15
PG2
PG3
I/O
h
-
-
-
-
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
FT_
I/O
h
-
-
-
112
113
132
133
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
E12
N7
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0,
EVENTOUT
FT_
h
F4
F1
G10 114
134 H14
135 G14
PG4
PG5
I/O
I/O
-
-
-
-
TIM1_ETR,
FMC_A15/FMC_BA1,
EVENTOUT
FT_
h
G9
115
TIM17_BKIN,
HRTIM_CHE1,
QUADSPI_BK1_NCS,
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
FT_
h
-
G11 116
136 G15
PG6
I/O
-
-
68/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
HRTIM_CHE2,
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
FT_
h
-
F8
117
137 F16
PG7
PG8
I/O
I/O
-
-
-
-
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6
_DE, SPDIFRX1_IN3,
ETH_PPS_OUT,
FT_
h
F2
F9
-
118
119
138 F15
FMC_SDCLK, LCD_G7,
EVENTOUT
F3
E3
E1
E2
139 G16
140 G17
141 F17
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F12 120
F13 121
VDD50USB
VDD33USB
VDD
-
-
-
M5
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK,
USART6_TX,
FT_
h
SDMMC1_D0DIR,
FMC_NWAIT,
F5
F11
122
142 F14
PC6
I/O
-
SWPMI_IO
SDMMC2_D6,
SDMMC1_D6,
DCMI_D0,
LCD_HSYNC,
EVENTOUT
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
FT_
h
SDMMC1_D123DIR,
FMC_NE1,
E4
E10 123
143 F13
PC7
I/O
-
-
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7,
DCMI_D1, LCD_G6,
EVENTOUT
DS12930 Rev 1
69/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
FT_
h
UART5_RTS/
UART5_DE,
D1
F10 124
144 E13
PC8
I/O
-
-
FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0,
DCMI_D2, EVENTOUT
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN,UART5_CTS,
QUADSPI_BK1_IO0,
LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1,
DCMI_D3, LCD_B2,
EVENTOUT
FT_f
h
D2
E11
125
126
145 E14
PC9
VDD
I/O
S
-
-
-
-
-
-
-
L5
-
-
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2,
I2C3_SCL,
FT_f
ha
USART1_CK,
OTG_FS_SOF,
UART7_RX,
D3
D10 127
146 E15
PA8
I/O
-
-
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
FT_
u
D4
D11 128
147 D15
PA9
I/O
-
OTG_FS_VBUS
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5,
EVENTOUT
70/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
FDCAN1_TXFD_MODE,
OTG_FS_ID,
FT_
u
C2
A13 129
148 D14
PA10
I/O
-
-
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS/USART1
_NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
FT_
u
C1
D12 130
149 E17
PA11
I/O
-
-
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/
LPUART1_DE,
SPI2_SCK/I2S2_CK,
UART4_TX,
FT_
u
B1
C3
D13 131
150 E16
PA12
I/O
-
-
-
-
USART1_RTS/
USART1_DE,
SAI2_FS_B,
FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
PA13(JTMS/
SWDIO)
JTMS-SWDIO,
EVENTOUT
B11
132
151 C15
152 D17
I/O FT
B2
A1
A2
B3
C13 133
134
B13 135
VCAP
VSS
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
153
154 C17
155 K5
-
VDDLDO
VDD
-
-
136
S
TIM8_CH1N,
UART4_TX,
FDCAN1_TX,
FT_
h
-
-
156 D16
PH13
I/O
-
-
FMC_D21, LCD_G2,
EVENTOUT
DS12930 Rev 1
71/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM8_CH2N,
UART4_RX,
FDCAN1_RX,
FT_
h
-
-
-
-
-
157 B17
PH14
PH15
PI0
I/O
I/O
I/O
-
-
-
-
-
-
FMC_D22, DCMI_D4,
LCD_G3, EVENTOUT
TIM8_CH3N,
FT_
h
FDCAN1_TXFD_MODE,
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
-
-
158 B16
159 A16
TIM5_CH4,
SPI2_NSS/I2S2_WS,
FDCAN1_RXFD_MODE,
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
FT_
h
-
-
-
-
-
-
-
160
-
VSS
VDD
S
S
-
-
-
-
-
-
B12
161 VDD
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
FT_
h
-
-
-
162 A15
PI1
I/O
-
-
TIM8_CH4,
FT_
h
SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
-
-
-
-
-
-
163 B15
164 C14
PI2
PI3
I/O
I/O
-
-
-
-
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10,
EVENTOUT
FT_
h
C4
B3
-
-
137
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
VDD
PA14(JTCK/
SWCLK)
JTCK-SWCLK,
EVENTOUT
E5
A11
138
165 B14
I/O FT
-
-
72/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS,
A3
B10 139
166 A14
PA15(JTDI)
I/O FT
-
-
UART4_RTS/UART4_D
E, UART7_TX, DSI_TE,
EVENTOUT
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2,
FT_
I/O
D5
C11 140
167 A13
PC10
-
-
ha
DCMI_D8, LCD_R2,
EVENTOUT
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3,
FT_
C5
E9
141
142
168 B13
PC11
PC12
I/O
h
-
-
-
-
DCMI_D4, EVENTOUT
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK,
FT_
B4
D9
169 C12
I/O
h
UART5_TX,
SDMMC1_CK,
DCMI_D9, EVENTOUT
-
-
A7
-
-
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
VDD
DFSDM1_CKIN6,
SAI3_SCK_A,
UART4_RX,
FT_
h
A4
C10 143
170 D13
PD0
I/O
-
-
FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
DS12930 Rev 1
73/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
DFSDM1_DATIN6,
SAI3_SD_A,
FT_
h
UART4_TX,
FDCAN1_TX,
FMC_D3/FMC_DA3,
EVENTOUT
F6
E6
B5
C9
144
171 E12
PD1
PD2
PD3
I/O
I/O
I/O
-
-
-
-
-
-
TRACED2, TIM3_ETR,
UART5_RX,
SDMMC1_CMD,
DCMI_D11, EVENTOUT
FT_
h
E8
145
172 D12
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2
_NSS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
FT_
h
A10 146
173 B12
HRTIM_FLT3,
SAI3_FS_A,
FT_
h
USART2_RTS/USART2
_DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
A5
F7
D8
C8
147
148
174 A12
PD4
PD5
I/O
I/O
-
-
-
-
HRTIM_EEV3,
USART2_TX,
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
FT_
h
175
A11
B6
A6
-
-
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
B2
VDD
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
FT_
h
USART2_RX,
SAI4_SD_A,
C6
B8
149
176
B11
PD6
I/O
-
-
FDCAN2_RXFD_MODE,
SAI4_D1,SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
74/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
USART2_CK,
FT_
h
D6
A8
150
177 C11
PD7
I/O
-
-
SPDIFRX1_IN0,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
TRGOUT, LCD_G3,
LCD_B0, EVENTOUT
-
-
-
-
-
-
-
-
D11
E10
PJ12
PJ13
I/O FT
I/O FT
-
-
-
-
LCD_B4, LCD_B1,
EVENTOUT
-
-
-
-
-
-
-
D10
B10
-
PJ14
PJ15
VSS
VDD
I/O FT
I/O FT
-
-
-
-
LCD_B2, EVENTOUT
-
-
-
-
-
LCD_B3, EVENTOUT
B9
-
B9
-
151
152
178
S
S
-
-
-
-
179 VDD
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
QUADSPI_BK2_IO2,
SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
FT_
h
-
-
-
C7
D7
E7
153
154
155
180 A10
PG9
PG10
PG11
I/O
I/O
I/O
-
-
-
-
-
-
EVENTOUT
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
FT_
h
181
182
A9
B9
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
FT_
h
SDMMC2_D2,
ETH_MII_TX_EN/ETH_
RMII_TX_EN,DCMI_D3,
LCD_B3, EVENTOUT
DS12930 Rev 1
75/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6
_DE, SPDIFRX1_IN2,
LCD_B4,
FT_
h
-
G7
156
183
C9
PG12
I/O
-
-
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
USART6_CTS/USART6
_NSS,
FT_
h
-
F7
157
184
D9
PG13
I/O
-
-
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
LCD_R0, EVENTOUT
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
FT_
h
USART6_TX,
-
E6
158
185
186
D8
PG14
I/O
-
-
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
-
-
-
-
-
-
-
-
-
159
-
VSS
VDD
PK3
PK4
PK5
PK6
PK7
VDD
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
160
187 VDD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C8
B8
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
LCD_B4, EVENTOUT
LCD_B5, EVENTOUT
LCD_B6, EVENTOUT
LCD_B7, EVENTOUT
LCD_DE, EVENTOUT
-
-
-
A8
-
C7
-
D7
B7
VDD
USART6_CTS/USART6
_NSS, FMC_SDNCAS,
DCMI_D13, EVENTOUT
FT_
A7
C6
161
188
D6
PG15
I/O
h
-
-
76/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK,
PB3(JTDO/TR
ACESWO)
B7
A6
162
189
C6
I/O FT
-
-
SDMMC2_D2,
CRS_SYNC,
UART7_RX,
EVENTOUT
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO,
A8
B6
163
190
B7 PB4(NJTRST) I/O FT
-
-
SDMMC2_D3,
UART7_TX, EVENTOUT
TIM17_BKIN,
TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI,
B8
A5
164
191
A5
PB5
I/O FT
-
-
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
A9
-
-
-
VDD
VDD
S
-
-
-
-
DS12930 Rev 1
77/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL,
USART1_TX,
C7
E5
165
192
B5
PB6
I/O FT_f
-
LPUART1_TX,
FDCAN2_TX,
-
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1,
DCMI_D5, UART5_TX,
EVENTOUT
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5,
FMC_NL,
FT_f
C8
D7
C5
B5
D5
166
167
168
193
194
195
C5
E8
D5
PB7
BOOT0
PB8
I/O
a
-
-
-
PVD_IN
DCMI_VSYNC,
EVENTOUT
I
B
-
VPP
TIM16_CH1,TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
UART4_RX,
FT_f
h
A10
I/O
FDCAN1_RX,
SDMMC2_D4,
-
ETH_MII_TXD3,
SDMMC1_D4,
DCMI_D6, LCD_B6,
EVENTOUT
78/242
DS12930 Rev 1
STM32H747xI/G
Pin descriptions
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM17_CH1,TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
SDMMC1_CDIR,
UART4_TX,
FDCAN1_TX,
FT_f
h
C9
D6
169
196
D4
PB9
I/O
-
-
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5,
DCMI_D7, LCD_B7,
EVENTOUT
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
UART8_RX,
FDCAN1_RXFD_MODE,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
FT_
h
B10
D4
C4
170
171
197
198
C4
PE0
PE1
I/O
I/O
-
-
-
-
LPTIM1_IN2,
HRTIM_SCOUT,
UART8_TX,
FT_
h
D8
B4
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
A11
C10
E7
A4
-
172
173
174
175
-
199
200
201
202
-
A7
B6
VCAP
VSS
S
S
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B3
A3
-
E7
PDR_ON
VDDLDO
VDD
FT
-
A12
B11
A6
S
S
VDD
-
TIM8_BKIN,
SAI2_MCLK_A,
FT_
h
-
-
-
203
A4
PI4
I/O
-
TIM8_BKIN_COMP12,
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
-
DS12930 Rev 1
79/242
95
Pin descriptions
STM32H747xI/G
Table 7. STM32H747xI/G pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM8_CH1,
SAI2_SCK_A,
FMC_NBL3,
FT_
h
-
-
-
204
A3
A2
PI5
I/O
-
-
DCMI_VSYNC,
LCD_B5, EVENTOUT
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6,
LCD_B6, EVENTOUT
FT_
h
-
-
-
-
205
PI6
PI7
I/O
I/O
-
-
-
-
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7,
LCD_B7, EVENTOUT
FT_
h
-
-
206
207
B3
-
-
-
-
-
-
-
-
VSS
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B11
M13
A13
-
176
208 VDD
-
-
-
-
-
-
-
-
VSS
DNC
M15
VSSDSI
S
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
3. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
80/242
DS12930 Rev 1
Table 8. Port A alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/CE
C
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
USART2_
CTS/USAR UART4_TX
T2_NSS
TIM2_CH1/
TIM2_ETR
SDMMC2_
CMD
ETH_MII_
CRS
EVENT
OUT
PA0
-
-
TIM5_CH1
TIM5_CH2
TIM8_ETR
TIM15_BKIN
-
-
-
-
SAI2_SD_B
-
-
-
-
-
USART2_
ETH_MII_
RX_CLK/
ETH_RMII_
REF_CLK
LPTIM3_
OUT
TIM15_
CH1N
RTS/
QUADSPI_ SAI2_MCLK
BK1_IO3
EVENT
OUT
PA1
TIM2_CH2
UART4_RX
USART2_
LCD_R2
_B
DE
LPTIM4_
OUT
USART2_
TX
SAI2_SCK
_B
MDIOS_
MDIO
EVENT
OUT
PA2
PA3
PA4
PA5
PA6
TIM2_CH3
TIM2_CH4
-
TIM5_CH3
TIM5_CH4
TIM5_ETR
-
TIM15_CH1
-
-
-
-
-
-
ETH_MDIO
-
-
LCD_R1
LCD_B5
LPTIM5_
OUT
USART2_
RX
OTG_HS_
ULPI_D0
ETH_MII_
COL
EVENT
OUT
TIM15_CH2
-
LCD_B2
-
D1PWR
E
SPI1_NSS/ SPI3_NSS/ USART2_C
OTG_HS_
SOF
DCMI_HSY LCD_VSY EVENT
-
-
-
-
SPI6_NSS
SPI6_SCK
SPI6_MISO
-
-
-
-
-
I2S1_WS
I2S3_WS
K
NC
NC
OUT
D2PWR
E
TIM2_CH1/
TIM2_ETR
SPI1_SCK/
I2S1_CK
OTG_HS_
ULPI_CK
EVENT
OUT
TIM8_CH1N
TIM8_BKIN
-
-
-
-
LCD_R4
SPI1_MISO
/I2S1_SDI
TIM13_CH TIM8_BKIN
MDIOS_
MDC
TIM1_BKIN DCMI_PIXC
_COMP12
EVENT
OUT
-
-
TIM1_BKIN
TIM3_CH1
-
-
-
-
LCD_G2
-
1
_COMP12
LK
ETH_MII_R
X_DV/ETH_
RMII_CRS_
DV
SPI1_MOSI
/I2S1_SDO
TIM14_
CH1
FMC_
SDNWE
EVENT
OUT
PA7
TIM1_CH1N TIM3_CH2 TIM8_CH1N
HRTIM_
-
SPI6_MOSI
-
USART1_
CK
OTG_FS_
SOF
TIM8_BKIN
2_COMP12
EVENT
OUT
PA8
PA9
MCO1
-
TIM1_CH1
TIM8_BKIN2
I2C3_SCL
-
-
-
-
-
-
UART7_RX
LCD_B3
LCD_R6
LCD_R5
CHB2
FDCAN1_
RXFD_
MODE
HRTIM_
CHC1
LPUART1_
TX
SPI2_SCK/
I2S2_CK
USART1_
TX
ETH_TX_
ER
EVENT
OUT
TIM1_CH2
I2C3_SMBA
-
-
DCMI_D0
FDCAN1_
TXFD_
MODE
HRTIM_
CHC2
LPUART1_
RX
USART1_
RX
OTG_FS_
ID
MDIOS_
MDIO
EVENT
OUT
PA10
PA11
-
-
TIM1_CH3
TIM1_CH4
-
-
-
-
-
-
LCD_B4
DCMI_D1
LCD_B1
LCD_R4
USART1_
CTS/
USART1_
NSS
HRTIM_
CHD1
LPUART1_
CTS
SPI2_NSS/
I2S2_WS
FDCAN1_
RX
OTG_FS_
DM
EVENT
OUT
UART4_RX
-
-
-
-
-
LPUART1_
RTS/
LPUART1_
DE
USART1_
RTS/
USART1_
DE
HRTIM_
CHD2
SPI2_SCK/
I2S2_CK
FDCAN1_
TX
OTG_FS_
DP
EVENT
OUT
PA12
-
TIM1_ETR
-
UART4_TX
SAI2_FS_B
-
LCD_R5
Table 8. Port A alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/CE
C
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
JTMS/
SWDIO
EVENT
OUT
PA13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
JTCK/
SWCLK
EVENT
OUT
PA14
PA15
-
UART4_
TIM2_CH1/
TIM2_ETR
HRTIM_FL
T1
SPI1_NSS/ SPI3_NSS/
I2S1_WS I2S3_WS
EVENT
OUT
JTDI
-
CEC
SPI6_NSS RTS/UART
4_DE
-
-
UART7_TX
-
DSI_TE
-
Table 9. Port B alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
DFSDM1_C
KOUT
UART4_
CTS
OTG_HS_
ULPI_D1
ETH_MII_
RXD2
EVENT
OUT
PB0
-
-
TIM1_CH2N TIM3_CH3 TIM8_CH2N
TIM1_CH3N TIM3_CH4 TIM8_CH3N
-
-
-
-
-
-
-
LCD_R3
LCD_R6
-
-
-
-
-
-
LCD_G1
LCD_G0
-
DFSDM1_
DATIN1
OTG_HS_
ULPI_D2
ETH_MII_
RXD3
EVENT
OUT
PB1
PB2
-
RTC_
OUT
DFSDM1_
CKIN1
SPI3_MOSI SAI4_SD_ QUADSPI_
EVENT
OUT
-
SAI1_D1
-
-
SAI1_SD_A
SAI4_D1
-
/I2S3_SDO
A
CLK
JTDO/
HRTIM_
FLT4
SPI1_SCK/ SPI3_SCK/I
I2S1_CK 2S3_CK
SDMMC2_
D2
EVENT
OUT
PB3 TRACES
WO
TIM2_CH2
-
-
SPI6_SCK
CRS_SYNC UART7_RX
-
-
-
-
-
HRTIM_EEV
6
SPI1_MISO SPI3_MISO/ SPI2_NSS/
SDMMC2_
D3
EVENT
OUT
PB4
PB5
PB6
NJTRST TIM16_BKIN TIM3_CH1
-
SPI6_MISO
SPI6_MOSI
-
UART7_TX
-
/I2S1_SDI
I2S3_SDI
I2S2_WS
HRTIM_EEV
7
SPI1_MOSI
/I2S1_SDO
SPI3_MOSI
/I2S3_SDO
FDCAN2_ OTG_HS_U ETH_PPS_ FMC_SDCK
UART5_R EVENT
OUT
-
-
TIM17_BKIN TIM3_CH2
I2C1_SMBA
I2C1_SCL
I2C4_SMBA
DCMI_D10
DCMI_D5
RX
LPI_D7
OUT
E1
X
TIM16_CH1
TIM4_CH1
N
HRTIM_EEV
8
USART1_
TX
LPUART1_
TX
FDCAN2_
TX
QUADSPI_ DFSDM1_D FMC_SDNE
UART5_T EVENT
CEC
I2C4_SCL
I2C4_SDA
I2C4_SCL
BK1_NCS
-
ATIN5
1
X
OUT
FDCAN2_
TXFD_
MODE
TIM17_CH1
TIM4_CH2
N
HRTIM_EEV
9
USART1_
RX
LPUART1_
RX
DFSDM1_C
KIN5
DCMI_VSY
NC
EVENT
OUT
PB7
PB8
-
-
I2C1_SDA
I2C1_SCL
-
-
FMC_NL
-
DFSDM1_C
KIN7
SDMMC1_
CKIN
FDCAN1_
RX
SDMMC2_
D4
ETH_MII_
TXD3
SDMMC1_
D4
EVENT
OUT
TIM16_CH1 TIM4_CH3
UART4_RX
DCMI_D6
LCD_B6
Table 9. Port B alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
DFSDM1_
DATIN7
SPI2_NSS/
I2S2_WS
SDMMC1_
CDIR
FDCAN1_
TX
SDMMC2_
D5
SDMMC1_
D5
EVENT
OUT
PB9
-
-
TIM17_CH1 TIM4_CH4
I2C1_SDA
I2C2_SCL
I2C4_SDA
UART4_TX
-
I2C4_SMBA
DCMI_D7
-
LCD_B7
LCD_G4
HRTIM_SC
TIM2_CH3
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN7
USART3_
TX
QUADSPI_
BK1_NCS
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER
EVENT
OUT
PB10
PB11
LPTIM2_IN1
-
-
OUT
ETH_MII_
HRTIM_
TIM2_CH4
LPTIM2_
ETR
DFSDM1_
CKIN7
USART3_
RX
OTG_HS_ TX_EN/ETH
ULPI_D4
EVENT
OUT
-
-
-
I2C2_SDA
I2C2_SMBA
-
-
-
-
-
-
DSI_TE
LCD_G5
SCIN
_RMII_TX_
EN
ETH_MII_
TXD0/ETH_
RMII_TXD0
SPI2_NSS/
I2S2_WS
DFSDM1_
DATIN1
USART3_
CK
FDCAN2_ OTG_HS_U
RX
OTG_HS_
ID
TIM1_BKIN
_COMP12
UART5_
RX
EVENT
OUT
PB12
PB13
TIM1_BKIN
TIM1_CH1N
-
-
-
LPI_D5
USART3_
CTS/
USART3_N
SS
ETH_MII_
TXD1/ETH_
RMII_TXD1
LPTIM2_
OUT
SPI2_SCK/
I2S2_CK
DFSDM1_
CKIN1
FDCAN2_
TX
OTG_HS_
ULPI_D6
UART5_T EVENT
-
-
X
OUT
USART3_
RTS/
USART3_
DE
UART4_
RTS/
UART4_DE
SPI2_MISO DFSDM1_
/I2S2_SDI DATIN2
SDMMC2_
D0
OTG_HS_
DM
EVENT
OUT
PB14
PB15
-
TIM1_CH2N
TIM1_CH3N
-
-
TIM8_CH2N USART1_TX
TIM8_CH3N USART1_RX
-
-
-
-
-
-
RTC_RE
FIN
SPI2_MOSI DFSDM1_
/I2S2_SDO CKIN2
UART4_
CTS
SDMMC2_
D1
OTG_HS_
DP
EVENT
OUT
-
Table 10. Port C alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
DFSDM1_C
KIN0
DFSDM1_
DATIN4
OTG_HS_
ULPI_STP
FMC_SDN
WE
EVENT
OUT
PC0
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_FS_B
-
-
-
-
-
-
LCD_R5
TRACED
0
DFSDM1_
DATIN0
DFSDM1_
CKIN4
SPI2_MOSI
/I2S2_SDO
SAI4_SD_
A
SDMMC2_
CK
MDIOS_
MDC
EVENT
OUT
PC1
PC2
PC3
SAI1_D1
SAI1_SD_A
SAI4_D1
ETH_MDC
-
-
-
C1
DSLEEP
DFSDM1_
CKIN1
SPI2_MISO DFSDM1_
OTG_HS_
ULPI_DIR
ETH_MII_
TXD2
FMC_SDNE
0
EVENT
OUT
-
-
-
-
-
-
-
-
/I2S2_SDI
CKOUT
C1
SLEEP
DFSDM1_
DATIN1
SPI2_MOSI
/I2S2_SDO
OTG_HS_U
LPI_NXT
ETH_MII_
TX_CLK
FMC_SDCK
E0
EVENT
OUT
-
ETH_MII_
RXD0/ETH_
RMII_RXD0
C2
DSLEEP
DFSDM1_
CKIN2
SPDIFRX1
_IN3
FMC_SDNE
0
EVENT
OUT
PC4
PC5
-
-
-
-
-
I2S1_MCK
-
-
-
-
-
-
-
-
-
ETH_MII_
RXD1/ETH_
RMII_RXD1
COMP1_
OUT
C2
SLEEP
DFSDM1_
DATIN2
SPDIFRX1
_IN4
FMC_
SDCKE0
EVENT
OUT
SAI1_D3
-
SAI4_D3
HRTIM_CH
A1
DFSDM1_
CKIN3
USART6_
TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6
SDMMC1_
D6
LCD_
HSYNC
EVENT
OUT
PC6
PC7
-
TIM3_CH1
TIM3_CH2
TIM8_CH1
TIM8_CH2
I2S2_MCK
-
-
-
DCMI_D0
DCMI_D1
HRTIM_CH
A2
DFSDM1_
DATIN3
USART6_
RX
SDMMC1_
D123DIR
SDMMC2_
D7
SDMMC1_
D7
EVENT
OUT
TRGIO
I2S3_MCK
FMC_NE1
SWPMI_TX
LCD_G6
-
UART5_
RTS/
UART5_DE
TRACED HRTIM_CH
USART6_
CK
FMC_NE2/
FMC_NCE
SDMMC1_
D0
EVENT
OUT
PC8
TIM3_CH3
TIM3_CH4
TIM8_CH3
TIM8_CH4
-
-
-
-
-
SWPMI_RX
DCMI_D2
1
B1
UART5_
CTS
QUADSPI_
BK1_IO0
SWPMI_
SUSPEND
SDMMC1_
D1
EVENT
OUT
PC9
MCO2
-
-
-
-
-
-
-
I2C3_SDA
I2S_CKIN
-
LCD_G3
DCMI_D3
LCD_B2
HRTIM_EE
V1
DFSDM1_
CKIN5
SPI3_SCK/
I2S3_CK
USART3_
TX
QUADSPI_
BK1_IO1
SDMMC1_
D2
EVENT
OUT
PC10
PC11
PC12
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART4_TX
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D8
LCD_R2
HRTIM_FL
T2
DFSDM1_
DATIN5
SPI3_MISO/ USART3_
I2S3_SDI RX
QUADSPI_
BK2_NCS
SDMMC1_
D3
EVENT
OUT
UART4_RX
DCMI_D4
-
-
-
-
-
TRACED
3
HRTIM_EE
V2
SPI3_MOSI/ USART3_
SDMMC1_
CK
EVENT
OUT
-
-
-
-
UART5_TX
-
-
-
-
DCMI_D9
I2S3_SDO
CK
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
EVENT
OUT
Table 11. Port D alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SAI1/TIM3/ TIM8/LPTI
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
TIM1/2/16/
17/LPTIM1
/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/3/6/
UART7/
Port
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
4/5/HRTIM
1
M2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
HRTIM1
DFSDM1
SDMMC1
DFSDM1_
CKIN6
SAI3_SCK_
A
FDCAN1_
RX
FMC_D2/
FMC_DA2
EVENT
OUT
PD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART4_RX
UART4_TX
UART5_RX
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_
DATIN6
FDCAN1_
TX
FMC_D3/
FMC_DA3
EVENT
OUT
PD1
PD2
PD3
-
SAI3_SD_A
-
-
TRACE
D2
SDMMC1_
CMD
EVENT
OUT
TIM3_ETR
-
-
-
-
-
-
DCMI_D11
DCMI_D5
-
DFSDM1_
CKOUT
SPI2_SCK/
I2S2_CK
USART2_CTS/
USART2_NSS
EVENT
OUT
-
-
FMC_CLK
FMC_NOE
LCD_G7
FDCAN1_
RXFD_
MODE
HRTIM_
FLT3
USART2_RTS/
USART2_DE
EVENT
OUT
PD4
PD5
PD6
-
-
-
-
-
-
-
-
-
SAI3_FS_A
-
-
-
-
-
-
-
FDCAN1_
TXFD_
MODE
HRTIM_EE
V3
USART2_
TX
EVENT
OUT
-
-
-
FMC_NWE
-
-
FDCAN2_
RXFD_
MODE
DFSDM1_
CKIN4
DFSDM1_ SPI3_MOSI
DATIN1
USART2_
RX
SAI4_SD_
A
SDMMC2_
CK
FMC_
NWAIT
EVENT
OUT
SAI1_D1
SAI1_SD_A
SAI4_D1
DCMI_D10
LCD_B2
/I2S3_SDO
DFSDM1_
DATIN4
SPI1_MOSI DFSDM1_
USART2_
CK
SPDIFRX1
_IN1
SDMMC2_
CMD
EVENT
OUT
PD7
PD8
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NE1
-
-
-
-
/I2S1_SDO
-
CKIN1
DFSDM1_
CKIN3
SAI3_SCK_
B
USART3_
TX
SPDIFRX1
_IN2
FMC_D13/
FMC_DA13
EVENT
OUT
-
-
FDCAN2_
RXFD_
MODE
DFSDM1_
DATIN3
USART3_
RX
FMC_D14/F
MC_DA14
EVENT
OUT
PD9
-
-
-
-
-
-
-
-
-
SAI3_SD_B
SAI3_FS_B
-
-
-
-
-
-
-
FDCAN2_
TXFD_
MODE
DFSDM1_
CKOUT
USART3_
CK
FMC_D15/
FMC_DA15
EVENT
OUT
PD10
-
-
-
LCD_B3
LPTIM2_IN I2C4_SMB
USART3_CTS/
USART3_NSS
QUADSPI_
BK1_IO0
EVENT
OUT
PD11
PD12
PD13
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_SD_A
SAI2_FS_A
-
-
-
FMC_A16
FMC_A17
FMC_A18
-
-
-
-
-
-
2
A
LPTIM1_IN
1
LPTIM2_IN
1
USART3_RTS/
USART3_DE
QUADSPI_
BK1_IO1
EVENT
OUT
TIM4_CH1
TIM4_CH2
I2C4_SCL
LPTIM1_
OUT
QUADSPI_ SAI2_SCK_
BK1_IO3
EVENT
OUT
I2C4_SDA
A
Table 11. Port D alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SAI1/TIM3/ TIM8/LPTI
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
TIM1/2/16/
17/LPTIM1
/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/3/6/
UART7/
Port
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
4/5/HRTIM
1
M2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
HRTIM1
DFSDM1
SDMMC1
SAI3_MCLK
_B
UART8_
CTS
FMC_D0/
FMC_DA0
EVENT
OUT
PD14
-
-
TIM4_CH3
TIM4_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART8_
RTS/UART
8_DE
SAI3_MCLK
_A
FMC_D1/
FMC_DA1
EVENT
OUT
PD15
Table 12. Port E alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/ SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
17/LPTIM1 4/5/HRTIM
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
/HRTIM1
1
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
FDCAN1_
RXFD_
MODE
LPTIM1_
ETR
HRTIM_
SCIN
LPTIM2_
ETR
SAI2_MCLK
_A
EVENT
OUT
PE0
-
-
TIM4_ETR
-
-
-
-
-
-
-
UART8_RX
UART8_TX
-
-
FMC_NBL0
FMC_NBL1
DCMI_D2
DCMI_D3
-
-
FDCAN1_
TXFD_
MODE
LPTIM1_
IN2
HRTIM_SC
OUT
EVENT
OUT
PE1
-
-
TRACE
CLK
SAI1_MCLK
_A
SAI4_MCL QUADSPI_
ETH_MII_
TXD3
EVENT
OUT
PE2
PE3
PE4
PE5
PE6
PE7
PE8
-
-
-
-
SAI1_CK1
-
-
-
SPI4_SCK
-
-
SAI4_CK1
-
FMC_A23
FMC_A19
FMC_A20
FMC_A21
FMC_A22
-
-
K_A
BK1_IO2
TRACE
D0
SAI4_SD_
B
EVENT
OUT
-
TIM15_BKIN
SAI1_SD_B
-
-
-
-
-
-
-
TRACE
D1
DFSDM1_
DATIN3
TIM15_CH1
N
EVENT
OUT
SAI1_D2
SPI4_NSS SAI1_FS_A
SAI1_SCK_
-
SAI4_FS_A
-
SAI4_D2
SAI4_CK2
DCMI_D4
DCMI_D6
DCMI_D7
-
LCD_B0
TRACE
D2
DFSDM1_C
KIN3
SAI4_SCK
_A
EVENT
OUT
SAI1_CK2
TIM15_CH1 SPI4_MISO
-
-
LCD_G0
A
TRACE
D3
TIM1_
BKIN2
SAI4_SD_
A
SAI2_MCLK TIM1_BKIN
EVENT
OUT
SAI1_D1
-
TIM15_CH2 SPI4_MOSI SAI1_SD_A
-
SAI4_D1
LCD_G1
_B
2_COMP12
DFSDM1_D
ATIN2
QUADSPI_
BK2_IO0
FMC_D4/
FMC_DA4
EVENT
OUT
-
-
TIM1_ETR
-
-
-
-
-
-
-
-
UART7_RX
UART7_TX
-
-
-
-
-
-
-
TIM1_CH1
N
DFSDM1_C
KIN2
QUADSPI_
BK2_IO1
FMC_D5/
FMC_DA5
COMP2_
OUT
EVENT
OUT
-
-
UART7_
RTS/UART
7_DE
DFSDM1_C
KOUT
QUADSPI_
BK2_IO2
FMC_D6/
FMC_DA6
EVENT
OUT
PE9
-
TIM1_CH1
-
-
-
-
-
-
-
-
TIM1_CH2
N
DFSDM1_
DATIN4
UART7_
CTS
QUADSPI_
BK2_IO3
FMC_D7/
FMC_DA7
EVENT
OUT
PE10
PE11
PE12
PE13
PE14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_C
KIN4
FMC_D8/
FMC_DA8
EVENT
OUT
TIM1_CH2
SPI4_NSS
SPI4_SCK
SPI4_MISO
SPI4_MOSI
-
-
-
-
SAI2_SD_B
LCD_G3
LCD_B4
LCD_DE
LCD_CLK
TIM1_CH3
N
DFSDM1_
DATIN5
SAI2_SCK_
B
FMC_D9/F
MC_DA9
COMP1_
OUT
EVENT
OUT
DFSDM1_C
KIN5
FMC_D10/
FMC_DA10
COMP2_
OUT
EVENT
OUT
TIM1_CH3
TIM1_CH4
SAI2_FS_B
SAI2_MCLK
_B
FMC_D11/
FMC_DA11
EVENT
OUT
-
-
-
TIM1_BKIN
_COMP12/
TIM1_
BKIN
FMC_D12/
FMC_DA12 COMP_TIM
1_BKIN
EVENT
OUT
PE15
-
-
-
TIM1_BKIN
-
-
-
-
-
-
LCD_R7
Table 13. Port F alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/ SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
17/LPTIM1/ 4/5/HRTIM
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
HRTIM1
1
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
EVENT
OUT
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A0
FMC_A1
FMC_A2
FMC_A3
FMC_A4
FMC_A5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PF1
PF2
PF3
PF4
PF5
PF6
PF7
I2C2_SCL
EVENT
OUT
I2C2_SMBA
EVENT
OUT
-
-
-
-
-
EVENT
OUT
EVENT
OUT
TIM16_CH
1
SAI4_SD_ QUADSPI_
BK1_IO3
EVENT
OUT
SPI5_NSS SAI1_SD_B UART7_RX
SAI1_MCLK
B
TIM17_CH
1
SAI4_MCL QUADSPI_
K_B
EVENT
OUT
SPI5_SCK
UART7_TX
-
_B
BK1_IO2
UART7_
RTS/UART
7_DE
TIM16_
CH1N
SAI1_SCK_
B
SAI4_SCK
_B
TIM13_CH QUADSPI_
BK1_IO0
EVENT
OUT
PF8
-
-
-
-
SPI5_MISO
-
-
-
-
1
TIM17_
CH1N
UART7_
CTS
TIM14_CH QUADSPI_
EVENT
OUT
PF9
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI5_MOSI SAI1_FS_B
SAI4_FS_B
-
-
-
-
-
-
1
BK1_IO1
TIM16_
BKIN
QUADSPI_
CLK
EVENT
OUT
DCMI_D11
LCD_DE
PF10
PF11
PF12
PF13
PF14
PF15
SAI1_D3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI4_D3
FMC_SDNR
AS
EVENT
OUT
DCMI_D12
-
-
-
-
-
-
-
-
-
-
-
SPI5_MOSI
-
-
-
-
-
SAI2_SD_B
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
FMC_A7
FMC_A8
FMC_A9
-
-
-
-
DFSDM1_D
ATIN6
EVENT
OUT
I2C4_SMBA
I2C4_SCL
I2C4_SDA
DFSDM1_C
KIN6
EVENT
OUT
EVENT
OUT
-
Table 14. Port G alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
EVENT
OUT
PG0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
FMC_A11
FMC_A12
FMC_A13
-
-
-
-
-
-
EVENT
OUT
PG1
PG2
PG3
PG4
PG5
PG6
PG7
-
-
TIM8_BKIN
_COMP12
EVENT
OUT
TIM8_BKIN
-
TIM8_BKIN
2_COMP12
EVENT
OUT
TIM8_BKIN2
-
TIM1_BKIN
2
TIM1_BKIN
2_COMP12
FMC_A14/
FMC_BA0
EVENT
OUT
-
-
-
-
FMC_A15/
FMC_BA1
EVENT
OUT
TIM1_ETR
-
-
-
-
-
TIM17_
BKIN
HRTIM_CH
E1
QUADSPI_
BK1_NCS
EVENT
OUT
DCMI_D12
FMC_NE3
FMC_INT
LCD_R7
LCD_CLK
HRTIM_CH
E2
SAI1_MCLK USART6_
EVENT
OUT
DCMI_D13
-
-
-
_A
CK
USART6_
RTS/USAR
T6_DE
SPDIFRX1
_IN3
ETH_PPS_ FMC_SDCL
OUT
EVENT
OUT
PG8
-
-
-
-
-
TIM8_ETR
-
SPI6_NSS
-
-
LCD_G7
K
SPI1_MISO
/I2S1_SDI
USART6_
RX
SPDIFRX1 QUADSPI_
_IN4
FMC_NE2/F
MC_NCE
EVENT
OUT
DCMI_
PG9
-
-
-
-
-
-
-
-
SAI2_FS_B
SAI2_SD_B
-
-
-
BK2_IO2
VSYNC
HRTIM_
FLT5
SPI1_NSS/
I2S1_WS
EVENT
OUT
DCMI_D2
DCMI_D3
LCD_B2
PG10
-
-
-
LCD_G3
FMC_NE3
-
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
LPTIM1_IN
2
HRTIM_
EEV4
SPI1_SCK/
I2S1_CK
SPDIFRX1
_IN1
SDMMC2_
D2
EVENT
OUT
PG11
PG12
PG13
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
LCD_B1
LCD_R0
USART6_
RTS/
USART6_
DE
ETH_MII_T
XD1/ETH_R FMC_NE4
MII_TXD1
LPTIM1_IN
1
HRTIM_
EEV5
SPDIFRX1
_IN2
EVENT
OUT
SPI6_MISO
SPI6_SCK
LCD_B4
-
-
-
-
USART6_
CTS/
USART6_
NSS
ETH_MII_T
XD0/ETH_R
MII_TXD0
TRACE
D0
LPTIM1_
OUT
HRTIM_
EEV10
EVENT
OUT
-
-
FMC_A24
Table 14. Port G alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
ETH_MII_
TXD1/ETH_
RMII_TXD1
TRACE
D1
LPTIM1_
ETR
USART6_
TX
QUADSPI_
BK2_IO3
EVENT
OUT
PG14
-
-
-
-
-
-
SPI6_MOSI
-
-
-
-
-
-
FMC_A25
-
LCD_B0
USART6_
CTS/
USART6_
NSS
DCMI_D13
FMC_SDNC
AS
EVENT
OUT
PG15
-
-
-
-
-
-
Table 15. Port H alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
EVENT
OUT
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH1
PH2
PH3
PH4
PH5
PH6
PH7
-
-
-
-
-
QUADSPI_ SAI2_SCK_
BK2_IO0
ETH_MII_
CRS
FMC_SDCK
E0
EVENT
OUT
LPTIM1_IN2
-
-
-
LCD_R0
B
QUADSPI_ SAI2_MCLK
BK2_IO1
ETH_MII_
COL
FMC_SDNE
0
EVENT
OUT
-
-
-
-
-
-
-
-
LCD_R1
_B
OTG_HS_
ULPI_NXT
EVENT
OUT
I2C2_SCL
I2C2_SDA
I2C2_SMBA
I2C3_SCL
-
LCD_G5
-
-
-
LCD_G4
FMC_
SDNWE
EVENT
OUT
SPI5_NSS
SPI5_SCK
SPI5_MISO
-
-
-
-
-
-
-
-
-
-
ETH_MII_R FMC_SDNE
XD2
EVENT
OUT
DCMI_D8
DCMI_D9
1
ETH_MII_R FMC_SDCK
XD3
EVENT
OUT
E1
EVENT
OUT
DCMI_
PH8
-
-
TIM5_ETR
-
I2C3_SDA
-
-
-
-
-
-
-
FMC_D16
LCD_R2
HSYNC
EVENT
OUT
DCMI_D0
DCMI_D1
DCMI_D2
DCMI_D3
PH9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_SMBA
I2C4_SMBA
I2C4_SCL
I2C4_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D17
FMC_D18
FMC_D19
FMC_D20
FMC_D21
FMC_D22
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_G2
LCD_G3
EVENT
OUT
PH10
PH11
PH12
PH13
PH14
TIM5_CH1
-
-
EVENT
OUT
TIM5_CH2
-
-
EVENT
OUT
TIM5_CH3
-
-
FDCAN1_
TX
EVENT
OUT
-
-
TIM8_CH1N
TIM8_CH2N
UART4_TX
UART4_RX
-
FDCAN1_
RX
EVENT
OUT
DCMI_D4
-
FDCAN1_
TXFD_
MODE
DCMI_D11
EVENT
OUT
PH15
-
-
-
TIM8_CH3N
-
-
-
-
-
-
-
FMC_D23
LCD_G4
Table 16. Port I alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
FDCAN1_
RXFD_
MODE
DCMI_D13
SPI2_NSS/
I2S2_WS
EVENT
OUT
PI0
-
-
TIM5_CH4
-
-
-
-
-
-
-
FMC_D24
LCD_G5
SPI2_SCK/
I2S2_CK
TIM8_BKIN
2_COMP12
EVENT
OUT
DCMI_D8
DCMI_D9
DCMI_D10
DCMI_D5
PI1
PI2
PI3
PI4
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_BKIN2
TIM8_CH4
TIM8_ETR
TIM8_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D25
FMC_D26
FMC_D27
FMC_NBL2
LCD_G6
LCD_G7
-
SPI2_MISO
/I2S2_SDI
EVENT
OUT
-
-
SPI2_MOSI
/I2S2_SDO
EVENT
OUT
SAI2_MCLK TIM8_BKIN
EVENT
OUT
-
-
LCD_B4
_A
_COMP12
SAI2_SCK_
A
EVENT
OUT
DCMI_VSY
NC
PI5
-
-
-
TIM8_CH1
-
-
-
-
-
-
FMC_NBL3
LCD_B5
EVENT
OUT
DCMI_D6
DCMI_D7
PI6
PI7
PI8
PI9
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_SD_A
-
-
-
-
FMC_D28
FMC_D29
-
LCD_B6
LCD_B7
-
EVENT
OUT
TIM8_CH3
-
SAI2_FS_A
EVENT
OUT
-
-
-
-
-
-
-
FDCAN1_
RX
LCD_
VSYNC
EVENT
OUT
UART4_RX
FMC_D30
FDCAN1_
RXFD_
MODE
ETH_MII_
RX_ER
LCD_
HSYNC
EVENT
OUT
PI10
PI11
PI12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D31
-
-
-
OTG_HS_U
LPI_DIR
EVENT
OUT
LCD_G6
-
-
-
-
-
EVENT
OUT
-
-
LCD_HSY
NC
EVENT
OUT
PI13
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_VSY
NC
EVENT
OUT
PI14
PI15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CLK
LCD_R0
EVENT
OUT
LCD_G2
Table 17. Port J alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
EVENT
OUT
PJ0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R1
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_R7
LCD_G0
LCD_G1
LCD_G2
LCD_G3
LCD_G4
LCD_B0
LCD_B1
LCD_B2
LCD_B3
EVENT
OUT
PJ1
PJ2
-
-
-
-
-
-
-
EVENT
OUT
DSI_TE
-
-
-
-
-
-
EVENT
OUT
PJ3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PJ4
-
-
-
-
-
-
EVENT
OUT
PJ5
-
-
-
-
-
-
EVENT
OUT
PJ6
-
-
TIM8_CH2
-
-
-
EVENT
OUT
PJ7
TRGIN
-
TIM8_CH2N
-
-
-
EVENT
OUT
PJ8
-
-
-
-
TIM1_CH3N
TIM8_CH1
-
UART8_TX
-
EVENT
OUT
PJ9
TIM1_CH3
TIM8_CH1N
-
UART8_RX
-
EVENT
OUT
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
TIM1_CH2N
TIM8_CH2
SPI5_MOSI
-
-
-
-
-
-
-
EVENT
OUT
TIM1_CH2
TIM8_CH2N
SPI5_MISO
-
TRGOU
T
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G3
EVENT
OUT
-
-
-
LCD_B4
EVENT
OUT
-
-
EVENT
OUT
Table 18. Port K alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI4/FDCA
I2C4/UART
7/SWPMI1/ TIM1/8/FMC
I2C1/2/3/4/U
SART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM
8/QUADSPI
/SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
LPUART/
SPI6/SAI2/ N1/FDACN
4/UART4/5/ 2/TIM13/14
8/LPUART/ /QUADSPI/
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/ TIM8/LPTIM
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
/SDMMC1/ TIM1/DCMI/
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
SYS
7/LPTIM1/
HRTIM1
4/5/HRTIM
1
2/3/4/5/
HRTIM1/
DFSDM1
MDIOS/
OTG1_FS/
LCD
LCD/DSI/
COMP
SYS
SDMMC1/
SPDIFRX1
FMC/SDM
MC2/LCD/
SPDIFRX1
DFSDM1
EVENT
OUT
PK0
-
-
-
-
-
-
-
-
TIM1_CH1N
-
-
-
-
-
-
-
-
TIM8_CH3
-
-
-
-
-
-
-
-
SPI5_SCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G5
LCD_G6
LCD_G7
LCD_B4
LCD_B5
LCD_B6
LCD_B7
LCD_DE
EVENT
OUT
PK1
PK2
PK3
PK4
PK5
PK6
PK7
TIM1_CH1
TIM8_CH3N
SPI5_NSS
TIM8_BKIN TIM1_BKIN
_COMP12
EVENT
OUT
TIM1_BKIN
TIM8_BKIN
-
-
-
-
-
-
_COMP12
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
EVENT
OUT
EVENT
OUT
EVENT
OUT
Electrical characteristics
STM32H747xI/G
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at T = 25 °C and T = T (given by the
J
J
Jmax
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
J
DD
1.7 V ≤ V
tested.
≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
MCU pin
MCU pin
V
C =50 pF
IN
MS19011V2
MS19010V2
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6.1.6
Power supply scheme
Figure 13. Power supply scheme
VDD50USB
VDD50USB
VDD33USB
VDD33USB
USB
VSS
IOs
VDDSMPS
VLXSMPS
VFBSMPS
VSSSMPS
Step
DSI
PHY
USB
regulator
DSI
regulator
Down
Coverter
(SMPS)
VSS
VDDLDO
VCAP
Core domain (VCORE
)
Voltage
regulator
VDDLDO
VSS
D3 domain
(System
logic,
D1 domain
(CPU, peripherals,
RAM)
D2 domain
(peripherals,
RAM)
EXTI,
IO
logic
IOs
Peripherals,
RAM)
Flash
VDD
VSS
VDD domain
HSI, CSI,
VDD
HSI48,
HSE, PLLs
VBAT
charging
Backup domain
Backup
regulator
VBAT
1.2 to 3.6V
VSW
VBKP
VBAT
Power switch
Power switch
LSI, LSE,
RTC, Wakeup
logic, backup
registers,
Backup
RAM
BKUP
IOs
IO
logic
Reset
VREF
VDDA
VSS
VDDA
VSS
Analog domain
REF_BUF
ADC, DAC
VREF+
VREF-
OPAMP,
Comparator
VREF+
VREF-
VSSA
MSv62410V2
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
3. VCAPDSI pin must be externally connected to VDD12DSI pin.
Caution:
Each power supply pair (V /V , V
/V
...) must be decoupled with filtering ceramic
DD SS
DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
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Electrical characteristics
STM32H747xI/G
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7
Current consumption measurement
Figure 14. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics,
Table 20: Current characteristics, and Table 21: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
(1)
Table 19. Voltage characteristics
Symbols
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
VDDX - VSS
−0.3
4.0
V
VDDLDO, VDDSMPS, VDDA, VDD33USB, VBAT
)
Min(VDD, VDDA
,
Input voltage on FT_xxx pins
VSS−0.3
VDD33USB, VBAT
)
V
+4.0(3)(4)
(2)
VIN
Input voltage on TT_xx pins
Input voltage on BOOT0 pin
Input voltage on any other pins
V
V
SS-0.3
VSS
4.0
9.0
4.0
V
V
V
SS-0.3
Variations between different VDDX power pins
of the same domain
|ꢀVDDX
|
-
-
50
50
mV
mV
|VSSx-VSS
|
Variations between all the different ground pins
1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 70: I/O current injection susceptibility for the
maximum allowed injected current values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
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4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 20. Current characteristics
Ratings
Symbols
Max
Unit
ΣIVDD
ΣIVSS
IVDD
IVSS
IIO
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
620
620
100
100
20
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
140
140
mA
ΣI(PIN)
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
(3)(4)
IINJ(PIN)
Injected current on PA4, PA5
−0/0
ΣIINJ(PIN)
Total injected current (sum of all I/Os and control pins)(5)
±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 19: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 21. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
− 65 to +150
°C
Maximum junction temperature
125
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STM32H747xI/G
6.3
Operating conditions
6.3.1
General operating conditions
Table 22. General operating conditions
Operating
conditions
Symbol
VDD
Parameter
Min
Typ
Max
Unit
V
-
Standard operating voltage
-
1.62(1)
1.62(1)
1.2(2)
3.6
3.6
3.6
-
-
Supply voltage for the internal
regulator
VDDLDO
VDDLDO ≤ VDD
V
Supply voltage for the internal SMPS
Step-down converter
VDDSMPS
VDDSMPS = VDD
1.62(1)
-
3.6
V
USB used
3.0
0
-
-
-
-
-
-
3.6
3.6
Standard operating voltage, USB
domain
VDD33USB
USB not used
ADC or COMP used
DAC used
1.62
1.8
2.0
1.8
OPAMP used
VREFBUF used
VDDA
Analog operating voltage
3.6
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
V
0
-
TT_xx I/O
BOOT0
−0.3
-
-
VDD+0.3
9
0
VIN
I/O Input voltage
Min(VDD, VDDA
,
All I/O except BOOT0
and TT_xx
VDD33USB
+3.6V <
)
−0.3
-
5.5V(3)(4)
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Symbol
Electrical characteristics
Table 22. General operating conditions (continued)
Operating
conditions
Parameter
Min
Typ
Max
Unit
VOS3 (max frequency
200 MHz)
0.95
1.05
1.15
1.26
0.95
1.05
1.15
0.98
1.08
1.17
1.37
1.0
1.26
1.26
1.26
1.40
1.26
1.26
1.26
1.26
1.26
1.26
1.40
VOS2 (max frequency
300 MHz)
1.10
1.20
1.35
1.0
Internal regulator ON (LDO)
VOS1 (max frequency
400 MHz)
VOS0(5) (max
frequency 480 MHz(6)
)
VOS3 (max frequency
200 MHz)
Internal regulator ON (SMPS step-
down converter)(7)
VOS2 (max frequency
300 MHz)
VCORE
1.10
1.20
1.03
1.13
1.23
1.38
V
VOS1 (max frequency
400 MHz)
VOS3 (max frequency
200 MHz)
VOS2 (max frequency
300 MHz)
Regulator OFF: external VCORE
voltage must be supplied from external
regulator on two VCAP pins
VOS1 (max frequency
400 MHz)
VOS0 (max frequency
480 MHz(6)
)
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Electrical characteristics
STM32H747xI/G
Table 22. General operating conditions (continued)
Operating
conditions
Symbol
Parameter
Min
Typ
Max
Unit
VOS3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
300
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
fCPU1
Arm® Cortex®-M7 clock frequency
400
480(6)
200
150
fCPU2
fACLK
fHCLK
fPCLK
Arm® Cortex®-M4 clock frequency
200
240(6)
100
150
AXI clock frequency
MHz
200
240(6)
100
150
AHB clock frequency
200
240(6)
50(8)
75
APB clock frequency
100
120(6)
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. Only for power-up sequence when the SMPS step-down converter is configured to supply the LDO and TJMax = 105 °C.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
4. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
5. VOS0 is available only when the LDO regulator is ON.
6. TJmax = 105 °C.
7. At startup, the external VCORE voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO).
8. Maximum APB clock frequency when at least one peripheral is enabled.
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Table 23. Supply voltage and maximum frequency configuration
Power scale
VCORE source
Max TJ (°C) Max frequency (MHz)
Min VDD (V)
LDO
105
-
480
-
1.7
VOS0
VOS1
VOS2
SMPS step-down
converter(1)
-
LDO
125
400
1.62
SMPS step-down
converter
LDO
125
125
300
64
1.62
1.2(2)
1.62
SMPS step-down
converter
LDO(2)
105
125
LDO
VOS3
200
SMPS step-down
converter
125
105
125
105
125
LDO
SVOS4
SVOS5
N/A
N/A
1.62
1.62
SMPS step-down
converter
LDO
SMPS step-down
converter
1. VOS0 (power scale 0) is not available when the SMPS step-down converter directly supplies VCORE
2. Only for power-up sequence when the SMPS step-down converter supplies the LDO.
.
6.3.2
VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
to
EXT
the VCAP pin. C
VCAP pins.
is specified in Table 24. Two external capacitors can be connected to
EXT
Figure 15. External capacitor C
EXT
C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
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221
Electrical characteristics
Symbol
STM32H747xI/G
(1)
Table 24. VCAP operating conditions
Parameter
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF(2)
< 100 mΩ
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
6.3.3
SMPS step-down converter
The devices embed a high power efficiency SMPS step-down converter. SMPS
characteristics for external usage are given in Table 26. The SMPS step-down converter
requires external components that are specified in Figure 16 and Table 25.
Figure 16. External components for SMPS step-down converter
VDDSMPS
VDDSMPS
VDDSMPS
VDDSMPS
VDD
VDD
VDD
VDD
L
VLXSMPS
VLXSMPS
L
VLXSMPS
VLXSMPS
Cin
Cin
SMPS
SMPS
SMPS
SMPS
Cfilt
Cfilt
VFBSMPS
VFBSMPS
VFBSMPS
VFBSMPS
(ON)
(ON)
(ON)
(ON)
VDD_
VDD
External
External
Cout1
2xCout
VSSSMPS
VSSSMPS
VSSSMPS
VSSSMPS
VCAP
VCAP
VCAP
VCAP
VDDLDO
VDDLDO
VDDLDO
VDDLDO
VCORE
VCORE
VCORE
VCORE
V reg
V reg
V reg
V reg
Cout2
CEXT
(OFF)
(OFF)
(ON)
(ON)
VSS
VSS
VSS
VSS
External SMPS supply, LDO supplied
by SMPS
Direct SMPS supply
MSv61398V2
Table 25. Characteristics of SMPS step-down converter external components
Symbol
Parameter
Conditions
Capacitance of external capacitor on VDDSMPS
ESR of external capacitor
4.7 µF
100 mΩ
220 pF
10 µF
Cin
Cfilt
Capacitance of external capacitor on VLXSMPS pin
Capacitance of external capacitor on VFBSMPS pin
ESR of external capacitor
COUT
20 mΩ
2.2 µH
150 mΩ
L
-
Inductance of external Inductor on VLXSMPS pin
Serial DC resistor
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Electrical characteristics
Table 25. Characteristics of SMPS step-down converter external components
Symbol
Parameter
Conditions
DC current at which the inductance drops 30% from
its value without current.
ISAT
1.7 A
Average current for a 40 °C rise: rated current for
which the temperature of the inductor is raised 40°C
by DC current
IRMS
1.4 A
Table 26. SMPS step-down converter characteristics for external usage
Parameters
Conditions
Min
Typ
Max
Unit
VOUT = 1.8 V
VOUT = 2.5 V
2.3
-
3.6
3.6
(1)
VDDSMPS
V
3
-
2.5
1.8
-
2.25
2.75
1.98
600
600
120
-
(2)
VOUT
Iout=600 mA
V
1.62
internal and external usage
External usage only(3)
-
-
-
-
-
-
-
IOUT
mA
-
RDSON
100
220
-
mꢁ
IDDSMPS_Q
Quiescent current
VOUT = 1.8 V
µA
225
300
TSMPS_START
µs
VOUT = 2.5 V
-
1. The switching frequency is 2.4 MHz±10%
2. Including line transient and load transient.
3. These characteristics are given for SDEXTHP bit is set in the PWR_CR3 register.
6.3.4
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 27. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
Min
Max
Unit
0
10
0
∞
∞
∞
∞
∞
∞
tVDD
VDD fall time rate
VDDA rise time rate
tVDDA
µs/V
VDDA fall time rate
10
0
VDDUSB rise time rate
VDDUSB fall time rate
tVDDUSB
10
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Electrical characteristics
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6.3.5
Embedded reset and power control block characteristics
The parameters given in Table 28 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions.
Table 28. Reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset temporization
after BOR0 released
(1)
tRSTTEMPO
-
-
377
-
µs
Rising edge(1)
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge in Run mode
1.62
1.58
2.04
1.95
2.34
2.25
2.63
2.54
1.90
1.81
2.05
1.96
2.19
2.10
2.35
2.25
2.49
2.39
2.64
2.55
2.78
2.69
1.67
1.62
2.10
2.00
2.41
2.31
2.70
2.61
1.96
1.86
2.10
2.01
2.26
2.15
2.41
2.31
2.56
2.45
2.71
2.61
2.86
2.76
1.71
1.68
2.15
2.06
2.47
2.37
2.78
2.68
2.01
1.91
2.16
2.06
2.32
2.21
2.47
2.37
2.62
2.51
2.78
2.68
2.94
2.83
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
VBOR1
VBOR2
VBOR3
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Programmable Voltage
Detector threshold 0
Programmable Voltage
Detector threshold 1
V
Programmable Voltage
Detector threshold 2
Programmable Voltage
Detector threshold 3
Programmable Voltage
Detector threshold 4
Programmable Voltage
Detector threshold 5
Programmable Voltage
Detector threshold 6
Hysteresis voltage of BOR
(unless BOR0) and PVD
Vhyst_BOR_PVD
Hysteresis in Run mode
-
-
-
100
-
mV
µA
BOR(2) (unless BOR0) and
PVD consumption from VDD
(1)
IDD_BOR_PVD
0.630
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Electrical characteristics
Table 28. Reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.66
1.56
2.06
1.96
2.42
2.35
2.74
2.64
1.71
1.61
2.12
2.02
2.50
2.42
2.83
2.72
1.76
1.66
2.19
2.08
2.58
2.49
2.91
2.80
Analog voltage detector for
VDDA threshold 0
VAVM_0
Analog voltage detector for
VDDA threshold 1
VAVM_1
VAVM_2
VAVM_3
V
Analog voltage detector for
VDDA threshold 2
Analog voltage detector for
VDDA threshold 3
Hysteresis of VDDA voltage
detector
Vhyst_VDDA
IDD_PVM
-
-
-
-
100
-
mV
µA
µA
PVM consumption from
VDD(1)
-
-
-
0.25
2.5
Voltage detector
consumption on VDDA
IDD_VDDA
Resistor bridge
(1)
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 6.3.7: Supply current characteristics).
6.3.6
Embedded reference voltage
The parameters given in Table 29 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions.
Table 29. Embedded reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
-40°C < TJ < 125 °C,
VDD = 3.3 V
Internal reference voltages
1.180
1.216
1.255
V
ADC sampling time when
reading the internal reference
voltage
(1)(2)
tS_vrefint
-
-
4.3
-
-
µs
VBAT sampling time when
reading the internal VBAT
reference voltage
(1)(2)
tS_vbat
9
9
-
-
13.5
5
-
Reference Buffer
consumption for ADC
(2)
Irefbuf
V
DDA=3.3 V
23
15
µA
Internal reference voltage
spread over the temperature
range
(2)
(2)
ΔVREFINT
-40°C < TJ < 125 °C
mV
Average temperature
coefficient
Average temperature
coefficient
(2)
Tcoeff
-
-
20
10
70
ppm/°C
ppm/V
VDDcoeff
Average Voltage coefficient
3.0V < VDD < 3.6V
1370
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Electrical characteristics
STM32H747xI/G
Table 29. Embedded reference voltage (continued)
Symbol
Parameter
Conditions
Min
Typ
25
Max
Unit
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
-
-
-
-
-
-
-
-
-
%
50
VREFINT
75
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
Table 30. Internal reference voltage calibration values
Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
Symbol
6.3.7
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode.
All peripherals are disabled except when explicitly mentioned.
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (f
) frequency and V
range” available in the reference manual).
rcc_c_ck
CORE
•
When the peripherals are enabled, the AHB clock frequency is the CPU1 frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in the below tables are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22: General operating
conditions.
108/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4
(1)(2)
(ART accelerator ON), LDO regulator ON
Arm
Arm
Max(3)
Cortex- Cortex-
Symbol Parameter
Conditions
M7
fCPU1
(MHz)
M4
fCPU2
(MHz)
Typ
Unit
Tj=
Tj=
Tj=
Tj=
25 °C 85 °C 105°C 125°C
480
400
400
300
200
480
400
400
300
200
240
200
200
150
100
240
200
200
150
100
179
151
132
91
272
-
387
-
498
-
VOS0
All
peripherals VOS1
181
122
79
292
211
150
462
-
382
281
206
571
-
502
377
284
disabled
VOS2
Supply
current in
Run mode
VOS3
VOS0
56
IDD
mA
247
208
181
126
78
374
-
All
peripherals VOS1
232
163
104
337
248
173
422
318
229
541
414
307
enabled
VOS2
VOS3
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. The grayed cells correspond to the forbidden configurations.
3. Guaranteed by characterization results, unless otherwise specified.
Table 32. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4,
(1)
ART accelerator ON, SMPS regulator
Arm
Cortex-
M4
Max
Arm
Cortex-
M7
fCPU1
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=
Tj=
Tj=
Tj=
fCPU2
(MHz)
25 °C 85 °C 105°C 125°C
VOS1
400
300
200
400
300
200
200
150
100
200
150
100
58.3 79.0 129.0 175.1 236.0
All
peripherals
disabled
VOS2
VOS3
VOS1
VOS2
VOS3
37.0 50.2
21.5 29.9
84.7 115.6 161.1
56.1 77.1 107.6
Supply
IDD
current in
mA
78.1 100.1 148.9 193.4 254.3
51.2 65.5 100.8 130.9 176.9
Run mode
All
peripherals
enabled
29.5 39.4
63.9
86.7 116.3
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
DS12930 Rev 1
109/242
221
Electrical characteristics
STM32H747xI/G
Table 33. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache ON,
(1)
ART accelerator ON, LDO regulator ON
Arm
Arm
Max(2)
Cortex Cortex-
Symbol Parameter
Conditions
-M7
fCPU1
(MHz)
M4
fCPU2
(MHz)
Typ
Unit
Tj=
Tj=
Tj=
Tj=
25 °C 85 °C 105°C 125°C
480
400
400
300
200
480
400
300
200
240
200
200
150
100
240
200
150
100
173
147
128
88
268
-
385
-
496
-
VOS0
All
peripherals VOS1
175
120
77
288
209
149
459
334
246
172
379
279
205
569
419(3)
316
228
499
374
283
disabled
VOS2
Supply
current in
Run mode
IDD
VOS3
VOS0
55
mA
242
178
123
77
368
229(3)
161
102
All
VOS1
537
412
306
peripherals
enabled
VOS2
VOS3
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
3. Guaranteed by tests in production.
Table 34. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache OFF,
(1)
ART accelerator OFF, LDO regulator ON
Arm
Arm
Max(2)
Cortex- Cortex-
Symbol Parameter
Conditions
M7
fCPU1
(MHz) (MHz)
M4
fCPU2
Typ
Unit
Tj=
Tj=
Tj=
Tj=
25 °C 85 °C 105°C 125°C
VOS0
480
400
300
200
480
400
300
200
240
200
150
100
240
200
150
100
109
96
191
149
95
330
256
187
136
403
310
224
159
444
347
257
192
517
401
295
215
All
VOS1
VOS2
VOS3
VOS0
VOS1
VOS2
VOS3
468
354
270
peripherals
disabled
67
Supply
43
62
IDD
current in
mA
178
147
103
64
291
224
136
87
Run mode
All
523
392
293
peripherals
enabled
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
110/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
Table 35. Typical and maximum current consumption in Run mode, code with data processing
(1)(2)
running from ITCM, only Arm Cortex-M7 running, LDO regulator ON
Max(3)
fCPU1
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85
°C
Tj=105 Tj=125
°C
°C
480
400
400
300
300
216
200
200
180
168
144
60
148
125
110
84
226
-
307
-
390
-
VOS0
168
-
230
-
296
-
384
-
VOS1
VOS2
76
114
88
-
170
152
-
224
205
-
297
278
-
56
All
peripherals
disabled
53
47
71
64
63
55
36
24
222
-
121
116
115
109
92
83
439
-
164
159
158
153
135
126
550
-
223
218
217
212
194
185
43
Supply
current in
Run mode
40
IDD
VOS3
mA
35
16
25
12
480
400
400
300
300
200
200
226
190
167
135
122
85
VOS0
VOS1
222
-
327
-
416
-
536
-
All
peripherals
enabled
160
-
248
-
320
-
419
-
VOS2
VOS3
76
103
174
233
313
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. The grayed cells correspond to the forbidden configurations.
3. Guaranteed by characterization results, unless otherwise specified.
DS12930 Rev 1
111/242
221
Electrical characteristics
STM32H747xI/G
Table 36. Typical and maximum current consumption in Run mode, code with data processing
(1)
running from ITCM, only Arm Cortex-M7 running, SMPS regulator
Max
fCPU1
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
Tj=25 Tj=85 Tj=105 Tj=125
°C
°C
°C
°C
VOS1
400
300
200
400
300
200
48.6
31.3
18.0
72.9
49.6
28.8
73.3
46.3
26.9
95.8
64.3
38.5
100.4 132.4
176.0
122.2
82.4
All
peripherals VOS2
68.3
45.3
90.0
60.6
disabled
Supply
current in
Run mode
VOS3
IDD
mA
VOS1
All
peripherals VOS2
144.5 190.7
252.0
179.1
118.6
99.6
64.3
131.7
88.3
enabled
VOS3
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
Table 37. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache ON,
(1)
LDO regulator ON
Max(2)
Tj=85 Tj=105 Tj=125
fCPU1
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25
°C
°C
°C
°C
480
400
400
300
216
200
200
480
400
400
300
300
200
200
110
91
222
-
304
-
388
-
VOS0
80
162
-
228
-
294
-
381
-
All
VOS1
peripherals
disabled
61.5
55
111
-
168
-
222
-
294
-
VOS2
VOS3
VOS0
38.5
34.5
220
195
175
135
120
83
Supply
current in
Run mode
69
342
-
120
436
-
163
546
-
222
IDD
mA
264
-
336
-
424
-
544
-
All
VOS1
peripherals
enabled
180
-
246
-
318
-
418
-
VOS2
VOS3
75
114
173
232
312
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
112/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
Table 38. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache OFF,
(1)
LDO regulator ON
Max(2)
Tj=105 Tj=125
fCPU1
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25°C Tj=85°C
°C
°C
VOS0
480
400
300
200
480
400
300
200
87
73
157
123
85
259
201
150
109
390
308
228
167
342
267
204
152
504
397
301
226
All
VOS1
VOS2
VOS3
VOS0
VOS1
VOS2
VOS3
355
277
212
peripherals
disabled
52
Supply
34
54
IDD
current in
mA
168
135
100
70
276
224
154
103
Run mode
All
519
401
307
peripherals
enabled
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
Table 39. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON
Max(1)
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=105 Tj=125
Tj=25°C Tj=85°C
°C
°C
D1
Standby,
D2
Standby,
D3 Run
64
2.7
1.1
4.7
-
12.9
-
19.0
27.5
Supply
current in
VOS3
8
-
-
IDD
batch
acquisition
mode
mA
D1 Stop,
D2 Stop, VOS3
D3 Run
64
8
5.4
3.8
18.4
-
83.7
-
132.6
-
202.4
-
1. Guaranteed by characterization results, unless otherwise specified.
DS12930 Rev 1
113/242
221
Electrical characteristics
STM32H747xI/G
Table 40. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,
(1)
LDO regulator ON
Max(2)
fCPU2
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85
°C
Tj=105 Tj=125
°C
°C
240
200
200
150
150
100
240
200
200
150
100
121
90
203
-
339
-
453
-
VOS0
All
79
123
-
234
-
323
-
444
-
peripherals
disabled
VOS1
61
VOS2
VOS3
56
85
59
303
-
178
131
412
-
250
189
525
-
350
269
Supply
current in
Run mode
IDD
35
mA
190
146
129
90
VOS0
All
peripherals
enabled
VOS1
VOS2
VOS3
195
134
100
287
214
158
376
287
216
499
386
297
61
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
Table 41. Typical and maximum current consumption in Run mode, code with data processing
running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,
(1)
SMPS regulator
Max
Symbol
Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85
°C
Tj=105
°C
Tj=125
°C
VOS1
35.3
23.3
13.6
57.0
36.6
23.1
54.3
35.0
22.3
84.1
54.5
37.4
102.1
70.6
49.0
126.8
84.9
58.4
144.4
99.2
203.5
145.8
101.9
234.6
165.0
112.5
All
peripherals
disabled
VOS2
VOS3
VOS1
VOS2
VOS3
Supply
current in Run
mode
69.8
IDD
mA
172.3
118.1
79.8
All
peripherals
enabled
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
114/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
(1)
Table 42. Typical and maximum current consumption in Stop, LDO regulator ON
Max(2)
Symbol
Parameter
Conditions
Typ
Unit
Tj=105
°C
Tj=125
°C
Tj=25°C Tj=85°C
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
1.27
1.96
2.78
1.27
2.25
3.07
0.91
1.42
2.02
0.91
1.70
2.31
0.49
0.76
1.10
0.15
0.22
0.35
6.3
9.4
42.5
57.4
75.9
42.5
57.9
76.4
30.4
41.1
54.4
30.4
41.5
54.9
16.5
22.2
29.3
4.3
72.0
94.6
Flash
memory
OFF, no
IWDG
13.8(3)
121.3(3)
183.8
184.8
130.0
130.8
71.2
D1 Stop,
D2 Stop,
D3 Stop
6.3
72.0
Flash
memory
ON, no
IWDG
9.8
95.2
14.1
4.6
122.0
51.2
Flash
memory
OFF, no
IWDG
6.8
67.3
D1 Stop,
IDD (Stop) D2 Standby,
D3 Stop
10.0
4.6
86.6
mA
51.2
Flash
memory
ON, no
IWDG
7.2
67.9
10.3
2.4
87.1
28.0
D1 Standby,
D2 Stop,
D3 Stop
3.6
36.6
Flash
memory
OFF, no
IWDG
5.3
46.9
0.7(3)
7.3(3)
D1 Standby,
D2 Standby,
D3 Stop
1.0
5.8
9.6
1.5(3)
7.8
12.3(3)
18.6
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
2. Guaranteed by characterization results, unless otherwise specified.
3. Guaranteed by tests in production.
DS12930 Rev 1
115/242
221
Electrical characteristics
STM32H747xI/G
(1)
Table 43. Typical and maximum current consumption in Stop, SMPS regulator
Max
Symbol
Parameter
Conditions
Typ
Unit
mA
µA
Tj=105
°C
Tj=125
°C
Tj=25°C
Tj=85°C
SVOS5
0.36
0.63
1.00
0.36
0.73
1.11
0.25
0.46
0.73
0.25
0.55
0.83
0.15
0.26
0.40
0.06
0.08
0.13
1.73
3.05
4.98
1.73
3.18
5.09
1.24
2.21
3.57
1.24
2.34
3.67
0.67
1.17
1.90
0.20
0.33
0.54
11.91
19.57
29.11
11.91
19.74
29.31
8.21
21.53
33.51
47.13
21.53
33.72
47.40
14.00
22.94
32.80
14.00
23.15
32.99
7.85
-
Flash
OFF, no
IWDG
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
-
D1 Stop,
D2 Stop,
D3 Stop
68.76
-
Flash
ON, no
IWDG
-
69.14
-
Flash
OFF, no
IWDG
14.01
19.62
8.21
-
D1 Stop,
49.24
IDD (Stop) D2 Standby,
D3 Stop
-
Flash
ON, no
IWDG
14.15
19.81
4.51
-
49.55
-
D1 Standby,
D2 Stop,
D3 Stop
Flash
OFF, no
IWDG
7.21
12.32
17.12
2.05
-
10.57
1.18
26.97
-
-
D1 Standby,
D2 Standby,
D3 Stop
Flash
ON, no
IWDG
1.90
3.11
2.80
4.47
6.77
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
116/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
(1)
Table 44. Typical and maximum current consumption in Sleep mode, LDO regulator
Max(2)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85 Tj=105 Tj=125
°C
°C
°C
480
400
400
300
300
200
200
480
400
400
300
300
200
200
50.7
43.4
35.3
27.9
24.6
18.8
16.5
136.0
115.0
97.7
74.9
67.3
52.8
47.1
96.3
87.8
66.5
-
253.4
245.5
181.3
-
366.1
357.9
265.8
-
VOS0
379.6
All
VOS1
peripherals
disabled
-
47.3
-
139.1
-
207.3
-
300.4
-
VOS2
VOS3
VOS0
Supply
current in
Sleep mode
33.6
194.7
169.0
138.2
-
106.4
348.5
325.9
251.3
-
160.9
464.4
441.7
338.4
-
236.1
IDD (Sleep)
mA
456.4
All
VOS1
peripherals
enabled
-
95.8
-
187.6
-
257.9
-
354.1
-
VOS2
VOS3
69.3
141.4
197.7
275.1
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
2. Guaranteed by characterization results, unless otherwise specified.
(1)
Table 45. Typical and maximum current consumption in Sleep mode, SMPS regulator
Max
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85
°C
Tj=105 Tj=125
°C °C
400
300
300
200
200
400
300
200
15.93
12.58
10.21
7.89
29.69
-
79.01
-
118.72 173.80
VOS1
-
-
All
peripherals
disabled
19.63
-
56.46
-
82.14
-
123.46
-
VOS2
Supply
current in
Sleep mode
IDD (Sleep)
mA
VOS3
VOS1
6.50
12.98
59.62
38.94
26.14
39.73
59.35
87.10
42.65
27.70
17.95
110.88 153.00 211.65
All
peripherals VOS2
75.26
52.75
102.22 147.38
72.95 104.09
Enabled
VOS3
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
DS12930 Rev 1
117/242
221
Electrical characteristics
STM32H747xI/G
Table 46. Typical and maximum current consumption in Standby
Typ
Max(1)
Conditions
3 V
Symbol
Parameter
Unit
RTC
and
LSE
1.62 V 2.4 V 3 V 3.3 V
Backup
SRAM
Tj=25 Tj=85 Tj=105 Tj=125
°C
°C
°C
°C
OFF
ON
OFF
OFF
ON
1,92
3,33
2,43
3,82
1,95 2,06 2,16
4
18
47
-
40
83
-
90
Supply
current in
Standby
mode
3,44 3,6 3,79 8.2
141
IDD
µA
(Standby)
OFF
ON
2,57 2,77 2,95
4,05 4,31 4,55
-
-
-
-
ON
-
-
1. Guaranteed by characterization results, unless otherwise specified.
Table 47. Typical and maximum current consumption in V
mode
BAT
Conditions
Typ
Max(1)
3 V
Tj=25 Tj=85 Tj=105 Tj=125
RTC
Symbol Parameter
Unit
Backup
SRAM
and 1.2 V 2 V
LSE
3 V 3.4 V
°C
°C
°C
°C
OFF
ON
OFF 0,02 0,02 0,03 0,05
OFF 1,33 1,45 1,58 1,7
0,46 0,57 0,75 0,87
1,77 2,3 2,5
0,5
4,4
-
4,1
22
-
10
48
-
24
87
-
Supply
IDD
current in
µA
(VBAT)
OFF
ON
ON
ON
VBAT mode
2
-
-
-
-
1. Guaranteed by characterization results, unless otherwise specified.
118/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
Typical SMPS efficiency versus load current and temperature
Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at T = 30 °C
J
100
90
80
70
VDDSMPS =
1.8V, VOS1
60
VDDSMPS =
3.3V, VOS1
VDDSMPS =
1.8V, VOS2
50
VDDSMPS =
3.3V, VOS2
40
VDDSMPS =
1.8V, VOS3
VDDSMPS =
3.3V, VOS3
30
20
10
0
0.001
0.01
0.1
1
MSv62424V1
Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at T = T
J
Jmax
100
90
80
70
VDDSMPS =
1.8V, VOS1
VDDSMPS =
3.3V, VOS1
VDDSMPS =
1.8V, VOS2
VDDSMPS =
3.3V, VOS2
VDDSMPS =
1.8V, VOS3
VDDSMPS =
3.3V, VOS3
60
50
40
30
20
10
0
0.001
0.01
0.1
1
MSv62425V1
DS12930 Rev 1
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221
Electrical characteristics
STM32H747xI/G
Figure 19. Typical SMPS efficiency (%) vs load current (A) in low-power mode at
T = 30 °C
J
°
100
90
80
70
60
50
40
30
20
10
0
VDDSMPS =
1.8V, SVOS5
VDDSMPS =
3.3V, SVOS5
VDDSMPS =
1.8V, SVOS4
VDDSMPS =
3.3V, SVOS4
VDDSMPS =
1.8V, SVOS3
VDDSMPS =
3.3V, SVOS3
0.00001
0.0001
0.001
0.01
0.1
MSv62426V1
120/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at
T = T
J
Jmax
100
90
80
70
60
50
40
30
20
10
0
VDDSMPS =
1.8V, SVOS5
VDDSMPS =
3.3V, SVOS5
VDDSMPS =
1.8V, SVOS4
VDDSMPS =
3.3V, SVOS4
VDDSMPS =
1.8V, SVOS3
VDDSMPS =
3.3V, SVOS3
0.00001
0.0001
0.001
0.01
0.1
MSv62427V1
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 71: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
DS12930 Rev 1
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221
Electrical characteristics
STM32H747xI/G
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 48: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
ISW = VDDx × fSW × CL
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the MCU supply voltage
DDx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
EXT
L
INT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
•
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
The I/O compensation cell is enabled.
f
is the CPU clock. f
= f
/4, and f
= f
/2.
rcc_c_ck
PCLK
rcc_c_ck
HCLK
rcc_c_ck
The given value is calculated by measuring the difference of current consumption
–
–
–
with all peripherals clocked off
with only one peripheral clocked on
f
= 480 MHz (Scale 0), f
= 400 MHz (Scale 1), f
= 300 MHz
rcc_c_ck
rcc_c_ck
rcc_c_ck
(Scale 2), f
= 200 MHz (Scale 3)
rcc_c_ck
•
The ambient operating temperature is 25 °C and V =3.3 V.
DD
122/242
DS12930 Rev 1
STM32H747xI/G
Bus
Electrical characteristics
Table 48. Peripheral current consumption in Run mode
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
MDMA
DMA2D
4.6
2.9
3.8
2.4
3.4
2.1
3.2
1.9
JPGDEC
4.1
3.7
3.4
3.1
FLASH
17.0
0.9
15.0
1.1
14.0
0.9
12.0
0.8
FMC registers
FMC kernel
QUADSPI registers
QSPI kernel
SDMMC1 registers
SDMMC1 kernel
DTCM1
7.0
6.1
5.6
5.0
1.5
1.5
1.4
1.3
1.0
0.9
0.8
0.7
AHB3
8.2
7.2
6.7
6.0
1.3
1.2
0.9
0.9
7.9
6.8
6.0
5.3
DTCM2
8.3
7.2
6.4
5.7
ITCM
7.0
6.3
5.6
5.1
D1SRAM1
13.0
35.0
120
54.0
55.0
4.5
11.0
32.0
106
48.0
49.0
4.1
9.9
8.7
AHB3 bridge
Total AHB3
DMA1
29.0
96
26.0
86
µA/MHz
41.0
42.0
3.7
37.0
37.0
3.3
DMA2
ADC12 registers
ADC12 kernel
ART accelerator
ETH1MAC
1.0
0.7
0.4
0.6
4.1
3.7
3.2
2.9
17.0
0.1
15.0
0.1
14.0
0.1
12.0
0.1
ETH1TX
ETH1RX
0.1
0.1
0.1
0.1
AHB1
USB1 OTG registers
USB1 OTG kernel
USB1 ULPI
USB2 OTG registers
USB2 OTG kernel
USB2 ULPI
AHB1 bridge
Total AHB1
23.0
8.2
21.0
0.5
19.0
8.3
17.0
8.2
0.1
0.1
0.1
0.1
21.0
8.5
19.0
0.4
17.0
8.6
15.0
8.3
23.0
0.1
19.0
0.1
20.0
0.1
19.0
0.1
220
181
178
161
DS12930 Rev 1
123/242
221
Electrical characteristics
STM32H747xI/G
Table 48. Peripheral current consumption in Run mode (continued)
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
DCMI
RNG registers
RNG kernel
SDMMC2 registers
SDMMC2 kernel
D2SRAM1
D2SRAM2
D2SRAM3
AHB2 bridge
Total AHB2
GPIOA
2.1
1.7
11.0
47.0
1.7
5.7
5.2
4.1
0.1
79
1.9
2.0
0.1
41.0
1.2
4.9
4.5
3.6
0.1
60
1.8
1.3
9.7
37.0
1.1
4.4
4.0
3.2
0.1
63
1.6
1.2
9.4
34.0
1.0
3.9
3.5
2.8
0.1
58
AHB2
1.5
1.2
0.8
1.1
0.7
0.8
0.9
1.1
0.9
0.8
0.7
0.4
6.6
1.7
0.4
2.3
0.1
22
1.3
1.0
0.7
1.0
0.7
0.8
0.8
1.0
0.9
0.8
0.8
0.5
5.9
1.5
0.3
1.9
0.1
20
1.3
1.0
0.7
1.0
0.7
0.7
0.8
1.0
0.8
0.7
0.7
0.4
5.3
1.2
0.5
1.7
0.1
19
1.1
0.9
0.6
0.9
0.6
0.6
0.7
0.9
0.7
0.7
0.6
0.3
4.8
1.2
0.2
1.5
0.1
16
GPIOB
GPIOC
GPIOD
GPIOE
µA/MHz
GPIOF
GPIOG
GPIOH
GPIOI
AHB4
GPIOJ
GPIOK
CRC
BDMA
ADC3 registers
ADC3 kernel
BKPRAM
AHB4 bridge
Total AHB4
WWDG1
0.7
81.0
4.7
0.1
0.3
87
0.5
36.0
4.2
0.1
0.2
41
0.5
33.0
4.0
0.1
0.1
38
0.2
30.0
3.6
0.1
0.1
34
LCD-TFT
DSI registers
DSI kernel
APB3 bridge
Total APB3
APB3
µA/MHz
124/242
DS12930 Rev 1
STM32H747xI/G
Bus
Electrical characteristics
Table 48. Peripheral current consumption in Run mode (continued)
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
TIM2
TIM3
7.7
6.7
6.3
7.4
1.4
1.4
3.2
2.3
2.1
0.7
2.4
0.6
2.0
0.8
1.8
0.7
0.5
3.5
1.9
4.3
1.9
4.4
1.7
3.9
1.6
3.8
1.1
2.5
1.0
3.6
3.2
3.1
3.5
0.7
0.7
1.5
1.1
1.1
0.5
2.3
0.5
1.8
0.6
1.6
0.9
0.7
2.8
1.7
3.9
1.7
3.9
1.5
3.4
1.4
3.4
0.8
2.3
0.8
3.3
3.0
2.8
3.2
0.8
0.7
1.5
1.1
1.1
0.8
1.9
0.5
1.7
0.5
1.6
0.7
0.7
2.4
1.4
3.6
1.4
3.5
1.4
3.1
1.4
3.0
0.9
2.0
0.9
3.0
2.7
2.5
2.8
0.6
0.6
1.3
0.9
0.9
0.7
1.7
0.4
1.4
0.6
1.3
0.7
0.6
2.2
1.3
3.2
1.3
3.2
1.4
2.8
1.3
2.7
0.8
1.9
0.8
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
LPTIM1 registers
LPTIM1 kernel
WWDG2
SPI2 registers
SPI2 kernel
SPI3 registers
SPI3 kernel
SPDIFRX1 registers
SPDIFRX1 kernel
USART2 registers
USART2 kernel
USART3 registers
USART3 kernel
UART4 registers
UART4 kernel
UART5 registers
UART5 kernel
I2C1 registers
I2C1 kernel
I2C2 registers
APB1
µA/MHz
DS12930 Rev 1
125/242
221
Electrical characteristics
STM32H747xI/G
Table 48. Peripheral current consumption in Run mode (continued)
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
I2C2 kernel
I2C3 registers
I2C3 kernel
2.3
0.8
2.4
0.7
0.1
3.6
1.8
4.0
2.0
3.9
6.4
2.7
0.1
0.2
3.3
19.0
9.1
0.1
142
11.0
10.0
3.6
0.1
4.5
0.1
2.0
0.9
2.1
0.6
5.5
4.1
4.1
2.0
0.5
1.3
2.2
1.0
1.9
0.5
0.1
1.3
1.8
3.3
1.6
3.4
5.5
2.4
0.1
0.3
2.9
17.0
7.9
0.1
108
5.0
4.7
2.5
0.1
3.0
0.1
1.7
0.8
1.7
0.5
2.5
2.0
1.9
1.8
0.4
1.1
1.9
0.8
1.8
0.6
3.2
1.2
1.6
3.0
1.6
3.1
5.0
2.3
0.1
0.3
2.6
15.0
6.9
0.1
102
4.5
4.3
2.7
0.1
3.1
0.1
1.6
0.7
1.6
0.5
2.3
1.8
1.8
1.6
0.4
1.1
1.7
0.8
1.6
0.5
0.1
1.0
1.4
2.8
1.4
2.8
4.5
1.9
0.1
0.2
2.3
13.0
6.4
0.1
88
HDMI-CEC registers
HDMI-CEC kernel
DAC12
USART7 registers
USART7 kernel
USART8 registers
USART8 kernel
CRS
APB1
(continued)
SWPMI registers
SWPMI kernel
OPAMP
MDIO
FDCAN registers
FDCAN kernel
APB1 bridge
Total APB1
TIM1
µA/MHz
4.0
3.8
2.9
0.1
3.4
0.1
1.4
0.6
1.5
0.3
2.1
1.7
1.6
1.3
0.5
1.0
TIM8
USART1 registers
USART1 kernel
USART6 registers
USART6 kernel
SPI1 registers
SPI1 kernel
APB2
SPI4 registers
SPI4 kernel
TIM15
TIM16
TIM17
SPI5 registers
SPI5 kernel
SAI1 registers
126/242
DS12930 Rev 1
STM32H747xI/G
Bus
Electrical characteristics
Table 48. Peripheral current consumption in Run mode (continued)
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
SAI1 kernel
SAI2 registers
SAI2 kernel
1.4
1.5
1.1
1.6
1.1
6.5
0.3
84.0
0.2
150
0.9
1.1
2.9
1.8
0.4
0.9
2.2
0.8
2.3
0.7
2.1
0.8
2.2
0.5
2.0
0.6
0.4
1.1
1.7
2.0
0.1
28
1.1
1.3
1.0
1.3
1.2
5.8
0.2
39.0
0.1
81
1.0
1.2
0.9
1.1
1.1
5.2
0.2
35.0
0.1
74
0.8
1.0
0.9
1.0
0.9
4.7
0.4
32.0
0.2
68
SAI3 registers
SAI3 kernel
APB2
(continued)
DFSDM1 registers
DFSDM1 kernel
HRTIM
APB2 bridge
Total APB2
SYSCFG
1.0
1.3
2.2
1.6
0.4
0.7
2.1
0.6
2.1
0.7
1.7
0.4
2.0
0.4
1.8
0.4
0.2
0.9
1.4
2.0
0.1
24.4
0.7
1.0
2.2
1.4
0.5
0.7
1.9
0.7
1.8
0.7
1.6
0.6
1.7
0.6
1.5
0.5
0.2
1.0
1.3
1.8
0.1
22.4
0.8
0.8
2.1
1.3
0.3
0.4
1.8
0.5
1.4
0.4
1.5
0.4
1.5
0.4
1.2
0.2
0.1
0.6
1.0
1.6
0.1
18.9
LPUART1 registers
LPUART1 kernel
SPI6 registers
SPI6 kernel
I2C4 registers
I2C4 kernel
µA/MHz
LPTIM2 registers
LPTIM2 kernel
LPTIM3 registers
LPTIM3 kernel
LPTIM4 registers
LPTIM4 kernel
LPTIM5 registers
LPTIM5 kernel
COMP12
APB4
VREF
RTC
SAI4 registers
SAI4 kernel
APB4 bridge
Total APB4
DS12930 Rev 1
127/242
221
Electrical characteristics
STM32H747xI/G
6.3.8
Wakeup time from low-power modes
The wakeup times given in Table 49 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
(1)
Table 49. Low-power mode wakeup timings
Typ(2)
Max(2)
Symbol
Parameter
Conditions
Unit
CPU
clock
cycles
(3)
tWUSLEEP
Wakeup from Sleep
-
9
10
VOS3, HSI, Flash memory in normal mode
4.4
12
15
23
39
39
30
36
38
47
68
68
5.6
15
20
28
71
47
37
50
48
61
75
77
VOS3, HSI, Flash memory in low-power
mode
VOS4, HSI, Flash memory in normal mode
VOS4, HSI, Flash memory in low-power
mode
VOS5, HSI, Flash memory in normal mode
VOS5, HSI, Flash memory in low-power
mode
(3)
tWUSTOP
Wakeup from Stop
VOS3, CSI, Flash memory in normal mode
VOS3, CSI, Flash memory in low power
mode
µs
VOS4, CSI, Flash memory in normal mode
VOS4, CSI, Flash memory in low-power
mode
VOS5, CSI, Flash memory in normal mode
VOS5, CSI, Flash memory in low-power
mode
VOS3, HSI, Flash memory in normal mode
VOS3, CSI, Flash memory in normal mode
2.6
26
3.4
36
tWUSTOP_
Wakeup from Stop,
clock kept running
(3)
KERON
Wakeup from Standby
mode
(3)
tWUSTDBY
-
390
500
1. The wakeup timings is valid for both CPUs.
2. Guaranteed by characterization results.
3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
128/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
6.3.9
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 71: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 21.
(1)
Table 50. High-speed external user clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fHSE_ext
User external clock source frequency
4
25
50
MHz
VSW
(VHSEH−VHSEL)
OSC_IN amplitude
0.7VDD
-
VDD
V
VDC
OSC_IN input voltage
VSS
7
-
-
0.3VSS
-
tW(HSE)
OSC_IN high or low time
ns
1. Guaranteed by design.
Figure 21. High-speed external clock source AC timing diagram
V
HSEH
90%
10 %
HSEL
V
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
I
L
OSC _I N
clock source
STM32
ai17528b
DS12930 Rev 1
129/242
221
Electrical characteristics
STM32H747xI/G
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 71: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 22.
(1)
Table 51. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
-
-
-
32.768
1000
VDDIOx
kHz
0.7 VDDIOx
VSS
-
-
V
0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
-
250
-
-
ns
1. Guaranteed by design.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
W(LSE)
t
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
I
L
OSC32_IN
clock source
STM32
ai17529b
130/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 52. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 52. 4-48 MHz HSE oscillator characteristics
Operating
Symbol
Parameter
Min
Typ
Max
Unit
conditions(2)
F
Oscillator frequency
Feedback resistor
-
4
-
-
200
-
48
-
MHz
RF
-
kꢁ
During startup(3)
-
4
V
DD=3 V, Rm=30 ꢁ
-
-
-
-
-
0.35
0.40
0.45
0.65
0.95
-
-
-
-
-
CL=10pF@4MHz
VDD=3 V, Rm=30 ꢁ
CL=10 pF at 8 MHz
IDD(HSE)
HSE current consumption
mA
VDD=3 V, Rm=30 ꢁ
CL=10 pF at 16 MHz
VDD=3 V, Rm=30 ꢁ
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 ꢁ
CL=10 pF at 48 MHz
Gmcritmax
Maximum critical crystal gm
Start-up time
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 23). C and C are usually
L1
L2
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . The PCB and MCU pin capacitance must be included
L1
L2
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing C and C .
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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STM32H747xI/G
Figure 23. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
OSC_OUT
(1)
STM32
R
EXT
C
L2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 53. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 53. Low-speed external user clock characteristics
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
-
32.768
-
kHz
LSEDRV[1:0] = 00,
Low drive capability
-
-
-
-
-
-
-
290
390
550
900
-
-
-
LSEDRV[1:0] = 01,
Medium Low drive capability
LSE current
consumption
IDD
nA
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
LSEDRV[1:0] = 00,
Low drive capability
0.5
0.75
1.7
LSEDRV[1:0] = 01,
Medium Low drive capability
-
Maximum critical crystal
gm
Gmcritmax
µA/V
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
-
-
2.7
-
(3)
tSU
Startup time
VDD is stabilized
2
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
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Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 24. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_IN
LSE
Bias
controlled
gain
32.768 kHz
resonator
R
F
OSC32_OUT
STM32
C
L2
ai17531b
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
6.3.10
Internal clock source characteristics
The parameters given in Table 54 to Table 57 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 22: General
DD
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 54. HSI48 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD=3.3 V,
TJ=30 °C
fHSI48
HSI48 frequency
47.5(1)
-
48
48.5(1) MHz
TRIM(2)
USER trimming step
USER TRIMMING Coverage
Duty Cycle
-
± 32 steps
-
0.175
-
-
%
%
%
%
USER TRIM
COVERAGE(3)
±4.79 ±5.60
DuCy(HSI48)(2)
45
-
-
55
3.5
Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
ACCHSI48_REL(3)(4)
TJ=-40 to 125 °C
–4.5
VDD=3 to 3.6 V
-
-
-
-
0.025
0.05
2.1
0.05
0.1
HSI48 oscillator frequency drift with
VDD
∆
VDD(HSI48)(3)
%
(5)
VDD=1.62 V to 3.6 V
(2)
tsu(HSI48)
HSI48 oscillator start-up time
-
-
4.0
µs
(2)
IDD(HSI48)
HSI48 oscillator power consumption
350
400
µA
Next transition jitter
Accumulated jitter on 28 cycles(6)
NT jitter
PT jitter
-
-
-
-
± 0.15
± 0.25
-
-
ns
ns
Paired transition jitter
Accumulated jitter on 56 cycles(6)
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization.
4. ꢀfHSI = ACCHSI48_REL + ꢀVDD
.
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STM32H747xI/G
5. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) /
Freq(1.62V).
6. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
(1)
Table 55. HSI oscillator characteristics
Symbol
Parameter
HSI frequency
Conditions
Min
Typ
Max
Unit
fHSI
VDD=3.3 V, TJ=30 °C
63.7(2)
64
64.3(2)
MHz
Trimming is not a multiple
of 32
-
0.24
−1.8
−0.8
0.32
Trimming is 128, 256 and
384
−5.2
−1.4
-
-
Trimming is 64, 192, 320
and 448
TRIM
HSI user trimming step
%
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
−0.6
−0.25
-
DuCy(HSI) Duty Cycle
-
45
-
-
55
%
%
HSI oscillator frequency drift over
ΔVDD (HSI)
VDD=1.62 to 3.6 V
−0.12
0.03
VDD (reference is 3.3 V)
TJ=-20 to 105 °C
−1(3)
-
-
1(3)
1(3)
2
HSI oscillator frequency drift over
temperature (reference is 64 MHz)
ΔTEMP (HSI)
%
TJ=−40 to TJmax °C
−2(3)
tsu(HSI)
HSI oscillator start-up time
-
-
-
-
1.4
4
µs
µs
µA
tstab(HSI) HSI oscillator stabilization time
DD(HSI) HSI oscillator power consumption
at 1% of target frequency
-
8
I
300
400
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
4 MHz low-power internal RC oscillator (CSI)
Table 56. CSI oscillator characteristics
(1)
Symbol
Parameter
CSI frequency
Conditions
Min
Typ
Max
Unit
fCSI
TRIM
VDD=3.3 V, TJ=30 °C
3.96(2)
4
0.35
-
4.04(2) MHz
Trimming step
Duty Cycle
-
-
45
-
-
%
%
DuCy(CSI)
-
55
TJ = 0 to 85 °C
TJ = −40 to 125 °C
−3.7(3) 4.5(3)
CSI oscillator frequency drift over
temperature
ꢀTEMP (CSI)
%
%
-
−11(3)
7.5(3)
CSI oscillator frequency drift over
VDD
DVDD (CSI)
VDD = 1.62 to 3.6 V
-
−0.06
0.06
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(1)
Table 56. CSI oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tsu(CSI)
CSI oscillator startup time
-
-
1
2
µs
CSI oscillator stabilization time
tstab(CSI)
IDD(CSI)
-
-
-
-
-
4
cycle
µA
(to reach ±3% of fCSI
)
CSI oscillator power consumption
23
30
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Low-speed internal (LSI) RC oscillator
Table 57. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V, TJ = 25 °C
31.4(1)
32
32.6(1)
TJ = –40 to 110 °C, VDD = 1.62 to
3.6 V
29.76(2)
-
-
33.6(2)
fLSI
LSI frequency
kHz
TJ = –40 to 125 °C, VDD = 1.62 to
3.6 V
29.4
-
33.6
LSI oscillator
startup time
(3)
tsu(LSI)
-
80
130
LSI oscillator
stabilization
time (5% of
final value)
µs
(3)
tstab(LSI)
-
-
-
120
130
170
280
LSI oscillator
power
(3)
IDD(LSI)
-
nA
consumption
1. Guaranteed by test in production.
2. Guaranteed by characterization results.
3. Guaranteed by design.
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6.3.11
PLL characteristics
The parameters given in Table 58 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 22: General operating conditions.
DD
(1)
Table 58. PLL characteristics (wide VCO frequency range)
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
2
10
1.5
1.5
1.5
1.5
192
-
-
16
MHz
%
PLL input clock duty cycle
-
-
90
VOS0
VOS1
VOS2
VOS3
-
-
480(2)
400(2)
300(2)
200(2)
960
-
fPLL_P_OUT PLL multiplier output clock P
-
MHz
µs
-
fVCO_OUT
PLL VCO output
PLL lock time
-
Normal mode
50(3)
150(3)
tLOCK
Sigma-delta mode
(CKIN ≥ 8 MHz)
-
-
-
-
-
-
58(3)
134
134
76
166(3)
VCO =
192 MHz
-
-
-
-
-
VCO =
200 MHz
Cycle-to-cycle jitter(4)
-
±ps
VCO =
400 MHz
VCO =
800 MHz
39
VCO =
800 MHz
Normal mode
±0.7
Jitter
Long term jitter
%
Sigma-delta
mode (CKIN =
16 MHz)
VCO =
800 MHz
-
±0.8
-
VDDA
VCORE
VDDA
-
-
-
-
590
720
180
280
1500
VCO freq =
836 MHz
-
600
-
(3)
IDD(PLL)
PLL power consumption on VDD
µA
VCO freq =
192 MHz
VCORE
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation (480 MHz for VOS0, 400 MHz for VOS1,
300 MHz for VOS2, 200 MHz for VOS3).
3. Guaranteed by characterization results.
4. Integer mode only.
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Symbol
Electrical characteristics
(1)
Table 59. PLL characteristics (medium VCO frequency range)
Parameter
Conditions
Min
Typ
Max Unit
PLL input clock
-
1
-
-
-
-
-
-
2
MHz
%
fPLL_IN
PLL input clock duty cycle
-
VOS1
10
90
1.17
1.17
1.17
150
-
210
210
200
420
PLL multiplier output clock P, Q,
R
fPLL_OUT
VOS2
MHz
µs
VOS3
fVCO_OUT
tLOCK
PLL VCO output
PLL lock time
-
Normal mode
Sigma-delta mode
60(2) 100(2)
forbidden
VCO =
150 MHz
-
-
-
-
-
-
-
145
-
-
-
-
-
-
-
VCO =
300 MHz
91
64
Cycle-to-cycle jitter(3)
-
±ps
VCO =
400 MHz
VCO =
420 MHz
Jitter
63
VCO =
150 MHz
55
fPLL_OUT
50 MHz
=
Period jitter
±-ps
%
VCO =
400 MHz
30
VCO =
400 MHz
Long term jitter
Normal mode
±0.3
VDD
VCORE
VDD
-
-
-
-
440
530
180
200
1150
VCO freq =
420MHz
-
500
-
I(PLL)(2)
PLL power consumption on VDD
µA
VCO freq =
150MHz
VCORE
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
6.3.12
MIPI D-PHY characteristics
The parameters given in Table 60 and Table 61 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions.
(1)
Table 60. MIPI D-PHY characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ns
Hi-Speed Input/Output Characteristics
UINST
UI instantaneous
-
2
-
12.5
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Electrical characteristics
STM32H747xI/G
(1)
Table 60. MIPI D-PHY characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
HS transmit common mode
voltage
VCMTX
-
150
200
250
VCMTX mismatch when output
is Differential-1 or Differential-0
|ꢀVCMTX
|VOD
|ꢀVOD
VOHHS
ZOS
|
-
-
-
-
-
-
140
-
-
200
-
5
mV
|
HS transmit differential voltage
270
14
VOD mismatch when output is
Differential-1 or Differential-0
|
HS output high voltage
-
-
360
62.5
Single ended output
impedance
40
50
ꢁ
Single ended output
impedance mismatch
ꢀZOS
-
-
-
-
-
10
%
tHSr & tHSf 20%-80% rise and fall time
100
0.35*UI
ps
LP Receiver Input Characteristics
Logic 0 input voltage (not in
ULP State)
VIL
-
-
-
-
-
-
550
300
Logic 0 input voltage in ULP
State
VIL-ULPS
mV
VIH
Input high level voltage
Voltage hysteresis
-
-
880
25
-
-
-
-
Vhys
LP Emitter Output Characteristics
VIL
Output low level voltage
-
-
1.1
-50
1.2
-
1.2
50
V
VIL-ULPS Output high level voltage
mV
Output impedance of LP
transmitter
VIH
-
-
110
-
-
-
-
ꢁ
Vhys
15%-85% rise and fall time
25
ns
LP Contention Detector Characteristics
VILCD
VIHCD
Logic 0 contention threshold
Logic 0 contention threshold
-
-
-
-
-
200
-
mV
450
1. Guaranteed based on test during characterization.
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Electrical characteristics
Table 61. MIPI D-PHY AC characteristics LP mode and HS/LP
(1)
transitions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Transmitted length of any Low-
Power state period
TLPX
-
50
-
-
Time that the transmitter drives
the Clock Lane LP-00 Line
TCLK-PREPARE state immediately before the
HS-0 Line state starting the HS
transmission.
-
-
-
38
300
8
-
-
-
95
-
ns
TCLK-PREPARE Time that the transmitter drives
+
the HS-0 state prior to starting
the clock.
TCLK-ZERO
Time that the HS clock shall be
driven by the transmitter prior to
any associated Data Lane
beginning the transition from
LP to HS mode.
TCLK-PRE
-
UI
Time that the transmitter
continues to send HS clock
after the last associated Data
Lane has transitioned to LP
Mode.
TCLK-POST
-
-
-
62+52*UI
-
-
-
-
Time that the transmitter drives
the HS-0 state after the last
payload clock bit of an HS
transmission burst.
TCLK-TRAIL
60
-
Time that the transmitter drives
the Data Lane LP-00 Line state
THS-PREPARE immediately before the HS-0
Line state starting the HS
transmission.
40+4*UI
145+10*UI
85+6*UI
THS-PREPARE+ Time that the
transmitter drives the HS-0
THS-PREPARE
ns
+
-
-
-
-
-
-
state prior to transmitting the
THS-ZERO
Sync sequence.
Time that the transmitter drives
the flipped differential state
after last payload data bit of a
HS transmission burst.
Max
(n*8*UI,
60+n*4*UI)
THS-TRAIL
Time that the transmitter drives
THS-EXIT
-
-
100
-
-
-
-
LP-11 following a HS burst.
TREOT
30%-85% rise time and fall time
35
Transmitted time interval from
the start of THS-TRAIL or
TCLK-TRAIL, to the start of the
LP-11 state following a HS
burst.
105+
n*12UI
TEOT
-
-
-
1. Guaranteed based on test during characterization.
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Electrical characteristics
STM32H747xI/G
Figure 25. MIPI D-PHY HS/LP clock lane transition timing diagram
TCLK-POST
TEOT
VIL
Clock
Lane
TCLK-TRAIL THS-EXIT
TLPX TCLK-PREPARE TCLK-ZERO TCLK-PRE
TLPX THS-PREPARE
VIL
Data
Lane
MS38282V1
Figure 26. MIPI D-PHY HS/LP data lane transition timing diagram
Clock
Lane
TLPX
THS-PREPARE THS-ZERO
Data
Lane
VIL
TREOT
LP-11
LP-01 LP-00
TEOT
THS-TRAIL
THS-EXIT
MS38283V1
6.3.13
MIPI D-PHY regulator characteristics
The parameters given in Table 62 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 22: General operating conditions.
DD
(1)
Table 62. DSI regulator characteristics
Symbol
Parameter
Regulator output voltage on VDDDSI
Conditions
Min Typ Max Unit
VDDDSI
-
1.62
-
-
V
VDD12DSI 1.2 V internal voltage on VDD12DSI
-
1.15 1.20 1.26
0.5 2.2(2) 3.3
CEXT
ESR
External capacitor on VCAPDSI
External serial resistor
Static load current
-
μF
-
0
-
25
-
600 mꢁ
ILOAD
-
50
mA
ILOAD = 0 mA
ILOAD = 50 mA
110 170 220
140 200 260
IDDDSIREG Regulator power consumption on VDDDSI
µA
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(1)
Table 62. DSI regulator characteristics (continued)
Parameter Conditions
Symbol
Min Typ Max Unit
C
EXT = 2.2 µF
-
-
-
80
-
-
tWAKEUP Startup delay
µs
CEXT = 3.3 µF
160
250
IINRUSH
Inrush current on VDDDSI
External capacitor load at start
60
mA
1. Based on test during characterization.
2. CEXT recommended value is 2.2 μF to achieve a better dynamic performance of the regulator. A 1 μF capacitor can be
used only if the minimum value does not drop below 0.5 μF.
6.3.14
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 125 °C unless otherwise specified.
J
The devices are shipped to customers with the Flash memory erased.
Table 63. Flash memory characteristics
Symbol
Parameter
Conditions
Write / Erase 8-bit mode
Min
Typ
Max
Unit
-
-
-
-
6.5
11.5
20
-
-
-
-
Write / Erase 16-bit mode
Write / Erase 32-bit mode
Write / Erase 64-bit mode
IDD
Supply current
mA
35
Table 64. Flash memory programming (single bank configuration nDBANK=1)
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
-
-
-
-
-
-
-
-
-
-
-
290
180
130
100
2
580(2)
360
µs
260
Word (266 bits) programming
time
tprog
200
4
tERASE128KB Sector (128 KB) erase time
1.8
3.6
13
8
26
16
12
10
s
tME
Mass erase time
6
5
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Electrical characteristics
STM32H747xI/G
Table 64. Flash memory programming (single bank configuration nDBANK=1) (continued)
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Program parallelism x 8
Program parallelism x 16
Program parallelism x 32
Program parallelism x 64
1.62
1.8
-
-
3.6
V
Vprog
Programming voltage
3.6
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
Table 65. Flash memory endurance and data retention
Value
Min(1)
Symbol
Parameter
Conditions
Unit
NEND
tRET
Endurance
Data retention
TJ = –40 to +125 °C (6 suffix versions)
1 kcycle at TA = 85 °C
kcycles
Years
10
30
20
10 kcycles at TA = 55 °C
1. Guaranteed by characterization results.
6.3.15
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 66. They are based on the EMS levels and classes
defined in application note AN1709.
Table 66. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
Voltage limits to be applied on any I/O pin to induce
a functional disturbance
VFESD
3B
5A
VDD = 3.3 V, TA = +25 °C,
UFBGA240, frcc_c_ck
=
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
400 MHz, conforms to
IEC 61000-4-2
VFTB
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As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 67. EMI characteristics
Max vs.
Monitored
frequency band
[fHSE/fCPU
]
Symbol Parameter
Conditions
Unit
8/400 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
11
6
dBµV
-
VDD = 3.6 V, TA = 25 °C, UFBGA240 package,
conforming to IEC61967-2
SEMI
Peak level
12
7
2.5
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STM32H747xI/G
6.3.16
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 68. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Packages
Class
Unit
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
001
All
1C
1000
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
002
All
C1
250
1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 69. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latchup class
TA = +25 °C conforming to JESD78
II level A
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6.3.17
I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
DD
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 70. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
PJ12, PB4
5
0
0
5
0
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11
NA
0
IINJ
mA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PH4, PH5, BOOT0
All other I/Os
NA
1. Guaranteed by characterization.
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STM32H747xI/G
6.3.18
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 71: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 22: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Table 71. I/O static characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I/O input low level voltage except
BOOT0
(1)
-
-
0.3VDD
I/O input low level voltage except
BOOT0
0.4VDD−0.
VIL
1.62 V<VDDIOx<3.6 V
-
-
-
V
1(2)
0.19VDD
+
BOOT0 I/O input low level voltage
-
0.1(2)
I/O input high level voltage except
BOOT0
(1)
0.7VDD
-
-
-
-
-
I/O input high level voltage except
BOOT0(3)
0.47VDD+0.
25(2)
VIH
1.62 V<VDDIOx<3.6 V
-
-
V
BOOT0 I/O input high level
voltage(3)
0.17VDD+0.
6(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis
-
250
(2)
VHYS
1.62 V< VDDIOx <3.6 V
mV
BOOT0 I/O input hysteresis
-
-
200
-
-
(9)
0< VIN ≤ Max(VDDXXX
)
+/-250
FT_xx Input leakage current(2)
Max(VDDXXX) < VIN ≤ 5.5 V
-
-
-
-
-
-
1500
(5)(6)(9)
(9)
0< VIN ≤ Max(VDDXXX
)
+/- 350
5000(7)
(4)
FT_u IO
Ileak
Max(VDDXXX) < VIN ≤ 5.5 V
nA
(5)(6)(9)
(9)
TT_xx Input leakage current
0< VIN ≤ Max(VDDXXX
0< VIN ≤ VDDIOX
)
-
-
-
-
+/-250
15
VPP (BOOT0 alternate function)
VDDIOX < VIN ≤ 9 V
35
Weak pull-up equivalent
resistor(8)
RPU
VIN=VSS
30
40
50
kꢁ
Weak pull-down equivalent
resistor(8)
(9)
RPD
CIO
VIN=VDD
-
30
-
40
5
50
-
I/O pin capacitance
pF
1. Compliant with CMOS requirements.
2. Guaranteed by design.
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max)
.
5. All FT_xx IO except FT_lu, FT_u and PC3.
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6. VIN must be less than Max(VDDXXX) + 3.6 V.
7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 27.
Figure 27. V /V for all I/Os except BOOT0
IL IH
3
2.5
2
TLL requirement: VIHmin = 2 V
1.5
1
TLL requirement: VILmin = 0.8 V
0.5
0
2.8
1.6
1.8
2
2.2
2.4
2.6
3
3.2
3.4
3.6
MSv46121V3
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 20).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 20).
VSS
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STM32H747xI/G
Output voltage levels
Unless otherwise specified, the parameters given in Table 72: Output voltage characteristics
for all I/Os except PC13, PC14, PC15 and PI8 and Table 73: Output voltage characteristics
for PC13, PC14, PC15 and PI8 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions. All I/Os are CMOS and TTL compliant.
(1)
Table 72. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO=8 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO=-8 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=8 mA
(3)
VOL
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=-8 mA
(3)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
V
IIO=20 mA
(3)
VOL
Output low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
1.3
-
2.7 V≤ VDD ≤3.6 V
IIO=-20 mA
(3)
VOH
VDD−1.3
2.7 V≤ VDD ≤3.6 V
IIO=4 mA
(3)
VOL
-
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO=-4 mA
1.62 V≤VDD<3.6 V
(3)
VOH
VDD−-0.4
IIO= 20 mA
-
-
0.4
0.4
2.3 V≤ VDD≤3.6 V
Output low level voltage for an FTf
I/O pin in FM+ mode
(3)
VOLFM+
IIO= 10 mA
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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(1)
Table 73. Output voltage characteristics for PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO=3 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO=-3 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=3 mA
(3)
VOL
-
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=-3 mA
(2)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
IIO=1.5 mA
(2)
VOL
Output low level voltage
Output high level voltage
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO=-1.5 mA
(2)
VOH
VDD−0.4
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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STM32H747xI/G
Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
(1)(2)
Table 74. Output timing characteristics (HSLV OFF)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
3
12
(3)
Fmax
Maximum frequency
MHz
3
16
4
00
16.6
33.3
13.3
25
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
10
20
60
15
80
(3)
Fmax
Maximum frequency
15
110
20
01
5.2
10
Output high to low level
fall time and output low
to high level rise time
4.2
7.5
2.8
5.2
tr/tf(4)
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Electrical characteristics
(continued)
(1)(2)
Table 74. Output timing characteristics (HSLV OFF)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 Vv
C=50 pF, 2.7 V≤VDD≤3.6 Vv
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 Vv
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85
35
110
40
(3)
Fmax
Maximum frequency
MHz
166
100
3.8
6.9
2.8
5.2
1.8
3.3
100
50
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
133
66
(3)
Fmax
Maximum frequency
220
85
11
3.3
6.6
2.4
4.5
1.5
2.7
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
1. Guaranteed by design.
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
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STM32H747xI/G
Output buffer timing characteristics (HSLV option enabled)
(1)
Table 75. Output timing characteristics (HSLV ON)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
10
10
11
(2)
Fmax
Maximum frequency
MHz
00
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
9
ns
MHz
ns
6.6
50
58
66
6.6
4.8
3
(2)
Fmax
Maximum frequency
01
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
55
80
133
5.8
4
(2)
Fmax
Maximum frequency
MHz
ns
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
2.4
60
90
175
5.3
3.6
1.9
(2)
Fmax
Maximum frequency
MHz
ns
11
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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6.3.19
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 71: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 76 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 22: General operating conditions.
Table 76. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Weak pull-up equivalent
resistor(1)
(2)
RPU
VIN = VSS
30
40
50
㏀
(2)
VF(NRST)
NRST Input filtered pulse
1.71 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
-
-
50
-
300
ns
(2)
VNF(NRST)
NRST Input not filtered pulse
1.62 V < VDD < 3.6 V 1000
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 28. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 71. Otherwise the reset is not taken into account by the device.
6.3.20
FMC characteristics
Unless otherwise specified, the parameters given in Table 77 to Table 90 for the FMC
interface are derived from tests performed under the ambient temperature, f
frequency
HCLK
and V supply voltage conditions summarized in Table 22: General operating conditions,
DD
with the following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1.
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Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics.
Asynchronous waveforms and timings
Figure 29 through Figure 31 represent asynchronous waveforms and Table 77 through
Table 84 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
Capacitive load C = 30 pF
L
In all timing tables, the T
is the f
clock period.
KERCK
mc_ker_ck
Figure 29. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Table 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
3Tfmc_ker_ck–1
0
3Tfmc_ker_ck+1
0.5
2Tfmc_ker_ck –1
2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high
hold time
th(NE_NOE)
tv(A_NE)
0
-
-
0.5
-
FMC_NEx low to FMC_A valid
Address hold time after
FMC_NOE high
th(A_NOE)
0
Data to FMC_NEx high setup
time
ns
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
11
11
0
-
-
-
-
Data to FMC_NOEx high setup
time
Data hold time after FMC_NOE
high
Data hold time after FMC_NEx
high
0
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV) FMC_NADV low time
-
-
0
Tfmc_ker_ck+1
1. Guaranteed by characterization results.
Table 78. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tw(NOE)
tw(NWAIT)
FMC_NE low time
FMC_NOE low time
FMC_NWAIT low time
7Tfmc_ker_ck+1
5Tfmc_ker_ck–1
Tfmc_ker_ck– 0.5
7Tfmc_ker_ck+1
5Tfmc_ker_ck +1
-
ns
FMC_NWAIT valid before FMC_NEx
high
tsu(NWAIT_NE)
th(NE_NWAIT)
4Tfmc_ker_ck +11
3Tfmc_ker_ck+11.5
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Figure 30. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Table 79. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
3Tfmc_ker_ck –1
Tfmc_ker_ck
3Tfmc_ker_ck
Tfmc_ker_ck+1
Tfmc_ker_ck+0.5
Tfmc_ker_ck –0.5
FMC_NWE high to FMC_NE high
hold time
th(NE_NWE)
tv(A_NE)
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Tfmc_ker_ck
-
2
FMC_NEx low to FMC_A valid
-
Address hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
-
-
ns
FMC_NEx low to FMC_BL valid
0.5
-
FMC_BL hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
Data to FMC_NEx low to Data valid
-
Tfmc_ker_ck+ 2.5
th(Data_NWE) Data hold time after FMC_NWE high
Tfmc_ker_ck+0.5
-
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
-
0
Tfmc_ker_ck+ 1
1. Guaranteed by characterization results.
Table 80. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
8Tfmc_ker_ck+1
tw(NWE)
FMC_NWE low time
6Tfmc_ker_ck –1.5
6Tfmc_ker_ck+0.5
FMC_NWAIT valid before FMC_NEx
high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
5Tfmc_ker_ck+13
4Tfmc_ker_ck+13
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Figure 31. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
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Table 81. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
4Tfmc_ker_ck –1
4Tfmc_ker_ck +1
2Tfmc_ker_ck
+0.5
tv(NOE_NE)
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2Tfmc_ker_ck
Tfmc_ker_ck –1
0
ttw(NOE)
Tfmc_ker_ck +1
-
FMC_NOE high to FMC_NE high hold
time
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
0.5
0.5
0
ns
Tfmc_ker_ck –0.5
Tfmc_ker_ck +1
FMC_AD(address) valid hold time
after FMC_NADV high)
th(AD_NADV)
th(A_NOE)
Tfmc_ker_ck +0.5
Tfmc_ker_ck –0.5
-
-
Address hold time after FMC_NOE
high
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NE)
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
11
11
0
-
-
-
th(Data_NOE)
0
-
1. Guaranteed by characterization results.
(1)(2)
Table 82. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
8Tfmc_ker_ck
tw(NOE)
FMC_NWE low time
5Tfmc_ker_ck –1.5
5Tfmc_ker_ck +0.5
FMC_NWAIT valid before
FMC_NEx high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
4Tfmc_ker_ck +11
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
3Tfmc_ker_ck +11.5
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Table 83. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
4Tfmc_ker_ck –1
Tfmc_ker_ck –1
4Tfmc_ker_ck
Tfmc_ker_ck +0.5
2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5
FMC_NWE high to FMC_NE high hold
time
th(NE_NWE)
Tfmc_ker_ck –0.5
-
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
0
0.5
0
Tfmc_ker_ck
Tfmc_ker_ck + 1
ns
FMC_AD(adress) valid hold time after
FMC_NADV high)
th(AD_NADV)
th(A_NWE)
Tfmc_ker_ck +0.5
-
-
-
Address hold time after FMC_NWE
high
Tfmc_ker_ck +0.5
FMC_BL hold time after FMC_NWE
high
th(BL_NWE)
Tfmc_ker_ck – 0.5
tv(BL_NE)
FMC_NEx low to FMC_BL valid
FMC_NADV high to Data valid
-
-
0.5
tv(Data_NADV)
th(Data_NWE)
Tfmc_ker_ck +2
-
Data hold time after FMC_NWE high
Tfmc_ker_ck +0.5
1. Guaranteed by characterization results.
(1)(2)
Table 84. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9Tfmc_ker_ck –1
9Tfmc_ker_ck
tw(NWE)
FMC_NWE low time
7Tfmc_ker_ck –0.5
7Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_NEx
high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
5Tfmc_ker_ck +11
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
4Tfmc_ker_ck +11.5
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Synchronous waveforms and timings
Figure 32 through Figure 35 represent synchronous waveforms and Table 85 through
Table 88 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
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In all the timing tables, the Tfmc_ker_ck is the f
clock period, with the following
mc_ker_ck
FMC_CLK maximum values:
•
•
•
For 2.7 V<V <3.6 V, FMC_CLK = 125 MHz at 20 pF
DD
For 1.8 V<V <1.9 V, FMC_CLK = 100 MHz at 20 pF
DD
For 1.62 V<V <1.8 V, FMC_CLK = 100 MHz at 15 pF
DD
Figure 32. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
MS32757V1
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Table 85. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
1
td(CLKL-NExL)
td(CLKH_NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
-
Tfmc_ker_ck+0.5
-
-
0
-
1
FMC_CLK low to FMC_NADV high
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2.5
FMC_CLK high to FMC_Ax invalid
(x=16…25)
td(CLKH-AIV)
Tfmc_ker_ck
-
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
1.5
ns
Tfmc_ker_ck –0.5
-
3
-
-
0
FMC_A/D[15:0] valid data before FMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
2
1
-
-
FMC_A/D[15:0] valid data after FMC_CLK
high
tsu(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Figure 33. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
FMC_A[25:16]
t
d(CLKH-NWEH)
d(CLKL-NWEL)
FMC_NWE
t
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
d(CLKL-Data)
d(CLKL-ADV)
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKH-NBLH)
FMC_NBL
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Electrical characteristics
Symbol
STM32H747xI/G
(1)
Table 86. Synchronous multiplexed PSRAM write timings
Parameter
Min
Max
Unit
2Tfmc_ker_ck –1
1
tw(CLK)
FMC_CLK period, VDD = 2.7 to 3.6 V
-
1
-
td(CLKL-NExL)
td(CLKH-NExH)
FMC_CLK low to FMC_NEx low (x =0..2)
-
FMC_CLK high to FMC_NEx high
(x = 0…2)
T
fmc_ker_ck +0.5
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
1.5
-
0
FMC_CLK low to FMC_Ax valid
(x =16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2
-
FMC_CLK high to FMC_Ax invalid
(x =16…25)
Tfmc_ker_ck
Ns
td(CLKL-NWEL)
t(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
FMC_CLK low to to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
1.5
-
Tfmc_ker_ck +0.5
-
2.5
-
0
FMC_A/D[15:0] valid data after FMC_CLK
low
td(CLKL-DATA)
-
2.5
td(CLKL-NBLL)
td(CLKH-NBLH)
tsu(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
-
2
-
Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Figure 34. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
t
t
h(CLKH-DV)
su(DV-CLKH)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
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Table 87. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
-
t(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
1
FMC_CLK high to FMC_NEx high
(x= 0…2)
td(CLKH-NExH)
2Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
0.5
-
0
FMC_CLK low to FMC_Ax valid
(x=16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2
-
FMC_CLK high to FMC_Ax invalid
(x=16…25)
2Tfmc_ker_ck
ns
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
-
1.5
-
2Tfmc_ker_ck-0.5
FMC_D[15:0] valid data before FMC_CLK
high
tsu(DV-CLKH)
th(CLKH-DV)
2
1
-
-
FMC_D[15:0] valid data after FMC_CLK
high
t(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Figure 35. Synchronous non-multiplexed PSRAM write timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKL-NExL)
FMC_NEx
d(CLKH-NExH)
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FMC_NADV
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
FMC_A[25:0]
FMC_NWE
td(CLKH-NWEH)
d(CLKL-NWEL)
t
t
d(CLKL-Data)
d(CLKL-Data)
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FMC_NBL
t
t
d(CLKH-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
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Table 88. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
t(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
2
FMC_CLK high to FMC_NEx high
(x= 0…2)
t(CLKH-NExH)
Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
0.5
-
0
FMC_CLK low to FMC_Ax valid
(x=16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2.
-
FMC_CLK high to FMC_Ax invalid
(x=16…25)
Tfmc_ker_ck
ns
td(CLKL-NWEL)
td(CLKH-NWEH)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
-
1.5
-
Tfmc_ker_ck+1
FMC_D[15:0] valid data after FMC_CLK
low
td(CLKL-Data)
-
3.5
td(CLKL-NBLL)
td(CLKH-NBLH)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
-
2
-
Tfmc_ker_ck+1
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
168/242
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Electrical characteristics
NAND controller waveforms and timings
Figure 36 through Figure 39 represent synchronous waveforms, and Table 89 and Table 90
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x01
COM.FMC_WaitSetupTime = 0x03
COM.FMC_HoldSetupTime = 0x02
COM.FMC_HiZSetupTime = 0x01
ATT.FMC_SetupTime = 0x01
ATT.FMC_WaitSetupTime = 0x03
ATT.FMC_HoldSetupTime = 0x02
ATT.FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
Capacitive load C = 30 pF
L
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 36. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
t
th(NOE-ALE)
d(ALE-NOE)
FMC_NOE (NRE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
MS32767V1
DS12930 Rev 1
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221
Electrical characteristics
STM32H747xI/G
Figure 37. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NWE-ALE)
d(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NWE-D)
v(NWE-D)
MS32768V1
Figure 38. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NOE-ALE)
d(ALE-NOE)
FMC_NWE
FMC_NOE
t
w(NOE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
MS32769V1
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Electrical characteristics
Figure 39. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
t
h(NOE-ALE)
d(ALE-NOE)
w(NWE)
FMC_NWE
FMC_N OE
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FMC_D[15:0]
MS32770V1
(1)
Table 89. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
Min
Max
4Tfmc_ker_ck+0.5
Unit
tw(N0E)
FMC_NOE low width
4Tfmc_ker_ck – 0.5
FMC_D[15-0] valid data before
FMC_NOE high
tsu(D-NOE)
th(NOE-D)
8
0
-
FMC_D[15-0] valid data after
FMC_NOE high
ns
-
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid
1. Guaranteed by characterization results.
-
3Tfmc_ker_ck +1
-
4Tfmc_ker_ck –2
(1)
Table 90. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
Min
Max
Unit
tw(NWE)
FMC_NWE low width
4Tfmc_ker_ck – 0.5
4Tfmc_ker_ck +0.5
FMC_NWE low to FMC_D[15-0]
valid
tv(NWE-D)
th(NWE-D)
0
-
FMC_NWE high to FMC_D[15-0]
invalid
2Tfmc_ker_ck – 0.5
5Tfmc_ker_ck – 1
-
-
ns
FMC_D[15-0] valid before
FMC_NWE high
td(D-NWE)
-
FMC_ALE valid before FMC_NWE
low
td(ALE-NWE)
th(NWE-ALE)
3Tfmc_ker_ck +0.5
-
FMC_NWE high to FMC_ALE
invalid
2Tfmc_ker_ck – 1
1. Guaranteed by characterization results.
DS12930 Rev 1
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Electrical characteristics
STM32H747xI/G
SDRAM waveforms and timings
In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
•
•
•
For 2.7 V<V <3.6 V: FMC_CLK =110 MHz at 20 pF
DD
For 1.8 V<V <1.9 V: FMC_CLK =100 MHz at 20 pF
DD
For 1.62 V< <1.8 V, FMC_CLK =100 MHz at 15 pF
DD
Figure 40. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
th(SDCLKL_NCAS)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
td(SDCLKL_NCAS)
FMC_SDNWE
FMC_D[31:0]
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Data1 Data2 Datai
Datan
MS32751V2
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Electrical characteristics
(1)
Table 91. SDRAM read timings
Symbol
Parameter
Min
Max
Unit
2Tfmc_ker_ck
+0.5
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck – 1
tsu(SDCLKH _Data)
th(SDCLKH_Data)
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2
1
-
-
td(SDCLKL_Add)
-
1.5
1.5
-
td(SDCLKL- SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0.5
-
1
0.5
-
-
0.5
-
0
1. Guaranteed by characterization results.
(1)
Table 92. LPSDR SDRAM read timings
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
tsu(SDCLKH_Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
2
1.5
-
-
-
2.5
2.5
-
td(SDCLKL_SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0
-
0.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
DS12930 Rev 1
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Electrical characteristics
STM32H747xI/G
Figure 41. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
th(SDCLKL_NCAS)
th(SDCLKL_NWE)
td(SDCLKL_NCAS)
td(SDCLKL_NWE)
td(SDCLKL_Data)
Data1
Data2
Datai
Datan
FMC_D[31:0]
td(SDCLKL_NBL)
FMC_NBL[3:0]
th(SDCLKL_Data)
MS32752V2
(1)
Table 93. SDRAM Write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
td(SDCLKL _Data
th(SDCLKL _Data)
td(SDCLKL_Add)
)
-
0
1
-
-
1.5
1.5
-
td(SDCLKL_SDNWE)
th(SDCLKL_SDNWE)
td(SDCLKL_ SDNE)
th(SDCLKL-_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
td(SDCLKL_SDNCAS)
-
0.5
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
1.5
-
0.5
-
1
0.5
-
-
1
0.5
-
1. Guaranteed by characterization results.
174/242
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STM32H747xI/G
Electrical characteristics
(1)
Table 94. LPSDR SDRAM Write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
td(SDCLKL _Data
)
-
0
-
2.5
-
th(SDCLKL _Data)
td(SDCLKL_Add)
2.5
2.5
-
td(SDCLKL-SDNWE)
th(SDCLKL-SDNWE)
td(SDCLKL- SDNE)
th(SDCLKL- SDNE)
td(SDCLKL-SDNRAS)
th(SDCLKL-SDNRAS)
td(SDCLKL-SDNCAS)
td(SDCLKL-SDNCAS)
-
0
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
3
0
-
-
1.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
6.3.21
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 95 and Table 96 for QUADSPI
are derived from tests performed under the ambient temperature, f frequency and V
AHB
DD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics.
The following table summarizes the parameters measured in SDR mode.
(1)
Table 95. QUADSPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7<VDD<3.6 V
CL = 20 pF
-
-
133
QUADSPI clock
frequency
Fck11/TCK
MHz
1.62<VDD<3.6 V
CL = 15 pF
-
-
100
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Electrical characteristics
STM32H747xI/G
(1)
Table 95. QUADSPI characteristics in SDR mode (continued)
Symbol
tw(CKH)
tw(CKL)
tw(CKH)
Parameter
Conditions
Min
TCK/2–0.5
Typ
Max
TCK/2
Unit
QUADSPI clock high
and low time Even
division
-
-
-
PRESCALER[7:0] =
n = 0,1,3,5...
TCK/2
TCK/2+0.5
(n/2)*TCK/ (n+1)
(n/2)*TCK/(n+1)-0.5
QUADSPI clock high
and low time Odd
division
PRESCALER[7:0] =
n = 2,4,6,8...
(n/2+1)*TCK
(n+1)+0.5
/
tw(CKL)
(n/2+1)*TCK/(n+1)
-
ns
ts(IN)
th(IN)
tv(OUT)
th(OUT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
1
3.5
-
-
-
-
-
-
-
-
1
-
2
-
0
1. Guaranteed by characterization results.
The following table summarizes the parameters measured in DDR mode.
(1)
Table 96. QUADSPI characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7<VDD<3.6 V
CL = 20 pF
-
-
100
Fck11/TCK
QUADSPI clock frequency
MHz
1.62<VDD<3.6 V
CL = 15 pF
-
-
100
tw(CKH)
tw(CKL)
TCK/2–0.5
TCK/2
-
-
TCK/2
QUADSPI clock high and PRESCALER[7:0] =
low time Even division n = 0,1,3,5...
TCK/2+0.5
(n/2)*TCK
(n+1)-0.5
/
(n/2)*TCK
(n+1)
/
tw(CKH)
-
-
QUADSPI clock high and PRESCALER[7:0] =
low time Odd division
n = 2,4,6,8...
(n/2+1)*TCK
/
(n/2+1)*TCK
(n+1)+0.5
/
tw(CKL)
(n+1)
tsr(IN), tsf(IN)
Data input setup time
Data input hold time
-
-
1.5
3.5
-
-
-
-
-
thr(IN),thf(IN)
ns
DHHC=0
DHHC=1
5
6
tvr(OUT)
,
Data output valid time
Data output hold time
tvf(OUT)
-
3
TCK/4+1
TCK/4+2
PRESCALER[7:0] =
1,2…
DHHC=0
-
-
-
-
thr(OUT)
,
DHHC=1
thf(OUT)
TCK/4
PRESCALER[7:0]=1
,2…
1. Guaranteed by characterization results.
176/242
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STM32H747xI/G
Electrical characteristics
Figure 42. Quad-SPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
Data input
D0
D1
D2
ts(IN)
th(IN)
D0
D1
D2
MSv36878V1
Figure 43. Quad-SPI timing diagram - DDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
tsr(IN)thr(IN)
D5
tsf(IN) thf(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv36879V1
6.3.22
Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 97 for Delay Block are derived
from tests performed under the ambient temperature, f frequency and VDD supply
rcc_c_ck
voltage summarized in Table 22: General operating conditions, with the following
configuration:
Table 97. Delay Block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tinit
t∆
Initial delay
Unit Delay
-
-
1400
35
2200
40
2400
45
ps
-
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221
Electrical characteristics
STM32H747xI/G
6.3.23
16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 98 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 22: General operating conditions.
(1)(2)
Table 98. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage for ADC
ON
V
-
1.62
-
3.6
V
DDA
Positive reference
voltage
V
-
-
1.62
-
V
V
V
REF+
DDA
Negative
reference voltage
V
V
SSA
REF-
BOOST = 11
BOOST = 10
BOOST = 01
BOOST = 00
0.12
0.12
0.12
-
-
-
-
-
50
25
ADC clock
frequency
f
1.62 V ≤ VDDA ≤ 3.6 V
MHz
ADC
12.5
6.25
Resolution = 16 bits,
>2.5 V
f
f
=36 MHz
SMP = 1.5
-
-
3.60
ADC
V
DDA
T
= 90 °C
= 125 °C
= 90 °C
J
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 16 bits,
=37 MHz
= 50 MHz
= 50 MHz
= 50 MHz
= 50 MHz
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 1.5
SMP = 1.5
-
-
-
-
-
-
-
-
-
-
3.35
5.00
5.50
7.10
8.30
ADC
Sampling rate for
f
f
f
f
ADC
ADC
ADC
ADC
(4)
Direct channels
T
J
f
f
=32 MHz
SMP = 2.5
-
-
2.90
ADC
ADC
V
>2.5 V
DDA
T
J
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 16 bits
resolution = 14 bits
resolution = 12 bits
resolution = 10 bits
resolution = 8 bits
=31 MHz
= 33 MHz
= 39 MHz
= 48 MHz
= 50 MHz
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.80
3.30
4.30
6.00
7.10
(3)
f
MSps
s
Sampling rate for
Fast channels
f
f
f
f
ADC
ADC
ADC
ADC
T
= 125 °C
= 90 °C
J
T
J
Sampling rate for
Slow channels
f
= 10 MHz
SMP = 1.5
1.00
10
ADC
T
= 125 °C
J
External trigger
period
1/
t
Resolution = 16 bits
-
-
-
TRIG
f
ADC
Conversion
voltage range
(5)
AIN
V
-
-
0
V
REF+
V
Common mode
input voltage
V
/2
V
/
V
/2
REF
REF
− 10%
REF
2
V
V
CMIV
+ 10%
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Electrical characteristics
(1)(2)
Table 98. ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resolution = 16 bits, T = 125 °C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
170
435
J
Resolution = 14 bits, T = 125 °C
-
-
-
-
J
External input
impedance
(6)
R
Resolution = 12 bits, T =125 °C
1150
5650
26500
ꢁ
AIN
J
Resolution = 10 bits, T = 125 °C
J
Resolution = 8 bits, T = 125 °C
J
Internal sample
and hold
capacitor
C
-
-
-
4
5
-
-
10
-
pF
us
ADC
t
ADC LDO startup
time
ADCVREG
_STUP
-
conver
sion
cycle
ADC Power-up
time
t
LDO already started
1
STAB
Offset and
linearity
calibration time
t
-
-
165010
1280
-
-
-
-
1/f
1/f
CAL
ADC
ADC
t
Offset calibration
time
OFF_
CAL
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
-
1.5
2
-
2.5
2.5
Trigger
conversion
latency regular
and injected
channels without
conversion abort
-
t
1/f
1/f
LATR
ADC
-
-
2.5
-
2.5
-
-
2.25
3.5
3
-
Trigger
conversion
latency regular
injected channels
aborting a regular
conversion
3.5
t
LATRINJ
ADC
-
-
3.5
-
-
3.25
810.5
t
Sampling time
1.5
-
1/f
1/f
S
ADC
ADC
Total conversion
time (including
sampling time)
ts + 0.5
+ N/2
t
Resolution = N bits
-
-
CONV
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Electrical characteristics
STM32H747xI/G
(1)(2)
Table 98. ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resolution = 16 bits, f
Resolution = 14 bits, f
Resolution = 12 bits, f
=25 MHz
=30 MHz
=40 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1440
1350
990
1080
810
585
630
432
315
360
270
225
720
675
495
540
405
292.5
315
216
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC
ADC
ADC
ADCconsumption
on V
,
DDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BOOST=11,
Differential mode
ADCconsumption
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
on V
DDA
BOOST=10,
Differential mode
f
=25 MHz
ADC
I
_
D
DDA
(ADC)
ADCconsumption
on V
DDA
BOOST=01,
Differential mode
f
=12.5 MHz
ADC
ADCconsumption
on V
DDA
BOOST=00,
Differential mode
f
=6.25 MHz
ADC
ADCconsumption
on V
Resolution = 16 bits, f
=25 MHz
ADC
DDA
Resolution = 14 bits, f
Resolution = 12 bits, f
=30 MHz
=40 MHz
BOOST=11,
Single-ended
mode
ADC
ADC
µA
ADCconsumption
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
on V
DDA
BOOST=10,
Singl-ended mode
f
=25 MHz
ADC
I
_
(
DDA SE
ADCconsumption
on V
ADC)
DDA
BOOST=01,
Single-ended
mode
Resolution = 12 bits
-
-
-
157.5
-
f
=12.5 MHz
ADC
ADCconsumption
on V
BOOST=00,
Single-ended
mode
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
180
135
-
-
DDA
Resolution = 12 bits
-
-
-
112.5
-
f
=6.25 MHz
ADC
f
=50 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
220
180
120
80
-
-
-
-
-
ADC
f
=25 MHz
ADC
I
ADCconsumption
on V
DD
f
f
=12.5 MHz
=6.25 MHz
ADC
ADC
(ADC)
DD
f
=3.125 MHz
ADC
1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid for UFBGA169 and one ADC. The values for other packages and multiple ADCs may be different.
4. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
5. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA
.
6. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.
180/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
(1)(2)
AIN
Table 99. Minimum sampling time vs R
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
16 bits
47
47
7.37E-08
6.29E-08
6.84E-08
7.80E-08
9.86E-08
1.32E-07
5.32E-08
5.74E-08
6.58E-08
8.37E-08
1.11E-07
1.56E-07
2.16E-07
3.01E-07
4.34E-08
4.68E-08
5.35E-08
6.68E-08
8.80E-08
1.24E-07
1.69E-07
2.38E-07
3.45E-07
5.15E-07
7.42E-07
1.10E-06
1.14E-07
9.74E-08
1.02E-07
1.12E-07
1.32E-07
1.61E-07
8.00E-08
8.50E-08
9.31E-08
1.10E-07
1.34E-07
1.78E-07
2.39E-07
3.29E-07
6.51E-08
6.89E-08
7.55E-08
8.77E-08
1.08E-07
1.43E-07
1.89E-07
2.60E-07
3.66E-07
5.35E-07
7.75E-07
1.14E-06
1.72E-07
1.55E-07
1.58E-07
1.62E-07
1.80E-07
2.01E-07
1.29E-07
1.32E-07
1.40E-07
1.51E-07
1.73E-07
2.14E-07
2.68E-07
3.54E-07
1.08E-07
1.11E-07
1.16E-07
1.26E-07
1.40E-07
1.71E-07
2.13E-07
2.80E-07
3.84E-07
5.48E-07
7.78E-07
1.14E-06
68
14 bits
100
150
220
47
68
100
150
220
330
470
680
47
12 bits
68
100
150
220
330
470
680
1000
1500
2200
3300
10 bits
DS12930 Rev 1
181/242
221
Electrical characteristics
STM32H747xI/G
(1)(2)
Table 99. Minimum sampling time vs R
(continued)
AIN
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
47
68
3.32E-08
3.59E-08
4.10E-08
5.06E-08
6.61E-08
9.17E-08
1.24E-07
1.74E-07
2.53E-07
3.73E-07
5.39E-07
8.02E-07
1.13E-06
1.62E-06
2.36E-06
3.50E-06
5.10E-08
5.35E-08
5.83E-08
6.76E-08
8.22E-08
1.08E-07
1.40E-07
1.91E-07
2.70E-07
3.93E-07
5.67E-07
8.36E-07
1.18E-06
1.69E-06
2.47E-06
3.69E-06
8.61E-08
8.83E-08
9.22E-08
9.95E-08
1.11E-07
1.32E-07
1.63E-07
2.12E-07
2.85E-07
4.05E-07
5.75E-07
8.38E-07
1.18E-06
1.68E-06
2.45E-06
3.65E-06
100
150
220
330
470
680
8 bits
1000
1500
2200
3300
4700
6800
10000
15000
1. Guaranteed by design.
2. Data valid at up to 125 °C, with a 47 pF PCB capacitor, and VDDA=1.6 V.
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to PF3, PF5, PF7, PF9, PA6, PC4, PB1, PF11 and PF13.
5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.
182/242
DS12930 Rev 1
STM32H747xI/G
Symbol
Electrical characteristics
(1)(2)
Table 100. ADC accuracy
Conditions(3)
Parameter
Min
Typ
Max
Unit
Single ended
Differential
-
-
-
-
-
+10/–20
±15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Direct
channel
Single ended
Differential
+10/–20
±15
ET
Total undadjusted error
Fast channel
Single ended
Differential
±10
Slow
channel
±10
EO
EG
Offset error
Gain error
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±10
±15
LSB
Single ended
Differential
+3/–1
+4.5/–1
±11
ED
Differential linearity error
Integral linearity error
Effective number of bits
Single ended
Direct
channel
Differential
Single ended
Differential
±7
±13
EL
Fast channel
±7
Single ended
Differential
±10
Slow
channel
±6
Single ended
12.2
13.2
75.2
81.2
77.0
81.0
87
ENOB
SINAD
SNR
Bits
dB
Differential
Single ended
Differential
Signal-to-noise and
distortion ratio
Single ended
Differential
Signal-to-noise ratio
Single ended
Differential
THD
Total harmonic distortion
90
1. Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V and BOOST=11.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
Section 6.3.17 does not affect the ADC accuracy.
and ΣI
in
INJ(PIN)
INJ(PIN)
DS12930 Rev 1
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221
Electrical characteristics
STM32H747xI/G
Figure 44. ADC accuracy characteristics (12-bit resolution)
V
V
DDA
4096
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
E
G
4095
4094
4093
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
E
O
L
E
D
1L SB
IDEAL
7
0
V
1
2
3
456
4093 4094 4095 4096
V
DDA
SSA
ai14395c
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 45. Typical connection diagram using the ADC
STM32
V
DD
Sample and hold ADC
V
T
converter
0.6 V
(1)
AIN
(1)
R
R
ADC
AINx
12-bit
converter
V
0.6 V
T
V
AIN
C
(1)
ADC
C
parasitic
I
1 μA
L
ai17534b
1. Refer to Table 98 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
184/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 46 or Figure 47,
depending on whether V is connected to V or not. The 100 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 46. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM32
(1)
VREF+
1 μF // 100 nF
VDDA
1 μF // 100 nF
(1)
VSSA/VREF+
MSv50648V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA
.
Figure 47. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32
(1)
VREF+/VDDA
1 μF // 100 nF
(1)
VREF-/VSSA
MSv50649V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA
.
DS12930 Rev 1
185/242
221
Electrical characteristics
STM32H747xI/G
6.3.24
DAC characteristics
(1)(2)
Table 101. DAC characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
1.8
3.3
-
3.6
VREF+
Positive reference voltage
-
-
1.80
VDDA
V
Negative reference
voltage
VREF-
-
VSSA
-
-
-
connected
to VSSA
5
DAC output buffer
ON
RL
RO
Resistive Load
connected
to VDDA
kꢁ
25
10.3
-
-
13
-
-
Output Impedance
DAC output buffer OFF
16
1.6
VDD
2.7 V
=
=
Output impedance
sample and hold mode,
output buffer ON
DAC output buffer
ON
RBON
kꢁ
kꢁ
VDD
-
-
-
-
-
-
2.6
2.0 V
VDD
=
17.8
18.7
Output impedance
sample and hold mode,
output buffer OFF
2.7 V
DAC output buffer
OFF
RBOFF
VDD
=
2.0 V
CL
DAC output buffer OFF
Sample and Hold mode
-
-
-
50
1
pF
µF
Capacitive Load
CSH
0.1
VDDA
−0.2
DAC output buffer ON
DAC output buffer OFF
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
0
-
-
VREF+
±0.5 LSB
2.05
1.97
1.67
1.66
1.65
-
-
-
-
-
Settling time (full scale:
for a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
±1 LSB
±2 LSB
±4 LSB
±8 LSB
-
Normal mode, DAC
output buffer ON,
CL ≤ 50 pF,
-
tSETTLING
µs
RL ≥ 5 ㏀
-
-
Normal mode, DAC output buffer
OFF, ±1LSB CL=10 pF
-
-
1.7
5
2
Wakeup time from off
state (setting the ENx bit
in the DAC Control
register) until the final
value of ±1LSB is reached
Normal mode, DAC output buffer
7.5
ON, CL ≤ 50 pF, RL = 5 ㏀
(3)
tWAKEUP
µs
Normal mode, DAC output buffer
2
5
OFF, CL ≤ 10 pF
DC VDDA supply rejection Normal mode, DAC output buffer
PSRR
-
−80
−28
dB
ratio
ON, CL ≤ 50 pF, RL = 5 ㏀
186/242
DS12930 Rev 1
STM32H747xI/G
Symbol
Electrical characteristics
(1)(2)
Table 101. DAC characteristics
Parameter Conditions
Sampling time in Sample
(continued)
Min
Typ
Max
Unit
MODE<2:0>_V12=100/101
(BUFFER ON)
-
-
0.7
2.6
and Hold mode
ms
CL=100 nF
MODE<2:0>_V12=110
(BUFFER OFF)
11.5
0.3
18.7
0.6
(code transition between
the lowest input code and
the highest input code
when DAC_OUT reaches
the ±1LSB final value)
tSAMP
MODE<2:0>_V12=111
-
µs
(INTERNAL BUFFER OFF)
Internal sample and hold
capacitor
CIint
-
1.8
2.2
-
2.6
-
pF
µs
Middle code offset trim
time
Minimum time to verify the each
code
tTRIM
50
VREF+ = 3.6 V
VREF+ = 1.8 V
-
-
850
425
-
-
Middle code offset for 1
trim code step
Voffset
µV
No load,
middle
code
-
-
-
-
-
-
-
360
490
-
-
-
-
-
-
-
DAC output buffer
(0x800)
ON
No load,
worst code
(0xF1C)
DAC quiescent
IDDA(DAC)
consumption from VDDA
No load,
DAC output buffer middle/wor
20
OFF
st code
(0x800)
360*TON
/
Sample and Hold mode,
CSH=100 nF
(TON+TOFF
)
(4)
No load,
middle
code
µA
170
170
160
DAC output buffer
ON
(0x800)
No load,
worst code
(0xF1C)
No load,
DAC output buffer middle/wor
DAC consumption from
VREF+
IDDV(DAC)
OFF
st code
(0x800)
170*TON
/
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code)
-
-
(TON+TOFF
)
)
-
-
(4)
160*TON
/
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code)
(TON+TOFF
(4)
1. Guaranteed by design unless otherwise specified.
DS12930 Rev 1
187/242
221
Electrical characteristics
STM32H747xI/G
2. TBD stands for “to be defined”.
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
(1)
Table 102. DAC accuracy
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON
DAC output buffer OFF
10 bits
−2
−2
-
-
-
-
2
2
-
Differential non
linearity(2)
DNL
-
LSB
-
Monotonicity
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀
−4
-
4
INL
Integral non linearity(3)
LSB
DAC output buffer OFF,
−4
-
-
4
CL ≤ 50 pF, no RL
DAC output
buffer ON,
CL ≤ 50 pF,
RL ≥ 5 ㏀
V
REF+ = 3.6 V
-
±15
Offset error at code
0x800 (3)
VREF+ = 1.8 V
-
-
-
-
±30
±8
Offset
LSB
DAC output buffer OFF,
CL ≤ 50 pF, no RL
Offset error at code
0x001(4)
DAC output buffer OFF,
Offset1
-
-
-
-
±5
±6
LSB
LSB
CL ≤ 50 pF, no RL
DAC output
VREF+ = 3.6 V
Offset error at code
0x800 after factory
calibration
buffer ON,
OffsetCal
CL ≤ 50 pF,
RL ≥ 5 ㏀
VREF+ = 1.8 V
-
-
±7
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀
-
-
-
-
-
±1
±1
-
Gain
SNR
Gain error(5)
%
DAC output buffer OFF,
CL ≤ 50 pF, no RL
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
67.8
Signal-to-noise ratio(6)
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL,1 kHz, BW =
500 KHz
-
67.8
-
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
-
-
-
-
−78.6
−78.6
67.5
-
-
-
-
Total harmonic
distortion(6)
THD
dB
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
Signal-to-noise and
distortion ratio(6)
SINAD
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
67.5
188/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
(1)
Table 102. DAC accuracy (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON,
-
10.9
-
CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
Effective number of
bits
ENOB
bits
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
-
10.9
-
1. Guaranteed by characterization.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5dBFS with Fsampling=1 MHz.
Figure 48. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
DAC_OUTx
12-bit
digital to
analog
converter
C
L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DS12930 Rev 1
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221
Electrical characteristics
STM32H747xI/G
6.3.25
Voltage reference buffer characteristics
(1)
Table 103. VREFBUF characteristics
Conditions
Symbol
Parameter
Min
2.8
Typ
Max
3.6
Unit
VSCALE = 000
3.3
VSCALE = 001
Normal mode
2.4
-
3.6
VSCALE = 010
2.1
-
3.6
VSCALE = 011
VSCALE = 000
1.8
-
3.6
VDDA
Analog supply voltage
1.62
1.62
1.62
1.62
2.498
2.046
1.801
-
2.80
2.40
2.10
1.80
2.5035
2.052
1.806
1.504
VSCALE = 001
Degraded mode
-
-
VSCALE = 010
VSCALE = 011
VSCALE = 000
-
2.5
2.049
1.804
V
VSCALE = 001
Normal mode
VSCALE = 010
VSCALE = 011 1.4995 1.5015
VDDA
150 mV
−
Voltage Reference
Buffer Output, at 30 °C,
Iload= 100 µA
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
-
-
-
-
VDDA
VDDA
VDDA
VDDA
VREFBUF
_OUT
VDDA
150 mV
−
Degraded mode(2)
VDDA
150 mV
−
VDDA
150 mV
−
TRIM
CL
Trim step resolution
Load capacitor
-
-
-
-
-
±0.05
1
±0.1
1.50
%
0.5
uF
Equivalent Serial
Resistor of CL
esr
-
-
-
-
-
-
2
Ω
Iload
Static load current
-
-
-
-
4
-
mA
I
load = 500 µA
Iload = 4 mA
200
100
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
ppm/V
-
ppm/
mA
Iload_reg
Load regulation
500 µA ≤ ILOAD ≤ 4 mA Normal Mode
−40 °C < TJ < +125 °C
-
-
50
-
-
Tcoeff
VREFINT
+ 100
ppm/
°C
Tcoeff
Temperature coefficient
DC
-
-
-
-
60
40
-
-
PSRR
Power supply rejection
dB
100KHz
190/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
(1)
Table 103. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
CL=0.5 µF
Min
Typ
300
500
650
Max
Unit
-
-
-
-
-
-
-
-
-
tSTART
Start-up time
CL=1 µF
µs
CL=1.5 µF
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
IINRUSH
-
-
8
-
mA
µA
ILOAD = 0 µA
-
-
-
-
-
-
15
16
32
25
30
50
VREFBUF
consumption from
VDDA
IDDA(VRE
ILOAD = 500 µA
FBUF)
ILOAD = 4 mA
1. Guaranteed by design.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
6.3.26
Temperature sensor characteristics
Table 104. Temperature sensor characteristics
Symbol
Parameter
Min Typ Max Unit
(1)
TL
VSENSE linearity with temperature
-
-
-
3
°C
mV/°C
V
Avg_Slope(2) Average slope
2
-
(3)
V30
Voltage at 30°C ± 5 °C
-
0.62
-
25.2
-
tstart_run
Startup time in Run mode (buffer startup)
ADC sampling time when reading the temperature
Sensor consumption
-
-
-
µs
(1)
tS_temp
9
-
(1)
Isens
0.18 0.31
3.8 6.5
µA
(1)
Isensbuf
Sensor buffer consumption
-
1. Guaranteed by design.
2. Guaranteed by characterization.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 105. Temperature sensor calibration values
Symbol
Parameter
Memory address
Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V
TS_CAL1
0x1FF1 E820 -0x1FF1 E821
Temperature sensor raw data acquired value at
110 °C, VDDA=3.3 V
TS_CAL2
0x1FF1 E840 - 0x1FF1 E841
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6.3.27
Temperature and V
monitoring
BAT
Table 106. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
26
4
-
Kꢁ
-
Ratio on VBAT measurement
Error on Q
-
-
Er(1)
–10
-
+10
%
µs
(1)
tS_vbat
ADC sampling time when reading VBAT input
High supply monitoring
9
-
-
-
-
-
VBAThigh
VBATlow
3.55
1.36
V
Low supply monitoring
-
1. Guaranteed by design.
Table 107. V
charging characteristics
BAT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBRS in PWR_CR3= 0
VBRS in PWR_CR3= 1
-
5
-
-
RBC
Battery charging resistor
Kꢁ
1.5
Table 108. Temperature monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
TEMPhigh
TEMPlow
High temperature monitoring
Low temperature monitoring
-
-
117
-
-
°C
–25
6.3.28
Voltage booster for analog switch
(1)
Table 109. Voltage booster for analog switch characteristics
Symbol
Parameter
Supply voltage
Condition
Min Typ Max Unit
VDD
-
1.62 2.6 3.6
V
Booster startup time
-
-
-
-
-
-
-
50
µs
tSU(BOOST)
1.62 V ≤ VDD ≤ 2.7 V
2.7 V < VDD < 3.6 V
125
250
Booster consumption
µA
IDD(BOOST)
1. Guaranteed by characterization results.
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6.3.29
Comparator characteristics
(1)
Table 110. COMP characteristics
Conditions
Symbol
VDDA
Parameter
Min
Typ
Max
Unit
Analog supply voltage
-
-
1.62
3.3
3.6
Comparator input voltage
range
VIN
0
-
VDDA
V
(2)
VBG
VSC
Scaler input voltage
Scaler offset voltage
-
-
-
-
±5
0.2
0.8
140
2
±10
0.3
1
mV
µA
µs
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
Scaler static consumption
from VDDA
IDDA(SCALER)
-
tSTART_SCALER Scaler startup time
-
250
5
High-speed mode
Medium mode
-
Comparator startup time to
reach propagation delay
tSTART
-
5
20
80
80
1.2
7
µs
specification
Ultra-low-power mode
High-speed mode
Medium mode
-
15
50
0.5
2.5
50
0.5
2.5
±5
0
-
ns
µs
Propagation delay for
200 mV step with 100 mV
overdrive
-
Ultra-low-power mode
High-speed mode
Medium mode
-
(3)
tD
-
120
1.2
7
ns
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
-
µs
Ultra-low-power mode
Full common mode range
No hysteresis
-
Voffset
Comparator offset error
-
±20
-
mV
-
Low hysteresis
5
8
16
-
10
20
30
400
22
37
52
600
Vhys
Comparator hysteresis
mV
nA
Medium hysteresis
High hysteresis
Static
Ultra-low-
With 50 kHz
±100 mV overdrive
square signal
power mode
-
-
-
-
-
800
5
-
Static
7
Comparator consumption
from VDDA
With 50 kHz
I
DDA(COMP)
Medium mode
±100 mV overdrive
square signal
6
-
100
-
µA
Static
70
75
High-speed
mode
With 50 kHz
±100 mV overdrive
square signal
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 29: Embedded reference voltage.
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3. Guaranteed by characterization results.
6.3.30
Operational amplifier characteristics
Table 111. Operational amplifier characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
Range
VDDA
CMIR
-
2
3.3
3.6
V
Common Mode Input
Range
-
0
-
-
VDDA
±1.5
±2.5
-
25°C, no load on output
-
-
VIOFFSET
Input offset voltage
mV
All voltages and
temperature, no load
-
ΔVIOFFSET
Input offset voltage drift
-
-
-
±3.0
μV/°C
Offset trim step at low
common input voltage
TRIMOFFSETP
-
-
1.1
1.1
1.5
1.5
TRIMLPOFFSETP
(0.1*VDDA
)
mV
Offset trim step at high
common input voltage
TRIMOFFSETN
-
TRIMLPOFFSETN
(0.9*VDDA
)
ILOAD
ILOAD_PGA
CLOAD
Drive current
Drive current in PGA mode
Capacitive load
-
-
-
-
-
-
-
-
-
500
270
50
μA
pF
dB
Common mode rejection
ratio
CMRR
PSRR
-
-
80
66
-
-
CLOAD ≤ 50pf /
RLOAD ≥ 4 kꢁ(1) at 1 kHz,
Vcom=VDDA/2
Power supply rejection
ratio
50
4
dB
Gain bandwidth for high
supply range
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
GBW
SR
7.3
12.3
MHz
V/µs
dB
Normal mode
-
-
3
-
-
Slew rate (from 10% and
90% of output voltage)
High-speed mode
30
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
AO
Open loop gain
59
90
129
φm
Phase margin
Gain margin
-
-
-
-
55
12
-
-
°
GM
dB
I
load=max or RLOAD=min,
Input at VDDA
VDDA
−100 mV
VOHSAT
High saturation voltage
Low saturation voltage
-
-
-
mV
Iload=max or RLOAD=min,
Input at 0 V
VOLSAT
-
100
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Symbol
Electrical characteristics
Table 111. Operational amplifier characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kꢁ,
-
0.8
3.2
mode
follower
configuration
Wake up time from OFF
state
tWAKEUP
µs
CLOAD ≤ 50pf,
RLOAD ≥ 4 kꢁ,
follower
High
speed
mode
-
0.9
2.8
configuration
PGA gain = 2
−1
−2
−2.5
−3
−1
−1
−2
−3
−1
−3
−3.5
−4
-
-
1
2
2.5
3
1
1
2
3
1
3
3.5
4
-
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA Gain=2
PGA Gain=4
PGA Gain=8
PGA Gain=16
PGA Gain = -1
PGA Gain = -3
PGA Gain = -7
PGA Gain = -15
-
Non inverting gain error
value
-
-
-
-
PGA gain
Inverting gain error value
%
-
-
-
-
External non-inverting gain
error value
-
-
10/10
30/10
70/10
150/10
10/10
30/10
70/10
150/10
R2/R1 internal resistance
values in non-inverting
PGA mode(2)
-
-
-
-
-
-
kꢁ/
kꢁ
Rnetwork
-
-
R2/R1 internal resistance
values in inverting PGA
mode(2)
-
-
-
-
-
-
Resistance variation (R1
or R2)
Delta R
-
−15
-
15
%
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Table 111. Operational amplifier characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Gain=2
Gain=4
-
-
-
-
-
-
-
-
GBW/2
GBW/4
GBW/8
GBW/16
5.00
-
-
-
-
-
-
-
-
PGA bandwidth for
different non inverting gain
MHz
Gain=8
Gain=16
Gain = -1
Gain = -3
Gain = -7
Gain = -15
PGA BW
3.00
PGA bandwidth for
different inverting gain
MHz
1.50
0.80
at
1 KHz
-
-
-
140
55
-
-
output loaded
with 4 kꢁ
nV/√
Hz
en
Voltage noise density
at
10 KHz
Normal
mode
570
1000
no Load,
quiescent mode,
follower
OPAMP consumption from
VDDA
IDDA(OPAMP)
µA
High-
speed
mode
-
610
1200
1. RLOAD is the resistive load connected to VSSA or to VDDA.
2. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
6.3.31
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 112 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 22: General operating conditions.
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).
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Table 112. DFSDM measured timing 1.62-3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DFSDM
clock
fDFSDMCLK
1.62 < VDD < 3.6 V
-
-
133
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
-
-
-
-
-
-
-
-
20
20
20
20
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
fCKIN
(1/TCKIN
Input clock
frequency
MH
z
)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]¹0),
2.7 < VDD < 3.6 V
Output clock
frequency
fCKOUT
1.62 < VDD < 3.6 V
1.62 < VDD < 3.6 V
-
-
20
55
Output clock
frequency
duty cycle
DuCyCKOU
45
50
%
T
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Input clock
high and low
time
twh(CKIN)
twl(CKIN)
TCKIN/2-0.5
TCKIN/2
-
-
-
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Data input
setup time
tsu
1.5
0.5
-
-
-
ns
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Data input
hold time
th
Manchester Manchester mode (SITP[1:0]=2,3),
data period
(recovered
clock period)
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
(CKOUTDIV+1)
* TDFSDMCLK
(2*CKOUTDIV)
* TDFSDMCLK
TManchester
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Figure 49. Channel transceiver timing diagrams
(SPICKSEL=0)
tr
tf
twl
twh
tsu
th
SITP = 00
SITP = 01
tsu
th
SPICKSEL=3
SPICKSEL=2
SPICKSEL=1
tr
tf
twl
twh
tsu
th
SITP = 0
SITP = 1
tsu
th
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V2
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6.3.32
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 113 for DCMI are derived from
tests performed under the ambient temperature, f
frequency and VDD supply voltage
HCLK
summarized in Table 22: General operating conditions, with the following configuration:
•
•
•
•
•
•
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
(1)
Table 113. DCMI characteristics
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
Pixel Clock input
-
-
0.4
80
70
-
-
DCMI_PIXCLK
Dpixel
MHz
%
Pixel Clock input duty cycle
Data input setup time
30
3
t
su(DATA)
-
th(DATA)
Data hold time
1
-
tsu(HSYNC),
tsu(VSYNC)
DCMI_HSYNC/ DCMI_VSYNC input setup time
DCMI_HSYNC/ DCMI_VSYNC input hold time
2
1
-
-
ns
-
th(HSYNC),
th(VSYNC)
1. Guaranteed by characterization results.
Figure 50. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
th(HSYNC)
tsu(HSYNC)
th(HSYNC)
tsu(VSYNC)
tsu(DATA) th(DATA)
MS32414V2
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6.3.33
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 114 for LCD-TFT are derived
from tests performed under the ambient temperature, f frequency and VDD supply
HCLK
voltage summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
•
•
•
•
•
LCD_CLK polarity: high
LCD_DE polarity: low
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5VDD
IO Compensation cell activated.
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
(1)
Table 114. LTDC characteristics
Symbol
Parameter
Min
Max
Unit
2.7<VD <3.6 V
D
150
LTDC clock
output
frequency
20pF
fCLK
-
MHz
%
2.7<VD <3.6 V
133
90
D
1.62<VD <3.6 V
D
DCLK
LTDC clock output duty cycle
Clock High time, low time
45
55
tw(CLKH),
tw(CLKL)
tw(CLK)//2-0.5
tw(CLK)//2+0.5
tv(DATA)
th(DATA)
tv(DATA)
2.7<VD <3.6 V
0.5
5
D
-
Data output valid time
-
1.62<VD <3.6 V
D
Data output hold time
0
-
-
tv(HSYNC),
tv(VSYNC),
tv(DE)
2.7<VD <3.6 V
0.5
D
HSYNC/VSYNC/DE output
valid time
1.62<VD <3.6 V
-
5
D
th(HSYNC),
HSYNC/VSYNC/DE output hold time
0
-
th(VSYNC)
,
th(DE)
1. Guaranteed by characterization results.
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Figure 51. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC)
tv(HSYNC)
LCD_HSYNC
th(DE)
tv(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
Pixel Pixel
1
Pixel
N
2
th(DATA)
Active width
HSYNCHorizontal
width back porch
Horizontal
back porch
One line
MS32749V1
Figure 52. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC)
tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
M lines data
VSYNC Vertical
width back porch
Active width
One frame
Vertical
back porch
MS32750V1
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6.3.34
Timer characteristics
The parameters given in Table 115 are guaranteed by design.
Refer to Section 6.3.18: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 115. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK
=
tTIMxCLK
1
-
240 MHz
tres(TIM)
Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK
=
tTIMxCLK
1
-
120 MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK/2
16/32
0
-
MHz
bit
f
TIMxCLK = 240 MHz
ResTIM
Timer resolution
Maximum possible count
with 32-bit counter
65536 ×
65536
tMAX_COUNT
tTIMxCLK
-
-
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2
.
6.3.35
Communication interfaces
I2C interface characteristics
2
The I C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
2
The I C timings requirements are guaranteed by design when the I C peripheral is properly
configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
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2
Table 116. Minimum i2c_ker_ck frequency in all I C modes
Symbol
Parameter
Condition
Min
Unit
Standard-mode
Fast-mode
-
2
Analog Filtre ON
DNF=0
8
9
MHz
Analog Filtre OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
Analog Filtre ON
DNF=0
17
16
Fast-mode Plus
Analog Filtre OFF
DNF=1
-
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but still present.
DDIOx
•
The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load C supported in Fm+, which is given by these formulas:
Load
t
=0.8473xR xC
P Load
r(SDA/SCL)
R
= (V -V
)/I
P(min)
DD OL(max) OL(max)
Where R is the I2C lines pull-up. Refer to Section 6.3.18: I/O port characteristics for
P
2
the I C I/Os characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
2
(1)
Table 117. I C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes
that are suppressed by analog
filter
tAF
50(2)
80(3)
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
USART interface characteristics
Unless otherwise specified, the parameters given in Table 118 for USART are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS1
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Electrical characteristics
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Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
(1)
Table 118. USART characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
Slave mode
Slave mode
Slave mode
12.5
fCK
USART clock frequency
-
-
MHz
25
-
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
tker+1
2
-
-
-
-
,
CK high and low time
Data input setup time
Master mode
1/fCK/2-2
1/fCK/2
1/fCK/2+2
tw(SCKL)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
t
ker+6
-
-
-
-
tsu(RX)
th(RX)
tv(TX)
th(TX)
1.5
0
-
-
Data input hold time
Data output valid time
Data output hold time
1.5
-
-
-
ns
12
0.5
-
20
1
-
-
9
0
-
-
1. Guaranteed by characterization results.
204/242
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STM32H747xI/G
Electrical characteristics
Figure 53. USART timing diagram in Master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
t
su(MI)
t
f(SCK)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 54. USART timing diagram in Slave mode
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
DS12930 Rev 1
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Electrical characteristics
STM32H747xI/G
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 119 for SPI are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 119. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
1.62<VDD<3.6 V
SPI1, 2, 3
80
Master mode
2.7<VDD<3.6 V
SPI1, 2, 3
100
50
Master mode
1.62<VDD<3.6 V
SPI4, 5, 6
fSCK
SPI clock frequency
-
-
MHz
Slave receiver mode
1.62<VDD<3.6 V
100
31
Slave mode transmitter/full duplex
2.7<VDD<3.6 V
Slave mode transmitter/full duplex
1.62 <VDD<3.6 V
29
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
2
1
-
-
-
-
-
,
SCK high and low time Master mode
TPCLK-2 TPCLK TPCLK+2
tw(SCKL)
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STM32H747xI/G
Electrical characteristics
(1)
Table 119. SPI characteristics (continued)
Parameter Conditions Min
Master mode
Symbol
Typ
Max
Unit
tsu(MI)
1
1
4
2
9
0
-
-
-
-
Data input setup time
tsu(SI)
th(MI)
Slave mode
Master mode
Slave mode
-
-
Data input hold time
th(SI)
-
-
ta(SO)
tdis(SO)
Data output access time Slave mode
Data output disable time Slave mode
13
1
27
5
Slave mode
ns
-
12.5
16
2.7<VDD<3.6 V
tv(SO)
Data output valid time
Data output hold time
Slave mode
-
-
12.5
17
3
-
1.62<VDD<3.6 V
tv(MO)
th(SO)
th(MO)
Master mode
1
-
Slave mode
10
0
1.62<VDD<3.6 V
Master mode
-
-
1. Guaranteed by characterization results.
Figure 55. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
DS12930 Rev 1
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Electrical characteristics
STM32H747xI/G
(1)
Figure 56. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
(1)
Figure 57. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
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STM32H747xI/G
Electrical characteristics
I2S Interface characteristics
2
Unless otherwise specified, the parameters given in Table 120 for I S are derived from tests
performed under the ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
2
(1)
Table 120. I S dynamic characteristics
Parameter Conditions
Symbol
Min
Max
Unit
fMCK
I2S main clock output
-
256x8K
256FS
MHz
Master data
-
64FS
fCK
I2S clock frequency
MHz
Slave data
-
64FS
tv(WS)
th(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
-
3
-
-
-
-
-
-
-
0
1
1
1
1
4
2
tsu(WS)
th(WS)
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
ns
Slave transmitter (after enable
edge)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
-
-
17
3
-
Data output valid time
Data output hold time
Master transmitter (after
enable edge)
Slave transmitter (after enable
edge)
9
0
Master transmitter (after
enable edge)
-
1. Guaranteed by characterization results.
DS12930 Rev 1
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Electrical characteristics
STM32H747xI/G
2
(1)
Figure 58. I S slave timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 59. I S master timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
210/242
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STM32H747xI/G
Electrical characteristics
SAI characteristics
Unless otherwise specified, the parameters given in Table 121 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
IO Compensation cell activated.
Measurement points are done at CMOS levels: 0.5VDD
VOS level set to VOS1.
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
(1)
Table 121. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
SAI Main clock output
-
256x8K 256xFS
(3)
(3)
Master Data: 32 bits
Slave Data: 32 bits
-
-
128xFS
128xFS
MHz
SAI clock
fCK
frequency(2)
DS12930 Rev 1
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Electrical characteristics
STM32H747xI/G
(1)
Table 121. SAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode
-
-
13
2.7≤VDD≤3.6
tv(FS)
FS valid time
Master mode
20
1.62≤VDD≤3.6
tsu(FS)
th(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
8
1
-
-
-
-
-
-
-
Slave mode
1
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
0.5
1
Data input setup time
Data input hold time
3.5
2
Slave transmitter (after enable
edge)
-
14
ns
2.7≤VDD≤3.6
tv(SD_B_ST) Data output valid time
th(SD_B_ST) Data output hold time
tv(SD_A_MT) Data output valid time
Slave transmitter (after enable
edge)
-
9
-
20
-
1.62≤VDD≤3.6
Slave transmitter (after enable
edge)
Master transmitter (after enable
edge)
12
2.7≤VDD≤3.6
Master transmitter (after enable
edge)
-
19
-
1.62≤VDD≤3.6
Master transmitter (after enable
edge)
th(SD_A_MT) Data output hold time
7.5
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
212/242
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STM32H747xI/G
Electrical characteristics
Figure 60. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 61. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
MDIO characteristics
Table 122. MDIO Slave timing parameters
Symbol
Parameter
Min
Typ
Max
Unit
FMDC
td(MDIO)
tsu(MDIO)
th(MDIO)
Management Data Clock
-
-
10
-
30
19
-
MHz
Management Data Iput/output output valid time
Management Data Iput/output setup time
Management Data Iput/output hold time
8
1
1
ns
-
-
DS12930 Rev 1
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221
Electrical characteristics
STM32H747xI/G
Figure 62. MDIO Slave timing diagram
tMDC)
td(MDIO)
tsu(MDIO)
th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 123 and Table 124 for SDIO are
derived from tests performed under the ambient temperature, f frequency and VDD
PCLKx
supply voltage summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 0x11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output
characteristics.
(1)(2)
Table 123. Dynamics characteristics: SD / MMC characteristics, V =2.7 to 3.6 V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
0
-
-
133
MHz
-
-
-
8/3
fPP =52MHz
fPP =52MHz
8.5
8.5
9.5
9.5
-
-
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
-
1.5
1.5
3
-
-
-
-
-
-
ns
-
(4)
tIDW
Input valid window (variable window)
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode
tOV
tOH
Output valid time HS
Output hold time HS
-
-
-
3.5
-
5
-
ns
2
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DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
(1)(2)
Table 123. Dynamics characteristics: SD / MMC characteristics, V =2.7 to 3.6 V
(continued)
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D inputs (referenced to CK) in SD default mode
Input setup time SD
Input hold time SD
-
-
1.5
1.5
-
-
tISUD
tIHD
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time SD
Output hold default time SD
-
-
-
0.5
-
2
-
ns
0
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. An external voltage converter is required to support SD 1.8 V.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
(1)(2)
Unit
Table 124. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V
Symbol
Parameter
Conditions
Min
Typ
Max
Clock frequency in data transfer
mode
fPP
-
0
-
120
MHz
-
-
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
-
8/3
tW(CKL)
tW(CKH)
fPP =52 MHz
fPP =52 MHz
8.5
8.5
9.5
9.5
-
-
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
1
-
-
-
-
2.5
Input valid window (variable
window)
(3)
tIDW
-
3.5
-
-
CMD, D outputs (referenced to CK) in eMMC mode
tOVD
tOHD
Output valid time HS
Output hold time HS
-
-
-
5
-
7
-
3
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
DS12930 Rev 1
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221
Electrical characteristics
STM32H747xI/G
Figure 63. SDIO high-speed mode
Figure 64. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
Figure 65. DDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
D5
tsf(IN) thf(IN)
tsr(IN)thr(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv36879V1
216/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
USB OTG_HS characteristics
Unless otherwise specified, the parameters given in Table 125 for ULPI are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
summarized in Table 22: General operating conditions, with the following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS1
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output
characteristics.
(1)
Table 125. Dynamics characteristics: USB ULPI
Symbol
Parameter
Condition
Min Typ Max Unit
Control in (ULPI_DIR , ULPI_NXT) setup
time
tSC
-
2.5
2
-
-
-
-
Control in (ULPI_DIR, ULPI_NXT) hold
time
tHC
-
tSD
tHD
Data in setup time
Data in hold time
-
-
2.5
0
-
-
-
-
ns
2.7<VDD<3.6 V
CL=20 pF
-
-
9
9
9.5
14
t
DC/tDD
Control/Datal output delay
1.71<VDD<3.6 V
CL=15 pF
1. Guaranteed by characterization results.
Figure 66. ULPI timing diagram
Clock
t
t
HC
SC
Control In
(ULPI_DIR,
ULPI_NXT)
t
t
HD
SD
data In
(8-bit)
t
t
DC
DC
Control out
(ULPI_STP)
t
DD
data out
(8-bit)
ai17361c
DS12930 Rev 1
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Electrical characteristics
STM32H747xI/G
Ethernet interface characteristics
Unless otherwise specified, the parameters given in Table 126, Table 127 and Table 128 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
f
frequency and V supply voltage conditions summarized in Table 22: General
rcc_c_ck
DD
operating conditions, with the following configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output
characteristics:
(1)
Table 126. Dynamics characteristics: Ethernet MAC signals for SMI
Symbol
Parameter
Min
Typ
Max
Unit
tMDC
MDC cycle time( 2.5 MHz)
Write data valid time
Read data setup time
Read data hold time
400
0.5
12.5
0
400
403
Td(MDIO)
tsu(MDIO)
th(MDIO)
1.5
4
-
ns
-
-
-
1. Guaranteed by characterization results.
Figure 67. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
ETH_MDIO(I)
tsu(MDIO)
th(MDIO)
MS31384V1
218/242
DS12930 Rev 1
STM32H747xI/G
Electrical characteristics
(1)
Table 127. Dynamics characteristics: Ethernet MAC signals for RMII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(CRS)
tih(CRS)
td(TXEN)
td(TXD)
Receive data setup time
Receive data hold time
2
2
-
-
-
-
Carrier sense setup time
Carrier sense hold time
1.5
1.5
7
-
-
ns
-
-
Transmit enable valid delay time
Transmit data valid delay time
8
9
9.5
11
8
1. Guaranteed by characterization results.
Figure 68. Ethernet RMII timing diagram
RMII_REF_CLK
t
t
d(TXEN)
d(TXD)
RMII_TX_EN
RMII_TXD[1:0]
t
t
t
t
su(RXD)
su(CRS)
ih(RXD)
ih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
(1)
Table 128. Dynamics characteristics: Ethernet MAC signals for MII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(DV)
tih(DV)
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
2
-
-
-
2
-
1.5
1.5
1.5
0.5
9
-
-
-
-
-
ns
tsu(ER)
tih(ER)
td(TXEN)
td(TXD)
Error setup time
-
Error hold time
-
-
Transmit enable valid delay time
Transmit data valid delay time
10
9.5
11
12.5
8.5
1. Guaranteed by characterization results.
DS12930 Rev 1
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221
Electrical characteristics
STM32H747xI/G
Figure 69. Ethernet MII timing diagram
MII_RX_CLK
t
t
t
t
t
t
su(RXD)
su(ER)
su(DV)
ih(RXD)
ih(ER)
ih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
t
t
d(TXEN)
d(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 129 and Table 130 for
JTAG/SWD are derived from tests performed under the ambient temperature, f
rcc_c_ck
frequency and V supply voltage summarized in Table 22: General operating conditions,
DD
with the following configuration:
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 0x10
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
Refer to Section 6.3.18: I/O port characteristics for more details on the input/output
characteristics:
Table 129. Dynamics JTAG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7V <VDD< 3.6 V
-
-
-
-
37
TCK clock frequency
1/tc(TCK)
tisu(TMS)
tih(TMS)
tisu(TDI)
tih(TDI)
1.62 <VDD< 3.6 V
27.5
MHz
TMS input setup time
TMS input hold time
TDI input setup time
TDI input hold time
-
2.5
1
-
-
-
-
-
-
1.5
1
-
-
-
-
-
-
-
-
-
-
2.7V <VDD< 3.6 V
1.62 <VDD< 3.6 V
-
-
8
8
-
13.5
18
-
tov(TDO)
toh(TDO)
TDO output valid time
TDO output hold time
-
7
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Electrical characteristics
Table 130. Dynamics SWD characteristics:
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7V <VDD< 3.6 V
-
-
-
-
71
52.5
-
SWCLK clock frequency
MHz
1/tc(SWCLK)
tisu(SWDIO)
tih(SWDIO)
1.62 <VDD< 3.6 V
SWDIO input setup time
SWDIO input hold time
-
2.5
1
-
-
-
-
-
-
-
2.7V <VDD< 3.6 V
1.62 <VDD< 3.6 V
-
8.5
14
tov(SWDIO)
SWDIO output valid time
SWDIO output hold time
-
8.5
-
19
-
-
-
toh(SWDIO)
-
8
Figure 70. JTAG timing diagram
tc(TCK)
TCK
TDI/TMS
TDO
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL)
tw(TCKH)
tov(TDO)
toh(TDO)
MSv40458V1
Figure 71. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL)
tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
DS12930 Rev 1
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Package information
STM32H747xI/G
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com.
®
ECOPACK is an ST trademark.
7.1
WLCSP156 package information
WLCSP156 is a 156-bump, 4.96 x 4.64 mm, 0.35 mm pitch, wafer level chip scale
package.
Figure 72. WLCSP156 package outline
bbb
Z
F
A1 ball location
e1
A1
G
Detail A
e2
E
E
e
A
D
D
e
A2
TOP VIEW
BOTTOM VIEW
SIDE
VIEW
A3
A2
BUMP
b
A1
FRONT VIEW
Z
ccc
ddd
Z X Y
Z
DETAIL A
ROTATED 90
SEATING
PLANE
A086_WLCSP156_ME_V1
1. Drawing is not to scale.
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Package information
Table 131. WLCSP156 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
b
-
-
0.17
0.38
0.025(2)
0.24
4.96
4.64
4.20
3.85
0.35
0.380(3)
0.395(3)
-
0.58
-
-
0.023
-
-
-
0.006
0.015
0.001
0.009
0.195
0.182
0.014
0.165
0.152
0.015
0.015
-
-
-
-
-
-
-
-
-
-
0.21
0.27
4.98
4.66
-
0.008
0.011
0.196
0.183
-
D
4.94
0.193
E
4.62
0.181
e1
e2
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.10
0.05
0.05
0.004
0.004
0.004
0.002
0.002
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to the 3rd decimal digits.
2. Back side coating. Nominal dimension rounded to the 3rd decimal place resulting from process capability.
3. Calculated dimensions are rounded to 3rd decimal place.
Figure 73. WLCSP156 bump recommended footprint
Dpad
Dsm
A086_WLCSP156_FP_V1
1. Dimensions are expressed in millimeters.
DS12930 Rev 1
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Package information
STM32H747xI/G
Table 132. WLCSP156 bump recommended PCB design rules
Dimension Recommended values
Pitch
Dpad
0.35 mm
0.210 mm
0.275 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.235 mm
0.100 mm
Device marking for WLSCP156
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 74. WLCSP156 marking example (package top view)
Ball A1
identifier
ES32H747ZI6
Product
identification(1)
Date code
Revision code
Y WW
R
MSv61385V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
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Package information
7.2
UFBGA169 package information
UFBGA169 is a 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 75. UFBGA169 package outline
Z
Seating plane
A4
A2
ddd
Z
A
A3
A1
b
SIDE VIEW
A1 ball
index area
A1 ball
identifier
X
E
E1
e
F
A
F
D
D1
e
Y
N
13
1
Øb (169 balls)
BOTTOM VIEW
TOP VIEW
Øeee M
Øfff
Z
Z
X Y
M
A0YV_ME_V2
1. Drawing is not in scale.
Table 133. UFBGA169 package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.280
7.000
6.000
7.000
6.000
0.500
0.500
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2362
0.2756
0.2362
0.0197
0.0197
0.0236
0.0043
0.0197
-
0.270
0.230
6.950
5.950
6.950
5.950
-
0.370
0.330
7.050
6.050
7.050
6.050
-
0.0106
0.0091
0.2736
0.2343
0.2736
0.2343
-
0.0146
0.0130
0.2776
0.2382
0.2776
0.2382
-
D
D1
E
E1
e
F
0.450
0.550
0.0177
0.0217
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Package information
STM32H747xI/G
Table 133. UFBGA169 package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.100
0.150
0.050
-
-
-
-
-
-
0.0039
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Device marking for UFBGA169
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 76. UFBGA169 marking example (package top view)
Ball A1
identifier
ES32H747
Product identification(1)
AII6
Date code
Y WW
Revision code
R
MSv61387V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
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Package information
7.3
LQFP176 package information
LQFP176 is a 176-pin, 24 x 24 mm low profile quad flat package.
Figure 77. LQFP176 package outline
Seating plane
C
0.25 mm
gauge plane
k
A1
L
HD
L1
PIN 1
IDENTIFICATION
D
ZE
E
HE
e
ZD
b
1T_ME_V2
1. Drawing is not to scale.
Table 134. LQFP176 package mechanical data
Dimensions
Ref.
Millimeters
Inches(1)
Typ.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
-
-
-
-
-
-
1.600
0.150
1.450
0.270
0.200
-
-
-
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.050
1.350
0.170
0.090
0.0020
0.0531
0.0067
0.0035
c
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Package information
STM32H747xI/G
Table 134. LQFP176 package mechanical data (continued)
Dimensions
Ref.
Millimeters
Typ.
Inches(1)
Typ.
Min.
Max.
Min.
Max.
D
HD
ZD
E
23.900
-
24.100
0.9409
-
0.9488
25.900
-
26.100
1.0197
-
1.0276
-
1.250
-
-
0.0492
-
23.900
-
24.100
0.9409
-
0.9488
HE
ZE
e
25.900
-
26.100
1.0197
-
1.0276
-
1.250
-
-
0.0492
-
-
0.500
-
0.750
-
-
0.0197
-
0.0295
-
L(2)
L1
k
0.450
-
0.0177
-
-
0°
-
1.000
-
0°
-
0.0394
-
-
7°
-
-
7°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
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Package information
Figure 78. LQFP176 package recommended footprint
1.2
176
133
132
0.5
1
0.3
44
45
89
88
1.2
21.8
26.7
1T_FP_V1
1. Dimensions are expressed in millimeters.
DS12930 Rev 1
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Package information
STM32H747xI/G
Device marking for LQFP176
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 79. LQFP176 marking example (package top view)
Product identification(1)
ES32H747IIT6
Date code
Revision code
Y WW
R
Pin 1identifier
MSv61389V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
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Package information
7.4
LQFP208 package information
LQFP208 is a 208-pin, 28 x 28 mm low-profile quad flat package.
Figure 80. LQFP208 package outline
SEATING
PLANE
C
ccc
C
0.25 mm
GAUGE PLANE
K
L
D
L1
D1
D3
105
156
104
157
208
53
PIN 1
IDENTIFICATION
1
52
e
UH_ME_V2
1. Drawing is not to scale.
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Package information
STM32H747xI/G
Table 135. LQFP208 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
29.800
27.800
-
-
1.600
0.150
1.450
0.270
0.200
30.200
28.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
-
0.0020
0.0531
0.0067
0.0035
1.1811
1.1024
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
30.000
28.000
25.500
30.000
28.000
25.500
0.500
0.600
1.000
3.5°
1.1732
1.0945
1.0039
1.1732
1.0945
1.0039
0.0197
0.0236
0.0394
3.5°
1.1890
D1
D3
E
1.1102
-
29.800
27.800
-
30.200
28.200
-
1.1811
1.1024
-
1.1890
E1
E3
e
1.1102
-
-
-
-
-
0.0295
-
L
0.450
-
0.750
-
0.0177
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
Figure 81. LQFP208 package recommended footprint
208
157
0.5
1
156
52
105
1.2
53
104
25.8
30.7
UH_FP_V2
1. Dimensions are expressed in millimeters.
DS12930 Rev 1
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Package information
STM32H747xI/G
Device marking for LQFP208
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 82. LQFP208 marking example (package top view)
Revision code
R
Product identification(1)
ES32H747BIT6
Y WW
Date code
Pin 1 identifier
MSv61391V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
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Package information
7.5
TFBGA240+25 package information
TFBGA240+25 is a 265 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array
package.
Figure 83. TFBGA240+25 package outline
SEATING
PLANE
C
A1 ball identifier
D
D1
e
A
e
S
1
17
F
b (240 + 25 balls)
BOTTOM VIEW
TOP VIEW
A07U_ME_V1
1. Dimensions are expressed in millimeters.
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Package information
STM32H747xI/G
Table 136. TFBG240+25 ball package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.100
-
-
0.0433
0.150
-
-
0.0059
-
-
-
0.760
0.400
14.000
12.800
14.000
12.800
0.800
0.600
0.600
-
-
-
0.0299
0.0157
0.5512
0.5039
0.5512
0.5039
0.0315
0.0236
0.0236
-
-
0.350
0.450
0.0138
0.0177
D
13.850
14.150
0.5453
0.5571
D1
E
-
-
-
-
13.850
14.150
0.5453
0.5571
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
-
G
-
-
ddd
eee
fff
0.100
0.150
0.080
0.0039
0.0059
0.0031
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 84. TFBGA240+25 package recommended footprint
Dpad
Dsm
A07U_FP_V2
1. Dimensions are expressed in millimeters.
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Package information
Table 137. TFBGA240+25 recommended PCB design rules (0.8 mm pitch)
Dimension Recommended values
Pitch
0.8 mm
Dpad
Dsm
0.225 mm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
Device marking for TFBGA240+25
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 85. TFBGA240+25 marking example (package top view)
Product
identification(1)
ES32H747XIH6
Revision code
R
Date code
Ball
A1identifier
Y WW
MSv61393V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12930 Rev 1
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Package information
STM32H747xI/G
7.6
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in ° C,
A
Θ
is the package junction-to-ambient thermal resistance, in ° C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 138. Thermal characteristics
Parameter
Symbol
Definition
Value
Unit
Thermal resistance junction-ambient
35
WLCSP156 - 4.96 x 4.64 mm /0.35 mm pitch
Thermal resistance junction-ambient
37.7
43.0
42.4
36.6
18.1
17.3
39.4
40.3
24.3
UFBGA169 - 7 x 7 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-ambient
Θ
°C/W
JA
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
LQFP208 - 28 x 28 mm /0.5 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
Thermal resistance junction-ambient
WLCSP156 - 4.96 x 4.64 mm /0.35 mm pitch
Thermal resistance junction-ambient
UFBGA169 - 7 x 7 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-board
Θ
°C/W
JB
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
LQFP208 - 28 x 28 mm /0.5 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
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Package information
Table 138. Thermal characteristics (continued)
Symbol
Definition
Parameter
Value
Unit
Thermal resistance junction-ambient
1
WLCSP156 - 4.96 x 4.64 mm /0.35 mm pitch
Thermal resistance junction-ambient
11
UFBGA169 - 7 x 7 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-case
Θ
11.2
11.1
7.4
°C/W
JC
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
LQFP208 - 28 x 28 mm /0.5 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
7.6.1
Reference document
•
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
•
For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available from www.st.com.
DS12930 Rev 1
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Ordering information
STM32H747xI/G
8
Ordering information
Example:
STM32 H
747
X
I
T
6
TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
747 = STM32H7x7 dual core MIPI-DSI line
Pin count
Z = 156 pins
A = 169 pins
I = 176 pins/balls
B = 208 pins
X = 240 balls
Flash memory size
G = 1 Mbytes
I = 2 Mbytes
Package
T = LQFP ECOPACK®2
I = UFBGA pitch 0.5 mm ECOPACK®2
H = TFBGA ECOPACK®2
Y = WLCSP ECOPACK®2
Temperature range
6 = –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Revision history
9
Revision history
Table 139. Document revision history
Date
Revision
Changes
16-May-2019
1
Initial release.
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
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ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
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相关型号:
STM32H747IG
带DSP和DP-FPU的高性能ARM Cortex-M7 + Cortex-M4 MCU,具有1 MB Flash、1 MB RAM、480 MHz CPU、ART加速器、一级缓存、外部存储器接口、大量外设、SMPS和MIPI-DSI
STMICROELECTR
STM32H747IGH6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
STM32H747IGI6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
STM32H747IGT6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
STM32H747IGY6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
STM32H747II
带DSP和DP-FPU的高性能ARM Cortex-M7 + Cortex-M4 MCU,具有2 MB Flash、1 MB RAM、480 MHz CPU、ART加速器、一级缓存、外部存储器接口、大量外设、SMPS和MIPI-DSI
STMICROELECTR
STM32H747IIH6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
STM32H747III6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
STM32H747IIT6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
STM32H747IIY6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
STM32H747XG
带DSP和DP-FPU的高性能ARM Cortex-M7 + Cortex-M4 MCU,具有1 MB Flash、1 MB RAM、480 MHz CPU、ART加速器、一级缓存、外部存储器接口、大量外设、SMPS和MIPI-DSI
STMICROELECTR
STM32H747XGH6TR
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, DSI
STMICROELECTR
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