STM32H750IB [STMICROELECTRONICS]
32-bit Arm® Cortex®-M7 480MHz MCUs, 128 Kbyte Flash, 1 Mbyte RAM, 46 com. and analog interfaces, crypto;
| 型号： | STM32H750IB |
| 厂家： | 
ST |
| 描述： | 32-bit Arm® Cortex®-M7 480MHz MCUs, 128 Kbyte Flash, 1 Mbyte RAM, 46 com. and analog interfaces, crypto |
| 文件： | 总335页 (文件大小：3993K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32H750VB STM32H750ZB
STM32H750IB STM32H750XB
32-bit Arm® Cortex®-M7 480MHz MCUs, 128 Kbyte Flash,
1 Mbyte RAM, 46 com. and analog interfaces, crypto
Datasheet - production data
Features
FBGA
FBGA
Core
®
®
32-bit Arm Cortex -M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
LQFP100
(14 x 14 mm)
LQFP144
(20 x 20 mm)
LQFP176
TFBGA240+25
(14x14 mm)
UFBGA176+25
(10x10 mm)
(24 x 24 mm)
– D2: communication peripherals and timers
– D3: reset/clock control/power management
Memories
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
128 Kbytes of Flash memory
1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
Embedded regulator (LDO) with configurable
scalable output to supply the digital circuitry
Dual mode Quad-SPI memory interface
Voltage scaling in Run and Stop mode (6
running up to 133 MHz
configurable ranges)
Flexible external memory controller with up to
Backup regulator (~0.9 V)
32-bit data bus:
Voltage reference for analog peripheral/V
REF+
– SRAM, PSRAM, NOR Flash memory
clocked up to 133 MHz in synchronous
mode
Low-power modes: Sleep, Stop, Standby and
V
supporting battery charging
BAT
– SDRAM/LPSDR SDRAM
Low-power consumption
– 8/16-bit NAND Flash memories
V
battery operating mode with charging
BAT
CRC calculation unit
capability
Security
CPU and domain power state monitoring pins
ROP, PC-ROP, active tamper, secure firmware
2.95 µAin Standby mode (Backup SRAM OFF,
upgrade support, Secure access mode
RTC/LSE ON)
General-purpose input/outputs
Clock management
Up to 168 I/O ports with interrupt capability
Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
Reset and power management
External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
3 separate power domains which can be
independently clock-gated or switched off:
3× PLLs (1 for the system clock, 2 for kernel
– D1: high-performance capabilities
clocks) with Fractional mode
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This is information on a product in full production.
www.st.com
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Chrom-ART graphical hardware Accelerator
Interconnect matrix
(DMA2D) to reduce CPU load
3 bus matrices (1 AXI and 2 AHB)
Bridges (5× AHB2-APB, 2× AXI2-AHB)
Hardware JPEG Codec
Up to 22 timers and watchdogs
4 DMA controllers to unload the CPU
1× high-resolution timer (2.1 ns max
1× high-speed master direct memory access
resolution)
controller (MDMA) with linked list support
2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
2× dual-port DMAs with FIFO
1× basic DMA with request router capabilities
2× 16-bit advanced motor control timers (up to
Up to 35 communication peripherals
240 MHz)
4× I2Cs FM+ interfaces (SMBus/PMBus)
10× 16-bit general-purpose timers (up to
4× USARTs/4x UARTs (ISO7816 interface,
240 MHz)
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
5× 16-bit low-power timers (up to 240 MHz)
2× watchdogs (independent and window)
1× SysTick timer
6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
4x SAIs (serial audio interface)
SPDIFRX interface
RTC with sub-second accuracy and hardware
calendar
SWPMI single-wire protocol master I/F
MDIO Slave interface
Cryptographic acceleration
AES 128, 192, 256, TDES,
2× SD/SDIO/MMC interfaces (up to 125 MHz)
HASH (MD5, SHA-1, SHA-2), HMAC
True random number generators
2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
2× USB OTG interfaces (1FS, 1HS/FS) crystal-
Debug mode
less solution with LPM and BCD
SWD & JTAG interfaces
4-Kbyte Embedded Trace Buffer
Ethernet MAC interface with DMA controller
HDMI-CEC
96-bit unique ID
8- to 14-bit camera interface (up to 80 MHz)
All packages are ECOPACK2 compliant
11 analog peripherals
3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
1× temperature sensor
2× 12-bit D/A converters (1 MHz)
2× ultra-low-power comparators
2× operational amplifiers (7.3 MHz bandwidth)
1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
Graphics
LCD-TFT controller up to XGA resolution
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
3.2
3.3
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1
3.3.2
3.3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.1
3.5.2
3.5.3
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6
3.7
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.1
3.7.2
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8
3.9
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 32
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 32
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 32
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.19
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 36
3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 39
3.29 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.29.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.29.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.29.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.29.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 43
3.29.6 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.7 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.30 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 44
3.31 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.32 Universal synchronous/asynchronous receiver transmitter (USART) . . . 45
3.33 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 46
3.34 Serial peripheral interfaces (SPI)/integrated interchip
sound interfaces (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.35 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.36 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.37 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 48
3.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 49
3.39 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 49
3.40 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 49
3.41 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 50
3.42 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 50
3.43 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.44 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Contents
4
5
6
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 99
Embedded reset and power control block characteristics . . . . . . . . . . 100
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 115
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 127
6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 168
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6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.24 Temperature and V
monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
BAT
6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 176
6.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 178
6.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 179
6.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.32 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.33 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 196
7
Electrical characteristics (rev V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.2
7.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 205
Embedded reset and power control block characteristics . . . . . . . . . . 206
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 220
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 233
7.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
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7.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
7.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
7.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
7.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.3.21 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 279
7.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
7.3.24 Temperature and V
monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
BAT
7.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 283
7.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 285
7.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 288
7.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 289
7.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.32 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
8.1
8.2
8.3
8.4
8.5
8.6
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
8.6.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
10
DS12556 Rev 5
7/334
7
List of tables
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
STM32H750xB features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STM32H750xB pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Port I alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
VCAP operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 99
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical consumption in Run mode and corresponding performance
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
versus code position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 105
Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 106
Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 106
Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 107
Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 114
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
8/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
PLL characteristics (wide VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 131
Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 132
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 139
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 139
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 140
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 141
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 142
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 144
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 149
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
BAT
BAT
Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
DS12556 Rev 5
9/334
12
List of tables
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 97.
Table 98.
Table 99.
OPAMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
DFSDM measured timing - 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 100. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 101. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 102. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 103. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 104. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
2
Table 105. I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 106. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 107. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 108. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 190
Table 109. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 191
Table 110. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 111. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 112. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 113. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 114. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 115. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 116. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 117. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 118. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 119. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 120. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 121. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 122. VCAP operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 123. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 205
Table 124. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 125. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 126. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 127. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 128. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON,
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 129. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF,
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 130. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 131. Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 211
Table 132. Typical and maximum current consumption in Sleep mode, LDO regulator . . . . . . . . . . 212
Table 133. Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 134. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 213
Table 135. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 136. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 137. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 138. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 139. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 140. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 141. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 142. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
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Table 143. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 144. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 145. PLL characteristics (wide VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 146. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 147. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 148. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 149. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 150. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 151. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 152. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 153. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 154. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 155. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 156. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 237
Table 157. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 238
Table 158. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 159. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 160. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 161. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 244
Table 162. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 244
Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 246
Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 246
Table 165. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 166. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 248
Table 167. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 168. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 249
Table 169. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 170. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 171. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 172. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 173. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 174. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 175. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 176. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 177. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 178. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 179. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 180. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 181. Delay Block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 182. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 183. Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 184. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 185. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 186. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 187. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 188. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 189. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 190. V
Table 191. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
BAT
BAT
Table 192. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 193. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 194. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
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Table 195. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 196. DFSDM measured timing - 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 197. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 198. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 199. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 200. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 201. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 202. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 203. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
2
Table 204. I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 205. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 206. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 207. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 303
Table 208. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V. . . . . . . . . . . . . . . 304
Table 209. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 210. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 211. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 212. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 213. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Table 214. Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Table 215. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Table 216. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Table 217. LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 218. UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 219. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA). . . . . . . . . . . . . 324
Table 220. TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 221. TFBGA240+25 recommended PCB design rules (0.8 mm pitch). . . . . . . . . . . . . . . . . . . 328
Table 222. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Table 223. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
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Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32H750xB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32H750xB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 13. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
EXT
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 16. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 18. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 138
Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 140
Figure 22. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 23. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 24. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 25. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 26. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 27. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 28. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 29. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 30. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 152
Figure 31. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 153
Figure 32. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 33. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 34. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 35. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 36. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 37. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 38. Power supply and reference decoupling (V
Figure 39. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 164
). . . . . . . . . . . . . . . . 164
REF+
DDA
connected to V
REF+
DDA
Figure 40. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 41. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 42. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 43. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 44. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 45. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
(1)
Figure 46. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
(1)
Figure 47. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
2
(1)
Figure 48. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
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(1)
Figure 49. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 50. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 51. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 52. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 53. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 54. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 55. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 56. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 57. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 58. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 59. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 60. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 61. SWD timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 62. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 63. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 64. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 65. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 66. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
EXT
Figure 67. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 68. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 69. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 70. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 71. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 72. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 243
Figure 74. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 245
Figure 75. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 76. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 77. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 78. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 79. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 80. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 81. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 82. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 259
Figure 83. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 260
Figure 84. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 85. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 86. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 87. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 88. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 89. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 90. Power supply and reference decoupling (V
Figure 91. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 274
). . . . . . . . . . . . . . . . 274
REF+
DDA
connected to V
REF+
DDA
Figure 92. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 93. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 94. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 95. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 96. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 97. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 98. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 99. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
(1)
Figure 100. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
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List of figures
(1)
Figure 101. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
2
(1)
Figure 102. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
2
(1)
Figure 103. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 104. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 105. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 106. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 107. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 108. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 109. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 110. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 111. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 112. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 113. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 114. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 115. SWD timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 116. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 117. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 118. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 119. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Figure 120. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 121. LQFP144 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 122. LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 123. LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 124. LQFP176 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 125. UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 126. UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 127. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 128. TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 129. TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 130. TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
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15
Introduction
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
1
Introduction
This document provides information on STM32H750xB microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering information.
This document should be read in conjunction with the STM32H750xB reference manual
(RM0433), available from the STMicroelectronics website www.st.com.
®(a)
®
®
For information on the Arm
Cortex -M7 core, please refer to the Cortex -M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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Description
2
Description
®
®
STM32H750xB devices are based on the high-performance Arm Cortex -M7 32-bit RISC
®
core operating at up to 480 MHz. The Cortex -M7 core features a floating point unit (FPU)
®
which supports Arm double-precision (IEEE 754 compliant) and single-precision data-
processing instructions and data types. STM32H750xB devices support a full set of DSP
instructions and a memory protection unit (MPU) to enhance application security.
STM32H750xB devices incorporate high-speed embedded memories with a Flash memory
of 128 Kbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes
of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced
I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix
and a multi layer AXI interconnect supporting internal and external memory access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG), and a cryptographic
acceleration cell. The devices support four digital filters for external sigma-delta modulators
(DFSDM). They also feature standard and advanced communication interfaces.
Standard peripherals
2
–
–
–
Four I Cs
Four USARTs, four UARTs and one LPUART
Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the
I2S peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
–
–
–
–
–
–
Four SAI serial audio interfaces
One SPDIFRX interface
One SWPMI (Single Wire Protocol Master Interface)
Management Data Input/Output (MDIO) slaves
Two SDMMC interfaces
A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
–
–
–
–
One FDCAN plus one TT-FDCAN interface
An Ethernet interface
Chrom-ART Accelerator
HDMI-CEC
Advanced peripherals including
–
–
–
–
–
A flexible memory control (FMC) interface
A Quad-SPI Flash memory interface
A camera interface for CMOS sensors
An LCD-TFT display controller
A JPEG hardware compressor/decompressor
Refer to Table 1: STM32H750xB features and peripheral counts for the list of peripherals
available on each part number.
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52
Description
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
STM32H750xB devices operate in the –40 to +85 °C temperature range from a 1.62 to
3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
V
. Otherwise the supply voltage must stay above 1.71 V with the embedded power
SS
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages
except LQFP100 to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H750xB devices are offered in 3 packages ranging from 100 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H750xB microcontrollers suitable for a wide range of
applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile applications, Internet of Things
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
Table 1. STM32H750xB features and peripheral counts
Peripherals
Flash memory in Kbytes
SRAM mapped onto AXI
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
128
512
bus
SRAM1 (D2 domain)
SRAM2 (D2 domain)
SRAM3 (D2 domain)
SRAM4 (D3 domain)
ITCM RAM (instruction)
DTCM RAM (data)
128
128
32
SRAM in Kbytes
64
64
TCM RAM in
Kbytes
128
4
Backup SRAM (Kbytes)
FMC
Yes
General-purpose input/outputs
Quad-SPI interface
Ethernet
82
114
140
168
Yes
Yes
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Description
Table 1. STM32H750xB features and peripheral counts (continued)
Peripherals
High-resolution
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
1
10
2
General-purpose
Advanced-control (PWM)
Basic
Timers
2
Low-power
5
Wakeup pins
Tamper pins
4
2
6
3
Random number generator
Cryptographic processor
SPI / I2S
Yes
Yes
6/3(1)
4
I2C
USART/UART/
LPUART
4/4
/1
SAI
4
4 inputs
Yes
Yes
2
SPDIFRX
Communication
interfaces
SWPMI
MDIO
SDMMC
FDCAN/TT-FDCAN
USB OTG_FS
USB OTG_HS
1/1
Yes
Yes
Yes
Yes
Yes
Yes
3
Ethernet and camera interface
LCD-TFT
JPEG Codec
Chrom-ART Accelerator (DMA2D)
16-bit ADCs
Number of Direct channels
Number of Fast channels
Number of Slow channels
2
3
2
9
4
9
2
9
21
11
17
23
Yes
2
12-bit DAC
Number of channels
Comparators
Operational amplifiers
DFSDM
2
2
Yes
Maximum CPU frequency
Operating voltage
480MHz(2)(3)/400 MHz
1.62 to 3.6 V(5)
1.71 to 3.6 V(4)
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52
Description
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 1. STM32H750xB features and peripheral counts (continued)
Peripherals
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Ambient temperatures: –40 up to +85 °C(6)
Junction temperature: –40 to + 125 °C
LQFP176,
Operating temperatures
Package
LQFP100
LQFP144
TFBGA240+25
UFBGA176+25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. The maximum CPU frequency of 480 MHz can be obtained on devices revision V.
3. The product junction temperature must be kept within the –40 to +105 °C temperature range.
4. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this
package is 1.71 V.
5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
6. The product junction temperature must be kept within the –40 to +125 °C temperature range.
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Description
Figure 1. STM32H750xB block diagram
DP, DM, STP,
SDMMC_
D[7:0],
CMD, CK as AF
MII / RMII
NXT,ULPI:CK DP, DM, ID,
To APB1-2
peripherals
MDIO
as AF
, D[7:0], DIR,
ID, VBUS
VBUS
AHB1
(200MHz)
I-TCM
64KB
D-TCM
64KB
D-TCM
64KB
PHY
PHY
ETHER
MAC
OTG_HS OTG_FS
DMA1 DMA2
8 Stream 8 Stream
SDMMC2
FIFO
AHBP
AXIM
Arm CPU
Cortex-M7
480 MHz
DMA/
FIFO
DMA/
FIFO
DMA/
FIFO
AXI/AHB12 (200MHz)
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
FIFOs
FIFOs
JTAG/SW
ETM
128 KB
FLASH
TRACECK
32-bit AHB BUS-MATRIX
TRACED[3:0]
I-Cache
D-Cache
16KB
512 KB AXI
SRAM
16KB
DMA
Mux1
AHBS
SRAM1 SRAM2 SRAM3
128 KB 128 KB 32 KB
FMC
16 Streams
FIFO
MDMA
RNG
HASH
ADC1
Up to 20 analog inputs
common to ADC1 & 2
FMC_signals
Quad-SPI
CLK, CS,D[7:0]
ADC2
CHROM-ART
(DMA2D)
FIFO
FIFO
AHB/APB
3DES/AES
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
TIM2
TIM3
TIM4
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels
LCD-TFT
WWDG
32b
16b
16b
AXI/AHB34 (200MHz)
TIM6
TIM7
16b
16b
JPEG
FIFO
AHB/APB
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
SWPMI
TIM5
TIM12
TIM13
TIM14
SDMMC1
32b
16b
16b
16b
2 channels as AF
1 channel as AF
Delay block
AHB2 (200MHz)
1 channel as AF
DCMI
HRTIM1
DFSDM1
HSYNC, VSYNC, PIXCLK, D[13:0]
AHB/APB
smcard
RX, TX, SCK, CTS,
RTS as AF
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
USART2
irDA
smcard
RX, TX, SCK
CTS, RTS as AF
USART3
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
irDA
UART4
UART5
RX, TX as AF
RX, TX as AF
SD, SCK, FS, MCLK, D/CK[4:1] as
SAI3
SAI2
SAI1
AF
SD, SCK, FS, MCLK, CK[2:1] as AF
UART7
RX, TX as AF
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
UART8
RX, TX as AF
MOSI, MISO, SCK, NSS /
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS as AF
SPI2/I2S2
SPI3/I2S3
SDO, SDI, CK, WS, MCK, as AF
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SCL, SDA, SMBAL as AF
I2C1/SMBUS
I2C2/SMBUS
DMA
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
SCL, SDA, SMBAL as AF
Mux2
MOSI, MISO, SCK, NSS as AF
AHB4
DAP
BDMA
I2C3/SMBUS
MDIOs
SCL, SDA, SMBAL as AF
MDC, MDIO
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI1/I2S1
smcard
RX, TX, SCK, CTS, RTS as AF
USART6
irDA
smcard
RAM
I/F
32-bit AHB BUS-MATRIX
64 KB SRAM
TX, RX
TX, RX
TT-FDCAN1
FDCAN2
RX, TX, SCK, CTS, RTS as AF
USART1
irDA
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR,
BKIN as AF
TIM1/PWM
TIM8/PWM
ADC3
16b
16b
USBCR
SPDIFRX1
HDMI-CEC
DAC
HSEM
CRC
4 KB BKP
IN[1:4] as AF
RAM
CEC as AF
Up to 17 analog inputs
common to ADC1 and 2
DAC_OUT1, DAC_OUT2 as AF
PA..J[15:0]
PK[7:0]
GPIO PORTA.. J
GPIO PORTK
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
LPTIM1
16b
RCC
Reset &
control
OPAMPx_VINM
OPAMP1&2
@VDD33
VDD12
BBgen + POWER MNGT
OPAMPx_VINP
OPAMPx_VOUT as AF
SD, SCK, FS, MCLK,
D[3;1], CK[2:1] as AF
SAI4
VDDMMC33 = 1.8 to 3.6V
VDDUSB33 = 3.0 to 3.6 V
VDD = 1.8 to 3.6 V
VSS
COMPx_INP, COMPx_INM,
Voltage
regulator
3.3 to 1.2V
COMP1&2
LPTIM5
COMPx_OUT as AF
VCAP
LPTIM5_OUT as AF
LPTIM4_OUT as AF
AHB/APB
VREF
SYSCFG
EXTI WKUP
IWDG
LPTIM4
LPTIM3
@VSW
OSC32_IN
OSC32_OUT
XTAL 32 kHz
LPTIM3_OUT as AF
RTC
Backup registers
SCL, SDA, SMBAL as AF
I2C4
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI6/I2S6
AWU
RTC_REFIN
Temperature
sensor
RX, TX, CK, CTS, RTS as AF
LPUART1
LPTIM2
@VDD
VBAT = 1.8 to 3.6 V
HS RC
CSI
HSI48
LS RC
HSI
LPTIM2_IN1, LPTIM2_IN2 and
LPTIM2_OUT
@VDD
OSC_IN
OSC_OUT
XTAL OSC
4- 48 MHz
LSI
PLL1+PLL2+PLL3
WDG_LS_D1
@VDD
SUPPLY SUPERVISION
POR/PDR/BOR
POR
VDDA, VSSA
NRESET
WKUP[5:0]
reset
Int
PVD
MSv50638V4
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3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
®
®
The Arm Cortex -M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
®
The Cortex -M7 processor is a highly efficient high-performance featuring:
Six-stage dual-issue pipeline
Dynamic branch prediction
Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
64-bit AXI interface
64-bit ITCM interface
2x32-bit DTCM interfaces
The following memory interfaces are supported:
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
AXI Bus interface to optimize Burst transfers
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H750xB family.
®
®
Note:
Cortex -M7 with FPU core is binary compatible with the Cortex -M4 core.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
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3.3
Memories
3.3.1
Embedded Flash memory
The STM32H750xB devices embed 128 Kbytes of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as follows:
•
128 Kbytes of user Flash memory containing 128 Kbytes of System Flash memory
from which the device can boot
2 Kbytes (64 Flash words) of user option bytes for user configuration
3.3.2
Secure access mode
In addition to other typical memory protection mechanism (RDP, PCROP), STM32H750xB
devices introduce the Secure access mode, a new enhanced security feature. This mode
allows developing user-defined secure services by ensuring, on the one hand code and
data protection and on the other hand code safe execution.
Two types of secure services are available:
STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure
services are proprietary user firmware update solution, secure Flash integrity check or
any other sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user Flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
®
The above secure services are available only for Cortex -M7 core operating in Secure
access mode. The other masters cannot access the option bytes involved in Secure access
mode settings or the Flash secured areas.
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3.3.3
Embedded SRAM
All devices feature:
512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
SRAM1 mapped on D2 domain: 128 Kbytes
SRAM2 mapped on D2 domain: 128 Kbytes
SRAM3 mapped on D2 domain: 32 Kbytes
SRAM4 mapped on D3 domain: 64 Kbytes
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or V
mode.
BAT
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed
either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave
of the CPU(AHBP):
–
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
–
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
®
load/store operations) thanks to the Cortex -M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
7 ECC bits are added per 32-bit word.
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.4
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
All Flash address space
All RAM address space: ITCM, DTCM RAMs and SRAMs
The System memory bootloader
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The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5
Power supply management
3.5.1
Power supply scheme
STM32H750xB power supply voltages are the following:
V
pins.
= 1.62 to 3.6 V: external power supply for I/Os, provided externally through V
DD
DD
V
= 1.62 to 3.6 V: supply voltage for the internal regulator supplying V
DDLDO
CORE
V
= 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
DDA
OPAMP.
V
V
:
DD33USB and DD50USB
V
can be supplied through the USB cable to generate the V
via the
DD50USB
DD33USB
USB internal regulator. This allows supporting a V supply different from 3.3 V.
DD
The USB regulator can be bypassed to supply directly V
if V = 3.3 V.
DD
DD33USB
V
V
= 1.2 to 3.6 V: power supply for the V
domain when V is not present.
SW DD
BAT
: V
supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
CAP
CORE
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The V domain is split into the
CORE
following power domains that can be independently switch off.
®
–
–
–
D1 domain containing some peripherals and the Cortex -M7 core.
D2 domain containing a large part of the peripherals.
D3 domain containing some peripherals and the system control.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
When V is below 1 V, other power supplies (V
, V
, V
) must
DD
DDA
DD33USB
DD50USB
remain below V + 300 mV.
DD
When V is above 1 V, all power supplies are independent.
DD
During the power-down phase, V can temporarily become lower than other supplies only
DD
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
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Figure 2. Power-up/power-down sequence
V
3.8
(1)
VDDX
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
VDDX < VDD + 300 mV
Power-down
time
VDDX independent from VDD
MSv47490V1
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB
.
3.5.2
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
Power-on reset (POR)
The POR supervisor monitors V power supply and compares it to a fixed threshold.
DD
The devices remain in Reset mode when V is below this threshold,
DD
Power-down reset (PDR)
The PDR supervisor monitors V power supply. A reset is generated when V drops
DD
DD
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
Brownout reset (BOR)
The BOR supervisor monitors V power supply. Three BOR thresholds (from 2.1 to
DD
2.7 V) can be configured through option bytes. A reset is generated when V drops
DD
below this threshold.
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3.5.3
Voltage regulator
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
Run mode (VOS0 to VOS3)
–
–
–
–
Scale 0: boosted performance (available only with LDO regulator)
Scale 1: high performance
Scale 2: medium performance and consumption
Scale 3: optimized performance and low-power consumption
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
3.6
Low-power strategy
There are several ways to reduce power consumption on STM32H750xB:
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
Save power consumption when the CPU is idle, by selecting among the available low-
power mode according to the user application needs. This allows achieving the best
compromise between short startup time, low-power consumption, as well as available
wakeup sources.
The devices feature several low-power modes:
CSleep (CPU clock stopped)
CStop (CPU sub-system clock stopped)
DStop (Domain bus matrix clock stopped)
Stop (System clock stopped)
DStandby (Domain powered down)
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
®
the Cortex -Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
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Table 2. System vs domain low-power mode
D1 domain power
mode
D2 domain power
mode
D3 domain power
mode
System power mode
Run
Stop
DRun/DStop/DStandby DRun/DStop/DStandby
DRun
DStop
DStop/DStandby
DStandby
DStop/DStandby
DStandby
Standby
DStandby
3.7
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
Internal oscillators:
–
–
–
–
64 MHz HSI clock
48 MHz RC oscillator
4 MHz CSI clock
32 kHz LSI clock
External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
–
LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
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3.7.2
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
Power-on reset (pwr_por_rst)
Brownout reset
Low level on NRST pin (external reset)
Window watchdog
Independent watchdog
Software reset
Low-power mode security reset
Exit from Standby
3.8
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 3).
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Figure 3. STM32H750xB bus matrix
AHBS
CPU
ITCM
Cortex-M7
D$
64 Kbyte
I$
DTCM
Ethernet
MAC
DMA1
DMA2
SDMMC2 USBHS1 USBHS2
16KB 16KB
128 Kbyte
SDMMC1 MDMA
DMA2D
LTDC
D1-to-D2 AHB
SRAM1 128
Kbyte
APB3
AHB3
SRAM2 128
Kbyte
SRAM3
32 Kbyte
Flash
memory
AHB1
AHB2
APB1
APB2
128 Kbytes
AXI SRAM
512 Kbyte
QSPI
FMC
64-bit AXI bus matrix
32-bit AHB bus matrix
D2 domain
D1 domain
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D3 AHB
32-bit AHB bus matrix
BDMA
D3 domain
Legend
AHB4
APB4
TCM AHB
32-bit bus
AXI
APB
SRAM4
64 Kbyte
Master interface
Slave interface
64-bit bus
Backup
SRAM
Bus multiplexer
4 Kbyte
MSv50639V1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Functional overview
3.10
DMA controllers
The devices feature four DMA instances to unload CPU activity:
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
®
access Cortex -M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11
Chrom-ART Accelerator (DMA2D)
The Chrom-Art Accelerator (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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3.12
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines
®
of the Cortex -M7 with FPU core.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events .
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
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3.15
Flexible memory controller (FMC)
The FMC controller main features are the following:
Interface with static-memory mapped devices including:
–
–
–
–
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
3.16
Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
Direct mode through registers
External Flash status register polling mode
Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17
Analog-to-digital converters (ADCs)
The STM32H750xB devices embed three analog-to-digital converters, which resolution can
be configured to 16, 14, 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18
Temperature sensor
STM32H750xB devices embed a temperature sensor that generates a voltage (V ) that
TS
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from ?40 up to +125 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.19
VBAT operation
The V
power domain contains the RTC, the backup registers and the backup SRAM.
BAT
To optimize battery duration, this power domain is supplied by V when available or by the
DD
voltage applied on VBAT pin (when V supply is not present). V
power is switched
DD
BAT
when the PDR detects that V dropped below the PDR level.
DD
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by V , in which case, the V mode is not functional.
DD
BAT
V
operation is activated when V is not present.
DD
BAT
The V
pin supplies the RTC, the backup registers and the backup SRAM.
BAT
Note:
When the microcontroller is supplied from V
, external interrupts and RTC alarm/events
BAT
do not exit it from V
operation.
BAT
When PDR_ON pin is connected to V (Internal Reset OFF), the V
functionality is no
BAT
SS
more available and V
pin should be connected to VDD.
BAT
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3.20
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel including DMA underrun error detection
external triggers for conversion
input voltage reference V
or internal VREFBUF reference.
REF+
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21
Ultra-low-power comparators (COMP)
STM32H750xB devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
An external I/O
A DAC output channel
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22
Operational amplifiers (OPAMP)
STM32H750xB devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
One positive input connected to DAC
Output connected to internal ADC
Low input bias current down to 1 nA
Low input offset voltage down to 1.5 mV
Gain bandwidth up to 7.3 MHz
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The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
8 multiplexed input digital serial channels:
–
–
–
–
–
configurable SPI interface to connect various SD modulator(s)
configurable Manchester coded 1 wire interface support
PDM (Pulse Density Modulation) microphone input support
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
clock output for SD modulator(s): 0..20 MHz
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
internal sources: ADC data or memory data streams (DMA)
–
4 digital filter modules with adjustable digital signal processing:
x
–
–
Sinc filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
integrator: oversampling ratio (1..256)
up to 24-bit output data resolution, signed output data format
automatic data offset correction (offset stored in register by user)
continuous or single conversion
start-of-conversion triggered by:
–
–
–
–
software trigger
internal timers
external events
start-of-conversion synchronously with first digital filter module (DFSDM0)
analog watchdog feature:
–
–
–
–
low value and high value data threshold registers
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
input from final output data or from selected input digital serial channels
continuous monitoring independently from standard conversion
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Functional overview
short circuit detector to detect saturated analog input values (bottom and top range):
–
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
monitoring continuously each input serial channel
break signal generation on analog watchdog event or on short circuit detector event
extremes detector:
–
–
storage of minimum and maximum values of final conversion data
refreshed by software
DMA capability to read the final conversion data
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Table 3. DFSDM implementation
DFSDM features
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
Number of external triggers
X
16
Regular channel information in
identification register
X
3.24
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports Continuous mode or Snapshot (a single frame) mode
Capability to automatically crop the image
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3.25
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2 display layers with dedicated FIFO (64x64-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events
AXI master interface with burst of 16 words
3.26
JPEG Codec (JPEG)
The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 10918-
1 specification. It provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features are as follows:
8-bit/channel pixel depths
Single clock per pixel encoding and decoding
Support for JPEG header generation and parsing
Up to four programmable quantization tables
Fully programmable Huffman tables (two AC and two DC)
Fully programmable minimum coded unit (MCU)
Encode/decode support (non simultaneous)
Single clock Huffman coding and decoding
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
Support for single greyscale component
Ability to enable/disable header processing
Fully synchronous design
Configuration for High-speed decode mode
3.27
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
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3.28
Cryptographic acceleration (CRYP and HASH)
The devices embed a cryptographic processor that supports the advanced cryptographic
algorithms usually required to ensure confidentiality, authentication, data integrity and non-
repudiation when exchanging messages with a peer:
Encryption/Decryption
–
DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
–
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (Counter
mode) chaining algorithms, 128, 192 or 256-bit key
Universal HASH
–
–
–
SHA-1 and SHA-2 (secure HASH algorithms)
MD5
HMAC
The cryptographic accelerator supports DMA request generation.
3.29
Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten general-
purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Max
Max
DMA
request
generation channels
Capture/ Comple-
compare mentary
timer
clock
Timer
type
Counter Counter Prescaler
interface
clock
Timer
resolution
type
factor
output
(MHz)
(MHz)
(1)
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
High-
resolution HRTIM1
timer
16-bit
Up
Yes
Yes
10
4
Yes
480
120
480
240
Any
integer
Down, between1
Up,
Advanced TIM1,
-control
16-bit
Yes
TIM8
Up/down
and
65536
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Table 4. Timer feature comparison (continued)
Max
timer
clock
Max
interface
clock
DMA
request
generation channels
Capture/ Comple-
compare mentary
Timer
Timer
Counter Counter Prescaler
type
resolution
type
factor
output
(MHz)
(MHz)
(1)
Any
Up,
integer
TIM2,
TIM5
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Down, between1
Up/down
Yes
Yes
No
4
4
2
1
2
1
0
0
No
120
120
120
120
120
120
120
120
240
240
240
240
240
240
240
240
and
65536
Any
integer
Down, between1
Up,
TIM3,
TIM4
No
No
No
1
Up/down
and
65536
Any
integer
between1
and
TIM12
Up
65536
General
purpose
Any
integer
between1
and
TIM13,
TIM14
Up
Up
Up
Up
Up
No
65536
Any
integer
between1
and
TIM15
Yes
Yes
Yes
No
65536
Any
integer
between1
and
TIM16,
TIM17
1
65536
Any
integer
between1
and
TIM6,
TIM7
Basic
No
No
65536
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
Low-
power
timer
1, 2, 4, 8,
16, 32, 64,
128
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
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Functional overview
3.29.1
High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, Burst mode
controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
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3.29.2
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (Edge- or Center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.29.3
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H750xB
devices (see Table 4 for differences).
TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
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Functional overview
3.29.4
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.29.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / One-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
Programmable digital glitch filter
Encoder mode
3.29.6
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.29.7
3.29.8
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
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3.30
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
Three anti-tamper detection pins with programmable filter.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in V
mode and in all low-power modes when it is clocked by the
BAT
LSE. When clocked by the LSI, the RTC is not functional in V
all low-power modes.
mode, but is functional in
BAT
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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Functional overview
3.31
Inter-integrated circuit interface (I2C)
2
STM32H750xB devices embed four I C interfaces.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and Master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
Power System Management Protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
3.32
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H750xB devices have four embedded universal synchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7 and UART8). Refer to Table 5 for a summary of
USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 5. USART features
USART modes/features(1)
USART1/2/3/6
UART4/5/7/8
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode (Master/Slave)
Smartcard mode
-
Single-wire Half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
X
X
Dual clock domain and wakeup from low power mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
X
Tx/Rx FIFO size
16
1. X = supported.
3.33
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
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The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.34
Serial peripheral interfaces (SPI)/integrated interchip
sound interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-
duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
2
Three standard I S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in Simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
2
I S interfaces is/are configured in Master mode, the master clock can be output to the
2
external DAC/CODEC at 256 times the sampling frequency. All I S interfaces support 16x 8-
bit embedded Rx and Tx FIFOs with DMA capability.
3.35
Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
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3.36
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.37
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
Full-duplex communication mode
automatic SWP bus state management (active, suspend, resume)
configurable bitrate up to 2 Mbit/s
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
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Functional overview
3.38
Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
32 x 16-bit firmware read-only, MDIO write-only input data registers
Configurable slave (port) address
Independently maskable interrupts/events:
–
–
–
MDIO Register write
MDIO Register read
MDIO protocol error
Able to operate in and wake up from Stop mode
3.39
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.40
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
DS12556 Rev 5
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52
Functional overview
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3.41
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1
features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using
the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
9 bidirectional endpoints (including EP0)
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Battery Charging Specification Revision 1.2 support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.42
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
50/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Functional overview
The devices include the following features:
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
3.43
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.44
Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
Breakpoint debugging
Code execution tracing
Software instrumentation
JTAG debug port
Serial-wire debug port
Trigger input and output
Serial-wire trace port
Trace port
®
Arm CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools.
The trace port performs data capture for logging and analysis.
DS12556 Rev 5
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52
Memory mapping
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
4
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
5
Pin descriptions
Figure 4. LQFP100 pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PE2
1
2
3
4
5
6
7
8
9
75 VDD
74 VSS
73 VCAP
72 PA13
71 PA12
70 PA11
69 PA10
68 PA9
67 PA8
66 PC9
65 PC8
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
VSS 10
VDD 11
PH0-OSC_IN 12
64 PC7
63 PC6
100-pins
PH1-OSC_OUT 13
NRST 14
PC0 15
62 PD15
61 PD14
60 PD13
59 PD12
58 PD11
57 PD10
56 PD9
PC1 16
PC2_C 17
PC3_C 18
VSSA 19
VREF+ 20
VDDA 21
PA0 22
55 PD8
54 PB15
53 PB14
52 PB13
51 PB12
PA1 23
PA2 24
PA3 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MSv41918V4
1. The above figure shows the package top view.
DS12556 Rev 5
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93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 5. LQFP144 pinout
VDD
VSS
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
9
108
107
106
105
104
103
102
101
100
99
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0 10
PF1 11
PF2 12
98
97
96
PC6
PF3 13
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PF4 14
PF5 15
VSS 16
VDD 17
PF6 18
PF7 19
PF8 20
PF9 21
95
94
93
92
91
90
89
88
87
86
85
84
144-pins
PF10 22
PH0-OSC_IN 23
PH1-OSC_OUT 24
NRST 25
PC0 26
83
PD13
PD12
PD11
PD10
PD9
PC1 27
82
81
80
79
78
77
76
75
PC2_C 28
PC3_C 29
VDD 30
VSSA 31
VREF+ 32
VDDA 33
PA0 34
PD8
PB15
PB14
PB13
PB12
PA1 35
74
73
PA2 36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
MSv41917V4
1. The above figure shows the package top view.
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 6. LQFP176 pinout
Pin descriptions
1
2
3
4
5
6
7
8
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PE2
PI1
PE3
PI0
PE4
PH15
PH14
PH13
VDD
VSS
PE5
PE6
VBAT
PI8
PC13
VCAP
PA13
PA12
PA11
PA10
PA9
9
PC14-OSC32_IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PC15-OSC32_OUT
PI9
PI10
PI11
VSS
PA8
VDD
PC9
PF0
PC8
PF1
PC7
PF2
PC6
PF3
VDD33USB
VSS
PF4
PF5
PG8
176-pins
VSS
PG7
VDD
PG6
PF6
PG5
PF7
PG4
PF8
PG3
PF9
PG2
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PC1
PC2_C
PC3_C
VDD
98
97
96
95
94
93
92
91
VSSA
VREF+
VDDA
PA0
PD8
PB15
PB14
PB13
PB12
VDD
VSS
PA1
PA2
90
89
PH2
PH3
PH12
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
MSv41916V5
1. The above figure shows the package top view.
DS12556 Rev 5
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93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 7. UFBGA176+25 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
C
D
E
F
PE3
PE2
PE1
PE0
PB8
PB5
PG14
PG13
PB4
PB3
PD7
PA15
PA14
PA13
PC12
PE4
PE5
PI7
PE6
PI6
PB9
PI5
PB7
VDD
VSS
PB6
PG15
VDD
VSS
PG12
VDD
VSS
PG11
VDD
VSS
PG10
PG9
PD4
PD6
PD5
PD3
PC11
PI3
PC10
PI2
PA12
PA11
PA10
PA9
PD0
PD1
PD2
PH13
VSS
VSS
VSS
VDD
VBAT
PC13
PDR_ON
BOOT0
PI8
PI9
PI4
PH15
PH14
VCAP
VDD
PI1
PC14-
OSC32_
IN
PC15-
OSC32_
OUT
PF0
VSS
VSS
PF2
PF3
PF6
PF9
PC0
PA1
PA2
PA3
PI10
VDD
VDD
PF1
PF4
PF5
PF8
PC1
PA0
PA6
PA7
PI11
PH2
PH3
PH4
PH5
VDD
VSS
PI0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PC9
PC8
PG8
PG7
PG4
PD15
PD14
PD11
PD9
PB14
PA8
PH0-
OSC_IN
G
H
J
PC7
PH1-
OSC_
OUT
VDD
33USB
PC6
NRST
VDD
PG5
PG6
K
L
PF7
PG3
PH12
PH11
PF10
PH10
PH9
PG2
M
N
P
R
VSSA
VREF-
VREF+
VDDA
PC2_C PC3_C
PB2
PF13
PF12
PF11
PG1
PG0
VSS
VDD
PE8
PE7
VSS
VDD
PE9
VCAP
VDD
PH6
PE13
PE14
PE15
PD13
PD10
PD8
PH8
PH7
PA4
PA5
PB1
PC4
PC5
PB0
PD12
PB13
PB11
PF15
PF14
PE11
PE12
PB12
PB10
PE10
PB15
MSv41912V3
1. The above figure shows the package top view.
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 8. TFBGA240+25 ballout
Pin descriptions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VDD
LDO
VCAP
VSS
VSS
PI6
PI4
PB5
PK5
PG10
PG9
PD5
PD4
PC10
PA15
PI1
PI0
PI5
A
B
C
D
E
F
VBAT
VSS
PI7
PE1
PE0
PB9
PI8
PB6
PB7
PB8
PE6
VDD
VDD
VDD
PF4
VDD
VDD
VDD
PA0
PI15
PA7
PB1
PB0
VSS
PB3
PB4
PK6
PK7
PK4
PK3
PG11
PG12
PJ15
VSS
PD6
PD7
PJ12
VDD
PD3
PC12
PD2
PD1
PC11
VSS
PD0
PC8
PC7
VDD
VDD
VDD
VDD
VDD
VDD
PJ8
PA14
PI3
PI2
PA13
PA9
PH15
VSS
PH13
PA12
PG7
VSS
PG2
VSS
NC
PH14
PC15-
OSC32_
OUT
PC14-
OSC32_ PE2
IN
VDD
LDO
VCAP
PA11
PE5
PE4
PE3
PC13
PI10
PF1
PG15
VDD
PG14 PG13
PJ14
PJ13
PA10
PC9
PDR_
ON
BOO
VDD
T0
NC
PI9
PA8
VDD33
USB
NC
NC
PI11
PF0
PF3
PF5
PF8
PF9
PC3
PA1
PH5
VSS
PC4
PC5
PC6
PG8
PG6
PG3
PK1
VDD50
USB
PF2
PI12
NC
VSS
VSS
VSS
VSS
VSS
PG5
PG4
G
H
J
PI13
PI14
VSS
PF7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PK2
VSS
NC
PH0-
OSC_
OUT
PH0-
OSC_IN
PK0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NRST
VDDA
VREF+
VREF-
VSSA
PF6
PC0
PC1
PH2
PH3
PJ11
PJ10
PJ9
VSS
VSS
VSS
PJ6
K
L
PF10
PC2
PA2
NC
NC
NC
NC
M
N
P
R
T
PJ0
PJ1
PB2
PJ2
PJ3
VDD
PF13
PF12
PF11
PJ4
VDD
PF14
VSS
PG0
PG1
PE10
PE9
VDD
PE11
PE12
PE13
PE14
VDD
PB10
PE15
VDD
PB11
PJ5
PJ7
VSS
PD14
PD12
PD10
PD8
NC
PH4
PA6
PH10
PH9
PH8
PH7
PH11
PH12
PB12
PB13
PD15
PD11
PB15
PB14
VDD
PD13
PD9
VSS
PC2_C PC3_C
PA0_C PA1_C
PF15
PE8
PA5
PH6
VSS
VDD
LDO
VCAP
VSS
PA3
PA4
PE7
U
MSv41911V2
1. The above figure shows the package top view.
DS12556 Rev 5
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93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 6. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
ANA
FT
TT
B
Input / output pin
Analog-only Input
5 V tolerant I/O
3.3 V tolerant I/O
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
RST
I/O structure
Option for TT and FT I/Os
_f
I2C FM+ option
_a
_u
_h
analog option (supplied by VDDA)
USB option (supplied by VDD33USB
)
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
functions
Functions directly selected/enabled through peripheral registers
58/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TRACECLK, SAI1_CK1,
SPI4_SCK, SAI1_MCLK_A,
SAI4_MCLK_A,
QUADSPI_BK1_IO2, SAI4_CK1,
ETH_MII_TXD3, FMC_A23,
EVENTOUT
1
1
A2
1
C3
PE2
I/O
FT_h
-
-
TRACED0, TIM15_BKIN,
SAI1_SD_B, SAI4_SD_B,
FMC_A19, EVENTOUT
2
3
2
3
A1
B1
2
3
D3
D2
PE3
PE4
I/O
I/O
FT_h
FT_h
-
-
-
-
TRACED1, SAI1_D2,
DFSDM1_DATIN3, TIM15_CH1N,
SPI4_NSS, SAI1_FS_A,
SAI4_FS_A, SAI4_D2, FMC_A20,
DCMI_D4, LCD_B0, EVENTOUT
TRACED2, SAI1_CK2,
DFSDM1_CKIN3, TIM15_CH1,
SPI4_MISO, SAI1_SCK_A,
SAI4_SCK_A, SAI4_CK2,
FMC_A21, DCMI_D6, LCD_G0,
EVENTOUT
4
5
4
5
B2
B3
4
5
D1
E5
PE5
PE6
I/O
I/O
FT_h
FT_h
-
-
-
-
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7, LCD_G1,
EVENTOUT
-
-
-
-
H10
-
-
-
A1
-
VSS
VDD
VBAT
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
-
6
-
C1
J6
6
-
B1
B2
RTC_
-
-
D2
D1
7
8
E4
E3
PI8
I/O
I/O
FT
FT
-
-
EVENTOUT
EVENTOUT
TAMP2/
WKUP3
RTC_
TAMP1/
RTC_TS/
WKUP2
7
7
PC13
VSS
-
-
J7
-
B6
C2
S
-
-
-
-
-
PC14-
8
8
E1
9
OSC32_IN
I/O
FT
EVENTOUT
OSC32_IN
(OSC32_IN)(1)
DS12556 Rev 5
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Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
PC15-
OSC32_OUT
(OSC32_OUT)(1)
OSC32_
OUT
9
-
9
-
F1
D3
10
11
C1
E2
I/O
I/O
FT
-
-
EVENTOUT
UART4_RX, FDCAN1_RX,
FMC_D30, LCD_VSYNC,
EVENTOUT
PI9
FT_h
-
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER, FMC_D31,
LCD_HSYNC, EVENTOUT
-
-
-
-
E3
E4
12
13
F3
F4
PI10
PI11
I/O
I/O
FT_h
FT
-
-
LCD_G6, OTG_HS_ULPI_DIR,
EVENTOUT
WKUP4
-
-
-
-
-
-
-
-
-
F2
F3
-
14
15
-
A17
E6
VSS
VDD
NC
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E1(2)
F1(3)
G2(4)
G4
-
-
-
-
-
-
-
NC
-
-
-
-
-
NC
-
-
-
10
11
E2
H3
16
17
PF0
PF1
I/O
I/O
FT_f
FT_f
I2C2_SDA, FMC_A0, EVENTOUT
I2C2_SCL, FMC_A1, EVENTOUT
G3
I2C2_SMBA, FMC_A2,
EVENTOUT
-
12
H2
18
G1
PF2
I/O
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H1
H2
H3
PI12
PI13
PI14
I/O
I/O
I/O
FT
FT
-
-
-
LCD_HSYNC, EVENTOUT
LCD_VSYNC, EVENTOUT
LCD_CLK, EVENTOUT
-
-
-
FT_h
ADC3_
INP5
-
-
-
13
14
15
J2
J3
K3
19
20
21
H4
J5
J4
PF3
PF4
PF5
I/O
I/O
I/O
FT_ha
FT_ha
FT_ha
-
-
-
FMC_A3, EVENTOUT
FMC_A4, EVENTOUT
FMC_A5, EVENTOUT
ADC3_
INN5,
ADC3_
INP9
ADC3_
INP4
10
11
16
17
G2
G3
22
23
C10
E9
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
SAI4_SD_B, QUADSPI_BK1_IO3,
EVENTOUT
ADC3_
INN4,
ADC3_
INP8
-
18
K2
24
K2
PF6
I/O
FT_ha
-
60/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
SAI4_MCLK_B,
ADC3_
INP3
-
-
-
19
20
21
K1
L3
L2
25
26
27
K3
K4
L4
PF7
PF8
I/O
I/O
I/O
FT_ha
FT_ha
FT_ha
-
-
-
QUADSPI_BK1_IO2, EVENTOUT
TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE,
SAI4_SCK_B, TIM13_CH1,
QUADSPI_BK1_IO0, EVENTOUT
ADC3_
INN3,
ADC3_
INP7
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS,
SAI4_FS_B, TIM14_CH1,
ADC3_
INP2
PF9
QUADSPI_BK1_IO1, EVENTOUT
ADC3_
INN2,
ADC3_
INP6
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK, SAI4_D3,
DCMI_D11, LCD_DE, EVENTOUT
-
22
23
L1
28
29
L3
J2
PF10
I/O
I/O
FT_ha
FT
-
-
PH0-OSC_IN
(PH0)
12
G1
EVENTOUT
OSC_IN
PH1-OSC_OUT
(PH1)
13
14
24
25
H1
J1
30
31
J1
I/O
I/O
FT
-
-
EVENTOUT
-
OSC_OUT
-
K1
NRST
RST
DFSDM1_CKIN0,
DFSDM1_DATIN4, SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_
INP10
15
26
M2
32
L2
PC0
I/O
FT_a
-
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A, SAI4_SD_A,
SDMMC2_CK, SAI4_D1,
ETH_MDC, MDIOS_MDC,
EVENTOUT
ADC123_
INN10,
ADC123_
INP11,
RTC_
TAMP3/
WKUP5
16
27
M3
33
M2
PC1
I/O
FT_ha
-
ADC123_
INN11,
ADC123_
INP12
M3(5)
PC2
I/O
FT_a
TT_a
-
-
CDSLEEP, DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2, FMC_SDNE0,
EVENTOUT
-
-
-
-
ADC3_
INN1,
ADC3_
INP0
17(6) 28(6) M4(6) 34(6) R1(5)
PC2_C
ANA
DS12556 Rev 5
61/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
ADC12_
INN12,
ADC12_
INP13
-
-
-
-
M4(5)
PC3
I/O
FT_a
TT_a
-
-
CSLEEP, DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0, EVENTOUT
ADC3_
INP1
18(6) 29(6) M5(6) 35(6) R2(5)
PC3_C
ANA
-
-
30
-
G3
J10
M1
N1
P1
36
-
E11
C13
P1
VDD
VSS
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
19
-
31
-
37
-
VSSA
VREF-
VREF+
VDDA
N1
20
21
32
33
38
39
M1
L1
R1
ADC1_
INP16,
WKUP0
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
22
-
34
-
N3
-
40
-
N5(5)
PA0
I/O
FT_a
TT_a
-
-
USART2_CTS/USART2_NSS,
UART4_TX, SDMMC2_CMD,
SAI2_SD_B, ETH_MII_CRS,
EVENTOUT
ADC12_
INN1,
ADC12_
INP0
T1(5)
PA0_C
ANA
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT, TIM15_CH1N,
USART2_RTS/USART2_DE,
UART4_RX, QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ADC1_
INN16,
ADC1_
INP17
23
-
35
-
N2
-
41
-
N4(5)
PA1
I/O
FT_ha
TT_a
-
-
ADC12_
INP1
T2(5)
PA1_C
ANA
ETH_MII_RX_CLK/ETH_RMII_RE
F_CLK, LCD_R2, EVENTOUT
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT, TIM15_CH1,
USART2_TX, SAI2_SCK_B,
ETH_MDIO, MDIOS_MDIO,
LCD_R1, EVENTOUT
ADC12_
INP14,
WKUP1
24
36
P2
F4
42
43
N3
N2
PA2
PH2
I/O
I/O
FT_a
-
-
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B, ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
ADC3_
INP13
-
-
FT_ha
-
-
-
-
-
-
-
F5
VDD
VSS
S
S
-
-
-
-
-
-
-
-
J8
C16
62/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
QUADSPI_BK2_IO1,
SAI2_MCLK_B, ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
ADC3_
INN13,
ADC3_
INP14
-
-
-
-
-
-
G4
H4
J4
44
45
46
P2
P3
P4
PH3
PH4
PH5
I/O
I/O
I/O
FT_ha
FT_fa
FT_fa
-
-
-
ADC3_
INN14,
ADC3_
INP15
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT, LCD_G4,
EVENTOUT
ADC3_
INN15,
ADC3_
INP16
I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT, TIM15_CH2,
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ADC12_
INP15
25
37
R2
47
U2
PA3
I/O
FT_ha
-
ETH_MII_COL, LCD_B5,
EVENTOUT
26
-
38
-
K6
L4
K4
-
F2(4)
-
VSS
VSS
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
48
49
27
39
G5
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
ADC12_
INP18,
DAC1_
OUT1
28
29
40
41
N4
P4
50
51
U3
T3
PA4
PA5
I/O
I/O
TT_a
-
-
USART2_CK, SPI6_NSS,
OTG_HS_SOF, DCMI_HSYNC,
LCD_VSYNC, EVENTOUT
ADC12_
INN18,
ADC12_
INP19,
DAC1_
OUT2
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, SPI1_SCK/I2S1_CK,
SPI6_SCK, OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
TT_ha
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO, TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
ADC12_
INP3
30
42
P3
52
R3
PA6
I/O
FT_a
-
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
DS12556 Rev 5
63/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
ADC12_
INN3,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI, TIM14_CH1,
ETH_MII_RX_DV/ETH_RMII_CRS OPAMP1_
ADC12_
INP7,
31
32
33
43
44
45
R3
N5
P5
53
54
55
R5
T4
U4
PA7
PC4
PC5
I/O
I/O
I/O
TT_a
TT_a
TT_a
-
-
-
_DV, FMC_SDNWE, EVENTOUT
VINM
ADC12_
INP4,
OPAMP1_
VOUT,
COMP1_
INM
DFSDM1_CKIN2, I2S1_MCK,
SPDIFRX1_IN3,
ETH_MII_RXD0/ETH_RMII_RXD0
, FMC_SDNE0, EVENTOUT
ADC12_
INN4,
ADC12_
INP8,
OPAMP1_
VINM
SAI1_D3, DFSDM1_DATIN2,
SPDIFRX1_IN4, SAI4_D3,
ETH_MII_RXD1/ETH_RMII_RXD1
, FMC_SDCKE0, COMP1_OUT,
EVENTOUT
-
-
-
-
-
-
-
G13
R4
VDD
VSS
S
S
-
-
-
-
-
-
-
-
J9
ADC12_
INN5,
ADC12_
INP9,
OPAMP1_
VINP,
COMP1_
INP
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
34
46
R5
56
U5
PB0
I/O
FT_a
-
ETH_MII_RXD2, LCD_G1,
EVENTOUT
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, DFSDM1_DATIN1,
LCD_R6, OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT
ADC12_
INP5,
COMP1_
INM
35
36
47
48
R4
M6
57
58
T5
R6
PB1
PB2
I/O
I/O
TT_u
-
-
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1, SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A, QUADSPI_CLK,
SAI4_D1, EVENTOUT
COMP1_
INP
FT_ha
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P5
N6
P6
T6
U6
PI15
PJ0
PJ1
PJ2
PJ3
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
-
-
-
-
-
LCD_G2, LCD_R0, EVENTOUT
LCD_R7, LCD_R1, EVENTOUT
LCD_R2, EVENTOUT
-
-
-
-
-
LCD_R3, EVENTOUT
LCD_R4, EVENTOUT
64/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
-
-
-
-
-
U7
T7
PJ4
I/O
I/O
FT
-
-
LCD_R5, EVENTOUT
-
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS, DCMI_D12,
EVENTOUT
ADC1_
INP2
49
R6
59
PF11
FT_a
ADC1_
INN2,
ADC1_
INP6
-
50
P6
60
R7
PF12
I/O
FT_ha
-
FMC_A6, EVENTOUT
-
-
51
52
M8
N8
61
62
J3
VSS
VDD
S
S
-
-
-
-
-
-
-
-
H5
DFSDM1_DATIN6, I2C4_SMBA,
FMC_A7, EVENTOUT
ADC2_
INP2
-
53
N6
63
P7
PF13
I/O
FT_ha
-
ADC2_
INN2,
ADC2_
INP6
DFSDM1_CKIN6, I2C4_SCL,
FMC_A8, EVENTOUT
-
54
R7
64
P8
PF14
I/O
FT_fha
-
-
-
-
-
55
56
-
P7
N7
F6
-
65
66
-
R9
T8
PF15
PG0
VSS
VDD
I/O
I/O
S
FT_fh
-
-
-
-
I2C4_SDA, FMC_A9, EVENTOUT
-
-
-
-
FT_h
FMC_A10, EVENTOUT
J16
H13
-
-
-
-
-
-
S
OPAMP2_
VINM
-
57
M7
67
U8
PG1
I/O
TT_h
-
FMC_A11, EVENTOUT
OPAMP2_
VOUT,
COMP2_
INM
TIM1_ETR, DFSDM1_DATIN2,
UART7_RX, QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4, EVENTOUT
37
58
R8
68
U9
PE7
I/O
TT_ha
-
TIM1_CH1N, DFSDM1_CKIN2,
UART7_TX, QUADSPI_BK2_IO1, OPAMP2_
38
39
59
60
P8
P9
69
70
T9
P9
PE8
PE9
I/O
I/O
TT_ha
TT_ha
-
-
FMC_D5/FMC_DA5,
VINM
COMP2_OUT, EVENTOUT
TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS/UART7_DE,
QUADSPI_BK2_IO2,
OPAMP2_
VINP,
COMP2_
INP
FMC_D6/FMC_DA6, EVENTOUT
-
-
61
62
M9
N9
71
72
J17
J13
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM1_CH2N, DFSDM1_DATIN4,
UART7_CTS,
COMP2_
INM
40
63
R9
73
N9
PE10
I/O
FT_ha
-
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7, EVENTOUT
DS12556 Rev 5
65/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM1_CH2, DFSDM1_CKIN4,
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8, LCD_G3,
EVENTOUT
COMP2_
INP
41
42
64
65
P10
R10
74
75
P10
R10
PE11
PE12
I/O
I/O
FT_ha
FT_h
-
-
TIM1_CH3N, DFSDM1_DATIN5,
SPI4_SCK, SAI2_SCK_B,
FMC_D9/FMC_DA9,
-
-
COMP1_OUT, LCD_B4,
EVENTOUT
TIM1_CH3, DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
43
66
N11
76
T10
PE13
I/O
FT_h
-
-
-
-
-
F7
-
-
-
T12
K13
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
FMC_D11/FMC_DA11, LCD_CLK,
EVENTOUT
44
45
67
68
P11
R11
77
78
U10
R11
PE14
PE15
I/O
I/O
FT_h
FT_h
-
-
-
-
TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12/COMP_
TIM1_BKIN, LCD_R7, EVENTOUT
TIM2_CH3, HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7, USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT
46
69
70
R12
79
80
P11
P12
PB10
PB11
I/O
I/O
FT_f
FT_f
-
-
TIM2_CH4, HRTIM_SCIN,
LPTIM2_ETR, I2C2_SDA,
DFSDM1_CKIN7, USART3_RX,
OTG_HS_ULPI_D4,
47
R13
-
-
ETH_MII_TX_EN/ETH_RMII_TX_
EN, LCD_G5, EVENTOUT
48
49
-
71
-
M10
K7
-
81
-
U11
-
VCAP
VSS
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
U12
L13
R12
VDDLDO
VDD
S
-
-
50
-
72
-
N10
-
82
-
S
-
-
PJ5
I/O
FT
LCD_R6, EVENTOUT
66/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM12_CH1, I2C2_SMBA,
SPI5_SCK, ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
-
M11
83
T11
PH6
I/O
FT
-
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3, FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
-
-
-
N12
M12
84
85
U13
T13
PH7
PH8
I/O
I/O
FT_fa
-
-
-
-
TIM5_ETR, I2C3_SDA, FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
FT_fha
-
-
-
-
F8
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
M13
TIM12_CH2, I2C3_SMBA,
FMC_D17, DCMI_D0, LCD_R3,
EVENTOUT
-
-
-
-
M13
L13
86
87
R13
P13
PH9
I/O
I/O
FT_h
FT_h
-
-
-
-
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1, LCD_R4,
EVENTOUT
PH10
TIM5_CH2, I2C4_SCL, FMC_D19,
DCMI_D2, LCD_R5, EVENTOUT
-
-
-
-
L12
K12
88
89
P14
R14
PH11
PH12
I/O
I/O
FT_fh
FT_fh
-
-
-
-
TIM5_CH3, I2C4_SDA, FMC_D20,
DCMI_D3, LCD_R6, EVENTOUT
-
-
-
-
H12
J12
90
91
N16
P17
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1, USART3_CK,
FDCAN2_RX,OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII_TXD0,
OTG_HS_ID,
51
73
P12
92
T14
PB12
I/O
FT_u
-
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
TIM1_CH1N, LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
OTG_HS_
VBUS
52
74
P13
93
U14
PB13
I/O
FT_u
-
USART3_CTS/USART3_NSS,
FDCAN2_TX, OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII_TXD1,
UART5_TX, EVENTOUT
DS12556 Rev 5
67/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM1_CH2N, TIM12_CH1,
TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3_DE,
UART4_RTS/UART4_DE,
SDMMC2_D0, OTG_HS_DM,
EVENTOUT
53
75
R14
94
U15
PB14
I/O
FT_u
-
-
RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
USART1_RX,
54
76
R15
95
T15
PB15
I/O
FT_u
-
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2, UART4_CTS,
SDMMC2_D1, OTG_HS_DP,
EVENTOUT
-
DFSDM1_CKIN3, SAI3_SCK_B,
USART3_TX, SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
55
56
77
78
P15
P14
96
97
U16
T17
PD8
PD9
I/O
I/O
FT_h
FT_h
-
-
-
-
DFSDM1_DATIN3, SAI3_SD_B,
USART3_RX,
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
DFSDM1_CKOUT, SAI3_FS_B,
USART3_CK,
57
79
N15
98
T16
PD10
I/O
FT_h
-
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15, LCD_B3,
EVENTOUT
-
-
-
-
-
-
-
-
N12
U17
VDD
VSS
S
S
-
-
-
-
-
-
-
-
F9
LPTIM2_IN2, I2C4_SMBA,
USART3_CTS/USART3_NSS,
QUADSPI_BK1_IO0, SAI2_SD_A,
FMC_A16, EVENTOUT
58
59
60
80
81
82
N14
N13
M15
99
R15
R16
R17
PD11
PD12
PD13
I/O
I/O
I/O
FT_h
FT_fh
FT_fh
-
-
-
-
-
-
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/USART3_DE,
QUADSPI_BK1_IO1, SAI2_FS_A,
FMC_A17, EVENTOUT
100
101
LPTIM1_OUT, TIM4_CH2,
I2C4_SDA, QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
68/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
-
-
83
84
K8
102
103
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
J13
N11
TIM4_CH3, SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0, EVENTOUT
61
62
85
86
M14
L14
104
105
P16
P15
PD14
PD15
I/O
I/O
FT_h
FT_h
-
-
-
-
TIM4_CH4, SAI3_MCLK_A,
UART8_RTS/UART8_DE,
FMC_D1/FMC_DA1, EVENTOUT
-
-
-
-
-
-
-
-
N15
N14
PJ6
PJ7
I/O
I/O
FT
FT
-
-
TIM8_CH2, LCD_R7, EVENTOUT
-
-
TRGIN, TIM8_CH2N, LCD_G0,
EVENTOUT
-
-
-
-
-
-
-
N10
R8
VDD
VSS
S
S
-
-
-
-
F10
TIM1_CH3N, TIM8_CH1,
UART8_TX, LCD_G1, EVENTOUT
-
-
-
-
-
-
-
-
N13
M14
PJ8
PJ9
I/O
I/O
FT
FT
-
-
-
-
TIM1_CH3, TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
-
-
-
-
-
-
-
-
L14
K14
PJ10
PJ11
I/O
I/O
FT
FT
-
-
-
-
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N8
VDD
VSS
NC
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G6
U1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N17(2)
M16(2)
M17(2)
K15
NC
-
NC
-
VSS
NC
S
-
L16(2)
L17(2)
K16(2)
K17(2)
L15
NC
-
NC
-
NC
-
VSS
S
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5, EVENTOUT
-
-
-
-
J14
PK0
I/O
FT
-
-
DS12556 Rev 5
69/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM1_CH1, TIM8_CH3N,
SPI5_NSS, LCD_G6, EVENTOUT
-
-
-
-
-
-
-
-
J15
PK1
PK2
I/O
I/O
FT
FT
-
-
-
-
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12, LCD_G7,
EVENTOUT
H17
TIM8_BKIN,
TIM8_BKIN_COMP12, FMC_A12,
EVENTOUT
-
-
87
88
L15
K15
106
107
H16
H15
PG2
PG3
I/O
I/O
FT_h
FT_h
-
-
-
-
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
-
-
-
-
G7
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
N7
TIM1_BKIN2,
-
-
-
89
90
91
K14
K13
J15
108
109
110
H14
G14
G15
PG4
PG5
PG6
I/O
I/O
I/O
FT_h
FT_h
FT_h
-
-
-
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0, EVENTOUT
-
-
-
TIM1_ETR, FMC_A15/FMC_BA1,
EVENTOUT
TIM17_BKIN, HRTIM_CHE1,
QUADSPI_BK1_NCS, FMC_NE3,
DCMI_D12, LCD_R7, EVENTOUT
HRTIM_CHE2, SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
-
92
93
J14
111
112
F16
F15
PG7
PG8
I/O
I/O
FT_h
FT_h
-
-
-
-
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_DE,
SPDIFRX1_IN3, ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
H14
-
-
-
-
94
-
G12
113
G16
G17
F17
M5
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H13
-
-
114
-
VDD50USB
VDD33USB
VDD
95
-
70/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
HRTIM_CHA1, TIM3_CH1,
TIM8_CH1, DFSDM1_CKIN3,
I2S2_MCK, USART6_TX,
63
96
H15
115
116
F14
PC6
I/O
FT_h
-
SDMMC1_D0DIR, FMC_NWAIT, SWPMI_IO
SDMMC2_D6, SDMMC1_D6,
DCMI_D0, LCD_HSYNC,
EVENTOUT
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3, I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR, FMC_NE1,
64
97
G15
F13
PC7
I/O
FT_h
-
-
SDMMC2_D7, SWPMI_TX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
TRACED1, HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
65
66
98
99
G14
F14
117
118
E13
E14
PC8
PC9
I/O
I/O
FT_h
-
-
UART5_RTS/UART5_DE,
FMC_NE2/FMC_NCE,
SWPMI_RX, SDMMC1_D0,
DCMI_D2, EVENTOUT
-
-
MCO2, TIM3_CH4, TIM8_CH4,
I2C3_SDA, I2S_CKIN,
UART5_CTS,
QUADSPI_BK1_IO0, LCD_G3,
SWPMI_SUSPEND,
FT_fh
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
-
-
-
-
G8
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
L5
MCO1, TIM1_CH1, HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK, OTG_FS_SOF,
UART7_RX,
TIM8_BKIN2_COMP12, LCD_B3,
LCD_R6, EVENTOUT
67 100 F15
119
120
E15
D15
PA8
PA9
I/O
I/O
FT_fha
FT_u
-
-
-
TIM1_CH2, HRTIM_CHC1,
LPUART1_TX, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
OTG_FS_
VBUS
68 101 E15
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5, EVENTOUT
DS12556 Rev 5
71/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM1_CH3, HRTIM_CHC2,
LPUART1_RX, USART1_RX,
FDCAN1_TXFD_MODE,
OTG_FS_ID, MDIOS_MDIO,
LCD_B4, DCMI_D1, LCD_B1,
EVENTOUT
69 102 D15
121
122
D14
E17
PA10
PA11
I/O
I/O
FT_u
FT_u
-
-
-
-
TIM1_CH4, HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS, UART4_RX,
USART1_CTS/USART1_NSS,
FDCAN1_RX, OTG_FS_DM,
LCD_R4, EVENTOUT
70 103 C15
TIM1_ETR, HRTIM_CHD2,
LPUART1_RTS/LPUART1_DE,
SPI2_SCK/I2S2_CK, UART4_TX,
USART1_RTS/USART1_DE,
SAI2_FS_B, FDCAN1_TX,
OTG_FS_DP, LCD_R5,
71 104 B15
123
124
E16
C15
PA12
I/O
I/O
FT_u
FT
-
-
-
-
EVENTOUT
PA13
(JTMS/SWDIO)
72 105 A15
JTMS-SWDIO, EVENTOUT
73 106 F13
74 107 F12
125
126
-
D17
-
VCAP
VSS
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C17
K5
VDDLDO
VDD
75 108 G13
127
S
TIM8_CH1N, UART4_TX,
FDCAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
-
-
-
E12
E13
128
129
D16
B17
PH13
PH14
I/O
FT_h
FT_h
-
-
-
-
TIM8_CH2N, UART4_RX,
FDCAN1_RX, FMC_D22,
DCMI_D4, LCD_G3, EVENTOUT
I/O
I/O
TIM8_CH3N,
FDCAN1_TXFD_MODE,
FMC_D23, DCMI_D11, LCD_G4,
EVENTOUT
-
-
D13
130
B16
PH15
FT_h
-
-
TIM5_CH4, SPI2_NSS/I2S2_WS,
FDCAN1_RXFD_MODE,
FMC_D24, DCMI_D13, LCD_G5,
EVENTOUT
-
-
-
-
E14
G9
131
-
A16
-
PI0
I/O
S
FT_h
-
-
-
-
-
VSS
-
72/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
-
-
D14
132
A15
PI1
I/O
FT_h
-
TIM8_BKIN2_COMP12,
FMC_D25, DCMI_D8, LCD_G6,
EVENTOUT
-
TIM8_CH4,SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9, LCD_G7,
EVENTOUT
-
-
-
-
C14
C13
133
134
B15
C14
PI2
PI3
I/O
I/O
FT_h
FT_h
-
-
-
-
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10,
EVENTOUT
-
-
-
-
D9
C9
135
136
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
PA14
(JTCK/SWCLK)
76 109 A14
137
B14
I/O
FT
-
JTCK-SWCLK, EVENTOUT
-
JTDI, TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
PA15
(JTDI)
SPI1_NSS/I2S1_WS,
77
78
110 A13
138
A14
I/O
FT
-
-
SPI3_NSS/I2S3_WS, SPI6_NSS,
UART4_RTS/UART4_DE,
UART7_TX, EVENTOUT
HRTIM_EEV1, DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
111 B14
139
A13
PC10
I/O
FT_ha
-
-
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
HRTIM_FLT2, DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX, UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
79
80
112 B13
140
141
B13
C12
PC11
PC12
I/O
I/O
FT_h
FT_h
-
-
-
-
TRACED3, HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK, UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT
113 A12
-
-
G10
-
-
VSS
PD0
S
-
-
-
-
-
-
DFSDM1_CKIN6, SAI3_SCK_A,
UART4_RX, FDCAN1_RX,
81
114 B12
142
D13
I/O
FT_h
FMC_D2/FMC_DA2, EVENTOUT
DS12556 Rev 5
73/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
DFSDM1_DATIN6, SAI3_SD_A,
UART4_TX, FDCAN1_TX,
FMC_D3/FMC_DA3, EVENTOUT
82
83
115 C12
116 D12
143
144
E12
D12
PD1
PD2
I/O
I/O
FT_h
FT_h
-
-
-
-
TRACED2, TIM3_ETR,
UART5_RX, SDMMC1_CMD,
DCMI_D11, EVENTOUT
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
84
117 D11
145
B12
PD3
I/O
FT_h
-
USART2_CTS/USART2_NSS,
FMC_CLK, DCMI_D5, LCD_G7,
EVENTOUT
-
HRTIM_FLT3, SAI3_FS_A,
USART2_RTS/USART2_DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
85
86
118 D10
119 C11
146
147
A12
A11
PD4
PD5
I/O
I/O
FT_h
FT_h
-
-
-
-
HRTIM_EEV3, USART2_TX,
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
-
-
120
121
D8
C8
148
149
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
SAI1_D1, DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A, USART2_RX,
SAI4_SD_A,
87 122 B11
150
B11
PD6
I/O
FT_h
-
-
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
88 123 A11
151
-
C11
D11
PD7
I/O
I/O
FT_h
FT
-
-
DFSDM1_CKIN1, USART2_CK,
SPDIFRX1_IN1, SDMMC2_CMD,
FMC_NE1, EVENTOUT
-
-
TRGOUT, LCD_G3, LCD_B0,
EVENTOUT
-
-
-
PJ12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E10
D10
B10
-
PJ13
PJ14
PJ15
VSS
VDD
I/O
I/O
I/O
S
FT
FT
FT
-
-
-
-
-
-
LCD_B4, LCD_B1, EVENTOUT
-
-
-
-
-
LCD_B2, EVENTOUT
-
LCD_B3, EVENTOUT
H6
-
-
-
-
S
-
74/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
SPI1_MISO/I2S1_SDI,
USART6_RX, SPDIFRX1_IN4,
QUADSPI_BK2_IO2, SAI2_FS_B,
FMC_NE2/FMC_NCE,
-
-
124 C10
152
153
A10
A9
PG9
I/O
I/O
FT_h
FT_h
-
-
-
-
DCMI_VSYNC, EVENTOUT
HRTIM_FLT5,
SPI1_NSS/I2S1_WS, LCD_G3,
SAI2_SD_B, FMC_NE3,
125 B10
PG10
DCMI_D2, LCD_B2, EVENTOUT
LPTIM1_IN2, HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1, SDMMC2_D2,
ETH_MII_TX_EN/ETH_RMII_TX_
EN, DCMI_D3, LCD_B3,
EVENTOUT
-
-
126
127
B9
B8
154
155
B9
C9
PG11
PG12
I/O
I/O
FT_h
FT_h
-
-
-
-
LPTIM1_IN1, HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_DE,
SPDIFRX1_IN2, LCD_B4,
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_NE4, LCD_B1, EVENTOUT
TRACED0, LPTIM1_OUT,
HRTIM_EEV10, SPI6_SCK,
-
-
128
129
A8
A7
156
157
D9
D8
PG13
PG14
I/O
I/O
FT_h
FT_h
-
-
USART6_CTS/USART6_NSS,
ETH_MII_TXD0/ETH_RMII_TXD0,
FMC_A24, LCD_R0, EVENTOUT
-
-
TRACED1, LPTIM1_ETR,
SPI6_MOSI, USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_A25, LCD_B0, EVENTOUT
-
-
-
-
-
-
-
-
130
D7
158
-
VSS
VDD
PK3
PK4
PK5
PK6
PK7
VSS
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
131
C7
159
-
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C8
B8
A8
C7
D7
-
I/O
I/O
I/O
I/O
I/O
S
FT
FT
FT
FT
FT
-
LCD_B4, EVENTOUT
LCD_B5, EVENTOUT
LCD_B6, EVENTOUT
LCD_B7, EVENTOUT
LCD_DE, EVENTOUT
-
-
-
-
H7
USART6_CTS/USART6_NSS,
FMC_SDNCAS, DCMI_D13,
EVENTOUT
-
132
B7
160
D6
PG15
I/O
FT_h
-
-
DS12556 Rev 5
75/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
JTDO/TRACESWO, TIM2_CH2,
HRTIM_FLT4,
PB3
(JTDO/TRACES
WO)
SPI1_SCK/I2S1_CK,
89 133 A10
161
162
C6
B7
I/O
I/O
FT
FT
-
-
-
-
SPI3_SCK/I2S3_CK, SPI6_SCK,
SDMMC2_D2, CRS_SYNC,
UART7_RX, EVENTOUT
NJTRST, TIM16_BKIN,
TIM3_CH1, HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS, SPI6_MISO,
SDMMC2_D3, UART7_TX,
EVENTOUT
90 134
A9
PB4(NJTRST)
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7, I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI, FDCAN2_RX,
OTG_HS_ULPI_D7,
91 135
A6
163
A5
PB5
I/O
FT
-
-
ETH_PPS_OUT, FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
-
-
H8
B6
-
-
VSS
PB6
S
-
-
-
-
-
-
TIM16_CH1N, TIM4_CH1,
HRTIM_EEV8, I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX, FDCAN2_TX,
QUADSPI_BK1_NCS,
92 136
164
B5
I/O
FT_f
DFSDM1_DATIN5, FMC_SDNE1,
DCMI_D5, UART5_TX,
EVENTOUT
TIM17_CH1N, TIM4_CH2,
HRTIM_EEV9, I2C1_SDA,
I2C4_SDA, USART1_RX,
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5, FMC_NL,
DCMI_VSYNC, EVENTOUT
93 137
94 138
B5
D6
165
166
C5
E8
PB7
I/O
FT_fa
B
-
-
PVD_IN
VPP
BOOT0
I
-
76/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7, I2C1_SCL,
I2C4_SCL, SDMMC1_CKIN,
UART4_RX, FDCAN1_RX,
SDMMC2_D4, ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
95 139
A5
B4
167
168
D5
D4
PB8
PB9
I/O
I/O
FT_fh
FT_fh
-
-
-
-
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7, I2C1_SDA,
SPI2_NSS/I2S2_WS, I2C4_SDA,
SDMMC1_CDIR, UART4_TX,
FDCAN1_TX, SDMMC2_D5,
I2C4_SMBA, SDMMC1_D5,
DCMI_D7, LCD_B7, EVENTOUT
96 140
LPTIM1_ETR, TIM4_ETR,
HRTIM_SCIN, LPTIM2_ETR,
UART8_RX,
FDCAN1_RXFD_MODE,
SAI2_MCLK_A, FMC_NBL0,
DCMI_D2, EVENTOUT
97 141
A4
A3
169
170
C4
B4
PE0
PE1
I/O
I/O
FT_h
FT_h
-
-
-
-
LPTIM1_IN2, HRTIM_SCOUT,
UART8_TX,
98 142
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
-
99
-
-
-
-
-
A7
-
VCAP
VSS
S
S
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
143
-
D5
C6
-
171
-
E7
A6
-
PDR_ON
VDDLDO
VDD
FT
-
-
S
S
100 144
C5
172
-
TIM8_BKIN, SAI2_MCLK_A,
TIM8_BKIN_COMP12,
FMC_NBL2, DCMI_D5, LCD_B4,
EVENTOUT
-
-
D4
173
A4
PI4
I/O
FT_h
-
-
TIM8_CH1, SAI2_SCK_A,
FMC_NBL3, DCMI_VSYNC,
LCD_B5, EVENTOUT
-
-
-
-
-
-
C4
C3
C2
174
175
176
A3
A2
B3
PI5
PI6
PI7
I/O
I/O
I/O
FT_h
FT_h
FT_h
-
-
-
-
-
-
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6, LCD_B6,
EVENTOUT
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7, LCD_B7,
EVENTOUT
DS12556 Rev 5
77/334
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
Pin/ball name
Pin name
(function after
reset)
Additional
functions
Alternate functions
-
-
-
-
-
-
H9
K9
-
-
-
-
-
VSS
VSS
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
K10
M15
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. This ball should remain floating.
3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.
4. This ball should be connected to VSS
.
5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
78/334
DS12556 Rev 5
Table 8. Port A alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4/
5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1/
3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
TIM1/DCMI
/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
DFSDM1
USART2_
CTS/
USART2_
NSS
TIM2_CH1/
TIM2_ETR
SDMMC2_
CMD
ETH_MII_
CRS
EVENT-
OUT
PA0
-
-
TIM5_CH1
TIM5_CH2
TIM8_ETR
TIM15_BKIN
-
-
-
-
UART4_TX
UART4_RX
SAI2_SD_B
-
-
-
-
-
USART2_
RTS/
USART2_
DE
ETH_MII_
RX_CLK/
ETH_RMII_
REF_CLK
LPTIM3_
OUT
TIM15_
CH1N
QUADSPI_ SAI2_MCLK
BK1_IO3
EVENT-
OUT
PA1
TIM2_CH2
LCD_R2
_B
LPTIM4_
OUT
USART2_ SAI2_SCK_
MDIOS_
MDIO
EVENT-
OUT
PA2
PA3
PA4
PA5
PA6
-
-
TIM2_CH3
TIM2_CH4
-
TIM5_CH3
TIM5_CH4
TIM5_ETR
-
TIM15_CH1
-
-
-
-
-
-
ETH_MDIO
-
-
LCD_R1
LCD_B5
TX
B
LPTIM5_
OUT
USART2_
RX
OTG_HS_
ULPI_D0
ETH_MII_
COL
EVENT-
OUT
TIM15_CH2
-
LCD_B2
-
D1
PWREN
SPI1_NSS/ SPI3_NSS/
I2S1_WS
USART2_
CK
OTG_HS_
SOF
DCMI_
HSYNC
LCD_
VSYNC
EVENT-
OUT
-
-
-
-
SPI6_NSS
SPI6_SCK
SPI6_MISO
-
-
-
-
-
I2S3_WS
D2
PWREN
TIM2_CH1/
TIM2_ETR
TIM8_
CH1N
SPI1_SCK
/I2S1_CK
OTG_HS_
ULPI_CK
EVENT-
OUT
-
-
-
-
-
LCD_R4
LCD_G2
SPI1_MISO
/I2S1_SDI
TIM13_
CH1
TIM8_BKIN
_COMP12
MDIOS_
MDC
TIM1_BKIN
_COMP12
DCMI_PIX
CLK
EVENT-
OUT
-
-
TIM1_BKIN
TIM3_CH1 TIM8_BKIN
-
-
ETH_MII_
RX_DV/
ETH_RMII_
CRS_DV
TIM8_CH1
SPI1_MOSI
/I2S1_SDO
TIM14_
CH1
FMC_SDN
WE
EVENT-
OUT
PA7
TIM1_CH1N TIM3_CH2
-
-
SPI6_MOSI
-
-
-
N
HRTIM_CH TIM8_BKIN
B2
USART1_
CK
OTG_FS_
SOF
TIM8_BKIN
2_COMP12
EVENT-
OUT
PA8
PA9
MCO1
-
TIM1_CH1
TIM1_CH2
I2C3_SCL
-
-
-
-
-
-
UART7_RX
-
LCD_B3
LCD_R6
LCD_R5
2
FDCAN1_
RXFD_
MODE
HRTIM_CH LPUART1_
C1 TX
SPI2_SCK/
I2S2_CK
USART1_
TX
EVENT-
OUT
I2C3_SMBA
-
-
DCMI_D0
FDCAN1_
TXFD_
MODE
HRTIM_CH LPUART1_
C2 RX
USART1_
RX
MDIOS_
MDIO
EVENT-
OUT
PA10
PA11
-
-
TIM1_CH3
TIM1_CH4
-
-
-
-
-
-
OTG_FS_ID
LCD_B4
DCMI_D1
LCD_B1
LCD_R4
USART1_
CTS/
USART1_
NSS
HRTIM_CH LPUART1_
SPI2_NSS
/I2S2_WS
FDCAN1_
RX
OTG_FS_
DM
EVENT-
OUT
UART4_RX
-
-
-
-
-
D1
CTS
LPUART1_
RTS/
LPUART1_
DE
USART1_
RTS/
USART1_
DE
HRTIM_CH
D2
SPI2_SCK/
I2S2_CK
FDCAN1_
TX
OTG_FS_
DP
EVENT-
OUT
PA12
-
TIM1_ETR
-
UART4_TX
SAI2_FS_B
-
LCD_R5
Table 8. Port A alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4/
5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1/
3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
TIM1/DCMI
/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
DFSDM1
JTMS-
SWDIO
EVENT-
OUT
PA13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
JTCK-
SWCLK
EVENT-
OUT
PA14
PA15
UART4_
RTS/
UART4_
DE
TIM2_CH1/
TIM2_ETR
HRTIM_
FLT1
SPI1_NSS/ SPI3_NSS/
I2S1_WS I2S3_WS
EVENT-
OUT
JTDI
-
CEC
SPI6_NSS
-
-
UART7_TX
-
-
-
Table 9. Port B alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/3
/6/UART7/S
DMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
TIM1/
DCMI/LCD
/COMP
SPI1/2/3/4/5/
6/CEC
UART5/
LCD
DFSDM1
TIM8_
CH2N
DFSDM1_
CKOUT
UART4_
CTS
OTG_HS_
ULPI_D1
ETH_MII_
RXD2
EVENT-
OUT
PB0
PB1
-
-
TIM1_CH2N TIM3_CH3
TIM1_CH3N TIM3_CH4
-
-
-
-
-
LCD_R3
LCD_R6
-
-
-
-
LCD_G1
LCD_G0
TIM8_
CH3N
DFSDM1_
DATIN1
OTG_HS_
ULPI_D2
ETH_MII_
RXD3
EVENT-
OUT
-
-
SPI3_
DFSDM1_
CKIN1
SAI4_SD_ QUADSPI_
EVENT-
OUT
PB2
RTC_OUT
-
SAI1_D1
-
-
-
SAI1_SD_A MOSI/I2S3_
SDO
SAI4_D1
-
-
-
-
A
CLK
JTDO/TRA
CESWO
HRTIM_
FLT4
SPI1_SCK/
I2S1_CK
SPI3_SCK/
-
SDMMC2_
D2
EVENT-
OUT
PB3
PB4
PB5
PB6
TIM2_CH2
-
SPI6_SCK
CRS_SYNC UART7_RX
-
-
-
-
-
-
I2S3_CK
TIM16_
BKIN
HRTIM_
EEV6
SPI1_MISO/ SPI3_MISO/ SPI2_NSS/I
I2S1_SDI
SPI6_
MISO
SDMMC2_
D3
EVENT-
OUT
NJTRST
TIM3_CH1
TIM3_CH2
TIM4_CH1
-
-
UART7_TX
I2S3_SDI
2S2_WS
TIM17_
BKIN
HRTIM_
EEV7
SPI1_MOSI/
I2S1_SDO
SPI3_MOSI/
I2S3_SDO
SPI6_
MOSI
FDCAN2_
RX
OTG_HS_
ULPI_D7
ETH_PPS_
OUT
FMC_
SDCKE1
DCMI_
D10
UART5_ EVENT-
RX OUT
-
-
I2C1_SMBA
I2C1_SCL
I2C4_SMBA
TIM16_
CH1N
HRTIM_
EEV8
USART1_
TX
LPUART1_ FDCAN2_
QUADSPI_
BK1_NCS
DFSDM1_
DATIN5
FMC_
SDNE1
UART5_ EVENT-
CEC
-
I2C4_SCL
I2C4_SDA
DCMI_D5
TX
TX
TX
-
OUT
FDCAN2_
TXFD_
MODE
TIM17_
CH1N
HRTIM_
EEV9
USART1_
RX
LPUART1_
RX
DFSDM1_
CKIN5
DCMI_
VSYNC
EVENT-
OUT
PB7
-
TIM4_CH2
I2C1_SDA
-
FMC_NL
Table 9. Port B alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/3
/6/UART7/S
DMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
TIM1/
DCMI/LCD
/COMP
SPI1/2/3/4/5/
6/CEC
UART5/
LCD
DFSDM1
DFSDM1_
CKIN7
SDMMC1_
CKIN
FDCAN1_
RX
SDMMC2_
D4
ETH_MII_
TXD3
SDMMC1_
D4
EVENT-
OUT
PB8
-
-
-
TIM16_CH1 TIM4_CH3
TIM17_CH1 TIM4_CH4
I2C1_SCL
I2C1_SDA
I2C2_SCL
-
I2C4_SCL
I2C4_SDA
UART4_RX
UART4_TX
-
DCMI_D6
DCMI_D7
-
LCD_B6
LCD_B7
LCD_G4
DFSDM1_
DATIN7
SPI2_NSS/
I2S2_WS
SDMMC1_
CDIR
FDCAN1_
TX
SDMMC2_
D5
I2C4_
SMBA
SDMMC1_
D5
EVENT-
OUT
PB9
HRTIM_
TIM2_CH3
LPTIM2_IN
1
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN7
USART3_
TX
QUADSPI_
BK1_NCS
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER
EVENT-
OUT
PB10
-
-
SCOUT
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
HRTIM_
TIM2_CH4
LPTIM2_
ETR
DFSDM1_
CKIN7
USART3_
RX
OTG_HS_
ULPI_D4
EVENT-
OUT
PB11
PB12
PB13
-
-
-
I2C2_SDA
I2C2_SMBA
-
-
-
-
-
-
-
LCD_G5
SCIN
ETH_MII_
TXD0/ETH_
RMII_TXD0
TIM1_
BKIN_
COMP12
SPI2_NSS/
I2S2_WS
DFSDM1_
DATIN1
USART3_
CK
FDCAN2_
RX
OTG_HS_
ULPI_D5
OTG_HS_
ID
UART5_ EVENT-
RX OUT
TIM1_BKIN
TIM1_CH1N
-
-
-
USART3_
CTS/
USART3_
NSS
ETH_MII_
TXD1/ETH_
RMII_TXD1
LPTIM2_
OUT
SPI2_SCK/
I2S2_CK
DFSDM1_
CKIN1
FDCAN2_
TX
OTG_HS_
ULPI_D6
UART5_ EVENT-
-
-
TX
OUT
USART3_
RTS/
USART3_
DE
UART4_
RTS/
UART4_
DE
TIM12_
CH1
TIM8_
CH2N
SPI2_MISO/
I2S2_SDI
DFSDM1_
DATIN2
SDMMC2_
D0
OTG_HS_
DM
EVENT-
OUT
PB14
PB15
-
TIM1_CH2N
TIM1_CH3N
USART1_TX
USART1_RX
-
-
-
-
-
-
-
-
RTC_
REFIN
TIM12_
CH2
TIM8_
CH3N
SPI2_MOSI/
I2S2_SDO
DFSDM1_
CKIN2
UART4_
CTS
SDMMC2_
D1
OTG_HS_
DP
EVENT-
OUT
-
Table 10. Port C alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
/LCD/
COMP
DFSDM1
DFSDM1_
CKIN0
DFSDM1_
DATIN4
OTG_HS_
ULPI_STP
FMC_
SDNWE
EVENT-
OUT
PC0
-
-
-
-
-
-
-
-
SAI2_FS_B
-
-
-
-
LCD_R5
-
SPI2_
DFSDM1_
DATIN0
DFSDM1_
CKIN4
SAI4_SD_ SDMMC2_
MDIOS_
MDC
EVENT-
OUT
PC1 TRACED0
PC2 CDSLEEP
SAI1_D1
MOSI/I2S2 SAI1_SD_A
_SDO
SAI4_D1
ETH_MDC
A
CK
SPI2_
DFSDM1_
MISO/I2S2
CKOUT
_SDI
DFSDM1_
CKIN1
OTG_HS_
ULPI_DIR
ETH_MII_
TXD2
FMC_SDNE
0
EVENT-
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_
MOSI/I2S2
_SDO
DFSDM1_
DATIN1
OTG_HS_
ULPI_NXT
ETH_MII_
TX_CLK
FMC_SDCK
E0
EVENT-
OUT
PC3
PC4
PC5
CSLEEP
-
-
-
-
-
-
-
ETH_MII_
RXD0/ETH_
RMII_RXD0
DFSDM1_
CKIN2
I2S1_
MCK
SPDIFRX1
_IN3
FMC_SDNE
0
EVENT-
OUT
-
-
-
-
ETH_MII_
RXD1/ETH_
RMII_RXD1
DFSDM1_
DATIN2
SPDIFRX1
_IN4
FMC_SDCK
E0
COMP1_
OUT
EVENT-
OUT
SAI1_D3
-
SAI4_D3
HRTIM_CH
A1
DFSDM1_
CKIN3
I2S2_
MCK
USART6_
TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6
SDMMC1_
D6
LCD_
HSYNC
EVENT-
OUT
PC6
PC7
-
TIM3_CH1 TIM8_CH1
TIM3_CH2 TIM8_CH2
-
-
DCMI_D0
DCMI_D1
HRTIM_CH
A2
DFSDM1_
DATIN3
USART6_
RX
SDMMC1_
D123DIR
SDMMC2_
D7
SDMMC1_
D7
EVENT-
OUT
TRGIO
-
-
I2S3_MCK
FMC_NE1
SWPMI_TX
LCD_G6
-
UART5_
RTS/
UART5_
DE
HRTIM_CH
B1
USART6_
CK
FMC_NE2/
FMC_NCE
SDMMC1_
D0
EVENT-
OUT
PC8 TRACED1
TIM3_CH3 TIM8_CH3
TIM3_CH4 TIM8_CH4
-
-
-
-
SWPMI_RX
DCMI_D2
UART5_
CTS
QUADSPI_
BK1_IO0
SWPMI_
SUSPEND
SDMMC1_
D1
EVENT-
OUT
PC9
PC10
PC11
MCO2
-
-
-
-
-
I2C3_SDA
I2S_CKIN
-
LCD_G3
DCMI_D3
DCMI_D8
DCMI_D4
DCMI_D9
-
LCD_B2
HRTIM_
EEV1
DFSDM1_
CKIN5
SPI3_SCK/
I2S3_CK
USART3_
TX
QUADSPI_
BK1_IO1
SDMMC1_
D2
EVENT-
OUT
-
-
-
-
-
-
-
-
-
-
UART4_TX
UART4_RX
UART5_TX
-
-
-
-
-
-
-
-
-
LCD_R2
HRTIM_
FLT2
DFSDM1_
DATIN5
SPI3_MISO/ USART3_
I2S3_SDI RX
QUADSPI_
BK2_NCS
SDMMC1_
D3
EVENT-
OUT
-
-
-
HRTIM_
EEV2
SPI3_MOSI/ USART3_
SDMMC1_
CK
EVENT-
OUT
PC12 TRACED3
-
-
-
-
I2S3_SDO
CK
EVENT-
OUT
PC13
-
-
-
-
-
Table 10. Port C alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
/LCD/
COMP
DFSDM1
EVENT-
OUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT-
OUT
PC15
Table 11. Port D alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
/LCD/
COMP
DFSDM1
DFSDM1_
CKIN6
SAI3_SCK_
A
FDCAN1_
RX
FMC_D2/
FMC_DA2
EVENT-
OUT
PD0
PD1
PD2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART4_RX
UART4_TX
UART5_RX
-
-
-
-
-
-
-
-
-
-
DFSDM1_
DATIN6
FDCAN1_
TX
FMC_D3/
FMC_DA3
EVENT-
OUT
-
-
SAI3_SD_A
-
-
SDMMC1_
CMD
EVENT-
OUT
TRACED2
TIM3_ETR
-
-
-
DCMI_D11
USART2_
CTS/
USART2_
NSS
DFSDM1_
CKOUT
SPI2_SCK/
I2S2_CK
EVENT-
OUT
PD3
PD4
-
-
-
-
-
-
-
-
-
-
-
FMC_CLK
DCMI_D5
LCD_G7
USART2_
RTS/
USART2_
DE
HRTIM_
FLT3
FDCAN1_R
XFD_MODE
EVENT-
OUT
-
-
-
-
-
SAI3_FS_A
-
-
-
-
-
FMC_NOE
FMC_NWE
-
-
HRTIM_
EEV3
USART2_
TX
FDCAN1_T
XFD_MODE
EVENT-
OUT
PD5
PD6
-
-
-
-
-
-
-
-
SPI3_
DFSDM1_
CKIN4
DFSDM1_
DATIN1
USART2_
RX
SAI4_SD_
A
FDCAN2_R
XFD_MODE
SDMMC2_
CK
FMC_
NWAIT
EVENT-
OUT
SAI1_D1
-
MOSI/I2S3 SAI1_SD_A
_SDO
SAI4_D1
DCMI_D10
LCD_B2
SPI1_
DFSDM1_
MOSI/I2S1
CKIN1
DFSDM1_
DATIN4
USART2_
CK
SPDIFRX1_
IN1
SDMMC2_
CMD
EVENT-
OUT
PD7
-
-
-
-
-
FMC_NE1
-
-
_SDO
Table 11. Port D alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
/LCD/
COMP
DFSDM1
DFSDM1_
CKIN3
SAI3_SCK_
B
USART3_
TX
SPDIFRX1_
IN2
FMC_D13/
FMC_DA13
EVENT-
OUT
PD8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_
DATIN3
USART3_
RX
FDCAN2_R
XFD_MODE
FMC_D14/
FMC_DA14
EVENT-
OUT
PD9
SAI3_SD_B
SAI3_FS_B
-
DFSDM1_
CKOUT
USART3_
CK
FDCAN2_T
XFD_MODE
FMC_D15/
FMC_DA15
EVENT-
OUT
PD10
LCD_B3
USART3_
CTS/
USART3_N
SS
LPTIM2_
IN2
QUADSPI_
BK1_IO0
EVENT-
OUT
PD11
PD12
-
-
-
-
I2C4_SMBA
I2C4_SCL
-
-
-
-
SAI2_SD_A
SAI2_FS_A
-
-
FMC_A16
-
-
-
-
USART3_
RTS/
USART3_
DE
LPTIM2_
IN1
QUADSPI_
BK1_IO1
EVENT-
OUT
LPTIM1_IN1 TIM4_CH1
-
-
-
-
FMC_A17
FMC_A18
LPTIM1_
TIM4_CH2
OUT
QUADSPI_ SAI2_SCK_
BK1_IO3
EVENT-
OUT
PD13
PD14
-
-
-
-
I2C4_SDA
-
-
-
-
-
-
-
-
-
A
SAI3_MCLK
_B
UART8_
CTS
FMC_D0/
FMC_DA0
EVENT-
OUT
-
-
TIM4_CH3
TIM4_CH4
-
-
-
-
UART8_
RTS/
UART8_
DE
SAI3_MCLK
_A
FMC_D1/
FMC_DA1
EVENT-
OUT
PD15
-
-
-
-
-
-
-
-
-
Table 12. Port E alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
/LCD/
COMP
DFSDM1
FDCAN1_
RXFD_
MODE
LPTIM1_
ETR
HRTIM_
SCIN
LPTIM2_
ETR
SAI2_
MCLK_A
EVENT-
OUT
PE0
-
-
TIM4_ETR
-
-
-
-
-
-
-
UART8_RX
UART8_TX
-
-
FMC_NBL0
FMC_NBL1
DCMI_D2
DCMI_D3
-
-
FDCAN1_
TXFD_
MODE
HRTIM_
SCOUT
EVENT-
OUT
PE1
LPTIM1_IN2
-
-
TRACE
CLK
SAI1_MCLK
_A
SAI4_
MCLK_A
QUADSPI_
BK1_IO2
ETH_MII_
TXD3
EVENT-
OUT
PE2
PE3
PE4
PE5
PE6
PE7
PE8
-
-
-
-
SAI1_CK1
-
-
-
SPI4_SCK
-
-
SAI4_CK1
-
FMC_A23
FMC_A19
FMC_A20
FMC_A21
FMC_A22
-
-
SAI4_SD_
B
EVENT-
OUT
TRACED0
TRACED1
TRACED2
TRACED3
-
-
TIM15_BKIN
SAI1_SD_B
-
-
-
-
-
-
-
DFSDM1_
DATIN3
TIM15_CH1
N
EVENT-
OUT
SAI1_D2
SPI4_NSS SAI1_FS_A
-
SAI4_FS_A
-
SAI4_D2
SAI4_CK2
DCMI_D4
DCMI_D6
DCMI_D7
-
LCD_B0
DFSDM1_
CKIN3
SPI4_
MISO
SAI1_SCK_
A
SAI4_SCK
_A
EVENT-
OUT
SAI1_CK2
TIM15_CH1
-
-
LCD_G0
TIM1_
BKIN2
SPI4_
MOSI
SAI4_SD_
A
SAI2_
MCLK_B
TIM1_BKIN
2_COMP12
EVENT-
OUT
SAI1_D1
-
TIM15_CH2
SAI1_SD_A
-
SAI4_D1
LCD_G1
DFSDM1_
DATIN2
QUADSPI_
BK2_IO0
FMC_D4/
FMC_DA4
EVENT-
OUT
TIM1_ETR
-
-
-
-
-
-
-
-
UART7_RX
UART7_TX
-
-
-
-
-
-
-
-
DFSDM1_
CKIN2
QUADSPI_
BK2_IO1
FMC_D5/
FMC_DA5
COMP2_
OUT
EVENT-
OUT
-
TIM1_CH1N
UART7_
RTS/
UART7_
DE
DFSDM1_
CKOUT
QUADSPI_
BK2_IO2
FMC_D6/
FMC_DA6
EVENT-
OUT
PE9
-
TIM1_CH1
-
-
-
-
-
-
-
-
-
DFSDM1_
DATIN4
UART7_
CTS
QUADSPI_
BK2_IO3
FMC_D7/
FMC_DA7
EVENT-
OUT
PE10
PE11
PE12
PE13
-
-
-
-
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_
CKIN4
FMC_D8/
FMC_DA8
EVENT-
OUT
SPI4_NSS
SPI4_SCK
-
-
-
SAI2_SD_B
LCD_G3
LCD_B4
LCD_DE
DFSDM1_
DATIN5
SAI2_SCK_
B
FMC_D9/
FMC_DA9
COMP1_
OUT
EVENT-
OUT
DFSDM1_
CKIN5
SPI4_
MISO
FMC_D10/
FMC_DA10
COMP2_
OUT
EVENT-
OUT
SAI2_FS_B
Table 12. Port E alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
/LCD/
COMP
DFSDM1
SPI4_
MOSI
SAI2_
MCLK_B
FMC_D11/
FMC_DA11
EVENT-
OUT
PE14
-
-
TIM1_CH4
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CLK
LCD_R7
TIM1_BKIN
_COMP12/
COMP_
FMC_D12/
FMC_DA12
EVENT-
OUT
PE15
-
TIM1_BKIN
Table 13. Port F alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
/LCD/
COMP
DFSDM1
EVENT-
OUT
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A0
FMC_A1
FMC_A2
FMC_A3
FMC_A4
FMC_A5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT-
OUT
PF1
PF2
PF3
PF4
PF5
PF6
PF7
-
I2C2_SCL
EVENT-
OUT
-
I2C2_SMBA
EVENT-
OUT
-
-
-
-
-
-
EVENT-
OUT
-
EVENT-
OUT
-
SAI4_SD_ QUADSPI_
EVENT-
OUT
TIM16_CH1
TIM17_CH1
SPI5_NSS SAI1_SD_B UART7_RX
SAI1_MCLK
B
BK1_IO3
SAI4_
MCLK_B
QUADSPI_
BK1_IO2
EVENT-
OUT
SPI5_SCK
UART7_TX
-
_B
UART7_
RTS/
UART7_
DE
TIM16_
CH1N
SPI5_
MISO
SAI1_SCK_
B
SAI4_SCK
_B
TIM13_
CH1
QUADSPI_
BK1_IO0
EVENT-
OUT
PF8
-
-
-
-
-
-
-
-
-
-
TIM17_
CH1N
SPI5_
MOSI
UART7_
CTS
TIM14_CH QUADSPI_
EVENT-
OUT
PF9
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI1_FS_B
SAI4_FS_B
-
-
-
-
-
-
-
-
-
1
BK1_IO1
TIM16_
BKIN
QUADSPI_
CLK
EVENT-
OUT
PF10
PF11
PF12
PF13
PF14
PF15
SAI1_D3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI4_D3
DCMI_D11 LCD_DE
SPI5_
MOSI
FMC_
SDNRAS
EVENT-
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_SD_B
DCMI_D12
-
-
-
-
-
EVENT-
OUT
-
-
-
-
-
-
-
-
-
FMC_A6
FMC_A7
FMC_A8
FMC_A9
-
-
-
-
DFSDM1_
DATIN6
EVENT-
OUT
I2C4_SMBA
I2C4_SCL
I2C4_SDA
DFSDM1_
CKIN6
EVENT-
OUT
EVENT-
OUT
-
Table 14. Port G alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM8/ I2C4/UART7
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
/SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/ETH
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
TIM1/
DCMI/LCD
/COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
DFSDM1
SDMMC2/
LCD/
SPDIFRX1
EVENT
-OUT
PG0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
FMC_A11
FMC_A12
FMC_A13
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
-OUT
PG1
PG2
PG3
PG4
PG5
PG6
PG7
-
TIM8_BKIN_
COMP12
EVENT
-OUT
TIM8_BKIN
TIM8_
BKIN2
TIM8_BKIN2
_COMP12
EVENT
-OUT
TIM1_
BKIN2
TIM1_BKIN2 FMC_A14/
_COMP12
EVENT
-OUT
-
-
-
-
FMC_BA0
FMC_A15/
FMC_BA1
EVENT
-OUT
TIM1_ETR
-
TIM17_
BKIN
HRTIM_
CHE1
QUADSPI_
BK1_NCS
DCMI_
D12
LCD_
R7
EVENT
-OUT
-
-
FMC_NE3
FMC_INT
HRTIM_
CHE2
SAI1_
MCLK_A
USART6_
CK
DCMI_
D13
LCD_
CLK
EVENT
-OUT
-
-
-
-
USART6_
RTS/
USART6_
DE
SPDIFRX1
_IN3
ETH_PPS_
OUT
FMC_
SDCLK
LCD_
G7
EVENT
-OUT
PG8
-
-
-
TIM8_ETR
-
SPI6_NSS
-
-
-
SPI1_
MISO/I2S1
_SDI
USART6_
RX
SPDIFRX1
_IN4
QUADSPI_
BK2_IO2
FMC_NE2/
FMC_NCE
DCMI_
VSYNC
EVENT
-OUT
PG9
-
-
-
-
-
-
-
-
-
-
SAI2_FS_B
SAI2_SD_B
-
-
-
HRTIM_
FLT5
SPI1_NSS/
I2S1_WS
LCD_
B2
EVENT
-OUT
PG10
-
-
-
LCD_G3
-
FMC_NE3
-
DCMI_D2
DCMI_D3
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
HRTIM_
EEV4
SPI1_SCK/
I2S1_CK
SPDIFRX1
_IN1
LCD_
B3
EVENT
-OUT
PG11
PG12
-
-
LPTIM1_IN2
LPTIM1_IN1
-
-
-
-
-
-
-
SDMMC2_D2
USART6_
RTS/
USART6_
DE
ETH_MII_
TXD1/ETH_
RMII_TXD1
HRTIM_
EEV5
SPI6_
MISO
SPDIFRX1
_IN2
LCD_
B1
EVENT
-OUT
LCD_B4
-
-
FMC_NE4
FMC_A24
-
-
USART6_
CTS/
USART6_
NSS
ETH_MII_
TXD0/ETH_
RMII_TXD0
LPTIM1_
OUT
HRTIM_
EEV10
LCD_
R0
EVENT
-OUT
PG13 TRACED0
SPI6_SCK
-
-
-
Table 14. Port G alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SAI2/4/TIM8/ I2C4/UART7
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
/SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/ETH
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
TIM1/
DCMI/LCD
/COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
DFSDM1
SDMMC2/
LCD/
SPDIFRX1
ETH_MII_
TXD1/ETH_
RMII_TXD1
LPTIM1_
ETR
SPI6_
MOSI
USART6_
TX
QUADSPI_
BK2_IO3
LCD_
B0
EVENT
-OUT
PG14 TRACED1
-
-
-
-
-
-
-
-
-
-
FMC_A25
-
USART6_
CTS/
USART6_
NSS
FMC_
SDNCAS
DCMI_
D13
EVENT
-OUT
PG15
-
-
-
-
-
-
-
Table 15. Port H alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
/LCD/
COMP
DFSDM1
EVENT-
OUT
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT-
OUT
PH1
PH2
-
-
-
-
-
-
QUADSPI_ SAI2_SCK_
BK2_IO0
ETH_MII_
CRS
FMC_
SDCKE0
EVENT-
OUT
LPTIM1_IN2
-
-
-
-
LCD_R0
LCD_R1
LCD_G4
-
B
QUADSPI_
BK2_IO1
SAI2_
MCLK_B
ETH_MII_
COL
FMC_
SDNE0
EVENT-
OUT
PH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OTG_HS_
ULPI_NXT
EVENT-
OUT
PH4
I2C2_SCL
I2C2_SDA
-
-
LCD_G5
-
-
-
-
FMC_
SDNWE
EVENT-
OUT
PH5
SPI5_NSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM12_
CH1
ETH_MII_
RXD2
FMC_
SDNE1
EVENT-
OUT
PH6
I2C2_SMBA SPI5_SCK
-
DCMI_D8
DCMI_D9
-
SPI5_
I2C3_SCL
ETH_MII_
RXD3
FMC_
SDCKE1
EVENT-
OUT
PH7
-
-
-
MISO
DCMI_
HSYNC
EVENT-
OUT
PH8
TIM5_ETR
I2C3_SDA
I2C3_SMBA
I2C4_SMBA
I2C4_SCL
I2C4_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D16
FMC_D17
FMC_D18
FMC_D19
FMC_D20
FMC_D21
FMC_D22
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_G2
LCD_G3
TIM12_
CH2
EVENT-
OUT
PH9
-
DCMI_D0
DCMI_D1
DCMI_D2
DCMI_D3
-
EVENT-
OUT
PH10
PH11
PH12
PH13
PH14
TIM5_CH1
-
EVENT-
OUT
TIM5_CH2
-
EVENT-
OUT
TIM5_CH3
-
TIM8_
CH1N
FDCAN1_
TX
EVENT-
OUT
-
-
UART4_TX
UART4_RX
TIM8_
CH2N
FDCAN1_
RX
EVENT-
OUT
-
DCMI_D4
FDCAN1_
TXFD_
MODE
TIM8_
CH3N
EVENT-
OUT
PH15
-
-
-
-
-
-
-
-
-
-
FMC_D23
DCMI_D11
LCD_G4
Table 16. Port I alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
/LCD/
COMP
DFSDM1
FDCAN1_
RXFD_
MODE
SPI2_NSS/
I2S2_WS
EVENT-
OUT
PI0
-
-
-
-
-
-
TIM5_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D24
FMC_D25
FMC_D26
DCMI_D13 LCD_G5
TIM8_
BKIN2
SPI2_SCK/
I2S2_CK
TIM8_BKIN
2_COMP12
EVENT-
OUT
PI1
PI2
-
-
-
-
DCMI_D8
DCMI_D9
LCD_G6
LCD_G7
SPI2_
MISO/I2S2
_SDI
EVENT-
OUT
TIM8_CH4
TIM8_ETR
-
-
SPI2_
MOSI/I2S2
_SDO
EVENT-
OUT
PI3
-
-
-
-
-
-
-
-
-
FMC_D27
DCMI_D10
DCMI_D5
-
SAI2_
MCLK_A
TIM8_BKIN
_COMP12
EVENT-
OUT
PI4
PI5
PI6
PI7
PI8
PI9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_BKIN
TIM8_CH1
TIM8_CH2
TIM8_CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NBL2
FMC_NBL3
FMC_D28
FMC_D29
-
LCD_B4
LCD_B5
LCD_B6
LCD_B7
-
SAI2_SCK_
A
DCMI_
VSYNC
EVENT-
OUT
-
-
-
-
-
-
EVENT-
OUT
-
SAI2_SD_A
DCMI_D6
EVENT-
OUT
-
SAI2_FS_A
DCMI_D7
EVENT-
OUT
-
-
-
-
-
FDCAN1_
RX
LCD_
VSYNC
EVENT-
OUT
-
UART4_RX
FMC_D30
FDCAN1_
RXFD_
MODE
ETH_MII_
RX_ER
LCD_
HSYNC
EVENT-
OUT
PI10
-
-
-
-
-
-
-
-
-
-
FMC_D31
-
OTG_HS_
ULPI_DIR
EVENT-
OUT
PI11
PI12
PI13
PI14
PI15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_
HSYNC
EVENT-
OUT
-
-
-
-
-
LCD_
VSYNC
EVENT-
OUT
-
EVENT-
OUT
-
LCD_CLK
LCD_R0
EVENT-
OUT
LCD_G2
Table 17. Port J alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
/LCD/
COMP
DFSDM1
EVENT-
OUT
PJ0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R1
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_R7
LCD_G0
LCD_G1
LCD_G2
LCD_G3
LCD_G4
LCD_B0
LCD_B1
LCD_B2
LCD_B3
EVENT-
OUT
PJ1
PJ2
-
-
-
-
-
EVENT-
OUT
-
-
-
-
-
EVENT-
OUT
PJ3
-
-
-
-
-
EVENT-
OUT
PJ4
-
-
-
-
-
EVENT-
OUT
PJ5
-
-
-
-
-
EVENT-
OUT
PJ6
-
-
TIM8_CH2
-
-
TIM8_
CH2N
EVENT-
OUT
PJ7
TRGIN
-
-
-
EVENT-
OUT
PJ8
-
TIM1_CH3N
TIM8_CH1
UART8_TX
-
TIM8_
CH1N
EVENT-
OUT
PJ9
-
TIM1_CH3
UART8_RX
-
SPI5_
MOSI
EVENT-
OUT
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
-
TIM1_CH2N
TIM8_CH2
-
-
-
-
-
-
-
TIM8_
CH2N
SPI5_
MISO
EVENT-
OUT
-
TIM1_CH2
-
EVENT-
OUT
TRGOUT
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G3
EVENT-
OUT
-
-
-
LCD_B4
EVENT-
OUT
-
-
EVENT-
OUT
Table 18. Port K alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
SAI2/4/
TIM8/
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
TIM1/8/FMC
/SDMMC1/ TIM1/DCMI
MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
/LCD/
COMP
DFSDM1
EVENT-
OUT
PK0
-
-
-
-
-
-
-
-
TIM1_CH1N
-
-
-
-
-
-
-
-
TIM8_CH3
-
-
-
-
-
-
-
-
SPI5_SCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G5
LCD_G6
LCD_G7
LCD_B4
LCD_B5
LCD_B6
LCD_B7
LCD_DE
TIM8_
CH3N
EVENT-
OUT
PK1
PK2
PK3
PK4
PK5
PK6
PK7
TIM1_CH1
SPI5_NSS
TIM8_BKIN TIM1_BKIN
_COMP12
EVENT-
OUT
TIM1_BKIN
TIM8_BKIN
-
-
-
-
-
-
_COMP12
EVENT-
OUT
-
-
-
-
-
-
-
-
-
-
-
-
EVENT-
OUT
-
-
-
-
-
-
-
-
EVENT-
OUT
EVENT-
OUT
EVENT-
OUT
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6
Electrical characteristics (rev Y)
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at T = 25 °C and T = T (given by the
J
J
Jmax
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
J
DD
1.7 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9. Pin loading conditions
Figure 10. Pin input voltage
MCU pin
MCU pin
V
C =50 pF
IN
MS19011V2
MS19010V2
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DS12556 Rev 5
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Electrical characteristics (rev Y)
6.1.6
Power supply scheme
Figure 11. Power supply scheme
VDD50USB
VDD33USB
VDD33USB
VDD50USB
USB
IOs
VSS
USB
regulator
VSS
VDDLDO
VCAP
Core domain (VCORE
)
Voltage
regulator
VDDLDO
VSS
D3 domain
(System
logic,
D1 domain
(CPU, peripherals,
RAM)
D2 domain
(peripherals,
RAM)
EXTI,
IO
logic
IOs
Peripherals,
RAM)
Flash
VDD
VSS
VDD domain
HSI, LSI,
VDD
CSI, HSI48,
HSE, PLLs
VBAT
charging
Backup domain
Backup
regulator
VBAT
1.2 to 3.6V
VSW
VBKP
VBAT
Power switch
Power switch
LSE, RTC,
Wakeup logic,
backup
Backup
RAM
BKUP
IOs
IO
logic
registers,
Reset
VREF
VDDA
VSS
VDDA
VSS
Analog domain
REF_BUF
ADC, DAC
VREF+
VREF-
OPAMP,
Comparator
VREF+
VREF-
VSSA
MSv46116V4
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution:
Each power supply pair (V /V , V
/V
...) must be decoupled with filtering ceramic
DD SS
DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
DS12556 Rev 5
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311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics,
Table 20: Current characteristics, and Table 21: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
(1)
Table 19. Voltage characteristics
Symbols
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
VDDX - VSS
−0.3
4.0
V
VDDLDO, VDDA, VDD33USB, VBAT
)
Min(VDD, VDDA
,
Input voltage on FT_xxx pins
VSS−0.3
VDD33USB, VBAT
)
V
+4.0(3)(4)
(2)
VIN
Input voltage on TT_xx pins
Input voltage on BOOT0 pin
Input voltage on any other pins
V
V
SS-0.3
VSS
4.0
9.0
4.0
V
V
V
SS-0.3
Variations between different VDDX power pins
of the same domain
|ΔVDDX
|
-
-
50
50
mV
mV
|VSSx-VSS
|
Variations between all the different ground pins
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 57 for the maximum allowed injected current
values.
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Electrical characteristics (rev Y)
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 20. Current characteristics
Symbols
Ratings
Max
Unit
ΣIVDD
ΣIVSS
IVDD
IVSS
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
620
620
100
100
20
IIO
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
140
140
mA
ΣI(PIN)
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
(3)(4)
IINJ(PIN)
Injected current on PA4, PA5
−0/0
±25
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5)
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 19: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 21. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
?65 to +150
°C
Maximum junction temperature
125
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3
Operating conditions
6.3.1
General operating conditions
Table 22. General operating conditions
Symbol
Parameter
Operating conditions
Min
Max
Unit
VDD
Standard operating voltage
-
1.62(1)
1.62(1)
3.0
3.6
3.6
3.6
3.6
VDDLDO
Supply voltage for the internal regulator
VDDLDO ≤ VDD
USB used
VDD33USB Standard operating voltage, USB domain
USB not used
ADC or COMP used
DAC used
0
1.62
1.8
OPAMP used
VREFBUF used
2.0
VDDA
Analog operating voltage
3.6
V
1.8
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
0
TT_xx I/O
BOOT0
−0.3
0
VDD+0.3
9
VIN
I/O Input voltage
Min(VDD, VDDA
,
All I/O except BOOT0
and TT_xx
−0.3
VDD33USB)+3.6V
< 5.5V(2)(3)
Maximum power dissipation
–40
–40
85
Ambient temperature for
the suffix 6 version
TA
TJ
°C
°C
Low-power dissipation(4)
105
Junction temperature
range
Suffix 6 version
–40
125
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.6:
Thermal characteristics).
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
6.3.2
VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
to
EXT
the VCAP pin. C
VCAP pins.
is specified in Table 23. Two external capacitors can be connected to
EXT
Figure 13. External capacitor C
EXT
C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
(1)
Table 23. VCAP operating conditions
Parameter
Symbol
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF(2)
< 100 m
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
6.3.3
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 24. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
Min
Max
Unit
0
10
0
∞
∞
∞
∞
∞
∞
tVDD
VDD fall time rate
VDDA rise time rate
tVDDA
µs/V
V
DDA fall time rate
VDDUSB rise time rate
DDUSB fall time rate
10
0
tVDDUSB
V
10
DS12556 Rev 5
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.4
Embedded reset and power control block characteristics
The parameters given in Table 25 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions.
Table 25. Reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset temporization
after BOR0 released
(1)
tRSTTEMPO
-
-
377
-
µs
Rising edge(1)
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge in Run mode
1.62
1.58
2.04
1.95
2.34
2.25
2.63
2.54
1.90
1.81
2.05
1.96
2.19
2.10
2.35
2.25
2.49
2.39
2.64
2.55
2.78
2.69
1.67
1.62
2.10
2.00
2.41
2.31
2.70
2.61
1.96
1.86
2.10
2.01
2.26
2.15
2.41
2.31
2.56
2.45
2.71
2.61
2.86
2.76
1.71
1.68
2.15
2.06
2.47
2.37
2.78
2.68
2.01
1.91
2.16
2.06
2.32
2.21
2.47
2.37
2.62
2.51
2.78
2.68
2.94
2.83
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
VBOR1
VBOR2
VBOR3
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Programmable Voltage
Detector threshold 0
Programmable Voltage
Detector threshold 1
V
Programmable Voltage
Detector threshold 2
Programmable Voltage
Detector threshold 3
Programmable Voltage
Detector threshold 4
Programmable Voltage
Detector threshold 5
Programmable Voltage
Detector threshold 6
Hysteresis voltage of BOR
(unless BOR0) and PVD
Vhyst_BOR_PVD
Hysteresis in Run mode
-
-
-
100
-
mV
µA
BOR(2) (unless BOR0) and
PVD consumption from VDD
(1)
IDD_BOR_PVD
0.630
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 25. Reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.66
1.56
2.06
1.96
2.42
2.35
2.74
2.64
1.71
1.61
2.12
2.02
2.50
2.42
2.83
2.72
1.76
1.66
2.19
2.08
2.58
2.49
2.91
2.80
Analog voltage detector for
VDDA threshold 0
VAVM_0
Analog voltage detector for
VDDA threshold 1
VAVM_1
VAVM_2
VAVM_3
V
Analog voltage detector for
VDDA threshold 2
Analog voltage detector for
VDDA threshold 3
Hysteresis of VDDA voltage
detector
Vhyst_VDDA
IDD_PVM
-
-
-
-
100
-
mV
µA
µA
PVM consumption from
VDD(1)
-
-
-
0.25
2.5
Voltage detector
consumption on VDDA
IDD_VDDA
Resistor bridge
(1)
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 6.3.6: Supply current characteristics).
6.3.5
Embedded reference voltage
The parameters given in Table 26 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions.
Table 26. Embedded reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
-40°C < TJ < 105°C,
VDD = 3.3 V
Internal reference voltages
1.180
1.216
1.255
V
ADC sampling time when
reading the internal reference
voltage
(1)(2)
tS_vrefint
-
-
4.3
-
-
µs
VBAT sampling time when
reading the internal VBAT
reference voltage
(1)(2)
tS_vbat
9
9
-
-
13.5
5
-
Reference Buffer
consumption for ADC
(2)
Irefbuf
V
DDA=3.3 V
23
15
µA
Internal reference voltage
spread over the temperature
range
(2)
ΔVREFINT
-40°C < TJ < 105°C
mV
Average temperature
coefficient
Average temperature
coefficient
(2)
Tcoeff
-
-
20
10
70
ppm/°C
ppm/V
(2)
VDDcoeff
Average Voltage coefficient
3.0V < VDD < 3.6V
1370
DS12556 Rev 5
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 26. Embedded reference voltage (continued)
Parameter Conditions Min
Symbol
Typ
25
Max
Unit
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
-
-
-
-
-
%
-
-
-
-
50
VREFINT
75
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
Table 27. Internal reference voltage calibration values
Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
Symbol
6.3.6
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in analog input mode.
All peripherals are disabled except when explicitly mentioned.
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (f
) frequency and V
range” available in the reference manual).
rcc_c_ck
CORE
When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in Table 28 to Table 36 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 22: General
operating conditions.
102/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 28. Typical and maximum current consumption in Run mode, code with data processing
(1)
running from ITCM, regulator ON
Max(2)
frcc_c_ck
(MHz)
Symbol
Parameter
Conditions
Typ
unit
TJ =
25°C
TJ =
TJ =
TJ =
85°C
105°C 125°C
400
300
300
216
200
200
180
168
144
60
71
56
110
-
210
-
290
-
540
-
VOS1
50
72
58
-
170
150
-
230
210
-
370
380
-
VOS2
37
35.5
33
All
peripherals
disabled
50
47
45
41
28
24
220(3)
-
130
130
130
120
110
99
190
180
180
180
160
160
500(3)
-
300
290
290
290
280
270
840
-
30
Supply
current in Run
mode
28
IDD
VOS3
VOS1
mA
25
13
25
10
400
300
300
200
200
165
130
120
83
400
-
All
peripherals
enabled
170
-
300
-
390
-
570
-
VOS2
VOS3
78
110
220
300
470
1. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
2. Guaranteed by characterization results unless otherwise specified.
3. Guaranteed by test in production.
DS12556 Rev 5
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON
Max(1)
frcc_c_ck
(MHz)
Symbol
Parameter
Conditions
Typ
unit
TJ =
25°C
TJ =
TJ =
TJ =
85°C
105°C 125°C
400
300
300
216
200
200
180
168
144
60
105
55
160
310
420
750
VOS1
-
-
-
-
50
72
160
230
370
VOS2
38
-
-
-
-
36
-
-
-
-
All
peripherals
disabled
33
50
130
190
300
30
-
-
-
-
Supply
current in Run
mode
29
-
-
-
-
IDD
VOS3
VOS1
mA
26
-
-
-
-
14
-
-
-
-
-
-
-
-
25
14
400
300
300
200
200
160
130
120
81
220
-
400
-
500
-
750
-
All
peripherals
enabled
160
-
300
-
390
-
560
-
VOS2
VOS3
77
110
220
300
460
1. Guaranteed by characterization results unless otherwise specified.
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON
Max(1)
frcc_c_ck
(MHz)
Symbol
Parameter
Conditions
Typ
unit
TJ =
25°C
TJ =
TJ =
TJ =
85°C
105°C 125°C
VOS1
400
300
200
400
300
200
73
52
110
75
220
170
130
360
270
210
290
230
190
470
370
300
540
370
300
730
550
460
All
peripherals VOS2
disabled
Supply
current in Run
mode
VOS3
34
52
IDD
mA
VOS1
All
peripherals VOS2
135
100
70
190
150
100
enabled
VOS3
1. Guaranteed by characterization results.
104/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 31. Typical consumption in Run mode and corresponding performance
versus code position
Conditions
frcc_c_ck
(MHz)
IDD/
CoreMark
Symbol
Parameter
CoreMark
Typ
Unit
Unit
Peripheral
Code
ITCM
400
400
2012
2012
71
35
52
FLASH
A
105
All
peripherals
disabled,
cache ON
AXI
SRAM
400
2012
105
52
SRAM1
SRAM4
ITCM
400
400
400
2012
2012
2012
105
105
71
52
52
35
Supply current
in Run mode
µA/
CoreMark
IDD
mA
FLASH
A
400
400
593
344
70.5
70.5
119
205
All
peripherals
disabled
cache OFF
AXI
SRAM
SRAM1
SRAM4
400
400
472
432
74.5
72
158
167
Table 32. Typical current consumption batch acquisition mode
frcc_ahb_ck(AHB4)
Symbol
Parameter
Conditions
Typ
unit
(MHz)
D1Standby,
D2Standby,
D3Run
VOS3
VOS3
64
6.5
12
Supply current in
batch acquisition
mode
IDD
mA
D1Stop, D2Stop,
D3Run
64
Table 33. Typical and maximum current consumption in Sleep mode, regulator ON
Max(1)
frcc_c_ck
(MHz)
Symbol
Parameter
Conditions
Typ
unit
TJ =
25°C
TJ =
TJ =
TJ =
85°C
105°C 125°C
400
300
300
200
200
31.0
24.5
22.0
17.0
15.5
64
57
48
42
37
220
210
180
170
150
330
330
270
270
230
660
650
500
490
400
VOS1
Supply
current in
Sleep mode
All
IDD(Sleep)
peripherals
disabled
mA
VOS2
VOS3
1. Guaranteed by characterization results.
DS12556 Rev 5
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311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 34. Typical and maximum current consumption in Stop mode, regulator ON
Max(1)
Symbol
Parameter
Conditions
Typ
unit
TJ =
TJ =
TJ =
TJ =
25°C
85°C
105°C
125°C
Flash
SVOS5
SVOS4
1.4
7.2(2)
49
66
75(2)
140
200
memory in
low-power
mode, no
IWDG
1.95
11
110
16(2)
91
150(2)
240
D1Stop,
D2Stop,
D3Stop
SVOS3
SVOS5
2.85
1.65
2.2
7.2
11
49
66
91
35
47
64
35
47
65
21
27
37
8
75
110
150
60
140
180
300
97
Flash
memory ON, SVOS4
no IWDG
SVOS3
3.15
0.99
1.4
16
SVOS5
SVOS4
SVOS3
SVOS5
5.1
7.5
12
Flash
memory
OFF, no
IWDG
79
130
170
98
D1Stop,
D2Standby,
D3Stop
2.05
1.25
1.65
2.3
110
61
IDD(Stop)
mA
5.5
7.8
12
Flash
memory ON, SVOS4
no IWDG
80
130
170
57
SVOS3
110
36
SVOS5
0.57
3
D1Standby,
D2Stop,
D3Stop
SVOS4 0.805
4.5
6.7
1.1(2)
1.5
2.4(2)
47
74
SVOS3
SVOS5
1.2
63
99
Flash OFF,
no IWDG
0.17
13(2)
20
D1Standby,
D2Standby,
D3Stop
SVOS4 0.245
SVOS3 0.405
11
15
17
26
23(2)
35
1. Guaranteed by characterization results.
2. Guaranteed by test in production.
Table 35. Typical and maximum current consumption in Standby mode
Conditions
Typ(3)
Max (3 V)(1)
Symbol Parameter
Unit
Backup RTC
SRAM & LSE
TJ =
TJ = TJ =
TJ =
1.62 V 2.4 V 3 V 3.3 V
25°C 85°C 105°C 125°C
4(2) 18(3) 40(2) 90(3)
8.2(3) 47(3) 83(3) 141(3)
OFF
ON
OFF
OFF
ON
1.8
3.4
1.9
3.4
3.5
5.1
1.95 2.05
3.5 3.7
Supply
IDD
current in
Standby
mode
µA
(Standby)
OFF
ON
2.4
3.86 4.12
5.46 5.97
-
-
-
-
-
-
-
-
ON
3.95
1. The maximum current consumption values are given for PDR OFF (internal reset OFF). When the PDR is OFF (internal
reset OFF), the current consumption is reduced by 1.2 µA compared to PDR ON.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.
106/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 36. Typical and maximum current consumption in VBAT mode
Conditions
Typ(1)
Max (3 V)
TJ = TJ = TJ =
Symbol Parameter
Unit
Backup RTC&
TJ =
25°C 85°C 105°C 125°C
1.2 V
2 V
3 V 3.4 V
SRAM
OFF
ON
LSE
OFF
OFF
ON
0.024 0.035 0.062 0.096 0.5(1) 4.1(1) 10(1)
24(1)
Supply
1.4
1.6
1.8
1.8
4.4(1) 22(1) 48(1)
87(1)
IDD
current in
standby
mode
µA
(VBAT)
OFF
ON
0.24
1.97
0.45 0.62 0.73
2.37 2.57 2.77
-
-
-
-
-
-
-
-
ON
1. Guaranteed by characterization results.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 58: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 37: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
ISW = VDDx fSW CL
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the MCU supply voltage
DDx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
EXT
L
INT
DS12556 Rev 5
107/334
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
The I/O compensation cell is enabled.
f
is the CPU clock. f
= f
/4, and f
= f
/2.
rcc_c_ck
PCLK
rcc_c_ck
HCLK
rcc_c_ck
The given value is calculated by measuring the difference of current consumption
–
–
–
with all peripherals clocked off
with only one peripheral clocked on
f
f
= 400 MHz (Scale 1), f
= 200 MHz (Scale 3)
= 300 MHz (Scale 2),
rcc_c_ck
rcc_c_ck
rcc_c_ck
The ambient operating temperature is 25 °C and V =3.3 V.
DD
108/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 37. Peripheral current consumption in Run mode
DD(Typ)
I
Peripheral
Unit
VOS1
VOS2
VOS3
MDMA
8.3
21
7.6
20
23
9
7
DMA2D
JPEG
18
24
21
FLASH
9.9
0.9
6.1
8.3
0.8
5.3
FMC registers
FMC kernel
0.9
5.5
QUADSPI
registers
1.5
0.9
8
1.4
0.8
7.2
1.3
0.7
6.8
AHB3
QUADSPI kernel
SDMMC1
registers
SDMMC1 kernel
DTCM1
2.4
5.7
5.5
3.2
7.6
7.5
1.1
1.7
3.9
0.9
5.5
2
1.8
4.5
4.3
2.6
6.1
6.3
1
5
DTCM2
4.8
2.9
6.8
6.8
1
ITCM
D1SRAM1
AHB3 bridge
DMA1
µA/MHz
DMA2
1.4
3.2
0.8
4.5
1.1
3.1
0.7
4.2
ADC1/2 registers
ADC1/2 kernel
ART accelerator
ETH1MAC
ETH1TX
16
15
14
13
ETH1RX
AHB1
USB1 OTG
registers
14
13
USB1 OTG kernel
USB1 ULPI
-
8.5
0.3
8.5
0.1
0.3
USB2 OTG
registers
15
13
12
USB2 OTG kernel
USB2 ULPI
-
8.6
16
8.6
16
16
10
AHB1 Bridge
9.6
8.6
DS12556 Rev 5
109/334
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 37. Peripheral current consumption in Run mode (continued)
IDD(Typ)
Peripheral
Unit
VOS1
VOS2
VOS3
DCMI
1.7
0.1
0.1
1.8
-
1.7
0.1
0.1
1.4
9.6
1.7
0.1
0.1
1.2
9.6
CRYP
HASH
RNG registers
RNG kernel
SDMMC2
registers
AHB2
13
12
11
SDMMC2 kernel
D2SRAM1
D2SRAM2
D2SRAM3
AHB2 bridge
GPIOA
2.7
3.3
2.9
1.9
0.1
1.1
1
2.5
3.1
2.7
1.8
0.1
1
2.4
2.8
2.5
1.7
0.1
0.9
0.9
1.3
0.9
0.8
0.8
0.7
0.9
0.8
0.8
0.7
0.4
5.5
1.7
0.1
1.8
0.1
10
GPIOB
0.9
1.3
1
GPIOC
1.4
1.1
1
µA/MHz
GPIOD
GPIOE
0.9
0.8
0.7
0.9
0.9
0.8
0.8
0.4
5.8
1.7
0.1
1.8
0.1
11
GPIOF
0.9
0.9
1
GPIOG
GPIOH
AHB4
GPIOI
0.9
0.9
0.9
0.5
6.2
1.8
0.1
1.9
0.1
12
GPIOJ
GPIOK
CRC
BDMA
ADC3 registers
ADC3 kernel
Backup SRAM
Bridge AHB4
LCD-TFT
WWDG1
APB3 bridge
APB3
0.5
0.5
0.4
0.2
0.3
0.1
µA/MHz
110/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 37. Peripheral current consumption in Run mode (continued)
DD(Typ)
I
Peripheral
Unit
VOS1
VOS2
VOS3
TIM2
3.5
3.4
2.7
3.2
1
3.2
3.1
2.5
2.9
0.8
0.9
1.5
1.3
1.3
0.6
2.1
0.4
1.5
0.5
1.3
0.5
2.9
2.7
1.9
2.5
0.7
0.7
1.2
1
TIM3
TIM4
TIM5
TIM6
TIM7
1
TIM12
1.7
1.5
1.4
0.7
2.3
0.6
1.8
0.6
1.5
0.6
TIM13
TIM14
0.9
0.5
1.9
0.4
1.2
0.5
1.1
0.5
LPTIM1 registers
LPTIM1 kernel
WWDG2
SPI2 registers
SPI2 kernel
SPI3 registers
SPI3 kernel
APB1
µA/MHz
SPDIFRX1
registers
0.6
0.5
0.3
SPDIFRX1 kernel
USART2 registers
USART2 kernel
USART3 registers
USART3 kernel
UART4 registers
UART4 kernel
2.9
1.4
4.7
1.4
4.2
1.5
3.7
2.4
1.3
4.1
1.3
3.8
1.1
3.6
2.4
1
4
1
3.5
1
3.2
DS12556 Rev 5
111/334
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 37. Peripheral current consumption in Run mode (continued)
IDD(Typ)
Peripheral
Unit
VOS1
VOS2
VOS3
UART5 registers
1.4
3.6
0.8
2
1.4
3.2
0.8
1.8
0.7
1.7
0.7
1.9
1
UART5 kernel
I2C1 registers
I2C1 kernel
3.1
0.6
1.7
0.4
1.6
0.6
1.9
I2C2 registers
I2C2 kernel
0.7
1.9
0.9
2.1
I2C3 registers
I2C3 kernel
HDMI-CEC
registers
0.5
0.3
0.3
DAC1/2
USART7 registers
USART7 kernel
USART8 registers
USART8 kernel
CRS
1.4
1.9
4
1.1
1.8
3.5
1.5
3.6
3.1
2
0.9
1.3
3.3
1.2
3.3
2.9
2
APB1
(continued)
µA/MHz
1.6
4
3.4
2.3
0.1
0.5
2.7
16
SWPMI registers
SWPMI kernel
OPAMP
0.1
0.4
2.4
15
0.1
0.4
2.3
14
MDIO
FDCAN registers
FDCAN kernel
Bridge APB1
7.8
0.1
7.6
0.1
7.1
0.1
112/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 37. Peripheral current consumption in Run mode (continued)
DD(Typ)
I
Peripheral
Unit
VOS1
VOS2
VOS3
TIM1
5.1
5.4
2.7
0.1
2.6
0.1
1.8
1
4.8
4.9
2.6
0.1
2.5
0.1
1.6
0.8
1.5
0.4
2.8
2.1
2
4.3
4.6
2.5
0.1
2.5
0.1
1.6
0.6
1.5
0.4
2.7
2.1
1.9
1.7
0.3
1.4
1.5
1.3
1.8
1.6
2.1
5.2
0.7
35
TIM8
USART1 registers
USART1 kernel
USART6 registers
USART6 kernel
SPI1 registers
SPI1 kernel
SPI4 registers
SPI4 kernel
1.6
0.5
3.1
2.4
2.2
1.8
0.6
1.5
2
TIM15
TIM16
APB2
TIM17
µA/MHz
SPI5 registers
SPI5 kernel
1.7
0.5
1.4
1.7
1.5
1.9
1.6
2.3
5.4
0.8
37
SAI1 registers
SAI1 kernel
SAI2 registers
SAI2 kernel
1.5
2.2
1.8
2.5
6
SAI3 registers
SAI3 kernel
DFSDM1 registers
DFSDM1 kernel
HRTIM
0.9
40
Bridge APB2
0.1
0.1
0.1
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 37. Peripheral current consumption in Run mode (continued)
IDD(Typ)
Peripheral
Unit
VOS1
VOS2
VOS3
SYSCFG
1
0.7
0.7
LPUART1
registers
1.1
1.1
1.1
LPUART1 kernel
SPI6 registers
SPI6 kernel
2.6
1.6
0.2
0.1
2.4
0.5
2.3
0.5
2
2.4
1.5
0.2
0.1
2.1
0.5
2.1
0.5
2.1
0.5
2
2.1
1.4
0.2
0.1
2
I2C4 registers
I2C4 kernel
LPTIM2 registers
LPTIM2 kernel
LPTIM3 registers
LPTIM3 kernel
LPTIM4 registers
LPTIM4 kernel
LPTIM5 registers
LPTIM5 kernel
COMP1/2
0.5
1.8
0.5
1.5
0.5
1.9
0.5
1.5
0.5
0.4
1.1
1.4
1.2
0.1
APB4
µA/MHz
0.5
2
0.5
2
0.5
1.8
0.5
0.4
1.1
1.5
1.3
0.1
0.7
0.6
1.2
1.6
1.3
0.1
VREFBUF
RTC
SAI4 registers
SAI4 kernel
Bridge APB4
Table 38. Peripheral current consumption in Stop, Standby and VBAT mode
Typ
Symbol
Parameter
Conditions
Unit
3 V
RTC+LSE low drive
-
-
2.32
RTC+LSE medium-
low drive
2.4
IDD
µA
RTC+LSE medium-
high drive
-
-
2.7
3
RTC+LSE High drive
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
6.3.7
Wakeup time from low-power modes
The wakeup times given in Table 39 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
Table 39. Low-power mode wakeup timings
Typ(1)
Max(1)
Symbol
Parameter
Conditions
Unit
CPU
clock
cycles
(2)
tWUSLEEP
Wakeup from Sleep
-
9
10
VOS3, HSI, Flash memory in normal mode
4.4
12
15
23
30
38
27
36
38
47
52
62
5.6
15
20
28
71
47
37
50
48
61
64
77
VOS3, HSI, Flash memory in low-power
mode
VOS4, HSI, Flash memory in normal mode
VOS4, HSI, Flash memory in low-power
mode
VOS5, HSI, Flash memory in normal mode
VOS5, HSI, Flash memory in low-power
mode
(2)
tWUSTOP
Wakeup from Stop
VOS3, CSI, Flash memory in normal mode
VOS3, CSI, Flash memory in low power
mode
µs
VOS4, CSI, Flash memory in normal mode
VOS4, CSI, Flash memory in low-power
mode
VOS5, CSI, Flash memory in normal mode
VOS5, CSI, Flash memory in low-power
mode
VOS3, HSI, Flash memory in normal mode
VOS3, CSI, Flash memory in normal mode
2.6
26
3.4
36
Wakeup from Stop,
clock kept running
(2)
tWUSTOP2
Wakeup from Standby
mode
(2)
tWUSTDBY
-
390
500
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
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6.3.8
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 58: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 14.
(1)
Table 40. High-speed external user clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fHSE_ext
User external clock source frequency
4
25
50
MHz
VSW
(VHSEH ?VHSEL)
OSC_IN amplitude
0.7VDD
-
VDD
V
VDC
OSC_IN input voltage
VSS
7
-
-
0.3VSS
-
tW(HSE)
OSC_IN high or low time
ns
1. Guaranteed by design.
Figure 14. High-speed external clock source AC timing diagram
V
HSEH
90%
10 %
HSEL
V
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
I
L
OSC _I N
clock source
STM32
ai17528b
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Electrical characteristics (rev Y)
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 58: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 15.
(1)
Table 41. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
-
-
-
32.768
1000
VDDIOx
kHz
0.7 VDDIOx
VSS
-
-
V
0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
-
250
-
-
ns
1. Guaranteed by design.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 15. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
W(LSE)
t
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
I
L
OSC32_IN
clock source
STM32
ai17529b
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 42. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 42. 4-48 MHz HSE oscillator characteristics
Operating
Symbol
Parameter
Min
Typ
Max
Unit
conditions(2)
F
Oscillator frequency
Feedback resistor
-
4
-
-
200
-
48
-
MHz
kΩ
RF
-
During startup(3)
-
4
V
DD=3 V, Rm=30 Ω
-
-
-
-
-
0.35
0.40
0.45
0.65
0.95
-
-
-
-
-
CL=10pF@4MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 8 MHz
IDD(HSE)
HSE current consumption
mA
VDD=3 V, Rm=30 Ω
CL=10 pF at 16 MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 48 MHz
Gmcritmax
Maximum critical crystal gm
Start-up time
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 16). C and C are usually
L1
L2
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . The PCB and MCU pin capacitance must be included
L1
L2
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing C and C .
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 16. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
OSC_OUT
(1)
STM32
R
EXT
C
L2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 43. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 43. Low-speed external user clock characteristics
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
-
32.768
-
kHz
LSEDRV[1:0] = 00,
Low drive capability
-
-
-
-
-
-
-
290
390
550
900
-
-
-
LSEDRV[1:0] = 01,
Medium Low drive capability
LSE current
consumption
IDD
nA
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
LSEDRV[1:0] = 00,
Low drive capability
0.5
0.75
1.7
LSEDRV[1:0] = 01,
Medium Low drive capability
-
Maximum critical crystal
gm
Gmcritmax
µA/V
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
-
-
2.7
-
(3)
tSU
Startup time
VDD is stabilized
DS12556 Rev 5
2
s
1. Guaranteed by design.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 17. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC32_IN
Bias
controlled
gain
32.768 kHz
resonator
RF
OSC32_OUT
STM32
CL2
ai17531c
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
6.3.9
Internal clock source characteristics
The parameters given in Table 44 and Table 47 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 22: General
DD
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 44. HSI48 oscillator characteristics
Symbol
Parameter
HSI48 frequency
Conditions
Min
Typ
Max
Unit
fHSI48
VDD=3.3 V, TJ=30 °C 47.5(1)
48
48.5(1) MHz
TRIM(2)
USER trimming step
-
-
-
0.17
-
-
%
%
%
%
USER TRIM
COVERAGE(3)
USER TRIMMING Coverage
± 32 steps
-
±5.45
DuCy(HSI48)(2) Duty Cycle
45
–4.5
-
-
55
3.5
Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
VDD=1.62 to 3.6 V,
TJ=-40 to 125 °C
ACCHSI48_REL(3)
∆VDD(HSI48)(3)
VDD=3 to 3.6 V
-
-
-
-
0.025
0.05
2.1
0.05
0.1
HSI48 oscillator frequency drift with
%
(4)
VDD
VDD=1.62 V to 3.6 V
(2)
tsu(HSI48)
HSI48 oscillator start-up time
-
-
3.5
µs
(2)
IDD(HSI48)
HSI48 oscillator power consumption
350
400
µA
Next transition jitter
Accumulated jitter on 28 cycles(5)
NT jitter
PT jitter
-
-
-
-
± 0.15
± 0.25
-
-
ns
ns
Paired transition jitter
Accumulated jitter on 56 cycles(5)
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization.
4. These values are obtained by using the formula:
(Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) / Freq(1.62V).
5. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
Table 45. HSI oscillator characteristics
(1)
Symbol
Parameter
HSI frequency
Conditions
Min
Typ
Max
Unit
fHSI
VDD=3.3 V, TJ=30 °C
63.7(2)
64
64.3(2)
MHz
Trimming is not a multiple
of 32
-
0.24
−1.8
−0.8
0.32
Trimming is 128, 256 and
384
−5.2
−1.4
-
-
Trimming is 64, 192, 320
and 448
TRIM
HSI user trimming step
%
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
−0.6
−0.25
-
DuCy(HSI) Duty Cycle
-
45
-
-
55
%
%
%
HSI oscillator frequency drift over
VDD (reference is 3.3 V)
ΔVDD (HSI)
V
DD=1.62 to 3.6 V
−0.12
0.03
TJ=-20 to 105 °C
−1(3)
-
-
1(3)
1(3)
2
HSI oscillator frequency drift over
temperature (reference is 64 MHz)
ΔTEMP (HSI)
TJ=−40 to TJmax °C
−2(3)
tsu(HSI)
HSI oscillator start-up time
-
-
-
-
1.4
4
µs
µs
µA
t
stab(HSI) HSI oscillator stabilization time
at 1% of target frequency
-
8
IDD(HSI) HSI oscillator power consumption
300
400
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
4 MHz low-power internal RC oscillator (CSI)
Table 46. CSI oscillator characteristics
(1)
Symbol
Parameter
CSI frequency
Conditions
Min
Typ
Max
Unit
fCSI
TRIM
VDD=3.3 V, TJ=30 °C
3.96(2)
4
0.35
-
4.04(2) MHz
Trimming step
Duty Cycle
-
-
-
-
%
%
DuCy(CSI)
45
55
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(1)
Table 46. CSI oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TJ = 0 to 85 °C
-
-
−3.7(3) 4.5(3)
CSI oscillator frequency drift over
temperature
ΔTEMP (CSI)
%
TJ = −40 to 125 °C
−11(3)
−0.06
1
7.5(3)
0.06
2
CSI oscillator frequency drift over
VDD
DVDD (CSI)
tsu(CSI)
VDD = 1.62 to 3.6 V
-
-
-
-
%
µs
CSI oscillator startup time
-
-
-
CSI oscillator stabilization time
tstab(CSI)
IDD(CSI)
4
8
cycle
µA
(to reach ±3% of fCSI
)
CSI oscillator power consumption
23
30
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Low-speed internal (LSI) RC oscillator
Table 47. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V, TJ = 25 °C
31.4
32
32.6
(1)
fLSI
LSI frequency
kHz
TJ = –40 to 105 °C, VDD
1.62 to 3.6 V
=
29.76
-
33.60
130
(2)
tsu(LSI)
LSI oscillator startup time
-
-
-
-
80
µs
LSI oscillator stabilization
time (5% of final value)
(2)
tstab(LSI)
120
170
LSI oscillator power
consumption
(2)
IDD(LSI)
-
-
130
280
nA
1. Guaranteed by characterization results.
2. Guaranteed by design.
6.3.10
PLL characteristics
The parameters given in Table 48 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 22: General operating conditions.
DD
(1)
Table 48. PLL characteristics (wide VCO frequency range)
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
-
2
-
-
16
90
MHz
%
PLL input clock duty cycle
10
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Electrical characteristics (rev Y)
(1)
Table 48. PLL characteristics (wide VCO frequency range) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOS1
VOS2
VOS3
VOS1
VOS2
VOS3
-
1.5
1.5
1.5
1.5
1.5
1.5
192
-
-
400(2)
300
fPLL_P_OUT PLL multiplier output clock P
fPLL_Q_OUT PLL multiplier output clock Q/R
-
-
200
-
400(2)
MHz
-
300
-
-
200
fVCO_OUT
PLL VCO output
PLL lock time
836
Normal mode
50(3)
150(3)
tLOCK
µs
±ps
%
Sigma-delta mode
(CKIN ≥8 MHz)
-
58(3)
166(3)
VCO = 192 MHz
VCO = 200 MHz
VCO = 400 MHz
VCO = 800 MHz
Normal mode
-
-
-
-
-
134
134
76
-
-
-
-
-
Cycle-to-cycle jitter(4)
Long term jitter
39
Jitter
±0.7
Sigma-delta mode
(CKIN = 16 MHz)
-
±0.8
-
VDDA
VCORE
VDDA
-
-
-
-
440
530
180
200
1150
VCO freq =
420 MHz
-
500
-
(3)
IDD(PLL)
PLL power consumption on VDD
µA
VCO freq =
150 MHz
VCORE
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation (400 MHz for VOS1, 300 MHz for VOS2,
200 MHz for VOS3).
3. Guaranteed by characterization results.
4. Integer mode only.
(1)
Table 49. PLL characteristics (medium VCO frequency range)
Symbol
Parameter
PLL input clock
Conditions
Min
Typ
Max Unit
-
1
10
-
-
-
-
-
-
2
MHz
%
fPLL_IN
PLL input clock duty cycle
-
VOS1
90
1.17
1.17
1.17
150
210
PLL multiplier output clock P, Q,
R
fPLL_OUT
VOS2
210 MHz
200
VOS3
fVCO_OUT
tLOCK
PLL VCO output
PLL lock time
-
420 MHz
Normal mode
Sigma-delta mode
-
60(2) 100(2) µs
forbidden
-
-
µs
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
(1)
Table 49. PLL characteristics (medium VCO frequency range) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VCO =
150 MHz
-
145
-
VCO =
300 MHz
-
-
-
-
-
-
-
-
91
64
63
55
30
-
-
+/-
Cycle-to-cycle jitter(3)
-
ps
-
VCO =
400 MHz
VCO =
420 MHz
-
VCO =
150 MHz
Jitter
-
fPLL_OUT
50 MHz
=
+/-
Period jitter
ps
-
VCO =
400 MHz
VCO =
150 MHz
-
VCO =
300 MHz
Long term jitter
Normal mode
-
-
-
%
VCO =
400 MHz
+/-0.3
VDD
VCORE
VDD
-
-
-
-
440
530
180
200
1150
VCO freq =
420MHz
-
500
-
I(PLL)(2)
PLL power consumption on VDD
µA
VCO freq =
150MHz
VCORE
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
6.3.11
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 125 °C unless otherwise specified.
J
The devices are shipped to customers with the Flash memory erased.
Table 50. Flash memory characteristics
Symbol
Parameter
Conditions
Write / Erase 8-bit mode
Min
Typ
Max
Unit
-
-
-
-
6.5
11.5
20
-
-
-
-
Write / Erase 16-bit mode
Write / Erase 32-bit mode
Write / Erase 64-bit mode
IDD
Supply current
mA
35
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 51. Flash memory programming
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
Program parallelism x 8
-
-
-
-
-
-
-
-
-
-
-
290
180
130
100
2
580(2)
360
µs
260
Word (266 bits) programming
time
tprog
200
4
tERASE128KB Sector (128 KB) erase time
1.8
3.6
13
8
26
16
12
10
s
tME
Mass erase time
6
5
Program parallelism x 16
1.62
1.8
-
-
3.6
3.6
Vprog
Programming voltage
V
Program parallelism x 32
Program parallelism x 64
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
Table 52. Flash memory endurance and data retention
Value
Min(1)
Symbol
Parameter
Conditions
Unit
NEND
tRET
Endurance
Data retention
TJ = –40 to +125 °C (6 suffix versions)
1 kcycle at TA = 85 °C
kcycles
Years
10
30
20
10 kcycles at TA = 55 °C
1. Guaranteed by characterization results.
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6.3.12
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 53. They are based on the EMS levels and classes
defined in application note AN1709.
Table 53. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
Voltage limits to be applied on any I/O pin to induce
a functional disturbance
VFESD
3B
4B
VDD = 3.3 V, TA = +25 °C,
UFBGA240, frcc_c_ck
=
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
400 MHz, conforms to
IEC 61000-4-2
VFTB
As a consequence, it is recommended to add a serial resistor (1 k?) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
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Prequalification trials
Electrical characteristics (rev Y)
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 54. EMI characteristics
Max vs.
Monitored
frequency band
[fHSE/fCPU
]
Symbol Parameter
Conditions
Unit
8/400 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
6
5
dBµV
-
VDD = 3.6 V, TA = 25 °C, UFBGA240 package,
conforming to IEC61967-2
SEMI
Peak level
13
7
2.5
6.3.13
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 55. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Packages
Class
Unit
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
001
All
1C
1000
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA =+25 °C conforming to
ANSI/ESDA/JEDEC JS-
002
All
C1
250
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
Static latchup
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 56. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latchup class
TA =+25 °C conforming to JESD78
II level A
6.3.14
I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
DD
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 57. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
PJ12, PB4
5
0
0
5
0
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11
NA
0
IINJ
mA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PH4, PH5, BOOT0
All other I/Os
NA
1. Guaranteed by characterization.
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Electrical characteristics (rev Y)
6.3.15
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 58: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 22: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Table 58. I/O static characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I/O input low level voltage except
BOOT0
(1)
-
-
0.3VDD
I/O input low level voltage except
BOOT0
0.4VDD
0.1(2)
−
VIL
1.62 V<VDDIOx<3.6 V
-
-
-
V
0.19VDD
+
BOOT0 I/O input low level voltage
-
0.1(2)
I/O input high level voltage except
BOOT0
(1)
0.7VDD
-
-
-
-
-
I/O input high level voltage except
BOOT0(3)
0.47VDD
0.25(2)
+
+
VIH
1.62 V<VDDIOx<3.6 V
-
-
V
BOOT0 I/O input high level
voltage(3)
0.17VDD
0.6(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis
-
250
(2)
VHYS
1.62 V< VDDIOx <3.6 V
mV
BOOT0 I/O input hysteresis
-
-
200
-
-
(9)
0< VIN ≤ Max(VDDXXX
)
+/-250
FT_xx Input leakage current(2)
Max(VDDXXX) < VIN ≤ 5.5 V
-
-
-
-
-
-
1500
(5)(6)(9)
(9)
0< VIN ≤ Max(VDDXXX
)
+/- 350
5000(7)
(4)
FT_u IO
Ileak
Max(VDDXXX) < VIN ≤ 5.5 V
nA
(5)(6)(9)
(9)
TT_xx Input leakage current
0< VIN ≤ Max(VDDXXX
0< VIN ≤ VDDIOX
)
-
-
-
-
+/-250
15
VPP (BOOT0 alternate function)
VDDIOX < VIN ≤ 9 V
35
Weak pull-up equivalent
resistor(8)
RPU
VIN=VSS
30
40
50
kΩ
pF
Weak pull-down equivalent
resistor(8)
(9)
RPD
CIO
VIN=VDD
-
30
-
40
5
50
-
I/O pin capacitance
1. Compliant with CMOS requirement.
2. Guaranteed by design.
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD
.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max)
5. All FT_xx IO except FT_lu, FT_u and PC3.
.
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6. VIN must be less than Max(VDDXXX) + 3.6 V.
7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 18.
Figure 18. V /V for all I/Os except BOOT0
IL IH
3
2.5
2
TLL requirement: VIHmin = 2 V
1.5
1
TLL requirement: VILmin = 0.8 V
0.5
0
2.8
1.6
1.8
2
2.2
2.4
2.6
3
3.2
3.4
3.6
MSv46121V3
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 20).
VDD
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 20).
VSS
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Output voltage levels
Electrical characteristics (rev Y)
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 22: General operating conditions. All I/Os are CMOS and TTL compliant.
(1)
Table 59. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO=8 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO=-8 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=8 mA
(3)
VOL
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=-8 mA
(3)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
V
IIO=20 mA
(3)
VOL
Output low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
1.3
-
2.7 V≤ VDD ≤3.6 V
IIO=-20 mA
(3)
VOH
VDD−1.3
2.7 V≤ VDD ≤3.6 V
IIO=4 mA
(3)
VOL
-
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO=-4 mA
1.62 V≤VDD<3.6 V
(3)
VOH
VDD−-0.4
IIO= 20 mA
-
-
0.4
0.4
2.3 V≤ VDD≤3.6 V
Output low level voltage for an FTf
I/O pin in FM+ mode
(3)
VOLFM+
IIO= 10 mA
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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(1)
Table 60. Output voltage characteristics for PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO=3 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO=-3 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=3 mA
(3)
VOL
-
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=-3 mA
(3)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
IIO=1.5 mA
(3)
VOL
Output low level voltage
Output high level voltage
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO=-1.5 mA
(3)
VOH
VDD−0.4
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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Electrical characteristics (rev Y)
Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.5 V.
(1)(2)
Table 61. Output timing characteristics (HSLV OFF)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
3
12
(3)
Fmax
Maximum frequency
MHz
3
16
4
00
16.6
33.3
13.3
25
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
10
20
60
15
80
(3)
Fmax
Maximum frequency
15
110
20
01
5.2
10
Output high to low level
fall time and output low
to high level rise time
4.2
7.5
2.8
5.2
tr/tf(4)
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(1)(2)
Table 61. Output timing characteristics (HSLV OFF)
(continued)
Min
Speed Symbol
Parameter
conditions
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85
35
110
40
(3)
Fmax
Maximum frequency
MHz
166
100
3.8
6.9
2.8
5.2
1.8
3.3
100
50
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
133
66
(3)
Fmax
Maximum frequency
220
85
11
3.3
6.6
2.4
4.5
1.5
2.7
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
1. Guaranteed by design.
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
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Electrical characteristics (rev Y)
Output buffer timing characteristics (HSLV option enabled)
(1)
Table 62. Output timing characteristics (HSLV ON)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
10
10
11
(2)
Fmax
Maximum frequency
MHz
00
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
9
ns
MHz
ns
6.6
50
58
66
6.6
4.8
3
(3)
Fmax
Maximum frequency
01
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
55
80
133
5.8
4
(3)
Fmax
Maximum frequency
MHz
ns
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
2.4
60
90
175
5.3
3.6
1.9
(3)
Fmax
Maximum frequency
MHz
ns
11
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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6.3.16
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 58: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 63 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 22: General operating conditions.
Table 63. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Weak pull-up equivalent
resistor(1)
(2)
RPU
VIN = VSS
30
40
50
?
(2)
VF(NRST)
NRST Input filtered pulse
1.71 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
-
-
50
-
300
ns
(2)
VNF(NRST)
NRST Input not filtered pulse
1.62 V < VDD < 3.6 V 1000
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 19. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 58. Otherwise the reset is not taken into account by the device.
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Electrical characteristics (rev Y)
6.3.17
FMC characteristics
Unless otherwise specified, the parameters given in Table 64 to Table 77 for the FMC
interface are derived from tests performed under the ambient temperature, f
rcc_c_ck
frequency and V supply voltage conditions summarized in Table 22: General operating
DD
conditions, with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 20 through Figure 23 represent asynchronous waveforms and Table 64 through
Table 71 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
Capcitive load C = 30 pF
L
In all timing tables, the T
is the f
clock period.
KERCK
mc_ker_ck
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Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Electrical characteristics (rev Y)
(1)
Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
th(A_NOE)
tv(BL_NE)
Parameter
Min
Max
Unit
FMC_NE low time
2Tfmc_ker_ck − 1
2 Tfmc_ker_ck +1
FMC_NEx low to FMC_NOE low
FMC_NOE low time
0
0.5
2Tfmc_ker_ck − 1
2Tfmc_ker_ck + 1
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
0
-
-
0.5
Address hold time after FMC_NOE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NOE high
Data to FMC_NEx high setup time
Data to FMC_NOEx high setup time
Data hold time after FMC_NOE high
Data hold time after FMC_NEx high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
0
-
-
0.5
ns
th(BL_NOE)
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
0
11
11
0
0
-
-
-
-
-
-
0
-
Tfmc_ker_ck + 1
1. Guaranteed by characterization results.
(1)(2)
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
7Tfmc_ker_ck +1 7Tfmc_ker_ck +1
tw(NOE)
tw(NWAIT)
tsu(NWAIT_NE)
th(NE_NWAIT)
FMC_NWE low time
5Tfmc_ker_ck −1 5Tfmc_ker_ck +1
Tfmc_ker_ck −0.5
ns
FMC_NWAIT low time
FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT invalid
4Tfmc_ker_ck +11
3Tfmc_ker_ck+11.5
-
-
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
(1)
Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
tw(NE)
Parameter
Min
Max
Unit
FMC_NE low time
3Tfmc_ker_ck ?1
Tfmc_ker_ck
fmc_ker_ck ?0.5 Tfmc_ker_ck + 0.5
3Tfmc_ker_ck
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
FMC_NEx low to FMC_NWE low
FMC_NWE low time
Tfmc_ker_ck + 1
T
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
Address hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NWE high
Data to FMC_NEx low to Data valid
Data hold time after FMC_NWE high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
Tfmc_ker_ck
-
2
-
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
th(Data_NWE)
tv(NADV_NE)
tw(NADV)
T
T
fmc_ker_ck ?0.5
-
ns
-
0.5
-
fmc_ker_ck ?0.5
-
Tfmc_ker_ck + 2.5
Tfmc_ker_ck+0.5
-
-
-
0
Tfmc_ker_ck + 1
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
(1)(2)
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck ?1
8Tfmc_ker_ck + 1
tw(NWE)
FMC_NWE low time
6Tfmc_ker_ck ?1.5 6Tfmc_ker_ck + 0.5
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
FMC_NWAIT valid before FMC_NEx high
5Tfmc_ker_ck + 13
-
-
FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+ 13
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Figure 22. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
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(1)
Table 68. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NOE_NE)
ttw(NOE)
FMC_NE low time
3Tfmc_ker_ck ?1
3Tfmc_ker_ck + 1
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2Tfmc_ker_ck
2Tfmc_ker_ck + 0.5
Tfmc_ker_ck ?1
Tfmc_ker_ck + 1
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
0
-
-
0.5
0
0.5
T
fmc_ker_ck ?0.5
Tfmc_ker_ck+1
FMC_AD(address) valid hold time after
FMC_NADV high
th(AD_NADV)
T
fmc_ker_ck + 0.5
-
ns
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FMC_NOE high
FMC_BL time after FMC_NOE high
FMC_NEx low to FMC_BL valid
T
fmc_ker_ck ?0.5
-
0
-
-
0.5
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NE)
th(Data_NOE)
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
T
fmc_ker_ck ?2
-
-
T
fmc_ker_ck ?2
0
0
-
-
1. Guaranteed by characterization results.
(1)
Table 69. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck ?1
8Tfmc_ker_ck
tw(NOE)
FMC_NWE low time
5Tfmc_ker_ck ?1.5 5Tfmc_ker_ck + 0.5
ns
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
5Tfmc_ker_ck + 3
4Tfmc_ker_ck
-
-
FMC_NEx hold time after FMC_NWAIT
invalid
th(NE_NWAIT)
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
Figure 23. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FMC_ NEx
FMC_NOE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
FMC_NWE
t
t
h(A_NWE)
v(A_NE)
FMC_ A[25:16]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_ NBL[1:0]
NBL
v(Data_NADV)
Data
t
t
h(Data_NWE)
t
v(A_NE)
Address
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
(1)
Table 70. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
4Tfmc_ker_c ?1
4Tfmc_ker_ck
tv(NWE_NE) FMC_NEx low to FMC_NWE low
tw(NWE) FMC_NWE low time
T
fmc_ker_c ?1
Tfmc_ker_ck + 0.5
2Tfmc_ker_ck+ 0.5
2Tfmc_ker_ck
0.5
?
th(NE_NWE) FMC_NWE high to FMC_NE high hold time
tv(A_NE) FMC_NEx low to FMC_A valid
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV) FMC_NADV low time
T
fmc_ker_ck ? 0.5
-
-
0
0
0.5
ns
Tfmc_ker_ck
Tfmc_ker_ck+ 1
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck+0.5
-
th(A_NWE) Address hold time after FMC_NWE high
th(BL_NWE) FMC_BL hold time after FMC_NWE high
Tfmc_ker_ck+0.5
-
Tfmc_ker_ck ?0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0.5
tv(Data_NADV) FMC_NADV high to Data valid
-
Tfmc_ker_ck + 2
-
th(Data_NWE) Data hold time after FMC_NWE high
Tfmc_ker_ck+0.5
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1. Guaranteed by characterization results.
(1)
Table 71. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9Tfmc_ker_ck – 1
9Tfmc_ker_ck
ns
tw(NWE)
FMC_NWE low time
7Tfmc_ker_ck – 0.5 7Tfmc_ker_ck + 0.5
tsu(NWAIT_NE)
th(NE_NWAIT)
FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT invalid
6Tfmc_ker_ck + 3
4Tfmc_ker_ck
-
-
1. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 24 through Figure 27 represent synchronous waveforms and Table 72 through
Table 75 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all the timing tables, the Tfmc_ker_ck is the f
FMC_CLK maximum values:
clock period, with the following
mc_ker_ck
For 2.7 V<V <3.6 V, FMC_CLK =100 MHz at 20 pF
DD
For 1.8 V<V <1.9 V, FMC_CLK =100 MHz at 20 pF
DD
For 1.62 V<V <1.8 V, FMC_CLK =100 MHz at 15 pF
DD
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Electrical characteristics (rev Y)
Figure 24. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
su(ADV-CLKH)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
MS32757V1
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(1)
Table 72. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck ?1
-
1
-
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
Tfmc_ker_ck + 0.5
-
1.
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
2.5
-
Tfmc_ker_ck
-
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
1.5
-
ns
T
fmc_ker_ck ?0.5
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
0
2
1
2
2
3
-
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
-
-
-
-
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Electrical characteristics (rev Y)
Figure 25. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
FMC_A[25:16]
t
d(CLKH-NWEH)
d(CLKL-NWEL)
FMC_NWE
t
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
d(CLKL-Data)
d(CLKL-ADV)
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKH-NBLH)
FMC_NBL
MS32758V1
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(1)
Table 73. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck ?1
-
1
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
-
Tfmc_ker_ck + 0.5
-
-
1.5
-
FMC_CLK low to FMC_NADV high
0
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NWE low
-
2
td(CLKH-AIV)
Tfmc_ker_ck
-
td(CLKL-NWEL)
t(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
td(CLKL-DATA)
td(CLKL-NBLL)
td(CLKH-NBLH)
-
1.5
-
ns
FMC_CLK high to FMC_NWE high
Tfmc_ker_ck + 0.5
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
FMC_A/D[15:0] valid data after FMC_CLK low
FMC_CLK low to FMC_NBL low
-
2.5
-
0
-
2.5
2
-
FMC_CLK high to FMC_NBL high
Tfmc_ker_ck + 0.5
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
Figure 26. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
MS32759V1
(1)
Table 74. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0..2)
2Tfmc_ker_ck ?1
-
t(CLKL-NExL)
-
2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
Tfmc_ker_ck + 0.5
-
-
0.5
0
-
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
2
Tfmc_ker_ck
-
ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
-
1.5
Tfmc_ker_ck + 0.5
-
-
-
-
-
tsu(DV-CLKH)
th(CLKH-DV)
FMC_D[15:0] valid data before FMC_CLK high
FMC_D[15:0] valid data after FMC_CLK high
2
1
2
2
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 27. Synchronous non-multiplexed PSRAM write timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKL-NExL)
FMC_NEx
d(CLKH-NExH)
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
FMC_NWE
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
td(CLKH-NWEH)
d(CLKL-NWEL)
t
t
d(CLKL-Data)
d(CLKL-Data)
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FMC_NBL
t
t
d(CLKH-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
MS32760V1
(1)
Table 75. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
t(CLK)
FMC_CLK period
2Tfmc_ker_ck ?1
-
2
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
-
Tfmc_ker_ck + 0.5
-
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
0.5
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
2
Tfmc_ker_ck
-
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
-
1.5
-
Tfmc_ker_ck + 1
td(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK low
-
3.5
2
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
-
Tfmc_ker_ck + 1
-
2
2
-
-
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NAND controller waveforms and timings
Electrical characteristics (rev Y)
Figure 28 through Figure 31 represent synchronous waveforms, and Table 76 and Table 77
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
COM.FMC_SetupTime = 0x01
COM.FMC_WaitSetupTime = 0x03
COM.FMC_HoldSetupTime = 0x02
COM.FMC_HiZSetupTime = 0x01
ATT.FMC_SetupTime = 0x01
ATT.FMC_WaitSetupTime = 0x03
ATT.FMC_HoldSetupTime = 0x02
ATT.FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
C = 30 pF
L
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 28. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
t
th(NOE-ALE)
d(ALE-NOE)
FMC_NOE (NRE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
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Figure 29. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NWE-ALE)
d(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NWE-D)
v(NWE-D)
MS32768V1
Figure 30. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NOE-ALE)
d(ALE-NOE)
FMC_NWE
FMC_NOE
t
w(NOE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
MS32769V1
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Electrical characteristics (rev Y)
Figure 31. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
t
h(NOE-ALE)
d(ALE-NOE)
w(NWE)
FMC_NWE
FMC_N OE
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FMC_D[15:0]
MS32770V1
(1)
Table 76. Switching characteristics for NAND Flash read cycles
Parameter Min
FMC_NOE low width 4Tfmc_ker_ck –0.5 4Tfmc_ker_ck + 0.5
Symbol
Max
Unit
tw(N0E)
tsu(D-NOE)
th(NOE-D)
FMC_D[15-0] valid data before FMC_NOE high
FMC_D[15-0] valid data after FMC_NOE high
8
-
0
-
ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid
1. Guaranteed by characterization results.
-
3Tfmc_ker_ck + 1
-
4Tfmc_ker_ck ?2
(1)
Table 77. Switching characteristics for NAND Flash write cycles
Parameter Min
FMC_NWE low width 4Tfmc_ker_ck ?0.5 4Tfmc_ker_ck + 0.5
Symbol
Max
Unit
tw(NWE)
tv(NWE-D)
th(NWE-D)
td(D-NWE)
td(ALE-NWE)
th(NWE-ALE)
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
FMC_D[15-0] valid before FMC_NWE high
FMC_ALE valid before FMC_NWE low
FMC_NWE high to FMC_ALE invalid
0
-
2Tfmc_ker_ck ?0.5
5Tfmc_ker_ck ?1
-
-
ns
-
3Tfmc_ker_ck + 0.5
-
2Tfmc_ker_ck ?1
1. Guaranteed by characterization results.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SDRAM waveforms and timings
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
For 1.8 V<V <3.6V: FMC_CLK =100 MHz at 20 pF
DD
For 1.62 V< <1.8 V, FMC_CLK =100 MHz at 15 pF
DD
Figure 32. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
th(SDCLKL_NCAS)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
td(SDCLKL_NCAS)
FMC_SDNWE
FMC_D[31:0]
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Data1 Data2
Datai
Datan
MS32751V2
(1)
Table 78. SDRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Tfmc_ker_ck ?1 2Tfmc_ker_ck + 0.5
tsu(SDCLKH _Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
2
1
-
-
-
1.5
1.5
-
td(SDCLKL- SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0.5
-
1
0.5
-
-
0.5
-
0
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
(1)
Table 79. LPSDR SDRAM read timings
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Tfmc_ker_ck ?1 2Tfmc_ker_ck + 0.5
tsu(SDCLKH_Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
2
1.5
-
-
-
2.5
2.5
-
td(SDCLKL_SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0
-
0.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
Figure 33. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
th(SDCLKL_NCAS)
th(SDCLKL_NWE)
td(SDCLKL_NCAS)
td(SDCLKL_NWE)
td(SDCLKL_Data)
Data1
Data2
Datai
Datan
FMC_D[31:0]
td(SDCLKL_NBL)
FMC_NBL[3:0]
th(SDCLKL_Data)
MS32752V2
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
(1)
Table 80. SDRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Tfmc_ker_ck ?1
2Tfmc_ker_ck + 0.5
td(SDCLKL _Data
th(SDCLKL _Data)
td(SDCLKL_Add)
)
-
0
3
-
-
1.5
1.5
-
td(SDCLKL_SDNWE)
th(SDCLKL_SDNWE)
td(SDCLKL_ SDNE)
th(SDCLKL-_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
td(SDCLKL_SDNCAS)
-
0.5
-
ns
1.5
-
0.5
-
1
0.5
-
-
1
0.5
-
1. Guaranteed by characterization results.
(1)
Table 81. LPSDR SDRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Tfmc_ker_ck ?1 2Tfmc_ker_ck + 0.5
td(SDCLKL _Data
)
-
0
-
2.5
-
th(SDCLKL _Data)
td(SDCLKL_Add)
2.5
2.5
-
td(SDCLKL-SDNWE)
th(SDCLKL-SDNWE)
td(SDCLKL- SDNE)
th(SDCLKL- SDNE)
td(SDCLKL-SDNRAS)
th(SDCLKL-SDNRAS)
td(SDCLKL-SDNCAS)
td(SDCLKL-SDNCAS)
-
0
-
ns
3
0
-
-
1.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
6.3.18
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 82 and Table 83 for QUADSPI
are derived from tests performed under the ambient temperature, f frequency and
rcc_c_ck
V
supply voltage conditions summarized in Table 22: General operating conditions, with
DD
the following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
I/O compensation cell enabled
DD
HSLV activated when V ≤2.7 V
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
Table 82. QUADSPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V ≤VDD<3.6 V
-
-
133
CL=20 pF
Fck1/TCK
QUADSPI clock frequency
MHz
1.62 V<VDD<3.6 V
CL=15 pF
-
-
100
tw(CKH)
tw(CKL)
ts(IN)
T
CK/2–0.5
-
TCK/2
QUADSPI clock high and low
time
-
-
TCK/2
1.5
2
-
TCK/2 + 0.5
Data input setup time
Data input hold time
Data output valid time
Data output hold time
-
-
-
-
ns
th(IN)
tv(OUT)
th(OUT)
-
-
-
1.5
-
2
-
0.5
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
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(1)
Table 83. QUADSPI characteristics in DDR mode
Parameter Conditions Min
Symbol
Typ
Max
Unit
2.7 V<VDD<3.6 V
CL=20 pF
-
-
-
100
QUADSPI clock
frequency
Fck1/t(CK)
MHz
1.62 V<VDD<3.6 V
CL=15 pF
-
100
tw(CKH)
tw(CKL)
TCK/2 –0.5
-
-
TCK/2
QUADSPI clock high and
low time
-
TCK/2
TCK/2+0.5
tsr(IN), tsf(IN)
Data input setup time
Data input hold time
-
2
2
-
-
-
-
t
hr(IN), thf(IN)
-
-
DHHC=0
3.5
4
ns
tvr(OUT)
,
Data output valid time
Data output hold time
DHHC=1
tvf(OUT)
-
TCK/4+3.5
TCK/4+4
Pres=1, 2...
DHHC=0
3
-
-
-
-
thr(OUT)
,
DHHC=1
thf(OUT)
T
CK/4+3
Pres=1, 2...
1. Guaranteed by characterization results.
Figure 34. Quad-SPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
Figure 35. Quad-SPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
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Electrical characteristics (rev Y)
6.3.19
Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 85 for the delay block are derived
from tests performed under the ambient temperature, f
frequency and V supply
rcc_c_ck
DD
voltage summarized in Table 22: General operating conditions.
(1)
Table 84. Dynamics characteristics: Delay Block characteristics
Symbol
Parameter
Initial delay
Unit Delay
Conditions
Min
1400
35
Typ
2200
40
Max
2400
45
Unit
tinit
t∆
-
-
ps
1. Guaranteed by characterization results.
6.3.20
16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 85 are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
PCLK2
DDA
conditions summarized in Table 22: General operating conditions.
(1)
Table 85. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog power supply
-
1.62
2
-
3.6
V
DDA ≥2 V
-
VDDA
VREF+ Positive reference voltage
V
VDDA< 2 V
-
VDDA
VREF-
fADC
Negative reference voltage
ADC clock frequency
VSSA
BOOST = 1
-
-
-
-
-
-
-
-
-
-
-
-
36
2 V≤VDDA≤3.3 V
MHz
BOOST = 0
16-bit resolution
20
3.60(2)
4.00(2)
4.50(2)
5.00(2)
6.00(2)
2.00(2)
2.20(2)
2.50(2)
2.80(2)
3.30(2)
1.00
14-bit resolution
12-bit resolution
10-bit resolution
8-bit resolution
16-bit resolution
14-bit resolution
12-bit resolution
10-bit resolution
8-bit resolution
16-bit resolution
14-bit resolution
12-bit resolution
10-bit resolution
8-bit resolution
Sampling rate for Fast
channels, BOOST = 1,
fADC = 36 MHz(2)
-
-
-
-
-
-
-
-
Sampling rate for Fast
channels, BOOST = 0,
fADC = 20 MHz
fS
MSPS
-
-
-
-
-
-
-
-
1.00
Sampling rate for Slow
channels, BOOST = 0,
fADC = 10 MHz
1.00
1.00
1.00
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(1)
Table 85. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fADC = 36 MHz
-
-
-
-
-
3.6
10
MHz
fTRIG
External trigger frequency
Conversion voltage range
16-bit resolution
-
1/fADC
(3)
VAIN
0
VREF+
V
Common mode input
voltage
V
REF/2−
10%
V
REF/2+
10%
VCMIV
RAIN
-
-
-
VREF/2
External input impedance
-
-
-
50
-
?
Internal sample and hold
capacitor
CADC
4
pF
tADCREG_
ADC LDO startup time
ADC power-up time
-
-
5
1
10
µs
STUP
conversion
cycle
tSTAB
tCAL
LDO already started
-
Offset and linearity
calibration time
165,010
tOFF_CAL Offset calibration time
-
1,280
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
-
1.5
-
2
-
2.5
2
Trigger conversion latency
for regular and injected
tLATR
channels without aborting
2.25
2.125
3.5
the conversion
1/fADC
2.5
3
-
Trigger conversion latency
for regular and injected
channels when a regular
conversion is aborted
-
-
3
tLATRINJ
-
3.25
3.125
640.5
-
-
tS
Sampling time
1.5
-
tS + 0.5 + N/2
Total conversion time
(including sampling time)
tCONV
N-bit resolution
(9 to 648 cycles in 14-bit
mode)
1. Guaranteed by design.
2. These values are obtained using the following formula: fS = fADC/ tCONV ,
where fADC = 36 MHz and tCONV = 1,5 cycle sampling time + tSAR sampling time.
Refer to the product reference manual for the value of tSAR depending on resolution.
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA
.
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Table 86. ADC accuracy
Electrical characteristics (rev Y)
(1)(2)(3)
Symbol
Parameter
Conditions(4)
Min
Typ
Max
Unit
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
BOOST = 1
BOOST = 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±6
±8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Total
unadjusted
error
ET
±10
±16
2
Differential
Single
ended
Differential
linearity
error
1
ED
±LSB
8
Differential
2
±6
Single
ended
Integral
linearity
error
±4
EL
±6
Differential
±4
11.6
12
Single
ended
Effective
number of
bits
ENOB(5)
SINAD(5)
SNR(5)
THD(5)
bits
13.3
13.5
71.6
74
Differential
(2 MSPS)
Signal-to-
noise and
distortion
ratio
Single
ended
81.83
83
Differential
(2 MSPS)
72
Single
ended
Signal-to-
noise ratio
74
dB
82
(2 MSPS)
Differential
83
−78
−80
−90
−95
Single
ended
Total
harmonic
distortion
Differential
1. Guaranteed by characterization for BGA packages, the values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. The above table gives the ADC performance in 16-bit mode.
4. ADC clock frequency ≤36 MHz, 2 V ≤ VDDA ≤3.3 V, 1.6 V ≤ VREF ≤ VDDA, BOOSTEN (for I/O) = 1.
5. ENOB, SINAD, SNR and THD are specified for VDDA = VREF = 3.3 V.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
DS12556 Rev 5
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
and ΣI
in
INJ(PIN)
INJ(PIN)
Section 6.3.14 does not affect the ADC accuracy.
Figure 36. ADC accuracy characteristics (12-bit resolution)
V
V
DDA
4096
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
E
G
4095
4094
4093
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
E
O
L
E
D
1L SB
IDEAL
7
0
V
1
2
3
456
4093 4094 4095 4096
V
DDA
SSA
ai14395c
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
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DS12556 Rev 5
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Electrical characteristics (rev Y)
Figure 37. Typical connection diagram using the ADC
STM32
V
DD
Sample and hold ADC
V
T
converter
0.6 V
(1)
AIN
(1)
R
R
ADC
AINx
12-bit
converter
V
0.6 V
T
V
AIN
C
(1)
ADC
C
parasitic
I
1 μA
L
ai17534b
1. Refer to Table 85 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 38 or Figure 39,
depending on whether V is connected to V or not. The 100 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 38. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM32
(1)
VREF+
1 μF // 100 nF
VDDA
1 μF // 100 nF
(1)
VSSA/VREF+
MSv50648V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA
.
Figure 39. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32
(1)
VREF+/VDDA
1 μF // 100 nF
(1)
VREF-/VSSA
MSv50649V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA
.
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
6.3.21
DAC electrical characteristics
(1)
Table 87. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
-
1.8
3.3
-
3.6
VREF+
Positive reference voltage
1.80
VDDA
V
Negative reference
voltage
VREF-
-
-
VSSA
-
-
-
connected to
5
VSSA
DAC output
buffer ON
RL
Resistive Load
connected to
VDDA
?
?
25
10.3
-
-
13
-
-
(2)
RO
Output Impedance
DAC output buffer OFF
16
1.6
VDD = 2.7 V
Output impedance sample
and hold mode, output
buffer ON
DAC output
buffer ON
RBON
VDD = 2.0 V
-
-
-
-
-
-
2.6
VDD = 2.7 V
VDD = 2.0 V
17.8
18.7
Output impedance sample
and hold mode, output
buffer OFF
DAC output
buffer OFF
RBOFF
?
(2)
CL
DAC output buffer OFF
Sample and Hold mode
-
-
-
50
1
pF
µF
Capacitive Load
(2)
CSH
0.1
VREF+
−0.2
DAC output buffer ON
DAC output buffer OFF
0.2
0
-
-
Voltage on DAC_OUT
output
VDAC_OUT
V
VREF+
Settling time (full scale: for
a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
Normal mode, DAC output buffer
OFF, ±1LSB CL=10 pF
tSETTLING
-
1.7(2)
2(2)
µs
Wakeup time from off
state (setting the Enx bit in Normal mode, DAC output buffer
(3)
tWAKEUP
-
5
7.5
µs
the DAC Control register)
until the ±1LSB final value
ON, CL ≤ 50 pF, RL = 5 ?
VREF+ = 3.6 V
VREF+ = 1.8 V
-
-
850
425
-
-
Middle code offset for 1
trim code step
(2)
Voffset
µV
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
(1)
Table 87. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
No load, middle
code (0x800)
-
360
-
DAC output
buffer ON
No load, worst
code (0xF1C)
-
-
490
-
-
DAC quiescent
IDDA(DAC)
No load,
middle/worst
code (0x800)
consumption from VDDA
DAC output
buffer OFF
20
Sample and Hold mode,
CSH=100 nF
360*TON/
(TON+TOFF
-
-
-
-
-
-
)
No load, middle
170
µA
code (0x800)
DAC output
buffer ON
No load, worst
code (0xF1C)
170
160
No load,
middle/worst
code (0x800)
DAC consumption from
VREF+
DAC output
buffer OFF
IDDV(DAC)
-
-
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code)
170*TON
(TON+TOFF
/
-
-
-
-
)
)
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code)
160*TON
(TON+TOFF
/
1. Guaranteed by characterization results.
2. Guaranteed by design.
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
(1)
Table 88. DAC accuracy
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON
DAC output buffer OFF
-
-
±2
±2
-
-
Differential non
linearity(2)
DNL
LSB
DAC output buffer ON, CL≤50 pF,
RL ≥5 ?
-
-
-
-
-
±4
±4
-
-
INL
Integral non linearity(3)
LSB
LSB
DAC output buffer OFF,
-
CL ≤50 pF, no RL
DAC output
buffer ON,
VREF+ = 3.6 V
±12
±25
±8
CL ≤50 pF,
RL ≥5 ?
Offset error at code
0x800 (3)
Offset
VREF+ = 1.8 V
-
DAC output buffer OFF,
-
CL ≤50 pF, no RL
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
(1)
Table 88. DAC accuracy (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Offset error at code
0x001(4)
DAC output buffer OFF,
Offset1
-
-
±5
LSB
CL ≤50 pF, no RL
DAC output
buffer ON,
V
REF+ = 3.6 V
-
-
-
-
-
-
-
-
-
-
±5
±7
Offset error at code
0x800 after factory
calibration
OffsetCal
Gain
LSB
%
CL ≤50 pF,
RL ≥5 ?
VREF+ = 1.8 V
DAC output buffer ON,CL≤50 pF,
RL ≥5 ?
±1
Gain error(5)
DAC output buffer OFF,
±1
CL ≤ 50 pF, no RL
DAC output buffer OFF,
TUE
SNR
Total unadjusted error
Signal-to-noise ratio(6)
±12
LSB
dB
CL ≤ 50 pF, no RL
DAC output buffer ON,CL ≤50 pF,
RL ≥5 ?, 1 kHz, BW = 500 KHz
-
67.8
-
Signal-to-noise and DAC output buffer ON, CL≤50 pF,
SINAD
ENOB
-
-
67.5
10.9
-
-
dB
distortion ratio(6)
RL ≥5 ?, 1 kHz
DAC output buffer ON,
Effective number of
bits
bits
CL ≤50 pF, RL ≥5 ?, 1 kHz
1. Guaranteed by characterization.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is -0.5dBFS with Fsampling=1 MHz.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 40. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
DAC_OUTx
12-bit
digital to
analog
converter
C
L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.22
Voltage reference buffer characteristics
(1)
Table 89. VREFBUF characteristics
Symbol
Parameter
Conditions
VSCALE = 000
Min
2.8
2.4
2.1
1.8
1.62
1.62
1.62
1.62
-
Typ
Max
3.6
3.6
3.6
3.6
2.80
2.40
2.10
1.80
-
Unit
3.3
VSCALE = 001
VSCALE = 010
VSCALE = 011
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
-
Normal mode
Degraded mode
Normal mode
-
-
VDDA
Analog supply voltage
-
-
-
-
2.5
2.048
1.8
1.5
V
-
-
-
-
-
-
VDDA
150 mV
−
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
-
-
-
-
VDDA
VDDA
VDDA
VDDA
VREFBUF
Voltage Reference
Buffer Output
_OUT
VDDA
150 mV
−
Degraded mode(2)
VDDA
150 mV
−
VDDA
150 mV
−
TRIM
CL
Trim step resolution
Load capacitor
-
-
-
-
-
±0.05
1
±0.2
1.50
%
0.5
uF
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
(1)
Table 89. VREFBUF characteristics (continued)
Symbol
esr
Parameter
Conditions
Min
Typ
Max
Unit
Equivalent Serial
Resistor of CL
-
-
-
-
-
2
?
Iload
Static load current
-
-
-
-
-
4
-
mA
I
load = 500 µA
Iload = 4 mA
200
100
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
ppm/V
-
ppm/
mA
Iload_reg
Load regulation
500 µA ≤ ILOAD ≤ 4 mA Normal Mode
-
-
50
-
-
Tcoeff
xVREFINT
+ 75
ppm/
°C
Tcoeff
Temperature coefficient −40 °C < TJ < +125 °C
-
DC
Power supply rejection
100KHz
-
-
-
-
-
-
-
-
-
-
60
40
-
-
-
-
-
PSRR
dB
µs
CL=0.5 µF
300
500
650
tSTART
Start-up time
CL=1 µF
CL=1.5 µF
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
IINRUSH
-
-
8
-
mA
µA
ILOAD = 0 µA
LOAD = 500 µA
ILOAD = 4 mA
-
-
-
-
-
-
15
16
32
25
30
50
VREFBUF
consumption from
VDDA
IDDA(VRE
I
FBUF)
1. Guaranteed by design.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
6.3.23
Temperature sensor characteristics
Table 90. Temperature sensor characteristics
Symbol
Parameter
Min Typ Max Unit
(1)
TL
VSENSE linearity with temperature
-
-
-
3
°C
mV/°C
V
Avg_Slope(2) Average slope
2
-
(3)
V30
Voltage at 30°C ± 5 °C
-
0.62
-
25.2
-
(1)
tstart_run
Startup time in Run mode (buffer startup)
ADC sampling time when reading the temperature
Sensor consumption
-
-
-
µs
(1)
tS_temp
9
-
(1)
Isens
0.18 0.31
3.8 6.5
µA
(1)
Isensbuf
Sensor buffer consumption
-
1. Guaranteed by design.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
2. Guaranteed by characterization.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 91. Temperature sensor calibration values
Symbol
Parameter
Memory address
Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V
TS_CAL1
0x1FF1 E820 -0x1FF1 E821
Temperature sensor raw data acquired value at
110 °C, VDDA=3.3 V
TS_CAL2
0x1FF1 E840 - 0x1FF1 E841
6.3.24
Temperature and V
monitoring
BAT
Table 92. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
26
4
-
KΩ
-
Ratio on VBAT measurement
Error on Q
-
-
Er(1)
–10
-
+10
%
µs
(1)
tS_vbat
ADC sampling time when reading VBAT input
High supply monitoring
9
-
-
-
-
-
VBAThigh
VBATlow
3.55
1.36
V
Low supply monitoring
-
1. Guaranteed by design.
Table 93. V
charging characteristics
BAT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBRS in PWR_CR3= 0
VBRS in PWR_CR3= 1
-
5
-
-
RBC
Battery charging resistor
KΩ
1.5
Table 94. Temperature monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
TEMPhigh
TEMPlow
High temperature monitoring
Low temperature monitoring
-
-
117
-
-
°C
–25
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
6.3.25
Voltage booster for analog switch
(1)
Table 95. Voltage booster for analog switch characteristics
Symbol
Parameter
Supply voltage
Condition
Min Typ Max Unit
VDD
-
1.62 2-6 3.6
V
Booster startup time
-
-
-
-
-
-
-
50
µs
tSU(BOOST)
1.62 V ≤ VDD ≤ 2.7 V
2.7 V < VDD < 3.6 V
125
250
Booster consumption
µA
IDD(BOOST)
1. Guaranteed by characterization results.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.26
Comparator characteristics
(1)
Table 96. COMP characteristics
Symbol
VDDA
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
-
1.62
3.3
3.6
Comparator input voltage
range
VIN
-
0
-
VDDA
V
(2)
VBG
Scaler input voltage
Scaler offset voltage
-
Refer to VREFINT
VSC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±5
0.2
0.8
140
2
±10
0.3
1
mV
µA
µs
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
Scaler static consumption
from VDDA
IDDA(SCALER)
tSTART_SCALER Scaler startup time
250
5
High-speed mode
Medium mode
Comparator startup time to
reach propagation delay
specification
tSTART
5
20
80
80
1.2
7
µs
Ultra-low-power mode
High-speed mode
Medium mode
15
50
0.5
2.5
50
0.5
2.5
±5
0
ns
µs
Propagation delay for
200 mV step with 100 mV
overdrive
Ultra-low-power mode
High-speed mode
Medium mode
tD
120
1.2
7
ns
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
µs
Ultra-low-power mode
Full common mode range
No hysteresis
Voffset
Comparator offset error
±20
-
mV
Low hysteresis
Medium hysteresis
High hysteresis
Static
10
20
30
400
-
Vhys
Comparator hysteresis
mV
nA
-
-
600
Ultra-low-
power mode
With 50 kHz
±100 mV overdrive
square signal
-
-
-
-
-
800
5
-
Static
7
Comparator consumption
from VDDA
With 50 kHz
±100 mV overdrive
square signal
I
DDA(COMP)
Medium mode
6
-
100
-
µA
Static
70
75
High-speed
mode
With 50 kHz
±100 mV overdrive
square signal
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 26: Embedded reference voltage.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
6.3.27
Operational amplifier characteristics
(1)
Table 97. OPAMP characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
Range
VDDA
CMIR
-
2
3.3
3.6
V
Common Mode Input
Range
-
0
-
-
-
VDDA
±1.5
25°C, no load on output
VIOFFSET
Input offset voltage
mV
All voltages and
temperature, no load
-
-
-
±2.5
-
ΔVIOFFSET
Input offset voltage drift
-
-
±3.0
μV/°C
Offset trim step at low
common input voltage
TRIMOFFSETP
-
-
1.1
1.1
1.5
1.5
TRIMLPOFFSETP
(0.1*VDDA
)
mV
μA
Offset trim step at high
common input voltage
TRIMOFFSETN
-
-
TRIMLPOFFSETN
(0.9*VDDA
)
ILOAD
Drive current
-
-
500
ILOAD_PGA
CLOAD
Drive current in PGA mode
Capacitive load
-
-
-
-
-
-
270
50
pF
dB
Common mode rejection
ratio
CMRR
PSRR
-
-
80
66
-
-
CLOAD ≤ 50pf /
Power supply rejection
ratio
RLOAD ≥ 4 kΩ(2) at 1 kHz,
Vcom=VDDA/2
50
4
dB
Gain bandwidth for high
supply range
GBW
SR
-
7.3
12.3
MHz
V/µs
Normal mode
-
-
3
-
-
Slew rate (from 10% and
90% of output voltage)
High-speed mode
30
AO
Open loop gain
Phase margin
-
-
59
-
90
55
129
-
dB
°
φm
GM
Gain margin
-
-
12
-
dB
DS12556 Rev 5
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
(1)
Table 97. OPAMP characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I
load=max or RLOAD=min(2)
,
,
VDDA
−100 mV
VOHSAT
High saturation voltage
-
-
Input at VDDA
mV
Iload=max or RLOAD=min(2)
Input at 0 V
VOLSAT
Low saturation voltage
-
-
-
100
3.2
CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kΩ(2)
,
,
0.8
mode
follower
configuration
Wake up time from OFF
state
tWAKEUP
µs
CLOAD ≤ 50pf,
RLOAD ≥ 4 kΩ(2)
follower
High
speed
-
0.9
2.8
configuration
-
-
-
-
-
-
-
-
-
-
-
-
2
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Non inverting gain value
Inverting gain value
-
8
-
16
PGA gain
-
−1
-
−3
-
−7
-
−15
10/10
30/10
70/10
PGA Gain=2
PGA Gain=4
PGA Gain=8
R2/R1 internal resistance
values in non-inverting
PGA mode(3)
PGA Gain=16
PGA Gain=-1
PGA Gain=-3
PGA Gain=-7
PGA Gain=-15
-
-
-
-
-
150/10
10/10
30/10
70/10
150/10
-
-
-
-
-
kΩ/
kΩ
Rnetwork
R2/R1 internal resistance
values in inverting PGA
mode(3)
Resistance variation (R1 or
R2)
Delta R
-
−15
-
15
%
Gain=2
Gain=4
Gain=8
Gain=16
-
-
-
-
GBW/2
GBW/4
GBW/8
GBW/16
-
-
-
-
PGA bandwidth for
different non inverting gain
PGA BW
MHz
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
(1)
Table 97. OPAMP characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
at
1 KHz
-
-
140
-
output loaded
with 4 kΩ
nV/√
Hz
en
Voltage noise density
at
10 KHz
55
-
Normal
mode
-
-
570
1000
no Load,
quiescent mode,
follower
OPAMP consumption from
VDDA
IDDA(OPAMP)
µA
High-
speed
mode
610
1200
1. Guaranteed by design, unless otherwise specified.
2. RLOAD is the resistive load connected to VSSA or to VDDA.
3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
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6.3.28
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 98 for DFSDM are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
PCLKx
DD
summarized in Table 22: General operating conditions, with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for
DFSDMx).
(1)
Table 98. DFSDM measured timing - 1.62-3.6 V
Symbol
fDFSDMCLK
Parameter
Conditions
Min
Typ
Max
Unit
DFSDM clock
1.62 V < VDD < 3.6 V
-
-
250
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 V < VDD < 3.6 V
20
-
-
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
20
-
-
-
-
(fDFSDMCLK/4)
fCKIN
(1/TCKIN
Input clock
frequency
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]0),
1.62 < VDD < 3.6 V
)
20
MHz
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]0),
2.7 < VDD < 3.6 V
20
-
-
(fDFSDMCLK/4)
Output clock
frequency
fCKOUT
1.62 < VDD < 3.6 V
1.62 < VDD < 3.6 V
-
-
20
55
Output clock
frequency duty
cycle
DuCyCKOUT
45
50
%
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DS12556 Rev 5
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Electrical characteristics (rev Y)
(1)
Table 98. DFSDM measured timing - 1.62-3.6 V (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
twh(CKIN)
twl(CKIN)
Input clock high
and low time
TCKIN/2 - 0.5
TCKIN/2
-
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Data input setup
time
tsu
4
-
-
ns
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Data input hold
time
th
0.5
-
-
-
Manchester mode
(SITP[1:0]=2,3),
Internal clock mode
(SPICKSEL[1:0]0),
1.62 < VDD < 3.6 V
Manchester data
TManchester period (recovered
clock period)
(CKOUTDIV+1)
* TDFSDMCLK
(2*CKOUTDIV)
* TDFSDMCLK
1. Guaranteed by characterization results.
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Figure 41. Channel transceiver timing diagrams
(SPICKSEL=0)
SITP = 00
tr
tf
twl
twh
tsu
th
tsu
th
SITP = 01
SPICKSEL=3
SPICKSEL=2
SPICKSEL=1
tr
tf
twl
twh
tsu
th
SITP = 0
SITP = 1
tsu
th
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V2
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Electrical characteristics (rev Y)
6.3.29
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 99 for DCMI are derived from
tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 22: General operating conditions, with the following
configuration:
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Capacitive load C=30 pF
Measurement points are done at CMOS levels: 0.5V
DD
(1)
Table 99. DCMI characteristics
Parameter
Symbol
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/frcc_c_ck
-
-
0.4
80
70
-
-
DCMI_PIXCLK Pixel clock input
MHz
%
DPixel
tsu(DATA)
th(DATA)
Pixel clock input duty cycle
30
1
Data input setup time
Data input hold time
1
-
tsu(HSYNC)
tsu(VSYNC)
th(HSYNC)
th(VSYNC)
ns
DCMI_HSYNC/DCMI_VSYNC input setup time
DCMI_HSYNC/DCMI_VSYNC input hold time
1.5
1
-
-
1. Guaranteed by characterization results.
Figure 42. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
th(HSYNC)
tsu(HSYNC)
th(HSYNC)
tsu(VSYNC)
tsu(DATA) th(DATA)
MS32414V2
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6.3.30
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 100 for LCD-TFT are derived
from tests performed under the ambient temperature, f
frequency and V supply
rcc_c_ck
DD
voltage summarized in Table 22: General operating conditions, with the following
configuration:
LCD_CLK polarity: high
LCD_DE polarity: low
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C=30 pF
Measurement points are done at CMOS levels: 0.5V
I/O compensation cell enabled
DD
(1)
Table 100. LTDC characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
2.7 V < VDD < 3.6 V,
20 pF
-
150
fCLK
LTDC clock output frequency
MHz
%
2.7 V < VDD < 3.6 V
-
-
133
90
1.62 V < VDD < 3.6 V
-
DCLK
LTDC clock output duty cycle
Clock High time, low time
Data output valid time
45
55
tw(CLKH),
tw(CLKL)
tw(CLK)/2−0.5 tw(CLK)/2+0.5
tv(DATA)
th(DATA)
-
0.5
-
Data output hold time
0
ns
tv(HSYNC),
tv(VSYNC),
tv(DE)
HSYNC/VSYNC/DE output valid
time
-
0.5
-
th(HSYNC),
HSYNC/VSYNC/DE output hold
time
0.5
th(VSYNC)
,
th(DE)
1. Guaranteed by characterization results.
180/334
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Electrical characteristics (rev Y)
Figure 43. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC)
tv(HSYNC)
LCD_HSYNC
th(DE)
tv(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
Pixel Pixel
1
Pixel
N
2
th(DATA)
HSYNCHorizontal
width back porch
Active width
Horizontal
back porch
One line
MS32749V1
Figure 44. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC)
tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
M lines data
VSYNC Vertical
width back porch
Active width
One frame
Vertical
back porch
MS32750V1
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6.3.31
Timer characteristics
The parameters given in Table 101 are guaranteed by design.
Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 101. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK
=
tTIMxCLK
1
-
200 MHz
tres(TIM)
Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK
=
tTIMxCLK
1
-
100 MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK/2
16/32
0
-
MHz
bit
f
TIMxCLK = 200 MHz
ResTIM
Timer resolution
Maximum possible count
with 32-bit counter
65536 ×
65536
tMAX_COUNT
tTIMxCLK
-
-
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 200 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2
.
182/334
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Electrical characteristics (rev Y)
6.3.32
Communications interfaces
I2C interface characteristics
2
2
The I C interface meets the timings requirements of the I C-bus specification and user
manual revision 03 for:
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s.
Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
2
The I C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0433 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
2
Table 102. Minimum i2c_ker_ck frequency in all I C modes
Symbol
Parameter
Condition
Min
Unit
Standard-mode
Fast-mode
2
Analog filter ON
8
9
DNF=0
Analog filter OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
MHz
Analog filter ON
DNF=0
17
16
Fast-mode Plus
Analog filter OFF
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions:
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but still present.
DD
The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load C
supported in Fm+, which is given by these formulas:
load
t
=0.8473xR xC
p load
r(SDA/SCL)
R
= (V -V
)/I
p(min)
DD OL(max) OL(max)
Where R is the I2C lines pull-up. Refer to Section 6.3.15: I/O port characteristics for
p
the I2C I/Os characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to Table 103 for the analog filter
characteristics:
(1)
Table 103. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes that
are suppressed by the analog filter
tAF
50(2)
260(3)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 104 for the SPI interface are
derived from tests performed under the ambient temperature, f frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
I/O compensation cell enabled
DD
HSLV activated when VDD ≤ 2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 104. SPI dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
90
1.62 V≤VDD≤3.6 V
Master mode
2.7 V≤VDD≤3.6 V
SPI1,2,3
133
100
Master mode
2.7 V≤VDD≤3.6 V
SPI4,5,6
Slave receiver mode
1.62 V≤VDD≤3.6 V
SPI1,2,3
fSCK
150
SPI clock frequency
-
-
MHz
1/tc(SCK)
Slave receiver mode
1.62 V≤VDD≤3.6 V
SPI4,5,6
100
Slave mode transmitter/full
duplex
31
25
2.7 V≤VDD≤3.6 V
Slave mode transmitter/full
duplex
1.62 V≤VDD≤3.6 V
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
2
1
-
-
-
-
Slave mode
ns
,
SCK high and low time Master mode
TPLCK - 2
TPLCK TPLCK + 2
tw(SCKL)
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
(1)
Table 104. SPI dynamic characteristics (continued)
Symbol
Parameter
Conditions
Master mode
Min
Typ
Max
Unit
tsu(MI)
tsu(SI)
th(MI)
1
2
2
1
9
0
-
-
-
-
Data input setup time
Slave mode
Master mode
Slave mode
-
-
-
Data input hold time
th(SI)
-
-
ta(SO)
tdis(SO)
Data output access time Slave mode
Data output disable time Slave mode
13
1
27
5
ns
Slave mode, 2.7 V≤VDD≤3.6 V
11.5
13
1
16
20
3
tv(SO)
Data output valid time Slave mode 1.62 V≤VDD≤3.6 V
Master mode
-
tv(MO)
th(SO)
th(MO)
-
Slave mode, 1.62 V≤VDD≤3.6 V
Data output hold time
9
0
-
-
Master mode
-
-
1. Guaranteed by characterization results.
Figure 45. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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(1)
Figure 46. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
(1)
Figure 47. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
186/334
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
I2S interface characteristics
Electrical characteristics (rev Y)
2
Unless otherwise specified, the parameters given in Table 105 for the I S interface are
derived from tests performed under the ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
I/O compensation cell enabled
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
2
(1)
Table 105. I S dynamic characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
I2S clock frequency
-
256x8K
256FS
MHz
Master data
-
-
64FS
fCK
MHz
Slave data
64FS
tv(WS)
th(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
-
3.5
0
1
1
1
1
4
2
-
-
-
tsu(WS)
th(WS)
Slave mode
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Master receiver
Slave receiver
Master receiver
Slave receiver
-
Data input setup time
Data input hold time
Data output valid time
Data output hold time
-
ns
-
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
20
3
-
-
9
0
-
1. Guaranteed by characterization results.
DS12556 Rev 5
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
2
(1)
Figure 48. I S slave timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 49. I S master timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
188/334
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SAI characteristics
Electrical characteristics (rev Y)
Unless otherwise specified, the parameters given in Table 106 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 22: General operating conditions, with the following
configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30 pF
Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
(1)
Table 106. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
SAI Main clock output
-
256 x 8K
256xFs
128xFs(3)
128xFs
MHz
Master data: 32 bits
Slave data: 32 bits
-
-
FCK
SAI clock frequency(2)
FS valid time
MHz
Master mode
-
-
15
20
2.7≤VDD≤3.6V
tv(FS)
Master mode
1.71≤VDD≤3.6V
tsu(FS)
th(FS)
FS setup time
FS hold time
Slave mode
Master mode
Slave mode
7
1
-
-
-
-
-
-
-
ns
1
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
0.5
1
Data input setup time
Data input hold time
3.5
2
Slave transmitter (after enable edge)
2.7≤VDD≤3.6V
-
17
tv(SD_B_ST)
Data output valid time
Data output hold time
Slave transmitter (after enable edge)
1.62≤VDD≤3.6V
-
7
-
20
-
th(SD_B_ST)
Slave transmitter (after enable edge)
ns
Master transmitter (after enable edge)
2.7≤VDD≤3.6V
17
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
1.62≤VDD≤3.6V
-
20
-
th(SD_A_MT)
Data output hold time Master transmitter (after enable edge)
7.55
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
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Figure 50. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
SAI_FS_X
t
h(FS)
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 51. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
MDIO characteristics
Table 107. MDIO Slave timing parameters
Symbol
Parameter
Management data clock
Min
Typ
Max
Unit
FsDC
-
-
8
-
40
20
-
MHz
td(MDIO) Management data input/output output valid time
tsu(MDIO) Management data input/output setup time
th(MDIO) Management data input/output hold time
7
4
1
ns
-
-
The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at
least 1.5 times the MDC frequency: F ≥ 1.5 * F
.
MDC
PCLK2
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Electrical characteristics (rev Y)
Figure 52. MDIO Slave timing diagram
tMDC)
td(MDIO)
tsu(MDIO)
th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 108 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, f
frequency and V
PCLK2
DD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
I/O compensation cell enabled
DD
HSLV activated when VDD ≤ 2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
(1)(2)
Table 108. Dynamic characteristics: SD / MMC characteristics, V =2.7V to 3.6V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
Clock low time
-
0
-
125
MHz
tW(CKL)
tW(CKH)
9.5
8.5
10.5
9.5
-
-
fPP =50 MHz
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tISU
tIH
Input setup time HS
Input hold time HS
2
1.5
3
-
-
-
-
-
-
f
PP ≥50 MHz
(3)
tIDW
Input valid window (variable window)
CMD, D outputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tOV
tOH
Output valid time HS
Output hold time HS
-
3.5
-
5
-
f
PP ≥50 MHz
2
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(1)(2)
Table 108. Dynamic characteristics: SD / MMC characteristics, V =2.7V to 3.6V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D inputs (referenced to CK) in SD default mode
2
-
-
-
-
tISUD
tIHD
Input setup time SD
Input hold time SD
fPP =25 MHz
ns
1.5
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
-
1
-
2
-
Output valid default time SD
Output hold default time SD
f
PP =25 MHz
ns
0
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
(1)(2)
Table 109. Dynamic characteristics: eMMC characteristics, V =1.71V to 1.9V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
Clock low time
-
0
-
120
MHz
tW(CKL)
tW(CKH)
9.5
8.5
10.5
9.5
-
-
fPP =50 MHz
PP ≥50 MHz
PP ≥50 MHz
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
1.5
2
-
-
-
-
-
-
f
(3)
tIDW
Input valid window (variable window)
3.5
CMD, D outputs (referenced to CK) in eMMC mode
tOV
tOH
Output valid time HS
Output hold time HS
-
5
-
7
-
f
3
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
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Electrical characteristics (rev Y)
Figure 53. SDIO high-speed mode
Figure 54. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
Figure 55. DDR mode
CAN (controller area network) interface
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCANx_TX and FDCANx_RX).
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USB OTG_FS characteristics
The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF
certified (for Full-speed device operation).
Table 110. USB OTG_FS electrical characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
USB transceiver operating
voltage
VDD33USB
-
3.0(1)
-
3.6
V
Embedded USB_DP pull-up
value during idle
RPUI
RPUR
ZDRV
-
-
900
1400
28
1250
2300
36
1600
3200
44
Embedded USB_DP pull-up
value during reception
Ω
Driver high
and low
Output driver impedance(2)
1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are
degraded in the 2.7 to 3.0 V voltage range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
USB OTG_HS characteristics
Unless otherwise specified, the parameters given in Table 111 for ULPI are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
rcc_c_ck
DD
conditions summarized in Table 22: General operating conditions, with the following
configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 20 pF
Measurement points are done at CMOS levels: 0.5V
.
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
(1)
Table 111. Dynamic characteristics: USB ULPI
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tSC
tHC
tSD
tHD
Control in (ULPI_DIR, ULPI_NXT) setup time
Control in (ULPI_DIR, ULPI_NXT) hold time
Data in setup time
-
-
-
-
0.5
6.5
2.5
0
-
-
-
-
-
-
-
-
Data in hold time
ns
2.7 V < VDD < 3.6 V,
CL = 20 pF
-
-
-
6.5
8.5
-
tDC/tDD Data/control output delay
6.5
13
1.7 V < VDD < 3.6 V,
CL = 15 pF
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
Figure 56. ULPI timing diagram
Clock
t
t
HC
SC
Control In
(ULPI_DIR,
ULPI_NXT)
t
t
HD
SD
data In
(8-bit)
t
t
DC
DC
Control out
(ULPI_STP)
t
DD
data out
(8-bit)
ai17361c
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 112, Table 113 and Table 114 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
f
frequency summarized in Table 22: General operating conditions, with the following
rcc_c_ck
configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 20 pF
Measurement points are done at CMOS levels: 0.5V
.
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 112 gives the list of Ethernet MAC signals for the SMI and Figure 57 shows the
corresponding timing diagram.
(1)
Table 112. Dynamics characteristics: Ethernet MAC signals for SMI
Symbol
Parameter
Min
Typ
Max
Unit
tMDC
MDC cycle time(2.5 MHz)
400
1
400
403
Td(MDIO) Write data valid time
tsu(MDIO) Read data setup time
th(MDIO) Read data hold time
1. Guaranteed by characterization results.
1.5
3
-
ns
8
-
-
0
-
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Figure 57. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
ETH_MDIO(I)
tsu(MDIO)
th(MDIO)
MS31384V1
Table 113 gives the list of Ethernet MAC signals for the RMII and Figure 58 shows the
corresponding timing diagram.
(1)
Table 113. Dynamics characteristics: Ethernet MAC signals for RMII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD) Receive data setup time
tih(RXD) Receive data hold time
tsu(CRS) Carrier sense setup time
tih(CRS) Carrier sense hold time
td(TXEN) Transmit enable valid delay time
2
3
-
-
-
-
2.5
2
-
-
-
ns
-
4
4.5
7.5
7
td(TXD)
Transmit data valid delay time
7
11.5
1. Guaranteed by characterization results.
Figure 58. Ethernet RMII timing diagram
RMII_REF_CLK
t
t
d(TXEN)
d(TXD)
RMII_TX_EN
RMII_TXD[1:0]
t
t
t
t
su(RXD)
su(CRS)
ih(RXD)
ih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 114 gives the list of Ethernet MAC signals for MII and Figure 59 shows the
corresponding timing diagram.
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Electrical characteristics (rev Y)
(1)
Table 114. Dynamics characteristics: Ethernet MAC signals for MII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD) Receive data setup time
tih(RXD) Receive data hold time
2
3
-
-
-
-
tsu(DV)
tih(DV)
tsu(ER)
tih(ER)
Data valid setup time
Data valid hold time
Error setup time
1.5
1
-
-
-
-
ns
1.5
0.5
4.5
7
-
-
Error hold time
-
-
td(TXEN) Transmit enable valid delay time
td(TXD) Transmit data valid delay time
6.5
7.5
11
15
1. Guaranteed by characterization results.
Figure 59. Ethernet MII timing diagram
MII_RX_CLK
t
t
t
t
t
t
su(RXD)
su(ER)
su(DV)
ih(RXD)
ih(ER)
ih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
t
t
d(TXEN)
d(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
6.3.33
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 115 and Table 116 for JTAG/SWD
are derived from tests performed under the ambient temperature, f frequency and
rcc_c_ck
V
supply voltage summarized in Table 22: General operating conditions, with the
DD
following configuration:
Output speed is set to OSPEEDRy[1:0] = 0x10
Capacitive load C=30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
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(1)
Table 115. Dynamics JTAG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7 V <VDD< 3.6 V
-
-
37
TCK clock
frequency
MHz
1/tc(TCK)
1.62 V <VDD< 3.6 V
-
-
27.5
TMS input
setup time
tisu(TMS)
tih(TMS)
tisu(TDI)
tih(TDI)
-
-
-
-
2
1
-
-
-
-
-
-
-
-
TMS input
hold time
TDI input
setup time
1.5
1
TDI input
hold time
ns
2.7 V <VDD< 3.6 V
1.62 V <VDD< 3.6 V
-
-
8
8
13.5
18
TDO output
valid time
tov (TDO)
TDO output
hold time
toh(TDO)
-
7
-
-
1. Guaranteed by characterization results.
(1)
Table 116. Dynamics SWD characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7 V <VDD< 3.6 V
-
-
71
SWCLK
clock
MHz
frequency
1/tc(SWCLK)
1.62 V <VDD< 3.6 V
-
-
55.5
SWDIO input
setup time
tisu(SWDIO)
tih(SWDIO)
-
-
2.5
1
-
-
-
-
SWDIO input
hold time
2.7 V <VDD< 3.6 V
1.62 V <VDD< 3.6 V
-
-
8.5
8.5
14
18
SWDIO
output valid
time
ns
tov (SWDIO)
SWDIO
output hold
time
toh(SWDIO)
-
8
-
-
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
Figure 60. JTAG timing diagram
tc(TCK)
TCK
TDI/TMS
TDO
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL)
tw(TCKH)
tov(TDO)
toh(TDO)
MSv40458V1
Figure 61. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL)
tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
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7
Electrical characteristics (rev V)
7.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at T = 25 °C and T = T (given by the
J
J
Jmax
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
7.1.2
7.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
J
DD
1.7 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
7.1.4
7.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 62.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 63.
Figure 62. Pin loading conditions
Figure 63. Pin input voltage
MCU pin
MCU pin
V
C =50 pF
IN
MS19011V2
MS19010V2
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Electrical characteristics (rev V)
7.1.6
Power supply scheme
Figure 64. Power supply scheme
VDD50USB
VDD33USB
VDD33USB
VDD50USB
USB
IOs
VSS
USB
regulator
VSS
VDDLDO
VCAP
Core domain (VCORE
)
Voltage
regulator
VDDLDO
VSS
D3 domain
(System
logic,
D1 domain
(CPU, peripherals,
RAM)
D2 domain
(peripherals,
RAM)
EXTI,
IO
logic
IOs
Peripherals,
RAM)
Flash
VDD
VSS
VDD domain
HSI, LSI,
VDD
CSI, HSI48,
HSE, PLLs
VBAT
charging
Backup domain
Backup
regulator
VBAT
1.2 to 3.6V
VSW
VBKP
VBAT
Power switch
Power switch
LSE, RTC,
Wakeup logic,
backup
Backup
RAM
BKUP
IOs
IO
logic
registers,
Reset
VREF
VDDA
VSS
VDDA
VSS
Analog domain
REF_BUF
ADC, DAC
VREF+
VREF-
OPAMP,
Comparator
VREF+
VREF-
VSSA
MSv46116V4
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution:
Each power supply pair (V /V , V
/V
...) must be decoupled with filtering ceramic
DD SS
DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
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device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
7.1.7
Current consumption measurement
Figure 65. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
7.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 117: Voltage characteristics,
Table 118: Current characteristics, and Table 119: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
(1)
Table 117. Voltage characteristics
Symbols
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
VDDX - VSS
−0.3
4.0
V
VDDLDO, VDDA, VDD33USB, VBAT
)
Min(VDD, VDDA
,
Input voltage on FT_xxx pins
VSS−0.3
VDD33USB, VBAT
)
V
+4.0(3)(4)
(2)
VIN
Input voltage on TT_xx pins
Input voltage on BOOT0 pin
Input voltage on any other pins
V
V
SS-0.3
VSS
4.0
9.0
4.0
V
V
V
SS-0.3
Variations between different VDDX power pins
of the same domain
|ΔVDDX
|
-
-
50
50
mV
mV
|VSSx-VSS
|
Variations between all the different ground pins
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 154: I/O current injection susceptibility for the
maximum allowed injected current values.
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Electrical characteristics (rev V)
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 118. Current characteristics
Symbols
Ratings
Max
Unit
ΣIVDD
ΣIVSS
IVDD
IVSS
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
620
620
100
100
20
IIO
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
140
140
mA
ΣI(PIN)
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
(3)(4)
IINJ(PIN)
Injected current on PA4, PA5
−0/0
±25
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5)
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 117: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 119. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
?65 to +150
°C
Maximum junction temperature
125
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7.3
Operating conditions
7.3.1
General operating conditions
Table 120. General operating conditions
Operating
Symbol
Parameter
Min
Typ
Max
Unit
conditions
-
VDD
Standard operating voltage
-
1.62(1)
1.62(1)
3.6
3.6
V
Supply voltage for the internal
regulator
VDDLDO
VDDLDO ≤ VDD
-
USB used
3.0
0
-
-
-
-
-
-
3.6
3.6
Standard operating voltage, USB
domain
VDD33USB
USB not used
ADC or COMP used
DAC used
1.62
1.8
2.0
1.8
OPAMP used
VREFBUF used
VDDA
Analog operating voltage
3.6
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
V
0
-
TT_xx I/O
BOOT0
−0.3
0
-
-
V
DD+0.3
9
VIN
I/O Input voltage
Min(VDD, VDDA
,
All I/O except BOOT0
and TT_xx
VDD33USB
+3.6V <
)
−0.3
-
5.5V(2)(3)
VOS3 (max frequency
200 MHz)
0.95
1.05
1.15
1.26
0.98
1.08
1.17
1.37
1.0
1.26
1.26
1.26
1.40
1.26
1.26
1.26
1.40
VOS2 (max frequency
300 MHz)
1.10
1.20
1.35
1.03
1.13
1.23
1.38
Internal regulator ON (LDO)
VOS1 (max frequency
400 MHz)
VOS0(4) (max
frequency 480 MHz(5)
)
VOS3 (max frequency
200 MHz)
VOS2 (max frequency
300 MHz)
VCORE
V
Regulator OFF: external VCORE
voltage must be supplied from external
regulator on two VCAP pins
VOS1 (max frequency
400 MHz)
VOS0 (max frequency
480 MHz(5)
)
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Electrical characteristics (rev V)
Table 120. General operating conditions (continued)
Operating
conditions
Symbol
Parameter
Min
Typ
Max
Unit
VOS3
-
-
-
-
-
-
-
-
-
-
-
-
-
200
300
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
-
fCPU
Arm® Cortex®-M7 clock frequency
-
400
-
480(5)
-
100
-
150
fHCLK
AHB clock frequency
APB clock frequency
-
200
-
240(5)
50(6)
75
-
-
fPCLK
MHz
-
100
-
120(5)
Maximum power dissipation
Low-power dissipation(7)
Suffix 6 version
–40
–40
–40
85
Ambient temperature for the suffix 6
version
TA
TJ
°C
°C
105
Junction temperature range
125
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. VOS0 is available only when the LDO regulator is ON.
5. TJmax = 105 °C.
6. Maximum APB clock frequency when at least one peripheral is enabled.
7. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.6:
Thermal characteristics).
Table 121. Supply voltage and maximum frequency configuration
Power scale
VCORE source
Max TJ (°C) Max frequency (MHz)
Min VDD (V)
VOS0
VOS1
LDO
LDO
LDO
LDO
LDO
LDO
105
125
125
125
105
105
480
400
300
200
N/A
N/A
1.7
1.62
1.62
1.62
1.62
1.62
VOS2
VOS3
SVOS4
SVOS5
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.2
VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
to
EXT
the VCAP pin. C
VCAP pins.
is specified in Table 122. Two external capacitors can be connected to
EXT
Figure 66. External capacitor C
EXT
C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
(1)
Table 122. VCAP operating conditions
Parameter
Symbol
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF(2)
< 100 m
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
7.3.3
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 123. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
Min
Max
Unit
0
10
0
∞
∞
∞
∞
∞
∞
tVDD
VDD fall time rate
VDDA rise time rate
tVDDA
µs/V
V
DDA fall time rate
VDDUSB rise time rate
DDUSB fall time rate
10
0
tVDDUSB
V
10
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
7.3.4
Embedded reset and power control block characteristics
The parameters given in Table 124 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 120: General
DD
operating conditions.
Table 124. Reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset temporization
after BOR0 released
(1)
tRSTTEMPO
-
-
377
-
µs
Rising edge(1)
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge in Run mode
1.62
1.58
2.04
1.95
2.34
2.25
2.63
2.54
1.90
1.81
2.05
1.96
2.19
2.10
2.35
2.25
2.49
2.39
2.64
2.55
2.78
2.69
1.67
1.62
2.10
2.00
2.41
2.31
2.70
2.61
1.96
1.86
2.10
2.01
2.26
2.15
2.41
2.31
2.56
2.45
2.71
2.61
2.86
2.76
1.71
1.68
2.15
2.06
2.47
2.37
2.78
2.68
2.01
1.91
2.16
2.06
2.32
2.21
2.47
2.37
2.62
2.51
2.78
2.68
2.94
2.83
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
VBOR1
VBOR2
VBOR3
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Programmable Voltage
Detector threshold 0
Programmable Voltage
Detector threshold 1
V
Programmable Voltage
Detector threshold 2
Programmable Voltage
Detector threshold 3
Programmable Voltage
Detector threshold 4
Programmable Voltage
Detector threshold 5
Programmable Voltage
Detector threshold 6
Hysteresis voltage of BOR
(unless BOR0) and PVD
Vhyst_BOR_PVD
Hysteresis in Run mode
-
-
-
100
-
mV
µA
BOR(2) (unless BOR0) and
PVD consumption from VDD
(1)
IDD_BOR_PVD
0.630
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 124. Reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.66
1.56
2.06
1.96
2.42
2.35
2.74
2.64
1.71
1.61
2.12
2.02
2.50
2.42
2.83
2.72
1.76
1.66
2.19
2.08
2.58
2.49
2.91
2.80
Analog voltage detector for
VDDA threshold 0
VAVM_0
Analog voltage detector for
VDDA threshold 1
VAVM_1
VAVM_2
VAVM_3
V
Analog voltage detector for
VDDA threshold 2
Analog voltage detector for
VDDA threshold 3
Hysteresis of VDDA voltage
detector
Vhyst_VDDA
IDD_PVM
-
-
-
-
100
-
mV
µA
µA
PVM consumption from
VDD(1)
-
-
-
0.25
2.5
Voltage detector
consumption on VDDA
IDD_VDDA
Resistor bridge
(1)
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 7.3.6: Supply current characteristics).
7.3.5
Embedded reference voltage
The parameters given in Table 125 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 120: General
DD
operating conditions.
Table 125. Embedded reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
-40°C < TJ < 125 °C,
VDD = 3.3 V
Internal reference voltages
1.180
1.216
1.255
V
ADC sampling time when
reading the internal reference
voltage
(1)(2)
tS_vrefint
-
-
4.3
-
-
µs
VBAT sampling time when
reading the internal VBAT
reference voltage
(1)(2)
tS_vbat
9
9
-
-
13.5
5
-
Reference Buffer
consumption for ADC
(2)
Irefbuf
V
DDA=3.3 V
23
15
µA
Internal reference voltage
spread over the temperature
range
(2)
ΔVREFINT
-40°C < TJ < 125 °C
mV
Average temperature
coefficient
Average temperature
coefficient
(2)
Tcoeff
-
-
20
10
70
ppm/°C
ppm/V
(2)
VDDcoeff
Average Voltage coefficient
3.0V < VDD < 3.6V
1370
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 125. Embedded reference voltage (continued)
Parameter Conditions Min Typ
Symbol
Max
Unit
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
-
-
25
50
75
-
-
-
%
-
-
-
-
VREFINT
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
Table 126. Internal reference voltage calibration values
Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
Symbol
7.3.6
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 65: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in analog input mode.
All peripherals are disabled except when explicitly mentioned.
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (f
) frequency and V
range” available in the reference manual).
rcc_c_ck
CORE
When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in the below tables are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 120: General operating
conditions.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 127. Typical and maximum current consumption in Run mode, code with data processing
(1)
running from ITCM, LDO regulator ON
Max(2)
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85
°C
Tj=105 Tj=125
°C
°C
480
400
400
300
300
216
200
200
180
168
144
60
148
125
110
84
226
-
307
-
390
-
-
VOS0
-
168
-
230
-
296
-
384
-
VOS1
VOS2
76
114
88
-
170
152
-
224
205
-
297
278
-
56
All
peripherals
disabled
53
47
71
64
63
55
36
24
348
-
121
116
115
109
92
83
439
-
164
159
158
153
135
126
550
-
223
218
217
212
194
185
-
43
Supply
current in
Run mode
40
IDD
VOS3
mA
35
16
25
12
480
400
400
300
300
200
200
226
190
167
135
122
85
VOS0
VOS1
-
256
-
327
-
416
-
536
-
All
peripherals
enabled
183
-
248
-
320
-
419
-
VOS2
VOS3
76
116
174
233
313
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. Guaranteed by characterization results, unless otherwise specified.
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 128. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON,
LDO regulator ON
Max(1)
Tj=85 Tj=105 Tj=125
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25
°C
°C
°C
°C
480
400
400
300
300
200
200
480
400
400
300
300
200
200
110
91
222
-
304
-
388
-
-
VOS0
-
381
-
80
162
-
228
-
294
-
All
VOS1
peripherals
disabled
61.5
55
111
-
168
-
222
-
294
-
VOS2
VOS3
VOS0
38.5
34.5
220
195
175
135
120
83
Supply
current in
Run mode
69
342
-
120
436
-
163
546
-
222
-
IDD
mA
-
264
-
336
-
424
-
544
-
All
VOS1
peripherals
enabled
180
-
246
-
318
-
418
-
VOS2
VOS3
75
114
173
232
312
1. Guaranteed by characterization results, unless otherwise specified.
Table 129. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF,
LDO regulator ON
Max(1)
Tj=105 Tj=125
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25°C Tj=85°C
°C
°C
VOS0
480
400
300
200
480
400
300
200
87
73
157
123
85
259
201
150
109
390
308
228
167
342
267
204
152
504
397
301
226
453
355
277
212
658
519
401
307
All
VOS1
VOS2
VOS3
VOS0
VOS1
VOS2
VOS3
peripherals
disabled
52
Supply
34
54
IDD
current in
mA
168
135
100
70
276
224
154
103
Run mode
All
peripherals
enabled
1. Guaranteed by characterization results, unless otherwise specified.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 130. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON
Max(1)
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=105 Tj=125
Tj=25°C Tj=85°C
°C
°C
D1
Standby,
D2
Standby,
D3 Run
64
2.7
1.1
4.7
-
12.9
-
19.0
27.5
Supply
current in
VOS3
8
-
-
IDD
batch
acquisition
mode
mA
D1 Stop,
D2 Stop, VOS3
D3 Run
64
8
5.4
3.8
18.4
-
83.7
-
132.6
-
202.4
-
1. Guaranteed by characterization results, unless otherwise specified.
Table 131. Typical and maximum current consumption in Stop, LDO regulator ON
Max(1)
Symbol
Parameter
Conditions
Typ
Unit
Tj=105
°C
Tj=125
°C
Tj=25°C Tj=85°C
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
1.27
1.96
2.78
1.27
2.25
3.07
0.91
1.42
2.02
0.91
1.70
2.31
0.49
0.76
1.10
0.15
0.22
0.35
6.3
9.4
42.5
57.4
75.9
42.5
57.9
76.4
30.4
41.1
54.4
30.4
41.5
54.9
16.5
22.2
29.3
4.3
72.0
94.6
121.3
72.0
95.2
122.0
51.2
67.3
86.6
51.2
67.9
87.1
28.0
36.6
46.9
7.3
-
Flash
memory
OFF, no
IWDG
-
D1 Stop,
D2 Stop,
D3 Stop
13.8
6.3
183.8
-
Flash
memory
ON, no
IWDG
9.8
-
14.1
4.6
184.8
-
Flash
memory
OFF, no
IWDG
6.8
-
D1 Stop,
IDD (Stop) D2 Standby,
D3 Stop
10.0
4.6
130.0
mA
-
Flash
memory
ON, no
IWDG
7.2
-
10.3
2.4
130.8
-
D1 Standby,
D2 Stop,
D3 Stop
3.6
-
71.2
-
Flash
memory
OFF, no
IWDG
5.3
0.7
D1 Standby,
D2 Standby,
D3 Stop
1.0
5.8
9.6
-
1.5
7.8
12.3
18.6
1. Guaranteed by characterization results, unless otherwise specified.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
(1)
Table 132. Typical and maximum current consumption in Sleep mode, LDO regulator
Max(2)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85 Tj=105 Tj=125
°C
°C
°C
480
400
400
300
300
200
200
480
400
400
300
300
200
200
50.7
43.4
35.3
27.9
24.6
18.8
16.5
136.0
115.0
97.7
74.9
67.3
52.8
47.1
96.3
87.8
66.5
-
253.4
245.5
181.3
-
366.1
357.9
265.8
-
VOS0
379.6
All
VOS1
peripherals
disabled
-
47.3
-
139.1
-
207.3
-
300.4
-
VOS2
VOS3
VOS0
Supply
current in
Sleep mode
33.6
194.7
169.0
138.2
-
106.4
348.5
325.9
251.3
-
160.9
464.4
441.7
338.4
-
236.1
IDD (Sleep)
mA
456.4
All
VOS1
peripherals
enabled
-
95.8
-
187.6
-
257.9
-
354.1
-
VOS2
VOS3
69.3
141.4
197.7
275.1
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
2. Guaranteed by characterization results, unless otherwise specified.
Table 133. Typical and maximum current consumption in Standby
Typ
Max(1)
Conditions
3 V
Symbol
Parameter
Unit
RTC
and
LSE
1.62 V 2.4 V 3 V 3.3 V
Backup
SRAM
Tj=25 Tj=85 Tj=105 Tj=125
°C
°C
°C
°C
OFF
ON
OFF
OFF
ON
1,92
3,33
2,43
3,82
1,95 2,06 2,16
4
18
47
-
40
83
-
90
Supply
current in
Standby
mode
3,44 3,6 3,79 8.2
141
IDD
µA
(Standby)
OFF
ON
2,57 2,77 2,95
4,05 4,31 4,55
-
-
-
-
ON
-
-
1. Guaranteed by characterization results, unless otherwise specified.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 134. Typical and maximum current consumption in V
mode
BAT
Conditions
Typ
Max(1)
3 V
RTC
Symbol Parameter
Unit
Backup
SRAM
and 1.2 V 2 V
LSE
3 V 3.4 V
Tj=25 Tj=85 Tj=105 Tj=125
°C
°C
°C
°C
OFF
ON
OFF 0,02 0,02 0,03 0,05
OFF 1,33 1,45 1,58 1,7
0,46 0,57 0,75 0,87
1,77 2,3 2,5
0,5
4,4
-
4,1
22
-
10
48
-
24
87
-
Supply
IDD
current in
µA
(VBAT)
OFF
ON
ON
ON
VBAT mode
2
-
-
-
-
1. Guaranteed by characterization results, unless otherwise specified.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 155: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
214/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
I/O dynamic current consumption
Electrical characteristics (rev V)
In addition to the internal peripheral current consumption (see Table 135: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
ISW = VDDx fSW CL
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the MCU supply voltage
DDx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
EXT
L
INT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
The I/O compensation cell is enabled.
f
is the CPU clock. f
= f
/4, and f
= f
/2.
rcc_c_ck
PCLK
rcc_c_ck
HCLK
rcc_c_ck
The given value is calculated by measuring the difference of current consumption
–
–
–
with all peripherals clocked off
with only one peripheral clocked on
f
= 480 MHz (Scale 0), f
= 400 MHz (Scale 1), f
= 300 MHz
rcc_c_ck
rcc_c_ck
rcc_c_ck
(Scale 2), f
= 200 MHz (Scale 3)
rcc_c_ck
The ambient operating temperature is 25 °C and V =3.3 V.
DD
DS12556 Rev 5
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 135. Peripheral current consumption in Run mode
Peripheral VOS0 VOS1 VOS2
MDMA 4.6 3.8 3.4
Bus
VOS3
Unit
3.2
1.9
DMA2D
JPGDEC
2.9
4.1
2.4
3.7
2.1
3.4
3.1
FLASH
17.0
0.9
15.0
1.1
14.0
0.9
12.0
0.8
FMC registers
FMC kernel
QUADSPI registers
QSPI kernel
SDMMC1 registers
SDMMC1 kernel
DTCM1
7.0
6.1
5.6
5.0
1.5
1.5
1.4
1.3
1.0
0.9
0.8
0.7
AHB3
8.2
7.2
6.7
6.0
1.3
1.2
0.9
0.9
7.9
6.8
6.0
5.3
DTCM2
8.3
7.2
6.4
5.7
ITCM
7.0
6.3
5.6
5.1
D1SRAM1
13.0
35.0
120
54.0
55.0
4.5
11.0
32.0
106
48.0
49.0
4.1
9.9
8.7
AHB3 bridge
Total AHB3
DMA1
29.0
96
26.0
86
µA/MHz
41.0
42.0
3.7
37.0
37.0
3.3
DMA2
ADC12 registers
ADC12 kernel
ART accelerator
ETH1MAC
1.0
0.7
0.4
0.6
4.1
3.7
3.2
2.9
17.0
0.1
15.0
0.1
14.0
0.1
12.0
0.1
ETH1TX
ETH1RX
0.1
0.1
0.1
0.1
AHB1
USB1 OTG registers
USB1 OTG kernel
USB1 ULPI
USB2 OTG registers
USB2 OTG kernel
USB2 ULPI
23.0
8.2
21.0
0.5
19.0
8.3
17.0
8.2
0.1
0.1
0.1
0.1
21.0
8.5
19.0
0.4
17.0
8.6
15.0
8.3
23.0
0.1
19.0
0.1
20.0
0.1
19.0
0.1
AHB1 bridge
Total AHB1
220
181
178
161
216/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 135. Peripheral current consumption in Run mode (continued)
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
DCMI
CRYPT
2.1
0.1
0.1
1.7
11.0
47.0
1.7
5.7
5.2
4.1
0.1
79
1.9
0.1
0.1
2.0
0.1
41.0
1.2
4.9
4.5
3.6
0.1
60
1.8
0.1
0.1
1.3
9.7
37.0
1.1
4.4
4.0
3.2
0.1
63
1.6
0.1
0.1
1.2
9.4
34.0
1.0
3.9
3.5
2.8
0.1
58
HASH
RNG registers
RNG kernel
SDMMC2 registers
SDMMC2 kernel
D2SRAM1
D2SRAM2
D2SRAM3
AHB2 bridge
Total AHB2
GPIOA
AHB2
1.5
1.2
0.8
1.1
0.7
0.8
0.9
1.1
0.9
0.8
0.7
0.4
6.6
1.7
0.4
2.3
0.1
22
1.3
1.0
0.7
1.0
0.7
0.8
0.8
1.0
0.9
0.8
0.8
0.5
5.9
1.5
0.3
1.9
0.1
20
1.3
1.0
0.7
1.0
0.7
0.7
0.8
1.0
0.8
0.7
0.7
0.4
5.3
1.2
0.5
1.7
0.1
19
1.1
0.9
0.6
0.9
0.6
0.6
0.7
0.9
0.7
0.7
0.6
0.3
4.8
1.2
0.2
1.5
0.1
16
GPIOB
GPIOC
µA/MHz
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
GPIOI
AHB4
GPIOJ
GPIOK
CRC
BDMA
ADC3 registers
ADC3 kernel
BKPRAM
AHB4 bridge
Total AHB4
WWDG1
0.7
81.0
0.3
87
0.5
36.0
0.2
41
0.5
33.0
0.1
38
0.2
30.0
0.1
34
LCD-TFT
APB3 bridge
Total APB3
APB3
µA/MHz
217/334
DS12556 Rev 5
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 135. Peripheral current consumption in Run mode (continued)
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
TIM2
TIM3
7.7
6.7
6.3
7.4
1.4
1.4
3.2
2.3
2.1
0.7
2.4
0.6
2.0
0.8
1.8
0.7
0.5
3.5
1.9
4.3
1.9
4.4
1.7
3.9
1.6
3.8
1.1
2.5
1.0
3.6
3.2
3.1
3.5
0.7
0.7
1.5
1.1
1.1
0.5
2.3
0.5
1.8
0.6
1.6
0.9
0.7
2.8
1.7
3.9
1.7
3.9
1.5
3.4
1.4
3.4
0.8
2.3
0.8
3.3
3.0
2.8
3.2
0.8
0.7
1.5
1.1
1.1
0.8
1.9
0.5
1.7
0.5
1.6
0.7
0.7
2.4
1.4
3.6
1.4
3.5
1.4
3.1
1.4
3.0
0.9
2.0
0.9
3.0
2.7
2.5
2.8
0.6
0.6
1.3
0.9
0.9
0.7
1.7
0.4
1.4
0.6
1.3
0.7
0.6
2.2
1.3
3.2
1.3
3.2
1.4
2.8
1.3
2.7
0.8
1.9
0.8
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
LPTIM1 registers
LPTIM1 kernel
WWDG2
SPI2 registers
SPI2 kernel
SPI3 registers
SPI3 kernel
SPDIFRX1 registers
SPDIFRX1 kernel
USART2 registers
USART2 kernel
USART3 registers
USART3 kernel
UART4 registers
UART4 kernel
UART5 registers
UART5 kernel
I2C1 registers
I2C1 kernel
I2C2 registers
APB1
µA/MHz
218/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 135. Peripheral current consumption in Run mode (continued)
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
I2C2 kernel
I2C3 registers
I2C3 kernel
2.3
0.8
2.4
0.7
0.1
3.6
1.8
4.0
2.0
3.9
6.4
2.7
0.1
0.2
3.3
19.0
9.1
0.1
142
11.0
10.0
3.6
0.1
4.5
0.1
2.0
0.9
2.1
0.6
5.5
4.1
4.1
2.0
0.5
1.3
2.2
1.0
1.9
0.5
0.1
1.3
1.8
3.3
1.6
3.4
5.5
2.4
0.1
0.3
2.9
17.0
7.9
0.1
108
5.0
4.7
2.5
0.1
3.0
0.1
1.7
0.8
1.7
0.5
2.5
2.0
1.9
1.8
0.4
1.1
1.9
0.8
1.8
0.6
3.2
1.2
1.6
3.0
1.6
3.1
5.0
2.3
0.1
0.3
2.6
15.0
6.9
0.1
102
4.5
4.3
2.7
0.1
3.1
0.1
1.6
0.7
1.6
0.5
2.3
1.8
1.8
1.6
0.4
1.1
1.7
0.8
1.6
0.5
0.1
1.0
1.4
2.8
1.4
2.8
4.5
1.9
0.1
0.2
2.3
13.0
6.4
0.1
88
HDMI-CEC registers
HDMI-CEC kernel
DAC12
USART7 registers
USART7 kernel
USART8 registers
USART8 kernel
CRS
APB1
(continued)
SWPMI registers
SWPMI kernel
OPAMP
MDIO
FDCAN registers
FDCAN kernel
APB1 bridge
Total APB1
TIM1
µA/MHz
4.0
3.8
2.9
0.1
3.4
0.1
1.4
0.6
1.5
0.3
2.1
1.7
1.6
1.3
0.5
1.0
TIM8
USART1 registers
USART1 kernel
USART6 registers
USART6 kernel
SPI1 registers
SPI1 kernel
APB2
SPI4 registers
SPI4 kernel
TIM15
TIM16
TIM17
SPI5 registers
SPI5 kernel
SAI1 registers
DS12556 Rev 5
219/334
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 135. Peripheral current consumption in Run mode (continued)
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
SAI1 kernel
SAI2 registers
SAI2 kernel
1.4
1.5
1.1
1.6
1.1
6.5
0.3
84.0
0.2
150
0.9
1.1
2.9
1.8
0.4
0.9
2.2
0.8
2.3
0.7
2.1
0.8
2.2
0.5
2.0
0.6
0.4
1.1
1.7
2.0
0.1
28
1.1
1.3
1.0
1.3
1.2
5.8
0.2
39.0
0.1
81
1.0
1.2
0.9
1.1
1.1
5.2
0.2
35.0
0.1
74
0.8
1.0
0.9
1.0
0.9
4.7
0.4
32.0
0.2
68
SAI3 registers
SAI3 kernel
APB2
(continued)
DFSDM1 registers
DFSDM1 kernel
HRTIM
APB2 bridge
Total APB2
SYSCFG
1.0
1.3
2.2
1.6
0.4
0.7
2.1
0.6
2.1
0.7
1.7
0.4
2.0
0.4
1.8
0.4
0.2
0.9
1.4
2.0
0.1
24.4
0.7
1.0
2.2
1.4
0.5
0.7
1.9
0.7
1.8
0.7
1.6
0.6
1.7
0.6
1.5
0.5
0.2
1.0
1.3
1.8
0.1
22.4
0.8
0.8
2.1
1.3
0.3
0.4
1.8
0.5
1.4
0.4
1.5
0.4
1.5
0.4
1.2
0.2
0.1
0.6
1.0
1.6
0.1
18.9
LPUART1 registers
LPUART1 kernel
SPI6 registers
SPI6 kernel
I2C4 registers
I2C4 kernel
µA/MHz
LPTIM2 registers
LPTIM2 kernel
LPTIM3 registers
LPTIM3 kernel
LPTIM4 registers
LPTIM4 kernel
LPTIM5 registers
LPTIM5 kernel
COMP12
APB4
VREF
RTC
SAI4 registers
SAI4 kernel
APB4 bridge
Total APB4
220/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
7.3.7
Wakeup time from low-power modes
The wakeup times given in Table 136 are measured starting from the wakeup event trigger
up to the first instruction executed by the CPU:
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
Table 136. Low-power mode wakeup timings
Typ(1)
Max(1)
Symbol
Parameter
Conditions
Unit
CPU
clock
cycles
(2)
tWUSLEEP
Wakeup from Sleep
-
9
10
VOS3, HSI, Flash memory in normal mode
4.4
12
15
23
39
39
30
36
38
47
68
68
5.6
15
20
28
71
47
37
50
48
61
75
77
VOS3, HSI, Flash memory in low-power
mode
VOS4, HSI, Flash memory in normal mode
VOS4, HSI, Flash memory in low-power
mode
VOS5, HSI, Flash memory in normal mode
VOS5, HSI, Flash memory in low-power
mode
(2)
tWUSTOP
Wakeup from Stop
VOS3, CSI, Flash memory in normal mode
VOS3, CSI, Flash memory in low power
mode
µs
VOS4, CSI, Flash memory in normal mode
VOS4, CSI, Flash memory in low-power
mode
VOS5, CSI, Flash memory in normal mode
VOS5, CSI, Flash memory in low-power
mode
VOS3, HSI, Flash memory in normal mode
VOS3, CSI, Flash memory in normal mode
2.6
26
3.4
36
tWUSTOP_
Wakeup from Stop,
clock kept running
(2)
KERON
Wakeup from Standby
mode
(2)
tWUSTDBY
-
390
500
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
DS12556 Rev 5
221/334
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.8
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 155: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 67.
(1)
Table 137. High-speed external user clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fHSE_ext
User external clock source frequency
4
25
50
MHz
VSW
(VHSEH ?VHSEL)
OSC_IN amplitude
0.7VDD
-
VDD
V
VDC
OSC_IN input voltage
VSS
7
-
-
0.3VSS
-
tW(HSE)
OSC_IN high or low time
ns
1. Guaranteed by design.
Figure 67. High-speed external clock source AC timing diagram
V
HSEH
90%
10 %
HSEL
V
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
I
L
OSC _I N
clock source
STM32
ai17528b
222/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 155: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 68.
(1)
Table 138. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
-
-
-
32.768
1000
VDDIOx
kHz
0.7 VDDIOx
VSS
-
-
V
0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
-
250
-
-
ns
1. Guaranteed by design.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 68. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
W(LSE)
t
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
I
L
OSC32_IN
clock source
STM32
ai17529b
DS12556 Rev 5
223/334
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 139. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 139. 4-48 MHz HSE oscillator characteristics
Operating
Symbol
Parameter
Min
Typ
Max
Unit
conditions(2)
F
Oscillator frequency
Feedback resistor
-
4
-
-
200
-
48
-
MHz
kΩ
RF
-
During startup(3)
-
4
V
DD=3 V, Rm=30 Ω
-
-
-
-
-
0.35
0.40
0.45
0.65
0.95
-
-
-
-
-
CL=10pF@4MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 8 MHz
IDD(HSE)
HSE current consumption
mA
VDD=3 V, Rm=30 Ω
CL=10 pF at 16 MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 Ω
CL=10 pF at 48 MHz
Gmcritmax
Maximum critical crystal gm
Start-up time
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 69). C and C are usually
L1
L2
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . The PCB and MCU pin capacitance must be included
L1
L2
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing C and C .
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
224/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 69. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
OSC_OUT
(1)
STM32
R
EXT
C
L2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 140. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 140. Low-speed external user clock characteristics
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
-
32.768
-
kHz
LSEDRV[1:0] = 00,
Low drive capability
-
-
-
-
-
-
-
290
390
550
900
-
-
-
LSEDRV[1:0] = 01,
Medium Low drive capability
LSE current
consumption
IDD
nA
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
LSEDRV[1:0] = 00,
Low drive capability
0.5
0.75
1.7
LSEDRV[1:0] = 01,
Medium Low drive capability
-
Maximum critical crystal
gm
Gmcritmax
µA/V
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
-
-
2.7
-
(3)
tSU
Startup time
VDD is stabilized
2
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
DS12556 Rev 5
225/334
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 70. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC32_IN
Bias
controlled
gain
32.768 kHz
resonator
RF
OSC32_OUT
STM32
CL2
ai17531c
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
7.3.9
Internal clock source characteristics
The parameters given in Table 141 to Table 144 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 120: General
DD
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 141. HSI48 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD=3.3 V,
TJ=30 °C
fHSI48
HSI48 frequency
47.5(1)
-
48
48.5(1) MHz
TRIM(2)
USER trimming step
USER TRIMMING Coverage
Duty Cycle
-
± 32 steps
-
0.175
-
-
%
%
%
%
USER TRIM
COVERAGE(3)
±4.79 ±5.60
DuCy(HSI48)(2)
45
-
-
55
3.5
Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
ACCHSI48_REL(3)(4)
TJ=-40 to 125 °C
–4.5
VDD=3 to 3.6 V
-
-
-
-
0.025
0.05
2.1
0.05
0.1
HSI48 oscillator frequency drift with
VDD
∆
VDD(HSI48)(3)
%
(5)
VDD=1.62 V to 3.6 V
(2)
tsu(HSI48)
HSI48 oscillator start-up time
-
-
4.0
µs
(2)
IDD(HSI48)
HSI48 oscillator power consumption
350
400
µA
Next transition jitter
Accumulated jitter on 28 cycles(6)
NT jitter
PT jitter
-
-
-
-
± 0.15
± 0.25
-
-
ns
ns
Paired transition jitter
Accumulated jitter on 56 cycles(6)
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization.
4. ΔfHSI = ACCHSI48_REL + ΔVDD
.
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5. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) /
Freq(1.62V).
6. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
(1)
Table 142. HSI oscillator characteristics
Symbol
Parameter
HSI frequency
Conditions
Min
Typ
Max
Unit
fHSI
VDD=3.3 V, TJ=30 °C
63.7(2)
64
64.3(2)
MHz
Trimming is not a multiple
of 32
-
0.24
−1.8
−0.8
0.32
Trimming is 128, 256 and
384
−5.2
−1.4
-
-
Trimming is 64, 192, 320
and 448
TRIM
HSI user trimming step
%
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
−0.6
−0.25
-
DuCy(HSI) Duty Cycle
-
45
-
-
55
%
%
HSI oscillator frequency drift over
ΔVDD (HSI)
VDD=1.62 to 3.6 V
−0.12
0.03
VDD (reference is 3.3 V)
TJ=-20 to 105 °C
−1(3)
-
-
1(3)
1(3)
2
HSI oscillator frequency drift over
temperature (reference is 64 MHz)
ΔTEMP (HSI)
%
TJ=−40 to TJmax °C
−2(3)
tsu(HSI)
HSI oscillator start-up time
-
-
-
-
1.4
4
µs
µs
µA
tstab(HSI) HSI oscillator stabilization time
DD(HSI) HSI oscillator power consumption
at 1% of target frequency
-
8
I
300
400
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
4 MHz low-power internal RC oscillator (CSI)
Table 143. CSI oscillator characteristics
(1)
Symbol
Parameter
CSI frequency
Conditions
Min
Typ
Max
Unit
fCSI
TRIM
VDD=3.3 V, TJ=30 °C
3.96(2)
4
0.35
-
4.04(2) MHz
Trimming step
Duty Cycle
-
-
45
-
-
%
%
DuCy(CSI)
-
55
TJ = 0 to 85 °C
TJ = −40 to 125 °C
−3.7(3) 4.5(3)
CSI oscillator frequency drift over
temperature
ΔTEMP (CSI)
DVDD (CSI)
%
%
-
−11(3)
7.5(3)
CSI oscillator frequency drift over
VDD
VDD = 1.62 to 3.6 V
-
−0.06
0.06
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Table 143. CSI oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tsu(CSI)
CSI oscillator startup time
-
-
1
2
µs
CSI oscillator stabilization time
tstab(CSI)
IDD(CSI)
-
-
-
-
-
4
cycle
µA
(to reach ±3% of fCSI
)
CSI oscillator power consumption
23
30
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Low-speed internal (LSI) RC oscillator
Table 144. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V, TJ = 25 °C
31.4(1)
32
32.6(1)
TJ = –40 to 110 °C, VDD = 1.62 to
3.6 V
29.76(2)
-
-
33.6(2)
fLSI
LSI frequency
kHz
TJ = –40 to 125 °C, VDD = 1.62 to
3.6 V
29.4
-
33.6
LSI oscillator
startup time
(3)
tsu(LSI)
-
80
130
LSI oscillator
stabilization
time (5% of
final value)
µs
(3)
tstab(LSI)
-
-
-
120
130
170
280
LSI oscillator
power
(3)
IDD(LSI)
-
nA
consumption
1. Guaranteed by test in production.
2. Guaranteed by characterization results.
3. Guaranteed by design.
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7.3.10
PLL characteristics
The parameters given in Table 145 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 120: General operating conditions.
DD
(1)
Table 145. PLL characteristics (wide VCO frequency range)
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
2
10
1.5
1.5
1.5
1.5
192
-
-
16
MHz
%
PLL input clock duty cycle
-
-
90
VOS0
VOS1
VOS2
VOS3
-
-
480(2)
400(2)
300(2)
200(2)
960
-
fPLL_P_OUT PLL multiplier output clock P
-
MHz
µs
-
fVCO_OUT
PLL VCO output
PLL lock time
-
Normal mode
50(3)
150(3)
tLOCK
Sigma-delta mode
(CKIN ≥8 MHz)
-
-
-
-
-
-
58(3)
134
134
76
166(3)
VCO =
192 MHz
-
-
-
-
-
VCO =
200 MHz
Cycle-to-cycle jitter(4)
-
±ps
VCO =
400 MHz
VCO =
800 MHz
39
VCO =
800 MHz
Normal mode
±0.7
Jitter
Long term jitter
%
Sigma-delta
mode (CKIN =
16 MHz)
VCO =
800 MHz
-
±0.8
-
VDDA
VCORE
VDDA
-
-
-
-
590
720
180
280
1500
VCO freq =
836 MHz
-
600
-
(3)
IDD(PLL)
PLL power consumption on VDD
µA
VCO freq =
192 MHz
VCORE
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation (480 MHz for VOS0, 400 MHz for VOS1,
300 MHz for VOS2, 200 MHz for VOS3).
3. Guaranteed by characterization results.
4. Integer mode only.
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Table 146. PLL characteristics (medium VCO frequency range)
Parameter Conditions Min
PLL input clock
Symbol
Typ
Max Unit
-
1
-
-
-
-
-
-
2
MHz
%
fPLL_IN
PLL input clock duty cycle
-
VOS1
10
1.17
1.17
1.17
150
-
90
210
210
200
420
PLL multiplier output clock P, Q,
R
fPLL_OUT
VOS2
MHz
µs
VOS3
fVCO_OUT
tLOCK
PLL VCO output
PLL lock time
-
Normal mode
Sigma-delta mode
60(2) 100(2)
forbidden
VCO =
150 MHz
-
-
-
-
-
-
-
145
-
-
-
-
-
-
-
VCO =
300 MHz
91
64
Cycle-to-cycle jitter(3)
-
±ps
VCO =
400 MHz
VCO =
420 MHz
Jitter
63
VCO =
150 MHz
55
fPLL_OUT
50 MHz
=
Period jitter
±-ps
%
VCO =
400 MHz
30
VCO =
400 MHz
Long term jitter
Normal mode
±0.3
VDD
VCORE
VDD
-
-
-
-
440
530
180
200
1150
VCO freq =
420MHz
-
500
-
I(PLL)(2)
PLL power consumption on VDD
µA
VCO freq =
150MHz
VCORE
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
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7.3.11
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 125 °C unless otherwise specified.
J
The devices are shipped to customers with the Flash memory erased.
Table 147. Flash memory characteristics
Symbol
Parameter
Conditions
Write / Erase 8-bit mode
Min
Typ
Max
Unit
-
-
-
-
6.5
11.5
20
-
-
-
-
Write / Erase 16-bit mode
Write / Erase 32-bit mode
Write / Erase 64-bit mode
IDD
Supply current
mA
35
Table 148. Flash memory programming
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
Program parallelism x 8
-
-
-
-
-
-
-
-
-
-
-
290
180
130
100
2
580(2)
360
µs
260
Word (266 bits) programming
time
tprog
200
4
tERASE128KB Sector (128 KB) erase time
1.8
3.6
13
8
26
16
12
10
s
tME
Mass erase time
6
5
Program parallelism x 16
1.62
1.8
-
-
3.6
3.6
Vprog
Programming voltage
V
Program parallelism x 32
Program parallelism x 64
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
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Table 149. Flash memory endurance and data retention
Value
Min(1)
Symbol
Parameter
Conditions
Unit
NEND
tRET
Endurance
Data retention
TJ = –40 to +125 °C (6 suffix versions)
1 kcycle at TA = 85 °C
kcycles
Years
10
30
20
10 kcycles at TA = 55 °C
1. Guaranteed by characterization results.
7.3.12
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 150. They are based on the EMS levels and classes
defined in application note AN1709.
Table 150. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
Voltage limits to be applied on any I/O pin to induce
a functional disturbance
VFESD
3B
5A
V
DD = 3.3 V, TA = +25 °C,
UFBGA240, frcc_c_ck
400 MHz, conforms to
IEC 61000-4-2
=
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
VFTB
As a consequence, it is recommended to add a serial resistor (1 k?) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
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Electrical characteristics (rev V)
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 151. EMI characteristics
Max vs.
Monitored
frequency band
[fHSE/fCPU
]
Symbol Parameter
Conditions
Unit
8/400 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
11
6
dBµV
-
VDD = 3.6 V, TA = 25 °C, UFBGA240 package,
conforming to IEC61967-2
SEMI
Peak level
12
7
2.5
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7.3.13
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 152. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Packages
Class
Unit
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
001
All
1C
1000
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA =+25 °C conforming to
ANSI/ESDA/JEDEC JS-
002
All
C1
250
1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 153. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latchup class
TA =+25 °C conforming to JESD78
II level A
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7.3.14
I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
DD
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 154. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
PJ12, PB4
5
0
0
5
0
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11
NA
0
IINJ
mA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PH4, PH5, BOOT0
All other I/Os
NA
1. Guaranteed by characterization.
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7.3.15
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 155: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 120: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Table 155. I/O static characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I/O input low level voltage except
BOOT0
(1)
-
-
0.3VDD
I/O input low level voltage except
BOOT0
0.4VDD−0.
1(2)
VIL
1.62 V<VDDIOx<3.6 V
-
-
-
V
0.19VDD
+
BOOT0 I/O input low level voltage
-
0.1(2)
I/O input high level voltage except
BOOT0
(1)
0.7VDD
-
-
-
-
-
I/O input high level voltage except
BOOT0(3)
0.47VDD+0.
25(2)
VIH
1.62 V<VDDIOx<3.6 V
-
-
V
BOOT0 I/O input high level
voltage(3)
0.17VDD+0.
6(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis
-
250
(2)
VHYS
1.62 V< VDDIOx <3.6 V
mV
BOOT0 I/O input hysteresis
-
-
200
-
-
(9)
0< VIN ≤ Max(VDDXXX
)
+/-250
FT_xx Input leakage current(2)
Max(VDDXXX) < VIN ≤ 5.5 V
-
-
-
-
-
-
1500
(5)(6)(9)
(9)
0< VIN ≤ Max(VDDXXX
)
+/- 350
5000(7)
(4)
FT_u IO
Ileak
Max(VDDXXX) < VIN ≤ 5.5 V
nA
(5)(6)(9)
(9)
TT_xx Input leakage current
0< VIN ≤ Max(VDDXXX
0< VIN ≤ VDDIOX
)
-
-
-
-
+/-250
15
VPP (BOOT0 alternate function)
VDDIOX < VIN ≤ 9 V
35
Weak pull-up equivalent
resistor(8)
RPU
VIN=VSS
30
40
50
kΩ
pF
Weak pull-down equivalent
resistor(8)
(9)
RPD
CIO
VIN=VDD
-
30
-
40
5
50
-
I/O pin capacitance
1. Compliant with CMOS requirements.
2. Guaranteed by design.
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max)
5. All FT_xx IO except FT_lu, FT_u and PC3.
.
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6. VIN must be less than Max(VDDXXX) + 3.6 V.
7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 71.
Figure 71. V /V for all I/Os except BOOT0
IL IH
3
2.5
2
TLL requirement: VIHmin = 2 V
1.5
1
TLL requirement: VILmin = 0.8 V
0.5
0
2.8
1.6
1.8
2
2.2
2.4
2.6
3
3.2
3.4
3.6
MSv46121V3
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 7.2. In particular:
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 118).
VDD
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 118).
VSS
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Output voltage levels
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Unless otherwise specified, the parameters given in Table 156: Output voltage
characteristics for all I/Os except PC13, PC14, PC15 and PI8 and Table 157: Output voltage
characteristics for PC13, PC14, PC15 and PI8 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 120: General
DD
operating conditions. All I/Os are CMOS and TTL compliant.
(1)
Table 156. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO=8 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO=-8 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=8 mA
(3)
VOL
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=-8 mA
(3)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
V
IIO=20 mA
(3)
VOL
Output low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
1.3
-
2.7 V≤ VDD ≤3.6 V
IIO=-20 mA
(3)
VOH
VDD−1.3
2.7 V≤ VDD ≤3.6 V
IIO=4 mA
(3)
VOL
-
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO=-4 mA
1.62 V≤VDD<3.6 V
(3)
VOH
VDD−-0.4
IIO= 20 mA
-
-
0.4
0.4
2.3 V≤ VDD≤3.6 V
Output low level voltage for an FTf
I/O pin in FM+ mode
(3)
VOLFM+
IIO= 10 mA
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 117:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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(1)
Table 157. Output voltage characteristics for PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO=3 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO=-3 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=3 mA
(3)
VOL
-
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=-3 mA
(2)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
IIO=1.5 mA
(2)
VOL
Output low level voltage
Output high level voltage
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO=-1.5 mA
(2)
VOH
VDD−0.4
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 117:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
(1)(2)
Table 158. Output timing characteristics (HSLV OFF)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
3
12
(3)
Fmax
Maximum frequency
MHz
3
16
4
00
16.6
33.3
13.3
25
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
10
20
60
15
80
(3)
Fmax
Maximum frequency
15
110
20
01
5.2
10
Output high to low level
fall time and output low
to high level rise time
4.2
7.5
2.8
5.2
tr/tf(4)
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Electrical characteristics (rev V)
(1)(2)
Table 158. Output timing characteristics (HSLV OFF)
(continued)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 Vv
C=50 pF, 2.7 V≤VDD≤3.6 Vv
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 Vv
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85
35
110
40
(3)
Fmax
Maximum frequency
MHz
166
100
3.8
6.9
2.8
5.2
1.8
3.3
100
50
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
133
66
(3)
Fmax
Maximum frequency
220
85
11
3.3
6.6
2.4
4.5
1.5
2.7
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
1. Guaranteed by design.
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
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Output buffer timing characteristics (HSLV option enabled)
(1)
Table 159. Output timing characteristics (HSLV ON)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
10
10
11
(2)
Fmax
Maximum frequency
MHz
00
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
9
ns
MHz
ns
6.6
50
58
66
6.6
4.8
3
(2)
Fmax
Maximum frequency
01
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
55
80
133
5.8
4
(2)
Fmax
Maximum frequency
MHz
ns
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
2.4
60
90
175
5.3
3.6
1.9
(2)
Fmax
Maximum frequency
MHz
ns
11
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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Electrical characteristics (rev V)
7.3.16
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 155: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 160 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 120: General operating conditions.
Table 160. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Weak pull-up equivalent
resistor(1)
(2)
RPU
VIN = VSS
30
40
50
?
(2)
VF(NRST)
NRST Input filtered pulse
1.71 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
-
-
50
-
300
ns
(2)
VNF(NRST)
NRST Input not filtered pulse
1.62 V < VDD < 3.6 V 1000
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 72. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 155. Otherwise the reset is not taken into account by the device.
7.3.17
FMC characteristics
Unless otherwise specified, the parameters given in Table 161 to Table 174 for the FMC
interface are derived from tests performed under the ambient temperature, f
frequency
HCLK
and V supply voltage conditions summarized in Table 120: General operating conditions,
DD
with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1.
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Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
Asynchronous waveforms and timings
Figure 73 through Figure 75 represent asynchronous waveforms and Table 161 through
Table 168 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
Capacitive load C = 30 pF
L
In all timing tables, the T
is the f
clock period.
KERCK
mc_ker_ck
Figure 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Electrical characteristics (rev V)
(1)
Table 161. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
3Tfmc_ker_ck–1
0
3Tfmc_ker_ck+1
0.5
2Tfmc_ker_ck –1
2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high
hold time
th(NE_NOE)
tv(A_NE)
0
-
-
0.5
-
FMC_NEx low to FMC_A valid
Address hold time after
FMC_NOE high
th(A_NOE)
0
Data to FMC_NEx high setup
time
ns
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
11
11
0
-
-
-
-
Data to FMC_NOEx high setup
time
Data hold time after FMC_NOE
high
Data hold time after FMC_NEx
high
0
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV) FMC_NADV low time
-
-
0
Tfmc_ker_ck+1
1. Guaranteed by characterization results.
Table 162. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tw(NOE)
tw(NWAIT)
FMC_NE low time
FMC_NOE low time
FMC_NWAIT low time
7Tfmc_ker_ck+1
5Tfmc_ker_ck–1
Tfmc_ker_ck– 0.5
7Tfmc_ker_ck+1
5Tfmc_ker_ck +1
-
ns
FMC_NWAIT valid before FMC_NEx
high
tsu(NWAIT_NE)
th(NE_NWAIT)
4Tfmc_ker_ck +11
3Tfmc_ker_ck+11.5
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Figure 74. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Electrical characteristics (rev V)
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Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
3Tfmc_ker_ck –1
Tfmc_ker_ck
3Tfmc_ker_ck
Tfmc_ker_ck+1
Tfmc_ker_ck+0.5
Tfmc_ker_ck –0.5
FMC_NWE high to FMC_NE high
hold time
th(NE_NWE)
tv(A_NE)
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Tfmc_ker_ck
-
2
FMC_NEx low to FMC_A valid
-
Address hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
-
-
ns
FMC_NEx low to FMC_BL valid
0.5
-
FMC_BL hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
Data to FMC_NEx low to Data valid
-
Tfmc_ker_ck+ 2.5
th(Data_NWE) Data hold time after FMC_NWE high
Tfmc_ker_ck+0.5
-
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
-
0
Tfmc_ker_ck+ 1
1. Guaranteed by characterization results.
Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
8Tfmc_ker_ck+1
tw(NWE)
FMC_NWE low time
6Tfmc_ker_ck –1.5
6Tfmc_ker_ck+0.5
FMC_NWAIT valid before FMC_NEx
high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
5Tfmc_ker_ck+13
4Tfmc_ker_ck+13
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Figure 75. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
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Electrical characteristics (rev V)
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Table 165. Asynchronous multiplexed PSRAM/NOR read timings
Symbol Parameter Min
FMC_NE low time 4Tfmc_ker_ck –1
Max
Unit
tw(NE)
4Tfmc_ker_ck +1
2Tfmc_ker_ck
+0.5
tv(NOE_NE)
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2Tfmc_ker_ck
Tfmc_ker_ck –1
0
ttw(NOE)
Tfmc_ker_ck +1
-
FMC_NOE high to FMC_NE high hold
time
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
0.5
0.5
0
ns
Tfmc_ker_ck –0.5
Tfmc_ker_ck +1
FMC_AD(address) valid hold time
after FMC_NADV high)
th(AD_NADV)
th(A_NOE)
Tfmc_ker_ck +0.5
Tfmc_ker_ck –0.5
-
-
Address hold time after FMC_NOE
high
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NE)
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
11
11
0
-
-
-
th(Data_NOE)
0
-
1. Guaranteed by characterization results.
(1)(2)
Table 166. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
8Tfmc_ker_ck
tw(NOE)
FMC_NWE low time
5Tfmc_ker_ck –1.5
5Tfmc_ker_ck +0.5
FMC_NWAIT valid before
FMC_NEx high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
4Tfmc_ker_ck +11
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
3Tfmc_ker_ck +11.5
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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(1)
Table 167. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
4Tfmc_ker_ck –1
Tfmc_ker_ck –1
4Tfmc_ker_ck
Tfmc_ker_ck +0.5
2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5
FMC_NWE high to FMC_NE high hold
time
th(NE_NWE)
Tfmc_ker_ck –0.5
-
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
0
0.5
0
Tfmc_ker_ck
Tfmc_ker_ck + 1
ns
FMC_AD(adress) valid hold time after
FMC_NADV high)
th(AD_NADV)
th(A_NWE)
Tfmc_ker_ck +0.5
-
-
-
Address hold time after FMC_NWE
high
Tfmc_ker_ck +0.5
FMC_BL hold time after FMC_NWE
high
th(BL_NWE)
Tfmc_ker_ck – 0.5
tv(BL_NE)
FMC_NEx low to FMC_BL valid
FMC_NADV high to Data valid
-
-
0.5
tv(Data_NADV)
th(Data_NWE)
Tfmc_ker_ck +2
-
Data hold time after FMC_NWE high
Tfmc_ker_ck +0.5
1. Guaranteed by characterization results.
(1)(2)
Table 168. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9Tfmc_ker_ck –1
9Tfmc_ker_ck
tw(NWE)
FMC_NWE low time
7Tfmc_ker_ck –0.5
7Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_NEx
high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
5Tfmc_ker_ck +11
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
4Tfmc_ker_ck +11.5
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Synchronous waveforms and timings
Figure 76 through Figure 79 represent synchronous waveforms and Table 169 through
Table 172 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
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Electrical characteristics (rev V)
In all the timing tables, the Tfmc_ker_ck is the f
FMC_CLK maximum values:
clock period, with the following
mc_ker_ck
For 2.7 V<V <3.6 V, FMC_CLK = 125 MHz at 20 pF
DD
For 1.8 V<V <1.9 V, FMC_CLK = 100 MHz at 20 pF
DD
For 1.62 V<V <1.8 V, FMC_CLK = 100 MHz at 15 pF
DD
Figure 76. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
su(ADV-CLKH)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
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(1)
Table 169. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
1
td(CLKL-NExL)
td(CLKH_NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
-
Tfmc_ker_ck+0.5
-
-
0
-
1
FMC_CLK low to FMC_NADV high
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2.5
FMC_CLK high to FMC_Ax invalid
(x=16…25)
td(CLKH-AIV)
Tfmc_ker_ck
-
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
1.5
ns
Tfmc_ker_ck –0.5
-
3
-
-
0
FMC_A/D[15:0] valid data before FMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
2
1
-
-
FMC_A/D[15:0] valid data after FMC_CLK
high
tsu(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Electrical characteristics (rev V)
Figure 77. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
FMC_A[25:16]
t
d(CLKH-NWEH)
d(CLKL-NWEL)
FMC_NWE
t
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
d(CLKL-Data)
d(CLKL-ADV)
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKH-NBLH)
FMC_NBL
MS32758V1
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(1)
Table 170. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
2Tfmc_ker_ck –1
1
tw(CLK)
FMC_CLK period, VDD = 2.7 to 3.6 V
-
1
-
td(CLKL-NExL)
td(CLKH-NExH)
FMC_CLK low to FMC_NEx low (x =0..2)
-
FMC_CLK high to FMC_NEx high
(x = 0…2)
T
fmc_ker_ck +0.5
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
1.5
-
0
FMC_CLK low to FMC_Ax valid
(x =16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2
-
FMC_CLK high to FMC_Ax invalid
(x =16…25)
Tfmc_ker_ck
Ns
td(CLKL-NWEL)
t(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
FMC_CLK low to to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
1.5
-
Tfmc_ker_ck +0.5
-
2.5
-
0
FMC_A/D[15:0] valid data after FMC_CLK
low
td(CLKL-DATA)
-
2.5
td(CLKL-NBLL)
td(CLKH-NBLH)
tsu(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
-
2
-
Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Electrical characteristics (rev V)
Figure 78. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
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(1)
Table 171. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
-
t(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
1
FMC_CLK high to FMC_NEx high
(x= 0…2)
td(CLKH-NExH)
2Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
0.5
-
0
FMC_CLK low to FMC_Ax valid
(x=16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2
-
FMC_CLK high to FMC_Ax invalid
(x=16…25)
2Tfmc_ker_ck
ns
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
-
1.5
-
2Tfmc_ker_ck-0.5
FMC_D[15:0] valid data before FMC_CLK
high
tsu(DV-CLKH)
th(CLKH-DV)
2
1
-
-
FMC_D[15:0] valid data after FMC_CLK
high
t(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Electrical characteristics (rev V)
Figure 79. Synchronous non-multiplexed PSRAM write timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKL-NExL)
FMC_NEx
d(CLKH-NExH)
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
FMC_NWE
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
td(CLKH-NWEH)
d(CLKL-NWEL)
t
t
d(CLKL-Data)
d(CLKL-Data)
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FMC_NBL
t
t
d(CLKH-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
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(1)
Table 172. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
t(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
2
FMC_CLK high to FMC_NEx high
(x= 0…2)
t(CLKH-NExH)
Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
0.5
-
0
FMC_CLK low to FMC_Ax valid
(x=16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2.
-
FMC_CLK high to FMC_Ax invalid
(x=16…25)
Tfmc_ker_ck
ns
td(CLKL-NWEL)
td(CLKH-NWEH)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
-
1.5
-
Tfmc_ker_ck+1
FMC_D[15:0] valid data after FMC_CLK
low
td(CLKL-Data)
-
3.5
td(CLKL-NBLL)
td(CLKH-NBLH)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
-
2
-
Tfmc_ker_ck+1
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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NAND controller waveforms and timings
Electrical characteristics (rev V)
Figure 80 through Figure 83 represent synchronous waveforms, and Table 173 and
Table 174 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
COM.FMC_SetupTime = 0x01
COM.FMC_WaitSetupTime = 0x03
COM.FMC_HoldSetupTime = 0x02
COM.FMC_HiZSetupTime = 0x01
ATT.FMC_SetupTime = 0x01
ATT.FMC_WaitSetupTime = 0x03
ATT.FMC_HoldSetupTime = 0x02
ATT.FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
Capacitive load C = 30 pF
L
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 80. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
t
th(NOE-ALE)
d(ALE-NOE)
FMC_NOE (NRE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
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Figure 81. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NWE-ALE)
d(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NWE-D)
v(NWE-D)
MS32768V1
Figure 82. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NOE-ALE)
d(ALE-NOE)
FMC_NWE
FMC_NOE
t
w(NOE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
MS32769V1
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Electrical characteristics (rev V)
Figure 83. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
t
h(NOE-ALE)
d(ALE-NOE)
w(NWE)
FMC_NWE
FMC_N OE
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FMC_D[15:0]
MS32770V1
(1)
Table 173. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
Min
Max
4Tfmc_ker_ck+0.5
Unit
tw(N0E)
FMC_NOE low width
4Tfmc_ker_ck – 0.5
FMC_D[15-0] valid data before
FMC_NOE high
tsu(D-NOE)
th(NOE-D)
8
0
-
FMC_D[15-0] valid data after
FMC_NOE high
ns
-
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid
1. Guaranteed by characterization results.
-
3Tfmc_ker_ck +1
-
4Tfmc_ker_ck –2
(1)
Table 174. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
Min
Max
Unit
tw(NWE)
FMC_NWE low width
4Tfmc_ker_ck – 0.5
4Tfmc_ker_ck +0.5
FMC_NWE low to FMC_D[15-0]
valid
tv(NWE-D)
th(NWE-D)
0
-
FMC_NWE high to FMC_D[15-0]
invalid
2Tfmc_ker_ck – 0.5
5Tfmc_ker_ck – 1
-
-
ns
FMC_D[15-0] valid before
FMC_NWE high
td(D-NWE)
-
FMC_ALE valid before FMC_NWE
low
td(ALE-NWE)
th(NWE-ALE)
3Tfmc_ker_ck +0.5
-
FMC_NWE high to FMC_ALE
invalid
2Tfmc_ker_ck – 1
1. Guaranteed by characterization results.
DS12556 Rev 5
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SDRAM waveforms and timings
In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
For 2.7 V<V <3.6 V: FMC_CLK =110 MHz at 20 pF
DD
For 1.8 V<V <1.9 V: FMC_CLK =100 MHz at 20 pF
DD
For 1.62 V< <1.8 V, FMC_CLK =100 MHz at 15 pF
DD
Figure 84. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
th(SDCLKL_NCAS)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
td(SDCLKL_NCAS)
FMC_SDNWE
FMC_D[31:0]
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Data1 Data2 Datai
Datan
MS32751V2
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Electrical characteristics (rev V)
(1)
Table 175. SDRAM read timings
Parameter
Symbol
Min
Max
Unit
2Tfmc_ker_ck
+0.5
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck – 1
tsu(SDCLKH _Data)
th(SDCLKH_Data)
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2
1
-
-
td(SDCLKL_Add)
-
1.5
1.5
-
td(SDCLKL- SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0.5
-
1
0.5
-
-
0.5
-
0
1. Guaranteed by characterization results.
(1)
Table 176. LPSDR SDRAM read timings
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
tsu(SDCLKH_Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
2
1.5
-
-
-
2.5
2.5
-
td(SDCLKL_SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0
-
0.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
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Figure 85. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
th(SDCLKL_NCAS)
th(SDCLKL_NWE)
td(SDCLKL_NCAS)
td(SDCLKL_NWE)
td(SDCLKL_Data)
Data1
Data2
Datai
Datan
FMC_D[31:0]
td(SDCLKL_NBL)
FMC_NBL[3:0]
th(SDCLKL_Data)
MS32752V2
(1)
Table 177. SDRAM Write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
td(SDCLKL _Data
th(SDCLKL _Data)
td(SDCLKL_Add)
)
-
0
1
-
-
1.5
1.5
-
td(SDCLKL_SDNWE)
th(SDCLKL_SDNWE)
td(SDCLKL_ SDNE)
th(SDCLKL-_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
td(SDCLKL_SDNCAS)
-
0.5
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
1.5
-
0.5
-
1
0.5
-
-
1
0.5
-
1. Guaranteed by characterization results.
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Electrical characteristics (rev V)
(1)
Table 178. LPSDR SDRAM Write timings
Parameter Min
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
Symbol
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
td(SDCLKL _Data
)
-
0
-
2.5
-
th(SDCLKL _Data)
td(SDCLKL_Add)
2.5
2.5
-
td(SDCLKL-SDNWE)
th(SDCLKL-SDNWE)
td(SDCLKL- SDNE)
th(SDCLKL- SDNE)
td(SDCLKL-SDNRAS)
th(SDCLKL-SDNRAS)
td(SDCLKL-SDNCAS)
td(SDCLKL-SDNCAS)
-
0
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
3
0
-
-
1.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
7.3.18
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 179 and Table 180 for QUADSPI
are derived from tests performed under the ambient temperature, f frequency and V
AHB
DD
supply voltage conditions summarized in Table 120: General operating conditions, with the
following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
The following table summarizes the parameters measured in SDR mode.
(1)
Table 179. QUADSPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7<VDD<3.6 V
CL = 20 pF
-
-
133
QUADSPI clock
frequency
Fck11/TCK
MHz
1.62<VDD<3.6 V
CL = 15 pF
-
-
100
DS12556 Rev 5
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
(1)
Table 179. QUADSPI characteristics in SDR mode (continued)
Symbol
tw(CKH)
tw(CKL)
tw(CKH)
Parameter
Conditions
Min
TCK/2–0.5
Typ
Max
TCK/2
Unit
QUADSPI clock high
and low time Even
division
-
PRESCALER[7:0] =
n = 0,1,3,5...
TCK/2
-
-
TCK/2+0.5
(n/2)*TCK/ (n+1)
(n/2)*TCK/(n+1)-0.5
QUADSPI clock high
and low time Odd
division
PRESCALER[7:0] =
n = 2,4,6,8...
(n/2+1)*TCK
(n+1)+0.5
/
tw(CKL)
(n/2+1)*TCK/(n+1)
-
ns
ts(IN)
th(IN)
tv(OUT)
th(OUT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
1
3.5
-
-
-
-
-
-
-
-
1
-
2
-
0
1. Guaranteed by characterization results.
The following table summarizes the parameters measured in DDR mode.
(1)
Table 180. QUADSPI characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7<VDD<3.6 V
CL = 20 pF
-
-
100
Fck11/TCK
QUADSPI clock frequency
MHz
1.62<VDD<3.6 V
CL = 15 pF
-
-
100
tw(CKH)
tw(CKL)
TCK/2–0.5
TCK/2
-
-
TCK/2
QUADSPI clock high and PRESCALER[7:0] =
low time Even division n = 0,1,3,5...
TCK/2+0.5
(n/2)*TCK
(n+1)-0.5
/
(n/2)*TCK
(n+1)
/
tw(CKH)
-
-
QUADSPI clock high and PRESCALER[7:0] =
low time Odd division
n = 2,4,6,8...
(n/2+1)*TCK
/
(n/2+1)*TCK
(n+1)+0.5
/
tw(CKL)
(n+1)
tsr(IN), tsf(IN)
Data input setup time
Data input hold time
-
-
1.5
3.5
-
-
-
-
-
thr(IN),thf(IN)
ns
DHHC=0
DHHC=1
5
6
tvr(OUT)
,
Data output valid time
Data output hold time
tvf(OUT)
-
3
TCK/4+1
TCK/4+2
PRESCALER[7:0] =
1,2…
DHHC=0
-
-
-
-
thr(OUT)
,
DHHC=1
thf(OUT)
TCK/4
PRESCALER[7:0]=1
,2…
1. Guaranteed by characterization results.
266/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 86. Quad-SPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
Figure 87. Quad-SPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
7.3.19
Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 181 for Delay Block are derived
from tests performed under the ambient temperature, f frequency and VDD supply
rcc_c_ck
voltage summarized in Table 120: General operating conditions, with the following
configuration:
Table 181. Delay Block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tinit
t∆
Initial delay
Unit Delay
-
-
1400
35
2200
40
2400
45
ps
-
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.20
16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 182 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 120: General operating conditions.
(1)(2)
Table 182. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage for ADC
ON
V
-
1.62
-
3.6
V
DDA
Positive reference
voltage
V
-
-
1.62
-
V
V
V
REF+
DDA
Negative
reference voltage
V
V
SSA
REF-
BOOST = 11
BOOST = 10
BOOST = 01
BOOST = 00
0.12
0.12
0.12
-
-
-
-
-
50
25
ADC clock
frequency
f
1.62 V ≤ VDDA ≤ 3.6 V
MHz
ADC
12.5
6.25
Resolution = 16 bits,
>2.5 V
f
f
=36 MHz
SMP = 1.5
-
-
3.60
ADC
V
DDA
T
= 90 °C
= 125 °C
= 90 °C
J
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 16 bits,
=37 MHz
= 50 MHz
= 50 MHz
= 50 MHz
= 50 MHz
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 1.5
SMP = 1.5
-
-
-
-
-
-
-
-
-
-
3.35
5.00
5.50
7.10
8.30
ADC
Sampling rate for
f
f
f
f
ADC
ADC
ADC
ADC
(4)
Direct channels
T
J
f
f
=32 MHz
SMP = 2.5
-
-
2.90
ADC
ADC
V
>2.5 V
DDA
T
J
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 16 bits
resolution = 14 bits
resolution = 12 bits
resolution = 10 bits
resolution = 8 bits
=31 MHz
= 33 MHz
= 39 MHz
= 48 MHz
= 50 MHz
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.80
3.30
4.30
6.00
7.10
(3)
f
MSps
s
Sampling rate for
Fast channels
f
f
f
f
ADC
ADC
ADC
ADC
T
= 125 °C
= 90 °C
J
T
J
Sampling rate for
Slow channels
f
= 10 MHz
SMP = 1.5
1.00
10
ADC
T
= 125 °C
J
External trigger
period
1/
t
Resolution = 16 bits
-
-
-
TRIG
f
ADC
Conversion
voltage range
(5)
AIN
V
-
-
0
V
REF+
V
Common mode
input voltage
V
/2
V
/
V
/2
REF
REF
− 10%
REF
2
V
V
CMIV
+ 10%
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
(1)(2)
Table 182. ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resolution = 16 bits, T = 125 °C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
170
435
J
Resolution = 14 bits, T = 125 °C
J
External input
impedance
(6)
R
Resolution = 12 bits, T =125 °C
1150
5650
26500
Ω
AIN
J
Resolution = 10 bits, T = 125 °C
J
Resolution = 8 bits, T = 125 °C
J
Internal sample
and hold
capacitor
C
-
-
-
4
5
-
-
10
-
pF
us
ADC
t
ADC LDO startup
time
ADCVREG
_STUP
-
conver
sion
cycle
ADC Power-up
time
t
LDO already started
1
STAB
Offset and
linearity
calibration time
t
-
-
165010
1280
-
-
-
-
1/f
1/f
CAL
ADC
ADC
t
Offset calibration
time
OFF_
CAL
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
-
1.5
2
-
2.5
2.5
Trigger
conversion
latency regular
and injected
channels without
conversion abort
-
t
1/f
1/f
LATR
ADC
-
-
2.5
-
2.5
-
-
2.25
3.5
3
-
Trigger
conversion
latency regular
injected channels
aborting a regular
conversion
3.5
t
LATRINJ
ADC
-
-
3.5
-
-
3.25
810.5
t
Sampling time
1.5
-
1/f
1/f
S
ADC
ADC
Total conversion
time (including
sampling time)
ts + 0.5
+ N/2
t
Resolution = N bits
-
-
CONV
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
(1)(2)
Table 182. ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resolution = 16 bits, f
Resolution = 14 bits, f
Resolution = 12 bits, f
=25 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1440
1350
990
1080
810
585
630
432
315
360
270
225
720
675
495
540
405
292.5
315
216
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC
ADC
ADC
ADCconsumption
on V
,
DDA
=30 MHz
=40 MHz
BOOST=11,
Differential mode
ADCconsumption
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
on V
DDA
BOOST=10,
Differential mode
f
=25 MHz
ADC
I
_
D
DDA
(ADC)
ADCconsumption
on V
DDA
BOOST=01,
Differential mode
f
=12.5 MHz
ADC
ADCconsumption
on V
DDA
BOOST=00,
Differential mode
f
=6.25 MHz
ADC
ADCconsumption
on V
Resolution = 16 bits, f
=25 MHz
ADC
DDA
Resolution = 14 bits, f
Resolution = 12 bits, f
=30 MHz
=40 MHz
BOOST=11,
Single-ended
mode
ADC
ADC
µA
ADCconsumption
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
on V
DDA
BOOST=10,
Singl-ended mode
f
=25 MHz
ADC
I
_
(
DDA SE
ADCconsumption
on V
ADC)
DDA
BOOST=01,
Single-ended
mode
Resolution = 12 bits
-
-
-
157.5
-
f
=12.5 MHz
ADC
ADCconsumption
on V
BOOST=00,
Single-ended
mode
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
180
135
-
-
DDA
Resolution = 12 bits
-
-
-
112.5
-
f
=6.25 MHz
ADC
f
=50 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
220
180
120
80
-
-
-
-
-
ADC
f
=25 MHz
ADC
I
ADCconsumption
on V
DD
f
f
=12.5 MHz
=6.25 MHz
ADC
ADC
(ADC)
DD
f
=3.125 MHz
ADC
1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid for UFBGA176+25 and one ADC. The values for other packages and multiple ADCs may be different.
4. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
5. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA
.
6. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 183. Minimum sampling time vs R
Electrical characteristics (rev V)
(1)(2)
AIN
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
16 bits
47
47
7.37E-08
6.29E-08
6.84E-08
7.80E-08
9.86E-08
1.32E-07
5.32E-08
5.74E-08
6.58E-08
8.37E-08
1.11E-07
1.56E-07
2.16E-07
3.01E-07
4.34E-08
4.68E-08
5.35E-08
6.68E-08
8.80E-08
1.24E-07
1.69E-07
2.38E-07
3.45E-07
5.15E-07
7.42E-07
1.10E-06
1.14E-07
9.74E-08
1.02E-07
1.12E-07
1.32E-07
1.61E-07
8.00E-08
8.50E-08
9.31E-08
1.10E-07
1.34E-07
1.78E-07
2.39E-07
3.29E-07
6.51E-08
6.89E-08
7.55E-08
8.77E-08
1.08E-07
1.43E-07
1.89E-07
2.60E-07
3.66E-07
5.35E-07
7.75E-07
1.14E-06
1.72E-07
1.55E-07
1.58E-07
1.62E-07
1.80E-07
2.01E-07
1.29E-07
1.32E-07
1.40E-07
1.51E-07
1.73E-07
2.14E-07
2.68E-07
3.54E-07
1.08E-07
1.11E-07
1.16E-07
1.26E-07
1.40E-07
1.71E-07
2.13E-07
2.80E-07
3.84E-07
5.48E-07
7.78E-07
1.14E-06
68
14 bits
100
150
220
47
68
100
150
220
330
470
680
47
12 bits
68
100
150
220
330
470
680
1000
1500
2200
3300
10 bits
DS12556 Rev 5
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
(1)(2)
Table 183. Minimum sampling time vs R
(continued)
AIN
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
47
68
3.32E-08
3.59E-08
4.10E-08
5.06E-08
6.61E-08
9.17E-08
1.24E-07
1.74E-07
2.53E-07
3.73E-07
5.39E-07
8.02E-07
1.13E-06
1.62E-06
2.36E-06
3.50E-06
5.10E-08
5.35E-08
5.83E-08
6.76E-08
8.22E-08
1.08E-07
1.40E-07
1.91E-07
2.70E-07
3.93E-07
5.67E-07
8.36E-07
1.18E-06
1.69E-06
2.47E-06
3.69E-06
8.61E-08
8.83E-08
9.22E-08
9.95E-08
1.11E-07
1.32E-07
1.63E-07
2.12E-07
2.85E-07
4.05E-07
5.75E-07
8.38E-07
1.18E-06
1.68E-06
2.45E-06
3.65E-06
100
150
220
330
470
680
8 bits
1000
1500
2200
3300
4700
6800
10000
15000
1. Guaranteed by design.
2. Data valid at up to 125 °C, with a 47 pF PCB capacitor, and VDDA=1.6 V.
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to PF3, PF5, PF7, PF9, PA6, PC4, PB1, PF11 and PF13.
5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.
272/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
(1)(2)
Table 184. ADC accuracy
Conditions(3)
Symbol
Parameter
Min
Typ
Max
Unit
Single ended
Direct
-
-
-
-
-
+10/–20
±15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
channel
Differential
Single ended
Fast channel
+10/–20
±15
ET
Total undadjusted error
Differential
Single ended
Slow
±10
channel
Differential
±10
EO
EG
Offset error
Gain error
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±10
-
±15
LSB
Single ended
Differential
+3/–1
+4.5/–1
±11
ED
Differential linearity error
Integral linearity error
Effective number of bits
Single ended
Direct
channel
Differential
±7
Single ended
Fast channel
±13
EL
Differential
±7
Single ended
Slow
±10
channel
Differential
±6
Single ended
Differential
12.2
13.2
75.2
81.2
77.0
81.0
87
ENOB
SINAD
SNR
Bits
dB
Single ended
Differential
Signal-to-noise and
distortion ratio
Single ended
Differential
Signal-to-noise ratio
Single ended
Differential
THD
Total harmonic distortion
90
1. Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V and BOOST=11.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
and ΣI
in
INJ(PIN)
INJ(PIN)
Section 7.3.14 does not affect the ADC accuracy.
DS12556 Rev 5
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311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 88. ADC accuracy characteristics (12-bit resolution)
V
V
DDA
4096
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
E
G
4095
4094
4093
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
E
O
L
E
D
1L SB
IDEAL
7
0
V
1
2
3
456
4093 4094 4095 4096
V
DDA
SSA
ai14395c
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 89. Typical connection diagram using the ADC
STM32
V
DD
Sample and hold ADC
V
T
converter
0.6 V
(1)
AIN
(1)
R
R
ADC
AINx
12-bit
converter
V
0.6 V
T
V
AIN
C
(1)
ADC
C
parasitic
I
1 μA
L
ai17534b
1. Refer to Table 182 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
274/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
General PCB design guidelines
Electrical characteristics (rev V)
Power supply decoupling should be performed as shown in Figure 90 or Figure 91,
depending on whether V is connected to V or not. The 100 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 90. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM32
(1)
VREF+
1 μF // 100 nF
VDDA
1 μF // 100 nF
(1)
VSSA/VREF+
MSv50648V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA
.
Figure 91. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32
(1)
VREF+/VDDA
1 μF // 100 nF
(1)
VREF-/VSSA
MSv50649V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA
.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.21
DAC characteristics
(1)(2)
Table 185. DAC characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
1.8
3.3
-
3.6
VREF+
Positive reference voltage
-
-
1.80
VDDA
V
Negative reference
voltage
VREF-
-
VSSA
-
-
-
connected
to VSSA
5
DAC output buffer
ON
RL
RO
Resistive Load
connected
to VDDA
kΩ
25
10.3
-
-
13
-
-
Output Impedance
DAC output buffer OFF
16
1.6
VDD
2.7 V
=
=
Output impedance
sample and hold mode,
output buffer ON
DAC output buffer
ON
RBON
kΩ
kΩ
VDD
-
-
-
-
-
-
2.6
2.0 V
VDD
=
17.8
18.7
Output impedance
sample and hold mode,
output buffer OFF
2.7 V
DAC output buffer
OFF
RBOFF
VDD
=
2.0 V
CL
DAC output buffer OFF
Sample and Hold mode
-
-
-
50
1
pF
µF
Capacitive Load
CSH
0.1
VDDA
−0.2
DAC output buffer ON
DAC output buffer OFF
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
0
-
-
VREF+
±0.5 LSB
2.05
1.97
1.67
1.66
1.65
-
-
-
-
-
Settling time (full scale:
for a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
±1 LSB
±2 LSB
±4 LSB
±8 LSB
-
Normal mode, DAC
output buffer ON,
CL ≤ 50 pF,
-
tSETTLING
µs
RL ≥ 5 ?
-
-
Normal mode, DAC output buffer
OFF, ±1LSB CL=10 pF
-
-
1.7
5
2
Wakeup time from off
state (setting the ENx bit
in the DAC Control
register) until the final
value of ±1LSB is reached
Normal mode, DAC output buffer
7.5
ON, CL ≤ 50 pF, RL = 5 ?
(3)
tWAKEUP
µs
Normal mode, DAC output buffer
2
5
OFF, CL ≤ 10 pF
DC VDDA supply rejection Normal mode, DAC output buffer
PSRR
-
−80
−28
dB
ratio
ON, CL ≤ 50 pF, RL = 5 ?
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
(1)(2)
Table 185. DAC characteristics
(continued)
Min
Symbol
Parameter
Conditions
Typ
Max
Unit
Sampling time in Sample
and Hold mode
MODE<2:0>_V12=100/101
(BUFFER ON)
-
-
0.7
2.6
ms
CL=100 nF
MODE<2:0>_V12=110
(BUFFER OFF)
11.5
0.3
18.7
0.6
(code transition between
the lowest input code and
the highest input code
when DAC_OUT reaches
the ±1LSB final value)
tSAMP
MODE<2:0>_V12=111
-
µs
(INTERNAL BUFFER OFF)
Internal sample and hold
capacitor
CIint
-
1.8
50
2.2
-
2.6
-
pF
µs
Middle code offset trim
time
Minimum time to verify the each
code
tTRIM
VREF+ = 3.6 V
VREF+ = 1.8 V
-
-
850
425
-
-
Middle code offset for 1
trim code step
Voffset
µV
No load,
middle
code
-
-
-
-
-
-
-
360
490
-
-
-
-
-
-
-
DAC output buffer
(0x800)
ON
No load,
worst code
(0xF1C)
DAC quiescent
IDDA(DAC)
consumption from VDDA
No load,
DAC output buffer middle/wor
20
OFF
st code
(0x800)
360*TON
/
Sample and Hold mode,
CSH=100 nF
(TON+TOFF
)
(4)
No load,
middle
code
µA
170
170
160
DAC output buffer
ON
(0x800)
No load,
worst code
(0xF1C)
No load,
DAC output buffer middle/wor
DAC consumption from
VREF+
IDDV(DAC)
OFF
st code
(0x800)
170*TON
/
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code)
-
-
(TON+TOFF
)
)
-
-
(4)
160*TON
/
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code)
(TON+TOFF
(4)
1. Guaranteed by design unless otherwise specified.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
2. TBD stands for “to be defined”.
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
(1)
Table 186. DAC accuracy
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON
DAC output buffer OFF
10 bits
−2
−2
-
-
-
-
2
2
-
Differential non
linearity(2)
DNL
-
LSB
-
Monotonicity
DAC output buffer ON, CL≤50 pF,
RL ≥5 ?
−4
-
4
INL
Integral non linearity(3)
LSB
DAC output buffer OFF,
−4
-
-
-
4
CL ≤50 pF, no RL
DAC output
buffer ON,
CL ≤50 pF,
RL ≥5 ?
V
REF+ = 3.6 V
±15
Offset error at code
0x800 (3)
VREF+ = 1.8 V
-
-
-
-
±30
±8
Offset
LSB
DAC output buffer OFF,
CL ≤50 pF, no RL
Offset error at code
0x001(4)
DAC output buffer OFF,
Offset1
-
-
-
-
±5
±6
LSB
LSB
CL ≤50 pF, no RL
DAC output
VREF+ = 3.6 V
Offset error at code
0x800 after factory
calibration
buffer ON,
OffsetCal
CL ≤50 pF,
RL ≥5 ?
VREF+ = 1.8 V
-
-
±7
DAC output buffer ON,CL≤50 pF,
RL ≥5 ?
-
-
-
-
-
±1
±1
-
Gain
SNR
Gain error(5)
%
DAC output buffer OFF,
CL ≤ 50 pF, no RL
DAC output buffer ON,CL ≤50 pF,
RL ≥5 ?, 1 kHz, BW = 500 KHz
67.8
Signal-to-noise ratio(6)
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL,1 kHz, BW =
500 KHz
-
67.8
-
DAC output buffer ON, CL≤50 pF,
RL ≥5 ?, 1 kHz
-
-
-
-
−78.6
−78.6
67.5
-
-
-
-
Total harmonic
distortion(6)
THD
dB
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON, CL≤50 pF,
RL ≥5 ?, 1 kHz
Signal-to-noise and
distortion ratio(6)
SINAD
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
67.5
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
(1)
Table 186. DAC accuracy (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON,
-
10.9
-
CL ≤50 pF, RL ≥5 ?, 1 kHz
Effective number of
bits
ENOB
bits
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
-
10.9
-
1. Guaranteed by characterization.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5dBFS with Fsampling=1 MHz.
Figure 92. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
DAC_OUTx
12-bit
digital to
analog
converter
C
L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
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Electrical characteristics (rev V)
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7.3.22
Voltage reference buffer characteristics
(1)
Table 187. VREFBUF characteristics
Symbol
Parameter
Conditions
VSCALE = 000
Min
2.8
Typ
Max
3.6
Unit
3.3
VSCALE = 001
VSCALE = 010
VSCALE = 011
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
VSCALE = 000
VSCALE = 001
VSCALE = 010
2.4
-
3.6
Normal mode
Degraded mode
Normal mode
2.1
-
3.6
1.8
-
3.6
VDDA
Analog supply voltage
1.62
1.62
1.62
1.62
2.498
2.046
1.801
-
2.80
2.40
2.10
1.80
2.5035
2.052
1.806
1.504
-
-
-
2.5
2.049
1.804
V
VSCALE = 011 1.4995 1.5015
VDDA
150 mV
−
Voltage Reference
Buffer Output, at 30 °C,
Iload= 100 µA
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
-
-
-
-
VDDA
VDDA
VDDA
VDDA
VREFBUF
_OUT
VDDA
150 mV
−
Degraded mode(2)
VDDA
150 mV
−
VDDA
150 mV
−
TRIM
CL
Trim step resolution
Load capacitor
-
-
-
-
-
±0.05
1
±0.1
1.50
%
0.5
uF
Equivalent Serial
Resistor of CL
esr
-
-
-
-
-
-
2
?
Iload
Static load current
-
-
-
-
4
-
mA
I
load = 500 µA
Iload = 4 mA
200
100
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
ppm/V
-
ppm/
mA
Iload_reg
Load regulation
500 µA ≤ ILOAD ≤ 4 mA Normal Mode
−40 °C < TJ < +125 °C
-
-
50
-
-
Tcoeff
VREFINT
+ 100
ppm/
°C
Tcoeff
Temperature coefficient
DC
-
-
-
-
60
40
-
-
PSRR
Power supply rejection
dB
100KHz
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
(1)
Table 187. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
CL=0.5 µF
Min
Typ
300
500
650
Max
Unit
-
-
-
-
-
-
-
-
-
tSTART
Start-up time
CL=1 µF
µs
CL=1.5 µF
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
IINRUSH
-
-
8
-
mA
µA
ILOAD = 0 µA
-
-
-
-
-
-
15
16
32
25
30
50
VREFBUF
consumption from
VDDA
IDDA(VRE
ILOAD = 500 µA
FBUF)
ILOAD = 4 mA
1. Guaranteed by design.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
7.3.23
Temperature sensor characteristics
Table 188. Temperature sensor characteristics
Symbol
Parameter
Min Typ Max Unit
(1)
TL
VSENSE linearity with temperature
-
-
-
3
°C
mV/°C
V
Avg_Slope(2) Average slope
2
-
(3)
V30
Voltage at 30°C ± 5 °C
-
0.62
-
25.2
-
tstart_run
Startup time in Run mode (buffer startup)
ADC sampling time when reading the temperature
Sensor consumption
-
-
-
µs
(1)
tS_temp
9
-
(1)
Isens
0.18 0.31
3.8 6.5
µA
(1)
Isensbuf
Sensor buffer consumption
-
1. Guaranteed by design.
2. Guaranteed by characterization.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 189. Temperature sensor calibration values
Symbol
Parameter
Memory address
Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V
TS_CAL1
0x1FF1 E820 -0x1FF1 E821
Temperature sensor raw data acquired value at
110 °C, VDDA=3.3 V
TS_CAL2
0x1FF1 E840 - 0x1FF1 E841
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.24
Temperature and V
monitoring
BAT
Table 190. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
26
4
-
KΩ
-
Ratio on VBAT measurement
Error on Q
-
-
Er(1)
–10
-
+10
%
µs
(1)
tS_vbat
ADC sampling time when reading VBAT input
High supply monitoring
9
-
-
-
-
-
VBAThigh
VBATlow
3.55
1.36
V
Low supply monitoring
-
1. Guaranteed by design.
Table 191. V
charging characteristics
BAT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBRS in PWR_CR3= 0
VBRS in PWR_CR3= 1
-
5
-
-
RBC
Battery charging resistor
KΩ
1.5
Table 192. Temperature monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
TEMPhigh
TEMPlow
High temperature monitoring
Low temperature monitoring
-
-
117
-
-
°C
–25
7.3.25
Voltage booster for analog switch
(1)
Table 193. Voltage booster for analog switch characteristics
Symbol
Parameter
Supply voltage
Condition
Min Typ Max Unit
VDD
-
1.62 2.6 3.6
V
Booster startup time
-
-
-
-
-
-
-
50
µs
tSU(BOOST)
1.62 V ≤ VDD ≤ 2.7 V
2.7 V < VDD < 3.6 V
125
250
Booster consumption
µA
IDD(BOOST)
1. Guaranteed by characterization results.
282/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
7.3.26
Comparator characteristics
(1)
Table 194. COMP characteristics
Symbol
VDDA
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
-
1.62
3.3
3.6
Comparator input voltage
range
VIN
-
0
-
VDDA
V
(2)
VBG
VSC
Scaler input voltage
Scaler offset voltage
-
-
-
-
±5
0.2
0.8
140
2
±10
0.3
1
mV
µA
µs
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
Scaler static consumption
from VDDA
IDDA(SCALER)
-
tSTART_SCALER Scaler startup time
-
250
5
High-speed mode
Medium mode
-
Comparator startup time to
reach propagation delay
tSTART
-
5
20
80
80
1.2
7
µs
specification
Ultra-low-power mode
High-speed mode
Medium mode
-
15
50
0.5
2.5
50
0.5
2.5
±5
0
-
ns
µs
Propagation delay for
200 mV step with 100 mV
overdrive
-
Ultra-low-power mode
High-speed mode
Medium mode
-
(3)
tD
-
120
1.2
7
ns
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
-
µs
Ultra-low-power mode
Full common mode range
No hysteresis
-
Voffset
Comparator offset error
-
±20
-
mV
-
Low hysteresis
5
8
16
-
10
20
30
400
22
37
52
600
Vhys
Comparator hysteresis
mV
nA
Medium hysteresis
High hysteresis
Static
Ultra-low-
With 50 kHz
±100 mV overdrive
square signal
power mode
-
-
-
-
-
800
5
-
Static
7
Comparator consumption
from VDDA
With 50 kHz
I
DDA(COMP)
Medium mode
±100 mV overdrive
square signal
6
-
100
-
µA
Static
70
75
High-speed
mode
With 50 kHz
±100 mV overdrive
square signal
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 125: Embedded reference voltage.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3. Guaranteed by characterization results.
7.3.27
Operational amplifier characteristics
Table 195. Operational amplifier characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
Range
VDDA
CMIR
-
2
3.3
3.6
V
Common Mode Input
Range
-
0
-
-
VDDA
±1.5
±2.5
-
25°C, no load on output
-
-
VIOFFSET
Input offset voltage
mV
All voltages and
temperature, no load
-
ΔVIOFFSET
Input offset voltage drift
-
-
-
±3.0
μV/°C
Offset trim step at low
common input voltage
TRIMOFFSETP
-
-
1.1
1.1
1.5
1.5
TRIMLPOFFSETP
(0.1*VDDA
)
mV
Offset trim step at high
common input voltage
TRIMOFFSETN
-
TRIMLPOFFSETN
(0.9*VDDA
)
ILOAD
ILOAD_PGA
CLOAD
Drive current
Drive current in PGA mode
Capacitive load
-
-
-
-
-
-
-
-
-
500
270
50
μA
pF
dB
Common mode rejection
ratio
CMRR
PSRR
-
-
80
66
-
-
CLOAD ≤ 50pf /
RLOAD ≥ 4 kΩ(1) at 1 kHz,
Vcom=VDDA/2
Power supply rejection
ratio
50
4
dB
Gain bandwidth for high
supply range
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
GBW
SR
7.3
12.3
MHz
V/µs
dB
Normal mode
-
-
3
-
-
Slew rate (from 10% and
90% of output voltage)
High-speed mode
30
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
AO
Open loop gain
59
90
129
φm
Phase margin
Gain margin
-
-
-
-
55
12
-
-
°
GM
dB
I
load=max or RLOAD=min,
Input at VDDA
VDDA
−100 mV
VOHSAT
High saturation voltage
Low saturation voltage
-
-
-
mV
Iload=max or RLOAD=min,
Input at 0 V
VOLSAT
-
100
284/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 195. Operational amplifier characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kΩ,
-
0.8
3.2
mode
follower
configuration
Wake up time from OFF
state
tWAKEUP
µs
CLOAD ≤ 50pf,
RLOAD ≥ 4 kΩ,
follower
High
speed
mode
-
0.9
2.8
configuration
PGA gain = 2
−1
−2
−2.5
−3
−1
−1
−2
−3
−1
−3
−3.5
−4
-
-
1
2
2.5
3
1
1
2
3
1
3
3.5
4
-
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA Gain=2
PGA Gain=4
PGA Gain=8
PGA Gain=16
PGA Gain = -1
PGA Gain = -3
PGA Gain = -7
PGA Gain = -15
-
Non inverting gain error
value
-
-
-
-
PGA gain
Inverting gain error value
%
-
-
-
-
External non-inverting gain
error value
-
-
10/10
30/10
70/10
150/10
10/10
30/10
70/10
150/10
R2/R1 internal resistance
values in non-inverting
PGA mode(2)
-
-
-
-
-
-
kΩ/
kΩ
Rnetwork
-
-
R2/R1 internal resistance
values in inverting PGA
mode(2)
-
-
-
-
-
-
Resistance variation (R1
or R2)
Delta R
-
−15
-
15
%
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 195. Operational amplifier characteristics (continued)
Symbol
Parameter
Conditions
Gain=2
Min
Typ
Max
Unit
-
GBW/2
GBW/4
GBW/8
GBW/16
5.00
-
-
-
-
-
-
-
-
Gain=4
Gain=8
-
-
-
-
-
-
-
PGA bandwidth for
different non inverting gain
MHz
Gain=16
Gain = -1
Gain = -3
Gain = -7
Gain = -15
PGA BW
3.00
PGA bandwidth for
different inverting gain
MHz
1.50
0.80
at
1 KHz
-
-
-
140
55
-
-
output loaded
with 4 kΩ
nV/√
Hz
en
Voltage noise density
at
10 KHz
Normal
mode
570
1000
no Load,
quiescent mode,
follower
OPAMP consumption from
VDDA
IDDA(OPAMP)
µA
High-
speed
mode
-
610
1200
1. RLOAD is the resistive load connected to VSSA or to VDDA.
2. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
7.3.28
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 196 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 120: General operating conditions.
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).
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Electrical characteristics (rev V)
Table 196. DFSDM measured timing - 1.62-3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DFSDM
clock
fDFSDMCLK
1.62 < VDD < 3.6 V
-
-
250
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
-
-
-
-
-
-
-
-
20
20
20
20
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
fCKIN
(1/TCKIN
Input clock
frequency
MH
z
)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]¹0),
2.7 < VDD < 3.6 V
Output clock
frequency
fCKOUT
1.62 < VDD < 3.6 V
1.62 < VDD < 3.6 V
-
-
20
55
Output clock
frequency
duty cycle
DuCyCKOU
45
50
%
T
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Input clock
high and low
time
twh(CKIN)
twl(CKIN)
TCKIN/2-0.5
TCKIN/2
-
-
-
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Data input
setup time
tsu
1.5
0.5
-
-
-
ns
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Data input
hold time
th
Manchester Manchester mode (SITP[1:0]=2,3),
data period
(recovered
clock period)
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
(CKOUTDIV+1)
* TDFSDMCLK
(2*CKOUTDIV)
* TDFSDMCLK
TManchester
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Figure 93. Channel transceiver timing diagrams
(SPICKSEL=0)
SITP = 00
tr
tf
twl
twh
tsu
th
tsu
th
SITP = 01
SPICKSEL=3
SPICKSEL=2
SPICKSEL=1
tr
tf
twl
twh
tsu
th
SITP = 0
SITP = 1
tsu
th
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V2
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Electrical characteristics (rev V)
7.3.29
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 197 for DCMI are derived from
tests performed under the ambient temperature, f frequency and VDD supply voltage
HCLK
summarized in Table 120: General operating conditions, with the following configuration:
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
(1)
Table 197. DCMI characteristics
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
Pixel Clock input
-
-
0.4
80
70
-
-
DCMI_PIXCLK
Dpixel
MHz
%
Pixel Clock input duty cycle
Data input setup time
Data hold time
30
3
t
su(DATA)
-
th(DATA)
1
-
tsu(HSYNC),
tsu(VSYNC)
DCMI_HSYNC/ DCMI_VSYNC input setup time
DCMI_HSYNC/ DCMI_VSYNC input hold time
2
1
-
-
ns
-
th(HSYNC),
th(VSYNC)
1. Guaranteed by characterization results.
Figure 94. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
th(HSYNC)
tsu(HSYNC)
th(HSYNC)
tsu(VSYNC)
tsu(DATA) th(DATA)
MS32414V2
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7.3.30
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 198 for LCD-TFT are derived
from tests performed under the ambient temperature, f
frequency and VDD supply
HCLK
voltage summarized in Table 120: General operating conditions, with the following
configuration:
LCD_CLK polarity: high
LCD_DE polarity: low
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5VDD
IO Compensation cell activated.
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
(1)
Table 198. LTDC characteristics
Symbol
Parameter
Min
Max
Unit
2.7<VD <3.6 V
D
150
LTDC clock
output
frequency
20pF
fCLK
-
MHz
%
2.7<VD <3.6 V
133
90
D
1.62<VD <3.6 V
D
DCLK
LTDC clock output duty cycle
Clock High time, low time
45
55
tw(CLKH),
tw(CLKL)
tw(CLK)//2-0.5
tw(CLK)//2+0.5
tv(DATA)
th(DATA)
tv(DATA)
2.7<VD <3.6 V
0.5
5
D
-
Data output valid time
-
1.62<VD <3.6 V
D
Data output hold time
0
-
-
tv(HSYNC),
tv(VSYNC),
tv(DE)
2.7<VD <3.6 V
0.5
D
HSYNC/VSYNC/DE output
valid time
1.62<VD <3.6 V
-
5
D
th(HSYNC),
HSYNC/VSYNC/DE output hold time
0
-
th(VSYNC)
,
th(DE)
1. Guaranteed by characterization results.
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Electrical characteristics (rev V)
Figure 95. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC)
tv(HSYNC)
LCD_HSYNC
th(DE)
tv(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
Pixel Pixel
1
Pixel
N
2
th(DATA)
HSYNCHorizontal
width back porch
Active width
Horizontal
back porch
One line
MS32749V1
Figure 96. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC)
tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
M lines data
VSYNC Vertical
width back porch
Active width
One frame
Vertical
back porch
MS32750V1
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7.3.31
Timer characteristics
The parameters given in Table 199 are guaranteed by design.
Refer to Section 7.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 199. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK
=
tTIMxCLK
1
-
240 MHz
tres(TIM)
Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK
=
tTIMxCLK
1
-
120 MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK/2
16/32
0
-
MHz
bit
f
TIMxCLK = 240 MHz
ResTIM
Timer resolution
Maximum possible count
with 32-bit counter
65536 ×
65536
tMAX_COUNT
tTIMxCLK
-
-
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2
.
7.3.32
Communication interfaces
I2C interface characteristics
2
The I C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
2
The I C timings requirements are guaranteed by design when the I C peripheral is properly
configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
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Electrical characteristics (rev V)
2
Table 200. Minimum i2c_ker_ck frequency in all I C modes
Symbol
Parameter
Condition
Min
Unit
Standard-mode
Fast-mode
-
2
Analog Filtre ON
DNF=0
8
9
MHz
Analog Filtre OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
Analog Filtre ON
DNF=0
17
16
Fast-mode Plus
Analog Filtre OFF
DNF=1
-
The SDA and SCL I/O requirements are met with the following restrictions:
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but still present.
DDIOx
The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load C supported in Fm+, which is given by these formulas:
Load
t
=0.8473xR xC
P Load
r(SDA/SCL)
R
= (V -V
)/I
P(min)
DD OL(max) OL(max)
Where R is the I2C lines pull-up. Refer to Section 7.3.15: I/O port characteristics for
P
2
the I C I/Os characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
2
(1)
Table 201. I C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes
that are suppressed by analog
filter
tAF
50(2)
80(3)
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
USART interface characteristics
Unless otherwise specified, the parameters given in Table 202 for USART are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 120: General operating conditions, with the following
configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS1
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Electrical characteristics (rev V)
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Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
(1)
Table 202. USART characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
Slave mode
Slave mode
Slave mode
12.5
fCK
USART clock frequency
-
-
MHz
25
-
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
tker+1
2
-
-
-
-
,
CK high and low time
Data input setup time
Master mode
1/fCK/2-2
1/fCK/2
1/fCK/2+2
tw(SCKL)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
t
ker+6
-
-
-
-
tsu(RX)
th(RX)
tv(TX)
th(TX)
1.5
0
-
-
Data input hold time
Data output valid time
Data output hold time
1.5
-
-
-
ns
12
0.5
-
20
1
-
-
9
0
-
-
1. Guaranteed by characterization results.
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Electrical characteristics (rev V)
Figure 97. USART timing diagram in Master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
t
su(MI)
f(SCK)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 98. USART timing diagram in Slave mode
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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SPI interface characteristics
Unless otherwise specified, the parameters given in Table 203 for SPI are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 120: General operating conditions, with the following
configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 203. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
1.62<VDD<3.6 V
SPI1, 2, 3
80
Master mode
2.7<VDD<3.6 V
SPI1, 2, 3
100
50
Master mode
1.62<VDD<3.6 V
SPI4, 5, 6
fSCK
SPI clock frequency
-
-
MHz
Slave receiver mode
1.62<VDD<3.6 V
100
31
Slave mode transmitter/full duplex
2.7<VDD<3.6 V
Slave mode transmitter/full duplex
1.62 <VDD<3.6 V
29
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
2
1
-
-
-
-
-
,
SCK high and low time Master mode
TPCLK-2 TPCLK TPCLK+2
tw(SCKL)
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Electrical characteristics (rev V)
(1)
Table 203. SPI characteristics (continued)
Symbol
Parameter
Conditions
Master mode
Min
Typ
Max
Unit
tsu(MI)
tsu(SI)
th(MI)
1
1
4
2
9
0
-
-
-
-
Data input setup time
Data input hold time
Slave mode
Master mode
Slave mode
-
-
th(SI)
-
-
ta(SO)
tdis(SO)
Data output access time Slave mode
Data output disable time Slave mode
13
1
27
5
Slave mode
ns
-
12.5
16
2.7<VDD<3.6 V
tv(SO)
Data output valid time
Data output hold time
Slave mode
-
-
12.5
17
3
-
1.62<VDD<3.6 V
tv(MO)
th(SO)
th(MO)
Master mode
1
-
Slave mode
10
0
1.62<VDD<3.6 V
Master mode
-
-
1. Guaranteed by characterization results.
Figure 99. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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(1)
Figure 100. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
(1)
Figure 101. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
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I2S Interface characteristics
Electrical characteristics (rev V)
2
Unless otherwise specified, the parameters given in Table 204 for I S are derived from tests
performed under the ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 120: General operating conditions, with the following
configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
2
(1)
Table 204. I S dynamic characteristics
Parameter Conditions
Symbol
Min
Max
Unit
fMCK
I2S main clock output
-
256x8K
256FS
MHz
Master data
-
64FS
fCK
I2S clock frequency
MHz
Slave data
-
64FS
tv(WS)
th(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
-
3
-
-
-
-
-
-
-
0
1
1
1
1
4
2
tsu(WS)
th(WS)
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
ns
Slave transmitter (after enable
edge)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
-
-
17
3
-
Data output valid time
Data output hold time
Master transmitter (after
enable edge)
Slave transmitter (after enable
edge)
9
0
Master transmitter (after
enable edge)
-
1. Guaranteed by characterization results.
DS12556 Rev 5
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2
(1)
Figure 102. I S slave timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 103. I S master timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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SAI characteristics
Electrical characteristics (rev V)
Unless otherwise specified, the parameters given in Table 205 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 120: General operating conditions, with the following
configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
IO Compensation cell activated.
Measurement points are done at CMOS levels: 0.5VDD
VOS level set to VOS1.
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
(1)
Table 205. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
SAI Main clock output
-
256x8K 256xFS
(3)
(3)
Master Data: 32 bits
Slave Data: 32 bits
-
-
128xFS
128xFS
MHz
SAI clock
fCK
frequency(2)
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(1)
Table 205. SAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode
2.7≤VDD≤3.6
-
13
tv(FS)
FS valid time
Master mode
1.62≤VDD≤3.6
-
20
tsu(FS)
th(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
8
1
-
-
-
-
-
-
-
Slave mode
1
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
0.5
1
Data input setup time
Data input hold time
3.5
2
Slave transmitter (after enable
edge)
-
14
ns
2.7≤VDD≤3.6
tv(SD_B_ST) Data output valid time
th(SD_B_ST) Data output hold time
tv(SD_A_MT) Data output valid time
Slave transmitter (after enable
edge)
-
9
-
20
-
1.62≤VDD≤3.6
Slave transmitter (after enable
edge)
Master transmitter (after enable
edge)
12
2.7≤VDD≤3.6
Master transmitter (after enable
edge)
-
19
-
1.62≤VDD≤3.6
Master transmitter (after enable
edge)
th(SD_A_MT) Data output hold time
7.5
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
302/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 104. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 105. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
MDIO characteristics
Table 206. MDIO Slave timing parameters
Symbol
Parameter
Min
Typ
Max
Unit
FMDC
td(MDIO)
tsu(MDIO)
th(MDIO)
Management Data Clock
-
-
10
-
30
19
-
MHz
Management Data Iput/output output valid time
Management Data Iput/output setup time
Management Data Iput/output hold time
8
1
1
ns
-
-
DS12556 Rev 5
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 106. MDIO Slave timing diagram
tMDC)
td(MDIO)
tsu(MDIO)
th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 207 and Table 208 for SDIO are
derived from tests performed under the ambient temperature, f frequency and VDD
PCLKx
supply voltage summarized in Table 120: General operating conditions, with the following
configuration:
Output speed is set to OSPEEDRy[1:0] = 0x11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics.
(1)(2)
Table 207. Dynamics characteristics: SD / MMC characteristics, V =2.7 to 3.6 V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
0
-
-
133
MHz
-
-
-
8/3
fPP =52MHz
fPP =52MHz
8.5
8.5
9.5
9.5
-
-
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
-
1.5
1.5
3
-
-
-
-
-
-
ns
-
(4)
tIDW
Input valid window (variable window)
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode
tOV
tOH
Output valid time HS
Output hold time HS
-
-
-
3.5
-
5
-
ns
2
304/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
(1)(2)
Table 207. Dynamics characteristics: SD / MMC characteristics, V =2.7 to 3.6 V
(continued)
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D inputs (referenced to CK) in SD default mode
Input setup time SD
Input hold time SD
-
-
1.5
1.5
-
-
tISUD
tIHD
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time SD
Output hold default time SD
-
-
-
0.5
-
2
-
ns
0
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. An external voltage converter is required to support SD 1.8 V.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
(1)(2)
Unit
Table 208. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V
Symbol
Parameter
Conditions
Min
Typ
Max
Clock frequency in data transfer
mode
fPP
-
0
-
120
MHz
-
-
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
-
8/3
tW(CKL)
tW(CKH)
fPP =52 MHz
fPP =52 MHz
8.5
8.5
9.5
9.5
-
-
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
1
-
-
-
-
2.5
Input valid window (variable
window)
(3)
tIDW
-
3.5
-
-
CMD, D outputs (referenced to CK) in eMMC mode
tOVD
tOHD
Output valid time HS
Output hold time HS
-
-
-
5
-
7
-
3
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 107. SDIO high-speed mode
Figure 108. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
Figure 109. DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
306/334
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
USB OTG_HS characteristics
Electrical characteristics (rev V)
Unless otherwise specified, the parameters given in Table 209 for ULPI are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
summarized in Table 120: General operating conditions, with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics.
(1)
Table 209. Dynamics characteristics: USB ULPI
Symbol
Parameter
Condition
Min Typ Max Unit
Control in (ULPI_DIR , ULPI_NXT) setup
time
tSC
-
2.5
2
-
-
-
-
Control in (ULPI_DIR, ULPI_NXT) hold
time
tHC
-
tSD
tHD
Data in setup time
Data in hold time
-
-
2.5
0
-
-
-
-
ns
2.7<VDD<3.6 V
CL=20 pF
-
-
9
9
9.5
14
t
DC/tDD
Control/Datal output delay
1.71<VDD<3.6 V
CL=15 pF
1. Guaranteed by characterization results.
Figure 110. ULPI timing diagram
Clock
t
t
HC
SC
Control In
(ULPI_DIR,
ULPI_NXT)
t
t
HD
SD
data In
(8-bit)
t
t
DC
DC
Control out
(ULPI_STP)
t
DD
data out
(8-bit)
ai17361c
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Ethernet interface characteristics
Unless otherwise specified, the parameters given in Table 210, Table 211 and Table 212 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
f
frequency and V supply voltage conditions summarized in Table 120: General
rcc_c_ck
DD
operating conditions, with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics:
(1)
Table 210. Dynamics characteristics: Ethernet MAC signals for SMI
Symbol
Parameter
Min
Typ
Max
Unit
tMDC
MDC cycle time( 2.5 MHz)
Write data valid time
Read data setup time
Read data hold time
400
0.5
12.5
0
400
403
Td(MDIO)
tsu(MDIO)
th(MDIO)
1.5
4
-
ns
-
-
-
1. Guaranteed by characterization results.
Figure 111. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
ETH_MDIO(I)
tsu(MDIO)
th(MDIO)
MS31384V1
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
(1)
Table 211. Dynamics characteristics: Ethernet MAC signals for RMII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(CRS)
tih(CRS)
td(TXEN)
td(TXD)
Receive data setup time
Receive data hold time
2
2
-
-
-
-
Carrier sense setup time
Carrier sense hold time
1.5
1.5
7
-
-
ns
-
-
Transmit enable valid delay time
Transmit data valid delay time
8
9
9.5
11
8
1. Guaranteed by characterization results.
Figure 112. Ethernet RMII timing diagram
RMII_REF_CLK
t
t
d(TXEN)
d(TXD)
RMII_TX_EN
RMII_TXD[1:0]
t
t
t
t
su(RXD)
su(CRS)
ih(RXD)
ih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
(1)
Table 212. Dynamics characteristics: Ethernet MAC signals for MII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(DV)
tih(DV)
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
2
-
-
-
2
-
1.5
1.5
1.5
0.5
9
-
-
-
-
-
ns
tsu(ER)
tih(ER)
td(TXEN)
td(TXD)
Error setup time
-
Error hold time
-
-
Transmit enable valid delay time
Transmit data valid delay time
10
9.5
11
12.5
8.5
1. Guaranteed by characterization results.
DS12556 Rev 5
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 113. Ethernet MII timing diagram
MII_RX_CLK
t
t
t
t
t
su(RXD)
su(ER)
ih(RXD)
ih(ER)
ih(DV)
t
su(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
t
t
d(TXEN)
d(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 213 and Table 214 for
JTAG/SWD are derived from tests performed under the ambient temperature, f
rcc_c_ck
frequency and V supply voltage summarized in Table 120: General operating conditions,
DD
with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 0x10
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics:
Table 213. Dynamics JTAG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7V <VDD< 3.6 V
-
-
-
-
37
TCK clock frequency
1/tc(TCK)
tisu(TMS)
tih(TMS)
tisu(TDI)
tih(TDI)
1.62 <VDD< 3.6 V
27.5
MHz
TMS input setup time
TMS input hold time
TDI input setup time
TDI input hold time
-
2.5
1
-
-
-
-
-
-
1.5
1
-
-
-
-
-
-
-
-
-
-
2.7V <VDD< 3.6 V
1.62 <VDD< 3.6 V
-
-
8
8
-
13.5
18
-
tov(TDO)
toh(TDO)
TDO output valid time
TDO output hold time
-
7
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DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 214. Dynamics SWD characteristics:
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7V <VDD< 3.6 V
-
-
-
-
71
52.5
-
SWCLK clock frequency
MHz
1/tc(SWCLK)
tisu(SWDIO)
tih(SWDIO)
1.62 <VDD< 3.6 V
SWDIO input setup time
SWDIO input hold time
-
2.5
1
-
-
-
-
-
-
-
2.7V <VDD< 3.6 V
1.62 <VDD< 3.6 V
-
8.5
14
tov(SWDIO)
SWDIO output valid time
SWDIO output hold time
-
8.5
-
19
-
-
-
toh(SWDIO)
-
8
Figure 114. JTAG timing diagram
tc(TCK)
TCK
TDI/TMS
TDO
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL)
tw(TCKH)
tov(TDO)
toh(TDO)
MSv40458V1
Figure 115. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL)
tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
DS12556 Rev 5
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com. ECOPACK
is an ST trademark.
8.1
LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 116. LQFP100 package outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
75
C
D
D1
D3
L
L1
51
50
76
100
26
PIN 1
IDENTIFICATION
25
1
e
1L_ME_V5
1. Drawing is not to scale.
DS12556 Rev 5
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 215. LQPF100 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
15.800
13.800
-
16.200
14.200
-
0.6220
0.5433
-
0.6378
0.5591
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0.0°
-
7.0°
0.0°
7.0°
ccc
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
312/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
Figure 117. LQFP100 recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
DS12556 Rev 5
313/334
331
Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Device marking for LQFP100
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 118. LQFP100 marking example (package top view)
Product identification(1)
STM32H750
VBT6 R
Revision code
Date code
YWW
Pin 1
indentifier
MSv62430V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
314/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
8.2
LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 119. LQFP144 package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
108
73
109
72
37
144
1
36
PIN 1
IDENTIFICATION
e
1A_ME_V4
1. Drawing is not to scale.
DS12556 Rev 5
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331
Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 216. LQFP144 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
316/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
Figure 120. LQFP144 package recommended footprint
1.35
108
73
109
72
0.35
0.5
19.9
17.85
22.6
144
37
1
36
19.9
22.6
ai14905e
1. Dimensions are expressed in millimeters.
DS12556 Rev 5
317/334
331
Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Device marking for LQFP144
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 121. LQFP144 marking example (package top view)
Revision code
Product identification(1)
R
STM32H750ZBT6
Date code
Y WW
Pin 1 identifier
MSv63961V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
318/334
DS12556 Rev 5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
8.3
LQFP176 package information
LQFP176 is a 176-pin, 24 x 24 mm low profile quad flat package.
Figure 122. LQFP176 package outline
Seating plane
C
0.25 mm
gauge plane
k
A1
L
HD
L1
PIN 1
IDENTIFICATION
D
ZE
E
HE
e
ZD
b
1T_ME_V2
1. Drawing is not to scale.
Table 217. LQFP176 package mechanical data
Dimensions
Ref.
Millimeters
Inches(1)
Typ.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
-
-
-
-
-
-
1.600
0.150
1.450
0.270
0.200
-
-
-
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.050
1.350
0.170
0.090
0.0020
0.0531
0.0067
0.0035
c
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 217. LQFP176 package mechanical data (continued)
Dimensions
Ref.
Millimeters
Typ.
Inches(1)
Typ.
Min.
Max.
Min.
Max.
D
HD
ZD
E
23.900
-
24.100
0.9409
-
0.9488
25.900
-
26.100
1.0197
-
1.0276
-
1.250
-
-
0.0492
-
23.900
-
24.100
0.9409
-
0.9488
HE
ZE
e
25.900
-
26.100
1.0197
-
1.0276
-
1.250
-
-
0.0492
-
-
0.500
-
0.750
-
-
0.0197
-
0.0295
-
L(2)
L1
k
0.450
-
0.0177
-
-
0°
-
1.000
-
0°
-
0.0394
-
-
7°
-
-
7°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
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Package information
Figure 123. LQFP176 package recommended footprint
1.2
176
1
133
132
0.5
0.3
44
45
89
88
1.2
21.8
26.7
1T_FP_V1
1. Dimensions are expressed in millimeters.
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Device marking for LQFP176
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 124. LQFP176 marking example (package top view)
Product identification(1)
STM32H750IBT6
Date code
Revision code
YWW
R
Pin 1identifier
MSv63962V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
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Package information
8.4
UFBGA176+25 package information
UFBGA176+25 is a 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package.
Figure 125. UFBGA176+25 package outline
Seating plane
C
A4
ddd
C
A
A3
A1
Z
A2
b
A1 ball
index
area
A
A1 ball
identifier
E
E1
e
Z
A
D1
D
e
B
R
15
1
Øb (176 + 25 balls)
BOTTOM VIEW
TOP VIEW
Ø eee M
Ø fff
C
C
A B
M
A0E7_ME_V8
1. Drawing is not to scale.
Table 218. UFBGA176+25 package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
-
-
0.600
-
-
0.0236
-
-
0.110
-
-
0.0043
-
0.130
0.450
0.320
0.290
10.000
9.100
10.000
9.100
0.650
0.450
-
-
-
0.0051
0.0177
0.0126
0.0114
0.3937
0.3583
0.3937
0.3583
0.0256
0.0177
-
-
-
-
-
-
-
-
-
-
0.240
0.340
0.0094
0.0134
D
9.850
10.150
0.3878
0.3996
D1
E
-
-
-
-
9.850
10.150
0.3878
0.3996
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
Z
-
ddd
0.080
0.0031
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 218. UFBGA176+25 package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
eee
fff
-
-
-
-
0.150
0.050
-
-
-
-
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 126. UFBGA176+25 package recommended footprint
Dpad
Dsm
A0E7_FP_V1
Table 219. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.65 mm
0.300 mm
0.400 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.300 mm
Between 0.100 mm and 0.125 mm
0.100 mm
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Device marking for UFBGA176+25
Package information
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 127. UFBGA176+25 marking example (package top view)
Revision code
R
Product identification(1)
STM32H750
IBK6
Date code
Ball A1
identifier
Y WW
MSv62431V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12556 Rev 5
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331
Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
8.5
TFBGA240+25 package information
TFBGA240+25 is a 265 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array
package.
Figure 128. TFBGA240+25 package outline
SEATING
PLANE
C
A1 ball identifier
D
D1
e
A
e
U
1
17
F
b (240 + 25 balls)
BOTTOM VIEW
TOP VIEW
A07U_ME_V2
1. Dimensions are expressed in millimeters.
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Package information
inches(1)
Table 220. TFBG240+25 ball package mechanical data
millimeters
Typ
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.100
-
-
0.0433
0.150
-
-
0.0059
-
-
-
0.760
0.400
14.000
12.800
14.000
12.800
0.800
0.600
0.600
-
-
-
0.0299
0.0157
0.5512
0.5039
0.5512
0.5039
0.0315
0.0236
0.0236
-
-
0.350
0.450
0.0138
0.0177
D
13.850
14.150
0.5453
0.5571
D1
E
-
-
-
-
13.850
14.150
0.5453
0.5571
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
-
G
-
-
ddd
eee
fff
0.100
0.150
0.080
0.0039
0.0059
0.0031
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 129. TFBGA240+25 package recommended footprint
Dpad
Dsm
A07U_FP_V2
1. Dimensions are expressed in millimeters.
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 221. TFBGA240+25 recommended PCB design rules (0.8 mm pitch)
Dimension Recommended values
Pitch
Dpad
0.8 mm
0.225 mm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
Device marking for TFBGA240+25
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 130. TFBGA240+25 marking example (package top view)
Product
identification(1)
STM32H750
XBH6
Revision code
R
Date code
Ball
A1identifier
Y WW
MSv62432V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
8.6
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × )
J
A
D
JA
Where:
T max is the maximum ambient temperature in C,
A
is the package junction-to-ambient thermal resistance, in C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
D
INT
I/O
D
INT I/O
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = (V × I ) + ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 222. Thermal characteristics
Parameter
Symbol
Definition
Value
Unit
Thermal resistance junction-ambient
45.0
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
43.7
43.0
37.4
36.6
36.3
38.3
43.0
19.3
24.3
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-ambient
JA
°C/W
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-board
JB
°C/W
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
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Package information
Symbol
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 222. Thermal characteristics
Definition
Parameter
Value
Unit
Thermal resistance junction-ambient
11.5
LQFP100 - 14 x 14 mm /0.5 mm pitch
Thermal resistance junction-ambient
11.3
11.2
23.9
7.4
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-case
JC
°C/W
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
8.6.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available from www.st.com.
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Ordering information
9
Ordering information
Example:
STM32 H
750
X
B
T
6
TR(1)
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
750 = STM32H750 value line with cryptographic
accelerator
Pin count
V = 100 pins
Z = 144 pins
I = 176 pins/balls
X = 240 balls
Flash memory size
B = 128 Kbytes
Package
T = LQFP ECOPACK2
K = UFBGA pitch 0.65 mm ECOPACK2
H = TFBGA ECOPACK2
Temperature range
6 = –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
1. The tape and reel packing is not available on all packages.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
DS12556 Rev 5
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Revision history
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
10
Revision history
Table 223. Document revision history
Changes
Date
Revision
21-May-2018
29-Jun-2018
1
Initial release.
Changed datasheet status to “production data”.
Added description of power-up and power-down phases in Section 3.5.1: Power supply
scheme.
Updated Table 44: HSI48 oscillator characteristics, Table 45: HSI oscillator
characteristics and Table 46: CSI oscillator characteristics.
2
Renamed Table 48 into “PLL characteristics (wide VCO frequency range)” and updated
note 2.. Added Table 49: PLL characteristics (medium VCO frequency range). Updated
tS_vbat in Table 92: VBAT monitoring characteristics.
Updated Table 97: OPAMP characteristics.
Changed maximum Arm Core-M7 frequency to 480 MHz.
Features:
– Changed operational amplifier bandwidth to 7.3 MHz
– Updated high-resolution timer to 2.1 ns
– Updated low-power consumption feature
Updated voltage scaling in Section 3.5.1: Power supply scheme. Added VOS0 in
Section 3.5.3: Voltage regulator.
Updated HSE clock in Section 3.7.1: Clock management.
Removed ETH_TX_ER from Table 7: STM32H750xB pin/ball definition.
Updated Section 6: Electrical characteristics (rev Y):
– Added note related to decoupling capacitor tolerance below Figure 11: Power supply
scheme.
– Added note 2. related to CEXT in Table 23: VCAP operating conditions.
– Updated note 2 below Figure 19: Recommended NRST pin protection.
– Updated fHSI48 in Table 44: HSI48 oscillator characteristics.
05-Apr-2019
3
– Updated tstab in Table 45: HSI oscillator characteristics.
– Removed note 2 in Table 49: PLL characteristics (medium VCO frequency range).
– Added Table 60: Output voltage characteristics for PC13, PC14, PC15 and PI8.
– Added note related to PC13, PC14, PC15 an PI8 limited frequency in Table 61:
Output timing characteristics (HSLV OFF).
– Updated Tcoeff in Table 89: VREFBUF characteristics.
– Table 85: ADC characteristics: updated fS and added note related to fS formula;
updated tCAL
.
– Renamed Section 6.3.24 into Temperature and VBAT monitoring and content
updated.
– Updated fDFSDMCLK in Table 98: DFSDM measured timing - 1.62-3.6 V.
Added Section 7: Electrical characteristics (rev V).
Updated paragraph introducing all package marking schematics to add the new
sentence “The printed markings may differ depending on the supply chain”. Updated
Table 222: Thermal characteristics. Added note related to ECOPACK®2 compliance in
Section 9: Ordering information.
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Table 223. Document revision history
Revision history
Date
Revision
Changes
Updated Figure 1: STM32H750xB block diagram
Updated Table 7: STM32H750xB pin/ball definition.
Updated Table 8 to Table 18 (alternate functions).
Updated Table 37: Peripheral current consumption in Run mode.
Updated Table 135: Peripheral current consumption in Run mode.
Updated Table 182: ADC characteristics.
24-Apr-2019
4
Updated Table 183: Minimum sampling time vs RAIN.
Updated Table 184: ADC accuracy.
Added device marking examples for all packages in Section 8: Package information
Added LQFP144 package together with STM32H750ZB part number, and LQFP176
package.
In Table 1: STM32H750xB features and peripheral counts, split number of ADC
channels into Direct, Fast and Slow channels; and added number of wakeup and tamper
pins.
Moved LSI from Backup to VDD domain in Figure 11 and Figure 64.
Updated capacitor value for 1.62 V<DD<1.8 V and FMC_CLK =100 MHz in Section :
SDRAM waveforms and timings.
Updated Section 6.2 and Section 7.2 introduction to device mission profile.
Power dissipation (PD) removed from Tables General operating conditions since this
parameter is redundant with JA thermal resistance.
Updated maximum frequency for condition “All peripherals disabled and VOS2”
Table 128: Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory, cache ON, LDO regulator ON
22-Nov-2019
5
Updated condition related to f
in Section : On-chip peripheral current
rcc_c_ck
consumption.
Updated Table 179: QUADSPI characteristics in SDR mode, Figure 35: Quad-SPI
timing diagram - DDR mode and Figure 87: Quad-SPI timing diagram - DDR mode.
Updated fDFSDMCLK maximum value in Table 98: DFSDM measured timing - 1.62-3.6 V
and Table 196: DFSDM measured timing - 1.62-3.6 V.
Updated notes 4. and 5. in Table 183: Minimum sampling time vs RAIN.
Updated Figure 128: TFBGA240+25 package outline.
Added note related to the availability of tape and reel packing in Section 9: Ordering
information.
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
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