STM32H755XIK6TR [STMICROELECTRONICS]
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, crypto;
| 型号： | STM32H755XIK6TR |
| 厂家： | 
ST |
| 描述： | Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, crypto |
| 文件： | 总252页 (文件大小：3438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32H755xI
Dual 32-bit Arm® Cortex®-M7 up to 480MHz and -M4 MCUs, 2MB
Flash, 1MB RAM, 46 com. and analog interfaces, SMPS, crypto
Datasheet - production data
Features
FBGA
FBGA
Dual core
UFBGA176+25
(10x10 mm)
LQFP144
(20x20 mm)
LQFP176
(24x24 mm)
LQFP208
®
®
TFBGA240+25
(14x14 mm)
• 32-bit Arm Cortex -M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
(28x28 mm)
Reset and power management
®
®
• 32-bit Arm 32-bit Cortex -M4 core with FPU,
Adaptive real-time accelerator (ART
• 3 separate power domains which can be
independently clock-gated or switched off:
Accelerator™) for internal Flash memory and
external memories, frequency up to 240 MHz,
MPU, 300 DMIPS/1.25 DMIPS /MHz
– D1: high-performance capabilities
– D2: communication peripherals and timers
– D3: reset/clock control/power management
(Dhrystone 2.1), and DSP instructions
• 1.62 to 3.6 V application supply and I/Os
• POR, PDR, PVD and BOR
Memories
• 2 Mbytes of Flash memory with read-while-
• Dedicated USB power embedding a 3.3 V
write support
internal regulator to supply the internal PHYs
• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
• Embedded regulator (LDO) to supply the digital
circuitry
• High power-efficiency SMPS step-down
converter regulator to directly supply V
and/or external circuitry
CORE
• Dual mode Quad-SPI memory interface
• Voltage scaling in Run and Stop mode (6
running up to 133 MHz
configurable ranges)
• Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
• Backup regulator (~0.9 V)
• Voltage reference for analog peripheral/V
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 125 MHz in
Synchronous mode
REF+
• 1.2 to 3.6 V V
supply
BAT
• Low-power modes: Sleep, Stop, Standby and
supporting battery charging
• CRC calculation unit
V
BAT
Security
Low-power consumption
• ROP, PC-ROP, active tamper, secure firmware
• V
battery operating mode with charging
capability
BAT
upgrade support, Secure access mode
• CPU and domain power state monitoring pins
General-purpose input/outputs
• 2.95 µAin Standby mode (Backup SRAM OFF,
• Up to 168 I/O ports with interrupt capability
RTC/LSE ON)
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www.st.com
STM32H755xI
• 2× operational amplifiers (7.3 MHz bandwidth)
Clock management
• 1× digital filters for sigma delta modulator
• Internal oscillators: 64 MHz HSI, 48 MHz
(DFSDM) with 8 channels/4 filters
HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-48 MHz HSE,
Graphics
32.768 kHz LSE
• LCD-TFT controller up to XGA resolution
• 3× PLLs (1 for the system clock, 2 for kernel
• Chrom-ART graphical hardware Accelerator™
clocks) with Fractional mode
(DMA2D) to reduce CPU load
Interconnect matrix
• Hardware JPEG Codec
•
•
3 bus matrices (1 AXI and 2 AHB)
Up to 22 timers and watchdogs
Bridges (5× AHB2-APB, 2× AXI2-AHB)
• 1× high-resolution timer (2.1 ns max
4 DMA controllers to unload the CPU
resolution)
• 1× high-speed master direct memory access
• 2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
controller (MDMA) with linked list support
• 2× dual-port DMAs with FIFO
• 2× 16-bit advanced motor control timers (up to
• 1× basic DMA with request router capabilities
240 MHz)
Up to 35 communication peripherals
• 10× 16-bit general-purpose timers (up to
240 MHz)
• 4× I2Cs FM+ interfaces (SMBus/PMBus)
• 5× 16-bit low-power timers (up to 240 MHz)
• 4× watchdogs (independent and window)
• 2× SysTick timers
• 4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
• 6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
• RTC with sub-second accuracy and hardware
calendar
• 4x SAIs (serial audio interface)
• SPDIFRX interface
Cryptographic acceleration
• AES 128, 192, 256, TDES,
• SWPMI single-wire protocol master I/F
• MDIO Slave interface
• HASH (MD5, SHA-1, SHA-2), HMAC
• True random number generators
• 2× SD/SDIO/MMC interfaces (up to 125 MHz)
• 2× CAN controllers: 2 with CAN FD, 1 with
Debug mode
time-triggered CAN (TT-CAN)
• SWD & JTAG interfaces
• 4-Kbyte Embedded Trace Buffer
• 2× USB OTG interfaces (1FS, 1HS/FS) crystal-
less solution with LPM and BCD
• Ethernet MAC interface with DMA controller
• HDMI-CEC
96-bit unique ID
Optional support of extended temperature
range up to 125 °C (specific part numbers)
• 8- to 14-bit camera interface (up to 80 MHz)
11 analog peripherals
All packages are ECOPACK®2 compliant
Table 1. Device summary
• 3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
Reference
Part number
• 1× temperature sensor
STM32H755ZI, STM32H755II,
STM32H755BI, STM32H755XI
• 2× 12-bit D/A converters (1 MHz)
• 2× ultra-low-power comparators
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Dual Arm® Cortex® cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
®
®
3.1.1
3.1.2
Arm Cortex -M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
®
®
Arm Cortex -M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2
3.3
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.1
3.3.2
3.3.3
3.3.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ART™ accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.1
3.5.2
3.5.3
3.5.4
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Voltage regulator (SMPS step-down converter and LDO) . . . . . . . . . . . 27
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6
3.7
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.1
3.7.2
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8
3.9
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 33
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 33
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 33
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 34
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3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.19
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 37
3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28 Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 40
3.29 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.29.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.29.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 44
3.29.6 Independent watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.7 Window watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.30 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 45
3.31 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.32 Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
3.33 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.34 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 48
3.35 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.36 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.37 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 49
3.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 50
3.39 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 50
3.40 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 50
3.41 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 51
3.42 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 51
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3.43 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.44 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4
5
6
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 114
Embedded reset and power control block characteristics . . . . . . . . . . 115
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 137
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 150
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.18 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
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6.3.19 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.20 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.3.21 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.22 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.25 Temperature and V
monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
BAT
6.3.26 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3.27 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.28 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.29 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 203
6.3.30 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 206
6.3.31 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 207
6.3.32 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.3.33 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.1
7.2
7.3
7.4
7.5
7.6
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.6.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
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List of tables
List of tables
Table 1.
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32H755xI features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
STM32H755xI pin/ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Port I alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 111
VCAP operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Characteristics of SMPS step-down converter external components. . . . . . . . . . . . . . . . 113
SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 114
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 114
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
(ART accelerator ON), LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4,
ART accelerator ON, SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache ON,
ART accelerator ON, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache OFF,
Table 32.
Table 33.
Table 34.
ART accelerator OFF, LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, LDO regulator ON . . . . . . . . . . . . . . . 120
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, SMPS regulator. . . . . . . . . . . . . . . . . 121
Typical and maximum current consumption in Run mode, code with data processing
Table 35.
Table 36.
Table 37.
DS12919 Rev 1
7/252
10
List of tables
STM32H755xI
running from Flash memory, only Arm Cortex-M7 running, cache ON,
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache OFF,
Table 38.
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical and maximum current consumption batch acquisition mode,
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,
Table 39.
Table 40.
LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Typical and maximum current consumption in Run mode, code with data processing
running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,
Table 41.
SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 124
Typical and maximum current consumption in Stop, SMPS regulator . . . . . . . . . . . . . . . 125
Typical and maximum current consumption in Sleep mode, LDO regulator ON . . . . . . . 126
Typical and maximum current consumption in Sleep mode, SMPS regulator . . . . . . . . . 126
Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 127
Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
PLL characteristics (wide VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 147
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 154
Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 155
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 161
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 161
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 163
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 163
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 165
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
8/252
DS12919 Rev 1
STM32H755xI
List of tables
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 166
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 172
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 177
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
QUADSPI characteristics in DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Delay Block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 100. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 101. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 102. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 103. V
Table 104. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
BAT
BAT
Table 105. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 106. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 107. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 108. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 109. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 110. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 111. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 112. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 113. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 114. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 115. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 116. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
2
Table 117. I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 118. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 119. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 120. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 221
Table 121. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V. . . . . . . . . . . . . . . 222
Table 122. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 123. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 124. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 125. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 126. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 127. Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 128. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 129. LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 130. LQFP208 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 131. UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 132. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA). . . . . . . . . . . . . 243
DS12919 Rev 1
9/252
10
List of tables
STM32H755xI
Table 133. TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 134. TFBGA240+25 recommended PCB design rules (0.8 mm pitch). . . . . . . . . . . . . . . . . . . 247
Table 135. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 136. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
10/252
DS12919 Rev 1
STM32H755xI
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32H755xI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA240+25 ball assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ART™ accelerator schematic and environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32H755xI bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 10. TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 15. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
EXT
Figure 16. External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C. . . . . . . . . . 128
Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . 128
Figure 19. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = 30 °C. . . . . 129
Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 130
Figure 21. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 22. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 23. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 24. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 25. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 26. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 27. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 160
Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 162
Figure 29. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 30. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 31. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 32. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 33. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 34. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 35. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 36. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 176
Figure 37. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 177
Figure 38. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 39. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 40. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 41. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 42. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 43. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 44. Power supply and reference decoupling (V
Figure 45. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 192
). . . . . . . . . . . . . . . . 192
REF+
DDA
connected to V
REF+
DDA
Figure 46. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 47. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 48. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
DS12919 Rev 1
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12
List of figures
STM32H755xI
Figure 49. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 50. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 51. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 52. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 53. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
(1)
Figure 54. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
(1)
Figure 55. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
2
(1)
Figure 56. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
2
(1)
Figure 57. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 58. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 59. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 60. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 61. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 62. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 63. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 64. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 65. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 66. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 67. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 68. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 69. SWD timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 70. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 71. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 72. LQFP144 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 73. LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 74. LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 75. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 76. LQFP208 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 77. LQFP208 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 78. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 79. UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 80. UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 81. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 82. TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 83. TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 84. TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
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DS12919 Rev 1
STM32H755xI
Introduction
1
Introduction
This document provides information on STM32H755xI microcontrollers, such as description,
functional overview, pin assignment and definition, electrical characteristics, packaging, and
ordering information.
This document should be read in conjunction with the STM32H755xI reference manual
(RM0399), available from the STMicroelectronics website www.st.com.
®(a)
®
®
®
For information on the Arm
Cortex -M7 core and Arm Cortex -M4 core, please refer to
®
the Cortex -M7 Technical Reference Manual, available from the http://www.arm.com
website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12919 Rev 1
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54
Description
STM32H755xI
2
Description
®
®
®
STM32H755xI devices are based on the high-performance Arm Cortex -M7 and Cortex -
®
®
M4 32-bit RISC cores. The Cortex -M7 core operates at up to 480 MHz and the Cortex -
M4 core at up to 240 MHz. Both cores feature a floating point unit (FPU) which supports
Arm single- and double-precision (Cortex -M7 core) operations and conversions (IEEE
754 compliant), including a full set of DSP instructions and a memory protection unit (MPU)
to enhance application security.
®
®
STM32H755xI devices incorporate high-speed embedded memories with a dual-bank Flash
memory of 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to
864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of
enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB
bus matrix and a multi layer AXI interconnect supporting internal and external memory
access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG), and a cryptographic
acceleration cell. The devices support four digital filters for external sigma-delta modulators
(DFSDM). They also feature standard and advanced communication interfaces.
•
Standard peripherals
2
–
–
–
Four I Cs
Four USARTs, four UARTs and one LPUART
2
2
Six SPIs, three I Ss in Half-duplex mode. To achieve audio class accuracy, the I S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
–
–
–
–
–
–
Four SAI serial audio interfaces
One SPDIFRX interface
One SWPMI (Single Wire Protocol Master Interface)
Management Data Input/Output (MDIO) slaves
Two SDMMC interfaces
A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
–
–
–
–
One FDCAN plus one TT-FDCAN interface
An Ethernet interface
™
Chrom-ART Accelerator
HDMI-CEC
•
Advanced peripherals including
–
–
–
–
–
A flexible memory control (FMC) interface
A Quad-SPI Flash memory interface
A camera interface for CMOS sensors
An LCD-TFT display controller
A JPEG hardware compressor/decompressor
Refer to Table 1: STM32H755xI features and peripheral counts for the list of peripherals
available on each part number.
14/252
DS12919 Rev 1
STM32H755xI
Description
STM32H755xI devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V
power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
V
. Otherwise the supply voltage must stay above 1.71 V with the embedded power
SS
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages to
allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H755xI devices are offered in 5 packages ranging from 144 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H755xI microcontrollers suitable for a wide range of
applications:
•
•
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile applications, Internet of Things
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
Table 1. STM32H755xI features and peripheral counts
STM32H755
XI
Peripherals
STM32H755ZI STM32H755II STM32H755BI
Flash memory in Kbytes
2 x 1 Mbyte
SRAM mapped onto AXI bus
512
128
128
32
SRAM1 (D2 domain)
SRAM2 (D2 domain)
SRAM3 (D2 domain)
SRAM4 (D3 domain)
ITCM RAM (instruction)
DTCM RAM (data)
SRAM in Kbytes
64
64
TCM RAM in
Kbytes
128
4
Backup SRAM (Kbytes)
FMC
Yes
General-purpose input/outputs
Quad-SPI
97
119/128
148
168
Yes
Yes
Ethernet
DS12919 Rev 1
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54
Description
STM32H755xI
STM32H755
Table 1. STM32H755xI features and peripheral counts (continued)
Peripherals STM32H755ZI STM32H755II STM32H755BI
High-resolution
XI
1
10
2
General-purpose
Advanced-control (PWM)
Basic
Timers
2
Low-power
5
Wakeup pins
Tamper pins
4
2
6
3
Random number generator
Yes
Yes
6/3(1)
4
Cryptographic accelerator
SPI / I2S
I2C
USART/ UART/
LPUART
4/4/
1
SAI
4
4 inputs
Yes
Yes
2
SPDIFRX
Communication
interfaces
SWPMI
MDIO
SDMMC
FDCAN/TT-FDCAN
USB OTG_FS
USB OTG_HS
1/1
Yes
Yes
Yes
Yes
Yes
Yes
3
Ethernet and camera interface
LCD-TFT
JPEG Codec
Chrom-ART Accelerator™ (DMA2D)
16-bit ADCs
Number of Direct channels
Number of Fast channels
Number of Slow channels
2
6
2
9
4
9
2
9
4
9
15
17
23
21
23
12-bit DAC
Yes
2
Number of channels
Comparators
Operational amplifiers
DFSDM
2
2
Yes
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DS12919 Rev 1
STM32H755xI
Description
Table 1. STM32H755xI features and peripheral counts (continued)
STM32H755
XI
Peripherals
STM32H755ZI STM32H755II STM32H755BI
480 MHz(2)
400 MHz(3)
Maximum CPU frequency
Operating voltage
300 MHz(4)
1.62 to 3.6 V(5)
–40 up to +85 °C(6)
–40 to + 125 °C
–40 to + 125 °C(4)(7)
Ambient temperature
Junction temperature
Ambient temperature
Operating
temperatures
Extended
operating
Junction temperature
–40 to + 140 °C(8)
temperatures
UFBGA
LQFP
176
TFBGA240+
25
Package
LQFP144
176+
25
LQFP208
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. The product junction temperature must be kept within the –40 to +105 °C range.
3. The product junction temperature must be kept within the –40 to +125 °C range.
4. Up to 300 MHz for STM32H755xxx3 sales types (extended industrial temperature range).
5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
6. Using appropriate cooling methods to guarantee that the maximum junction temperature (125 °C) is not exceeded, the
maximum ambient temperature (85°C) can be exceeded.
7. The product junction temperature must be kept within the –40 to +140 °C range.
8. It is mandatory to use the SMPS step-down converter when the maximum junction temperature is higher than 125 °C.
DS12919 Rev 1
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54
Description
STM32H755xI
Figure 1. STM32H755xI block diagram
DP, DM, STP,
SDMMC_
D[7:0],
CMD, CK as AF
MII / RMII
MDIO
as AF
NXT,ULPI:CK DP, DM, ID,
To APB1-2
peripherals
, D[7:0], DIR,
ID, VBUS
VBUS
AHB1
(200MHz)
PHY
PHY
ETHER
MAC
I-
D-
TCM
64KB
D-
OTG_HS OTG_FS
DMA1 DMA2
8 Stream 8 Stream
SDMMC2
FIFO
Arm
Cortex
M4
D- S-
Bus Bus Bus
TCM
64KB
TCM
64KB
DMA/
FIFO
DMA/
FIFO
DMA
I-
FIFOs
FIFOs
AXI/AHB12 (200MHz)
AHBP
JTDO/SWD, JTDO
JTRST, JTDI,
JTCK/SWCLK
1 MB
FLASH
1 MB
Arm
JTAG/SW
ETM
Cortex
M7
32-bit AHB BUS-MATRIX
AXIM
TRACECK
TRACED[3:0]
FLASH
DMA
Mux1
I-Cache
16KB
D-Cache
16KB
SRAM1 SRAM2 SRAM3
128 KB 128 KB 32 KB
512 KB AXI
SRAM
AHBS
RNG
HASH
ADC1
FMC
16 Streams
FIFO
Up to 20 analog inputs
common to ADC1 & 2
MDMA
ADC2
FMC_signals
Quad-SPI
CLK, CS,D[7:0]
CHROM-ART
(DMA2D)
AHB/APB
3DES/AES
FIFO
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE,
LCD_CLK
TIM2
TIM3
TIM4
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels
32b
16b
16b
LCD-TFT FIFO
WWDG1 JPEG
TIM6
TIM7
16b
16b
AXI/AHB34 (200MHz)
AHB/APB
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
SWPMI
TIM5
TIM12
TIM13
TIM14
32b
16b
16b
16b
FIFO
SDMMC1
2 channels as AF
1 channel as AF
ART
(instruction cache)
1 channel as AF
AHB ART (200MHz)
smcard
RX, TX, SCK, CTS,
RTS as AF
AHB2 (200MHz)
USART2
Delay block
DCMI
irDA
smcard
RX, TX, SCK
CTS, RTS as AF
USART3
HSYNC, VSYNC, PUIXCLK, D[13:0]
irDA
AHB/APB
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
UART4
UART5
RX, TX as AF
RX, TX as AF
HRTIM1
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
DFSDM1
UART7
RX, TX as AF
RX, TX as AF
SD, SCK, FS, MCLK as AF
SAI3
SAI2
SAI1
UART8
MOSI, MISO, SCK, NSS/SDO,
SDI, CK, WS, MCK, as AF
SD, SCK, FS, MCLK as AF
SPI2/I2S2
SPI3/I2S3
MOSI, MISO, SCK, NSS/SDO,
SDI, CK, WS, MCK, as AF
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
I2C1/SMBUS
I2C2/SMBUS
SCL, SDA, SMBAL as AF
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS as AF
DMA
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
SCL, SDA, SMBAL as AF
Mux2
AHB4
DAP
BDMA
I2C3/SMBUS
MDIOS
SCL, SDA, SMBAL as AF
MDC, MDIO
TX, RX
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
RAM
I/F
MOSI, MISO, SCK, NSS as AF
32-bit AHB BUS-MATRIX
64 KB SRAM
FDCAN1
FDCAN2
IWDG1
IWDG2
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
TX, RX
SPI/I2S1
smcard
CRS
RX, TX, SCK, CTS, RTS as AF
USART6
irDA
smcard
SPDIFRX1
IN[1:4] as AF
4 KB BKP
RX, TX, SCK, CTS, RTS as AF
USART1
irDA
RAM
HDMI-CEC
DAC1&2
CEC as AF
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR, BKIN as
AF
TIM1/PWM
TIM8/PWM
16b
16b
DAC1_OUT, DAC2_OUT as AF
HSEM
CRC
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
LPTIM1
16b
OPAMP1&2
OPAMPx_VINM
Up to 17 analog inputs
common to ADC1 and 2
WWDG2
@VDD33
OPAMPx_VINP
ADC3
OPAMPx_VOUT as AF
VDDREF_ADC
PA..J[15:0]
VDD12
@VSW
Tem. sensor
POWER MANAGEMENT
VDD = 1.62 to 3.6V
VDD33USB = 3.0 to 3.6V
VSS
RCC
Reset &
control
Voltage regulator
3.3 to 1.2V
SMPS step-down
converter
GPIO PORTA.. J
GPIO PORTK
VCAP
VDDMMC33 = 1.8 to 3.6V
VDDSMPS, VSSSMPS
VLXSMP, VFBSMPS,
PK[7:0]
AHB/APB
SD, SCK, FS, MCLK,
PDM_DI/CK[4:1] as AF
SAI4
OSC32_IN
OSC32_OUT
XTAL 32 kHz
COMPx_INP, COMPx_INM,
COMP1&2
LPTIM5
COMPx_OUT as AF
RTC
Backup registers
AWU
RTC_TS
@VDD
RTC_TAMP[1:3]
RTC_OUT
LPTIM5_OUT as AF
LPTIM4_OUT as AF
VREF
CSI
4 MHz CSI
RTC_REFIN
LPTIM4
LPTIM3
SYSCFG
48 MHz HSI48 RC
64 MHz HSI RC
32 KHz LSI RC
PLL1+PLL2+PLL3
RC48
HSI
LPTIM3_OUT as AF
SCL, SDA, SMBAL as AF
VBAT = 1.2 to 3.6 V
EXTI WKUP
@VDD
I2C4
SPI6
LSI
OSC_IN
OSC_OUT
XTAL OSC
4- 48 MHz
MISO, MOSI, SCK, NSS as AF
IWDG1
IWDG2
RX, TX, CK, CTS, RTS as AF
LPTIM2_OUT as AF
LPUART1
LPTIM2
@VDD
SUPPLY SUPERVISION
POR/PDR/BOR
POR
reset
Int
VDDA, VSSA
NRESET
WKUP[5:0]
PVD
MSv43742V14
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Description
Compatibility throughout the family
STM32H755xI devices are not pin-to-pin compatible with STM32H7x3 devices (single core
line):
•
The TFBGA240+25 ballout is compatible with STM32H7x3 devices, except for a few
I/O balls as shown in Figure 2.
•
LQFP208 and LQFP176 pinouts, as well as UFBGA176+25 ballout are not compatible
with STM32H7x3 devices.
Figure 2. TFBGA240+25 ball assignment differences
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VCAP
A
B
C
D
E
F
VSS
PI6
PI5
PI4
PB5
VDDLDO
PK5
PG10
PG9
PD5
PD4
PC10
PA15
PI1
PI0
VSS
VBAT
VSS
PI7
PE2
PE3
PC13
PI10
PF1
PI14
VSS
PF7
PF10
PC2
PA2
PH4
PA6
PA5
PA4
PE1
PE0
PB9
PI8
PB6
PB7
PB8
PE6
VDD
VDD
VDD
PF4
VDD
VDD
VDD
PA0
PI15
PA7
PB1
PB0
VSS
PB3
PB4
PK6
PK7
PK4
PK3
PG11
PG12
PG13
VDD
PJ15
VSS
PD6
PD7
PJ12
VDD
PD3
PC12
PD2
PC11
VSS
PD0
PC8
PC7
VDD
VDD
VDD
VDD
VDD
VDD
PJ8
PA14
PI3
PI2
PH15
PH14
PC15-
OSC32_
OUT
PC14-
OSC32_
IN
PA13
PA9
VSS VDDLDO
PE5
PE4
PG15
VDD
PG14
BOOT0
PJ14
PJ13
PA10
PC9
PC6
PG5
PG4
PK0
PH13
PA12
PG7
VSS
PG2
VSS
NC
VCAP
PA11
PDR
_ON
PI9
PD1
PA8
VDD33
USB
PI11
PF0
PF3
PF5
PF8
PF9
PC3
PA1
PH5
VSS
PC4
PC5
PG8
PG6
PG3
PK1
VDD50
USB
G
H
J
PF2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PI12
PI13
PK2
VSS
NC
PH1-
OSC_
OUT
PH0-
OSC_IN
K
L
NRST
VDDA
VREF+
VREF-
VSSA
PF6
PC0
PC1
PH2
PH3
PJ11
PJ10
PJ9
VSS
VSS
VSS
PJ6
NC
NC
M
N
P
R
T
NC
NC
PJ0
PJ1
PB2
PJ2
PJ3
VDD
PF13
PF12
PF11
PJ4
VDD
PF14
VSS
PG0
PG1
PE10
PE9
VDD
PE11
PE12
PE13
PE14
VDD
PB10
PE15
PH6
VDD
PB11
PJ5
PJ7
VSS
PD14
PD12
PD10
PD8
NC
PH10
PH9
PH8
PH11
PH12
PB12
PB13
PD15
PD11
PB15
PB14
VDD
PD13
PD9
VSS
PC2_C PC3_C
PF15
PE8
PA0_C
VSS
PA1_C
PA3
VSS
VCAP
U
PE7
VDDLDO PH7
STM32H7x5
STM32H7x3
VLX
PI9
PI9
NC
NC
SMPS
VDD
VSS
SMPS
VFB
NC
NC
SMPS
PF2
PF2
SMPS
MSv48801V2
1. The balls highlighted in gray correspond to different signals on STM32H755xI and STM32H7x3 devices.
DS12919 Rev 1
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54
Functional overview
STM32H755xI
3
Functional overview
®
®
3.1
Dual Arm Cortex cores
®
®
®
The industrial STM32H755xI devices embed two Arm cores, a Cortex -M7 and a Cortex -
®
M4. The Cortex -M4 offers optimal performance for real-time applications while the
Cortex -M7 core can execute high-performance tasks in parallel.
®
The two cores belong to separate power domains. This allows designing gradual high-
power efficiency solutions in combination with the low-power modes already available on all
STM32 microcontrollers.
®
®
3.1.1
Arm Cortex -M7 with FPU
®
®
The Arm Cortex -M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
®
The Cortex -M7 processor is a highly efficient high-performance featuring:
•
•
•
•
•
•
Six-stage dual-issue pipeline
Dynamic branch prediction
Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
64-bit AXI interface
64-bit ITCM interface
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
•
AXI Bus interface to optimize Burst transfers
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H755xI family.
®
®
Note:
Cortex -M7 with FPU core is binary compatible with the Cortex -M4 core.
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DS12919 Rev 1
STM32H755xI
Functional overview
®
®
3.1.2
Arm Cortex -M4 with FPU
®
®
The Arm Cortex -M4 processor is a high-performance embedded processor which
supports DSP instructions. It was developed to provide an optimized power consumption
MCU, while delivering outstanding computational performance and low interrupt latency.
®
®
The Arm Cortex -M4 processor is a highly efficient MCU featuring:
•
•
•
•
•
3-stage pipeline with branch prediction
Harvard architecture
32-bit System (S-BUS) interface
32-bit I-BUS interface
32-bit D-BUS interface
®
®
The Arm Cortex -M4 processor also features a dedicated hardware adaptive real-time
™
accelerator (ART Accelerator ). This is an instruction cache memory composed of sixty-
four 256-bit lines, a 256-bit cache buffer connected to the 64-bit AXI interface and a 32-bit
interface for non-cacheable accesses.
3.2
Memory protection unit (MPU)
The devices feature two memory protection units. Each MPU manages the CPU access
rights and the attributes of the system resources. It has to be programmed and enabled
before use. Its main purposes are to prevent an untrusted user program to accidentally
corrupt data used by the OS and/or by a privileged task, but also to protect data processes
or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
DS12919 Rev 1
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54
Functional overview
STM32H755xI
3.3
Memories
3.3.1
Embedded Flash memory
The STM32H755xI devices embed 2 Mbytes of Flash memory that can be used for storing
programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•
•
One Flash word (8 words, 32 bytes or 256 bits)
10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
•
1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes
(4 K Flash memory words)
•
128 Kbytes of System Flash memory from which the device can boot
2 Kbytes (64 Flash words) of user option bytes for user configuration
•
3.3.2
Secure access mode
In addition to other typical memory protection mechanism (RDP, PCROP), STM32H755xI
devices introduce the Secure access mode, a new enhanced security feature. This mode
allows developing user-defined secure services by ensuring, on the one hand code and
data protection and on the other hand code safe execution.
Two types of secure services are available:
•
STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
•
User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure
services are proprietary user firmware update solution, secure Flash integrity check or
any other sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user Flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
®
The above secure services are available only for Cortex -M7 core operating in Secure
access mode. The other masters cannot access the option bytes involved in Secure access
mode settings or the Flash secured areas.
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STM32H755xI
Functional overview
3.3.3
Embedded SRAM
All devices feature around 1 Mbyte of RAM with hardware ECC. The RAM is divided as
follows:
•
•
•
•
•
•
512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
SRAM1 mapped on D2 domain: 128 Kbytes
SRAM2 mapped on D2 domain: 128 Kbytes
SRAM3 mapped on D2 domain: 32 Kbytes
SRAM4 mapped on D3 domain: 64 Kbytes
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or V
mode.
BAT
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
®
®
from the Arm Cortex -M7 CPU or the MDMA (even in Sleep mode) through a specific
®
AHB slave of the Cortex -M7(AHBS):
–
–
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
®
real-times routines by the Cortex -M7.
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
®
load/store operations) thanks to the Cortex -M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•
•
7 ECC bits are added per 32-bit word.
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
™
3.3.4
ART accelerator
™
The ART (adaptive real-time) accelerator block speeds up instruction fetch accesses of
®
the Cortex -M4 core from D1-domain internal memories (Flash memory bank 1, Flash
memory bank 2, AXI SRAM) and from D1-domain external memories attached via Quad-
SPI controller and Flexible memory controller (FMC).
™
The ART accelerator is a 256-bit cache line using 64-bit WRAP4 accesses from the 64-bit
AXI D1 domain. The acceleration is achieved by loading selected code into an embedded
®
cache and making it instantly available to Cortex -M4 core, thus avoiding latency due to
memory wait states.
DS12919 Rev 1
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54
Functional overview
STM32H755xI
Figure 3. shows the block schematic and the environment of the ART accelerator.
™
Figure 3. ART accelerator schematic and environment
AHB from D2 domain
D1 domain
ART accelerator
Non-cacheable
access path
Cacheable
access path
AHB switch
control
Detect of
instruction
fetch
write to cacheable page
Cache
Cache buffer
1 x 256-bit
cache cache
hit miss
non-
Cache
cacheable
access
manager
Cache memory
64 x 256-bit
cache
refill
AHB access
AXI access
Flash bank 1
Flash bank 2
AXI SRAM
QSPI
Legend
Control
32-bit bus
64-bit bus
Bus multiplexer
Master interface
Slave interface
FMC
AXI AHB
64-bit AXI bus matrix
MSv39757V2
3.4
Boot modes
By default, the boot codes are executed simultaneously by both cores. However, by
programming the appropriate Flash user option byte, it is possible to boot from one core
while clock-gating the other core.
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
•
All Flash address space
Flash memory and SRAMs (except for ITCM /DTCM RAMs which cannot be accessed
®
by the Cortex -M4 core)
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DS12919 Rev 1
STM32H755xI
Functional overview
The bootloader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5
Power supply management
3.5.1
Power supply scheme
STM32H755xI power supply voltages are the following:
•
V
pins.
= 1.62 to 3.6 V: external power supply for I/Os, provided externally through V
DD
DD
•
•
V
= 1.62 to 3.6 V: supply voltage for the internal regulator supplying V
DDLDO
CORE
V
= 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
DDA
OPAMP.
•
V
V
:
DD33USB and DD50USB
V
can be supplied through the USB cable to generate the V
via the
DD33USB
DD50USB
USB internal regulator. This allows supporting a V supply different from 3.3 V.
DD
The USB regulator can be bypassed to supply directly V
if V = 3.3 V.
DD
DD33USB
•
•
V
= 1.2 to 3.6 V: power supply for the V
domain when V is not present.
BAT
SW DD
V
: V
supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
CAP
CORE
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The V domain is split into the
CORE
following power domains that can be independently switch off.
®
–
D1 domain containing some peripherals and the Cortex -M7 core.
®
–
D2 domain containing a large part of the peripherals and the Cortex -M4 core.
D3 domain containing some peripherals and the system control.
= 1.62 V to 3.6 V: SMPS step-down converter power supply
–
•
V
V
V
V
DDSMPS
DDSMPS
LXSMPS
FBSMPS
must be kept at the same voltage level as V
.
DD
•
•
= SMPS step-down converter output coupled to an inductor.
= V , 1.8 V or 2.5 V external SMPS step-down converter feedback
CORE
voltage sense input.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 4):
•
When V is below 1 V, other power supplies (V
, V
, V ) must
DD50USB
DD
DDA
DD33USB
remain below V + 300 mV.
DD
•
When V is above 1 V, all power supplies are independent (except for V
,
DD
DDSMPS
which must remain at the same level as V ).
DD
During the power-down phase, V can temporarily become lower than other supplies only
DD
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
DS12919 Rev 1
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54
Functional overview
STM32H755xI
Figure 4. Power-up/power-down sequence
V
3.6
(1)
VDDX
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB
Operating mode
Power-down
time
VDDX < VDD + 300 mV
VDDX independent from VDD
MSv47490V1
.
2. VDD and VDDSMPS must be wired together into order to follow the same voltage sequence.
3.5.2
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors V power supply and compares it to a fixed threshold.
DD
The devices remain in Reset mode when V is below this threshold,
DD
•
Power-down reset (PDR)
The PDR supervisor monitors V power supply. A reset is generated when V drops
DD
DD
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
Brownout reset (BOR)
•
The BOR supervisor monitors V power supply. Three BOR thresholds (from 2.1 to
DD
2.7 V) can be configured through option bytes. A reset is generated when V drops
DD
below this threshold.
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DS12919 Rev 1
STM32H755xI
Functional overview
3.5.3
Voltage regulator (SMPS step-down converter and LDO)
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
•
Run mode (VOS0 to VOS3)
–
–
–
–
Scale 0: boosted performance (available only with LDO regulator)
Scale 1: high performance
Scale 2: medium performance and consumption
Scale 3: optimized performance and low-power consumption
Note:
For STM32H755xxx3 sales types (industrial temperature range) the voltage regulator output
can be set only to VOS2 or VOS3 in Run mode (VOS0 and VOS1 are not available for
industrial temperature range).
•
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
3.5.4
SMPS step-down converter
The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear
switching regulator that provides lower power consumption than a conventional voltage
regulator (LDO).
DS12919 Rev 1
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54
Functional overview
STM32H755xI
The SMPS step-down converter can be used for the following purposes:
•
Direct supply of the V
domain
CORE
–
the SMPS step-down converter operating modes follow the device system
operating modes (Run, Stop, Standby).
–
the SMPS step-down converter output voltage are set according to the selected
VOS and SVOS bits (voltage scaling)
•
Delivery of an intermediate voltage level to supply the internal voltage regulator (LDO)
–
SMPS step-down converter operating modes
When the SDEXTHP bit is equal to 0 in the PWR_CR3 register, the SMPS step-
down converter follows the device system operating modes (Run, Stop and
Standby).
When the SDEXTHP bit is equal to 1 in PWR_CR3, the SMPS step-down
converter is forced to High-performance mode and does not follow the device
system operating modes (Run, Stop and Standby).
–
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the
selected SD level
•
Delivery of an external supply
–
The SMPS step-down converter is forced to High-performance mode (provided
SDEXTHP bit is equal to 1 in PWR_CR3)
–
The SMPS step-down converter output equals 1.8 V or 2.5 V according to the
selected SD level
3.6
Low-power strategy
There are several ways to reduce power consumption on STM32H755xI:
•
Select the SMPS step-down converter as V
enhance power efficiency.
supply voltage source, as it allows to
CORE
•
•
Select the adequate voltage scaling
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode, and by individually clock gating the peripherals that are not used.
•
Save power consumption when one or both CPUs are idle, by selecting among the
available low-power mode according to the user application needs. This allows
achieving the best compromise between short startup time, low-power consumption, as
well as available wakeup sources.
The devices feature several low-power modes:
•
•
•
•
•
•
CSleep (CPU clock stopped)
CStop (CPU sub-system clock stopped)
DStop (Domain bus matrix clock stopped)
Stop (System clock stopped)
DStandby (Domain powered down)
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
®
the Cortex -Mx core is set after returning from an interrupt service routine.
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Functional overview
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode. For instance
D1 or D2 domain enters DStop/DStandby mode when the CPU of the domain is in CStop
mode AND the other CPU has no peripheral allocated in that domain, or if it is in CStop
mode too. D3 domain can enter DStop/DStandby mode if both core subsystems do not have
active peripherals in D3 domain, and D3 is not forced in Run mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
®
The clock system can be re-initialize by a master CPU (either the Cortex -M4 or -M7) after
exiting Stop mode while the slave CPU is held in low-power mode. Once the master CPU
has re-initialized the system, the slave CPU can receive a wakeup interrupt and proceed
with the interrupt service routine.
Table 2. System vs domain low-power mode
D1 domain power
mode
D2 domain power
mode
D3 domain power
mode
System power mode
Run
Stop
DRun/DStop/DStandby DRun/DStop/DStandby
DRun
DStop
DStop/DStandby
DStandby
DStop/DStandby
DStandby
Standby
DStandby
3.7
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
Internal oscillators:
–
–
–
–
64 MHz HSI clock
48 MHz RC oscillator
4 MHz CSI clock
32 kHz LSI clock
•
External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
–
LSE clock: 32.768 kHz
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Functional overview
STM32H755xI
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
3.7.2
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
•
•
•
•
•
•
•
•
•
•
Power-on reset (pwr_por_rst)
Brownout reset
Low level on NRST pin (external reset)
Independent watchdog 1 (from D1 domain)
Independent watchdog 2 (from D2 domain)
Window watchdog 1 (from D1 domain)
Window watchdog 2 (from D2 domain)
Software reset
Low-power mode security reset
Exit from Standby
3.8
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 5).
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Figure 5. STM32H755xI bus matrix
AHBS
7
CPU
ITCM
CPU
Cortex-M7
D$
64 Kbyte
Cortex-M4
I$
DTCM
Ethernet
SDMMC2 USBHS1 USBHS2
DMA1
DMA2
16KB 16KB
128 Kbyte
MAC
ART
SDMMC1 MDMA
DMA2D
LTDC
D1-to-D2 AHB
APB3
SRAM1 128
Kbyte
4
SRAM2 128
Kbyte
AHB3
SRAM3
32 Kbyte
Flash A
5
Up to 1 Mbyte
AHB1
AHB2
APB1
APB2
Flash B
Up to 1 Mbyte
AXI SRAM
512 Kbyte
QSPI
FMC
1
64-bit AXI bus matrix
D1 domain
2
32-bit AHB bus matrix
D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
BDMA
D1-to-D3 AHB
Legend
6
3
AHB4
APB4
TCM AHB
32-bit bus
AXI
APB
SRAM4
64 Kbyte
Master interface
Slave interface
64-bit bus
Backup
SRAM
Bus multiplexer
32-bit AHB bus matrix
4 Kbyte
D3 domain
MSv39740V3
Functional overview
STM32H755xI
3.10
DMA controllers
The devices feature four DMA instances to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
®
access Cortex -M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•
•
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
•
•
•
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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Functional overview
3.12
Nested vectored interrupt controller (NVIC)
®
®
Both Cortex -M7 (CPU1) and Cortex -M4 (CPU2) cores have their own nested vector
interrupt controller (respectively NVIC1 and NVIC2). Each NVIC instance is able to manage
16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt
®
lines of the Cortex -M7 with FPU core.
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processors, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events (including two interrupt lines for inter-core management).
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
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3.15
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
–
–
–
–
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
•
•
•
•
•
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
3.16
Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
•
•
•
Direct mode through registers
External Flash status register polling mode
Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17
Analog-to-digital converters (ADCs)
The STM32H755xI devices embed three analog-to-digital converters, which resolution can
be configured to 16, 14, 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
•
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18
Temperature sensor
STM32H755xI devices embed a temperature sensor that generates a voltage (V ) that
TS
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 up to +140 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.19
VBAT operation
The V
power domain contains the RTC, the backup registers and the backup SRAM.
BAT
To optimize battery duration, this power domain is supplied by V when available or by the
DD
voltage applied on VBAT pin (when V supply is not present). V
power is switched
DD
BAT
when the PDR detects that V dropped below the PDR level.
DD
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by V , in which case, the V mode is not functional.
DD
BAT
V
operation is activated when V is not present.
DD
BAT
The V
pin supplies the RTC, the backup registers and the backup SRAM.
BAT
Note:
When the microcontroller is supplied from V
, external interrupts and RTC alarm/events
BAT
do not exit it from V
operation.
BAT
When PDR_ON pin is connected to V (Internal Reset OFF), the V
functionality is no
BAT
SS
more available and V
pin should be connected to VDD.
BAT
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3.20
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
•
•
•
•
•
•
•
•
•
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel including DMA underrun error detection
external triggers for conversion
input voltage reference V
or internal VREFBUF reference.
REF+
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21
Ultra-low-power comparators (COMP)
STM32H755xI devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•
•
•
An external I/O
A DAC output channel
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22
Operational amplifiers (OPAMP)
STM32H755xI devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•
•
•
•
•
One positive input connected to DAC
Output connected to internal ADC
Low input bias current down to 1 nA
Low input offset voltage down to 1.5 mV
Gain bandwidth up to 7.3 MHz
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Functional overview
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
8 multiplexed input digital serial channels:
–
–
–
–
–
configurable SPI interface to connect various SD modulator(s)
configurable Manchester coded 1 wire interface support
PDM (Pulse Density Modulation) microphone input support
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
clock output for SD modulator(s): 0..20 MHz
•
•
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
internal sources: ADC data or memory data streams (DMA)
–
4 digital filter modules with adjustable digital signal processing:
x
–
–
Sinc filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
integrator: oversampling ratio (1..256)
•
•
•
•
up to 24-bit output data resolution, signed output data format
automatic data offset correction (offset stored in register by user)
continuous or single conversion
start-of-conversion triggered by:
–
–
–
–
software trigger
internal timers
external events
start-of-conversion synchronously with first digital filter module (DFSDM0)
•
analog watchdog feature:
–
–
–
–
low value and high value data threshold registers
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
input from final output data or from selected input digital serial channels
continuous monitoring independently from standard conversion
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Functional overview
STM32H755xI
•
short circuit detector to detect saturated analog input values (bottom and top range):
–
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
monitoring continuously each input serial channel
•
•
break signal generation on analog watchdog event or on short circuit detector event
extremes detector:
–
–
storage of minimum and maximum values of final conversion data
refreshed by software
•
•
DMA capability to read the final conversion data
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Table 3. DFSDM implementation
DFSDM features
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
Number of external triggers
X
16
Regular channel information in
identification register
X
3.24
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 105 Mbyte/s using a 60 MHz pixel clock. It
features:
•
•
•
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
•
Supports Continuous mode or Snapshot (a single frame) mode
Capability to automatically crop the image
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Functional overview
3.25
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
•
•
•
•
•
•
•
•
2 display layers with dedicated FIFO (64x64-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events
AXI master interface with burst of 16 words
3.26
JPEG Codec (JPEG)
The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 10918-
1 specification. It provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features are as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit/channel pixel depths
Single clock per pixel encoding and decoding
Support for JPEG header generation and parsing
Up to four programmable quantization tables
Fully programmable Huffman tables (two AC and two DC)
Fully programmable minimum coded unit (MCU)
Encode/decode support (non simultaneous)
Single clock Huffman coding and decoding
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
Support for single greyscale component
Ability to enable/disable header processing
Fully synchronous design
Configuration for High-speed decode mode
3.27
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
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Functional overview
STM32H755xI
3.28
Cryptographic acceleration (CRYP and HASH)
The devices embed a cryptographic processor that supports the advanced cryptographic
algorithms usually required to ensure confidentiality, authentication, data integrity and non-
repudiation when exchanging messages with a peer:
•
Encryption/Decryption
–
DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
–
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (Counter
mode) chaining algorithms, 128, 192 or 256-bit key
•
Universal HASH
–
–
–
SHA-1 and SHA-2 (secure HASH algorithms)
MD5
HMAC
The cryptographic accelerator supports DMA request generation.
3.29
Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten general-
purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Max
Max
DMA
request
generation channels
Capture/ Comple-
compare mentary
timer
clock
Timer
type
Counter Counter Prescaler
interface
clock
Timer
resolution
type
factor
output
(MHz)
(MHz)
(1)(2)
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
High-
resolution HRTIM1
timer
16-bit
Up
Yes
Yes
10
4
Yes
480(2)
480
240
Any
integer
Down, between1
Up,
Advanced TIM1,
-control
16-bit
Yes
120
TIM8
Up/down
and
65536
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Functional overview
Table 4. Timer feature comparison (continued)
Max
Max
DMA
request
generation channels
Capture/ Comple-
compare mentary
timer
clock
Timer
type
Counter Counter Prescaler
interface
clock
Timer
resolution
type
factor
output
(MHz)
(MHz)
(1)(2)
Any
Up,
integer
TIM2,
TIM5
32-bit
Down, between1
Up/down
Yes
Yes
No
4
4
2
1
2
1
0
0
No
120
120
120
120
120
120
120
120
240
240
240
240
240
240
240
240
and
65536
Any
integer
Down, between1
Up,
TIM3,
TIM4
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
No
No
No
1
Up/down
and
65536
Any
integer
between1
and
TIM12
Up
65536
General
purpose
Any
integer
between1
and
TIM13,
TIM14
Up
Up
Up
Up
Up
No
65536
Any
integer
between1
and
TIM15
Yes
Yes
Yes
No
65536
Any
integer
between1
and
TIM16,
TIM17
1
65536
Any
integer
between1
and
TIM6,
TIM7
Basic
No
No
65536
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
Low-
power
timer
1, 2, 4, 8,
16, 32, 64,
128
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
2. On STM32H755xxx3 sales types (extended industrial temperature range), the maximum clock frequency is 300 MHz for the
high-resolution timer and 150 MHz for the other timers.
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Functional overview
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3.29.1
High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
(a)
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, Burst mode
controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
a. Up to 300 MHz for STM32H755xxx3 sales types (extended industrial temperature range).
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3.29.2
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (Edge- or Center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.29.3
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H755xI
devices (see Table 4 for differences).
•
TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
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Functional overview
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3.29.4
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.29.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
•
•
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / One-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
•
Programmable digital glitch filter
Encoder mode
3.29.6
Independent watchdogs
There are two independent watchdogs, one per domain. Each independent watchdog is
based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32
kHz internal RC and as it operates independently from the main clock, it can operate in Stop
and Standby modes. It can be used either as a watchdog to reset the device when a
problem occurs, or as a free-running timer for application timeout management. It is
hardware- or software-configurable through the option bytes.
3.29.7
3.29.8
Window watchdogs
There are two window watchdogs, one per domain. Each window watchdog is based on a 7-
bit downcounter that can be set as free-running. It can be used as a watchdog to reset the
device or each respective domain (configurable in the RCC register), when a problem
occurs. It is clocked from the main clock. It has an early warning interrupt capability and the
counter can be frozen in Debug mode.
SysTick timer
The devices feature two SysTick timers, one per CPU. These timers are dedicated to real-
time operating systems, but could also be used as a standard downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
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Functional overview
3.30
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
•
Three anti-tamper detection pins with programmable filter.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in V
mode and in all low-power modes when it is clocked by the
BAT
LSE. When clocked by the LSI, the RTC is not functional in V
all low-power modes.
mode, but is functional in
BAT
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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54
Functional overview
STM32H755xI
3.31
Inter-integrated circuit interface (I2C)
2
STM32H755xI devices embed four I C interfaces.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and Master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power System Management Protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
3.32
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H755xI devices have four embedded universal synchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7 and UART8). Refer to Table 5 for a summary of
USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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Functional overview
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 5. USART features
USART modes/features(1)
USART1/2/3/6
UART4/5/7/8
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode (Master/Slave)
Smartcard mode
-
Single-wire Half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
X
X
X
X
X
X
Dual clock domain and wakeup from low power mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
X
Tx/Rx FIFO size
16
1. X = supported.
3.33
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
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54
Functional overview
STM32H755xI
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.34
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-
duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
2
Three standard I S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in Simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
2
I S interfaces is/are configured in Master mode, the master clock can be output to the
2
external DAC/CODEC at 256 times the sampling frequency. All I S interfaces support 16x 8-
bit embedded Rx and Tx FIFOs with DMA capability.
3.35
Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
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Functional overview
3.36
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
•
•
•
•
•
•
•
•
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.37
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
•
•
•
Full-duplex communication mode
automatic SWP bus state management (active, suspend, resume)
configurable bitrate up to 2 Mbit/s
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
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54
Functional overview
STM32H755xI
3.38
Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
•
Configurable slave (port) address
Independently maskable interrupts/events:
–
–
–
MDIO Register write
MDIO Register read
MDIO protocol error
•
Able to operate in and wake up from Stop mode
3.39
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.40
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
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Functional overview
3.41
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1
features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using
the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
•
•
•
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
9 bidirectional endpoints (including EP0)
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Battery Charging Specification Revision 1.2 support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
•
•
•
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.42
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
DS12919 Rev 1
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54
Functional overview
STM32H755xI
The devices include the following features:
•
•
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
•
•
•
•
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
•
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
3.43
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.44
Debug infrastructure
The devices offer a comprehensive set of debug and trace features on both cores to support
software development and system integration.
•
•
•
•
•
•
•
•
•
Breakpoint debugging
Code execution tracing
Software instrumentation
JTAG debug port
Serial-wire debug port
Trigger input and output
Serial-wire trace port
Trace port
®
Arm CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools. The debug infrastructure allows debugging one core at a time, or
both cores in parallel.
The trace port performs data capture for logging and analysis.
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DS12919 Rev 1
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Functional overview
A 4-Kbyte embedded trace FIFO (ETF) allows recording data and sending them to any com
port. In Trace mode, the trace is transferred by DMA to system RAM or to a high-speed
interface (such as SPI or USB). It can even be monitored by a software running on one of
the cores. Unlike hardware FIFO mode, this mode is invasive since it uses system
resources which are shared by the processors.
DS12919 Rev 1
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54
Memory mapping
STM32H755xI
4
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
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DS12919 Rev 1
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Pin descriptions
5
Pin descriptions
Figure 6. LQFP144 pinout
PE2
PE3
1
2
3
4
5
6
7
8
9
108
107
106
105
104
103
102
101
100
99
PA15
PA14
VDD
VDDLDO
VSS
PE4
PE5
PE6
VSS
VDD
VBAT
PC13
VCAP
PA13
PA12
PA11
PA10
PA9
PC14-OSC32_IN 10
PC15-OSC32_OUT 11
VSS 12
98
97
PA8
VDD 13
96
PC9
VSSSMPS 14
VLXSMPS 15
VDDSMPS 16
VFBSMPS 17
VSS 18
95
PC8
94
PC7
93
PC6
92
VDD
144-pins
91
VDD33USB
VDD50USB
VSS
VDD 19
90
PF6 20
89
PF7 21
88
PG8
PF8 22
87
PG7
PF9 23
86
PG6
PF10 24
85
PD15
PD14
PD13
PD12
PD11
VSS
PH0-OSC_IN 25
PH1-OSC_OUT 26
NRST 27
84
83
82
PC0 28
PC1 29
PC2_C 30
PC3_C 31
VDD 32
VSS 33
VSSA 34
VREF+ 35
VDDA 36
81
80
79
VDD
PD10
PD9
PD8
PB15
PB14
78
77
76
75
74
73 PB13
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
MSv43750V3
DS12919 Rev 1
55/252
104
Pin descriptions
STM32H755xI
Figure 7. LQFP176 pinout
PE2
PE3
1
2
3
4
5
6
7
8
9
PA13
PA12
PA11
PA10
PA9
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PE4
PE5
PE6
VSS
VDD
VBAT
PC13
PA8
VDD
PC9
PC8
PC14-OSC32_IN 10
PC15-OSC32_OUT 11
VSS 12
PC7
PC6
VDD33USB
VDD50USB
VSS
VDD 13
VSSSMPS 14
VLXSMPS 15
VDDSMPS 16
VFBSMPS 17
PF0 18
PG8
PG7
PG6
PG5
PF1 19
PG4
PF2 20
VDD
VSS
PF3 21
176-pins
PF4 22
PG3
PF5 23
PG2
VSS 24
PK2
VDD 25
PK1
PF6 26
PK0
PF7 27
VSS
PF8 28
VDD
PJ11
PJ10
PJ9
PF9 29
PF10 30
PH0-OSC_IN 31
PH1-OSC_OUT 32
NRST 33
PC0 34
PJ8
VSS
VDD
PD15
PD14
PD13
PD12
PD11
VSS
98
97
96
95
94
93
92
91
PC1 35
PC2_C 36
PC3_C 37
VSSA 38
VREF+ 39
VDDA 40
PA0 41
VDD
PD10
PD9
PA1 42
90
89
PA2 43
VDD 44
PD8
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
MSv43751V3
1. The above figure shows the package top view.
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DS12919 Rev 1
STM32H755xI
Pin descriptions
Figure 8. UFBGA176+25 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDD
LDO
VDD
LDO
PA14
A
B
C
D
E
F
VSS
PE4
PB8
VCAP
PB6
PB3
PG11
PG9
PD3
PD1
PA15
VCAP
VSS
PA13
PE3
PB9
PE2
PE0
PE1
PB7
BOOT0
VDD
PB4
PB5
VSS
PG13
PG14
PG15
PD7
PD5
PD4
PD6
PD2
PD0
VSS
PC12
PC11
VDD
PH14
PC10
PH15
VDD
VSS
PA8
PA10
PC8
PA12
PA11
PC7
PC13
VSS
PG10
PG12
PH13
PA9
PC15-
PC14-
PDR_
ON
PE5
OSC32 OSC32_
_OUT
IN
VDD50
USB
VSS
VBAT
PE6
VDD
PF0
PC9
PC6
VLX
SMPS
VSS
SMPS
VDD33
USB
PF1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PG6
PG4
PD14
VSS
PB15
PD8
PG5
PG2
VDD
SMPS
VFB
SMPS
G
H
J
PF2
VDD
PF3
PG8
PG7
PG3
PF6
PF4
PF8
VSS
PC0
PC3
PF5
VDD
PD15
VSS
PD13
PD12
PB14
PB13
PB12
PH12
PH6
PH0-
OSC_IN
PF7
PF9
PD11
PD9
PH1-
OSC_
OUT
K
L
PF10
PC1
VDD
VREF-
VDDA
PH2
NRST
VDD
PE14
PB10
PE12
PE11
PD10
PH11
PH8
M
N
P
R
PC2
VREF+
VSSA
PA1_C
PA0_C
VDD
PA3
PA4
PH5
VSS
PA7
PA5
PC4
PC5
PF11
PB2
PA6
PB1
PE8
PG0
PB0
VDD
PG1
PE7
VSS
PF15
PB11
PF14
PH7
PF13
PF12
PE9
PH9
PC2_C PC3_C
PH10
PE15
PA0
PA1
PH4
PE13
VCAP
VDD
LDO
VSS
PA2
PH3
PE10
VSS
MSv43752V4
1. The above figure shows the package top view.
DS12919 Rev 1
57/252
104
Pin descriptions
STM32H755xI
Figure 9. LQFP208 pinout
1
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PE2
PE3
PH13
VDD
VDDLDO
VSS
2
3
PE4
4
PE5
5
PE6
VCAP
PA13
PA12
PA11
PA10
PA9
6
VSS
7
VDD
8
VBAT
9
PI8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PI9
PA8
PC9
PC8
PI10
PC7
PI11
PC6
VSS
VDD33USB
VDD50USB
VSS
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
PF0
PG8
PG7
PG6
PG5
PF1
PG4
PF2
VDD
VSS
PF3
208-pins
PF4
PG3
PF5
PG2
VSS
PK2
VDD
PK1
PF6
PK0
PF7
VSS
PF8
VDD
PJ11
PJ10
PJ9
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PJ8
VSS
VDD
PJ7
PC1
PC2_C
PC3_C
VSSA
VREF+
VDDA
PA0
PJ6
PD15
PD14
VDD
VSS
PD13
PD12
PD11
VSS
PA1
PA2
PH2
VDD
VDD
PD10
PD9
VSS
PH3
PH4
PD8
MSv43753V3
1. The above figure shows the package top view.
58/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Figure 10. TFBGA240+25 ballout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VDD
LDO
VCAP
A
B
C
D
E
F
VSS
PI6
PI5
PI4
PB5
PK5
PG10
PG9
PD5
PD4
PC10
PA15
PI1
PI0
VSS
VBAT
VSS
PI7
PE2
PE3
PC13
PI10
PF1
PI14
VSS
PF7
PF10
PC2
PA2
PE1
PE0
PB9
PI8
PB6
PB7
PB8
PE6
VDD
VDD
VDD
PF4
VDD
VDD
VDD
PA0
PI15
PA7
PB1
PB0
VSS
PB3
PB4
PK6
PK7
PK4
PK3
PG11
PG12
PG13
PJ15
VSS
PD6
PD7
PJ12
VDD
PD3
PC12
PD2
PC11
VSS
PD0
PC8
PC7
VDD
VDD
VDD
VDD
VDD
VDD
PJ8
PA14
PI3
PI2
PH15
VSS
PH13
PA12
PG7
VSS
PG2
VSS
NC
PH14
PC15-
OSC32_
OUT
PC14-
OSC32
_IN
VDD
LDO
PA13
PA9
VCAP
PA11
PE5
PE4
PG15
VDD
PG14
PJ14
PJ13
PA10
PC9
PC6
PG5
PG4
PK0
VLX
SMPS
PDR
_ON
PI9
BOOT0 VDD
PD1
PA8
VDD
SMPS SMPS
VSS
VDD
33USB
PI11
PF0
PF3
PF5
PF8
PF9
PC3
PA1
PH5
VSS
PC4
PC5
PG8
PG6
PG3
PK1
VFB
PF2
VDD
50USB
G
H
J
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SMPS
PI12
PI13
PK2
VSS
NC
PH1-
OSC_
OUT
PH0-
OSC
_IN
K
L
NRST
PF6
PJ11
PJ10
PJ9
VSS
VSS
VSS
PJ6
VDDA
PC0
NC
NC
M
N
P
R
T
VREF+ PC1
NC
NC
VREF-
VSSA
PH2
PH3
PJ0
PJ1
PB2
PJ2
PJ3
VDD
PF13
PF12
PF11
PJ4
VDD
PF14
VSS
PG0
PG1
PE10
PE9
VDD
PE11
PE12
PE13
PE14
VDD
PB10
PE15
PH6
VDD
PB11
PJ5
PJ7
VSS
PD14
PD12
PD10
PD8
NC
PH4
PH10
PH9
PH8
PH7
PH11
PH12
PB12
PB13
PD15
PD11
PB15
PB14
VDD
PD13
PD9
VSS
PC2_C PC3_C PA6
PF15
PE8
PA0_C PA1_C
VSS PA3
PA5
PA4
VSS
VDD
LDO
U
PE7
VCAP
MSv43744V3
1. The above figure shows the package top view.
DS12919 Rev 1
59/252
104
Pin descriptions
STM32H755xI
Table 6. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
ANA
FT
TT
B
Input / output pin
Analog-only Input
5 V tolerant I/O
3.3 V tolerant I/O
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
RST
I/O structure
Option for TT and FT I/Os
_f
I2C FM+ option
_a
_u
_h
analog option (supplied by VDDA)
USB option (supplied by VDD33USB
)
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
functions
Functions directly selected/enabled through peripheral registers
60/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
FT_
h
SAI4_MCLK_A,
QUADSPI_BK1_IO2,
SAI4_CK1,
1
C3
1
1
C3
PE2
I/O
-
-
ETH_MII_TXD3,
FMC_A23, EVENTOUT
TRACED0, TIM15_BKIN,
SAI1_SD_B,
SAI4_SD_B, FMC_A19,
EVENTOUT
FT_
h
2
3
B2
B1
2
3
2
3
D3
D2
PE3
PE4
I/O
I/O
-
-
-
-
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
FT_
h
SPI4_NSS, SAI1_FS_A,
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1,
SPI4_MISO,
SAI1_SCK_A,
SAI4_SCK_A,
FT_
h
4
D3
4
4
D1
PE5
I/O
-
-
SAI4_CK2, FMC_A21,
DCMI_D6, LCD_G0,
EVENTOUT
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI,SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
FT_
h
5
E3
5
5
E5
PE6
I/O
-
-
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
6
7
8
-
A1
D5
6
7
8
-
6
7
8
-
A1
-
VSS
VDD
VBAT
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E2
B1
B2
A15
DS12919 Rev 1
61/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
RTC_TAMP2/WK
UP3
-
-
-
9
E4
PI8
I/O
FT
-
EVENTOUT
RTC_TAMP1/RTC
_TS/WKUP2
9
-
C1
C2
9
-
10
-
E3
-
PC13
VSS
I/O
S
FT
-
-
-
EVENTOUT
-
-
PC14-
OSC32_IN
10
11
-
D2
D1
-
10
11
-
11
12
13
C2
C1
E2
I/O
I/O
I/O
FT
FT
-
-
-
EVENTOUT
EVENTOUT
OSC32_IN
(OSC32_IN)
(1)
PC15-
OSC32_OUT
(OSC32_
OUT)(1)
OSC32_OUT
UART4_RX,
FDCAN1_RX, FMC_D30,
LCD_VSYNC,
FT_
h
PI9
-
EVENTOUT
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER,
FMC_D31,LCD_HSYNC,
EVENTOUT
FT_
h
-
-
-
-
-
-
14
15
F3
F4
PI10
PI11
I/O
I/O
-
-
-
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
FT
WKUP4
12
13
14
15
16
17
D10
D11
F2
12
13
14
15
16
17
16
17
18
19
20
21
A17
E6
F2
VSS
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD
VSSSMPS
VLXSMPS
VDDSMPS
VFBSMPS
F1
E1
F1
G1
G2
G2
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
-
F4
F3
G3
18
19
20
22
23
24
G4
G3
G1
PF0
PF1
PF2
I/O FT_f
I/O FT_f
-
-
-
-
-
-
I2C2_SCL, FMC_A1,
EVENTOUT
I2C2_SMBA, FMC_A2,
EVENTOUT
I/O
FT
62/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
LCD_HSYNC,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
H1
H2
H3
H4
J5
PI12
PI13
PI14
PF3
PF4
PF5
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
-
-
-
-
-
-
-
LCD_VSYNC,
EVENTOUT
-
-
FT_
h
-
-
-
LCD_CLK, EVENTOUT
FMC_A3, EVENTOUT
FMC_A4, EVENTOUT
FMC_A5, EVENTOUT
-
FT_
ha
H4
H2
H3
21
22
23
25
26
27
ADC3_INP5
FT_
ha
ADC3_INN5,
ADC3_INP9
FT_
ha
J4
ADC3_INP4
18
19
E1
E4
24
25
28
29
C10
E9
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
SAI4_SD_B,
QUADSPI_BK1_IO3,
EVENTOUT
FT_
ha
ADC3_INN4,
ADC3_INP8
20
21
H1
J3
26
27
30
31
K2
K3
PF6
PF7
I/O
I/O
-
-
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_TX,
SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
FT_
ha
ADC3_INP3
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
FT_
ha
UART7_RTS/UART7_DE
, SAI4_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_INN3,
ADC3_INP7
22
23
J2
J4
28
29
32
33
K4
L4
PF8
PF9
I/O
I/O
-
-
TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
UART7_CTS,
SAI4_FS_B,TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
FT_
ha
ADC3_INP2
DS12919 Rev 1
63/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK,
SAI4_D3, DCMI_D11,
LCD_DE, EVENTOUT
FT_
ha
ADC3_INN2,
ADC3_INP6
24
25
K3
30
34
L3
J2
PF10
I/O
-
-
PH0-
OSC_IN
(PH0)
J1
31
35
I/O
I/O
FT
FT
EVENTOUT
OSC_IN
PH1-
OSC_OUT
(PH1)
26
27
K1
L1
32
33
36
37
J1
-
-
EVENTOUT
-
OSC_OUT
-
K1
NRST
I/O RST
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B,
FT_
28
L2
34
38
L2
PC0
I/O
a
-
ADC123_INP10
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO, ADC123_INN10,
FT_
SAI1_SD_A,
SAI4_SD_A,
SDMMC2_CK, SAI4_D1,
ETH_MDC,
ADC123_INP11,
RTC_TAMP3/WK
UP5
29
L3
35
39
M2
PC1
I/O
ha
-
MDIOS_MDC,
EVENTOUT
FT_
C1DSLEEP,
DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
ADC123_INN11,
ADC123_INP12
-
M1
-
-
M3(2)
PC2
I/O
a
-
-
TT_
ADC3_INN1,
ADC3_INP0
30(3) N1(3) 36(3) 40(3) R1(2)
PC2_C
ANA
a
EVENTOUT
FT_
C1SLEEP,
DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
ADC12_INN12,
ADC12_INP13
-
M2
-
-
M4(2)
PC3
I/O
a
-
-
TT_
31(3) N2(3) 37(3) 41(3) R2(2)
PC3_C
ANA
a
ADC3_INP1
EVENTOUT
64/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
32
33
34
-
E12
F6
-
-
-
-
E11
C13
P1
VDD
VSS
S
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N3
L4
38
-
42
-
VSSA
VREF-
VREF+
VDDA
N1
35
36
M3
M4
39
40
43
44
M1
L1
FT_
a
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
USART2_CTS/USART2_
NSS, UART4_TX,
SDMMC2_CMD,
SAI2_SD_B,
ADC1_INP16,
WKUP0
37
P1
R3
P2
41
45 N5(2)
PA0
PA0_C
PA1
I/O
ANA
I/O
-
-
-
TT_
a
ADC12_INN1,
ADC12_INP0
-
-
-
T1(2)
ETH_MII_CRS,
EVENTOUT
FT_
ha
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT,
ADC1_INN16,
ADC1_INP17
38
42
46 N4(2)
TIM15_CH1N,
USART2_RTS/USART2_
DE, UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
TT_
a
-
P3
-
-
T2(2)
PA1_C
ANA
-
ADC12_INP1
LCD_R2, EVENTOUT
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
FT_
a
USART2_TX,
SAI2_SCK_B,
ADC12_INP14,
WKUP1
39
R2
43
47
N3
PA2
I/O
-
ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
ETH_MII_CRS,
FMC_SDCKE0,LCD_R0,
EVENTOUT
FT_
ha
-
-
N4
G4
-
48
49
N2
F5
PH2
VDD
I/O
S
-
-
ADC3_INP13
44
-
-
-
DS12919 Rev 1
65/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
-
-
F7
45
50
C16
P2
VSS
PH3
S
-
-
-
-
-
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
FT_
ha
ADC3_INN13,
ADC3_INP14
R4
-
51
I/O
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
FT_f
a
ADC3_INN14,
ADC3_INP15
-
-
P4
R5
-
-
52
53
P3
P4
PH4
PH5
I/O
I/O
-
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
FT_f
a
ADC3_INN15,
ADC3_INP16
EVENTOUT
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
FT_
ha
40
N5
46
54
U2
PA3
I/O
-
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC12_INP15
41
42
F8
47
48
55
56
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
H12
G5
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
TT_
a
ADC12_INP18,
DAC1_OUT1
43
P5
49
57
U3
PA4
PA5
I/O
-
SPI6_NSS,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
SPI6_SCK,
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
TT_
ha
44
P6
50
58
T3
I/O
-
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
66/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO,
FT_
a
TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
45
R7
51
59
R3
PA6
I/O
-
ADC12_INP3
TIM1_BKIN_COMP12,
DCMI_PIXCLK,LCD_G2,
EVENTOUT
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI,
TIM14_CH1,
ETH_MII_RX_DV/ETH_R OPAMP1_VINM
MII_CRS_DV,
ADC12_INN3,
ADC12_INP7,
TT_
a
46
47
48
N6
R6
M7
52
53
54
60
61
62
R5
T4
U4
PA7
PC4
PC5
I/O
I/O
I/O
-
-
-
FMC_SDNWE,
EVENTOUT
C2DSLEEP,
DFSDM1_CKIN2,
I2S1_MCK,
ADC12_INP4,
TT_
a
SPDIFRX1_IN3,
OPAMP1_VOUT,
ETH_MII_RXD0/ETH_R
COMP1_INM
MII_RXD0,
FMC_SDNE0,
EVENTOUT
C2SLEEP, SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
SAI4_D3,
ETH_MII_RXD1/ETH_R
MII_RXD1,
ADC12_INN4,
ADC12_INP8,
OPAMP1_VINM
TT_
a
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
-
-
K4
F9
-
-
-
-
G13
R4
VDD
VSS
S
S
-
-
-
-
-
-
-
-
DS12919 Rev 1
67/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP1_INP
FT_
a
49
50
51
R8
55
63
U5
T5
R6
PB0
PB1
PB2
I/O
I/O
I/O
-
-
-
LCD_G1, EVENTOUT
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN1,
LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
TT_
u
ADC12_INP5,
COMP1_INM
M8
P7
56
57
64
65
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
FT_
ha
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A,
COMP1_INP
QUADSPI_CLK,
SAI4_D1, EVENTOUT
LCD_G2, LCD_R0,
EVENTOUT
-
-
-
-
-
-
66
-
P5
N6
PI15
PJ0
I/O
I/O
FT
FT
-
-
-
-
LCD_R7, LCD_R1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P6
T6
U6
U7
PJ1
PJ2
PJ3
PJ4
I/O
I/O
I/O
I/O
FT
FT
FT
FT
-
-
-
-
LCD_R2, EVENTOUT
LCD_R3, EVENTOUT
LCD_R4, EVENTOUT
LCD_R5, EVENTOUT
-
-
-
-
SPI5_MOSI,SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
FT_
a
52
-
N7
58
59
67
68
T7
R7
PF11
PF12
I/O
I/O
-
-
ADC1_INP2
FT_
ha
ADC1_INN2,
ADC1_INP6
P11
FMC_A6, EVENTOUT
-
-
F10
L12
-
-
-
-
J3
VSS
VDD
S
S
-
-
-
-
-
-
-
-
H5
DFSDM1_DATIN6,
I2C4_SMBA, FMC_A7,
EVENTOUT
FT_
ha
-
N11
60
69
P7
PF13
I/O
-
ADC2_INP2
68/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
DFSDM1_CKIN6,
I2C4_SCL, FMC_A8,
EVENTOUT
FT_f
ha
ADC2_INN2,
ADC2_INP6
53
R10
61
70
P8
PF14
I/O
-
FT_f
h
I2C4_SDA, FMC_A9,
EVENTOUT
54
-
N10
P8
62
63
71
72
R9
T8
PF15
PG0
I/O
I/O
-
-
-
-
FT_
h
FMC_A10, EVENTOUT
55
56
F12
M5
64
65
73
74
J16
VSS
VDD
S
S
-
-
-
-
-
-
-
-
H13
TT_
h
-
N9
66
75
U8
U9
PG1
I/O
-
FMC_A11, EVENTOUT
OPAMP2_VINM
TIM1_ETR,
DFSDM1_DATIN2,
UART7_RX,
QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4,
EVENTOUT
TT_
ha
OPAMP2_VOUT,
COMP2_INM
57
P9
67
76
PE7
I/O
-
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_TX,
QUADSPI_BK2_IO1,
FMC_D5/FMC_DA5,
COMP2_OUT,
TT_
ha
58
59
N8
68
69
77
78
T9
P9
PE8
PE9
I/O
I/O
-
-
OPAMP2_VINM
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
UART7_RTS/UART7_DE OPAMP2_VINP,
, QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6,
EVENTOUT
TT_
ha
R11
COMP2_INP
-
-
G6
M9
70
71
79
80
J17
J13
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM1_CH2N,
DFSDM1_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
FT_
ha
60
R9
72
81
N9
PE10
I/O
-
COMP2_INM
DS12919 Rev 1
69/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_CH2,
DFSDM1_CKIN4,
FT_
ha
61
62
R12
73
82
P10
R10
PE11
PE12
I/O
I/O
-
-
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
COMP2_INP
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
FT_
h
P12
P13
74
75
83
84
SAI2_SCK_B,
-
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
FT_
h
63
T10
PE13
I/O
-
-
-
-
G7
-
-
-
-
-
T12
K13
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
FT_
h
64
65
M12
P14
76
77
85
86
U10
R11
PE14
PE15
I/O
I/O
-
-
-
-
TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12/C
OMP_TIM1_BKIN,
FT_
h
LCD_R7, EVENTOUT
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
USART3_TX,
66
N12
78
87
P11
PB10
I/O FT_f
-
-
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
70/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
67
P10
79
88
P12
PB11
I/O FT_f
-
-
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
68
69
70
71
-
R13
M10
R14
-
80
81
82
-
89
90
91
-
U11
-
VCAP
VSS
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
U12
L13
R12
VDDLDO
VDD
S
-
-
S
-
-
-
-
-
PJ5
I/O
FT
LCD_R6, EVENTOUT
TIM12_CH1,
I2C2_SMBA, SPI5_SCK,
ETH_MII_RXD2,
-
P15
-
92
T11
PH6
I/O
FT
-
-
FMC_SDNE1, DCMI_D8,
EVENTOUT
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
FT_f
a
-
-
M11
N13
-
-
93
94
U13
T13
PH7
PH8
I/O
I/O
-
-
-
-
TIM5_ETR, I2C3_SDA,
FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
FT_f
ha
-
-
G9
-
-
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
M13
TIM12_CH2,
I2C3_SMBA, FMC_D17,
DCMI_D0, LCD_R3,
EVENTOUT
FT_
h
-
-
M14
N14
-
-
95
96
R13
P13
PH9
I/O
I/O
-
-
-
-
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1,
LCD_R4, EVENTOUT
FT_
h
PH10
DS12919 Rev 1
71/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2,
LCD_R5, EVENTOUT
FT_f
h
-
-
M13
-
97
P14
R14
PH11
PH12
I/O
I/O
-
-
-
-
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3,
LCD_R6, EVENTOUT
FT_f
h
N15
-
98
-
-
G10
-
83
84
99
N16
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
100
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FT_
u
72
M15
85
101 T14
PB12
I/O
-
FDCAN2_RX,
-
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_R
MII_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
FT_
u
USART3_CTS/USART3_
NSS, FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_R
MII_TXD1, UART5_TX,
EVENTOUT
73
L15
86
102 U14
PB13
I/O
-
OTG_HS_VBUS
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3_
DE,
FT_
u
74
K15
87
103 U15
PB14
I/O
-
-
UART4_RTS/UART4_DE
, SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
72/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
FT_
u
75
K14
88
104 T15
PB15
I/O
-
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2,
UART4_CTS,
-
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
DFSDM1_CKIN3,
SAI3_SCK_B,
FT_
h
USART3_TX,
76
77
78
L14
K13
L13
89
90
91
105 U16
106 T17
107 T16
PD8
PD9
I/O
I/O
I/O
-
-
-
-
-
-
SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
DFSDM1_DATIN3,
SAI3_SD_B,
FT_
h
USART3_RX,
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
DFSDM1_CKOUT,
SAI3_FS_B,
USART3_CK,
FT_
h
PD10
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
79
80
-
92
93
108 N12
109 U17
VDD
VSS
S
S
-
-
-
-
-
-
-
-
H6
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3_
NSS,
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
FT_
h
81
J13
94
110 R15
PD11
I/O
-
-
DS12919 Rev 1
73/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/USART3_
DE, QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
FT_f
h
82
83
J15
95
111 R16
PD12
PD13
I/O
I/O
-
-
-
-
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
FT_f
h
H15
96
112 R17
-
-
R1
-
-
-
113
114
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
N11
TIM4_CH3,
SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0,
EVENTOUT
FT_
h
84
85
H14
J12
97
98
115 P16
PD14
PD15
I/O
I/O
-
-
-
-
TIM4_CH4,
SAI3_MCLK_A,
UART8_RTS/UART8_DE
, FMC_D1/FMC_DA1,
EVENTOUT
FT_
h
116 P15
117 N15
TIM8_CH2, LCD_R7,
EVENTOUT
-
-
-
-
-
-
PJ6
PJ7
I/O
I/O
FT
FT
-
-
-
-
TRGIN, TIM8_CH2N,
LCD_G0, EVENTOUT
118 N14
119 N10
-
-
-
99
VDD
VSS
S
S
-
-
-
-
-
-
-
-
D6
100
120
R8
TIM1_CH3N, TIM8_CH1,
UART8_TX, LCD_G1,
EVENTOUT
-
-
-
-
-
-
101
102
103
121 N13
122 M14
PJ8
PJ9
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
TIM1_CH3, TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
123
L14
PJ10
74/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
-
104
124 K14
PJ11
I/O
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
105
-
125
N8
P17
U1
VDD
VDD
VSS
NC
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R15 106
126
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N17
M16
M17
K15
L16
L17
K16
K17
L15
NC
-
NC
-
VSS
NC
S
-
NC
-
NC
-
NC
-
VSS
S
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5,
EVENTOUT
-
-
-
-
107
108
127
128
J14
J15
PK0
PK1
I/O
I/O
FT
FT
-
-
-
-
TIM1_CH1, TIM8_CH3N,
SPI5_NSS, LCD_G6,
EVENTOUT
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
-
-
109
129 H17
PK2
I/O
FT
-
-
TIM8_BKIN,
TIM8_BKIN_COMP12,
FMC_A12, EVENTOUT
FT_
h
-
-
G15 110
130 H16
131 H15
PG2
PG3
I/O
I/O
-
-
-
-
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
FT_
h
H13 111
H10 112
-
-
132
133
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
-
113
N7
DS12919 Rev 1
75/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0,
EVENTOUT
FT_
h
-
-
G14 114
134 H14
PG4
PG5
I/O
I/O
-
-
-
-
TIM1_ETR,
FMC_A15/FMC_BA1,
EVENTOUT
FT_
h
F15
F14
115
116
135 G14
136 G15
TIM17_BKIN,
HRTIM_CHE1,
QUADSPI_BK1_NCS,
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
FT_
h
86
87
PG6
PG7
I/O
I/O
-
-
-
-
HRTIM_CHE2,
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
FT_
h
G13 117
137 F16
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_
DE, SPDIFRX1_IN3,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
FT_
h
88
G12 118
138 F15
139 G16
PG8
VSS
I/O
-
-
89
90
91
92
J6
119
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E15 120
F13 121
140 G17 VDD50USB
141 F17 VDD33USB
-
-
-
M5
VDD
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK,USART6_TX,
SDMMC1_D0DIR,
FMC_NWAIT,
FT_
h
93
E14 122
142 F14
PC6
I/O
-
SWPMI_IO
SDMMC2_D6,
SDMMC1_D6,DCMI_D0,
LCD_HSYNC,
EVENTOUT
76/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR,
FMC_NE1,
FT_
h
94
D15 123
143 F13
PC7
I/O
-
-
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7,DCMI_D1,
LCD_G6, EVENTOUT
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS/UART5_DE
, FMC_NE2/FMC_NCE,
SWPMI_RX,
FT_
h
95
D14 124
144 E13
PC8
I/O
-
-
SDMMC1_D0,DCMI_D2,
EVENTOUT
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
LCD_G3,
FT_f
h
96
E13 125
145 E14
PC9
I/O
-
-
SWPMI_SUSPEND,
SDMMC1_D1,DCMI_D3,
LCD_B2, EVENTOUT
-
-
J7
-
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
126
L5
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
FT_f
ha
97
B14 127
146 E15
PA8
I/O
-
OTG_FS_SOF,
UART7_RX,
-
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
DS12919 Rev 1
77/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5,
EVENTOUT
FT_
u
98
D13 128
147 D15
PA9
PA10
PA11
I/O
I/O
I/O
-
-
-
OTG_FS_VBUS
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
FDCAN1_TXFD_MODE,
OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
FT_
u
99
C14 129
148 D14
-
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS/USART1_
NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
FT_
u
100 C15 130
149 E17
-
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/LPUART
1_DE,
SPI2_SCK/I2S2_CK,
UART4_TX,
USART1_RTS/USART1_
DE, SAI2_FS_B,
FDCAN1_TX,
FT_
u
101 B15 131
150 E16
PA12
I/O
I/O
-
-
-
-
OTG_FS_DP, LCD_R5,
EVENTOUT
PA13(JTMS/
SWDIO)
JTMS-SWDIO,
EVENTOUT
102 B13 132
103 A14 133
151 C15
152 D17
FT
VCAP
VSS
S
S
-
-
-
-
-
-
-
-
104
M6
134
153
-
78/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
105 A13 135
154 C17
155 K5
VDDLDO
VDD
-
-
-
-
-
-
-
-
-
106
-
136
S
TIM8_CH1N,
UART4_TX,
FDCAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
FT_
h
-
C13
-
156 D16
157 B17
158 B16
159 A16
PH13
PH14
PH15
PI0
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
TIM8_CH2N,
UART4_RX,
FDCAN1_RX, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
FT_
h
-
-
-
B12
D12
-
-
-
-
TIM8_CH3N,
FT_
h
FDCAN1_TXFD_MODE,
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
TIM5_CH4,
SPI2_NSS/I2S2_WS,
FDCAN1_RXFD_MODE,
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
FT_
h
-
-
J9
-
-
-
160
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
161 VDD
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
FT_
h
-
-
-
162 A15
PI1
I/O
-
-
TIM8_CH4,
FT_
h
SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
-
-
-
-
-
-
163 B15
164 C14
PI2
PI3
I/O
I/O
-
-
-
-
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10,
EVENTOUT
FT_
h
-
-
J10
-
137
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
VDD
PA14(JTCK/
SWCLK)
JTCK-SWCLK,
EVENTOUT
107 A12 138
165 B14
I/O
FT
-
-
DS12919 Rev 1
79/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS,
108 A11 139
166 A14 PA15(JTDI)
I/O
FT
-
-
UART4_RTS/UART4_DE
, UART7_TX,
EVENTOUT
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
FT_
ha
109 C12 140
167 A13
PC10
I/O
-
-
UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2,DCMI_D8,
LCD_R2, EVENTOUT
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX,
FT_
h
110 C11 141
168 B13
PC11
PC12
I/O
I/O
-
-
-
-
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3,DCMI_D4,
EVENTOUT
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK,
FT_
h
111
B11 142
169 C12
UART5_TX,
SDMMC1_CK,
DCMI_D9, EVENTOUT
-
-
J14
-
-
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
VDD
DFSDM1_CKIN6,
SAI3_SCK_A,
UART4_RX,
FT_
h
112 C10 143
170 D13
PD0
I/O
-
-
FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
80/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
DFSDM1_DATIN6,
SAI3_SD_A, UART4_TX,
FDCAN1_TX,
FMC_D3/FMC_DA3,
EVENTOUT
FT_
h
113 A10 144
171 E12
172 D12
PD1
PD2
I/O
I/O
-
-
-
-
TRACED2, TIM3_ETR,
UART5_RX,
FT_
h
114 B10 145
SDMMC1_CMD,
DCMI_D11, EVENTOUT
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_
NSS, FMC_CLK,
FT_
h
115
A9
146
173 B12
PD3
I/O
-
-
DCMI_D5, LCD_G7,
EVENTOUT
HRTIM_FLT3,
SAI3_FS_A,
FT_
h
USART2_RTS/USART2_
DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
116
117
C9
B9
147
148
174 A12
PD4
PD5
I/O
I/O
-
-
-
-
HRTIM_EEV3,
USART2_TX,
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
FT_
h
175 A11
118
119
K2
-
-
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
VDD
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
FT_
h
USART2_RX,
SAI4_SD_A,
120
D9
149
176 B11
PD6
I/O
-
-
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
DS12919 Rev 1
81/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
USART2_CK,
FT_
h
121
B8
150
177 C11
PD7
I/O
-
-
SPDIFRX1_IN1,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
TRGOUT, LCD_G3,
LCD_B0, EVENTOUT
-
-
-
-
-
-
-
-
D11
E10
PJ12
PJ13
I/O
I/O
FT
FT
-
-
-
-
LCD_B4, LCD_B1,
EVENTOUT
-
-
-
-
-
-
-
-
-
D10
B10
-
PJ14
PJ15
VSS
VDD
I/O
I/O
S
FT
FT
-
-
-
-
-
LCD_B2, EVENTOUT
-
-
-
-
-
LCD_B3, EVENTOUT
K6
-
151
152
178
-
-
179 VDD
S
-
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
QUADSPI_BK2_IO2,
SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
FT_
h
122
123
124
A8
C8
A7
153
154
155
180 A10
PG9
PG10
PG11
I/O
I/O
I/O
-
-
-
-
-
-
EVENTOUT
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
FT_
h
181
182
A9
B9
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
FT_
h
SDMMC2_D2,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
82/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_
DE, SPDIFRX1_IN2,
LCD_B4,
FT_
h
125
D8
156
183
C9
PG12
I/O
-
-
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
USART6_CTS/USART6_
NSS,
FT_
h
126
B7
157
184
D9
PG13
I/O
-
-
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
LCD_R0, EVENTOUT
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
FT_
h
USART6_TX,
127
C7
158
185
186
D8
PG14
I/O
-
-
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
K7
159
-
VSS
VDD
PK3
PK4
PK5
PK6
PK7
VSS
VDD
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
160
187 VDD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C8
B8
A8
C7
D7
-
I/O
I/O
I/O
I/O
I/O
S
FT
FT
FT
FT
FT
-
LCD_B4, EVENTOUT
LCD_B5, EVENTOUT
LCD_B6, EVENTOUT
LCD_B7, EVENTOUT
LCD_DE, EVENTOUT
-
-
-
-
-
-
-
-
-
128
129
K8
-
VDD
S
-
-
USART6_CTS/USART6_
NSS, FMC_SDNCAS,
DCMI_D13, EVENTOUT
FT_
h
-
D7
161
188
D6
PG15
I/O
-
-
DS12919 Rev 1
83/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK,
PB3(JTDO/T
RACESWO)
130
A6
162
189
C6
I/O
FT
-
-
SDMMC2_D2,
CRS_SYNC,
UART7_RX, EVENTOUT
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO,
PB4(NJTRS
T)
131
B6
163
190
B7
I/O
FT
-
-
SDMMC2_D3,
UART7_TX, EVENTOUT
TIM17_BKIN,TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI,
132
C6
164
191
A5
PB5
I/O
FT
-
-
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
-
-
K9
-
-
-
-
-
-
VSS
VDD
S
S
-
-
-
-
-
-
-
-
VDD
84/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX,
133
A5
165
192
B5
PB6
I/O FT_f
-
-
FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1, DCMI_D5,
UART5_TX, EVENTOUT
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
FT_f
134
135
136
B5
C5
A2
166
167
168
193
194
195
C5
E8
D5
PB7
BOOT0
PB8
I/O
a
-
-
-
PVD_IN
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5,
FMC_NL,DCMI_VSYNC,
EVENTOUT
I
B
-
VPP
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
FT_f
h
UART4_RX,
FDCAN1_RX,
I/O
-
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4,DCMI_D6,
LCD_B6, EVENTOUT
DS12919 Rev 1
85/252
104
Pin descriptions
STM32H755xI
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
FT_f
h
SDMMC1_CDIR,
UART4_TX,
137
B3
169
196
D4
PB9
I/O
-
-
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5,DCMI_D7,
LCD_B7, EVENTOUT
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
UART8_RX,
FDCAN1_RXFD_MODE,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
FT_
h
138
B4
170
197
198
C4
PE0
PE1
I/O
I/O
-
-
-
-
LPTIM1_IN2,
HRTIM_SCOUT,
UART8_TX,
FT_
h
139
140
C4
A4
171
172
B4
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
199
200
201
202
-
A7
B6
VCAP
VSS
S
S
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
141 K10 173
142
143
-
D4
A3
-
174
175
-
E7
PDR_ON
VDDLDO
VDD
FT
-
A6
S
S
VDD
-
TIM8_BKIN,
SAI2_MCLK_A,
FT_
h
-
-
-
203
A4
PI4
I/O
-
TIM8_BKIN_COMP12,
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
-
86/252
DS12919 Rev 1
STM32H755xI
Pin descriptions
Table 7. STM32H755xI pin/ball definition (continued)
Pin name
Pin/ball name
Additional
functions
(function
Alternate functions
after reset)
TIM8_CH1,
SAI2_SCK_A,
FMC_NBL3,
FT_
h
-
-
-
204
205
A3
A2
PI5
I/O
-
-
DCMI_VSYNC, LCD_B5,
EVENTOUT
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6,
LCD_B6, EVENTOUT
FT_
h
-
-
-
-
-
-
PI6
PI7
I/O
I/O
-
-
-
-
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7,
LCD_B7, EVENTOUT
FT_
h
206
207
B3
-
-
144
-
K12
-
176
-
VSS
VDD
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
208 VDD
M15
-
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
3. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
DS12919 Rev 1
87/252
104
Table 8. Port A alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
USART2_
CTS/
USART2_
NSS
TIM2_CH1/
TIM2_ETR
SDMMC2_
CMD
ETH_MII_
CRS
EVENT
OUT
PA0
-
-
TIM5_CH1 TIM8_ETR TIM15_BKIN
-
-
-
-
UART4_TX
UART4_RX
SAI2_SD_B
-
-
-
-
-
USART2_
RTS/
USART2_
DE
ETH_MII_RX
_CLK/ETH_
RMII_REF_
CLK
LPTIM3_
OUT
TIM15_
CH1N
QUADSPI_
BK1_IO3
SAI2_
MCLK_B
EVENT
OUT
PA1
TIM2_CH2
TIM5_CH2
LCD_R2
LPTIM4_
OUT
USART2_
TX
SAI2_SCK
_B
MDIOS_
MDIO
EVENT
OUT
PA2
PA3
PA4
PA5
-
-
TIM2_CH3
TIM2_CH4
-
TIM5_CH3
TIM5_CH4
TIM5_ETR
-
TIM15_CH1
-
-
-
-
-
-
ETH_MDIO
-
-
LCD_R1
LCD_B5
LPTIM5_
OUT
USART2_
RX
OTG_HS_
ULPI_D0
ETH_MII_
COL
EVENT
OUT
TIM15_CH2
-
LCD_B2
-
D1PWR
EN
SPI1_NSS/ SPI3_NSS/
I2S1_WS
USART2_
CK
OTG_HS_
SOF
DCMI_
HSYNC
LCD_
VSYNC
EVENT
OUT
-
-
-
SPI6_NSS
SPI6_SCK
-
-
-
-
-
I2S3_WS
D2PWR TIM2_CH1/
TIM8_
CH1N
SPI1_SCK/
I2S1_CK
OTG_HS_
ULPI_CK
EVENT
OUT
-
-
-
-
-
LCD_R4
LCD_G2
EN
-
TIM2_ETR
SPI1_
MISO/I2S1
_SDI
SPI6_
MISO
TIM8_BKIN
_COMP12
MDIOS_
MDC
TIM1_BKIN DCMI_PIX
_COMP12
EVENT
OUT
PA6
PA7
TIM1_BKIN TIM3_CH1 TIM8_BKIN
-
-
-
-
TIM13_CH1
CLK
ETH_MII_RX
_DV/ETH_
RMII_CRS_
DV
SPI1_
MOSI/I2S1
_SDO
TIM8_
TIM1_CH1N TIM3_CH2
CH1N
SPI6_
MOSI
FMC_SDN
WE
EVENT
OUT
-
-
TIM14_CH1
-
-
-
-
HRTIM_
CHB2
TIM8_BKIN
2
USART1_
CK
OTG_FS_
SOF
TIM8_BKIN
2_COMP12
EVENT
OUT
PA8
PA9
MCO1
-
TIM1_CH1
TIM1_CH2
I2C3_SCL
-
-
-
-
-
UART7_RX
-
LCD_B3
LCD_R6
LCD_R5
FDCAN1_
RXFD_
MODE
HRTIM_
CHC1
LPUART1_
TX
SPI2_SCK/
I2S2_CK
USART1_
TX
EVENT
OUT
I2C3_SMBA
-
-
DCMI_D0
FDCAN1_
TXFD_MOD
E
HRTIM_
CHC2
LPUART1_
RX
USART1_
RX
OTG_FS_
ID
MDIOS_
MDIO
EVENT
OUT
PA10
PA11
-
-
TIM1_CH3
TIM1_CH4
-
-
-
-
-
-
LCD_B4
DCMI_D1
LCD_B1
LCD_R4
USART1_
CTS/
USART1_
NSS
HRTIM_
CHD1
LPUART1_
CTS
SPI2_NSS/
I2S2_WS
FDCAN1_
RX
OTG_FS_
DM
EVENT
OUT
UART4_RX
-
-
-
Table 8. Port A alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
LPUART1_
RTS/
LPUART1_
DE
USART1_
RTS/
USART1_D
E
HRTIM_
CHD2
SPI2_SCK/
I2S2_CK
FDCAN1_
TX
OTG_FS_
DP
EVENT
OUT
PA12
-
TIM1_ETR
-
UART4_TX
SAI2_FS_B
-
-
-
-
LCD_R5
JTMS-
SWDIO
EVENT
OUT
PA13
PA14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
JTCK-
SWCLK
EVENT
OUT
-
UART4_
SPI6_NSS RTS/UART
4_DE
TIM2_CH1/
TIM2_ETR
HRTIM_
FLT1
SPI1_NSS/ SPI3_NSS/
I2S1_WS I2S3_WS
EVENT
OUT
PA15
JTDI
-
CEC
-
-
UART7_TX
-
-
-
Table 9. Port B alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
TIM8_CH2
N
DFSDM1_
CKOUT
UART4_
CTS
OTG_HS_ ETH_MII_RX
ULPI_D1 D2
EVENT
OUT
PB0
-
-
TIM1_CH2N TIM3_CH3
TIM1_CH3N TIM3_CH4
-
-
-
-
-
LCD_R3
LCD_R6
-
-
-
-
LCD_G1
LCD_G0
TIM8_CH3
N
DFSDM1_
DATIN1
OTG_HS_ ETH_MII_RX
EVENT
OUT
PB1
PB2
-
-
ULPI_D2
SAI4_D1
D3
-
SPI3_
RTC_
OUT
DFSDM1_
CKIN1
SAI4_SD_
A
QUADSPI_
CLK
EVENT
OUT
-
SAI1_D1
-
-
-
SAI1_SD_A MOSI/I2S3
_SDO
-
-
-
-
-
-
-
-
-
JTDO/
TRACE
SWO
HRTIM_
FLT4
SPI1_SCK/ SPI3_SCK/
SDMMC2_D
2
EVENT
OUT
PB3
TIM2_CH2
-
-
-
SPI6_SCK
CRS_SYNC UART7_RX
I2S1_CK
I2S3_CK
SPI1_
MISO/I2S1
_SDI
TIM16_
BKIN
HRTIM_
EEV6
SPI3_MISO/ SPI2_NSS/
I2S3_SDI
SPI6_
MISO
SDMMC2_D
3
EVENT
OUT
PB4 NJTRST
TIM3_CH1
-
UART7_TX
I2S2_WS
SPI1_
SPI3_
TIM17_
BKIN
HRTIM_
EEV7
SPI6_
MOSI
FDCAN2_
RX
OTG_HS_
ULPI_D7
ETH_PPS_ FMC_SDCK
UART5_
RX
EVENT
OUT
PB5
PB6
PB7
-
-
-
TIM3_CH2
TIM4_CH1
TIM4_CH2
I2C1_SMBA MOSI/I2S1 I2C4_SMBA MOSI/I2S3
DCMI_D10
DCMI_D5
OUT
E1
_SDO
_SDO
TIM16_CH1
N
HRTIM_
EEV8
USART1_
TX
LPUART1_
TX
FDCAN2_
TX
QUADSPI_
BK1_NCS
DFSDM1_
DATIN5
FMC_SDNE
1
UART5_
TX
EVENT
OUT
I2C1_SCL
I2C1_SDA
CEC
I2C4_SCL
I2C4_SDA
FDCAN2_
TXFD_
MODE
TIM17_CH1
N
HRTIM_
EEV9
USART1_
RX
LPUART1_
RX
DFSDM1_
CKIN5
DCMI_
VSYNC
EVENT
OUT
-
-
-
FMC_NL
-
DFSDM1_
CKIN7
SDMMC1_
CKIN
FDCAN1_
RX
SDMMC2_ ETH_MII_TX SDMMC1_
EVENT
OUT
PB8
PB9
-
-
-
TIM16_CH1 TIM4_CH3
TIM17_CH1 TIM4_CH4
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C4_SCL
I2C4_SDA
UART4_RX
UART4_TX
-
DCMI_D6
DCMI_D7
-
LCD_B6
LCD_B7
LCD_G4
D4
D3
D4
DFSDM1_
DATIN7
SPI2_NSS/
I2S2_WS
SDMMC1_
CDIR
FDCAN1_
TX
SDMMC2_
D5
SDMMC1_
D5
EVENT
OUT
I2C4_SMBA
HRTIM_SC LPTIM2_IN
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN7
USART3_
TX
QUADSPI_
BK1_NCS
OTG_HS_ ETH_MII_RX
ULPI_D3
EVENT
OUT
PB10
TIM2_CH3
TIM2_CH4
-
-
OUT
1
_ER
ETH_MII_TX
_EN/ETH_
HRTIM_
SCIN
LPTIM2_
ETR
DFSDM1_
CKIN7
USART3_
RX
OTG_HS_
ULPI_D4
EVENT
OUT
PB11
PB12
-
-
I2C2_SDA
-
-
-
-
-
LCD_G5
RMII_TX_EN
ETH_MII_TX
D0/ETH_
RMII_TXD0
SPI2_NSS/
I2S2_WS
DFSDM1_
DATIN1
USART3_
CK
FDCAN2_
RX
OTG_HS_
ULPI_D5
OTG_HS_ TIM1_BKIN UART5_
EVENT
OUT
TIM1_BKIN
TIM1_CH1N
-
-
-
I2C2_SMBA
ID
_COMP12
RX
USART3_
CTS/
USART3_
NSS
ETH_MII_
TXD1/ETH_
RMII_TXD1
LPTIM2_
OUT
SPI2_SCK/
I2S2_CK
DFSDM1_
CKIN1
FDCAN2_
TX
OTG_HS_
ULPI_D6
UART5_
TX
EVENT
OUT
PB13
-
-
-
-
-
Table 9. Port B alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
SPI2_
USART3_
RTS/USAR RTS/UART
T3_DE
UART4_
TIM12_CH TIM8_CH2
DFSDM1_
DATIN2
SDMMC2_
D0
OTG_HS_
DM
EVENT
OUT
PB14
-
TIM1_CH2N
TIM1_CH3N
USART1_TX MISO/I2S2
_SDI
-
-
-
-
-
-
-
-
1
N
4_DE
SPI2_
USART1_RX MOSI/I2S2
_SDO
RTC_
REFIN
TIM12_CH TIM8_CH3
DFSDM1_
CKIN2
UART4_
CTS
SDMMC2_D
1
OTG_HS_
DP
EVENT
OUT
PB15
-
2
N
Table 10. Port C alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
DFSDM1_
CKIN0
DFSDM1_
DATIN4
OTG_HS_
ULPI_STP
FMC_SDN
WE
EVENT
OUT
PC0
-
-
-
-
-
-
-
-
SAI2_FS_B
-
-
-
-
LCD_R5
-
SPI2_
TRACE
D0
DFSDM1_
DATIN0
DFSDM1_
CKIN4
SAI4_SD_
A
SDMMC2_
CK
MDIOS_
MDC
EVENT
OUT
PC1
PC2
PC3
PC4
PC5
SAI1_D1
MOSI/I2S2 SAI1_SD_A
_SDO
SAI4_D1
ETH_MDC
SPI2_
DFSDM1_
MISO/I2S2
CKOUT
_SDI
C1DSLE
EP
DFSDM1_
CKIN1
OTG_HS_ ETH_MII_TX FMC_SDNE
ULPI_DIR D2
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
SPI2_
MOSI/I2S2
_SDO
C1
SLEEP
DFSDM1_
DATIN1
OTG_HS_ ETH_MII_TX FMC_SDCK
ULPI_NXT
EVENT
OUT
-
-
-
-
_CLK
E0
C2
DSLEE
P
ETH_MII_RX
D0/ETH_
RMII_RXD0
DFSDM1_
CKIN2
SPDIFRX1_
IN3
FMC_SDNE
0
EVENT
OUT
-
I2S1_MCK
-
-
ETH_MII_RX
D1/ETH_
RMII_RXD1
C2
SLEEP
DFSDM1_
DATIN2
SPDIFRX1_
IN4
FMC_SDCK
E0
COMP1_
OUT
EVENT
OUT
SAI1_D3
SAI4_D3
HRTIM_CH
A1
DFSDM1_
CKIN3
USART6_
TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6
SDMMC1_
D6
LCD_
HSYNC
EVENT
OUT
PC6
PC7
-
TIM3_CH1 TIM8_CH1
TIM3_CH2 TIM8_CH2
I2S2_MCK
-
-
-
DCMI_D0
DCMI_D1
HRTIM_CH
A2
DFSDM1_
DATIN3
USART6_
RX
SDMMC1_
D123DIR
SDMMC2_
D7
SDMMC1_
D7
EVENT
OUT
TRGIO
I2S3_MCK
FMC_NE1
SWPMI_TX
LCD_G6
-
UART5_
RTS/UART
5_DE
TRACE
D1
HRTIM_CH
B1
USART6_
CK
FMC_NE2/
FMC_NCE
SDMMC1_
D0
EVENT
OUT
PC8
TIM3_CH3 TIM8_CH3
-
-
-
-
-
SWPMI_RX
DCMI_D2
UART5_
CTS
QUADSPI_
BK1_IO0
SWPMI_
SUSPEND
SDMMC1_
D1
EVENT
OUT
PC9
PC10
PC11
PC12
PC13
MCO2
-
-
-
-
-
TIM3_CH4 TIM8_CH4
HRTIM_EE DFSDM1_
I2C3_SDA
I2S_CKIN
-
LCD_G3
DCMI_D3
DCMI_D8
DCMI_D4
DCMI_D9
-
LCD_B2
SPI3_SCK/I
2S3_CK
USART3_
TX
QUADSPI_
BK1_IO1
SDMMC1_
D2
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
UART4_TX
UART4_RX
UART5_TX
-
-
-
-
-
-
-
-
-
LCD_R2
V1
CKIN5
HRTIM_
FLT2
DFSDM1_
DATIN5
SPI3_MISO/ USART3_
I2S3_SDI RX
QUADSPI_
BK2_NCS
SDMMC1_
D3
EVENT
OUT
-
-
-
TRACE
D3
HRTIM_EE
V2
SPI3_MOSI/ USART3_
SDMMC1_
CK
EVENT
OUT
-
-
-
-
I2S3_SDO
CK
EVENT
OUT
-
-
-
-
-
Table 10. Port C alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
EVENT
OUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC15
Table 11. Port D alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/3/
6/UART7/SD
MMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
DFSDM1_
CKIN6
SAI3_SCK_
A
FDCAN1_
RX
FMC_D2/
FMC_DA2
EVENT
OUT
PD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART4_RX
UART4_TX
UART5_RX
-
-
-
-
-
-
-
-
-
-
DFSDM1_
DATIN6
FDCAN1_
TX
FMC_D3/
FMC_DA3
EVENT
OUT
PD1
PD2
-
SAI3_SD_A
-
-
TRACE
D2
SDMMC1_
CMD
EVENT
OUT
TIM3_ETR
-
-
-
DCMI_D11
USART2_
CTS/
USART2_
NSS
DFSDM1_
CKOUT
SPI2_SCK/
I2S2_CK
EVENT
OUT
PD3
-
-
-
-
-
-
-
-
FMC_CLK
DCMI_D5
LCD_G7
USART2_
SAI3_FS_A RTS/USART2
_DE
FDCAN1_
RXFD_
MODE
HRTIM_
FLT3
EVENT
OUT
PD4
PD5
PD6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NOE
FMC_NWE
-
-
FDCAN1_
TXFD_
MODE
HRTIM_EE
V3
USART2_
TX
EVENT
OUT
-
-
-
-
-
SPI3_
FDCAN2_
RXFD_
MODE
DFSDM1_
CKIN4
DFSDM1_
DATIN1
USART2_
RX
SAI4_SD_
A
SDMMC2_
CK
FMC_
NWAIT
EVENT
OUT
SAI1_D1
MOSI/I2S3 SAI1_SD_A
_SDO
SAI4_D1
DCMI_D10
LCD_B2
SPI1_
DFSDM1_
MOSI/I2S1
CKIN1
DFSDM1_
DATIN4
USART2_
CK
SPDIFRX1_
IN1
SDMMC2_
CMD
EVENT
OUT
PD7
PD8
PD9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NE1
-
-
-
-
-
-
_SDO
DFSDM1_
CKIN3
SAI3_SCK_
USART3_
TX
SPDIFRX1_
IN2
FMC_D13/
FMC_DA13
EVENT
OUT
-
-
-
B
FDCAN2_
RXFD_
MODE
DFSDM1_
DATIN3
USART3_
RX
FMC_D14/
FMC_DA14
EVENT
OUT
-
-
SAI3_SD_B
SAI3_FS_B
FDCAN2_
TXFD_
MODE
DFSDM1_
CKOUT
USART3_
CK
FMC_D15/
FMC_DA15
EVENT
OUT
PD10
PD11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
USART3_
CTS/
USART3_
NSS
LPTIM2_
IN2
QUADSPI_
BK1_IO0
EVENT
OUT
I2C4_SMBA
-
-
-
-
SAI2_SD_A
FMC_A16
FMC_A17
-
USART3_
RTS/
USART3_
LPTIM2_IN
1
QUADSPI_
BK1_IO1
EVENT
OUT
PD12
-
LPTIM1_IN1 TIM4_CH1
I2C4_SCL
-
SAI2_FS_A
-
-
-
DE
Table 11. Port D alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/3/
6/UART7/SD
MMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
LPTIM1_
OUT
QUADSPI_ SAI2_SCK_
EVENT
OUT
PD13
-
-
TIM4_CH2
TIM4_CH3
-
-
I2C4_SDA
-
-
-
-
-
-
-
-
-
FMC_A18
-
-
-
-
BK1_IO3
A
SAI3_MCLK
_B
UART8_
CTS
FMC_D0/
FMC_DA0
EVENT
OUT
PD14
PD15
-
-
-
-
UART8_
RTS/
UART8_DE
SAI3_MCLK
_A
FMC_D1/
FMC_DA1
EVENT
OUT
-
TIM4_CH4
-
-
-
-
-
-
-
-
-
Table 12. Port E alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
FDCAN1_
RXFD_
MODE
LPTIM1_
ETR
HRTIM_
SCIN
LPTIM2_
ETR
SAI2_
MCLK_A
EVENT
OUT
PE0
-
-
TIM4_ETR
-
-
-
-
-
-
-
UART8_RX
UART8_TX
-
-
FMC_NBL0
FMC_NBL1
DCMI_D2
DCMI_D3
-
-
FDCAN1_
TXFD_
MODE
HRTIM_
SCOUT
EVENT
OUT
PE1
LPTIM1_IN2
-
-
TRACE
CLK
SAI1_MCLK
_A
SAI4_
MCLK_A
QUADSPI_
BK1_IO2
ETH_MII_TX
D3
EVENT
OUT
PE2
PE3
PE4
PE5
PE6
PE7
PE8
-
-
-
-
SAI1_CK1
-
-
-
SPI4_SCK
-
-
SAI4_CK1
-
FMC_A23
FMC_A19
FMC_A20
FMC_A21
FMC_A22
-
-
TRACE
D0
SAI4_SD_
B
EVENT
OUT
-
TIM15_BKIN
SAI1_SD_B
-
-
-
-
-
-
-
TRACE
D1
DFSDM1_
DATIN3
TIM15_CH1
N
EVENT
OUT
SAI1_D2
SPI4_NSS SAI1_FS_A
-
SAI4_FS_A
-
SAI4_D2
SAI4_CK2
DCMI_D4
DCMI_D6
DCMI_D7
-
LCD_B0
TRACE
D2
DFSDM1_
CKIN3
SPI4_
MISO
SAI1_SCK_
A
SAI4_SCK
_A
EVENT
OUT
SAI1_CK2
TIM15_CH1
-
-
LCD_G0
TRACE
D3
TIM1_BKIN
2
SPI4_
MOSI
SAI4_SD_
A
SAI2_
MCLK_B
TIM1_BKIN2
_COMP12
EVENT
OUT
SAI1_D1
-
TIM15_CH2
SAI1_SD_A
-
SAI4_D1
LCD_G1
DFSDM1_
DATIN2
QUADSPI_
BK2_IO0
FMC_D4/
FMC_DA4
EVENT
OUT
-
-
TIM1_ETR
-
-
-
-
-
-
-
-
UART7_RX
UART7_TX
-
-
-
-
-
-
-
-
DFSDM1_
CKIN2
QUADSPI_
BK2_IO1
FMC_D5/
FMC_DA5
COMP2_
OUT
EVENT
OUT
TIM1_CH1N
UART7_
RTS/
UART7_DE
DFSDM1_
CKOUT
QUADSPI_
BK2_IO2
FMC_D6/
FMC_DA6
EVENT
OUT
PE9
-
TIM1_CH1
-
-
-
-
-
-
-
-
-
DFSDM1_
DATIN4
UART7_
CTS
QUADSPI_
BK2_IO3
FMC_D7/
FMC_DA7
EVENT
OUT
PE10
PE11
PE12
PE13
-
-
-
-
TIM1_CH2N
TIM1_CH2
TIM1_CH3N
TIM1_CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_
CKIN4
FMC_D8/
FMC_DA8
EVENT
OUT
SPI4_NSS
SPI4_SCK
-
-
-
SAI2_SD_B
LCD_G3
LCD_B4
LCD_DE
DFSDM1_
DATIN5
SAI2_SCK_
B
FMC_D9/
FMC_DA9
COMP1_
OUT
EVENT
OUT
DFSDM1_
CKIN5
SPI4_
MISO
FMC_D10/
FMC_DA10
COMP2_
OUT
EVENT
OUT
SAI2_FS_B
Table 12. Port E alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
SPI4_
MOSI
SAI2_MCL
K_B
FMC_D11/
FMC_DA11
LCD_CL
K
EVENT
OUT
PE14
-
-
TIM1_CH4
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_BKIN
FMC_D12/ _COMP12/
FMC_DA12
EVENT
OUT
PE15
-
-
LCD_R7
COMP_
TIM1_BKIN
Table 13. Port F alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
EVENT
OUT
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A0
FMC_A1
FMC_A2
FMC_A3
FMC_A4
FMC_A5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PF1
PF2
PF3
PF4
PF5
PF6
PF7
-
I2C2_SCL
EVENT
OUT
-
I2C2_SMBA
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
-
EVENT
OUT
-
SAI4_SD_
B
QUADSPI_
BK1_IO3
EVENT
OUT
TIM16_CH1
TIM17_CH1
SPI5_NSS SAI1_SD_B UART7_RX
SAI1_MCLK
SAI4_
MCLK_B
QUADSPI_
BK1_IO2
EVENT
OUT
SPI5_SCK
UART7_TX
-
_B
UART7_
RTS/
UART7_DE
TIM16_CH1
N
SPI5_
MISO
SAI1_SCK_
B
SAI4_SCK
_B
QUADSPI_
BK1_IO0
EVENT
OUT
PF8
-
-
-
-
TIM13_CH1
-
-
-
-
-
-
TIM17_CH1
N
SPI5_
MOSI
UART7_
CTS
QUADSPI_
BK1_IO1
EVENT
OUT
PF9
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI1_FS_B
SAI4_FS_B TIM14_CH1
-
-
-
-
-
-
-
-
-
TIM16_BKI
N
QUADSPI_
CLK
EVENT
OUT
PF10
PF11
PF12
PF13
PF14
PF15
SAI1_D3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI4_D3
DCMI_D11 LCD_DE
SPI5_
MOSI
FMC_
SDNRAS
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_SD_B
DCMI_D12
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
FMC_A6
FMC_A7
FMC_A8
FMC_A9
-
-
-
-
DFSDM1_
DATIN6
EVENT
OUT
I2C4_SMBA
I2C4_SCL
I2C4_SDA
DFSDM1_
CKIN6
EVENT
OUT
EVENT
OUT
-
Table 14. Port G alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
EVENT
OUT
PG0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
FMC_A11
FMC_A12
FMC_A13
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PG1
PG2
PG3
PG4
PG5
PG6
PG7
-
TIM8_BKIN_
COMP12
EVENT
OUT
TIM8_BKIN
TIM8_BKIN
2
TIM8_BKIN2
_COMP12
EVENT
OUT
TIM1_BKIN
2
TIM1_BKIN2 FMC_A14/
_COMP12
EVENT
OUT
-
-
-
-
FMC_BA0
FMC_A15/
FMC_BA1
EVENT
OUT
TIM1_ETR
-
TIM17_
BKIN
HRTIM_
CHE1
QUADSPI_
BK1_NCS
EVENT
OUT
-
-
FMC_NE3
FMC_INT
DCMI_D12 LCD_R7
HRTIM_
CHE2
SAI1_MCLK USART6_
LCD_CL
EVENT
OUT
-
-
-
-
DCMI_D13
K
_A
-
CK
USART6_
RTS/
USART6_
DE
SPDIFRX1
_
IN3
ETH_PPS_
OUT
FMC_
SDCLK
EVENT
OUT
PG8
-
-
-
TIM8_ETR
-
SPI6_NSS
-
-
LCD_G7
SPI1_
MISO/I2S1
_SDI
USART6_
RX
SPDIFRX1
_
IN4
QUADSPI_
BK2_IO2
FMC_NE2/
FMC_NCE
DCMI_
VSYNC
EVENT
OUT
PG9
PG10
PG11
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI2_FS_B
SAI2_SD_B
-
-
HRTIM_
FLT5
SPI1_NSS/
I2S1_WS
EVENT
OUT
-
-
-
-
LCD_G3
-
-
FMC_NE3
-
DCMI_D2
DCMI_D3
LCD_B2
LCD_B3
ETH_MII_
HRTIM_
EEV4
SPI1_SCK/
I2S1_CK
SPDIFRX1
_
IN1
SDMMC2_ TX_EN/ETH
EVENT
OUT
LPTIM1_IN2
D2
_RMII_TX_
EN
USART6_
RTS/
USART6_
DE
ETH_MII_TX
D1/ETH_
RMII_TXD1
HRTIM_
EEV5
SPI6_
MISO
EVENT
OUT
PG12
-
LPTIM1_IN1
-
-
-
SPDIFRX1
_IN2
LCD_B4
-
FMC_NE4
-
LCD_B1
Table 14. Port G alternate functions (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
USART6_
CTS/
USART6_
NSS
ETH_MII_TX
D0/ETH_
RMII_TXD0
TRACE
D0
LPTIM1_
OUT
HRTIM_
EEV10
EVENT
OUT
PG13
-
-
-
-
-
-
SPI6_SCK
-
-
-
-
-
-
-
-
-
-
FMC_A24
FMC_A25
-
LCD_R0
LCD_B0
-
ETH_MII_TX
D1/ETH_
RMII_TXD1
TRACE
D1
LPTIM1_
ETR
SPI6_
MOSI
USART6_
TX
QUADSPI_
BK2_IO3
EVENT
OUT
PG14
PG15
-
-
-
USART6_
CTS/
USART6_
NSS
FMC_
SDNCAS
EVENT
OUT
-
-
-
-
-
DCMI_D13
Table 15. Port H alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
EVENT
OUT
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PH1
PH2
-
-
-
-
-
-
QUADSPI_ SAI2_SCK_
BK2_IO0
ETH_MII_
CRS
FMC_
SDCKE0
EVENT
OUT
LPTIM1_IN2
-
-
-
-
LCD_R0
LCD_R1
LCD_G4
-
B
QUADSPI_
BK2_IO1
SAI2_
MCLK_B
ETH_MII_
COL
FMC_SDNE
0
EVENT
OUT
PH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OTG_HS_U
LPI_NXT
EVENT
OUT
PH4
I2C2_SCL
I2C2_SDA
-
-
LCD_G5
-
-
-
-
FMC_SDN
WE
EVENT
OUT
PH5
SPI5_NSS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM12_CH
1
ETH_MII_RX FMC_SDNE
EVENT
OUT
PH6
I2C2_SMBA SPI5_SCK
-
DCMI_D8
DCMI_D9
-
D2
1
SPI5_
I2C3_SCL
ETH_MII_RX
D3
FMC_
SDCKE1
EVENT
OUT
PH7
-
-
-
MISO
DCMI_HSY
NC
EVENT
OUT
PH8
TIM5_ETR
I2C3_SDA
I2C3_SMBA
I2C4_SMBA
I2C4_SCL
I2C4_SDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D16
FMC_D17
FMC_D18
FMC_D19
FMC_D20
FMC_D21
FMC_D22
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_G2
LCD_G3
TIM12_CH
2
EVENT
OUT
PH9
-
DCMI_D0
DCMI_D1
DCMI_D2
DCMI_D3
-
EVENT
OUT
PH10
PH11
PH12
PH13
PH14
TIM5_CH1
-
EVENT
OUT
TIM5_CH2
-
EVENT
OUT
TIM5_CH3
-
TIM8_CH1
N
FDCAN1_
TX
EVENT
OUT
-
-
UART4_TX
UART4_RX
TIM8_CH2
N
FDCAN1_
RX
EVENT
OUT
-
DCMI_D4
FDCAN1_
TXFD_
MODE
TIM8_CH3
N
EVENT
OUT
PH15
-
-
-
-
-
-
-
-
-
-
FMC_D23
DCMI_D11 LCD_G4
Table 16. Port I alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
SPI2_NSS/
I2S2_WS
FDCAN1_
RXFD_MODE
EVENT
OUT
PI0
-
-
-
-
TIM5_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D24
FMC_D25
DCMI_D13 LCD_G5
TIM8_BKIN
2
SPI2_SCK/
I2S2_CK
TIM8_BKIN2
_COMP12
EVENT
OUT
PI1
PI2
-
-
DCMI_D8
DCMI_D9
LCD_G6
LCD_G7
SPI2_MIS
O/I2S2_SD
I
EVENT
OUT
-
-
-
-
-
-
TIM8_CH4
TIM8_ETR
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D26
FMC_D27
SPI2_
MOSI/I2S2
_SDO
EVENT
OUT
PI3
-
DCMI_D10
DCMI_D5
-
SAI2_
MCLK_A
TIM8_BKIN_
COMP12
EVENT
OUT
PI4
PI5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NBL2
LCD_B4
LCD_B5
LCD_B6
LCD_B7
-
SAI2_SCK_
A
DCMI_
VSYNC
EVENT
OUT
TIM8_CH1
-
-
-
-
-
-
FMC_NBL3
EVENT
OUT
PI6
TIM8_CH2
-
SAI2_SD_A
FMC_D28
DCMI_D6
EVENT
OUT
PI7
TIM8_CH3
-
SAI2_FS_A
FMC_D29
DCMI_D7
EVENT
OUT
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FDCAN1_
RX
LCD_VS EVENT
YNC OUT
PI9
UART4_RX
FMC_D30
FDCAN1_
RXFD_MODE
ETH_MII_RX
_ER
LCD_HS EVENT
PI10
PI11
PI12
PI13
PI14
PI15
-
-
-
-
-
-
FMC_D31
YNC
OUT
OTG_HS_
ULPI_DIR
EVENT
OUT
LCD_G6
-
-
-
-
-
-
-
-
-
-
-
LCD_HS EVENT
YNC OUT
-
-
-
-
-
LCD_VS EVENT
-
YNC
OUT
LCD_CL
K
EVENT
OUT
-
EVENT
OUT
LCD_G2
LCD_R0
Table 17. Port J alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
EVENT
OUT
PJ0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R1
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_R7
LCD_G0
LCD_G1
LCD_G2
LCD_G3
LCD_G4
LCD_B0
LCD_B1
LCD_B2
LCD_B3
EVENT
OUT
PJ1
PJ2
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
EVENT
OUT
PJ3
-
-
-
-
-
EVENT
OUT
PJ4
-
-
-
-
-
EVENT
OUT
PJ5
-
-
-
-
-
EVENT
OUT
PJ6
-
-
TIM8_CH2
-
-
TIM8_CH2
N
EVENT
OUT
PJ7
TRGIN
-
-
-
EVENT
OUT
PJ8
-
-
-
-
TIM1_CH3N
TIM8_CH1
UART8_TX
-
TIM8_CH1
N
EVENT
OUT
PJ9
TIM1_CH3
UART8_RX
-
SPI5_
MOSI
EVENT
OUT
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
TIM1_CH2N
TIM8_CH2
-
-
-
-
-
-
-
TIM8_CH2
N
SPI5_µ
MISO
EVENT
OUT
TIM1_CH2
-
TRGOU
T
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G3
EVENT
OUT
-
-
-
LCD_B4
EVENT
OUT
-
-
EVENT
OUT
Table 18. Port K alternate functions
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM/
SDMMC2/
MDIOS/ETH
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM/CEC
SPI6/SAI2/
4/UART4/5
/8/LPUART
/SDMMC1/
SPDIFRX1
TIM1/8/FM
C/SDMMC1
/MDIOS/
OTG1_FS/
LCD
SPI2/3/SAI1
/3/I2C4/
UART4/
SPI2/3/6/
USART1/2/
3/6/UART7
/SDMMC1
Port
TIM1/2/16/1 SAI1/TIM3/
7/LPTIM1/
HRTIM1
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD/CRS
TIM1/
DCMI/LCD/
COMP
SPI1/2/3/4/
5/6/CEC
UART5/
LCD
4/5/12/
HRTIM1
DFSDM
EVENT
OUT
PK0
-
-
-
-
-
-
-
-
TIM1_CH1N
-
-
-
-
-
-
-
-
TIM8_CH3
-
-
-
-
-
-
-
-
SPI5_SCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G5
LCD_G6
LCD_G7
LCD_B4
LCD_B5
LCD_B6
LCD_B7
LCD_DE
TIM8_CH3
N
EVENT
OUT
PK1
PK2
PK3
PK4
PK5
PK6
PK7
TIM1_CH1
SPI5_NSS
TIM8_BKIN TIM1_BKIN_
_COMP12
EVENT
OUT
TIM1_BKIN
TIM8_BKIN
-
-
-
-
-
-
COMP12
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
EVENT
OUT
EVENT
OUT
EVENT
OUT
STM32H755xI
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at T = 25 °C and T = T (given by the
J
J
Jmax
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
J
DD
1.7 V ≤ V
tested.
≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
MCU pin
MCU pin
V
C =50 pF
IN
MS19011V2
MS19010V2
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STM32H755xI
6.1.6
Power supply scheme
Figure 13. Power supply scheme
VDD50USB
VDD33USB
VDD33USB
VDD50USB
USB
IOs
VSS
VDDSMPS
VLXSMPS
VFBSMPS
VSSSMPS
VDDLDO
VCAP
Step
Down
Coverter
(SMPS)
USB
VSS
regulator
Core domain (VCORE
)
Voltage
regulator
VDDLDO
VSS
D3 domain
(System
logic,
D1 domain
(CPU, peripherals,
RAM)
D2 domain
(peripherals,
RAM)
EXTI,
IO
logic
IOs
Peripherals,
RAM)
Flash
VDD
VSS
VDD domain
HSI, CSI,
VDD
HSI48,
HSE, PLLs
VBAT
charging
Backup domain
Backup
regulator
VBAT
1.2 to 3.6V
VSW
VBKP
VBAT
Power switch
Power switch
LSI, LSE,
RTC, Wakeup
logic, backup
Backup
RAM
BKUP
IOs
IO
logic
registers,
Reset
VREF
VDDA
VSS
VDDA
VSS
Analog domain
REF_BUF
ADC, DAC
VREF+
VREF-
OPAMP,
Comparator
VREF+
VREF-
VSSA
MSv62410V1
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution:
Each power supply pair (V /V , V
/V
...) must be decoupled with filtering ceramic
DD SS
DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
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Electrical characteristics
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7
Current consumption measurement
Figure 14. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics,
Table 20: Current characteristics, and Table 21: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
(1)
Table 19. Voltage characteristics
Symbols
Ratings
Min
Max
Unit
External main supply voltage (including VDD
,
VDDX - VSS
−0.3
4.0
V
VDDLDO, VDDSMPS, VDDA, VDD33USB, VBAT
)
Min(VDD, VDDA
,
Input voltage on FT_xxx pins
VSS−0.3
VDD33USB, VBAT
)
V
+4.0(3)(4)
(2)
VIN
Input voltage on TT_xx pins
Input voltage on BOOT0 pin
Input voltage on any other pins
V
V
SS-0.3
VSS
4.0
9.0
4.0
V
V
V
SS-0.3
Variations between different VDDX power pins
of the same domain
|ꢀVDDX
|
-
-
50
50
mV
mV
|VSSx-VSS
|
Variations between all the different ground pins
1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 67: I/O current injection susceptibility for the
maximum allowed injected current values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
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Electrical characteristics
Symbols
STM32H755xI
Table 20. Current characteristics
Ratings
Max
Unit
ΣIVDD
ΣIVSS
IVDD
IVSS
IIO
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
620
620
100
100
20
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
140
140
mA
ΣI(PIN)
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
(3)(4)
IINJ(PIN)
Injected current on PA4, PA5
−0/0
ΣIINJ(PIN)
Total injected current (sum of all I/Os and control pins)(5)
±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 19: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 21. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
− 65 to +150
125(1)
°C
TJ
Maximum junction temperature
140(2)
1. For industrial temperature range 6.
2. For extended industrial temperature range 3.
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Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 22. General operating conditions
Operating
conditions
Symbol
VDD
Parameter
Min
Typ
Max
Unit
V
-
Standard operating voltage
-
1.62(1)
1.62(1)
1.2(2)
3.6
3.6
3.6
-
-
Supply voltage for the internal
regulator
VDDLDO
VDDLDO ≤ VDD
V
Supply voltage for the internal SMPS
Step-down converter
VDDSMPS
VDDSMPS = VDD
1.62(1)
-
3.6
V
USB used
3.0
0
-
-
-
-
-
-
3.6
3.6
Standard operating voltage, USB
domain
VDD33USB
USB not used
ADC or COMP used
DAC used
1.62
1.8
2.0
1.8
OPAMP used
VREFBUF used
VDDA
Analog operating voltage
3.6
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
V
0
-
TT_xx I/O
BOOT0
−0.3
-
-
VDD+0.3
9
0
VIN
I/O Input voltage
Min(VDD, VDDA
,
All I/O except BOOT0
and TT_xx
VDD33USB
+3.6V <
)
−0.3
-
5.5V(3)(4)
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Table 22. General operating conditions (continued)
Operating
conditions
Symbol
Parameter
Min
Typ
Max
Unit
VOS3 (max frequency
200 MHz)
0.95
1.05
1.15
1.26
0.95
1.05
1.15
0.98
1.08
1.17
1.37
1.0
1.26
1.26
1.26
1.40
1.26
1.26
1.26
1.26
1.26
1.26
1.40
VOS2 (max frequency
300 MHz)
1.10
1.20
1.35
1.0
Internal regulator ON (LDO)
VOS1 (max frequency
400 MHz)
VOS0(5) (max
frequency 480 MHz(6)
)
VOS3 (max frequency
200 MHz)
Internal regulator ON (SMPS step-
down converter)(7)
VOS2 (max frequency
300 MHz)
VCORE
1.10
1.20
1.03
1.13
1.23
1.38
V
VOS1 (max frequency
400 MHz)
VOS3 (max frequency
200 MHz)
VOS2 (max frequency
300 MHz)
Regulator OFF: external VCORE
voltage must be supplied from external
regulator on two VCAP pins
VOS1 (max frequency
400 MHz)
VOS0 (max frequency
480 MHz(6)
)
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Symbol
Electrical characteristics
Table 22. General operating conditions (continued)
Operating
conditions
Parameter
Min
Typ
Max
Unit
VOS3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
300
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
VOS3
VOS2
VOS1
VOS0
fCPU1
fCPU2
fACLK
fHCLK
fPCLK
Arm® Cortex®-M7 clock frequency
Arm® Cortex®-M4 clock frequency
AXI clock frequency
400
480(6)
200
150
200
240(6)
100
150
MHz
200
240(6)
100
150
AHB clock frequency
200
240(6)
50(8)
75
APB clock frequency
100
120(6)
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. Only for power-up sequence when the SMPS step-down converter is configured to supply the LDO and TJMax = 105 °C.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
4. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
5. VOS0 is available only when the LDO regulator is ON.
6. TJmax = 105 °C.
7. At startup, the external VCORE voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO).
8. Maximum APB clock frequency when at least one peripheral is enabled.
Table 23. Supply voltage and maximum frequency configuration
Power scale
VCORE source
Max TJ (°C)
Max frequency (MHz)
Min VDD (V)
LDO
105
480
1.7
VOS0
SMPS step-down
converter(1)
-
-
-
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Electrical characteristics
STM32H755xI
Table 23. Supply voltage and maximum frequency configuration (continued)
Power scale
VCORE source
Max TJ (°C)
Max frequency (MHz)
Min VDD (V)
LDO
VOS1
125
400
1.62
SMPS step-down
converter
LDO
125
125
VOS2
VOS3
300
64
1.62
1.2(2)
1.62
SMPS step-down
converter
140
LDO(2)
LDO
105
125
125
200
SMPS step-down
converter
140(3)
LDO
105
SVOS4
SVOS5
125
N/A
N/A
1.62
1.62
SMPS step-down
converter
140(3)
LDO
105
125
SMPS step-down
converter
140(3)
1. VOS0 (power scale 0) is not available when the SMPS step-down converter directly supplies VCORE
2. Only for power-up sequence when the SMPS step-down converter supplies the LDO.
3. Extended Industrial temperature range sales types (range 3).
.
6.3.2
VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
to
EXT
the VCAP pin. C
VCAP pins.
is specified in Table 24. Two external capacitors can be connected to
EXT
Figure 15. External capacitor C
EXT
C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
(1)
Table 24. VCAP operating conditions
Parameter
Symbol
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF(2)
< 100 mΩ
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Electrical characteristics
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
6.3.3
SMPS step-down converter
The devices embed a high power efficiency SMPS step-down converter. SMPS
characteristics for external usage are given in Table 26. The SMPS step-down converter
requires external components that are specified in Figure 16 and Table 25.
Figure 16. External components for SMPS step-down converter
VDDSMPS
VDDSMPS
VDDSMPS
VDDSMPS
VDD
VDD
VDD
VDD
L
VLXSMPS
VLXSMPS
L
VLXSMPS
VLXSMPS
Cin
Cin
SMPS
SMPS
SMPS
SMPS
Cfilt
Cfilt
VFBSMPS
VFBSMPS
VFBSMPS
VFBSMPS
(ON)
(ON)
(ON)
(ON)
VDD_
VDD
External
External
Cout1
2xCout
VSSSMPS
VSSSMPS
VSSSMPS
VSSSMPS
VCAP
VCAP
VCAP
VCAP
VDDLDO
VDDLDO
VDDLDO
VDDLDO
VCORE
VCORE
VCORE
VCORE
V reg
V reg
V reg
V reg
Cout2
CEXT
(OFF)
(OFF)
(ON)
(ON)
VSS
VSS
VSS
VSS
External SMPS supply, LDO supplied
by SMPS
Direct SMPS supply
MSv61398V2
Table 25. Characteristics of SMPS step-down converter external components
Symbol
Parameter
Conditions
Capacitance of external capacitor on VDDSMPS
ESR of external capacitor
4.7 µF
100 mΩ
220 pF
10 µF
Cin
Cfilt
Capacitance of external capacitor on VLXSMPS pin
Capacitance of external capacitor on VFBSMPS pin
ESR of external capacitor
COUT
20 mΩ
2.2 µH
150 mΩ
L
-
Inductance of external Inductor on VLXSMPS pin
Serial DC resistor
DC current at which the inductance drops 30% from
its value without current.
ISAT
1.7 A
1.4 A
Average current for a 40 °C rise: rated current for
which the temperature of the inductor is raised 40°C
by DC current
IRMS
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Electrical characteristics
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Table 26. SMPS step-down converter characteristics for external usage
Parameters
Conditions
Min
Typ
Max
Unit
VOUT = 1.8 V
VOUT = 2.5 V
2.3
-
3.6
3.6
(1)
VDDSMPS
V
3
-
2.5
1.8
-
2.25
2.75
1.98
600
600
120
-
(2)
VOUT
Iout=600 mA
V
1.62
internal and external usage
External usage only(3)
-
-
-
-
-
-
-
IOUT
mA
-
RDSON
100
220
-
mꢁ
IDDSMPS_Q
Quiescent current
VOUT = 1.8 V
µA
225
300
TSMPS_START
µs
VOUT = 2.5 V
-
1. The switching frequency is 2.4 MHz±10%
2. Including line transient and load transient.
3. These characteristics are given for SDEXTHP bit is set in the PWR_CR3 register.
6.3.4
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 27. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
Min
Max
Unit
0
10
0
∞
∞
∞
∞
∞
∞
tVDD
VDD fall time rate
VDDA rise time rate
tVDDA
µs/V
V
DDA fall time rate
VDDUSB rise time rate
DDUSB fall time rate
10
0
tVDDUSB
V
10
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Electrical characteristics
6.3.5
Embedded reset and power control block characteristics
The parameters given in Table 28 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions.
Table 28. Reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset temporization
after BOR0 released
(1)
tRSTTEMPO
-
-
377
-
µs
Rising edge(1)
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge in Run mode
1.62
1.58
2.04
1.95
2.34
2.25
2.63
2.54
1.90
1.81
2.05
1.96
2.19
2.10
2.35
2.25
2.49
2.39
2.64
2.55
2.78
2.69
1.67
1.62
2.10
2.00
2.41
2.31
2.70
2.61
1.96
1.86
2.10
2.01
2.26
2.15
2.41
2.31
2.56
2.45
2.71
2.61
2.86
2.76
1.71
1.68
2.15
2.06
2.47
2.37
2.78
2.68
2.01
1.91
2.16
2.06
2.32
2.21
2.47
2.37
2.62
2.51
2.78
2.68
2.94
2.83
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
VBOR1
VBOR2
VBOR3
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Programmable Voltage
Detector threshold 0
Programmable Voltage
Detector threshold 1
V
Programmable Voltage
Detector threshold 2
Programmable Voltage
Detector threshold 3
Programmable Voltage
Detector threshold 4
Programmable Voltage
Detector threshold 5
Programmable Voltage
Detector threshold 6
Hysteresis voltage of BOR
(unless BOR0) and PVD
Vhyst_BOR_PVD
Hysteresis in Run mode
-
-
-
100
-
mV
µA
BOR(2) (unless BOR0) and
PVD consumption from VDD
(1)
IDD_BOR_PVD
0.630
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Table 28. Reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
1.66
1.56
2.06
1.96
2.42
2.35
2.74
2.64
1.71
1.61
2.12
2.02
2.50
2.42
2.83
2.72
1.76
1.66
2.19
2.08
2.58
2.49
2.91
2.80
Analog voltage detector for
VDDA threshold 0
VAVM_0
Analog voltage detector for
VDDA threshold 1
VAVM_1
VAVM_2
VAVM_3
V
Analog voltage detector for
VDDA threshold 2
Analog voltage detector for
VDDA threshold 3
Hysteresis of VDDA voltage
detector
Vhyst_VDDA
IDD_PVM
-
-
-
-
100
-
mV
µA
µA
PVM consumption from
VDD(1)
-
-
-
0.25
2.5
Voltage detector
consumption on VDDA
IDD_VDDA
Resistor bridge
(1)
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 6.3.7: Supply current characteristics).
6.3.6
Embedded reference voltage
The parameters given in Table 29 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions.
Table 29. Embedded reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
-40°C < TJ < 140 °C,
VDD = 3.3 V
Internal reference voltages
1.180
1.216
1.255
V
ADC sampling time when
reading the internal reference
voltage
(1)(2)
tS_vrefint
-
-
4.3
-
-
µs
VBAT sampling time when
reading the internal VBAT
reference voltage
(1)(2)
tS_vbat
9
9
-
-
13.5
5
-
Reference Buffer
consumption for ADC
(2)
Irefbuf
V
DDA=3.3 V
23
15
µA
Internal reference voltage
spread over the temperature
range
(2)
(2)
ΔVREFINT
-40°C < TJ < 140 °C
mV
Average temperature
coefficient
Average temperature
coefficient
(2)
Tcoeff
-
-
20
10
70
ppm/°C
ppm/V
VDDcoeff
Average Voltage coefficient
3.0V < VDD < 3.6V
1370
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Symbol
Electrical characteristics
Table 29. Embedded reference voltage (continued)
Parameter
Conditions
Min
Typ
25
Max
Unit
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
-
-
-
-
-
-
-
-
-
%
50
VREFINT
75
1. The shortest sampling time for the application can be determined by multiple iterations.
2. Guaranteed by design.
Table 30. Internal reference voltage calibration values
Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
Symbol
6.3.7
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode.
All peripherals are disabled except when explicitly mentioned.
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (f
) frequency and V
range” available in the reference manual).
rcc_c_ck
CORE
•
When the peripherals are enabled, the AHB clock frequency is the CPU1 frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in the below tables are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22: General operating
conditions.
DS12919 Rev 1
117/252
228
Electrical characteristics
STM32H755xI
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4
(1)(2)
(ART accelerator ON), LDO regulator ON
Arm
Arm
Max(3)
Cortex- Cortex-
Symbol Parameter
Conditions
M7
fCPU1
(MHz)
M4
fCPU2
(MHz)
Typ
Unit
Tj=
Tj=
Tj=
Tj=
Tj=
25 °C 85 °C 105°C 125°C 140°C
480
400
400
300
200
480
400
400
300
200
240
200
200
150
100
240
200
200
150
100
179
151
132
91
272
-
387
-
498
-
VOS0
All
peripherals VOS1
181
122
79
292
211
150
462
-
382
281
206
571
-
502
377
284
disabled
VOS2
Supply
current in
Run mode
VOS3
VOS0
56
382
406
IDD
mA
247
208
181
126
78
374
-
All
peripherals VOS1
232
163
104
337
248
173
422
318
229
541
414
307
enabled
VOS2
VOS3
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. The grayed cells correspond to the forbidden configurations.
3. Guaranteed by characterization results, unless otherwise specified.
Table 32. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4,
(1)
ART accelerator ON, SMPS regulator
Arm
Cortex- Cortex-
M7
fCPU1
(MHz)
Arm
Max
Tj=
Symbol Parameter
Conditions
M4
fCPU2
(MHz)
Typ
Unit
Tj=
Tj=
Tj=
Tj=
25 °C 85 °C 105°C 125°C 140°C
VOS1
400
300
200
400
300
200
200
150
100
200
150
100
58.3 79.0 129.0 175.1 236.0
37.0 50.2 84.7 115.6 161.1 218.4
21.5 29.9 56.1 77.1 107.6 152.3
78.1 100.1 148.9 193.4 254.3
51.2 65.5 100.8 130.9 176.9 235.5
29.5 39.4 63.9 86.7 116.3 161.9
-
All
peripherals VOS2
disabled
Supply
VOS3
IDD
current in
mA
VOS1
All
peripherals VOS2
-
Run mode
enabled
VOS3
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and
typical SMPS efficiency factors.
118/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
Table 33. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache ON,
(1)
ART accelerator ON, LDO regulator ON
Arm
Arm
Max(2)
Cortex Cortex-
Symbol Parameter
Conditions
-M7
fCPU1
(MHz)
M4
fCPU2
(MHz)
Typ
Unit
Tj=
Tj=
Tj=
Tj=
Tj=
25 °C 85 °C 105°C 125°C 140°C
480
400
400
300
200
480
240
200
200
150
100
240
173
147
128
88
268
-
385
-
496
-
VOS0
All
peripherals VOS1
175
120
77
288
209
149
459
379
279
205
569
499
374
283
disabled
VOS2
Supply
current in
Run mode
VOS3
VOS0
55
381
405
IDD
mA
242
368
229
334 419(3) 537
All
VOS1
400
200
178
(3)
peripherals
enabled
VOS2
300
200
150
100
123
77
161
102
246
172
316
228
412
306
VOS3
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
3. Guaranteed by tests in production.
Table 34. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache OFF,
(1)
ART accelerator OFF, LDO regulator ON
Arm
Cortex Cortex
-M7 -M4
fCPU1 fCPU2
(MHz) (MHz)
Arm
Max(2)
Symbol Parameter
Conditions
Typ
Unit
Tj=
Tj=
Tj=
Tj=
Tj=
25 °C 85 °C 105°C 125°C 140°C
VOS0
480
400
300
200
480
400
300
200
240
200
150
100
240
200
150
100
109
96
191
149
95
330
256
187
136
403
310
224
159
444
347
257
192
517
401
295
215
All
VOS1
VOS2
VOS3
VOS0
VOS1
VOS2
VOS3
468
354
270
peripherals
disabled
67
Supply
current in
Run mode
43
62
368
392
IDD
mA
178
147
103
64
291
224
136
87
All
523
392
293
peripherals
enabled
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
DS12919 Rev 1
119/252
228
Electrical characteristics
STM32H755xI
Table 35. Typical and maximum current consumption in Run mode, code with data processing
(1)(2)
running from ITCM, only Arm Cortex-M7 running, LDO regulator ON
Max(3)
fCPU1
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85 Tj=105 Tj=125 Tj=140
°C
°C
°C
°C
480
400
400
300
300
148
125
110
84
226
-
307
-
390
-
VOS0
168
-
230
-
296
-
384
-
VOS1
76
114
88
-
170
152
-
224
205
-
297
278
-
VOS2 216
56
All
peripherals
disabled
200
200
180
53
47
71
64
63
55
36
24
222
-
121
116
115
109
92
83
439
-
164
159
158
153
135
126
550
-
223
218
217
212
194
185
295
291
290
284
267
257
43
Supply
168
VOS3
40
IDD
current in
mA
144
35
Run mode
60
25
16
12
480
VOS0
226
190
167
135
122
85
400
400
VOS1
222
-
327
-
416
-
536
-
All
peripherals
enabled
300
300
VOS2
160
-
248
-
320
-
419
-
200
VOS3 200
76
103
174
233
313
413
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. The grayed cells correspond to the forbidden configurations.
3. Guaranteed by characterization results, unless otherwise specified.
120/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
Table 36. Typical and maximum current consumption in Run mode, code with data processing
(1)(2)
running from ITCM, only Arm Cortex-M7 running, SMPS regulator
Max
fCPU1
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25 Tj=85 Tj=105 Tj=125 Tj=140
°C
°C
°C
°C
°C
VOS1
400
300
200
400
300
200
48.6
31.3
18.0
72.9
49.6
28.8
73.3
46.3
26.9
95.8
64.3
38.5
100.4
68.3
45.3
144.5
99.6
64.3
132.4
90.0
176.0
122.2
82.4
All
peripherals VOS2
164.5
111.7
disabled
Supply
current in
VOS3
60.6
IDD
mA
VOS1
All
peripherals VOS2
190.7
131.7
88.3
252.0
179.1
118.6
Run mode
238.2
164.7
enabled
VOS3
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
2. The grayed cells correspond to the forbidden configurations.
Table 37. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache ON,
(1)
LDO regulator ON
Max(2)
fCPU1
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25° Tj=85° Tj=105 Tj=125 Tj=140
C
C
°C
°C
°C
480
400
400
300
300
200
200
480
400
400
300
300
200
200
110
91
222
-
304
-
388
-
VOS0
80
162
-
228
-
294
-
381
-
All
VOS1
peripherals
disabled
61.5
55
111
-
168
-
222
-
294
-
VOS2
VOS3
VOS0
38.5
34.5
220
195
175
135
120
83
Supply
current in
Run mode
69
342
-
120
436
-
163
546
-
222
294
IDD
mA
264
-
336
-
424
-
544
-
All
VOS1
peripherals
enabled
180
-
246
-
318
-
418
-
VOS2
VOS3
75
114
173
232
312
412
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
DS12919 Rev 1
121/252
228
Electrical characteristics
STM32H755xI
Table 38. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache OFF,
(1)
LDO regulator ON
Max(2)
fCPU1
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25° Tj=85° Tj=105 Tj=125 Tj=140
C
C
°C
°C
°C
VOS0
480
400
300
200
480
400
300
200
87
73
157
123
85
259
201
150
109
390
308
228
167
342
267
204
152
504
397
301
226
All
VOS1
VOS2
VOS3
VOS0
VOS1
VOS2
VOS3
355
277
212
peripherals
disabled
52
Supply
current in
Run mode
34
54
284
407
IDD
mA
168
135
100
70
276
224
154
103
All
519
401
307
peripherals
enabled
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
Table 39. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON
Max(1)
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25° Tj=85° Tj=105 Tj=125 Tj=140
C
C
°C
°C
°C
D1
Standby,
D2
Standby,
D3 Run
64
2.7
1.1
4.7
12.9
19.0
27.5
37.8
Supply
current in
VOS3
VOS3
8
-
-
-
-
-
IDD
batch
acquisition
mode
mA
D1 Stop,
D2 Stop,
D3 Run
64
8
5.4
3.8
18.4
-
83.7
-
132.6
-
202.4
-
289.3
-
1. Guaranteed by characterization results, unless otherwise specified.
122/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
Table 40. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,
(1)
LDO regulator ON
Max(2)
fCPU2
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25 Tj=85 Tj=105 Tj=125 Tj=140
°C
°C
°C
°C
°C
240
200
200
150
150
100
240
200
200
150
100
121
90
203
-
339
-
453
-
VOS0
All
79
123
-
234
-
323
-
444
-
peripherals VOS1
disabled
61
VOS2
VOS3
56
85
59
303
-
178
131
412
-
250
189
525
-
350
269
Supply
current in
Run mode
IDD
35
369
398
mA
190
146
129
90
VOS0
All
peripherals VOS1
195
134
100
287
214
158
376
287
216
499
386
297
enabled
VOS2
VOS3
61
1. The grayed cells correspond to the forbidden configurations.
2. Guaranteed by characterization results, unless otherwise specified.
Table 41. Typical and maximum current consumption in Run mode, code with data processing
running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,
(1)(2)
SMPS regulator
Max
Symbol Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85
°C
Tj=105 Tj=125 Tj=140
°C
°C
°C
VOS1
35.3
23.3
13.6
57.0
36.6
23.1
54.3
35.0
22.3
84.1
54.5
37.4
102.1
70.6
49.0
126.8
84.9
58.4
144.4
99.2
203.5
145.8
101.9
234.6
165.0
112.5
All
peripherals
disabled
VOS2
VOS3
VOS1
VOS2
VOS3
207.0
147.1
Supply
current in
69.8
IDD
mA
172.3
118.1
79.8
Run mode
All
peripherals
enabled
223.7
158.7
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
2. The grayed cells correspond to the forbidden configurations.
DS12919 Rev 1
123/252
228
Electrical characteristics
STM32H755xI
(1)(2)
Table 42. Typical and maximum current consumption in Stop, LDO regulator ON
Max(3)
Symbol Parameter
Conditions
Typ
Unit
Tj=105 Tj=125 Tj=140
Tj=25°C Tj=85°C
°C
°C
°C
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
SVOS5
SVOS4
SVOS3
1.27
1.96
2.78
1.27
2.25
3.07
0.91
1.42
2.02
0.91
1.70
2.31
0.49
0.76
1.10
0.15
0.22
0.35
6.3
9.4
42.5
57.4
75.9
42.5
57.9
76.4
30.4
41.1
54.4
30.4
41.5
54.9
16.5
22.2
29.3
4.3
72.0
94.6
Flash
memory
OFF, no
IWDG
13.8(4)
121.3(4) 183.8
264.9
266.5
186.1
187.2
102.2
26.6
D1 Stop,
D2 Stop,
D3 Stop
6.3
72.0
95.2
Flash
memory
ON, no
IWDG
9.8
14.1
4.6
122.0
51.2
67.3
86.6
51.2
67.9
87.1
28.0
36.6
46.9
7.3(4)
9.6
184.8
130.0
130.8
71.2
Flash
memory
OFF, no
IWDG
6.8
D1 Stop,
IDD (Stop) D2 Standby,
D3 Stop
10.0
4.6
mA
Flash
memory
ON, no
IWDG
7.2
10.3
2.4
Flash
memory
OFF, no
IWDG
D1Standby,
D2 Stop,
D3 Stop
3.6
5.3
0.7(4)
Flash
memory
OFF, no
IWDG
D1Standby,
D2Standby,
D3 Stop
1.0
5.8
1.5(4)
7.8
12.3(4)
18.6
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
2. The grayed cells correspond to the forbidden configurations.
3. Guaranteed by characterization results, unless otherwise specified.
4. Guaranteed by tests in production.
124/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
(1)
Table 43. Typical and maximum current consumption in Stop, SMPS regulator
Max
Symbol
Parameter
Conditions
Typ
Unit
Tj=105 Tj=125 Tj=140
Tj=25°C Tj=85°C
°C
°C
°C
SVOS5
0.36
0.63
1.00
0.36
0.73
1.11
0.25
0.46
0.73
0.25
0.55
0.83
0.15
0.26
0.40
0.06
0.08
0.13
1.73
3.05
4.98
1.73
3.18
5.09
1.24
2.21
3.57
1.24
2.34
3.67
0.67
1.17
1.90
0.20
0.33
0.54
11.91
19.57
29.11
11.91
19.74
29.31
8.21
21.53
33.51
47.13
21.53
33.72
47.40
14.00
22.94
32.80
14.00
23.15
32.99
7.85
-
-
Flash
OFF, no SVOS4
-
-
IWDG
D1 Stop,
D2 Stop,
D3 Stop
SVOS3
68.76
100.34
SVOS5
Flash
ON, no SVOS4
-
-
-
-
IWDG
SVOS3
69.14
100.95
SVOS5
Flash
OFF, no SVOS4
-
-
14.01
19.62
8.21
-
-
IWDG
D1 Stop,
SVOS3
49.24
68.77
IDD (Stop) D2 Standby,
D3 Stop
mA
SVOS5
Flash
ON, no SVOS4
-
-
14.15
19.81
4.51
-
-
IWDG
SVOS3
49.55
69.18
SVOS5
Flash
OFF, no SVOS4
-
-
D1 Standby,
D2 Stop,
D3 Stop
7.21
12.32
17.12
2.05
-
-
IWDG
SVOS3
10.57
1.18
26.97
39.20
SVOS5
Flash
ON, no SVOS4
-
-
-
-
D1 Standby,
D2 Standby,
D3 Stop
1.90
3.11
IWDG
SVOS3
2.80
4.47
6.77
9.58
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
DS12919 Rev 1
125/252
228
Electrical characteristics
STM32H755xI
(1)(2)
Table 44. Typical and maximum current consumption in Sleep mode, LDO regulator ON
Max(3)
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25° Tj=85° Tj=105 Tj=125 Tj=140
C
C
°C
°C
°C
480
400
400
300
300
200
200
480
400
400
300
300
200
200
50.7
43.4
35.3
27.9
24.6
18.8
16.5
96.3
87.8
66.5
-
253.4 366.1
245.5 357.9
VOS0
181.3 265.8 379.6
All
VOS1
peripherals
disabled
-
-
-
47.3
-
139.1 207.3 300.4
VOS2
VOS3
VOS0
-
-
-
Supply
current in
Sleep
mode
33.6
106.4 160.9 236.1 330.3
IDD (Sleep)
mA
136.0 194.7 348.5 464.4
115.0 169.0 325.9 441.7
97.7
74.9
67.3
52.8
47.1
138.2 251.3 338.4 456.4
All
VOS1
peripherals
enabled
-
-
-
-
95.8
-
187.6 257.9 354.1
VOS2
VOS3
-
-
-
69.3
141.4 197.7 275.1 372.8
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and
typical SMPS efficiency factors.
2. The grayed cells correspond to the forbidden configurations.
3. Guaranteed by characterization results, unless otherwise specified.
(1)(2)(3)
Table 45. Typical and maximum current consumption in Sleep mode, SMPS regulator
Max
fHCLK
(MHz)
Symbol Parameter
Conditions
Typ
Unit
Tj=25
°C
Tj=85 Tj=105 Tj=125 Tj=140
°C °C °C °C
400 15.93 29.69
300 12.58
300 10.21 19.63
200 7.89
VOS3 200 6.50 12.98
79.01 118.72 173.80
VOS1
-
-
-
-
All
peripherals
disabled
56.46
-
82.14 123.46 177.95
VOS2
Supply
IDD
-
-
-
-
current in
mA
(Sleep)
39.73
59.35
87.10 125.00
Sleep mode
VOS1 400 42.65 59.62 110.88 153.00 211.65
-
All
peripherals VOS2 300 27.70 38.94
75.26 102.22 147.38 208.16
Enabled
VOS3 200 17.95 26.14
52.75
72.95 104.09 148.48
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
126/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
2. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors.
3. The grayed cells correspond to the forbidden configurations.
Table 46. Typical and maximum current consumption in Standby
Typ
Max(1)
Conditions
3 V
Symbol Parameter
Unit
RTC
and
LSE
1.62 V 2.4 V 3 V 3.3 V
Backup
SRAM
Tj=25 Tj=85 Tj=105 Tj=125 Tj=140
°C
°C
°C
°C
°C
OFF
ON
OFF 1,92
OFF 3,33
1,95 2,06 2,16
4
18
47
-
40
83
-
90
140
Supply
3,44 3,6 3,79 8.2
141
230
IDD
current in
Standby
mode
µA
(Standby)
OFF
ON
ON
ON
2,43
3,82
2,57 2,77 2,95
4,05 4,31 4,55
-
-
-
-
-
-
-
-
1. Guaranteed by characterization results, unless otherwise specified.
Table 47. Typical and maximum current consumption in V
mode
BAT
Conditions
Typ
Max(1)
3 V
RTC
and 1.2 V 2 V
LSE
Symbol Parameter
Unit
Backup
SRAM
3.4
V
3 V
Tj=25 Tj=85 Tj=105 Tj=125 Tj=140
°C
°C
°C
°C
°C
OFF
ON
OFF 0,02 0,02 0,03 0,05 0,5
4,1
22
-
10
48
-
24
87
-
47
Supply
IDD
OFF 1,33 1,45 1,58 1,7
4,4
132
current in
µA
(VBAT)
OFF
ON
ON
ON
0,46 0,57 0,75 0,87
1,77 2,3 2,5
-
-
-
-
VBAT mode
2
-
-
-
1. Guaranteed by characterization results, unless otherwise specified.
DS12919 Rev 1
127/252
228
Electrical characteristics
STM32H755xI
Typical SMPS efficiency versus load current and temperature
Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at T = 30 °C
J
100
90
80
70
VDDSMPS =
1.8V, VOS1
60
VDDSMPS =
3.3V, VOS1
VDDSMPS =
1.8V, VOS2
50
VDDSMPS =
3.3V, VOS2
40
VDDSMPS =
1.8V, VOS3
VDDSMPS =
3.3V, VOS3
30
20
10
0
0.001
0.01
0.1
1
MSv62424V1
Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at T = T
J
Jmax
100
90
80
70
VDDSMPS =
1.8V, VOS1
VDDSMPS =
3.3V, VOS1
VDDSMPS =
1.8V, VOS2
VDDSMPS =
3.3V, VOS2
VDDSMPS =
1.8V, VOS3
VDDSMPS =
3.3V, VOS3
60
50
40
30
20
10
0
0.001
0.01
0.1
1
MSv62425V1
128/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
Figure 19. Typical SMPS efficiency (%) vs load current (A) in low-power mode at
T = 30 °C
J
°
100
90
80
70
60
50
40
30
20
10
0
VDDSMPS =
1.8V, SVOS5
VDDSMPS =
3.3V, SVOS5
VDDSMPS =
1.8V, SVOS4
VDDSMPS =
3.3V, SVOS4
VDDSMPS =
1.8V, SVOS3
VDDSMPS =
3.3V, SVOS3
0.00001
0.0001
0.001
0.01
0.1
MSv62426V1
DS12919 Rev 1
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228
Electrical characteristics
STM32H755xI
Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at
T = T
J
Jmax
100
90
80
70
60
50
40
30
20
10
0
VDDSMPS =
1.8V, SVOS5
VDDSMPS =
3.3V, SVOS5
VDDSMPS =
1.8V, SVOS4
VDDSMPS =
3.3V, SVOS4
VDDSMPS =
1.8V, SVOS3
VDDSMPS =
3.3V, SVOS3
0.00001
0.0001
0.001
0.01
0.1
MSv62427V1
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 68: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
130/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 48: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
ISW = VDDx × fSW × CL
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the MCU supply voltage
DDx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
EXT
L
INT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
•
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
The I/O compensation cell is enabled.
f
is the CPU clock. f
= f
/4, and f
= f
/2.
rcc_c_ck
PCLK
rcc_c_ck
HCLK
rcc_c_ck
The given value is calculated by measuring the difference of current consumption
–
–
–
with all peripherals clocked off
with only one peripheral clocked on
f
= 480 MHz (Scale 0), f
= 400 MHz (Scale 1), f
= 300 MHz
rcc_c_ck
rcc_c_ck
rcc_c_ck
(Scale 2), f
= 200 MHz (Scale 3)
rcc_c_ck
•
The ambient operating temperature is 25 °C and V =3.3 V.
DD
DS12919 Rev 1
131/252
228
Electrical characteristics
STM32H755xI
Table 48. Peripheral current consumption in Run mode
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
MDMA
DMA2D
4.6
2.9
3.8
2.4
3.4
2.1
3.2
1.9
JPGDEC
4.1
3.7
3.4
3.1
FLASH
17.0
0.9
15.0
1.1
14.0
0.9
12.0
0.8
FMC registers
FMC kernel
QUADSPI registers
QSPI kernel
SDMMC1 registers
SDMMC1 kernel
DTCM1
7.0
6.1
5.6
5.0
1.5
1.5
1.4
1.3
1.0
0.9
0.8
0.7
AHB3
8.2
7.2
6.7
6.0
1.3
1.2
0.9
0.9
7.9
6.8
6.0
5.3
DTCM2
8.3
7.2
6.4
5.7
ITCM
7.0
6.3
5.6
5.1
D1SRAM1
13.0
35.0
120
54.0
55.0
4.5
11.0
32.0
106
48.0
49.0
4.1
9.9
8.7
AHB3 bridge
Total AHB3
DMA1
29.0
96
26.0
86
µA/MHz
41.0
42.0
3.7
37.0
37.0
3.3
DMA2
ADC12 registers
ADC12 kernel
ART accelerator
ETH1MAC
1.0
0.7
0.4
0.6
4.1
3.7
3.2
2.9
17.0
0.1
15.0
0.1
14.0
0.1
12.0
0.1
ETH1TX
ETH1RX
0.1
0.1
0.1
0.1
AHB1
USB1 OTG registers
USB1 OTG kernel
USB1 ULPI
USB2 OTG registers
USB2 OTG kernel
USB2 ULPI
AHB1 bridge
Total AHB1
23.0
8.2
21.0
0.5
19.0
8.3
17.0
8.2
0.1
0.1
0.1
0.1
21.0
8.5
19.0
0.4
17.0
8.6
15.0
8.3
23.0
0.1
19.0
0.1
20.0
0.1
19.0
0.1
220
181
178
161
132/252
DS12919 Rev 1
STM32H755xI
Bus
Electrical characteristics
Table 48. Peripheral current consumption in Run mode (continued)
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
DCMI
CRYPT
2.1
0.1
0.1
1.7
11.0
47.0
1.7
5.7
5.2
4.1
0.1
79
1.9
0.1
0.1
2.0
0.1
41.0
1.2
4.9
4.5
3.6
0.1
60
1.8
0.1
0.1
1.3
9.7
37.0
1.1
4.4
4.0
3.2
0.1
63
1.6
0.1
0.1
1.2
9.4
34.0
1.0
3.9
3.5
2.8
0.1
58
HASH
RNG registers
RNG kernel
SDMMC2 registers
SDMMC2 kernel
D2SRAM1
D2SRAM2
D2SRAM3
AHB2 bridge
Total AHB2
GPIOA
AHB2
1.5
1.2
0.8
1.1
0.7
0.8
0.9
1.1
0.9
0.8
0.7
0.4
6.6
1.7
0.4
2.3
0.1
22
1.3
1.0
0.7
1.0
0.7
0.8
0.8
1.0
0.9
0.8
0.8
0.5
5.9
1.5
0.3
1.9
0.1
20
1.3
1.0
0.7
1.0
0.7
0.7
0.8
1.0
0.8
0.7
0.7
0.4
5.3
1.2
0.5
1.7
0.1
19
1.1
0.9
0.6
0.9
0.6
0.6
0.7
0.9
0.7
0.7
0.6
0.3
4.8
1.2
0.2
1.5
0.1
16
GPIOB
GPIOC
µA/MHz
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
GPIOI
AHB4
GPIOJ
GPIOK
CRC
BDMA
ADC3 registers
ADC3 kernel
BKPRAM
AHB4 bridge
Total AHB4
WWDG1
0.7
81.0
0.3
87
0.5
36.0
0.2
41
0.5
33.0
0.1
38
0.2
30.0
0.1
34
LCD-TFT
APB3 bridge
Total APB3
APB3
µA/MHz
133/252
DS12919 Rev 1
228
Electrical characteristics
STM32H755xI
Table 48. Peripheral current consumption in Run mode (continued)
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
TIM2
TIM3
7.7
6.7
6.3
7.4
1.4
1.4
3.2
2.3
2.1
0.7
2.4
0.6
2.0
0.8
1.8
0.7
0.5
3.5
1.9
4.3
1.9
4.4
1.7
3.9
1.6
3.8
1.1
2.5
1.0
3.6
3.2
3.1
3.5
0.7
0.7
1.5
1.1
1.1
0.5
2.3
0.5
1.8
0.6
1.6
0.9
0.7
2.8
1.7
3.9
1.7
3.9
1.5
3.4
1.4
3.4
0.8
2.3
0.8
3.3
3.0
2.8
3.2
0.8
0.7
1.5
1.1
1.1
0.8
1.9
0.5
1.7
0.5
1.6
0.7
0.7
2.4
1.4
3.6
1.4
3.5
1.4
3.1
1.4
3.0
0.9
2.0
0.9
3.0
2.7
2.5
2.8
0.6
0.6
1.3
0.9
0.9
0.7
1.7
0.4
1.4
0.6
1.3
0.7
0.6
2.2
1.3
3.2
1.3
3.2
1.4
2.8
1.3
2.7
0.8
1.9
0.8
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
LPTIM1 registers
LPTIM1 kernel
WWDG2
SPI2 registers
SPI2 kernel
SPI3 registers
SPI3 kernel
SPDIFRX1 registers
SPDIFRX1 kernel
USART2 registers
USART2 kernel
USART3 registers
USART3 kernel
UART4 registers
UART4 kernel
UART5 registers
UART5 kernel
I2C1 registers
I2C1 kernel
I2C2 registers
APB1
µA/MHz
134/252
DS12919 Rev 1
STM32H755xI
Bus
Electrical characteristics
Table 48. Peripheral current consumption in Run mode (continued)
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
I2C2 kernel
I2C3 registers
I2C3 kernel
2.3
0.8
2.4
0.7
0.1
3.6
1.8
4.0
2.0
3.9
6.4
2.7
0.1
0.2
3.3
19.0
9.1
0.1
142
11.0
10.0
3.6
0.1
4.5
0.1
2.0
0.9
2.1
0.6
5.5
4.1
4.1
2.0
0.5
1.3
2.2
1.0
1.9
0.5
0.1
1.3
1.8
3.3
1.6
3.4
5.5
2.4
0.1
0.3
2.9
17.0
7.9
0.1
108
5.0
4.7
2.5
0.1
3.0
0.1
1.7
0.8
1.7
0.5
2.5
2.0
1.9
1.8
0.4
1.1
1.9
0.8
1.8
0.6
3.2
1.2
1.6
3.0
1.6
3.1
5.0
2.3
0.1
0.3
2.6
15.0
6.9
0.1
102
4.5
4.3
2.7
0.1
3.1
0.1
1.6
0.7
1.6
0.5
2.3
1.8
1.8
1.6
0.4
1.1
1.7
0.8
1.6
0.5
0.1
1.0
1.4
2.8
1.4
2.8
4.5
1.9
0.1
0.2
2.3
13.0
6.4
0.1
88
HDMI-CEC registers
HDMI-CEC kernel
DAC12
USART7 registers
USART7 kernel
USART8 registers
USART8 kernel
CRS
APB1
(continued)
SWPMI registers
SWPMI kernel
OPAMP
MDIO
FDCAN registers
FDCAN kernel
APB1 bridge
Total APB1
TIM1
µA/MHz
4.0
3.8
2.9
0.1
3.4
0.1
1.4
0.6
1.5
0.3
2.1
1.7
1.6
1.3
0.5
1.0
TIM8
USART1 registers
USART1 kernel
USART6 registers
USART6 kernel
SPI1 registers
SPI1 kernel
APB2
SPI4 registers
SPI4 kernel
TIM15
TIM16
TIM17
SPI5 registers
SPI5 kernel
SAI1 registers
DS12919 Rev 1
135/252
228
Electrical characteristics
STM32H755xI
Table 48. Peripheral current consumption in Run mode (continued)
Bus
Peripheral
VOS0
VOS1
VOS2
VOS3
Unit
SAI1 kernel
SAI2 registers
SAI2 kernel
1.4
1.5
1.1
1.6
1.1
6.5
0.3
84.0
0.2
150
0.9
1.1
2.9
1.8
0.4
0.9
2.2
0.8
2.3
0.7
2.1
0.8
2.2
0.5
2.0
0.6
0.4
1.1
1.7
2.0
0.1
28
1.1
1.3
1.0
1.3
1.2
5.8
0.2
39.0
0.1
81
1.0
1.2
0.9
1.1
1.1
5.2
0.2
35.0
0.1
74
0.8
1.0
0.9
1.0
0.9
4.7
0.4
32.0
0.2
68
SAI3 registers
SAI3 kernel
APB2
(continued)
DFSDM1 registers
DFSDM1 kernel
HRTIM
APB2 bridge
Total APB2
SYSCFG
1.0
1.3
2.2
1.6
0.4
0.7
2.1
0.6
2.1
0.7
1.7
0.4
2.0
0.4
1.8
0.4
0.2
0.9
1.4
2.0
0.1
24.4
0.7
1.0
2.2
1.4
0.5
0.7
1.9
0.7
1.8
0.7
1.6
0.6
1.7
0.6
1.5
0.5
0.2
1.0
1.3
1.8
0.1
22.4
0.8
0.8
2.1
1.3
0.3
0.4
1.8
0.5
1.4
0.4
1.5
0.4
1.5
0.4
1.2
0.2
0.1
0.6
1.0
1.6
0.1
18.9
LPUART1 registers
LPUART1 kernel
SPI6 registers
SPI6 kernel
I2C4 registers
I2C4 kernel
µA/MHz
LPTIM2 registers
LPTIM2 kernel
LPTIM3 registers
LPTIM3 kernel
LPTIM4 registers
LPTIM4 kernel
LPTIM5 registers
LPTIM5 kernel
COMP12
APB4
VREF
RTC
SAI4 registers
SAI4 kernel
APB4 bridge
Total APB4
136/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
6.3.8
Wakeup time from low-power modes
The wakeup times given in Table 49 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
(1)
Table 49. Low-power mode wakeup timings
Typ(2)
Max(2)
Symbol
Parameter
Conditions
Unit
CPU
clock
cycles
(3)
tWUSLEEP
Wakeup from Sleep
-
9
10
VOS3, HSI, Flash memory in normal mode
4.4
12
15
23
39
39
30
36
38
47
68
68
5.6
15
20
28
71
47
37
50
48
61
75
77
VOS3, HSI, Flash memory in low-power
mode
VOS4, HSI, Flash memory in normal mode
VOS4, HSI, Flash memory in low-power
mode
VOS5, HSI, Flash memory in normal mode
VOS5, HSI, Flash memory in low-power
mode
(3)
tWUSTOP
Wakeup from Stop
VOS3, CSI, Flash memory in normal mode
VOS3, CSI, Flash memory in low power
mode
µs
VOS4, CSI, Flash memory in normal mode
VOS4, CSI, Flash memory in low-power
mode
VOS5, CSI, Flash memory in normal mode
VOS5, CSI, Flash memory in low-power
mode
VOS3, HSI, Flash memory in normal mode
VOS3, CSI, Flash memory in normal mode
2.6
26
3.4
36
tWUSTOP_
Wakeup from Stop,
clock kept running
(3)
KERON
Wakeup from Standby
mode
(3)
tWUSTDBY
-
390
500
1. The wakeup timings is valid for both CPUs.
2. Guaranteed by characterization results.
3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
DS12919 Rev 1
137/252
228
Electrical characteristics
STM32H755xI
6.3.9
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 68: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 21.
(1)
Table 50. High-speed external user clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fHSE_ext
User external clock source frequency
4
25
50
MHz
VSW
(VHSEH−VHSEL)
OSC_IN amplitude
0.7VDD
-
VDD
V
VDC
OSC_IN input voltage
VSS
7
-
-
0.3VSS
-
tW(HSE)
OSC_IN high or low time
ns
1. Guaranteed by design.
Figure 21. High-speed external clock source AC timing diagram
V
HSEH
90%
10 %
HSEL
V
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
I
L
OSC _I N
clock source
STM32
ai17528b
138/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 68: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 22.
(1)
Table 51. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
-
-
-
32.768
1000
VDDIOx
kHz
0.7 VDDIOx
VSS
-
-
V
0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
-
250
-
-
ns
1. Guaranteed by design.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
W(LSE)
t
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
I
L
OSC32_IN
clock source
STM32
ai17529b
DS12919 Rev 1
139/252
228
Electrical characteristics
STM32H755xI
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 52. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 52. 4-48 MHz HSE oscillator characteristics
Operating
Symbol
Parameter
Min
Typ
Max
Unit
conditions(2)
F
Oscillator frequency
Feedback resistor
-
4
-
-
200
-
48
-
MHz
RF
-
kꢁ
During startup(3)
-
4
V
DD=3 V, Rm=30 ꢁ
-
-
-
-
-
0.35
0.40
0.45
0.65
0.95
-
-
-
-
-
CL=10pF@4MHz
VDD=3 V, Rm=30 ꢁ
CL=10 pF at 8 MHz
IDD(HSE)
HSE current consumption
mA
VDD=3 V, Rm=30 ꢁ
CL=10 pF at 16 MHz
VDD=3 V, Rm=30 ꢁ
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 ꢁ
CL=10 pF at 48 MHz
Gmcritmax
Maximum critical crystal gm
Start-up time
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 23). C and C are usually
L1
L2
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . The PCB and MCU pin capacitance must be included
L1
L2
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing C and C .
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Figure 23. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
OSC_OUT
(1)
STM32
R
EXT
C
L2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 53. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 53. Low-speed external user clock characteristics
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
-
32.768
-
kHz
LSEDRV[1:0] = 00,
Low drive capability
-
-
-
-
-
-
-
290
390
550
900
-
-
-
LSEDRV[1:0] = 01,
Medium Low drive capability
LSE current
consumption
IDD
nA
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
LSEDRV[1:0] = 00,
Low drive capability
0.5
0.75
1.7
LSEDRV[1:0] = 01,
Medium Low drive capability
-
Maximum critical crystal
gm
Gmcritmax
µA/V
LSEDRV[1:0] = 10,
Medium high drive capability
-
LSEDRV[1:0] = 11,
High drive capability
-
-
-
2.7
-
(3)
tSU
Startup time
VDD is stabilized
2
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
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Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 24. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_IN
LSE
Bias
controlled
gain
32.768 kHz
resonator
R
F
OSC32_OUT
STM32
C
L2
ai17531b
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
6.3.10
Internal clock source characteristics
The parameters given in Table 54 to Table 57 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 22: General
DD
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 54. HSI48 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD=3.3 V,
TJ=30 °C
fHSI48
HSI48 frequency
47.5(1)
-
48
48.5(1) MHz
TRIM(2)
USER trimming step
USER TRIMMING Coverage
Duty Cycle
-
0.175
-
-
%
%
%
USER TRIM
COVERAGE(3)
± 32 steps
±4.79 ±5.60
DuCy(HSI48)(2)
-
45
-
-
55
3.5
4
TJ=-40 to 125 °C
TJ=-40 to 140 °C
VDD=3 to 3.6 V
VDD=1.62 V to 3.6 V
-
–4.5
Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
ACCHSI48_REL(3)(4)
%
%
–4.5
-
-
-
-
-
0.025
0.05
2.1
350
0.05
0.1
4.0
400
HSI48 oscillator frequency drift with
∆
VDD(HSI48)(3)
(5)
VDD
(2)
tsu(HSI48)
HSI48 oscillator start-up time
µs
(2)
IDD(HSI48)
HSI48 oscillator power consumption
-
µA
Next transition jitter
Accumulated jitter on 28 cycles(6)
NT jitter
PT jitter
-
-
-
-
± 0.15
± 0.25
-
-
ns
ns
Paired transition jitter
Accumulated jitter on 56 cycles(6)
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization.
4. ꢀfHSI = ACCHSI48_REL + ꢀVDD
.
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5. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) /
Freq(1.62V).
6. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
(1)
Table 55. HSI oscillator characteristics
Symbol
Parameter
HSI frequency
Conditions
Min
Typ
Max
Unit
fHSI
VDD=3.3 V, TJ=30 °C
63.7(2)
64
64.3(2)
MHz
Trimming is not a multiple
of 32
-
0.24
−1.8
−0.8
0.32
Trimming is 128, 256 and
384
−5.2
−1.4
-
-
Trimming is 64, 192, 320
and 448
TRIM
HSI user trimming step
%
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
−0.6
−0.25
-
DuCy(HSI) Duty Cycle
-
45
-
-
55
%
%
HSI oscillator frequency drift over
ΔVDD (HSI)
VDD=1.62 to 3.6 V
−0.12
0.03
VDD (reference is 3.3 V)
TJ=-20 to 105 °C
−1(3)
-
-
1(3)
1(3)
2
HSI oscillator frequency drift over
temperature (reference is 64 MHz)
ΔTEMP (HSI)
%
TJ=−40 to TJmax °C
−2(3)
tsu(HSI)
HSI oscillator start-up time
-
-
-
-
1.4
4
µs
µs
µA
tstab(HSI) HSI oscillator stabilization time
DD(HSI) HSI oscillator power consumption
at 1% of target frequency
-
8
I
300
400
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
4 MHz low-power internal RC oscillator (CSI)
Table 56. CSI oscillator characteristics
(1)
Symbol
Parameter
CSI frequency
Conditions
Min
Typ
Max
Unit
fCSI
TRIM
VDD=3.3 V, TJ=30 °C
3.96(2)
4
0.35
-
4.04(2) MHz
Trimming step
Duty Cycle
-
-
45
-
-
%
%
DuCy(CSI)
-
55
TJ = 0 to 85 °C
TJ = −40 to 140 °C
−3.7(3) 4.5(3)
CSI oscillator frequency drift over
temperature
ꢀTEMP (CSI)
%
%
-
−11(3)
7.5(3)
CSI oscillator frequency drift over
VDD
DVDD (CSI)
VDD = 1.62 to 3.6 V
-
−0.06
0.06
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(1)
Table 56. CSI oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tsu(CSI)
CSI oscillator startup time
-
-
1
2
µs
CSI oscillator stabilization time
tstab(CSI)
IDD(CSI)
-
-
-
-
-
4
cycle
µA
(to reach ±3% of fCSI
)
CSI oscillator power consumption
23
30
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Low-speed internal (LSI) RC oscillator
Table 57. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V, TJ = 25 °C
31.4(1)
32
32.6(1)
TJ = –40 to 110 °C, VDD = 1.62 to
3.6 V
29.76(2)
29.4
29.4
-
-
-
33.6(2)
33.6
33.6
130
fLSI
LSI frequency
kHz
TJ = –40 to 125 °C, VDD = 1.62 to
3.6 V
TJ = –40 to 140 °C, VDD = 1.62 to
3.6 V
-
LSI oscillator
startup time
(3)
tsu(LSI)
-
80
LSI oscillator
stabilization
time (5% of
final value)
µs
(3)
tstab(LSI)
-
-
-
120
130
170
280
LSI oscillator
power
(3)
IDD(LSI)
-
nA
consumption
1. Guaranteed by test in production.
2. Guaranteed by characterization results.
3. Guaranteed by design.
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6.3.11
PLL characteristics
The parameters given in Table 58 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 22: General operating conditions.
DD
(1)
Table 58. PLL characteristics (wide VCO frequency range)
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
2
10
1.5
1.5
1.5
1.5
192
-
-
16
MHz
%
PLL input clock duty cycle
-
-
90
VOS0
VOS1
VOS2
VOS3
-
-
480(2)
400(2)
300(2)
200(2)
960
-
fPLL_P_OUT PLL multiplier output clock P
-
MHz
µs
-
fVCO_OUT
PLL VCO output
PLL lock time
-
Normal mode
50(3)
150(3)
tLOCK
Sigma-delta mode
(CKIN ≥ 8 MHz)
-
-
-
-
-
-
58(3)
134
134
76
166(3)
VCO =
192 MHz
-
-
-
-
-
VCO =
200 MHz
Cycle-to-cycle jitter(4)
-
±ps
VCO =
400 MHz
VCO =
800 MHz
39
VCO =
800 MHz
Normal mode
±0.7
Jitter
Long term jitter
%
Sigma-delta
mode (CKIN =
16 MHz)
VCO =
800 MHz
-
±0.8
-
VDDA
VCORE
VDDA
-
-
-
-
590
720
180
280
1500
VCO freq =
836 MHz
-
600
-
(3)
IDD(PLL)
PLL power consumption on VDD
µA
VCO freq =
192 MHz
VCORE
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation (480 MHz for VOS0, 400 MHz for VOS1,
300 MHz for VOS2, 200 MHz for VOS3).
3. Guaranteed by characterization results.
4. Integer mode only.
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Max Unit
(1)
Table 59. PLL characteristics (medium VCO frequency range)
Symbol
Parameter
PLL input clock
Conditions
Min
Typ
-
1
-
-
-
-
-
-
2
MHz
%
fPLL_IN
PLL input clock duty cycle
-
VOS1
10
90
1.17
1.17
1.17
150
-
210
210
200
420
PLL multiplier output clock P, Q,
R
fPLL_OUT
VOS2
MHz
µs
VOS3
fVCO_OUT
tLOCK
PLL VCO output
PLL lock time
-
Normal mode
Sigma-delta mode
60(2) 100(2)
forbidden
145
VCO =
150 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCO =
300 MHz
91
64
Cycle-to-cycle jitter(3)
-
±ps
VCO =
400 MHz
VCO =
420 MHz
Jitter
63
VCO =
55
150 MHz
fPLL_OUT
50 MHz
=
Period jitter
±-ps
%
VCO =
30
400 MHz
VCO =
400 MHz
Long term jitter
Normal mode
±0.3
VDD
VCORE
VDD
-
-
-
-
440
530
180
200
1150
VCO freq =
420MHz
-
500
-
I(PLL)(2)
PLL power consumption on VDD
µA
VCO freq =
150MHz
VCORE
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
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6.3.12
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 125 °C unless otherwise specified.
J
The devices are shipped to customers with the Flash memory erased.
Table 60. Flash memory characteristics
Symbol
Parameter
Conditions
Write / Erase 8-bit mode
Min
Typ
Max
Unit
-
-
-
-
6.5
11.5
20
-
-
-
-
Write / Erase 16-bit mode
Write / Erase 32-bit mode
Write / Erase 64-bit mode
IDD
Supply current
mA
35
Table 61. Flash memory programming (single bank configuration nDBANK=1)
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 8
Program/erase parallelism x 16
Program/erase parallelism x 32
Program/erase parallelism x 64
Program parallelism x 8
-
-
-
-
-
-
-
-
-
-
-
290
180
130
100
2
580(2)
360
µs
260
Word (266 bits) programming
time
tprog
200
4
tERASE128KB Sector (128 KB) erase time
1.8
3.6
13
8
26
16
12
10
s
tME
Mass erase time
6
5
Program parallelism x 16
1.62
1.8
-
-
3.6
3.6
Vprog
Programming voltage
V
Program parallelism x 32
Program parallelism x 64
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
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Table 62. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions
Unit
Min(1)
NEND
tRET
Endurance
Data retention
TJ = –40 to +125 °C (6 suffix versions)
1 kcycle at TA = 85 °C
kcycles
Years
10
30
20
10 kcycles at TA = 55 °C
1. Guaranteed by characterization results.
6.3.13
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 63. They are based on the EMS levels and classes
defined in application note AN1709.
Table 63. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
Voltage limits to be applied on any I/O pin to induce
a functional disturbance
VFESD
3B
5A
V
DD = 3.3 V, TA = +25 °C,
UFBGA240, frcc_c_ck
400 MHz, conforms to
IEC 61000-4-2
=
Fast transient voltage burst limits to be applied
through 100 pF on VDD and VSS pins to induce a
functional disturbance
VFTB
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
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Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 64. EMI characteristics
Max vs.
Monitored
frequency band
[fHSE/fCPU
]
Symbol Parameter
Conditions
Unit
8/400 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
11
6
dBµV
-
VDD = 3.6 V, TA = 25 °C, UFBGA240 package,
conforming to IEC61967-2
SEMI
Peak level
12
7
2.5
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STM32H755xI
6.3.14
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 65. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Packages
Class
Unit
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
001
All
1C
1000
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-
002
All
C1
250
1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 66. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latchup class
TA = +25 °C conforming to JESD78
II level A
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6.3.15
I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
DD
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 67. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
PJ12, PB4
5
0
0
5
0
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11
NA
0
IINJ
mA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PH4, PH5, BOOT0
All other I/Os
NA
1. Guaranteed by characterization.
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6.3.16
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 68: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 22: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Table 68. I/O static characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I/O input low level voltage except
BOOT0
(1)
-
-
0.3VDD
I/O input low level voltage except
BOOT0
0.4VDD−0.
VIL
1.62 V<VDDIOx<3.6 V
-
-
-
V
1(2)
0.19VDD
+
BOOT0 I/O input low level voltage
-
0.1(2)
I/O input high level voltage except
BOOT0
(1)
0.7VDD
-
-
-
-
-
I/O input high level voltage except
BOOT0(3)
0.47VDD+0.
25(2)
VIH
1.62 V<VDDIOx<3.6 V
-
-
V
BOOT0 I/O input high level
voltage(3)
0.17VDD+0.
6(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis
-
250
(2)
VHYS
1.62 V< VDDIOx <3.6 V
mV
BOOT0 I/O input hysteresis
-
-
200
-
-
(9)
0< VIN ≤ Max(VDDXXX
)
+/-250
FT_xx Input leakage current(2)
Max(VDDXXX) < VIN ≤ 5.5 V
-
-
-
-
-
-
1500
(5)(6)(9)
(9)
0< VIN ≤ Max(VDDXXX
)
+/- 350
5000(7)
(4)
FT_u IO
Ileak
Max(VDDXXX) < VIN ≤ 5.5 V
nA
(5)(6)(9)
(9)
TT_xx Input leakage current
0< VIN ≤ Max(VDDXXX
0< VIN ≤ VDDIOX
)
-
-
-
-
+/-250
15
VPP (BOOT0 alternate function)
VDDIOX < VIN ≤ 9 V
35
Weak pull-up equivalent
resistor(8)
RPU
VIN=VSS
30
40
50
kꢁ
Weak pull-down equivalent
resistor(8)
(9)
RPD
CIO
VIN=VDD
-
30
-
40
5
50
-
I/O pin capacitance
pF
1. Compliant with CMOS requirements.
2. Guaranteed by design.
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max)
.
5. All FT_xx IO except FT_lu, FT_u and PC3.
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6. VIN must be less than Max(VDDXXX) + 3.6 V.
7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 25.
Figure 25. V /V for all I/Os except BOOT0
IL IH
3
2.5
2
TLL requirement: VIHmin = 2 V
1.5
1
TLL requirement: VILmin = 0.8 V
0.5
0
2.8
1.6
1.8
2
2.2
2.4
2.6
3
3.2
3.4
3.6
MSv46121V3
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 20).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 20).
VSS
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STM32H755xI
Output voltage levels
Unless otherwise specified, the parameters given in Table 69: Output voltage characteristics
for all I/Os except PC13, PC14, PC15 and PI8 and Table 70: Output voltage characteristics
for PC13, PC14, PC15 and PI8 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 22: General operating
DD
conditions. All I/Os are CMOS and TTL compliant.
(1)
Table 69. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO=8 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO=-8 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=8 mA
(3)
VOL
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=-8 mA
(3)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
V
IIO=20 mA
(3)
VOL
Output low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
1.3
-
2.7 V≤ VDD ≤3.6 V
IIO=-20 mA
(3)
VOH
VDD−1.3
2.7 V≤ VDD ≤3.6 V
IIO=4 mA
(3)
VOL
-
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO=-4 mA
1.62 V≤VDD<3.6 V
(3)
VOH
VDD−-0.4
IIO= 20 mA
-
-
0.4
0.4
2.3 V≤ VDD≤3.6 V
Output low level voltage for an FTf
I/O pin in FM+ mode
(3)
VOLFM+
IIO= 10 mA
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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(1)
Table 70. Output voltage characteristics for PC13, PC14, PC15 and PI8
Symbol
Parameter
Conditions(3)
Min
Max
Unit
CMOS port(2)
IIO=3 mA
VOL
Output low level voltage
-
0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
IIO=-3 mA
VOH
Output high level voltage
Output low level voltage
Output high level voltage
V
DD−0.4
-
0.4
-
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=3 mA
(3)
VOL
-
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
IIO=-3 mA
(2)
VOH
2.4
-
2.7 V≤ VDD ≤3.6 V
IIO=1.5 mA
(2)
VOL
Output low level voltage
Output high level voltage
0.4
-
1.62 V≤ VDD ≤3.6 V
IIO=-1.5 mA
(2)
VOH
VDD−0.4
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
(1)(2)
Table 71. Output timing characteristics (HSLV OFF)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 2.7 V≤ VDD≤3.6 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 2.7 V≤VDD≤3.6 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 2.7 V≤VDD≤3.6 V
C=10 pF, 1.62 V≤VDD≤2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
3
12
(3)
Fmax
Maximum frequency
MHz
3
16
4
00
16.6
33.3
13.3
25
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
10
20
60
15
80
(3)
Fmax
Maximum frequency
15
110
20
01
5.2
10
Output high to low level
fall time and output low
to high level rise time
4.2
7.5
2.8
5.2
tr/tf(4)
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(continued)
(1)(2)
Table 71. Output timing characteristics (HSLV OFF)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 Vv
C=50 pF, 2.7 V≤VDD≤3.6 Vv
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 Vv
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
C=50 pF, 2.7 V≤VDD≤3.6 V(5)
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
C=30 pF, 2.7 V≤VDD≤3.6 V(5)
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
85
35
110
40
(3)
Fmax
Maximum frequency
MHz
166
100
3.8
6.9
2.8
5.2
1.8
3.3
100
50
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
ns
MHz
ns
133
66
(3)
Fmax
Maximum frequency
220
85
11
3.3
6.6
2.4
4.5
1.5
2.7
Output high to low level
fall time and output low
to high level rise time
tr/tf(4)
1. Guaranteed by design.
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
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Output buffer timing characteristics (HSLV option enabled)
(1)
Table 72. Output timing characteristics (HSLV ON)
Speed Symbol
Parameter
conditions
Min
Max
Unit
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V
C=30 pF, 1.62 V≤VDD≤2.7 V
C=10 pF, 1.62 V≤VDD≤2.7 V
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
10
10
11
(2)
Fmax
Maximum frequency
MHz
00
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
9
ns
MHz
ns
6.6
50
58
66
6.6
4.8
3
(2)
Fmax
Maximum frequency
01
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
55
80
133
5.8
4
(2)
Fmax
Maximum frequency
MHz
ns
10
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
2.4
60
90
175
5.3
3.6
1.9
(2)
Fmax
Maximum frequency
MHz
ns
11
Output high to low level
fall time and output low
to high level rise time
tr/tf(3)
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 68: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 73 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 22: General operating conditions.
Table 73. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Weak pull-up equivalent
resistor(1)
(2)
RPU
VIN = VSS
30
40
50
㏀
(2)
VF(NRST)
NRST Input filtered pulse
1.71 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
-
-
50
-
300
ns
(2)
VNF(NRST)
NRST Input not filtered pulse
1.62 V < VDD < 3.6 V 1000
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 26. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 68. Otherwise the reset is not taken into account by the device.
6.3.18
FMC characteristics
Unless otherwise specified, the parameters given in Table 74 to Table 87 for the FMC
interface are derived from tests performed under the ambient temperature, f
frequency
HCLK
and V supply voltage conditions summarized in Table 22: General operating conditions,
DD
with the following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1.
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STM32H755xI
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics.
Asynchronous waveforms and timings
Figure 27 through Figure 29 represent asynchronous waveforms and Table 74 through
Table 81 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
Capacitive load C = 30 pF
L
In all timing tables, the T
is the f
clock period.
KERCK
mc_ker_ck
Figure 27. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FMC_NOE
FMC_NWE
tv(A_NE)
t
h(A_NOE)
FMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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(1)
Table 74. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
3Tfmc_ker_ck–1
0
3Tfmc_ker_ck+1
0.5
2Tfmc_ker_ck –1
2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high
hold time
th(NE_NOE)
tv(A_NE)
0
-
-
0.5
-
FMC_NEx low to FMC_A valid
Address hold time after
FMC_NOE high
th(A_NOE)
0
Data to FMC_NEx high setup
time
ns
tsu(Data_NE)
11
11
0
-
-
-
-
Data to FMC_NOEx high setup
time
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
Data hold time after FMC_NOE
high
Data hold time after FMC_NEx
high
0
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV) FMC_NADV low time
-
-
0
Tfmc_ker_ck+1
1. Guaranteed by characterization results.
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tw(NOE)
tw(NWAIT)
FMC_NE low time
FMC_NOE low time
FMC_NWAIT low time
7Tfmc_ker_ck+1
5Tfmc_ker_ck–1
Tfmc_ker_ck– 0.5
7Tfmc_ker_ck+1
5Tfmc_ker_ck +1
-
ns
FMC_NWAIT valid before FMC_NEx
high
tsu(NWAIT_NE)
th(NE_NWAIT)
4Tfmc_ker_ck +11
3Tfmc_ker_ck+11.5
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FMC_NEx
FMC_NOE
FMC_NWE
t
t
w(NWE)
t
h(NE_NWE)
v(NWE_NE)
t
th(A_NWE)
v(A_NE)
FMC_A[25:0]
Address
t
t
v(BL_NE)
h(BL_NWE)
FMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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(1)
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
3Tfmc_ker_ck –1
Tfmc_ker_ck
3Tfmc_ker_ck
Tfmc_ker_ck+1
Tfmc_ker_ck+0.5
Tfmc_ker_ck –0.5
FMC_NWE high to FMC_NE high
hold time
th(NE_NWE)
tv(A_NE)
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Tfmc_ker_ck
-
2
FMC_NEx low to FMC_A valid
-
Address hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
-
-
ns
FMC_NEx low to FMC_BL valid
0.5
-
FMC_BL hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
Data to FMC_NEx low to Data valid
-
Tfmc_ker_ck+ 2.5
th(Data_NWE) Data hold time after FMC_NWE high
Tfmc_ker_ck+0.5
-
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
-
0
Tfmc_ker_ck+ 1
1. Guaranteed by characterization results.
Table 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
(1)(2)
timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
8Tfmc_ker_ck+1
tw(NWE)
FMC_NWE low time
6Tfmc_ker_ck –1.5
6Tfmc_ker_ck+0.5
FMC_NWAIT valid before FMC_NEx
high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
5Tfmc_ker_ck+13
4Tfmc_ker_ck+13
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Figure 29. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FMC_ NE
FMC_NOE
t
t
h(NE_NOE)
v(NOE_NE)
t
w(NOE)
t
FMC_NWE
t
h(A_NOE)
v(A_NE)
FMC_ A[25:16]
Address
NBL
t
t
v(BL_NE)
h(BL_NOE)
FMC_ NBL[1:0]
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
Address
su(Data_NOE)
Data
FMC_ AD[15:0]
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
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(1)
Table 78. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
4Tfmc_ker_ck –1
4Tfmc_ker_ck +1
2Tfmc_ker_ck
+0.5
tv(NOE_NE)
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2Tfmc_ker_ck
Tfmc_ker_ck –1
0
ttw(NOE)
Tfmc_ker_ck +1
-
FMC_NOE high to FMC_NE high hold
time
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
0.5
0.5
0
ns
Tfmc_ker_ck –0.5
Tfmc_ker_ck +1
FMC_AD(address) valid hold time
after FMC_NADV high)
th(AD_NADV)
th(A_NOE)
Tfmc_ker_ck +0.5
Tfmc_ker_ck –0.5
-
-
Address hold time after FMC_NOE
high
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NE)
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
11
11
0
-
-
-
th(Data_NOE)
0
-
1. Guaranteed by characterization results.
(1)(2)
Table 79. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
8Tfmc_ker_ck
tw(NOE)
FMC_NWE low time
5Tfmc_ker_ck –1.5
5Tfmc_ker_ck +0.5
FMC_NWAIT valid before
FMC_NEx high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
4Tfmc_ker_ck +11
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
3Tfmc_ker_ck +11.5
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Table 80. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
4Tfmc_ker_ck –1
Tfmc_ker_ck –1
4Tfmc_ker_ck
Tfmc_ker_ck +0.5
2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5
FMC_NWE high to FMC_NE high hold
time
th(NE_NWE)
Tfmc_ker_ck –0.5
-
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
-
0
0.5
0
Tfmc_ker_ck
Tfmc_ker_ck + 1
ns
FMC_AD(adress) valid hold time after
FMC_NADV high)
th(AD_NADV)
th(A_NWE)
Tfmc_ker_ck +0.5
-
-
-
Address hold time after FMC_NWE
high
Tfmc_ker_ck +0.5
FMC_BL hold time after FMC_NWE
high
th(BL_NWE)
Tfmc_ker_ck – 0.5
tv(BL_NE)
FMC_NEx low to FMC_BL valid
FMC_NADV high to Data valid
-
-
0.5
tv(Data_NADV)
th(Data_NWE)
Tfmc_ker_ck +2
-
Data hold time after FMC_NWE high
Tfmc_ker_ck +0.5
1. Guaranteed by characterization results.
(1)(2)
Table 81. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
9Tfmc_ker_ck –1
9Tfmc_ker_ck
tw(NWE)
FMC_NWE low time
7Tfmc_ker_ck –0.5
7Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_NEx
high
ns
tsu(NWAIT_NE)
th(NE_NWAIT)
5Tfmc_ker_ck +11
-
-
FMC_NEx hold time after
FMC_NWAIT invalid
4Tfmc_ker_ck +11.5
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Synchronous waveforms and timings
Figure 30 through Figure 33 represent synchronous waveforms and Table 82 through
Table 85 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable
MemoryType = FMC_MemoryType_CRAM
WriteBurst = FMC_WriteBurst_Enable
CLKDivision = 1
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
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Electrical characteristics
In all the timing tables, the Tfmc_ker_ck is the f
clock period, with the following
mc_ker_ck
FMC_CLK maximum values:
•
•
•
For 2.7 V<V <3.6 V, FMC_CLK = 125 MHz at 20 pF
DD
For 1.8 V<V <1.9 V, FMC_CLK = 100 MHz at 20 pF
DD
For 1.62 V<V <1.8 V, FMC_CLK = 100 MHz at 15 pF
DD
Figure 30. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
td(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
td(CLKH-AIV)
d(CLKL-AV)
FMC_A[25:16]
t
td(CLKH-NOEH)
d(CLKL-NOEL)
FMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
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(1)
Table 82. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
1
td(CLKL-NExL)
td(CLKH_NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
-
Tfmc_ker_ck+0.5
-
-
0
-
1
FMC_CLK low to FMC_NADV high
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2.5
FMC_CLK high to FMC_Ax invalid
(x=16…25)
td(CLKH-AIV)
Tfmc_ker_ck
-
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
1.5
ns
Tfmc_ker_ck –0.5
-
3
-
-
0
FMC_A/D[15:0] valid data before FMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
2
1
-
-
FMC_A/D[15:0] valid data after FMC_CLK
high
tsu(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Electrical characteristics
Figure 31. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FMC_NADV
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
FMC_A[25:16]
t
d(CLKH-NWEH)
d(CLKL-NWEL)
FMC_NWE
t
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
d(CLKL-Data)
d(CLKL-ADV)
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKH-NBLH)
FMC_NBL
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Electrical characteristics
Symbol
STM32H755xI
(1)
Table 83. Synchronous multiplexed PSRAM write timings
Parameter
Min
Max
Unit
2Tfmc_ker_ck –1
1
tw(CLK)
FMC_CLK period, VDD = 2.7 to 3.6 V
-
1
-
td(CLKL-NExL)
td(CLKH-NExH)
FMC_CLK low to FMC_NEx low (x =0..2)
-
FMC_CLK high to FMC_NEx high
(x = 0…2)
T
fmc_ker_ck +0.5
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
1.5
-
0
FMC_CLK low to FMC_Ax valid
(x =16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2
-
FMC_CLK high to FMC_Ax invalid
(x =16…25)
Tfmc_ker_ck
Ns
td(CLKL-NWEL)
t(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
FMC_CLK low to to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
1.5
-
Tfmc_ker_ck +0.5
-
2.5
-
0
FMC_A/D[15:0] valid data after FMC_CLK
low
td(CLKL-DATA)
-
2.5
td(CLKL-NBLL)
td(CLKH-NBLH)
tsu(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
-
2
-
Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Electrical characteristics
Figure 32. Synchronous non-multiplexed NOR/PSRAM read timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKH-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FMC_NEx
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
FMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
t
t
h(CLKH-DV)
su(DV-CLKH)
FMC_D[15:0]
FMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
(WAITCFG = 1b,
WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
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(1)
Table 84. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
-
t(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
1
FMC_CLK high to FMC_NEx high
(x= 0…2)
td(CLKH-NExH)
2Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
0.5
-
0
FMC_CLK low to FMC_Ax valid
(x=16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2
-
FMC_CLK high to FMC_Ax invalid
(x=16…25)
2Tfmc_ker_ck
ns
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
-
1.5
-
2Tfmc_ker_ck-0.5
FMC_D[15:0] valid data before FMC_CLK
high
tsu(DV-CLKH)
th(CLKH-DV)
2
1
-
-
FMC_D[15:0] valid data after FMC_CLK
high
t(NWAIT-CLKH)
th(CLKH-NWAIT)
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Electrical characteristics
Figure 33. Synchronous non-multiplexed PSRAM write timings
t
t
w(CLK)
w(CLK)
FMC_CLK
t
t
d(CLKL-NExL)
FMC_NEx
d(CLKH-NExH)
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FMC_NADV
FMC_A[25:0]
FMC_NWE
t
d(CLKH-AIV)
t
t
d(CLKL-AV)
td(CLKH-NWEH)
d(CLKL-NWEL)
t
t
d(CLKL-Data)
d(CLKL-Data)
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FMC_NBL
t
t
d(CLKH-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
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(1)
Table 85. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
t(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
2
FMC_CLK high to FMC_NEx high
(x= 0…2)
t(CLKH-NExH)
Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
-
0.5
-
0
FMC_CLK low to FMC_Ax valid
(x=16…25)
td(CLKL-AV)
td(CLKH-AIV)
-
2.
-
FMC_CLK high to FMC_Ax invalid
(x=16…25)
Tfmc_ker_ck
ns
td(CLKL-NWEL)
td(CLKH-NWEH)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
-
1.5
-
Tfmc_ker_ck+1
FMC_D[15:0] valid data after FMC_CLK
low
td(CLKL-Data)
-
3.5
td(CLKL-NBLL)
td(CLKH-NBLH)
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
-
2
-
Tfmc_ker_ck+1
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
2
2
-
-
1. Guaranteed by characterization results.
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Electrical characteristics
NAND controller waveforms and timings
Figure 34 through Figure 37 represent synchronous waveforms, and Table 86 and Table 87
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x01
COM.FMC_WaitSetupTime = 0x03
COM.FMC_HoldSetupTime = 0x02
COM.FMC_HiZSetupTime = 0x01
ATT.FMC_SetupTime = 0x01
ATT.FMC_WaitSetupTime = 0x03
ATT.FMC_HoldSetupTime = 0x02
ATT.FMC_HiZSetupTime = 0x01
Bank = FMC_Bank_NAND
MemoryDataWidth = FMC_MemoryDataWidth_16b
ECC = FMC_ECC_Enable
ECCPageSize = FMC_ECCPageSize_512Bytes
TCLRSetupTime = 0
TARSetupTime = 0
Capacitive load C = 30 pF
L
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 34. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
t
th(NOE-ALE)
d(ALE-NOE)
FMC_NOE (NRE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
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Figure 35. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NWE-ALE)
d(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
t
t
h(NWE-D)
v(NWE-D)
MS32768V1
Figure 36. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
h(NOE-ALE)
d(ALE-NOE)
FMC_NWE
FMC_NOE
t
w(NOE)
t
t
h(NOE-D)
su(D-NOE)
FMC_D[15:0]
MS32769V1
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Electrical characteristics
Figure 37. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
t
t
t
h(NOE-ALE)
d(ALE-NOE)
w(NWE)
FMC_NWE
FMC_N OE
t
d(D-NWE)
t
t
v(NWE-D)
h(NWE-D)
FMC_D[15:0]
MS32770V1
(1)
Table 86. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
Min
Max
4Tfmc_ker_ck+0.5
Unit
tw(N0E)
FMC_NOE low width
4Tfmc_ker_ck – 0.5
FMC_D[15-0] valid data before
FMC_NOE high
tsu(D-NOE)
th(NOE-D)
8
0
-
FMC_D[15-0] valid data after
FMC_NOE high
ns
-
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid
-
3Tfmc_ker_ck +1
-
4Tfmc_ker_ck –2
1. Guaranteed by characterization results.
(1)
Table 87. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
Min
Max
Unit
tw(NWE)
FMC_NWE low width
4Tfmc_ker_ck – 0.5
4Tfmc_ker_ck +0.5
FMC_NWE low to FMC_D[15-0]
valid
tv(NWE-D)
th(NWE-D)
0
-
FMC_NWE high to FMC_D[15-0]
invalid
2Tfmc_ker_ck – 0.5
5Tfmc_ker_ck – 1
-
-
ns
FMC_D[15-0] valid before
FMC_NWE high
td(D-NWE)
-
FMC_ALE valid before FMC_NWE
low
td(ALE-NWE)
th(NWE-ALE)
3Tfmc_ker_ck +0.5
-
FMC_NWE high to FMC_ALE
invalid
2Tfmc_ker_ck – 1
1. Guaranteed by characterization results.
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Electrical characteristics
STM32H755xI
SDRAM waveforms and timings
In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
•
•
•
For 2.7 V<V <3.6 V: FMC_CLK =110 MHz at 20 pF
DD
For 1.8 V<V <1.9 V: FMC_CLK =100 MHz at 20 pF
DD
For 1.62 V< <1.8 V, FMC_CLK =100 MHz at 15 pF
DD
Figure 38. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
th(SDCLKL_NCAS)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
td(SDCLKL_NCAS)
FMC_SDNWE
FMC_D[31:0]
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Data1 Data2 Datai
Datan
MS32751V2
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Electrical characteristics
(1)
Table 88. SDRAM read timings
Symbol
Parameter
Min
Max
Unit
2Tfmc_ker_ck
+0.5
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck – 1
tsu(SDCLKH _Data)
th(SDCLKH_Data)
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2
1
-
-
td(SDCLKL_Add)
-
1.5
1.5
-
td(SDCLKL- SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0.5
-
1
0.5
-
-
0.5
-
0
1. Guaranteed by characterization results.
(1)
Table 89. LPSDR SDRAM read timings
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
tsu(SDCLKH_Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
2
1.5
-
-
-
2.5
2.5
-
td(SDCLKL_SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0
-
0.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
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Electrical characteristics
STM32H755xI
Figure 39. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
Row n
Col1
Col2
Coli
Coln
FMC_A[12:0]
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
th(SDCLKL_NCAS)
th(SDCLKL_NWE)
td(SDCLKL_NCAS)
td(SDCLKL_NWE)
td(SDCLKL_Data)
Data1
Data2
Datai
Datan
FMC_D[31:0]
td(SDCLKL_NBL)
FMC_NBL[3:0]
th(SDCLKL_Data)
MS32752V2
(1)
Table 90. SDRAM Write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
td(SDCLKL _Data
th(SDCLKL _Data)
td(SDCLKL_Add)
)
-
0
1
-
-
1.5
1.5
-
td(SDCLKL_SDNWE)
th(SDCLKL_SDNWE)
td(SDCLKL_ SDNE)
th(SDCLKL-_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
td(SDCLKL_SDNCAS)
-
0.5
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
1.5
-
0.5
-
1
0.5
-
-
1
0.5
-
1. Guaranteed by characterization results.
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DS12919 Rev 1
STM32H755xI
Electrical characteristics
(1)
Table 91. LPSDR SDRAM Write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
td(SDCLKL _Data
)
-
0
-
2.5
-
th(SDCLKL _Data)
td(SDCLKL_Add)
2.5
2.5
-
td(SDCLKL-SDNWE)
th(SDCLKL-SDNWE)
td(SDCLKL- SDNE)
th(SDCLKL- SDNE)
td(SDCLKL-SDNRAS)
th(SDCLKL-SDNRAS)
td(SDCLKL-SDNCAS)
td(SDCLKL-SDNCAS)
-
0
-
ns
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
3
0
-
-
1.5
-
0
-
1.5
-
0
1. Guaranteed by characterization results.
6.3.19
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 92 and Table 93 for QUADSPI
are derived from tests performed under the ambient temperature, f frequency and V
AHB
DD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics.
The following table summarizes the parameters measured in SDR mode.
(1)
Table 92. QUADSPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7<VDD<3.6 V
CL = 20 pF
-
-
133
QUADSPI clock
frequency
Fck11/TCK
MHz
1.62<VDD<3.6 V
CL = 15 pF
-
-
100
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Electrical characteristics
STM32H755xI
(1)
Table 92. QUADSPI characteristics in SDR mode (continued)
Symbol
tw(CKH)
tw(CKL)
tw(CKH)
Parameter
Conditions
Min
TCK/2–0.5
Typ
Max
Unit
QUADSPI clock high
and low time Even
division
-
-
-
TCK/2
PRESCALER[7:0] =
n = 0,1,3,5...
TCK/2
TCK/2+0.5
(n/2)*TCK/(n+1)-0.5
(n/2)*TCK/ (n+1)
QUADSPI clock high
and low time Odd
division
PRESCALER[7:0] =
n = 2,4,6,8...
(n/2+1)*TCK
(n+1)+0.5
/
tw(CKL)
(n/2+1)*TCK/(n+1)
-
ns
ts(IN)
th(IN)
tv(OUT)
th(OUT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
1
3.5
-
-
-
-
-
-
-
-
1
-
2
-
0
1. Guaranteed by characterization results.
The following table summarizes the parameters measured in DDR mode.
(1)
Table 93. QUADSPI characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7<VDD<3.6 V
CL = 20 pF
-
-
100
Fck11/TCK
QUADSPI clock frequency
MHz
1.62<VDD<3.6 V
CL = 15 pF
-
-
100
tw(CKH)
tw(CKL)
TCK/2–0.5
TCK/2
-
-
TCK/2
QUADSPI clock high and PRESCALER[7:0] =
low time Even division n = 0,1,3,5...
TCK/2+0.5
(n/2)*TCK
(n+1)-0.5
/
(n/2)*TCK
(n+1)
/
tw(CKH)
-
-
QUADSPI clock high and PRESCALER[7:0] =
low time Odd division
n = 2,4,6,8...
(n/2+1)*TCK
/
(n/2+1)*TCK
(n+1)+0.5
/
tw(CKL)
(n+1)
tsr(IN), tsf(IN)
Data input setup time
Data input hold time
-
-
1.5
3.5
-
-
-
-
-
thr(IN),thf(IN)
ns
DHHC=0
DHHC=1
5
6
tvr(OUT)
,
Data output valid time
Data output hold time
tvf(OUT)
-
3
TCK/4+1
TCK/4+2
PRESCALER[7:0] =
1,2…
DHHC=0
-
-
-
-
thr(OUT)
,
DHHC=1
thf(OUT)
TCK/4
PRESCALER[7:0]=1
,2…
1. Guaranteed by characterization results.
182/252
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Electrical characteristics
Figure 40. Quad-SPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
Figure 41. Quad-SPI timing diagram - DDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
tsr(IN)thr(IN)
D5
tsf(IN) thf(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv36879V1
6.3.20
Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 94 for Delay Block are derived
from tests performed under the ambient temperature, f frequency and VDD supply
rcc_c_ck
voltage summarized in Table 22: General operating conditions, with the following
configuration:
Table 94. Delay Block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tinit
t∆
Initial delay
Unit Delay
-
-
1400
35
2200
40
2400
45
ps
-
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Electrical characteristics
STM32H755xI
6.3.21
16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 95 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 22: General operating conditions.
(1)(2)
Table 95. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage for ADC
ON
V
-
1.62
-
3.6
V
DDA
Positive reference
voltage
V
-
-
1.62
-
V
V
V
REF+
DDA
Negative
reference voltage
V
V
SSA
REF-
BOOST = 11
BOOST = 10
BOOST = 01
BOOST = 00
0.12
0.12
0.12
-
-
-
-
-
50
25
ADC clock
frequency
f
1.62 V ≤ VDDA ≤ 3.6 V
MHz
ADC
12.5
6.25
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DS12919 Rev 1
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Electrical characteristics
(1)(2)
Table 95. ADC characteristics
Conditions
(continued)
Symbol
Parameter
Min
Typ
Max
Unit
Resolution = 16 bits,
f
f
=36 MHz
SMP = 1.5
-
-
3.60
ADC
ADC
V
>2.5 V
DDA
T
= 90 °C
J
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 16 bits,
=37 MHz
= 50 MHz
= 50 MHz
= 50 MHz
= 50 MHz
= 49 MHz
= 50 MHz
= 50 MHz
= 50 MHz
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 1.5
SMP = 1.5
SMP = 2.5
SMP = 2.5
SMP = 1.5
SMP = 1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.35
5.00
5.50
7.10
8.30
4.90
5.50
6.70
8.30
f
f
f
f
f
f
f
f
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
T
= 125 °C
J
Sampling rate for
Direct channels
T
= 140 °C
= 90 °C
J
f
f
=32 MHz
SMP = 2.5
-
-
2.90
ADC
ADC
V
>2.5 V
DDA
T
J
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 16 bits
resolution = 14 bits
resolution = 12 bits
resolution = 10 bits
resolution = 8 bits
resolution = 12 bits
resolution = 10 bits
resolution = 8 bits
=31 MHz
= 33 MHz
= 39 MHz
= 48 MHz
= 50 MHz
= 37 MHz
= 46 MHz
= 50 MHz
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
SMP = 2.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.80
3.30
4.30
6.00
7.10
4.10
5.70
7.10
f
f
f
f
f
f
f
ADC
ADC
ADC
ADC
ADC
ADC
ADC
(3)
f
MSps
s
Sampling rate for
Fast channels
T
= 125 °C
J
T
= 140 °C
= 90 °C
J
T
J
T
T
= 125 °C
= 140 °C
J
J
Sampling rate for
Slow channels
f
= 10 MHz
SMP = 1.5
1.00
ADC
External trigger
period
1/
t
Resolution = 16 bits
-
-
-
10
TRIG
f
ADC
Conversion
voltage range
(4)
AIN
V
-
-
0
V
REF+
V
Common mode
input voltage
V
/2
V
/
V
/2
REF
+ 10%
REF
− 10%
REF
2
V
V
CMIV
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Electrical characteristics
STM32H755xI
(1)(2)
Table 95. ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resolution = 16 bits, T = 140 °C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
170
J
Resolution = 16 bits, T = 125 °C
-
-
-
-
-
-
-
-
-
J
Resolution = 14 bits, T = 140 °C
200
J
Resolution = 14 bits, T = 125 °C
435
J
Resolution = 12 bits, T = 140 °C
700
J
External input
impedance
(5)
R
ꢁ
AIN
Resolution = 12 bits, T =125 °C
1150
3700
5650
18000
26500
J
Resolution = 10 bits, T = 140 °C
J
Resolution = 10 bits, T = 125 °C
J
Resolution = 8 bits, T = 140 °C
J
Resolution = 8 bits, T = 125 °C
J
Internal sample
and hold
capacitor
C
-
-
-
4
5
-
-
10
-
pF
us
ADC
t
ADC LDO startup
time
ADCVREG
_STUP
-
conver
sion
cycle
ADC Power-up
time
t
LDO already started
1
STAB
Offset and
linearity
calibration time
t
-
-
165010
1280
-
-
-
-
1/f
1/f
CAL
ADC
ADC
t
Offset calibration
time
OFF_
CAL
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
-
1.5
2
-
2.5
2.5
Trigger
conversion
latency regular
and injected
channels without
conversion abort
-
t
1/f
1/f
LATR
ADC
-
-
2.5
-
2.5
-
-
2.25
3.5
3
-
Trigger
conversion
latency regular
injected channels
aborting a regular
conversion
3.5
t
LATRINJ
ADC
-
-
3.5
-
-
3.25
810.5
t
Sampling time
1.5
-
1/f
1/f
S
ADC
ADC
Total conversion
time (including
sampling time)
ts + 0.5
+ N/2
t
Resolution = N bits
-
-
CONV
186/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
(1)(2)
Table 95. ADC characteristics
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resolution = 16 bits, f
Resolution = 14 bits, f
Resolution = 12 bits, f
=25 MHz
=30 MHz
=40 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1440
1350
990
1080
810
585
630
432
315
360
270
225
720
675
495
540
405
292.5
315
216
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADC
ADC
ADC
ADCconsumption
on V
BOOST=11,
,
DDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Differential mode
ADCconsumption
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
on V
DDA
BOOST=10,
Differential mode
f
=25 MHz
ADC
I
_
D
DDA
(ADC)
ADCconsumption
on V
DDA
BOOST=01,
Differential mode
f
=12.5 MHz
ADC
ADCconsumption
on V
DDA
BOOST=00,
Differential mode
f
=6.25 MHz
ADC
ADCconsumption
on V
Resolution = 16 bits, f
=25 MHz
ADC
DDA
Resolution = 14 bits, f
Resolution = 12 bits, f
=30 MHz
=40 MHz
BOOST=11,
Single-ended
mode
ADC
ADC
µA
ADCconsumption
Resolution = 16 bits
Resolution = 14 bits
Resolution = 12 bits
Resolution = 16 bits
Resolution = 14 bits
on V
DDA
BOOST=10,
Singl-ended mode
f
=25 MHz
ADC
I
_
(
DDA SE
ADCconsumption
on V
ADC)
DDA
BOOST=01,
Single-ended
mode
Resolution = 12 bits
-
-
-
157.5
-
f
=12.5 MHz
ADC
ADCconsumption
on V
BOOST=00,
Single-ended
mode
Resolution = 16 bits
Resolution = 14 bits
-
-
-
-
-
-
180
135
-
-
DDA
Resolution = 12 bits
-
-
-
112.5
-
f
=6.25 MHz
ADC
f
=50 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
220
180
120
80
-
-
-
-
-
ADC
f
=25 MHz
ADC
I
ADCconsumption
on V
DD
f
f
=12.5 MHz
=6.25 MHz
ADC
ADC
(ADC)
DD
f
=3.125 MHz
ADC
1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid for UFBGA176+25 and one ADC. The values for other packages and multiple ADCs may be different.
4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA
.
5. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.
DS12919 Rev 1
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Electrical characteristics
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(1)(2)
AIN
Table 96. Minimum sampling time vs R
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
16 bits
47
47
7.37E-08
6.29E-08
6.84E-08
7.80E-08
9.86E-08
1.32E-07
5.32E-08
5.74E-08
6.58E-08
8.37E-08
1.11E-07
1.56E-07
2.16E-07
3.01E-07
4.34E-08
4.68E-08
5.35E-08
6.68E-08
8.80E-08
1.24E-07
1.69E-07
2.38E-07
3.45E-07
5.15E-07
7.42E-07
1.10E-06
1.14E-07
9.74E-08
1.02E-07
1.12E-07
1.32E-07
1.61E-07
8.00E-08
8.50E-08
9.31E-08
1.10E-07
1.34E-07
1.78E-07
2.39E-07
3.29E-07
6.51E-08
6.89E-08
7.55E-08
8.77E-08
1.08E-07
1.43E-07
1.89E-07
2.60E-07
3.66E-07
5.35E-07
7.75E-07
1.14E-06
1.72E-07
1.55E-07
1.58E-07
1.62E-07
1.80E-07
2.01E-07
1.29E-07
1.32E-07
1.40E-07
1.51E-07
1.73E-07
2.14E-07
2.68E-07
3.54E-07
1.08E-07
1.11E-07
1.16E-07
1.26E-07
1.40E-07
1.71E-07
2.13E-07
2.80E-07
3.84E-07
5.48E-07
7.78E-07
1.14E-06
68
14 bits
100
150
220
47
68
100
150
220
330
470
680
47
12 bits
68
100
150
220
330
470
680
1000
1500
2200
3300
10 bits
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STM32H755xI
Resolution
Electrical characteristics
(1)(2)
Table 96. Minimum sampling time vs R
(continued)
AIN
Minimum sampling time (s)
RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
47
68
3.32E-08
3.59E-08
4.10E-08
5.06E-08
6.61E-08
9.17E-08
1.24E-07
1.74E-07
2.53E-07
3.73E-07
5.39E-07
8.02E-07
1.13E-06
1.62E-06
2.36E-06
3.50E-06
5.10E-08
5.35E-08
5.83E-08
6.76E-08
8.22E-08
1.08E-07
1.40E-07
1.91E-07
2.70E-07
3.93E-07
5.67E-07
8.36E-07
1.18E-06
1.69E-06
2.47E-06
3.69E-06
8.61E-08
8.83E-08
9.22E-08
9.95E-08
1.11E-07
1.32E-07
1.63E-07
2.12E-07
2.85E-07
4.05E-07
5.75E-07
8.38E-07
1.18E-06
1.68E-06
2.45E-06
3.65E-06
100
150
220
330
470
680
8 bits
1000
1500
2200
3300
4700
6800
10000
15000
1. Guaranteed by design.
2. Data valid at up to 140 °C, with a 47 pF PCB capacitor, and VDDA=1.6 V.
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to PF3, PF5, PF7, PF9, PA6, PC4, PB1, PF11 and PF13.
5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.
DS12919 Rev 1
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Electrical characteristics
STM32H755xI
(1)(2)
Table 97. ADC accuracy
Conditions(3)
Symbol
Parameter
Min
Typ
Max
Unit
Single ended
Differential
-
-
-
-
-
+10/–20
±15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Direct
channel
Single ended
Differential
+10/–20
±15
ET
Total undadjusted error
Fast channel
Single ended
Differential
±10
Slow
channel
±10
EO
EG
Offset error
Gain error
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±10
±15
LSB
Single ended
Differential
+3/–1
+4.5/–1
±11
ED
Differential linearity error
Integral linearity error
Effective number of bits
Single ended
Direct
channel
Differential
Single ended
Differential
±7
±13
EL
Fast channel
±7
Single ended
Differential
±10
Slow
channel
±6
Single ended
12.2
13.2
75.2
81.2
77.0
81.0
87
ENOB
SINAD
SNR
Bits
dB
Differential
Single ended
Differential
Signal-to-noise and
distortion ratio
Single ended
Differential
Signal-to-noise ratio
Single ended
Differential
THD
Total harmonic distortion
90
1. Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V and BOOST=11.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
Section 6.3.15 does not affect the ADC accuracy.
and ΣI
in
INJ(PIN)
INJ(PIN)
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DS12919 Rev 1
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Electrical characteristics
Figure 42. ADC accuracy characteristics (12-bit resolution)
V
V
DDA
4096
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
E
G
4095
4094
4093
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
E
O
L
E
D
1L SB
IDEAL
7
0
V
1
2
3
456
4093 4094 4095 4096
V
DDA
SSA
ai14395c
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 43. Typical connection diagram using the ADC
STM32
V
DD
Sample and hold ADC
V
T
converter
0.6 V
(1)
AIN
(1)
R
R
ADC
AINx
12-bit
converter
V
0.6 V
T
V
AIN
C
(1)
ADC
C
parasitic
I
1 μA
L
ai17534b
1. Refer to Table 95 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
DS12919 Rev 1
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Electrical characteristics
STM32H755xI
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 44 or Figure 45,
depending on whether V is connected to V or not. The 100 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 44. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM32
(1)
VREF+
1 μF // 100 nF
VDDA
1 μF // 100 nF
(1)
VSSA/VREF+
MSv50648V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA
.
Figure 45. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32
(1)
VREF+/VDDA
1 μF // 100 nF
(1)
VREF-/VSSA
MSv50649V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA
.
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STM32H755xI
Electrical characteristics
6.3.22
DAC characteristics
(1)(2)
Table 98. DAC characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
1.8
3.3
-
3.6
VREF+
Positive reference voltage
-
-
1.80
VDDA
V
Negative reference
voltage
VREF-
-
VSSA
-
-
-
connected
to VSSA
5
DAC output buffer
ON
RL
RO
Resistive Load
connected
to VDDA
kꢁ
25
10.3
-
-
13
-
-
Output Impedance
DAC output buffer OFF
16
1.6
VDD
2.7 V
=
=
Output impedance
sample and hold mode,
output buffer ON
DAC output buffer
ON
RBON
kꢁ
kꢁ
VDD
-
-
-
-
-
-
2.6
2.0 V
VDD
=
17.8
18.7
Output impedance
sample and hold mode,
output buffer OFF
2.7 V
DAC output buffer
OFF
RBOFF
VDD
=
2.0 V
CL
DAC output buffer OFF
Sample and Hold mode
-
-
-
50
1
pF
µF
Capacitive Load
CSH
0.1
VDDA
−0.2
DAC output buffer ON
DAC output buffer OFF
0.2
-
Voltage on DAC_OUT
output
VDAC_OUT
V
0
-
-
VREF+
±0.5 LSB
2.05
1.97
1.67
1.66
1.65
-
-
-
-
-
Settling time (full scale:
for a 12-bit code transition
between the lowest and
the highest input codes
when DAC_OUT reaches
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
±1 LSB
±2 LSB
±4 LSB
±8 LSB
-
Normal mode, DAC
output buffer ON,
CL ≤ 50 pF,
-
tSETTLING
µs
RL ≥ 5 ㏀
-
-
Normal mode, DAC output buffer
OFF, ±1LSB CL=10 pF
-
-
1.7
5
2
Wakeup time from off
state (setting the ENx bit
in the DAC Control
register) until the final
value of ±1LSB is reached
Normal mode, DAC output buffer
7.5
ON, CL ≤ 50 pF, RL = 5 ㏀
(3)
tWAKEUP
µs
Normal mode, DAC output buffer
2
5
OFF, CL ≤ 10 pF
DC VDDA supply rejection Normal mode, DAC output buffer
PSRR
-
−80
−28
dB
ratio
ON, CL ≤ 50 pF, RL = 5 ㏀
DS12919 Rev 1
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Electrical characteristics
STM32H755xI
(1)(2)
Table 98. DAC characteristics
Parameter Conditions
(continued)
Min
Symbol
Typ
Max
Unit
Sampling time in Sample
and Hold mode
MODE<2:0>_V12=100/101
(BUFFER ON)
-
-
0.7
2.6
ms
CL=100 nF
MODE<2:0>_V12=110
(BUFFER OFF)
11.5
0.3
18.7
0.6
(code transition between
the lowest input code and
the highest input code
when DAC_OUT reaches
the ±1LSB final value)
tSAMP
MODE<2:0>_V12=111
-
µs
(INTERNAL BUFFER OFF)
Internal sample and hold
capacitor
CIint
-
1.8
2.2
-
2.6
-
pF
µs
Middle code offset trim
time
Minimum time to verify the each
code
tTRIM
50
VREF+ = 3.6 V
VREF+ = 1.8 V
-
-
850
425
-
-
Middle code offset for 1
trim code step
Voffset
µV
No load,
middle
code
-
-
-
-
-
-
-
360
490
-
-
-
-
-
-
-
DAC output buffer
(0x800)
ON
No load,
worst code
(0xF1C)
DAC quiescent
IDDA(DAC)
consumption from VDDA
No load,
DAC output buffer middle/wor
20
OFF
st code
(0x800)
360*TON
/
Sample and Hold mode,
CSH=100 nF
(TON+TOFF
)
(4)
No load,
middle
code
µA
170
170
160
DAC output buffer
ON
(0x800)
No load,
worst code
(0xF1C)
No load,
DAC output buffer middle/wor
DAC consumption from
VREF+
IDDV(DAC)
OFF
st code
(0x800)
170*TON
/
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code)
-
-
(TON+TOFF
)
)
-
-
(4)
160*TON
/
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code)
(TON+TOFF
(4)
1. Guaranteed by design unless otherwise specified.
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DS12919 Rev 1
STM32H755xI
Electrical characteristics
2. TBD stands for “to be defined”.
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
(1)
Table 99. DAC accuracy
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON
DAC output buffer OFF
10 bits
−2
−2
-
-
-
-
2
2
-
Differential non
linearity(2)
DNL
-
LSB
-
Monotonicity
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀
−4
-
4
INL
Integral non linearity(3)
LSB
DAC output buffer OFF,
−4
-
-
4
CL ≤ 50 pF, no RL
DAC output
buffer ON,
CL ≤ 50 pF,
RL ≥ 5 ㏀
V
REF+ = 3.6 V
-
±15
Offset error at code
0x800 (3)
VREF+ = 1.8 V
-
-
-
-
±30
±8
Offset
LSB
DAC output buffer OFF,
CL ≤ 50 pF, no RL
Offset error at code
0x001(4)
DAC output buffer OFF,
Offset1
-
-
-
-
±5
±6
LSB
LSB
CL ≤ 50 pF, no RL
DAC output
VREF+ = 3.6 V
Offset error at code
0x800 after factory
calibration
buffer ON,
OffsetCal
CL ≤ 50 pF,
RL ≥ 5 ㏀
VREF+ = 1.8 V
-
-
±7
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀
-
-
-
-
-
±1
±1
-
Gain
SNR
Gain error(5)
%
DAC output buffer OFF,
CL ≤ 50 pF, no RL
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
67.8
Signal-to-noise ratio(6)
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL,1 kHz, BW =
500 KHz
-
67.8
-
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
-
-
-
-
−78.6
−78.6
67.5
-
-
-
-
Total harmonic
distortion(6)
THD
dB
dB
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
Signal-to-noise and
distortion ratio(6)
SINAD
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
67.5
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Electrical characteristics
STM32H755xI
(1)
Table 99. DAC accuracy (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DAC output buffer ON,
-
10.9
-
CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
Effective number of
bits
ENOB
bits
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
-
10.9
-
1. Guaranteed by characterization.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5dBFS with Fsampling=1 MHz.
Figure 46. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
DAC_OUTx
12-bit
digital to
analog
converter
C
L
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
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Electrical characteristics
6.3.23
Voltage reference buffer characteristics
(1)
Table 100. VREFBUF characteristics
Conditions
Symbol
Parameter
Min
2.8
Typ
Max
3.6
Unit
VSCALE = 000
3.3
VSCALE = 001
Normal mode
2.4
-
3.6
VSCALE = 010
2.1
-
3.6
VSCALE = 011
VSCALE = 000
1.8
-
3.6
VDDA
Analog supply voltage
1.62
1.62
1.62
1.62
2.498
2.046
1.801
-
2.80
2.40
2.10
1.80
2.5035
2.052
1.806
1.504
VSCALE = 001
Degraded mode
-
-
VSCALE = 010
VSCALE = 011
VSCALE = 000
-
2.5
2.049
1.804
V
VSCALE = 001
Normal mode
VSCALE = 010
VSCALE = 011 1.4995 1.5015
VDDA
150 mV
−
Voltage Reference
Buffer Output, at 30 °C,
Iload= 100 µA
VSCALE = 000
VSCALE = 001
VSCALE = 010
VSCALE = 011
-
-
-
-
VDDA
VDDA
VDDA
VDDA
VREFBUF
_OUT
VDDA
150 mV
−
Degraded mode(2)
VDDA
150 mV
−
VDDA
150 mV
−
TRIM
CL
Trim step resolution
Load capacitor
-
-
-
-
-
±0.05
1
±0.1
1.50
%
0.5
uF
Equivalent Serial
Resistor of CL
esr
-
-
-
-
-
-
2
Ω
Iload
Static load current
-
-
-
-
4
-
mA
I
load = 500 µA
Iload = 4 mA
200
100
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
ppm/V
-
ppm/
mA
Iload_reg
Load regulation
500 µA ≤ ILOAD ≤ 4 mA Normal Mode
−40 °C < TJ < +125 °C
-
-
50
-
-
Tcoeff
VREFINT
+ 100
ppm/
°C
Tcoeff
Temperature coefficient
DC
-
-
-
-
60
40
-
-
PSRR
Power supply rejection
dB
100KHz
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Electrical characteristics
STM32H755xI
(1)
Table 100. VREFBUF characteristics (continued)
Symbol
Parameter
Conditions
CL=0.5 µF
Min
Typ
300
500
650
Max
Unit
-
-
-
-
-
-
-
-
-
tSTART
Start-up time
CL=1 µF
µs
CL=1.5 µF
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
IINRUSH
-
-
8
-
mA
µA
ILOAD = 0 µA
-
-
-
-
-
-
15
16
32
25
30
50
VREFBUF
consumption from
VDDA
IDDA(VRE
ILOAD = 500 µA
FBUF)
ILOAD = 4 mA
1. Guaranteed by design.
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
6.3.24
Temperature sensor characteristics
Table 101. Temperature sensor characteristics
Symbol
Parameter
Min Typ Max Unit
(1)
TL
VSENSE linearity with temperature
-
-
-
3
°C
mV/°C
V
Avg_Slope(2) Average slope
2
-
(3)
V30
Voltage at 30°C ± 5 °C
-
0.62
-
25.2
-
tstart_run
Startup time in Run mode (buffer startup)
ADC sampling time when reading the temperature
Sensor consumption
-
-
-
µs
(1)
tS_temp
9
-
(1)
Isens
0.18 0.31
3.8 6.5
µA
(1)
Isensbuf
Sensor buffer consumption
-
1. Guaranteed by design.
2. Guaranteed by characterization.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 102. Temperature sensor calibration values
Symbol
Parameter
Memory address
Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V
TS_CAL1
0x1FF1 E820 -0x1FF1 E821
Temperature sensor raw data acquired value at
110 °C, VDDA=3.3 V
TS_CAL2
0x1FF1 E840 - 0x1FF1 E841
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DS12919 Rev 1
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Electrical characteristics
6.3.25
Temperature and V
monitoring
BAT
Table 103. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
26
4
-
Kꢁ
-
Ratio on VBAT measurement
Error on Q
-
-
Er(1)
–10
-
+10
%
µs
(1)
tS_vbat
ADC sampling time when reading VBAT input
High supply monitoring
9
-
-
-
-
-
VBAThigh
VBATlow
3.55
1.36
V
Low supply monitoring
-
1. Guaranteed by design.
Table 104. V
charging characteristics
BAT
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBRS in PWR_CR3= 0
VBRS in PWR_CR3= 1
-
5
-
-
RBC
Battery charging resistor
Kꢁ
1.5
Table 105. Temperature monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
TEMPhigh
TEMPlow
High temperature monitoring
Low temperature monitoring
-
-
117
-
-
°C
–25
6.3.26
Voltage booster for analog switch
(1)
Table 106. Voltage booster for analog switch characteristics
Symbol
Parameter
Supply voltage
Condition
Min Typ Max Unit
VDD
-
1.62 2.6 3.6
V
Booster startup time
-
-
-
-
-
-
-
50
µs
tSU(BOOST)
1.62 V ≤ VDD ≤ 2.7 V
2.7 V < VDD < 3.6 V
125
250
Booster consumption
µA
IDD(BOOST)
1. Guaranteed by characterization results.
DS12919 Rev 1
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Electrical characteristics
STM32H755xI
6.3.27
Comparator characteristics
(1)
Table 107. COMP characteristics
Conditions
Symbol
VDDA
Parameter
Min
Typ
Max
Unit
Analog supply voltage
-
-
1.62
3.3
3.6
Comparator input voltage
range
VIN
0
-
VDDA
V
(2)
VBG
VSC
Scaler input voltage
Scaler offset voltage
-
-
-
-
±5
0.2
0.8
140
2
±10
0.3
1
mV
µA
µs
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
Scaler static consumption
from VDDA
IDDA(SCALER)
-
tSTART_SCALER Scaler startup time
-
250
5
High-speed mode
Medium mode
-
Comparator startup time to
reach propagation delay
tSTART
-
5
20
80
80
1.2
7
µs
specification
Ultra-low-power mode
High-speed mode
Medium mode
-
15
50
0.5
2.5
50
0.5
2.5
±5
0
-
ns
µs
Propagation delay for
200 mV step with 100 mV
overdrive
-
Ultra-low-power mode
High-speed mode
Medium mode
-
(3)
tD
-
120
1.2
7
ns
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
-
µs
Ultra-low-power mode
Full common mode range
No hysteresis
-
Voffset
Comparator offset error
-
±20
-
mV
-
Low hysteresis
5
8
16
-
10
20
30
400
22
37
52
600
Vhys
Comparator hysteresis
mV
nA
Medium hysteresis
High hysteresis
Static
Ultra-low-
With 50 kHz
±100 mV overdrive
square signal
power mode
-
-
-
-
-
800
5
-
Static
7
Comparator consumption
from VDDA
With 50 kHz
I
DDA(COMP)
Medium mode
±100 mV overdrive
square signal
6
-
100
-
µA
Static
70
75
High-speed
mode
With 50 kHz
±100 mV overdrive
square signal
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 29: Embedded reference voltage.
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3. Guaranteed by characterization results.
6.3.28
Operational amplifier characteristics
Table 108. Operational amplifier characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
Range
VDDA
CMIR
-
2
3.3
3.6
V
Common Mode Input
Range
-
0
-
-
VDDA
±1.5
±2.5
-
25°C, no load on output
-
-
VIOFFSET
Input offset voltage
mV
All voltages and
temperature, no load
-
ΔVIOFFSET
Input offset voltage drift
-
-
-
±3.0
μV/°C
Offset trim step at low
common input voltage
TRIMOFFSETP
-
-
1.1
1.1
1.5
1.5
TRIMLPOFFSETP
(0.1*VDDA
)
mV
Offset trim step at high
common input voltage
TRIMOFFSETN
-
TRIMLPOFFSETN
(0.9*VDDA
)
ILOAD
ILOAD_PGA
CLOAD
Drive current
Drive current in PGA mode
Capacitive load
-
-
-
-
-
-
-
-
-
500
270
50
μA
pF
dB
Common mode rejection
ratio
CMRR
PSRR
-
-
80
66
-
-
CLOAD ≤ 50pf /
RLOAD ≥ 4 kꢁ(1) at 1 kHz,
Vcom=VDDA/2
Power supply rejection
ratio
50
4
dB
Gain bandwidth for high
supply range
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
GBW
SR
7.3
12.3
MHz
V/µs
dB
Normal mode
-
-
3
-
-
Slew rate (from 10% and
90% of output voltage)
High-speed mode
30
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
AO
Open loop gain
59
90
129
φm
Phase margin
Gain margin
-
-
-
-
55
12
-
-
°
GM
dB
I
load=max or RLOAD=min,
Input at VDDA
VDDA
−100 mV
VOHSAT
High saturation voltage
Low saturation voltage
-
-
-
mV
Iload=max or RLOAD=min,
Input at 0 V
VOLSAT
-
100
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Table 108. Operational amplifier characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kꢁ,
-
0.8
3.2
mode
follower
configuration
Wake up time from OFF
state
tWAKEUP
µs
CLOAD ≤ 50pf,
RLOAD ≥ 4 kꢁ,
follower
High
speed
mode
-
0.9
2.8
configuration
PGA gain = 2
−1
−2
−2.5
−3
−1
−1
−2
−3
−1
−3
−3.5
−4
-
-
1
2
2.5
3
1
1
2
3
1
3
3.5
4
-
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA Gain=2
PGA Gain=4
PGA Gain=8
PGA Gain=16
PGA Gain = -1
PGA Gain = -3
PGA Gain = -7
PGA Gain = -15
-
Non inverting gain error
value
-
-
-
-
PGA gain
Inverting gain error value
%
-
-
-
-
External non-inverting gain
error value
-
-
10/10
30/10
70/10
150/10
10/10
30/10
70/10
150/10
R2/R1 internal resistance
values in non-inverting
PGA mode(2)
-
-
-
-
-
-
kꢁ/
kꢁ
Rnetwork
-
-
R2/R1 internal resistance
values in inverting PGA
mode(2)
-
-
-
-
-
-
Resistance variation (R1
or R2)
Delta R
-
−15
-
15
%
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Symbol
Electrical characteristics
Table 108. Operational amplifier characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
Gain=2
Gain=4
-
-
-
-
-
-
-
-
GBW/2
GBW/4
GBW/8
GBW/16
5.00
-
-
-
-
-
-
-
-
PGA bandwidth for
different non inverting gain
MHz
Gain=8
Gain=16
Gain = -1
Gain = -3
Gain = -7
Gain = -15
PGA BW
3.00
PGA bandwidth for
different inverting gain
MHz
1.50
0.80
at
1 KHz
-
-
-
140
55
-
-
output loaded
with 4 kꢁ
nV/√
Hz
en
Voltage noise density
at
10 KHz
Normal
mode
570
1000
no Load,
quiescent mode,
follower
OPAMP consumption from
VDDA
IDDA(OPAMP)
µA
High-
speed
mode
-
610
1200
1. RLOAD is the resistive load connected to VSSA or to VDDA.
2. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
6.3.29
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 109 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 22: General operating conditions.
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).
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Table 109. DFSDM measured timing 1.62-3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DFSDM
clock
fDFSDMCLK
1.62 < VDD < 3.6 V
-
-
133
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
-
-
-
-
-
-
-
-
20
20
20
20
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
fCKIN
(1/TCKIN
Input clock
frequency
MH
z
)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]¹0),
2.7 < VDD < 3.6 V
Output clock
frequency
fCKOUT
1.62 < VDD < 3.6 V
1.62 < VDD < 3.6 V
-
-
20
55
Output clock
frequency
duty cycle
DuCyCKOU
45
50
%
T
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Input clock
high and low
time
twh(CKIN)
twl(CKIN)
TCKIN/2-0.5
TCKIN/2
-
-
-
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Data input
setup time
tsu
1.5
0.5
-
-
-
ns
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Data input
hold time
th
Manchester Manchester mode (SITP[1:0]=2,3),
data period
(recovered
clock period)
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
(CKOUTDIV+1)
* TDFSDMCLK
(2*CKOUTDIV)
* TDFSDMCLK
TManchester
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Figure 47. Channel transceiver timing diagrams
(SPICKSEL=0)
SITP = 00
tr
tf
twl
twh
tsu
th
tsu
th
SITP = 01
SPICKSEL=3
SPICKSEL=2
SPICKSEL=1
tr
tf
twl
twh
tsu
th
SITP = 0
SITP = 1
tsu
th
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V2
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6.3.30
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 110 for DCMI are derived from
tests performed under the ambient temperature, f
frequency and VDD supply voltage
HCLK
summarized in Table 22: General operating conditions, with the following configuration:
•
•
•
•
•
•
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
(1)
Table 110. DCMI characteristics
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
Pixel Clock input
-
-
0.4
80
70
-
-
DCMI_PIXCLK
Dpixel
MHz
%
Pixel Clock input duty cycle
Data input setup time
30
3
t
su(DATA)
-
th(DATA)
Data hold time
1
-
tsu(HSYNC),
tsu(VSYNC)
DCMI_HSYNC/ DCMI_VSYNC input setup time
DCMI_HSYNC/ DCMI_VSYNC input hold time
2
1
-
-
ns
-
th(HSYNC),
th(VSYNC)
1. Guaranteed by characterization results.
Figure 48. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
th(HSYNC)
tsu(HSYNC)
th(HSYNC)
tsu(VSYNC)
tsu(DATA) th(DATA)
MS32414V2
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Electrical characteristics
6.3.31
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 111 for LCD-TFT are derived
from tests performed under the ambient temperature, f
frequency and VDD supply
HCLK
voltage summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
•
•
•
•
•
LCD_CLK polarity: high
LCD_DE polarity: low
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5VDD
IO Compensation cell activated.
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
(1)
Table 111. LTDC characteristics
Symbol
Parameter
Min
Max
Unit
2.7<VD <3.6 V
D
150
LTDC clock
output
frequency
20pF
fCLK
-
MHz
%
2.7<VD <3.6 V
133
90
D
1.62<VD <3.6 V
D
DCLK
LTDC clock output duty cycle
Clock High time, low time
45
55
tw(CLKH),
tw(CLKL)
tw(CLK)//2-0.5
tw(CLK)//2+0.5
tv(DATA)
th(DATA)
tv(DATA)
2.7<VD <3.6 V
0.5
5
D
-
Data output valid time
-
1.62<VD <3.6 V
D
Data output hold time
0
-
-
tv(HSYNC),
tv(VSYNC),
tv(DE)
2.7<VD <3.6 V
0.5
D
HSYNC/VSYNC/DE output
valid time
1.62<VD <3.6 V
-
5
D
th(HSYNC),
HSYNC/VSYNC/DE output hold time
0
-
th(VSYNC)
,
th(DE)
1. Guaranteed by characterization results.
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Figure 49. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC)
tv(HSYNC)
LCD_HSYNC
th(DE)
tv(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
Pixel Pixel
1
Pixel
N
2
th(DATA)
Active width
HSYNCHorizontal
width back porch
Horizontal
back porch
One line
MS32749V1
Figure 50. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC)
tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
M lines data
VSYNC Vertical
width back porch
Active width
One frame
Vertical
back porch
MS32750V1
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Electrical characteristics
6.3.32
Timer characteristics
The parameters given in Table 112 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 112. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK
=
tTIMxCLK
1
-
240 MHz
tres(TIM)
Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK
=
tTIMxCLK
1
-
120 MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK/2
16/32
0
-
MHz
bit
f
TIMxCLK = 240 MHz
ResTIM
Timer resolution
Maximum possible count
with 32-bit counter
65536 ×
65536
tMAX_COUNT
tTIMxCLK
-
-
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2
.
6.3.33
Communication interfaces
I2C interface characteristics
2
The I C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
2
The I C timings requirements are guaranteed by design when the I C peripheral is properly
configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
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Electrical characteristics
Symbol
STM32H755xI
Unit
2
Table 113. Minimum i2c_ker_ck frequency in all I C modes
Parameter
Condition
Min
Standard-mode
Fast-mode
-
2
Analog Filtre ON
DNF=0
8
9
MHz
Analog Filtre OFF
DNF=1
I2CCLK
frequency
f(I2CCLK)
Analog Filtre ON
DNF=0
17
16
Fast-mode Plus
Analog Filtre OFF
DNF=1
-
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and V is disabled, but still present.
DDIOx
•
The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load C supported in Fm+, which is given by these formulas:
Load
t
=0.8473xR xC
P Load
r(SDA/SCL)
R
= (V -V
)/I
P(min)
DD OL(max) OL(max)
Where R is the I2C lines pull-up. Refer to Section 6.3.16: I/O port characteristics for
P
2
the I C I/Os characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
2
(1)
Table 114. I C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes
that are suppressed by analog
filter
tAF
50(2)
80(3)
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
USART interface characteristics
Unless otherwise specified, the parameters given in Table 115 for USART are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS1
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Electrical characteristics
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
(1)
Table 115. USART characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
Slave mode
Slave mode
Slave mode
12.5
fCK
USART clock frequency
-
-
MHz
25
-
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
tker+1
2
-
-
-
-
,
CK high and low time
Data input setup time
Master mode
1/fCK/2-2
1/fCK/2
1/fCK/2+2
tw(SCKL)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
t
ker+6
-
-
-
-
tsu(RX)
th(RX)
tv(TX)
th(TX)
1.5
0
-
-
Data input hold time
Data output valid time
Data output hold time
1.5
-
-
-
ns
12
0.5
-
20
1
-
-
9
0
-
-
1. Guaranteed by characterization results.
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Figure 51. USART timing diagram in Master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 52. USART timing diagram in Slave mode
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 116 for SPI are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 116. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
1.62<VDD<3.6 V
SPI1, 2, 3
80
Master mode
2.7<VDD<3.6 V
SPI1, 2, 3
100
50
Master mode
1.62<VDD<3.6 V
SPI4, 5, 6
fSCK
SPI clock frequency
-
-
MHz
Slave receiver mode
1.62<VDD<3.6 V
100
31
Slave mode transmitter/full duplex
2.7<VDD<3.6 V
Slave mode transmitter/full duplex
1.62 <VDD<3.6 V
29
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
2
1
-
-
-
-
-
,
SCK high and low time Master mode
TPCLK-2 TPCLK TPCLK+2
tw(SCKL)
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Electrical characteristics
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(1)
Table 116. SPI characteristics (continued)
Parameter Conditions Min
Master mode
Symbol
Typ
Max
Unit
tsu(MI)
tsu(SI)
th(MI)
1
1
4
2
9
0
-
-
-
-
Data input setup time
Slave mode
Master mode
Slave mode
-
-
Data input hold time
th(SI)
-
-
ta(SO)
tdis(SO)
Data output access time Slave mode
Data output disable time Slave mode
13
1
27
5
Slave mode
ns
-
12.5
16
2.7<VDD<3.6 V
tv(SO)
Data output valid time
Data output hold time
Slave mode
-
-
12.5
17
3
-
1.62<VDD<3.6 V
tv(MO)
th(SO)
th(MO)
Master mode
1
-
Slave mode
10
0
1.62<VDD<3.6 V
Master mode
-
-
1. Guaranteed by characterization results.
Figure 53. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
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STM32H755xI
Electrical characteristics
(1)
Figure 54. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
(1)
Figure 55. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
DS12919 Rev 1
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Electrical characteristics
STM32H755xI
I2S Interface characteristics
2
Unless otherwise specified, the parameters given in Table 117 for I S are derived from tests
performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
2
(1)
Table 117. I S dynamic characteristics
Parameter Conditions
Symbol
Min
Max
Unit
fMCK
I2S main clock output
-
256x8K
256FS
MHz
Master data
-
64FS
fCK
I2S clock frequency
MHz
Slave data
-
64FS
tv(WS)
th(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
-
3
-
-
-
-
-
-
-
0
1
1
1
1
4
2
tsu(WS)
th(WS)
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
Data input setup time
Data input hold time
ns
Slave transmitter (after enable
edge)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
-
-
17
3
-
Data output valid time
Data output hold time
Master transmitter (after
enable edge)
Slave transmitter (after enable
edge)
9
0
Master transmitter (after
enable edge)
-
1. Guaranteed by characterization results.
216/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
2
(1)
Figure 56. I S slave timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 57. I S master timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DS12919 Rev 1
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Electrical characteristics
STM32H755xI
SAI characteristics
Unless otherwise specified, the parameters given in Table 118 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
L
IO Compensation cell activated.
Measurement points are done at CMOS levels: 0.5VDD
VOS level set to VOS1.
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
(1)
Table 118. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
SAI Main clock output
-
256x8K 256xFS
(3)
(3)
Master Data: 32 bits
Slave Data: 32 bits
-
-
128xFS
128xFS
MHz
SAI clock
fCK
frequency(2)
218/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
(1)
Table 118. SAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode
-
-
13
2.7≤VDD≤3.6
tv(FS)
FS valid time
Master mode
20
1.62≤VDD≤3.6
tsu(FS)
th(FS)
FS hold time
FS setup time
FS hold time
Master mode
Slave mode
8
1
-
-
-
-
-
-
-
Slave mode
1
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
0.5
1
Data input setup time
Data input hold time
3.5
2
Slave transmitter (after enable
edge)
-
14
ns
2.7≤VDD≤3.6
tv(SD_B_ST) Data output valid time
th(SD_B_ST) Data output hold time
tv(SD_A_MT) Data output valid time
Slave transmitter (after enable
edge)
-
9
-
20
-
1.62≤VDD≤3.6
Slave transmitter (after enable
edge)
Master transmitter (after enable
edge)
12
2.7≤VDD≤3.6
Master transmitter (after enable
edge)
-
19
-
1.62≤VDD≤3.6
Master transmitter (after enable
edge)
th(SD_A_MT) Data output hold time
7.5
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
DS12919 Rev 1
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Electrical characteristics
STM32H755xI
Figure 58. SAI master timing waveforms
1/f
SCK
SAI_SCK_X
t
h(FS)
SAI_FS_X
(output)
t
t
t
h(SD_MT)
v(FS)
v(SD_MT)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_MR)
su(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 59. SAI slave timing waveforms
1/f
SCK
SAI_SCK_X
t
t
t
h(FS)
w(CKH_X)
w(CKL_X)
SAI_FS_X
(input)
t
t
t
h(SD_ST)
su(FS)
v(SD_ST)
SAI_SD_X
(transmit)
Slot n
Slot n+2
t
t
h(SD_SR)
su(SD_SR)
SAI_SD_X
(receive)
Slot n
MS32772V1
MDIO characteristics
Table 119. MDIO Slave timing parameters
Symbol
Parameter
Min
Typ
Max
Unit
FMDC
td(MDIO)
tsu(MDIO)
th(MDIO)
Management Data Clock
-
-
10
-
30
19
-
MHz
Management Data Iput/output output valid time
Management Data Iput/output setup time
Management Data Iput/output hold time
8
1
1
ns
-
-
220/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
Figure 60. MDIO Slave timing diagram
tMDC)
td(MDIO)
tsu(MDIO)
th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 120 and Table 121 for SDIO are
derived from tests performed under the ambient temperature, f
frequency and VDD
PCLKx
supply voltage summarized in Table 22: General operating conditions, with the following
configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 0x11
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when V ≤ 2.7 V
DD
VOS level set to VOS1
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
(1)(2)
Table 120. Dynamics characteristics: SD / MMC characteristics, V =2.7 to 3.6 V
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
0
-
-
133
MHz
-
-
-
8/3
fPP =52MHz
fPP =52MHz
8.5
8.5
9.5
9.5
-
-
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
-
1.5
1.5
3
-
-
-
-
-
-
ns
-
(4)
tIDW
Input valid window (variable window)
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode
tOV
tOH
Output valid time HS
Output hold time HS
-
-
-
3.5
-
5
-
ns
2
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Electrical characteristics
STM32H755xI
(1)(2)
Table 120. Dynamics characteristics: SD / MMC characteristics, V =2.7 to 3.6 V
(continued)
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D inputs (referenced to CK) in SD default mode
Input setup time SD
Input hold time SD
-
-
1.5
1.5
-
-
tISUD
tIHD
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time SD
Output hold default time SD
-
-
-
0.5
-
2
-
ns
0
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. An external voltage converter is required to support SD 1.8 V.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
(1)(2)
Unit
Table 121. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V
Symbol
Parameter
Conditions
Min
Typ
Max
Clock frequency in data transfer
mode
fPP
-
0
-
120
MHz
-
-
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
-
8/3
tW(CKL)
tW(CKH)
fPP =52 MHz
fPP =52 MHz
8.5
8.5
9.5
9.5
-
-
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
-
-
1
-
-
-
-
2.5
Input valid window (variable
window)
(3)
tIDW
-
3.5
-
-
CMD, D outputs (referenced to CK) in eMMC mode
tOVD
tOHD
Output valid time HS
Output hold time HS
-
-
-
5
-
7
-
3
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
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STM32H755xI
Electrical characteristics
Figure 61. SDIO high-speed mode
Figure 62. SD default mode
CK
t
t
OVD
OHD
D, CMD
(output)
ai14888
Figure 63. DDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tvf(OUT) thr(OUT)
D0
tvr(OUT)
thf(OUT)
D3
Data output
D1
D2
D4
D5
tsf(IN) thf(IN)
tsr(IN)thr(IN)
Data input
D0
D1
D2
D3
D4
D5
MSv36879V1
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Electrical characteristics
STM32H755xI
USB OTG_HS characteristics
Unless otherwise specified, the parameters given in Table 122 for ULPI are derived from
tests performed under the ambient temperature, f frequency and V supply voltage
PCLKx
DD
summarized in Table 22: General operating conditions, with the following configuration:
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
VOS level set to VOS1
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
(1)
Table 122. Dynamics characteristics: USB ULPI
Symbol
Parameter
Condition
Min Typ Max Unit
Control in (ULPI_DIR , ULPI_NXT) setup
time
tSC
-
2.5
2
-
-
-
-
Control in (ULPI_DIR, ULPI_NXT) hold
time
tHC
-
tSD
tHD
Data in setup time
Data in hold time
-
-
2.5
0
-
-
-
-
ns
2.7<VDD<3.6 V
CL=20 pF
-
-
9
9
9.5
14
t
DC/tDD
Control/Datal output delay
1.71<VDD<3.6 V
CL=15 pF
1. Guaranteed by characterization results.
Figure 64. ULPI timing diagram
Clock
t
t
HC
SC
Control In
(ULPI_DIR,
ULPI_NXT)
t
t
HD
SD
data In
(8-bit)
t
t
DC
DC
Control out
(ULPI_STP)
t
DD
data out
(8-bit)
ai17361c
224/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
Ethernet interface characteristics
Unless otherwise specified, the parameters given in Table 123, Table 124 and Table 125 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
f
frequency and V supply voltage conditions summarized in Table 22: General
rcc_c_ck
DD
operating conditions, with the following configuration:
•
•
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C =20 pF
L
Measurement points are done at CMOS levels: 0.5V
IO Compensation cell activated.
DD
HSLV activated when VDD ≤ 2.7 V
VOS level set to VOS1
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics:
(1)
Table 123. Dynamics characteristics: Ethernet MAC signals for SMI
Symbol
Parameter
Min
Typ
Max
Unit
tMDC
MDC cycle time( 2.5 MHz)
Write data valid time
Read data setup time
Read data hold time
400
0.5
12.5
0
400
403
Td(MDIO)
tsu(MDIO)
th(MDIO)
1.5
4
-
ns
-
-
-
1. Guaranteed by characterization results.
Figure 65. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
ETH_MDIO(I)
tsu(MDIO)
th(MDIO)
MS31384V1
DS12919 Rev 1
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Electrical characteristics
STM32H755xI
(1)
Table 124. Dynamics characteristics: Ethernet MAC signals for RMII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(CRS)
tih(CRS)
td(TXEN)
td(TXD)
Receive data setup time
Receive data hold time
2
2
-
-
-
-
Carrier sense setup time
Carrier sense hold time
1.5
1.5
7
-
-
ns
-
-
Transmit enable valid delay time
Transmit data valid delay time
8
9
9.5
11
8
1. Guaranteed by characterization results.
Figure 66. Ethernet RMII timing diagram
RMII_REF_CLK
t
t
d(TXEN)
d(TXD)
RMII_TX_EN
RMII_TXD[1:0]
t
t
t
t
su(RXD)
su(CRS)
ih(RXD)
ih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
(1)
Table 125. Dynamics characteristics: Ethernet MAC signals for MII
Symbol
Parameter
Min
Typ
Max
Unit
tsu(RXD)
tih(RXD)
tsu(DV)
tih(DV)
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
2
-
-
-
2
-
1.5
1.5
1.5
0.5
9
-
-
-
-
-
ns
tsu(ER)
tih(ER)
td(TXEN)
td(TXD)
Error setup time
-
Error hold time
-
-
Transmit enable valid delay time
Transmit data valid delay time
10
9.5
11
12.5
8.5
1. Guaranteed by characterization results.
226/252
DS12919 Rev 1
STM32H755xI
Electrical characteristics
Figure 67. Ethernet MII timing diagram
MII_RX_CLK
t
t
t
t
t
t
su(RXD)
su(ER)
su(DV)
ih(RXD)
ih(ER)
ih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
t
t
d(TXEN)
d(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 126 and Table 127 for
JTAG/SWD are derived from tests performed under the ambient temperature, f
rcc_c_ck
frequency and V supply voltage summarized in Table 22: General operating conditions,
DD
with the following configuration:
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 0x10
Capacitive load C =30 pF
L
Measurement points are done at CMOS levels: 0.5V
VOS level set to VOS1
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics:
Table 126. Dynamics JTAG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7V <VDD< 3.6 V
-
-
-
-
37
TCK clock frequency
1/tc(TCK)
tisu(TMS)
tih(TMS)
tisu(TDI)
tih(TDI)
1.62 <VDD< 3.6 V
27.5
MHz
TMS input setup time
TMS input hold time
TDI input setup time
TDI input hold time
-
2.5
1
-
-
-
-
-
-
1.5
1
-
-
-
-
-
-
-
-
-
-
2.7V <VDD< 3.6 V
1.62 <VDD< 3.6 V
-
-
8
8
-
13.5
18
-
tov(TDO)
toh(TDO)
TDO output valid time
TDO output hold time
-
7
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Electrical characteristics
Symbol
STM32H755xI
Table 127. Dynamics SWD characteristics:
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
2.7V <VDD< 3.6 V
-
-
-
-
71
52.5
-
SWCLK clock frequency
MHz
1/tc(SWCLK)
tisu(SWDIO)
tih(SWDIO)
1.62 <VDD< 3.6 V
SWDIO input setup time
SWDIO input hold time
-
2.5
1
-
-
-
-
-
-
-
2.7V <VDD< 3.6 V
1.62 <VDD< 3.6 V
-
8.5
14
tov(SWDIO)
SWDIO output valid time
SWDIO output hold time
-
8.5
-
19
-
-
-
toh(SWDIO)
-
8
Figure 68. JTAG timing diagram
tc(TCK)
TCK
TDI/TMS
TDO
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL)
tw(TCKH)
tov(TDO)
toh(TDO)
MSv40458V1
Figure 69. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL)
tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
228/252
DS12919 Rev 1
STM32H755xI
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com.
®
ECOPACK is an ST trademark.
DS12919 Rev 1
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250
Package information
STM32H755xI
7.1
LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 70. LQFP144 package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
108
73
109
72
37
144
1
36
PIN 1
IDENTIFICATION
e
1A_ME_V4
1. Drawing is not to scale.
230/252
DS12919 Rev 1
STM32H755xI
Package information
Table 128. LQFP144 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS12919 Rev 1
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250
Package information
STM32H755xI
Figure 71. LQFP144 package recommended footprint
1.35
108
73
109
72
0.35
0.5
19.9
17.85
22.6
144
37
1
36
19.9
22.6
ai14905e
1. Dimensions are expressed in millimeters.
232/252
DS12919 Rev 1
STM32H755xI
Package information
Device marking for LQFP144
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 72. LQFP144 marking example (package top view)
Revision code
Product identification(1)
R
ES32H755ZIT6
Date code
Y WW
Pin 1 identifier
MSv50640V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12919 Rev 1
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Package information
STM32H755xI
7.2
LQFP176 package information
LQFP176 is a 176-pin, 24 x 24 mm low profile quad flat package.
Figure 73. LQFP176 package outline
Seating plane
C
0.25 mm
gauge plane
k
A1
L
HD
L1
PIN 1
IDENTIFICATION
D
ZE
E
HE
e
ZD
b
1T_ME_V2
1. Drawing is not to scale.
Table 129. LQFP176 package mechanical data
Dimensions
Ref.
Millimeters
Inches(1)
Typ.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
-
-
-
-
-
-
1.600
0.150
1.450
0.270
0.200
-
-
-
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.050
1.350
0.170
0.090
0.0020
0.0531
0.0067
0.0035
c
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STM32H755xI
Package information
Table 129. LQFP176 package mechanical data (continued)
Dimensions
Ref.
Millimeters
Typ.
Inches(1)
Typ.
Min.
Max.
Min.
Max.
D
HD
ZD
E
23.900
-
24.100
0.9409
-
0.9488
25.900
-
26.100
1.0197
-
1.0276
-
1.250
-
-
0.0492
-
23.900
-
24.100
0.9409
-
0.9488
HE
ZE
e
25.900
-
26.100
1.0197
-
1.0276
-
1.250
-
-
0.0492
-
-
0.500
-
0.750
-
-
0.0197
-
0.0295
-
L(2)
L1
k
0.450
-
0.0177
-
-
0°
-
1.000
-
0°
-
0.0394
-
-
7°
-
-
7°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
DS12919 Rev 1
235/252
250
Package information
STM32H755xI
Figure 74. LQFP176 package recommended footprint
1.2
176
133
132
0.5
1
0.3
44
45
89
88
1.2
21.8
26.7
1T_FP_V1
1. Dimensions are expressed in millimeters.
236/252
DS12919 Rev 1
STM32H755xI
Package information
Device marking for LQFP176
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 75. LQFP176 marking example (package top view)
Product identification(1)
ST32H755IIT6
Date code
Revision code
Y WW
R
Pin 1identifier
MSv61378V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12919 Rev 1
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250
Package information
STM32H755xI
7.3
LQFP208 package information
LQFP208 is a 208-pin, 28 x 28 mm low-profile quad flat package.
Figure 76. LQFP208 package outline
SEATING
PLANE
C
ccc
C
0.25 mm
GAUGE PLANE
K
L
D
L1
D1
D3
105
156
104
157
208
53
PIN 1
IDENTIFICATION
1
52
e
UH_ME_V2
1. Drawing is not to scale.
238/252
DS12919 Rev 1
STM32H755xI
Package information
Table 130. LQFP208 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
29.800
27.800
-
-
1.600
0.150
1.450
0.270
0.200
30.200
28.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
1.1890
1.1102
-
-
0.0020
0.0531
0.0067
0.0035
1.1811
1.1024
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
30.000
28.000
25.500
30.000
28.000
25.500
0.500
0.600
1.000
3.5°
1.1732
1.0945
1.0039
1.1732
1.0945
1.0039
0.0197
0.0236
0.0394
3.5°
D1
D3
E
29.800
27.800
-
30.200
28.200
-
1.1811
1.1024
-
1.1890
1.1102
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS12919 Rev 1
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250
Package information
STM32H755xI
Figure 77. LQFP208 package recommended footprint
208
157
0.5
1
156
52
105
1.2
53
104
25.8
30.7
UH_FP_V2
1. Dimensions are expressed in millimeters.
240/252
DS12919 Rev 1
STM32H755xI
Package information
Device marking for LQFP208
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 78. LQFP208 marking example (package top view)
Revision code
R
Product identification(1)
STM32H755BIT6
Y WW
Date code
Pin 1 identifier
MSv50644V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12919 Rev 1
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250
Package information
STM32H755xI
7.4
UFBGA176+25 package information
UFBGA176+25 is a 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package.
Figure 79. UFBGA176+25 package outline
Seating plane
C
A4
ddd
C
A
A3
A1
Z
A2
b
A1 ball
index
area
A
A1 ball
identifier
E
E1
e
Z
A
D1
D
e
B
R
15
1
Øb (176 + 25 balls)
BOTTOM VIEW
TOP VIEW
Ø eee M
Ø fff
C
C
A B
M
A0E7_ME_V8
1. Drawing is not to scale.
Table 131. UFBGA176+25 package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
-
-
0.600
-
-
0.0236
-
-
0.110
-
-
0.0043
-
0.130
0.450
0.320
0.290
10.000
9.100
10.000
9.100
0.650
0.450
-
-
-
0.0051
0.0177
0.0126
0.0114
0.3937
0.3583
0.3937
0.3583
0.0256
0.0177
-
-
-
-
-
-
-
-
-
-
0.240
0.340
0.0094
0.0134
D
9.850
10.150
0.3878
0.3996
D1
E
-
-
-
-
9.850
10.150
0.3878
0.3996
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
Z
-
ddd
0.080
0.0031
242/252
DS12919 Rev 1
STM32H755xI
Package information
Table 131. UFBGA176+25 package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
eee
fff
-
-
-
-
0.150
0.050
-
-
-
-
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 80. UFBGA176+25 package recommended footprint
Dpad
Dsm
A0E7_FP_V1
Table 132. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.65 mm
0.300 mm
0.400 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.300 mm
Between 0.100 mm and 0.125 mm
0.100 mm
DS12919 Rev 1
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250
Package information
STM32H755xI
Device marking for UFBGA176+25
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 81. UFBGA176+25 marking example (package top view)
STM32H755
Product identification(1)
Revision code
IIK6
R
Date code
Y
WW
Ball 1 identifier
MSv50644V2
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
244/252
DS12919 Rev 1
STM32H755xI
Package information
7.5
TFBGA240+25 package information
TFBGA240+25 is a 265 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array
package.
Figure 82. TFBGA240+25 package outline
SEATING
PLANE
C
A1 ball identifier
D
D1
e
A
e
S
1
17
F
b (240 + 25 balls)
BOTTOM VIEW
TOP VIEW
A07U_ME_V1
1. Dimensions are expressed in millimeters.
DS12919 Rev 1
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Package information
STM32H755xI
Table 133. TFBG240+25 ball package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.100
-
-
0.0433
0.150
-
-
0.0059
-
-
-
0.760
0.400
14.000
12.800
14.000
12.800
0.800
0.600
0.600
-
-
-
0.0299
0.0157
0.5512
0.5039
0.5512
0.5039
0.0315
0.0236
0.0236
-
-
0.350
0.450
0.0138
0.0177
D
13.850
14.150
0.5453
0.5571
D1
E
-
-
-
-
13.850
14.150
0.5453
0.5571
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
-
G
-
-
ddd
eee
fff
0.100
0.150
0.080
0.0039
0.0059
0.0031
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 83. TFBGA240+25 package recommended footprint
Dpad
Dsm
A07U_FP_V2
1. Dimensions are expressed in millimeters.
246/252
DS12919 Rev 1
STM32H755xI
Package information
Table 134. TFBGA240+25 recommended PCB design rules (0.8 mm pitch)
Dimension Recommended values
Pitch
0.8 mm
Dpad
Dsm
0.225 mm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
Device marking for TFBGA240+25
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 84. TFBGA240+25 marking example (package top view)
Product
identification(1)
STM32H755XIH6
Revision code
R
Date code
Ball
A1identifier
Y WW
MSv61380V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12919 Rev 1
247/252
250
Package information
STM32H755xI
7.6
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in ° C,
A
Θ
is the package junction-to-ambient thermal resistance, in ° C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 135. Thermal characteristics
Parameter
Symbol
Definition
Value
Unit
Thermal resistance junction-ambient
43.7
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
43.0
42.4
37.4
36.6
11.3
11.2
11.1
23.9
7.4
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-ambient
Θ
°C/W
JA
LQFP208 - 28 x 28 mm /0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-case
Θ
°C/W
JC
LQFP208 - 28 x 28 mm /0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
248/252
DS12919 Rev 1
STM32H755xI
Package information
Table 135. Thermal characteristics
Parameter
Symbol
Definition
Value
Unit
Thermal resistance junction-ambient
38.3
LQFP144 - 20 x 20 mm /0.5 mm pitch
Thermal resistance junction-ambient
39.4
40.3
19.3
24.3
LQFP176 - 24 x 24 mm /0.5 mm pitch
Thermal resistance junction-ambient
Thermal resistance
junction-board
Θ
°C/W
JB
LQFP208 - 28 x 28 mm /0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
7.6.1
Reference document
•
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
•
For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available from www.st.com.
DS12919 Rev 1
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250
Ordering information
STM32H755xI
8
Ordering information
Example:
STM32 H
755
X
I
T
6
TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
755 = STM32H7x5 High performance and industrial line
with cryptographic accelerator
Pin count
Z = 144 pins
I = 176 pins/balls
B = 208 pins
X = 240 balls
Flash memory size
I = 2 Mbytes
Package
T = LQFP ECOPACK®2
K = UFBGA pitch 0.65 mm ECOPACK®2
H = TFBGA ECOPACK®2
Temperature range
3 = Extended temperature range: –40 to 125 °C
6 = –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
250/252
DS12919 Rev 1
STM32H755xI
Revision history
9
Revision history
Table 136. Document revision history
Date
Revision
Changes
16-May-2019
1
Initial release.
DS12919 Rev 1
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251
STM32H755xI
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
252/252
DS12919 Rev 1
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