STM32L021F4T3DTR [STMICROELECTRONICS]
Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AES;
| 型号： | STM32L021F4T3DTR |
| 厂家： | 
ST |
| 描述： | Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AES 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 静态存储器 |
| 文件： | 总114页 (文件大小：1618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32L021D4 STM32L021F4
STM32L021G4 STM32L021K4
®
Access line ultra-low-power 32-bit MCU Arm -based
®
Cortex -M0+, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AES
Datasheet - production data
Features
•
Ultra-low-power platform
–
–
–
–
–
1.65 V to 3.6 V power supply
-40 to 125 °C temperature range
0.23 µA Standby mode (2 wakeup pins)
0.29 µA Stop mode (16 wakeup lines)
0.54 µA Stop mode + RTC + 2 KB RAM
retention
TSSOP14/20
169 mils
LQFP32
7x7 mm
UFQFPN20 3x3 mm
UFQFPN28 4x4 mm
UFQFPN32 5x5 mm
•
•
Rich Analog peripherals
–
12-bit ADC 1.14 Msps up to 10 channels (down
to 1.65 V)
–
–
–
Down to 76 µA/MHz in Run mode
5 µs wakeup time (from Flash memory)
41 µA 12-bit ADC conversion at 10 ksps
–
2x ultra-low-power comparators (window mode
and wake up capability, down to 1.65 V)
®
®
5-channel DMA controller, supporting ADC, SPI,
I2C, USART, Timers, AES
•
•
Core: Arm 32-bit Cortex -M0+
–
–
From 32 kHz to 32 MHz max.
0.95 DMIPS/MHz
Reset and supply management
Ultra-safe, low-power BOR (brownout reset)
with 5 selectable thresholds
Ultralow power POR/PDR
•
•
•
•
•
4x peripherals communication interface
1x USART (ISO 7816, IrDA), 1x UART (low power)
1x SPI 16 Mbits/s
–
1x I2C (SMBus/PMBus)
–
–
Programmable voltage detector (PVD)
7x timers: 1x 16-bit with up to 4 channels, 1x 16-bit
with up to 2 channels, 1x 16-bit ultra-low-power
timer, 1x SysTick, 1x RTC and 2x watchdogs
(independent/window)
•
Clock sources
–
–
–
0 to 32 MHz external clock
32 kHz oscillator for RTC with calibration
High speed internal 16 MHz factory-trimmed RC
(+/- 1%)
Internal low-power 37 kHz RC
•
CRC calculation unit, 96-bit unique ID
• Hardware Encryption Engine AES 128-bit
•
–
–
®
All packages are ECOPACK 2
Internal multispeed low-power 65 kHz to
4.2 MHz RC
–
PLL for CPU clock
•
•
Pre-programmed bootloader
USART, SPI supported
Development support
Serial wire debug supported
–
–
•
•
Up to 28 fast I/Os (23 I/Os 5V tolerant)
Memories
–
–
–
–
16 KB Flash memory with ECC
2 KB RAM
512 B of data EEPROM with ECC
20-byte backup register
–
Sector protection against R/W operation
–
September 2017
DocID027982 Rev 5
1/114
This is information on a product in full production.
www.st.com
Contents
STM32L021x4
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
3.2
3.3
3.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Arm® Cortex®-M0+ core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
3.4.2
3.4.3
3.4.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
3.6
3.7
3.8
3.9
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 24
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.1
Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REFINT
3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.13 System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.1 General-purpose timers (TIM2, TIM21) . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.2 Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 31
3.16.3 Low-power universal asynchronous receiver transmitter (LPUART) . . . 31
3.16.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.17 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 32
3.18 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4
5
6
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Embedded reset and power control block characteristics . . . . . . . . . . . 49
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Contents
STM32L021x4
6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.17 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.1
7.2
7.3
7.4
7.5
7.6
7.7
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
UFQFPN28 4 x 4 mm package information . . . . . . . . . . . . . . . . . . . . . . . 99
UFQFPN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.7.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Ultra-low-power STM32L021x4 device features and peripheral counts . . . . . . . . . . . . . . . 11
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Functionalities depending on the working mode
(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32L021x4 peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5.
Table 6.
Table 7.
Table 8.
2
STM32L021x4 I C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9.
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SPI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 49
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Current consumption in Run mode, code with data processing running from Flash. . . . . . 53
Current consumption in Run mode vs code type,
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current consumption in Run mode, code with data processing running from RAM . . . . . . 55
Current consumption in Run mode vs code type,
Table 23.
Table 24.
code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Current consumption in Low-power Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Current consumption in Low-power Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 59
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 60
Average current consumption during wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Peripheral current consumption in run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 62
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 71
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
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List of tables
STM32L021x4
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
R
max for f
= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
AIN
ADC
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
I2C frequency in all I2C modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP32 - 32-pin, 7 x 7 mm, 32-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
TSSOP14 – 14-lead thin shrink small outline, 5 x 4.4 mm, 0.65 mm pitch,
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
STM32L021x4 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 73.
Table 74.
Table 75.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32L021x4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32L021x4 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32L021x4 UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32L021x4 UFQFPN28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L021x4 UFQFPN20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L021x4 TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L021x4 TSSOP14 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 13. IDD vs VDD, at TA= 25 °C, Run mode, code running from
Flash memory, Range 2, 16 MHz HSE, 1WS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 14. IDD vs VDD, at TA= 25 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 15. IDD vs VDD, at TA= -40/25/55/ 85/105/125 °C, Low-power run mode,
code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . 58
Figure 16. IDD vs VDD, at TA= -40/25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. IDD vs VDD, at TA= -40/25/55/85/105/125 °C, Stop mode with RTC disabled,
all clocks OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21. HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 22. VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 23. VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 26. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
(1)
Figure 29. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
(1)
Figure 30. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 31. LQFP32 - 32-pin, 7 x 7 mm, 32-pin low-profile quad flat package outline . . . . . . . . . . . . . 94
Figure 32. LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 33. Example of LQFP32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 34. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 35. UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 36. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 37. UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 38. Example of UFQFPN28 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 39. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 40. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
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STM32L021x4
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 41. Example of UFQFPN20 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 42. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 43. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 44. TSSOP14 – 14-lead thin shrink small outline, 5.0 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 45. Example of TSSOP14 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 46. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Introduction
1
Introduction
The ultra-low-power STM32L021x4 family includes devices in 6 different package types
from 14 to 32 pins. The description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the ultra-low-power STM32L021x4 microcontrollers suitable for a wide
range of applications:
•
•
•
•
•
Gas/water meters and industrial sensors
Healthcare and fitness equipment
Remote control and user interface
PC peripherals, gaming, GPS equipment
Alarm system, wired and wireless sensors, video intercom
This STM32L021x4 datasheet should be read in conjunction with the STM32L0x1 reference
manual (RM0377).
®
For information on the Arm Cortex®-M0+ core please refer to the Cortex®-M0+ Technical
Reference Manual, available from the www.arm.com website.
Figure 1 shows the general block diagram of the device family.
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32
Description
STM32L021x4
2
Description
The access line ultra-low-power STM32L021x4 family incorporates the high-performance
Arm® Cortex®-M0+ 32-bit RISC core operating at a 32 MHz frequency, high-speed
embedded memories (16 Kbytes of Flash program memory, 512 bytes of data EEPROM and
2 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.
The STM32L021x4 devices provide high power efficiency for a wide range of performance.
It is achieved with a large choice of internal and external clock sources, an internal voltage
adaptation and several low-power modes.
The STM32L021x4 devices offer several analog features, one 12-bit ADC with hardware
oversampling, two ultra-low-power comparators, AES, several timers, one low-power timer
(LPTIM), three general-purpose 16-bit timers, one RTC and one SysTick which can be used
as timebases. They also feature two watchdogs, one watchdog with independent clock and
window capability and one window watchdog based on bus clock.
Moreover, the STM32L021x4 devices embed standard and advanced communication
interfaces: one I2C, one SPI, one USART, and a low-power UART (LPUART).
The STM32L021x4 also include a real-time clock and a set of backup registers that remain
powered in Standby mode.
The ultra-low-power STM32L021x4 devices operate from a 1.8 to 3.6 V power supply (down
to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR
option. They are available in the -40 to +125 °C temperature range. A comprehensive set of
power-saving modes allows the design of low-power applications.
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Description
2.1
Device overview
Table 1. Ultra-low-power STM32L021x4 device features and peripheral counts
Peripheral
STM32 L021D4 STM32 L021F4 STM32 L021G4 STM32L021K4
Flash (Kbytes)
16
512
2
Data EEPROM (bytes)
RAM (Kbytes)
AES
1
General-
purpose
2
1
Timers
LPTIM
RTC/SYSTICK/IWDG/
WWDG
1/1/1/1
SPI
I2C
1
1
1
1
Communication
interfaces
USART
LPUART
GPIOs
11
16
24
26/28(1)
Clocks: HSE(2)/LSE/HSI/MSI/LSI
1/1/1/1/1
12-bit synchronized ADC
Number of channels
1
4
1
1
10
7/9(3)
Comparators
2
Max. CPU frequency
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Operating voltage
Operating temperatures
Packages
Ambient temperature: –40 to +125 °C
Junction temperature: –40 to +130 °C
TSSOP20,
UFQFPN20
LQFP32,
UFQFPN32
TSSOP14
UFQFPN28
1. The devices feature 26 and 28 GPIOs on LQFP32 and UFQFPN32, respectively.
2. HSE available only as external clock input (HSE bypass).
3. The devices feature 7 and 9 ADC channels on UFQFPN20 and TSSOP20, respectively.
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32
Description
STM32L021x4
Figure 1. STM32L021x4 block diagram
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STM32L021x4
Description
2.2
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary
core up to Arm® Cortex®-M4, including Arm® Cortex®-M3 and Arm® Cortex®-M0+. The
STM32Lx series are the best choice to answer your needs in terms of ultra-low-power
features. The STM32 Ultra-low-power series are the best solution for applications such as
gas/water meter, keyboard/mouse or fitness and healthcare application. Several built-in
features like LCD drivers, dual-bank memory, low-power Run mode, operational amplifiers,
128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly
cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and
long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all
STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other
hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to
respond to the latest market feature and efficiency requirements.
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32
Functional overview
STM32L021x4
3
Functional overview
3.1
Low-power modes
The ultra-low-power STM32L021x4 supports dynamic voltage scaling to optimize its power
consumption in Run mode. The voltage from the internal low-drop regulator that supplies
the logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.
There are three power consumption ranges:
•
•
•
Range 1 (V range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz
DD
Range 2 (full V range), with a maximum CPU frequency of 16 MHz
DD
Range 3 (full V range), with a maximum CPU frequency limited to 4.2 MHz
DD
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the low-
speed clock (max 131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In Low-
power run mode, the clock frequency and the number of enabled peripherals are both
limited.
•
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the Run
mode with the regulator on.
Stop mode with RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the V
domain are stopped, the
CORE
PLL, MSI RC, HSE and HSI RC oscillators are disabled. The LSE or LSI is still running.
The voltage regulator is in the low-power mode.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the
processor can serve the interrupt or resume the code. The EXTI line source can be any
GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event
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Functional overview
(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup
events, the USART/I2C/LPUART/LPTIM wakeup events.
•
Stop mode without RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and
LSE crystal oscillator are disabled.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The voltage regulator is in the low-power mode. The device can be woken up from Stop
mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or
resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the
comparator 1 event or comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USART/I2C/LPUART/LPTIM wakeup events.
•
Standby mode with RTC
The Standby mode is used to achieve the lowest power consumption and real time
clock. The internal voltage regulator is switched off so that the entire V
domain is
CORE
powered off. The PLL, MSI RC, HSE bypass and HSI RC oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•
Standby mode without RTC
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire V
domain is powered off. The
CORE
PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillator are also switched off.
After entering Standby mode, the RAM and register contents are lost except for
registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz
oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
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32
Functional overview
STM32L021x4
Table 2. Functionalities depending on the operating power supply range
Functionalities depending on the operating power
supply range
Operating power supply range
Dynamic voltage scaling
ADC operation
range
ADC only, conversion time
up to 570 ksps
Range 2 or
range 3
VDD = 1.65 to 1.71 V
VDD = 1.71 to 1.8 V(1)
VDD = 1.8 to 2.0 V(1)
ADC only, conversion time
up to 1.14 Msps
Range 1, range 2 or range 3
Range1, range 2 or range 3
Conversion time up to 1.14
Msps
Conversion time up to 1.14
Msps
V
DD = 2.0 to 2.4 V
Range 1, range 2 or range 3
Range 1, range 2 or range 3
Conversion time up to 1.14
Msps
VDD = 2.4 to 3.6 V
1. CPU frequency changes from initial to final must respect the condition: fCPU initial <4fCPU initial. It must also
respect 5 μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch
from 4.2 MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.
Table 3. CPU frequency range depending on dynamic voltage scaling
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
Range 2
Range 3
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
32 kHz to 4.2 MHz (0ws)
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Functional overview
Table 4. Functionalities depending on the working mode
(1)(2)
(from Run/active down to standby)
Stop
Standby
Low-
power
run
Low-
power
sleep
IPs
Run/Active
Sleep
Wakeup
capability
Wakeup
capability
CPU
Y
O
Y
Y
O
-
Y
O
Y
Y
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Flash memory
RAM
O
Y
Y
O
O
Y
Y
O
Y
Y
-
-
Backup registers
EEPROM
Y
-
Brown-out reset
(BOR)
O
O
O
O
O
O
O
O
O
-
O
-
O
-
O
-
DMA
Programmable
Voltage Detector
(PVD)
O
O
O
O
O
O
-
-
Power-on/down
reset (POR/PDR)
Y
O
O
O
O
O
Y
Y
O
O
O
O
O
Y
Y
-
Y
-
Y
Y
-
Y
-
Y
-
High Speed
Internal (HSI)
(3)
High Speed
External (HSE)
O
O
O
Y
Y
O
O
O
Y
Y
-
-
-
-
Low Speed Internal
(LSI)
O
O
-
-
O
O
-
-
Low Speed
External (LSE)
-
-
Multi-Speed
Internal (MSI)
-
-
Inter-Connect
Controller
Y
-
-
-
RTC
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
RTC Tamper
O
Auto WakeUp
(AWU)
O
O
O
O
O
-
O
O
USART
LPUART
SPI
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
O
O
O
O
-
O(4)
O(4)
-
O
O
-
-
-
-
-
-
-
-
-
-
I2C
O(5)
O
-
ADC
-
Temperature
sensor
O
O
O
O
O
-
-
-
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32
Functional overview
STM32L021x4
Standby
Table 4. Functionalities depending on the working mode
(1)(2)
(from Run/active down to standby) (continued)
Stop
Low-
power
run
Low-
power
sleep
IPs
Run/Active
Sleep
Wakeup
capability
Wakeup
capability
Comparators
16-bit timers
LPTIM
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
O
-
-
-
-
-
O
O
-
O
O
-
-
-
IWDG
O
-
O
WWDG
-
-
SysTick Timer
GPIOs
-
-
-
O
O
-
2 pins
Wakeup time to
Run mode
7 CPU
cycles
0 µs
6 CPU cycles
3 µs
5 µs
65 µs
0.29 µA (No
0.18 µA (No
RTC) VDD=1.8 V RTC) VDD=1.8 V
0.54 µA (with 0.41 µA (with
RTC) VDD=1.8 V RTC) VDD=1.8 V
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to
128 µA/MHz
(from Flash)
Down to
31 µA/MHz
(from Flash)
Down to Down to
7 µA 3.8 µA
0.34 µA (No
0.23 µA (No
RTC) VDD=3.0 V RTC) VDD=3.0 V
0.67 µA (with 0.53 µA (with
RTC) VDD=3.0 V RTC) VDD=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional, can be enabled/disabled by software)
“-” = Not available
2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes.
3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
4. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start.To generate a wakeup on
address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep running
the HSI clock.
5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.
3.2
Interconnect matrix
Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.
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Table 5. STM32L021x4 peripherals interconnect matrix
Low-
Low-
Run Sleep power power Stop
Interconnect Interconnect
Interconnect action
source
destination
run
sleep
Timer input channel,
trigger from analog
signals comparison
TIM2,TIM21
Y
Y
Y
Y
Y
Y
-
COMPx
Timer input channel,
trigger from analog
signals comparison
LPTIM1
Y
Y
Y
Timer triggered by other
timer
TIMx
RTC
TIMx
TIM21
LPTIM1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Timer triggered by Auto
wake-up
Timer triggered by RTC
event
Y
Clock source used as
input channel for RC
measurement and
trimming
All clock
source
TIMx
TIMx
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Timer input channel and
trigger
GPIO
Timer input channel and
trigger
LPTIM1
ADC
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Conversion trigger
3.3
Arm® Cortex®-M0+ core
The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:
•
•
•
•
•
•
a simple architecture that is easy to learn and program
ultra-low power, energy-efficient operation
excellent code density
deterministic, high-performance interrupt handling
upward compatibility with Cortex-M processor family
platform security robustness.
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-
bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded Arm core, the STM32L021x4 are compatible with all Arm tools and
software.
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32
Functional overview
STM32L021x4
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L021x4 embed a nested vectored interrupt controller able to
handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
•
•
•
includes a Non-Maskable Interrupt (NMI)
provides zero jitter interrupt option
provides four interrupt priority levels
The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart load-
multiple and store-multiple operations. Interrupt handlers do not require any assembler
wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also
significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to enter rapidly stop or standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.4
Reset and supply management
3.4.1
Power supply schemes
•
V
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
DD
externally through V pins.
DD
•
V
, V
= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
SSA DDA
and PLL. V
and V
must be connected to V and V , respectively. On
SSA DD SS
DDA
TSSOP14 package, V
is internally connected to V
.
DDA
DD
3.4.2
Power supply supervisor
The devices feature an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
Two versions are available:
•
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
The other version without BOR operates between 1.65 V and 3.6 V.
After the V threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
DD
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on V at least 1 ms after it exits
DD
the POR area.
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Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V ) in Stop mode. The device remains in reset mode when
REFINT
V
is below a specified threshold, V
or V
, without the need for any external
DD
POR/PDR
BOR
reset circuit.
Note:
3.4.3
3.4.4
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The devices feature an embedded programmable voltage detector (PVD) that monitors the
V
power supply and compares it to the V
threshold. This PVD offers 7 different
DD/VDDA
PVD
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V drops below the V threshold and/or when
DD/VDDA
PVD
V
is higher than the V
threshold. The interrupt service routine can then generate
DD/VDDA
PVD
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
•
•
•
MR is used in Run mode (nominal regulation)
LPR is used in the Low-power run, Low-power sleep and Stop modes
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).
Boot modes
At startup, BOOT0 pin and nBOOT0, nBOOT1 and nBOOT_SEL option bits are used to
select one of three boot options:
•
•
•
Boot from Flash memory
Boot from System memory
Boot from embedded RAM
The bootloader is located in System memory. It is used to reprogram the Flash memory by
using SPI1 (PA4, PA7, PA13 and PA14 on TSSOP14 package or PA4, PA5, PA6 and PA7
on other packages) or USART2 (PA2, PA3 and PA9, PA10).
If the bootloader is activated (the bootloader is active on all empty devices due to the empty
check mechanism), then the above mentioned bits are configured depending on whether
SPI1 or USART2 functionality is used.
See STM32™ microcontroller system memory boot mode AN2606 for details.
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32
Functional overview
STM32L021x4
3.5
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
•
•
•
Clock prescaler
To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.
Safe clock switching
Clock sources can be changed safely on the fly in Run mode through a configuration
register.
Clock management
To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.
System clock source
Three different clock sources can be used to drive the master clock SYSCLK:
–
–
0-32 MHz high-speed external (HSE bypass), that can supply a PLL
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
•
Auxiliary clock source
Two ultra-low-power clock sources that can be used to drive the real-time clock:
–
–
32.768 kHz low-speed external crystal (LSE)
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
•
•
RTC clock sources
The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system
clock.
Startup clock
After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.
•
•
Clock security system (CSS)
This feature can be enabled by software. If an LSE clock failure occurs, it provides an
interrupt or wakeup event which is generated assuming it has been previously enabled.
This feature is not available on the HSE clock.
Clock-out capability (MCO: microcontroller clock output)
It outputs one of the internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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Figure 2. Clock tree
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Functional overview
STM32L021x4
3.6
Low-power real-time clock and backup registers
The real time clock (RTC) and the 5 backup registers are supplied in all modes including
standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
•
•
•
•
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
Two programmable alarms with wake up from Stop and Standby mode capability
Periodic wakeup from Stop and Standby with programmable resolution and period
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 37 kHz)
The high-speed external clock
3.7
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.
The BOOT0 pin is shared with PB9 GPIO pin. This pin is an input-only pin. If nBOOT_SEL
option bit is reset, sampling this pin on NRST rising edge gives the internal BOOT0 state.
This pin then works as PB9 pin. The input voltage characteristics of this pin are specific for
BOOT0 pin type (see Table 49: I/O static characteristics).
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 26 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
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(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 38 GPIOs can be connected
to the 16 configurable interrupt/event lines. The 10 other lines are connected to PVD, RTC,
USART, I2C, LPUART, LPTIM or comparator events.
3.8
Memories
The STM32L021x4 devices have the following features:
•
2 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
–
–
16 Kbytes of embedded Flash program memory
512 bytes of data EEPROM
Information block containing 32 user and factory options bytes plus 4 Kbytes of
system memory
The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:
•
•
Level 0: no protection
Level 1: memory readout protected.
The Flash memory cannot be read from or written to if either debug features are
connected or boot in RAM is selected
•
Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.9
Direct memory access (DMA)
The flexible 5-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
2
The DMA can be used with the main peripherals: AES, SPI, I C, USART, LPUART,
general-purpose timers, and ADC.
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Functional overview
STM32L021x4
3.10
Analog-to-digital converter (ADC)
A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into STM32L021x4 devices. It has up to 10 external channels and 2
internal channels (temperature sensor, voltage reference). Three channels, PA0, PA4 and
PA5, are fast channels, while the others are standard channels.
The ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all
frequencies (~25 µA at 10 kSPS, ~200 µA at 1MSPS). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate from a supply voltage down to
1.65 V.
The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits (see AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
3.11
Temperature sensor
The temperature sensor (T
temperature.
) generates a voltage V
that varies linearly with
SENSE
SENSE
The temperature sensor is internally connected to the ADC_IN18 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode (see Table 56:
Temperature sensor calibration values).
3.11.1
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC and Comparators. V
is internally connected to the ADC_IN17 input channel. It
REFINT
enables accurate monitoring of the V value (since no external voltage, V
, is available
DD
REF+
for ADC). The precise voltage of V
is individually measured for each part by ST during
REFINT
production test and stored in the system memory area (see Table 19: Embedded internal
reference voltage calibration values). It is accessible in read-only mode.
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Functional overview
3.12
Ultra-low-power comparators and reference voltage
The STM32L021x4 embed two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
•
•
•
One comparator with ultra low consumption
One comparator with rail-to-rail inputs, fast or slow mode.
The threshold can be one of the following:
–
–
–
External I/O pins
Internal reference voltage (V
)
REFINT
submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail
comparator.
Both comparators can wake up the devices from Stop mode, and be combined into a
window comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
3.13
3.14
System configuration controller
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM21 and LPTIM1 timer input captures. It also controls the
routing of internal analog signals to the ADC, COMP1 and COMP2 and the internal
reference voltage V
.
REFINT
AES
The AES Hardware Accelerator can be used to encrypt and decrypt data using the AES
algorithm (compatible with FIPS PUB 197, 2001 Nov 26):
•
•
•
•
•
•
Key scheduler
Key derivation for decryption
128-bit data block processed
128-bit key length
213 clock cycles to encrypt/decrypt one 128-bit block
Electronic codebook (ECB), cypher block chaining (CBC), and counter mode (CTR)
supported by hardware.
The AES can be served by the DMA controller.
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Functional overview
STM32L021x4
3.15
Timers and watchdogs
The ultra-low-power STM32L021x4 devices include two general-purpose timers, one low-
power timer (LPTIM1), two watchdog timers and the SysTick timer.
Table 6 compares the features of the general-purpose and basic timers.
Table 6. Timer feature comparison
DMA
Counter
resolution
Capture/compare Complementary
Timer
Counter type
Prescaler factor
request
channels
outputs
generation
Up, down,
up/down
Any integer between
1 and 65536
TIM2
16-bit
16-bit
Yes
No
4
2
No
No
Up, down,
up/down
Any integer between
1 and 65536
TIM21
3.15.1
General-purpose timers (TIM2, TIM21)
There are three synchronizable general-purpose timers embedded in the STM32L021x4
devices (see Table 6 for differences).
TIM2
TIM2 is based on 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It
features four independent channels each for input capture/output compare, PWM or one-
pulse mode output.
The TIM2 general-purpose timers can work together or with the TIM21 general-purpose
timer via the Timer Link feature for synchronization or event chaining. Its counter can be
frozen in debug mode. Any of the general-purpose timers can be used to generate PWM
outputs.
TIM2 has independent DMA request generation.
This timer is capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 3 hall-effect sensors.
TIM21
TIM21 is based on a 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It has
two independent channels for input capture/output compare, PWM or one-pulse mode
output. It can work together and be synchronized with TIM2 full-featured general-purpose
timer.
It can also be used as simple timebase and be clocked by the LSE clock source
(32.768 kHz) to provide independent timebase from the main CPU clock.
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Functional overview
3.15.2
Low-power Timer (LPTIM)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one shot mode
Selectable software / hardware input trigger
Selectable clock source
–
–
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM1 input (working even with no internal clock
source running, used by the Pulse Counter Application)
•
•
Programmable digital glitch filter
Encoder mode
3.15.3
3.15.4
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches ‘0’.
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
3.15.5
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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Functional overview
STM32L021x4
3.16
Communication interfaces
2
3.16.1
I C bus
2
2
One I C interface (I2C1) can operate in multimaster or slave modes. The I C interface can
support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to 400 kbit/s) and Fast
Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
2
The I C interface supports 7-bit and 10-bit addressing modes, multiple 7-bit slave
addresses (2 addresses, 1 with configurable mask). They also include programmable
analog and digital noise filters.
Table 7. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
≥ 50 ns
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Benefits
Available in Stop mode
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Variations depending on
temperature, voltage, process
Drawbacks
In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. I2C1 also has a clock domain independent from the CPU
clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.
The I2C interface can be served by the DMA controller.
Refer to Table 8 for the supported modes and features of I2C interface.
2
Table 8. STM32L021x4 I C implementation
I2C features(1)
I2C1
7-bit addressing mode
X
X
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
X
X
Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X(2)
Independent clock
SMBus
X
X
Wakeup from STOP
X
1. X = supported.
2. See Table 12: Pin definitions on page 36 for the list of I/Os that feature Fast Mode Plus capability
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Functional overview
3.16.2
Universal synchronous/asynchronous receiver transmitter (USART)
The USART interface (USART2) is able to communicate at speeds of up to 4 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 driver enable (DE) signals,
multiprocessor communication mode and single-wire half-duplex communication mode.
USART2 also supports Smartcard communication (ISO 7816, T=0 protocol) and IrDA SIR
ENDEC.
USART2 interface can be served by the DMA controller.
Table 9 for the supported modes and features of USART interface.
Table 9. USART implementation
USART modes/features(1)
USART2
Hardware flow control for modem
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
Smartcard mode
X
X
X
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
-
-
-
Auto baud rate detection (4 modes)
Driver Enable
-
X
1. X = supported.
3.16.3
Low-power universal asynchronous receiver transmitter (LPUART)
The devices embed one Low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wake up the
system from Stop mode, using baudrates up to 46 Kbaud. The Wakeup events from Stop
mode are programmable and can be:
•
•
•
Start bit detection
Or any received data frame
Or a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
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Functional overview
STM32L021x4
3.16.4
Serial peripheral interface (SPI)
The SPI is able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPI can be served by the DMA controller.
Refer to Table 10 for the supported modes and features of SPI interface.
Table 10. SPI implementation
SPI features(1)
SPI1
Hardware CRC calculation
I2S mode
X
-
TI mode
X
1. X = supported.
3.17
3.18
Cyclic redundancy check (CRC) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
Serial wire debug port (SW-DP)
An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.
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Pin descriptions
4
Pin descriptions
Figure 3. STM32L021x4 LQFP32 pinout
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1. The above figure shows the package top view.
DocID027982 Rev 5
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42
Pin descriptions
STM32L021x4
Figure 5. STM32L021x4 UFQFPN28 pinout
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Figure 6. STM32L021x4 UFQFPN20 pinout
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Pin descriptions
Figure 7. STM32L021x4 TSSOP20 pinout
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Figure 8. STM32L021x4 TSSOP14 pinout
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1. The above figure shows the package top view.
Table 11. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
FTf
TTa
TC
B
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
3.3 V tolerant I/O directly connected to the ADC
Standard 3.3V I/O
I/O structure
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
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Pin descriptions
STM32L021x4
Table 11. Legend/abbreviations used in the pinout table (continued)
Abbreviation Definition
Name
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Notes
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 12. Pin definitions
Pin functions
Pin number
Pin name
(function
Notes
Alternate functions Additional functions
after reset)
PC14-
OSC32_IN
2
3
1
2
2
3
2
3
2
3
2
3
I/O FT
-
-
-
-
OSC32_IN
PC15-
OSC32_OUT
I/O TC
I/O RST
OSC32_OUT
(2)
4
3
4
4
5
4
5
4
5
4
5
NRST
VDDA
-
-
-
-
(3)(4)
10
S
-
USART2_RX,
LPTIM1_IN1,
TIM2_CH1,
USART2_CTS,
TIM2_ETR,
COMP1_INM,
ADC_IN0,
RTC_TAMP2/WKUP1
/CK_IN
5
6
5
6
6
6
6
PA0-CK_IN
I/O TTa
-
LPUART1_RX,
COMP1_OUT
EVENTOUT,
LPTIM1_IN2,
TIM2_CH2,
COMP1_INP,
ADC_IN1
6
7
8
7
8
7
8
7
8
PA1
PA2
I/O FT
-
-
I2C1_SMBA,
USART2_RTS_DE,
TIM21_ETR,
LPUART1_TX
TIM21_CH1,
TIM2_CH3,
USART2_TX,
LPUART1_TX,
COMP2_OUT
COMP2_INM,
ADC_IN2,
RTC_TAMP3/RTC_T
S/RTC_OUT/WKUP3
-
-
I/O TTa
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Pin descriptions
Table 12. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function
Notes
Alternate functions Additional functions
after reset)
TIM21_CH2,
TIM2_CH4,
USART2_RX,
LPUART1_RX
COMP2_INP,
ADC_IN3
-
-
9
9
9
9
PA3
PA4
I/O FT
-
-
SPI1_NSS,
LPTIM1_IN1,
LPTIM1_ETR,
I2C1_SCL,
USART2_CK,
TIM2_ETR,
COMP1_INM,
COMP2_INM,
ADC_IN4
7
7
10 10 10 10
I/O TTa
LPUART1_TX,
COMP2_OUT
SPI1_SCK,
LPTIM1_IN2,
TIM2_ETR,
TIM2_CH1
COMP1_INM,
COMP2_INM,
ADC_IN5
-
-
8
9
11 11 11 11
PA5
PA6
I/O TTa
I/O FT
-
-
SPI1_MISO,
LPTIM1_ETR,
LPUART1_CTS,
EVENTOUT,
12 12 12 12
ADC_IN6
COMP1_OUT
SPI1_MOSI,
LPTIM1_OUT,
USART2_CTS,
TIM21_ETR,
EVENTOUT,
COMP2_OUT
COMP2_INP,
ADC_IN7
8
-
10 13 13 13 13
PA7
PB0
I/O FT
-
-
EVENTOUT,
SPI1_MISO,
TIM2_CH2,
ADC_IN8,
VREF_OUT
-
-
14 14 14
I/O FT
USART2_RTS_DE,
TIM2_CH3
USART2_CK,
SPI1_MOSI,
LPTIM1_IN1,
ADC_IN9,
VREF_OUT
-
-
11 14 15 15 15
PB1
PB2
I/O FT
I/O FT
-
-
LPUART1_RTS_DE,
TIM2_CH4
-
-
-
-
16
LPTIM1_OUT
-
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Pin descriptions
STM32L021x4
Table 12. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function
Notes
Alternate functions Additional functions
after reset)
(5)
(6)
9
12 15 16 16
-
VSS
VDD
S
S
-
-
-
-
-
-
10 13 16 17 17 17
MCO, LPTIM1_IN1,
EVENTOUT,
-
-
-
18 18 18
PA8
PA9
I/O FT
I/O FTf
-
-
-
-
USART2_CK,
TIM2_CH1
MCO, I2C1_SCL,
LPTIM1_OUT,
USART2_TX,
TIM21_CH2,
11 14 17 19 19 19
COMP1_OUT
TIM21_CH1,
I2C1_SDA,
RTC_REFIN,
USART2_RX,
TIM2_CH3,
(7)
12 15 18 20 20 20
PA10
I/O FTf
-
COMP1_OUT
SPI1_MISO,
LPTIM1_OUT,
EVENTOUT,
USART2_CTS,
TIM21_CH2,
COMP1_OUT
-
-
-
-
-
-
-
-
21 21
PA11
PA12
PA13
I/O FT
I/O FT
I/O FTf
-
-
-
-
-
-
SPI1_MOSI,
EVENTOUT,
USART2_RTS_DE,
COMP2_OUT
22 22
SWDIO,
LPTIM1_ETR,
I2C1_SDA,
13 16 19 21 23 23
SPI1_SCK,
LPUART1_RX,
COMP1_OUT
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Pin descriptions
Table 12. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function
Notes
Alternate functions Additional functions
after reset)
SWCLK,
LPTIM1_OUT,
I2C1_SMBA,
USART2_TX,
SPI1_MISO,
(7)
14 17 20 22 24 24
PA14
PA15
I/O FT
-
-
LPUART1_TX,
COMP2_OUT
SPI1_NSS,
TIM2_ETR,
EVENTOUT,
USART2_RX,
TIM2_CH1
-
-
-
23 25 25
I/O FT
-
SPI1_SCK,
TIM2_CH2,
EVENTOUT
-
-
-
-
-
-
24 26 26
25 27 27
PB3
PB4
I/O FT
I/O FT
-
-
COMP2_INM
COMP2_INP
SPI1_MISO,
EVENTOUT
SPI1_MOSI,
LPTIM1_IN1,
I2C1_SMBA,
TIM21_CH1
-
-
-
-
-
26 28 28
PB5
PB6
I/O FT
I/O FTf
-
-
COMP2_INP
COMP2_INP
USART2_TX,
I2C1_SCL,
LPTIM1_ETR,
TIM2_CH3,
18
27 29 29
LPUART1_TX
USART2_RX,
I2C1_SDA,
LPTIM1_IN2,
TIM2_CH4,
COMP2_INP,
VREF_PVD_IN
-
19
-
28 30 30
PB7
I/O FTf
-
LPUART1_RX
BOOT0 (Boot
memory selection)
1
-
20
-
1
-
1
-
31 31 PB9-BOOT0
I
B
-
-
-
USART2_TX,
EVENTOUT,
I2C1_SCL,
SPI1_NSS
-
32
PB8
I/O FTf
-
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42
Pin descriptions
STM32L021x4
Table 12. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function
Notes
Alternate functions Additional functions
after reset)
(4)
(5)
-
-
-
-
-
-
32
1
-
VSS
VDD
S
S
-
-
-
-
-
-
1
-
1. VSS pins are connected to the exposed pad (see Figure 34: UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine
pitch quad flat package outline).
2. Device reset input/internal reset output (active low).
3. Analog power supply.
4. On TSSOP14 package, VDDA is internally connected to VDD
5. Digital and analog ground.
.
6. Digital power supply.
7. PA14 pin on TSSOP14 package acts as an output pin when the embedded bootloader is active (SPI1_MISO). On empty
devices (devices from factory), the bootloader is active due to the empty check mechanism (refer to RM0377 reference
manual). PA14 pin also acts as SWCLK. When programming devices in TSSOP14 for the first time, it is necessary to use
the "connect under reset" method and the SWD interface to disable the bootloader by driving this PA14/SWCLK pin.
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Table 13. Alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/USART2/
TIM21/
EVENTOUT/
SYS_AF
LPUART1/
LPTIM/TIM2/
EVENTOUT/
SYS_AF
I2C1/USART2/L
PUART1/
EVENTOUT
Ports
SPI1/I2C1/
LPTIM
I2C1/LPTIM/
EVENTOUT
LPUART1/EVE
VENTOUT
SPI1/TIM2/21
COMP1/2
PA0
USART2_RX
EVENTOUT
LPTIM1_IN1
LPTIM1_IN2
TIM2_CH1
TIM2_CH2
-
USART2_CTS
TIM2_ETR
LPUART1_RX COMP1_OUT
LPUART1_TX
USART2_RTS_
DE
PA1
I2C1_SMBA
TIM21_ETR
-
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
TIM21_CH1
TIM21_CH2
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
MCO
-
TIM2_CH3
TIM2_CH4
LPTIM1_ETR
TIM2_ETR
-
-
USART2_TX
USART2_RX
USART2_CK
-
-
LPUART1_TX COMP2_OUT
LPUART1_RX
LPUART1_TX COMP2_OUT
-
-
-
-
LPTIM1_IN1
LPTIM1_IN2
LPTIM1_ETR
LPTIM1_OUT
-
I2C1_SCL
TIM2_ETR
TIM2_CH1
-
-
-
-
-
LPUART1_CTS
USART2_CTS
USART2_CK
USART2_TX
USART2_RX
USART2_CTS
EVENTOUT
COMP1_OUT
COMP2_OUT
-
-
-
TIM21_ETR
TIM2_CH1
TIM21_CH2
TIM2_CH3
TIM21_CH2
EVENTOUT
Port A
LPTIM1_IN1
LPTIM1_OUT
RTC_REFIN
EVENTOUT
EVENTOUT
-
-
-
-
MCO
I2C1_SCL
I2C1_SDA
LPTIM1_OUT
-
-
-
COMP1_OUT
COMP1_OUT
COMP1_OUT
TIM21_CH1
SPI1_MISO
USART2_RTS_
DE
PA12
SPI1_MOSI
-
EVENTOUT
-
-
-
COMP2_OUT
PA13
PA14
PA15
SWDIO
SWCLK
LPTIM1_ETR
-
I2C1_SDA
I2C1_SMBA
EVENTOUT
-
SPI1_SCK
SPI1_MISO
TIM2_CH1
LPUART1_RX COMP1_OUT
LPUART1_TX COMP2_OUT
LPTIM1_OUT
-
-
USART2_TX
USART2_RX
SPI1_NSS
TIM2_ETR
-
-
Table 13. Alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/USART2/
TIM21/
EVENTOUT/
SYS_AF
LPUART1/
LPTIM/TIM2/
EVENTOUT/
SYS_AF
I2C1/USART2/L
PUART1/
EVENTOUT
Ports
SPI1/I2C1/
LPTIM
I2C1/LPTIM/
EVENTOUT
LPUART1/EVE
VENTOUT
SPI1/TIM2/21
COMP1/2
USART2_RTS_
DE
PB0
EVENTOUT
USART2_CK
SPI1_MISO
SPI1_MOSI
TIM2_CH2
-
-
TIM2_CH3
TIM2_CH4
-
-
-
-
LPUART1_RTS_
DE
PB1
LPTIM1_IN1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PC14
PC15
-
-
LPTIM1_OUT
TIM2_CH2
EVENTOUT
LPTIM1_IN1
LPTIM1_ETR
LPTIM1_IN2
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI1_SCK
SPI1_MISO
SPI1_MOSI
USART2_TX
USART2_RX
USART2_TX
-
-
-
EVENTOUT
-
-
Port B
-
-
-
-
-
-
I2C1_SMBA
-
TIM21_CH1
-
I2C1_SCL
-
-
-
-
-
-
-
TIM2_CH3
LPUART1_TX
I2C1_SDA
-
TIM2_CH4
LPUART1_RX
-
-
-
-
I2C1_SCL
SPI1_NSS
-
-
-
-
-
-
-
-
-
-
-
-
Port C
-
-
STM32L021x4
Memory mapping
5
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
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43
Electrical characteristics
STM32L021x4
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.6 V (for the
A
DD
1.65 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9. Pin loading conditions
Figure 10. Pin input voltage
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STM32L021x4
Electrical characteristics
6.1.6
Power supply scheme
Figure 11. Power supply scheme
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1. On TSSOP14 package, VDDA is internally connected to VDD
2. VSSA is internally connected to VSS on all packages.
.
6.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
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DocID027982 Rev 5
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93
Electrical characteristics
STM32L021x4
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics, and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are
available on demand.
Table 14. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage
VDD–VSS
–0.3
4.0
(1)
(including VDDA, VDD
)
Input voltage on FT and FTf pins
Input voltage on TC pins
VSS −0.3
VSS −0.3
VSS
VDD+4.0
4.0
V
(2)
VIN
Input voltage on BOOT0
VDD +4.0
4.0
Input voltage on any other pin
Variations between different VDDx power pins
VSS −0.3
-
|ΔVDD
|VDDA-VDDx
|ΔVSS
VESD(HBM)
|
50
mV
Variations between any VDDx and VDDA power
pins(3)
|
-
-
300
50
|
Variations between all different ground pins
Electrostatic discharge voltage
(human body model)
see Section 6.3.11
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 15 for maximum allowed injected current values.
3. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and device operation. its value does not need to
respect this rule.
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Electrical characteristics
Table 15. Current characteristics
Ratings
Symbol
Max.
Unit
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
105
105
100
100
(2)
ΣIVDD
(2)
ΣIVSS
IVDD(PIN)
IVSS(PIN)
Output current sunk by any I/O and control pin except FTf
pins
16
IIO
Output current sunk by FTf pins
22
Output current sourced by any I/O and control pin
-16
Total output current sunk by sum of all IOs and control
pins(4)
45
-45
90
mA
(3)
ΣIIO(PIN)
Total output current sourced by sum of all IOs and control
pins
Total output current sunk by sum of all IOs and control
pins(2)
ΣIIO(PIN)
Total output current sourced by sum of all IOs and control
pins(2)
-90
Injected current on FT, FFf, RST and B pins
-5/+0(5)
± 5(6)
± 25
IINJ(PIN)
Injected current on TC pin
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(7)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. These values apply only to STM32L021GxUx part number (UFQFPN28 package).
4. This current consumption must be correctly distributed over all I/Os and control pins. In particular, it must
be located the closest possible to the couple of supply and ground, and distributed on both sides.
5. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 14 for maximum allowed input voltage values.
6. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 14: Voltage characteristics for the maximum allowed input voltage
values.
7. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 16. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
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Electrical characteristics
STM32L021x4
6.3
Operating conditions
6.3.1
General operating conditions
Table 17. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK1
fPCLK2
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
-
0
0
32
32
32
3.6
-
MHz
-
0
BOR detector disabled
1.65
BOR detector enabled,
at power on
1.8
3.6
3.6
3.6
VDD
Standard operating voltage
V
BOR detector disabled,
after power on
1.65
1.65
Analog operating voltage
(all features)
Must be the same voltage
VDDA
V
V
(1)
as VDD
2.0 V ≤ VDD ≤3.6 V
1.65 V ≤ VDD ≤2.0 V
-
-0.3
5.5
5.2
Input voltage on FT, FTf and RST pins(2)
-0.3
VIN
Input voltage on BOOT0 pin
Input voltage on TC pin
0
5.5
-
-0.3
VDD+0.3
333
513
206
270
196
210
83
LQFP32 package
UFQFPN32 package
UFQFPN28 package
TSSOP20 package
UFQFPN20 package
TSSOP14 package
LQFP32 package
UFQFPN32 package
UFQFPN28 package
TSSOP20 package
UFQFPN20 package
TSSOP14 package
-
-
-
-
-
-
-
-
-
-
-
-
Power dissipation at TA = 85 °C (range 6)
or TA =105 °C (rage 7) (3)
PD
mW
128
52
Power dissipation at TA = 125 °C (range
3) (3)
67
49
53
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Symbol
Electrical characteristics
Table 17. General operating conditions (continued)
Parameter
Conditions
Min
Max
Unit
Maximum power
dissipation (range 6)
–40
85
Maximum power
dissipation (range 7)
TA
TJ
Temperature range
–40
–40
105
125
Maximum power
dissipation (range 3)
°C
Junction temperature range (range 6)
Junction temperature range (range 7)
Junction temperature range (range 3)
-40 °C ≤ TA ≤ 85 °
–40
–40
–40
105
125
130
-40 °C ≤ TA ≤ 105 °C
-40 °C ≤ TA ≤ 125 °C
1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
DDA can be tolerated during power-up and normal operation.
V
2. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 16: Thermal characteristics
on page 47).
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 17.
Table 18. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
BOR detector enabled
BOR detector disabled
BOR detector enabled
BOR detector disabled
0
0
-
-
∞
VDD rise time rate
1000
µs/V
∞
(1)
tVDD
20
0
-
VDD fall time rate
-
1000
V
DD rising, BOR enabled
-
2
3.3
ms
1.6
(1)
TRSTTEMPO
Reset temporization
VDD rising, BOR disabled(2)
0.4
1
0.7
1.5
1.5
1.7
Falling edge
1.65
1.65
1.74
Power on/power down reset
threshold
VPOR/PDR
Rising edge
1.3
1.67
Falling edge
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Rising edge
1.69 1.76
1.8
V
Falling edge
1.87 1.93 1.97
1.96 2.03 2.07
2.22 2.30 2.35
2.31 2.41 2.44
VBOR1
Rising edge
Falling edge
VBOR2
Rising edge
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Electrical characteristics
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Table 18. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Falling edge
Min
Typ
Max Unit
2.45 2.55
2.54 2.66
2.6
2.7
VBOR3
Brown-out reset threshold 3
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
BOR0 threshold
2.68
2.78
1.8
2.8
2.9
2.85
2.95
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Brown-out reset threshold 4
1.85 1.88
Programmable voltage detector
threshold 0
1.88 1.94 1.99
1.98 2.04 2.09
2.08 2.14 2.18
2.20 2.24 2.28
2.28 2.34 2.38
2.39 2.44 2.48
2.47 2.54 2.58
2.57 2.64 2.69
2.68 2.74 2.79
2.77 2.83 2.88
2.87 2.94 2.99
2.97 3.05 3.09
3.08 3.15 3.20
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
V
-
-
40
-
-
Vhyst
Hysteresis voltage
mV
All BOR and PVD thresholds
excepting BOR0
100
1. Guaranteed by characterization results, not tested in production.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.
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6.3.3
Embedded internal reference voltage
The parameters given in Table 20 are based on characterization results, unless otherwise
specified.
Table 19. Embedded internal reference voltage calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 25°C
VREFINT_CAL
0x1FF8 0078 - 0x1FF8 0079
VDDA= 3 V
(1)
Table 20. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(2)
VREFINT out
Internal reference voltage
– 40 °C < TJ < +125 °C 1.202
1.224
2
1.242
3
V
TVREFINT
Internal reference startup time
-
-
-
ms
VDDA voltage during VREFINT
factory measure
VVREF_MEAS
2.99
3
-
3.01
±5
V
Including uncertainties
due to ADC and VDDA
values
Accuracy of factory-measured
VREFINT value(3)
AVREF_MEAS
-
mV
–40 °C < TJ < +125 °C
0 °C < TJ < +50 °C
-
-
-
-
25
-
100
20
(4)
TCoeff
Temperature coefficient
ppm/°C
(4)
ACoeff
Long-term stability
Voltage coefficient
1000 hours, T= 25 °C
3.0 V < VDDA < 3.6 V
-
1000
2000
ppm
(4)
VDDCoeff
-
ppm/V
ADC sampling time when
reading the internal reference
voltage
(4)(5)
TS_vrefint
-
5
10
-
µs
Startup time of reference
voltage buffer for ADC
(4)
TADC_BUF
-
-
-
-
-
10
25
µs
Consumption of reference
voltage buffer for ADC
(4)
IBUF_ADC
13.5
µA
(4)
IVREF_OUT
VREF_OUT output current(6)
-
-
-
-
-
-
1
µA
pF
(4)
CVREF_OUT
VREF_OUT output load
50
Consumption of reference
voltage buffer for VREF_OUT
and COMP
(4)
ILPBUF
-
-
730
1200
nA
(4)
VREFINT_DIV1
VREFINT_DIV2
VREFINT_DIV3
1/4 reference voltage
1/2 reference voltage
3/4 reference voltage
-
-
-
24
49
74
25
50
75
26
51
76
%
(4)
(4)
VREFINT
1. Refer to Table 32: Peripheral current consumption in Stop and Standby mode for the value of the internal reference current
consumption (IREFINT).
2. Guaranteed by test in production.
3. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
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4. Guaranteed by design, not tested in production.
5. Shortest sampling time can be determined in the application by multiple iterations.
6. To guarantee less than 1% VREF_OUT deviation.
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified
otherwise.
The current consumption values are derived from the tests performed under ambient
temperature and V supply voltage conditions summarized in Table 17: General operating
DD
conditions unless otherwise specified.
The MCU is placed under the following conditions:
•
•
•
All I/O pins are configured in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time and prefetch is adjusted depending on f
and voltage range to provide the best CPU performance unless otherwise specified.
frequency
HCLK
•
•
When the peripherals are enabled f = f = f
APB1
APB2
APB
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used)
•
The HSE user clock is applied to CK_IN. It follows the characteristic specified in
Table 34: High-speed external user clock characteristics
•
•
For maximum current consumption V = V
= 3.6 V is applied to all supply pins
DD
DDA
For typical current consumption V = V
= 3.0 V is applied to all supply pins if not
DDA
DD
specified otherwise
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Table 21. Current consumption in Run mode, code with data processing running from Flash
Symbol
Parameter
Conditions
fHCLK
Typ
Max(1) Unit
1 MHz
2 MHz
140
245
460
0.56
1.1
180
Range 3, VCORE=1.2 V
290
540
0.65
1.3
2.4
1.6
3
µA
VOS[1:0]=11
4 MHz
4 MHz
fHSE = fHCLK up to
16 MHz included,
Range 2, VCORE=1.5 V,
fHSE = fHCLK/2 above VOS[1:0]=10,
8 MHz
16 MHz (PLL ON)(2)
16 MHz
8 MHz
2.1
mA
Supply
1.3
IDD
current in
Run mode,
code
executed
from Flash
Range 1, VCORE=1.8 V,
VOS[1:0]=01
(Run
from
Flash)
16 MHz
32 MHz
65 kHz
524 kHz
4.2 MHz
2.6
5.3
6.5
54
34.5
86
Range 3, VCORE=1.2 V,
VOS[1:0]=11
MSI clock
HSI clock
120
560
µA
505
Range 2, VCORE=1.5 V,
VOS[1:0]=10,
16 MHz
32 MHz
2.2
5.4
2.6
5.9
mA
Range 1, VCORE=1.8 V,
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 22. Current consumption in Run mode vs code type,
code with data processing running from Flash
Symbol
Parameter
Conditions
fHCLK
Typ
Unit
Dhrystone
CoreMark
Fibonacci
while(1)
460
440
330
305
Range 3,
VCORE=1.2 V,
4 MHz
µA
VOS[1:0]=11
Supply
while(1), prefetch
OFF
IDD
current in
Run mode,
code
executed
from Flash
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2 above
16 MHz (PLL ON)(1)
320
(Run
from
Flash)
Dhrystone
CoreMark
Fibonacci
while(1)
5.4
4.9
5
Range 1,
VOS[1:0]=01,
VCORE=1.8 V
32 MHz
mA
4.35
while(1), prefetch
OFF
3.7
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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Figure 13. I vs V , at T = 25 °C, Run mode, code running from
DD
DD
A
Flash memory, Range 2, 16 MHz HSE, 1WS
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Figure 14. I vs V , at T = 25 °C, Run mode, code running from
DD
DD
A
Flash memory, Range 2, HSI16, 1WS
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Table 23. Current consumption in Run mode, code with data processing running from RAM
Symbol
Parameter
Conditions
fHCLK
Typ
Max(1) Unit
1 MHz
2 MHz
115
205
385
0.48
0.935
1.8
140
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
240
420
0.55
1.1
2
µA
4 MHz
fHSE = fHCLK up to 16
MHz, included
4 MHz
Range 2,
fHSE = fHCLK/2 above VCORE=1.5 ,V,
8 MHz
16 MHz
VOS[1:0]=10
16 MHz
8 MHz
(PLL ON)(2)
mA
1.1
1.4
2.5
4.9
38
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
Supply current in
16 MHz
32 MHz
65 kHz
524 kHz
4.2 MHz
2.1
I
DD (Run Run mode, code
from
RAM)
executed from
RAM, Flash
4.5
22
switched OFF
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
MSI clock
67
91
µA
415
450
Range 2,
VCORE=1.5 V,
VOS[1:0]=10
16 MHz
32 MHz
1.95
4.7
2.2
5.2
HSI16 clock source
(16 MHz)
mA
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 24. Current consumption in Run mode vs code type,
(1)
code with data processing running from RAM
Symbol
Parameter
Conditions
fHCLK
Typ Unit
Dhrystone
CoreMark
Fibonacci
while(1)
385
(3)
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
-
4 MHz
µA
350
Supply current in
IDD (Run Run mode, code
fHSE = fHCLK up to 16
MHz, included,
340
4.5
from
RAM)
executed from
RAM, Flash
switched OFF
fHSE = fHCLK/2 above
Dhrystone
CoreMark
Fibonacci
while(1)
16 MHz (PLL ON)(2)
(3)
Range 1,
-
VCORE=1.8 V,
32 MHz
mA
4.2
VOS[1:0]=01
3
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. CoreMark code is unable to run from RAM since the RAM size is only 2 Kbytes.
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Table 25. Current consumption in Sleep mode
Symbol
Parameter
Conditions
fHCLK
Typ
Max(1)
Unit
1 MHz
2 MHz
36.5
58
70
95
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
4 MHz
100
125
230
450
275
555
1350
15.5
26.5
115
150
170
300
540
350
650
1600
32
fHSE = fHCLK up to
4 MHz
16 MHz included,
fHSE = fHCLK/2
above 16 MHz
(PLL ON)(2)
Range 2,
VCORE=1.5 V,
VOS[1:0]=10
8 MHz
16 MHz
8 MHz
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
Supplycurrent
in Sleep
mode, Flash
OFF
16 MHz
32 MHz
65 kHz
524 kHz
4.2 MHz
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
MSI clock
55
160
Range 2,
VCORE=1.5 V,
VOS[1:0]=10
16 MHz
32 MHz
585
670
HSI16 clock source
(16 MHz)
Range 1,
VCORE=1.8 V,
1500
1700
VOS[1:0]=01
IDD (Sleep)
µA
1 MHz
2 MHz
49
69
88
120
190
200
340
650
400
750
1900
46
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
4 MHz
115
135
240
460
290
565
1350
26.5
38.5
125
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
4 MHz
Range 2,
CORE=1.5 V,
above 16 MHz (PLL VOS[1:0]=10
8 MHz
16 MHz
8 MHz
ON)(2)
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
Supplycurrent
in Sleep
mode, Flash
ON
16 MHz
32 MHz
65 kHz
524 kHz
4.2 MHz
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
MSI clock
70
190
Range 2,
VCORE=1.5 V,
VOS[1:0]=10
16 MHz
32 MHz
600
760
HSI16 clock source
(16 MHz)
Range 1,
VCORE=1.8 V,
1500
1850
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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Table 26. Current consumption in Low-power Run mode
Symbol Parameter
Conditions
Typ
Max(1)
Unit
TA = -40 °C to 25 °C
TA = 85 °C
5.7
6.5
8
8.1
9
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = 105 °C
13
22
11
12
15
24
19
19.5
20
22
31
22
24
27
37
25
27
30
39
34
35
37
39
47
TA = 125 °C
11.5
8.7
9.5
11
All
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
TA =-40 °C to 25 °C
TA = 85 °C
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = 105 °C
TA = 125 °C
15
TA = -40 °C to 25 °C
TA = 55 °C
17
17
MSI clock, 131 kHz
TA = 85 °C
17.5
19
f
HCLK = 131 kHz
TA = 105 °C
Supply
current in
(LP Run) Low-power
run mode
TA = 125 °C
22.5
18
IDD
µA
TA = -40 °C to 25 °C
TA = 85 °C
20
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = 105 °C
22
TA = 125 °C
26.5
22
All
TA = -40 °C to 25 °C
TA = 85 °C
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
24
MSI clock, 65 kHz
f
HCLK = 65 kHz
TA = 105 °C
26
TA = 125 °C
30.5
32
TA = -40 °C to 25 °C
TA = 55 °C
32.5
34
MSI clock, 131 kHz
HCLK = 131 kHz
TA = 85 °C
f
TA = 105 °C
36
TA = 125 °C
40
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
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Figure 15. I vs V , at T = -40/25/55/ 85/105/125 °C, Low-power run mode,
DD
DD
A
code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS
06Yꢋꢁꢄꢊꢍ9ꢇ
Table 27. Current consumption in Low-power Sleep mode
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
MSI clock, 65 kHz
f
HCLK = 32 kHz
TA = -40 °C to 25 °C 2.5(2)
-
Flash OFF
TA = -40 °C to 25 °C
TA = 85 °C
13
15.5
17.5
21
19
20
22
29
19
20
22
29
21
22
23
24
31
MSI clock, 65 kHz
f
HCLK = 32 kHz
TA = 105 °C
Flash ON
TA = 125 °C
Supply
current in
(LP Sleep) Low-power
sleep mode
TA = -40 °C to 25 °C
TA = 85 °C
13.5
16
All peripherals
OFF, VDD from
1.65 V to 3.6 V
IDD
MSI clock, 65 kHz
fHCLK = 65 kHz,
Flash ON
µA
TA = 105 °C
18
TA = 125 °C
21.5
15.5
17
TA = -40 °C to 25 °C
TA = 55 °C
MSI clock, 131 kHz
fHCLK = 131 kHz,
Flash ON
TA = 85 °C
18
TA = 105 °C
19.5
23.5
TA = 125 °C
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. As the CPU is in Sleep mode, the difference between the current consumption with Flash memory ON and OFF (nearly
12 µA) is the same whatever the clock frequency.
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Table 28. Typical and maximum current consumptions in Stop mode
Symbol
Parameter
Conditions
Typ
Max(1) Unit
TA = -40°C to 25°C
TA = 55°C
0.34
0.43
0.94
2.0
0.99
1.9
IDD (Stop) Supply current in Stop mode
TA= 85°C
4.2
9
µA
TA = 105°C
TA = 125°C
4.9
19
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
Figure 16. I vs V , at T = -40/25/55/ 85/105/125 °C, Stop mode with RTC enabled
DD
DD
A
and running on LSE Low drive
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Figure 17. I vs V , at T = -40/25/55/85/105/125 °C, Stop mode with RTC disabled,
DD
DD
A
all clocks OFF
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Table 29. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Conditions
Typ
Max(1) Unit
TA = -40 °C to 25 °C
TA = 55 °C
0.8
0.9
1.6
1.8
2
Independent watchdog
and LSI enabled
TA= 85 °C
1
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
TA = 55 °C
1.25
2
3
7
IDD
Supply current in Standby
µA
0.6
(Standby) mode
0.23
0.25
0.36
0.62
1.35
0.7
1
Independent watchdog
and LSI OFF
TA = 85 °C
TA = 105 °C
TA = 125 °C
1.7
5
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified
Table 30. Average current consumption during wakeup
Current
Symbol
parameter
System frequency
consumption
Unit
during wakeup
HSI
HSI/4
1
0,7
0,7
0,4
0,1
0,21
I
DD (WU from
Stop)
Supply current during wakeup from
Stop mode
MSI 4,2 MHz
MSI 1,05 MHz
MSI 65 KHz
-
mA
IDD (Reset)
Reset pin pulled down
IDD (Power Up) BOR ON
-
0,23
With Fast wakeup set
With Fast wakeup disabled
MSI 2,1 MHz
MSI 2,1 MHz
0,5
IDD (WU from
StandBy)
0,12
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following tables. The
MCU is placed under the following conditions:
•
•
•
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked OFF
with only one peripheral clocked ON
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(1)
Table 31. Peripheral current consumption in run or Sleep mode
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
CORE=1.8 V
Range 2,
CORE=1.5 V
Range 3,
CORE=1.2 V
Low-power
sleep and
run
Peripheral
Unit
V
V
V
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
WWDG
LPUART1
I2C1
2.5
8.3
11
2
1.6
5.4
6.8
8.7
6.4
5.4
3.3
2.9
4.5
1.1
2
7.2
8.2
11
7.2
8.9
11
µA/MHz
APB1
(fHCLK
)
LPTIM1
TIM2
14
10.5
8.5
5.0
4.5
6.8
1.7
8.5
6.8
3.9
3.5
6.1
1.7
8.5
7.1
4
USART2
ADC1(2)
SPI1
3.6
5.6
1.4
TIM21
µA/MHz
(fHCLK
APB2
)
DBGMCU
SYSCFG/
COMP
2.5
2.4
1.6
2.3
GPIOA
7.6
5.1
1.1
1.5
10
6.3
4.1
0.7
1.1
8.5
3.0
4.2
80
4.9
3.2
0.6
1
6.5
4
Cortex-
µA/MHz
(fHCLK
M0+ core GPIOB
)
I/O port
GPIOC
0.8
1.2
8.5
2.8
4.8
88
CRC
FLASH(3)
AHB
AES
7
µA/MHz
(fHCLK
3.6
5.3
96
2.4
3.5
62
)
DMA1
All enabled
µA/MHz
(fHCLK
PWR
2.1
1.9
1.4
1.8
)
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. These values correspond to the Flash memory dynamic current consumption. The Flash memory static
consumption (Flash memory ON) equals 12 µA and does not depend on the frequency.
The Flash memory consumption is already taken into account in all the supply current consumption tables
(Flash memory ON cases).
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Table 32. Peripheral current consumption in Stop and Standby mode
Typical consumption, TA = 25 °C
Symbol
Peripheral
Unit
VDD=1.8 V
VDD=3.0 V
IDD(PVD / BOR)
-
0.6
1.25
0.11
1
IREFINT
-
-
1.3
0.16
LSE Low drive
-
-
LPTIM1, Input 100 Hz
LPTIM1, Input 1 MHz
0.01
8
0.02
9
µA
-
-
LPUART1
RTC
0.025
0.1
0.027
0.19
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI or HSI16 RC
oscillator. The clock source used to wake up the device depends on the current operating
mode:
•
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
Stop mode: the clock source is either the MSI oscillator in the range configured before
entering Stop mode, the HSI16 or HSI16/4.
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 17.
Table 33. Low-power mode wakeup timings
Symbol
Parameter
Conditions
fHCLK = 32 MHz
Typ
Max
Unit
tWUSLEEP
Wakeup from Sleep mode
7
8
fHCLK = 262 kHz
Flash enabled
7
9
8
CPU
cycles
Wakeup from Low-power sleep mode,
fHCLK = 262 kHz
tWUSLEEP_LP
fHCLK = 262 kHz
Flash switched OFF
10
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Symbol
Electrical characteristics
Table 33. Low-power mode wakeup timings (continued)
Parameter
Conditions
Typ
Max
Unit
fHCLK = fMSI = 4.2 MHz
5.1
5.1
8.1
8
7
Wakeup from Stop mode, regulator in
Run mode
f
HCLK = fHSI = 16 MHz
fHCLK = fHSI/4 = 4 MHz
11
fHCLK = fMSI = 4.2 MHz
Voltage range 1
5
5
5
8
8
8
fHCLK = fMSI = 4.2 MHz
Voltage range 2
f
HCLK = fMSI = 4.2 MHz
Voltage range 3
fHCLK = fMSI = 2.1 MHz
7.4
14
13
23
38
65
120
260
7
Wakeup from Stop mode, regulator in
low-power mode
f
HCLK = fMSI = 1.05 MHz
fHCLK = fMSI = 524 kHz
HCLK = fMSI = 262 kHz
28
tWUSTOP
f
51
µs
fHCLK = fMSI = 131 kHz
fHCLK = fMSI = 65 kHz
99
196
5.1
8.2
f
HCLK = fHSI = 16 MHz
fHCLK = fHSI/4 = 4 MHz
fHCLK = fHSI = 16 MHz
fHCLK = fHSI = 16 MHz
11
Wakeup from Stop mode, regulator in
low-power mode, HSI kept running in
Stop mode
3.25
-
4.9
7.9
4.8
7
10
8
Wakeup from Stop mode, regulator in
low-power mode, code running from
RAM
f
HCLK = fHSI/4 = 4 MHz
fHCLK = fMSI = 4.2 MHz
fHCLK = fMSI = 2.1 MHz
Wakeup from Standby mode
FWU bit = 1
65
130
3
tWUSTDBY
Wakeup from Standby mode
FWU bit = 0
f
HCLK = fMSI = 2.1 MHz
2.2
ms
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6.3.6
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the input pin is a standard GPIO.The external clock signal has to respect
the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform
is shown in Figure 18.
(1)
Table 34. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CSS is ON or
PLL is used
1
8
32
MHz
User external clock source
frequency
fHSE_ext
CSS is OFF,
PLL not used
0
8
32
MHz
V
VHSEH
VHSEL
tw(HSE)
CK_IN input pin high level voltage
CK_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
0.3VDD
CK_IN high or low time
CK_IN rise or fall time
12
-
-
-
-
tw(HSE)
-
ns
tr(HSE)
tf(HSE)
20
Cin(HSE) CK_IN input capacitance
DuCy(HSE) Duty cycle
-
45
-
2.6
-
pF
%
-
-
55
±1
IL
CK_IN Input leakage current
VSS ≤ VIN ≤ VDD
µA
1. Guaranteed by design, not tested in production.
Figure 18. High-speed external clock source AC timing diagram
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Electrical characteristics
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
(1)
Table 35. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSE)
0.7VDD
VSS
465
-
-
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level
voltage
-
OSC32_IN high or low time
OSC32_IN rise or fall time
tw(LSE)
ns
tr(LSE)
tf(LSE)
10
CIN(LSE) OSC32_IN input capacitance
DuCy(LSE) Duty cycle
-
-
-
45
-
0.6
-
pF
%
-
-
55
±1
IL
OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD
µA
1. Guaranteed by design, not tested in production
Figure 19. Low-speed external clock source AC timing diagram
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Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 36. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
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Electrical characteristics
STM32L021x4
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 36. LSE oscillator characteristics
Symbol
Parameter
Conditions(2)
Min(2) Typ
Max Unit
fLSE
LSE oscillator frequency
-
-
32.768
-
-
kHz
µA/V
s
LSEDRV[1:0]=00
lower driving capability
0.5
LSEDRV[1:0]= 01
medium low driving capability
-
-
-
-
0.75
1.7
Maximum critical crystal
transconductance
Gm
LSEDRV[1:0] = 10
medium high driving capability
LSEDRV[1:0]=11
higher driving capability
-
-
-
2.7
-
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST
microcontrollers”.
3. Guaranteed by characterization results, not tested in production. tSU(LSE) is the startup time measured from the moment it is
enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal
resonator and it can vary significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a
high- driver mode.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website http://www.st.com.
Figure 20. Typical application with a 32.768 kHz crystal
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to add one.
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6.3.7
Internal clock source characteristics
The parameters given in Table 37 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 17.
DD
High-speed internal 16 MHz (HSI16) RC oscillator
Table 37. 16 MHz HSI16 oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ Max Unit
fHSI16
VDD = 3.0 V
-
-
16
-
MHz
%
Trimming code is not a multiple of 16
Trimming code is a multiple of 16
VDDA = 3.0 V, TA = 25 °C
0.4 0.7
HSI16 user-
trimmed resolution
(1)(2)
TRIM
-
-
-
-
-
-
-
1.5
%
-1(3)
-1.5
-2
1(3)
1.5
2
%
VDDA = 3.0 V, TA = 0 to 55 °C
VDDA = 3.0 V, TA = -10 to 70 °C
%
%
Accuracy of the
factory-calibrated
HSI16 oscillator
ACCHSI16
(2)
V
DDA = 3.0 V, TA = -10 to 85 °C
VDDA = 3.0 V, TA = -10 to 105 °C
DDA = 1.65 V to 3.6 V
-2.5
-4
2
%
2
%
V
-5.45
-
3.25
6
%
µs
µA
TA = -40 to 125 °C
HSI16 oscillator
startup time
(2)
tSU(HSI16)
-
-
-
3.7
100
HSI16 oscillator
power consumption
(2)
IDD(HSI16)
-
140
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results, not tested in production.
3. Guaranteed by test in production.
Figure 21. HSI16 minimum and maximum value versus temperature
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Low-speed internal (LSI) RC oscillator
Table 38. LSI oscillator characteristics
Symbol
Parameter
LSI frequency
Min
Typ
Max
Unit
(1)
fLSI
26
38
56
4
kHz
LSI oscillator frequency drift
0°C ≤ TA ≤ 85°C
(2)
DLSI
-10
-
%
(3)
tsu(LSI)
LSI oscillator startup time
-
-
-
200
510
µs
(3)
IDD(LSI)
LSI oscillator power consumption
400
nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design, not tested in production.
Multi-speed internal (MSI) RC oscillator
Table 39. MSI oscillator characteristics
Symbol
Parameter
Condition
Typ
Max Unit
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
-
65.5
131
262
524
1.05
2.1
-
-
kHz
-
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
fMSI
-
-
-
-
-
MHz
4.2
ACCMSI
Frequency error after factory calibration
0.5
%
%
MSI oscillator frequency drift
0 °C ≤ TA ≤ 85 °C
(1)
DTEMP(MSI)
-
-
3
-
-
MSI oscillator frequency drift
1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C
(1)
DVOLT(MSI)
2.5 %/V
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
0.75
1
-
-
-
1.5
2.5
4.5
8
(2)
IDD(MSI)
MSI oscillator power consumption
-
-
-
-
µA
15
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Table 39. MSI oscillator characteristics (continued)
Symbol
Parameter
Condition
Typ
Max Unit
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
30
20
15
10
6
-
-
-
-
-
tSU(MSI)
MSI oscillator startup time
µs
-
5
MSI range 6,
Voltage range 1
and 2
3.5
5
-
-
MSI range 6,
Voltage range 3
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
-
-
-
-
-
-
40
20
10
4
2.5
µs
2
(2)
tSTAB(MSI)
MSI oscillator stabilization time
MSI range 6,
Voltage range 1
and 2
-
2
3
MSI range 3,
Voltage range 3
-
-
-
Any range to
range 5
4
fOVER(MSI) MSI oscillator frequency overshoot
MHz
6
Any range to
range 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results, not tested in production.
6.3.8
PLL characteristics
The parameters given in Table 40 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 17.
DD
Table 40. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
PLL input clock duty cycle
2
-
-
24
55
MHz
%
fPLL_IN
45
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Table 40. PLL characteristics (continued)
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
fPLL_OUT
tLOCK
PLL output clock
2
-
32
MHz
µs
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
Jitter
Cycle-to-cycle jitter
-
-
-
600
450
150
ps
IDDA(PLL)
IDD(PLL)
Current consumption on VDDA
Current consumption on VDD
220
120
µA
1. Guaranteed by characterization results, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
6.3.9
Memory characteristics
RAM memory
Table 41. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM Data retention mode(1)
STOP mode (or RESET)
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
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Flash memory and data EEPROM
Table 42. Flash memory and data EEPROM characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
Operating voltage
VDD
-
1.65
-
3.6
V
Read / Write / Erase
Erasing
-
-
3.28
3.28
3.94
3.94
Programming time for
word or half-page
tprog
ms
Programming
Average current during
the whole programming /
erase operation
-
-
500
1.5
700
2.5
µA
IDD
TA = 25 °C, VDD = 3.6 V
Maximum current (peak)
during the whole
programming / erase
operation
mA
1. Guaranteed by design, not tested in production.
Table 43. Flash memory and data EEPROM endurance and retention
Value
Symbol
Parameter
Conditions
Unit
Min(1)
Cycling (erase / write)
Program memory
10
TA = -40°C to 105 °C
Cycling (erase / write)
EEPROM data memory
100
0.2
2
(2)
NCYC
kcycles
Cycling (erase / write)
Program memory
TA = -40°C to 125 °C
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
30
30
T
RET = +85 °C
Data retention (EEPROM data memory)
after 100 kcycles at TA = 85 °C
Data retention (program memory) after
10 kcycles at TA = 105 °C
(2)
tRET
TRET = +105 °C
years
Data retention (EEPROM data memory)
after 100 kcycles at TA = 105 °C
10
Data retention (program memory) after
200 cycles at TA = 125 °C
TRET = +125 °C
Data retention (EEPROM data memory)
after 2 kcycles at TA = 125 °C
1. Guaranteed by characterization results, not tested in production.
2. Characterization is done according to JEDEC JESD22-A117.
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6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 44. They are based on the EMS levels and classes
defined in application note AN1709.
Table 44. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP32, TA = +25 °C,
fHCLK = 32 MHz
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
3B
4A
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP32, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
VEFTB
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
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To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 45. EMI characteristics
Monitored
Max vs. frequency range
Symbol Parameter
Conditions
Unit
frequency band (32 MHz voltage Range 1)
0.1 to 30 MHz
-22
-7
VDD = 3.3 V,
TA = 25 °C,
LQFP32 package
compliant with IEC
61967-2
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
dBµV
-
SEMI
Peak level
-12
1
6.3.11
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 46. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
TA = +25 °C,
Electrostatic discharge
voltage (human body model)
VESD(HBM)
conforming to
2
2000
ANSI/JEDEC JS-001
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C,
conforming to
C4
500
ANSI/ESD STM5.3.1.
1. Guaranteed by characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
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Electrical characteristics
Symbol
STM32L021x4
Table 47. Electrical sensitivities
Conditions
Parameter
Static latch-up class
Class
LU
TA = +125 °C conforming to JESD78A
II level A
6.3.12
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard pins) should be avoided during normal product operation.
DD
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation).
The test results are given in the Table 48.
Table 48. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0
-0
NA(1)
NA(1)
+5
IINJ
Injected current on all FT pins
Injected current on any other pin
-5 (2)
-5 (2)
mA
1. Current injection is not possible.
2. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
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6.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL
compliant.
Table 49. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TC, FT, FTf, RST
I/Os
-
-
-
-
0.3VDD
VIL
Input low level voltage
(1)
BOOT0 pin
-
0.14VDD
-
All I/Os except
BOOT0 pin
0.7 VDD
V
VIH
Input high level voltage
0.15
BOOT0 pin
-
-
VDD+0.56(1)
(3)
Standard I/Os
BOOT0 pin
-
-
10% VDD
0.01
-
-
I/O Schmitt trigger voltage hysteresis
Vhys
(2)
VSS ≤ VIN ≤ VDD
All I/Os except
BOOT0 and FTf
I/Os
-
-
-
±50
-
nA
µA
BOOT0(5)
+2
VIN = VDD
BOOT0
Ilkg
Input leakage current (4)
-
-
-
-
0
-
-
VIN = VSS
VDD ≤ VIN ≤ 5 V
200
500
10
FT I/Os
nA
µA
VDD ≤ VIN ≤ 5 V
-
FTf I/Os
VDD ≤ VIN ≤ 5 V
-
BOOT0
RPU
RPD
CIO
Weak pull-up equivalent resistor(6)
Weak pull-down equivalent resistor(6)
I/O pin capacitance
VIN = VSS
VIN = VDD
-
25
25
-
45
45
5
65
65
-
kΩ
kΩ
pF
1. Guaranteed by characterization, not tested in production
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in production.
3. With a minimum of 200 mV. Guaranteed by characterization results, not tested in production.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. BOOT0/PB9 pin limitation: typical input leakage current = 2 µA and input frequency limited to 10 kHz (1.65 V < VDD < 2.7 V)
and 5 MHz (2.7 V < VDD < 3.6 V).
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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STM32L021x4
Figure 22. V /V versus VDD (CMOS I/Os)
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±15 mA with the non-standard V /V specifications given in Table 50.
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 15).
VDD(Σ)
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 15).
VSS(Σ)
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Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 17. All I/Os are CMOS and TTL compliant.
Table 50. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
Output low level voltage for an I/O
pin
(1)
CMOS port(2)
IIO = +8 mA
2.7 V ≤ VDD ≤ 3.6 V
,
VOL
-
0.4
Output high level voltage for an I/O
pin
(3)
VOH
VDD-0.4
-
TTL port(2)
IIO =+ 8 mA
2.7 V ≤ VDD ≤ 3.6 V
,
Output low level voltage for an I/O
pin
(1)
VOL
-
0.4
TTL port(2)
IIO = -6 mA
2.7 V ≤ VDD ≤ 3.6 V
,
Output high level voltage for an I/O
pin
(3)(4)
VOH
2.4
-
-
Output low level voltage for an I/O
pin
IIO = +15 mA
2.7 V ≤ VDD ≤ 3.6 V
(1)(4)
VOL
1.3
V
Output high level voltage for an I/O
pin
IIO = -15 mA
2.7 V ≤ VDD ≤ 3.6 V
(3)(4)
VOH
V
DD-1.3
-
0.45
-
Output low level voltage for an I/O
pin
IIO = +4 mA
1.65 V ≤ VDD < 3.6 V
(1)(4)
VOL
-
Output high level voltage for an I/O
pin
IIO = -4 mA
1.65 V ≤ VDD ≤ 3.6 V
(3)(4)
VOH
VDD-0.45
IIO = 20 mA
2.7 V ≤ VDD ≤ 3.6 V
-
-
0.4
0.4
Output low level voltage for an FTf
I/O pin in Fm+ mode
(1)(4)
VOLFM+
I
IO = 10 mA
1.65 V ≤ VDD ≤ 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15.
The sum of the currents sunk by all the I/Os (I/O ports and control pins) must always be respected and
must not exceed ΣIIO(PIN)
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 15. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be
respected and must not exceed ΣIIO(PIN)
.
4. Guaranteed by characterization results, not tested in production.
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STM32L021x4
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 51, respectively.
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 17.
(1)(2)
Table 51. I/O AC characteristics
OSPEEDRx
[1:0] bit
Symbol
Parameter
Conditions
Min Max(3) Unit
value(1)
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
100
125
320
2
fmax(IO)out Maximum frequency(4)
kHz
ns
00
01
10
tf(IO)out
Output rise and fall time
tr(IO)out
fmax(IO)out Maximum frequency(4)
MHz
ns
0.6
30
65
10
2
tf(IO)out
Output rise and fall time
tr(IO)out
Fmax(IO)out Maximum frequency(4)
MHz
ns
13
28
35
10
6
tf(IO)out
Output rise and fall time
tr(IO)out
Fmax(IO)out Maximum frequency(4)
MHz
ns
11
-
tf(IO)out
Output rise and fall time
tr(IO)out
17
Pulse width of external
tEXTIpw
signals detected by the
EXTI controller
-
8
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO
Port configuration register.
2. BOOT0/PB9 maximum input frequency is 10 kHz (1.65 V < VDD < 2.7 V) and 5 MHz (2.7 V < VDD < 3.6 V).
3. Guaranteed by design. Not tested in production.
4. The maximum frequency is defined in Figure 24.
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Electrical characteristics
Figure 24. I/O AC characteristics definition
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6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R , except when it is internally driven low (see Table 52).
PU
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 17.
Table 52. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)
VIL(NRST)
NRST input low level voltage
-
-
-
0.3VDD
0.39VDD
0.59
+
(1)
VIH(NRST)
NRST input high level voltage
NRST output low level voltage
-
-
-
V
I
OL = 2 mA
2.7 V < VDD < 3.6 V
-
-
-
(1)
(1)
VOL(NRST)
0.4
I
OL = 1.5 mA
1.65 V < VDD < 2.7 V
-
10%VDD
45
NRST Schmitt trigger voltage
hysteresis
(2)
Vhys(NRST)
-
-
-
mV
Weak pull-up equivalent
resistor(3)
RPU
VIN = VSS
25
65
kΩ
(1)
VF(NRST)
NRST input filtered pulse
-
-
-
-
-
50
-
ns
ns
(1)
VNF(NRST)
NRST input not filtered pulse
350
1. Guaranteed by design, not tested in production.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.
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93
Electrical characteristics
STM32L021x4
Figure 25. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 52. Otherwise the reset will not be taken into account by the device.
6.3.15
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 53 are values derived from tests
performed under ambient temperature, f
frequency and V
supply voltage conditions
PCLK
DDA
summarized in Table 17: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 53. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fast channel
Standard channels
1.14 Msps
1.65
-
-
3.6
Analog supply voltage for
ADC ON
VDDA
V
1.75(1)
3.6
-
-
200
40
70
1
-
Current consumption of the
ADC on VDDA
10 ksps
-
-
IDDA (ADC)
µA
1.14 Msps
-
Current consumption of the
(2)
ADC on VDD
10 ksps
-
-
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 3
-
0.14
0.14
0.14
0.05
-
16
8
fADC
ADC clock frequency
-
MHz
-
4
(3)
fS
Sampling rate
-
1.14
MHz
kHz
fADC = 16 MHz,
16-bit resolution
-
-
941
(3)
External trigger frequency
fTRIG
-
-
-
-
-
17
1/fADC
V
VAIN
Conversion voltage range
External input impedance
Sampling switch resistance
0
VDDA
See Equation 1 and
Table 54 for details
(3)
RAIN
-
-
-
-
50
1
kΩ
kΩ
(3)(4)
-
RADC
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Symbol
Electrical characteristics
Table 53. ADC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
Internal sample and hold
capacitor
(3)
-
-
-
8
pF
CADC
f
ADC = 16 MHz
-
5.2
83
µs
(3)
Calibration time
tCAL
1/fADC
1.5 ADC
cycles + 3
fPCLK cycles
1.5 ADC
cycles + 2
PCLK cycles
ADC clock = HSI16
ADC clock = PCLK/2
-
-
f
ADC_DR register write
latency
fPCLK
cycle
WLATENCY
-
-
4.5
8.5
-
-
fPCLK
cycle
ADC clock = PCLK/4
fADC = fPCLK/2 = 16 MHz
0.266
8.5
µs
1/fPCLK
µs
fADC = fPCLK/2
(3)
Trigger conversion latency
fADC = fPCLK/4 = 8 MHz
fADC = fPCLK/4
0.516
16.5
-
tlatr
1/fPCLK
µs
fADC = fHSI16 = 16 MHz
0.252
-
0.260
-
ADC jitter on trigger
conversion
JitterADC
f
ADC = fHSI16
1
1/fHSI16
fADC = 16 MHz
0.093
1.5
-
-
10.03
239.5
1
µs
1/fADC
µs
(3)
Sampling time
Power-up time
tS
-
(3)
tSTAB
-
0
0
fADC = 16 MHz
0.875
10.81
µs
Total conversion time
(including sampling time)
(3)
tConV
14 to 173 (tS for sampling +12.5 for
successive approximation)
-
1/fADC
1. VDDA minimum value can be decreased in specific temperature conditions. Refer to Table 54: RAIN max for fADC = 16
MHz.
2. A current consumption proportional to the APB clock frequency has to be added (see Table 31: Peripheral current
consumption in run or Sleep mode).
3. Guaranteed by design, not tested in production.
4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 54: RAIN max for
fADC = 16 MHz.
Equation 1: R
max formula
AIN
TS
---------------------------------------------------------------
– RADC
RAIN
<
fADC × CADC × ln(2N + 2
)
The simplified formula above (Equation 1) is used to determine the maximum external
impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
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Electrical characteristics
STM32L021x4
(1)
Table 54. R
max for f
= 16 MHz
AIN
ADC
RAIN max for standard channels (kΩ)
RAIN max for
fast channels
(kΩ)
Ts
tS
VDD > 1.65 V
and
V
DD > 1.65 V
VDD
2.7 V
>
VDD
2.4 V
>
VDD
2.0 V
>
VDD
1.8 V
>
VDD >
1.75 V
(cycles) (µs)
and
TA > −10 °C
TA > 25 °C
1.5
3.5
0.09
0.22
0.47
0.78
1.22
2.47
4.97
0.5
1
< 0.1
0.2
NA
< 0.1
1.5
3
NA
NA
< 0.1
1
NA
NA
NA
NA
NA
NA
< 0.1
32
NA
NA
NA
NA
NA
NA
NA
NA
< 0.1
5
7.5
2.5
4
1.7
NA
NA
12.5
19.5
39.5
79.5
3.2
NA
NA
6.5
13
27
50
5.7
5.5
12
3.5
10
NA
NA
12.2
26.2
49.2
NA
NA
26
24
NA
NA
19
160.5 10.03
49
47
< 0.1
< 0.1
42
1. Guaranteed by design.
(1)(2)(3)(4)
Table 55. ADC accuracy
Symbol
Parameter
Total unadjusted error
Conditions
Min
Typ
Max
Unit
ET
EO
EG
EL
-
2
1
4
Offset error
Gain error
-
2.5
2
-
1
LSB
Integral linearity error
Differential linearity error
Effective number of bits
-
-
1.5
1
2.5
1.5
ED
10.2
11
1.65 V < VDDA < 3.6 V, range
1/2/3, except for TSSOP14
package
ENOB
bits
dB
Effective number of bits (16-bit mode
oversampling with ratio =256)(5)
11.3 12.1
-
SINAD Signal-to-noise distortion
62
63
67.8
68
-
-
Signal-to-noise ratio
SNR
Signal-to-noise ratio (16-bit mode
70
-
76
-
oversampling with ratio =256)(5)
THD
Total harmonic distortion
-81
-68.5
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STM32L021x4
Symbol
Electrical characteristics
(1)(2)(3)(4)
Table 55. ADC accuracy
Conditions
Parameter
Min
Typ
Max
Unit
ET
EO
EG
EL
Total unadjusted error
-
3
2
5
Offset error
Gain error
-
-
2.5
2.5
2.5
1.7
-
2
LSB
Integral linearity error
Differential linearity error
Effective number of bits
-
1.5
1
ED
-
9.5
10.5
1.65 V < VDDA < 3.6 V, range
1/2/3, TSSOP14 package
ENOB
bits
dB
Effective number of bits (16-bit mode
oversampling with ratio =256)(5)
10.7 11.6
-
SINAD Signal-to-noise distortion
59
59
65
65
-
-
Signal-to-noise ratio
SNR
Signal-to-noise ratio (16-bit mode
66
-
73
-
oversampling with ratio =256)(5)
THD
Total harmonic distortion
-75
-63
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input.
It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative
current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. In TSSOP14 package, where VDDA pin is shared with VDD pin, I/O toggling should be minimized to reach the values given in
the above table. I/O toggling with loaded I/O pins can generate ripple on VDD/VDDA and degrade the ADC accuracy.
5. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode.
Figure 26. ADC accuracy characteristics
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Electrical characteristics
STM32L021x4
Figure 27. Typical connection diagram using the ADC
9
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1. Refer to Table 53: ADC characteristics for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
6.3.16
Temperature sensor characteristics
Table 56. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
TS_CAL2
temperature of 130 °C ± 5 °C,
0x1FF8 007E - 0x1FF8 007F
V
DDA= 3 V ± 10 mV
Table 57. Temperature sensor characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
-
1.48
640
-
1
1.61
670
3.4
-
2
1.75
700
6
°C
mV/°C
mV
Avg_Slope(1) Average slope
V130
Voltage at 130°C ±5°C(2)
IDDA
(3)
Current consumption
Startup time
µA
(TEMP)
(3)
tSTART
-
10
µs
ADC sampling time when reading the
temperature
(4)(3)
TS_temp
10
-
-
1. Guaranteed by characterization results, not tested in production.
2. Measured at VDD = 3 V ±10 mV. V30 ADC conversion result is stored in the TS_CAL1 byte.
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
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Electrical characteristics
6.3.17
Comparators
Table 58. Comparator 1 characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
VDDA
R400K
R10K
Analog supply voltage
R400K value
-
-
-
1.65
3.6
V
-
-
400
10
-
-
kΩ
R10K value
Comparator 1 input
voltage range
VIN
-
0.6
-
VDDA
V
tSTART
td
Comparator startup time
Propagation delay(2)
Comparator offset(3)
-
-
-
-
-
-
7
3
3
10
10
10
µs
Voffset
mV
VDDA = 3.6 V
VIN+ = 0 V
VIN- = VREFINT
TA = 25 °C
Comparator offset
dVoffset/dt variation in worst voltage
0
-
1.5
10
mV/1000 h
nA
stress conditions(3)
ICOMP1
Current consumption(4)
-
160
260
1. Guaranteed by characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. In TSSOP14 package, where VDDA pin is shared with VDD pin, I/O toggling should be minimized to reach
the values given in the above table. I/O toggling with loaded I/O pins can generate ripple on VDD/VDDA and
degrade the comparator performance.
4. Comparator consumption only. Internal reference voltage not included.
Table 59. Comparator 2 characteristics
Symbol
Parameter
Conditions
Min Typ Max(1) Unit
VDDA
VIN
Analog supply voltage
-
-
1.65
-
3.6
VDDA
20
25
3.5
6
V
V
Comparator 2 input voltage range
0
-
-
-
-
-
-
-
-
Fast mode
15
20
1.8
2.5
0.8
1.2
4
tSTART
Comparator startup time
Slow mode
1.65 V ≤ VDDA ≤ 2.7 V
2.7 V ≤ VDDA ≤ 3.6 V
1.65 V ≤ VDDA ≤ 2.7 V
2.7 V ≤ VDDA ≤ 3.6 V
td slow
Propagation delay(2) in slow mode
µs
2
td fast
Propagation delay(2) in fast mode
Comparator offset error(3)
4
Voffset
20
mV
VDDA = 3.3V
TA = 0 to 50 °C
dThreshold/ Threshold voltage temperature
dt coefficient
V- =VREFINT
,
ppm
/°C
-
15
30
3/4 VREFINT
1/2 VREFINT
1/4 VREFINT
,
,
.
DocID027982 Rev 5
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93
Electrical characteristics
STM32L021x4
Table 59. Comparator 2 characteristics (continued)
Symbol
Parameter
Conditions
Fast mode
Slow mode
Min Typ Max(1) Unit
-
-
3.5
0.5
5
2
ICOMP2
Current consumption(4)
µA
1. Guaranteed by characterization results, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. In TSSOP14 package, where VDDA pin is shared with VDD pin, I/O toggling should be minimized to reach
the values given in the above table. I/O toggling with loaded I/O pins can generate ripple on VDD/VDDA and
degrade the comparator performance.
4. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
6.3.18
Timer characteristics
TIM timer characteristics
The parameters given in the Table 60 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 60. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
1
-
tTIMxCLK
ns
tres(TIM)
Timer resolution time
fTIMxCLK = 32 MHz 31.25
0
-
fTIMxCLK/2
16
MHz
MHz
bit
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 32 MHz
0
ResTIM
Timer resolution
-
-
16
16-bit counter clock
period when internal clock
is selected (timer’s
1
65536
tTIMxCLK
tCOUNTER
fTIMxCLK = 32 MHz 0.0312
2048
µs
prescaler disabled)
-
-
-
65536 × 65536 tTIMxCLK
134.2
tMAX_COUNT Maximum possible count
fTIMxCLK = 32 MHz
s
1. TIMx is used as a general term to refer to the TIM2 and TIM21 timers.
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Electrical characteristics
6.3.19
Communications interfaces
I2C interface characteristics
2
2
I
I
The C interface meets the timings requirements of the C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm) : with a bit rate up to 100 kbit/s
Fast-mode (Fm) : with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.
2
2
I
I
The C timing requirements are guaranteed by design when the C peripheral is properly
configured (refer to the reference manual for details) and when the I2CCLK frequency is
greater than the minimum given in Table 62. The SDA and SCL I/O requirements are met
with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When
configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is
disabled, but is still present. Only FTf I/O pins support Fm+ low level output current
maximum requirement (refer to Section 6.3.13: I/O port characteristics for the I2C I/Os
characteristics).
2
I
All C SDA and SCL I/Os embed an analog filter (see Table 61 for the analog filter
characteristics).
2
I
The analog spike filter is compliant with C timings requirements only for the following
voltage ranges:
•
•
Fast mode Plus: 2.7 V ≤V ≤3.6 V and voltage scaling Range 1
Fast mode:
DD
–
–
2 V ≤V ≤3.6 V and voltage scaling Range 1 or Range 2.
DD
V
< 2 V, voltage scaling Range 1 or Range 2, C
< 200 pF.
load
DD
In other ranges, the analog filter should be disabled. The digital filter can be used instead.
Note:
In Standard mode, no spike filter is required.
(1)
Table 61. I2C analog filter characteristics
Symbol
Parameter
Conditions
Range 1
Min
Max
Unit
260(3)
Maximum pulse width of spikes that
are suppressed by the analog filter
tAF
Range 2
Range 3
50(2)
-
-
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
DocID027982 Rev 5
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93
Electrical characteristics
Symbol
STM32L021x4
Table 62. I2C frequency in all I2C modes
Parameter Condition
Min
Unit
Standard-mode
Fast-mode
2
8
Analog filter ON,
DNF = 0
fI2CCLK
I2C clock frequency
MHz
18
16
Fast-mode Plus
Analog filter OFF,
DNF = 1
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STM32L021x4
Electrical characteristics
SPI characteristics
Unless otherwise specified, the parameters given in the following tables are derived from
tests performed under ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 17.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
(1)
Table 63. SPI characteristics in voltage Range 1
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
16
16
-
-
Slave mode receiver
fSCK
1/tc(SCK)
Slave mode Transmitter
1.71<VDD<3.6V
12(2)
16(2)
70
SPI clock frequency
MHz
-
-
-
-
Slave mode Transmitter
2.7<VDD<3.6V
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
%
tsu(NSS)
th(NSS)
tw(SCKH)
tw(SCKL)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
4Tpclk
2Tpclk
-
-
-
-
SCK high and low time
Data input setup time
Master mode
Tpclk-2 Tpclk Tpclk+2
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
3
3
-
-
-
-
Master mode
3.5
0
-
-
Data input hold time
th(SI)
Slave mode
-
-
ns
ta(SO
Data output access time
Data output disable time
Slave mode
15
10
-
-
36
30
35
20
6
tdis(SO)
Slave mode
-
Slave mode 1.71<VDD<3.6V
Slave mode 2.7<VDD<3.6V
Master mode
14
14
4
-
tv(SO)
Data output valid time
Data output hold time
-
tv(MO)
th(SO)
th(MO)
-
Slave mode
10
3
-
Master mode
-
-
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
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93
Electrical characteristics
STM32L021x4
(1)
Table 64. SPI characteristics in voltage Range 2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
8
Slave mode Transmitter
1.65<VDD<3.6V
fSCK
1/tc(SCK)
8
SPI clock frequency
-
-
MHz
Slave mode Transmitter
2.7<VDD<3.6V
8(2)
70
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
%
tsu(NSS)
th(NSS)
tw(SCKH)
tw(SCKL)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
4Tpclk
2Tpclk
-
-
-
-
SCK high and low time
Data input setup time
Master mode
Tpclk-2 Tpclk Tpclk+2
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
3
3
-
-
-
-
-
-
-
-
6
-
Data input hold time
ns
th(SI)
2
-
ta(SO
Data output access time
Data output disable time
18
12
52
42
tdis(SO)
Slave mode
-
16
33
tv(SO)
Data output valid time
Data output hold time
Master mode
Slave mode
Master mode
-
4
-
6
-
tv(MO)
th(SO)
11
3
-
-
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
90/114
DocID027982 Rev 5
STM32L021x4
Symbol
Electrical characteristics
(1)
Table 65. SPI characteristics in voltage Range 3
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
Slave mode
2
fSCK
1/tc(SCK)
SPI clock frequency
-
-
MHz
2(2)
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
70
%
tsu(NSS)
th(NSS)
tw(SCKH)
tw(SCKL)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2 4Tpclk
Slave mode, SPI presc = 2 2Tpclk
-
-
-
-
SCK high and low time
Data input setup time
Master mode
Tpclk-2
Tpclk
Tpclk+2
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
3
-
-
-
-
-
-
-
-
3
16
14
30
40
-
Data input hold time
ns
th(SI)
-
ta(SO
Data output access time
Data output disable time
70
80
tdis(SO)
Slave mode
-
26.5
47
tv(SO)
Data output valid time
Data output hold time
Master mode
Slave mode
Master mode
-
4
-
6
-
tv(MO)
th(SO)
20
3
-
-
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
DocID027982 Rev 5
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93
Electrical characteristics
STM32L021x4
Figure 28. SPI timing diagram - slave mode and CPHA = 0
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Figure 29. SPI timing diagram - slave mode and CPHA = 1
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
92/114
DocID027982 Rev 5
STM32L021x4
Electrical characteristics
(1)
Figure 30. SPI timing diagram - master mode
+LJK
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
DocID027982 Rev 5
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93
Package information
STM32L021x4
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at http://www.st.com.
®
ECOPACK is an ST trademark.
7.1
LQFP32 package information
Figure 31. LQFP32 - 32-pin, 7 x 7 mm, 32-pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢉꢊꢆꢈ MM
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CCC
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1. Drawing is not to scale.
94/114
DocID027982 Rev 5
STM32L021x4
Package information
Table 66. LQFP32 - 32-pin, 7 x 7 mm, 32-pin low-profile quad flat package
mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.300
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.450
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
-
-
-
1.400
0.370
-
0.0551
0.0146
-
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
-
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
-
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
ccc
k
-
0.100
7°
-
0.0039
7°
0°
3.5°
0°
3.5°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 32. LQFP32 recommended footprint
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ꢈ6?&0?6ꢆ
1. Dimensions are expressed in millimeters.
DocID027982 Rev 5
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110
Package information
STM32L021x4
LQFP32 device marking
The following figure gives an example of topside marking versus pin 1 position identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 33. Example of LQFP32 marking (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Package information
7.2
UFQFPN32 package information
Figure 34. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline
'
$
GGG &
$ꢇ
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&
6($7,1*3/$1(
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H
E
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1. Drawing is not to scale.
2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.
DocID027982 Rev 5
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110
Package information
STM32L021x4
Table 67. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A3
b
0.500
-
0.550
-
0.600
0.050
-
0.0197
-
0.0217
-
0.0236
0.0020
-
-
0.152
0.230
5.000
3.500
3.500
5.000
3.500
3.500
0.500
0.400
-
-
0.0060
0.0091
0.1969
0.1378
0.1378
0.1969
0.1378
0.1378
0.0197
0.0157
-
0.180
4.900
3.400
3.400
4.900
3.400
3.400
-
0.280
5.100
3.600
3.600
5.100
3.600
3.600
-
0.0071
0.1929
0.1339
0.1339
0.1929
0.1339
0.1339
-
0.0110
0.2008
0.1417
0.1417
0.2008
0.1417
0.1417
-
D
D1
D2
E
E1
E2
e
L
0.300
-
0.500
0.080
0.0118
-
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 35. UFQFPN32 recommended footprint
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1. Dimensions are expressed in millimeters.
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Package information
7.3
UFQFPN28 4 x 4 mm package information
Figure 36. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
'HWDLOꢀ<
'
(
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(ꢇ
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1. Drawing is not to scale.
Table 68. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
(1)
package mechanical data
millimeters
Typ
inches
Typ
Symbol
Min
Max
Min
Max
A
A1
D
0.500
-
0.550
0.000
4.000
3.000
4.000
3.000
0.400
0.350
0.152
0.600
0.050
4.100
3.100
4.100
3.100
0.500
0.450
-
0.0197
-
0.0217
0.0000
0.1575
0.1181
0.1575
0.1181
0.0157
0.0138
0.0060
0.0236
0.0020
0.1614
0.1220
0.1614
0.1220
0.0197
0.0177
-
3.900
2.900
3.900
2.900
0.300
0.250
-
0.1535
0.1142
0.1535
0.1142
0.0118
0.0098
-
D1
E
E1
L
L1
T
DocID027982 Rev 5
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110
Package information
STM32L021x4
Table 68. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
(1)
package mechanical data (continued)
millimeters
Typ
inches
Typ
Symbol
Min
Max
Min
Max
b
e
0.200
-
0.250
0.500
0.300
-
0.0079
-
0.0098
0.0197
0.0118
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 37. UFQFPN28 recommended footprint
ꢁꢊꢁꢉ
ꢉꢊꢈꢉ
ꢁꢊꢆꢉ
ꢇꢊꢁꢉ
ꢁꢊꢁꢉ
ꢁꢊꢆꢉ
ꢉꢊꢁꢉ
ꢉꢊꢈꢈ
ꢉꢊꢈꢉ
ꢉꢊꢈꢉ
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1. Dimensions are expressed in millimeters.
100/114
DocID027982 Rev 5
STM32L021x4
Package information
UFQFPN28 device marking
The following figure gives an example of topside marking versus pin 1 position identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 38. Example of UFQFPN28 marking (package top view)
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5
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06Yꢋꢁꢎꢅꢌ9ꢇ
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027982 Rev 5
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110
Package information
STM32L021x4
7.4
UFQFPN20 package information
Figure 39. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
'
(
3LQꢀꢇ
723ꢀ9,(:
/ꢇ
'
'ꢇ
H
GGG
/ꢄ
ꢇꢁ
/ꢅ
$ꢄ
$ꢇ
ꢊ
H
E
(
(ꢇ
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/ꢊ
$
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6,'(ꢀ9,(:
$ꢁ$ꢊB0(B9ꢋ
1. Drawing is not to scale.
Table 69. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
0.500
0.550
0.020
0.152
3.000
2.000
3.000
2.000
0.550
0.350
0.200
0.150
0.600
0.0197
0.0000
-
0.0217
0.0008
0.060
0.0236
0.0020
-
A1
A3
D
0.000
0.050
-
-
2.900
3.100
0.1142
-
0.1181
0.0790
0.1181
0.0790
0.0217
0.0138
0.0079
0.0059
0.1220
-
D1
E
-
-
2.900
3.100
0.1142
-
0.1220
-
E1
L1
L2
L3
L5
-
-
0.500
0.600
0.0197
0.0118
0.0236
0.0157
0.300
0.400
-
-
-
-
102/114
DocID027982 Rev 5
STM32L021x4
Package information
Table 69. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
b
e
0.180
0.250
0.500
-
0.300
-
0.0071
0.0098
0.0197
-
0.0118
-
-
-
-
-
ddd
0.050
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 40. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
!ꢉ!ꢈ?&0?6ꢆ
1. Dimensions are expressed in millimeters.
DocID027982 Rev 5
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110
Package information
STM32L021x4
UFQFPN20 device marking
The following figure gives an example of topside marking versus pin 1 position identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 41. Example of UFQFPN20 marking (package top view)
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LQGHQWLILHU
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
104/114
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STM32L021x4
Package information
7.5
TSSOP20 package information
Figure 42.TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline
'
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N
DDD
&
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H
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1. Drawing is not to scale.
Table 70. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
6.600
6.600
4.500
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.2598
0.2598
0.1772
-
0.050
0.800
0.190
0.090
6.400
6.200
4.300
-
-
0.0020
0.0315
0.0075
0.0035
0.2520
0.2441
0.1693
-
-
1.000
-
0.0394
-
c
-
-
D(2)
6.500
6.400
4.400
0.650
0.600
1.000
0.2559
0.2520
0.1732
0.0256
0.0236
0.0394
E
E1(3)
e
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
DocID027982 Rev 5
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110
Package information
STM32L021x4
Table 70. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
k
0°
-
-
-
8°
0°
-
-
-
8°
aaa
0.100
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
Figure 43. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint
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<$B)3B9ꢇ
1. Dimensions are expressed in millimeters.
106/114
DocID027982 Rev 5
STM32L021x4
Package information
7.6
TSSOP14 package information
Figure 44.TSSOP14 – 14-lead thin shrink small outline, 5.0 x 4.4 mm, 0.65 mm pitch,
package outline
$
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#
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,
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1. Drawing is not to scale.
Table 71. TSSOP14 – 14-lead thin shrink small outline, 5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
5.100
6.600
4.500
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.2008
0.2598
0.1772
-
0.050
0.800
0.190
0.090
4.900
6.200
4.300
-
-
0.0020
0.0315
0.0075
0.0035
0.1929
0.2441
0.1693
-
-
1.000
-
0.0394
-
c
-
-
D
5.000
6.400
4.400
0.650
0.600
1.000
-
0.1969
0.2520
0.1732
0.0256
0.0236
0.0394
-
E
E1
e
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
8°
0°
8°
aaa
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
DocID027982 Rev 5
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110
Package information
STM32L021x4
TSSOP14 device marking
The following figure gives an example of topside marking versus pin 1 position identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 45. Example of TSSOP14 marking (package top view)
3URGXFWꢀLGHQWLILFDWLRQꢑꢇꢒ
/ꢂꢁꢃ'ꢄ3ꢅ
'DWHꢀFRGH 5HYLVLRQꢀFRGH
< :: 5
3LQꢀꢇꢀ
LQGHQWLILHU
06Yꢋꢁꢎꢅꢍ9ꢇ
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
7.7
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in ° C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
108/114
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STM32L021x4
Package information
Table 72. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
60
LQFP32 - 7 x 7 mm / 0.8 mm pitch
Thermal resistance junction-ambient
39
97
UFQFPN32 - 5 x 5 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFQFPN28 - 4 x 4 mm, 0.5 mm pitch
Thermal resistance junction-ambient
Θ
102
74
°C/W
JA
UFQFPN20 - 3 x 3 mm, 0.5 mm pitch
Thermal resistance junction-ambient
TSSOP20 - 169 mils
Thermal resistance junction-ambient
95
TSSOP14 - 169 mils
Figure 46. Thermal resistance
/4)31ꢄꢅ
84)1ꢄꢅ
8)4)31ꢅꢎ
76623ꢅꢁ
3'ꢀꢑP:ꢒ
7HPSHUDWXUHꢀꢑ&ꢒ
06Yꢄꢍꢎꢌꢄ9ꢇ
1. The above curves are valid for range 3.
7.7.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID027982 Rev 5
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110
Ordering information
STM32L021x4
8
Ordering information
Table 73. STM32L021x4 ordering information scheme
STM32 L 021
Example:
K
4
T
6
D xxx
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
L = Low power
Device subfamily
021 = Access line with AES
Pin count
K = 32 pins
G = 28 pins
F = 20 pins
D = 14 pins
Flash memory size
4 = 16 Kbytes
Package
T = LQFP
U = UFQFPN
P = TSSOP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
3 = Industrial temperature range, –40 to 125 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
110/114
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STM32L021x4
Revision history
9
Revision history
Table 75. Document revision history
Date
Revision
Changes
07-Dec-2015
1
Initial release.
Features: modified current consumption in run mode,
®
Cortex -M0+ core frequency range and total number of timers.
Updated ADC conversion consumption on cover page.
Updated ADC conversion consumption on cover page.
Updated UFQFPN28 pinout: Figure 5: STM32L021x4
UFQFPN28 pinout and Table 12: Pin definitions.
11-Feb-2016
2
Updated Table 54: RAIN max for fADC = 16 MHz.
Modified TS_CAL2 description in Table 56: Temperature
sensor calibration values.
Added Section : UFQFPN20 device marking, Section :
TSSOP14 device marking and Section : UFQFPN28
device marking.
Changed minimum comparator supply voltage to 1.65 V
on cover page.
Added baudrate allowing to wake up the MCU from Stop
mode in Section 3.16.3: Low-power universal
asynchronous receiver transmitter (LPUART).
Added number of fast and standard channels in
Section 3.10: Analog-to-digital converter (ADC).
Updated Table 15: Current characteristics to add the
total output current for STM32L021GxUx.
Changed VDDA minimum value to 1.65 V in Table 17:
General operating conditions.
Updated Table 25: Current consumption in Sleep mode,
Table 26: Current consumption in Low-power Run
mode, Table 27: Current consumption in Low-power
Sleep mode and Table 29: Typical and maximum current
consumptions in Standby mode.
17-Mar-2016
3
Section 6.3.15: 12-bit ADC characteristics:
– Table 53: ADC characteristics:
Distinction made between VDDA for fast and standard
channels; added note 1.
Updated condition for fTRIG measurement.
Added note 4. related to RADC and removed
measurement condition.
Updated tS and tCONV
.
– Updated equation 1 description.
– Updated Table 54: RAIN max for fADC = 16 MHz for
fADC = 16 MHz and distinction made between fast and
standard channels.
– Updated measurement condition in Table 55: ADC
accuracy.
Added Table 63: USART/LPUART characteristics.
DocID027982 Rev 5
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113
Revision history
STM32L021x4
Table 75. Document revision history
Date
Revision
Changes
Updated:
– Features in cover page: Stop mode values, number of
DMA channels, number of I/Os, number of
communication peripherals.
20-Jun-2016
4
– Table 26: Current consumption in Low-power Run
mode, Table 27: Current consumption in Low-power
Sleep mode, Table 33: Low-power mode wakeup
timings, Table 35: Low-speed external user clock
characteristics
Removed I/O operation from Table 2: Functionalities
depending on the operating power supply range.
Updated Section 3.4.4: Boot modes and added Note 7.
in Table 12: Pin definitions.
Changed USARTx_RTS and LPUARTx_RTS into
USARTx_RTS_DE and LPUARTx_RTS_DE,
respectively in Section 4: Pin descriptions.
In Section 5: Memory mapping, replaced memory
mapping schematic by reference to the reference
manual.
Updated introduction text in Section 6.2: Absolute
maximum ratings to mention device mission profile and
extended mission profiles.
Added note in Table 48: I/O current injection
susceptibility.
Updated minimum and maximum values of I/O weak
pull-up equivalent resistor (RPU) and weak pull-down
12-Sep-2017
5
equivalent resistor (RPD) in Table 49: I/O static
characteristics.
Updated minimum and maximum values of NRST weak
pull-up equivalent resistor (RPU) in Table 52: NRST pin
characteristics. Added note 2 related to the position of
the external capacitor below Figure 25: Recommended
NRST pin protection.
Updated Section : I2C interface characteristics.
Removed section USART/LPUART characteristics.
Updated Figure 28: SPI timing diagram - slave mode
and CPHA = 0, Figure 29: SPI timing diagram - slave
mode and CPHA = 1(1) and Figure 30: SPI timing
diagram - master mode(1).
112/114
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STM32L021x4
Revision history
Table 75. Document revision history
Date
Revision
Changes
In Section 7: Package information:
– Added paragraph related to optional marking or
inset/upset marks in all device marking sections.
– Updated Table 66: LQFP32 - 32-pin, 7 x 7 mm, 32-pin
low-profile quad flat package mechanical data.
– Updated Figure 34: UFQFPN32 - 32-pin, 5x5 mm,
0.5 mm pitch ultra thin fine pitch quad flat package
outline and Table 67: UFQFPN32 - 32-pin, 5x5 mm,
0.5 mm pitch ultra thin fine pitch quad flat package
mechanical data.
– Updated Figure 39: UFQFPN20 - 20-lead, 3x3 mm,
0.5 mm pitch, ultra thin fine pitch quad flat package
outline and Table 70: UFQFPN20 - 20-lead, 3x3 mm,
0.5 mm pitch, ultra thin fine pitch quad flat package
mechanical data.
12-Sep-2017
5 (continued)
– Added notes related to D and E1 in Table 71:
TSSOP20 – 20-lead thin shrink small outline, 6.5 x
4.4 mm, 0.65 mm pitch, package mechanical data.
– Updated Figure 44: TSSOP14 – 14-lead thin shrink
small outline, 5.0 x 4.4 mm, 0.65 mm pitch, package
outline and Table 71: TSSOP20 – 20-lead thin shrink
small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package
mechanical data
– Added notes related to D and E1 in Table 71:
TSSOP20 – 20-lead thin shrink small outline, 6.5 x
4.4 mm, 0.65 mm pitch, package mechanical data.
Section 8 renamed into Ordering information.
DocID027982 Rev 5
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113
STM32L021x4
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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STM32L021G4P3DTR
Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM32L021G4P6DTR
Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM32L021G4P7DTR
Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM32L021G4T3DTR
Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32L021G4T6DTR
Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
STM32L021G4T7DTR
Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
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