STM32L073RBH7DTR [STMICROELECTRONICS]
Ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, up to 192KB Flash, 20KB SRAM, 6KB EEPROM, LCD, USB, ADC, DACs;
| 型号： | STM32L073RBH7DTR |
| 厂家： | 
ST |
| 描述： | Ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, up to 192KB Flash, 20KB SRAM, 6KB EEPROM, LCD, USB, ADC, DACs 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 CD 静态存储器 |
| 文件： | 总157页 (文件大小：2182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32L073x8 STM32L073xB
STM32L073xZ
®
®
Ultra-low-power 32-bit MCU Arm -based Cortex -M0+, up to 192KB
Flash, 20KB SRAM, 6KB EEPROM, LCD, USB, ADC, DACs
Datasheet - production data
Features
FBGA
FBGA
• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
UFQFPN48
–
-40 to 125 °C temperature range
UFBGA100
7x7 mm
LQFP48 (7 x 7 mm)
LQFP64 (10x10 mm)
LQFP100 (14x14 mm)
(7x7 mm)
TFBGA64
5x5 mm
– 0.29 µA Standby mode (3 wakeup pins)
– 0.43 µA Stop mode (16 wakeup lines)
– 0.86 µA Stop mode + RTC + 20-Kbyte
RAM retention
– Down to 93 µA/MHz in Run mode
WLCSP49
(3.294x3.258 mm)
– 5 µs wakeup time (from Flash memory)
– 41 µA 12-bit ADC conversion at 10 ksps
• Pre-programmed bootloader
– USB, USART supported
• Development support
®
®
• Core: Arm 32-bit Cortex -M0+ with MPU
– From 32 kHz up to 32 MHz max.
– 0.95 DMIPS/MHz
– Serial wire debug supported
• Memories
• LCD driver for up to 4x52 or 8x48 segments
– Support contrast adjustment
– Support blinking mode
– Up to 192-Kbyte Flash memory with ECC
(2 banks with read-while-write capability)
– 20-Kbyte RAM
– Step-up converted on board
– 6 Kbytes of data EEPROM with ECC
– 20-byte backup register
• Rich Analog peripherals
– 12-bit ADC 1.14 Msps up to 16 channels
(down to 1.65 V)
– Sector protection against R/W operation
• Up to 84 fast I/Os (78 I/Os 5V tolerant)
• Reset and supply management
– 2 x 12-bit channel DACs with output buffers
(down to 1.8 V)
– Ultra-safe, low-power BOR (brownout
reset) with 5 selectable thresholds
– 2x ultra-low-power comparators (window
mode and wake up capability, down to
1.65 V)
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock sources
• Up to 24 capacitive sensing channels
supporting touchkey, linear and rotary touch
sensors
– 1 to 25 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
• 7-channel DMA controller, supporting ADC,
– High speed internal 16 MHz factory-
trimmed RC (+/- 1%)
SPI, I2C, USART, DAC, Timers
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz RC
– Internal self calibration of 48 MHz RC for
USB
– PLL for CPU clock
August 2020
DS10685 Rev 6
1/157
This is information on a product in full production.
www.st.com
STM32L073xx
• 11x peripheral communication interfaces
• 11x timers: 2x 16-bit with up to 4 channels, 2x
16-bit with up to 2 channels, 1x 16-bit ultra-low-
power timer, 1x SysTick, 1x RTC, 2x 16-bit
basic for DAC, and 2x watchdogs
– 1x USB 2.0 crystal-less, battery charging
detection and LPM
– 4x USART (2 with ISO 7816, IrDA), 1x
UART (low power)
(independent/window)
• CRC calculation unit, 96-bit unique ID
• True RNG and firewall protection
• All packages are ECOPACK2
– Up to 6x SPI 16 Mbits/s
– 3x I2C (2 with SMBus/PMBus)
Table 1. Device summary
Reference
Part number
STM32L073x8
STM32L073xB
STM32L073xZ
STM32L073V8
STM32L073VB, STM32L073RB, STM32L073CB
STM32L073VZ, STM32L073RZ, STM32L073CZ
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Contents
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
3.2
3.3
3.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4.1
3.4.2
3.4.3
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5
3.6
3.7
3.8
3.9
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 28
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.11 Liquid crystal display (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.12 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.13 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.13.1 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
REFINT
3.13.2
V
voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LCD
3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.15 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 32
3.16 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.17.1 General-purpose timers (TIM2, TIM3, TIM21 and TIM22) . . . . . . . . . . . 34
3.17.2 Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.17.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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STM32L073xx
3.17.4 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.17.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.17.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.18 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.18.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.18.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 37
3.18.3 Low-power universal asynchronous receiver transmitter (LPUART) . . . 37
3.18.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 38
3.18.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.19 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.20 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 39
3.21 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4
5
6
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Embedded reset and power control block characteristics . . . . . . . . . . . 71
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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Contents
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.16 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.18 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.21 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.8.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
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List of tables
STM32L073xx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ultra-low-power STM32L073xxx device features and peripheral counts . . . . . . . . . . . . . . 13
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 19
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 19
Functionalities depending on the working mode
(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM32L073xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Capacitive sensing GPIOs available on STM32L073xx devices . . . . . . . . . . . . . . . . . . . . 33
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
2
STM32L073xx I C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STM32L073xx pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Alternate functions port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Alternate functions port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Alternate functions port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Alternate functions port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Alternate functions port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Alternate functions port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 71
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Current consumption in Run mode, code with data processing running from
Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Current consumption in Run mode vs code type,
Table 31.
code with data processing running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Current consumption in Run mode, code with data processing running from RAM . . . . . . 76
Current consumption in Run mode vs code type,
Table 32.
Table 33.
code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 82
Average current consumption during Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Peripheral current consumption in Run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 86
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
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List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 96
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
R
max for f
= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
AIN
ADC
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
Table 83.
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 133
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
Table 84.
Table 85.
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
Table 86.
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 139
WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
Table 87.
Table 88.
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 143
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 145
UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Table 89.
Table 90.
Table 91.
DS10685 Rev 6
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8
List of tables
STM32L073xx
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 92.
Table 93.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32L073xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32L073xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STM32L073xx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STM32L073xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STM32L073xx TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STM32L073xx WLCSP49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STM32L073xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32L073xx UFQFPN48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 12. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 13. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 15. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSE, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 17. IDD vs VDD, at TA= 25 °C, Low-power run mode, code running
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 18. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 19. IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled,
all clocks OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 22. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 24. HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 25. VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 26. VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 27. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 29. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 30. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 31. Power supply and reference decoupling (V
Figure 32. Power supply and reference decoupling (V
not connected to V
) . . . . . . . . . . . . 110
). . . . . . . . . . . . . . . . 111
REF+
DDA
connected to V
REF+
DDA
Figure 33. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 34. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
(1)
Figure 35. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
(1)
Figure 36. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2
(1)
Figure 37. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2
(1)
Figure 38. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 39. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 40. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 129
Figure 41. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 42. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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List of figures
STM32L073xx
Figure 43. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 44. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 45. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 46. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 135
Figure 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 136
Figure 48. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 49. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 50. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
,grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 51. TFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 52. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 53. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 54. WLCSP49 marking example (package top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 55. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 144
Figure 56. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 145
Figure 57. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 58. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 59. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 60. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 61. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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Introduction
1
Introduction
The ultra-low-power STM32L073xx are offered in 7 different package types from 48 to 100
pins. Depending on the device chosen, different sets of peripherals are included, the
description below gives an overview of the complete range of peripherals proposed in this
family.
These features make the ultra-low-power STM32L073xx microcontrollers suitable for a wide
range of applications:
•
•
•
•
•
Gas/water meters and industrial sensors
Healthcare and fitness equipment
Remote control and user interface
PC peripherals, gaming, GPS equipment
Alarm system, wired and wireless sensors, video intercom
This STM32L073xx datasheet should be read in conjunction with the STM32L0x3xx
reference manual (RM0367).
®(a)
For information on the Arm
Cortex®-M0+ core please refer to the Cortex®-M0+ Technical
Reference Manual, available from the www.arm.com website.
Figure 1 shows the general block diagram of the device family.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS10685 Rev 6
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39
Description
STM32L073xx
2
Description
The ultra-low-power STM32L073xx microcontrollers incorporate the connectivity power of
the universal serial bus (USB 2.0 crystal-less) with the high-performance Arm Cortex-M0+
32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-
speed embedded memories (up to 192 Kbytes of Flash program memory,
6 Kbytes of data
EEPROM and 20 Kbytes of RAM) plus an extensive range of enhanced I/Os and
peripherals.
The STM32L073xx devices provide high power efficiency for a wide range of performance.
It is achieved with a large choice of internal and external clock sources, an internal voltage
adaptation and several low-power modes.
The STM32L073xx devices offer several analog features, one 12-bit ADC with hardware
oversampling, two DACs, two ultra-low-power comparators, several timers, one low-power
timer (LPTIM), four general-purpose 16-bit timers and two basic timer, one RTC and one
SysTick which can be used as timebases. They also feature two watchdogs, one watchdog
with independent clock and window capability and one window watchdog based on bus
clock.
Moreover, the STM32L073xx devices embed standard and advanced communication
interfaces: up to three I2Cs, two SPIs, one I2S, four USARTs, a low-power UART
(LPUART), and a crystal-less USB. The devices offer up to 24 capacitive sensing channels
to simply add touch sensing functionality to any application.
The STM32L073xx also include a real-time clock and a set of backup registers that remain
powered in Standby mode.
Finally, their integrated LCD controller has a built-in LCD voltage generator that allows to
drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.
The ultra-low-power STM32L073xx devices operate from a 1.8 to 3.6 V power supply (down
to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR
option. They are available in the -40 to +125 °C temperature range. A comprehensive set of
power-saving modes allows the design of low-power applications.
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Description
2.1
Device overview
Table 2. Ultra-low-power STM32L073xxx device features and peripheral counts
STM32L073 STM32L073 STM32L073 STM32L073 STM32L073 STM32L073 STM32L073
Peripheral
V8
CB
VB
RB
CZ
VZ
RZ
Flash (Kbytes)
64 Kbytes
3 Kbytes
128 Kbytes
192 Kbytes
Data EEPROM (Kbytes)
RAM (Kbytes)
6 Kbytes
20 Kbytes
4
General-
purpose
Timers
Basic
2
LPTIMER
RTC/SYSTICK/IWDG/WWDG
SPI/I2S
1
1/1/1/1
6(4)(1)/1
3
I2C
Commu-
nication
USART
4
interfaces
LPUART
1
USB/(VDD_USB)
1/(1)
51(2)
GPIOs
84
37
84
37(3)
84
51(2)
Clocks:
HSE/LSE/HSI/MSI/LSI
1/1/1/1/1
12-bit synchronized ADC
Number of channels
1
16
1
10
1
1
1
16(2)
10(3)
16(2)
12-bit DAC
Number of channels
2
2
1
1
1
1
1
LCD
COM x SEG
1
4x18
1
4x52 or
8x48
4x52 or
8x48
4x32 or
8x28(2)
4x18 or
4x21(3)
4x32 or
8x28(2)
4x52 or 8x48
Comparators
2
Capacitive sensing
channels
24
17
24
24(2)
17(3)
24
24(2)
Max. CPU frequency
Operating voltage
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 to 3.6 V without BOR option
Ambient temperature: –40 to +125 °C
Junction temperature: –40 to +130 °C
Operating temperatures
Packages
LQFP48,
UFQFPN48,
WLCSP49
LQFP100,
LQFP100,
LQFP100,
LQFP48,
UFQFPN48
LQFP64,
LQFP64,
TFBGA64
TFBGA64
UFBGA100
UFBGA100
UFBGA100
1. 4 SPI interfaces are USARTs operating in SPI master mode.
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Description
STM32L073xx
2. TFBGA64 has one GPIO, one ADC input, one capacitive sensing channel and one COMxSEG (4x31 or 8x27) less than
LQFP64.
3. LQFP48 has three GPIOs, three ADC channels, two capacitive sensing channel and three COMxSEG (4x18) less than
WLCSP49.
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DS10685 Rev 6
STM32L073xx
Description
Figure 1. STM32L073xx block diagram
Temp
sensor
SWD
SWD
FLASH
EEPROM
BOOT
ADC1
SPI1
AINx
MISO, MOSI,
SCK, NSS
FIREWALL
CORTEX M0+ CPU
Fmax:32MHz
RAM
RX, TX, RTS,
CTS, CK
USART1
TIM21
MPU
A
P
B
2
DBG
EXTI
DMA1
2ch
NVIC
TIM22
COMP1
COMP2
2ch
BRIDGE
INP, INM, OUT
INP, INM, OUT
TSC
CRC
RNG
GPIO PORT A
PA[0:15]
PB[0:15]
PC[0:15]
GPIO PORT B
GPIO PORT C
IN1, IN2,
ETR, OUT
LPTIM1
BRIDGE
RAM 1K
TIM6
DP, DM, OE,
CRS_SYNC,
VDD_USB
USB 2.0 FS
GPIO PORT D
GPIO PORT E
PD[0:15]
PE[0:15]
DAC1
DAC2
I2C1
OUT1
OUT1
TIM7
SCL, SDA,
SMBA
WWDG
GPIO PORT H
PH[0:1], [9:10]
I2C2
I2C3
SCL, SDA
SCL, SDA,
SMBA
A
P
B
1
RX, TX, RTS,
CTS, CK
USART2
USART4
HSI 48M
LSI
CRS
IWDG
RTC
OSC_IN,
OSC_OUT
RX, TX, RTS,
CTS, CK
HSE
PLL
HSI 16M
RX, TX, RTS,
CTS, CK
RX, TX, RTS,
CTS
USART5
MSI
LPUART1
MISO/MCK,
MOSI/SD,
SCK/CK, NSS/
WS
SPI2/I2S
TIM2
BCKP REG
WKUPx
RESET & CLK
4ch
OSC32_IN,
LSE
TIM3
LCD
4ch
OSC32_OUT
PVD_IN
VREF_OUT
COMx, SEGx,
LCD_VLCDx
PMU
NRST
VDDA
REGULATOR
VDD
MSv35410V1
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Description
STM32L073xx
2.2
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary
core up to Arm® Cortex®-M4, including Arm® Cortex®-M3 and Arm® Cortex®-M0+. The
STM32Lx series are the best choice to answer your needs in terms of ultra-low-power
features. The STM32 ultra-low-power series are the best solution for applications such as
gaz/water meter, keyboard/mouse or fitness and healthcare application. Several built-in
features like LCD drivers, dual-bank memory, low-power run mode, operational amplifiers,
128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly
cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and
long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all
STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other
hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to
respond to the latest market feature and efficiency requirements.
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DS10685 Rev 6
STM32L073xx
Functional overview
3
Functional overview
3.1
Low-power modes
The ultra-low-power STM32L073xx support dynamic voltage scaling to optimize its power
consumption in Run mode. The voltage from the internal low-drop regulator that supplies
the logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.
There are three power consumption ranges:
•
•
•
Range 1 (V range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz
DD
Range 2 (full V range), with a maximum CPU frequency of 16 MHz
DD
Range 3 (full V range), with a maximum CPU frequency limited to 4.2 MHz
DD
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the low-
speed clock (max 131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In Low-
power run mode, the clock frequency and the number of enabled peripherals are both
limited.
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the Run
mode with the regulator on.
Stop mode with RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the V
domain are stopped, the
CORE
PLL, MSI RC, HSE crystal and HSI RC oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the
processor can serve the interrupt or resume the code. The EXTI line source can be any
GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event
(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup
events, the USB/USART/I2C/LPUART/LPTIMER wakeup events.
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Functional overview
STM32L073xx
•
Stop mode without RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and
LSE crystal oscillators are disabled.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The voltage regulator is in the low-power mode. The device can be woken up from Stop
mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or
resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the
comparator 1 event or comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB/USART/I2C/LPUART/LPTIMER wakeup events.
•
Standby mode with RTC
The Standby mode is used to achieve the lowest power consumption and real time
clock. The internal voltage regulator is switched off so that the entire V
domain is
CORE
powered off. The PLL, MSI RC, HSE crystal and HSI RC oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•
Standby mode without RTC
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire V
domain is powered off. The
CORE
PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off.
After entering Standby mode, the RAM and register contents are lost except for
registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz
oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode. The LCD is not stopped automatically by entering Stop
mode.
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STM32L073xx
Functional overview
Table 3. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply
range
Operating power supply
range(1)
DAC and ADC
operation
Dynamic voltage
scaling range
USB
ADC only, conversion
time up to 570 ksps
Range 2 or
range 3
V
DD = 1.65 to 1.71 V
Not functional
Functional(3)
Functional(3)
Functional(3)
Functional(3)
ADC only, conversion
time up to 1.14 Msps
Range 1, range 2 or
range 3
VDD = 1.71 to 1.8 V(2)
VDD = 1.8 to 2.0 V(2)
VDD = 2.0 to 2.4 V
VDD = 2.4 to 3.6 V
Conversion time up to
1.14 Msps
Range1, range 2 or
range 3
Conversion time up to
1.14 Msps
Range 1, range 2 or
range 3
Conversion time up to
1.14 Msps
Range 1, range 2 or
range 3
1. GPIO speed depends on VDD voltage range. Refer to Table 62: I/O AC characteristics for more information
about I/O speed.
2. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5
μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2
MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.
3. To be USB compliant from the I/O voltage standpoint, the minimum VDD_USB is 3.0 V.
Table 4. CPU frequency range depending on dynamic voltage scaling
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
Range 3
32 kHz to 4.2 MHz (0ws)
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Functional overview
STM32L073xx
Standby
Table 5. Functionalities depending on the working mode
(1)(2)
(from Run/active down to standby)
Stop
Low-
power
run
Low-
power
sleep
IPs
Run/Active
Sleep
Wakeup
capability
Wakeup
capability
CPU
Y
O
Y
Y
O
--
O
Y
Y
O
Y
O
Y
Y
O
--
O
Y
Y
O
--
--
Y
Y
--
--
--
--
Y
--
Flash memory
RAM
Backup registers
EEPROM
Brown-out reset
(BOR)
O
O
O
O
O
O
O
O
O
--
O
O
--
O
DMA
Programmable
Voltage Detector
(PVD)
O
O
O
O
O
O
Y
-
Power-on/down
reset (POR/PDR)
Y
O
O
O
O
O
Y
Y
O
O
O
O
O
Y
Y
--
O
O
O
Y
Y
Y
--
O
O
O
Y
Y
Y
Y
--
--
O
O
--
--
Y
High Speed
Internal (HSI)
(3)
High Speed
External (HSE)
--
O
O
--
Y
Low Speed Internal
(LSI)
Low Speed
External (LSE)
Multi-Speed
Internal (MSI)
Inter-Connect
Controller
RTC
O
O
O
O
O
O
O
O
O
O
O
O
O
O
RTC Tamper
O
O
Auto WakeUp
(AWU)
O
O
O
O
O
O
O
LCD
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
--
O
O
O
--
--
O
--
O
--
--
--
--
--
--
--
--
USB
O
O
O
USART
LPUART
SPI
O
O
O
--
O(4)
O(4)
--
I2C
O(5)
O
ADC
--
--
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Functional overview
Standby
Table 5. Functionalities depending on the working mode
(1)(2)
(from Run/active down to standby) (continued)
Stop
Low-
power
run
Low-
power
sleep
IPs
Run/Active
Sleep
Wakeup
Wakeup
capability
capability
DAC
O
O
O
O
O
O
O
O
O
O
--
--
Temperature
sensor
Comparators
16-bit timers
LPTIMER
IWDG
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
--
O
--
--
O
O
--
O
O
O
--
O
WWDG
Touch sensing
controller (TSC)
O
O
--
--
--
--
--
SysTick Timer
GPIOs
O
O
O
O
O
O
O
O
O
O
2 pins
50 µs
Wakeup time to
Run mode
0 µs
0.36 µs
3 µs
32 µs
3.5 µs
0.4 µA (No
0.28 µA (No
RTC) VDD=1.8 V RTC) VDD=1.8 V
0.8 µA (with 0.65 µA (with
RTC) VDD=1.8 V RTC) VDD=1.8 V
Down to
140 µA/MHz
(from Flash
memory)
Down to
37 µA/MHz
(from Flash
memory)
Consumption
Down to Down to
8 µA 4.5 µA
VDD=1.8 to 3.6 V
0.4 µA (No
0.29 µA (No
(Typ)
RTC) VDD=3.0 V RTC) VDD=3.0 V
1 µA (with RTC)
DD=3.0 V
0.85 µA (with
RTC) VDD=3.0 V
V
1. Legend:
“Y” = Yes (enable).
“O” = Optional can be enabled/disabled by software)
“-” = Not available
2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes.
3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
4. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup
on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep
running the HSI clock.
5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.
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Functional overview
STM32L073xx
3.2
Interconnect matrix
Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.
Table 6. STM32L073xx peripherals interconnect matrix
Low-
Low-
Interconnect Interconnect
Interconnect action
Run Sleep power power Stop
source
destination
run
sleep
Timer input channel,
trigger from analog
signals comparison
TIM2,TIM21,
TIM22
Y
Y
Y
Y
Y
Y
-
COMPx
Timer input channel,
trigger from analog
signals comparison
LPTIM
Y
Y
Y
Timer triggered by other
timer
TIMx
RTC
TIMx
TIM21
LPTIM
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Timer triggered by Auto
wake-up
Timer triggered by RTC
event
Y
Clock source used as
input channel for RC
measurement and
trimming
All clock
source
TIMx
Y
Y
Y
Y
Y
-
Y
-
-
-
the clock recovery
system trims the HSI48
based on USB SOF
CRS/HSI48
USB
USB_SOF is channel
input for calibration
TIM3
TIMx
Y
Y
Y
Y
-
-
-
-
Timer input channel and
trigger
Y
Y
GPIO
Timer input channel and
trigger
LPTIM
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
ADC,DAC
Conversion trigger
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DS10685 Rev 6
STM32L073xx
Functional overview
3.3
Arm® Cortex®-M0+ core with MPU
The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:
•
•
•
•
•
•
a simple architecture that is easy to learn and program
ultra-low power, energy-efficient operation
excellent code density
deterministic, high-performance interrupt handling
upward compatibility with Cortex-M processor family
platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-
bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded Arm core, the STM32L073xx are compatible with all Arm tools and
software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L073xx embed a nested vectored interrupt controller able to
handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
•
•
•
includes a Non-Maskable Interrupt (NMI)
provides zero jitter interrupt option
provides four interrupt priority levels
The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart load-
multiple and store-multiple operations. Interrupt handlers do not require any assembler
wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also
significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to enter rapidly stop or standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
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39
Functional overview
STM32L073xx
3.4
Reset and supply management
3.4.1
Power supply schemes
•
•
•
V
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
DD
externally through V pins.
DD
V
, V
= 1.65 to 3.6 V: external analog power supplies for ADC reset blocks, RCs
DDA
SSA
and PLL. V
and V
must be connected to V and V , respectively.
DDA
SSA DD SS
V
= 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11)
DD_USB
and USB_DP (PA12). To guarantee a correct voltage level for USB communication
must be above 3.0V. If USB is not used this pin must be tied to V or V .
SS
V
DD_USB
DD
On packages without VDD_USB pin, V
voltage.
voltage is internally connected to V
DD_USB
DD
3.4.2
Power supply supervisor
The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
Two versions are available:
•
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
The other version without BOR operates between 1.65 V and 3.6 V.
After the V threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
DD
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on V at least 1 ms after it exits
DD
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
) in Stop mode. The device remains in reset mode when
REFINT
V
is below a specified threshold, V
or V
, without the need for any external
DD
POR/PDR
BOR
reset circuit.
Note:
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The devices feature an embedded programmable voltage detector (PVD) that monitors the
V
power supply and compares it to the V
threshold. This PVD offers 7 different
DD/VDDA
PVD
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V drops below the V threshold and/or when
DD/VDDA
PVD
V
is higher than the V
threshold. The interrupt service routine can then generate
DD/VDDA
PVD
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
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Functional overview
3.4.3
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
•
•
•
MR is used in Run mode (nominal regulation)
LPR is used in the Low-power run, Low-power sleep and Stop modes
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).
3.5
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
•
•
•
Clock prescaler
To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.
Safe clock switching
Clock sources can be changed safely on the fly in Run mode through a configuration
register.
Clock management
To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.
System clock source
Three different clock sources can be used to drive the master clock SYSCLK:
–
–
1-25 MHz high-speed external crystal (HSE), that can supply a PLL
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLLMultispeed internal RC oscillator (MSI), trimmable by software, able
to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1
MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE),
the MSI frequency can be trimmed by software down to a ±0.5% accuracy.
•
Auxiliary clock source
Two ultra-low-power clock sources that can be used to drive the LCD controller and the
real-time clock:
–
–
32.768 kHz low-speed external crystal (LSE)
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
•
•
RTC and LCD clock source
The LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever
the system clock.
USB clock source
A 48 MHz clock trimmed through the USB SOF or LSE supplies the USB interface.
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Functional overview
STM32L073xx
•
Startup clock
After reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.
•
Clock security system (CSS)
This feature can be enabled by software. If an HSE clock failure occurs, the master
clock is automatically switched to HSI and a software interrupt is generated if enabled.
Another clock security system can be enabled, in case of failure of the LSE it provides
an interrupt or wakeup event which is generated if enabled.
•
Clock-out capability (MCO: microcontroller clock output)
It outputs one of the internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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Functional overview
Figure 2. Clock tree
@V33
Enable Watchdog
Legend:
Watchdog LS
LSI RC
LSI tempo
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low-speed external clock signal
MSI = Multispeed internal clock signal
RTCSEL
RTC2 enable
RTC
LSE OSC
LSE tempo
LCD enable
LSU LSD LSD LSD
1 MHz
@V18
LCDCLK
MCOSEL
@V33
ADC enable
ADCCLK
LSI
MSI RC
LSE
MSI
Level shifters
@V18
MCO
not deepsleep
/ 1,2,4,8,16
/ 2,4,8,16
CK_PWR
@V33
not deepsleep
HSI16 RC
Level shifters
@V18
ck_rchs
HSI16
/ 1,4
FCLK
not (sleep or
deepsleep)
System
Clock
HCLK
not (sleep or
deepsleep)
/ 8
MSI
HSI16
HSE
SysTick
Timer
@V33
AHB
HSE OSC
Level shifters
@V18
PRESC
PCLK1 to APB1
peripherals
/ 1,2,…, 512
32 MHz
max.
PLLSRC
@V3P3 LLCLK
APB1
PRESC
ck_pllin
PLL
/ 1,2,4,8,16
LSU
LSD
X
Peripheral
@V33
3,4,6,8,12,16,
24,32,48
clock enable
to TIMx
1 MHz Clock
Detector
If (APB1 presc=1) x1
else x2)
/ 2,3,4
Level shifters
@VDDCORE
Peripheral
clock enable
HSE present or not
Clock
Source
Control
PCLK2 to APB2
peripherals
32 MHz
max.
Dedicated 48MHz PLL output
HSI48MSEL
APB2
PRESC
/ 1,2,4,8,16
Peripheral
clock enable
@V33
to TIMx
RC 48MHz
Level shifters
If (APB2 presc=1) x1
HSI48
else x2)
@V18
Peripheral
LSI
clock enable
SYSCLK
Clock
Recovery
System
LPTIMCLK
Peripheral
clock enable
LSE
HSI16
LPUART/
UARTCLK
Peripheral
clock enable
PCLK
I2CCLK
usb_en
rng_en
48MHz
USBCLK
48MHz RNG
MSv35411V1
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Functional overview
STM32L073xx
3.6
Low-power real-time clock and backup registers
The real time clock (RTC) and the 5 backup registers are supplied in all modes including
standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
•
•
•
•
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
Two programmable alarms with wake up from Stop and Standby mode capability
Periodic wakeup from Stop and Standby with programmable resolution and period
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 37 kHz)
The high-speed external clock
3.7
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 29 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 84 GPIOs can be connected
to the 16 configurable interrupt/event lines. The 13 other lines are connected to PVD, RTC,
USB, USARTs, I2C, LPUART, LPTIMER or comparator events.
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Functional overview
3.8
Memories
The STM32L073xx devices have the following features:
•
20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
–
–
64, 128 or 192 Kbytes of embedded Flash program memory
6 Kbytes of data EEPROM
Information block containing 32 user and factory options bytes plus 8 Kbytes of
system memory
Flash program and data EEPROM are divided into two banks. This allows writing in one
bank while running code or reading data from the other bank.
The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:
•
•
Level 0: no protection
Level 1: memory readout protected.
The Flash memory cannot be read from or written to if either debug features are
connected or boot in RAM is selected
•
Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)
The firewall protects parts of code/data from access by the rest of the code that is executed
outside of the protected area. The granularity of the protected code segment or the non-
volatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the
volatile data segment (RAM).
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.9
Boot modes
At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:
•
•
•
Boot from Flash memory
Boot from System memory
Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USB (PA11, PA12), USART1(PA9, PA10) or USART2(PA2, PA3). See STM32
microcontroller system memory boot mode AN2606 for details.
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Functional overview
STM32L073xx
3.10
Direct memory access (DMA)
The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
2
The DMA can be used with the main peripherals: SPI, I C, USART, LPUART,
general-purpose timers, DAC, and ADC.
3.11
Liquid crystal display (LCD)
The LCD drives up to 8 common terminals and 48 segment terminals to drive up to 384
pixels.
•
Internal step-up converter to guarantee functionality and contrast control irrespective of
. This converter can be deactivated, in which case the V pin is used to provide
V
DD
LCD
the voltage to the LCD
•
•
•
•
•
•
•
•
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
Supports static, 1/2, 1/3 and 1/4 bias
Phase inversion to reduce power consumption and EMI
Up to 8 pixels can be programmed to blink
Unneeded segments and common pins can be used as general I/O pins
LCD RAM can be updated at any time owing to a double-buffer
The LCD controller can operate in Stop mode
V
rails decoupling capability
LCD
3.12
Analog-to-digital converter (ADC)
A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into STM32L073xx device. It has up to 16 external channels and 3
internal channels (temperature sensor, voltage reference, V
voltage measurement).
LCD
Three channels, PA0, PA4 and PA5, are fast channels, while the others are standard
channels.
The ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all
frequencies (~25 µA at 10 kSPS, ~240 µA at 1MSPS). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate from a supply voltage down to
1.65 V.
The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits (see AN2668).
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Functional overview
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
3.13
Temperature sensor
The temperature sensor (T
temperature.
) generates a voltage V
that varies linearly with
SENSE
SENSE
The temperature sensor is internally connected to the ADC_IN18 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 7. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3 V
TSENSE_CAL1
0x1FF8 007A - 0x1FF8 007B
TS ADC raw data acquired at
temperature of 130 °C
TSENSE_CAL2
0x1FF8 007E - 0x1FF8 007F
VDDA= 3 V
3.13.1
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC and Comparators. V
is internally connected to the ADC_IN17 input channel. It
REFINT
enables accurate monitoring of the V value (when no external voltage, V
, is available
DD
REF+
for ADC). The precise voltage of V
is individually measured for each part by ST during
REFINT
production test and stored in the system memory area. It is accessible in read-only mode.
Table 8. Internal voltage reference measured values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 25 °C
VREFINT_CAL
0x1FF8 0078 - 0x1FF8 0079
VDDA = 3 V
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3.13.2
V
voltage monitoring
LCD
This embedded hardware feature allows the application to measure the V
supply voltage
LCD
using the internal ADC channel ADC_IN16. As the V
voltage may be higher than V
,
LCD
DDA
and thus outside the ADC input range, the ADC input is connected to LCD_VLCD1 (which
provides 1/3V when the LCD is configured 1/3Bias and 1/4V when the LCD is
LCD
LCD
configured 1/4Bias or 1/2Bias).
3.14
Digital-to-analog converter (DAC)
Two 12-bit buffered DACs can be used to convert digital signal into analog voltage signal
output. An optional amplifier can be used to reduce the output signal impedance.
This digital Interface supports the following features:
•
•
•
•
•
•
•
•
•
One data holding register (for each channel)
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channels with independent or simultaneous conversions
DMA capability (including the underrun interrupt)
External triggers for conversion
Input reference voltage V
REF+
Six DAC trigger inputs are used in the STM32L073xx. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
3.15
Ultra-low-power comparators and reference voltage
The STM32L073xx embed two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
•
•
•
One comparator with ultra low consumption
One comparator with rail-to-rail inputs, fast or slow mode.
The threshold can be one of the following:
–
–
–
–
DAC output
External I/O pins
Internal reference voltage (V
)
REFINT
submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail
comparator.
Both comparators can wake up the devices from Stop mode, and be combined into a
window comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
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3.16
Touch sensing controller (TSC)
The STM32L073xx provide a simple solution for adding capacitive sensing functionality to
any application. These devices offer up to 24 capacitive sensing channels distributed over 8
analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (such as glass, plastic). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 9. Capacitive sensing GPIOs available on STM32L073xx devices
Capacitive sensing
signal name
Pin
name
Capacitive sensing
signal name
Pin
name
Group
Group
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
PA0
PA1
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
TSC_G6_IO1
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
TSC_G7_IO1
TSC_G7_IO2
TSC_G7_IO3
TSC_G7_IO4
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
PB3
PB4
PB6
PB7
PB11
PB12
PB13
PB14
PC0
PC1
PC2
PC3
PC6
PC7
PC8
PC9
1
5
PA2
PA3
PA4(1)
PA5
2
3
4
6
7
8
PA6
PA7
PC5
PB0
PB1
PB2
PA9
PA10
PA11
PA12
1. This GPIO offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling
capacitor I/O.
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Functional overview
STM32L073xx
3.17
Timers and watchdogs
The ultra-low-power STM32L073xx devices include three general-purpose timers, one low-
power timer (LPTIM), one basic timer, two watchdog timers and the SysTick timer.
Table 10 compares the features of the general-purpose and basic timers.
Table 10. Timer feature comparison
DMA
Counter
resolution
Capture/compare Complementary
Timer
Counter type
Prescaler factor
request
channels
outputs
generation
TIM2,
TIM3
Up, down,
up/down
Any integer between
1 and 65536
16-bit
16-bit
16-bit
Yes
No
4
2
0
No
No
No
TIM21,
TIM22
Up, down,
up/down
Any integer between
1 and 65536
TIM6,
TIM7
Any integer between
1 and 65536
Up
Yes
3.17.1
General-purpose timers (TIM2, TIM3, TIM21 and TIM22)
There are four synchronizable general-purpose timers embedded in the STM32L073xx
device (see Table 10 for differences).
TIM2, TIM3
TIM2 and TIM3 are based on 16-bit auto-reload up/down counter. It includes a 16-bit
prescaler. It features four independent channels each for input capture/output compare,
PWM or one-pulse mode output.
The TIM2/TIM3 general-purpose timers can work together or with the TIM21 and TIM22
general-purpose timers via the Timer Link feature for synchronization or event chaining.
Their counter can be frozen in debug mode. Any of the general-purpose timers can be used
to generate PWM outputs.
TIM2/TIM3 have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM21 and TIM22
TIM21 and TIM22 are based on a 16-bit auto-reload up/down counter. They include a 16-bit
prescaler. They have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can work together and be synchronized with the TIM2/TIM3,
full-featured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
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3.17.2
Low-power Timer (LPTIM)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one shot mode
Selectable software / hardware input trigger
Selectable clock source
–
–
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by the Pulse Counter Application)
•
•
Programmable digital glitch filter
Encoder mode
3.17.3
3.17.4
Basic timer (TIM6, TIM7)
These timers can be used as a generic 16-bit timebase.
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches ‘0’.
3.17.5
3.17.6
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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Functional overview
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3.18
Communication interfaces
2
3.18.1
I C bus
2
Up to three I C interfaces (I2C1 and I2C3) can operate in multimaster or slave modes.
2
Each I C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to
400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with
configurable mask) are also supported as well as programmable analog and digital noise
filters.
Table 11. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
≥ 50 ns
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Benefits
Available in Stop mode
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Variations depending on
temperature, voltage, process
Drawbacks
In addition, I2C1 and I2C3 provide hardware support for SMBus 2.0 and PMBus 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1/I2C3 also have a clock domain
independent from the CPU clock, allowing the I2C1/I2C3 to wake up the MCU from Stop
mode on address match.
Each I2C interface can be served by the DMA controller.
Refer to Table 12 for an overview of I2C interface features.
2
Table 12. STM32L073xx I C implementation
I2C features(1)
I2C1
I2C2
I2C3
7-bit addressing mode
X
X
X
X
X
X
X
X
X
X
X
X
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus with 20 mA output drive I/Os (up to 1
Mbit/s)
X
X(2)
X
Independent clock
SMBus
X
X
X
-
-
-
X
X
X
Wakeup from STOP
1. X = supported.
2. See Table 16: STM32L073xx pin definition on page 46 for the list of I/Os that feature Fast Mode Plus
capability
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3.18.2
Universal synchronous/asynchronous receiver transmitter (USART)
The four USART interfaces (USART1, USART2, USART4 and USART5) are able to
communicate at speeds of up to 4 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 driver enable (DE)
signals, multiprocessor communication mode, master synchronous communication and
single-wire half-duplex communication mode. USART1 and USART2 also support
SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto
baud rate feature and has a clock domain independent from the CPU clock, allowing to
wake up the MCU from Stop mode using baudrates up to 42 Kbaud.
All USART interfaces can be served by the DMA controller.
Table 13 for the supported modes and features of USART interfaces.
Table 13. USART implementation
USART modes/features(1)
USART1 and USART2 USART4 and USART5
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
X
-
LIN mode
-
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
Modbus communication
-
-
-
Auto baud rate detection (4 modes)
Driver Enable
-
X
1. X = supported.
2. This mode allows using the USART as an SPI master.
3.18.3
Low-power universal asynchronous receiver transmitter (LPUART)
The devices embed one Low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock. It can wake up the
system from Stop mode using baudrates up to 46 Kbaud. The Wakeup events from Stop
mode are programmable and can be:
•
•
•
Start bit detection
Or any received data frame
Or a specific programmed data frame
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Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
3.18.4
Serial peripheral interface (SPI)/Inter-integrated sound (I2S)
Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The USARTs with synchronous capability can also be used as SPI master.
One standard I2S interfaces (multiplexed with SPI2) is available. It can operate in master or
slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output
channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When the
I2S interfaces is configured in master mode, the master clock can be output to the external
DAC/CODEC at 256 times the sampling frequency.
The SPIs can be served by the DMA controller.
Refer to Table 14 for the differences between SPI1 and SPI2.
Table 14. SPI/I2S implementation
SPI features(1)
SPI1
SPI2
Hardware CRC calculation
I2S mode
X
-
X
X
X
TI mode
X
1. X = supported.
3.18.5
Universal serial bus (USB)
The STM32L073xx embed a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up to 1 Kbyte and suspend/resume support. It requires a
precise 48 MHz clock which can be generated from the internal main PLL (the clock source
must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming
mode. The synchronization for this oscillator can be taken from the USB data stream itself
(SOF signalization) which allows crystal-less operation.
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3.19
Clock recovery system (CRS)
The STM32L073xx embed a special block which allows automatic trimming of the internal
48 MHz oscillator to guarantee its optimal accuracy over the whole device operational
range. This automatic trimming is based on the external synchronization signal, which could
be either derived from USB SOF signalization, from LSE oscillator, from an external signal
on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.20
Cyclic redundancy check (CRC) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
3.21
Serial wire debug port (SW-DP)
An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.
DS10685 Rev 6
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39
Pin descriptions
STM32L073xx
4
Pin descriptions
Figure 3. STM32L073xx LQFP100 pinout
PE2
1
2
3
4
5
6
7
8
9
10
75
74
73
72
71
70
69
VDD_USB
PE3
VSS
PE4
VDD
PA13
PA12
PA 11
PA10
PA9
PE5
PE6
VLCD
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PH9
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA8
PC9
PH10 11
PC8
12
13
PH0-OSC_IN
PC7
PH1-OSC_OUT
PC6
LQFP100
NRST 14
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
15
16
PC2 17
PC3
18
19
20
21
22
VSSA
VREF-
VREF+
VDDA
PD8
PB15
PB14
PB13
PB12
PA0 23
PA1
PA2
24
25
MSv35413V2
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
40/157
DS10685 Rev 6
STM32L073xx
Pin descriptions
Figure 4. STM32L073xx UFBGA100 ballout
1
2
3
4
5
6
7
8
9
10
11
12
PB8
PD5 PB4
PB3
PA14 PA13
PA12
PA11
PA10
PE3 PE1
BOOT0 PD7
PA15
A
B
PE2
PB9 PB7
PB6
PB5
PD4
PD3 PD1
PC10
PD2 PD0 PC11 VDD
PE4
PD6
PC12
PC13
PE5 PE0 VDD
C
PC14-
D
OSC32 PE6
VSS
PC9
PC6
PA9
PC8
PA8
PC7
_IN
PC15-
OSC32 VLCD VSS
_OUT
E
F
PH0-
OSC_IN
PH9
VSS
VSS
PH1-
OSC_ PH10
OUT
VDD_
USB
VDD
G
PD15 PD14
PD12 PD11
PD13
PC0 NRST VDD
H
J
VSSA PC1
PC2
PD10
VREF
PC3
-
K
L
PA5
PA6
PC4
PC5
PD8 PB15 PB14
PB13
PB12
PA2
PA3
PD9
VREF
PA0
PE10
PB10
PB2
PE8
PE7
PE12
PB11
+
VDDA
PA1
PA4
PB0 PB1
PE13 PE14
M
PA7
PE9 PE11
PE15
MSv35414V3
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USBare shown in grey.
DS10685 Rev 6
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62
Pin descriptions
STM32L073xx
Figure 5. STM32L073xx LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD_USB
VSS
V
48
1
2
3
4
5
6
7
8
LCD
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC13
PA13
PA12
PA11
PA10
PA9
PC14-OSC32_IN
PC15-OSC32_OUT
PH0 -OSC_IN
PH1-OSC_OUT
NRST
PC0
PA8
LQFP64
PC9
PC1
9
PC8
PC2
10
11
12
13
14
15
16
PC7
PC3
PC6
VSSA
PB15
PB14
PB13
PB12
VDDA
PA0
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MS31485V3
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
42/157
DS10685 Rev 6
STM32L073xx
Pin descriptions
Figure 6. STM32L073xx TFBGA64 ballout
1
2
3
4
5
6
7
8
PC14-
OSC32
_IN
PC13
PB9
PB4
PB3
PA15
PA14
PA13
A
B
PC15-
OSC32
_OUT
BOOT
0
VLCD
VSS
PB8
PB7
PD2
PC11
PA10
PC10
PA9
PA12
PA11
PH0-
OSC_IN
PB5
PC12
C
D
E
PH1-
OSC_
OUT
VDD
PC1
PB6
PC0
VSS
VDD
VSS
VDD
VSS
PA8
PC7
PC9
PC8
VDD_
USB
NRST
VSSA
PC2
PA2
PA5
PB0
PC6
PB15
PB14
F
G
H
VREF
+
PA0
PA1
PA3
PA4
PA6
PA7
PB1
PC4
PB2
PC5
PB10
PB11
PB13
PB12
VDDA
MSv37829V2
1. The above figure shows the package top view.
2. the I/O pins supplied by VDD_USB are shown in grey.
DS10685 Rev 6
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62
Pin descriptions
STM32L073xx
Figure 7. STM32L073xx WLCSP49 ballout
1
2
3
4
5
6
7
VDD_
USB
VDD
A
B
C
D
E
F
PA15
PB3
PB5
BOOT0
PB9
PC13
PA12
PA10
PA14
PA13
PB4
PB7
PB6
PC1
PB8
PC0
VLCD
PC15-
OSC32
_OUT
PC14-
OSC32
_IN
PH1-
OSC_
OUT
PH0-
OSC_IN
PA8
PA11
PA9
PB1
PB2
VSS
PA1
NRST
PA0
PC2
VDDA
PA3
PB15
VREF+
PA2
PB13
VDD
PB11
PB10
PA7
PB0
PB14
PB12
PA4
PA6
G
PA5
MSv66802V1
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
44/157
DS10685 Rev 6
STM32L073xx
Pin descriptions
Figure 8. STM32L073xx LQFP48 pinout
48 47 46 45 44 43 42 41 40 39 38 37
VDD_USB
V
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
LCD
VSS
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
PA13
PA12
PA11
PA10
PA9
LQFP48
PA8
VSSA
PB15
PB14
PB13
PB12
VDDA
9
PA0
10
PA1 11
12
PA2
24
13 14 15 16 17 18 19 20 21 22 23
MS31484V3
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
Figure 9. STM32L073xx UFQFPN48
VLCD
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD_USB
2
VSS
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
3
PA13
PA12
PA11
PA10
PA9
4
5
6
UFQFPN48
7
VSSA
8
PA8
VDDA
9
PB15
PB14
PB13
PB12
PA0
10
11
12
PA1
PA2
MSv62439V1
1. The above figure shows the package top view.
2. The I/O pins supplied by VDD_USB are shown in grey.
DS10685 Rev 6
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62
Pin descriptions
STM32L073xx
Table 15. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
FTf
TC
B
Input / output pin
5 V tolerant I/O
5 V tolerant I/O, FM+ capable
Standard 3.3V I/O
I/O structure
Notes
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 16. STM32L073xx pin definition
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
LCD_SEG38,
TIM3_ETR
-
-
-
-
-
-
-
-
1
2
B2
A1
PE2
PE3
I/O FT
I/O FT
-
-
-
-
TIM22_CH1,
LCD_SEG39,
TIM3_CH1
TIM22_CH2,
TIM3_CH2
-
-
-
-
-
-
-
-
3
4
B1
C2
PE4
PE5
I/O FT
I/O FT
-
-
-
-
TIM21_CH1,
TIM3_CH3
46/157
DS10685 Rev 6
STM32L073xx
Pin descriptions
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
TIM21_CH2,
TIM3_CH4
-
-
-
-
5
6
D2
E2
PE6
I/O FT
S
-
-
RTC_TAMP3/WKUP3
1
B6
1
B2
VLCD
-
RTC_TAMP1/RTC_T
S/
RTC_OUT/WKUP2
2
3
4
B7
C6
C7
2
3
4
A2
A1
B1
7
8
9
C1
D1
E1
PC13
I/O FT
-
-
-
-
PC14-
OSC32_IN I/O FT
(PC14)
-
-
OSC32_IN
PC15-
OSC32_OU I/O TC
T (PC15)
OSC32_OUT
-
-
-
-
-
-
-
-
10
11
F2
PH9
I/O FT
I/O FT
-
-
-
-
-
-
G2
PH10
PH0-
OSC_IN
(PH0)
5
D6
5
C1 12
F1
I/O TC
-
USB_CRS_SYNC
OSC_IN
PH1-
6
7
D7
D5
6
7
D1 13
E1 14
G1
H2
OSC_OUT I/O TC
(PH1)
-
-
-
-
OSC_OUT
-
NRST
PC0
I/O
-
LPTIM1_IN1,
LCD_SEG18,
EVENTOUT,
TSC_G7_IO1,
LPUART1_RX,
I2C3_SCL
-
-
C5
C4
8
9
E3 15
H1
J2
I/O FTf
-
-
ADC_IN10
ADC_IN11
LPTIM1_OUT,
LCD_SEG19,
EVENTOUT,
TSC_G7_IO2,
LPUART1_TX,
I2C3_SDA
E2 16
PC1
I/O FTf
DS10685 Rev 6
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62
Pin descriptions
STM32L073xx
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
LPTIM1_IN2,
LCD_SEG20,
SPI2_MISO/I2S2_MCK
, TSC_G7_IO3
-
-
E7 10 F2 17
J3
PC2
PC3
I/O FTf
I/O FT
-
-
ADC_IN12
ADC_IN13
LPTIM1_ETR,
LCD_SEG21,
SPI2_MOSI/I2S2_SD,
TSC_G7_IO4
-
11
-
18
K2
8
-
-
-
12 F1 19
J1
K1
L1
VSSA
VREF-
VREF+
VDDA
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
-
E6
G1 21
9
F7 13 H1 22
M1
TIM2_CH1,
TSC_G1_IO1,
USART2_CTS,
TIM2_ETR,
USART4_TX,
COMP1_OUT
COMP1_INM,
ADC_IN0,
RTC_TAMP2/WKUP1
10 E5 14 G2 23
L2
PA0
I/O TC
-
EVENTOUT,
LCD_SEG0,
TIM2_CH2,
TSC_G1_IO2,
USART2_RTS/
USART2_DE,
TIM21_ETR,
USART4_RX
COMP1_INP,
ADC_IN1
11 E4 15 H2 24
M2
PA1
I/O FT
-
TIM21_CH1,
LCD_SEG1,
TIM2_CH3,
TSC_G1_IO3,
USART2_TX,
LPUART1_TX,
COMP2_OUT
COMP2_INM,
ADC_IN2
12 F6 16 F3 25
K3
PA2
I/O FT
-
48/157
DS10685 Rev 6
STM32L073xx
Pin descriptions
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
TIM21_CH2,
LCD_SEG2,
TIM2_CH4,
TSC_G1_IO4,
USART2_RX,
LPUART1_RX
COMP2_INP,
ADC_IN3
13 G7 17 G3 26
L3
PA3
I/O FT
-
-
-
-
-
18 C2 27
19 D2 28
E3
H3
VSS
VDD
S
S
-
-
-
-
-
-
-
-
SPI1_NSS,
TSC_G2_IO1,
USART2_CK,
TIM22_ETR
COMP1_INM,
COMP2_INM,
ADC_IN4,
(1)
14 F5 20 H3 29
M3
K4
PA4
PA5
I/O TC
I/O TC
DAC_OUT1
COMP1_INM,
COMP2_INM,
ADC_IN5,
SPI1_SCK, TIM2_ETR,
TSC_G2_IO2,
15 G6 21 F4 30
-
TIM2_CH1
DAC_OUT2
SPI1_MISO,
LCD_SEG3,
TIM3_CH1,
TSC_G2_IO3,
LPUART1_CTS,
TIM22_CH1,
EVENTOUT,
COMP1_OUT
16 G5 22 G4 31
L4
PA6
I/O FT
-
ADC_IN6
SPI1_MOSI,
LCD_SEG4,
TIM3_CH2,
17 F4 23 H4 32
M4
K5
PA7
PC4
I/O FT
-
-
TSC_G2_IO4,
TIM22_CH2,
EVENTOUT,
COMP2_OUT
ADC_IN7
EVENTOUT,
LCD_SEG22,
LPUART1_TX
-
-
24 H5 33
I/O FT
ADC_IN14
DS10685 Rev 6
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62
Pin descriptions
STM32L073xx
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
LCD_SEG23,
LPUART1_RX,
TSC_G3_IO1
-
-
25 H6 34
L5
PC5
PB0
I/O FT
I/O FT
-
-
ADC_IN15
EVENTOUT,
LCD_SEG5,
TIM3_CH3,
LCD_VLCD3,
ADC_IN8,
VREF_OUT
18 G4 26 F5 35
M5
TSC_G3_IO2
LCD_SEG6,
TIM3_CH4,
TSC_G3_IO3,
LPUART1_RTS/
LPUART1_DE
ADC_IN9,
VREF_OUT
19 D3 27 G5 36
M6
L6
PB1
PB2
I/O FT
I/O FT
-
-
LPTIM1_OUT,
TSC_G3_IO4,
I2C3_SMBA
20 E3 28 G6 37
LCD_VLCD2
LCD_SEG45,
USART5_CK/
USART5_RTS/
USART5_DE
-
-
-
-
-
-
-
-
-
-
-
-
38
39
40
M7
L7
PE7
PE8
PE9
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
LCD_SEG46,
USART4_TX
TIM2_CH1,
LCD_SEG47,
TIM2_ETR,
M8
USART4_RX
TIM2_CH2,
LCD_SEG40,
USART5_TX
-
-
-
-
41
L8
PE10
I/O FT
-
-
TIM2_CH3,
USART5_RX
-
-
-
-
-
-
-
-
-
-
-
-
42
43
M9
L9
PE11
PE12
PE13
I/O FT
I/O FT
I/O FT
-
-
-
LCD_VLCD1
LCD_VLCD3
-
TIM2_CH4, SPI1_NSS
LCD_SEG41,
SPI1_SCK
44 M10
50/157
DS10685 Rev 6
STM32L073xx
Pin descriptions
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
LCD_SEG42,
SPI1_MISO
-
-
-
-
-
-
-
-
45 M11
46 M12
PE14
PE15
I/O FT
I/O FT
-
-
-
-
LCD_SEG43,
SPI1_MOSI
LCD_SEG10,
TIM2_CH3,
TSC_SYNC,
21 G3 29 G7 47 L10
PB10
PB11
I/O FT
-
-
-
-
LPUART1_TX,
SPI2_SCK, I2C2_SCL,
LPUART1_RX
EVENTOUT,
LCD_SEG11,
TIM2_CH4,
TSC_G6_IO1,
LPUART1_RX,
I2C2_SDA,
22 F3 30 H7 48
L11
I/O FT
LPUART1_TX
23 D4 31 D6 49 F12
24 G2 32 E5 50 G12
VSS
VDD
S
S
-
-
-
-
-
-
SPI2_NSS/I2S2_WS,
LCD_SEG12,
LPUART1_RTS/
LPUART1_DE,
TSC_G6_IO2,
I2C2_SMBA,
25 G1 33 H8 51 L12
PB12
PB13
I/O FT
-
-
LCD_VLCD1
EVENTOUT
SPI2_SCK/I2S2_CK,
LCD_SEG13, MCO,
TSC_G6_IO3,
26 F2 34 G8 52 K12
I/O FTf
-
LPUART1_CTS,
I2C2_SCL, TIM21_CH1
DS10685 Rev 6
51/157
62
Pin descriptions
STM32L073xx
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
SPI2_MISO/I2S2_MCK
, LCD_SEG14,
RTC_OUT,
TSC_G6_IO4,
LPUART1_RTS/
LPUART1_DE,
I2C2_SDA,
27 F1 35 F8 53 K11
PB14
I/O FTf
-
-
TIM21_CH2
SPI2_MOSI/I2S2_SD,
LCD_SEG15,
28 E1 36 F7 54 K10
PB15
PD8
I/O FT
I/O FT
-
-
-
-
RTC_REFIN
LPUART1_TX,
LCD_SEG28
-
-
-
-
55
56
K9
K8
LPUART1_RX,
LCD_SEG29
-
-
-
-
-
-
-
-
-
-
-
-
PD9
PD10
PD11
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
57 J12
58 J11
LCD_SEG30
LPUART1_CTS,
LCD_SEG31
LPUART1_RTS/
LPUART1_DE,
LCD_SEG32
-
-
-
-
59 J10
PD12
I/O FT
-
-
-
-
-
-
-
-
-
-
60 H12
61 H11
PD13
PD14
I/O FT
I/O FT
-
-
LCD_SEG33
LCD_SEG34
-
-
USB_CRS_SYNC,
LCD_SEG35
-
-
-
-
62 H10
PD15
I/O FT
-
-
TIM22_CH1,
LCD_SEG24,
TIM3_CH1,
-
-
37 F6 63 E12
PC6
I/O FT
-
-
TSC_G8_IO1
TIM22_CH2,
LCD_SEG25,
TIM3_CH2,
-
-
38 E7 64 E11
PC7
I/O FT
-
-
TSC_G8_IO2
52/157
DS10685 Rev 6
STM32L073xx
Pin descriptions
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
TIM22_ETR,
LCD_SEG26,
TIM3_CH3,
-
-
-
-
39 E8 65 E10
PC8
PC9
I/O FT
I/O FTf
-
-
-
-
TSC_G8_IO3
TIM21_ETR,
LCD_SEG27,
USB_NOE/TIM3_CH4,
TSC_G8_IO4,
40 D8 66 D12
I2C3_SDA
MCO, LCD_COM0,
USB_CRS_SYNC,
EVENTOUT,
29 D1 41 D7 67 D11
PA8
I/O FTf
-
-
-
USART1_CK,
I2C3_SCL
MCO, LCD_COM1,
TSC_G4_IO1,
USART1_TX,
I2C1_SCL,
30 E2 42 C7 68 D10
31 C1 43 C6 69 C12
32 D2 44 C8 70 B12
PA9
PA10
PA11
I/O FTf
I/O FTf
I/O FT
-
I2C3_SMBA
LCD_COM2,
TSC_G4_IO2,
USART1_RX,
I2C1_SDA
-
-
SPI1_MISO,
EVENTOUT,
TSC_G4_IO3,
USART1_CTS,
COMP1_OUT
(2)
USB_DM
SPI1_MOSI,
EVENTOUT,
TSC_G4_IO4,
USART1_RTS/
USART1_DE,
COMP2_OUT
(2)
33 B1 45 B8 71 A12
PA12
PA13
I/O FT
I/O FT
USB_DP
SWDIO, USB_NOE,
LPUART1_RX
34 C2 46 A8 72 A11
-
-
DS10685 Rev 6
53/157
62
Pin descriptions
STM32L073xx
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
-
-
-
-
-
73 C11
VDD
VSS
S
S
S
-
-
-
-
-
-
-
-
-
35
47 D5 74 F11
36 A1 48 E6 75 G11
37 B2 49 A7 76 A10
VDD_USB
SWCLK, USART2_TX,
LPUART1_TX
PA14
I/O FT
-
-
SPI1_NSS,
LCD_SEG17,
TIM2_ETR,
EVENTOUT,
USART2_RX,
TIM2_CH1,
38 A2 50 A6 77
A9
PA15
I/O FT
-
-
USART4_RTS/
USART4_DE
LPUART1_TX,
LCD_COM4/LCD_SEG
28/LCD_SEG48,
USART4_TX
-
-
-
-
-
-
51 B7 78 B11
52 B6 79 C10
53 C5 80 B10
PC10
PC11
PC12
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
LPUART1_RX,
LCD_COM5/LCD_SEG
29/LCD_SEG49,
USART4_RX
LCD_COM6/LCD_SEG
30/LCD_SEG50,
USART5_TX,
USART4_CK
TIM21_CH1,
SPI2_NSS/I2S2_WS
-
-
-
-
-
-
-
-
81
82
C9
B9
PD0
PD1
I/O FT
I/O FT
-
-
-
-
SPI2_SCK/I2S2_CK
LPUART1_RTS/
LPUART1_DE,
LCD_COM7/LCD_SEG
31/LCD_SEG51,
TIM3_ETR,
-
-
54 B5 83
C8
PD2
I/O FT
-
-
USART5_RX
54/157
DS10685 Rev 6
STM32L073xx
Pin descriptions
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
USART2_CTS,
LCD_SEG44,
SPI2_MISO/I2S2_MCK
-
-
-
-
-
-
-
-
84
85
B8
B7
PD3
PD4
I/O FT
I/O FT
-
-
-
-
USART2_RTS/
USART2_DE,
SPI2_MOSI/I2S2_SD
-
-
-
-
-
-
-
-
86
87
A6
B6
PD5
PD6
I/O FT
I/O FT
-
-
USART2_TX
USART2_RX
-
-
USART2_CK,
TIM21_CH2
-
-
-
-
88
A5
PD7
I/O FT
-
-
SPI1_SCK,
LCD_SEG7,
TIM2_CH2,
TSC_G5_IO1,
EVENTOUT,
USART1_RTS/
USART1_DE,
USART5_TX
39 A3 55 A5 89
A8
PB3
I/O FT
-
COMP2_INM
SPI1_MISO,
LCD_SEG8,
TIM3_CH1,
TSC_G5_IO2,
TIM22_CH1,
USART1_CTS,
USART5_RX,
I2C3_SDA
40 B3 56 A4 90
A7
PB4
I/O FTf
-
COMP2_INP
SPI1_MOSI,
LCD_SEG9,
LPTIM1_IN1,
I2C1_SMBA,
41 A4 57 C4 91
C5
PB5
I/O FT
-
TIM3_CH2/TIM22_CH2
, USART1_CK,
USART5_CK,
COMP2_INP
USART5_RTS/
USART5_DE
DS10685 Rev 6
55/157
62
Pin descriptions
STM32L073xx
Table 16. STM32L073xx pin definition (continued)
Pin number
Pin name
(function
Alternate functions
Additional functions
after reset)
USART1_TX,
I2C1_SCL,
LPTIM1_ETR,
TSC_G5_IO3
42 B4 58 D3 92
B5
B4
PB6
PB7
I/O FTf
I/O FTf
-
-
COMP2_INP
USART1_RX,
I2C1_SDA,
LPTIM1_IN2,
TSC_G5_IO4,
USART4_CTS
43 C3 59 C3 93
COMP2_INP, PVD_IN
44 A5 60 B4 94
45 B5 61 B3 95
A4
A3
BOOT0
PB8
I
-
-
-
-
-
LCD_SEG16,
TSC_SYNC, I2C1_SCL
I/O FTf
LCD_COM3,
EVENTOUT,
I2C1_SDA,
46 A6 62 A3 96
B3
C3
PB9
I/O FTf
-
-
SPI2_NSS/I2S2_WS
LCD_SEG36,
EVENTOUT
-
-
-
-
-
-
97
98
PE0
PE1
I/O FT
I/O FT
-
-
-
-
LCD_SEG37,
EVENTOUT
-
-
-
A2
D3
47
63 D4 99
VSS
VDD
S
S
-
-
-
-
-
-
-
-
48 A7 64 E4 100 C4
1. PA4 offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O.
2. These pins are powered by VDD_USB. For all characteristics that refer to VDD, VDD_USB must be used instead.
56/157
DS10685 Rev 6
Table 17. Alternate functions port A
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/SPI2/I2S2/
USART1/2/
LPUART1/USB/ SPI1/SPI2/I2S2/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/L
PTIM1/TIM2/3/E
VENTOUT/
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21
/
I2C1/USART1/2
/LPUART1/
TIM3/22/
SPI2/I2S2/I2C2/
USART1/
TIM2/21/22
I2C3/LPUART1/
COMP1/2/
TIM3
Port
I2C1/TSC/
EVENTOUT
I2C1/LCD/
TIM2/21
EVENTOUT
SYS_AF
EVENTOUT
PA0
-
-
TIM2_CH1
TIM2_CH2
TSC_G1_IO1
TSC_G1_IO2
USART2_CTS
TIM2_ETR
USART4_TX
USART4_RX
COMP1_OUT
-
USART2_RTS/
USART2_DE
PA1
EVENTOUT
LCD_SEG0
TIM21_ETR
PA2
PA3
PA4
PA5
PA6
PA7
TIM21_CH1
TIM21_CH2
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
LCD_SEG1
LCD_SEG2
-
TIM2_CH3
TIM2_CH4
-
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
USART2_TX
USART2_RX
USART2_CK
-
LPUART1_TX
COMP2_OUT
-
LPUART1_RX
-
TIM22_ETR
TIM2_CH1
TIM22_CH1
TIM22_CH2
-
-
-
TIM2_ETR
TIM3_CH1
TIM3_CH2
-
-
LCD_SEG3
LCD_SEG4
TSC_G2_IO3 LPUART1_CTS
EVENTOUT
EVENTOUT
COMP1_OUT
COMP2_OUT
TSC_G2_IO4
EVENTOUT
-
USB_CRS_
SYNC
PA8
MCO
LCD_COM0
USART1_CK
-
-
I2C3_SCL
PA9
PA10
PA11
MCO
LCD_COM1
LCD_COM2
-
-
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
USART1_TX
USART1_RX
USART1_CTS
-
-
-
I2C1_SCL
I2C1_SDA
-
I2C3_SMBA
-
-
-
SPI1_MISO
EVENTOUT
COMP1_OUT
USART1_RTS/
USART1_DE
PA12
SPI1_MOSI
-
EVENTOUT
TSC_G4_IO4
-
-
COMP2_OUT
PA13
PA14
SWDIO
SWCLK
-
-
USB_NOE
-
-
-
-
-
-
LPUART1_RX
LPUART1_TX
-
-
USART2_TX
USART4_RTS/
USART4_DE
PA15
SPI1_NSS
LCD_SEG17
TIM2_ETR
EVENTOUT
USART2_RX
TIM2_CH1
-
Table 18. Alternate functions port B
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/SPI2/I2S2/
USART1/2/
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/L
PTIM1/TIM2/3/E
VENTOUT/
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21/
EVENTOUT
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
Port
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
SPI1/SPI2/I2S2/I
2C1/LCD/
SPI2/I2S2/I2C2/
USART1/
TIM2/21/22
I2C3/LPUART1/
COMP1/2/
TIM3
I2C1/TSC/
EVENTOUT
TIM2/21
SYS_AF
PB0
EVENTOUT
LCD_SEG5
LCD_SEG6
-
TIM3_CH3
TIM3_CH4
LPTIM1_OUT
TIM2_CH2
TIM3_CH1
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G5_IO1
TSC_G5_IO2
-
-
-
-
-
-
LPUART1_RTS/
LPUART1_DE
PB1
PB2
PB3
PB4
-
-
-
-
-
-
I2C3_SMBA
-
USART1_RTS/
USART1_DE
SPI1_SCK
SPI1_MISO
LCD_SEG7
LCD_SEG8
EVENTOUT
TIM22_CH1
USART5_TX
USART5_RX
USART1_CTS
I2C3_SDA
USART5_CK,
USART5_RTS/
USART5_DE
TIM3_CH2/
TIM22_CH2
PB5
SPI1_MOSI
LCD_SEG9
LPTIM1_IN1
I2C1_SMBA
USART1_CK
-
PB6
PB7
PB8
USART1_TX
USART1_RX
-
I2C1_SCL
I2C1_SDA
LPTIM1_ETR
LPTIM1_IN2
-
TSC_G5_IO3
TSC_G5_IO4
TSC_SYNC
-
-
-
-
-
-
-
-
-
USART4_CTS
-
LCD_SEG16
I2C1_SCL
SPI2_NSS/
I2S2_WS
PB9
-
LCD_COM3
EVENTOUT
-
I2C1_SDA
-
-
PB10
PB11
-
LCD_SEG10
LCD_SEG11
TIM2_CH3
TIM2_CH4
TSC_SYNC
LPUART1_TX
LPUART1_RX
SPI2_SCK
-
I2C2_SCL
I2C2_SDA
LPUART1_RX
LPUART1_TX
EVENTOUT
TSC_G6_IO1
LPUART1_RTS/
LPUART1_DE
PB12 SPI2_NSS/I2S2_WS
PB13 SPI2_SCK/I2S2_CK
LCD_SEG12
LCD_SEG13
LCD_SEG14
TSC_G6_IO2
TSC_G6_IO3
TSC_G6_IO4
I2C2_SMBA
I2C2_SCL
I2C2_SDA
EVENTOUT
TIM21_CH1
TIM21_CH2
-
-
-
MCO
LPUART1_CTS
SPI2_MISO/
PB14
LPUART1_RTS/
LPUART1_DE
RTC_OUT
I2S2_MCK
SPI2_MOSI/
I2S2_SD
PB15
LCD_SEG15
RTC_REFIN
-
-
-
-
-
Table 19. Alternate functions port C
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/SPI2/I2S2/
USART1/2/
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/
I2C1/2/
LPUART1/
USART4/
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
SPI2/I2S2
/I2C2/
USART1/
TIM2/21/22
Port
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
SPI1/SPI2/I2S2/I2C1/
LCD/
I2C3/LPUART1/
COMP1/2/
TIM3
I2C1/TSC/
EVENTOUT
TIM2/21
LPTIM1/TIM2/3
/EVENTOUT/SYS_AF
UASRT5/TIM21/E
VENTOUT
PC0
LPTIM1_IN1
LPTIM1_OUT
LCD_SEG18
LCD_SEG19
EVENTOUT
EVENTOUT
TSC_G7_IO1
TSC_G7_IO2
LPUART1_RX
LPUART1_TX
I2C3_SCL
I2C3_SDA
PC1
PC2
SPI2_MISO/
I2S2_MCK
LPTIM1_IN2
LCD_SEG20
LCD_SEG21
TSC_G7_IO3
TSC_G7_IO4
SPI2_MOSI/
I2S2_SD
PC3
LPTIM1_ETR
EVENTOUT
PC4
PC5
PC6
PC7
PC8
PC9
LCD_SEG22
LCD_SEG23
LCD_SEG24
LCD_SEG25
LCD_SEG26
LCD_SEG27
LPUART1_TX
LPUART1_RX
TIM3_CH1
TSC_G3_IO1
TSC_G8_IO1
TSC_G8_IO2
TSC_G8_IO3
TSC_G8_IO4
TIM22_CH1
TIM22_CH2
TIM22_ETR
TIM21_ETR
TIM3_CH2
TIM3_CH3
USB_NOE/TIM3_CH4
I2C3_SDA
LCD_COM4/LCD_SEG
28/LCD_SEG48
PC10
PC11
PC12
LPUART1_TX
LPUART1_RX
USART4_TX
USART4_RX
USART4_CK
LCD_COM5/LCD_SEG
29/LCD_SEG49
LCD_COM6/LCD_SEG
30/LCD_SEG50
USART5_TX
PC13
PC14
PC15
Table 20. Alternate functions port D
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/SPI2/I2S2/
USART1/2/
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/
LPTIM1/TIM2/3
/EVENTOUT/
SYS_AF
I2C1/2/
LPUART1/
USART4/
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
SPI2/I2S2
/I2C2/
USART1/
TIM2/21/22
Port
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
SPI1/SPI2/I2S2/I2C1/
LCD/TIM2/21
I2C1/TSC/
EVENTOUT
I2C3/LPUART1/
COMP1/2/TIM3
UASRT5/TIM21/E
VENTOUT
PD0
TIM21_CH1
-
SPI2_NSS/I2S2_WS
SPI2_SCK/I2S2_CK
-
-
-
-
-
-
-
-
-
-
-
-
PD1
LCD_COM7/
LCD_SEG31/
LCD_SEG51
LPUART1_RTS/
LPUART1_DE
PD2
TIM3_ETR
-
-
-
USART5_RX
-
SPI2_MISO/
I2S2_MCK
PD3
PD4
USART2_CTS
LCD_SEG44
-
-
-
-
-
-
-
-
-
-
USART2_RTS/
USART2_DE
SPI2_MOSI/I2S2_SD
-
PD5
PD6
PD7
PD8
PD9
PD10
PD11
USART2_TX
USART2_RX
USART2_CK
LPUART1_TX
LPUART1_RX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM21_CH2
LCD_SEG28
LCD_SEG29
LCD_SEG30
LCD_SEG31
LPUART1_CTS
LPUART1_RTS/
LPUART1_DE
PD12
LCD_SEG32
-
-
-
-
-
-
PD13
PD14
-
-
LCD_SEG33
LCD_SEG34
LCD_SEG35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD15 USB_CRS_SYNC
Table 21. Alternate functions port E
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/SPI2/I2S2/
USART1/2/
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/
LPTIM1/TIM2/3
/EVENTOUT/
SYS_AF
I2C1/2/
LPUART1/
USART4/
UASRT5/TIM21/
EVENTOUT
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
SPI2/I2S2
/I2C2/
USART1/
TIM2/21/22
Port
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
EVENTOUT/
SYS_AF
SPI1/SPI2/I2S2/I2C1
/LCD/TIM2/21
I2C1/TSC/
EVENTOUT
I2C3/LPUART1/
COMP1/2/TIM3
PE0
-
LCD_SEG36
EVENTOUT
EVENTOUT
TIM3_ETR
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE1
PE2
PE3
PE4
PE5
PE6
-
LCD_SEG37
-
LCD_SEG38
TIM22_CH1
TIM22_CH2
TIM21_CH1
TIM21_CH2
LCD_SEG39
-
-
-
USART5_CK,
USART5_RTS/
USART5_DE
PE7
-
LCD_SEG45
-
-
-
-
-
PE8
PE9
-
LCD_SEG46
LCD_SEG47
LCD_SEG40
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART4_TX
-
-
-
-
-
-
-
-
TIM2_CH1
TIM2_ETR
-
USART4_RX
PE10
PE11
PE12
PE13
PE14
PE15
TIM2_CH2
USART5_TX
TIM2_CH3
-
USART5_RX
TIM2_CH4
-
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
-
-
-
-
-
-
-
LCD_SEG41
LCD_SEG42
LCD_SEG43
Table 22. Alternate functions port H
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/SPI2/
I2S2/USART1/2/
LPUART1/USB/
LPTIM1/TSC/
TIM2/21/22/
SPI1/SPI2/I2S2/
LPUART1/
USART5/USB/
LPTIM1/TIM2/3/
EVENTOUT/
SYS_AF
I2C1/2/
LPUART1/
USART4/
I2C1/USART1/2/
LPUART1/
TIM3/22/
EVENTOUT
I2C3/
LPUART1/
COMP1/2/
TIM3
Port
SPI2/I2S2/I2C2/
USART1/
TIM2/21/22
SPI1/SPI2/I2S2
/I2C1/LCD/TIM2/21
I2C1/TSC/
EVENTOUT
UASRT5/TIM21/
EVENTOUT
EVENTOUT/
SYS_AF
PH0
PH1
USB_CRS_SYNC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
STM32L073xx
Memory mapping
5
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
DS10685 Rev 6
63/157
63
Electrical characteristics
STM32L073xx
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.6 V (for the
A
DD
1.65 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
ai17851c
ai17852c
64/157
DS10685 Rev 6
STM32L073xx
Electrical characteristics
6.1.6
Power supply scheme
Figure 12. Power supply scheme
Standby-power circuitry
(OSC32,RTC,Wake-up
logic, RTC backup
registers)
OUT
IN
IO
Logic
GP I/Os
Kernel logic
(CPU,
Digital &
Memories)
VDD
VDD
Regulator
N × 100 nF
+ 1 × 10 μF
VSS
VDDA
VDDA
VREF
VREF+
Analog:
RC,PLL,COMP,
….
100 nF
+ 1 μF
ADC/
DAC
100 nF
+ 1 μF
VREF-
VSSA
VLCD
VSS
LCD
VSS
USB
transceiver
VDD_USB
MSv33790V1
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Electrical characteristics
STM32L073xx
6.1.7
Optional LCD power supply scheme
Figure 13. Optional LCD power supply scheme
VSEL
VDD
VDD
Step-up
Converter
N x 100 nF
+ 1 x 10 μF
Option 1
Option 2
VLCD
100 nF
LCD
VLCD
CEXT
VSS
MSv33791V1
1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.
6.1.8
Current consumption measurement
Figure 14. Current consumption measurement scheme
VDDA
IDD
NxVDD
N × 100 nF
+ 1 × 10 μF
NxVSS
MSv34711V1
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Electrical characteristics
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 23: Voltage characteristics,
Table 24: Current characteristics, and Table 25: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are
available on demand.
Table 23. Voltage characteristics
Symbol
Definition
Min
Max
Unit
External main supply voltage
(including VDDA, VDD_USB, VDD
VDD–VSS
–0.3
4.0
(1)
)
Input voltage on FT and FTf pins
Input voltage on TC pins
VSS − 0.3
VSS − 0.3
VSS
VDD+4.0
4.0
V
(2)
VIN
Input voltage on BOOT0
VDD + 4.0
4.0
Input voltage on any other pin
Variations between different VDDx power pins
VSS − 0.3
-
|ΔVDD
|VDDA-VDDx
|ΔVSS
|
50
Variations between any VDDx and VDDA power
pins(3)
|
-
300
mV
V
Variations between all different ground pins
including VREF- pin
|
-
-
50
V
REF+ –VDDA Allowed voltage difference for VREF+ > VDDA
0.4
Electrostatic discharge voltage
(human body model)
VESD(HBM)
see Section 6.3.11
1. All main power (VDD,VDD_USB, VDDA) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 24 for maximum allowed injected current values.
3. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and device operation. VDD_USB is independent
from VDD and VDDA: its value does not need to respect this rule.
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Electrical characteristics
Symbol
STM32L073xx
Table 24. Current characteristics
Ratings
Max.
Unit
(2)
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Total current into VDD_USB power lines (source)
105
105
25
(2)
ΣIVSS
ΣIVDD_USB
IVDD(PIN)
IVSS(PIN)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
100
100
Output current sunk by any I/O and control pin except FTf
pins
16
IIO
Output current sunk by FTf pins
22
Output current sourced by any I/O and control pin
-16
mA
Total output current sunk by sum of all IOs and control pins
except PA11 and PA12(2)
90
25
ΣIIO(PIN)
Total output current sunk by PA11 and PA12
Total output current sourced by sum of all IOs and control
pins(2)
-90
Injected current on FT, FTf, RST and B pins
Injected current on TC pin
-5/+0(3)
± 5(4)
± 25
IINJ(PIN)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 23 for maximum allowed input voltage values.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 23: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 25. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
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Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 26. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK Internal AHB clock frequency
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
-
-
-
0
0
32
32
MHz
0
32
BOR detector disabled
BOR detector enabled, at power-on
1.65
1.8
3.6
3.6
3.6
VDD
Standard operating voltage
V
BOR detector disabled, after power-on 1.65
Analog operating voltage (DAC not
used)
(1)
VDDA
VDDA
Must be the same voltage as VDD
1.65
1.8
3.6
3.6
V
V
Analog operating voltage (all
features)
(1)
Must be the same voltage as VDD
USB peripheral used
USB peripheral not used
2.0 V ≤ VDD ≤ 3.6 V
1.65 V ≤ VDD ≤ 2.0 V
-
3.0
3.6
3.6
VDD_ Standard operating voltage, USB
V
V
domain(2)
USB
0
-0.3
5.5
Input voltage on FT, FTf and RST
pins(3)
-0.3
5.2
VIN
Input voltage on BOOT0 pin
0
5.5
Input voltage on TC pin
-
-0.3
VDD+0.3
351
488
313
435
417
370
714
88
UFBGA100
LQFP100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TFBGA64
Power dissipation at TA = 85 °C
LQFP64
(range 6) or TA = 105 °C (range 7) (4)
WLCSP49
LQFP48
UFQFPN48
UFBGA100
LQFP100
PD
mW
122
78
TFBGA64
Power dissipation at TA = 125 °C
(range 3) (4)
WLCSP49
LQFP64
104
109
93
LQFP48
UFQFPN48
179
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Electrical characteristics
STM32L073xx
Table 26. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Maximum power dissipation (range 6)
Maximum power dissipation (range 7)
Maximum power dissipation (range 3)
–40
–40
–40
–40
–40
–40
85
TA
Temperature range
105
125
105
125
130
°C
Junction temperature range (range 6) -40 °C ≤ TA ≤ 85 °
Junction temperature range (range 7) -40 °C ≤ TA ≤ 105 °C
Junction temperature range (range 3) -40 °C ≤ TA ≤ 125 °C
TJ
1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA
can be tolerated during power-up and normal operation.
2. VDD_USB must respect the following conditions:
- When VDD is powered-on (VDD < VDD_min), VDD_USB should be always lower than VDD.
- When VDD is powered-down (VDD < VDD_min), VDD_USB should be always lower than VDD.
- In operating mode, VDD_USB could be lower or higher VDD.
- If the USB is not used, VDD_USB must range from VDD_min to VDD_max to be able to use PA11 and PA12 as standard I/Os.
- If the USB is not used and PA11/PA12 are not used as standard I/Os, VDD_USB must be connected to a VSS or VDD power
supply voltage (VDD_USB must not be left floating).
3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 92: Thermal characteristics on
page 150).
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Electrical characteristics
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 26.
Table 27. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
BOR detector enabled
BOR detector disabled
BOR detector enabled
BOR detector disabled
0
0
-
-
∞
VDD rise time rate
1000
µs/V
∞
(1)
tVDD
20
0
-
VDD fall time rate
-
1000
V
DD rising, BOR enabled
-
2
3.3
ms
1.6
(1)
TRSTTEMPO
Reset temporization
VDD rising, BOR disabled(2)
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
0.4
1
0.7
1.5
1.5
1.7
1.65
1.65
1.74
1.8
Power-on/power down reset
threshold
VPOR/PDR
VBOR0
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
1.3
1.67
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
1.69 1.76
1.87 1.93 1.97
1.96 2.03 2.07
2.22 2.30 2.35
2.31 2.41 2.44
2.45 2.55
2.54 2.66
2.6
2.7
2.68
2.78
1.8
2.8
2.9
2.85
2.95
V
1.85 1.88
Programmable voltage detector
threshold 0
1.88 1.94 1.99
1.98 2.04 2.09
2.08 2.14 2.18
2.20 2.24 2.28
2.28 2.34 2.38
2.39 2.44 2.48
2.47 2.54 2.58
2.57 2.64 2.69
2.68 2.74 2.79
2.77 2.83 2.88
2.87 2.94 2.99
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
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Electrical characteristics
STM32L073xx
Table 27. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Falling edge
Min
Typ
Max Unit
2.97 3.05 3.09
3.08 3.15 3.20
VPVD6
PVD threshold 6
V
Rising edge
BOR0 threshold
-
-
40
-
-
Vhyst
Hysteresis voltage
mV
All BOR and PVD thresholds
excepting BOR0
100
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.
6.3.3
Embedded internal reference voltage
The parameters given in Table 29 are based on characterization results, unless otherwise
specified.
Table 28. Embedded internal reference voltage calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 25 °C
VREFINT_CAL
0x1FF8 0078 - 0x1FF8 0079
VDDA= 3 V
(1)
Table 29. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(2)
VREFINT out
Internal reference voltage
– 40 °C < TJ < +125 °C 1.202
1.224
2
1.242
3
V
TVREFINT
Internal reference startup time
-
-
-
ms
VDDA and VREF+ voltage during
VREFINT factory measure
VVREF_MEAS
2.99
3
-
3.01
±5
V
Including uncertainties
due to ADC and
Accuracy of factory-measured
VREFINT value(3)
AVREF_MEAS
-
mV
VDDA/VREF+ values
(4)
TCoeff
Temperature coefficient
Long-term stability
Voltage coefficient
–40 °C < TJ < +125 °C
1000 hours, T= 25 °C
3.0 V < VDDA < 3.6 V
-
-
-
25
-
100
1000
2000
ppm/°C
ppm
(4)
ACoeff
(4)
VDDCoeff
-
ppm/V
ADC sampling time when
reading the internal reference
voltage
(4)(5)
TS_vrefint
-
5
10
-
µs
Startup time of reference
voltage buffer for ADC
(4)
TADC_BUF
-
-
-
-
-
10
25
µs
Consumption of reference
voltage buffer for ADC
(4)
IBUF_ADC
13.5
µA
(4)
IVREF_OUT
VREF_OUT output current(6)
-
-
-
-
-
-
1
µA
pF
(4)
CVREF_OUT
VREF_OUT output load
50
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Symbol
Electrical characteristics
(1)
Table 29. Embedded internal reference voltage (continued)
Parameter
Conditions
Min
Typ
Max
Unit
Consumption of reference
voltage buffer for VREF_OUT
and COMP
(4)
ILPBUF
-
-
730
1200
nA
(4)
VREFINT_DIV1
1/4 reference voltage
1/2 reference voltage
3/4 reference voltage
-
-
-
24
49
74
25
50
75
26
51
76
%
(4)
VREFINT_DIV2
VREFINT
(4)
VREFINT_DIV3
1. Refer to Table 41: Peripheral current consumption in Stop and Standby mode for the value of the internal reference current
consumption (IREFINT).
2. Guaranteed by test in production.
3. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
4. Guaranteed by design.
5. Shortest sampling time can be determined in the application by multiple iterations.
6. To guarantee less than 1% VREF_OUT deviation.
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified
otherwise.
The current consumption values are derived from the tests performed under ambient
temperature and V supply voltage conditions summarized in Table 26: General operating
DD
conditions unless otherwise specified.
The MCU is placed under the following conditions:
•
•
•
All I/O pins are configured in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time and prefetch is adjusted depending on fHCLK
frequency and voltage range to provide the best CPU performance unless otherwise
specified.
•
•
When the peripherals are enabled f
= f
= f
APB1
APB2 APB
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used)
•
The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 43: High-speed external user clock characteristics
•
•
For maximum current consumption V = V
= 3.6 V is applied to all supply pins
DD
DDA
For typical current consumption V = V
= 3.0 V is applied to all supply pins if not
DDA
DD
specified otherwise
The parameters given in Table 51, Table 26 and Table 27 are derived from tests performed
under ambient temperature and V supply voltage conditions summarized in Table 26.
DD
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Electrical characteristics
STM32L073xx
Table 30. Current consumption in Run mode, code with data processing running from
Flash memory
fHCLK
(MHz)
Symbol
Parameter
Condition
Typ
Max(1) Unit
1
2
190
345
650
0,8
250
Range3,
Vcore=1.2 V
VOS[1:0]=11
380
670
0,86
1,7
µA
4
4
fHSE = fHCLK up to
Range2,
Vcore=1.5 V
VOS[1:0]=10
16MHz included,
fHSE = fHCLK/2 above
16 MHz (PLL ON)(2)
8
1,55
2,95
1,9
16
8
3,1
mA
2,1
Range1,
Vcore=1.8 V
VOS[1:0]=01
16
32
0,065
0,524
4,2
3,55
6,65
39
3,8
IDD (Run
from Flash
memory)
Supply current in Run
mode code executed
from Flash memory
7,2
130
210
770
Range3,
Vcore=1.2 V
VOS[1:0]=11
MSI clock source
115
700
µA
Range2,
Vcore=1.5 V
VOS[1:0]=10
16
32
2,9
3,2
7,4
HSI clock source
(16MHz)
mA
Range1,
Vcore=1.8 V
VOS[1:0]=01
7,15
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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Symbol Parameter
Supply
Electrical characteristics
Table 31. Current consumption in Run mode vs code type,
code with data processing running from Flash memory
Conditions
fHCLK
Typ
Unit
Dhrystone
CoreMark
650
655
485
385
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
Fibonacci
4 MHz
µA
while(1)
IDD
(Run
from
current in
Run mode,
code
while(1), 1WS,
prefetch OFF
fHSE = fHCLK up to
16 MHz included, fHSE
= fHCLK/2 above 16
MHz (PLL ON)(1)
375
Dhrystone
CoreMark
Fibonacci
while(1)
6,65
6,9
Flash executed
memory) from Flash
memory
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
6,75
5,8
32 MHz
mA
while(1), prefetch
OFF
5,5
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Figure 15. I vs V , at T = 25/55/85/105 °C, Run mode, code running from
DD
DD
A
Flash memory, Range 2, HSE, 1WS
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
VDD (V)
1.65
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C
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Electrical characteristics
STM32L073xx
Figure 16. I vs V , at T = 25/55/85/105 °C, Run mode, code running from
DD
DD
A
Flash memory, Range 2, HSI16, 1WS
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
VDD (V)
1.65
1.8
2
2.2
2.4
2.6
-40 °C
2.8
3
3.2
3.4
3.6
25 °C
55 °C
85 °C
105 °C
125 °C
MSv37844V1
Table 32. Current consumption in Run mode, code with data processing running from RAM
fHCLK
Symbol
Parameter
Condition
Typ
Max(1)
Unit
(MHz)
1
2
175
315
570
0,71
1,35
2,7
230
360
630
0,78
1,6
3
Range3,
Vcore=1.2 V
VOS[1:0]=11
µA
4
4
fHSE = fHCLK up to
Range2,
Vcore=1.5 V
VOS[1:0]=10
16 MHz included,
fHSE = fHCLK/2 above
16 MHz (PLL ON)(2)
8
16
8
mA
1,7
1,9
3,7
7,1
98
Range1,
Vcore=1.8 V
VOS[1:0]=01
Supply current in Run
mode code executed
from RAM, Flash
16
32
0,065
0,524
4,2
3,2
I
DD (Run
6,65
38
from RAM)
memory switched off
Range3,
Vcore=1.2 V
VOS[1:0]=11
MSI clock
105
615
160
710
µA
Range2,
Vcore=1.5 V
VOS[1:0]=10
16
32
2,85
6,85
3
HSI clock source
(16 MHz)
mA
Range1,
Vcore=1.8 V
VOS[1:0]=01
7,3
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
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Electrical characteristics
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 33. Current consumption in Run mode vs code type,
(1)
code with data processing running from RAM
Symbol
Parameter
Conditions
fHCLK
Typ Unit
Dhrystone
CoreMark
Fibonacci
while(1)
570
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
670
µA
410
4 MHz
Supply current in
Run mode, code
executed from
RAM, Flash
fHSE = fHCLK up to
16 MHz included,
IDD (Run
from
RAM)
375
fHSE = fHCLK/2 above
Dhrystone
CoreMark
Fibonacci
while(1)
6,65
memory switched 16 MHz (PLL ON)(2)
off
Range 1,
6,95
mA
5,9
VCORE=1.8 V,
32 MHz
VOS[1:0]=01
5,2
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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Electrical characteristics
STM32L073xx
Table 34. Current consumption in Sleep mode
Symbol
Parameter
Condition
fHCLK (MHz)
Typ
Max(1)
Unit
1
2
43,5
72
110
140
200
220
380
690
460
840
2000
93
Range3,
Vcore=1.2 V
VOS[1:0]=11
4
130
160
305
590
370
715
1650
18
4
fHSE = fHCLK up to
16 MHz included,
Range2,
Vcore=1.5 V
VOS[1:0]=10
8
fHSE = fHCLK/2 above
16 MHz (PLL ON)(2)
16
8
Range1,
Vcore=1.8 V
VOS[1:0]=01
Supply current in
Sleep mode, Flash
memory switched
OFF
16
32
0,065
0,524
4,2
Range3,
Vcore=1.2 V
VOS[1:0]=11
MSI clock
31,5
140
110
230
Range2,
Vcore=1.5 V
VOS[1:0]=10
16
32
665
850
HSI clock source
(16 MHz)
Range1,
Vcore=1.8 V
VOS[1:0]=01
1750
2100
IDD
(Sleep)
µA
1
2
57,5
84
130
160
220
240
400
710
470
860
2000
110
120
240
Range3,
Vcore=1.2 V
VOS[1:0]=11
4
150
170
315
605
380
730
1650
29,5
44,5
150
4
fHSE = fHCLK up to
16MHz included,
Range2,
Vcore=1.5 V
VOS[1:0]=10
8
fHSE = fHCLK/2 above
16 MHz (PLL ON)(2)
16
8
Range1,
Vcore=1.8 V
VOS[1:0]=01
Supply current in
Sleep mode, Flash
memory switched
ON
16
32
0,065
0,524
4,2
Range3,
Vcore=1.2 V
VOS[1:0]=11
MSI clock
Range2,
Vcore=1.5 V
VOS[1:0]=10
16
32
680
930
HSI clock source
(16MHz)
Range1,
Vcore=1.8 V
VOS[1:0]=01
1750
2200
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
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Electrical characteristics
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 35. Current consumption in Low-power run mode
fHCLK
(MHz)
Symbol Parameter
Condition
Typ Max(1) Unit
TA = − 40 to 25°C
TA = 85°C
9,45
14
12
58
MSI clock = 65 kHz,
fHCLK= 32 kHz
0,032
0,065
TA = 105°C
TA = 125°C
TA = − 40 to 25°C
TA = 85°C
21
64
36,5
14,5
19,5
26
160
18
All peripherals
OFF, code
executed from
RAM, Flash
memory switched
OFF, VDD from
1.65 to 3.6 V
60
MSI clock = 65 kHz,
fHCLK= 65kHz
TA = 105°C
TA = 125°C
TA = − 40 to 25°C
TA = 55°C
65
42
160
30
26,5
27,5
31
60
MSI clock=131 kHz,
fHCLK= 131 kHz
TA = 85°C
0,131
66
TA = 105°C
TA = 125°C
TA = − 40 to 25°C
TA = 85°C
37,5
53,5
24,5
30
77
Supply
current in
(LP Run) Low-power
run mode
170
34
IDD
µA
82
MSI clock = 65 kHz,
fHCLK= 32 kHz
0,032
0,065
TA = 105°C
TA = 125°C
TA = − 40 to 25°C
TA = 85°C
38,5
58
90
120
40
30,5
36,5
45
All peripherals
OFF, code
executed from
Flash memory,
VDD from 1.65 V
to 3.6 V
88
MSI clock = 65 kHz,
fHCLK= 65 kHz
TA = 105°C
TA = 125°C
TA = − 40 to 25°C
TA = 55°C
96
64,5
45
120
56
48
96
MSI clock =
131 kHz,
fHCLK= 131 kHz
TA = 85°C
0,131
51
110
120
150
TA = 105°C
TA = 125°C
59,5
79,5
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
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128
Electrical characteristics
STM32L073xx
Figure 17. I vs V , at T = 25 °C, Low-power run mode, code running
DD
DD
A
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS
IDD (mA)
4,5E-02
4,0E-02
3,5E-02
3,0E-02
2,5E-02
2,0E-02
1,5E-02
1,0E-02
5,0E-03
0
VDD (V)
3,6
1,65
1,8
2
2,2
2,4
2,6
-40
2,8
3
3,2
3,4
25
55
85
105
125
MSv37845V2
Table 36. Current consumption in Low-power sleep mode
Max
Symbol
Parameter
Condition
Typ
Unit
(1)
MSI clock = 65 kHz,
f
HCLK= 32 kHz,
TA = −40 to 25°C 4,7
TA = −40 to 25°C 17
-
Flash memory OFF
24
30
47
70
24
31
47
70
27
28
33
50
73
TA = 85°C
TA= 105°C
TA= 125°C
19,5
23
MSI clock = 65 kHz,
fHCLK= 32 kHz
32,5
All peripherals
OFF, code
executed from
TA= − 40 to 25°C 17
Supply current in
Low-power sleep
mode
IDD
(LP Sleep)
µA
TA= 85°C
TA = 105°C
TA = 125°C
20
MSI clock = 65 kHz,
fHCLK= 65 kHz
Flash memory, VDD
from 1.65 to 3.6 V
23,5
32,5
TA= − 40 to 25°C 19,5
TA = 55°C
TA = 85°C
TA = 105°C
TA= 125°C
20,5
22,5
26
MSI clock = 131kHz,
fHCLK= 131 kHz
35
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
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Electrical characteristics
Table 37. Typical and maximum current consumptions in Stop mode
Symbol
Parameter
Conditions
Typ
Max(1) Unit
TA = − 40 to 25°C
TA = 55°C
0,43
0,735
2,25
5,3
1,00
2,50
IDD (Stop) Supply current in Stop mode
TA= 85°C
4,90
13,00
28,00
µA
TA = 105°C
TA = 125°C
12,5
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
Figure 18. I vs V , at T = 25/55/ 85/105/125 °C, Stop mode with RTC enabled
DD
DD
A
and running on LSE Low drive
1.6E-02
1.4E-02
1.2E-02
1.0E-02
8.0E-03
6.0E-03
4.0E-03
2.0E-03
0
VDD (V)
1.65
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C
MSv37846V1
DS10685 Rev 6
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128
Electrical characteristics
STM32L073xx
Figure 19. I vs V , at T = 25/55/85/105/125 °C, Stop mode with RTC disabled,
DD
DD
A
all clocks OFF
1.4E-02
1.2E-02
1.0E-02
8.0E-03
6.0E-03
4.0E-03
2.0E-03
0
VDD (V)
3.6
1.65
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
-40 °C
25 °C
55 °C
85 °C
105 °C
125 °C
MSv37847V1
Table 38. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Conditions
TA = − 40 to 25°C
Typ
Max(1) Unit
0,855
-
1,70
2,90
3,30
4,10
TA = 55 °C
TA= 85 °C
Independent watchdog
and LSI enabled
-
TA = 105 °C
TA = 125 °C
TA = − 40 to 25°C
TA = 55 °C
-
-
8,50
µA
0,60
IDD
(Standby)
Supply current in Standby
mode
0,29
0,32
0,5
0,94
2,6
1,20
2,30
3,00
7,00
Independent watchdog
and LSI OFF
TA = 85 °C
TA = 105 °C
TA = 125 °C
1. Guaranteed by characterization results at 125 °C, unless otherwise specified
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Symbol
Electrical characteristics
Table 39. Average current consumption during Wakeup
Current
parameter
System frequency
consumption
during wakeup
Unit
HSI
HSI/4
1
0,7
0,7
0,4
0,1
0,21
IDD (Wakeup from Supply current during Wakeup from
MSI clock = 4,2 MHz
MSI clock = 1,05 MHz
MSI clock = 65 KHz
-
Stop)
Stop mode
mA
I
DD (Reset)
Reset pin pulled down
BOR ON
I
DD (Power-up)
-
0,23
With Fast wakeup set
MSI clock = 2,1 MHz
MSI clock = 2,1 MHz
0,5
IDD (Wakeup from
StandBy)
With Fast wakeup disabled
0,12
DS10685 Rev 6
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128
Electrical characteristics
STM32L073xx
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following tables. The
MCU is placed under the following conditions:
•
•
•
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked OFF
with only one peripheral clocked on
(1)
Table 40. Peripheral current consumption in Run or Sleep mode
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
Range 2,
Range 3,
Low-power
Peripheral
Unit
VCORE=1.8 V
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
V
CORE=1.5 V
V
CORE=1.2 V
sleep and
run
CRS
2.5
4
2
3.5
9.5
9
2
3
2
2.5
9
DAC1/2
I2C1
11
11
4
7.5
7
I2C3
9
LCD1
3.5
8.5
6.5
4.5
12
4
3
2.5
8
LPTIM1
LPUART1
SPI2
10
8
6.5
5.5
3.5
9.5
3
6
9
4
µA/MHz
APB1
USART2
USART4
USART5
USB
14.5
5
11
5
(fHCLK
)
5
4
3
5
8.5
10.5
12
3.5
3.5
3
4.5
8.5
10
3
4
4.5
9
TIM2
7
TIM3
8
11
2
TIM6
2.5
2.5
2
TIM7
3
2
WWDG
2
2
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STM32L073xx
Electrical characteristics
(1)
Table 40. Peripheral current consumption in Run or Sleep mode (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
VCORE=1.8 V
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
Range 2,
CORE=1.5 V
Range 3,
CORE=1.2 V
Low-power
sleep and
run
Peripheral
Unit
V
V
ADC1(2)
SPI1
5.5
4
5
3
3.5
3
4
2.5
12
5.5
6
USART1
TIM21
14.5
7.5
7
11.5
6
9.5
5
µA/MHz
APB2
(fHCLK
)
TIM22
6
5
FIREWALL
DBGMCU
SYSCFG
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOH
CRC
1.5
1.5
2.5
3.5
3.5
8.5
1
1
1
0.5
0.5
1.5
2.5
2.5
7
1
1
2
2
3
2.5
2
2.5
6.5
0.5
6
Cortex-
M0+ core
I/O port
5.5
0.5
5
µA/MHz
(fHCLK
)
0.5
6
8
1.5
1.5
0(3)
10
5.5
3
1
1
0.5
1
1
1
FLASH
DMA1
0(3)
0(3)
6.5
0.5
2
0(3)
8.5
0.5
3
µA/MHz
(fHCLK
AHB
8
)
RNG
1
TSC
2.5
µA/MHz
(fHCLK
All enabled
PWR
204
2.5
162
2
130
2
202
1
)
µA/MHz
(fHCLK
)
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. Current consumption is negligible and close to 0 µA.
DS10685 Rev 6
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128
Electrical characteristics
STM32L073xx
(1)
Table 41. Peripheral current consumption in Stop and Standby mode
Typical consumption, TA = 25 °C
Symbol
Peripheral
Unit
VDD=1.8 V
VDD=3.0 V
IDD(PVD / BOR)
-
0.7
-
1.2
1.7
IREFINT
-
LSE Low drive(2)
LSI
-
-
-
0.11
0.27
0.2
0,13
0.31
0.3
IWDG
-
-
LPTIM1, Input 100 Hz
LPTIM1, Input 1 MHz
0.01
11
0,01
12
µA
-
-
-
LPUART1
RTC
-
0,5
0,3
0.16
0.15
LCD1 (static duty)
0.15
µA
-
LCD1 (1/8 duty)
1.6
2.6
1. LCD, LPTIM, LPUART peripherals can operate in Stop mode but not in Standby mode.
2. LSE Low drive consumption is the difference between an external clock on OSC32_IN and a quartz between OSC32_IN
and OSC32_OUT.-
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI or HSI16 RC
oscillator. The clock source used to wake up the device depends on the current operating
mode:
•
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
Stop mode: the clock source is either the MSI oscillator in the range configured before
entering Stop mode, the HSI16 or HSI16/4.
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 26.
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Symbol
Electrical characteristics
Table 42. Low-power mode wakeup timings
Parameter Conditions
fHCLK = 32 MHz
Typ
Max
Unit
tWUSLEEP Wakeup from Sleep mode
7
8
fHCLK = 262 kHz
Flash memory enabled
Number
of clock
cycles
7
9
8
tWUSLEEP_ Wakeup from Low-power sleep mode,
fHCLK = 262 kHz
LP
f
HCLK = 262 kHz
10
Flash memory switched OFF
fHCLK = fMSI = 4.2 MHz
fHCLK = fHSI = 16 MHz
fHCLK = fHSI/4 = 4 MHz
5.0
4.9
8.0
8
7
Wakeup from Stop mode, regulator in Run
mode
11
fHCLK = fMSI = 4.2 MHz
Voltage range 1
5.0
5.0
5.0
8
8
8
fHCLK = fMSI = 4.2 MHz
Voltage range 2
f
HCLK = fMSI = 4.2 MHz
Voltage range 3
f
HCLK = fMSI = 2.1 MHz
7.3
13
13
23
38
65
120
260
7
Wakeup from Stop mode, regulator in low-
power mode
fHCLK = fMSI = 1.05 MHz
fHCLK = fMSI = 524 kHz
tWUSTOP
µs
28
f
HCLK = fMSI = 262 kHz
51
fHCLK = fMSI = 131 kHz
fHCLK = MSI = 65 kHz
100
190
4.9
8.0
4.9
7.9
4.7
f
HCLK = fHSI = 16 MHz
fHCLK = fHSI/4 = 4 MHz
fHCLK = fHSI = 16 MHz
11
7
Wakeup from Stop mode, regulator in low-
power mode, code running from RAM
f
HCLK = fHSI/4 = 4 MHz
10
8
fHCLK = fMSI = 4.2 MHz
fHCLK = MSI = 2.1 MHz
Wakeup from Standby mode
FWU bit = 1
65
130
3
tWUSTDBY
Wakeup from Standby mode
FWU bit = 0
f
HCLK = MSI = 2.1 MHz
2.2
ms
µs
Wakeup time required to calculate the
maximum USART/LPUART baudrate
while waking up from Stop mode using the mode
USART/LPUART
tWUUSART
Stop mode, regulator in Run
tWUSTOP
tWULPUART
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Electrical characteristics
STM32L073xx
6.3.6
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the
recommended clock input waveform is shown in Figure 20.
(1)
Table 43. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CSS is ON or
PLL is used
1
8
32
MHz
User external clock source
frequency
fHSE_ext
CSS is OFF,
PLL not used
0
8
32
MHz
V
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
0.3VDD
OSC_IN high or low time
OSC_IN rise or fall time
12
-
-
-
-
tw(HSE)
-
ns
tr(HSE)
tf(HSE)
20
Cin(HSE) OSC_IN input capacitance
DuCy(HSE) Duty cycle
-
45
-
2.6
-
pF
%
-
-
55
±1
IL
OSC_IN Input leakage current
VSS ≤ VIN ≤ VDD
µA
1. Guaranteed by design.
Figure 20. High-speed external clock source AC timing diagram
VHSEH
90%
10%
VHSEL
t
tW(HSE)
tr(HSE)
tf(HSE)
tW(HSE)
THSE
fHSE_ext
EXTERNAL
IL
STM32Lxx
OSC _IN
CLOCK SOURCE
ai18232c
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STM32L073xx
Electrical characteristics
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 26.
(1)
Table 44. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
1
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSE)
0.7VDD
VSS
465
-
-
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level
voltage
-
OSC32_IN high or low time
OSC32_IN rise or fall time
tw(LSE)
ns
tr(LSE)
tf(LSE)
10
CIN(LSE) OSC32_IN input capacitance
DuCy(LSE) Duty cycle
-
-
-
45
-
0.6
-
pF
%
-
-
55
±1
IL
OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD
µA
1. Guaranteed by design, not tested in production
Figure 21. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
t
tW(LSE)
tr(LSE)
tf(LSE)
tW(LSE)
TLSE
fLSE_ext
EXTERNAL
IL
STM32Lxx
OSC32_IN
CLOCK SOURCE
ai18233c
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Electrical characteristics
STM32L073xx
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 45. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 45. HSE oscillator characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
fOSC_IN Oscillator frequency
-
-
1
-
25 MHz
RF
Feedback resistor
200
-
-
kΩ
Maximum critical crystal
transconductance
µA
/V
Gm
Startup
-
-
700
tSU(HSE)
Startup time
VDD is stabilized
2
-
ms
(2)
1. Guaranteed by design.
2. Guaranteed by characterization results. tSU(HSE) is the startup time measured from the moment it is
enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 22). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C . Refer to the application note AN2867 “Oscillator design guide for ST
C
L1
L2
microcontrollers” available from the ST website www.st.com.
Figure 22. HSE oscillator circuit diagram
f
to core
HSE
R
m
R
F
C
O
L
m
C
L1
OSC_IN
C
m
g
m
Resonator
Consumption
control
Resonator
STM32
OSC_OUT
C
L2
ai18235b
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DS10685 Rev 6
STM32L073xx
Electrical characteristics
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 46. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 46. LSE oscillator characteristics
Symbol
Parameter
Conditions(2)
Min(2) Typ
Max Unit
fLSE
LSE oscillator frequency
-
-
32.768
-
-
kHz
µA/V
s
LSEDRV[1:0]=00
lower driving capability
0.5
LSEDRV[1:0]= 01
medium low driving capability
-
-
-
-
0.75
1.7
Maximum critical crystal
transconductance
Gm
LSEDRV[1:0] = 10
medium high driving capability
LSEDRV[1:0]=11
higher driving capability
-
-
-
2.7
-
(3)
tSU(LSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. Guaranteed by characterization results. tSU(LSE) is the startup time measured from the moment it is enabled (by software)
to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a high- driver mode.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 23. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
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Electrical characteristics
STM32L073xx
6.3.7
Internal clock source characteristics
The parameters given in Table 47 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 26.
DD
High-speed internal 16 MHz (HSI16) RC oscillator
Table 47. 16 MHz HSI16 oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ Max Unit
fHSI16
VDD = 3.0 V
-
-
16
-
MHz
%
Trimming code is not a multiple of 16
Trimming code is a multiple of 16
VDDA = 3.0 V, TA = 25 °C
0.4 0.7
HSI16 user-
trimmed resolution
(1)(2)
TRIM
-
-
-
-
-
-
-
1.5
%
-1(3)
-1.5
-2
1(3)
1.5
2
%
VDDA = 3.0 V, TA = 0 to 55 °C
VDDA = 3.0 V, TA = -10 to 70 °C
%
%
Accuracy of the
factory-calibrated
HSI16 oscillator
ACCHSI16
(2)
V
DDA = 3.0 V, TA = -10 to 85 °C
VDDA = 3.0 V, TA = -10 to 105 °C
DDA = 1.65 V to 3.6 V
-2.5
-4
2
%
2
%
V
-5.45
-
3.25
6
%
µs
µA
TA = − 40 to 125 °C
HSI16 oscillator
startup time
(2)
tSU(HSI16)
-
-
-
3.7
100
HSI16 oscillator
power consumption
(2)
IDD(HSI16)
-
140
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
Figure 24. HSI16 minimum and maximum value versus temperature
4.00%
3.00%
2.00%
1.00%
1.65V min
3V typ
0.00%
-20
-60
-40
0
20
40
60
80
100
120
140
-1.00%
-2.00%
-3.00%
-4.00%
-5.00%
-6.00%
3.6V max
1.65V max
3.6V min
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High-speed internal 48 MHz (HSI48) RC oscillator
(1)
Table 48. HSI48 oscillator characteristics
Symbol
Parameter
Frequency
HSI48 user-trimming step
Conditions
Min
Typ
Max
Unit
fHSI48
TRIM
-
48
0.14
-
-
MHz
%
0.09(2)
45(2)
0.2(2)
55(2)
DuCy(HSI48) Duty cycle
Accuracy of the HSI48
ACCHSI48 oscillator (factory calibrated TA = 25 °C
before CRS calibration)
%
-4(3)
-
4(3)
%
tsu(HSI48) HSI48 oscillator startup time
-
-
-
6(2)
µs
HSI48 oscillator power
IDDA(HSI48)
330
380(2)
µA
consumption
1.
VDDA = 3.3 V, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
Low-speed internal (LSI) RC oscillator
Table 49. LSI oscillator characteristics
Symbol
Parameter
LSI frequency
Min
Typ
Max
Unit
(1)
fLSI
26
38
56
4
kHz
%
LSI oscillator frequency drift
0°C ≤ TA ≤ 85°C
(2)
DLSI
-10
-
(3)
tsu(LSI)
LSI oscillator startup time
-
-
-
200
510
µs
(3)
IDD(LSI)
LSI oscillator power consumption
400
nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design.
Multi-speed internal (MSI) RC oscillator
Table 50. MSI oscillator characteristics
Symbol
Parameter
Condition
Typ
Max Unit
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
65.5
131
262
524
1.05
2.1
-
-
kHz
-
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
fMSI
-
-
-
-
MHz
4.2
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Typ Max Unit
Table 50. MSI oscillator characteristics (continued)
Symbol
Parameter
Condition
ACCMSI
Frequency error after factory calibration
-
0.5
3
-
-
%
MSI oscillator frequency drift
0 °C ≤ TA ≤ 85 °C
-
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
− 8.9
− 7.1
− 6.4
− 6.2
− 5.2
− 4.8
− 4.7
+7.0
+5.0
+4.0
+3.0
+3.0
+2.0
+2.0
(1)
DTEMP(MSI)
%
MSI oscillator frequency drift
VDD = 3.3 V, − 40 °C ≤ TA ≤ 110 °C
MSI oscillator frequency drift
1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C
(1)
DVOLT(MSI)
-
-
2.5 %/V
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
0.75
1
-
-
-
1.5
2.5
4.5
8
(2)
IDD(MSI)
MSI oscillator power consumption
-
-
-
-
-
-
-
-
-
-
µA
15
30
20
15
10
6
tSU(MSI)
MSI oscillator startup time
µs
5
MSI range 6,
Voltage range 1
and 2
3.5
5
-
-
MSI range 6,
Voltage range 3
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Table 50. MSI oscillator characteristics (continued)
Symbol
Parameter
Condition
Typ
Max Unit
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
-
-
-
-
-
-
40
20
10
4
2.5
µs
2
(2)
tSTAB(MSI)
MSI oscillator stabilization time
MSI range 6,
Voltage range 1
and 2
-
2
3
MSI range 3,
Voltage range 3
-
-
-
Any range to
range 5
4
fOVER(MSI) MSI oscillator frequency overshoot
MHz
6
Any range to
range 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.
6.3.8
PLL characteristics
The parameters given in Table 51 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 26.
DD
Table 51. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
45
2
-
-
-
24
55
32
MHz
%
fPLL_IN
fPLL_OUT
tLOCK
PLL input clock duty cycle
PLL output clock
MHz
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
µs
ps
Jitter
Cycle-to-cycle jitter
-
-
-
600
450
150
IDDA(PLL)
IDD(PLL)
Current consumption on VDDA
Current consumption on VDD
220
120
µA
1. Guaranteed by characterization results.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
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6.3.9
Memory characteristics
RAM memory
Table 52. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM Data retention mode(1)
STOP mode (or RESET)
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
Flash memory and data EEPROM
Table 53. Flash memory and data EEPROM characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
Operating voltage
VDD
-
1.65
-
3.6
V
Read / Write / Erase
Erasing
-
-
3.28
3.28
3.94
3.94
Programming time for
word or half-page
tprog
ms
Programming
Average current during
the whole programming /
erase operation
-
-
500
1.5
700
2.5
µA
IDD
TA = 25 °C, VDD = 3.6 V
Maximum current (peak)
during the whole
programming / erase
operation
mA
1. Guaranteed by design.
Table 54. Flash memory and data EEPROM endurance and retention
Value
Symbol
Parameter
Conditions
Unit
Min(1)
Cycling (erase / write)
Program memory
10
TA = -40°C to 105 °C
Cycling (erase / write)
EEPROM data memory
100
0.2
2
(2)
NCYC
kcycles
Cycling (erase / write)
Program memory
TA = -40°C to 125 °C
Cycling (erase / write)
EEPROM data memory
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Electrical characteristics
Table 54. Flash memory and data EEPROM endurance and retention (continued)
Value
Symbol
Parameter
Conditions
Unit
Min(1)
Data retention (program memory) after
10 kcycles at TA = 85 °C
30
TRET = +85 °C
Data retention (EEPROM data memory)
after 100 kcycles at TA = 85 °C
30
10
Data retention (program memory) after
10 kcycles at TA = 105 °C
(2)
tRET
TRET = +105 °C
years
Data retention (EEPROM data memory)
after 100 kcycles at TA = 105 °C
Data retention (program memory) after
200 cycles at TA = 125 °C
TRET = +125 °C
Data retention (EEPROM data memory)
after 2 kcycles at TA = 125 °C
1. Guaranteed by characterization results.
2. Characterization is done according to JEDEC JESD22-A117.
6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 55. They are based on the EMS levels and classes
defined in application note AN1709.
Table 55. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
3B
4A
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
VEFTB
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STM32L073xx
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 56. EMI characteristics
Max vs.
Monitored
frequency band
frequency
range at
32 MHz
Symbol Parameter
Conditions
Unit
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
EMI Level
-7
14
9
VDD = 3.6 V,
TA = 25 °C,
LQFP100 package
compliant with IEC 61967-2
dBµV
-
SEMI
Peak level
2
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Electrical characteristics
6.3.11
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 57. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
TA = +25 °C,
Electrostatic discharge
voltage (human body model)
VESD(HBM)
conforming to
2
2000
ANSI/JEDEC JS-001
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C,
conforming to
C4
500
ANSI/ESD STM5.3.1.
1. Guaranteed by characterization results.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 58. Electrical sensitivities
Symbol
Parameter
Conditions
Class
II level A
LU
Static latch-up class
TA = +125 °C conforming to JESD78A
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6.3.12
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard pins) should be avoided during normal product operation.
DD
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation).
The test results are given in the Table 59.
Table 59. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0
-0
-5
NA(1)
Injected current on PA0, PA4, PA5, PC15,
PH0 and PH1
0
IINJ
mA
Injected current on any other FT, FTf pins
Injected current on any other pins
-5 (2)
-5 (2)
NA(1)
+5
1. Current injection is not possible.
2. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
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Electrical characteristics
6.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under the conditions summarized in Table 26. All I/Os are CMOS and TTL
compliant.
Note:
For information on GPIO configuration, refer to application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption” available from the ST
website www.st.com.
Table 60. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TC, FT, FTf, RST
I/Os
-
-
0.3VDD
VIL
Input low level voltage
Input high level voltage
(1)
BOOT0 pin
All I/Os
-
-
-
0.14VDD
V
VIH
0.7 VDD
-
-
-
(3)
Standard I/Os
BOOT0 pin
-
-
10% VDD
0.01
I/O Schmitt trigger voltage hysteresis
Vhys
(2)
VSS ≤ VIN ≤ VDD
All I/Os except for
PA11, PA12, BOOT0
and FTf I/Os
-
-
±50
nA
VSS ≤ VIN ≤ VDD
PA11 and PA12 I/Os
,
-
-
-
-
-50/+250
±100
VSS ≤ VIN ≤ VDD
FTf I/Os
Ilkg
Input leakage current (4)
VDD≤ VIN ≤ 5 V
All I/Os except for
PA11, PA12, BOOT0
and FTf I/Os
-
-
200
nA
µA
VDD≤ VIN ≤ 5 V
-
-
-
-
500
10
FTf I/Os
VDD≤ VIN ≤ 5 V
PA11, PA12 and
BOOT0
RPU
RPD
CIO
Weak pull-up equivalent resistor(5)
Weak pull-down equivalent resistor(5)
I/O pin capacitance
VIN = VSS
VIN = VDD
-
25
25
-
45
45
5
65
65
-
kΩ
kΩ
pF
1. Guaranteed by characterization.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
3. With a minimum of 200 mV. Guaranteed by characterization results.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Figure 25. V /V versus VDD (CMOS I/Os)
IH IL
VIL/VIH (V)
VIHmin 2.0
1.3
Input range not
guaranteed
CMOS standard requirements VILmax = 0.3VDD
VILmax 0.7
0.6
VDD (V)
2.0
2.7
3.0
3.3
3.6
MSv34789V1
Figure 26. V /V versus VDD (TTL I/Os)
IH IL
VIL/VIH (V)
TTL standard requirements VIHmin = 2 V
VIHmin 2.0
1.3
Input range not
guaranteed
VILmax 0.8
0.7
TTL standard requirements VILmax = 0.8 V
VDD (V)
2.0
2.7
3.0
3.3
3.6
MSv34790V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±15 mA with the non-standard V /V specifications given in Table 61.
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 24).
VDD(Σ)
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 24).
VSS(Σ)
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Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 26. All I/Os are CMOS and TTL compliant.
Table 61. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
Output low level voltage for an I/O
pin
(1)
CMOS port(2)
IIO = +8 mA
2.7 V ≤ VDD ≤ 3.6 V
,
VOL
-
0.4
Output high level voltage for an I/O
pin
(3)
VOH
VDD-0.4
-
TTL port(2)
IIO =+ 8 mA
2.7 V ≤ VDD ≤ 3.6 V
,
Output low level voltage for an I/O
pin
(1)
VOL
-
0.4
TTL port(2)
IIO = -6 mA
2.7 V ≤ VDD ≤ 3.6 V
,
Output high level voltage for an I/O
pin
(3)(4)
VOH
2.4
-
-
Output low level voltage for an I/O
pin
IIO = +15 mA
2.7 V ≤ VDD ≤ 3.6 V
(1)(4)
VOL
1.3
V
Output high level voltage for an I/O
pin
IIO = -15 mA
2.7 V ≤ VDD ≤ 3.6 V
(3)(4)
VOH
V
DD-1.3
-
0.45
-
Output low level voltage for an I/O
pin
IIO = +4 mA
1.65 V ≤ VDD < 3.6 V
(1)(4)
VOL
-
Output high level voltage for an I/O
pin
IIO = -4 mA
1.65 V ≤ VDD ≤ 3.6 V
(3)(4)
VOH
VDD-0.45
IIO = 20 mA
2.7 V ≤ VDD ≤ 3.6 V
-
-
0.4
0.4
Output low level voltage for an FTf
I/O pin in Fm+ mode
(1)(4)
VOLFM+
I
IO = 10 mA
1.65 V ≤ VDD ≤ 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 24.
The sum of the currents sunk by all the I/Os (I/O ports and control pins) must always be respected and
must not exceed ΣIIO(PIN)
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 24. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be
respected and must not exceed ΣIIO(PIN)
.
4. Guaranteed by characterization results.
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 27 and
Table 62, respectively.
Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 26.
(1)
Table 62. I/O AC characteristics
OSPEEDRx[1:0]
bit value(1)
Symbol
Parameter
Conditions
Min Max(2) Unit
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
100
125
320
2
fmax(IO)out Maximum frequency(3)
kHz
ns
00
01
10
11
tf(IO)out
Output rise and fall time
tr(IO)out
fmax(IO)out Maximum frequency(3)
MHz
ns
0.6
30
65
10
2
tf(IO)out
Output rise and fall time
tr(IO)out
Fmax(IO)out Maximum frequency(3)
MHz
ns
13
28
35
10
6
tf(IO)out
Output rise and fall time
tr(IO)out
Fmax(IO)out Maximum frequency(3)
MHz
tf(IO)out
Output rise and fall time
tr(IO)out
ns
MHz
ns
17
1
fmax(IO)out Maximum frequency(3)
tf(IO)out
Output fall time
CL = 50 pF, VDD = 2.5 V to 3.6 V
10
30
350
15
60
tr(IO)out
Output rise time
Fm+
configuration(4)
fmax(IO)out Maximum frequency(3)
KHz
ns
tf(IO)out
tr(IO)out
Output fall time
Output rise time
CL = 50 pF, VDD = 1.65 V to 3.6 V
Pulse width of external
signals detected by the
EXTI controller
-
tEXTIpw
-
8
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO Port
configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 27.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the line reference manual for a detailed
description of Fm+ I/O configuration.
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STM32L073xx
Electrical characteristics
Figure 27. I/O AC characteristics definition
90%
10%
50%
50%
90%
t
10%
t
EXTERNAL
OUTPUT
ON CL
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t ) ≤ (2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by CL specified in the table “ I/O AC characteristics”.
ai14131d
6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R , except when it is internally driven low (see Table 63).
PU
Unless otherwise specified, the parameters given in Table 63 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 26.
Table 63. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
(1)
VIL(NRST)
NRST input low level voltage
NRST input high level voltage
-
-
VSS
1.4
-
-
0.8
(1)
VIH(NRST)
VDD
IOL = 2 mA
2.7 V < VDD < 3.6 V
V
-
-
-
NRST output low level
voltage
(1)
VOL(NRST)
0.4
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
10%VDD
45
NRST Schmitt trigger voltage
hysteresis
(1)
(2)
Vhys(NRST)
RPU
-
-
-
mV
Weak pull-up equivalent
resistor(3)
VIN = VSS
25
65
kΩ
(1)
VF(NRST)
NRST input filtered pulse
-
-
-
-
-
50
-
ns
ns
(1)
VNF(NRST)
NRST input not filtered pulse
350
1. Guaranteed by design.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
DS10685 Rev 6
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128
Electrical characteristics
STM32L073xx
Figure 28. Recommended NRST pin protection
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UHVHWꢅFLUFXLWꢆꢀꢇ
9''
538
1567ꢆꢈꢇ
,QWHUQDOꢅUHVHW
)LOWHU
ꢉꢊꢀꢅ)
06ꢀꢁꢂꢃꢂ9ꢄ
1. The reset network protects the device against parasitic resets.
2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 63. Otherwise the reset will not be taken into account by the device.
6.3.15
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 64 are derived from tests
performed under ambient temperature, f
frequency and V
supply voltage conditions
PCLK
DDA
summarized in Table 26: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 64. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fast channel
Standard channel
-
1.65
-
-
3.6
Analog supply voltage for
ADC ON
VDDA
V
V
1.75(1)
3.6
VREF+
VREF-
Positive reference voltage
Negative reference voltage
1.65
VDDA
-
-
0
200
40
70
1
-
1.14 Msps
-
-
-
Current consumption of the
ADC on VDDAand VREF+
10 ksps
-
-
IDDA (ADC)
µA
1.14 Msps
-
Current consumption of the
(2)
ADC on VDD
10 ksps
-
-
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 3
12-bit resolution
0.14
0.14
0.14
0.01
-
16
8
fADC
ADC clock frequency
-
MHz
-
4
(3)
fS
Sampling rate
-
1.14
MHz
kHz
fADC = 16 MHz,
12-bit resolution
-
-
941
(3)
External trigger frequency
Conversion voltage range
fTRIG
-
-
-
-
-
17
1/fADC
V
VAIN
0
VREF+
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Electrical characteristics
Table 64. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
50
1
Unit
kΩ
See Equation 1 and
Table 65 for details
(3)
RAIN
External input impedance
Sampling switch resistance
-
-
-
-
-
-
(3)(4)
-
-
kΩ
RADC
Internal sample and hold
capacitor
(3)
8
pF
CADC
f
ADC = 16 MHz
5.2
83
µs
(3)(5)
Calibration time
tCAL
-
1/fADC
1.5 ADC
cycles + 3
fPCLK cycles
1.5 ADC
cycles + 2
PCLK cycles
ADC clock = HSI16
-
-
f
ADC_DR register write
latency
(6)
fPCLK
cycle
WLATENCY
ADC clock = PCLK/2
ADC clock = PCLK/4
-
-
4.5
8.5
-
-
fPCLK
cycle
fADC = fPCLK/2 = 16 MHz
fADC = fPCLK/2
0.266
8.5
µs
1/fPCLK
µs
(3)
Trigger conversion latency fADC = fPCLK/4 = 8 MHz
fADC = fPCLK/4
0.516
16.5
-
tlatr
1/fPCLK
µs
fADC = fHSI16 = 16 MHz
0.252
-
0.260
-
ADC jitter on trigger
fADC = fHSI16
JitterADC
1
1/fHSI16
conversion
f
ADC = 16 MHz
0.093
1.5
-
-
-
10.03
160.5
10
µs
(3)
Sampling time
tS
-
-
-
1/fADC
µs
(3)(5)
tUP_LDO
Internal LDO power-up time
ADC stabilization time
-
(3)(5)
tSTAB
14
1/fADC
fADC = 16 MHz,
12-bit resolution
0.875
-
10.81
µs
Total conversion time
(including sampling time)
(3)
tConV
14 to 173 (tS for sampling +12.5
for successive approximation)
12-bit resolution
1/fADC
1. VDDA minimum value can be decreased in specific temperature conditions. Refer to Table 65: RAIN max for fADC = 16 MHz.
2. A current consumption proportional to the APB clock frequency has to be added (see Table 40: Peripheral current
consumption in Run or Sleep mode).
3. Guaranteed by design.
4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 65: RAIN max for
fADC = 16 MHz.
5. This parameter only includes the ADC timing. It does not take into account register access latency.
6. This parameter specifies the latency to transfer the conversion result into the ADC_DR register. EOC bit is set to indicate the
conversion is complete and has the same latency.
DS10685 Rev 6
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128
Electrical characteristics
Equation 1: R
STM32L073xx
max formula
AIN
TS
RAIN < ------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The simplified formula above (Equation 1) is used to determine the maximum external
impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
(1)
Table 65. R
max for f
= 16 MHz
AIN
ADC
RAIN max for standard channels (kΩ)
RAIN max for
fast channels
(kΩ)
Ts
tS
VDD > 1.65 V
and
V
DD > 1.65 V
VDD
2.7 V
>
VDD
2.4 V
>
VDD
2.0 V
>
VDD
1.8 V
>
VDD >
1.75 V
(cycles) (µs)
and
TA > −10 °C
TA > 25 °C
1.5
3.5
0.09
0.22
0.47
0.78
1.22
2.47
4.97
0.5
1
< 0.1
0.2
NA
< 0.1
1.5
3
NA
NA
< 0.1
1
NA
NA
NA
NA
NA
NA
< 0.1
32
NA
NA
NA
NA
NA
NA
NA
NA
< 0.1
5
7.5
2.5
4
1.7
NA
NA
12.5
19.5
39.5
79.5
3.2
NA
NA
6.5
13
27
50
5.7
5.5
12
3.5
10
NA
NA
12.2
26.2
49.2
NA
NA
26
24
NA
NA
19
160.5 10.03
49
47
< 0.1
< 0.1
42
1. Guaranteed by design.
(1)(2)(3)
Table 66. ADC accuracy
Symbol
Parameter
Total unadjusted error
Conditions
Min
Typ
Max
Unit
ET
EO
EG
EL
-
2
1
4
Offset error
Gain error
-
2.5
2
-
1
LSB
Integral linearity error
Differential linearity error
Effective number of bits
-
-
1.5
1
2.5
1.5
ED
10.2
11
1.65 V < VDDA = VREF+< 3.6 V,
range 1/2/3
ENOB
bits
dB
Effective number of bits (16-bit mode
oversampling with ratio =256)(4)
11.3 12.1
-
SINAD Signal-to-noise distortion
63
63
69
69
-
-
Signal-to-noise ratio
SNR
Signal-to-noise ratio (16-bit mode
70
-
76
-
oversampling with ratio =256)(4)
THD
Total harmonic distortion
-85
-73
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STM32L073xx
Symbol
Electrical characteristics
(1)(2)(3)
Table 66. ADC accuracy
(continued)
Parameter
Conditions
Min
Typ
Max
Unit
ET
EO
EG
EL
Total unadjusted error
-
-
-
-
-
2
1
5
2.5
2
Offset error
Gain error
1
LSB
Integral linearity error
1.5
1
3
1.65 V < VREF+ <VDDA < 3.6 V,
range 1/2/3
ED
Differential linearity error
2
ENOB Effective number of bits
SINAD Signal-to-noise distortion
10.0 11.0
-
bits
dB
62
61
-
69
69
-
SNR
THD
Signal-to-noise ratio
-
Total harmonic distortion
-85
-65
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode.
Figure 29. ADC accuracy characteristics
VSSA
4095
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4094
4093
(3) End point correlation line
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
EO = offset error: maximum deviation
between the first actual transition and
the first ideal one.
EG = gain error: deviation between the last
ideal transition and the last actual one.
ED = differential linearity error: maximum
deviation between actual steps and the ideal ones.
EL = integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
(2)
ET
(3)
7
(1)
6
5
4
3
2
1
EO
EL
ED
1 LSB IDEAL
0
4096
VDDA
4094 4095
7
4093
2
3
4
5
6
1
MS19880V2
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Electrical characteristics
STM32L073xx
Figure 30. Typical connection diagram using the ADC
V
DDA
Sample and hold ADC
converter
V
T
(1)
R
R
AIN
ADC
AINx
parasitic
12-bit
converter
IL 50nA
C
V
T
V
AIN
C
ADC
MSv34712V1
1. Refer to Table 64: ADC characteristics for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 31 or Figure 32,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed as close as possible to the chip.
Figure 31. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
STM32Lxx
V
REF+
1 μF // 100 nF
V
DDA
1 μF // 100 nF
V
/ V
SSA REF–
MS39601V1
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DS10685 Rev 6
STM32L073xx
Electrical characteristics
Figure 32. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32Lxx
VREF+/VDDA
1 μF // 100 nF
VREF–/VSSA
MS39602V1
DS10685 Rev 6
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128
Electrical characteristics
STM32L073xx
6.3.16
DAC electrical characteristics
Data guaranteed by design, not tested in production, unless otherwise specified.
Table 67. DAC characteristics
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
1.8
-
3.6
V
V
REF+ must always be
VREF+
VREF-
Reference supply voltage
Lower reference voltage
1.8
-
3.6
V
V
below VDDA
-
VSSA
No load, middle code
(0x800)
-
-
-
-
130
220
210
320
220
350
320
520
Current consumption on VREF+
supply
VREF+ = 3.3 V
(1)
IDDVREF+
µA
µA
No load, worst code
(0x000)
No load, middle code
(0x800)
Current consumption on VDDA
supply,
VDDA = 3.3 V
(2)
IDDA
No load, worst code
(0xF1C)
RL
connected
to VSSA
5
-
-
-
-
DAC output
ON
(3)
RL
Resistive load
kΩ
RL
connected
to VDDA
25
(3)
CL
Capacitive load
DAC output buffer ON
DAC output buffer OFF
-
-
50
20
pF
RO
Output impedance
12
16
kΩ
DAC output buffer ON
DAC output buffer OFF
0.2
0.5
-
-
V
DDA – 0.2
V
VDAC_OUT
Voltage on DAC_OUT output
VREF+
1LSB
–
mV
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DS10685 Rev 6
STM32L073xx
Symbol
Electrical characteristics
Table 67. DAC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
1.5
3
DNL(2)
Differential non linearity(4)
Integral non linearity(5)
No RLOAD, CL ≤ 50 pF
-
-
-
-
-
-
1.5
2
3
4
DAC output buffer OFF
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
INL(2)
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
LSB
2
4
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
±10
±5
±25
±8
±5
Offset(2)
Offset error at code 0x800 (6)
Offset error at code 0x001(7)
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
Offset1(2)
±1.5
VDDA = 3.3V
VREF+= 3.0 V
TA = 0 to 50 °C
DAC output buffer OFF
-20
0
-10
20
0
Offset error temperature
coefficient (code 0x800)
dOffset/dT(2)
µV/°C
VDDA = 3.3V
VREF+= 3.0 V
TA = 0 to 50 °C
DAC output buffer ON
50
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
+0.1 / -0.2% +0.2 / -0.5%
+0 / -0.2% +0 / -0.4%
DAC output buffer ON
Gain(2)
Gain error(8)
%
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
VDDA = 3.3V
VREF+= 3.0 V
TA = 0 to 50 °C
DAC output buffer OFF
-10
-40
-2
-8
0
0
Gain error temperature
coefficient
dGain/dT(2)
µV/°C
VDDA = 3.3V
VREF+= 3.0 V
TA = 0 to 50 °C
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
12
8
30
12
DAC output buffer ON
TUE(2)
Total unadjusted error
LSB
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
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128
Electrical characteristics
STM32L073xx
Table 67. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Settling time (full scale: for a
12-bit code transition between
the lowest and the highest
input codes till DAC_OUT
reaches final value ±1LSB
tSETTLING
CL ≤ 50 pF, RL ≥ 5 kΩ
-
7
12
µs
Max frequency for a correct
DAC_OUT change (95% of
final value) with 1 LSB
Update rate
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
1
Msps
variation in the input code
Wakeup time from off state
tWAKEUP
PSRR+
(setting the ENx bit in the DAC CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
9
15
µs
Control register)(9)
VDDA supply rejection ratio
CL ≤ 50 pF, RL ≥ 5 kΩ
-60
-35
dB
(static DC measurement)
1. Guaranteed by characterization results.
2. Guaranteed by design, not tested in production.
3. Connected between DAC_OUT and V
.
SSA
4. Difference between two consecutive codes - 1 LSB.
5. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
6. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
7. Difference between the value measured at Code (0x001) and the ideal value.
8. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (V
– 0.2) V when buffer is ON.
DDA
9. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 33. 12-bit buffered/non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
L
12-bit
digital to
analog
DAC_OUTx
converter
C
L
MSv45341V1
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
114/157
DS10685 Rev 6
STM32L073xx
Electrical characteristics
6.3.17
Temperature sensor characteristics
Table 68. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
temperature of 30 °C, VDDA= 3 V
TS_CAL1
0x1FF8 007A - 0x1FF8 007B
TS ADC raw data acquired at
temperature of 130 °C, VDDA= 3 V
TS_CAL2
0x1FF8 007E - 0x1FF8 007F
Table 69. Temperature sensor characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
-
1.48
640
-
1
1.61
670
3.4
-
2
°C
Avg_Slope(1) Average slope
V130
Voltage at 130°C ±5°C(2)
IDDA
1.75 mV/°C
700
6
mV
µA
(3)
Current consumption
(TEMP)
(3)
tSTART
Startup time
-
10
-
µs
(4)(3)
TS_temp
ADC sampling time when reading the temperature
10
-
1. Guaranteed by characterization results.
2. Measured at VDD = 3 V ±10 mV. V130 ADC conversion result is stored in the TS_CAL2 byte.
3. Guaranteed by design.
4. Shortest sampling time can be determined in the application by multiple iterations.
6.3.18
Comparators
Table 70. Comparator 1 characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
VDDA
Analog supply voltage
-
1.65
3.6
V
Comparator 1 input voltage
range
VIN
-
0.6
-
VDDA
V
tSTART
td
Comparator startup time
Propagation delay(2)
Comparator offset
-
-
-
-
-
-
7
3
3
10
10
10
µs
Voffset
mV
mV/1000 h
nA
Comparator offset variation in VDDA = 3.6 V, VIN+ = 0 V,
worst voltage stress conditions VIN- = VREFINT, TA = 25 °C
Current consumption(3)
dVoffset/dt
ICOMP1
0
-
1.5
10
-
160
260
1. Guaranteed by characterization.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to
the reference.
3. Comparator consumption only. Internal reference voltage not included.
DS10685 Rev 6
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128
Electrical characteristics
Symbol
STM32L073xx
Table 71. Comparator 2 characteristics
Parameter
Conditions
Min Typ Max(1) Unit
VDDA
VIN
Analog supply voltage
-
-
1.65
-
3.6
VDDA
20
25
3.5
6
V
V
Comparator 2 input voltage range
0
-
-
-
-
-
-
-
-
Fast mode
15
20
1.8
2.5
0.8
1.2
4
tSTART
Comparator startup time
Slow mode
1.65 V ≤ VDDA ≤ 2.7 V
2.7 V ≤ VDDA ≤ 3.6 V
1.65 V ≤ VDDA ≤ 2.7 V
2.7 V ≤ VDDA ≤ 3.6 V
td slow
Propagation delay(2) in slow mode
µs
2
td fast
Propagation delay(2) in fast mode
Comparator offset error
4
Voffset
20
mV
VDDA = 3.3V, TA = 0 to 50 °C,
V- = VREFINT
,
dThreshold/ Threshold voltage temperature
ppm
/°C
3/4 VREFINT
1/2 VREFINT
1/4 VREFINT
,
,
.
-
15
30
dt
coefficient
Fast mode
Slow mode
-
-
3.5
0.5
5
2
ICOMP2
Current consumption(3)
µA
1. Guaranteed by characterization results.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to
the reference.
3. Comparator consumption only. Internal reference voltage (required for comparator operation) is not included.
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Electrical characteristics
6.3.19
Timer characteristics
TIM timer characteristics
The parameters given in the Table 72 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 72. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
1
-
tTIMxCLK
ns
tres(TIM)
Timer resolution time
fTIMxCLK = 32 MHz 31.25
0
-
fTIMxCLK/2
16
MHz
MHz
bit
Timer external clock frequency on CH1
to CH4
fEXT
f
TIMxCLK = 32 MHz
0
ResTIM
Timer resolution
-
-
16
16-bit counter clock period when
1
65536
tTIMxCLK
tCOUNTER internal clock is selected (timer’s
prescaler disabled)
fTIMxCLK = 32 MHz 0.0312
2048
µs
-
-
-
65536 × 65536 tTIMxCLK
134.2
tMAX_COUNT Maximum possible count
fTIMxCLK = 32 MHz
s
1. TIMx is used as a general term to refer to the TIM2, TIM6, TIM21, and TIM22 timers.
6.3.20
Communications interfaces
I2C interface characteristics
2
2
I
I
The C interface meets the timings requirements of the C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm) : with a bit rate up to 100 kbit/s
Fast-mode (Fm) : with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.
2
2
I
I
The C timing requirements are guaranteed by design when the C peripheral is properly
configured (refer to the reference manual for details). The SDA and SCL I/O requirements
are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain.
When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is
disabled, but is still present. Only FTf I/O pins support Fm+ low level output current
maximum requirement (refer to Section 6.3.13: I/O port characteristics for the I2C I/Os
characteristics).
2
I
All C SDA and SCL I/Os embed an analog filter (see Table 73 for the analog filter
characteristics).
DS10685 Rev 6
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128
Electrical characteristics
STM32L073xx
2
I
The analog spike filter is compliant with C timings requirements only for the following
voltage ranges:
•
•
Fast mode Plus: 2.7 V ≤ V ≤ 3.6 V and voltage scaling Range 1
Fast mode:
DD
–
–
2 V ≤ V ≤ 3.6 V and voltage scaling Range 1 or Range 2.
DD
V
< 2 V, voltage scaling Range 1 or Range 2, C
< 200 pF.
load
DD
In other ranges, the analog filter should be disabled. The digital filter can be used instead.
Note:
In Standard mode, no spike filter is required.
(1)
Table 73. I2C analog filter characteristics
Symbol
Parameter
Conditions
Range 1
Min
Max
Unit
100(3)
Maximum pulse width of spikes that
are suppressed by the analog filter
tAF
Range 2
Range 3
50(2)
-
-
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI characteristics
Unless otherwise specified, the parameters given in the following tables are derived from
tests performed under ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 26.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
(1)
Table 74. SPI characteristics in voltage Range 1
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
16
-
-
Slave mode
receiver
16
Slave mode
Transmitter
1.71<VDD<3.6V
fSCK
1/tc(SCK)
12(2)
SPI clock frequency
MHz
-
-
Slave mode
Transmitter
2.7<VDD<3.6V
-
-
16(2)
70
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
%
118/157
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STM32L073xx
Electrical characteristics
(1)
Table 74. SPI characteristics in voltage Range 1
(continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Slave mode, SPI
presc = 2
tsu(NSS)
NSS setup time
4*Tpclk
-
-
-
Slave mode, SPI
presc = 2
th(NSS)
NSS hold time
2*Tpclk
-
tw(SCKH)
tw(SCKL)
Tpclk+
2
SCK high and low time
Master mode
Tpclk-2 Tpclk
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
0
3
-
-
-
-
-
-
-
-
Data input setup time
Data input hold time
7
-
th(SI)
3.5
15
10
-
ns
ta(SO
Data output access time
Data output disable time
36
30
tdis(SO)
Slave mode
1.65 V<VDD<3.6 V
-
-
18
18
41
25
tv(SO)
Data output valid time
Data output hold time
Slave mode
2.7 V<VDD<3.6 V
tv(MO)
th(SO)
th(MO)
Master mode
Slave mode
Master mode
-
10
0
4
-
7
-
-
-
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI)
which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be
achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
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128
Electrical characteristics
STM32L073xx
(1)
Table 75. SPI characteristics in voltage Range 2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
8
Slave mode Transmitter
1.65<VDD<3.6V
fSCK
1/tc(SCK)
8
SPI clock frequency
-
-
MHz
Slave mode Transmitter
2.7<VDD<3.6V
8(2)
70
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
%
tsu(NSS)
th(NSS)
tw(SCKH)
tw(SCKL)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
4*Tpclk
2*Tpclk
-
-
-
-
SCK high and low time
Data input setup time
Master mode
Tpclk-2 Tpclk Tpclk+2
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
0
3
-
-
-
-
-
-
-
-
11
4.5
18
12
-
Data input hold time
ns
th(SI)
-
ta(SO
Data output access time
Data output disable time
52
42
tdis(SO)
tv(SO)
Slave mode
-
20
56.5
Data output valid time
Data output hold time
tv(MO)
th(SO)
th(MO)
Master mode
Slave mode
Master mode
-
5
-
9
-
13
3
-
-
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
120/157
DS10685 Rev 6
STM32L073xx
Symbol
Electrical characteristics
(1)
Table 76. SPI characteristics in voltage Range 3
Parameter
Conditions
Min
Typ
Max
Unit
Master mode
Slave mode
2
fSCK
1/tc(SCK)
SPI clock frequency
-
-
MHz
2(2)
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
70
%
tsu(NSS)
th(NSS)
tw(SCKH)
tw(SCKL)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2 4*Tpclk
Slave mode, SPI presc = 2 2*Tpclk
-
-
-
-
SCK high and low time
Data input setup time
Master mode
Tpclk-2
Tpclk
Tpclk+2
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
1.5
6
-
-
-
-
-
-
-
-
13.5
16
-
Data input hold time
ns
th(SI)
-
ta(SO
Data output access time
Data output disable time
30
70
80
tdis(SO)
40
tv(SO)
Slave mode
-
30
70
Data output valid time
Data output hold time
tv(MO)
th(SO)
th(MO)
Master mode
Slave mode
Master mode
-
7
-
9
-
25
8
-
-
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
DS10685 Rev 6
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128
Electrical characteristics
STM32L073xx
Figure 34. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
(1)
Figure 35. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
122/157
DS10685 Rev 6
STM32L073xx
Electrical characteristics
(1)
Figure 36. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136d
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
DS10685 Rev 6
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128
Electrical characteristics
STM32L073xx
I2S characteristics
(1)
Table 77. I2S characteristics
Conditions
Symbol
Parameter
Min
Max
Unit
fMCK
I2S Main clock output
I2S clock frequency
-
256 x 8K
256xFs (2)
64xFs
MHz
Master data: 32 bits
Slave data: 32 bits
-
-
fCK
MHz
%
64xFs
I2S clock frequency duty
cycle
DCK
Slave receiver
30
70
tv(WS)
th(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
-
11
6
15
-
tsu(WS)
-
th(WS)
Slave mode
2
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Master receiver
Slave receiver
Master receiver
Slave receiver
0
-
Data input setup time
Data input hold time
Data output valid time
Data output hold time
6.5
18
15.5
-
-
ns
-
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
77
8
-
-
18
1.5
-
1. Guaranteed by characterization results.
2. 256xFs maximum value is equal to the maximum clock frequency.
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), f , f and D values. These values reflect only the digital peripheral
MCK CK
CK
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
124/157
DS10685 Rev 6
STM32L073xx
Electrical characteristics
2
(1)
Figure 37. I S slave timing diagram (Philips protocol)
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 38. I S master timing diagram (Philips protocol)
1. Guaranteed by characterization results.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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128
Electrical characteristics
STM32L073xx
USB characteristics
The USB interface is USB-IF certified (full speed).
Table 78. USB startup time
Parameter
USB transceiver startup time
Symbol
Max
Unit
(1)
tSTARTUP
1
µs
1. Guaranteed by design.
Table 79. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1) Unit
Input levels
VDD
USB operating voltage
Differential input sensitivity
-
3.0
0.2
0.8
1.3
3.6
-
V
V
(2)
VDI
I(USB_DP, USB_DM)
(2)
VCM
Differential common mode range Includes VDI range
2.5
2.0
(2)
VSE
Single ended receiver threshold
-
Output levels
(3)
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩ to 3.6 V(4)
-
0.3
3.6
V
(3)
(4)
RL of 15 kΩ to VSS
2.8
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
RL is the load connected on the USB drivers.
4.
Figure 39. USB timings: definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf
tr
ai14137b
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Electrical characteristics
Table 80. USB: full speed electrical characteristics
Driver characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall Time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
Output signal crossover voltage
90
1.3
110
2.0
1. Guaranteed by design.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
6.3.21
LCD controller
The devices embed a built-in step-up converter to provide a constant LCD reference voltage
independently from the V voltage. An external capacitor C must be connected to the
DD
ext
V
pin to decouple this converter.
LCD
Table 81. LCD controller characteristics
Symbol
Parameter
LCD external voltage
Min
Typ
Max
Unit
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
VLCD6
VLCD7
Cext
-
-
3.6
LCD internal reference voltage 0
LCD internal reference voltage 1
LCD internal reference voltage 2
LCD internal reference voltage 3
LCD internal reference voltage 4
LCD internal reference voltage 5
LCD internal reference voltage 6
LCD internal reference voltage 7
VLCD external capacitance
-
2.6
2.73
2.86
2.98
3.12
3.26
3.4
3.55
-
-
-
-
-
-
-
-
V
-
-
-
-
-
-
-
0.1
-
-
2
µF
µA
Supply current at VDD = 2.2 V
3.3
3.1
6.6
240
-
-
(1)
ILCD
Supply current at VDD = 3.0 V
-
-
(2)
RHtot
Low drive resistive network overall value
High drive resistive network total value
Segment/Common highest level voltage
5.28
192
-
7.92
288
VLCD
MΩ
kΩ
V
(2)
RL
V44
DS10685 Rev 6
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128
Electrical characteristics
Symbol
STM32L073xx
Table 81. LCD controller characteristics (continued)
Parameter
Min
Typ
Max
Unit
V34
V23
V12
V13
V14
V0
Segment/Common 3/4 level voltage
Segment/Common 2/3 level voltage
Segment/Common 1/2 level voltage
Segment/Common 1/3 level voltage
Segment/Common 1/4 level voltage
Segment/Common lowest level voltage
-
-
3/4 VLCD
2/3 VLCD
1/2 VLCD
1/3 VLCD
1/4 VLCD
-
-
-
-
-
-
-
-
V
-
-
0
Segment/Common level voltage error
ΔVxx(3)
-
-
50
mV
TA = -40 to 85 °C
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD
connected.
2. Guaranteed by design.
3. Guaranteed by characterization results.
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Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com. ECOPACK
is an ST trademark.
7.1
LQFP100 package information
Figure 40. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
75
C
D
D1
D3
L
L1
51
50
76
100
26
PIN 1
IDENTIFICATION
25
1
e
1L_ME_V5
1. Drawing is not to scale. Dimensions are in millimeters.
Table 82. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
-
-
-
1.600
0.150
-
-
-
0.0630
0.0059
A1
0.050
0.0020
DS10685 Rev 6
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152
Package information
STM32L073xx
Table 82. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data (continued)
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A2
b
1.350
0.170
0.090
15.800
13.800
-
1.400
0.220
-
1.450
0.270
0.200
16.200
14.200
-
0.0531
0.0067
0.0035
0.6220
0.5433
-
0.0551
0.0087
-
0.0571
0.0106
0.0079
0.6378
0.5591
-
c
D
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
15.800
13.800
-
16.200
14.200
-
0.6220
0.5433
-
0.6378
0.5591
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0.0°
-
7.0°
0.0°
7.0°
ccc
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 41. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
1. Dimensions are expressed in millimeters.
130/157
DS10685 Rev 6
STM32L073xx
Package information
Device marking for LQFP100
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 42. LQFP100 marking example (package top view)
Product identification(1)
STM32L073
Revision code
VZT6D
R
Date code
YWW
Pin 1
indentifier
MS34771V3
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS10685 Rev 6
131/157
152
Package information
STM32L073xx
7.2
UFBGA100 package information
Figure 43. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline
Seating plane
Z
ddd Z
A4
A2
A
A3
A1 A
E1
X
A1 ball
A1 ball
E
identifier index area
Z
e
Z
D1
D
e
Y
M
12
1
Øb (100 balls)
BOTTOM VIEW
TOP VIEW
eee M
Ø
Z Y X
M
Øfff
Z
A0C2_ME_V5
1. Drawing is not to scale.
Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
-
-
0.600
-
-
0.0236
-
-
0.110
-
-
0.0043
-
0.450
0.130
0.320
0.290
7.000
5.500
7.000
5.500
0.500
0.750
-
-
0.0177
0.0051
0.0126
0.0114
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
-
-
-
-
0.0094
-
-
-
-
0.240
0.340
0.0094
0.0134
D
6.850
7.150
0.2697
0.2815
D1
E
-
-
-
-
6.850
7.150
0.2697
0.2815
E1
e
-
-
-
-
-
-
-
-
-
-
-
Z
-
132/157
DS10685 Rev 6
STM32L073xx
Package information
Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.080
0.150
0.050
-
-
-
-
-
-
0.0031
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 44. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint
Dpad
Dsm
A0C2_FP_V1
Table 84. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.280 mm
Between 0.100 mm and 0.125 mm
DS10685 Rev 6
133/157
152
Package information
STM32L073xx
Device marking for UFBGA100
The following figure gives an example of topside marking versus ball A 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 45. UFBGA100 marking example (package top view)
Product identification(1)
STM32L
073VZI6
Date code
YWW
Ball 1
indentifier
Revision code
R
MSv37821V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
134/157
DS10685 Rev 6
STM32L073xx
Package information
7.3
LQFP64 package information
Figure 46. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
D1
D3
L
L1
33
48
32
49
64
b
17
16
1
PIN 1
e
IDENTIFICATION
5W_ME_V3
1. Drawing is not to scale.
Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
-
-
-
-
12.000
10.000
7.500
12.000
10.000
-
-
-
-
-
-
-
-
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
-
-
-
-
-
D1
D3
E
E1
DS10685 Rev 6
135/157
152
Package information
STM32L073xx
Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E3
e
-
7.500
0.500
3.5°
-
-
0.2953
0.0197
3.5°
-
-
-
7°
-
-
7°
K
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint
48
33
0.3
0.5
49
32
12.7
10.3
10.3
7.8
17
64
1.2
16
1
12.7
ai14909c
1. Dimensions are expressed in millimeters.
136/157
DS10685 Rev 6
STM32L073xx
Package information
Device marking for LQFP64
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 48. LQFP64 marking example (package top view)
Product identification(1)
Revision code
R
STM32L
073RZT6
Date code
YWW
Pin 1
indentifier
MSv36150V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS10685 Rev 6
137/157
152
Package information
STM32L073xx
7.4
TFBGA64 package information
Figure 49. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball
grid array package outline
A
E1
E
F
e
H
F
e
D
D1
Øb (64 balls)
Øeee M C B A
Øfff M C
B
A
1
8
A1 ball
A1 ball
TOP VIEW
SIDE VIEW
BOTTOM VIEW
index area
identifier
C Seating plane
ddd C
A4
A2
A1
A
R8_ME_V4
1. Drawing is not to scale.
Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
array package outline
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A4
b
-
-
1.200
-
-
0.0472
0.150
-
-
0.0059
-
-
-
0.200
-
-
-
0.0079
-
-
-
0.600
-
0.0236
0.250
0.300
5.000
3.500
5.000
3.500
0.500
0.750
0.350
0.0098
0.0118
0.1969
0.1378
0.1969
0.1378
0.0197
0.0295
0.0138
D
4.850
5.150
0.1909
0.2028
D1
E
-
-
-
-
4.850
5.150
0.1909
0.2028
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
F
138/157
DS10685 Rev 6
STM32L073xx
Package information
Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid
array package outline (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
ddd
eee
fff
-
-
-
-
-
-
0.080
0.150
0.050
-
-
-
-
-
-
0.0031
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 50. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
,grid array recommended footprint
Dpad
Dsm
R8_FP_V1
Table 87. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.280 mm
Between 0.100 mm and 1.125 mm
0.100 mm
DS10685 Rev 6
139/157
152
Package information
STM32L073xx
Device marking for TFBGA64
The following figure gives an example of topside marking versus ball A 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 51. TFBGA64 marking example (package top view)
Product identification(1)
L073RBH6
Date code = Year + week
Y WW
Revision
code
Ball A1
R
MSv37820V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
140/157
DS10685 Rev 6
STM32L073xx
Package information
7.5
WLCSP49 package information
Figure 52. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
package outline
bbb
e1
Z
F
A1 ball location
A1
G
e
Detail A
e2
E
e
A
D
A2
Bottom view
Bump side
Side view
A2
A3
b
Bump
Front view
A1
eee
Z
Z
b49x
ccc
ddd
Z
Z
X
Y
E
Seating plane
Note 1
Detail A
(rotated 90 )
Note 2
A1
Orientation
reference
aaa
(4x)
D
Top view
Wafer back side
A038_ME_V1
1. Drawing is not to scale.
DS10685 Rev 6
141/157
152
Package information
STM32L073xx
Table 88. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
0.555
0.175
0.380
0.025
0.250
3.294
3.258
0.400
2.400
2.400
0.447
0.429
-
Max
Min
Typ
0.0219
0.0069
0.0150
0.0010
0.0098
0.1297
0.1283
0.0157
0.0945
0.0945
0.0176
0.0169
-
Max
A
A1
A2
A3(2)
b(3)
D
0.525
0.585
0.0207
0.0230
-
-
-
-
-
-
-
-
-
-
-
-
0.220
0.280
3.329
3.293
-
0.0087
0.0110
0.1311
0.1296
-
3.259
0.1283
E
3.223
0.1269
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
-
-
e2
-
-
F
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.100
0.100
0.100
0.050
0.050
0.0039
0.0039
0.0039
0.0020
0.0020
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 53. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale
recommended footprint
Dpad
Dsm
MS18965V2
142/157
DS10685 Rev 6
STM32L073xx
Package information
Table 89. WLCSP49 recommended PCB design rules (0.4 mm pitch)
Dimension
Recommended values
Pitch
Dpad
0.4
260 µm max. (circular)
220 µm recommended
Dsm
300 µm min. (for 260 µm diameter pad)
Non-solder mask defined via underbump allowed.
PCB pad design
Device marking for WLCSP49
The following figure gives an example of topside marking versus ball A 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 54. WLCSP49 marking example (package top view
Ball 1
indentifier
Product identification(1)
L073CZ6
Revision code
Date code
Y WW R
MSv66803V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS10685 Rev 6
143/157
152
Package information
STM32L073xx
7.6
LQFP48 package information
Figure 55. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
36
25
37
24
b
48
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
144/157
DS10685 Rev 6
STM32L073xx
Package information
Table 90. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 56. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
DS10685 Rev 6
145/157
152
Package information
STM32L073xx
Device marking for LQFP48
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 57. LQFP48 marking example (package top view)
Product identification(1)
STM32L
073CZT6
Date code
YWW
Revision code
Pin 1
indentifier
R
MSv37819V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
146/157
DS10685 Rev 6
STM32L073xx
Package information
7.7
UFQFPN48 package information
Figure 58. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
Pin 1 identifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500x45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DS10685 Rev 6
147/157
152
Package information
STM32L073xx
Table 91. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 59. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
148/157
DS10685 Rev 6
STM32L073xx
Package information
Device marking for UFQFPN48
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 60. UFQFPN48 marking example (package top view)
Product identification(1)
STM32L073
CZU6D
Date code
YWW
Revision code
Pin 1
indentifier
R
MSv62438V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS10685 Rev 6
149/157
152
Package information
STM32L073xx
7.8
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 92. Thermal characteristics
Parameter
Symbol
Value
Unit
Thermal resistance junction-ambient
54
LQFP48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
28
46
64
48
41
57
UFQFPN48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
TFBGA64 - 5 x 5 mm / 0.5 mm pitch
ΘJA
°C/W
Thermal resistance junction-ambient
WLCSP49 - 0.4 mm pitch
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFBGA100 - 7 x 7 mm / 0.5 mm pitch
150/157
DS10685 Rev 6
STM32L073xx
Package information
Figure 61. Thermal resistance
UFQFPN48
LQFP48
PD (mW)
WLCSP49
Temperature (°C)
MSv35427V6
7.8.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DS10685 Rev 6
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152
Ordering information
STM32L073xx
8
Ordering information
Example:
STM32 L
073
R
8
T
6
D TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
L = Low power
Device subfamily
073 = USB + LCD
Pin count
C = 48/49 pins
R = 64 pins
V = 100 pins
Flash memory size
8 = 64 Kbytes
B = 128 Kbytes
Z = 192 Kbytes
Package
T = LQFP
H = TFBGA
I = UFBGA
U = UFQFPN
Y = Standard WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
3 = Industrial temperature range, –40 to 125 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
152/157
DS10685 Rev 6
STM32L073xx
Revision history
9
Revision history
Table 93. Document revision history
Changes
Date
Revision
03-Aug-2015
1
Initial release
Changed confidentiality level to public.
Updated datasheet status to “production data”.
Modified ultra-low-power platform features on cover page.
Changed number of GPIOs for LQFP48 for 37 in Table 2: Ultra-low-
power STM32L073xxx device features and peripheral counts.
Changed LCD_VLCD1 into LCD_VLCD2 in Section 3.13.2: VLCD
voltage monitoring.
In Section 6: Electrical characteristics, updated notes related to
values guaranteed by characterization.
26-Oct-2015
2
Updated |ΔVSS| definition to include VREF- in Table 23: Voltage
characteristics.
Added ΣVDD_USB and updated ΣIIO(PIN) in Figure 24: Current
characteristics.
Updated Table 56: EMI characteristics.
Updated fTRIG and VAIN maximum value, added VREF+ and VREF- in
Table 64: ADC characteristics.
Updated Section 7.2: UFBGA100 package information. Updated
Figure 60: UFQFPN48 marking example (package top view).
DS10685 Rev 6
153/157
156
Revision history
STM32L073xx
Table 93. Document revision history (continued)
Date
Revision
Changes
Updated number of SPIs on cover page and in Table 2: Ultra-low-
power STM32L073xxx device features and peripheral counts.
Changed minimum comparator supply voltage to 1.65 V on cover
page. Added minimum DAC supply voltage on cover page.
Added number of fast and standard channels in Section 3.12:
Analog-to-digital converter (ADC).
Updated Section 3.18.2: Universal synchronous/asynchronous
receiver transmitter (USART) and Section 3.18.4: Serial peripheral
interface (SPI)/Inter-integrated sound (I2S) to mention the fact that
USARTs with synchronous mode feature can be used as SPI master
interfaces.
Added baudrate allowing to wake up the MCU from Stop mode in
Section 3.18.2: Universal synchronous/asynchronous receiver
transmitter (USART) and Section 3.18.3: Low-power universal
asynchronous receiver transmitter (LPUART).
22-Mar-2016
3
Section 6.3.15: 12-bit ADC characteristics:
– Table 64: ADC characteristics:
Distinction made between VDDA for fast and standard channels;
added note 1.
Added note 4. related to RADC
.
Updated fTRIG..
Updated tS and tCONV
.
– Updated equation 1 description.
– Updated Table 65: RAIN max for fADC = 16 MHz for fADC = 16 MHz
and distinction made between fast and standard channels.
Updated RO and added Note 2. in Table 67: DAC characteristics.
Added Table 71: USART/LPUART characteristics.
154/157
DS10685 Rev 6
STM32L073xx
Revision history
Table 93. Document revision history (continued)
Date
Revision
Changes
Memories and I/Os moved after Core in Features.
Removed column "I/O operation" from Table 3: Functionalities
depending on the operating power supply range and added note
related to GPIO speed.
Updated VDD_USB in Section 3.4.1: Power supply schemes.
In Section 4: Pin descriptions, renamed USB_OE into USB_NOE.
In Section 5: Memory mapping, replaced memory mapping
schematic by reference to the reference manual.
Added mission profile compliance with JEDEC JESD47 in
Section 6.2: Absolute maximum ratings.
Updated minimum and maximum values of I/O weak pull-up
equivalent resistor (RPU) and weak pull-down equivalent resistor
(RPD) in Table 60: I/O static characteristics.
Updated minimum and maximum values of NRST weak pull-up
equivalent resistor (RPU) in Table 63: NRST pin characteristics.
Added note 2. related to the position of the external capacitor below
Figure 28: Recommended NRST pin protection.
12-Sep-2017
4
Updated RAIN in Table 64: ADC characteristics.
Updated Figure 33: 12-bit buffered/non-buffered DAC and added
note below figure.
Updated tAF maximum value for range 1 in Table 73: I2C analog filter
characteristics.
Removed Table 90: USART/LPUART characteristics.
NSS timing waveforms updated in Figure 34: SPI timing diagram -
slave mode and CPHA = 0 and Figure 35: SPI timing diagram - slave
mode and CPHA = 1(1)
.
Updated Figure 49: TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin
profile fine pitch ball grid array package outline.
Added reference to optional marking or inset/upset marks in all
package device marking sections. Updated note below marking
schematics.
DS10685 Rev 6
155/157
156
Revision history
STM32L073xx
Table 93. Document revision history (continued)
Date
Revision
Changes
Added UFQFPN48 package.
Updated Arm logo and added Arm word mark notice in Section 1:
Introduction.
Removed Cortex logo.
Updated Table 5: Functionalities depending on the working mode
(from Run/active down to standby) to change I2C functionality to
disabled in Low-power Run and Low-power Sleep modes.
Updated VDD_USB description in Section 3.4.1: Power supply
schemes.
Replaced LCD_VLCD2 by LCD_VLCD1 in Section 3.13.2: VLCD
voltage monitoring.
Changed USARTx_RTS, USARTx_RTS_DE into
USARTx_RTS/USARTx_DE, and LPUART1_RTS,
LPUART1_RTS_DE into LPUART1_RTS/LPUART1_DE in
Section 4: Pin descriptions and in all alternate function tables. In
Table 16: STM32L073xx pin definition changed PB2 and PB12/PE11
additional functions to LCD_VLCD2 and LCD_VLCD1, respectively.
08-Oct-2019
5
Updated VDD_USB and note 2. in Table 26: General operating
conditions.
Updated tAF maximum value for range 1 in Table 73: I2C analog filter
characteristics.
Updated paragraph introducing all package marking schematics to
add the new sentence “The printed markings may differ depending
on the supply chain.”
Updated Figure 49: TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin
profile fine pitch ball grid array package outline, Figure 50: TFBGA64
– 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball ,grid
array recommended footprint and Figure 87: TFBGA64
recommended PCB design rules (0.5 mm pitch BGA).
Added WLCSP49 package.
Added tWUUSART and tWULPUART in Table 42: Low-power mode
wakeup timings.
19-Aug-2020
6
Added reference to AN4899 in Section 6.3.13: I/O port
characteristics.
Removed R10K and R400K from Table 70: Comparator 1
characteristics.
156/157
DS10685 Rev 6
STM32L073xx
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