STM32L151UC [STMICROELECTRONICS]
Reset and supply management;
| 型号： | STM32L151UC |
| 厂家： | 
ST |
| 描述： | Reset and supply management |
| 文件： | 总136页 (文件大小：2032K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32L15xCC STM32L15xRC
STM32L15xUC STM32L15xVC
Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3,
256KB Flash, 32KB SRAM, 8KB EEPROM, LCD, USB, ADC, DAC
Datasheet - production data
Features
• Ultra-low-power platform
WLCSP63
UFQFPN48
UFBGA100
(7 x 7 mm)
– 1.65 V to 3.6 V power supply
– -40 °C to 105 °C temperature range
– 0.29µA Standby mode (3 wakeup pins)
– 1.15 µA Standby mode + RTC
– 0.44 µA Stop mode (16 wakeup lines)
– 1.4 µA Stop mode + RTC
(0.4 mm pitch) (7x7 mm)
LQFP100 (14 × 14 mm)
LQFP64 (10 × 10 mm)
LQFP48 (7 x 7 mm)
• Memories
– 256 KB Flash memory with ECC
– 32 KB RAM
– 8 KB of true EEPROM with ECC
– 128-byte backup register
– 8.6 µA Low-power run mode
– 185 µA/MHz Run mode
• LCD Driver (except STM32L151xC devices) up
to 8x40 segments, contrast adjustment,
blinking mode, step-up converter
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time
• Rich analog peripherals (down to 1.8 V)
– 2x operational amplifiers
®
®
• Core: ARM Cortex -M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit
– 12-bit ADC 1Msps up to 25 channels
– 12-bit DAC 2 channels with output buffers
– 2x ultra-low-power-comparators
(window mode and wake up capability)
• Reset and supply management
• DMA controller 12x channels
– Low-power, ultrasafe BOR (brownout reset)
with 5 selectable thresholds
• 9x peripheral communication interfaces
– 1x USB 2.0 (internal 48 MHz PLL)
– 3x USARTs
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
– Up to 8x SPIs (2x I2S, 3x 16 Mbit/s)
• Clock sources
– 2x I2Cs (SMBus/PMBus)
– 1 to 24 MHz crystal oscillator
• 11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timers,
2x watchdog timers (independent and window)
– 32 kHz oscillator for RTC with calibration
– High Speed Internal 16 MHz
factory-trimmed RC (+/- 1%)
• Up to 23 capacitive sensing channels
• CRC calculation unit, 96-bit unique ID
– Internal Low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz PLL for CPU clock and USB
(48 MHz)
Table 1. Device summary
Reference
Part number
STM32L151CC
STM32L151CCT6, STM32L151CCU6
STM32L151RCT6
STM32L151UCY6
• Pre-programmed bootloader
(1)
STM32L151RC
STM32L151UC
– USB and USART supported
(1)
STM32L151VC
STM32L151VCT6, STM32L151VCH6
• Development support
STM32L152CC
STM32L152RC
STM32L152UC
STM32L152CCT6, STM32L152CCU6
STM32L152RCT6
STM32L152UCY6
(1)
– Serial wire debug supported
– JTAG and trace supported
(1)
STM32L152VC
STM32L152VCT6, STM32L152VCH6
• Up to 83 fast I/Os (70 I/Os 5V tolerant), all
1. For sales types ending with “A” and STM32L15xxC products
in WLCSP64 package, please refer to STM32L15xxC/C-A
datasheet.
mappable on 16 external interrupt vectors
March 2016
DocID022799 Rev 12
1/136
This is information on a product in full production.
www.st.com
Contents
STM32L151xC STM32L152xC
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1
2.2.2
2.2.3
2.2.4
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ARM® Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1
3.3.2
3.3.3
3.3.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
3.5
3.6
3.7
3.8
3.9
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REFINT
3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.14 System configuration controller and routing interface . . . . . . . . . . . . . . . 27
3.15 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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3.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 30
3.17.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30
3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4
5
6
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.1
6.3.2
6.3.3
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Embedded reset and power control block characteristics . . . . . . . . . . . 57
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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STM32L151xC STM32L152xC
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.21 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.22 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.1
7.2
7.3
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
7.4
7.5
UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information . . . . . . . . . . .119
UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.6
7.7
WLCSP63, 0.400 mm pitch wafer level chip size package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.7.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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List of tables
List of tables
Table 1.
Table 2.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ultra-low-power STM32L151xC and STM32L152xC device features
and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Functionalities depending on the working mode (from Run/active down to
Table 3.
Table 4.
Table 5.
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6.
V
rail decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LCD
Table 7.
Table 8.
Table 9.
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STM32L151xC and STM32L152xC pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 57
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Current consumption in Run mode, code with data processing running from Flash. . . . . . 61
Current consumption in Run mode, code with data processing running from RAM . . . . . . 62
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 68
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 81
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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6
List of tables
STM32L151xC STM32L152xC
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2
SCL frequency (f
= 32 MHz, V = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 91
PCLK1
DD
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum source impedance R
max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
AIN
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 110
LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 113
LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 117
UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm,
0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . 122
UFBGA100, 7 x 7 mm, 0.50 mm pitch, recommended PCB design rules . . . . . . . . . . . . 123
WLCSP63, 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . . 126
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
STM32L151xC and STM32L152xC ordering information scheme . . . . . . . . . . . . . . . . . . 130
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Ultra-low-power STM32L151xC and STM32L152xC block diagram . . . . . . . . . . . . . . . . . 13
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32L15xVC UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32L15xVC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32L15xRC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L15xUC WLCSP63 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L15xCC UFQFPN48 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM32L15xCC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 13. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 19. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 20. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2
Figure 21. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 22. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
(1)
Figure 23. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
(1)
Figure 24. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 25. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2
(1)
Figure 26. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2
(1)
Figure 27. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 28. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 30. Maximum dynamic current consumption on V
supply pin during ADC
REF+
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 31. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 32. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 110
Figure 33. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 34. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . 112
Figure 35. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 113
Figure 36. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 37. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . 115
Figure 38. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 116
Figure 39. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 40. LQFP48 package top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 41. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 42. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 43. UFQFPN48 package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 44. UFBGA100, 7 x 7 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 45. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package recommended footprint. . . . . . . . . . . . . . 123
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8
List of figures
STM32L151xC STM32L152xC
Figure 46. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . 124
Figure 47. WLCSP63, 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . . 125
Figure 48. WLCSP63 device marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 49. Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 50. Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
®
®
the STM32L151xC and STM32L152xC ultra-low-power ARM Cortex -M3 based
microcontroller product line with a Flash memory of 256 Kbytes.
The ultra-low-power STM32L151xC and STM32L152xC family includes devices in 6
different package types: from 48 pins to 100 pins. Depending on the device chosen,
different sets of peripherals are included, the description below gives an overview of the
complete range of peripherals proposed in this family.
These features make the ultra-low-power STM32L151xC and STM32L152xC
microcontroller family suitable for a wide range of applications:
•
•
•
•
•
Medical and handheld equipment
Application control and user interface
PC peripherals, gaming, GPS and sport equipment
Alarm systems, wired and wireless sensors, video intercom
Utility metering
This STM32L151xC and STM32L152xC datasheet should be read in conjunction with the
STM32L1xxxx reference manual (RM0038). The application note “Getting started with
STM32L1xxxx hardware development” (AN3216) gives a hardware implementation
overview. Both documents are available from the STMicroelectronics website www.st.com.
®
®
®
®
For information on the ARM Cortex -M3 core please refer to the ARM Cortex -M3
technical reference manual, available from the www.arm.com website. Figure 1 shows the
general block diagram of the device family.
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51
Description
STM32L151xC STM32L152xC
2
Description
The ultra-low-power STM32L151xC and STM32L152xC devices incorporate the
®
connectivity power of the universal serial bus (USB) with the high-performance ARM
®
Cortex -M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory
protection unit (MPU), high-speed embedded memories (Flash memory up to 256 Kbytes
and RAM up to 32 Kbytes) and an extensive range of enhanced I/Os and peripherals
connected to two APB buses.
The STM32L151xC and STM32L152xC devices offer two operational amplifiers, one 12-bit
ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six
general-purpose 16-bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L151xC and STM32L152xC devices contain standard and advanced
communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs and an USB.
The STM32L151xC and STM32L152xC devices offer up to 23 capacitive sensing channels
to simply add a touch sensing functionality to any application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller (except STM32L151xC devices) has a built-in LCD
voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast
independent of the supply voltage.
The ultra-low-power STM32L151xC and STM32L152xC devices operate from a 1.8 to 3.6 V
power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power
supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C
temperature ranges. A comprehensive set of power-saving modes allows the design of low-
power applications.
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Description
2.1
Device overview
Table 2. Ultra-low-power STM32L151xC and STM32L152xC device features
and peripheral counts
STM32L15xUC
STM32L15xRC
Peripheral
Flash (Kbytes)
STM32L15xCC
STM32L15xVC
256
8
Data EEPROM (Kbytes)
RAM (Kbytes)
32
1
32 bit
General-
purpose
Timers
6
Basic
SPI
2
8(3)(1)
I2S
2
2
Communica
tion interfaces
I2C
USART
USB
3
1
GPIOs
37
51
2
83
Operation amplifiers
12-bit synchronized ADC
Number of channels
1
14
1
21
1
25
12-bit DAC
Number of channels
2
2
LCD (2)
1
1
1
COM x SEG
4x18
4x32 or 8x28
4x44 or 8x40
Comparators
2
Capacitive sensing channels
Max. CPU frequency
16
23
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Operating voltage
Operating temperatures
Packages
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: –40 to + 110 °C
LQFP48,
LQFP64,
LQFP100,
UFQFPN48
WLCSP63
UFBGA100
1. 5 SPIs are USART configured in synchronous mode emulating SPI master.
2. STM32L152xx devices only.
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51
Description
STM32L151xC STM32L152xC
2.2
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of cores and features. From proprietary 8-
bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power
series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and
healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others will clearly allow to build very cost-optimized applications by reducing BOM.
Note:
STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, the old applications can be upgraded to respond to the latest market features and
efficiency demand.
2.2.1
Performance
All the families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2
2.2.3
Shared peripherals
STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
•
•
Analog peripherals: ADC, DAC and comparators
Digital peripherals: RTC and some communication interfaces
Common system strategy.
To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:
•
•
Same power supply range from 1.65 V to 3.6 V
Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
•
•
•
Fast startup strategy from low-power modes
Flexible system clock
Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
2.2.4
Features
ST ultra-low-power continuum also lies in feature compatibility:
•
•
More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
Memory density ranging from 2 to 512 Kbytes
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Functional overview
3
Functional overview
Figure 1. Ultra-low-power STM32L151xC and STM32L152xC block diagram
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DocID022799 Rev 12
13/136
51
Functional overview
STM32L151xC STM32L152xC
3.1
Low-power modes
The ultra-low-power STM32L151xC and STM32L152xC devices support dynamic voltage
scaling to optimize its power consumption in run mode. The voltage from the internal low-
drop regulator that supplies the logic can be adjusted according to the system’s maximum
operating frequency and the external voltage supply.
There are three power consumption ranges:
•
•
•
Range 1 (V range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz
DD
Range 2 (full V range), with a maximum CPU frequency of 16 MHz
DD
Range 3 (full V range), with a maximum CPU frequency limited to 4 MHz (generated
DD
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In low-power
run mode, the clock frequency and the number of enabled peripherals are both limited.
•
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the V
domain are stopped, the
CORE
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.
14/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Functional overview
•
Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
•
Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire V
domain is
CORE
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•
Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire V
domain is powered off. The PLL, MSI
CORE
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power supply
DAC and ADC
operation
Dynamic voltage
scaling range
USB
I/O operation
range
Range 2 or
Range 3
Degraded speed
performance
VDD= VDDA = 1.65 to 1.71 V
VDD=VDDA= 1.71 to 1.8 V(1)
VDD=VDDA= 1.8 to 2.0 V(1)
Not functional
Not functional
Not functional
Not functional
Not functional
Range 1, Range 2
or Range 3
Degraded speed
performance
Range 1, Range 2
Conversion time up
to 500 Ksps
Degraded speed
performance
or
Range 3
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51
Functional overview
STM32L151xC STM32L152xC
Table 3. Functionalities depending on the operating power supply range (continued)
Functionalities depending on the operating power supply range
Operating power supply
range
DAC and ADC
operation
Dynamic voltage
scaling range
USB
I/O operation
Conversion time up
to 500 Ksps
Range 1, Range 2
or Range 3
VDD=VDDA = 2.0 to 2.4 V
Functional(2)
Functional(2)
Full speed operation
Full speed operation
Conversion time up
to 1 Msps
Range 1, Range 2
or Range 3
VDD=VDDA = 2.4 to 3.6 V
1. CPU frequency changes from initial to final must respect “FCPU initial < 4*FCPU final” to limit VCORE drop due to current
consumption peak when frequency increases. It must also respect 5 µs delay between two changes. For example to switch
from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz.
2. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V.
Table 4. CPU frequency range depending on dynamic voltage scaling
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
Range 3
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws)
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DocID022799 Rev 12
STM32L151xC STM32L152xC
Functional overview
Table 5. Functionalities depending on the working mode (from Run/active down to
standby)
Stop
Standby
Low-
power
Run
Low-
power
Sleep
Ips
Run/Active
Sleep
Wakeup
capability
Wakeup
capability
CPU
Flash
RAM
Y
Y
Y
Y
Y
--
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
Y
Y
Y
--
--
Y
Y
Y
--
--
--
--
--
--
--
--
Y
--
--
--
--
--
--
Backup Registers
EEPROM
Brown-out rest
(BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
--
Y
--
--
--
DMA
Programmable
Voltage Detector
(PVD)
Y
Y
Y
Y
Y
Y
Y
--
Power On Reset
(POR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
--
Y
Y
Y
Y
Y
Y
--
--
Y
Y
Y
Y
Y
Y
--
--
Y
Y
--
--
Y
--
--
--
--
--
--
--
Y
Y
--
--
Y
Y
--
--
--
--
--
--
--
--
--
--
Power Down Rest
(PDR)
High Speed
Internal (HSI)
High Speed
External (HSE)
Low Speed Internal
(LSI)
Low Speed
External (LSE)
Multi-Speed
Internal (MSI)
Inter-Connect
Controller
RTC
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
RTC Tamper
Auto WakeUp
(AWU)
Y
Y
Y
Y
Y
Y
--
Y
Y
LCD
USB
USART
SPI
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
--
--
--
--
--
--
--
--
--
--
--
--
Y
(1)
--
(1)
I2C
DocID022799 Rev 12
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51
Functional overview
STM32L151xC STM32L152xC
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Stop
Standby
Wakeup
Low-
power
Run
Low-
power
Sleep
Ips
Run/Active
Sleep
Wakeup
capability
capability
ADC
DAC
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
Y
Y
Y
--
--
--
--
Y
--
--
--
--
--
--
--
--
--
--
Tempsensor
OP amp
Comparators
16-bit and 32-bit
Timers
Y
Y
Y
Y
--
--
--
--
IWDG
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
Y
Y
--
--
Y
--
--
--
Y
Y
--
--
--
--
Y
--
WWDG
Touch sensing
Systic Timer
GPIOs
--
--
Y
3 pins
Wakeup time to
Run mode
0 µs
0.4 µs
3 µs
46 µs
< 8 µs
58 µs
0.43 µA
(no RTC)
VDD=1.8V
0.29 µA
(no RTC)
VDD=1.8V
1.15 µA
0.9 µA
(with RTC)
(with RTC)
VDD=1.8V
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to 185
µA/MHz (from
Flash)
Down to 34.5
µA/MHz (from
Flash)
VDD=1.8V
Down to Down to
8.6 µA 4.4 µA
0.44 µA
(no RTC)
0.29 µA
(no RTC)
VDD=3.0V
VDD=3.0V
1.4 µA
(with RTC)
DD=3.0V
1.15 µA
(with RTC)
VDD=3.0V
V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
3.2
ARM® Cortex®-M3 core with MPU
®
®
The ARM Cortex -M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
®
®
The ARM Cortex -M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
18/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Functional overview
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L151xC and STM32L152xC devices are
compatible with all ARM tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L151xC and STM32L152xC devices embed a nested vectored
interrupt controller able to handle up to 53 maskable interrupt channels (not including the 16
®
®
interrupt lines of ARM Cortex -M3) and 16 priority levels.
•
•
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3
Reset and supply management
3.3.1
Power supply schemes
•
V
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
DD
externally through V pins.
DD
•
V
, V
= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
SSA DDA
and PLL (minimum voltage to be applied to V
is 1.8 V when the ADC is used). V
DDA
DDA
and V
must be connected to V and V , respectively.
SSA
DD SS
3.3.2
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
•
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
The other version without BOR operates between 1.65 V and 3.6 V.
After the V threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
DD
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the V min value becomes
DD
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
DocID022799 Rev 12
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51
Functional overview
STM32L151xC STM32L152xC
power ramp-up should guarantee that 1.65 V is reached on V at least 1 ms after it exits
DD
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
) in Stop mode. The device remains in reset mode when
REFINT
V
is below a specified threshold, V
or V
, without the need for any external
DD
POR/PDR
BOR
reset circuit.
Note:
3.3.3
3.3.4
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
/V
power supply and compares it to the V
threshold. This PVD offers 7 different
DD DDA
PVD
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V /V drops below the V threshold and/or when
DD DDA
PVD
V
/V
is higher than the V
threshold. The interrupt service routine can then generate
DD DDA
PVD
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR) and power down.
•
•
•
MR is used in Run mode (nominal regulation)
LPR is used in the Low-power run, Low-power sleep and Stop modes
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
Boot modes
At startup, boot pins are used to select one of three boot options:
•
•
•
Boot from Flash memory
Boot from System memory
Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See Application note “STM32 microcontroller system
memory boot mode” (AN2606) for details.
20/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Functional overview
3.4
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
•
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
–
–
1-24 MHz high-speed external crystal (HSE), that can supply a PLL
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
•
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
–
–
32.768 kHz low-speed external crystal (LSE)
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
•
•
•
RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
•
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
DocID022799 Rev 12
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51
Functional overview
STM32L151xC STM32L152xC
Figure 2. Clock tree
3TANDBY SUPPLIED VOLTAGE DOMAIN
ENABLE
7ATCHDOG
7ATCHDOG
,3
,3) 2#
,3) TEMPO
24# ENABLE
24#
,3% /3#
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2ADIO 3LEEP 4IMER
2ADIO 3LEEP 4IMER ENABLE
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,3
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CK?LSE
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-#/
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ꢈ ꢇꢄꢅꢄꢁꢄꢀꢆ
#+?072
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DEEPSLEEP
LEVEL SHIFTERS
6
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NOT ꢋSLEEP OR
DEEPSLEEPꢍ
6ꢃꢃ
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CK?HSI
CK?HSE
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/3#
#+?4)-393
ꢈ ꢁ
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ꢈ ꢀꢄꢇꢄꢉꢉꢂꢀꢇ
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6
$$#/2%
CK?PLL
6ꢃꢃ
0,,
!0"ꢀ
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CK?PLLIN
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PRESCALER PRESCALER
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STM32L151xC STM32L152xC
Functional overview
3.5
Low-power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 µs to 36 hours.
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
The RTC can also be automatically corrected with a 50/60Hz stable powerline.
The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronization.
A time stamp can record an external event occurrence, and generates an interrupt.
There are thirty-two 32-bit backup registers provided to store 128 bytes of user application
data. They are cleared in case of tamper detection.
Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.
3.6
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.
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Functional overview
STM32L151xC STM32L152xC
3.7
Memories
The STM32L151xC and STM32L152xC devices have the following features:
•
32 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
–
–
256 Kbytes of embedded Flash program memory
8 Kbytes of data EEPROM
Options bytes
The options bytes are used to write-protect or read-out protect the memory (with 4
Kbytes granularity) and/or readout-protect the whole memory with the following
options:
–
–
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
The user area of the Flash memory can be protected against Dbus read access by
PCROP feature (see RM0038 for details).
3.8
DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
2
The DMA can be used with the main peripherals: SPI, I C, USART, general-purpose timers,
DAC and ADC.
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STM32L151xC STM32L152xC
Functional overview
3.9
LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
•
Internal step-up converter to guarantee functionality and contrast control irrespective of
. This converter can be deactivated, in which case the V pin is used to provide
V
DD
LCD
the voltage to the LCD
•
•
•
•
•
•
•
•
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
Supports static, 1/2, 1/3 and 1/4 bias
Phase inversion to reduce power consumption and EMI
Up to 8 pixels can be programmed to blink
Unneeded segments and common pins can be used as general I/O pins
LCD RAM can be updated at any time owing to a double-buffer
The LCD controller can operate in Stop mode
V
rail decoupling capability
LCD
Table 6. V
rail decoupling
LCD
Bias
1/3
Pin
1/2
1/4
VLCDRAIL1
VLCDRAIL2
VLCDRAIL3
1/2 VLCD
N/A
2/3 VLCD
1/3 VLCD
N/A
1/2 VLCD
1/4 VLCD
3/4 VLCD
PB2
PB12
PB0
PE11
PE12
N/A
3.10
ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L151xC and STM32L152xC
devices with up to 25 external channels, performing conversions in single-shot or scan
mode. In scan mode, automatic conversion is performed on a selected group of analog
inputs with up to 24 external channels in a group.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.
The ADC includes a specific low-power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
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Functional overview
STM32L151xC STM32L152xC
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
that varies linearly with
SENSE
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode. See Table 61:
Temperature sensor calibration values.
3.10.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC and Comparators. V
is internally connected to the ADC_IN17 input channel. It
REFINT
enables accurate monitoring of the V value (when no external voltage, VREF+, is
DD
available for ADC). The precise voltage of V
is individually measured for each part by
REFINT
ST during production test and stored in the system memory area. It is accessible in read-
only mode. See Table 16: Embedded internal reference voltage calibration values.
3.11
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
•
•
•
•
•
•
•
•
•
•
Two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channels, independent or simultaneous conversions
DMA capability for each channel (including the underrun interrupt)
External triggers for conversion
Input reference voltage V
REF+
Eight DAC trigger inputs are used in the STM32L151xC and STM32L152xC devices. The
DAC channels are triggered through the timer update outputs that are also connected to
different DMA channels.
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Functional overview
3.12
Operational amplifier
The STM32L151xC and STM32L152xC devices embed two operational amplifiers with
external or internal follower routing capability (or even amplifier and filter capability with
external components). When one operational amplifier is selected, one external ADC
channel is used to enable output measurement.
The operational amplifiers feature:
•
•
•
•
Low input bias current
Low offset voltage
Low-power mode
Rail-to-rail input
3.13
Ultra-low-power comparators and reference voltage
The STM32L151xC and STM32L152xC devices embed two comparators sharing the same
current bias and reference voltage. The reference voltage can be internal or external
(coming from an I/O).
•
•
One comparator with fixed threshold
One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
–
–
–
DAC output
External I/O
Internal reference voltage (V
) or a sub-multiple (1/4, 1/2, 3/4)
REFINT
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
3.14
3.15
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
V
.
REFINT
Touch sensing
The STM32L151xC and STM32L152xC devices provide a simple solution for adding
capacitive sensing functionality to any application. These devices offer up to 23 capacitive
sensing channels distributed over 10 analog I/O groups. Both software and timer capacitive
sensing acquisition modes are supported.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
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Functional overview
STM32L151xC STM32L152xC
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups
(see Section 3.14: System configuration controller and routing interface).
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
3.16
Timers and watchdogs
The ultra-low-power STM32L151xC and STM32L152xC devices include seven general-
purpose timers, two basic timers, and two watchdog timers.
Table 7 compares the features of the general-purpose and basic timers.
Table 7. Timer feature comparison
DMA
Counter
resolution
Capture/compare Complementary
Timer
Counter type
Prescaler factor
request
channels
outputs
generation
TIM2,
TIM3,
TIM4
Up, down,
up/down
Any integer between
1 and 65536
16-bit
Yes
4
No
Up, down,
up/down
Any integer between
1 and 65536
TIM5
TIM9
32-bit
16-bit
16-bit
16-bit
Yes
No
4
2
1
0
No
No
No
No
Up, down,
up/down
Any integer between
1 and 65536
TIM10,
TIM11
Any integer between
1 and 65536
Up
Up
No
TIM6,
TIM7
Any integer between
1 and 65536
Yes
3.16.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11)
There are seven synchronizable general-purpose timers embedded in the STM32L151xC
and STM32L152xC devices (see Table 7 for differences).
TIM2, TIM3, TIM4, TIM5
TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32-
bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four
independent channels each for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input captures/output compares/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,
TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or
event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs.
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Functional overview
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.16.2
3.16.3
Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.16.4
3.16.5
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.17
Communication interfaces
3.17.1
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
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Functional overview
STM32L151xC STM32L152xC
3.17.2
Universal synchronous/asynchronous receiver transmitter (USART)
The three USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They
support IrDA SIR ENDEC and have LIN Master/Slave capability. The three USARTs provide
hardware management of the CTS and RTS signals and are ISO 7816 compliant.
All USART interfaces can be served by the DMA controller.
3.17.3
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
2
3.17.4
Inter-integrated sound (I S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192
kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
The I2Ss can be served by the DMA controller.
3.17.5
Universal serial bus (USB)
The STM32L151xC and STM32L152xC devices embed a USB device peripheral
compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed
(12 Mbit/s) function interface. It has software-configurable endpoint setting and supports
suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the
clock source must use a HSE crystal oscillator).
3.18
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
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Functional overview
3.19
Development support
3.19.1
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
3.19.2
Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L151xC and STM32L152xC device through a small number of ETM pins to an
external hardware trace port analyzer (TPA) device. The TPA is connected to a host
computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and
data flow activity can be recorded and then formatted for display on the host computer
running debugger software. TPA hardware is commercially available from common
development tool vendors. It operates with third party debugger software tools.
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Pin descriptions
STM32L151xC STM32L152xC
4
Pin descriptions
Figure 3. STM32L15xVC UFBGA100 ballout
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STM32L151xC STM32L152xC
Pin descriptions
Figure 4. STM32L15xVC LQFP100 pinout
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DocID022799 Rev 12
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51
Pin descriptions
STM32L151xC STM32L152xC
Figure 5. STM32L15xRC LQFP64 pinout
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AIꢀꢂꢆꢌꢃC
1. This figure shows the package top view.
34/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Pin descriptions
Figure 6. STM32L15xUC WLCSP63 ballout
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1. This figure shows the package top view.
DocID022799 Rev 12
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51
Pin descriptions
STM32L151xC STM32L152xC
Figure 7. STM32L15xCC UFQFPN48 pinout
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AIꢀꢂꢆꢌꢂD
1. This figure shows the package top view.
36/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Pin descriptions
Figure 8. STM32L15xCC LQFP48 pinout
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06ꢀꢁꢂꢃꢋ9ꢂ
1. This figure shows the package top view.
DocID022799 Rev 12
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51
Pin descriptions
STM32L151xC STM32L152xC
Table 8. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
TC
B
Input / output pin
5 V tolerant I/O
Standard 3.3 V I/O
I/O structure
Notes
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 9. STM32L151xC and STM32L152xC pin definitions
Pin functions
Pins
Main
function(2)
(after
Pin name
Alternate functions
Additional functions
reset)
TIM3_ETR/LCD_SEG38
/TRACECLK
B2
A1
1
2
-
-
-
-
-
-
PE2
PE3
I/O FT
I/O FT
PE2
PE3
-
-
TIM3_CH1/LCD_SEG39
/TRACED0
B1
C2
3
4
-
-
-
-
-
-
PE4
PE5
I/O FT
I/O FT
PE4
PE5
TIM3_CH2/TRACED1
TIM9_CH1/TRACED2
TIM9_CH2/ TRACED3
-
-
PE6-
WKUP3
WKUP3/
RTC_TAMP3
D2
E2
5
6
-
-
-
I/O FT
PE6
(3)
1
C7
1
VLCD
S
-
VLCD
-
-
38/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Pin descriptions
Table 9. STM32L151xC and STM32L152xC pin definitions (continued)
Pin functions
Pins
Main
function(2)
(after
Pin name
Alternate functions
Additional functions
reset)
WKUP2/
RTC_TAMP1/
RTC_TS/RTC_OUT
PC13-
WKUP2
C1
7
2
D5
2
I/O FT
PC13
-
PC14-
D1
E1
8
9
3
4
D7
D6
3
4
I/O
PC14
PC15
-
-
OSC32_IN
TC
OSC32_IN(4)
PC15-
OSC32_OUT
I/O
OSC32_OUT
TC
F2 10
G2 11
-
-
-
-
-
-
VSS_5
VDD_5
S
S
-
-
VSS_5
VDD_5
-
-
-
-
PH0-
F1 12
5
F6
5
I/O
I/O
PH0
-
OSC_IN
TC
TC
OSC_IN(5)
PH1-
G1 13
H2 14
H1 15
6
7
8
F7
E7
E6
6
7
-
PH1
NRST
PC0
-
OSC_OUT
-
OSC_OUT(5)
NRST
PC0
I/O RST
I/O FT
-
ADC_IN10/
COMP1_INP
LCD_SEG18
ADC_IN11/
COMP1_INP
J2 16
9
E5
-
-
-
PC1
PC2
PC3
I/O FT
I/O FT
PC1
PC2
PC3
LCD_SEG19
LCD_SEG20
LCD_SEG21
ADC_IN12/
COMP1_INP
J3 17 10 G7
ADC_IN13/
COMP1_INP
18 11 G6
I/O
TC
K2
J1 19 12 F5
8
-
VSSA
VREF-
VREF+
VDDA
S
S
S
S
-
-
-
-
VSSA
VREF-
VREF+
VDDA
-
-
-
-
-
-
-
-
K1 20
L1 21
-
-
-
-
-
M1 22 13 H7
9
WKUP1/
RTC_TAMP2/
ADC_IN0/
TIM2_CH1_ETR/
TIM5_CH1/
USART2_CTS
L2 23 14 E4 10 PA0-WKUP1 I/O FT
PA0
COMP1_INP
DocID022799 Rev 12
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51
Pin descriptions
STM32L151xC STM32L152xC
Pin functions
Table 9. STM32L151xC and STM32L152xC pin definitions (continued)
Pins
Main
function(2)
(after
Pin name
Alternate functions
Additional functions
reset)
TIM2_CH2/TIM5_CH2/
USART2_RTS/
LCD_SEG0
ADC_IN1/
COMP1_INP/
OPAMP1_VINP
M2 24 15 G5 11
K3 25 16 H6 12
L3 26 17 J7 13
PA1
PA2
PA3
I/O FT
I/O FT
PA1
PA2
PA3
TIM2_CH3/TIM5_CH3/
TIM9_CH1/USART2_TX
/LCD_SEG1
ADC_IN2/
COMP1_INP/
OPAMP1_VINM
TIM2_CH4/TIM5_CH4/
TIM9_CH2/USART2_RX
/LCD_SEG2
ADC_IN3/
COMP1_INP/
OPAMP1_VOUT
I/O
TC
E3 27 18
H3 28 19
-
-
-
-
VSS_4
VDD_4
S
S
-
-
VSS_4
VDD_4
-
-
-
-
SPI1_NSS/SPI3_NSS/
I2S3_WS/
ADC_IN4/
DAC_OUT1/
COMP1_INP
M3 29 20 J6 14
K4 30 21 H4 15
L4 31 22 G4 16
M4 32 23 J5 17
PA4
PA5
PA6
PA7
I/O
I/O
PA4
PA5
PA6
PA7
TC
TC
USART2_CK
ADC_IN5/
DAC_OUT2/
COMP1_INP
TIM2_CH1_ETR/
SPI1_SCK
ADC_IN6/
COMP1_INP/
OPAMP2_VINP
TIM3_CH1/TIM10_CH1/
SPI1_MISO/LCD_SEG3
I/O FT
I/O FT
ADC_IN7/
COMP1_INP/
OPAMP2_VINM
TIM3_CH2/TIM11_CH1/
SPI1_MOSI/LCD_SEG4
ADC_IN14/
COMP1_INP
K5 33 24 F4
L5 34 25 J4
-
-
PC4
PC5
I/O FT
I/O FT
PC4
PC5
LCD_SEG22
LCD_SEG23
ADC_IN15/
COMP1_INP
ADC_IN8/
COMP1_INP/
OPAMP2_VOUT/
VLCDRAIL3/
VREF_OUT
M5 35 26 J3 18
PB0
I/O
PB0
TIM3_CH3/LCD_SEG5
TC
40/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Pin descriptions
Table 9. STM32L151xC and STM32L152xC pin definitions (continued)
Pin functions
Pins
Main
function(2)
(after
Pin name
Alternate functions
Additional functions
reset)
ADC_IN9/
COMP1_INP/
VREF_OUT
M6 36 27 H3 19
L6 37 28 G3 20
PB1
I/O FT
I/O FT
PB1
TIM3_CH4/LCD_SEG6
PB2
/BOOT1
VLCDRAIL1/
ADCIN0b
PB2
PE7
PE8
PE9
PE10
BOOT1
ADC_IN22/
COMP1_INP
M7 38
L7 39
M8 40
L8 41
-
-
-
-
-
-
-
-
-
-
-
-
I/O
PE7
PE8
-
-
TC
ADC_IN23/
COMP1_INP
I/O
TC
TIM2_CH1_ETR/
TIM5_ETR
ADC_IN24/
COMP1_INP
-
PE9
TC
ADC_IN25/
COMP1_INP
I/O
PE10
TIM2_CH2
TC
M9 42
L9 43
M10 44
M11 45
M12 46
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PE11
PE12
PE13
PE14
PE15
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
PE11
PE12
PE13
PE14
PE15
TIM2_CH3
TIM2_CH4/SPI1_NSS
SPI1_SCK
VLCDRAIL2
VLCDRAIL3
-
-
-
SPI1_MISO
SPI1_MOSI
TIM2_CH3/I2C2_SCL/
USART3_TX/
L10 47 29 J2 21
L11 48 30 H2 22
PB10
PB11
I/O FT
I/O FT
PB10
PB11
-
-
LCD_SEG10
TIM2_CH4/I2C2_SDA/
USART3_RX/
LCD_SEG11
-
-
-
H5
-
VSS
S
S
S
-
-
-
VSS
-
-
-
-
-
-
F12 49 31 J1 23
G12 50 32 H1 24
VSS_1
VDD_1
VSS_1
VDD_1
DocID022799 Rev 12
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51
Pin descriptions
STM32L151xC STM32L152xC
Pin functions
Table 9. STM32L151xC and STM32L152xC pin definitions (continued)
Pins
Main
function(2)
(after
Pin name
Alternate functions
Additional functions
reset)
TIM10_CH1
/I2C2_SMBA/
SPI2_NSS/I2S2_WS/
USART3_CK/
ADC_IN18/
COMP1_INP/
VLCDRAIL2
L12 51 33 G2 25
PB12
PB13
I/O FT
I/O FT
PB12
PB13
LCD_SEG12
TIM9_CH1/SPI2_SCK/
I2S2_CK/
ADC_IN19/
COMP1_INP
K12 52 34 G1 26
USART3_CTS/
LCD_SEG13
TIM9_CH2/SPI2_MISO/
USART3_RTS/
ADC_IN20/
COMP1_INP
K11 53 35 F3 27
K10 54 36 F2 28
PB14
PB15
I/O FT
I/O FT
PB14
PB15
LCD_SEG14
ADC_IN21/
COMP1_INP/
RTC_REFIN
TIM11_CH1/SPI2_MOSI
/I2S2_SD/LCD_SEG15
USART3_TX/
LCD_SEG28
K9 55
K8 56
J12 57
J11 58
-
-
-
-
-
-
-
-
-
-
-
-
PD8
PD9
I/O FT
I/O FT
I/O FT
I/O FT
PD8
PD9
-
-
-
-
USART3_RX/
LCD_SEG29
USART3_CK/
LCD_SEG30
PD10
PD11
PD10
PD11
USART3_CTS/
LCD_SEG31
TIM4_CH1/
USART3_RTS/
LCD_SEG32
J10 59
-
-
-
PD12
I/O FT
PD12
-
H12 60
H11 61
H10 62
-
-
-
-
-
-
-
-
-
PD13
PD14
PD15
I/O FT
I/O FT
I/O FT
PD13
PD14
PD15
TIM4_CH2/LCD_SEG33
TIM4_CH3/LCD_SEG34
TIM4_CH4/LCD_SEG35
-
-
-
TIM3_CH1/I2S2_MCK/
LCD_SEG24
E12 63 37 F1
-
PC6
I/O FT
PC6
-
42/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Pin descriptions
Table 9. STM32L151xC and STM32L152xC pin definitions (continued)
Pin functions
Pins
Main
function(2)
(after
Pin name
Alternate functions
Additional functions
reset)
TIM3_CH2/I2S3_MCK/
LCD_SEG25
E11 64 38 E1
-
PC7
I/O FT
PC7
-
E10 65 39 D1
D12 66 40 E2
-
-
PC8
PC9
I/O FT
I/O FT
PC8
PC9
TIM3_CH3/LCD_SEG26
TIM3_CH4/LCD_SEG27
-
-
USART1_CK/MCO/
LCD_COM0
D11 67 41 E3 29
D10 68 42 C1 30
C12 69 43 D2 31
B12 70 44 B1 32
A12 71 45 D3 33
A11 72 46 C2 34
PA8
PA9
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
PA8
PA9
-
USART1_TX/
LCD_COM1
-
USART1_RX/
LCD_COM2
PA10
PA11
PA12
PA13
PA10
PA11
PA12
-
USART1_CTS/
SPI1_MISO
USB_DM
USB_DP
-
USART1_RTS/
SPI1_MOSI
JTMS-
SWDIO
I/O FT
I/O FT
JTMS-SWDIO
C11 73
-
-
-
PH2
VSS_2
VDD_2
PH2
VSS_2
VDD_2
-
-
-
-
-
-
F11 74 47 A1 35
G11 75 48 B2 36
S
S
-
-
JTCK-
SWCLK
A10 76 49 C3 37
PA14
I/O FT
JTCK-SWCLK
-
TIM2_CH1_ETR/
SPI1_NSS/
SPI3_NSS/I2S3_WS/
LCD_SEG17/JTDI
A9 77 50 A2 38
PA15
I/O FT
JTDI
-
SPI3_SCK/I2S3_CK/
USART3_TX/
LCD_SEG28/
LCD_SEG40/
LCD_COM4
B11 78 51 B3
-
PC10
I/O FT
PC10
-
DocID022799 Rev 12
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51
Pin descriptions
STM32L151xC STM32L152xC
Pin functions
Table 9. STM32L151xC and STM32L152xC pin definitions (continued)
Pins
Main
function(2)
(after
Pin name
Alternate functions
Additional functions
reset)
SPI3_MISO/
USART3_RX/
LCD_SEG29/
LCD_SEG41/
LCD_COM5
C10 79 52 A3
-
-
PC11
PC12
I/O FT
PC11
PC12
-
-
SPI3_MOSI/I2S3_SD/
USART3_CK/
LCD_SEG30/
B10 80 53 B4
I/O FT
LCD_SEG42/
LCD_COM6
TIM9_CH1/SPI2_NSS/
I2S2_WS
C9 81
B9 82
-
-
-
-
-
-
PD0
PD1
I/O FT
I/O FT
PD0
PD1
-
-
SPI2_SCK/I2S2_CK
TIM3_ETR/LCD_SEG31
/LCD_SEG43/
C8 83 54 A4
-
PD2
I/O FT
PD2
-
LCD_COM7
SPI2_MISO/
USART2_CTS
B8 84
B7 85
-
-
-
-
-
-
PD3
PD4
I/O FT
I/O FT
PD3
PD4
-
-
SPI2_MOSI/I2S2_SD/
USART2_RTS
A6 86
B6 87
A5 88
-
-
-
-
-
-
PD5
PD6
PD7
I/O FT
I/O FT
I/O FT
PD5
PD6
PD7
USART2_TX
USART2_RX
-
-
-
-
-
TIM9_CH2/USART2_CK
TIM2_CH2/SPI1_SCK/
SPI3_SCK/I2S3_CK/
LCD_SEG7/JTDO
COMP2_INM
A8 89 55 C4 39
A7 90 56 D4 40
C5 91 57 A5 41
PB3
PB4
PB5
I/O FT
I/O FT
I/O FT
JTDO
TIM3_CH1/SPI1_MISO/
NJTRST SPI3_MISO/LCD_SEG8
/NJTRST
COMP2_INP
TIM3_CH2/I2C1_SMBA/
SPI1_MOSI/SPI3_MOSI
/I2S3_SD/LCD_SEG9
PB5
COMP2_INP
44/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Pin descriptions
Table 9. STM32L151xC and STM32L152xC pin definitions (continued)
Pin functions
Pins
Main
function(2)
(after
Pin name
Alternate functions
Additional functions
reset)
TIM4_CH1/I2C1_SCL/
USART1_TX
B5 92 58 B5 42
PB6
I/O FT
I/O FT
PB6
COMP2_INP
TIM4_CH2/I2C1_SDA/
USART1_RX
B4 93 59 C5 43
A4 94 60 A6 44
A3 95 61 B6 45
PB7
BOOT0
PB8
PB7
BOOT0
PB8
COMP2_INP/PVD_IN
I
B
-
-
-
TIM4_CH3/TIM10_CH1/
I2C1_SCL/LCD_SEG16
I/O FT
I/O FT
I/O FT
I/O FT
TIM4_CH4/TIM11_CH1/
I2C1_SDA/LCD_COM3
B3 96 62 C6 46
PB9
PE0
PE1
PB9
PE0
PE1
-
-
-
TIM4_ETR/TIM10_CH1/
LCD_SEG36
C3 97
A2 98
-
-
-
-
-
-
TIM11_CH1/
LCD_SEG37
D3 99 63 A7 47
C4 100 64 B7 48
VSS_3
VDD_3
S
S
-
-
VSS_3
VDD_3
-
-
-
-
1. I = input, O = output, S = supply.
2. Function availability depends on the chosen device.
3. Applicable to STM32L152xC devices only. In STM32L151xC devices, this pin should be connected to VDD
.
4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over
the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).
5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON
bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO
function.
DocID022799 Rev 12
45/136
51
Alternate functions
Table 10. Alternate function input/output
Digital alternate function number
.
.
.
.
AFIO0
AFIO1
TIM2
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO11
LCD
AFIO14 AFIO15
Port
name
Alternate function
TIM9/
10/11
SYSTEM
TIM3/4/5
I2C1/2
SPI1/2
SPI3
USART1/2/3
CPRI
SYSTEM
BOOT0
NRST
BOOT0
NRST
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT OUT
-
PA0-
WKUP1
-
TIM2_CH1_ ETR TIM5_CH1
-
-
-
-
-
USART2_CTS
-
TIMx_IC1
EVENT OUT
PA1
PA2
PA3
-
-
-
TIM2_CH2
TIM2_CH3
TIM2_CH4
TIM5_CH2
-
-
-
-
-
-
-
-
-
USART2_RTS
USART2_TX
USART2_RX
SEG0
SEG1
SEG2
TIMx_IC2
TIMx_IC3
TIMx_IC4
EVENT OUT
EVENT OUT
EVENT OUT
TIM5_CH3 TIM9_CH1
TIM5_CH4 TIM9_CH2
SPI3_NSS
I2S3_WS
PA4
-
-
-
-
-
-
-
SPI1_NSS
USART2_CK
-
TIMx_IC1
EVENT OUT
PA5
-
-
-
TIM2_CH1_ETR
-
-
-
-
-
-
-
-
-
-
SPI1_SCK
-
-
-
-
-
-
-
-
-
-
-
-
TIMx_IC2
TIMx_IC3
TIMx_IC4
TIMx_IC1
TIMx_IC2
TIMx_IC3
TIMx_IC4
TIMx_IC1
TIMx_IC2
TIMx_IC3
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVEN TOUT
PA6
-
-
-
-
-
-
-
-
-
TIM3_CH1 TIM10_ CH1
TIM3_CH2 TIM11_ CH1
SPI1_MISO
-
SEG3
PA7
SPI1_MOSI
-
SEG4
PA8
MCO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
USART1_RTS
-
COM0
PA9
-
-
-
-
-
COM1
PA10
PA11
PA12
PA13
PA14
-
COM2
SPI1_MISO
-
-
-
-
SPI1_MOSI
JTMS-SWDIO
JTCK-SWCLK
-
-
-
SPI3_NSS
I2S3_WS
PA15
JTDI
TIM2_CH1_ETR
-
-
-
SPI1_NSS
-
SEG17
TIMx_IC4
EVEN TOUT
Table 10. Alternate function input/output (continued)
Digital alternate function number
.
.
.
.
AFIO0
AFIO1
TIM2
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO11
LCD
AFIO14 AFIO15
Port
name
Alternate function
TIM9/
10/11
SYSTEM
TIM3/4/5
I2C1/2
SPI1/2
SPI3
USART1/2/3
CPRI
SYSTEM
PB0
-
-
-
-
-
TIM3_CH3
TIM3_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG5
SEG6
-
-
-
-
EVEN TOUT
EVENT OUT
EVENT OUT
PB1
PB2
BOOT1
SPI3_SCK
I2S3_CK
PB3
PB4
PB5
JTDO
NJTRST
-
TIM2_CH2
-
-
-
-
-
-
SPI1_SCK
-
-
-
SEG7
SEG8
SEG9
-
-
-
EVENT OUT
EVENT OUT
EVENT OUT
-
-
TIM3_CH1
TIM3_CH2
SPI1_MISO SPI3_MISO
SPI3_MOSI
I2S3_SD
I2C1_SMBA SPI1_MOSI
PB6
PB7
PB8
PB9
PB10
PB11
-
-
-
-
-
-
TIM4_CH1
TIM4_CH2
-
-
I2C1_SCL
I2C1_SDA
-
-
-
-
-
-
-
-
-
-
-
-
USART1_TX
USART1_RX
-
-
-
-
-
-
-
-
-
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
-
-
-
TIM4_CH3 TIM10_CH1 I2C1_SCL
SEG16
COM3
SEG10
SEG11
TIM4_CH4 TIM11_CH1
I2C1_SDA
I2C2_SCL
I2C2_SDA
-
TIM2_CH3
TIM2_CH4
-
-
-
-
USART3_TX
USART3_RX
SPI2_NSS
I2S2_WS
PB12
-
-
-
TIM10_CH1 I2C2_SMBA
-
USART3_CK
SEG12
-
EVENT OUT
SPI2_SCK
I2S2_CK
PB13
PB14
PB15
-
-
-
-
-
-
-
-
-
TIM9_CH1
TIM9_CH2
TIM11_CH1
-
-
-
-
-
-
USART3_CTS
SEG13
SEG14
SEG15
-
-
-
EVENT OUT
EVENT OUT
EVENT OUT
SPI2_MISO
USART3_RTS
-
SPI2_MOSI
I2S2_SD
PC0
PC1
PC2
PC3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG18
SEG19
SEG20
SEG21
TIMx_IC1
TIMx_IC2
TIMx_IC3
TIMx_IC4
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
Table 10. Alternate function input/output (continued)
Digital alternate function number
.
.
.
.
AFIO0
AFIO1
TIM2
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO11
LCD
AFIO14 AFIO15
Port
name
Alternate function
TIM9/
10/11
SYSTEM
TIM3/4/5
I2C1/2
SPI1/2
SPI3
USART1/2/3
CPRI
SYSTEM
PC4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
TIMx_IC1
TIMx_IC2
TIMx_IC3
TIMx_IC4
TIMx_IC1
TIMx_IC2
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
PC5
PC6
PC7
PC8
PC9
-
-
-
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
I2S2_MCK
-
-
-
-
I2S3_MCK
-
-
COM4/
SEG28/
SEG40
SPI3_SCK
I2S3_CK
PC10
PC11
PC12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_TX
TIMx_IC3
TIMx_IC4
TIMx_IC1
EVENT OUT
EVENT OUT
EVENT OUT
COM5/
SEG29
/SEG41
SPI3_MISO USART3_RX
COM6/
SEG30/
SEG42
SPI3_MOSI
USART3_CK
I2S3_SD
PC13-
WKUP2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIMx_IC2
TIMx_IC3
EVENT OUT
EVENT OUT
PC14
OSC32_IN
PC15
OSC32_
OUT
-
-
-
-
-
-
-
-
-
TIMx_IC4
EVENT OUT
SPI2_NSS
I2S2_WS
PD0
PD1
-
-
-
-
-
-
TIM9_CH1
-
-
-
-
-
-
-
-
-
TIMx_IC1
TIMx_IC2
EVENT OUT
EVENT OUT
SPI2 SCK
I2S2_CK
COM7/
SEG31/
SEG43
PD2
-
-
TIM3_ETR
-
-
-
-
-
TIMx_IC3
EVENT OUT
Table 10. Alternate function input/output (continued)
Digital alternate function number
.
.
.
.
AFIO0
AFIO1
TIM2
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO11
LCD
AFIO14 AFIO15
Port
name
Alternate function
TIM9/
10/11
SYSTEM
TIM3/4/5
I2C1/2
SPI1/2
SPI3
USART1/2/3
CPRI
SYSTEM
PD3
-
-
-
-
-
-
-
-
-
-
-
SPI2_MISO
-
-
USART2_CTS
USART2_RTS
-
-
TIMx_IC4
TIMx_IC1
EVENT OUT
EVENT OUT
SPI2_MOSI
I2S2_SD
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_TX
-
-
TIMx_IC2
TIMx_IC3
TIMx_IC4
TIMx_IC1
TIMx_IC2
TIMx_IC3
TIMx_IC4
TIMx_IC1
TIMx_IC2
TIMx_IC3
TIMx_IC4
TIMx_IC1
TIMx_IC2
TIMx_IC3
TIMx_IC4
TIMx_IC1
TIMx_IC2
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_RX
-
-
TIM9_CH2
USART2_CK
-
-
-
-
-
-
-
-
-
-
-
USART3_TX
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG 38
SEG 39
-
-
-
USART3_RX
-
-
USART3_CK
-
-
USART3_CTS
-
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
USART3_RTS
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM4_ETR TIM10_CH1
PE1
-
-
TIM11_CH1
PE2
TRACECK
TRACED0
TRACED1
TRACED2
TIM3_ETR
TIM3_CH1
TIM3_CH2
-
-
PE3
-
-
-
-
-
-
-
-
-
-
PE4
-
PE5
TIM9_CH1
-
PE6-
WKUP3
TRACED3
-
-
-
-
-
TIM9_CH2
-
-
-
-
-
-
-
-
-
-
-
TIMx_IC3
TIMx_IC4
EVENT OUT
EVENT OUT
PE7
Table 10. Alternate function input/output (continued)
Digital alternate function number
.
.
.
.
AFIO0
AFIO1
TIM2
AFIO2
AFIO3
AFIO4
AFIO5
AFIO6
AFIO7
AFIO11
LCD
AFIO14 AFIO15
Port
name
Alternate function
TIM9/
10/11
SYSTEM
TIM3/4/5
I2C1/2
SPI1/2
SPI3
USART1/2/3
CPRI
SYSTEM
PE8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIMx_IC1
TIMx_IC2
TIMx_IC3
TIMx_IC4
TIMx_IC1
TIMx_IC2
TIMx_IC3
TIMx_IC4
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
EVENT OUT
PE9
TIM2_CH1_ETR
TIM5_ETR
-
PE10
PE11
PE12
PE13
PE14
PE15
TIM2_CH2
-
-
-
-
-
-
-
TIM2_CH3
-
TIM2_CH4
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
-
-
-
PH0OSC
_IN
-
-
-
-
-
-
-
-
-
-
-
PH1OSC_
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PH2
STM32L151xC STM32L152xC
Memory mapping
5
Memory mapping
Figure 9. Memory map
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DocID022799 Rev 12
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Electrical characteristics
STM32L151xC STM32L152xC
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean ±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.6 V (for the
A
DD
1.65 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
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52/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Electrical characteristics
6.1.6
Power supply scheme
Figure 12. Power supply scheme
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109
Electrical characteristics
STM32L151xC STM32L152xC
6.1.7
Optional LCD power supply scheme
Figure 13. Optional LCD power supply scheme
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1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.
6.1.8
Current consumption measurement
Figure 14. Current consumption measurement scheme
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54/136
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STM32L151xC STM32L152xC
Electrical characteristics
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,
Table 12: Current characteristics, and Table 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 11. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage
VDD–VSS
–0.3
4.0
(1)
(including VDDA and VDD
)
V
Input voltage on five-volt tolerant pin
Input voltage on any other pin
VSS −0.3
VDD+4.0
4.0
(2)
VIN
VSS −0.3
|ΔVDDx
|
Variations between different VDD power pins
Variations between all different ground pins(3)
-
-
-
50
mV
V
|VSSX −VSS
|
50
V
REF+ –VDDA Allowed voltage difference for VREF+ > VDDA
0.4
Electrostatic discharge voltage
(human body model)
VESD(HBM)
see Section 6.3.11
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. VIN maximum must always be respected. Refer to Table 12 for maximum allowed injected current values.
3. Include VREF- pin.
Table 12. Current characteristics
Symbol
Ratings
Max.
Unit
IVDD(Σ)
Total current into sum of all VDD_x power lines (source)(1)
Total current out of sum of all VSS_x ground lines (sink)(1)
Maximum current into each VDD_x power pin (source)(1)
Maximum current out of each VSS_x ground pin (sink)(1)
Output current sunk by any I/O and control pin
100
100
70
(2)
IVSS(Σ)
IVDD(PIN)
IVSS(PIN)
-70
25
IIO
Output current sourced by any I/O and control pin
Total output current sunk by sum of all IOs and control pins(2)
Total output current sourced by sum of all IOs and control pins(2)
Injected current on five-volt tolerant I/O(4), RST and B pins
Injected current on any other pin (5)
- 25
60
mA
ΣIIO(PIN)
-60
-5/+0
± 5
(3)
IINJ(PIN)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17.
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Electrical characteristics
STM32L151xC STM32L152xC
4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 11 for maximum allowed input voltage values.
5. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 13. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
TSTG
TJ
–65 to +150
150
°C
°C
6.3
Operating conditions
6.3.1
General operating conditions
Table 14. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK Internal AHB clock frequency
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
-
0
0
32
32
32
3.6
-
MHz
-
0
BOR detector disabled
1.65
BOR detector enabled, at
power on
1.8
3.6
3.6
3.6
VDD
Standard operating voltage
V
BOR detector disabled, after
power on
1.65
1.65
Analog operating voltage
(ADC and DAC not used)
Must be the same voltage as
(1)
VDDA
V
V
(2)
VDD
Analog operating voltage
(ADC or DAC used)
1.8
3.6
FT pins; 2.0 V ≤VDD
FT pins; VDD < 2.0 V
BOOT0 pin
-0.3
5.5(3)
-0.3
5.25(3)
VIN
I/O input voltage
0
5.5
Any other pin
-0.3
VDD+0.3
LQFP48 package
LQFP100 package
LQFP64 package
UFQFPN48 package
UFBGA100
-
-
-
-
-
-
364
465
435
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix 7(4)
PD
mW
625
339
WLCSP63 package
408
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STM32L151xC STM32L152xC
Electrical characteristics
Table 14. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Ambient temperature for 6 suffix version Maximum power dissipation(5)
Ambient temperature for 7 suffix version Maximum power dissipation
–40
–40
–40
–40
85
TA
°C
105
105
110
6 suffix version
Junction temperature range
TJ
°C
7 suffix version
1. When the ADC is used, refer to Table 56: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
V
DDA can be tolerated during power-up and up to 140 mV in operation.
3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 73: Thermal characteristics
on page 128).
5. In low-power dissipation state, TA can be extended to -40°C to 105°C temperature range as long as TJ does not exceed TJ
max (see Table 73: Thermal characteristics on page 128).
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
conditions summarized in Table 14.
Table 15. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
BOR detector enabled
BOR detector disabled
BOR detector enabled
BOR detector disabled
0
0
-
∞
1000
∞
VDD rise time rate
-
(1)
tVDD
µs/V
20
-
VDD fall time rate
0
-
1000
3.3
VDD rising, BOR enabled
-
2
(1)
TRSTTEMPO
Reset temporization
ms
VDD rising, BOR disabled(2)
0.4
1
0.7
1.5
1.5
1.7
1.76
1.93
2.03
2.30
2.41
1.6
Falling edge
1.65
1.65
1.74
1.8
Power on/power down reset
threshold
VPOR/PDR
Rising edge
1.3
1.67
1.69
1.87
1.96
2.22
2.31
Falling edge
VBOR0
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Rising edge
V
Falling edge
1.97
2.07
2.35
2.44
VBOR1
Rising edge
Falling edge
VBOR2
Rising edge
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Table 15. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Falling edge
Min
Typ
Max
Unit
2.45
2.54
2.68
2.78
1.8
2.55
2.66
2.8
2.6
2.7
VBOR3
Brown-out reset threshold 3
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
BOR0 threshold
2.85
2.95
1.88
1.99
2.09
2.18
2.28
2.38
2.48
2.58
2.69
2.79
2.88
2.99
3.09
3.20
-
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Brown-out reset threshold 4
2.9
1.85
1.94
2.04
2.14
2.24
2.34
2.44
2.54
2.64
2.74
2.83
2.94
3.05
3.15
40
Programmable voltage detector
threshold 0
1.88
1.98
2.08
2.20
2.28
2.39
2.47
2.57
2.68
2.77
2.87
2.97
3.08
-
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
V
Vhyst
Hysteresis voltage
mV
All BOR and PVD
thresholds excepting BOR0
-
100
-
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. Please see option “D” in Ordering information scheme for more details.
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Electrical characteristics
6.3.3
Embedded internal reference voltage
The parameters given in Table 17 are based on characterization results, unless otherwise
specified.
Table 16. Embedded internal reference voltage calibration values
Calibration value name
Description
Memory address
Raw data acquired at
VREFINT_CAL
temperature of 30 °C ±5 °C
0x1FF8 00F8 - 0x1FF8 00F9
VDDA= 3 V ±10 mV
Table 17. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)
VREFINT out
IREFINT
Internal reference voltage
– 40 °C < TJ < +110 °C 1.202 1.224 1.242
V
Internal reference current
consumption
-
-
-
-
-
1.4
2
2.3
3
µA
ms
V
TVREFINT
Internal reference startup time
VDDA and VREF+ voltage during
VREFINT factory measure
VVREF_MEAS
2.99
3
3.01
Including uncertainties
due to ADC and
VDDA/VREF+ values
Accuracy of factory-measured VREF
value(2)
AVREF_MEAS
-
-
-
±5
mV
ppm/°
C
(3)
TCoeff
Temperature coefficient
–40 °C < TJ < +110 °C
25
100
(3)
ACoeff
Long-term stability
Voltage coefficient
1000 hours, T= 25 °C
3.0 V < VDDA < 3.6 V
-
-
-
-
1000
2000
ppm
(3)
VDDCoeff
ppm/V
ADC sampling time when reading
the internal reference voltage
(3)
TS_vrefint
-
-
-
4
-
-
-
-
µs
µs
µA
Startup time of reference voltage
buffer for ADC
(3) (4)
TADC_BUF
10
25
Consumption of reference voltage
buffer for ADC
(3)
IBUF_ADC
-
13.5
(3)
IVREF_OUT
VREF_OUT output current (5)
-
-
-
-
-
-
1
µA
pF
(3)
CVREF_OUT
VREF_OUT output load
50
Consumption of reference voltage
buffer for VREF_OUT and COMP
(3)
ILPBUF
-
-
730
1200
nA
(3)
VREFINT_DIV1
1/4 reference voltage
1/2 reference voltage
3/4 reference voltage
-
-
-
24
49
74
25
50
75
26
51
76
%
VREFIN
(3)
VREFINT_DIV2
T
(3)
VREFINT_DIV3
1. Guaranteed by test in production.
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by characterization results.
4. Shortest sampling time can be determined in the application by multiple iterations.
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Electrical characteristics
STM32L151xC STM32L152xC
5. To guarantee less than 1% VREF_OUT deviation.
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless
otherwise specified. The current consumption values are derived from tests performed
under ambient temperature T = 25 °C and V supply voltage conditions summarized in
A
DD
Table 14: General operating conditions, unless otherwise specified.
The MCU is placed under the following conditions:
•
•
•
All I/O pins are configured in analog input mode
All peripherals are disabled except when explicitly mentioned.
The Flash memory access time, 64-bit access and prefetch is adjusted depending on
f
frequency and voltage range to provide the best CPU performance.
HCLK
•
•
When the peripherals are enabled f
= f
= f
.
APB1
APB2
AHB
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used).
•
The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 27: High-speed external user clock characteristics.
•
•
For maximum current consumption V = V
= 3.6 V is applied to all supply pins.
DD
DDA
For typical current consumption V = V
= 3.0 V is applied to all supply pins if not
DDA
DD
specified otherwise.
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STM32L151xC STM32L152xC
Electrical characteristics
Table 18. Current consumption in Run mode, code with data processing running from Flash
Symbol
Parameter
Conditions
fHCLK
Typ
Max(1) Unit
1 MHz
2 MHz
4 MHz
4 MHz
8 MHz
16 MHz
8 MHz
16 MHz
32 MHz
215
400
725
0.915
1.75
3.4
400
Range 3, VCORE=1.2 V
VOS[1:0] = 11
600
960
1.1
2.1
3.9
2.8
4.9
9.4
µA
mA
µA
fHSE = fHCLK up to 16
MHz included, fHSE
=
Range 2, VCORE=1.5 V
fHCLK/2 above 16 MHz VOS[1:0] = 10
(PLL ON)(2)
Supply
2.1
IDD
current in
Run mode,
code
executed
from Flash
Range 1, VCORE=1.8 V
VOS[1:0] = 01
(Run
from
Flash)
4.2
8.25
Range 2, VCORE=1.5 V
VOS[1:0] = 10
16 MHz
32 MHz
3.5
8.2
4
HSI clock source (16
MHz)
Range 1, VCORE=1.8 V
VOS[1:0] = 01
9.6
MSI clock, 65 kHz
MSI clock, 524 kHz
MSI clock, 4.2 MHz
65 kHz
524 kHz
4.2 MHz
40.5
125
775
110
190
900
Range 3, VCORE=1.2 V
VOS[1:0] = 11
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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109
Electrical characteristics
STM32L151xC STM32L152xC
Table 19. Current consumption in Run mode, code with data processing running from RAM
Symbol
Parameter
Conditions
fHCLK
Typ
Max(1) Unit
1 MHz
185
345
645
0.755
1.5
240
Range 3,
VCORE=1.2 V VOS[1:0] 2 MHz
410
880(3)
1.4
µA
mA
µA
= 11
4 MHz
f
HSE = fHCLK
4 MHz
up to 16 MHz,
included
Range 2,
VCORE=1.5 V VOS[1:0] 8 MHz
2.1
fHSE = fHCLK/2 above
16 MHz
= 10
16 MHz
3
3.5
(PLL ON)(2)
8 MHz
1.8
2.8
Range 1,
Supply current in
DD (Run Run mode, code
VCORE=1.8 V
16 MHz
32 MHz
3.6
4.1
I
VOS[1:0] = 01
from
RAM)
executed from
RAM, Flash
switched off
7.15
8.3
Range 2,
VCORE=1.5 V VOS[1:0] 16 MHz
2.95
7.15
3.5
8.4
= 10
HSI clock source (16
MHz)
Range 1,
VCORE=1.8 V VOS[1:0] 32 MHz
= 01
MSI clock, 65 kHz
MSI clock, 524 kHz
MSI clock, 4.2 MHz
65 kHz
38.5
110
690
85
Range 3,
VCORE=1.2 V VOS[1:0] 524 kHz
= 11
160
810
4.2 MHz
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. Guaranteed by test in production.
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STM32L151xC STM32L152xC
Electrical characteristics
Table 20. Current consumption in Sleep mode
Symbol
Parameter
Conditions
fHCLK
Typ
Max(1)
Unit
1 MHz
2 MHz
4 MHz
4 MHz
8 MHz
16 MHz
8 MHz
16 MHz
32 MHz
50
78.5
140
165
310
590
350
680
1600
130
195
310
310
440
830
550
990
2100
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
f
HSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
Range 2,
VCORE=1.5 V
above 16 MHz (PLL VOS[1:0] = 10
ON)(2)
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
Supplycurrent
in Sleep
mode, Flash
OFF
Range 2,
V
CORE=1.5 V
16 MHz
32 MHz
640
890
VOS[1:0] = 10
HSI clock source
(16 MHz)
Range 1,
VCORE=1.8 V
1600
2200
VOS[1:0] = 01
MSI clock, 65 kHz
65 kHz
524 kHz
4.2 MHz
1 MHz
19
33
60
99
Range 3,
MSI clock, 524 kHz VCORE=1.2 V
VOS[1:0] = 11
MSI clock, 4.2 MHz
145
60.5
89.5
150
180
320
605
380
695
1600
210
130
190
320
320
460
840
540
1000
2100
IDD (Sleep)
µA
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
2 MHz
4 MHz
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
4 MHz
Range 2,
VCORE=1.5 V
8 MHz
above 16 MHz (PLL VOS[1:0] = 10
16 MHz
8 MHz
ON)(2)
Supplycurrent
in Sleep
mode, Flash
ON
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
16 MHz
32 MHz
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
32 MHz
650
910
HSI clock source
(16 MHz)
Range 1,
VCORE=1.8 V
1600
2200
VOS[1:0] = 01
MSI clock, 65 kHz
65 kHz
524 kHz
4.2 MHz
30
44
90
96
Supplycurrent
in Sleep
mode, Flash
ON
Range 3,
MSI clock, 524 kHz VCORE=1.2V
VOS[1:0] = 11
MSI clock, 4.2 MHz
155
220
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
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Table 21. Current consumption in Low-power run mode
Symbol Parameter
Conditions
Typ
Max(1)
Unit
TA = -40 °C to 25 °C
TA = 85 °C
8.6
19
35
14
24
40
26
28
36
52
20
32
49
26
38
55
41
44
56
73
12
25
47
16
29
51
29
31
42
64
24
37
61
30
44
67
46
50
87
110
MSI clock, 65 kHz
fHCLK = 32 kHz
All
TA = 105 °C
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
TA =-40 °C to 25 °C
TA = 85 °C
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = 105 °C
TA = -40 °C to 25 °C
TA = 55 °C
MSI clock, 131 kHz
f
HCLK = 131 kHz
TA = 85 °C
Supply
TA = 105 °C
IDD (LP
current in
Low-power
run mode
Run)
TA = -40 °C to 25 °C
TA = 85 °C
MSI clock, 65 kHz
fHCLK = 32 kHz
µA
TA = 105 °C
All
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
TA = -40 °C to 25 °C
TA = 85 °C
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = 105 °C
TA = -40 °C to 25 °C
TA = 55 °C
MSI clock, 131 kHz
f
HCLK = 131 kHz
TA = 85 °C
TA = 105 °C
Max allowed
DD max current in
(LP Run) Low-power
run mode
VDD from
1.65 V to
3.6 V
I
-
-
-
200
1. Guaranteed by characterization results, unless otherwise specified.
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Electrical characteristics
Table 22. Current consumption in Low-power sleep mode
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
MSI clock, 65 kHz
f
HCLK = 32 kHz
TA = -40 °C to 25 °C
4.4
-
Flash OFF
TA = -40 °C to 25 °C
TA = 85 °C
14
19
27
15
20
28
17
18
22
30
14
19
27
15
20
28
17
18
22
30
16
23
33
17
23
33
19
21
25
35
16
22
32
17
23
33
19
21
25
36
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash ON
TA = 105 °C
All peripherals
OFF, VDD from
1.65 V to 3.6 V
TA = -40 °C to 25 °C
TA = 85 °C
MSI clock, 65 kHz
f
HCLK = 65 kHz,
Flash ON
TA = 105 °C
TA = -40 °C to 25 °C
TA = 55 °C
MSI clock, 131 kHz
fHCLK = 131 kHz,
Flash ON
Supply
TA = 85 °C
IDD
current in
(LP Sleep) Low-power
sleep mode
TA = 105 °C
TA = -40 °C to 25 °C
TA = 85 °C
µA
MSI clock, 65 kHz
f
HCLK = 32 kHz
TA = 105 °C
TA = -40 °C to 25 °C
TA = 85 °C
TIM9 and
USART1
enabled, Flash
ON, VDD from
1.65 V to 3.6 V
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = 105 °C
TA = -40 °C to 25 °C
TA = 55 °C
MSI clock, 131 kHz
f
HCLK = 131 kHz
TA = 85 °C
TA = 105 °C
Max
allowed
current in
Low-power
IDD max
(LP Sleep)
VDD from 1.65 V
to 3.6 V
-
-
-
200
sleep mode
1. Guaranteed by characterization results, unless otherwise specified.
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Electrical characteristics
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Table 23. Typical and maximum current consumptions in Stop mode
Symbol
Parameter
Conditions
Typ
Max(1) Unit
TA = -40°C to 25°C
VDD = 1.8 V
1.15
-
TA = -40°C to 25°C
TA = 55°C
1.4
2
-
LCD
OFF
-
TA= 85°C
3.4
10
23
6
RTC clocked by LSI
TA = 105°C
6.35
1.55
2.15
3.55
6.3
or LSE external clock
(32.768kHz),
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog)
TA = -40°C to 25°C
TA = 55°C
LCD
ON
7
(static
TA= 85°C
12
27
10
11
16
44
-
duty)(2)
TA = 105°C
TA = -40°C to 25°C
TA = 55°C
3.9
LCD
4.65
6.25
9.1
ON (1/8
duty)(3)
TA= 85°C
TA = 105°C
TA = -40°C to 25°C
TA = 55°C
1.5
Supply current in
Stop mode with RTC
enabled
IDD (Stop
with RTC)
2.15
3.7
-
-
-
-
-
-
-
-
-
-
-
µA
LCD
OFF
TA= 85°C
TA = 105°C
6.75
1.6
TA = -40°C to 25°C
TA = 55°C
LCD
ON
2.3
(static
TA= 85°C
3.8
RTC clocked by LSE
external quartz
duty)(2)
TA = 105°C
6.85
4
(32.768kHz),
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog(4)
TA = -40°C to 25°C
TA = 55°C
LCD
4.85
6.5
ON (1/8
duty)(3)
TA= 85°C
TA = 105°C
9.1
TA = -40°C to 25°C
VDD = 1.8V
1.2
1.5
-
-
-
LCD
OFF
TA = -40°C to 25°C
VDD = 3.0V
TA = -40°C to 25°C
VDD = 3.6V
1.75
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Electrical characteristics
Table 23. Typical and maximum current consumptions in Stop mode (continued)
Symbol
Parameter
Conditions
Typ
Max(1) Unit
Regulator in LP mode, HSI and
HSE OFF, independent
TA = -40°C to 25°C
1.8
2.2
watchdog and LSI enabled
Supply current in
IDD (Stop) Stop mode (RTC
disabled)
TA = -40°C to 25°C 0.435
1
µA
Regulator in LP mode, LSI, HSI
and HSE OFF (no independent
watchdog)
TA = 55°C
TA= 85°C
TA = 105°C
0.99
2.4
3
9
5.5
22(5)
MSI = 4.2 MHz
MSI = 1.05 MHz
MSI = 65 kHz(6)
2
-
IDD
(WU from wakeup from Stop
Stop) mode
Supply current during
TA = -40°C to 25°C
1.45
1.45
-
-
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.
3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
5. Guaranteed by test in production.
6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part
of the wakeup period, the current corresponds the Run mode current.
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Table 24. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
TA = -40 °C to 25 °C
VDD = 1.8 V
0.905
-
TA = -40 °C to 25 °C
1.15
1.5
1.9
2.2
RTC clocked by LSI (no
independent watchdog) TA = 55 °C
TA= 85 °C
1.75
2.1
4
8.3(2)
IDD
Supply current in
TA = 105 °C
(Standby Standby mode with RTC
with RTC) enabled
TA = -40 °C to 25 °C
0.98
-
VDD = 1.8 V
TA = -40 °C to 25 °C
TA = 55 °C
RTC clocked by LSE
external quartz (no
independent
1.3
1.7
-
-
-
-
µA
watchdog)(3)
TA= 85 °C
2.05
2.45
TA = 105 °C
Independent watchdog
and LSI enabled
TA = -40 °C to 25 °C
1
1.7
TA = -40 °C to 25 °C
TA = 55 °C
0.29
0.345
0.575
1.45
0.6
0.9
Supply current in
Standby mode (RTC
disabled)
IDD
(Standby)
Independent watchdog
and LSI OFF
TA = 85 °C
2.75
7(2)
TA = 105 °C
IDD
Supply current during
(WU from wakeup time from
Standby) Standby mode
-
TA = -40 °C to 25 °C
1
-
mA
1. Guaranteed by characterization results, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
•
•
•
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
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Electrical characteristics
(1)
Table 25. Peripheral current consumption
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1, Range 2, Range 3,
VCORE
1.8 V
=
VCORE
1.5 V
=
VCORE
1.2 V
=
Low-power
sleep and
run
Peripheral
Unit
VOS[1:0] = VOS[1:0] = VOS[1:0] =
01
10
11
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
LCD
11.2
11.2
12.9
14.4
4.0
8.9
9.0
10.4
11.5
3.1
3.0
4.6
2.3
5.2
4.6
7.0
6.8
5.8
6.3
10.6
2.2
4.9
3.8
7.0
7.1
8.2
9.0
2.4
2.3
3.6
1.8
4.1
3.6
5.5
5.3
4.6
5.0
8.3
1.8
3.9
3.0
8.9
9.0
10.4
11.5
3.1
3.0
4.6
2.3
5.2
4.6
7.0
6.8
5.8
6.3
10.6
2.2
4.9
3.8
3.8
5.8
WWDG
2.9
SPI2
6.5
µA/MHz
APB1
(fHCLK
)
SPI3
5.9
USART2
USART3
I2C1
8.8
8.4
7.3
I2C2
7.9
USB
13.3
2.8
PWR
DAC
6.1
COMP
4.8
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Electrical characteristics
STM32L151xC STM32L152xC
(1)
Table 25. Peripheral current consumption (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1, Range 2, Range 3,
VCORE
1.8 V
=
VCORE
1.5 V
=
VCORE
1.2 V
=
Low-power
sleep and
run
Peripheral
Unit
VOS[1:0] = VOS[1:0] = VOS[1:0] =
01
10
11
SYSCFG &
RI
2.6
2.0
1.6
2.0
TIM9
7.9
5.9
6.4
4.7
4.6
8.3
3.4
7.1
3.3
3.5
3.2
3.3
3.4
3.0
0.6
9.4
12.7
13.4
154
5.0
3.8
3.7
6.6
2.8
5.6
2.6
2.8
2.5
2.5
2.7
2.3
0.5
8
6.4
4.7
4.6
8.3
3.4
7.1
3.3
3.5
3.2
3.3
3.4
3.0
0.6
TIM10
TIM11
ADC(2)
SPI1
APB2
5.9
10.5
4.3
USART1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOH
CRC
8.8
4.3
µA/MHz
4.3
(fHCLK
)
4.0
4.1
4.2
AHB
3.7
0.8
(3)
FLASH
DMA1
DMA2
11.1
15.6
16.3
187
-
10
12.7
13.4
10.5
120
All enabled
IDD (RTC)
IDD (LCD)
144.6
0.4
3.1
1450
340
0.16
2
(4)
IDD (ADC)
(5)
IDD (DAC)
IDD (COMP1)
IDD (COMP2)
µA
Slow mode
Fast mode
5
(6)
IDD (PVD / BOR)
IDD (IWDG)
2.6
0.25
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling.
2. HSI oscillator is OFF for this measure.
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Electrical characteristics
3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC
conversion (HSI consumption not included).
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC
conversion of VDD/2. DAC is in buffered mode, output is left floating.
6. Including supply current of internal reference voltage.
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
•
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under the conditions summarized in Table 14.
Table 26. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ Max(1) Unit
tWUSLEEP
Wakeup from Sleep mode
fHCLK = 32 MHz
0.4
46
-
-
fHCLK = 262 kHz
Flash enabled
Wakeup from Low-power sleep
mode, fHCLK = 262 kHz
tWUSLEEP_LP
fHCLK = 262 kHz
Flash switched OFF
46
-
-
Wakeup from Stop mode,
regulator in Run mode
fHCLK = fMSI = 4.2 MHz
8.2
ULP bit = 1 and FWU bit = 1
fHCLK = fMSI = 4.2 MHz
Voltage range 1 and 2
7.7
8.2
8.9
µs
fHCLK = fMSI = 4.2 MHz
Voltage range 3
13.1
tWUSTOP
f
HCLK = fMSI = 2.1 MHz
10.2
16
13.4
20
Wakeup from Stop mode,
regulator in low-power mode
fHCLK = fMSI = 1.05 MHz
fHCLK = fMSI = 524 kHz
ULP bit = 1 and FWU bit = 1
31
37
fHCLK = fMSI = 262 kHz
57
66
fHCLK = fMSI = 131 kHz
fHCLK = MSI = 65 kHz
112
221
123
236
Wakeup from Standby mode
ULP bit = 1 and FWU bit = 1
fHCLK = MSI = 2.1 MHz
fHCLK = MSI = 2.1 MHz
58
104
tWUSTDBY
Wakeup from Standby mode
FWU bit = 0
2.6
3.25
ms
1. Guaranteed by characterization, unless otherwise specified
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6.3.6
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the
recommended clock input waveform is shown in Figure 15.
(1)
Table 27. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CSS is on or
PLL is used
1
8
32
MHz
User external clock source
frequency
fHSE_ext
CSS is off, PLL
not used
0
8
32
MHz
V
VHSEH
VHSEL
tw(HSEH)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
0.3VDD
OSC_IN high or low time
OSC_IN rise or fall time
12
-
-
tw(HSEL)
-
ns
pF
tr(HSE)
tf(HSE)
-
-
-
20
-
Cin(HSE) OSC_IN input capacitance
1. Guaranteed by design.
2.6
Figure 15. High-speed external clock source AC timing diagram
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9
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9
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W
W
W
W
Uꢊ+6(ꢍ
Iꢊ+6(ꢍ
Zꢊ+6(/ꢍ
7
+6(
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Electrical characteristics
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under the conditions summarized in Table 14.
(1)
Table 28. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
1
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
0.7VDD
VSS
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level
voltage
-
-
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
OSC32_IN rise or fall time
465
ns
tr(LSE)
tf(LSE)
-
-
-
10
-
CIN(LSE) OSC32_IN input capacitance
1. Guaranteed by design.
0.6
pF
Figure 16. Low-speed external clock source AC timing diagram
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9
/6(+
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ꢂꢉꢕ
9
/6(/
W
W
W
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Iꢊ/6(ꢍ
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 29. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
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109
Electrical characteristics
STM32L151xC STM32L152xC
(1)(2)
Table 29. HSE oscillator characteristics
Symbol
Parameter
Conditions
Min Typ
Max
Unit
fOSC_IN
RF
Oscillator frequency
Feedback resistor
-
-
1
24
-
MHz
-
-
200
20
kΩ
Recommended load
capacitance versus
equivalent serial
resistance of the crystal
(RS)(3)
C
RS = 30 Ω
-
pF
mA
mA
VDD= 3.3 V,
VIN = VSS with 30 pF
load
IHSE
HSE driving current
-
-
3
2.5 (startup)
C = 20 pF
OSC = 16 MHz
-
-
-
-
f
0.7 (stabilized)
HSE oscillator power
consumption
IDD(HSE)
2.5 (startup)
C = 10 pF
fOSC = 16 MHz
Startup
0.46 (stabilized)
Oscillator
transconductance
gm
3.5
-
-
-
-
mA /V
ms
(4)
tSU(HSE)
Startup time
VDD is stabilized
1
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by characterization results.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C . Refer to the application note AN2867 “Oscillator design guide for ST
C
L1
L2
microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
Figure 17. HSE oscillator circuit diagram
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1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 30. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 30. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Low speed external oscillator
frequency
fLSE
RF
C(2)
ILSE
-
-
-
-
32.768
1.2
-
-
kHz
Feedback resistor
MΩ
Recommended load capacitance
versus equivalent serial
RS = 30 kΩ
-
8
-
pF
µA
resistance of the crystal (RS)(3)
LSE driving current
VDD = 3.3 V, VIN = VSS
-
-
-
1.1
V
DD = 1.8 V
450
600
750
-
-
-
-
-
-
LSE oscillator current
consumption
IDD (LSE)
VDD = 3.0 V
-
nA
V
DD = 3.6V
-
gm
Oscillator transconductance
Startup time
-
3
-
µA/V
s
(4)
tSU(LSE)
VDD is stabilized
1
1. Guaranteed by characterization results.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.
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109
Electrical characteristics
STM32L151xC STM32L152xC
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Note:
For C and C , it is recommended to use high-quality ceramic capacitors in the 5 pF to
L1 L2
15 pF range selected to match the requirements of the crystal or resonator (see Figure 18).
and C are usually the same size. The crystal manufacturer typically specifies a load
C
L1
L2,
capacitance which is the series combination of C and C .
L1
L2
Load capacitance C has the following formula: C = C x C / (C + C ) + C where
L
L
L1
L2
L1
L2
stray
C
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
stray
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended
L1
L2
to use a resonator with a load capacitance C ≤7 pF. Never use a resonator with a load
L
capacitance of 12.5 pF.
Example: if the user chooses a resonator with a load capacitance of C = 6 pF and C
=
stray
L
2 pF, then C = C = 8 pF.
L1
L2
Figure 18. Typical application with a 32.768 kHz crystal
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STM32L151xC STM32L152xC
Electrical characteristics
6.3.7
Internal clock source characteristics
The parameters given in Table 31 are derived from tests performed under the conditions
summarized in Table 14.
High-speed internal (HSI) RC oscillator
Table 31. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ Max Unit
fHSI
VDD = 3.0 V
-
-
16
-
MHz
%
Trimming code is not a multiple of 16
Trimming code is a multiple of 16
VDDA = 3.0 V, TA = 25 °C
0.4 0.7
HSI user-trimmed
resolution
(1)(2)
TRIM
-
-
-
-
-
-
-
1.5
%
-1(3)
-1.5
-2
1(3)
1.5
2
%
VDDA = 3.0 V, TA = 0 to 55 °C
VDDA = 3.0 V, TA = -10 to 70 °C
%
%
Accuracy of the
factory-calibrated
HSI oscillator
(2)
ACCHSI
V
DDA = 3.0 V, TA = -10 to 85 °C
VDDA = 3.0 V, TA = -10 to 105 °C
DDA = 1.65 V to 3.6 V
-2.5
-4
2
%
2
%
V
-4
-
-
3
6
%
µs
µA
TA = -40 to 105 °C
HSI oscillator
startup time
(2)
tSU(HSI)
-
3.7
100
HSI oscillator
power consumption
(2)
IDD(HSI)
-
-
140
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
Low-speed internal (LSI) RC oscillator
Table 32. LSI oscillator characteristics
Symbol
Parameter
LSI frequency
Min
Typ
Max
Unit
(1)
fLSI
26
38
56
kHz
%
LSI oscillator frequency drift
0°C ≤TA ≤ 105°C
(2)
DLSI
-10
-
4
(3)
tsu(LSI)
LSI oscillator startup time
-
-
-
200
510
µs
(3)
IDD(LSI)
LSI oscillator power consumption
400
nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design.
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109
Electrical characteristics
STM32L151xC STM32L152xC
Multi-speed internal (MSI) RC oscillator
Table 33. MSI oscillator characteristics
Symbol
Parameter
Condition
Typ
Max Unit
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
-
65.5
131
262
524
1.05
2.1
-
-
kHz
-
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
fMSI
-
-
-
-
-
MHz
4.2
ACCMSI
Frequency error after factory calibration
0.5
%
%
MSI oscillator frequency drift
0 °C ≤TA ≤105 °C
(1)
DTEMP(MSI)
-
-
3
-
-
MSI oscillator frequency drift
1.65 V ≤VDD ≤3.6 V, TA = 25 °C
(1)
DVOLT(MSI)
2.5 %/V
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
0.75
1
-
-
-
1.5
2.5
4.5
8
(2)
IDD(MSI)
MSI oscillator power consumption
-
-
-
-
-
-
-
-
-
-
µA
15
30
20
15
10
6
tSU(MSI)
MSI oscillator startup time
µs
5
MSI range 6,
Voltage range 1
and 2
3.5
5
-
-
MSI range 6,
Voltage range 3
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Symbol
Electrical characteristics
Table 33. MSI oscillator characteristics (continued)
Parameter
Condition
Typ
Max Unit
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
-
-
-
-
-
-
40
20
10
4
2.5
µs
2
(2)
tSTAB(MSI)
MSI oscillator stabilization time
MSI range 6,
Voltage range 1
and 2
-
2
3
MSI range 3,
Voltage range 3
-
-
-
Any range to
range 5
4
fOVER(MSI) MSI oscillator frequency overshoot
MHz
6
Any range to
range 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.
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109
Electrical characteristics
STM32L151xC STM32L152xC
6.3.8
PLL characteristics
The parameters given in Table 34 are derived from tests performed under the conditions
summarized in Table 14.
Table 34. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
45
2
-
-
-
24
55
32
MHz
%
fPLL_IN
fPLL_OUT
tLOCK
PLL input clock duty cycle
PLL output clock
MHz
PLL lock time
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
µs
Jitter
Cycle-to-cycle jitter
-
-
-
-
600
450
150
ps
I
DDA(PLL)
Current consumption on VDDA
Current consumption on VDD
220
120
µA
IDD(PLL)
1. Guaranteed by characterization results.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
6.3.9
Memory characteristics
The characteristics are given at TA = -40 to 105 °C unless otherwise specified.
RAM memory
Table 35. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM Data retention mode(1)
STOP mode (or RESET)
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
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Electrical characteristics
Flash memory and data EEPROM
Table 36. Flash memory and data EEPROM characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
Operating voltage
VDD
-
1.65
-
3.6
V
Read / Write / Erase
Programming/ erasing
time for byte / word /
double word / half-page
Erasing
-
-
3.28
3.28
3.94
3.94
tprog
ms
Programming
Average current during
the whole programming /
erase operation
-
-
600
1.5
900
2.5
µA
IDD
TA = 25 °C, VDD = 3.6 V
Maximum current (peak)
during the whole
programming / erase
operation
mA
1. Guaranteed by design.
Table 37. Flash memory and data EEPROM endurance and retention
Value
Symbol
Parameter
Conditions
Unit
Min(1) Typ Max
Cycling (erase / write)
Program memory
-
-
-
-
-
-
-
-
-
-
-
-
10
300
30
TA = -40°C to
(2)
NCYC
kcycles
105 °C
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
TRET = +85 °C
Data retention (EEPROM data memory)
after 300 kcycles at TA = 85 °C
30
(2)
tRET
years
Data retention (program memory) after
10 kcycles at TA = 105 °C
10
TRET = +105 °C
Data retention (EEPROM data memory)
after 300 kcycles at TA = 105 °C
10
1. Guaranteed by characterization results.
2. Characterization is done according to JEDEC JESD22-A117.
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Electrical characteristics
STM32L151xC STM32L152xC
6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 38. They are based on the EMS levels and classes
defined in application note AN1709.
Table 38. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
4A
conforms to IEC 61000-4-2
VDD = 3.3 V, LQFP100, TA = +25
°C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VEFTB
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
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Electrical characteristics
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 39. EMI characteristics
Max vs. frequency range
Monitored
4 MHz 16 MHz
32MHz
voltage
range 1
Symbol Parameter
Conditions
Unit
frequency band
voltage voltage
range 3 range 2
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
3
-6
4
-5
-7
-7
1
VDD = 3.3 V,
TA = 25 °C,
LQFP100 package
compliant with IEC
61967-2
18
15
2.5
dBµV
-
SEMI
Peak level
5
2
6.3.11
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114, ANSI/ESD STM5.3.1. standard.
Table 40. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic
VESD(HBM) discharge voltage
(human body model)
TA = +25 °C, conforming
to JESD22-A114
2
2000
V
Electrostatic
VESD(CDM) discharge voltage
(charge device model)
TA = +25 °C, conforming
to ANSI/ESD STM5.3.1.
C4
500
V
1. Guaranteed by characterization results.
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109
Electrical characteristics
Static latch-up
STM32L151xC STM32L152xC
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 41. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
6.3.12
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard pins) should be avoided during normal product operation.
DD
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation, LCD levels).
The test results are given in the Table 42.
Table 42. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on all 5 V tolerant (FT) pins
Injected current on BOOT0
-5 (1)
NA
NA
+5
IINJ
-0
mA
Injected current on any other pin
-5 (1)
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
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Electrical characteristics
6.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL
compliant.
Table 43. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(1)(2)
TC and FT I/O
BOOT0
-
-
0.3 VDD
VIL
Input low level voltage
(2)
-
-
0.14 VDD
TC I/O
0.45 VDD+0.38(2)
-
-
-
-
-
-
VIH
Input high level voltage
FT I/O
0.39 VDD+0.59(2)
-
-
V
BOOT0
0.15 VDD+0.56(2)
(3)
TC and FT I/O
BOOT0
-
-
10% VDD
0.01
I/O Schmitt trigger voltage
hysteresis(2)
Vhys
VSS ≤VIN ≤VDD
I/Os with LCD
-
-
-
-
±50
±50
VSS ≤VIN ≤VDD
I/Os with analog
switches
VSS ≤VIN ≤VDD
I/Os with analog
switches and LCD
nA
-
-
±50
Ilkg
Input leakage current (4)
VSS ≤VIN ≤VDD
I/Os with USB
-
-
-
-
±250
±50
±10
60
VSS ≤VIN ≤VDD
TC and FT I/Os
FT I/O
-
-
µA
VDD ≤VIN ≤5V
Weak pull-up equivalent
resistor(5)(1)
RPU
VIN = VSS
30
45
kΩ
Weak pull-down equivalent
resistor(5)
RPD
CIO
VIN = VDD
30
-
45
5
60
-
kΩ
I/O pin capacitance
-
pF
1. Guaranteed by test in production
2. Guaranteed by design.
3. With a minimum of 200 mV.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Electrical characteristics
STM32L151xC STM32L152xC
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA with the non-standard V /V specifications given in Table 44.
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 12).
Σ
VDD( )
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 12).
Σ
VSS( )
Output voltage levels
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL
compliant.
Table 44. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
(1)(2)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
0.4
-
I
IO = 8 mA
(2)(3)
2.7 V < VDD < 3.6 V
VOH
VDD-0.4
(3)(4)
VOL
-
0.45
IIO = 4 mA
V
(3)(4)
1.65 V < VDD < 3.6 V
VOH
VDD-0.45
-
-
(1)(4)
VOL
1.3
-
I
IO = 20 mA
2.7 V < VDD < 3.6 V
(3)(4)
VOH
VDD-1.3
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. Guaranteed by test in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Guaranteed by characterization results.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 19 and
Table 45, respectively.
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the conditions summarized in Table 14.
(1)
Table 45. I/O AC characteristics
OSPEEDRx
[1:0] bit
Symbol
Parameter
Conditions
Min Max(2) Unit
value(1)
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
400
625
625
2
fmax(IO)out Maximum frequency(3)
kHz
ns
00
01
10
tf(IO)out
Output rise and fall time
tr(IO)out
fmax(IO)out Maximum frequency(3)
MHz
ns
1
125
250
10
2
tf(IO)out
Output rise and fall time
tr(IO)out
Fmax(IO)out Maximum frequency(3)
MHz
ns
25
125
50
8
tf(IO)out
Output rise and fall time
tr(IO)out
Fmax(IO)out Maximum frequency(3)
MHz
11
-
5
tf(IO)out
Output rise and fall time
tr(IO)out
30
ns
Pulse width of external
tEXTIpw
signals detected by the
EXTI controller
-
8
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 19.
DocID022799 Rev 12
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109
Electrical characteristics
STM32L151xC STM32L152xC
Figure 19. I/O AC characteristics definition
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6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 46)
PU
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the conditions summarized in Table 14.
Table 46. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST input low level
voltage
(1)
VIL(NRST)
-
-
-
0.3 VDD
NRST input high
level voltage
(1)
(1)
VIH(NRST)
-
0.39VDD+0.59
-
-
V
IOL = 2 mA
2.7 V < VDD < 3.6 V
-
-
-
NRST output low
level voltage
VOL(NRST)
0.4
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
NRST Schmitt trigger
voltage hysteresis
(1)
(2)
Vhys(NRST)
RPU
-
-
10%VDD
-
mV
kΩ
ns
Weak pull-up
VIN = VSS
30
-
45
-
60
50
-
equivalent resistor(3)
NRST input filtered
pulse
(1)
VF(NRST)
-
-
NRST input not
filtered pulse
(3)
VNF(NRST)
350
-
ns
1. Guaranteed by design.
2. With a minimum of 200 mV.
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.
88/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Electrical characteristics
Figure 20. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 46. Otherwise the reset will not be taken into account by the device.
6.3.15
TIM timer characteristics
The parameters given in the Table 47 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output ction
characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 47. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
ns
tres(TIM)
Timer resolution time
fTIMxCLK = 32 MHz 31.25
-
fTIMxCLK/2
16
-
0
0
MHz
MHz
bit
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 32 MHz
ResTIM
Timer resolution
-
-
16
16-bit counter clock
period when internal clock
is selected (timer’s
1
65536
tTIMxCLK
tCOUNTER
fTIMxCLK = 32 MHz 0.0312
2048
µs
prescaler disabled)
-
-
-
65536 × 65536 tTIMxCLK
tMAX_COUNT Maximum possible count
fTIMxCLK = 32 MHz
134.2
s
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
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109
Electrical characteristics
STM32L151xC STM32L152xC
6.3.16
Communications interfaces
I2C interface characteristics
2
2
I
The device C interface meets the requirements of the standard I C communication
protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins.
When configured as open-drain, the PMOS connected between the I/O pin and V is
DD
disabled, but is still present.
2
The I C characteristics are described in Table 48. Refer also to Section 6.3.13: I/O port
for more details on the input/output ction characteristics (SDA and SCL)
characteristics
.
2
Table 48. I C characteristics
Standard mode
Fast mode I2C(1)(2)
I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
250
-
-
1.3
0.6
100
-
-
µs
-
-
-
-
SDA data hold time
3450(3)
900(3)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
-
300
-
300
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
µs
Repeated Start condition
setup time
tsu(STO)
Stop condition setup time
μs
μs
Stop to Start condition time
(bus free)
tw(STO:STA)
Capacitive load for each bus
line
Cb
-
400
-
400
pF
ns
Pulse width of spikes that
are suppressed by the
analog filter
tSP
0
50(4)
0
50(4)
Guaranteed by design.
1.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
3.
4. The minimum width of the spikes filtered by the analog filter is above tSP(max)
.
90/136
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STM32L151xC STM32L152xC
Electrical characteristics
2
Figure 21. I C bus AC waveforms and measurement circuit
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1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
4.
(1)(2)
Table 49. SCL frequency (f
fSCL (kHz)
= 32 MHz, VDD = VDD_I2C = 3.3 V)
I2C_CCR value
PCLK1
RP = 4.7 kΩ
400
300
200
100
50
0x801B
0x8024
0x8035
0x00A0
0x0140
0x0320
20
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external
components used to design the application.
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109
Electrical characteristics
STM32L151xC STM32L152xC
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the conditions summarized in Table 14.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
(1)
Table 50. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max(2)
Unit
-
-
-
16
16
fSCK
1/tc(SCK)
SPI clock frequency
Slave mode
MHz
Slave transmitter
12(3)
(2)
tr(SCK)
tf(SCK)
SPI clock rise and fall time
Capacitive load: C = 30 pF
-
6
ns
%
(2)
DuCy(SCK)
tsu(NSS)
SPI slave input clock duty cycle Slave mode
30
70
-
NSS setup time
NSS hold time
Slave mode
Slave mode
4tHCLK
2tHCLK
th(NSS)
-
(2)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2−5 tSCK/2+3
(2)
(2)
tsu(MI)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
5
6
5
5
-
(2)
tsu(SI)
-
(2)
th(MI)
-
ns
Data input hold time
(2)
th(SI)
-
(4)
ta(SO)
Data output access time
Data output valid time
Data output valid time
0
3tHCLK
(2)
tv(SO)
-
33
6.5
-
(2)
tv(MO)
-
(2)
th(SO)
17
0.5
Data output hold time
(2)
th(MO)
-
1. The characteristics above are given for voltage range 1.
2. Guaranteed by characterization results.
3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK))
ranging between 40 to 60%.
4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
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Electrical characteristics
Figure 22. SPI timing diagram - slave mode and CPHA = 0
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Figure 23. SPI timing diagram - slave mode and CPHA = 1
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
DocID022799 Rev 12
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109
Electrical characteristics
STM32L151xC STM32L152xC
(1)
Figure 24. SPI timing diagram - master mode
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM32L151xC STM32L152xC
USB characteristics
Electrical characteristics
The USB interface is USB-IF certified (full speed).
Table 51. USB startup time
Parameter
USB transceiver startup time
Symbol
Max
Unit
(1)
tSTARTUP
1
µs
1. Guaranteed by design.
Table 52. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1) Unit
Input levels
VDD
USB operating voltage
Differential input sensitivity
-
3.0
0.2
0.8
1.3
3.6
-
V
V
(2)
VDI
I(USB_DP, USB_DM)
(2)
VCM
Differential common mode range Includes VDI range
2.5
2.0
(2)
VSE
Single ended receiver threshold
-
Output levels
(3)
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩ to 3.6 V(4)
-
0.3
3.6
V
(3)
(4)
RL of 15 kΩ to VSS
2.8
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
RL is the load connected on the USB drivers.
4.
Figure 25. USB timings: definition of data signal rise and fall time
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Table 53. USB: full speed electrical characteristics
Driver characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall Time(2)
CL = 50 pF
CL = 50 pF
4
4
20
20
ns
ns
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109
Electrical characteristics
STM32L151xC STM32L152xC
Table 53. USB: full speed electrical characteristics (continued)
Driver characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
trfm
Rise/ fall time matching
tr/tf
90
110
2.0
%
V
VCRS
Output signal crossover voltage
1.3
1. Guaranteed by design.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
I2S characteristics
Table 54. I2S characteristics
Conditions
Symbol
Parameter
I2S Main Clock Output
Min
Max
Unit
fMCK
256 x 8K 256xFs (1) MHz
Master data: 32 bits
Slave data: 32 bits
-
-
64xFs
fCK
I2S clock frequency
MHz
%
64xFs
DCK
tr(CK)
tf(CK)
tv(WS)
th(WS)
I2S clock frequency duty cycle Slave receiver, 48KHz
30
70
8
8
24
-
I2S clock rise time
Capacitive load CL=30pF
I2S clock fall time
-
WS valid time
WS hold time
Master mode
Master mode
Slave mode
4
0
tsu(WS) WS setup time
th(WS) WS hold time
15
0
-
Slave mode
-
tsu(SD_MR) Data input setup time
tsu(SD_SR) Data input setup time
Master receiver
Slave receiver
Master receiver
Slave receiver
8
-
9
-
ns
th(SD_MR)
Data input hold time
th(SD_SR)
5
-
4
-
Slave transmitter
(after enable edge)
tv(SD_ST) Data output valid time
th(SD_ST) Data output hold time
tv(SD_MT) Data output valid time
-
22
-
64
-
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
12
-
Master transmitter
(after enable edge)
th(SD_MT) Data output hold time
1. The maximum for 256xFs is 8 MHz
8
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), f , f and D values. These values reflect only the digital peripheral
MCK CK
CK
behavior, source clock precision might slightly change them. DCK depends mainly on the
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Electrical characteristics
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
2
(1)
Figure 26. I S slave timing diagram (Philips protocol)
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1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 27. I S master timing diagram (Philips protocol)
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1. Guaranteed by characterization results.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DocID022799 Rev 12
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109
Electrical characteristics
STM32L151xC STM32L152xC
6.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 56 are guaranteed by design.
Table 55. ADC clock frequency
Symbol Parameter
Conditions
Min
Max
Unit
VREF+ = VDDA
16
VREF+ < VDDA
8
4
2.4 V ≤VDDA ≤3.6 V
VREF+ > 2.4 V
Voltage
range 1 & 2
VREF+ < VDDA
VREF+ ≤2.4 V
ADC clock
fADC
0.480
MHz
frequency
V
REF+ = VDDA
8
4
4
1.8 V ≤VDDA ≤2.4 V
VREF+ < VDDA
Voltage range 3
Table 56. ADC characteristics
Conditions
Symbol
Parameter
Power supply
Min
Typ
Max
Unit
VDDA
-
1.8
-
3.6
VDDA
-
VREF+ Positive reference voltage
VREF- Negative reference voltage
IVDDA Current on the VDDA input pin
-
1.8(1)
-
V
-
-
VSSA
1000
-
-
1450
700
450
VREF+
1
µA
Peak
-
(2)
IVREF
Current on the VREF input pin
Conversion voltage range(3)
12-bit sampling rate
400
Average
-
VAIN
-
0(4)
-
-
-
-
-
-
-
-
-
V
Direct channels
Multiplexed channels
Direct channels
Multiplexed channels
Direct channels
Multiplexed channels
Direct channels
Multiplexed channels
-
-
-
-
-
-
-
-
Msps
0.76
1.07
0.8
10-bit sampling rate
8-bit sampling rate
6-bit sampling rate
Msps
Msps
Msps
fS
1.23
0.89
1.45
1
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STM32L151xC STM32L152xC
Electrical characteristics
Table 56. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Direct channels
2.4 V ≤VDDA ≤3.6 V
0.25
-
-
Multiplexed channels
2.4 V ≤VDDA ≤3.6 V
0.56
0.56
1
-
-
-
-
-
-
µs
(5)
tS
Sampling time
Direct channels
1.8 V ≤VDDA ≤2.4 V
Multiplexed channels
1.8 V ≤VDDA ≤2.4 V
-
4
1
-
-
384
1/fADC
µs
f
ADC = 16 MHz
24.75
Total conversion time
tCONV
4 to 384 (sampling phase) +12
(successive approximation)
(including sampling time)
-
1/fADC
Direct channels
Multiplexed channels
12-bit conversions
6/8/10-bit conversions
12-bit conversions
6/8/10-bit conversions
-
-
-
Internal sample and hold
capacitor
CADC
fTRIG
fTRIG
16
pF
-
-
-
-
-
-
-
-
-
-
-
-
Tconv+1 1/fADC
Tconv 1/fADC
Tconv+2 1/fADC
Tconv+1 1/fADC
External trigger frequency
Regular sequencer
-
-
External trigger frequency
Injected sequencer
-
(6)
RAIN
Signal source impedance
-
50
281
4.5
219
3.5
3.5
kΩ
ns
fADC = 16 MHz
219
3.5
156
2.5
-
Injection trigger conversion
latency
tlat
-
1/fADC
ns
fADC = 16 MHz
Regular trigger conversion
latency
tlatr
-
-
1/fADC
µs
tSTAB
Power-up time
1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage
reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pin descriptions for further details.
4. VSSA or VREF- must be tied to ground.
5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 58: Maximum
source impedance RAIN max.
6. External impedance has another high value limitation when using short sampling time as defined in Table 58: Maximum
source impedance RAIN max.
DocID022799 Rev 12
99/136
109
Electrical characteristics
STM32L151xC STM32L152xC
(1)(2)
Table 57. ADC accuracy
Test conditions
Symbol
Parameter
Min(3)
Typ Max(3) Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
-
2
1
4
2
-
-
2.4 V ≤VDDA ≤ 3.6 V
2.4 V ≤VREF+ ≤ 3.6 V
fADC = 8 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Gain error
1.5
1
3.5
2
LSB
Differential linearity error
Integral linearity error
-
-
1.7
10
3
ENOB Effective number of bits
9.2
-
bits
dB
2.4 V ≤VDDA ≤ 3.6 V
VDDA = VREF+
fADC = 16 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Finput=10kHz
Signal-to-noise and
SINAD
57.5
62
-
distortion ratio
SNR
THD
Signal-to-noise ratio
57.5
-
62
-70
10
-
-65
-
Total harmonic distortion
ENOB Effective number of bits
9.2
bits
dB
1.8 V ≤VDDA ≤ 2.4 V
VDDA = VREF+
fADC = 8 MHz or 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Finput=10kHz
Signal-to-noise and
SINAD
57.5
62
-
distortion ratio
SNR
THD
ET
Signal-to-noise ratio
Total harmonic distortion
Total unadjusted error
Offset error
57.5
62
-70
4
-
-65
6.5
4
-
-
-
-
-
-
-
-
-
-
-
EO
EG
ED
EL
2
2.4 V ≤VDDA ≤ 3.6 V
1.8 V ≤VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Gain error
4
6
LSB
LSB
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
1
2
1.5
2
3
ET
3
EO
EG
ED
EL
1
1.5
2
1.8 V ≤VDDA ≤ 2.4 V
1.8 V ≤VREF+ ≤ 2.4 V
Gain error
1.5
1
f
ADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Differential linearity error
Integral linearity error
2
1
1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as
this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to
add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Guaranteed by characterization results.
100/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Electrical characteristics
Figure 28. ADC accuracy characteristics
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Figure 29. Typical connection diagram using the ADC
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1. Refer to Table 58: Maximum source impedance RAIN max for the value of RAIN and Table 56: ADC
characteristics for the value of CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
DocID022799 Rev 12
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109
Electrical characteristics
STM32L151xC STM32L152xC
Figure 30. Maximum dynamic current consumption on V
supply pin during ADC
REF+
conversion
Sampling (n cycles)
Conversion (12 cycles)
ADC clock
I
ref+
700µA
300µA
MS36686V1
(1)
Table 58. Maximum source impedance R
max
AIN
RAIN max (kΩ)
Ts (cycles)
ADC=16 MHz(2)
Ts
(µs)
Multiplexed channels
Direct channels
f
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V
0.25
Not allowed
0.8
Not allowed
Not allowed
0.8
0.7
2.0
Not allowed
1.0
4
9
0.5625
1
1.5
3
2.0
4.0
3.0
16
24
48
96
192
384
3.0
1.8
6.0
4.5
6.8
4.0
15.0
30.0
50.0
50.0
10.0
6
15.0
32.0
50.0
10.0
20.0
12
24
25.0
40.0
50.0
50.0
1. Guaranteed by design.
2. Number of samples calculated for fADC = 16 MHz. For fADC = 8 and 4 MHz the number of sampling cycles can be reduced
with respect to the minimum sampling time Ts (µs),
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 12. The applicable
procedure depends on whether V
is connected to V
or not. The 100 nF capacitors
REF+
DDA
should be ceramic (good quality). They should be placed as close as possible to the chip.
102/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Electrical characteristics
6.3.18
DAC electrical specifications
Data guaranteed by design, unless otherwise specified.
Table 59. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
1.8
-
3.6
Reference supply
voltage
VREF+ must always be below
VDDA
V
VREF+
VREF-
1.8
-
3.6
Lower reference voltage
-
VSSA
Current consumption on No load, middle code (0x800)
VREF+ supply
-
-
-
-
130
220
210
320
220
350
320
520
(1)
IDDVREF+
No load, worst code (0x000)
VREF+ = 3.3 V
µA
Current consumption on No load, middle code (0x800)
VDDA supply
No load, worst code (0xF1C)
VDDA = 3.3 V
(1)
IDDA
(2)
RL
Resistive load
5
-
-
-
-
kΩ
pF
kΩ
DAC output buffer ON
Capacitive load
(2)
CL
50
20
RO
Output impedance
DAC output buffer OFF
12
16
DAC output buffer ON
0.2
-
VDDA – 0.2
V
Voltage on DAC_OUT
output
VDAC_OUT
VREF+
1LSB
–
DAC output buffer OFF
0.5
-
-
mV
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
1.5
3
Differential non
linearity(3)
DNL(1)
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
-
-
-
-
-
1.5
2
3
4
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
INL(1)
Integral non linearity(4)
No RL, CL ≤ 50 pF
DAC output buffer OFF
LSB
2
4
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
±10
±5
±25
±8
±5
Offset error at code
0x800 (5)
Offset(1)
No RL, CL ≤ 50 pF
DAC output buffer OFF
Offset error at code
0x001(6)
No RL, CL ≤ 50 pF
DAC output buffer OFF
Offset1(1)
±1.5
DocID022799 Rev 12
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109
Electrical characteristics
STM32L151xC STM32L152xC
Table 59. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA = 3.3V
VREF+ = 3.0V
-20
-10
0
TA = 0 to 50 ° C
DAC output buffer OFF
Offset error temperature
coefficient (code 0x800)
dOffset/dT(1)
µV/°C
VDDA = 3.3V
VREF+ = 3.0V
0
20
50
TA = 0 to 50 ° C
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
+0.1 / -0.2% +0.2 / -0.5%
DAC output buffer ON
Gain(1)
Gain error(7)
%
No RL, CL ≤ 50 pF
DAC output buffer OFF
+0 / -0.2%
-2
+0 / -0.4%
0
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer OFF
-10
-40
Gain error temperature
coefficient
dGain/dT(1)
µV/°C
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer ON
-8
0
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
12
8
30
12
DAC output buffer ON
TUE(1)
Total unadjusted error
LSB
No RL, CL ≤ 50 pF
DAC output buffer OFF
Settling time (full scale:
for a 12-bit code
transition between the
lowest and the highest
input codes till
DAC_OUT reaches final
value ±1LSB
tSETTLING
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
7
12
µs
Max frequency for a
correct DAC_OUT
change (95% of final
value) with 1 LSB
variation in the input
code
Update rate
CL ≤ 50 pF, RL ≥ 5 kΩ
-
1
Msps
Wakeup time from off
state (setting the ENx bit
in the DAC Control
register)(8)
tWAKEUP
CL ≤ 50 pF, RL ≥ 5 kΩ
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
9
15
µs
VDDA supply rejection
ratio (static DC
measurement)
PSRR+
-60
-35
dB
1. Data based on characterization results.
2. Connected between DAC_OUT and V
.
SSA
3. Difference between two consecutive codes - 1 LSB.
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STM32L151xC STM32L152xC
Electrical characteristics
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (V
– 0.2) V when buffer is ON.
DDA
8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 31. 12-bit buffered /non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.19
Operational amplifier characteristics
Table 60. Operational amplifier characteristics
Symbol
Parameter
Condition(1)
Min(2)
Typ
Max(2)
Unit
CMIR
Common mode input range
-
0
-
VDD
Maximum
calibration range
-
-
-
-
-
-
15
VIOFFSET
Input offset voltage
mV
After offset
calibration
1.5
Normal mode
-
-
-
-
-
-
-
-
40
80
1
µV/°C
Input offset voltage
drift
ΔVIOFFSET
Low-power mode
Dedicated input
IIB
Input current bias
75 °C
nA
General purpose
input
-
-
10
Normal mode
-
-
-
-
-
-
-
-
-
500
100
220
60
-
ILOAD
Drive current
Consumption
µA
µA
dB
Low-power mode
Normal mode
-
100
30
-85
-90
No load,
IDD
quiescent mode
Low-power mode
Normal mode
-
-
Common mode
rejection ration
CMRR
Low-power mode
-
DocID022799 Rev 12
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109
Electrical characteristics
STM32L151xC STM32L152xC
Table 60. Operational amplifier characteristics (continued)
Symbol
Parameter
Normal mode
Condition(1)
Min(2)
Typ
Max(2)
Unit
-
-85
-90
-
Power supply
rejection ratio
PSRR
DC
dB
Low-power mode
Normal mode
-
-
400
150
200
70
1000
300
500
150
3000
800
2200
800
VDD>2.4 V
Low-power mode
Normal mode
GBW
Bandwidth
kHZ
V
DD<2.4 V
Low-power mode
VDD>2.4 V
Normal mode
(between 0.1 V and
VDD-0.1 V)
-
700
-
SR
AO
Slew rate
V/ms
dB
Low-power mode
Normal mode
V
DD>2.4 V
-
-
100
300
50
100
110
-
-
-
V
DD<2.4 V
Low-power mode
Normal mode
-
-
55
65
4
-
Open loop gain
Low-power mode
Normal mode
-
-
RL
CL
Resistive load
Capacitive load
VDD<2.4 V
kΩ
Low-power mode
20
-
-
-
-
-
50
pF
VDD
100
-
Normal mode
-
-
High saturation
voltage
VOHSAT
VOLSAT
ILOAD = max or
RL = min
Low-power mode
Normal mode
VDD-50
-
-
-
100
50
-
mV
-
-
-
-
Low saturation
voltage
Low-power mode
-
ϕm
Phase margin
Gain margin
-
-
60
-12
°
GM
-
dB
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
tOFFTRIM
-
-
1
-
ms
µs
CL ≤50 pf,
RL ≥ 4 kΩ
Normal mode
Wakeup time
-
-
10
30
-
-
tWAKEUP
CL ≤50 pf,
Low-power mode
RL ≥ 20 kΩ
1. Operating conditions are limited to junction temperature (0 °C to 105 °C) when VDD is below 2 V. Otherwise to the full
ambient temperature range (-40 °C to 85 °C, -40 °C to 105 °C).
2. Guaranteed by characterization results.
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Electrical characteristics
6.3.20
Temperature sensor characteristics
Table 61. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
temperature of 30 °C 5 °C
TS_CAL1
0x1FF8 00FA - 0x1FF8 00FB
VDDA= 3 V 10 mV
TS ADC raw data acquired at
temperature of 110 °C 5 °C
TS_CAL2
0x1FF8 00FE - 0x1FF8 00FF
VDDA= 3 V 10 mV
Table 62. Temperature sensor characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
-
1.48
612
-
1
1.61
626.8
3.4
2
1.75
641.5
6
°C
mV/°C
mV
Avg_Slope(1) Average slope
V110
Voltage at 110°C ±5°C(2)
IDDA
(3)
Current consumption
Startup time
µA
(TEMP)
(3)
tSTART
-
-
10
µs
ADC sampling time when reading the
temperature
(3)
TS_temp
4
-
-
1. Guaranteed by characterization results.
2. Measured at VDD = 3 V ±10 mV. V110 ADC conversion result is stored in the TS_CAL2 byte.
3. Guaranteed by design.
6.3.21
Comparator
Table 63. Comparator 1 characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
VDDA
R400K
R10K
Analog supply voltage
R400K value
-
-
-
1.65
3.6
V
-
-
400
10
-
-
kΩ
R10K value
Comparator 1 input
voltage range
VIN
-
0.6
-
VDDA
V
tSTART
td
Comparator startup time
Propagation delay(2)
Comparator offset
-
-
-
-
-
-
7
3
3
10
10
10
µs
Voffset
mV
VDDA = 3.6 V
VIN+ = 0 V
VIN- = VREFINT
TA = 25 °C
Comparator offset
dVoffset/dt variation in worst voltage
stress conditions
0
-
1.5
10
mV/1000 h
nA
ICOMP1
Current consumption(3)
-
160
260
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109
Electrical characteristics
STM32L151xC STM32L152xC
1. Guaranteed by characterization results.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
Table 64. Comparator 2 characteristics
Symbol
Parameter
Conditions
Min Typ Max(1) Unit
VDDA
VIN
Analog supply voltage
-
-
1.65
-
3.6
VDDA
20
25
3.5
6
V
V
Comparator 2 input voltage range
0
-
-
-
-
-
-
-
-
Fast mode
15
20
1.8
2.5
0.8
1.2
4
tSTART
Comparator startup time
Slow mode
1.65 V ≤VDDA ≤2.7 V
2.7 V ≤VDDA ≤3.6 V
1.65 V ≤VDDA ≤2.7 V
2.7 V ≤VDDA ≤3.6 V
td slow
Propagation delay(2) in slow mode
µs
2
td fast
Propagation delay(2) in fast mode
Comparator offset error
4
Voffset
20
mV
VDDA = 3.3V
TA = 0 to 50 °C
dThreshold/ Threshold voltage temperature
V- =VREFINT
3/4 VREFINT
1/2 VREFINT
1/4 VREFINT
,
ppm
/°C
-
15
100
dt
coefficient
,
,
.
Fast mode
Slow mode
-
-
3.5
0.5
5
2
ICOMP2
Current consumption(3)
µA
1. Guaranteed by characterization results.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
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STM32L151xC STM32L152xC
Electrical characteristics
6.3.22
LCD controller
The device embeds a built-in step-up converter to provide a constant LCD reference voltage
independently from the V voltage. An external capacitor C must be connected to the
DD
ext
V
pin to decouple this converter.
LCD
Table 65. LCD controller characteristics
Symbol
Parameter
LCD external voltage
Min
Typ
Max
Unit
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
VLCD6
VLCD7
Cext
-
-
2.6
3.6
LCD internal reference voltage 0
LCD internal reference voltage 1
LCD internal reference voltage 2
LCD internal reference voltage 3
LCD internal reference voltage 4
LCD internal reference voltage 5
LCD internal reference voltage 6
LCD internal reference voltage 7
VLCD external capacitance
-
-
-
2.73
2.86
2.98
3.12
3.26
3.4
-
-
-
-
-
V
-
-
-
-
-
-
-
3.55
-
-
0.1
2
µF
µA
Supply current at VDD = 2.2 V
-
3.3
-
(1)
ILCD
Supply current at VDD = 3.0 V
-
3.1
-
(2)
RHtot
Low drive resistive network overall value
High drive resistive network total value
Segment/Common highest level voltage
Segment/Common 3/4 level voltage
Segment/Common 2/3 level voltage
Segment/Common 1/2 level voltage
Segment/Common 1/3 level voltage
Segment/Common 1/4 level voltage
Segment/Common lowest level voltage
5.28
6.6
7.92
MΩ
kΩ
V
(2)
RL
192
240
288
V44
V34
V23
V12
V13
V14
V0
-
-
-
VLCD
3/4 VLCD
2/3 VLCD
1/2 VLCD
1/3 VLCD
1/4 VLCD
-
-
-
-
-
-
-
-
-
V
-
-
0
Segment/Common level voltage error
ΔVxx(3)
-
-
50
mV
TA = -40 to 105 °C
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD
connected.
2. Guaranteed by design.
3. Guaranteed by characterization results.
DocID022799 Rev 12
109/136
109
Package information
STM32L151xC STM32L152xC
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
7.1
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
information
Figure 32. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline
3%!4).' 0,!.%
#
ꢏꢉꢇꢂ MM
'!5'% 0,!.%
CCC
ꢎꢂ
#
$
,
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,ꢀ
ꢂꢀ
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ꢇꢆ
0). ꢀ
)$%.4)&)#!4)/.
ꢇꢂ
ꢀ
E
ꢀ,?-%?6ꢂ
1. Drawing is not to scale.
Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical
data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
-
-
-
1.600
0.150
1.450
-
-
0.0630
0.0059
0.0571
A1
A2
0.050
1.350
0.0020
0.0531
-
1.400
0.0551
110/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
Table 66. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical
data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
b
c
0.170
0.220
-
0.270
0.200
16.200
14.200
-
0.0067
0.0087
-
0.0106
0.0079
0.6378
0.5591
-
0.090
0.0035
D
15.800
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
0.6220
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
13.800
0.5433
-
-
15.800
16.200
14.200
-
0.6220
0.6378
0.5591
-
E1
E3
e
13.800
0.5433
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
-
0.0°
-
7.0°
7.0°
ccc
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 33. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint
ꢎꢂ
ꢂꢀ
ꢎꢆ
ꢂꢏ
ꢏꢉꢂ
ꢏꢉꢃ
ꢀꢆꢉꢎ ꢀꢅꢉꢃ
ꢀꢏꢏ
ꢇꢆ
ꢀꢉꢇ
ꢀ
ꢇꢂ
ꢀꢇꢉꢃ
ꢀꢆꢉꢎ
06ꢀꢁꢂꢃꢒ9ꢂ
1. Dimensions are in millimeters.
DocID022799 Rev 12
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135
Package information
STM32L151xC STM32L152xC
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 34. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view
example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
112/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
7.2
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
information
Figure 35. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline
6($7,1*ꢅ3/$1(
&
ꢉꢄꢆꢏꢅPP
*$8*(ꢅ3/$1(
FFF
&
'
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ꢀꢀ
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ꢀꢆ
ꢁꢒ
ꢌꢁ
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ꢂꢌ
ꢂ
3,1ꢅꢂ
H
,'(17,),&$7,21
ꢏ:B0(B9ꢀ
1. Drawing is not to scale.
Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical
data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
-
-
-
-
12.000
10.000
7.500
12.000
10.000
-
-
-
-
-
-
-
-
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
-
-
-
-
-
D1
D3
E
E1
DocID022799 Rev 12
113/136
135
Package information
STM32L151xC STM32L152xC
Table 67. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data
(continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E3
e
-
7.500
0.500
3.5°
-
-
0.2953
0.0197
3.5°
-
-
-
7°
-
-
7°
K
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
recommended footprint
ꢅꢁ
ꢃꢃ
ꢏꢉꢃ
ꢏꢉꢂ
ꢅꢌ
ꢃꢇ
ꢀꢇꢉꢎ
ꢀꢏꢉꢃ
ꢀꢏꢉꢃ
ꢎꢉꢁ
ꢀꢎ
ꢆꢅ
ꢀꢉꢇ
ꢀꢆ
ꢀ
ꢀꢇꢉꢎ
AIꢀꢅꢌꢏꢌC
1. Dimensions are in millimeters.
114/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 37. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
DocID022799 Rev 12
115/136
135
Package information
STM32L151xC STM32L152xC
7.3
LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package
information
Figure 38. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢏꢉꢇꢂ MM
'!5'% 0,!.%
CCC
#
$
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E
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1. Drawing is not to scale.
116/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
Table 68. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 39. LQFP48 recommended footprint
ꢏꢉꢂꢏ
ꢀꢉꢇꢏ
ꢏꢉꢃꢏ
ꢃꢆ
ꢇꢂ
ꢃꢎ
ꢇꢅ
ꢏꢉꢇꢏ
ꢎꢉꢃꢏ
ꢌꢉꢎꢏ ꢂꢉꢁꢏ
ꢎꢉꢃꢏ
ꢅꢁ
ꢀꢃ
ꢀꢇ
ꢀ
ꢀꢉꢇꢏ
ꢂꢉꢁꢏ
ꢌꢉꢎꢏ
AIꢀꢅꢌꢀꢀD
1. Dimensions are in millimeters.
DocID022799 Rev 12
117/136
135
Package information
STM32L151xC STM32L152xC
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 40. LQFP48 package top view example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
118/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
7.4
UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information
Figure 41. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline
3LQꢅꢂꢅLGHQWLILHU
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SLQꢂꢅFRUQHU
5ꢅꢉꢄꢂꢆꢏꢅW\Sꢄ
'HWDLOꢅ=
(ꢆ
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ꢁꢋ
=
$ꢉ%ꢒB0(B9ꢀ
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DocID022799 Rev 12
119/136
135
Package information
STM32L151xC STM32L152xC
Table 69. UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm,
0.5 mm pitch package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. UFQFPN48 recommended footprint
ꢎꢉꢃꢏ
ꢆꢉꢇꢏ
ꢅꢁ
ꢃꢎ
ꢀ
ꢃꢆ
ꢂꢉꢆꢏ
ꢏꢉꢇꢏ
ꢎꢉꢃꢏ
ꢂꢉꢁꢏ
ꢆꢉꢇꢏ
ꢂꢉꢆꢏ
ꢏꢉꢃꢏ
ꢀꢇ
ꢇꢂ
ꢀꢃ
ꢇꢅ
ꢏꢉꢎꢂ
ꢏꢉꢂꢏ
ꢏꢉꢂꢂ
ꢂꢉꢁꢏ
!ꢏ"ꢌ?&0?6ꢇ
1. Dimensions are in millimeters.
120/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 43. UFQFPN48 package top view example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
DocID022799 Rev 12
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135
Package information
STM32L151xC STM32L152xC
7.5
UFBGA100, 7 x 7 mm, 100-ball ultra thin, fine pitch ball grid
array package information
Figure 44. UFBGA100, 7 x 7 mm, 0.5 mm pitch package outline
=
6HDWLQJꢅSODQH
GGG =
$ꢁ
$ꢀ $ꢆ
$ꢂ
$
(ꢂ
;
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HHH 0 = < ;
III 0 =
%27720ꢅ9,(:
723ꢅ9,(:
$ꢉ&ꢆB0(B9ꢁ
1. Drawing is not to scale.
Table 70. UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
A4
b
0.460
0.050
0.400
0.080
0.270
0.200
6.950
5.450
6.950
5.450
-
0.530
0.080
0.450
0.130
0.320
0.250
7.000
5.500
7.000
5.500
0.500
0.750
-
0.600
0.110
0.500
0.180
0.370
0.300
7.050
5.550
7.050
5.550
-
0.0181
0.0020
0.0157
0.0031
0.0106
0.0079
0.2736
0.2146
0.2736
0.2146
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0098
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
-
0.0236
0.0043
0.0197
0.0071
0.0146
0.0118
0.2776
0.2185
0.2776
0.2185
-
D
D1
E
E1
e
F
0.700
-
0.800
0.100
0.0276
-
0.0315
0.0039
ddd
122/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
Table 70. UFBGA100, 7 x 7 mm, 0.5 mm pitch package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
eee
fff
-
-
-
-
0.150
0.050
-
-
-
-
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 45. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package recommended footprint
'SDG
'VP
$ꢉ&ꢆB)3B9ꢂ
Table 71. UFBGA100, 7 x 7 mm, 0.50 mm pitch, recommended PCB design rules
Dimension Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.280 mm
Between 0.100 mm and 0.125 mm
DocID022799 Rev 12
123/136
135
Package information
STM32L151xC STM32L152xC
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 46. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package top view example
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06ꢀꢃꢏꢉꢒ9ꢂ
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
124/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
7.6
WLCSP63, 0.400 mm pitch wafer level chip size package
information
Figure 47. WLCSP63, 0.400 mm pitch wafer level chip size package outline
Hꢂ
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$ꢉ7*B0(B9ꢆ
1. Drawing is not to scale.
DocID022799 Rev 12
125/136
135
Package information
STM32L151xC STM32L152xC
Table 72. WLCSP63, 0.400 mm pitch wafer level chip size package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
Øb
D
0.540
0.570
0.190
0.380
0.025
0.270
3.228
4.164
0.400
2.400
3.200
0.414
0.482
-
0.600
0.0213
0.0224
0.0075
0.0150
0.0010
0.0106
0.1271
0.1639
0.0157
0.0945
0.1260
0.0163
0.0190
-
0.0236
-
-
-
-
-
-
-
-
-
-
-
-
0.240
0.300
3.263
4.199
-
0.0094
0.0118
0.1285
0.1653
-
3.193
0.1257
E
4.129
0.1626
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
F
-
-
-
-
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.100
0.100
0.100
0.050
0.050
-
-
-
-
-
0.0039
0.0039
0.0039
0.0020
0.0020
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM32L151xC STM32L152xC
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 48. WLCSP63 device marking example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
DocID022799 Rev 12
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135
Package information
STM32L151xC STM32L152xC
7.7
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in ° C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 73. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
UFBGA100 - 7 x 7 mm
59
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
43
46
49
55
33
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
Θ
°C/W
JA
Thermal resistance junction-ambient
WLCSP63 - 0.400 mm pitch
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFQFPN48 - 7 x 7 mm / 0.5 mm pitch
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DocID022799 Rev 12
STM32L151xC STM32L152xC
Package information
Figure 49. Thermal resistance suffix 6
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Figure 50. Thermal resistance suffix 7
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7.7.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID022799 Rev 12
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135
Part numbering
STM32L151xC STM32L152xC
8
Part numbering
Table 74. STM32L151xC and STM32L152xC ordering information scheme
Example:
STM32 L 151 R
C
T
6
D
TR
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
L = Low-power
Device subfamily
151: Devices without LCD
152: Devices with LCD
Pin count
C = 48 pins
U = 63 pins
R = 64 pins
V = 100 pins
Flash memory size
C = 256 Kbytes of Flash memory
Package
H = BGA
T = LQFP
Y = WLCSP
U = UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = V range: 1.65 to 3.6 V and BOR disabled
DD
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact the nearest ST sales office.
130/136
DocID022799 Rev 12
STM32L151xC STM32L152xC
Revision History
9
Revision History
Table 75. Document revision history
Changes
Date
Revision
21-Feb-2012
1
Initial release.
Added WLCSP63 package.
Updated Figure 1: Ultra-low-power STM32L162xC block diagram.
Changed maximum number of touch sensing channels to 34, and
updated Table 2: Ultralow power STM32L15xxC device features and
peripheral counts.
Added Table 4: Functionalities depending on the working mode (from
Run/active down to standby), and Table 3: ange depending on
dynamic voltage scaling.
Updated Section 3.10: ADC (analog-to-digital converter) to add
Section 3.10.1: Temperature sensor and Section 3.10.2: Internal
voltage reference (VREFINT).
Updated Figure 3: STM32L162VC LQFP100 pinout.
Table 10: STM32L15xxC pin definitions: updated name of reference
manual in footnote 5.
Changed I2C1_SMBAI into I2C1_SMBA in Table 10: STM32L15xxC
pin definitions.
Modified PB10/11/12 for AFIO4 alternate function, and replaced LBAR
by NADV for AFIO12 in Table 10: Alternate function input/output.
12-Oct-2012
2
Removed caution note below Figure 8: Power supply scheme.
Added Note 2 in Table 15: Embedded reset and power control block
characteristics.
Updated Table 14: General operating conditions.
Updated Table 22: Typical and maximum current consumptions in Stop
mode and added Note 6. Updated Table 23: Typical and maximum
current consumptions in Standby mode. Updated tWUSTOP in Table : .
Updated Table 26: Peripheral current consumption.
Updated Table 60: SPI characteristics, added Note 1 and Note 3, and
applied Note 2 to tr(SCK), tf(SCK), tw(SCKH), tw(SCKL), tsu(MI), tsu(SI), th(MI)
and th(SI)
Added Table 61: I2S characteristics, Figure 29: I2S slave timing
,
.
diagram (Philips protocol)(1) and Figure 30: I2S master timing diagram
(Philips protocol)(1).
Updated Table 72: Temperature sensor characteristics.
Added Figure 40: Thermal resistance.
DocID022799 Rev 12
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135
Revision History
STM32L151xC STM32L152xC
Table 75. Document revision history (continued)
Date
Revision
Changes
Removed AHB1/AHB2 and corrected typo on APB1/APB2 in:Figure 1:
Ultra-low-power STM32L162xC block diagram-low-power
STM32L162xC block diagram
Updated “OP amp” line in Table 4: Functionalities depending on the
working mode (from Run/active down to standby)
Added IWDG and WWDG rows in Table 4: Functionalities depending
on the working mode (from Run/active down to standby)
Updated address range in Table 7: Internal voltage reference
measured values
The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz)"
replaced by "fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2
above 16 MHz (PLL ON)(2)” in table Table 27: Current consumption in
Sleep mode
01-Feb-2013
3
replaced pin names D7,C7,C6,C8,B8,A8 respectively by
D11,D10,C12,B12,A12,A11 in column UFBGA100 of Table 9:
STM32L15xxC pin definitionsAdded more alternate functions
supported on pin K3 and M4 for UFBGA100 package in Table 9:
STM32L15xxC pin definitions
Added part number STM32L151CC in Table 1: Device summary
Updated Stop mode current to 1.5 µA in Ultra-low-power platform
Updated entire Section 7: Package information
Removed UFBGA132 and LQFP144 packages
Removed first sentence in Section : I2C interface characteristics
Added Section Table 5.: VLCD rail decoupling
Added VRAIL functions in Table 9: STM32L15xxC pin definitions
Updated PH0-OSC_IN and PH1-OSC_OUT type in Table 9:
STM32L15xxC pin definitions.
Added Table 6.1.7: Optional LCD power supply scheme.
Updated consumption data in Table 6.3.4: Supply current
characteristics
Updated Table 7: Pin loading conditions
Updated Table 8: Pin input voltage Updated Table 15: Typical
application with a 32.768 kHz crystal
02-Sep-2013
4
Updated Table 25: Recommended NRST pin protection
Table 26: I2C bus AC waveforms and measurement circuitUpdated
Table 35: Typical connection diagram using the ADC and
definition of symbol “RAIN” in Table 77: ADC characteristics
Updated dThreshold/dt conditions in Table 85: Comparator 2
characteristics.
Updated Table 49: Thermal resistance suffix 6.
Added D2 and E2 in Table 69: UFQFPN48 – ultra thin fine pitch quad
flat pack no-lead 7 × 7 mm, 0.5 mm pitch package mechanical data
Fixed columns inversion in Table 67: LQFP64, 10 x 10 mm 64-pin low-
profile quad flat package mechanical data and Table 70: UFBGA100, 7
x 7 mm, 0.5 mm pitch package mechanical data
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STM32L151xC STM32L152xC
Revision History
Table 75. Document revision history (continued)
Revision Changes
Date
Updated Section 3.15: Touch sensing.
Added VDD= 1.71 to 1.8 V operating power supply range in Table 4:
Functionalities depending on the working mode (from Run/active down
to standby)
Renamed "I/O Level" to "I/O structure" in Table 9: STM32L15xxC pin
definitions, added the I/O structure for PC14, PC15, PC3, PH0, PH1,
PA3, PA4, PA5, PB0, PE7, PE8, PE9, PE10, NRST and BOOT0
Updated Table 10: Voltage characteristics added row
Updated Table 11: Current characteristics replaced with the one inside
STM32L15xxBxxA datasheet.
Updated Table 13: General operating conditions, footnote and added
row.
Updated Table 15: Embedded internal reference voltage calibration
values and moved inside Section 6.3.3: Embedded internal reference
voltage
Updated Section 6.3.4: Supply current characteristics.
Updated Table 19: Current consumption in Run mode, code with data
processing running from Flash.
Updated Table 22: Current consumption in Run mode, code with data
processing running from RAM.
Created Section 6.3.5: Wakeup time from low-power mode..
Updated Table 38: High-speed external user clock characteristics.
Moved Figure 12: High-speed external clock source AC timing diagram
after Table 38: High-speed external user clock characteristics.
12-Nov-2013
5
Updated Table 40: HSE oscillator characteristics.
Updated Section 6.3.12: Electrical sensitivity characteristics (title).
Updated Section 6.3.13: I/O current injection characteristics.
Updated Table 61: I/O current injection susceptibility and added
footnote.
Updated Table 63: I/O static characteristics
Updated Section 6.3.15: NRST pin characteristics.
Updated Table 77: ADC characteristics.
Added footnote(5) and (6) in Table 77: ADC characteristics
Updated THD values and added 4 more rows ENOB, SINAD, SNR,
THD in Table 78: ADC accuracy
Updated “SDA data hold time” and “SDA and SCL rise time” values
and added “Pulse width of spikes that are suppressed by the analog
filter” row in Table 68: I2C characteristics
Updated direct channels VDDA range in Table 79: RAIN max for fADC
=
16 MHz
Moved Table 82: Temperature sensor calibration values and moved
inside Section 6.3.23: Temperature sensor characteristics
Updated IDD (WU from Standby) unit in Table 31: Typical and
maximum current consumptions in Standby mode.
Updated Table 67: LQFP64, 10 x 10 mm 64-pin low-profile quad flat
package mechanical data
Updated Chapter 8: Part numbering (title).
DocID022799 Rev 12
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135
Revision History
STM32L151xC STM32L152xC
Table 75. Document revision history (continued)
Date
Revision
Changes
Apply footnote 1 also to VDD= 1.8 to 2.0 V in Table 2: Functionalities
depending on the operating power supply range.
Updated Iinj pin in Table 11: Current characteristics.
Added Input Voltage in Table 13: General operating conditions.
Updated Input leakage current conditions in Table 63: I/O static
09-Dec-2013
6
characteristics
Removed minimum value for fSin Table 77: ADC characteristics.
Removed Finput for ENOB,SINAD,SNR,THD in Table 78: ADC
accuracy.
Added tolerance for TS_CAL1 and TS_CAL2 in Table 82: Temperature
sensor calibration values.
Updated Section 3.7: Memories, Table 33: Peripheral current
consumption : updated Flash value, Table 61: I/O current injection
susceptibility, Table 63: I/O static characteristics:added BOOT0 pin
Table 66: NRST pin characteristics, Chapter 2.2: Ultra-low-power
device continuum. removed figures “Power supply and reference
decoupling (VREF+ not connected to VDDA) and “Power supply and
reference decoupling(VREF+ connected to VDDA). Updated Table 19:
Current consumption in Run mode, code with data processing running
from Flash
13-Mar-2014
7
Updated Section 6.3.1: General operating conditions.
Updated Table 80: DAC characteristics
Added marking for LQFP48/UFQFPN48 packages
Updated Table 66: NRST pin characteristics
Updated Table 63: I/O static characteristics
Updated IIO in Table 12: Current characteristics.
Updated conditions in Table 44: Output voltage characteristics.
Removed note 4 in Table 62: Temperature sensor characteristics
Updated the conditions in Table 26: Low-power mode wakeup timings.
16-May-2014
8
Removed ambiguity of “ambient temperature” in the electrical
characteristics description.
Updated Section 3.17: Communication interfaces putting I2S
characteristics inside.
Updated DMIPS features in cover page and Section 2: Description.
Updated max temperature at 105°C instead of 85°C in the whole
datasheet.
13-Oct-2014
06-Mar-2015
9
Updated current consumption in Table 20: Current consumption in
Sleep mode.
Updated Table 25: Peripheral current consumption with new measured
current values.
Updated Table 58: Maximum source impedance RAIN max adding
note 2.
Updated Section 7: Package information with new package device
marking.
10
Updated Figure 9: Memory map.
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Revision History
Table 75. Document revision history (continued)
Revision Changes
Date
Updated Table 17: Embedded internal reference voltage temperature
coefficient at 100ppm/°C and table footnote 3: “guaranteed by design”
changed by “guaranteed by characterization results”.
20-Aug-2015
11
Updated Table 64: Comparator 2 characteristics new maximum
threshold voltage temperature coefficient at 100ppm/°C.
Updated cover page putting eight SPIs in the peripheral
communication interface list.
Updated Table 2: Ultra-low-power STM32L151xC and STM32L152xC
device features and peripheral counts SPI and I2S lines.
Updated Table 40: ESD absolute maximum ratings CDM class.
Updated all the notes, removing ‘not tested in production’.
10-Mar-2016
12
Updated thermal resistance for UFQFPN48 to value of 33 °C/W.
Updated Table 11: Voltage characteristics adding note about VREF- pin.
Updated Table 5: Functionalities depending on the working mode (from
Run/active down to standby) LSI and LSE functionalities putting “Y” in
Standby mode.
Removed note 1 below Figure 2: Clock tree.
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135
STM32L151xC STM32L152xC
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
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