STM32L152x6_技术文档

STM32L151x6/8/B

STM32L152x6/8/B

Ultra-low-power 32-bit MCU ARM^®-based Cortex^®-M3,

128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC

Datasheet - production data

Features

• Ultra-low-power platform

LQFP100 14 × 14 mm UFBGA100 7 × 7 mm UFQFPN48 7 × 7 mm

– 1.65 V to 3.6 V power supply

– -40°C to 85°C/105°C temperature range

– 0.3 µA Standby mode (3 wakeup pins)

– 0.9 µA Standby mode + RTC

LQFP64 10 × 10 mm TFBGA64 5 × 5 mm

LQFP48 7 × 7 mm

– Up to 4 Kbytes of true EEPROM with ECC

– 80-byte backup register

– 0.57 µA Stop mode (16 wakeup lines)

• LCD Driver (except STM32L151x/6/8/B

– 1.2 µA Stop mode + RTC

– 9 µA Low-power run mode

– 214 µA/MHz Run mode

– 10 nA ultra-low I/O leakage

– < 8 µs wakeup time

devices) for up to 8x40 segments

– Support contrast adjustment

– Support blinking mode

– Step-up converter on board

®

• Rich analog peripherals (down to 1.8 V)

– 12-bit ADC 1 Msps up to 24 channels

– 12-bit DAC 2 channels with output buffers

• Core: ARM Cortex -M3 32-bit CPU

– From 32 kHz up to 32 MHz max

– 1.25 DMIPS/MHz (Dhrystone 2.1)

– Memory protection unit

– 2x ultra-low-power-comparators

(window mode and wake up capability)

• Reset and supply management

• DMA controller 7x channels

– Ultra-safe, low-power BOR (brownout

• 8x peripheral communication interfaces

– 1x USB 2.0 (internal 48 MHz PLL)

– 3x USARTs (ISO 7816, IrDA)

– 2x SPIs 16 Mbit/s

reset) with 5 selectable thresholds

– Ultra-low-power POR/PDR

– Programmable voltage detector (PVD)

• Clock sources

– 2x I2Cs (SMBus/PMBus)

– 1 to 24 MHz crystal oscillator

• 10x timers: 6x 16-bit with up to 4 IC/OC/PWM

channels, 2x 16-bit basic timers, 2x watchdog

timers (independent and window)

– 32 kHz oscillator for RTC with calibration

– High Speed Internal 16 MHz factory-

trimmed RC (+/- 1%)

• Up to 20 capacitive sensing channels

supporting touchkey, linear and rotary touch

sensors

– Internal low-power 37 kHz RC

– Internal multispeed low-power 65 kHz to

4.2 MHz

• CRC calculation unit, 96-bit unique ID

– PLL for CPU clock and USB (48 MHz)

• Pre-programmed bootloader

Table 1. Device summary

– USART supported

Reference

Part number

• Development support

– Serial wire debug supported

– JTAG and trace supported

STM32L151CB, STM32L151C8,

STM32L151C6, STM32L151RB,

STM32L151R8, STM32L151R6,

STM32L151VB, STM32L151V8

STM32L151x6/8/B

• Up to 83 fast I/Os (73 I/Os 5V tolerant), all

mappable on 16 external interrupt vectors

STM32L152CB, STM32L152C8,

STM32L152C6, STM32L152RB,

STM32L152R8, STM32L152R6,

STM32L152VB, STM32L152V8

• Memories

STM32L152x6/8/B

– Up to 128 Kbytes Flash memory with ECC

– Up to 16 Kbytes RAM

April 2016

DocID17659 Rev 12

1/133

This is information on a product in full production.

www.st.com

Contents

STM32L151x6/8/B STM32L152x6/8/B

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

2.2

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1

2.2.2

2.2.3

2.2.4

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1

3.2

3.3

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ARM^®Cortex^®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3.1

3.3.2

3.3.3

3.3.4

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4

3.5

3.6

3.7

3.8

3.9

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23

GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.2 Internal voltage reference (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

REFINT

3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 26

3.13 Routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.14 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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3.15.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) . 28

3.15.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.15.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.15.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.15.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 29

3.16.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.17 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30

3.18 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4

5

6

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

6.1.8

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.2

6.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Embedded reset and power control block characteristics . . . . . . . . . . . 54

Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Wakeup time from Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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6.3.9

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.3.20 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.3.21 LCD controller (STM32L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

7.1

LQFP100 14 x 14 mm, 100-pin low-profile quad flat package

information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

7.2

7.3

7.4

7.5

LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information . 108

LQFP48 7 x 7 mm, 48-pin low-profile quad flat package information . . . .111

UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information . . . . . . . . . . .114

UFBGA100 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch

ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

7.6

7.7

TFBGA64 5 x 5 mm, 0.5 mm pitch, thin fine-pitch ball

grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.7.1

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

8

9

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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List of tables

Table 1.

Table 2.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B device features and

peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15

CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16

Working mode-dependent functionalities (from Run/active down to standby) . . . . . . . . . . 17

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

STM32L151x6/8/B and STM32L152x6/8/B pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . 37

Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 54

Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Current consumption in Run mode, code with data processing running from Flash. . . . . . 58

Current consumption in Run mode, code with data processing running from RAM . . . . . . 59

Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 64

Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 66

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

LSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Flash memory, data EEPROM endurance and data retention . . . . . . . . . . . . . . . . . . . . . . 78

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2

I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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List of tables

STM32L151x6/8/B STM32L152x6/8/B

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

Table 69.

Table 70.

Table 71.

Table 72.

Table 73.

SCL frequency (f

= 32 MHz, V = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 88

PCLK1 DD

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Maximum source impedance R

max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

AIN

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

LQPF100 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 106

LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 108

LQFP48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 112

UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 115

UFBGA100 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 117

UFBGA100 7 x 7 mm, 0.5 mm pitch, recommended PCB design rules . . . . . . . . . . . . . . 118

TFBGA64 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . 120

TFBGA64 5 x 5 mm, 0.5 mm pitch, recommended PCB design rules . . . . . . . . . . . . . . . 121

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B block diagram. . . . . . . . . . . . 13

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STM32L15xVx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

STM32L15xVx LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

STM32L15xRx TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

STM32L15xRx LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

STM32L15xCx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

STM32L15xCx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 13. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 19. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 20. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2

Figure 21. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 22. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

(1)

Figure 23. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

(1)

Figure 24. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 25. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 26. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 28. Maximum dynamic current consumption on V

supply pin during ADC

REF+

conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 29. Power supply and reference decoupling (V

Figure 30. Power supply and reference decoupling (V

not connected to V

). . . . . . . . . . . . . . 98

). . . . . . . . . . . . . . . . . 98

REF+

DDA

connected to V

REF+

DDA

Figure 31. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 32. LQFP100 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 105

Figure 33. LQPF100 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . 107

Figure 34. LQFP100 14 x 14 mm, 100-pin package top view example . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 35. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 108

Figure 36. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint . . . . 109

Figure 37. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . 110

Figure 38. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 111

Figure 39. LQFP48 7 x 7 mm, 48-pin low-profile quad flat recommended footprint. . . . . . . . . . . . . . 112

Figure 40. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package top view example . . . . . . . . . . . 113

Figure 41. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 42. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package recommended footprint . . . . . . . . . . . . . . 115

Figure 43. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . 116

Figure 44. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 45. UFBGA100 7 x 7 mm, 0.5 mm pitch, package recommended footprint . . . . . . . . . . . . . . 118

Figure 46. UFBGA100 7 x 7 mm, 0.5 mm pitch, package top view example. . . . . . . . . . . . . . . . . . . 119

Figure 47. TFBGA64 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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8

List of figures

STM32L151x6/8/B STM32L152x6/8/B

Figure 48. TFBGA64, 5 x 5 mm, 0.5 mm pitch, recommended footprint . . . . . . . . . . . . . . . . . . . . . . 121

Figure 49. TFBGA64 5 x 5 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . . . 122

Figure 50. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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Introduction

1

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

®

the STM32L151x6/8/B and STM32L152x6/8/B ultra-low-power ARM Cortex -M3 based

microcontrollers product line.

The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B family includes devices in 3

different package types: from 48 to 100 pins. Depending on the device chosen, different sets

of peripherals are included, the description below gives an overview of the complete range

of peripherals proposed in this family.

These features make the ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B

microcontroller family suitable for a wide range of applications:

•

Medical and handheld equipment

Application control and user interface

PC peripherals, gaming, GPS and sport equipment

Alarm systems, Wired and wireless sensors, Video intercom

Utility metering

This STM32L151x6/8/B and STM32L152x6/8/B datasheet should be read in conjunction

with the STM32L1xxxx reference manual (RM0038).

The document "Getting started with STM32L1xxxx hardware development” AN3216 gives a

hardware implementation overview. Both documents are available from the

STMicroelectronics website www.st.com.

®

For information on the ARM Cortex -M3 core please refer to the Cortex -M3 Technical

Reference Manual, available from the www.arm.com website.

Figure 1 shows the general block diagram of the device family.

Caution:

This datasheet does not apply to STM32L15xx6/8/B-A covered by a separate datasheet.

DocID17659 Rev 12

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48

Description

STM32L151x6/8/B STM32L152x6/8/B

2

Description

The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices incorporate the

®

connectivity power of the universal serial bus (USB) with the high-performance ARM

®

Cortex -M3 32-bit RISC core operating at 32 MHz frequency (33.3 DMIPS), a memory

protection unit (MPU), high-speed embedded memories (Flash memory up to 128 Kbytes

and RAM up to 16 Kbytes) and an extensive range of enhanced I/Os and peripherals

connected to two APB buses.

All the devices offer a 12-bit ADC, 2 DACs and 2 ultra-low-power comparators, six general-

purpose 16-bit timers and two basic timers, which can be used as time bases.

Moreover, the STM32L151x6/8/B and STM32L152x6/8/B devices contain standard and

2

advanced communication interfaces: up to two I Cs and SPIs, three USARTs and a USB.

The STM32L151x6/8/B and STM32L152x6/8/B devices offer up to 20 capacitive sensing

channels to simply add touch sensing functionality to any application.

They also include a real-time clock and a set of backup registers that remain powered in

Standby mode.

Finally, the integrated LCD controller (except STM32L151x6/8/B devices) has a built-in LCD

voltage generator that allows to drive up to 8 multiplexed LCDs with contrast independent of

the supply voltage.

The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices operate from a 1.8

to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V

power supply without BOR option. It is available in the -40 to +85 °C temperature range,

extended to 105°C in low power dissipation state. A comprehensive set of power-saving

modes allows the design of low-power applications.

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Description

2.1

Device overview

Table 2. Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B device features and

peripheral counts

Peripheral

STM32L15xCx

STM32L15xRx

STM32L15xVx

Flash (Kbytes)

32

64

10

128

32

10

64

4

128

64

10

128

16

Data EEPROM (Kbytes)

RAM (Kbytes)

10

16

10

16

General-

6

purpose

Basic

SPI

Timers

2

I²C

2

Communication

interfaces

USART

USB

3

1

GPIOs

37

51

83

1

12-bit synchronized ADC

Number of channels

1

14 channels

20 channels

24 channels

12-bit DAC

Number of channels

2

LCD (STM32L152xx Only)

COM x SEG

4x32

8x28

4x44

8x40

4x18

13

Comparator

2

Capacitive sensing channels

Max. CPU frequency

20

32 MHz

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

1.65 V to 3.6 V without BOR option

Operating voltage

Ambient temperatures: –40 to +85 °C

Junction temperature: –40 to + 105 °C

Operating temperatures

Packages

LQFP48, UFQFPN48

LQFP64, BGA64

LQFP100, BGA100

DocID17659 Rev 12

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48

Description

STM32L151x6/8/B STM32L152x6/8/B

2.2

Ultra-low-power device continuum

The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices are fully pin-to-pin

and software compatible. Besides the full compatibility within the family, the devices are part

of STMicroelectronics microcontrollers ultra-low-power strategy which also includes

STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a

continuum of performance, peripherals, system architecture and features.

They are all based on STMicroelectronics ultra-low leakage process.

Note:

The ultra-low-power STM32L and general-purpose STM32Fxxxx families are pin-to-pin

compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx

devices. Please refer to the STM32F and STM8L documentation for more information on

these devices.

2.2.1

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and

®

pipelined execution: advanced STM8 core for STM8L families and ARM Cortex -M3 core

for STM32L family. In addition specific care for the design architecture has been taken to

optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

2.2.2

2.2.3

Shared peripherals

STM8L15xxx and STM32L1xxxx share identical peripherals which ensure a very easy

migration from one family to another:

•

Analog peripherals: ADC, DAC and comparators

Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L15xx and STM32L1xxxx families

use a common architecture:

•

Same power supply range from 1.65 V to 3.6 V, (1.65 V at power down only for

STM8L15xx devices)

•

Architecture optimized to reach ultra-low consumption both in low power modes and

Run mode

•

Fast startup strategy from low power modes

Flexible system clock

Ultrasafe reset: same reset strategy including power-on reset, power-down reset,

brownout reset and programmable voltage detector.

2.2.4

Features

ST ultra-low-power continuum also lies in feature compatibility:

•

More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm

Memory density ranging from 4 to 384 Kbytes

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STM32L151x6/8/B STM32L152x6/8/B

Functional overview

3

Functional overview

Figure 1 shows the block diagram.

Figure 1. Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B block diagram

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06Yꢀꢁꢂꢃꢃ9ꢄ

1. AF = alternate function on I/O port pin.

DocID17659 Rev 12

13/133

48

Functional overview

STM32L151x6/8/B STM32L152x6/8/B

3.1

Low power modes

The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices support dynamic

voltage scaling to optimize its power consumption in run mode. The voltage from the internal

low-drop regulator that supplies the logic can be adjusted according to the system’s

maximum operating frequency and the external voltage supply:

•

In Range 1 (V range limited to 1.71-3.6 V), the CPU runs at up to 32 MHz (refer to

Table 17 for consumption).

DD

In Range 2 (full V range), the CPU runs at up to 16 MHz (refer to Table 17 for

DD

consumption)

In Range 3 (full V range), the CPU runs at up to 4 MHz (generated only with the

DD

multispeed internal RC oscillator clock source). Refer to Table 17 for consumption.

Seven low power modes are provided to achieve the best compromise between low power

consumption, short startup time and available wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

Sleep mode power consumption: refer to Table 19.

Low power run mode

•

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the

minimum clock (65 kHz), execution from SRAM or Flash memory, and internal

regulator in low power mode to minimize the regulator's operating current. In the Low

power run mode, the clock frequency and the number of enabled peripherals are both

limited.

Low power run mode consumption: refer to Table 20: Current consumption in Low

power run mode.

•

Low power sleep mode

This mode is achieved by entering the Sleep mode with the internal voltage regulator in

Low power mode to minimize the regulator’s operating current. In the Low power sleep

mode, both the clock frequency and the number of enabled peripherals are limited; a

typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the run

mode with the regulator on.

Low power sleep mode consumption: refer to Table 21: Current consumption in Low

power sleep mode.

•

Stop mode with RTC

Stop mode achieves the lowest power consumption while retaining the RAM and

register contents and real time clock. All clocks in the V

domain are stopped, the

CORE

PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still

running. The voltage regulator is in the low power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI

line source can be one of the 16 external lines. It can be the PVD output, the

Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can

be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp

event or the RTC wakeup.

•

Stop mode without RTC

Stop mode achieves the lowest power consumption while retaining the RAM and

register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and

14/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Functional overview

HSE crystal oscillators are disabled. The voltage regulator is in the low power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI

line source can be one of the 16 external lines. It can be the PVD output, the

Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can

also be wakened by the USB wakeup.

Stop mode consumption: refer to Table 22: Typical and maximum current

consumptions in Stop mode.

•

Standby mode with RTC

Standby mode is used to achieve the lowest power consumption and real time clock.

The internal voltage regulator is switched off so that the entire V

domain is

CORE

powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched

off. The LSE or LSI is still running. After entering Standby mode, the RAM and register

contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,

RTC, LSI, LSE Crystal 32K osc, RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG

reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),

RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.

•

Standby mode without RTC

Standby mode is used to achieve the lowest power consumption. The internal voltage

regulator is switched off so that the entire V

domain is powered off. The PLL, MSI,

CORE

RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After

entering Standby mode, the RAM and register contents are lost except for registers in

the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,

RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising

edge on one of the three WKUP pin occurs.

Standby mode consumption: refer to Table 23.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the

Stop or Standby mode.

Table 3. Functionalities depending on the operating power supply range

Functionalities depending on the operating power supply range

Operating power

DAC and ADC

operation

Dynamicvoltage

scaling range

supply range

USB

I/O operation

Range 2 or

Range 3

Degraded speed

performance

V_DD= 1.65 to 1.71 V

V_DD= 1.71 to 1.8 V⁽¹⁾

V_DD= 1.8 to 2.0 V⁽¹⁾

Not functional

Range 1,

Range 2 or

Range 3

Degraded speed

performance

Range 1,

Range 2 or

Range 3

Conversion time

up to 500 Ksps

Degraded speed

performance

DocID17659 Rev 12

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48

Functional overview

STM32L151x6/8/B STM32L152x6/8/B

Table 3. Functionalities depending on the operating power supply range (continued)

Functionalities depending on the operating power supply range

Operating power

DAC and ADC

operation

Dynamicvoltage

scaling range

supply range

USB

I/O operation

Range 1,

Range 2 or

Range 3

Conversion time

up to 500 Ksps

V_DD= 2.0 to 2.4 V

Functional⁽²⁾

Full speed operation

Range 1,

Range 2 or

Range 3

Conversion time

up to 1 Msps

V_DD= 2.4 to 3.6 V

1. The CPU frequency changes from initial to final must respect "F_CPUinitial < 4*F_CPUfinal" to limit V_CORE

drop due to current consumption peak when frequency increases. It must also respect 5 µs delay between

two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz,

wait 5 µs, then switch from 16 MHz to 32 MHz.

2. Should be USB compliant from I/O voltage standpoint, the minimum V_DDis 3.0 V.

Table 4. CPU frequency range depending on dynamic voltage scaling

CPU frequency range

Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

Range 1

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

Range 2

Range 3

2.1 MHz to 4.2 MHz (1ws)

32 kHz to 2.1 MHz (0ws)

16/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Functional overview

Table 5. Working mode-dependent functionalities (from Run/active down to standby)

Stop

Standby

Low-

power

Run

Low-

power

Sleep

Ips

Run/Active

Sleep

Wakeup

capability

Wakeup

capability

CPU

Flash

RAM

Y

-

Y

-

Y

-

Y

-

Y

-

Backup Registers

EEPROM

Y

-

Brown-out rest

(BOR)

Y

-

Y

-

Y

-

DMA

Programmable

Voltage Detector

(PVD)

Y

-

Power On Reset

(POR)

Y

-

Y

-

Y

-

Y

-

Y

-

Power Down Rest

(PDR)

High Speed

Internal (HSI)

-

High Speed

External (HSE)

-

Low Speed Internal

(LSI)

Y

-

Y

-

Low Speed

External (LSE)

-

Multi-Speed

Internal (MSI)

-

Inter-Connect

Controller

-

RTC

Y

-

RTC Tamper

Y

Auto Wakeup

(AWU)

Y

-

Y

LCD

USB

USART

SPI

Y

-

Y

-

Y

-

Y

(1)

Y

-

Y

-

Y

-

(1)

I2C

-

ADC

-

DocID17659 Rev 12

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48

Functional overview

STM32L151x6/8/B STM32L152x6/8/B

Table 5. Working mode-dependent functionalities (from Run/active down to standby) (continued)

Stop

Standby

Low-

power

Run

Low-

power

Sleep

Ips

Run/Active

Sleep

Wakeup

capability

Wakeup

capability

DAC

Y

-

Temperature

sensor

-

Comparators

Y

-

16-bit and 32-bit

Timers

IWDG

Y

-

Y

-

Y

-

Y

-

Y

-

Y

-

Y

WWDG

-

Touch sensing

Systick Timer

GPIOs

-

Y

-

Y

-

3 Pins

Wakeup time to

Run mode

0 µs

0.36 µs

3 µs

32 µs

< 8 µs

50 µs

0.5 µA (No

RTC) V_DD=1.8V

0.3 µA (No RTC)

V_DD=1.8V

1.4 µA (with

RTC) V_DD=1.8V

1 µA (with RTC)

V_DD=1.8V

Consumption

V_DD=1.8V to 3.6V

(Typ)

Down to

214 µA/MHz

(from Flash)

Down to

50 µA/MHz

(from Flash)

Down to Down to

9 µA 4.4 µA

0.5 µA (No

RTC) V_DD=3.0V

0.3 µA (No RTC)

V_DD=3.0V

1.6 µA (with

1.3 µA (with

RTC) V_DD=3.0V RTC) V_DD=3.0V

1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before

entering run mode.

3.2

ARM^®Cortex^®-M3 core with MPU

®

The ARM Cortex -M3 processor is the industry leading processor for embedded systems.

It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

®

The ARM Cortex -M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually

associated with 8- and 16-bit devices.

The memory protection unit (MPU) improves system reliability by defining the memory

attributes (such as read/write access permissions) for different memory regions. It provides

up to eight different regions and an optional predefined background region.

Owing to its embedded ARM core, the STM32L151x6/8/B and STM32L152x6/8/B devices

are compatible with all ARM tools and software.

18/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Functional overview

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices embed a nested

vectored interrupt controller able to handle up to 45 maskable interrupt channels (not

®

including the 16 interrupt lines of Cortex -M3) and 16 priority levels.

•

Closely coupled NVIC gives low-latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving, higher-priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.3

Reset and supply management

3.3.1

Power supply schemes

•

V

= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.

DD

Provided externally through V pins.

DD

•

V

, V

= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

SSA DDA

and PLL (minimum voltage to be applied to V

is 1.8 V when the ADC is used).

DDA

V

and V

must be connected to V and V , respectively.

DDA

SSA DD SS

3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

The device exists in two versions:

•

The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

The other version without BOR operates between 1.65 V and 3.6 V.

After the V threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or

DD

not at power-on), the option byte loading process starts, either to confirm or modify default

thresholds, or to disable the BOR permanently: in this case, the V min value becomes

DD

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever

the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the

power ramp-up should guarantee that 1.65 V is reached on V at least 1 ms after it exits

DD

the POR area.

DocID17659 Rev 12

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48

Functional overview

STM32L151x6/8/B STM32L152x6/8/B

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Stop mode, it is possible to automatically switch off the

internal reference voltage (V

) in Stop mode. The device remains in reset mode when

REFINT

V

is below a specified threshold, V

or V

, without the need for any external

DD

POR/PDR

BOR

reset circuit.

Note:

3.3.3

3.3.4

The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-

up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive

at power-up.

The device features an embedded programmable voltage detector (PVD) that monitors the

V

/V

power supply and compares it to the V

threshold. This PVD offers 7 different

DD DDA

PVD

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when V /V drops below the V threshold and/or when

DD DDA

PVD

V

/V

is higher than the V

threshold. The interrupt service routine can then generate

DD DDA

PVD

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

•

MR is used in Run mode (nominal regulation)

LPR is used in the Low-power run, Low-power sleep and Stop modes

Power down is used in Standby mode. The regulator output is high impedance, the

kernel circuitry is powered down, inducing zero consumption but the contents of the

registers and RAM are lost are lost except for the standby circuitry (wakeup logic,

IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR).

Boot modes

At startup, boot pins are used to select one of three boot options:

•

Boot from Flash memory

Boot from System Memory

Boot from embedded RAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1 or USART2. See STM32™ microcontroller system memory boot mode

AN2606 for details.

20/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Functional overview

3.4

Clock management

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low power modes and ensures clock

robustness. It features:

•

Clock prescaler: to get the best trade-off between speed and current consumption, the

clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

•

Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

Master clock source: three different clock sources can be used to drive the master

clock:

–

1-24 MHz high-speed external crystal (HSE), that can supply a PLL

16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can

supply a PLL

–

Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7

frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz)

with a consumption proportional to speed, down to 750 nA typical. When a

32.768 kHz clock source is available in the system (LSE), the MSI frequency can

be trimmed by software down to a ±0.5% accuracy.

•

Auxiliary clock source: two ultra-low-power clock sources that can be used to drive

the LCD controller and the real-time clock:

–

32.768 kHz low-speed external crystal (LSE)

37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for

greater precision.

•

RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock

the RTC and the LCD, whatever the system clock.

USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply

the USB interface.

Startup clock: after reset, the microcontroller restarts by default with an internal

2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the

application program as soon as the code execution starts.

•

Clock security system (CSS): this feature can be enabled by software. If a HSE clock

failure occurs, the master clock is automatically switched to HSI and a software

interrupt is generated if enabled.

Clock-out capability (MCO: microcontroller clock output): it outputs one of the

internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the APB domains is 32 MHz. See Figure 2 for details on the clock tree.

DocID17659 Rev 12

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48

Functional overview

STM32L151x6/8/B STM32L152x6/8/B

Figure 2. Clock tree

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TO 53" INTERFACE

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ꢋꢃ -(Z MAX

0#,+ꢁ

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TO 4)-ꢉꢂ ꢁꢊꢂ AND ꢁꢁ

4)-X#,+

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ꢋꢃꢄꢌꢈꢇ K(Z

24##,+

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)7$'#,+

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ꢋꢌ K(Z

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(3) ꢎ (IGHꢐSPEED INTERNAL CLOCK SIGNAL

,3) ꢎ ,OWꢐSPEED INTERNAL CLOCK SIGNAL

,3% ꢎ ,OWꢐSPEED EXTERNAL CLOCK SIGNAL

-3) ꢎ -ULTISPEED INTERNAL CLOCK SIGNAL

393#,+

(3)

ꢀꢁꢂꢃꢂꢆꢂ

ꢇꢂꢁꢈ

-3)

-#/

(3%

0,,#,+

,3)

,3%

-#/3%,

AIꢁꢌꢃꢁꢃC

22/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Functional overview

3.5

Low power real-time clock and backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain

the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded

decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made

automatically. The RTC provides a programmable alarm and programmable periodic

interrupts with wakeup from Stop and Standby modes.

•

The programmable wakeup time ranges from 120 µs to 36 hours

Stop mode consumption with LSI and Auto-wakeup: 1.2 µA (at 1.8 V) and 1.4 µA (at

3.0 V)

•

Stop mode consumption with LSE, calendar and Auto-wakeup: 1.3 µA (at 1.8V), 1.6 µA

(at 3.0 V)

The RTC can be calibrated with an external 512 Hz output, and a digital compensation

circuit helps reduce drift due to crystal deviation.

There are twenty 32-bit backup registers provided to store 80 bytes of user application data.

They are cleared in case of tamper detection.

3.6

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions, and can be individually

remapped using dedicated AFIO registers. All GPIOs are high current capable. The

alternate function configuration of I/Os can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/O registers. The I/O controller is

connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge detector lines used to generate

interrupt/event requests. Each line can be individually configured to select the trigger event

(rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected

to the 16 external interrupt lines. The 7 other lines are connected to RTC, PVD, USB or

Comparator events.

DocID17659 Rev 12

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48

Functional overview

STM32L151x6/8/B STM32L152x6/8/B

3.7

Memories

The STM32L151x6/8/B and STM32L152x6/8/B devices have the following features:

•

Up to 16 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0

wait states. With the enhanced bus matrix, operating the RAM does not lead to any

performance penalty during accesses to the system bus (AHB and APB buses).

•

The non-volatile memory is divided into three arrays:

–

32, 64 or 128 Kbytes of embedded Flash program memory

4 Kbytes of data EEPROM

Options bytes

The options bytes are used to write-protect the memory (with 4 Kbytes granularity)

and/or readout-protect the whole memory with the following options:

–

Level 0: no readout protection

Level 1: memory readout protection, the Flash memory cannot be read from or

written to if either debug features are connected or boot in RAM is selected

®

–

Level 2: chip readout protection, debug features (Cortex -M3 JTAG and serial

wire) and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.8

DMA (direct memory access)

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management, avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger

support for each channel. Configuration is done by software and transfer sizes between

source and destination are independent.

2

The DMA can be used with the main peripherals: SPI, I C, USART, general-purpose timers

and ADC.

3.9

LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320

pixels.

•

Internal step-up converter to guarantee functionality and contrast control irrespective of

. This converter can be deactivated, in which case the V pin is used to provide

V

DD

LCD

the voltage to the LCD

•

Supports static, 1/2, 1/3, 1/4 and 1/8 duty

Supports static, 1/2, 1/3 and 1/4 bias

Phase inversion to reduce power consumption and EMI

Up to 8 pixels can be programmed to blink

Unneeded segments and common pins can be used as general I/O pins

LCD RAM can be updated at any time owing to a double-buffer

The LCD controller can operate in Stop mode

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STM32L151x6/8/B STM32L152x6/8/B

Functional overview

3.10

ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L151x6/8/B and

STM32L152x6/8/B devices with up to 24 external channels, performing conversions in

single-shot or scan mode. In scan mode, automatic conversion is performed on a selected

group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to

the ADC start trigger and injection trigger, to allow the application to synchronize A/D

conversions and timers. An injection mode allows high priority conversions to be done by

interrupting a scan mode which runs in as a background task.

The ADC includes a specific low power mode. The converter is able to operate at maximum

speed even if the CPU is operating at a very low frequency and has an auto-shutdown

function. The ADC’s runtime and analog front-end current consumption are thus minimized

whatever the MCU operating mode.

3.10.1

Temperature sensor

The temperature sensor (TS) generates a voltage V

temperature.

that varies linearly with

SENSE

The temperature sensor is internally connected to the ADC_IN16 input channel which is

used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall

accuracy of the temperature measurement. As the offset of the temperature sensor varies

from chip to chip due to process variation, the uncalibrated internal temperature sensor is

suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode, see Table 58:

Temperature sensor calibration values.

3.10.2

Internal voltage reference (V

)

REFINT

The internal voltage reference (V

) provides a stable (bandgap) voltage output for the

REFINT

ADC and Comparators. V

is internally connected to the ADC_IN17 input channel. It

REFINT

enables accurate monitoring of the V value (when no external voltage, VREF+, is

DD

available for ADC). The precise voltage of V

is individually measured for each part by

REFINT

ST during production test and stored in the system memory area. It is accessible in read-

only mode see Table 16: Embedded internal reference voltage.

3.11

DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two

analog voltage signal outputs. The chosen design structure is composed of integrated

resistor strings and an amplifier in non-inverting configuration.

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48

Functional overview

STM32L151x6/8/B STM32L152x6/8/B

This dual digital Interface supports the following features:

•

two DAC converters: one for each output channel

left or right data alignment in 12-bit mode

synchronized update capability

noise-wave generation

triangular-wave generation

dual DAC channels’ independent or simultaneous conversions

DMA capability for each channel (including the underrun interrupt)

external triggers for conversion

input reference voltage V

REF+

Eight DAC trigger inputs are used in the STM32L151x6/8/B and STM32L152x6/8/B devices.

The DAC channels are triggered through the timer update outputs that are also connected

to different DMA channels.

3.12

Ultra-low-power comparators and reference voltage

The STM32L151x6/8/B and STM32L152x6/8/B devices embed two comparators sharing

the same current bias and reference voltage. The reference voltage can be internal or

external (coming from an I/O).

•

one comparator with fixed threshold

one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of

the following:

–

DAC output

External I/O

Internal reference voltage (V

) or V

submultiple (1/4, 1/2, 3/4)

REFINT

Both comparators can wake up from Stop mode, and be combined into a window

comparator.

The internal reference voltage is available externally via a low power / low current output

buffer (driving current capability of 1 µA typical).

3.13

3.14

Routing interface

This interface controls the internal routing of I/Os to TIM2, TIM3, TIM4 and to the

comparator and reference voltage output.

Touch sensing

The STM32L151x6/8/B and STM32L152x6/8/B devices provide a simple solution for adding

capacitive sensing functionality to any application. These devices offer up to 20 capacitive

sensing channels distributed over 10 analog I/O groups. Only software capacitive sensing

acquisition mode is supported.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which

is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation

introduced by the finger (or any conductive object) is measured using a proven

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STM32L151x6/8/B STM32L152x6/8/B

Functional overview

implementation based on a surface charge transfer acquisition principle. It consists of

charging the sensor capacitance and then transferring a part of the accumulated charges

into a sampling capacitor until the voltage across this capacitor has reached a specific

threshold. The capacitive sensing acquisition only requires few external components to

operate.

Reliable touch sensing functionality can be quickly and easily implemented using the free

STM32L1xx STMTouch touch sensing firmware library.

3.15

Timers and watchdogs

The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices include six general-

purpose timers, two basic timers and two watchdog timers.

Table 6 compares the features of the general-purpose and basic timers.

Table 6. Timer feature comparison

Counter

resolution

Counter Prescaler DMA request Capture/compare Complementary

Timer

type

factor

generation

channels

outputs

TIM2,

TIM3,

TIM4

Up,

down,

up/down and 65536

Any integer

between 1

16-bit

Yes

4

No

Any integer

between 1

and 65536

TIM9

Up

No

2

1

0

No

Any integer

between 1

and 65536

TIM10,

TIM11

Any integer

between 1

and 65536

TIM6,

TIM7

Yes

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Functional overview

STM32L151x6/8/B STM32L152x6/8/B

3.15.1

General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11)

There are six synchronizable general-purpose timers embedded in the STM32L151x6/8/B

and STM32L152x6/8/B devices (see Table 6 for differences).

TIM2, TIM3, TIM4

These timers are based on a 16-bit auto-reload up/down-counter and a 16-bit prescaler.

They feature 4 independent channels each for input capture/output compare, PWM or one-

pulse mode output. This gives up to 12 input captures/output compares/PWMs on the

largest packages.

The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11

and TIM9 general-purpose timers via the Timer Link feature for synchronization or event

chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers

can be used to generate PWM outputs.

TIM2, TIM3, TIM4 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload up-counter and a 16-bit prescaler. They

include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas

TIM9 has two independent channels for input capture/output compare, PWM or one-pulse

mode output. They can be synchronized with the TIM2, TIM3, TIM4 full-featured general-

purpose timers.

They can also be used as simple time bases and be clocked by the LSE clock source

(32.768 kHz) to provide time bases independent from the main CPU clock.

3.15.2

3.15.3

Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic

16-bit time bases.

SysTick timer

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is

based on a 24-bit down-counter with autoreload capability and a programmable clock

source. It features a maskable system interrupt generation when the counter reaches 0.

3.15.4

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit down-counter and 8-bit prescaler. It is

clocked from an independent 37 kHz internal RC and, as it operates independently of the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free-running timer for application timeout

management. It is hardware- or software-configurable through the option bytes. The counter

can be frozen in debug mode.

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STM32L151x6/8/B STM32L152x6/8/B

Functional overview

3.15.5

Window watchdog (WWDG)

The window watchdog is based on a 7-bit down-counter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

3.16

Communication interfaces

3.16.1

I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support

standard and fast modes.

They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master

mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

3.16.2

3.16.3

Universal synchronous/asynchronous receiver transmitter (USART)

All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide

hardware management of the CTS and RTS signals and are ISO 7816 compliant. They

support IrDA SIR ENDEC and have LIN Master/Slave capability.

All USART interfaces can be served by the DMA controller.

Serial peripheral interface (SPI)

Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in

full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

3.16.4

Universal serial bus (USB)

The STM32L151x6/8/B and STM32L152x6/8/B devices embed a USB device peripheral

compatible with the USB full speed 12 Mbit/s. The USB interface implements a full speed

(12 Mbit/s) function interface. It has software-configurable endpoint setting and supports

suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the

clock source must use a HSE crystal oscillator).

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48

Functional overview

STM32L151x6/8/B STM32L152x6/8/B

3.17

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.18

Development support

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a

specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.

The JTAG port can be permanently disabled with a JTAG fuse.

Embedded Trace Macrocell™

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data

flow inside the CPU core by streaming compressed data at a very high rate from the

STM32L151x6/8/B and STM32L152x6/8/B device through a small number of ETM pins to

an external hardware trace port analyzer (TPA) device. The TPA is connected to a host

computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and

data flow activity can be recorded and then formatted for display on the host computer

running debugger software. TPA hardware is commercially available from common

development tool vendors. It operates with third party debugger software tools.

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Pin descriptions

4

Pin descriptions

Figure 3. STM32L15xVx UFBGA100 ballout

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DocID17659 Rev 12

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48

Pin descriptions

STM32L151x6/8/B STM32L152x6/8/B

Figure 4. STM32L15xVx LQFP100 pinout

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32/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Pin descriptions

Figure 5. STM32L15xRx TFBGA64 ballout

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DocID17659 Rev 12

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48

Pin descriptions

STM32L151x6/8/B STM32L152x6/8/B

Figure 6. STM32L15xRx LQFP64 pinout

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1. This figure shows the package top view.

34/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Pin descriptions

Figure 8. STM32L15xCx UFQFPN48 pinout

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6

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AIꢁꢅꢈꢉꢅD

1. This figure shows the package top view.

DocID17659 Rev 12

35/133

48

Pin descriptions

STM32L151x6/8/B STM32L152x6/8/B

Table 7. Legend/abbreviations used in the pinout table

Abbreviation Definition

Name

Unless otherwise specified in brackets below the pin name, the pin function

during and after reset is the same as the actual pin name

Pin name

S

I

Supply pin

Input only pin

Pin type

I/O

FT

TC

B

Input / output pin

5 V tolerant I/O

Standard 3.3 V I/O

I/O structure

Notes

Dedicated BOOT0 pin

RST

Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during

and after reset

Alternate

functions

Functions selected through GPIOx_AFR registers

functions

Additional

functions

Functions directly selected/enabled through peripheral registers

36/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Pin descriptions

Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions

Pins

Pins functions

Main

Pin name

function⁽²⁾

(after reset)

Additional

functions

Alternate functions

TRACECLK/LCD_SEG38/

TIM3_ETR

1

2

-

B2

A1

-

PE2

PE3

I/O FT

PE2

PE3

-

TRACED0/LCD_SEG39/

TIM3_CH1

3

4

5

6

-

B1

C2

D2

-

PE4

PE5

I/O FT

PE4

PE5

PE6

V_LCD

TRACED1/TIM3_CH2

TRACED2/TIM9_CH1

TRACED3/TIM9_CH2

-

PE6-WKUP3 I/O FT

WKUP3

-

(3)

1

B2 E2

1

V_LCD

S

RTC_TAMP1/

RTC_TS/

PC13-

WKUP2

7

2

A2 C1

2

I/O FT

PC13

-

RTC_OUT/

WKUP2

PC14-

8

9

3

4

A1 D1

B1 E1

3

4

I/O TC

PC14

PC15

-

OSC32_IN

OSC32_IN⁽⁴⁾

PC15-

OSC32_OUT I/O TC

OSC32_OUT

(4)

10

11

-

F2

-

V_{SS_5}

V_{DD_5}

S

-

V_{SS_5}

V_{DD_5}

-

G2

PH0-

12

5

C1 F1

5

I/O TC

PH0

-

OSC_IN

OSC_IN⁽⁵⁾

PH1-

OSC_OUT

13

14

15

6

7

8

D1 G1

E1 H2

E3 H1

6

7

-

I/O TC

I/O RST

I/O FT

PH1

NRST

PC0

-

OSC_OUT

-

NRST

PC0

-

ADC_IN10/

LCD_SEG18

/COMP1_INP

ADC_IN11/

16

9

E2 J2

-

PC1

PC2

PC3

I/O FT

I/O TC

PC1

PC2

PC3

LCD_SEG19

LCD_SEG20

LCD_SEG21

COMP1_INP

ADC_IN12/

17 10 F2 J3

COMP1_INP

ADC_IN13/

18 11 -⁽⁶⁾

K2

COMP1_INP

DocID17659 Rev 12

37/133

48

Pin descriptions

STM32L151x6/8/B STM32L152x6/8/B

Pins functions

Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)

Pins

Main

Pin name

function⁽²⁾

(after reset)

Additional

Alternate functions

functions

19 12 F1 J1

8

-

V_SSA

S

-

V_SSA

-

20

21

-

K1

L1

V_REF-

G1

-

V_REF+

V_DDA

S

-

V_REF+

V_DDA

-

(6)

22 13 H1 M1

9

WKUP1/

ADC_IN0/

USART2_CTS/

TIM2_CH1_ETR

23 14 G2 L2 10 PA0-WKUP1 I/O FT

PA0

COMP1_INP

USART2_RTS/

ADC_IN1/

24 15 H2 M2 11

25 16 F3 K3 12

26 17 G3 L3 13

PA1

PA2

PA3

I/O FT

I/O TC

PA1

PA2

PA3

TIM2_CH2/LCD_SEG0

COMP1_INP

ADC_IN2/

USART2_TX/TIM2_CH3/

TIM9_CH1/LCD_SEG1

COMP1_INP

ADC_IN3/

USART2_RX/TIM2_CH4/

TIM9_CH2/LCD_SEG2

COMP1_INP

27 18 C2 E3

28 19 D2 H3

-

V_{SS_4}

V_{DD_4}

S

-

V_{SS_4}

V_{DD_4}

-

ADC_IN4/

DAC_OUT1/

COMP1_INP

29 20 H3 M3 14

PA4

PA5

I/O TC

PA4

PA5

SPI1_NSS/USART2_CK

ADC_IN5/

DAC_OUT2/

SPI1_SCK/

30 21 F4 K4 15

TIM2_CH1_ETR

COMP1_INP

ADC_IN6

SPI1_MISO/TIM3_CH1/

LCD_SEG3/TIM10_CH1

31 22 G4 L4 16

32 23 H4 M4 17

PA6

PA7

PC4

PC5

I/O FT

PA6

PA7

PC4

PC5

/COMP1_INP

ADC_IN7/

SPI1_MOSI//TIM3_CH2/

LCD_SEG4/TIM11_CH1

COMP1_INP

ADC_IN14/

33 24 H5 K5

34 25 H6 L5

-

LCD_SEG22

LCD_SEG23

COMP1_INP

ADC_IN15/

COMP1_INP

38/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Pin descriptions

Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)

Pins

Pins functions

Main

Pin name

function⁽²⁾

(after reset)

Additional

functions

Alternate functions

ADC_IN8/

COMP1_INP/

35 26 F5 M5 18

PB0

PB1

I/O TC

I/O FT

PB0

PB1

TIM3_CH3/LCD_SEG5

TIM3_CH4/LCD_SEG6

VREF_OUT

ADC_IN9/

COMP1_INP/

36 27 G5 M6 19

37 28 G6 L6 20

VREF_OUT

PB2

PE7

I/O FT PB2/BOOT1

BOOT1

-

ADC_IN22/

38

39

40

41

-

M7

L7

-

I/O TC

PE7

PE8

COMP1_INP

ADC_IN23/

PE8

PE9

-

COMP1_INP

ADC_IN24/

M8

L8

PE9

TIM2_CH1_ETR

TIM2_CH2

COMP1_INP

ADC_IN25/

PE10

COMP1_INP

42

43

44

45

46

-

M9

L9

-

PE11

PE12

PE13

PE14

PE15

I/O FT

PE11

PE12

PE13

PE14

PE15

TIM2_CH3

TIM2_CH4/SPI1_NSS

SPI1_SCK

-

M10

M11

M12

SPI1_MISO

SPI1_MOSI

I2C2_SCL/USART3_TX/

TIM2_CH3/LCD_SEG10

47 29 G7 L10 21

48 30 H7 L11 22

PB10

PB11

I/O FT

PB10

PB11

-

I2C2_SDA/USART3_RX/

TIM2_CH4/LCD_SEG11

49 31 D6 F12 23

50 32 E6 G12 24

V_{SS_1}

V_{DD_1}

S

-

V_{SS_1}

V_{DD_1}

-

SPI2_NSS/I2C2_SMBA/

ADC_IN18/

51 33 H8 L12 25

52 34 G8 K12 26

PB12

PB13

I/O FT

PB12

PB13

USART3_CK/

LCD_SEG12/TIM10_CH1

COMP1_INP

SPI2_SCK/USART3_CTS/

LCD_SEG13/

ADC_IN19/

COMP1_INP

TIM9_CH1

DocID17659 Rev 12

39/133

48

Pin descriptions

STM32L151x6/8/B STM32L152x6/8/B

Pins functions

Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)

Pins

Main

Pin name

function⁽²⁾

(after reset)

Additional

Alternate functions

functions

SPI2_MISO/

ADC_IN20/

53 35 F8 K11 27

54 36 F7 K10 28

PB14

PB15

I/O FT

PB14

PB15

USART3_RTS/

COMP1_INP

LCD_SEG14//TIM9_CH2

ADC_IN21/

SPI2_MOSI/LCD_SEG15/

COMP1_INP/

TIM11_CH1

RTC_REFIN

USART3_TX/

-

55

56

57

58

-

K9

K8

-

PD8

PD9

I/O FT

PD8

PD9

LCD_SEG28

USART3_RX/

-

LCD_SEG29

USART3_CK/

J12

J11

PD10

PD11

PD10

PD11

-

LCD_SEG30

USART3_CTS/

-

LCD_SEG31

TIM4_CH1/

59

-

J10

-

PD12

I/O FT

PD12

USART3_RTS/

LCD_SEG32

-

60

61

62

-

H12

H11

H10

-

PD13

PD14

PD15

PC6

I/O FT

PD13

PD14

PD15

PC6

TIM4_CH2/LCD_SEG33

TIM4_CH3/LCD_SEG34

TIM4_CH4/LCD_SEG35

TIM3_CH1/LCD_SEG24

TIM3_CH2/LCD_SEG25

TIM3_CH3/LCD_SEG26

TIM3_CH4/LCD_SEG27

-

63 37 F6 E12

64 38 E7 E11

65 39 E8 E10

66 40 D8 D12

PC7

PC8

PC9

USART1_CK/MCO/

LCD_COM0

67 41 D7 D11 29

PA8

I/O FT

PA8

-

68 42 C7 D10 30

69 43 C6 C12 31

PA9

I/O FT

PA9

USART1_TX/LCD_COM1

USART1_RX/LCD_COM2

-

PA10

USART1_CTS/

SPI1_MISO

70 44 C8 B12 32

PA11

I/O FT

PA11

USB_DM

40/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Pin descriptions

Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)

Pins

Pins functions

Main

Pin name

function⁽²⁾

(after reset)

Additional

functions

Alternate functions

USART1_RTS/

SPI1_MOSI

71 45 B8 A12 33

72 46 A8 A11 34

PA12

PA13

I/O FT

PA12

USB_DP

-

JTMS-

SWDIO

I/O FT

JTMS-SWDIO

73

-

C11

-

PH2

V_{SS_2}

V_{DD_2}

PH2

V_{SS_2}

V_{DD_2}

-

74 47 D5 F11 35

75 48 E5 G11 36

S

-

JTCK

-SWCLK

76 49 A7 A10 37

77 50 A6 A9 38

PA14

PA15

I/O FT

JTCK-SWCLK

-

TIM2_CH1_ETR/PA15/

JTDI

SPI1_NSS/

LCD_SEG17

USART3_TX/LCD_SEG28

/LCD_SEG40/LCD_COM4

78 51 B7 B11

79 52 B6 C10

80 53 C5 B10

-

PC10

PC11

PC12

I/O FT

PC10

PC11

PC12

-

USART3_RX/LCD_SEG29

/LCD_SEG41/LCD_COM5

USART3_CK/LCD_SEG30

/LCD_SEG42/LCD_COM6

81

82

-

C9

B9

-

PD0

PD1

I/O FT

PD0

PD1

SPI2_NSS/TIM9_CH1

SPI2_SCK

-

TIM3_ETR/LCD_SEG31/

LCD_SEG43/LCD_COM7

83 54 B5 C8

-

PD2

PD3

PD4

I/O FT

PD2

PD3

PD4

-

USART2_CTS/

SPI2_MISO

84

85

-

B8

B7

USART2_RTS/

SPI2_MOSI

86

87

88

-

A6

B6

A5

-

PD5

PD6

PD7

I/O FT

PD5

PD6

PD7

USART2_TX

USART2_RX

-

USART2_CK/TIM9_CH2

TIM2_CH2/PB3/

SPI1_SCK/LCD_SEG7/

JTDO

89 55 A5 A8 39

PB3

I/O FT

JTDO

COMP2_INM

DocID17659 Rev 12

41/133

48

Pin descriptions

STM32L151x6/8/B STM32L152x6/8/B

Pins functions

Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)

Pins

Main

Pin name

function⁽²⁾

(after reset)

Additional

Alternate functions

functions

TIM3_CH1/PB4/

90 56 A4 A7 40

PB4

I/O FT

NJTRST

SPI1_MISO/LCD_SEG8/

NJTRST

COMP2_INP

I2C1_SMBA/TIM3_CH2/

SPI1_MOSI/LCD_SEG9

91 57 C4 C5 41

92 58 D3 B5 42

PB5

PB6

I/O FT

PB5

PB6

I2C1_SCL/TIM4_CH1/

USART1_TX

I2C1_SDA/TIM4_CH2/

USART1_RX

PVD_IN

93 59 C3 B4 43

94 60 B4 A4 44

95 61 B3 A3 45

PB7

BOOT0

PB8

PB7

BOOT0

PB8

I

B

-

TIM4_CH3/I2C1_SCL/

I/O FT

LCD_SEG16/TIM10_CH1

TIM4_CH4/I2C1_SDA/

LCD_COM3/TIM11_CH1

96 62 A3 B3 46

PB9

PE0

PB9

PE0

-

TIM4_ETR/LCD_SEG36/

TIM10_CH1

97

98

-

C3

A2

-

I/O FT

PE1

LCD_SEG37/TIM11_CH1

-

99 63 D4 D3 47

100 64 E4 C4 48

V_{SS_3}

S

-

V_{SS_3}

V_{DD_3}

-

1. I = input, O = output, S = supply.

2. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower

number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1

and USART1 & USART2, respectively. Refer to Table 2 on page 11.

3. Applicable to STM32L152xx devices only. In STM32L151xx devices, this pin should be connected to V_DD

.

4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the

LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose

PC14/PC15 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over

the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins

section in the STM32L1xxxx reference manual (RM0038).

5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on (by setting the HSEON bit

in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,

respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off). The HSE has priority over the GPIO

function.

6. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V_REF+functionality is provided instead.

42/133

DocID17659 Rev 12

Memory mapping

STM32L151x6/8/B STM32L152x6/8/B

5

Memory mapping

The memory map is shown in Figure 9.

Figure 9. Memory map

!0" MEMORY SPACE

ꢀX&&&& &&&&

RESERVED

ꢀX%ꢀꢅꢀ ꢀꢀꢀꢀ

ꢀXꢇꢀꢀꢀ ꢀꢀꢀꢀ

RESERVED

$-!

ꢀXꢁꢀꢀꢃ ꢇꢁꢀꢀ

ꢀXꢁꢀꢀꢃ ꢇꢀꢀꢀ

ꢀXꢁꢀꢀꢃ ꢁꢀꢀꢀ

ꢀXꢁꢀꢀꢃ ꢄ#ꢀꢀ

ꢀX&&&& &&&&

RESERVED

&LASH )NTERFACE

2##

ꢀXꢁꢀꢀꢃ ꢄꢂꢀꢀ

ꢌ

RESERVED

ꢀXꢁꢀꢀꢃ ꢄꢁꢀꢀ

ꢀXꢁꢀꢀꢃ ꢄꢀꢀꢀ

ꢀX%ꢀꢅꢀ ꢀꢀꢀꢀ

#ORTEXꢐ-ꢋ )NTERNAL

0ERIPHERALS

#2#

ꢀX%ꢀꢀꢀ ꢀꢀꢀꢀ

RESERVED

ꢀXꢁꢀꢀꢃ ꢅꢂꢀꢀ

ꢀXꢁꢀꢀꢃ ꢅꢁꢀꢀ

0ORT (

RESERVED

0ORT $

ꢀXꢁꢀꢀꢃ ꢅꢀꢀꢀ

ꢀXꢁꢀꢀꢃ ꢀ#ꢀꢀ

ꢀXꢁꢀꢀꢃ ꢀꢂꢀꢀ

ꢀXꢁꢀꢀꢃ ꢀꢁꢀꢀ

ꢈ

0ORT #

0ORT "

ꢀX#ꢀꢀꢀ ꢀꢀꢀꢀ

0ORT !

ꢀXꢁꢀꢀꢃ ꢀꢀꢀꢀ

RESERVED

ꢀXꢁꢀꢀꢅ ꢄ#ꢀꢀ

ꢀXꢁꢀꢀꢅ ꢄꢂꢀꢀ

ꢀXꢁꢀꢀꢅ ꢄꢁꢀꢀ

53!24ꢁ

RESERVED

30)ꢁ

ꢅ

ꢀX!ꢀꢀꢀ ꢀꢀꢀꢀ

ꢀXꢁꢀꢀꢅ ꢄꢀꢀꢀ

RESERVED

!$#

ꢀXꢁꢀꢀꢅ ꢃꢂꢀꢀ

ꢀXꢁꢀꢀꢅ ꢃꢁꢀꢀ

ꢆ

RESERVED

4)-ꢁꢁ

ꢀXꢁꢀꢀꢅ ꢅꢁꢀꢀ

ꢀXꢁꢀꢀꢅ ꢅꢀꢀꢀ

ꢀXꢂꢀꢀꢀ ꢀꢀꢀꢀ

4)-ꢁꢊ

4)-ꢉ

%84)

ꢀXꢁꢀꢀꢅ ꢀ#ꢀꢀ

ꢀXꢁꢀꢀꢅ ꢀꢂꢀꢀ

ꢋ

ꢀXꢁꢀꢀꢅ ꢀꢁꢀꢀ

ꢀXꢁꢀꢀꢅ ꢀꢀꢀꢀ

ꢀXꢅ&&ꢂ ꢀꢀꢅ&

393#&'

RESERVED

/PTION "YTES

RESERVED

ꢀXꢅ&&ꢂ ꢀꢀꢀꢀ

ꢀXꢇꢀꢀꢀ ꢀꢀꢀꢀ

#/-0 ꢒ 2)

RESERVED

ꢀXꢁꢀꢀꢀ ꢈ#ꢀꢀ

ꢀXꢅ&&ꢀ ꢅꢀꢀꢀ

ꢀXꢁꢀꢀꢀ ꢈꢂꢀꢀ

ꢀXꢁꢀꢀꢀ ꢈꢁꢀꢀ

RESERVED

$!#ꢁ ꢓ ꢃ

072

ꢃ

3YSTEM MEMORY

ꢀXꢁꢀꢀꢀ ꢈꢀꢀꢀ

ꢀXꢁꢀꢀꢀ ꢇꢃꢀꢀ

RESERVED

0ERIPHERALS

ꢀXꢁꢀꢀꢀ ꢀꢀꢀꢀ

ꢀXꢅ&&ꢀ ꢀꢀꢀꢀ

ꢅꢁꢃ BYTE

53"

53" 2EGISTERS

ꢀXꢁꢀꢀꢀ ꢇꢀꢀꢀ

ꢀXꢁꢀꢀꢀ ꢆ#ꢀꢀ

ꢁ

)ꢃ#ꢃ

)ꢃ#ꢁ

ꢀXꢁꢀꢀꢀ ꢆꢂꢀꢀ

ꢀXꢁꢀꢀꢀ ꢆꢁꢀꢀ

ꢀXꢁꢀꢀꢀ ꢁ#ꢀꢀ

RESERVED

32!-

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48/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

6

Electrical characteristics

6.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

6.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes. Based on characterization, the minimum and maximum

values refer to sample tests and represent the mean value plus or minus three times the

standard deviation (mean±3σ).

Please refer to device ErrataSheet for possible latest changes of electrical characteristics.

6.1.2

6.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.6 V (for the

A

DD

1.65 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean±2σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

6.1.4

6.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

Figure 10. Pin loading conditions

Figure 11. Pin input voltage

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DocID17659 Rev 12

49/133

104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

6.1.6

Power supply scheme

Figure 12. Power supply scheme

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50/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

6.1.7

Optional LCD power supply scheme

Figure 13. Optional LCD power supply scheme

VSEL

V_DD

V_DD1/2/.../N

Step-up

Converter

N x 100 nF

+ 1 x 10 μF

Option 1

Option 2

V_LCD

100 nF

LCD

V_LCD

C_EXT

V_SS1/2/.../N

MS32462V1

1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.

2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an

external capacitance is needed for correct behavior of this converter.

6.1.8

Current consumption measurement

Figure 14. Current consumption measurement scheme

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DocID17659 Rev 12

51/133

104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

6.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics,

Table 11: Current characteristics, and Table 12: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Table 10. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

External main supply voltage

V_DD–V_SS

–0.3

4.0

(1)

(including V_DDAand V_DD

)

V

Input voltage on five-volt tolerant pin

Input voltage on any other pin

V_SS−0.3

V_DD+4.0

4.0

(2)

V_IN

V_SS−0.3

|ΔV_DDx

|

Variations between different V_DDpower pins

Variations between all different ground pins⁽³⁾

-

50

mV

|V_SSX−V_SS

|

50

V_REF+−V_DDAAllowed voltage difference for V_REF+> V_DDA

0.4

V

-

Electrostatic discharge voltage

V_ESD(HBM)

see Section 6.3.11

(human body model)

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. V_INmaximum must always be respected. Refer to Table 11 for maximum allowed injected current values.

3. Include VREF- pin.

Table 11. Current characteristics

Symbol

Ratings

Max.

Unit

I_VDDΣ

I_VSSΣ

Total current into V_DD/V_DDApower lines (source)⁽¹⁾

Total current out of V_SSground lines (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current sourced by any I/O and control pin

Injected current on five-volt tolerant I/O⁽³⁾

80

25

I_IO

- 25

-5/+0

± 5

(2)

I_INJ(PIN)

Injected current on any other pin ⁽⁴⁾

mA

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁵⁾

± 25

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17.

3. Positive current injection is not possible on these I/Os. A negative injection is induced by V_IN<V_SS. I_INJ(PIN)

must never be exceeded. Refer to Table 10 for maximum allowed input voltage values.

4. A positive injection is induced by V_IN> V_DDwhile a negative injection is induced by V_IN< V_SS. I_INJ(PIN)

must never be exceeded. Refer to Table 10: Voltage characteristics for the maximum allowed input voltage

values.

5. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values).

52/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Symbol

Electrical characteristics

Table 12. Thermal characteristics

Ratings

Value

Unit

T_STG

T_J

Storage temperature range

Maximum junction temperature

–65 to +150

150

°C

6.3

Operating conditions

6.3.1

General operating conditions

Table 13. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK1

f_PCLK2

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

-

0

32

3.6

-

MHz

-

0

BOR detector disabled

1.65

BOR detector enabled,

at power on

1.8

1.65

1.8

3.6

V_DD

Standard operating voltage

V

BOR detector disabled, after

power on

Analog operating voltage

(ADC and DAC not used)

Must be the same voltage as

(1)

V_DDA

(2)

V_DD

Analog operating voltage

(ADC or DAC used)

Input voltage on FT pins⁽³⁾

2.0 V ≤V_DD≤ 3.6 V

–0.3

0

5.5

5.25

1.65 V ≤ V_DD≤ 2.0 V

V_IN

V

Input voltage on BOOT0 pin

Input voltage on any other pin

5.5

–0.3

V_DD+0.3

Power dissipation at

T_A= 85 °C⁽⁴⁾

P_D

BGA100 package

-

339

mW

Maximum power dissipation

Low power dissipation⁽⁵⁾

-40 °C ≤T_A≤105°C

–40

85

TA

TJ

Temperature range

°C

105

Junction temperature range

1. When the ADC is used, refer to Table 54: ADC characteristics.

2. It is recommended to power V_DDand V_DDAfrom the same source. A maximum difference of 300 mV between V_DDand

V_DDAcan be tolerated during power-up and operation.

3. To sustain a voltage higher than V_DD+0.3 V, the internal pull-up/pull-down resistors must be disabled.

4. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax (see Table 12: Thermal characteristics

on page 53).

5. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax (see Table 12:

Thermal characteristics on page 53).

DocID17659 Rev 12

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104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

6.3.2

Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the

ambient temperature condition summarized in the following table.

Table 14. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

BOR detector enabled

BOR detector disabled

BOR detector enabled

BOR detector disabled

0

-

∞

V_DDrise time rate

1000

µs/V

∞

(1)

t_VDD

20

0

-

V_DDfall time rate

-

1000

V

_DDrising, BOR enabled

-

2

3.3

ms

1.6

(1)

T_RSTTEMPO

Reset temporization

V_DDrising, BOR disabled⁽²⁾

Falling edge

Rising edge

0.4

1

0.7

1.5

1.7

1.65

V

1.65

Power on/power down reset

threshold

V_POR/PDR

V_BOR0

V_BOR1

V_BOR2

V_BOR3

V_BOR4

1.3

1.67

Falling edge

Rising edge

1.74

1.8

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

1.69 1.76

Falling edge

Rising edge

1.87 1.93 1.97

1.96 2.03 2.07

2.22 2.30 2.35

2.31 2.41 2.44

2.45 2.55 2.60

Falling edge

Rising edge

V

Falling edge

Rising edge

2.54 2.66

2.7

Falling edge

Rising edge

2.68

2.78

2.8

2.9

2.85

2.95

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DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

Table 14. Embedded reset and power control block characteristics (continued)

Symbol

Parameter

Conditions

Falling edge

Min

Typ

Max Unit

1.8

1.85 1.88

Programmable voltage detector

threshold 0

V_PVD0

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

BOR0 threshold

1.88 1.94 1.99

1.98 2.04 2.09

2.08 2.14 2.18

2.20 2.24 2.28

2.28 2.34 2.38

2.39 2.44 2.48

2.47 2.54 2.58

2.57 2.64 2.69

2.68 2.74 2.79

2.77 2.83 2.88

2.87 2.94 2.99

2.97 3.05 3.09

3.08 3.15 3.20

V_PVD1

V_PVD2

V_PVD3

V_PVD4

V_PVD5

V_PVD6

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

V

-

40

-

V_hyst

Hysteresis voltage

mV

All BOR and PVD thresholds

excepting BOR0

100

1. Guaranteed by characterization results.

2. Valid for device version without BOR at power up. Please see option "T" in Ordering information scheme for more details.

DocID17659 Rev 12

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104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

6.3.3

Embedded internal reference voltage

The parameters given in the following table are based on characterization results, unless

otherwise specified.

Table 15. Embedded internal reference voltage calibration values

Calibration value name

Description

Memory address

Raw data acquired at

temperature of 30 °C, V_DDA= 3 V

VREFINT_CAL

0x1FF8 0078-0x1FF8 0079

Table 16. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

(1)

V_{REFINT out}

I_REFINT

Internal reference voltage

– 40 °C < T_J< +105 °C 1.202 1.224 1.242

V

Internal reference current

consumption

-

1.4

2

2.3

3

µA

ms

V

T_VREFINT

Internal reference startup time

V_DDAand V_REF+voltage during

V_REFINTfactory measure

V_{VREF_MEAS}

2.99

3

3.01

Including uncertainties

due to ADC and

V_DDA/V_REF+values

Accuracy of factory-measured V_REF

value ⁽²⁾

A_{VREF_MEAS}

-

±5

mV

(3)

T_Coeff

Temperature coefficient

Long-term stability

Voltage coefficient

–40 °C < T_J< +105 °C

1000 hours, T= 25 °C

3.0 V < V_DDA< 3.6 V

-

25

-

100

1000

2000

ppm/°C

ppm

(3)

A_Coeff

(3)

V_DDCoeff

-

ppm/V

ADC sampling time when reading the

internal reference voltage

(3)(4)

T_{S_vrefint}

-

5

-

10

-

µs

µA

Startup time of reference voltage

buffer for ADC

(3)

T_{ADC_BUF}

10

25

Consumption of reference voltage

buffer for ADC

(3)

I_{BUF_ADC}

-

13.5

(3)

I_{VREF_OUT}

VREF_OUT output current⁽⁵⁾

-

1

µA

pF

(3)

C_{VREF_OUT}

VREF_OUT output load

50

Consumption of reference voltage

buffer for VREF_OUT and COMP

(3)

I_LPBUF

-

730 1200

nA

(3)

V_{REFINT_DIV1}

V_{REFINT_DIV2}

V_{REFINT_DIV3}

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

-

24

49

74

25

50

75

26

51 % V_REFINT

76

(3)

1. Tested in production.

2. The internal V_REFvalue is individually measured in production and stored in dedicated EEPROM bytes.

3. Guaranteed by characterization results.

4. Shortest sampling time can be determined in the application by multiple iterations.

5. To guarantee less than 1% VREF_OUT deviation.

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DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

6.3.4

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code. The current consumption is measured as described in Figure 14: Current

consumption measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a

reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

The current consumption values are derived from the tests performed under ambient

temperature TA=25°C and VDD supply voltage conditions summarized in Table 13: General

operating conditions, unless otherwise specified. The MCU is placed under the following

conditions:

The MCU is placed under the following conditions:

•

V

= 3.6 V

DD

All I/O pins are configured in analog input mode.

All peripherals are disabled except when explicitly mentioned

The Flash memory access time, 64-bit access and prefetch is adjusted depending on

fHCLK frequency and voltage range to provide the best CPU performance.

•

When the peripherals are enabled f

= f

APB1

APB2 AHB

When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or

HSE = 16 MHz (if HSE bypass mode is used).

•

The HSE user clock applied to OSC_IN input follows the characteristics specified in

Table 26: High-speed external user clock characteristics.

DocID17659 Rev 12

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104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

Table 17. Current consumption in Run mode, code with data processing running from Flash

Max⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Typ

Unit

55 °C 85 °C 105 °C

1 MHz

2 MHz

4 MHz

8 MHz

270

470

400

600

400

600

400

600

Range 3,

V_CORE=1.2 V

VOS[1:0] = 11

µA

890 1025 1025 1025

f_HSE= f_HCLK

up to 16 MHz,

included

f_HSE= f_HCLK/2

above 16 MHz

(PLL ON)⁽²⁾

1

2

1.3

2.5

5

1.3

2.5

5

1.3

2.5

5

Range 2,

V_CORE=1.5 V

VOS[1:0] = 10

16 MHz 3.9

8 MHz 2.16

16 MHz 4.8

32 MHz 9.6

3

Supply

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01

current in

Run mode,

code

executed

5.5

11

5.5

11

5.5

11

I_{DD (Run}

from

Flash)

Range 2,

mA

from Flash

V_CORE=1.5 V

16 MHz

4

5

VOS[1:0] = 10

HSI clock source

(16 MHz)

Range 1,

V_CORE=1.8 V

32 MHz 9.4

11

VOS[1:0] = 01

MSI clock, 65 kHz

65 kHz 0.05 0.085 0.09

524 kHz 0.15 0.185 0.19

0.1

0.2

1

Range 3,

MSI clock, 524 kHz V_CORE=1.2 V

VOS[1:0] = 11

MSI clock, 4.2 MHz

4.2 MHz 0.9

1

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

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DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

Table 18. Current consumption in Run mode, code with data processing running from RAM

Max⁽¹⁾

Symbol

Parameter

Conditions

f_HCLK

Typ

Unit

55 °C 85 °C 105 °C

1 MHz

2 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

200

380

720

0.9

1.65

3.2

2

300

500

860

1

300

500

300

500

Range 3,

V_CORE=1.2 V

VOS[1:0] = 11

µA

860 860⁽³⁾

f_HSE= f_HCLK

up to 16 MHz,

included

f_HSE= f_HCLK/2

above 16 MHz

(PLL ON)⁽²⁾

1

Range 2,

V_CORE=1.5 V

VOS[1:0] = 10

2

3.7

2.5

4.5

8.5

3.7

2.5

4.5

8.5

3.7

2.5

4.5

8.5

Supply current

in Run mode,

code executed

from RAM,

Flash switched

off

Range 1,

V_CORE=1.8 V

4

I_{DD (Run}

VOS[1:0] = 01

mA

from

7.7

RAM)

Range 2,

V_CORE=1.5 V

16 MHz

3.3

3.8

9.2

3.8

9.2

3.8

9.2

VOS[1:0] = 10

HSI clock source

(16 MHz)

Range 1,

V_CORE=1.8 V

32 MHz

65 kHz

7.8

40

VOS[1:0] = 01

MSI clock, 65 kHz

60

80

Range 3,

MSI clock, 524 kHz V_CORE=1.2 V

524 kHz 110

4.2 MHz 700

140

800

140

800

160

820

µA

VOS[1:0] = 11

MSI clock, 4.2 MHz

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

3. Tested in production.

DocID17659 Rev 12

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104

Electrical characteristics

Symbol Parameter

STM32L151x6/8/B STM32L152x6/8/B

Table 19. Current consumption in Sleep mode

Max⁽¹⁾

Conditions

f_HCLK

Typ

Unit

55 °C 85 °C 105 °C

1 MHz

2 MHz

4 MHz

8 MHz

80

140

210

330

400

550

140

210

330

400

550

140

210

Range 3,

V_CORE=1.2 V

VOS[1:0] = 11

150

280

450

330⁽³⁾

f_HSE= f_HCLKup to

16 MHz included,

f_HSE= f_HCLK/2

400

Range 2,

V_CORE=1.5 V

550

above 16 MHz (PLL VOS[1:0] = 10

Supply

current in

Sleep

mode,

code

executed

from RAM,

Flash

switched

OFF

16 MHz 900 1050 1050 1050

8 MHz 550 650 650 650

ON)⁽²⁾

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01

16 MHz 1050 1200 1200 1200

32 MHz 2300 2500 2500 2500

µA

Range 2,

V_CORE=1.5 V

16 MHz 1000 1100 1100

1100

VOS[1:0] = 10

HSI clock source

(16 MHz)

Range 1,

V_CORE=1.8 V

32 MHz 2300 2500 2500 2500

VOS[1:0] = 01

MSI clock, 65 kHz

65 kHz

30

50

60

80

Range 3,

I_DD

MSI clock, 524 kHz V_CORE=1.2 V

524 kHz 50

4.2 MHz 200

70

(Sleep)

VOS[1:0] = 11

MSI clock, 4.2 MHz

240

140

210

350

400

600

240

140

210

350

400

600

250

140

210

350

400

600

1100

650

1 MHz

2 MHz

4 MHz

8 MHz

80

Range 3,

V_CORE=1.2 V

VOS[1:0] = 11

150

290

300

500

f_HSE= f_HCLKup to

16 MHz included,

f_HSE= f_HCLK/2

Range 2,

V_CORE=1.5 V

Supply

current in

Sleep

above 16 MHz (PLL VOS[1:0] = 10

16 MHz 1000 1100 1100

8 MHz 550 650 650

ON)⁽²⁾

mode,

µA

Range 1,

code

executed

from Flash

V_CORE=1.8 V

VOS[1:0] = 01

16 MHz 1050 1200 1200 1200

32 MHz 2300 2500 2500 2500

Range 2,

V_CORE=1.5 V

16 MHz 1000 1100 1100

1100

VOS[1:0] = 10

HSI clock source

(16 MHz)

Range 1,

V_CORE=1.8 V

32 MHz 2300 2500 2500 2500

VOS[1:0] = 01

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Electrical characteristics

Table 19. Current consumption in Sleep mode (continued)

Max⁽¹⁾

Symbol Parameter

Conditions

f_HCLK

Typ

Unit

55 °C 85 °C 105 °C

Supply

current in

Sleep

MSI clock, 65 kHz

MSI clock, 524 kHz

65 kHz

40

70

90

70

90

80

524 kHz 60

100

Range 3,

I_DD

mode,

code

executed

V_CORE=1.2V

VOS[1:0] = 11

µA

(Sleep)

MSI clock, 4.2 MHz

4.2 MHz 210

250

260

from Flash

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)

3. Tested in production

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104

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Table 20. Current consumption in Low power run mode

Max

Symbol

Parameter

Conditions

Typ

Unit

(1)

T_A= -40 °C to 25 °C

T_A= 85 °C

9

17.5

31

14

22

35

37

48

24

33

48

31

40

54

48

54

56

70

12

24

46

17

29

51

42

65

32

42

64

40

48

70

58

63

65

90

MSI clock, 65 kHz

f_HCLK= 32 kHz

All

T_A= 105 °C

peripherals

OFF, code

executed

from RAM,

Flash

switched

OFF, V_DD

from 1.65 V

to 3.6 V

T_A= -40 °C to 25 °C

T_A= 85 °C

MSI clock, 65 kHz

f_HCLK= 65 kHz

T_A= 105 °C

T_A= -40 °C to 25 °C

T_A= 55 °C

MSI clock, 131 kHz

f_HCLK= 131 kHz

T_A= 85 °C

Supply

T_A= 105 °C

I_{DD (LP}

current in

Low power

run mode

Run)

T_A= -40 °C to 25 °C

T_A= 85 °C

MSI clock, 65 kHz

f_HCLK= 32 kHz

µA

T_A= 105 °C

All

peripherals

OFF, code

executed

from Flash,

V_DDfrom

1.65 V to

3.6 V

T_A= -40 °C to 25 °C

T_A= 85 °C

MSI clock, 65 kHz

f_HCLK= 65 kHz

T_A= 105 °C

T_A= -40 °C to 25 °C

T_A= 55 °C

MSI clock, 131 kHz

f_HCLK= 131 kHz

T_A= 85 °C

T_A= 105 °C

Max allowed

current in

Low power

run mode

I_DDMax

(LP

V_DDfrom

1.65 V to

3.6 V

-

200

Run)⁽²⁾

1. Guaranteed by characterization results, unless otherwise specified.

2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator.

Consumption of the I/Os is not included in this limitation.

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Symbol Parameter

Electrical characteristics

Table 21. Current consumption in Low power sleep mode

Max

Conditions

Typ

Unit

(1)

MSI clock, 65 kHz

f_HCLK= 32 kHz

Flash OFF

T_A= -40 °C to 25 °C 4.4

-

T_A= -40 °C to 25 °C 17.5 25

MSI clock, 65 kHz

f_HCLK= 32 kHz

Flash ON

T_A= 85 °C

22

31

27

39

26

28

40

30

32

34

45

All

T_A= 105 °C

peripherals

T_A= -40 °C to 25 °C 18

OFF, V_DD

from1.65 V

to 3.6 V

MSI clock, 65 kHz

T_A= 85 °C

23

31

f_HCLK= 65 kHz,

Flash ON

T_A= 105 °C

T_A= -40 °C to 25 °C 22

MSI clock, 131 kHz

Supply

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

24

26

34

f_HCLK= 131 kHz,

Flash ON

current in

Low power

sleep

I_DD(LP

Sleep)

mode

T_A= -40 °C to 25 °C 17.5 25

µA

MSI clock, 65 kHz

f_HCLK= 32 kHz

T_A= 85 °C

22

31

27

39

26

28

40

30

32

34

45

T_A= 105 °C

TIM9 and

USART1

enabled,

Flash ON,

V_DDfrom

1.65 V to

3.6 V

T_A= -40 °C to 25 °C 18

MSI clock, 65 kHz

f_HCLK= 65 kHz

T_A= 85 °C

23

31

T_A= 105 °C

T_A= -40 °C to 25 °C 22

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

24

26

34

MSI clock, 131 kHz

f_HCLK= 131 kHz

Max

allowed

current in

(LP Sleep) Low power

V_DDfrom

1.65 V to

3.6 V

I

_DDMax

-

200

Sleep

mode

1. Guaranteed by characterization results, unless otherwise specified.

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104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

Table 22. Typical and maximum current consumptions in Stop mode

Typ Max

Symbol

Parameter

Conditions

Unit

(1)

(1)(2)

T_A= -40°C to 25°C

V_DD= 1.8 V

1.2 2.75

T_A= -40°C to 25°C 1.4

4

LCD

OFF

T_A= 55°C

T_A= 85°C

T_A= 105°C

2.6

4.8

6

10

23

6

10.2

RTC clocked by LSI,

T_A= -40°C to 25°C 3.3

regulator in LP mode,

HSI and HSE OFF

(no independent

watchdog)

LCD ON

(static

T_A= 55°C

T_A= 85°C

T_A= 105°C

4.5

6.6

8

duty)⁽³⁾

12

27

10

12

16

40

4

13.6

T_A= -40°C to 25°C 7.7

LCD ON

(1/8

T_A= 55°C

T_A= 85°C

T_A= 105°C

8.6

duty)⁽⁴⁾

10.7

19.8

T_A= -40°C to 25°C 1.6

Supply current

I_{DD (Stop}in Stop mode

T_A= 55°C

T_A= 85°C

T_A= 105°C

2.7

4.8

6

µA

LCD

OFF

with RTC

enabled

with RTC)

10

23

6

10.3

RTC clocked by LSE

external clock (32.768

kHz), regulator in LP

mode, HSI and HSE

OFF (no independent

watchdog)

T_A= -40°C to 25°C 3.6

LCD ON

(static

T_A= 55°C

T_A= 85°C

T_A= 105°C

4.6

6.7

8

duty)⁽³⁾

12

23

10

12

16

40

10.9

T_A= -40°C to 25°C 7.6

LCD ON

(1/8

T_A= 55°C

T_A= 85°C

T_A= 105°C

8.6

duty)⁽⁴⁾

10.7

19.8

T_A= -40°C to 25°C

V_DD= 1.8 V

1.45

1.9

-

RTC clocked by LSE

(no independent

watchdog)⁽⁵⁾

LCD

OFF

T_A= -40°C to 25°C

V_DD= 3.0 V

T_A= -40°C to 25°C

V_DD= 3.6 V

2.2

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Electrical characteristics

Table 22. Typical and maximum current consumptions in Stop mode (continued)

Typ Max

Symbol

Parameter

Conditions

Unit

(1)

(1)(2)

Regulator in LP mode, HSI and

HSE OFF, independent

watchdog and LSI enabled

T_A= -40°C to 25°C 1.1

T_A= -40°C to 25°C 0.5

2.2

Supply current

in Stop mode

(RTC

0.9

5

I_{DD (Stop)}

µA

Regulator in LP mode, LSI, HSI

and HSE OFF (no independent

watchdog)

T_A= 55°C

T_A= 85°C

T_A= 105°C

1.9

disabled)

3.7

8

8.9 20⁽⁶⁾

RMS (root

MSI = 4.2 MHz

MSI = 1.05 MHz

2

-

mean square)

supply current

duringwakeup

time when

exiting from

Stop mode

1.45

I_{DD (WU}

V_DD= 3.0 V

T_A= -40°C to 25°C

mA

from Stop)

MSI = 65 kHz⁽⁷⁾

1.45

-

1. The typical values are given for V_DD= 3.0 V and max values are given for V_DD= 3.6 V, unless otherwise

specified.

2. Guaranteed by characterization results, unless otherwise specified

3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected

4. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD

connected.

5. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY)

with two 6.8pF loading capacitors.

6. Tested in production

7. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the

remaining time of the wakeup period, the current is similar to the Run mode current.

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104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

Table 23. Typical and maximum current consumptions in Standby mode

Max

Symbol

Parameter

Conditions

Typ⁽¹⁾

Unit

(1)(2)

T_A= -40 °C to 25 °C

V_DD= 1.8 V

0.9

-

T_A= -40 °C to 25 °C

T_A= 55 °C

1.1

1.8

2.5

3

RTC clocked by LSI (no

independent watchdog)

1.42

1.87

2.78

T_A= 85 °C

I_DD

T_A= 105 °C

5

Supply current in Standby

mode with RTC enabled

(Standby

T_A= -40 °C to 25 °C

V_DD= 1.8 V

with RTC)

1

-

T_A= -40 °C to 25 °C

1.33

1.59

2.01

3.27

2.9

3.4

4.3

6.3

RTC clocked by LSE (no

independent watchdog)⁽³⁾T_A= 55 °C

µA

T_A= 85 °C

T_A= 105 °C

Independent watchdog

and LSI enabled

T_A= -40 °C to 25 °C

1.1

1.6

T_A= -40 °C to 25 °C

T_A= 55 °C

0.3

0.5

1

0.55

0.8

I_DD

Supply current in Standby

mode with RTC disabled

(Standby)

Independent watchdog

and LSI OFF

T_A= 85 °C

1.7

T_A= 105 °C

2.5

4⁽⁴⁾

I_{DD (WU}RMS supply current during

V_DD= 3.0 V

T_A= -40 °C to 25 °C

wakeup time when exiting

from Standby mode

-

1

-

from

Standby)

1. The typical values are given for V_DD= 3.0 V and max values are given for V_DD= 3.6 V, unless otherwise specified.

2. Guaranteed by characterization results, unless otherwise specified.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF

loading capacitors.

4. Tested in production.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU

is placed under the following conditions:

•

all I/O pins are in input mode with a static value at V or V (no load)

DD SS

all peripherals are disabled unless otherwise mentioned

the given value is calculated by measuring the current consumption

–

with all peripherals clocked off

with only one peripheral clocked on

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Electrical characteristics

(1)

Table 24. Peripheral current consumption

Typical consumption, V_DD= 3.0 V, T_A= 25 °C

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11

Range 2,

_CORE=1.5 V

Range 3,

_CORE=1.2 V

Peripheral

Unit

Low power

sleep and run

V

TIM2

TIM3

TIM4

TIM6

TIM7

LCD

13

14

12.5

5.5

4

10.5

12

10.5

4.5

5

8

9

10.5

12

11

4.5

5

8

3.5

2.5

4

5

WWDG

3.5

5

3.5

5

SPI2

5.5

9

µA/MHz

APB1

(f_HCLK

)

USART2

USART3

I2C1

8

5.5

6

8.5

8

10.5

8.5

12.5

4.5

9

7

5.5

6.5

3

7.5

6.5

10

3.5

7

I2C2

7

USB

10

4

PWR

DAC

7.5

4

6

COMP

SYSCFG & RI

TIM9

4.5

3

3.5

2

4.5

2.5

7

2.5

7.5

5.5

6

9

6

TIM10

TIM11

ADC⁽²⁾

SPI1

6.5

7

4.5

8

5.5

9

µA/MHz

(f_HCLK

APB2

)

11.5

5

9.5

4.5

7.5

3

4

USART1

9

6

7.5

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(1)

Table 24. Peripheral current consumption (continued)

Typical consumption, V_DD= 3.0 V, T_A= 25 °C

Range 1,

V_CORE=1.8 V

VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11

Range 2,

_CORE=1.5 V

Range 3,

_CORE=1.2 V

Peripheral

Unit

Low power

sleep and run

V

GPIOA

5

4.5

4

3.5

3

4

GPIOB

GPIOC

GPIOD

GPIOE

GPIOH

CRC

4.5

3.5

0.5

18.5

10.5

130

5

AHB

5

µA/MHz

(f_HCLK

)

4

1

0.5

11.5

10

0.5

9

FLASH

DMA1

13

12

166

8

All enabled

I_{DD (RTC)}

I_{DD (LCD)}

138

106

0.47

3.1

1450

340

0.16

2

(3)

I_{DD (ADC)}

(4)

I_{DD (DAC)}

I_{DD (COMP1)}

I_{DD (COMP2)}

µA

Slow mode

Fast mode

5

(5)

I_{DD (PVD / BOR)}

I_{DD (IWDG)}

2.6

0.25

1. Data based on differential I_DDmeasurement between all peripherals OFF an one peripheral with clock enabled, in the

following conditions: f_HCLK= 32 MHz (Range 1), f_HCLK= 16 MHz (Range 2), f_HCLK= 4 MHz (Range 3), f_HCLK= 64kHz

(Low power run/sleep), f_APB1= f_HCLK, f_APB2= f_HCLK, default prescaler value for each peripheral. The CPU is in Sleep

mode in both cases. No I/O pins toggling.

2. HSI oscillator is OFF for this measure.

3. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI

consumption not included).

4. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of

VDD/2. DAC is in buffered mode, output is left floating.

5. Including supply current of internal reference voltage.

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Electrical characteristics

6.3.5

Wakeup time from Low power mode

The wakeup times given in the following table are measured with the MSI RC oscillator. The

clock source used to wake up the device depends on the current operating mode:

•

Sleep mode: the clock source is the clock that was set before entering Sleep mode

Stop mode: the clock source is the MSI oscillator in the range configured before

entering Stop mode

•

Standby mode: the clock source is the MSI oscillator running at 2.1 MHz

All timings are derived from tests performed under ambient temperature and V supply

DD

voltage conditions summarized in Table 13.

Table 25. Low-power mode wakeup timings

Symbol

Parameter

Wakeup from Sleep mode f_HCLK= 32 MHz

_HCLK= 262 kHz

Conditions

Typ Max⁽¹⁾Unit

t_WUSLEEP

0.36

32

-

f

Wakeup from Low power

sleep mode

Flash enabled

t_{WUSLEEP_LP}

f_HCLK= 262 kHz

34

8.2

-

Flash switched OFF

Wakeup from Stop mode,

regulator in Run mode

f_HCLK= f_MSI= 4.2 MHz

Voltage Range 1 and 2

9.3

11.2

f_HCLK= f_MSI= 4.2 MHz

Voltage Range 3

7.8

10

µs

t_WUSTOP

f_HCLK= f_MSI= 2.1 MHz

12

20

Wakeup from Stop mode,

regulator in low power

mode

f_HCLK= f_MSI= 1.05 MHz 15.5

f_HCLK= f_MSI= 524 kHz

f_HCLK= f_MSI= 262 kHz

29

53

35

63

f

_HCLK= f_MSI= 131 kHz

105

210

118

237

f_HCLK= MSI = 65 kHz

Wakeup from Standby

mode

f_HCLK= MSI = 2.1 MHz

50

103

3.2

FWU bit = 1

t_WUSTDBY

Wakeup from Standby

mode

f_HCLK= MSI = 2.1 MHz

2.5

ms

FWU bit = 0

1. Guaranteed by characterization results, unless otherwise specified

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6.3.6

External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The

external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the

recommended clock input waveform is shown in Figure 15: High-speed external clock

source AC timing diagram.

(1)

Table 26. High-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CSS is on or

PLL is used

1

User external clock source

frequency

f_{HSE_ext}

8

32

MHz

CSS is off, PLL

not used

0

V_HSEH

V_HSEL

t_w(HSEH)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

0.7V_DD

V_SS

-

V_DD

V

0.3V_DD

-

OSC_IN high or low time

OSC_IN rise or fall time

12

-

t_w(HSEL)

ns

t_r(HSE)

t_f(HSE)

20

C_in(HSE)OSC_IN input capacitance

DuCy_(HSE)Duty cycle

-

45

-

2.6

-

pF

%

-

55

±1

I_L

OSC_IN Input leakage current

V_SS≤V_IN≤V_DD

µA

1. Guaranteed by design.

Figure 15. High-speed external clock source AC timing diagram

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9

+6(/

W

Uꢑ+6(ꢓ

Iꢑ+6(ꢓ

Zꢑ+6(/ꢓ

7

+6(

06ꢄꢂꢅꢄꢆ9ꢅ

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Electrical characteristics

Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a low-

speed external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 13.

(1)

Table 27. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

User external clock source

frequency

f_{LSE_ext}

1

32.768

1000

kHz

OSC32_IN input pin high level

voltage

V_LSEH

V_LSEL

t_w(LSEH)

0.7V_DD

V_SS

465

-

V_DD

0.3V_DD

-

V

OSC32_IN input pin low level

voltage

-

OSC32_IN high or low time

OSC32_IN rise or fall time

t_w(LSEL)

ns

t_r(LSE)

t_f(LSE)

10

C_IN(LSE)OSC32_IN input capacitance

DuCy_(LSE)Duty cycle

-

45

-

0.6

-

pF

%

-

55

±1

I_L

OSC32_IN Input leakage current V_SS≤V_IN≤V_DD

µA

1. Guaranteed by design.

Figure 16. Low-speed external clock source AC timing diagram

W

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9

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9

/6(/

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Iꢑ/6(ꢓ

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06ꢄꢂꢅꢄꢁ9ꢅ

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 28. In

the application, the resonator and the load capacitors have to be placed as close as

possible to the oscillator pins in order to minimize output distortion and startup stabilization

time. Refer to the crystal resonator manufacturer for more details on the resonator

characteristics (frequency, package, accuracy).

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104

Electrical characteristics

Symbol

STM32L151x6/8/B STM32L152x6/8/B

(1)(2)

Table 28. HSE oscillator characteristics

Parameter

Conditions

Min Typ

Max

Unit

f_{OSC_IN}Oscillator frequency

-

1

24

-

MHz

R_F

Feedback resistor

200

kΩ

Recommended load

capacitance versus

C

R_S= 30 Ω

-

20

-

pF

equivalent serial resistance

of the crystal (R_S)⁽³⁾

V

_DD= 3.3 V, V_IN= V_SS

with 30 pF load

I_HSE

I_DD(HSE)

g_m

HSE driving current

-

3

mA

C = 20 pF

2.5 (startup)

f_OSC= 16 MHz

0.7 (stabilized)

HSE oscillator power

consumption

mA

C = 10 pF

2.5 (startup)

-

3.5

-

f_OSC= 16 MHz

0.46 (stabilized)

mA

/V

Oscillator transconductance

Startup time

Startup

-

t_SU(HSE)

V_DDis stabilized

1

ms

(4)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by characterization results.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a

humid environment, due to the induced leakage and the bias condition change. However, it is

recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer.

For C and C , it is recommended to use high-quality external ceramic capacitors in the

L1

L2

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 17). C and C are usually the

L1

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of C and C . PCB and MCU pin capacitance must be included (10 pF

L1

L2

can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C . Refer to the application note AN2867 “Oscillator design guide for ST

C

L1

L2

microcontrollers” available from the ST website www.st.com.

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Electrical characteristics

Figure 17. HSE oscillator circuit diagram

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1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 29. In

the application, the resonator and the load capacitors have to be placed as close as

possible to the oscillator pins in order to minimize output distortion and startup stabilization

time. Refer to the crystal resonator manufacturer for more details on the resonator

characteristics (frequency, package, accuracy).

(1)

Table 29. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Low speed external oscillator

frequency

f_LSE

R_F

C⁽²⁾

I_LSE

-

32.768

1.2

-

kHz

Feedback resistor

MΩ

Recommended load capacitance

versus equivalent serial

R_S= 30 kΩ

-

8

-

pF

µA

resistance of the crystal (R_S)⁽³⁾

LSE driving current

V_DD= 3.3 V, V_IN= V_SS

V_DD= 1.8 V

-

1.1

450

600

750

-

LSE oscillator current

consumption

I_{DD (LSE)}

V

_DD= 3.0 V

-

nA

V_DD= 3.6V

-

g_m

Oscillator transconductance

Startup time

-

3

-

µA/V

s

(4)

t_SU(LSE)

V_DDis stabilized

1

1. Guaranteed by characterization results.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator

design guide for ST microcontrollers”.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with

small R_Svalue for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.

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4. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary

significantly with the crystal manufacturer.

Note:

For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator (see Figure 18 ).

CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load

capacitance which is the series combination of CL1 and CL2.

Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray

where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically,

it is between 2 pF and 7 pF.

Caution:

To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended

to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load

capacitance of 12.5 pF.

Example: if a resonator is chosen with a load capacitance of CL = 6 pF and Cstray = 2 pF,

then CL1 = CL2 = 8 pF.

Figure 18. Typical application with a 32.768 kHz crystal

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74/133

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Electrical characteristics

6.3.7

Internal clock source characteristics

The parameters given in the following table are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 13.

DD

High-speed internal (HSI) RC oscillator

Table 30. HSI oscillator characteristics

Symbol

Parameter

Frequency

Conditions

Min

Typ Max Unit

f_HSI

V_DD= 3.0 V

-

16

-

MHz

%

Trimming code is not a multiple of 16

Trimming code is a multiple of 16

0.4 0.7

HSI user-trimmed

resolution

(1)(2)

TRIM

-

1.5

%

V

_DDA= 3.0 V, T_A= 25 °C

-1⁽³⁾

-1.5

-2

1⁽³⁾

1.5

2

%

V_DDA= 3.0 V, T_A= 0 to 55 °C

V_DDA= 3.0 V, T_A= -10 to 70 °C

%

Accuracy of the

factory-calibrated

HSI oscillator

(2)

ACC_HSI

V

_DDA= 3.0 V, T_A= -10 to 85 °C

V_DDA= 3.0 V, T_A= -10 to 105 °C

_DDA= 1.65 V to 3.6 V

T_A= -40 to 105 °C

-2.5

-4

2

%

2

%

V

-4

-

3

6

%

µs

µA

HSI oscillator

startup time

(2)

t_SU(HSI)

-

3.7

100

HSI oscillator

power consumption

(2)

I_DD(HSI)

-

140

1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are

multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).

2. Guaranteed by characterization results.

3. Tested in production.

Low-speed internal (LSI) RC oscillator

Table 31. LSI oscillator characteristics

Symbol

Parameter

LSI frequency

Min

Typ

Max

Unit

(1)

f_LSI

26

38

56

kHz

%

LSI oscillator frequency drift

(2)

D_LSI

-10

-

4

0°C ≤T_A≤ 85°C

(3)

t_su(LSI)

LSI oscillator startup time

-

200

510

µs

(3)

I_DD(LSI)

LSI oscillator power consumption

400

nA

1. Tested in production.

2. This is a deviation for an individual part, once the initial frequency has been measured.

3. Guaranteed by design.

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Multi-speed internal (MSI) RC oscillator

Table 32. MSI oscillator characteristics

Symbol

Parameter

Condition

Typ Max Unit

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

-

65.5

131

262

524

1.05

2.1

-

kHz

Frequency after factory calibration, done at

V_DD= 3.3 V and T_A= 25 °C

f_MSI

MHz

4.2

ACC_MSI

Frequency error after factory calibration

0.5

%

MSI oscillator frequency drift

0 °C ≤T_A≤85 °C

(1)

D_TEMP(MSI)

-

3

-

MSI oscillator frequency drift

1.65 V ≤V_DD≤3.6 V, T_A= 25 °C

(1)

D_VOLT(MSI)

2.5 %/V

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

0.75

1

-

1.5

2.5

4.5

8

(2)

I_DD(MSI)

MSI oscillator power consumption

-

µA

15

30

20

15

10

6

t_SU(MSI)

MSI oscillator startup time

µs

5

MSI range 6,

Voltage range 1

and 2

3.5

5

-

MSI range 6,

Voltage range 3

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Electrical characteristics

Table 32. MSI oscillator characteristics (continued)

Symbol

Parameter

Condition

Typ Max Unit

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

-

40

20

10

4

2.5

2

(2)

t_STAB(MSI)

MSI oscillator stabilization time

µs

MSI range 6,

Voltage range 1

and 2

-

2

MSI range 3,

Voltage Range 3

-

3

4

6

Any range to

range 5

f_OVER(MSI)MSI oscillator frequency overshoot

MHz

Any range to

range 6

1. This is a deviation for an individual part, once the initial frequency has been measured.

2. Guaranteed by characterization results.

6.3.8

PLL characteristics

The parameters given in Table 33 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 13.

DD

Table 33. PLL characteristics

Value

Symbol

Parameter

Unit

Min

Typ

Max⁽¹⁾

PLL input clock⁽²⁾

2

45

2

-

24

55

32

MHz

%

f_{PLL_IN}

f_{PLL_OUT}

PLL input clock duty cycle

PLL output clock

MHz

Worst case PLL lock time

PLL input = 2 MHz

t_LOCK

-

100

130

µs

PLL VCO = 96 MHz

Jitter

Cycle-to-cycle jitter

-

± 600

450

ps

I_DDA(PLL)

I_DD(PLL)

Current consumption on V_DDA

Current consumption on V_DD

220

120

µA

150

1. Guaranteed by characterization results.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

the range defined by f_{PLL_OUT}

.

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6.3.9

Memory characteristics

The characteristics are given at T = -40 to 105 °C unless otherwise specified.

A

RAM memory

Table 34. RAM and hardware registers

Symbol

Parameter

Data retention mode⁽¹⁾

Conditions

Min

1.65

Typ

Max Unit

VRM

STOP mode (or RESET)

-

V

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware

registers (only in Stop mode).

Flash memory and data EEPROM

Table 35. Flash memory and data EEPROM characteristics

Symbol

Parameter

Operating voltage

Read / Write / Erase

Conditions

Min

Typ

Max⁽¹⁾Unit

V_DD

-

1.65

-

3.6

V

Programming / erasing time for Erasing

byte / word / double word / half-

page

-

3.28

3.94

t_prog

ms

Programming

Average current during whole

program/erase operation

-

300

1.5

-

µA

I_DD

T_A= 25 °C, V_DD= 3.6 V

Maximum current (peak) during

program/erase operation

2.5

mA

1. Guaranteed by design.

Table 36. Flash memory, data EEPROM endurance and data retention

Value

Symbol

Parameter

Conditions

Unit

Min⁽¹⁾Typ Max

Cycling (erase / write)

Program memory

-

10

300

30

T_A= -40°C to

NCYC⁽²⁾

kcycles

105 °C

Cycling (erase / write)

EEPROM data memory

Data retention (program memory) after

10 kcycles at T_A= 85 °C

TRET = +85 °C

TRET = +105 °C

Data retention (EEPROM data memory)

after 300 kcycles at T_A= 85 °C

30

(2)

t_RET

years

Data retention (program memory) after

10 kcycles at T_A= 105 °C

10

Data retention (EEPROM data memory)

after 300 kcycles at T_A= 105 °C

10

1. Guaranteed by characterization results.

2. Characterization is done according to JEDEC JESD22-A117.

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Electrical characteristics

6.3.10

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

the device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

•

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

•

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 37. They are based on the EMS levels and classes

defined in application note AN1709.

Table 37. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD= 3.3 V, LQFP100, T_A= +25 °C,

f_HCLK= 32 MHz

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

V_FESD

2B

4A

conforms to IEC 61000-4-2

V_DD= 3.3 V, LQFP100, T_A= +25

°C,

f_HCLK= 32 MHz

conforms to IEC 61000-4-4

Fast transient voltage burst limits to be

applied through 100 pF on V_DDand V_SS

pins to induce a functional disturbance

V_EFTB

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

•

Corrupted program counter

Unexpected reset

Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1

second.

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To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 38. EMI characteristics

Max vs. frequency range

Monitored

4 MHz

16 MHz

voltage

32 MHz

voltage

Range 1

Symbol Parameter

Conditions

Unit

frequency band

voltage

Range 3 Range 2

0.1 to 30 MHz

3

-6

4

-5

-7

1

V_DD= 3.3 V,

T_A= 25 °C,

LQFP100 package

compliant with IEC

61967-2

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

18

15

2.5

dBµV

-

S_EMI

Peak level

5

2

6.3.11

Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 39. ESD absolute maximum ratings

Maximum

Symbol

Ratings

Conditions

Packages Class

Unit

value⁽¹⁾

Electrostatic discharge voltage T_A= +25 °C, conforming to

V_ESD(HBM)

All

2

2000

(human body model)

JESD22-A114

V

Electrostatic discharge voltage T_A= +25 °C, conforming to

V_ESD(CDM)

III

500

(charge device model)

JESD22-C101

1. Guaranteed by characterization results.

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Static latch-up

Electrical characteristics

Two complementary static tests are required on six parts to assess the latch-up

performance:

•

A supply overvoltage is applied to each power supply pin

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 40. Electrical sensitivities

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T_A= +105 °C conforming to JESD78A

II level A

6.3.12

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V or

SS

above V (for standard pins) should be avoided during normal product operation.

DD

However, in order to give an indication of the robustness of the microcontroller in cases

when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error, out of spec current

injection on adjacent pins or other functional failure (for example reset, oscillator frequency

deviation, LCD levels, etc.).

The test results are given in Table 41.

Table 41. I/O current injection susceptibility

Functional susceptibility

Symbol

Description

Unit

Negative

injection

Positive

injection

Injected current on all 5 V tolerant (FT) pins

Injected current on any other pin

-5

+0

+5

I_INJ

mA

Note:

It is recommended to add a Schottky diode (pin to ground) to analog pins which may

potentially inject negative currents.

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6.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 42 are derived from tests

performed under conditions summarized in Table 13. All I/Os are CMOS and TTL compliant.

Table 42. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

(1)

V_IL

Input low level voltage

-

Standard I/O

FT I/O

-

0.3V_DD

-

V_IH

Input high level voltage

0.7 V_DD

-

V

(3)

Standard I/O

FT I/O

-

10% V_DD

I/O Schmitt trigger voltage

hysteresis⁽²⁾

V_hys

(4)

5% V_DD

-

V_SS≤V_IN≤V_DD

I/Os with LCD

-

±50

V_SS≤V_IN≤V_DD

I/Os with analog

switches

-

V_SS≤V_IN≤V_DD

I/Os with analog

switches and LCD

-

±50

I_lkg

Input leakage current ⁽⁵⁾

nA

V_SS≤V_IN≤V_DD

I/Os with USB

-

TBD

±50

FT I/O

V_DD≤V_IN≤5V

V_SS≤V_IN≤V_DD

Standard I/Os

R_PU

R_PD

C_IO

Weak pull-up equivalent resistor⁽⁶⁾⁽¹⁾

Weak pull-down equivalent resistor⁽⁶⁾

I/O pin capacitance

V_IN= V_SS

V_IN= V_DD

30

-

45

5

60

-

kΩ

pF

-

1. Tested in production

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization.

3. With a minimum of 200 mV. Based on characterization results.

4. With a minimum of 100 mV. Based on characterization results.

5. The max. value may be exceeded if negative current is injected on adjacent pins.

6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

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Output driving current

Electrical characteristics

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or

source up to ±20 mA (with the non-standard V /V specifications given in Table 43.

OL OH

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

•

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

I

(see Table 11).

VDDΣ

•

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

I

(see Table 11).

VSSΣ

Output voltage levels

Unless otherwise specified, the parameters given in Table 43 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 13. All I/Os are CMOS and TTL compliant.

Table 43. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

(1)(2)

V_OL

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

-

0.4

I_IO= 8 mA

(3)(2)

2.7 V < V_DD< 3.6 V

V_OH

2.4

-

0.45

-

(1)(4)

V_OL

-

I_IO= 4 mA

V

(3)(4)

1.65 V < V_DD< 2.7 V

V_OH

V_DD-0.45

-

(1)(4)

V_OL

1.3

-

I_IO= 20 mA

(3)(4)

2.7 V < V_DD< 3.6 V

V_OH

V_DD-1.3

1. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 11 and the sum of

I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. Tested in production.

3. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in Table 11 and the sum

of I_IO(I/O ports and control pins) must not exceed I_VDD

.

4. Guaranteed by characterization results.

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Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 19 and

Table 44, respectively.

Unless otherwise specified, the parameters given in Table 44 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 13.

(1)

Table 44. I/O AC characteristics

OSPEEDRx

[1:0] bit

Symbol

Parameter

Conditions

Min

Max⁽²⁾

Unit

value⁽¹⁾

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 50 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

C_L= 30 pF, V_DD= 2.7 V to 3.6 V

C_L= 50 pF, V_DD= 1.65 V to 2.7 V

-

400

625

2

f_max(IO)outMaximum frequency⁽³⁾

kHz

ns

00

01

10

t_f(IO)out

Output rise and fall time

t_r(IO)out

f_max(IO)outMaximum frequency⁽³⁾

MHz

ns

1

125

250

10

2

t_f(IO)out

Output rise and fall time

t_r(IO)out

F_max(IO)outMaximum frequency⁽³⁾

MHz

ns

25

125

50

8

t_f(IO)out

Output rise and fall time

t_r(IO)out

F_max(IO)outMaximum frequency⁽³⁾

MHz

11

-

5

t_f(IO)out

Output rise and fall time

t_r(IO)out

30

ns

Pulse width of external

t_EXTIpw

signals detected by the

EXTI controller

-

8

-

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151x6/8/B and STM32L152x6/8/B

reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. The maximum frequency is defined in Figure 19.

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Electrical characteristics

Figure 19. I/O AC characteristics definition

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6.3.14

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, RPU (see Table 45).

Unless otherwise specified, the parameters given in Table 45 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 13.

Table 45. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

(1)

V_IL(NRST)

NRST input low level voltage

NRST input high level voltage

-

0.8

(1)

V_IH(NRST)

1.4

I_OL= 2 mA

V

-

2.7 V < V_DD< 3.6 V

NRST output low level

voltage

(1)

V_OL(NRST)

0.4

I_OL= 1.5 mA

-

10%V_DD

45

1.65 V < V_DD< 2.7 V

NRST Schmitt trigger voltage

hysteresis

(1)

(2)

V_hys(NRST)

R_PU

-

mV

Weak pull-up equivalent

resistor⁽³⁾

V_IN= V_SS

30

60

50

kΩ

(1)

V_F(NRST)

NRST input filtered pulse

-

ns

(1)

V_NF(NRST)

NRST input not filtered pulse

350

1. Guaranteed by design.

2. 200 mV minimum value

3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance is around 10%.

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Figure 20. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 45. Otherwise the reset will not be taken into account by the device.

6.3.15

TIM timer characteristics

The parameters given in Table 46 are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

(1)

Table 46. TIMx characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

-

1

-

t_TIMxCLK

ns

t_res(TIM)

Timer resolution time

f_TIMxCLK= 32 MHz 31.25

-

f_TIMxCLK/2

16

-

0

-

MHz

bit

Timer external clock

frequency on CH1 to CH4

f_EXT

f_TIMxCLK= 32 MHz

Res_TIM

Timer resolution

-

16

16-bit counter clock

period when internal clock

is selected (timer’s

1

65536

t_TIMxCLK

t_COUNTER

f_TIMxCLK= 32 MHz 0.0312

2048

µs

prescaler disabled)

-

65536 × 65536 t_TIMxCLK

134.2

t_{MAX_COUNT}Maximum possible count

f_TIMxCLK= 32 MHz

s

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

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Electrical characteristics

6.3.16

Communication interfaces

I²C interface characteristics

2

I

The STM32L151x6/8/B and STM32L152x6/8/B product line C interface meets the

2

requirements of the standard I C communication protocol with the following restrictions:

SDA and SCL are not “true” open-drain I/O pins. When configured as open-drain, the PMOS

connected between the I/O pin and V is disabled, but is still present.

DD

2

The I C characteristics are described in Table 47. Refer also to Section 6.3.12: I/O current

for more details on the input/output alternate function characteristics

injection characteristics

(SDA and SCL)

.

2

Table 47. I C characteristics

Standard mode I²C⁽¹⁾

Fast mode I²C⁽¹⁾⁽²⁾

Symbol

Parameter

Unit

Min

Max

Min

Max

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

SCL clock high time

SDA setup time

4.7

4.0

250

0

-

1.3

0.6

100

0

-

µs

-

SDA data hold time

900⁽³⁾

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

-

1000

20 + 0.1C_b

300

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

Start condition hold time

-

300

-

300

t_h(STA)

t_su(STA)

4.0

4.7

4.0

4.7

-

0.6

1.3

-

µs

Repeated Start condition

setup time

t_su(STO)

Stop condition setup time

μs

Stop to Start condition time

(bus free)

t_w(STO:STA)

Capacitive load for each bus

line

C_b

-

400

-

400

pF

Guaranteed by design.

1.

2. f_PCLK1must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to

achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast

mode clock.

The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL

signal.

3.

DocID17659 Rev 12

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STM32L151x6/8/B STM32L152x6/8/B

2

Figure 21. I C bus AC waveforms and measurement circuit

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1. R_S= series protection resistors

2. R_P= pull-up resistors

3. V_{DD_I2C}= I2C bus supply

Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD.

4.

(1)(2)

Table 48. SCL frequency (f

f_SCL(kHz)

= 32 MHz, V_DD= V_{DD_I2C}= 3.3 V)

I2C_CCR value

PCLK1

R_P= 4.7 kΩ

400

300

200

100

50

0x801B

0x8024

0x8035

0x00A0

0x0140

0x0320

20

1. R_P= External pull-up resistance, f_SCL= I²C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the

tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external

components used to design the application.

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SPI characteristics

Electrical characteristics

Unless otherwise specified, the parameters given in the following table are derived from

tests performed under ambient temperature, f

frequency and V supply voltage

PCLKx

DD

conditions summarized in Table 13.

Refer to Section 6.3.12: I/O current injection characteristics for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

(1)

Table 49. SPI characteristics

Symbol

Parameter

Conditions

Master mode

Min

Max⁽²⁾Unit

-

16

f_SCK

1/t_c(SCK)

SPI clock frequency

Slave mode

16

MHz

Slave transmitter

12⁽³⁾

(2)

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 30 pF

Slave mode

-

6

ns

%

(2)

SPI slave input clock duty

cycle

DuCy(SCK)

30

70

t_su(NSS)

t_h(NSS)

NSS setup time

NSS hold time

Slave mode

4t_HCLK

2t_HCLK

-

(2)

t_w(SCKH)

t_w(SCKL)

t_SCK/2− t_SCK/2+

SCK high and low time

Data input setup time

Master mode

(2)

5

6

5

3

(2)

t_su(MI)

Master mode

Slave mode

Master mode

Slave mode

-

(2)

t_su(SI)

-

(2)

t_h(MI)

-

ns

Data input hold time

(2)

t_h(SI)

-

(4)

t_a(SO)

Data output access time Slave mode

0

3t_HCLK

(2)

t_v(SO)

Data output valid time

Slave mode

Master mode

Slave mode

Master mode

-

33

6.5

-

(2)

t_v(MO)

-

(2)

t_h(SO)

17

0.5

Data output hold time

(2)

t_h(MO)

-

1. The characteristics above are given for voltage Range 1.

2. Guaranteed by characterization results.

3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty

cycle (DuCy(SCK)) ranging between 40 to 60%.

4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the

data.

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Figure 22. SPI timing diagram - slave mode and CPHA = 0

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1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD.

90/133

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Electrical characteristics

(1)

Figure 24. SPI timing diagram - master mode

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USB characteristics

The USB interface is USB-IF certified (full speed).

Table 50. USB startup time

Symbol

Parameter

Max

Unit

(1)

t_STARTUP

USB transceiver startup time

1

µs

1. Guaranteed by design.

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Table 51. USB DC electrical characteristics

Symbol

Parameter

Conditions

Min.⁽¹⁾

Max.⁽¹⁾Unit

Input levels

V_DD

USB operating voltage⁽²⁾

Differential input sensitivity

-

3.0

0.2

0.8

1.3

3.6

-

V

(3)

V_DI

I(USB_DP, USB_DM)

(3)

V_CM

Differential common mode range Includes V_DIrange

2.5

2.0

(3)

V_SE

Single ended receiver threshold

-

Output levels

(4)

V_OL

V_OH

Static output level low

Static output level high

R_Lof 1.5 kΩ to 3.6 V⁽⁵⁾

-

0.3

3.6

V

(4)

(5)

R_Lof 15 kΩ to V_SS

2.8

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full speed electrical specification, the USB_DP (D+) pin should be pulled

up with a 1.5 kΩresistor to a 3.0-to-3.6 V voltage range.

3. Guaranteed by characterization results.

4. Tested in production.

R_Lis the load connected on the USB drivers.

5.

Figure 25. USB timings: definition of data signal rise and fall time

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Table 52. USB: full speed electrical characteristics

Driver characteristics⁽¹⁾

Symbol

Parameter

Conditions

Min

Max

Unit

t_r

t_f

Rise time⁽²⁾

Fall Time⁽²⁾

C_L= 50 pF

t_r/t_f

4

20

ns

%

V

t_rfm

V_CRS

Rise/ fall time matching

90

1.3

110

2.0

Output signal crossover voltage

1. Guaranteed by design.

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

2.

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Electrical characteristics

6.3.17

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 54 are guaranteed by design.

Table 53. ADC clock frequency

Symbol Parameter

Conditions

Min

Max

Unit

V_{REF+ =}V_DDA

16

V_REF+< V_DDA

8

4

2.4 V ≤V_DDA≤3.6 V V_REF+> 2.4 V

Voltage

Range 1 &

2

V_REF+< V_DDA

V_REF+≤2.4 V

ADC clock

f_ADC

0.480

MHz

frequency

V

_{REF+ =}V_DDA

8

4

1.8 V ≤V_DDA≤2.4 V

V_REF+< V_DDA

Voltage Range 3

Table 54. ADC characteristics

Conditions

Symbol

Parameter

Power supply

Min

Typ

Max

Unit

V_DDA

-

1.8

-

3.6

V

2.4 V ≤V_DDA≤3.6 V

V_REF+must be below

or equal to V_DDA

V_REF+

Positive reference voltage

1.8⁽¹⁾

-

V_DDA

V

V_REF-

I_VDDA

Negative reference voltage

-

V_SSA

1000

-

V

Current on the V_DDAinput

1450

µA

Peak

-

700

450

V_REF+

1

µA

V

Current on the V_REFinput

(2)

I_VREF

400

Average

-

V_AIN

Conversion voltage range⁽³⁾

-

0⁽⁴⁾

0.03

-

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

Direct channels

Multiplexed channels

12-bit sampling rate

Msps

0.76

1.07

0.8

10-bit sampling rate

8-bit sampling rate

6-bit sampling rate

f_S

1.23

0.89

1.45

1

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Electrical characteristics

Symbol

STM32L151x6/8/B STM32L152x6/8/B

Table 54. ADC characteristics (continued)

Parameter

Conditions

Min

Typ

Max

Unit

Direct channels

0.25

-

2.4 V ≤V_DDA≤3.6 V

Multiplexed channels

0.56

1

-

2.4 V ≤V_DDA≤3.6 V

µs

t_S

Sampling time⁽⁵⁾

Direct channels

1.8 V ≤V_DDA≤2.4 V

Multiplexed channels

1.8 V ≤V_DDA≤2.4 V

-

4

1

-

384

1/f_ADC

µs

f_ADC= 16 MHz

24.75

Total conversion time

(including sampling time)

4 to 384 (sampling

phase) +12 (successive

approximation)

t_CONV

-

1/f_ADC

Direct channels

-

Internal sample and hold

capacitor

C_ADC

16

pF

Multiplexed channels

-

12-bit conversions

-

Tconv+1 1/f_ADC

Tconv 1/f_ADC

External trigger frequency

Regular sequencer

f_TRIG

6/8/10-bit conversions

-

12-bit conversions

Tconv+2 1/f_ADC

Tconv+1 1/f_ADC

External trigger frequency

Injected sequencer

f_TRIG

R_AIN

t_lat

6/8/10-bit conversions

-

Signal source impedance⁽⁵⁾

-

50

281

4.5

219

3.5

κΩ

ns

f_ADC= 16 MHz

219

3.5

156

2.5

-

Injection trigger conversion

latency

-

1/f_ADC

ns

f_ADC= 16 MHz

Regular trigger conversion

latency

t_latr

-

1/f_ADC

µs

t_STAB

Power-up time

1. The V_REF+input can be grounded iif neither the ADC nor the DAC are used (this allows to shut down an

external voltage reference).

2. The current consumption through V_REFis composed of two parameters:

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.

So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400

= 450 µA at 1Msps

3. V_REF+can be internally connected to V_DDAand V_REF-can be internally connected to V_SSA, depending on

the package. Refer to Section 4: Pin descriptions for further details.

4. V_SSAmust be tied to ground.

5. See Table 56: Maximum source impedance RAIN max for R_AINlimitation.

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Electrical characteristics

(1)(2)

Table 55. ADC accuracy

Symbol

Parameter

Test conditions

Min⁽³⁾

Typ

Max⁽³⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

-

2

1

4

2

2.4 V ≤ V_DDA≤ 3.6 V

2.4 V ≤ V_REF+≤ 3.6 V

f_ADC= 8 MHz, R_AIN= 50 Ω

T_A= -40 to 105 ° C

-

Gain error

-

1.5

1

3.5

2

LSB

Differential linearity error

Integral linearity error

-

1.7

10

3

ENOB Effective number of bits

9.2

-

bits

dB

2.4 V ≤ V_DDA≤ 3.6 V

Signal-to-noise and

SINAD

V_{DDA =}V_REF+

57.5

62

-

distortion ratio

f_ADC= 16 MHz, R_AIN= 50 Ω

T_A= -40 to 105 ° C

1 kHz ≤ F_input≤ 100 kHz

SNR

THD

ET

Signal-to-noise ratio

Total harmonic distortion

Total unadjusted error

Offset error

57.5

62

-75

4

-

-74

-

6.5

4

2.4 V ≤ V_DDA≤ 3.6 V

1.8 V ≤ V_REF+≤ 2.4 V

EO

EG

ED

EL

2

Gain error

4

6

LSB

f_ADC= 4 MHz, R_AIN= 50 Ω

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

1

2

T_A= -40 to 105 ° C

1.5

2

3

ET

3

1.8 V ≤ V_DDA≤ 2.4 V

1.8 V ≤ V_REF+≤ 2.4 V

f_ADC= 4 MHz, R_AIN= 50 Ω

T_A= -40 to 105 ° C

EO

EG

ED

EL

1

1.5

2

Gain error

1.5

1

Differential linearity error

Integral linearity error

2

1

1.5

1. ADC DC accuracy values are measured after internal calibration.

2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this

significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a

Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 6.3.12 does not affect the ADC

accuracy.

3. Guaranteed by characterization results.

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STM32L151x6/8/B STM32L152x6/8/B

Figure 26. ADC accuracy characteristics

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Figure 27. Typical connection diagram using the ADC

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1. Refer to Table 56: Maximum source impedance RAIN max for the value of R_AINand Table 54: ADC

characteristics for the value of CADC

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high C_parasiticvalue will downgrade conversion accuracy. To remedy

this, f_ADCshould be reduced.

96/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

Figure 28. Maximum dynamic current consumption on V

supply pin during ADC

REF+

conversion

Sampling (n cycles)

Conversion (12 cycles)

ADC clock

I

ref+

700µA

300µA

MS36686V1

(1)

Table 56. Maximum source impedance R

R_AINmax (kOhm)

max

AIN

Ts (cycles)

Ts

(µs)

Multiplexed channels

Direct channels

f

= 16 MHz⁽²⁾

ADC

2.4 V < V_DDA< 3.6 V 1.8 V < V_DDA< 2.4 V 2.4 V < V_DDA< 3.3 V 1.8 V < V_DDA< 2.4 V

0.25

Not allowed

0.8

Not allowed

0.8

0.7

2.0

Not allowed

1.0

4

9

0.5625

1

1.5

3

2.0

4.0

3.0

16

24

48

96

192

384

3.0

1.8

6.0

4.5

6.8

4.0

15.0

30.0

50.0

10.0

6

15.0

32.0

50.0

10.0

20.0

12

24

25.0

40.0

50.0

1. Guaranteed by design.

2. Number of samples calculated for f_ADC= 16 MHz. For f_ADC= 8 and 4 MHz the number of sampling cycles can be

reduced with respect to the minimum sampling time Ts (us).

General PCB design guidelines

Power supply decoupling should be performed as shown in The 10 nF capacitors should be

ceramic (good quality). They should be placed as close as possible to the chip.

DocID17659 Rev 12

97/133

104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

Figure 29. Power supply and reference decoupling (V

not connected to V

)

DDA

REF+

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1. V_REF+and V_REF–inputs are available only on 100-pin packages.

Figure 30. Power supply and reference decoupling (V

connected to V

)

DDA

REF+

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1. V_REF+and V_REF–inputs are available only on 100-pin packages.

98/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

6.3.18

DAC electrical specifications

Data guaranteed by design, unless otherwise specified.

Table 57. DAC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDA

Analog supply voltage

-

1.8

-

3.6

V

V_DDA

_REF+must always be below

V_REF+

V_REF-

Reference supply voltage

Lower reference voltage

1.8

-

3.6

V

-

V_SSA

V

Current consumption on No load, middle code (0x800)

V_REF+supply

-

130

220

210

320

220

350

320

520

µA

(1)

I_DDVREF+

No load, worst code (0x000)

µA

V_REF+= 3.3 V

Current consumption on No load, middle code (0x800)

V_DDAsupply

-

(1)

I_DDA

No load, worst code (0xF1C)

-

V_DDA= 3.3 V

Connected to V_SSA

DACoutput

5

-

R_L

Resistive load

buffer ON

kΩ

Connected to V_DDA25

-

C_L

Capacitive load

DAC output buffer ON

-

50

20

pF

R_O

Output impedance

DAC output buffer OFF

12

16

kΩ

DAC output buffer ON

0.2

-

V_DDA– 0.2

V

Voltage on DAC_OUT

output

V_{DAC_OUT}

V_REF+

1LSB

–

DAC output buffer OFF

0.5

-

mV

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

1.5

3

Differential non

linearity⁽²⁾

DNL⁽¹⁾

No R_LOAD, C_L≤ 50 pF

-

1.5

2

3

4

DAC output buffer OFF

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

INL⁽¹⁾

Integral non linearity⁽³⁾

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

LSB

2

4

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

±10

±5

±25

±8

±5

Offset error at code

0x800 ⁽⁴⁾

Offset⁽¹⁾

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

Offset error at code

0x001⁽⁵⁾

Offset1⁽¹⁾

±1.5

DocID17659 Rev 12

99/133

104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

Table 57. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDA= 3.3V, T_A= 0 to 50 °C

DAC output buffer OFF

-20

-10

0

Offset error temperature

coefficient (code 0x800)

dOffset/dT⁽¹⁾

µV/°C

V_DDA= 3.3V, T_A= 0 to 50 °C

DAC output buffer ON

0

20

50

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

+0.1 /

-0.2%

+0.2 / -

0.5%

-

Gain⁽¹⁾

Gain error⁽⁶⁾

%

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

+0 / -0.2% +0 / -0.4%

V_DDA= 3.3V, T_A= 0 to 50 °C

DAC output buffer OFF

-10

-40

-

-2

-8

12

8

0

Gain error temperature

coefficient

dGain/dT⁽¹⁾

µV/°C

LSB

V_DDA= 3.3V, T_A= 0 to 50 °C

DAC output buffer ON

C_L≤ 50 pF, R_L≥ 5 kΩ

DAC output buffer ON

30

12

TUE⁽¹⁾

Total unadjusted error

No R_LOAD, C_L≤ 50 pF

DAC output buffer OFF

-

Settling time (full scale:

for a 12-bit code

transition between the

lowest and the highest

input codes till

DAC_OUT reaches final

value ±1LSB

t_SETTLING

C_L≤ 50 pF, R_L≥ 5 kΩ

-

7

12

µs

Max frequency for a

correct DAC_OUT

change (95% of final

value) with 1 LSB

variation in the input

code

Update rate

C_L≤ 50 pF, R_L≥ 5 kΩ

-

1

Msps

Wakeup time from off

state (setting the ENx bit

in the DAC Control

register)⁽⁷⁾

t_WAKEUP

C_L≤ 50 pF, R_L≥ 5 kΩ

-

9

15

µs

V_DDAsupply rejection

ratio (static DC

measurement)

PSRR+

-60

-35

dB

1. Guaranteed by characterization results.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x800) and the ideal value = V/2.

5. Difference between the value measured at Code (0x001) and the ideal value.

6. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when

buffer is OFF, and from code giving 0.2 V and (V_DDA– 0.2) V when buffer is ON.

7. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

100/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

Figure 31. 12-bit buffered /non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

loads directly without the use of an external operational amplifier. The buffer can be bypassed by

configuring the BOFFx bit in the DAC_CR register.

6.3.19

Temperature sensor characteristics

Table 58. Temperature sensor calibration values

Calibration value name

Description

Memory address

TS ADC raw data acquired at

temperature of 30 °C,

TS_CAL1

0x1FF8 007A-0x1FF8 007B

V_DDA= 3 V

TS ADC raw data acquired at

temperature of 110 °C

V_DDA= 3 V

TS_CAL2

0x1FF8 007E-0x1FF8 007F

Table 59. Temperature sensor characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(1)

T_L

V_SENSElinearity with temperature

-

1.48

612

-

1

1.61

626.8

3.4

2

1.75

641.5

6

°C

mV/°C

mV

Avg_Slope⁽¹⁾Average slope

V₁₁₀

Voltage at 110°C ±5°C⁽²⁾

(3)

I_DDA(TEMP)

Current consumption

Startup time

µA

(3)

t_START

-

10

µs

ADC sampling time when reading the

temperature

(4)(3)

T_{S_temp}

10

-

1. Guaranteed by characterization results.

2. Measured at V_DD= 3 V ±10 mV. V110 ADC conversion result is stored in the TS_CAL2 byte.

3. Guaranteed by design.

4. Shortest sampling time can be determined in the application by multiple iterations.

DocID17659 Rev 12

101/133

104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

6.3.20

Comparator

Table 60. Comparator 1 characteristics

Symbol

Parameter

Conditions

Min⁽¹⁾Typ

Max⁽¹⁾

Unit

V_DDA

R_400K

R_10K

Analog supply voltage

R_400Kvalue

-

1.65

3.6

V

-

400

10

-

kΩ

R_10Kvalue

Comparator 1 input

voltage range

V_IN

-

0.6

-

V_DDA

V

t_START

td

Comparator startup time

Propagation delay⁽²⁾

Comparator offset

-

7

3

10

µs

Voffset

mV

V_DDA= 3.6 V

V_IN+= 0 V

Comparator offset

d_Voffset/dt variation in worst voltage

stress conditions

0

-

1.5

10

mV/1000 h

nA

V_IN-= V_REFINT

T_A= 25 °C

I_COMP1

Current consumption⁽³⁾

-

160

260

1. Guaranteed by characterization results.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-

inverting input set to the reference.

3. Comparator consumption only. Internal reference voltage not included.

102/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Electrical characteristics

Table 61. Comparator 2 characteristics

Symbol

Parameter

Conditions

Min Typ Max⁽¹⁾Unit

V_DDA

V_IN

Analog supply voltage

-

1.

-

3.6

V_DDA

20

25

3.5

6

V

Comparator 2 input voltage range

0

-

Fast mode

-

15

20

1.8

2.5

0.8

1.2

4

t_START

Comparator startup time

Slow mode

1. V ≤V_DDA≤2.7 V

2.7 V ≤V_DDA≤3.6 V

1. V ≤V_DDA≤2.7 V

2.7 V ≤V_DDA≤3.6 V

-

t_{d slow}

Propagation delay⁽²⁾in slow mode

µs

2

t_{d fast}

Propagation delay⁽²⁾in fast mode

Comparator offset error

4

V_offset

20

mV

V_DDA= 3.3V

T_A= 0 to 50 °C

dThreshold/ Threshold voltage temperature

V- = V_REFINT

3/4 V_REFINT

1/2 V_REFINT

,

ppm

/°C

-

15

100

dt

coefficient

,

1/4 V_REFINT

Fast mode

Slow mode

-

3.5

0.5

5

2

I_COMP2

Current consumption⁽³⁾

µA

1. Guaranteed by characterization results.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-

inverting input set to the reference.

3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not

included.

DocID17659 Rev 12

103/133

104

Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

6.3.21

LCD controller (STM32L152xx only)

The STM32L152xx embeds a built-in step-up converter to provide a constant LCD reference

voltage independently from the V voltage. An external capacitor C must be connected

DD

ext

to the V

pin to decouple this converter.

LCD

Table 62. LCD controller characteristics

Symbol

Parameter

LCD external voltage

Min

Typ

Max

Unit

V_LCD

V_LCD0

V_LCD1

V_LCD2

V_LCD3

V_LCD4

V_LCD5

V_LCD6

V_LCD7

C_ext

-

2.6

3.6

LCD internal reference voltage 0

LCD internal reference voltage 1

LCD internal reference voltage 2

LCD internal reference voltage 3

LCD internal reference voltage 4

LCD internal reference voltage 5

LCD internal reference voltage 6

LCD internal reference voltage 7

V_LCDexternal capacitance

-

2.73

2.86

2.98

3.12

3.26

3.4

-

V

-

3.55

-

0.1

2

µF

µA

Supply current at V_DD= 2.2 V

-

3.3

-

(1)

I_LCD

Supply current at V_DD= 3.0 V

-

3.1

-

(2)

R_Htot

Low drive resistive network overall value

High drive resistive network total value

Segment/Common highest level voltage

Segment/Common 3/4 level voltage

Segment/Common 2/3 level voltage

Segment/Common 1/2 level voltage

Segment/Common 1/3 level voltage

Segment/Common 1/4 level voltage

Segment/Common lowest level voltage

5.28

6.6

7.92

MΩ

kΩ

V

(2)

R_L

192

240

288

V₄₄

V₃₄

V₂₃

V₁₂

V₁₃

V₁₄

V₀

-

V_LCD

3/4 V_LCD

2/3 V_LCD

1/2 V_LCD

1/3 V_LCD

1/4 V_LCD

-

V

-

0

Segment/Common level voltage error

ΔVxx⁽³⁾

-

50

mV

T_A= -40 to 85 °C

1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD

connected

2. Guaranteed by design.

3. Guaranteed by characterization results.

104/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Package information

7

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specification

s, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

7.1

LQFP100 14 x 14 mm, 100-pin low-profile quad flat package

information

Figure 32. LQFP100 14 x 14 mm, 100-pin low-profile quad flat package outline

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1. Drawing is not to scale.

DocID17659 Rev 12

105/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

Table 63. LQPF100 14 x 14 mm, 100-pin low-profile quad flat package mechanical

data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

-

1.600

0.150

1.450

0.270

0.200

16.200

14.200

-

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

-

0.050

1.350

0.170

0.090

15.800

13.800

-

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

-

1.400

0.220

-

0.0551

0.0087

-

c

D

16.000

14.000

12.000

16.000

14.000

12.000

0.500

0.600

1.000

3.5°

0.6299

0.5512

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

D1

D3

E

15.800

13.800

-

16.200

14.200

-

0.6220

0.5433

-

0.6378

0.5591

-

E1

E3

e

-

L

0.450

-

0.750

-

0.0177

-

0.0295

-

L1

k

0.0°

-

7.0°

0.0°

7.0°

ccc

-

0.080

-

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

106/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Package information

Figure 33. LQPF100 14 x 14 mm, 100-pin low-profile quad flat package recommended

footprint

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1. Dimensions are in millimeters.

LQFP100 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Figure 34. LQFP100 14 x 14 mm, 100-pin package top view example

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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

DocID17659 Rev 12

107/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

7.2

LQFP64 10 x 10 mm, 64-pin low-profile quad flat package

information

Figure 35. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline

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3,1ꢌꢄ

H

,'(17,),&$7,21

ꢁ:B0(B9ꢀ

1. Drawing is not to scale.

Table 64. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical

data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Typ

Min

Max

A

A1

A2

b

-

1.600

-

0.0630

0.050

-

0.150

0.0020

-

0.0059

1.350

1.400

0.220

-

1.450

0.0531

0.0551

0.0087

-

0.0571

0.170

0.270

0.0067

0.0106

c

0.090

0.200

0.0035

0.0079

D

-

12.000

10.000

7.500

12.000

10.000

-

0.4724

0.3937

0.2953

0.4724

0.3937

-

D1

D3

E

E1

108/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Package information

Table 64. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical

data (continued)

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Typ

Min

Max

E3

e

-

7.500

0.500

3.5°

-

0.2953

0.0197

3.5°

-

7°

-

7°

K

0°

L

0.450

0.600

1.000

-

0.750

-

0.0177

0.0236

0.0394

-

0.0295

-

L1

ccc

-

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 36. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package recommended

footprint

ꢆꢇ

ꢋꢋ

ꢊꢄꢋ

ꢊꢄꢅ

ꢆꢉ

ꢋꢃ

ꢁꢃꢄꢌ

ꢁꢊꢄꢋ

ꢌꢄꢇ

ꢁꢌ

ꢈꢆ

ꢁꢄꢃ

ꢁꢈ

ꢁ

ꢁꢃꢄꢌ

AIꢁꢆꢉꢊꢉC

1. Dimensions are in millimeters.

DocID17659 Rev 12

109/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

LQFP64 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Figure 37. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example

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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

110/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Package information

7.3

LQFP48 7 x 7 mm, 48-pin low-profile quad flat package

information

Figure 38. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package outline

3%!4).'

0,!.%

#

ꢊꢄꢃꢅ MM

'!5'% 0,!.%

CCC

#

$

,

$ꢁ

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,ꢁ

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B

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0). ꢁ

)$%.4)&)#!4)/.

ꢁ

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E

ꢅ"?-%?6ꢃ

1. Drawing is not to scale.

DocID17659 Rev 12

111/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

Table 65. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

-

1.600

0.150

1.450

0.270

0.200

9.200

7.200

-

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

-

0.050

1.350

0.170

0.090

8.800

6.800

-

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

-

1.400

0.220

-

0.0551

0.0087

-

c

D

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

0.3543

0.2756

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

D1

D3

E

8.800

6.800

-

9.200

7.200

-

0.3465

0.2677

-

0.3622

0.2835

-

E1

E3

e

-

L

0.450

-

0.750

-

0.0177

-

0.0295

-

L1

k

0°

7°

0°

7°

ccc

-

0.080

-

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 39. LQFP48 7 x 7 mm, 48-pin low-profile quad flat recommended footprint

ꢊꢄꢅꢊ

ꢁꢄꢃꢊ

ꢊꢄꢋꢊ

ꢋꢈ

ꢃꢅ

ꢋꢌ

ꢃꢆ

ꢊꢄꢃꢊ

ꢌꢄꢋꢊ

ꢉꢄꢌꢊ ꢅꢄꢇꢊ

ꢌꢄꢋꢊ

ꢆꢇ

ꢁꢋ

ꢁꢃ

ꢁ

ꢁꢄꢃꢊ

ꢅꢄꢇꢊ

ꢉꢄꢌꢊ

AIꢁꢆꢉꢁꢁD

1. Dimensions are in millimeters.

112/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

LQFP48 device marking

Package information

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Figure 40. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package top view example

3URGXFW

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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

DocID17659 Rev 12

113/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

7.4

UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information

Figure 41. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline

3LQꢌꢄꢌLGHQWLILHU

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'

$

(

<

(

6HDWLQJꢌ

SODQH

7

GGG

$ꢄ

E

H

'HWDLOꢌ<

'

([SRVHGꢌSDGꢌ

DUHD

'ꢅ

ꢄ

/

ꢆꢃ

&ꢌꢇꢎꢁꢇꢇ[ꢆꢁ

SLQꢄꢌFRUQHU

5ꢌꢇꢎꢄꢅꢁꢌW\Sꢎ

'HWDLOꢌ=

(ꢅ

ꢄ

ꢆꢃ

=

$ꢇ%ꢂB0(B9ꢀ

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and

solder this back-side pad to PCB ground.

114/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Package information

Table 66. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

0.500

0.000

6.900

5.500

0.300

-

0.550

0.020

7.000

5.600

0.400

0.152

0.250

0.500

-

0.600

0.050

7.100

5.700

0.500

-

0.0197

0.0000

0.2717

0.2165

0.0118

-

0.0217

0.0008

0.2756

0.2205

0.0157

0.0060

0.0098

0.0197

-

0.0236

0.0020

0.2795

0.2244

0.0197

-

A1

D

E

D2

E2

L

T

b

0.200

-

0.300

-

0.0079

-

0.0118

-

e

ddd

-

0.080

-

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 42. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package recommended footprint

ꢌꢄꢋꢊ

ꢈꢄꢃꢊ

ꢆꢇ

ꢋꢌ

ꢁ

ꢋꢈ

ꢅꢄꢈꢊ

ꢊꢄꢃꢊ

ꢌꢄꢋꢊ

ꢅꢄꢇꢊ

ꢈꢄꢃꢊ

ꢅꢄꢈꢊ

ꢊꢄꢋꢊ

ꢁꢃ

ꢃꢅ

ꢁꢋ

ꢃꢆ

ꢊꢄꢌꢅ

ꢊꢄꢅꢊ

ꢊꢄꢅꢅ

ꢅꢄꢇꢊ

!ꢊ"ꢉ?&0?6ꢃ

1. Dimensions are in millimeters.

DocID17659 Rev 12

115/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

UFQFPN48 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Figure 43. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example

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3

06ꢀꢊꢊꢄꢀ9ꢄ

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

116/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Package information

7.5

UFBGA100 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch

ball grid array package information

Figure 44. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package outline

= 6HDWLQJꢌSODQH

GGG =

$ꢆ

$ꢅ

$

$ꢀ

$ꢄ

$

(ꢄ

;

$ꢄꢌEDOOꢌ

(

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H

)

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'

H

<

0

ꢄꢅ

ꢄ

EꢌꢑꢄꢇꢇꢌEDOOVꢓ

HHH 0 = < ;

III 0 =

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723ꢌ9,(:

$ꢇ&ꢅB0(B9ꢆ

1. Drawing is not to scale.

Table 67. UFBGA100 7 x 7 mm, 0.5 mm pitch, package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

A3

A4

b

-

0.6

0.11

0.5

-

0.0236

0.0043

0.0197

0.0071

0.0146

0.0118

0.2776

0.2185

0.2776

0.2185

-

0.05

0.4

0.08

0.27

0.2

6.95

5.45

6.95

5.45

-

0.08

0.45

0.13

0.32

0.25

7

0.002

0.0157

0.0031

0.0106

0.0079

0.2736

0.2146

0.2736

0.2146

-

0.0031

0.0177

0.0051

0.0126

0.0098

0.2756

0.2165

0.2756

0.2165

0.0197

0.0295

-

0.18

0.37

0.3

D

7.05

5.55

7.05

5.55

-

D1

E

5.5

7

E1

e

5.5

0.5

0.75

-

F

0.7

-

0.8

0.0276

-

0.0315

0.0039

ddd

0.1

DocID17659 Rev 12

117/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

Table 67. UFBGA100 7 x 7 mm, 0.5 mm pitch, package mechanical data (continued)

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

eee

fff

-

0.15

0.05

-

0.0059

0.002

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 45. UFBGA100 7 x 7 mm, 0.5 mm pitch, package recommended footprint

'SDG

'VP

$ꢇ&ꢅB)3B9ꢄ

Table 68. UFBGA100 7 x 7 mm, 0.5 mm pitch, recommended PCB design rules

Dimension Recommended values

Pitch

Dpad

0.5

0.280 mm

0.370 mm typ. (depends on the soldermask

registration tolerance)

Dsm

Stencil opening

Stencil thickness

0.280 mm

Between 0.100 mm and 0.125 mm

118/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

UFBGA100 device marking

Package information

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

Figure 46. UFBGA100 7 x 7 mm, 0.5 mm pitch, package top view example

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3

06ꢀꢊꢊꢄꢆ9ꢅ

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

DocID17659 Rev 12

119/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

7.6

TFBGA64 5 x 5 mm, 0.5 mm pitch, thin fine-pitch ball

grid array package information

Figure 47. TFBGA64 5 x 5 mm, 0.5 mm pitch, package outline

$

(ꢄ

(

)

H

+

)

H

'

'ꢄ

EꢌꢑꢊꢆꢌEDOOVꢓ

HHH 0 & % $

III 0 &

%

$

ꢄ

ꢃ

$ꢄꢌEDOOꢌ

723ꢌ9,(:

6,'(ꢌ9,(:

%27720ꢌ9,(:

LQGH[ꢌDUHD

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& 6HDWLQJꢌSODQH

GGG &

$ꢆ

$ꢅ

$ꢄ

$

5ꢃB0(B9ꢆ

1. Drawing is not to scale.

Table 69. TFBGA64 5 x 5 mm, 0.5 mm pitch, package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

A4

b

-

1.200

-

0.0472

0.150

-

0.0059

-

0.200

-

0.0079

-

0.600

-

0.0236

0.250

0.300

5.000

3.500

5.000

3.500

0.500

0.750

-

0.350

0.0098

0.0118

0.1969

0.1378

0.1969

0.1378

0.0197

0.0295

-

0.0138

D

4.850

5.150

0.1909

0.2028

D1

E

-

4.850

5.150

0.1909

0.2028

E1

e

-

F

-

ddd

0.080

0.0031

120/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Package information

Table 69. TFBGA64 5 x 5 mm, 0.5 mm pitch, package mechanical data (continued)

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

eee

fff

-

0.15

0.05

-

0.0059

0.002

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 48. TFBGA64, 5 x 5 mm, 0.5 mm pitch, recommended footprint

'SDG

'VP

06ꢄꢃꢂꢊꢁ9ꢅ

Table 70. TFBGA64 5 x 5 mm, 0.5 mm pitch, recommended PCB design rules

Dimension Recommended values

Pitch

Dpad

0.5

0.27 mm

0.35 mm typ. (depends on the soldermask

registration tolerance)

Dsm

Solder paste

0.27 mm aperture diameter.

DocID17659 Rev 12

121/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

TFBGA64 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

Figure 49. TFBGA64 5 x 5 mm, 0.5 mm pitch, package top view example

3URGXFWꢌLGHQWLILFDWLRQ^ꢑꢄꢓ

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5

06Yꢀꢊꢊꢄꢁ9ꢄ

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

122/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Package information

7.7

Thermal characteristics

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max × Θ )

J

A

D

JA

Where:

•

T max is the maximum ambient temperature in ° C,

A

Θ

is the package junction-to-ambient thermal resistance, in °C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (V × I ) + Σ((V – V ) × I ),

OL OL DD OH OH

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 71. Thermal characteristics

Parameter

Symbol

Value

Unit

Thermal resistance junction-ambient

BGA100 - 7 x 7 mm

59

Thermal resistance junction-ambient

LQFP100 - 14 x 14 mm / 0.5 mm pitch

46

65

45

55

16

Thermal resistance junction-ambient

TFBGA64 - 5 x 5 mm

Θ

°C/W

JA

Thermal resistance junction-ambient

LQFP64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

UFQFPN48 - 7 x 7 mm / 0.5 mm pitch

DocID17659 Rev 12

123/133

132

Package information

STM32L151x6/8/B STM32L152x6/8/B

Figure 50. Thermal resistance

ꢀꢇꢇꢇꢎꢇꢇ

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7-ꢌ!ꢌ7-ꢌPD[

ꢅꢁꢇꢇꢎꢇꢇ

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84)3ꢆꢃꢌꢋ[ꢋꢌPP

/4)3ꢆꢃꢌꢋ[ꢋꢌPP

3'ꢌꢑP:ꢓ

ꢄꢁꢇꢇꢎꢇꢇ

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/4)3ꢊꢆꢌꢄꢇ[ꢄꢇꢌPP

/4)3ꢄꢇꢇꢌꢄꢆ[ꢄꢆꢌPP

8)%*$ꢄꢇꢇꢌꢋ[ꢋꢌPP

7)%*$ꢊꢆꢌꢁ[ꢁꢌPP

ꢇ ꢎꢇꢇ

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06Yꢀꢁꢂꢃꢊ9ꢄꢌ

7.7.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

124/133

DocID17659 Rev 12

STM32L151x6/8/B STM32L152x6/8/B

Ordering information

8

Ordering information

Table 72. Ordering information scheme

Example:

STM32 L 151 C 8

T

6

T

TR

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

L = Low power

Device subfamily

151: Devices without LCD

152: Devices with LCD

Pin count

C = 48 pins

R = 64 pins

V = 100 pins

Flash memory size

6 = 32 Kbytes of Flash memory

8 = 64 Kbytes of Flash memory

B = 128 Kbytes of Flash memory

Package

H = BGA

T = LQFP

U = UFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C

Options

No character = V_DDrange: 1.8 to 3.6 V and BOR enabled

T = V_DDrange: 1.65 to 3.6 V and BOR disabled

Packing

TR = tape and reel

No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

DocID17659 Rev 12

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Revision history

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9

Revision history

Table 73. Document revision history

Date

Revision

Changes

02-Jul-2010

1

Initial release.

Removed 5 V tolerance (FT) from PA3, PB0 and PC3 in Table 8:

STM32L15xx6/8/B pin definitions

Updated Table 14: Embedded reset and power control block

characteristics

01-Oct-2010

16-Dec-2010

2

3

Updated Table 16: Embedded internal reference voltage

Added Table 53: ADC clock frequency

Updated Table 54: ADC characteristics

Modified consumptions on page 1 and in Section 3.1: Low power

modes

LED_SEG8 removed on PB6.

Updated Section 6: Electrical characteristics

VFQFPN48 replaced by UFQFPN48

Section 3.3.2: Power supply supervisor: updated note.

Table 8: STM32L15xx6/8/B pin definitions: modified main function

(after reset) and alternate function for OSC_IN and OSC_OUT pins;

modified footnote 5; added footnote to OSC32_IN and OSC32_OUT

pins; C1 and D1 removed on PD0 and PD1 pins (TFBGA64

column).

Section 3.11: DAC (digital-to-analog converter): updated bullet list.

Table 10: Voltage characteristics on page 52: updated footnote 3

regarding I_INJ(PIN)

.

Table 11: Current characteristics on page 52: updated footnote 4

regarding positive and negative injection.

Table 14: Embedded reset and power control block characteristics

on page 54: updated typ and max values for T_RSTTEMPO(V_DD

rising, BOR enabled).

Table 17: Current consumption in Run mode, code with data

processing running from Flash on page 58: removed values for HSI

clock source (16 MHz), Range 3.

25-Feb-2011

4

Table 18: Current consumption in Run mode, code with data

processing running from RAM on page 59: removed values for HSI

clock source (16 MHz), Range 3.

Table 19: Current consumption in Sleep mode on page 60 removed

values for HSI clock source (16 MHz), Range 3 for both RAM and

Flash; changed units.

Table 20: Current consumption in Low power run mode on page 62:

updated parameter and max value of I_DDMax (LP Run).

Table 21: Current consumption in Low power sleep mode on

page 63: updated symbol, parameter, and max value of I_DDMax (LP

Sleep).

Table 22: Typical and maximum current consumptions in Stop mode

on page 64 updated values for I_{DD (Stop with RTC)}- RTC clocked by

LSE external clock (32.768 kHz), regulator in LP mode, HSI and

HSE OFF (no independent watchdog).

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Revision history

Table 73. Document revision history (continued)

Date

Revision

Changes

Updated Table 23: Typical and maximum current consumptions in

Standby mode on page 66 (I_DD(WU from Standby) instead of (I_DD

(WU from Stop).

Table 25: Low-power mode wakeup timings on page 69: updated

condition for Wakeup from Stop mode, regulator in Run mode;

updated max values for Wakeup from Stop mode, regulator in low

power mode; updated max values for t_WUSTDBY

.

Table 24: Peripheral current consumption on page 67: updated

values for column Low power sleep and run; updated Flash values;

renamed ADC1 to ADC; updated I_{DD (LCD)}value; updated units;

added values for I_{DD (RTC)}and I_{DD (IWDG)}; updated footnote 1 and 3;

added foot note 2 concerning ADC.

Table 26: High-speed external user clock characteristics on

page 70: added min value for t_{w(HSE) w(HSE)}

time; added max value for t_r(HSE)/t_f(HSE)OSC_IN rise or fall time;

updated I_Lfor typ and max values.

/t

OSC_IN high or low

Table 27: Low-speed external user clock characteristics on page 71:

updated max value for I_L.

Table 28: HSE oscillator characteristics on page 72: renamed i₂as

I_HSEand updated max value; updated max values for I_DD(HSE)

Table 29: LSE oscillator characteristics (fLSE = 32.768 kHz) on

page 73: updated max value for I_LSE

Table 30: HSI oscillator characteristics on page 75: updated some

.

4

25-Feb-2011

(continued)

min and max values for ACC_HSI

Table 32: MSI oscillator characteristics on page 76: updated

parameter, typ, and max values for D_VOLT(MSI)

Table 35: Flash memory and data EEPROM characteristics on

page 78: updated typ values for t_prog

.

Table 44: I/O AC characteristics on page 84: updated some max

values for 01, 10, and 11; updated min value; updated footnotes.

Table 55: ADC accuracy on page 95: updated typ values and some

of the test conditions for ENOB, SINAD, SNR, and THD.

Table 57: DAC characteristics on page 99: updated footnote 7 and

added footnote 8.

Updated leakage value in Figure 27: Typical connection diagram

using the ADC.

Added Figure 28: Maximum dynamic current consumption on

VREF+ supply pin during ADC conversion.

Added Table 56: R_AINmax for f_ADC= 16 MHz on page 98

Figure 29: Power supply and reference decoupling (VREF+ not

connected to VDDA): replaced all 10 nF capacitors with 100 nF

capacitors.

Figure 30: Power supply and reference decoupling (VREF+

connected to VDDA): replaced 10 nF capacitor with 100 nF

capacitor.

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Table 73. Document revision history (continued)

Date

Revision

Changes

Modified 1st page (low power features)

Added STM32L15xC6 and STM32L15xR6 devices (32 Kbytes of

Flash memory).

Modified Section 3.6: GPIOs (general-purpose inputs/outputs) on

page 22

17-June-2011

5

Modified Section 6.3: Operating conditions on page 53

Modified Table 55: ADC accuracy on page 95, Table 57: DAC

characteristics on page 99 and Table 60: Comparator 1

characteristics on page 102

Features: updated internal multispeed low power RC.

Table 2: Ultralow power STM32L15xx6/8/B device features and

peripheral counts: LCD 4x44 and 8x40 available for both 64- and

128-Kbyte devices; two comparators available for all devices.

Table 3: Functionalities depending on the operating power supply

range: added footnote 1.

Figure 8: STM32L15xCx UFQFPN48 pinout: replaced VFQPN48 by

UFQFPN48 as name of package.

Table 8: STM32L15xx6/8/B pin definitions: replaced PH0/PH1 by

PC14/PC15.

Table 9: Alternate function input/output: removed EVENT OUT from

PH2 port, AFIO15 column.

Table 19: Current consumption in Sleep mode: updated MSI

conditions and f_HCLK

.

Table 20: Current consumption in Low power run mode: updated

some temperature conditions; added footnote 2.

Table 21: Current consumption in Low power sleep mode: updated

some temperature conditions and one of the MSI clock conditions.

Table 22: Typical and maximum current consumptions in Stop

mode: updated I_DD(WU from Stop) parameter.

25-Jan-2012

6

Table 23: Typical and maximum current consumptions in Standby

mode: updated I_DD(WU from Standby) parameter.

Table 25: Low-power mode wakeup timings: updated f_HCLKvalue

for t_{WUSLEEP_LP}; updated typical value of parameter “Wakeup from

Stop mode, regulator in Run mode”.

Table 24: Peripheral current consumption: replaced GPIOF by

GPIOH.

Table 33: PLL characteristics: updated “PLL output clock”

Table 35: Flash memory and data EEPROM characteristics:

updated all information for I_DD

.

Figure 19: I/O AC characteristics definition: replaced the falling

edge “t_r(IO)out” by “t_f(IO)out”.

Table 47: I2C characteristics: amended footnote 2.

Table 54: ADC characteristics: updated f_Smax value for direct

channels, 6-bit sampling rate.

Table 55: ADC accuracy: Updated the first, third and fourth f_ADCtest

condition.

Table 59: Temperature sensor characteristics: updated typ, min,

and max values of the T_{S_temp}parameter.

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Revision history

Table 73. Document revision history (continued)

Date

Revision

Changes

Updated cover page.

Updated Section 3.10: ADC (analog-to-digital converter)

Updated Table 3: Functionalities depending on the operating power

supply range, added Table 4: CPU frequency range depending on

dynamic voltage scaling and Table 5: Working mode-dependent

functionalities (from Run/active down to standby).

Updated Table 27: Low-speed external user clock

characteristicsAdded footnote 2. in Table 14: Embedded reset and

power control block characteristics

Updated Table 22: Typical and maximum current consumptions in

Stop mode and Table 23: Typical and maximum current

consumptions in Standby mode

Updated footnote 4. in Table 22: Typical and maximum current

consumptions in Stop mode

26-Oct-2012

7

Updated Table 44: I/O AC characteristics

Updated Table 47: I2C characteristics

Updated Table 49: SPI characteristics

Updated Section 6.3.9: Memory characteristics

Updated “non-robust” Table 54: ADC characteristics

Removed the note “position of 4.7 µf capacitor” in Section 6.1.6:

Power supply scheme

Updated Table 66: UFQFPN48 7 x 7 mm, 0.5 mm pitch, ultra thin

fine-pitch quad flat no-lead package mechanical data

Updated Table 65: LQFP48 7 x 7 mm, 48-pin low-profile quad flat

package mechanical data

Added the resistance of TFBGA in Table 71: Thermal characteristics

Added Figure 50: Thermal resistance

Removed AHB1/AHB2 in Figure 1: Ultralow power

STM32L15xx6/8/B block diagram

Added IWDG and WWDG rows in Table 5: Working mode-

dependent functionalities (from Run/active down to standby).

Updated I_DD(Supply current during wakeup time from Standby

mode) in Table 23: Typical and maximum current consumptions in

Standby mode

The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16

MHz)" replaced by "fHSE = fHCLK up to 16 MHz included, fHSE =

fHCLK/2 above 16 MHz (PLL ON)(2)” in Table 19: Current

consumption in Sleep mode

07-Feb-2013

8

Updated Stop mode current to 1.2 µA in Ultra-low-power platform

Updated entire Section 7: Package information

Removed alternate function “I2C2_SMBA” for GPIO pin “PH2” in

Table 8: STM32L15xx6/8/B pin definitions

Updated Table 27: Low-speed external user clock characteristics

and definition of symbol “R_AIN” in Table 54: ADC characteristics

Removed first sentence in I2C interface characteristics

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Table 73. Document revision history (continued)

Date

Revision

Changes

Changed voltage Range 1 minimum to 1.71 V and updated dynamic

voltage scaling range in Table 3: Functionalities depending on the

operating power supply range

Updated LCD and ADC features in Table 2: Ultralow power

STM32L15xx6/8/B device features and peripheral counts.

Updated Table 3: Functionalities depending on the operating power

supply range.

Updated Table 5: Working mode-dependent functionalities (from

Run/active down to standby).

Updated Figure 3: STM32L15xVx UFBGA100 ballout

Added Table 7: Legend/abbreviations used in the pinout table.

Updated Table 8: STM32L15xx6/8/B pin definitions

Updated Figure 10: Pin loading conditions and Figure 11: Pin input

voltage. Updated Figure 12: Power supply scheme.

Replaced “Σ” by “σ” in Section 6.1.1 and Section 6.1.2.

Updated Table 10: Voltage characteristics.

Updated Table 13: General operating conditions.

Added Section 6.1.7: Optional LCD power supply scheme.

Updated Table 16: Embedded internal reference voltage.

Added this Note in Section : High-speed external clock generated

from a crystal/ceramic resonator

Updated Section : Functional susceptibility to I/O current injection.

This Section 6.3.5: Wakeup time from Low power mode was

previously a paragraph in Section 6.3.4: Supply current

characteristics.

12-Nov-2013

9

Updated f_HSEconditions in Table 17: Current consumption in Run

mode, code with data processing running from Flash and Table 18:

Current consumption in Run mode, code with data processing

running from RAM. Fixed IDD unit in Table 23: Typical and

maximum current consumptions in Standby mode.

This Figure 15: High-speed external clock source AC timing

diagram was moved up (was previously after Figure 16: Low-speed

external clock source AC timing diagram.

Updated first sentence in Section 6.3.14: NRST pin characteristics.

Updated Table 25: Low-power mode wakeup timings title.

Updated Table 26: High-speed external user clock characteristics

Updated Table 28: HSE oscillator characteristics and Table 29: LSE

oscillator characteristics (fLSE = 32.768 kHz).

Updated Section 6.3.11: Electrical sensitivity characteristics title.

Updated Table 39: ESD absolute maximum ratings.

Updated Table 41: I/O current injection susceptibility and Table 42:

I/O static characteristics.

Updated Figure 21: I2C bus AC waveforms and measurement

circuit.

Removed any occurrence of “when 8 pins are sourced at same

time” in Table 43: Output voltage characteristics.

Updated section link in second paragraph of Section 6.3.15: TIM

timer characteristics.

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Revision history

Table 73. Document revision history (continued)

Date

Revision

Changes

Updated Table 54: ADC characteristics and Figure 27: Typical

connection diagram using the ADC.

Table 58: Temperature sensor calibration values was previously in

Section 3.10.1: Temperature sensor. Updated Table 59:

Temperature sensor characteristics.

In Table 61: Comparator 2 characteristics, parameter dThreshold/dt,

replaced any occurrence of “VREF+” by “V_REFINT”Updated

Table 63: LQPF100 14 x 14 mm, 100-pin low-profile quad flat

package mechanical data, Table 64: LQFP64 10 x 10 mm 64-pin

low-profile quad flat package mechanical data, Table 65: LQFP48 7

x 7 mm, 48-pin low-profile quad flat package mechanical data and

Table 66: UFQFPN48 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch

quad flat no-lead package mechanical data.

9

12-Nov-2013

(continued)

Updated Figure 33: LQFP100 recommended footprint.

Updated Figure 46: TFBGA64 - 5.0x5.0x1.2 mm, 0.5 mm pitch, thin

fine-pitch ball grid array package outline title.

Remove minimum and typical values of A dimension in Table 67:

UFBGA100 7 x 7 x 0.6 mm 0.5 mm pitch, ultra thin fine-pitch ball

grid array package mechanical data

Deleted second footnote in Figure 42: UFQFPN48 recommended

footprint.

Updated Section 8: Ordering information title and added first

sentence.

Changed BOR disabled option identifier in Table 72: Ordering

information scheme.

Updated Figure 14, Figure 15.

Updated Table 5.

22-Jul-2014

10

Updated Figure 6.3.4.

Updated note 5 inside Table 54.

Updated Ro value inside Table 54.

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Revision history

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Table 73. Document revision history (continued)

Date

Revision

Changes

Updated DMIPS features in cover page and Section 2: Description.

Updated Table 8: STM32L151x6/8/B and STM32L152x6/8/B pin

definitions and Table 9: Alternate function input/output putting

additional functions.

Updated package top view marking in Section 7.1: Package

mechanical data.

30-Jan-2015

11

Updated Figure 9: Memory map.

Updated Table 56: Maximum source impedance RAIN max adding

note 2.

Updated Table 72: Ordering information scheme.

Updated Section 7: Package information structure: Paragraph titles

and paragraph heading level.

Updated Section 7: Package information for all package device

markings, adding text for device orientation versus pin 1/ ball A1

identifier.

Updated Figure 34: LQFP100 14 x 14 mm, 100-pin package top

view example removing gate mark.

Updated Table 64: LQFP64 10 x 10 mm, 64-pin low-profile quad flat

package mechanical data.

Updated Section 7.5: UFBGA100 7 x 7 mm, 0.5 mm pitch, ultra thin

fine-pitch ball grid array package information adding Table 68:

UFBGA100 7 x 7 mm, 0.5 mm pitch, recommended PCB design

rules and Figure 45: UFBGA100 7 x 7 mm, 0.5 mm pitch, package

recommended footprint.

Updated Section 7.6: TFBGA64 5 x 5 mm, 0.5 mm pitch, thin fine-

pitch ball grid array package information adding Table 70: TFBGA64

5 x 5 mm, 0.5 mm pitch, recommended PCB design rules and

changing Figure 48: TFBGA64, 5 x 5 mm, 0.5 mm pitch,

recommended footprint.

28-Apr-2016

12

Updated Table 16: Embedded internal reference voltage

temperature coefficient at 100ppm/°C.

Updated note 3 below Table 16.

Updated Table 61: Comparator 2 characteristics new maximum

threshold voltage temperature coefficient at 100ppm/°C.

Updated Table 39: ESD absolute maximum ratings CDM class.

Updated all the notes, removing ‘not tested in production’.

Updated Table 10: Voltage characteristics adding note about V_REF-

pin.

Updated Table 5: Working mode-dependent functionalities (from

Run/active down to standby) LSI and LSE functionalities putting “Y”

in Standby mode.

Removed note 1 below Figure 2: Clock tree.

Updated Table 57: DAC characteristics resistive load.

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型号：	STM32L152x6
厂家：	ST
描述：	Reset and supply management
文件：	总133页 (文件大小：2086K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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