STM32L412RBY6PXXX [STMICROELECTRONICS]
Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 100DMIPS, up to 128KB Flash, 40KB SRAM, analog, ext. SMPS;
| 型号： | STM32L412RBY6PXXX |
| 厂家： | 
ST |
| 描述： | Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 100DMIPS, up to 128KB Flash, 40KB SRAM, analog, ext. SMPS 静态存储器 |
| 文件： | 总192页 (文件大小：2689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32L412xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,
up to 128KB Flash, 40KB SRAM, analog, ext. SMPS
Datasheet - production data
Features
• Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply
WLCSP36
(2.6x3.1 mm)
LQFP32 (7x7 mm)
LQFP48 (7x7 mm)
LQFP64 (10x10 mm)
UFQFPN32 (5x5 mm)
UFQFPN48 (7x7 mm)
UFBGA64 (5x5 mm)
– -40 °C to 85/125 °C temperature range
– 300 nA in V
mode: supply for RTC and
BAT
– PLL for system clock
32x32-bit backup registers
• Up to 52 fast I/Os, most 5 V-tolerant
– 16 nA Shutdown mode (4 wakeup pins)
– 32 nA Standby mode (4 wakeup pins)
– 245 nA Standby mode with RTC
– 0.7 µA Stop 2 mode, 0.95 µA with RTC
– 79 µA/MHz run mode (LDO Mode)
• RTC with HW calendar, alarms and calibration
• Up to 12 capacitive sensing channels: support
touchkey, linear and rotary touch sensors
• 10x timers: 1x 16-bit advanced motor-control,
1x 32-bit and 2x 16-bit general purpose, 1x 16-
bit basic, 2x low-power 16-bit timers (available
in Stop mode), 2x watchdogs, SysTick timer
– 28 μA/MHz run mode (@3.3 V SMPS
Mode)
– Batch acquisition mode (BAM)
– 4 µs wakeup from Stop mode
– Brown out reset (BOR)
• Memories
– 128 KB single bank Flash, proprietary code
readout protection
– Interconnect matrix
®
®
– 40 KB of SRAM including 8 KB with
hardware parity check
• Core: Arm 32-bit Cortex -M4 CPU with FPU,
Adaptive real-time accelerator (ART
– Quad SPI memory interface with XIP
capability
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 80 MHz,
MPU, 100DMIPS and DSP instructions
• Rich analog peripherals (independent supply)
• Performance benchmark
– 2x 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
– 1.25 DMIPS/MHz (Drystone 2.1)
®
– 2x operational amplifiers with built-in PGA
– 1x ultra-low-power comparator
– 273.55 CoreMark (3.42 CoreMark/MHz @
80 MHz)
– Accurate 2.5 V or 2.048 V reference
voltage buffered output
• Energy benchmark
®
– 442 ULPMark-CP
®
• 12x communication interfaces
– 165 ULPMark-PP
– USB 2.0 full-speed crystal less solution
with LPM and BCD
• Clock Sources
– 4 to 48 MHz crystal oscillator
– 3x I2C FM+(1 Mbit/s), SMBus/PMBus
– 3x USARTs (ISO 7816, LIN, IrDA, modem)
– 1x LPUART (Stop 2 wake-up)
– 2x SPIs (and 1x Quad SPI)
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
– IRTIM (Infrared interface)
• 14-channel DMA controller
– Internal 48 MHz with clock recovery
• True random number generator
November 2020
DS12469 Rev 8
1/192
This is information on a product in full production.
www.st.com
STM32L412xx
• CRC calculation unit, 96-bit unique ID
• All packages are ECOPACK2 compliant
• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
Table 1. Device summary
Reference
STM32L412xx
Part numbers
STM32L412CB, STM32L412KB, STM32L412RB, STM32L412TB
STM32L412C8, STM32L412K8, STM32L412R8, STM32L412T8
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Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 16
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 19
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 36
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 36
3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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3.17 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.18 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.19 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.2 General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 41
3.20.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.20.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.20.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.20.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.21 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 43
3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.23 Universal synchronous/asynchronous receiver transmitter (USART) . . . 45
3.24 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 46
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.26 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.27 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.28 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.29 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.29.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.29.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 79
Embedded reset and power control block characteristics . . . . . . . . . . . 79
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.7
6.3.8
6.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 137
6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 138
6.3.19 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.20 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.22
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
BAT
6.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.24 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 157
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
7.1
7.2
7.3
7.4
7.5
7.6
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
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7.7
7.8
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.8.1
7.8.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 187
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32L412xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13
Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 17
STM32L412xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32L412xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STM32L412xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STM32L412xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
STM32L412xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 70
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 79
Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 85
Current consumption in Run modes, code with data processing running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
Table 26.
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current consumption in Run modes, code with data processing running from Flash,
ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . . 88
Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Current consumption in Run, code with data processing running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . . . . . 90
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 91
Typical current consumption in Run, with different codes running from Flash,
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Typical current consumption in Run, with different codes running from Flash,
Table 33.
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.00 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Typical current consumption in Run modes, with different codes running from
Table 34.
Table 35.
DS12469 Rev 8
7/192
9
List of tables
STM32L412xx
Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . 93
Table 36.
Table 37.
Table 38.
Table 39.
Typical current consumption in Run modes, with different codesrunning from
Flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V). . . . . . . . . 94
Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical current consumption in Run, with different codes running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . . . . . 95
Typical current consumption in Run, with different codes running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.00 V). . . . . . . . . . . . . . . . . . 95
Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . . 96
Current consumption in Sleep, Flash ON and power supplied by external SMPS
Table 40.
Table 41.
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . . 97
Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LSE
HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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List of tables
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
V
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
BAT
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
LQFP64 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
UFBGA64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . 170
LQFP48 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
WLCSP36 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 100. WLCSP36 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 101. UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 102. LQFP32 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 103. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 104. STM32L412xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 105. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
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9
List of figures
STM32L412xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32L412xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(1)
STM32L412Rx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
(1)
STM32L412Rx, external SMPS, LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
(1)
STM32L412Rx UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
(1)
STM32L412Rx UFBGA64, external SMPS, ballout
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
(1)
STM32L412Cx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
(1)
Figure 10. STM32L412Cx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. STM32L412Tx WLCSP36 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 12. STM32L412Tx, external SMPS, WLCSP36 ballout
Figure 13. STM32L412Kx LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
(1)
(1)
Figure 14. STM32L412Kx UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 15. STM32L412xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 16. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 17. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 18. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 19. Current consumption measurement scheme with and without external
SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 20. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 21. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 22. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 23. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 24. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 25. HSI16 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 26. Typical current consumption versus MSI frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 27. HSI48 frequency versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 28. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
(1)
Figure 29. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 30. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 31. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 32. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 34. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 35. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 36. Quad SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 37. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 38. LQFP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 39. LQFP64 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 40. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 41. LQFP64 (external SMPS device) marking (package top view). . . . . . . . . . . . . . . . . . . . . 168
Figure 42. UFBGA64 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 43. UFBGA64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 44. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 45. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 46. LQFP48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 47. LQFP48 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
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List of figures
Figure 48. LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 49. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 50. UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 51. UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 52. WLCSP36 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 53. WLCSP36 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 54. WLCSP36 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 55. UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 56. UFQFPN32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 57. UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 58. LQFP32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 59. LQFP32 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 60. LQFP32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
DS12469 Rev 8
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11
Introduction
STM32L412xx
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L412xx microcontrollers.
This document should be read in conjunction with the STM32L41x, STM32L42x,
STM32L43x, STM32L44x, STM32L45x, STM32L46x reference manual (RM0394), available
from the STMicroelectronics website www.st.com.
®(a)
®
®
For information on the Arm
Cortex -M4 core, refer to the Cortex -M4 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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Description
2
Description
The STM32L412xx devices are ultra-low-power microcontrollers based on the
®
®
high-performance Arm Cortex -M4 32-bit RISC core operating at a frequency of up to
80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision that
®
supports all Arm single-precision data-processing instructions and data types. It also
implements a full set of DSP instructions and a memory protection unit (MPU) which
enhances application security.
The STM32L412xx devices embed high-speed memories (Flash memory up to 128
Kbyte,40 Kbyte of SRAM), a Quad SPI Flash memories interface (available on all packages)
and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two
AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L412xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.
The devices offer two fast 12-bit ADC (5 Msps), two comparators, one operational amplifier,
a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to
motor control, four general-purpose 16-bit timers, and two 16-bit low-power timers.
In addition, up to 12 capacitive sensing channels are available.
They also feature standard and advanced communication interfaces, namely three I2Cs,
two SPIs, three USARTs and one Low-Power UART, one USB full-speed device crystal
less.
The STM32L412xx operates in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V V power supply when using
DD
internal LDO regulator and a 1.00 to 1.32V V
power supply when using external SMPS
DD12
supply. A comprehensive set of power-saving modes makes possible the design of low-
power applications.
Some independent power supplies are supported: analog independent supply input for
ADC, OPAMP and comparator. A VBAT input makes it possible to backup the RTC and
backup registers. Dedicated V
power supplies can be used to bypass the internal LDO
DD12
regulator when connected to an external SMPS.
The STM32L412xx family offers six packages from 32 to 64-pin packages.
Table 2. STM32L412xx family device features and peripheral counts
Peripheral
Flash memory
128KB
64KB
128KB
64KB
Yes
128KB
40KB
64KB
128KB
64KB
SRAM
Quad SPI
DS12469 Rev 8
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49
Description
STM32L412xx
Table 2. STM32L412xx family device features and peripheral counts (continued)
Peripheral
Advanced
control
1 (16-bit)
2 (16-bit)
1 (32-bit)
General
purpose
Basic
1 (16-bit)
2 (16-bit)
1
Timers
Low -power
SysTick timer
Watchdog
timers
(independent,
window)
2
SPI
I2C
2
3
1
2
Comm.
interfac
es
USART
LPUART
3
1
2
1
USB FS
Yes
Yes
RTC
Tamper pins
2
2
1
2
Random generator
GPIOs(1)
Wakeup pins
Yes
52
4
38
3
30
2
26
2
Capacitive sensing
Number of channels
12
6
2
12-bit ADC
2
2
2
Number of channels
10
10
10
16
Internal voltage
reference buffer
No
Analog comparator
Operational amplifiers
Max. CPU frequency
Operating voltage (VDD
Operating voltage
1
1
80 MHz
1.71 to 3.6 V
)
1.00 to 1.32 V
(VDD12
)
Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
Junction temperature: -40 to 105 °C / -40 to 130 °C
Operating temperature
Packages
LQFP64
LQFP48
UFQFPN32
LQFP32
WLCSP36
UFBGA64
UFQFPN48
1. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS
power supplies hence reducing the number of available GPIO's by 2.
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STM32L412xx
Description
Figure 1. STM32L412xx block diagram
D0[3:0],
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
D1[3:0],
CLK0,
CLK1
CS
Quad SPI memory interface
MPU
JTAG & SW
ETM
NVIC
TRACECLK
D-BUS
TRACED[3:0]
ARM Cortex-M4
80 MHz
I-BUS
S-BUS
FPU
RNG
Flash
up to
128 KB
SRAM2 8 KB
SRAM1 32 KB
Power management
VDD
AHB2 80 MHz
DMA2
Voltage
regulator
3.3 to 1.2 V
VDD = 1.71 to 3.6 V
VSS
DMA1
@ VDD
@ VDD
Supply
supervision
reset
Int
MSI
7 Groups of
VDDUSB
RC HSI
RC LSI
Touch sensing controller
GPIO PORT A
BOR
4 channels max as AF
VDDA, VSSA
VDD, VSS, NRST
PA[15:0]
PB[15:0]
PC[15:0]
PD2
PVD, PVM
@VDD
PLL 1&2
HSI48
GPIO PORT B
GPIO PORT C
OSC_IN
OSC_OUT
XTAL OSC
4- 16MHz
IWDG
VBAT = 1.55 to 3.6 V
GPIO PORT D
GPIO PORT H
Standby
interface
@VBAT
PH[1:0],
PH[3]
Reset & clock
control
OSC32_IN
XTAL 32 kHz
RTC
AWU
Backup register
OSC32_OUT
@ VDD
RTC_TS
RTC_TAMPx
RTC_OUT
Temperature sensor
TIM2
32b
4 channels, ETR as AF
CRC
@ VDDA
ADC1
@ VDDUSB
DP
DM
NOE
16 external analog inputs
16 external analog inputs
USB FS
ITF
ADC2
CRS_SYNC
CRS
@ VDDA
smcard
IrDA
USART2
RX, TX, CK, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
VREF+
83 AF
VREF Buffer
AHB/APB2
AHB/APB1
smcard
IrDA
USART3
EXT IT. WKUP
TIM1 / PWM
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF
16b
SPI2
MOSI, MISO, SCK, NSS as AF
WWDG
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
2 channels,
16b
16b
TIM15
TIM16
1 compl. channel, BKIN as AF
1 channel,
1 compl. channel, BKIN as AF
smcard
IrDA
RX, TX, CK,CTS,
RTS as AF
USART1
TIM6
16b
MOSI, MISO,
SCK, NSS as AF
SPI1
@VDDA
VOUT, VINM, VINP
OpAmp1
LPUART1
RX, TX, CTS, RTS as AF
@ VDDA
COMP1
INP, INM, OUT
LPTIM1
LPTIM2
IN1, IN2, OUT, ETR as AF
IN1, OUT, ETR as AF
FIREWALL
MSv45999V2
Note:
AF: alternate function on I/O pins.
DS12469 Rev 8
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49
Functional overview
STM32L412xx
3
Functional overview
3.1
Arm® Cortex®-M4 core with FPU
®
®
®
The Arm Cortex -M4 with FPU processor is the latest generation of Arm processors for
embedded systems, developed to provide a low-cost platform that meets the needs of MCU
implementation with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
®
®
The Arm Cortex -M4 with FPU 32-bit RISC processor features exceptional code-
®
efficiency, delivering the high-performance expected from an Arm core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions enabling efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
®
®
With its embedded Arm core, the STM32L412xx family is compatible with all Arm tools
and software.
Figure 1 shows the general block diagram of the STM32L412xx family devices.
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
®
®
®
Arm Cortex -M4 processors. It balances the inherent performance advantage of the Arm
®
Cortex -M4 over Flash memory technologies, which normally requires the processor to wait
for the Flash memory at higher frequencies.
To release the processor near 100 DMIPS performance at 80 MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 80 MHz.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole
4 Gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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Functional overview
3.4
Embedded Flash memory
STM32L412xx devices feature 128Kbyte of embedded Flash memory available for storing
programs and data in single bank architecture.The Flash memory contains 64 pages of 2
Kbyte
Flexible protections can be configured thanks to option bytes:
•
Readout protection (RDP) to protect the whole memory. Three levels are available:
–
–
Level 0: no readout protection
Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
–
Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial
wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
Debug, boot from RAM or boot
User execution
Protection
level
from system memory (loader)
Area
Read
Write
Erase
Read
Write
Erase
1
2
1
2
1
2
1
2
1
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
N/A
Yes
N/A
Yes
N/A
No
No
N/A
No
No
N/A
No
Main
memory
System
memory
No
No
N/A
Yes
N/A
No
N/A
Yes
Yes
No
Yes
No
Option
bytes
N/A
N/A(1)
N/A
No(1)
N/A
Yes
Yes
Yes
Yes
N/A(1)
N/A
Yes(1)
Yes
Backup
registers
N/A
No
N/A
No
SRAM2
N/A
N/A
1. Erased when RDP change from Level 1 to Level 0.
•
•
Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 2-Kbyte granularity.
Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)
allows the user to select if the PCROP area is erased or not when the RDP protection
is changed from Level 1 to Level 0.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•
•
single error detection and correction
double error detection.
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49
Functional overview
STM32L412xx
The address of the ECC fail can be read in the ECC register.
3.5
Embedded SRAM
STM32L412xx devices feature 40 Kbyte of embedded SRAM, split into two blocks:
•
•
32 Kbyte mapped at address 0x2000 0000 (SRAM1)
8 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2000 8000, offering a contiguous address
space with the SRAM1 (8 Kbyte aliased by bit band)
This block is accessed through the ICode/DCode buses for maximum performance.
These 8 Kbyte SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6
Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The Firewall main features are the following:
•
Three segments can be protected and defined thanks to the Firewall registers:
–
Code segment (located in Flash or SRAM1 if defined as executable protected
area)
–
–
Non-volatile data segment (located in Flash)
Volatile data segment (located in SRAM1)
•
•
The start address and the length of each segments are configurable:
–
–
–
Code segment: up to 1024 Kbyte with granularity of 256 bytes
Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
Volatile data segment: up to 128 Kbyte with a granularity of 64 bytes
Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)
•
•
Volatile data segment can be shared or not with the non-protected code
Volatile data segment can be executed or not depending on the Firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
3.7
Boot modes
At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select
one of three boot options:
•
•
•
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
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STM32L412xx
Functional overview
BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
A Flash empty check mechanism is implemented to force the boot from system flash if the
first flash memory location is not programmed and if the boot selection is configured to boot
from main flash.
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART, I2C, SPI or USB FS in Device mode through DFU (device firmware upgrade).
3.8
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.9
Power supply management
3.9.1
Power supply schemes
•
V
= 1.71 to 3.6 V: external power supply for I/Os (V
), the internal regulator and
DD
DDIO1
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.
•
V
= 1.00 to 1.32 V: external power supply bypassing internal regulator when
DD12
connected to an external SMPS. It is provided externally through VDD12 pins and only
available on packages with the external SMPS supply option. VDD12 does not require
any external decoupling capacitance and cannot support any external load.
•
V
= 1.62 V (ADC/COMP) / 1.8 (OPAMP) to 3.6 V: external analog power supply for
DDA
ADC, OPAMP, Comparator. The V
voltage.
voltage level is independent from the V
DDA
DD
•
•
V
V
= 3.0 to 3.6 V: external independent power supply for USB transceivers. The
DDUSB
DDUSB
voltage level is independent from the V voltage.
DD
V
= 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
Note:
Note:
Note:
When the functions supplied by V
are not used, this supply should preferably be shorted
DDA
to V
.
DD
If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V
tolerant.
V
V
is the I/Os general purpose digital functions supply. V
represents V , with
DDIO1
DDIOx
DDIO1
DDIOx
= V
.
DD
DS12469 Rev 8
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49
Functional overview
STM32L412xx
Figure 2. Power supply overview
VDDA domain
A/D converters
VDDA
VSSA
Comparators
Operational amplifiers
Voltage reference buffer
VDDUSB
VSS
USB transceivers
VDD domain
VDDIO1
I/O ring
VDD
Reset block
Temp. sensor
PLL, HSI, MSI, HSI48
VSS
Standby circuitry
(Wakeup logic, IWDG)
VCORE domain
Core
VCORE
Voltage regulator
Memories
Digital peripherals
VDD12
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC
VBAT
MS49685V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
•
When V is below 1 V, other power supplies (V
300 mV.
V
) must remain below V
+
DD
DD
DDA DDUSB
•
When V is above 1 V, all power supplies are independent.
DD
During the power-down phase, V can temporarily become lower than other supplies only
DD
if the energy provided to the MCU remains below 1 mJ; this allows external decoupling
capacitors to be discharged with different time constants during the power-down transient
phase.
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STM32L412xx
Functional overview
Figure 3. Power-up/down sequence
V
3.6
(1)
VDDX
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
Power-down
VDDX independent from VDD
time
VDDX < VDD + 300 mV
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDUSB
.
3.9.2
Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage V is below a
DD
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the V power supply and compares it to the VPVD threshold. An
DD
interrupt can be generated when V drops below the VPVD threshold and/or when V is
DD
DD
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a Peripheral Voltage Monitor which compares the
independent supply voltage V
with a fixed threshold in order to ensure that the
DDA
peripheral is in its functional supply range.
DS12469 Rev 8
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49
Functional overview
STM32L412xx
3.9.3
Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
•
•
The MR is used in the Run and Sleep modes and in the Stop 0 mode.
The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 8 Kbyte SRAM2 in Standby with SRAM2 retention.
•
Both regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.
The ultralow-power STM32L412xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(V
) can be adjusted according to the system’s maximum operating frequency.
CORE
There are two power consumption ranges:
•
•
Range 1 with the CPU running at up to 80 MHz.
Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The V
can be supplied by the low-power regulator, the main regulator being switched
CORE
off. The system is then in Low-power run mode.
•
Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by HSI16.
3.9.4
Low-power modes
The ultra-low-power STM32L412xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.
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Table 4. STM32L412xx modes overview
Mode
Regulator(1)
CPU Flash SRAM Clocks
DMA and Peripherals(2)
Wakeup source
Consumption(3)
Wakeup time
MR range 1
SMPS range 2 high
MR range2
91 µA/MHz
34 µA/MHz
79 µA/MHz
28 µA/MHz
All
Run
Yes ON(4)
ON
ON
Any
N/A
N/A
N/A
All except USB_FS, RNG
All except USB_FS, RNG
SMPS range 2 low
Any
except
PLL
to Range 1: 4 µs
to Range 2: 64 µs
LPRun
Sleep
LPR
Yes ON(4)
83 µA/MHz
MR range 1
SMPS range 2 high
MR range2
21 µA/MHz
7.5 µA/MHz
20 µA/MHz
7 µA/MHz
All
Any interrupt or
event
No
No
ON(4) ON(5)
Any
6 cycles
6 cycles
All except USB_FS, RNG
SMPS range 2 low
Any
Any interrupt or
event
LPSleep
LPR
ON(4) ON(5)
All except USB_FS, RNG
83 µA/MHz
except
PLL
BOR, PVD, PVM
RTC, IWDG
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
MR Range 1
COMP1, OPAMP1
USARTx (x=1...3)(6)
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
***
COMP1
LSE
LSI
2.47 µs in SRAM
4.1 µs in Flash
Stop 0
No
OFF
ON
USARTx (x=1...3)(6)
LPUART1(6)
105 µA
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
USB_FS(8)
All other peripherals are
frozen.
MR Range 2
Table 4. STM32L412xx modes overview (continued)
Mode
Regulator(1)
CPU Flash SRAM Clocks
DMA and Peripherals(2)
Wakeup source
Consumption(3)
Wakeup time
BOR, PVD, PVM
RTC, IWDG
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMP1, OPAMP1
USARTx (x=1...3)(6)
COMP1
LSE
LSI
LPUART1(6)
5.7 µs in SRAM
7 µs in Flash
3.25 µA w/o RTC
3.65 µA w RTC
USARTx (x=1...3)(6)
Stop 1
LPR
No
Off
ON
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
***
LPUART1(6)
I2Cx (x=1...3)(7)
LPTIMx (x=1,2)
USB_FS(8)
All other peripherals are
frozen.
BOR, PVD, PVM
RTC, IWDG
COMP1
Reset pin, all I/Os
BOR, PVD, PVM
RTC, IWDG
COMP1
I2C3(7)
LSE
LSI
5.8 µs in SRAM
8.3 µs in Flash
710 nA w/o RTC
950 nA w RTC
LPUART1(6)
LPTIMx (x = 1, 2)
***
Stop 2
LPR
No
Off
ON
I2C3(7)
LPUART1(6)
LPTIMx (x = 1, 2)
All other peripherals are
frozen.
Table 4. STM32L412xx modes overview (continued)
Mode
Regulator(1)
CPU Flash SRAM Clocks
DMA and Peripherals(2)
Wakeup source
Consumption(3)
Wakeup time
SRAM
2 ON
BOR, RTC, IWDG
***
LPR
195 nA
Reset pin
5 I/Os (WKUPx)(9)
All other peripherals are
powered off.
LSE
LSI
Power
ed Off
Standby
Off
16.1 µs
Power
ed
***
BOR, RTC, IWDG
OFF
OFF
105 nA
Off
I/O configuration can be
floating, pull-up or pull-down
RTC
***
All other peripherals are
powered off.
Reset pin
5 I/Os (WKUPx)(9)
RTC
Power
ed
Power
ed Off
Shutdown
Off
LSE
18 nA
256 µs
***
Off
I/O configuration can be
floating, pull-up or pull-
down(10)
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in
LPRun/LPSleep.
4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
5. The SRAM1 and SRAM2 clocks can be gated on or off independently.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. USB_FS wakeup by resume from suspend and attach detection protocol event.
9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
Functional overview
STM32L412xx
By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the
user to select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Low-power run mode
This mode is achieved with V
supplied by the low-power regulator to minimize the
CORE
regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
•
•
Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the low-
power run mode.
Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the V
domain are stopped, the PLL, the MSI
CORE
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the V
domain is put in a lower leakage mode.
CORE
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the V
domain is powered off. The PLL, the
CORE
MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in
Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention
mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
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Functional overview
•
Shutdown mode
The Shutdown mode permits to achieve the lowest power consumption. The internal
regulator is switched off so that the V domain is powered off. The PLL, the HSI16,
CORE
the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
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49
Functional overview
STM32L412xx
(1)
Table 5. Functionalities depending on the working mode
Stop 0/1 Stop 2 Standby Shutdown
Low-
Low-
Peripheral
Run
Sleep power power
VBAT
-
-
-
-
run
sleep
CPU
Y
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Flash memory (up to
128 KB)
O(2)
O(2)
O(2)
O(2)
SRAM1 (32 KB)
SRAM2 (8 KB)
Quad SPI
Y
Y
O
Y
Y(3)
Y(3)
O
Y
Y
O
Y
Y(3)
Y(3)
O
Y
Y
-
-
-
-
-
Y
Y
-
-
-
-
-
-
O(4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Backup registers
Y
Y
Y
Y
Y
Y
Y
Brown-out reset
(BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
-
-
-
-
-
-
Programmable
voltage detector
(PVD)
O
O
O
O
O
O
O
O
Peripheral voltage
monitor (PVMx;
x=1,3,4)
O
O
O
O
O
O
O
O
-
-
-
-
-
DMA
O
O
O
O
O
O
O
O
O
O
-
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High speed Internal
(HSI16)
(5)
(5)
Oscillator RC48
-
-
-
-
High speed external
(HSE)
O
O
Low speed internal
(LSI)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
O
O
-
-
-
-
-
O
O
-
-
-
-
-
-
O
-
-
-
-
-
-
O
-
Low speed external
(LSE)
Multi-Speed internal
(MSI)
Clock security
system (CSS)
-
-
-
-
-
Clock security
system on LSE
O
O
2
O
O
2
O
O
2
O
O
2
O
O
2
O
O
O
O
O
2
-
O
O
O
-
O
O
2
-
O
O
O
-
-
O
2
-
-
-
O
2
-
RTC / Auto wakeup
O
O
-
Number of RTC
Tamper pins
USARTx (x=1,2,3)
O
O
O
O
O(6) O(6)
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Functional overview
(1)
Table 5. Functionalities depending on the working mode (continued)
Stop 0/1 Stop 2 Standby Shutdown
Low-
Low-
Peripheral
Run
Sleep power power
VBAT
-
-
-
-
run
sleep
Low-power UART
(LPUART)
O
O
O
O
O(6) O(6) O(6) O(6)
O(7) O(7)
O(7) O(7) O(7) O(7)
-
-
-
-
-
I2Cx (x=1,2)
I2C3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPIx (x=1,2)
ADCx (x=1,2)
OPAMPx (x=1)
COMP1
-
-
-
-
-
-
-
-
O
O
-
-
-
-
O
-
O
-
O
-
Temperature sensor
Timers (TIMx)
-
-
-
-
Low-power timer 1
(LPTIM1)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
Low-power timer 2
(LPTIM2)
Independent
watchdog (IWDG)
O
O
Window watchdog
(WWDG)
O
O
O
O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SysTick timer
Touch sensing
controller (TSC)
Random number
generator (RNG)
O(8)
O
O(8)
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CRC calculation unit
O
O
-
-
4
4
(9)
(11)
GPIOs
O
O
O
O
O
O
O
O
pins
pins
-
(10)
(10)
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame
event.
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49
Functional overview
STM32L412xx
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.5
3.9.6
Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
VBAT operation
The VBAT pin permits to power the device VBAT domain from an external battery, an
external supercapacitor, or from V when no external battery and an external
DD
supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup
registers. Two anti-tamper detection pins are available in VBAT mode.
VBAT operation is automatically activated when V is not present.
DD
An internal VBAT battery charging circuit is embedded and can be activated when V is
DD
present.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
3.10
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 6. STM32L412xx peripherals interconnect matrix
Interconnect
destination
Interconnect source
Interconnect action
TIMx
Timers synchronization or chaining
Conversion triggers
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
ADCx
TIMx
DMA
Memory to memory transfer trigger
Comparator output blanking
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
COMPx
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Functional overview
Table 6. STM32L412xx peripherals interconnect matrix (continued)
Interconnect
destination
Interconnect source
Interconnect action
TIM15/TIM16
COMPx
IRTIM
Infrared interface output generation
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
TIM1
TIM2
Timer input channel, trigger, break from
analog signals comparison
Low-power timer triggered by analog
signals comparison
LPTIMERx
Y
Y
Y
Y
Y
Y
ADCx
RTC
TIM1
Timer triggered by analog watchdog
Timer input channel from RTC events
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
TIM16
Low-power timer triggered by RTC alarms
or tampers
LPTIMERx
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
-
TIM2
All clocks sources (internal
and external)
Clock source used as input channel for
RC measurement and trimming
TIM15, 16
CSS
CPU (hard fault)
RAM (parity error)
TIM1
Timer break
Y
Y
Y
Y
-
-
Flash memory (ECC error) TIM15,16
COMPx
PVD
TIMx
External trigger
External trigger
Y
Y
Y
Y
Y
Y
Y
Y
-
-
LPTIMERx
Y
Y
GPIO
ADCx
Conversion external trigger
Y
Y
Y
Y
-
-
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49
Functional overview
STM32L412xx
3.11
Clocks and startup
The clock controller (see Figure 4) distributes the clocks coming from different oscillators to
the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•
•
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
–
–
–
4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply
a PLL. The HSE can also be configured in bypass mode for an external clock.
16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
–
System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 80 MHz.
•
•
RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be
used to drive the USB or the RNG peripherals. This clock can be output on the MCO.
Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the real-time clock:
–
–
32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
•
•
•
Peripheral clock sources: Several peripherals (RNG, USARTs, I2Cs, LPTimers) have
their own independent clock whatever the system clock. PLL having three independent
outputs allowing the highest flexibility, can generate independent clocks for the RNG.
Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
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Functional overview
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
•
Clock-out capability:
–
MCO: microcontroller clock output: it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSI, LSE) are available
down to Stop 1 low power state.
–
LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes
down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
LSCO is not available in VBAT mode.
Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 80 MHz.
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49
Functional overview
STM32L412xx
Figure 4. Clock tree
to IWDG
to RTC
LSI RC 32 kHz
LSCO
OSC32_OUT
OSC32_IN
LSE OSC
32.768 kHz
/32
LSE
LSI
HSE
MCO
/ 1→16
to PWR
to AHB bus, core, memory and DMA
FCLK Cortex free running clock
to Cortex system timer
SYSCLK
HSI16
HSI48
Clock
source
control
HCLK
AHB PRESC
/ 1,2,..512
MSI
PLLCLK
OSC_OUT
OSC_IN
HSE OSC
4-48 MHz
HSE
/ 8
Clock
detector
MSI
SYSCLK
PCLK1
to APB1 peripherals
APB1 PRESC
/ 1,2,4,8,16
HSI16
x1 or x2
HSI RC
16 MHz
to TIMx
x=2,6,7
LSE
HSI16
SYSCLK
to USARTx
x=2..3
to LPUART1
HSI16
MSI RC
100 kHz – 48 MHz
to I2Cx
x=1,2,3
SYSCLK
LSI
LSE
to LPTIMx
x=1,2
HSI16
MSI
PCLK2
HSI16
PLL
/ M
APB2 PRESC
/ 1,2,4,8,16
HSE
to APB2 peripherals
/ P
PLL48M1CLK
PLLCLK
/ Q
/ R
x1 or x2
to TIMx
x=1,15,16
LSE
HSI16
to
SYSCLK
USART1
MSI
48 MHz clock to USB, RNG
to ADCx, x=1,2
HSI RC
48 MHz
SYSCLK
CRS
MSv46900V3
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Functional overview
3.12
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.13
Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 14 channels in total, each dedicated to managing memory
access requests from one or more peripherals. Each has an arbiter for handling the priority
between DMA requests.
The DMA supports:
•
•
14 independently configurable channels (requests)
Each channel is connected to dedicated hardware DMA requests, software trigger is
also supported on each channel. This configuration is done by software.
•
•
Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(example: request 1 has priority over request 2)
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•
•
Support for circular buffer management
3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
•
•
Memory-to-memory transfer
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
•
•
Access to Flash, SRAM, APB and AHB peripherals as source and destination
Programmable number of data to be transferred: up to 65536.
Table 7. DMA implementation
DMA features
DMA1
7
DMA2
7
Number of regular channels
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49
Functional overview
STM32L412xx
3.14
Interrupts and events
3.14.1
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
®
and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex -
M4.
The NVIC benefits are the following:
•
•
•
•
•
•
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail chaining
Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.14.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 37 edge detector lines used to generate
interrupt/event requests and wake-up the system from Stop mode. Each external line can be
independently configured to select the trigger event (rising edge, falling edge, both) and can
be masked independently. A pending register maintains the status of the interrupt requests.
The internal lines are connected to peripherals with wakeup from Stop mode capability. The
EXTI can detect an external line with a pulse width shorter than the internal clock period. Up
to 52 GPIOs can be connected to the 16 external interrupt lines.
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Functional overview
3.15
Analog to digital converter (ADC)
The device embeds 2 successive approximation analog-to-digital converter with the
following features:
•
•
12-bit native resolution, with built-in calibration
5.33 Msps maximum conversion rate with full resolution
–
–
Down to 18.75 ns sampling time
Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
•
•
•
Up to 16 external channels, some of them shared between ADC1 and ADC2.
3 internal channels: internal reference voltage, temperature sensor, VBAT/3.
One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
•
•
Single-ended and differential mode inputs
Low-power design
–
Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
•
Highly versatile digital interface
–
Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–
–
Handles two ADC converters for dual mode operation (simultaneous or
interleaved sampling modes)
Each ADC supports multiple trigger inputs for synchronization with on-chip timers
and external signals
–
–
–
–
–
Results stored into 2 data register or in RAM with DMA controller support
Data pre-processing: left/right alignment and per channel offset compensation
Built-in oversampling unit for enhanced SNR
Channel-wise programmable sampling time
Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
–
Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.15.1
Temperature sensor
The temperature sensor (TS) generates a voltage V that varies linearly with temperature.
TS
The temperature sensor is internally connected to the ADC1_IN17 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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49
Functional overview
STM32L412xx
Table 8. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
TS_CAL1
TS_CAL2
0x1FFF 75A8 - 0x1FFF 75A9
0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 9. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT
temperature of 30 °C (± 5 °C),
0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15.3
VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the V
battery voltage
BAT
using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the V
voltage may be
BAT
higher than V
, and thus outside the ADC input range, the VBAT pin is internally
DDA
connected to a bridge divider by 3. As a consequence, the converted digital value is one
third the V voltage.
BAT
3.16
Comparators (COMP)
The STM32L412xx devices embed one rail-to-rail comparator with programmable reference
voltage (internal or external), hysteresis and speed (low speed for low-power) and with
selectable output polarity.
The reference voltage can be one of the following:
•
•
External I/O
Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can be also combined into a window comparator.
3.17
Operational amplifier (OPAMP)
The STM32L412xx embeds one operational amplifier with external or internal follower
routing and PGA capability.
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Functional overview
The operational amplifier features:
•
•
•
•
Low input bias current
Low offset voltage
Low-power mode
Rail-to-rail input
3.18
Touch sensing controller (TSC)
The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric (such as
glass or plastic). The capacitive variation introduced by the finger (or any conductive object)
is measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
•
•
•
Proven and robust surface charge transfer acquisition principle
Supports up to 12 capacitive sensing channels
Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
•
•
•
•
•
•
•
•
Spread spectrum feature to improve system robustness in noisy environments
Full hardware management of the charge transfer acquisition sequence
Programmable charge transfer frequency
Programmable sampling capacitor I/O pin
Programmable channel I/O pin
Programmable max count value to avoid long acquisition when a channel is faulty
Dedicated end of acquisition and max count error flags with interrupt capability
One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
•
•
Compatible with proximity, touchkey, linear and rotary touch sensor implementation
Designed to operate with STMTouch touch sensing firmware library
Note:
The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
3.19
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
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49
Functional overview
STM32L412xx
3.20
Timers and watchdogs
The STM32L412xx includes one advanced control timers, up to five general-purpose timers,
two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table
below compares the features of the advanced control, general purpose and basic timers.
Table 10. Timer feature comparison
DMA
request
generation channels
Capture/
compare
Counter
resolution
Counter
type
Prescaler
factor
Complementary
outputs
Timer type
Timer
Any integer
between 1
and 65536
Advanced
control
Up, down,
Up/down
TIM1
TIM2
16-bit
32-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
Yes
Yes
4
4
2
1
0
3
No
1
Any integer
between 1
and 65536
General-
purpose
Up, down,
Up/down
Any integer
between 1
and 65536
General-
purpose
TIM15
TIM16
TIM6
Up
Up
Up
Any integer
between 1
and 65536
General-
purpose
1
Any integer
between 1
and 65536
Basic
No
3.20.1
Advanced-control timer (TIM1)
The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers. The 4 independent
channels can be used for:
•
•
•
Input capture
Output compare
PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.20.2) using the same architecture, so the advanced-control timer can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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Functional overview
3.20.2
General-purpose timers (TIM2, TIM15, TIM16)
There are up to three synchronizable general-purpose timers embedded in the
STM32L412xx (see Table 10 for differences). Each general-purpose timer can be used to
generate PWM outputs, or act as a simple time base.
•
TIM2
It is a full-featured general-purpose timers:
–
TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.
This timers feature 4 independent channels for input capture/output compare, PWM or
one-pulse mode output. They can work with the other general-purpose timers via the
Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoder.
TIM15 and 16
•
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
–
TIM15 has 2 channels and 1 complementary channel
TIM16 has 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.20.3
3.20.4
Basic timer (TIM6)
The basic timer can be used as generic 16-bit timebase.
Low-power timer (LPTIM1 and LPTIM2)
The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
Both LPTIM1 and LPTIM2 are active in Stop 0, Stop 1 and Stop 2 modes.
This low-power timer supports the following features:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous/ one shot mode
Selectable software/hardware input trigger
Selectable clock source
–
–
Internal clock sources: LSE, LSI, HSI16 or APB clock
External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•
•
Programmable digital glitch filter
Encoder mode (LPTIM1 only)
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49
Functional overview
STM32L412xx
3.20.5
Infrared interface (IRTIM)
The STM32L412xx includes one infrared interface (IRTIM), which can be used with an
infrared LED to perform remote control functions. It uses TIM15 and TIM16 output channels
to generate output signal waveforms on IR_OUT pin.
3.20.6
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.20.7
3.20.8
System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
•
•
•
•
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
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Functional overview
3.21
Real-time clock (RTC) and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
•
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
•
Two anti-tamper detection pins with programmable filter.
Timestamp feature, which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the V supply when present or from the VBAT pin.
DD
The backup registers are 32-bit registers used to store 128 bytes of user application data
when V power is not present. They are not reset by a system or power reset, or when the
DD
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
•
•
•
•
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
DS12469 Rev 8
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49
Functional overview
STM32L412xx
3.22
Inter-integrated circuit interface (I2C)
The device embeds three I2C. Refer to Table 11: I2C implementation for the features
implementation.
2
The I C bus interface handles communications between the microcontroller and the serial
2
2
I C bus. It controls all I C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
I2C-bus specification and user manual rev. 5 compatibility:
–
–
–
–
–
–
–
Slave and master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
•
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
–
Address resolution protocol (ARP) support
SMBus alert
TM
•
•
Power System Management Protocol (PMBus ) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 4: Clock tree.
•
•
•
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
Table 11. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
Standard-mode (up to 100 kbit/s)
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Programmable analog and digital noise filters
SMBus/PMBus hardware support
Independent clock
Wakeup from Stop 1 mode on address match
Wakeup from Stop 2 mode on address match
1. X: supported
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DS12469 Rev 8
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Functional overview
3.23
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32L412xx devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable, and are able to communicate at speeds of up to
10 Mbit/s.
USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and
SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake
up events from Stop mode are programmable and can be:
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 12. STM32L412xx USART/UART/LPUART features
USART modes/features(1)
USART1 USART2 USART3 LPUART1
Hardware flow control for modem
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
-
X
X
X
Smartcard mode
X
-
Single-wire half-duplex communication
IrDA SIR ENDEC block
LIN mode
X
X
-
X
X
-
Dual clock domain
X
X
X
X
-
Wakeup from Stop 0 / Stop 1 modes
Wakeup from Stop 2 mode
Receiver timeout interrupt
Modbus communication
Auto baud rate detection
Driver Enable
X
-
X
X
X
X
X
X
X (4 modes)
X
-
-
X
X
X
LPUART/USART data length
1. X = supported.
7, 8 and 9 bits
DS12469 Rev 8
45/192
49
Functional overview
STM32L412xx
3.24
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
•
•
•
Start bit detection
Any received data frame
A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
46/192
DS12469 Rev 8
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Functional overview
3.25
Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.26
Universal serial bus (USB)
The STM32L412xx devices embed a full-speed USB device peripheral compliant with the
USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.
It requires a precise 48 MHz clock which can be generated from the internal main PLL (the
clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in
automatic trimming mode. The synchronization for this oscillator can be taken from the USB
data stream itself (SOF signalization) which allows crystal less operation.
3.27
3.28
Clock recovery system (CRS)
The STM32L412xx devices embed a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from LSE oscillator, from an external signal on CRS_SYNC
pin or generated by user software. For faster lock-in during startup it is also possible to
combine automatic trimming with manual trimming action.
Quad SPI memory interface (QUADSPI)
The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
Flash memories. It can operate in any of the three following modes:
•
•
Indirect mode: all the operations are performed using the QUADSPI registers
Status polling mode: the external Flash memory status register is periodically read and
an interrupt can be generated in case of flag setting
•
Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad SPI flash memories are accessed simultaneously.
DS12469 Rev 8
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49
Functional overview
STM32L412xx
The Quad SPI interface supports:
•
•
Three functional modes: indirect, status-polling, and memory-mapped
Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two
flash memories in parallel.
•
•
•
•
SDR and DDR support
Fully programmable opcode for both indirect and memory mapped mode
Fully programmable frame format for both indirect and memory mapped mode
Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
–
–
–
–
–
Instruction phase
Address phase
Alternate bytes phase
Dummy cycles phase
Data phase
•
•
•
•
•
•
Integrated FIFO for reception and transmission
8, 16, and 32-bit data accesses are allowed
DMA channel for indirect mode operations
Programmable masking for external flash flag management
Timeout management
Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
48/192
DS12469 Rev 8
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Functional overview
3.29
Development support
3.29.1
Serial wire JTAG debug port (SWJ-DP)
®
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins
can be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.29.2
Embedded Trace Macrocell™
®
The Arm Embedded Trace Macrocell™ provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L412xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell™ operates with third party debugger software tools.
DS12469 Rev 8
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49
Pinouts and pin description
STM32L412xx
4
Pinouts and pin description
(1)
Figure 5. STM32L412Rx LQFP64 pinout
VBAT
1
2
48
47
VDDUSB
VSS
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
3
4
5
6
7
8
9
10
11
12
13
14
15
16
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC0
PC1
PC2
PC3
LQFP64
VSSA/VREF-
VDDA/VREF+
PA0
PC6
PB15
PB14
PB13
PB12
PA1
PA2
MSv46920V1
1. The above figure shows the package top view.
(1)
Figure 6. STM32L412Rx, external SMPS, LQFP64 pinout
VBAT
PC13
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDUSB
VSS
PC14-OSC32_IN
PC15-OSC32_OUT
PH0-OSC_IN
PH1-OSC_OUT
NRST
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC0
PC1
PC2
PC3
LQFP64
9
10
11
12
13
14
15
16
VSSA/VREF-
VDDA/VREF+
PA0
PC6
PB15
PB14
PB13
PB12
PA1
PA2
MS46959V1
1. The above figure shows the package top view.
50/192
DS12469 Rev 8
STM32L412xx
Pinouts and pin description
(1)
Figure 7. STM32L412Rx UFBGA64 ballout
1
2
3
4
5
6
7
8
PC14-
A
B
C
D
E
F
PC13
VBAT
VSS
VDD
PC1
PC2
PA0
PB9
PB8
PB7
PB6
PC0
PA2
PA3
PA4
PB4
PB3
PA15
PC11
PA10
VSS
VDD
PC6
PB2
PC5
PA14
PC10
PA9
PA13
PA12
PA11
PC9
OSC32_IN
PC15-
OSC32_OUT
PH3-BOOT0
PB5
PD2
PH0-OSC_IN
PC12
VSS
PH1-
OSC_OUT
VSS
PA8
NRST
VSSA/VREF-
PC3
VDD
VDDUSB
PB0
PC7
PC8
PA5
PB15
PB10
PB11
PB14
PB13
PB12
G
H
PA6
PB1
VDDA/VREF+
PA1
PA7
PC4
MSv46919V1
1. The above figure shows the package top view.
(1)
Figure 8. STM32L412Rx UFBGA64, external SMPS, ballout
1
2
3
4
5
6
7
8
PC14-
A
B
C
D
E
F
PC13
VBAT
VSS
VDD
PC1
PC2
PA0
PB9
PB8
PB7
PB6
PC0
PA2
PA3
PA4
PB4
PB3
PA15
PC11
PA10
VSS
PA14
PC10
PA9
PA13
PA12
PA11
PC9
OSC32_IN
PC15-
OSC32_OUT
PH3-BOOT0
PB5
VDD12
PC12
VSS
PH0-OSC_IN
PH1-
OSC_OUT
VSS
PA8
NRST
VSSA/VREF-
PC3
VDD
VDDUSB
PB0
VDD
PC6
PC7
PC8
PA5
PB15
PB10
PB11
PB14
PB13
PB12
G
H
PA6
PB1
PB2
VDDA/VREF+
PA1
PA7
PC4
VDD12
MS53656V1
1. The above figure shows the package top view.
DS12469 Rev 8
51/192
72
Pinouts and pin description
STM32L412xx
(1)
Figure 9. STM32L412Cx LQFP48 pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDDUSB
VSS
2
PC14/OSC32_IN
3
PA13
PA12
PA11
PA10
PA9
PC15/OSC32_OUT
PH0/OSC_IN
PH1/OSC_OUT
NRST
4
5
6
LQFP48
7
VSSA
8
PA8
VDDA
9
PB15
PB14
PB13
PB12
PA0/CK_IN
PA1
10
11
12
PA2
MSv46916V1
1. The above figure shows the package top view.
(1)
Figure 10. STM32L412Cx UFQFPN48 pinout
VBAT
PC13
1
36
35
34
33
32
31
30
29
28
27
26
25
VDDUSB
2
VSS
PC14/OSC32_IN
PC15/OSC32_OUT
PH0/OSC_IN
PH1/OSC_OUT
NRST
3
PA13
PA12
PA11
PA10
PA9
4
5
6
UFQFPN48
7
VSSA
8
PA8
VDDA
9
PB15
PB14
PB13
PB12
PA0/CK_IN
PA1
10
11
12
PA2
MSv46917V1
1. The above figure shows the package top view.
52/192
DS12469 Rev 8
STM32L412xx
Pinouts and pin description
(1)
Figure 11. STM32L412Tx WLCSP36 ballout
1
2
3
4
5
6
PA12
PA11
PA9
PA14
PA13
PA10
PB1
PB4
PB3
PA15
PA6
PA7
PB0
PB7
PB6
PB5
PA1
PA5
PA4
VSS
PB8
VDD
PC14
PC15
NRST
VREF+
VDDA
A
B
C
D
E
F
PH3
BOOT0
PA8
PA0
PA2
PA3
VDD
VSS
PB2
PB10
MS49688V1
1. The above figure shows the package top view.
(1)
Figure 12. STM32L412Tx, external SMPS, WLCSP36 ballout
1
2
3
4
5
VSS
VDD12
PH3
PA1
6
PA12
PA11
PA9
PA14
PA13
PA10
PB1
PB4
PB3
PA15
PA6
PB0
PB2
PB7
PB6
PB5
PA2
PA5
PA7
VDD
PC14
PC15
NRST
A
B
C
D
E
F
PA8
VDDA/
VREF+
VDD
VSS
PB10
VDD12
PA3
PA4
PA0
MS51459V1
1. The above figure shows the package top view.
DS12469 Rev 8
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72
Pinouts and pin description
STM32L412xx
(1)
Figure 13. STM32L412Kx LQFP32 pinout
VDD
PC14-OSC32_IN
PC15-OSC32_OUT
NRST
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PA14
PA13
PA12
PA11
PA10
PA9
LQFP32
VDDA/VREF+
PA0-CK_IN
PA1
PA8
PA2
VDD
MSv46914V1
1. The above figure shows the package top view.
(1)
Figure 14. STM32L412Kx UFQFPN32 pinout
VDD
PC14-OSC32_IN
PC15-OSC32_OUT
NRST
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PA14
PA13
PA12
PA11
PA10
PA9
UFQFPN32
VDDA/VREF+
PA0-CK_IN
PA1
PA8
PA2
VDD
MSv46915V1
1. The above figure shows the package top view.
54/192
DS12469 Rev 8
STM32L412xx
Pinouts and pin description
Table 13. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Pin type
Input only pin
I/O
FT
TT
RST
Input / output pin
5 V tolerant I/O
3.6 V tolerant I/O
Bidirectional reset pin with embedded weak pull-up resistor
I/O structure
Option for TT or FT I/Os
_f (1)
_u (2)
_a (3)
I/O, Fm+ capable
I/O, with USB function supplied by VDDUSB
I/O, with Analog switch function supplied by VDDA
Notes
Alternate
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 14 are: FT_f, FT_fa.
2. The related I/O structures in Table 14 are: FT_u, FT_fu.
3. The related I/O structures in Table 14 are: FT_a, FT_fa, TT_a.
DS12469 Rev 8
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72
Table 14. STM32L412xx pin definitions
Pin Number
Pin name
(function after
reset)
Alternate functions
Additional functions
-
-
-
-
-
-
-
-
1
2
1
2
1
2
1
2
B2
A2
B2
A2
VBAT
PC13
S
-
-
-
-
-
RTC_TAMP1/RTC_TS/RT
C_OUT1/WKUP2
I/O
FT
EVENTOUT
PC14-OSC32_IN
(PC14)
2
3
-
2
3
-
B6
C6
-
B6
C6
-
3
4
5
3
4
5
3
4
5
3
4
5
A1
B1
C1
A1
B1
C1
I/O
I/O
I/O
FT
FT
FT
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
OSC32_IN
OSC32_OUT
OSC_IN
PC15-
OSC32_OUT
(PC15)
PH0-OSC_IN
(PH0)
PH1-OSC_OUT
(PH1)
-
-
-
-
6
7
6
7
6
7
6
7
D1
E1
D1
E1
I/O
I/O
FT
-
-
EVENTOUT
-
OSC_OUT
-
4
4
D6
D6
NRST
RST
TRACECK, LPTIM1_IN1,
I2C3_SCL, LPUART1_RX,
LPTIM2_IN1, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
8
9
8
9
E3
E2
E3
E2
PC0
I/O
I/O
FT_fa
FT_fa
-
-
ADC12_IN1
ADC12_IN2
TRACED0, LPTIM1_OUT,
I2C3_SDA, LPUART1_TX,
EVENTOUT
PC1
LPTIM1_IN2, SPI2_MISO,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
10
11
10
11
F2
F2
PC2
PC3
I/O
I/O
FT_a
FT_a
-
-
ADC12_IN3
ADC12_IN4
LPTIM1_ETR, SPI2_MOSI,
LPTIM2_ETR, EVENTOUT
G1
G1
-
-
-
-
-
-
8
-
8
-
12
-
12
-
F1
-
F1
-
VSSA/VREF-
VREF+
S
S
-
-
-
-
-
-
-
-
E6
E6
Table 14. STM32L412xx pin definitions (continued)
Pin name
Pin Number
(function after
reset)
Alternate functions
Additional functions
-
-
-
F6
-
-
-
-
-
-
-
VDDA
S
S
-
-
-
-
-
-
5
5
E6
9
9
13
13
H1
H1
VDDA/VREF+
-
-
TIM2_CH1, USART2_CTS,
OPAMP1_VINP,
-
-
-
-
10 10 14
14
-
G2
-
G2
-
PA0
I/O
FT_a
-
COMP1_OUT, TIM2_ETR, COMP1_INM, ADC1_IN5,
EVENTOUT
RTC_TAMP2/WKUP1
OPAMP1_VINP,
COMP1_INM, ADC1_IN5,
RTC_TAMP2/WKUP1,
CK_IN
TIM2_CH1, USART2_CTS,
COMP1_OUT, TIM2_ETR,
EVENTOUT
6
6
F6
D5
-
-
-
PA0-CK_IN
I/O
FT_a
-
TIM2_CH2, I2C1_SMBA,
SPI1_SCK,
USART2_RTS_DE,
TIM15_CH1N, EVENTOUT
OPAMP1_VINM,
COMP1_INP, ADC1_IN6
7
8
9
7
8
9
D5
D4
F5
D4 11 11 15
15
16
17
H2
F3
G3
H2
F3
G3
PA1
PA2
PA3
I/O
I/O
I/O
FT_a
FT_a
TT_a
-
-
-
TIM2_CH3, USART2_TX,
LPUART1_TX,
QUADSPI_BK1_NCS,
TIM15_CH1, EVENTOUT
ADC12_IN7,
WKUP4/LSCO
E5
F5
12 12 16
TIM2_CH4, USART2_RX,
LPUART1_RX,
OPAMP1_VOUT,
ADC12_IN8
13 13 17
QUADSPI_CLK,
TIM15_CH2, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
18
19
18
19
C2
D2
C2
D2
VSS
VDD
S
S
-
-
-
-
-
-
-
-
SPI1_NSS, USART2_CK,
LPTIM2_OUT, EVENTOUT
10 10
F5
F4
14 14 20
20
H3
H3
PA4
I/O
TT_a
COMP1_INM, ADC12_IN9
Table 14. STM32L412xx pin definitions (continued)
Pin name
Pin Number
(function after
reset)
Alternate functions
Additional functions
TIM2_CH1, TIM2_ETR,
SPI1_SCK, LPTIM2_ETR,
EVENTOUT
COMP1_INM,
ADC12_IN10
11 11
E4
E4
15 15 21
21
22
F4
F4
PA5
PA6
I/O
I/O
TT_a
FT_a
TIM1_BKIN, SPI1_MISO,
COMP1_OUT,
USART3_CTS,
LPUART1_CTS,
QUADSPI_BK1_IO3,
TIM16_CH1, EVENTOUT
12 12 D3
D3 16 16 22
G4
G4
ADC12_IN11
ADC12_IN12
TIM1_CH1N, I2C3_SCL,
SPI1_MOSI,
QUADSPI_BK1_IO2,
EVENTOUT
13 13
F4
E3
17 17 23
23
H4
H4
PA7
I/O
FT_fa
COMP1_INM,
ADC12_IN13
-
-
-
-
-
-
-
-
-
-
-
-
24
-
24
25
H5
H6
H5
-
PC4
PC5
I/O
I/O
FT_a
FT_a
USART3_TX, EVENTOUT
USART3_RX, EVENTOUT
COMP1_INP,
ADC12_IN14, WKUP5
TRACED0, TIM1_CH2N,
SPI1_NSS, USART3_CK,
QUADSPI_BK1_IO1,
14 14
E3
F3
18 18 25
26
F5
F5
PB0
I/O
FT_a
ADC12_IN15
COMP1_OUT, EVENTOUT
TRACED1, TIM1_CH3N,
USART3_RTS_DE,
LPUART1_RTS_DE,
QUADSPI_BK1_IO0,
LPTIM2_IN1, EVENTOUT
COMP1_INM,
ADC12_IN16
15 15 D2
D2 19 19 26
27
28
G5
G6
G5
G6
PB1
PB2
I/O
I/O
FT_a
FT_a
LPTIM1_OUT, I2C3_SMBA,
EVENTOUT
-
-
F3
E2
20 20 27
COMP1_INP, RTC_OUT2
Table 14. STM32L412xx pin definitions (continued)
Pin name
Pin Number
(function after
reset)
Alternate functions
Additional functions
TIM2_CH3, I2C2_SCL,
SPI2_SCK, USART3_TX,
LPUART1_RX, TSC_SYNC,
QUADSPI_CLK,
-
-
E2
-
F2
-
21 21 28
29
30
G7
H7
G7
H7
PB10
PB11
I/O
I/O
FT_f
FT_f
-
-
COMP1_OUT, EVENTOUT
TIM2_CH4, I2C2_SDA,
USART3_RX,LPUART1_TX,
QUADSPI_BK1_NCS,
EVENTOUT
-
-
-
-
22 22 29
F2
F1
E1
-
-
-
30
-
-
H6
D6
E6
VDD12
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
16 16
17 17
F1
E1
23 23 31
24 24 32
31
32
D6
E6
VDD
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS, USART3_CK,
LPUART1_RTS_DE,
TSC_G1_IO1, TIM15_BKIN,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
25 25 33
26 26 34
27 27 35
33
34
35
H8
G8
F8
H8
G8
F8
PB12
PB13
PB14
I/O
I/O
I/O
FT
-
-
-
-
-
-
TIM1_CH1N, I2C2_SCL,
SPI2_SCK, USART3_CTS,
LPUART1_CTS,
TSC_G1_IO2, TIM15_CH1N,
EVENTOUT
FT_f
FT_f
TIM1_CH2N, I2C2_SDA,
SPI2_MISO,
USART3_RTS_DE,
TSC_G1_IO3, TIM15_CH1,
EVENTOUT
Table 14. STM32L412xx pin definitions (continued)
Pin name
Pin Number
(function after
reset)
Alternate functions
Additional functions
RTC_REFIN, TIM1_CH3N,
SPI2_MOSI, TSC_G1_IO4,
TIM15_CH2, EVENTOUT
-
-
-
-
28 28 36
36
F7
F7
PB15
I/O
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
37
38
39
37
38
39
F6
E7
E8
F6
E7
E8
PC6
PC7
PC8
I/O
I/O
I/O
FT
FT
FT
-
-
-
TSC_G4_IO1, EVENTOUT
TSC_G4_IO2, EVENTOUT
TSC_G4_IO3, EVENTOUT
-
-
-
TSC_G4_IO4, USB_NOE,
EVENTOUT
-
-
-
-
-
-
40
40
D8
D8
PC9
I/O
FT
-
-
MCO, TIM1_CH1,
USART1_CK, LPTIM2_OUT,
EVENTOUT
18 18 D1
19 19 C1
D1 29 29 41
C1 30 30 42
41
D7
D7
PA8
I/O
FT
-
-
TIM1_CH2, I2C1_SCL,
USART1_TX, TIM15_BKIN,
EVENTOUT
42
43
C7
C6
C7
C6
PA9
I/O
I/O
FT_f
FT_f
-
-
-
-
TIM1_CH3, I2C1_SDA,
USART1_RX,
USB_CRS_SYNC,
EVENTOUT
20 20 C2
C2 31 31 43
PA10
TIM1_CH4, TIM1_BKIN2,
SPI1_MISO, COMP1_OUT,
USART1_CTS, USB_DM,
TIM1_BKIN2_COMP1,
EVENTOUT
21 21
22 22
B1
A1
B1
A1
32 32 44
44
45
C8
B8
C8
B8
PA11
PA12
I/O
I/O
FT_u
FT_u
-
-
-
-
TIM1_ETR, SPI1_MOSI,
USART1_RTS_DE,
33 33 45
USB_DP, EVENTOUT
Table 14. STM32L412xx pin definitions (continued)
Pin name
Pin Number
(function after
reset)
Alternate functions
Additional functions
PA13
(JTMS/SWDIO)
JTMS/SWDIO, IR_OUT,
USB_NOE, EVENTOUT
23 23
B2
B2
34 34 46
46
A8
A8
I/O
FT
-
-
-
-
-
-
-
-
-
-
35 35 47
36 36 48
47
48
D5
E5
D5
E5
VSS
S
S
-
-
-
-
-
-
-
-
VDDUSB
JTCK/SWCLK,
LPTIM1_OUT, I2C1_SMBA,
EVENTOUT
PA14
(JTCK/SWCLK)
24 24
A2
A2
37 37 49
49
A7
A7
I/O
FT
-
-
JTDI, TIM2_CH1,
TIM2_ETR, USART2_RX,
SPI1_NSS,
25 25 C3
C3 38 38 50
50
A6
A6
PA15 (JTDI)
I/O
FT
-
-
USART3_RTS_DE,
TSC_G3_IO1, EVENTOUT
TRACED1, USART3_TX,
TSC_G3_IO2, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
51
52
53
51
52
53
B7
B6
C5
B7
B6
C5
PC10
PC11
PC12
I/O
I/O
I/O
FT
FT
FT
-
-
-
-
-
-
USART3_RX, TSC_G3_IO3,
EVENTOUT
TRACED3, USART3_CK,
TSC_G3_IO4, EVENTOUT
TRACED2,
-
-
-
-
-
-
-
54
55
B5
A5
-
PD2
PB3
I/O
FT
-
-
USART3_RTS_DE,
TSC_SYNC, EVENTOUT
-
-
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
USART1_RTS_DE,
EVENTOUT
26 26
B3
B3
39 39 54
A5 (JTDO/TRACESW I/O
O)
FT_a
Table 14. STM32L412xx pin definitions (continued)
Pin name
Pin Number
(function after
reset)
Alternate functions
Additional functions
NJTRST, I2C3_SDA,
SPI1_MISO, USART1_CTS,
TSC_G2_IO1, EVENTOUT
27 27
A3
A3
40 40 55
56
57
A4
C4
A4
C4
PB4 (NJTRST)
PB5
I/O
I/O
FT_fa
FT
-
-
-
-
TRACED2, LPTIM1_IN1,
I2C1_SMBA, SPI1_MOSI,
USART1_CK, TSC_G2_IO2,
TIM16_BKIN, EVENTOUT
28 28 C4
C4 41 41 56
TRACED3, LPTIM1_ETR,
I2C1_SCL, USART1_TX,
TSC_G2_IO3, TIM16_CH1N,
EVENTOUT
29 29
30 30
B4
A4
B4
A4
42 42 57
43 43 58
58
59
D3
C3
D3
C3
PB6
PB7
I/O
I/O
FT_fa
FT_fa
-
-
-
TRACECK, LPTIM1_IN2,
I2C1_SDA, USART1_RX,
TSC_G2_IO4, EVENTOUT
PVD_IN
PH3-BOOT0
(BOOT0)
31 31 C5
C5 44 44 59
60
61
62
B4
B3
A3
B4
B3
A3
I/O
I/O
I/O
FT
-
-
-
EVENTOUT
-
-
-
I2C1_SCL, TIM16_CH1,
EVENTOUT
-
-
-
-
B5
-
45 45 60
46 46 61
PB8
PB9
FT_f
FT_f
IR_OUT, I2C1_SDA,
SPI2_NSS, EVENTOUT
-
-
-
-
B5
A5
A6
-
-
-
62
-
-
B5
D4
E4
VDD12
VSS
S
S
S
-
-
-
-
-
-
-
-
-
32 32
A5
A6
47 47 63
48 48 64
63
64
D4
E4
1
1
VDD
(1)
Table 15. Alternate function AF0 to AF7
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
Port
TIM1/TIM2/LPT
IM1
USART1/USA
RT2/USART3
SYS_AF
TIM1/TIM2
USART2
I2C1/I2C2/I2C3
SPI1/SPI2
COMP1
PA0
PA1
-
-
TIM2_CH1
TIM2_CH2
-
-
-
-
-
-
-
-
USART2_CTS
USART2_RTS_
DE
I2C1_SMBA
SPI1_SCK
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
-
TIM2_CH3
TIM2_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_TX
USART2_RX
USART2_CK
-
-
-
-
-
-
SPI1_NSS
-
TIM2_CH1
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM2_ETR
SPI1_SCK
-
-
SPI1_MISO
COMP1_OUT USART3_CTS
-
-
I2C3_SCL
SPI1_MOSI
-
-
-
-
-
Port A
MCO
-
-
USART1_CK
USART1_TX
USART1_RX
-
-
-
-
I2C1_SCL
I2C1_SDA
-
-
PA10
PA11
-
-
TIM1_BKIN2
SPI1_MISO
COMP1_OUT USART1_CTS
USART1_RTS_
PA12
-
TIM1_ETR
-
-
-
SPI1_MOSI
-
DE
PA13 JTMS/SWDAT
PA14 JTCK/SWCLK
IR_OUT
-
-
-
-
-
-
-
-
-
-
-
LPTIM1_OUT
I2C1_SMBA
USART3_RTS_
DE
PA15
JTDI
TIM2_CH1
TIM2_ETR
USART2_RX
-
SPI1_NSS
-
(1)
Table 15. Alternate function AF0 to AF7
(continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
Port
TIM1/TIM2/LPT
IM1
USART1/USA
RT2/USART3
SYS_AF
TIM1/TIM2
USART2
I2C1/I2C2/I2C3
SPI1/SPI2
COMP1
PB0
TRACED0
TRACED1
-
TIM1_CH2N
TIM1_CH3N
LPTIM1_OUT
TIM2_CH2
-
-
-
-
-
-
-
-
-
SPI1_NSS
-
-
-
-
USART3_CK
USART3_RTS_
DE
PB1
PB2
PB3
-
-
I2C3_SMBA
-
-
-
JTDO/TRACES
WO
USART1_RTS_
DE
SPI1_SCK
PB4
PB5
NJTRST
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_SDA
I2C1_SMBA
I2C1_SCL
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
I2C2_SMBA
I2C2_SCL
SPI1_MISO
-
-
-
-
-
-
-
-
-
-
USART1_CTS
USART1_CK
USART1_TX
USART1_RX
-
TRACED2
LPTIM1_IN1
LPTIM1_ETR
LPTIM1_IN2
-
SPI1_MOSI
PB6
TRACED3
-
PB7
TRACECK
-
Port B
PB8
-
-
-
-
-
-
-
PB9
IR_OUT
SPI2_NSS
SPI2_SCK
-
PB10
PB11
PB12
PB13
TIM2_CH3
TIM2_CH4
TIM1_BKIN
TIM1_CH1N
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
SPI2_NSS
SPI2_SCK
USART3_RTS_
DE
PB14
PB15
-
TIM1_CH2N
TIM1_CH3N
-
-
-
-
I2C2_SDA
-
SPI2_MISO
SPI2_MOSI
-
-
RTC_REFIN
-
(1)
Table 15. Alternate function AF0 to AF7
(continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
Port
TIM1/TIM2/LPT
IM1
USART1/USA
RT2/USART3
SYS_AF
TIM1/TIM2
USART2
I2C1/I2C2/I2C3
SPI1/SPI2
COMP1
PC0
TRACECK
LPTIM1_IN1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_SCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC1
PC2
TRACED0
LPTIM1_OUT
I2C3_SDA
-
-
-
LPTIM1_IN2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_MISO
-
PC3
-
LPTIM1_ETR
SPI2_MOSI
-
PC4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_TX
PC5
-
USART3_RX
PC6
-
-
PC7
-
-
Port C
PC8
-
-
PC9
-
-
PC10
PC11
PC12
PC13
PC14
PC15
TRACED1
USART3_TX
-
USART3_RX
TRACED3
USART3_CK
-
-
-
-
-
-
USART3_RTS_
DE
Port D PD2
TRACED2
-
-
-
-
-
-
PH0
Port H PH1
PH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1. Refer to Table 16 for AF8 to AF15.
(1)
Table 16. Alternate function AF8 to AF15
AF8
AF9
TSC
AF10
AF11
AF12
AF13
-
AF14
AF15
Port
TIM2/TIM15/
TIM16/LPTIM2
LPUART1
QUADSPI
-
COMP1
EVENOUT
PA0
PA1
-
-
-
-
-
-
-
-
COMP1_OUT
-
-
-
TIM2_ETR
EVENTOUT
EVENTOUT
TIM15_CH1N
QUADSPI_BK1
_NCS
PA2 LPUART1_TX
PA3 LPUART1_RX
-
-
-
-
TIM15_CH1
EVENTOUT
-
-
-
QUADSPI_CLK
-
-
-
-
-
-
-
-
-
TIM15_CH2
LPTIM2_OUT
LPTIM2_ETR
EVENTOUT
EVENTOUT
EVENTOUT
PA4
PA5
-
-
-
-
QUADSPI_BK1
_IO3
PA6 LPUART1_CTS
-
-
-
-
-
-
-
-
TIM16_CH1
-
EVENTOUT
EVENTOUT
QUADSPI_BK1
_IO2
PA7
-
Port A
PA8
PA9
-
-
-
-
-
-
-
-
-
-
-
-
LPTIM2_OUT
TIM15_BKIN
EVENTOUT
EVENTOUT
USB_CRS_SY
NC
PA10
PA11
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
TIM1_BKIN2_C
OMP1
USB_DM
PA12
PA13
PA14
PA15
-
-
-
-
-
USB_DP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
USB_NOE
-
-
-
TSC_G3_IO1
(1)
Table 16. Alternate function AF8 to AF15 (continued)
AF8
AF9
TSC
AF10
AF11
AF12
AF13
AF14
AF15
Port
TIM2/TIM15/
TIM16/LPTIM2
LPUART1
QUADSPI
-
COMP1
-
EVENOUT
QUADSPI_BK1
_IO1
PB0
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
LPUART1_RTS
_DE
QUADSPI_BK1
_IO0
PB1
COMP1_OUT
LPTIM2_IN1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
-
-
TSC_G2_IO1
-
-
TSC_G2_IO2
-
TIM16_BKIN
TSC_G2_IO3
-
TIM16_CH1N
TSC_G2_IO4
-
-
Port B
-
-
-
-
TIM16_CH1
-
-
-
PB10 LPUART1_RX
QUADSPI_CLK
QUADSPI_BK1
_NCS
PB11 LPUART1_TX TSC_SYNC
LPUART1_RTS
-
-
COMP1_OUT
-
-
-
-
EVENTOUT
EVENTOUT
PB12
TSC_G1_IO1
-
TIM15_BKIN
_DE
PB13 LPUART1_CTS TSC_G1_IO2
-
-
-
-
-
-
-
-
-
-
-
-
TIM15_CH1N
TIM15_CH1
TIM15_CH2
EVENTOUT
EVENTOUT
EVENTOUT
PB14
PB15
-
-
TSC_G1_IO3
TSC_G1_IO4
(1)
Table 16. Alternate function AF8 to AF15 (continued)
AF8
AF9
TSC
AF10
AF11
AF12
AF13
AF14
AF15
Port
TIM2/TIM15/
TIM16/LPTIM2
LPUART1
QUADSPI
-
COMP1
-
EVENOUT
PC0 LPUART1_RX
PC1 LPUART1_TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LPTIM2_IN1
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
-
-
-
-
PC2
PC3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LPTIM2_ETR
PC4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC5
-
-
PC6
TSC_G4_IO1
-
PC7
TSC_G4_IO2
-
Port C
PC8
TSC_G4_IO3
-
PC9
TSC_G4_IO4
USB_NOE
PC10
PC11
PC12
PC13
PC14
PC15
TSC_G3_IO2
-
-
-
-
-
-
-
-
-
-
TSC_G3_IO3
TSC_G3_IO4
-
-
-
Port D PD2
PH0
TSC_SYNC
-
-
-
Port H PH1
PH3
EVENTOUT
1. Refer to Table 15 for AF0 to AF7.
STM32L412xx
Memory mapping
5
Memory mapping
Figure 15. STM32L412xx memory map
0xFFFF FFFF
0xE000 0000
0xC000 0000
0xBFFF FFFF
Reserved
Cortex™-M4
0xA000 1400
0xA000 1000
with FPU
Internal
7
6
QUADSPI registers
Peripherals
0x5FFF FFFF
0x5006 0C00
0x4800 0000
0x4002 4400
Reserved
AHB2
Reserved
QUADSPI
registers
AHB1
5
4
0x4002 0000
Reserved
0xA000 1000
0xA000 0000
0x4001 5800
0x4001 0000
0x4000 9800
APB2
Reserved
APB1
QUADSPI Flash
bank
0x9000 0000
0x8000 0000
0x4000 0000
0x1FFF FFFF
3
2
Reserved
0x6000 0000
0x1FFF 7810
Options Bytes
Reserved
0x1FFF 7800
0x1FFF 7400
Peripherals
OTP area
0x4000 0000
0x1FFF 7000
System memory
Reserved
0x2000 A000
0x2000 8000
1
0
0x1FFF 0000
0x1000 2000
SRAM2
SRAM1
SRAM2
0x2000 0000
0x1000 0000
0x0802 0000
Reserved
CODE
Flash memory
Reserved
0x0800 0000
0x0002 0000
0x0000 0000
Flash, system memory
or SRAM, depending on
BOOT configuration
0x0000 0000
Reserved
MSv45997V1
DS12469 Rev 8
69/192
72
Memory mapping
STM32L412xx
(1)
Table 17. STM32L412xx memory map and peripheral register boundary addresses
Bus
Boundary address
Size(bytes)
Peripheral
0x5006 0800 - 0x5006 0BFF
0x5006 0400 - 0x5006 07FF
0x5004 0400 - 5006 07FF
0x5004 0000 - 0x5004 03FF
0x5000 0000 - 0x5003 FFFF
0x4800 2000 - 0x4FFF FFFF
0x4800 1C00 - 0x4800 1FFF
0x4800 1000 - 0x4800 1BFF
0x4800 0C00 - 0x4800 0FFF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0800 - 0x4002 0FFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
1 KB
1 KB
RNG
Reserved
Reserved
ADC
128 KB
1 KB
16 KB
~127 MB
1 KB
Reserved
Reserved
GPIOH
AHB2
3 KB
Reserved
GPIOD
1 KB
1 KB
GPIOC
1 KB
GPIOB
1 KB
GPIOA
-
~127 MB
1 KB
Reserved
TSC
1 KB
Reserved
CRC
1 KB
3 KB
Reserved
FLASH registers
Reserved
RCC
1 KB
AHB1
3 KB
1 KB
2 KB
Reserved
DMA2
1 KB
1 KB
DMA1
70/192
DS12469 Rev 8
STM32L412xx
Memory mapping
(1)
Table 17. STM32L412xx memory map and peripheral register boundary addresses
(continued)
Bus
Boundary address
Size(bytes)
Peripheral
Reserved
0x4001 4800 - 0x4001 FFFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2000 - 0x4001 2BFF
0x4001 1C00 - 0x4001 1FFF
0x4001 0800- 0x4001 1BFF
0x4001 0400 - 0x4001 07FF
0x4001 0200 - 0x4001 03FF
0x4001 0030 - 0x4001 01FF
0x4001 0000 - 0x4001 002F
0x4000 9800 - 0x4000 FFFF
0x4000 9400 - 0x4000 97FF
0x4000 8400 - 0x4000 93FF
0x4000 8000 - 0x4000 83FF
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00- 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 4C00 - 0x4000 53FF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
46 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
3 KB
1 KB
5 KB
1 KB
1 KB
1 KB
1 KB
26 KB
1 KB
4 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
2 KB
1 KB
1 KB
1 KB
TIM16
TIM15
Reserved
USART1
Reserved
SPI1
APB2
TIM1
Reserved
FIREWALL
Reserved
EXTI
COMP
Reserved
SYSCFG
Reserved
LPTIM2
Reserved
LPUART1
LPTIM1
OPAMP
Reserved
PWR
USB SRAM
USB FS
Reserved
CRS
APB1
I2C3
I2C2
I2C1
Reserved
USART3
USART2
Reserved
DS12469 Rev 8
71/192
72
Memory mapping
STM32L412xx
(1)
Table 17. STM32L412xx memory map and peripheral register boundary addresses
(continued)
Bus
Boundary address
Size(bytes)
Peripheral
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 1400 - 0x4000 27FF
0x4000 1000 - 0x4000 13FF
0x4000 0400- 0x4000 0FFF
0x4000 0000 - 0x4000 03FF
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
5 KB
1 KB
3 KB
1 KB
SPI3
SPI2
Reserved
IWDG
WWDG
RTC
APB1
Reserved
TIM6
Reserved
TIM2
1. The gray color is used for reserved boundary addresses.
72/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 16.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 17.
Figure 16. Pin loading conditions
Figure 17. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19210V1
MS19211V1
DS12469 Rev 8
73/192
164
Electrical characteristics
STM32L412xx
6.1.6
Power supply scheme
Figure 18. Power supply scheme
VBAT
Backup circuitry
(LSE, RTC,
Backup registers)
1.55 – 3.6 V
Power switch
VDD
VCORE
n x VDD
Regulator
VDDIO1
OUT
Kernel logic
(CPU, Digital
& Memories)
IO
logic
n x 100 nF
+1 x 4.7 μF
GPIOs
n x VSS
VDDA
IN
VDDA
VREF
ADCs/
OPAMPs/
COMPs/
10 nF
VREF+
VREF-
+1 μF
100 nF +1 μF
VSSA
MS49692V1
Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
74/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
6.1.7
Current consumption measurement
Figure 19. Current consumption measurement scheme with and without external
SMPS power supply
IDD_USB
VDDUSB
IDD_USB
VDDUSB
IDD_VBAT
VBAT
IDD_VBAT
VBAT
IDD
VDD12
SMPS
IDD
VDD
VDD
IDDA
IDDA
VDDA
VDDA
MSv45729V1
The I
parameters given in Table 25 to Table 47 represent the total MCU consumption
DD_ALL
including the current supplying V , V
, V
and V
.
DD
DDA
DDUSB
BAT
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
(1)
Table 18. Voltage characteristics
Symbol
VDDX - VSS
VDD12 - VSS
Ratings
Min
Max
Unit
External main supply voltage (including
VDD, VDDA, VDDUSB, VBAT
-0.3
4.0
V
V
)
External SMPS supply voltage
Input voltage on FT_xxx pins
-0.3
1.32
min (VDD, VDDA, VDDUSB
+ 4.0(3)(4)
)
V
V
SS-0.3
SS-0.3
(2)
V
VIN
Input voltage on TT_xx pins
4.0
4.0
Input voltage on any other pins
VSS-0.3
DS12469 Rev 8
75/192
164
Electrical characteristics
Symbol
STM32L412xx
(1)
Table 18. Voltage characteristics (continued)
Ratings
Min
Max
Unit
Variations between different VDDX power
pins of the same domain
|∆VDDx
|
-
50
mV
Variations between all the different ground
pins(5)
|VSSx-VSS
|
-
50
mV
1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected
current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 19. Current characteristics
Symbol
Ratings
Max
Unit
∑IVDD
∑IVSS
Total current into sum of all VDD power lines (source)(1)(2)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin except FT_f
Output current sunk by any FT_f pin
140
140
100
100
20
IVDD(PIN)
IVSS(PIN)
IIO(PIN)
20
mA
Output current sourced by any I/O and control pin
20
Total output current sunk by sum of all I/Os and control pins(3)
Total output current sourced by sum of all I/Os and control pins(3)
100
100
∑IIO(PIN)
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,
PA5
-5/+0(5)
(4)
IINJ(PIN)
Injected current on PA4, PA5
-5/0
25
∑|IINJ(PIN)
|
Total injected current (sum of all I/Os and control pins)(6)
1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supplies, in the permitted range.
2. Valid also for VDD12 on SMPS packages.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage
characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
76/192
DS12469 Rev 8
STM32L412xx
Symbol
Electrical characteristics
Table 20. Thermal characteristics
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
Maximum junction temperature
–65 to +150
150
°C
°C
DS12469 Rev 8
77/192
164
Electrical characteristics
STM32L412xx
6.3
Operating conditions
6.3.1
General operating conditions
Table 21. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK Internal AHB clock frequency
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
-
-
-
0
0
0
80
80
80
MHz
1.71
VDD
Standard operating voltage
-
3.6
V
V
(1)
ADC or COMP used
1.62
1.8
0
VDDA Analog supply voltage
OPAMP used
ADC, OPAMP, COMP not used
Full frequency range
Up to 26 MHz
-
3.6
1.08
1.00
1.55
3.0
0
VDD12 Standard operating voltage
VBAT Backup operating voltage
VDDUSB USB supply voltage
1.32
V
V
V
3.6
3.6
USB used
USB not used
TT_xx I/O
3.6
-0.3
V
DDIOx+0.3
Min(Min(VDD, VDDA
VDDUSB)+3.6 V,
5.5 V)(2)(3)
,
VIN
I/O input voltage
V
All I/O except TT_xx
-0.3
LQFP64
-
-
-
-
303
317
294
667
235
294
541
76
UFBGA64
LQFP48
Power dissipation at
TA = 85 °C for suffix 6
or
PD
UFQFPN48
WLCSP36
LQFP32
mW
TA = 105 °C for suffix 7(4)
UFQFPN32
LQFP64
-
-
-
-
-
-
-
UFBGA64
LQFP48
79
75
Power dissipation at
PD
UFQFPN48
WLCSP36
LQFP32
167
59
mW
TA = 125 °C for suffix 3(4)
75
UFQFPN32
135
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DS12469 Rev 8
STM32L412xx
Symbol
Electrical characteristics
Table 21. General operating conditions (continued)
Parameter
Conditions
Min
Max
Unit
Maximum power dissipation
Low-power dissipation(5)
Maximum power dissipation
Low-power dissipation(5)
Suffix 6 version
–40
–40
–40
–40
–40
–40
85
Ambient temperature for the
suffix 6 version
105
125
130
105
130
TA
TJ
°C
Ambient temperature for the
suffix 3 version
Junction temperature range
°C
Suffix 3 version
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDUSB)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristics).
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
Table 22. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
-
0
10
100
0
∞
∞
∞
∞
∞
∞
∞
µs/V
tVDD
ULPEN = 0
ULPEN = 1
VDD fall time rate
ms/V
VDDA rise time rate
tVDDA
-
-
VDDA fall time rate
10
0
µs/V
VDDUSB rise time rate
VDDUSB fall time rate
tVDDUSB
10
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature conditions summarized in Table 21: General operating conditions.
Table 23. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Reset temporization after
BOR0 is detected
(2)
tRSTTEMPO
VDD rising
-
250
400
μs
Rising edge
Falling edge
1.62
1.6
1.66
1.64
1.7
(2)
VBOR0
Brown-out reset threshold 0
V
1.69
DS12469 Rev 8
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164
Electrical characteristics
STM32L412xx
Table 23. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.06
1.96
2.26
2.16
2.56
2.47
2.85
2.76
2.1
2.1
2.14
2.04
2.35
2.24
2.66
2.57
2.95
2.86
2.19
2.1
VBOR1
Brown-out reset threshold 1
V
2
2.31
2.20
2.61
2.52
2.90
2.81
2.15
2.05
2.31
2.20
2.46
2.36
2.61
2.52
2.74
2.64
2.91
2.81
2.98
2.90
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
V
V
V
V
V
V
V
V
V
V
Programmable voltage
detector threshold 0
2
2.26
2.15
2.41
2.31
2.56
2.47
2.69
2.59
2.85
2.75
2.92
2.84
2.36
2.25
2.51
2.41
2.66
2.57
2.79
2.69
2.96
2.86
3.04
2.96
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
Hysteresis in
continuous
mode
-
20
-
Vhyst_BORH0 Hysteresis voltage of BORH0
mV
Hysteresis in
other mode
-
-
-
30
100
1.1
-
-
Hysteresis voltage of BORH
Vhyst_BOR_PVD
-
-
mV
µA
(except BORH0) and PVD
BOR(3) (except BOR0) and
1.6
PVD consumption from VDD
IDD
BOR(3) (except BOR0) and
PVD average consumption
from VDD with ENULP = 1
(BOR_PVD)(2)
-
-
-
55
1000
1.26
nA
VDDUSB peripheral voltage
monitoring
VPVM1
1.18
1.22
V
V
Rising edge
Falling edge
1.61
1.6
1.65
1.64
1.69
1.68
VDDA peripheral voltage
monitoring
VPVM3
80/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
Table 23. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions(1)
Min
Typ
Max
Unit
Rising edge
1.78
1.82
1.81
10
1.86
VDDA peripheral voltage
monitoring
VPVM4
V
Falling edge
1.77
1.85
Vhyst_PVM3
Vhyst_PVM4
PVM3 hysteresis
PVM4 hysteresis
-
-
-
-
-
-
mV
mV
10
I
DD (PVM1)
PVM1 consumption from VDD
-
-
-
-
0.2
2
-
-
µA
µA
(2)
IDD
PVM3 and PVM4
consumption from VDD
(PVM3/PVM4)
(2)
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
DS12469 Rev 8
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164
Electrical characteristics
STM32L412xx
6.3.4
Embedded voltage reference
The parameters given in Table 24 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 24. Embedded internal voltage reference
Symbol
VREFINT
Parameter
Conditions
Min
Typ
Max
Unit
Internal reference voltage
–40 °C < TA < +130 °C
1.182 1.212 1.232
V
ADC sampling time when
reading the internal reference
voltage
(1)
tS_vrefint
-
-
-
4(2)
-
8
-
µs
µs
µA
Start time of reference voltage
buffer when ADC is enable
tstart_vrefint
-
-
12(2)
20(2)
VREFINT buffer consumption
from VDD when converted by
ADC
12.5
I
DD(VREFINTBUF)
Internal reference voltage
spread over the temperature
range
ꢀVREFINT
VDD = 3 V
-
5
7.5(2)
50(2)
mV
TCoeff
ACoeff
Temperature coefficient
Long term stability
Voltage coefficient
–40°C < TA < +130°C
1000 hours, T = 25°C
3.0 V < VDD < 3.6 V
-
-
30
ppm/°C
ppm
300 1000(2)
VDDCoeff
-
250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage
VREFINT_DIV2 1/2 reference voltage
VREFINT_DIV3 3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
-
VREFINT
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.
82/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
Figure 20. V
versus temperature
REFINT
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
°C
-40
-20
0
20
Mean
40
60
80
100
120
Min
Max
MSv40169V1
DS12469 Rev 8
83/192
164
Electrical characteristics
STM32L412xx
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 19: Current consumption
measurement scheme with and without external SMPS power supply.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted with the minimum wait states number,
depending on the f
frequency (refer to the table “Number of wait states according
HCLK
to CPU clock (HCLK) frequency” available in the RM0394 reference manual).
•
When the peripherals are enabled f = f
PCLK
HCLK
The parameters given in Table 25 to Table 48 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
84/192
DS12469 Rev 8
Table 25. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF)
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
26 MHz 2.05
16 MHz 1.30
2.10
1.35
2.10
1.40
2.20
1.45
2.35
1.60
1.00
2.20
1.40
0.76
0.45
0.30
0.20
0.15
7.75
7.00
6.25
4.70
3.20
2.40
1.70
235
2.25
1.45
0.78
0.50
0.30
0.25
0.20
7.80
7.00
6.30
4.75
3.25
2.40
1.75
230
2.30
1.50
0.84
0.55
0.40
0.30
0.25
7.80
7.10
6.35
4.80
3.30
2.50
1.80
315
2.40
1.60
0.96
0.70
0.50
0.44
0.40
7.90
7.20
6.40
4.90
3.40
2.60
1.90
455
2.60
1.80
1.25
0.90
0.80
0.70
0.60
8.10
7.40
6.65
5.10
3.60
2.90
2.20
725
8 MHz 0.715 0.730 0.780 0.855
Range 2 4 MHz 0.415 0.430 0.475 0.555 0.710
2 MHz 0.265 0.28 0.325 0.400 0.555
1 MHz 0.190 0.205 0.250 0.325 0.480
100 kHz 0.120 0.135 0.180 0.255 0.410
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
Supply
current in
Run mode
IDD_ALL
(Run)
mA
80 MHz 7.30
72 MHz 6.60
7.35
6.65
5.90
4.40
3.00
2.30
1.60
205
7.40
6.70
6.00
4.50
3.05
2.35
1.65
255
7.55
6.80
6.10
4.60
3.15
2.45
1.75
335
7.70
7.00
6.30
4.80
3.35
2.65
1.90
505
peripherals disable
64 MHz 5.90
Range 1 48 MHz 4.40
32 MHz 3.00
24 MHz 2.30
16 MHz 1.55
2 MHz
1 MHz
190
110
Supply
120
165
250
415
135
145
230
370
645
IDD_ALL
(LPRun)
current in
Low-power all peripherals disable
run mode
fHCLK = fMSI
µA
400 kHz 55.0
100 kHz 26.0
65.5
40.0
115
195
360
75.0
45.0
90.5
65.5
180
325
590
87.5
170
335
160
290
550
1. Guaranteed by characterization results, unless otherwise specified.
Table 26. Current consumption in Run modes, code with data processing running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(V
= 1.10 V)
DD12
Conditions(1)
TYP
Symbol
Parameter
Unit
-
fHCLK
25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
2.62
2.37
2.12
1.58
1.08
0.83
0.56
0.26
0.15
9.53
0.07
2.64
2.39
2.12
1.58
1.08
0.83
0.58
0.26
0.15
0.10
0.07
0.01
2.66
2.41
2.16
1.62
1.10
0.84
0.59
0.28
0.17
0.12
0.09
0.03
2.71
2.44
2.19
1.65
1.13
0.88
0.63
0.31
0.20
0.14
0.12
0.06
2.77
2.52
2.26
1.73
1.20
0.95
0.68
0.36
0.26
0.20
0.17
0.12
fHCLK = fHSE up to 48MHz included, bypass mode
PLL ON above
48 MHz all peripherals disable
Supply current in Run
mode
IDD_ALL(Run)
mA
4 MHz
2 MHz
1 MHz
100 kHz 0.01
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V
Table 27. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART disable
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
26 MHz 2.40
16 MHz 1.70
2.45
1.75
2.50
1.80
2.55
1.85
1.10
2.75
2.05
1.25
2.60
1.85
1.05
0.61
0.40
0.25
0.14
8.20
7.40
7.40
6.30
4.50
3.40
2.50
325
2.65
1.90
1.10
0.63
0.40
0.30
0.20
8.30
7.45
7.45
6.35
4.55
3.40
2.50
360
2.70
1.95
1.15
0.70
0.50
0.34
0.25
8.40
7.50
7.50
6.50
4.70
3.50
2.60
425
2.80
2.05
1.25
0.80
0.60
0.50
0.40
8.50
7.60
7.60
6.65
4.80
3.60
2.70
565
3.00
2.30
1.50
1.10
0.80
0.70
0.60
8.80
7.80
7.80
6.90
5.10
3.90
3.00
840
8 MHz 0.970 0.985 1.05
Range 2
4 MHz 0.570 0.585 0.630 0.710 0.865
2 MHz 0.340 0.355 0.400 0.475 0.635
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
1 MHz 0.230 0.240 0.285 0.365
0.52
Supply
current in
Run mode
100 kHz 0.125 0.140 0.185 0.260 0.415
IDD_ALL
(Run)
mA
80 MHz 7.65
72 MHz 6.95
64 MHz 6.90
48 MHz 5.85
32 MHz 4.20
24 MHz 3.15
16 MHz 2.25
7.70
6.95
6.95
5.90
4.20
3.20
2.30
290
7.85
7.05
7.05
6.00
4.30
3.25
2.35
340
8.00
7.15
7.20
6.15
4.45
3.35
2.50
425
8.20
7.35
7.40
6.35
4.65
3.55
2.65
590
peripherals disable
Range 1
2 MHz
1 MHz
275
155
Supply
165
83.0
45.5
210
130
92.0
295
215
175
460
280
340
185
90.5
48.0
195
108
69
275
195
155
420
340
300
690
600
570
IDD_ALL
(LPRun)
current in fHCLK = fMSI
Low-power all peripherals disable
run
µA
400 kHz 69.0
100 kHz 32.0
1. Guaranteed by characterization results, unless otherwise specified.
Table 28. Current consumption in Run modes, code with data processing running from Flash,
ART disable and power supplied by external SMPS (V
= 1.10 V)
DD12
Conditions(1)
TYP
25 °C 55 °C 85 °C 105 °C 125 °C
Uni
t
Symbol
Parameter
-
fHCLK
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
2.75
2.50
2.48
2.10
1.51
1.13
0.81
0.35
0.20
12.22
0.08
2.77
2.50
2.50
2.12
1.51
1.15
0.83
0.35
0.21
0.13
0.09
0.02
2.82
2.53
2.53
2.16
1.55
1.17
0.84
0.38
0.23
0.14
0.10
0.03
2.88
2.57
2.59
2.21
1.60
1.20
0.90
0.40
0.26
0.17
0.13
0.06
2.95
2.64
2.66
2.28
1.67
1.28
0.95
0.45
0.31
0.23
0.19
0.12
Supply current in Run
mode
fHCLK = fHSE up to 48MHz included, bypass mode
PLL ON above 48 MHz all peripherals disable
IDD_ALL(Run)
mA
4 MHz
2 MHz
1 MHz
100 kHz 0.01
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
DD12 = 1.10 V
V
Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
Voltage
scaling
105
°C
125
°C
105
°C
125
°C
-
fHCLK
25 °C 55 °C 85 °C
25 °C 55 °C 85 °C
26 MHz 2.00
16 MHz 1.30
2.05
1.30
2.10
1.35
2.15
1.45
2.35
1.60
2.20
1.40
0.75
2.20
1.45
0.77
0.46
0.30
0.22
0.15
7.65
6.95
6.20
4.65
3.15
2.40
1.70
225
2.25
1.45
0.83
0.52
0.37
0.29
0.23
7.75
7.00
6.25
4.70
3.20
2.50
1.75
300
2.35
1.55
0.94
0.64
0.49
0.42
0.35
7.75
7.05
6.30
4.80
3.30
2.60
1.85
450
2.55
1.80
1.20
0.90
0.75
0.67
0.61
8.00
7.25
6.50
5.00
3.55
2.85
2.10
720
8 MHz 0.705 0.720 0.765 0.845 1.00
Range 2
4 MHz 0.410 0.425 0.470 0.550 0.700 0.44
2 MHz 0.265 0.275 0.320 0.395 0.555 0.28
1 MHz 0.190 0.200 0.245 0.325 0.475 0.21
100 kHz 0.120 0.135 0.180 0.255 0.410 0.14
fHCLK = fHSE up to
48MHz included,
bypass mode
PLL ON above
48 MHz all
Supply
current in
Run mode
IDD_ALL
(Run)
mA
80 MHz 7.15
72 MHz 6.45
64 MHz 5.75
48 MHz 4.20
32 MHz 2.95
24 MHz 2.25
16 MHz 1.55
7.20
6.50
5.80
4.35
2.95
2.25
1.55
190
7.25
6.55
5.85
4.40
3.00
2.30
1.60
240
7.45
6.75
6.05
4.50
3.10
2.40
1.70
320
7.55
6.85
6.15
7.70
3.30
2.60
1.85
485
7.65
6.90
6.15
4.65
3.15
2.40
1.65
215
peripherals disable
Range 1
2 MHz
1 MHz
180
Supply
fHCLK = fMSI
all peripherals disable
FLASH in power-down
90.5
110
56.0
32.0
155
105
78.5
235
185
160
400
350
325
120
60.0
33.5
135
76.5
53.5
220
165
140
360
315
285
640
565
555
IDD_ALL
(LPRun)
current in
low-power
run mode
µA
400 kHz 40.5
100 kHz 17.5
1. Guaranteed by characterization results, unless otherwise specified.
Table 30. Current consumption in Run, code with data processing running from
SRAM1 and power supplied by external SMPS (V
= 1.10 V)
DD12
Conditions(1)
TYP
25 °C 55 °C 85 °C 105 °C 125 °C
Symbol
Parameter
Unit
-
fHCLK
80 MHz 2.57
72 MHz 2.32
64 MHz 2.07
48 MHz 1.55
32 MHz 1.06
24 MHz 0.81
16 MHz 0.56
2.59
2.34
2.08
1.56
1.06
0.81
0.56
0.26
0.15
0.10
0.07
0.01
2.61
2.35
2.10
1.58
1.08
0.83
0.58
0.28
0.17
0.12
0.09
0.03
2.68
2.43
2.17
1.62
1.11
0.86
0.61
0.30
0.20
0.15
0.14
0.06
2.71
2.46
2.21
1.69
1.19
0.93
0.67
0.36
0.25
0.20
0.17
0.12
f
HCLK = fHSE up to 48MHz included, bypass mode
IDD_ALL(Run) Supply current in Run mode PLL ON above
48 MHz all peripherals disable
mA
8 MHz
4 MHz
2 MHz
1 MHz
0.25
0.15
9.53
0.07
100 kHz 0.01
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
DD12 = 1.10 V
V
STM32L412xx
Electrical characteristics
Table 31. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF)
Conditions
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
Reduced code(1)
Coremark
2.05
2.30
2.35
2.25
1.95
7.30
8.15
8.35
8.10
7.20
190
79
88
Dhrystone 2.1
Fibonacci
mA
90
µA/MHz
fHCLK = fHSE up
to 48 MHz
87
Supply
included, bypass
While(1)
75
IDD_ALL
(Run)
current in mode PLL ON
Run mode above 48 MHz
all peripherals
Reduced code(1)
91
Coremark
102
104
101
90
disable
Dhrystone 2.1
Fibonacci
mA
µA/MHz
µA/MHz
While(1)
Reduced code(1)
95
Coremark
205
103
110
103
113
Supply
current in
IDD_ALL
(LPRun)
fHCLK = fMSI = 2 MHz
Low-power all peripherals disable
run
Dhrystone 2.1
Fibonacci
220
µA
205
While(1)
225
1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 32. Typical current consumption in Run, with different codes running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(V
= 1.10 V)
DD12
Conditions(1)
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
Reduced code(2) 0.88
34
38
39
37
32
39
44
45
44
39
Coremark
Dhrystone 2.1
Fibonacci
While(1)
0.99
1.01
0.97
0.84
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
Supply
IDD_ALL
(Run)
current in ON above
Run mode 48 MHz
mA
µA/MHz
Reduced code(2) 3.15
all peripherals
disable
Coremark
Dhrystone 2.1
Fibonacci
While(1)
3.52
3.60
3.49
3.11
DS12469 Rev 8
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164
Electrical characteristics
STM32L412xx
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:
SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 33. Typical current consumption in Run, with different codes running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(V
= 1.00 V)
DD12
Conditions(1)
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
fHCLK = fHSE up to
48 MHz included,
bypass mode PLL
Reduced code(2) 0.73
28
32
32
31
Coremark
0.82
0.84
0.80
Supply
IDD_ALL
(Run)
Dhrystone 2.1
Fibonacci
current in ON above
Run mode 48 MHz
mA
µA/MHz
all peripherals
disable
While(1)
0.70
27
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:
SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
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DS12469 Rev 8
STM32L412xx
Electrical characteristics
Table 34. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART disable
Conditions
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
Reduced code(1)
Coremark
2.40
2.15
2.20
2.05
1.90
7.65
6.95
7.00
6.60
6.85
275
92
83
mA
µA/MHz
Dhrystone 2.1
Fibonacci
85
fHCLK = fHSE up to
48 MHz included,
bypass mode
79
Supply
While(1)
Reduced code(1)
73
IDD_ALL
(Run)
current in PLL ON above
Run mode 48 MHz
all peripherals
96
Coremark
87
disable
mA
µA
µA/MHz
µA/MHz
Dhrystone 2.1
Fibonacci
88
83
While(1)
Reduced code(1)
86
138
150
158
153
193
Supply
Coremark
300
IDD_ALL
(LPRun)
current in fHCLK = fMSI = 2 MHz
Low-power all peripherals disable
run
Dhrystone 2.1
Fibonacci
315
305
While(1)
385
1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 35. Typical current consumption in Run modes, with different codes running from
Flash, ART disable and power supplied by external SMPS (V
= 1.10 V)
DD12
Conditions(1)
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
Reduced code(2)
Coremark
1.04
0.93
0.95
0.88
0.82
3.30
3.00
3.02
2.85
2.95
40
36
37
34
32
41
37
38
36
37
Dhrystone 2.1
Fibonacci
fHCLK = fHSE up to
48 MHz included,
bypass mode
Supply
current in
While(1)
Reduced code(2)
IDD_ALL
(Run)
PLL ON above
mA
µA/MHz
Run mode 48 MHz
all peripherals
disable
Coremark
Dhrystone 2.1
Fibonacci
While(1)
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
DS12469 Rev 8
93/192
164
Electrical characteristics
STM32L412xx
Table 36. Typical current consumption in Run modes, with different codesrunning from
Flash, ART disable and power supplied by external SMPS (V
= 1.00 V)
DD12
Conditions(1)
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz
Reduced code(2)
Coremark
0.86
0.77
0.78
0.73
0.68
33
29
30
28
26
Supply
current in
Run mode
IDD_ALL
(Run)
mA
µA/MHz
Dhrystone 2.1
Fibonacci
all peripherals
While(1)
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 37. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1
Conditions
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
Reduced code(1)
Coremark
2.00
2.00
2.05
2.00
1.85
7.15
7.00
7.15
7.10
6.60
180
77
77
79
77
71
89
88
89
89
83
90
90
93
85
85
mA
µA/MHz
Dhrystone 2.1
Fibonacci
fHCLK = fHSE up to
48 MHz included,
bypass mode
Supply
While(1)
Reduced code(1)
IDD_ALL
(Run)
current in PLL ON above
Run mode 48 MHz all
peripherals
Coremark
disable
mA
µA
µA/MHz
µA/MHz
Dhrystone 2.1
Fibonacci
While(1)
Reduced code(1)
Supply
Coremark
180
IDD_ALL
(LPRun)
current in fHCLK = fMSI = 2 MHz
Low-power all peripherals disable
run
Dhrystone 2.1
Fibonacci
185
170
While(1)
170
1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
94/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
Table 38. Typical current consumption in Run, with different codes running from
SRAM1 and power supplied by external SMPS (V
Conditions(1)
= 1.10 V)
DD12
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
Reduced code(2)
Coremark
0.86
0.86
0.88
0.86
0.80
3.08
3.02
3.08
3.06
2.85
33
33
34
33
31
39
38
39
38
36
Dhrystone 2.1
Fibonacci
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz all
Supply
current in
Run mode
While(1)
Reduced code(2)
IDD_ALL
(Run)
mA
µA/MHz
Coremark
peripherals disable
Dhrystone 2.1
Fibonacci
While(1)
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
Table 39. Typical current consumption in Run, with different codes running from
SRAM1 and power supplied by external SMPS (V
Conditions(1)
= 1.00 V)
DD12
TYP
TYP
Symbol
Parameter
Unit
Unit
Voltage
scaling
-
Code
25 °C
25 °C
Reduced code(2)
Coremark
0.71
0.71
0.73
0.71
0.66
27
27
28
27
25
fHCLK = fHSE up to
48 MHz included,
bypass mode
PLL ON above
48 MHz all
Supply
current in
Run mode
IDD_ALL
(Run)
mA
µA/MHz
Dhrystone 2.1
Fibonacci
peripherals disable
While(1)
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V
2. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
DS12469 Rev 8
95/192
164
Table 40. Current consumption in Sleep and Low-power sleep modes, Flash ON
Conditions TYP
MAX(1)
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
26 MHz 0.535 0.550 0.600 0.680 0.835
16 MHz 0.375 0.390 0.435 0.515 0.670
8 MHz 0.245 0.260 0.305 0.385 0.540
4 MHz 0.180 0.195 0.240 0.315 0.470
2 MHz 0.150 0.160 0.205 0.285 0.435
1 MHz 0.130 0.145 0.190 0.265 0.420
100 kHz 0.115 0.130 0.175 0.250 0.405
0.58
0.41
0.27
0.20
0.17
0.15
0.13
1.80
1.60
1.45
1.10
0.78
0.62
0.47
71.0
0.60
0.43
0.29
0.22
0.18
0.16
0.15
1.80
1.65
1.50
1.15
0.80
0.64
0.48
91.5
0.66
0.50
0.36
0.29
0.25
0.24
0.22
1.85
1.70
1.55
1.20
0.87
0.72
0.56
175
0.79
0.62
0.49
0.42
0.38
0.36
0.35
1.95
1.80
1.65
1.35
1.05
0.86
0.71
315
1.05
0.88
0.74
0.67
0.63
0.62
0.60
2.25
2.10
1.95
1.65
1.35
1.15
1.00
600
Range 2
f
HCLK = fHSE up
to 48 MHz
included, bypass
Supply
IDD_ALL
(Sleep)
current in mode
mA
sleep
mode,
pll ON above
80 MHz 1.65
72 MHz 1.50
64 MHz 1.35
48 MHz 1.00
1.70
1.55
1.40
1.05
1.75
1.60
1.45
1.10
1.85
1.70
1.55
1.2
2.00
1.85
1.70
1.35
1.05
48 MHz all
peripherals
disable
Range 1
32 MHz 0.725 0.740 0.795 0.885
24 MHz 0.575 0.595 0.650 0.740 0.910
16 MHz 0.425 0.440 0.495 0.585 0.760
2 MHz
1 MHz
52.5
37.0
66.5
51.5
39.0
33.5
115
97.5
85.0
80.5
195
180
170
165
360
345
330
325
Supply
current in
low-power
sleep
55.0
41.0
36.0
73.0
63.0
57.5
165
150
145
295
280
280
575
565
560
IDD_ALL
(LPSleep)
fHCLK = fMSI
µA
all peripherals disable
400 kHz 25.5
100 kHz 18.5
mode
1. Guaranteed by characterization results, unless otherwise specified.
Table 41. Current consumption in Sleep, Flash ON and power supplied by external SMPS
(V = 1.10 V)
DD12
Conditions(1)
TYP
Symbol
Parameter
Unit
-
fHCLK
25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz
72 MHz
64 MHz
48 MHz
32 MHz
24 MHz
16 MHz
8 MHz
0.59
0.54
0.49
0.36
0.26
0.21
0.15
0.09
0.06
5.39
0.05
0.01
0.61
0.56
0.50
0.38
0.27
0.21
0.16
0.09
0.07
0.06
0.05
0.01
0.63
0.58
0.52
0.40
0.29
0.23
0.18
0.11
0.09
0.07
0.07
0.03
0.67
0.61
0.56
0.43
0.32
0.27
0.21
0.14
0.11
0.10
0.10
0.06
0.72
0.67
0.61
0.49
0.38
0.33
0.27
0.19
0.17
0.15
0.15
0.12
fHCLK = fHSE up to 48 MHz included, bypass
mode
pll ON above
I
DD_ALL(Sleep) Supply current in sleep mode,
mA
48 MHz all peripherals disable
4 MHz
2 MHz
1 MHz
100 kHz
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V
Table 42. Current consumption in Low-power sleep modes, Flash in power-down
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
Voltage
scaling
-
fHCLK
25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
2 MHz
1 MHz
50
35
20
15
60
45
32
25
105
89.0
76.5
71.5
185
170
155
150
350
335
320
315
63
46
32
25
83
65
51
46
170
150
135
135
300
285
270
270
585
570
560
555
Supply current
in low-power
sleep mode
IDD_ALL
(LPSleep)
fHCLK = fMSI
all peripherals disable
µA
400 kHz
100 kHz
1. Guaranteed by characterization results, unless otherwise specified.
Table 43. Current consumption in Stop 2 mode
Conditions TYP
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
MAX(1)
Symbol
Parameter
Unit
-
1.8 V 0.77
2.4 V 0.78
2.35
2.35
2.40
2.55
2.35
2.35
2.65
2.90
2.70
2.90
3.10
3.35
2.65
2.90
3.15
3.55
2.45
2.60
2.75
3.05
8.60
8.75
9.00
9.40
9.35
9.65
10.0
10.5
9.00
9.30
9.65
10.0
9.55
10.0
10.5
11.5
9.35
9.70
10.0
11.0
20.5
21.0
21.5
22.5
21.0
22.0
22.5
24.0
21.0
21.5
22.5
23.5
21.5
22.0
23.0
24.5
21.5
22.0
23.0
24.0
46.0
47.0
49.0
51.5
46.5
48.0
50.0
52.5
46.0
47.5
49.5
52.0
46.5
48.5
50.5
53.0
46.5
48.0
50.0
52.5
2.0
5.6
21.5
51.0
115
2.1
5.8
22.0
52.5
120
-
3 V
0.79
2.1
5.9
22.5
54.0
125
Supply current in
Stop 2 mode,
RTC disabled
3.6 V 0.84
1.8 V 0.72
2.4 V 0.74
2.3
6.1
23.0
56.0
130
IDD_ALL
(Stop 2)
µA
-
-
-
-
-
-
-
-
-
-
ENULP = 1
3 V
0.75
-
-
-
-
-
3.6 V 0.79
1.8 V 1.05
2.4 V 1.10
-
-
-
-
-
2.5
6.2
22.0
51.5
120
2.8
6.4
22.5
53.0
120
RTC clocked by LSI
3 V
1.20
3.0
6.8
23.0
54.5
125
3.6 V 1.30
1.8 V 1.00
2.4 V 1.05
3.3
7.2
24.5
57.0
130
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IDD_ALL
Supply current in RTC clocked by LSI
(Stop 2 with Stop 2 mode,
RTC) RTC enabled
ENULP = 1
LPCAL = 1
µA
3 V
1.10
3.6 V 1.20
1.8 V 0.86
2.4 V 0.88
RTC clocked by LSI
ENULP = 1
LPCAL = 1
3 V
0.93
LSIPREDIV = 1
3.6 V 0.98
Table 43. Current consumption in Stop 2 mode (continued)
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 1.35
2.4 V 1.60
2.85
3.15
3.85
6.60
2.80
3.10
3.90
6.75
2.65
2.75
2.90
3.10
2.55
2.75
3.00
3.25
9.15
9.60
11.0
15.0
9.70
10.5
11.5
16.0
8.85
9.10
9.45
9.95
9.50
9.90
10.5
11.0
21.0
22.0
24.0
29.5
21.5
22.5
25.0
30.5
20.5
21.0
22.0
23.0
21.0
22.0
23.0
25.0
46.0
48.0
51.5
58.5
46.5
48.5
52.5
59.5
47.5
49.0
51.0
53.0
48.0
49.5
52.0
54.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked by LSE
bypassed at 32768 Hz
3 V
2.00
3.6 V 3.90
1.8 V 1.20
2.4 V 1.35
RTC clocked by LSE
bypassed at 32768 Hz,
ENULP = 1,
3 V
1.80
LPCAL = 1
IDD_ALL
Supply current in
3.6 V 3.65
1.8 V 1.20
2.4 V 1.25
(Stop 2 with Stop 2 mode,
µA
RTC)
RTC enabled
RTC clocked by LSE
quartz in low drive
mode
3 V
1.35
3.6 V 1.50
1.8 V 1.00
2.4 V 1.10
RTC clocked by LSE
quartz(2) in low drive
mode, ENULP = 1,
LPCAL = 1
3 V
1.15
3.6 V 1.25
Wakeup clock is
MSI = 48 MHz,
voltage Range 1.
3 V
3 V
3 V
185
155
152
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
See (3)
.
Wakeup clock is
MSI = 4 MHz,
voltage Range 2.
Supply current
during wakeup
from Stop 2
mode
IDD_ALL
(wakeup from
Stop2)
mA
See (3)
.
Wakeup clock is
HSI16 = 16 MHz,
voltage Range 1.
See (3)
.
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
Table 44. Current consumption in Stop 1 mode
Conditions TYP
25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
MAX(1)
Symbol
Parameter
Unit
-
-
VDD
1.8 V
2.4 V
3 V
3.95
3.95
4.00
4.10
4.40
4.60
4.75
5.05
4.50
4.70
5.35
7.20
4.25
4.35
4.40
4.50
13.0
13.0
13.5
13.5
13.5
14.0
14.0
14.5
13.5
14.0
14.5
17.5
13.5
13.5
13.5
14.0
47.5
48.0
48.0
48.5
48.0
48.5
48.5
49.5
48.5
49.0
50.0
54.5
47.5
48.0
48.0
49.0
110
110
110
110
110
110
110
115
110
110
115
120
110
110
110
125
230
230
235
240
230
235
235
240
230
230
240
245
-
7.40
7.50
7.30
7.85
8.05
8.10
8.20
8.55
11.5
29.0
36.0
26.0
-
24.5
24.5
24.5
25.0
24.5
25.0
25.5
27.0
26.5
31.5
31.5
28.0
-
87.0
86.0
87.0
90.0
86.5
90.0
89.0
89.5
86.0
90.0
87.5
88.0
-
190
190
195
195
190
195
195
195
190
190
195
195
-
395
395
400
405
395
395
400
405
395
395
400
405
-
µA
Supplycurrent
in Stop 1
mode,
RTC disabled
IDD_ALL
(Stop 1)
-
3.6 V
1.8 V
2.4 V
3 V
RTC clocked by LSI
3.6 V
1.8 V
2.4 V
3 V
Supplycurrent
in stop 1
mode,
IDD_ALL
(Stop 1 with
RTC)
RTC clocked by LSE
bypassed at 32768 Hz
µA
RTC enabled
3.6 V
1.8 V
2.4 V
3 V
RTC clocked by LSE quartz(2)
in low drive mode
-
-
-
-
-
-
-
-
-
-
-
-
3.6 V
-
-
-
-
-
-
Wakeup clock MSI = 48 MHz,
voltage Range 1.
3 V
3 V
1.15
1.25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
See (3)
.
Wakeup clock MSI = 4 MHz,
voltage Range 2.
Supplycurrent
during
wakeup from
Stop 1
IDD_ALL
(wakeup
from Stop1)
mA
See (3)
.
Wakeup clock
HSI16 = 16 MHz,
voltage Range 1.
3 V
1.20
-
-
-
-
-
-
-
-
-
See (3)
.
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
Table 45. Current consumption in Stop 0
TYP
Conditions
VDD
MAX(1)
Symbol
Parameter
Unit
25 °C 55 °C 85 °C
105 °C 125 °C 25 °C
55 °C
85 °C 105 °C 125 °C
1.8 V
2.4 V
3 V
110
110
115
115
125
125
125
130
165
170
170
175
240
240
245
250
380
385
385
390
130
130
130
135
145
145
145
150
215
215
220
220
340
340
345
345
585
585
590
595
Supply current
in Stop 0 mode,
RTC disabled
IDD_ALL
(Stop 0)
µA
3.6 V
1. Guaranteed by characterization results, unless otherwise specified.
Table 46. Current consumption in Standby mode
Conditions TYP
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
MAX(1)
Symbol
Parameter
Unit
-
1.8 V
2.4 V 105
3 V 120
3.6 V 150
95
255
290
354
410
225
315
430
570
450
530
635
775
415
540
710
915
1150
1300
1550
1850
1400
1800
2400
3050
1300
1500
1800
2200
1450
1950
2550
3300
3200
3600
8350
9500
115
405
2750
3250
3750
7150 19500
8350 23000
9600 26000
175
540
No independent watchdog
4350 11500
5050 13000
215
650
280
835
4450 11500 29500
1.8 V
2.4 V
3 V
32
46
66
3850
9000
115
405
2750
3250
3750
7250 19500
8350 23000
9600 26000
4500 10500
5450 12500
6350 14500
175
540
No independent watchdog
ENULP = 1
Supply current
in Standby
215
650
3.6 V 115
1.8 V 295
2.4 V 350
280
835
4450 11500 29500
IDD_ALL
(Standby) registers
retained),
mode (backup
nA
3250
3750
8250
9450
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
With independent
watchdog
RTC disabled
3 V
415
4450 11500
5350 13500
3.6 V 505
1.8 V 230
2.4 V 290
3900
8850
With independent
watchdog
ENULP = 1
4600 10550
5500 12500
6600 14500
3 V
365
3.6 V 460
Table 46. Current consumption in Standby mode (continued)
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 480
2.4 V 615
635
800
995
1500
1800
2150
3450
4050
8400
9700
560
770
975
900
3180
3850
7500 19500
880 23000
1200
RTC clocked by LSI, no
independent watchdog
3 V
775
4850 11500
1450
4450 10500 26000
5300 12000 29500
3.6 V 970 1250 2650
5850 14000 1250
1850
1.8 V 330
2.4 V 435
515
690
915
1600
2100
2750
4000
9000
560
900
3180
3850
7500 19500
8800 23000
RTC clocked by LSI, no
independent watchdog
ENULP = 1
4750 10500
5750 12500
770
1200
Supply current
in Standby
mode (backup
registers
retained),
RTC enabled
3 V
565
975
1450
4450 10500 26000
5300 12000 29500
IDD_ALL
(Standby
with RTC)
3.6 V 725 1200 3600
6900
3500
4100
1500
8450
9850
1250
1850
nA
1.8 V 530
2.4 V 675
680
855
1550
1850
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked by LSI, with
independent watchdog
3 V 850 1050 2250
3.6 V 1050 1350 2750
4900 11500
4900 11500
1.8 V 370
2.4 V 495
560
755
985
1600
2150
2850
4050
9050
RTC clocked by LSI, with
independent watchdog
ENULP = 1
4800 10500
5800 12500
6950 15000
3 V
645
3.6 V 825 1300 3700
Table 46. Current consumption in Standby mode (continued)
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
-
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 480
2.4 V 615
640
800
995
1500
1800
2150
3450
4000
8100
9300
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC clocked by LSE
bypassed at 32768 Hz
3 V
775
4800 11000
5800 13000
3.6 V 960 1250 2650
1.8 V 330
2.4 V 435
510
695
910
1600
2100
2750
4000
8800
RTC clocked by LSE
bypassed at 32768 Hz
ENULP = 1
4750 10000
5700 12000
6900 14500
Supply current
in Standby
mode (backup
registers
retained),
RTC enabled
(cont.)
3 V
565
IDD_ALL
(Standby
with RTC)
(cont.)
3.6 V 730 1200 3600
nA
1.8 V 415
2.4 V 485
575
670
800
985
450
565
705
915
230
230
235
240
1450
1650
1950
2400
1600
2050
2650
3400
750
3400
3900
4600
-
-
-
RTC clocked by LSE
quartz (2) in low drive mode
3 V
550
-
3.6 V 690
1.8 V 245
2.4 V 290
-
4000
4650
5500
-
-
-
RTC clocked by LSE
quartz (2) in low drive mode
ENULP = 1
3 V
355
-
LPCAL = 1
3.6 V 450
1.8 V 100
2.4 V 100
-
Supply current
to be added in
Standby mode
when SRAM2
is retained
1600
1650
1700
1700
3500
3500
3500
3500
750
IDD_ALL
-
nA
(SRAM2)(3)
3 V
100
750
3.6 V 100
750
IDD_ALL
(wakeup
from
Supply current
during wakeup
from Standby
mode
Wakeup clock is
MSI = 4 MHz.
3 V
1.25
-
-
-
-
-
-
-
-
-
mA
See (4)
.
Standby)
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby
+ RTC) + IDD_ALL(SRAM2).
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
Table 47. Current consumption in Shutdown mode
Conditions TYP
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
MAX(1)
Symbol
Parameter
Unit
-
Supply current
in Shutdown
mode
(backup
registers
1.8 V
2.4 V
3 V
16
22
31
100
120
155
600
705
870
1850
2150
2650
5450
6250
7700
56
65
97
310
365
600
1200
1350
1700
3350
9550
3800 11000
4750 12500
IDD_ALL
(Shutdown)
-
nA
retained) RTC
disabled
3.6 V
52
220
1150
3350
9350
95
440
1850
5050 14500
1.8 V 210
2.4 V 315
300
445
820
2050
2650
5750
6950
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1100
RTC clocked by LSE
bypassed at 32768 Hz
3 V
625
1000 2200 44000 10000
1650 3500 5600 14500
3.6 V 820
1.8 V 210
2.4 V 315
300
445
820
2050
2650
5750
6950
RTC clocked by LSE
bypassed at 32768 Hz
ENULP = 1
1100
Supply current
in Shutdown
mode
(backup
registers
3 V
625
1000 2200 44000 10000
1650 3500 5600 14500
IDD_ALL
(Shutdown
with RTC)
3.6 V 820
1.8 V 325
2.4 V 400
nA
425
515
630
795
325
380
455
575
930
1100
1350
1750
830
2200
2550
3100
-
-
-
-
-
-
-
-
-
RTC clocked by LSE
quartz (2) in low drive
mode
retained) RTC
enabled
3 V
475
3.6 V 595
1.8 V 230
2.4 V 270
2050
2400
1950
-
RTC clocked by LSE
quartz (2) in low drive
mode ENULP = 1
975
3 V
320
1200
1500
3.6 V 400
Supply current
during wakeup
from Shutdown
mode
Wakeup clock is
MSI = 4 MHz.
IDD_ALL
(wakeup from
Shutdown)
3 V
0.78
-
-
-
-
-
-
-
-
-
mA
See (3)
.
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
Table 48. Current consumption in VBAT mode
Conditions
TYP
MAX(1)
Symbol
Parameter
Unit
-
VBAT
25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V
2.4 V
3 V
2
3
12
14
66
73
195
215
540
600
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RTC disabled
5
16
92
265
730
3.6 V
1.8 V
2.4 V
3 V
6
30
161
460
575
595
820
460
1250
1750
1950
2550
2950
IDD_VBAT
(VBAT)
Backup domain
supply current
nA
300
380
445
495
455
515
550
630
990
RTC enabled and
clocked by LSE
quartz(2)
1050
1200
1500
3.6 V
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Electrical characteristics
STM32L412xx
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 69: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 49: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
ISW = VDDIOx × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the I/O supply voltage
DDIOx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
+ C
S
INT
EXT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
108/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 49. The MCU is placed
under the following conditions:
•
•
All I/O pins are in Analog mode
The given value is calculated by measuring the difference of the current consumptions:
–
–
when the peripheral is clocked on
when the peripheral is clocked off
•
•
Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in
Table 49. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 49. Peripheral current consumption
Low-power run
Peripheral
Range 1
Range 2
Unit
and sleep
Bus Matrix(1)
ADC clock domain
CRC
3.0
2.2
0.5
1.3
1.3
5.9
1.6
1.5
1.7
0.6
6.9
2.2
0.5
0.7
0.9
1.5
21.9
0.8
1.7
0.3
2.9
1.8
0.3
1.2
1.2
4.9
1.5
1.4
1.6
0.5
7.0
NA
NA
0.6
0.7
1.3
19.2
0.6
1.1
0.3
2.8
1.8
0.2
1.1
1.1
5.6
1.3
1.3
1.5
0.6
5.6
NA
NA
0.7
0.8
1.3
20.5
0.8
2.1
0.5
DMA1
DMA2
FLASH
GPIOA(2)
GPIOB(2)
)
AHB
GPIOC(2)
GPIOH(2)
QSPI
µA/MHz
RNG independent clock domain
RNG clock domain
SRAM1
SRAM2
TSC
All AHB Peripherals
AHB to APB1 bridge(3)
RTCA
CRS
APB1
USB FS independent clock
domain
2.8
2.2
NA
NA
NA
NA
USB FS clock domain
DS12469 Rev 8
109/192
164
Electrical characteristics
STM32L412xx
Table 49. Peripheral current consumption (continued)
Low-power run
Peripheral
Range 1
Range 2
Unit
and sleep
I2C1 independent clock domain
I2C1 clock domain
3.4
1.0
3.4
1.0
2.8
0.9
2.8
0.9
2.8
0.9
2.3
0.4
3.3
0.9
3.3
0.9
2.4
0.7
I2C2 independent clock domain
I2C2 clock domain
I2C3 independent clock domain
I2C3 clock domain
LPUART1 independent clock
domain
1.8
0.6
2.8
0.8
2.9
1.6
0.6
2.3
0.4
2.6
1.7
1.7
2.7
0.7
3.8
LPUART1 clock domain
LPTIM1 independent clock
domain
LPTIM1 clock domain
LPTIM2 independent clock
domain
LPTIM2 clock domain
0.8
0.4
0.4
1.7
1.7
6.2
1.0
0.7
0.2
0.1
1.5
1.4
5.0
0.6
0.8
0.4
0.4
1.5
1.5
5.8
0.9
APB1
µA/MHz
OPAMP
PWR
SPI2
SPI3
TIM2
TIM6
USART2 independent clock
domain
4.0
1.3
4.2
3.5
0.8
3.4
3.7
1.1
4.1
USART2 clock domain
USART3 independent clock
domain
USART3 clock domain
WWDG
1.5
0.5
1.1
0.5
1.3
0.5
All APB1 on
41.4
28.5
38.9
110/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
Table 49. Peripheral current consumption (continued)
Low-power run
and sleep
Peripheral
Range 1
Range 2
Unit
AHB to APB2(4)
FW
1.0
0.2
1.7
0.6
8.1
3.7
2.6
0.9
0.2
1.6
0.5
6.4
3.0
2.1
0.9
0.2
1.7
0.6
7.6
3.4
2.5
SPI1
SYSCFG/COMP
TIM1
APB2
µA/MHz
TIM15
TIM16
USART1 independent clock
domain
4.1
4.1
4.4
USART1 clock domain
All APB2 on
ALL
1.5
1.2
1.6
19.2
82.5
16.1
63.8
17.8
77.2
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when
the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current
consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog
mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).
3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.
4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.
The consumption for the peripherals when using SMPS can be found using STM32CubeMX
PCC tool.
6.3.6
Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 50 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
(1)
Table 50. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ Max Unit
Wakeup time from Sleep
mode to Run mode
tWUSLEEP
-
6
6
6
Nb of
CPU
cycles
Wakeup time from Low-
tWULPSLEEP power sleep mode to Low- during low-power sleep mode (SLEEP_PD=1 in
power run mode FLASH_ACR) and with clock MSI = 2 MHz
Wakeup in Flash with Flash in power-down
8.3
DS12469 Rev 8
111/192
164
Electrical characteristics
STM32L412xx
(1)
Table 50. Low-power mode wakeup timings (continued)
Symbol
Parameter
Conditions
Typ Max Unit
Wakeup clock MSI = 48 MHz
3.8
5.7
6.9
6.2
6.8
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
Range 1
Range 2
Wakeup clock HSI16 = 16 MHz 4.1
Wakeup clock MSI = 24 MHz 4.07
Wakeup clock HSI16 = 16 MHz 4.1
Wake up time from Stop 0
mode to Run mode in
Flash
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 48 MHz
8.45 11.8
tWUSTOP0
µs
1.5
2.9
Wakeup clock HSI16 = 16 MHz 2.4
Wakeup clock MSI = 24 MHz 2.4
Wakeup clock HSI16 = 16 MHz 2.4
2.76
3.48
2.76
Wake up time from Stop 0
mode to Run mode in
SRAM1
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 48 MHz
8.16 10.94
6.34 7.86
Wakeup clock HSI16 = 16 MHz 6.84 8.23
Wakeup clock MSI = 24 MHz 6.74 8.1
Wakeup clock HSI16 = 16 MHz 6.89 8.21
Wake up time from Stop 1
mode to Run in Flash
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 48 MHz
10.47 12.1
4.7
5.97
6.92
6.51
6.92
Wakeup clock HSI16 = 16 MHz 5.9
Wakeup clock MSI = 24 MHz 5.4
Wakeup clock HSI16 = 16 MHz 5.9
Wake up time from Stop 1
mode to Run mode in
SRAM1
tWUSTOP1
µs
Wakeup clock MSI = 4 MHz
11.1 12.2
Wake up time from Stop 1
mode to Low-power run
mode in Flash
16.4 17.73
Regulator in
low-power
mode (LPR=1
in PWR_CR1)
Wakeup clock MSI = 2 MHz
Wake up time from Stop 1
mode to Low-power run
mode in SRAM1
17.3 18.82
112/192
DS12469 Rev 8
STM32L412xx
Symbol
Electrical characteristics
(1)
Table 50. Low-power mode wakeup timings (continued)
Parameter
Conditions
Typ Max Unit
Wakeup clock MSI = 48 MHz
8.02 9.24
Range 1
Range 2
Range 1
Range 2
Wakeup clock HSI16 = 16 MHz 7.66 8.95
Wakeup clock MSI = 24 MHz 8.5 9.54
Wakeup clock HSI16 = 16 MHz 7.75 8.95
Wake up time from Stop 2
mode to Run mode in
Flash
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 48 MHz
12.06 13.16
5.45 6.79
tWUSTOP2
µs
Wakeup clock HSI16 = 16 MHz 6.9
Wakeup clock MSI = 24 MHz 6.3
Wakeup clock HSI16 = 16 MHz 6.9
7.98
7.36
7.9
Wake up time from Stop 2
mode to Run mode in
SRAM1
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 8 MHz
Wakeup clock MSI = 4 MHz
Wakeup clock MSI = 8 MHz
Wakeup clock MSI = 4 MHz
13.1 13.31
12.2 18.35
19.14 25.8
12.1 18.3
19.2 25.87
Wakeup time from Standby
mode to Run mode
tWUSTBY
Range 1
Range 1
µs
µs
tWUSTBY
Wakeup time from Standby
with SRAM2 to Run mode
SRAM2
Wakeup time from
tWUSHDN Shutdown mode to Run
mode
Range 1
Wakeup clock MSI = 4 MHz
261.5 315.7
µs
1. Guaranteed by characterization results.
(1)
Table 51. Regulator modes transition times
Symbol
Parameter
Conditions
Typ
Max
Unit
Wakeup time from Low-power run mode to
Run mode(2)
tWULPRUN
Code run with MSI 2 MHz
5
7
µs
Regulator transition time from Range 2 to
Range 1 or Range 1 to Range 2(3)
tVOST
Code run with MSI 24 MHz
20
40
1. Guaranteed by characterization results.
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
(1)
Table 52. Wakeup time using USART/LPUART
Symbol
Parameter
Conditions
Stop 0 mode
Typ
Max
Unit
Wakeup time needed to calculate the
maximum USART/LPUART baudrate
allowing to wakeup up from stop mode
when USART/LPUART clock source is
HSI
-
1.7
tWUUSART
µs
Stop 1 mode and Stop 2
mode
tWULPUART
-
8.5
1. Guaranteed by design.
DS12469 Rev 8
113/192
164
Electrical characteristics
STM32L412xx
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 21: High-speed external clock
source AC timing diagram.
(1)
Table 53. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Voltage scaling
Range 1
-
8
48
fHSE_ext User external clock source frequency
MHz
Voltage scaling
Range 2
-
8
26
VHSEH OSC_IN input pin high level voltage
VHSEL OSC_IN input pin low level voltage
-
-
0.7 VDDIOx
VSS
-
-
VDDIOx
V
0.3 VDDIOx
Voltage scaling
Range 1
7
-
-
-
-
tw(HSEH)
OSC_IN high or low time
tw(HSEL)
ns
Voltage scaling
Range 2
18
1. Guaranteed by design.
Figure 21. High-speed external clock source AC timing diagram
t
w(HSEH)
V
HSEH
90%
10%
V
HSEL
t
t
t
t
r(HSE)
f(HSE)
w(HSEL)
T
HSE
MS19214V2
114/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 22.
(1)
Table 54. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
-
-
-
32.768
1000
VDDIOx
kHz
0.7 VDDIOx
VSS
-
-
V
0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
-
250
-
-
ns
1. Guaranteed by design.
Figure 22. Low-speed external clock source AC timing diagram
t
w(LSEH)
V
LSEH
90%
10%
V
LSEL
t
t
t
r(LSE)
f(LSE)
t
w(LSEL)
T
LSE
MS19215V2
DS12469 Rev 8
115/192
164
Electrical characteristics
STM32L412xx
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 55. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
(1)
Table 55. HSE oscillator characteristics
Symbol
fOSC_IN Oscillator frequency
RF Feedback resistor
Parameter
Conditions(2)
Min
Typ
Max
Unit
-
4
-
8
200
-
48
-
MHz
-
kΩ
During startup(3)
-
5.5
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
-
-
-
-
0.44
0.45
0.68
0.94
1.77
-
-
-
-
-
VDD = 3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
VDD = 3 V,
IDD(HSE) HSE current consumption
mA
Rm = 30 Ω,
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω,
CL = 20 pF@48 MHz
Maximum critical crystal
transconductance
Gm
Startup
-
-
-
1.5
-
mA/V
ms
(4)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 23). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
116/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 23. Typical application with an 8 MHz crystal
Resonator with integrated
capacitors
CL1
OSC_IN
fHSE
Bias
controlled
gain
8 MHz
resonator
RF
(1)
OSC_OUT
REXT
CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 56. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
(1)
Table 56. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(2)
Min
Typ
Max Unit
LSEDRV[1:0] = 00
Low drive capability
-
250
-
LSEDRV[1:0] = 01
Medium low drive capability
-
-
-
-
-
-
315
-
IDD(LSE) LSE current consumption
nA
LSEDRV[1:0] = 10
Medium high drive capability
500
-
LSEDRV[1:0] = 11
High drive capability
630
-
LSEDRV[1:0] = 00
Low drive capability
-
-
-
0.5
LSEDRV[1:0] = 01
Medium low drive capability
0.75
µA/V
1.7
Maximum critical crystal
Gmcritmax
gm
LSEDRV[1:0] = 10
Medium high drive capability
LSEDRV[1:0] = 11
High drive capability
-
-
-
2.7
(3)
tSU(LSE)
Startup time
VDD is stabilized
DS12469 Rev 8
2
-
s
117/192
164
Electrical characteristics
STM32L412xx
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 24. Typical application with a 32.768 kHz crystal
Resonator with integrated
capacitors
CL1
OSC32_IN
fLSE
Drive
32.768 kHz
resonator
programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
118/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
6.3.8
Internal clock source characteristics
The parameters given in Table 57 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
(1)
Table 57. HSI16 oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fHSI16
HSI16 Frequency
VDD=3.0 V, TA=30 °C
15.88
-
16.08
MHz
Trimming code is not a
multiple of 64
0.2
-4
0.3
-6
0.4
-8
TRIM
HSI16 user trimming step
%
Trimming code is a
multiple of 64
DuCy(HSI16)(2) Duty Cycle
-
45
-1
-2
-
-
-
55
1
%
%
TA= 0 to 85 °C
TA= -40 to 125 °C
HSI16 oscillator frequency
drift over temperature
ꢀTemp(HSI16)
1.5
%
%
HSI16 oscillator frequency
drift over VDD
ꢀVDD(HSI16)
tsu(HSI16)(2)
tstab(HSI16)(2)
IDD(HSI16)(2)
VDD=1.62 V to 3.6 V
-0.1
-
0.05
1.2
5
HSI16 oscillator start-up
time
-
-
-
-
-
-
0.8
3
μs
μs
μA
HSI16 oscillator
stabilization time
HSI16 oscillator power
consumption
155
190
1. Guaranteed by characterization results.
2. Guaranteed by design.
DS12469 Rev 8
119/192
164
Electrical characteristics
STM32L412xx
Figure 25. HSI16 frequency versus temperature
MHz
16.4
+2%
+1.5%
+1%
16.3
16.2
16.1
16
15.9
15.8
15.7
-1%
-1.5%
-2%
15.6
-40
-20
0
20
40
mean
60
80
100
120 °C
min
max
MSv39299V1
120/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
Multi-speed internal (MSI) RC oscillator
Table 58. MSI oscillator characteristics(1)
Conditions
Symbol
Parameter
Min
Typ
Max Unit
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
TA= -0 to 85 °C
98.7
100
200
101.3
197.4
202.6
kHz
405.2
394.8
400
789.6
800
810.4
1.013
2.026
4.052
0.987
1
1.974
2
MSI mode
3.948
4
7.896
8
8.104
MHz
16.21
15.79
16
23.69
24
24.31
32.42
48.62
-
31.58
32
MSI frequency
after factory
calibration, done
at VDD=3 V and
TA=30 °C
47.38
48
fMSI
-
98.304
196.608
393.216
786.432
1.016
1.999
3.998
7.995
15.991
23.986
32.014
48.005
-
-
-
kHz
-
-
-
-
-
-
-
-
PLL mode
XTAL=
32.768 kHz
-
-
-
-
MHz
-
-
-
-
-
-
-
-
MSI oscillator
-3.5
3
ꢀTEMP(MSI)(2) frequency drift
MSI mode
%
6
TA= -40 to 125 °C
-8
-
over temperature
DS12469 Rev 8
121/192
164
Electrical characteristics
STM32L412xx
Table 58. MSI oscillator characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VDD=1.62 V
to 3.6 V
-1.2
-0.5
-2.5
-0.8
-5
-
Range 0 to 3
0.5
VDD=2.4 V
to 3.6 V
-
-
-
-
-
VDD=1.62 V
to 3.6 V
MSI oscillator
frequency drift
over VDD
ꢀVDD(MSI)(2)
MSI mode Range 4 to 7
0.7
1
%
VDD=2.4 V
(reference is 3 V)
to 3.6 V
VDD=1.62 V
to 3.6 V
Range 8 to 11
VDD=2.4 V
to 3.6 V
-1.6
Frequency
TA= -40 to 85 °C
TA= -40 to 125 °C
-
-
1
2
2
4
ꢀFSAMPLING
variation in
MSI mode
%
(MSI)(2)(6)
sampling mode(3)
for next
transition
-
-
-
-
-
-
-
-
-
-
-
-
3.458
P_USB
Period jitter for
USB clock(4)
PLL mode
Range 11
ns
Jitter(MSI)(6)
for paired
transition
3.916
for next
transition
-
2
1
-
MT_USB
Medium term jitter PLL mode
ns
Jitter(MSI)(6)
for USB clock(5)
Range 11
for paired
transition
-
RMS cycle-to-
cycle jitter
CC jitter(MSI)(6)
PLL mode Range 11
60
ps
ps
P jitter(MSI)(6) RMS Period jitter PLL mode Range 11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
10
5
-
20
10
8
Range 0
Range 1
Range 2
4
MSI oscillator
start-up time
t
SU(MSI)(6)
us
Range 3
3
7
Range 4 to 7
Range 8 to 11
3
6
2.5
6
10 % of final
frequency
-
-
-
-
-
-
0.25
0.5
-
0.5
MSI oscillator
stabilization time Range 11
PLL mode 5 % of final
tSTAB(MSI)(6)
1.25 ms
2.5
frequency
1 % of final
frequency
122/192
DS12469 Rev 8
STM32L412xx
Symbol
Electrical characteristics
Table 58. MSI oscillator characteristics(1) (continued)
Parameter
Conditions
Min
Typ
Max Unit
Range 0
Range 1
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
Range 9
Range 10
Range 11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.6
0.8
1.2
1.9
4.7
6.5
11
1
1.2
1.7
2.5
6
MSI oscillator
power
consumption
9
MSI and
PLL mode
IDD(MSI)(6)
µA
15
18.5
62
25
80
85
110
130
190
110
155
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter
of MSI @48 MHz clock.
5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28
cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over
56 cycles.
6. Guaranteed by design.
DS12469 Rev 8
123/192
164
Electrical characteristics
STM32L412xx
Figure 26. Typical current consumption versus MSI frequency
High-speed internal 48 MHz (HSI48) RC oscillator
Table 59. HSI48 oscillator characteristics
(1)
Symbol
Parameter
HSI48 Frequency
Conditions
Min
Typ
Max
Unit
fHSI48
TRIM
VDD=3.0V, TA=30°C
-
-
-
48
-
MHz
%
HSI48 user trimming step
0.11(2)
0.18(2)
USER TRIM
COVERAGE
HSI48 user trimming coverage
±32 steps
-
±3(3)
45(2)
-
±3.5(3)
-
%
%
DuCy(HSI48) Duty Cycle
-
-
55(2)
±3(3)
VDD = 3.0 V to 3.6 V,
TA = –15 to 85 °C
Accuracy of the HSI48 oscillator
ACCHSI48_REL over temperature (factory
calibrated)
%
VDD = 1.65 V to 3.6 V,
TA = –40 to 125 °C
-
-
±4.5(3)
VDD = 3 V to 3.6 V
-
-
-
0.025(3)
0.05(3)
2.5(2)
0.05(3)
0.1(3)
6(2)
HSI48 oscillator frequency drift
DVDD(HSI48)
with VDD
%
VDD = 1.65 V to 3.6 V
-
tsu(HSI48)
IDD(HSI48)
HSI48 oscillator start-up time
μs
HSI48 oscillator power
consumption
-
-
340(2)
380(2)
μA
124/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
(1)
Table 59. HSI48 oscillator characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Next transition jitter
NT jitter
-
-
+/-0.15(2)
-
ns
Accumulated jitter on 28 cycles(4)
Paired transition jitter
PT jitter
-
-
+/-0.25(2)
-
ns
Accumulated jitter on 56 cycles(4)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.
Figure 27. HSI48 frequency versus temperature
%
6
4
2
0
-2
-4
-6
-50
-30
-10
10
30
50
70
90
110
130
°C
Avg
min
max
MSv40989V1
Low-speed internal (LSI) RC oscillator
(1)
Table 60. LSI oscillator characteristics
Conditions
Symbol
Parameter
Min
Typ
Max Unit
VDD = 3.0 V, TA = 30 °C
31.04
29.5
-
-
32.96
kHz
34
fLSI
LSI Frequency
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C
LSI oscillator start-
up time
tSU(LSI)(2)
-
-
-
-
80
130
180
180
μs
μs
nA
LSI oscillator
stabilization time
tSTAB(LSI)(2)
5% of final frequency
-
125
110
LSI oscillator power
consumption
I
DD(LSI)(2)
1. Guaranteed by characterization results.
2. Guaranteed by design.
DS12469 Rev 8
125/192
164
Electrical characteristics
STM32L412xx
6.3.9
PLL characteristics
The parameters given in Table 61 are derived from tests performed under temperature and
V
supply voltage conditions summarized in Table 21: General operating conditions.
DD
(1)
Table 61. PLL characteristics
Symbol
fPLL_IN
Parameter
Conditions
Min
Typ Max Unit
PLL input clock(2)
-
-
4
-
-
16
55
80
26
80
26
80
26
344
128
40
-
MHz
%
PLL input clock duty cycle
45
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
Voltage scaling Range 1
Voltage scaling Range 2
-
3.0968
-
fPLL_P_OUT PLL multiplier output clock P
fPLL_Q_OUT PLL multiplier output clock Q
fPLL_R_OUT PLL multiplier output clock R
fVCO_OUT PLL VCO output
MHz
MHz
MHz
3.0968
-
12
12
12
12
96
96
-
-
-
-
-
-
MHz
μs
-
tLOCK
Jitter
PLL lock time
15
40
30
RMS cycle-to-cycle jitter
RMS period jitter
-
System clock 80 MHz
±ps
-
-
VCO freq = 96 MHz
VCO freq = 192 MHz
VCO freq = 344 MHz
-
200 260
300 380
520 650
PLL power consumption on
VDD
I
DD(PLL)
-
μA
(1)
-
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the 2 PLLs.
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Electrical characteristics
6.3.10
Flash memory characteristics
(1)
Table 62. Flash memory characteristics
Symbol
Parameter
Conditions
Typ
Max Unit
tprog
64-bit programming time
-
81.69
2.61
90.76
2.90
2.12
µs
normal programming
fast programming
normal programming
fast programming
-
one row (32 double
word) programming time
tprog_row
1.91
20.91
15.29
22.02
5.35
23.24 ms
16.98
one page (2 Kbyte)
programming time
tprog_page
tERASE
Page (2 KB) erase time
24.47
normal programming
fast programming
5.95
s
4.35
one bank (512 Kbyte)
programming time
tprog_bank
3.91
Mass erase time
(one or two banks)
tME
-
22.13
24.59 ms
-
Write mode
Erase mode
Write mode
Erase mode
3.4
Average consumption
from VDD
3.4
-
IDD
mA
-
7 (for 2 μs)
7 (for 41 μs)
Maximum current (peak)
-
1. Guaranteed by design.
Table 63. Flash memory endurance and data retention
Symbol
Parameter
Endurance
Conditions
Min(1)
Unit
NEND
TA = –40 to +105 °C
10
30
15
7
kcycles
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
1 kcycle(2) at TA = 125 °C
10 kcycles(2) at TA = 55 °C
10 kcycles(2) at TA = 85 °C
10 kcycles(2) at TA = 105 °C
tRET
Data retention
Years
30
15
10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
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6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 64. They are based on the EMS levels and classes
defined in application note AN1709.
Table 64. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, TA = +25 °C,
fHCLK = 80 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
2B
5A
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 80 MHz,
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 65. EMI characteristics
Max vs.
[fHSE/fHCLK
]
Monitored
frequency band
Symbol Parameter
Conditions
Unit
8 MHz/ 80 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
3
3
VDD = 3.6 V, TA = 25 °C,
LQFP64 package
compliant with IEC
61967-2
dBµV
-
SEMI
Peak level
4
8
2.5
6.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 66. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Package Class
Unit
value(1)
TA = +25 °C, conforming
to ANSI/ESDA/JEDEC
JS-001
Electrostatic discharge voltage
(human body model)
VESD(HBM)
All
2
2000
V
TA = +25 °C,
conforming to
ANSI/ESDA/JEDEC-002
BGA64
C2a
C1
500
250
Electrostatic discharge voltage
(charge device model)
VESD
All others
1. Guaranteed by characterization results.
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Electrical characteristics
Static latch-up
STM32L412xx
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 67. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II
6.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V
(for standard, 3.3 V-capable I/O pins) should be avoided during normal
DDIOx
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 68.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
(1)
Table 68. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
Injected current on all pins except PA4, PA5
Injected current on PA4, PA5 pins
-5
-5
N/A(2)
0
IINJ
mA
1. Guaranteed by characterization results.
2. Injection is not possible.
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6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 69 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 69. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I/O input low level
voltage
(2)
1.62 V<VDDIOx<3.6 V
-
-
0.3xVDDIOx
I/O input low level
voltage
(1)
VIL
1.62 V<VDDIOx<3.6 V
1.08 V<VDDIOx<1.62 V
1.62 V<VDDIOx<3.6 V
1.62 V<VDDIOx<3.6 V
-
-
-
-
-
-
0.39xVDDIOx-0.06 (3)
V
I/O input low level
voltage
-
0.43xVDDIOx-0.1 (3)
I/O input high level
voltage
(2)
0.7xVDDIOx
-
-
-
I/O input high level
voltage
(1)
VIH
0.49xVDDIOX+0.26 (3)
V
I/O input high level
voltage
1.08 V<VDDIOx<1.62 V 0.61xVDDIOX+0.05 (3)
TT_xx, FT_xxx and
NRST I/O input
hysteresis
(3)
Vhys
1.62 V<VDDIOx<3.6 V
-
200
-
mV
VIN
Max(VDDXXX
≤
-
-
-
-
-
-
-
-
-
-
±100
650
(6)(7)
)
FT_xx input leakage Max(VDDXXX) ≤ VIN
≤
current(3)(5)
Max(VDDXXX)+1 V(6)(7)
Max(VDDXXX)+1 V <
200
VIN ≤ 5.5 V(6)(7)
VIN
Max(VDDXXX
≤
±150
2500(3)
(6)(7)
(4)
)
Ilkg
nA
Max(VDDXXX) ≤ VIN
≤
FT_u and PC3 I/O
Max(VDDXXX)+1 V(6)(7)
Max(VDDXXX)+1 V <
-
-
-
-
-
-
250
±150
VIN ≤ 5.5 V(6)(7)
(6)
VIN ≤ Max(VDDXXX)
TT_xx input leakage
current
Max(VDDXXX) ≤ VIN
<
2000(3)
3.6 V(6)
Weak pull-up
RPU
VIN = VSS
25
40
55
kΩ
equivalent resistor (8)
Weak pull-down
RPD
CIO
VIN = VDDIOx
25
-
40
5
55
-
kΩ
equivalent resistor(8)
I/O pin capacitance
-
pF
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Electrical characteristics
STM32L412xx
1. Refer to Figure 28: I/O input characteristics.
2. Tested in production.
3. Guaranteed by design.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max).
5. All FT_xx GPIOs except FT_u and PC3 I/O.
6. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.
7. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 28 for standard I/Os, and in Figure 28 for
5 V tolerant I/Os.
Figure 28. I/O input characteristics
TTL requirement Vih min = 2V
TTL requirement Vil max = 0.8V
MSv37613V1
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed V /V ).
OL OH
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Electrical characteristics
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum
DDIOx,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 18: Voltage characteristics).
VDD
•
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating ΣI
(see
SS
VSS
Table 18: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
(1)
Table 70. Output voltage characteristics
Symbol
VOL
Parameter
Conditions
Min
Max
0.4
-
Unit
Output low level voltage for an I/O pin CMOS port(2)
|IIO| = 8 mA
Output high level voltage for an I/O pin
-
VOH
VDDIOx-0.4
VDDIOx ≥ 2.7 V
(3)
VOL
Output low level voltage for an I/O pin TTL port(2)
|IIO| = 8 mA
-
0.4
-
(3)
VOH
Output high level voltage for an I/O pin
2.4
VDDIOx ≥ 2.7 V
(3)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
(3)
VOH
VDDIOx-1.3
-
(3)
VOL
-
0.45
|IIO| = 4 mA
VDDIOx ≥ 1.62 V
V
(3)
VOH
VDDIOx-0.45
-
-
(3)
VOL
0.35ₓVDDIOx
|IIO| = 2 mA
1.62 V ≥ VDDIOx ≥ 1.08 V
(3)
VOH
0.65ₓVDDIOx
-
|IIO| = 20 mA
-
-
-
0.4
0.4
0.4
VDDIOx ≥ 2.7 V
Output low level voltage for an FT I/O
pin in FM+ mode (FT I/O with "f"
option)
VOLFM+
|IIO| = 10 mA
VDDIOx ≥ 1.62 V
(3)
|IIO| = 2 mA
1.62 V ≥ VDDIOx ≥ 1.08 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 29 and
Table 71, respectively.
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Electrical characteristics
STM32L412xx
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
(1)(2)
Table 71. I/O AC characteristics
Speed Symbol
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
1
0.1
10
1.5
0.1
25
52
140
17
37
110
25
10
1
Fmax Maximum frequency
Tr/Tf Output rise and fall time
Fmax Maximum frequency
Tr/Tf Output rise and fall time
MHz
00
ns
MHz
ns
50
15
1
01
9
16
40
4.5
9
21
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Speed Symbol
Electrical characteristics
(1)(2)
Table 71. I/O AC characteristics
(continued)
Parameter
Conditions
Min
Max
Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=50 pF, 2.7 V≤VDDIOx≤3.6 V
C=50 pF, 1.62 V≤VDDIOx≤2.7 V
C=50 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=30 pF, 2.7 V≤VDDIOx≤3.6 V
C=30 pF, 1.62 V≤VDDIOx≤2.7 V
C=30 pF, 1.08 V≤VDDIOx≤1.62 V
C=10 pF, 2.7 V≤VDDIOx≤3.6 V
C=10 pF, 1.62 V≤VDDIOx≤2.7 V
C=10 pF, 1.08 V≤VDDIOx≤1.62 V
C=30 pF, 2.7 V≤VDDIOx≤3.6 V
C=30 pF, 1.62 V≤VDDIOx≤2.7 V
C=30 pF, 1.08 V≤VDDIOx≤1.62 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
25
5
Fmax Maximum frequency
Tr/Tf Output rise and fall time
Fmax Maximum frequency
MHz
100(3)
37.5
5
10
5.8
11
28
ns
2.5
5
12
120(3)
50
10
MHz
180(3)
11
75
10
3.3
6
Tr/Tf Output rise and fall time
Fmax Maximum frequency
ns
16
1
MHz
ns
Fm+
C=50 pF, 1.6 V≤VDDIOx≤3.6 V
Tf
Output fall time(4)
5
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0394 reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
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Electrical characteristics
STM32L412xx
(1)
Figure 29. I/O AC characteristics definition
10%
90%
50%
50%
10%
90%
t
t
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 71: I/O AC characteristics.
6.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
(1)
Table 72. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST input low level
voltage
VIL(NRST)
VIH(NRST)
Vhys(NRST)
RPU
-
-
-
0.3ₓVDDIOx
V
NRST input high level
voltage
-
0.7ₓVDDIOx
-
200
40
-
-
-
NRST Schmitt trigger
voltage hysteresis
-
-
25
-
mV
kΩ
ns
Weak pull-up
VIN = VSS
55
70
-
equivalent resistor(2)
NRST input filtered
pulse
VF(NRST)
VNF(NRST)
-
NRST input not filtered
pulse
1.71 V ≤ VDD ≤ 3.6 V
350
-
ns
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
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Electrical characteristics
Figure 30. Recommended NRST pin protection
External
reset circuit(1)
VDD
RPU
NRST(2)
Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 72: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.16
Extended interrupt and event controller input (EXTI) characteristics
The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
(1)
Table 73. EXTI Input Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pulse length to event
controller
PLEC
-
20
-
-
ns
1. Guaranteed by design.
6.3.17
Analog switches booster
(1)
Table 74. Analog switches booster characteristics
Symbol
Parameter
Supply voltage
Min
Typ
Max
Unit
VDD
1.62
-
-
-
3.6
V
tSU(BOOST)
Booster startup time
240
µs
Booster consumption for
-
-
-
-
-
-
250
500
900
1.62 V ≤ VDD ≤ 2.0 V
Booster consumption for
IDD(BOOST)
µA
2.0 V ≤ VDD ≤ 2.7 V
Booster consumption for
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.
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Electrical characteristics
STM32L412xx
6.3.18
Analog-to-Digital converter characteristics
Unless otherwise specified, the parameters given in Table 75 are preliminary values derived
from tests performed under ambient temperature, f
frequency and V
supply voltage
PCLK
DDA
conditions summarized in Table 21: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
(1) (2)
Table 75. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
3.6
Unit
VDDA
Analog supply voltage
-
1.62
2
-
-
V
V
V
V
DDA ≥ 2 V
VDDA
VREF+
Positive reference voltage
VDDA < 2 V
VDDA
Negative reference
voltage
VREF-
-
VSSA
V
Range 1
Range 2
0.14
-
-
-
-
-
-
-
-
-
-
80
fADC
ADC clock frequency
MHz
0.14
26
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 6 bits
Resolution = 12 bits
Resolution = 10 bits
Resolution = 8 bits
Resolution = 6 bits
-
-
-
-
-
-
-
-
5.33
6.15
7.27
8.88
4.21
4.71
5.33
6.15
Sampling rate for FAST
channels
fs
Msps
Sampling rate for SLOW
channels
fADC = 80 MHz
Resolution = 12 bits
-
-
-
5.33
MHz
fTRIG
External trigger frequency
Input common mode
Resolution = 12 bits
Differential mode
-
15
1/fADC
(VREF+
REF-)/2
- 0.18
+
(VREF++
REF-)/2
(VREF+
VREF-)/2
+
V
V
V
V
CMIN
+ 0.18
VREF+
50
Conversion voltage
range(2)
(3)
VAIN
-
-
-
0
-
-
-
V
RAIN
External input impedance
kΩ
pF
Internal sample and hold
capacitor
CADC
-
5
-
conversion
cycle
tSTAB
Power-up time
Calibration time
-
1
f
ADC = 80 MHz
-
1.45
116
µs
tCAL
1/fADC
138/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
(1) (2)
Table 75. ADC characteristics
Parameter Conditions
CKMODE = 00
(continued)
Min
Symbol
Typ
Max
Unit
1.5
2
-
2.5
2.0
Trigger conversion
latency Regular and
injected channels without
conversion abort
CKMODE = 01
CKMODE = 10
CKMODE = 11
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
-
tLATR
1/fADC
-
-
2.25
-
-
2.125
3.5
2.5
3
-
Trigger conversion
latency Injected channels
aborting a regular
conversion
-
3.0
tLATRINJ
1/fADC
-
-
-
3.25
-
3.125
8.00625
640.5
f
ADC = 80 MHz
-
0.03125
2.5
-
µs
ts
Sampling time
-
1/fADC
ADC voltage regulator
start-up time
-
-
-
-
20
tADCVREG_STUP
µs
f
ADC = 80 MHz
Resolution = 12 bits
0.1875
8.1625
µs
Total conversion time
(including sampling time)
tCONV
ts + 12.5 cycles for
successive approximation
= 15 to 653
Resolution = 12 bits
1/fADC
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
-
-
-
-
-
-
-
-
-
730
160
16
830
220
50
ADC consumption from
the VDDA supply
IDDA(ADC)
µA
130
30
160
40
ADC consumption from
IDDV_S(ADC) the VREF+ single ended
mode
µA
µA
0.6
260
60
2
310
70
ADC consumption from
IDDV_D(ADC) the VREF+ differential
mode
1.3
3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
DDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
V
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
The maximum value of R
can be found in Table 76: Maximum ADC RAIN.
AIN
DS12469 Rev 8
139/192
164
Electrical characteristics
Resolution
STM32L412xx
(1)(2)
Table 76. Maximum ADC R
AIN
RAIN max (Ω)
Sampling cycle
Sampling time [ns]
@80 MHz
@80 MHz
Fast channels(3)
Slow channels(4)
2.5
6.5
31.25
81.25
100
330
N/A
100
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
680
470
1500
2200
4700
12000
39000
120
1200
1800
3900
10000
33000
N/A
12 bits
10 bits
8 bits
6.5
81.25
390
180
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
820
560
1500
2200
5600
12000
47000
180
1200
1800
4700
10000
39000
N/A
6.5
81.25
470
270
12.5
24.5
47.5
92.5
247.5
640.5
2.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
31.25
1000
1800
2700
6800
15000
50000
220
680
1500
2200
5600
12000
50000
N/A
6.5
81.25
560
330
12.5
24.5
47.5
92.5
247.5
640.5
156.25
306.25
593.75
1156.25
3093.75
8006.75
1200
2700
3900
8200
18000
50000
1000
2200
3300
6800
15000
50000
6 bits
1. Guaranteed by design.
140/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1.
4. Slow channels are: all ADC inputs except the fast channels.
DS12469 Rev 8
141/192
164
Electrical characteristics
STM32L412xx
(1)(2)(3)
Table 77. ADC accuracy - limited test conditions 1
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
4
5
5
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
3.5 4.5
3.5 4.5
Differential
1
1
2.5
2.5
Single
ended
Offset
error
1.5 2.5
1.5 2.5
2.5 4.5
2.5 4.5
2.5 3.5
2.5 3.5
Differential
Single
ended
Gain error
LSB
Differential
1
1
1
1
1.5
1.5
1.2
1.2
Single
ended
Differential
linearity
error
ADC clock frequency ≤
80 MHz,
Differential
Sampling rate ≤ 5.33 Msps,
VDDA = VREF+ = 3 V,
TA = 25 °C
1.5 2.5
1.5 2.5
Single
ended
Integral
linearity
error
1
1
2
2
-
-
-
-
-
-
-
-
-
-
-
-
Differential
Fast channel (max speed) 10.4 10.5
Slow channel (max speed) 10.4 10.5
Fast channel (max speed) 10.8 10.9
Slow channel (max speed) 10.8 10.9
Fast channel (max speed) 64.4 65
Slow channel (max speed) 64.4 65
Fast channel (max speed) 66.8 67.4
Slow channel (max speed) 66.8 67.4
Single
ended
Effective
ENOB number of
bits
bits
Differential
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Differential
dB
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 67
Slow channel (max speed) 67
66
66
68
68
Single
ended
Signal-to-
SNR
noise ratio
Differential
142/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
(1)(2)(3)
Table 77. ADC accuracy - limited test conditions 1
(continued)
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-74 -73
-74 -73
-79 -76
-79 -76
ADC clock frequency ≤
80 MHz,
Single
ended
Total
THD harmonic
distortion
Sampling rate ≤ 5.33 Msps,
VDDA = VREF+ = 3 V,
TA = 25 °C
dB
Differential
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
DS12469 Rev 8
143/192
164
Electrical characteristics
STM32L412xx
(1)(2)(3)
Table 78. ADC accuracy - limited test conditions 2
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
4
6.5
6.5
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
3.5 5.5
3.5 5.5
Differential
1
4.5
5
Single
ended
1
Offset
error
1.5
1.5
2.5
2.5
3
Differential
3
6
Single
ended
6
Gain error
LSB
2.5 3.5
2.5 3.5
Differential
1
1
1
1
1.5
1.5
1.2
1.2
Single
ended
Differential
linearity
error
ADC clock frequency ≤
80 MHz,
Differential
Sampling rate ≤ 5.33 Msps,
2 V ≤ VDDA
1.5 3.5
1.5 3.5
Single
ended
Integral
linearity
error
1
1
3
Differential
2.5
Fast channel (max speed) 10 10.5
Slow channel (max speed) 10 10.5
Fast channel (max speed) 10.7 10.9
Slow channel (max speed) 10.7 10.9
-
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Effective
ENOB number of
bits
bits
Differential
Fast channel (max speed) 62
Slow channel (max speed) 62
65
65
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Fast channel (max speed) 66 67.4
Slow channel (max speed) 66 67.4
Differential
dB
Fast channel (max speed) 64
Slow channel (max speed) 64
66
66
Single
ended
Signal-to-
SNR
noise ratio
Fast channel (max speed) 66.5 68
Slow channel (max speed) 66.5 68
Differential
144/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
(1)(2)(3)
Table 78. ADC accuracy - limited test conditions 2
(continued)
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-74 -65
-74 -67
-79 -70
-79 -71
Single
ended
ADC clock frequency ≤
80 MHz,
Total
THD harmonic
distortion
dB
Sampling rate ≤ 5.33 Msps,
2 V ≤ VDDA
Differential
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
DS12469 Rev 8
145/192
164
Electrical characteristics
STM32L412xx
(1)(2)(3)
Table 79. ADC accuracy - limited test conditions 3
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5 7.5
4.5 6.5
4.5 7.5
4.5 5.5
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
Differential
2
5
5
Single
ended
2.5
2
Offset
error
3.5
3
Differential
2.5
4.5
3.5
3.5
3.5
7
Single
ended
6
Gain error
LSB
4
Differential
5
1.2 1.5
1.2 1.5
Single
ended
Differential
linearity
error
ADC clock frequency ≤
80 MHz,
1
1
3
1.2
1.2
3.5
Differential
Sampling rate ≤ 5.33 Msps,
1.65 V ≤ VDDA = VREF+
3.6 V,
≤
Single
ended
Integral
linearity
error
2.5 3.5
Voltage scaling Range 1
2
2
2.5
Differential
2.5
Fast channel (max speed) 10 10.4
Slow channel (max speed) 10 10.4
Fast channel (max speed) 10.6 10.7
Slow channel (max speed) 10.6 10.7
-
-
-
-
-
-
-
-
-
-
-
-
Single
ended
Effective
ENOB number of
bits
bits
Differential
Fast channel (max speed) 62
Slow channel (max speed) 62
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 63
Slow channel (max speed) 63
Fast channel (max speed) 66
Slow channel (max speed) 66
64
64
66
66
65
65
67
67
Single
ended
Signal-to-
noise and
distortion
ratio
SINAD
Differential
dB
Single
ended
Signal-to-
SNR
noise ratio
Differential
146/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
(1)(2)(3)
Table 79. ADC accuracy - limited test conditions 3
(continued)
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
ADC clock frequency ≤
80 MHz,
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
-
-
-
-69 -67
-71 -67
-72 -71
Single
ended
Total
THD harmonic
distortion
Sampling rate ≤ 5.33 Msps,
dB
1.65 V ≤ VDDA = VREF+
≤
Differential
3.6 V,
Slow channel (max speed)
-
-72 -71
Voltage scaling Range 1
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
DS12469 Rev 8
147/192
164
Electrical characteristics
STM32L412xx
(1)(2)(3)
Table 80. ADC accuracy - limited test conditions 4
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
4
4
5.4
5
Single
ended
Total
unadjusted
error
ET
EO
EG
ED
EL
5
Differential
3.5 4.5
2
2
4
4
Single
ended
Offset
error
2
3.5
3.5
4.5
4.5
4
Differential
2
4
Single
ended
4
Gain error
LSB
3
Differential
3
4
1
1.5
1.5
1.2
1.2
3
Single
ended
Differential
linearity
error
1
1
ADC clock frequency ≤
26 MHz,
Differential
1
1.65 V ≤ VDDA = VREF+ ≤
3.6 V,
2.5
2.5
2
Single
ended
Integral
linearity
error
Voltage scaling Range 2
3
2.5
2.5
-
Differential
2
Fast channel (max speed) 10.2 10.5
Slow channel (max speed) 10.2 10.5
Fast channel (max speed) 10.6 10.7
Slow channel (max speed) 10.6 10.7
Single
ended
Effective
ENOB number of
bits
-
bits
-
Differential
-
Fast channel (max speed) 63
Slow channel (max speed) 63
Fast channel (max speed) 65
Slow channel (max speed) 65
Fast channel (max speed) 64
Slow channel (max speed) 64
Fast channel (max speed) 66
Slow channel (max speed) 66
65
65
66
66
65
65
67
67
-
Single
ended
Signal-to-
noise and
distortion
ratio
-
SINAD
-
Differential
-
dB
-
Single
ended
-
Signal-to-
SNR
noise ratio
-
Differential
-
148/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
(1)(2)(3)
Table 80. ADC accuracy - limited test conditions 4
(continued)
Sym-
bol
Parameter
Conditions(4)
Min Typ Max Unit
Fast channel (max speed)
Slow channel (max speed)
Fast channel (max speed)
Slow channel (max speed)
-
-
-
-
-71 -69
-71 -69
-73 -72
-73 -72
ADC clock frequency ≤
26 MHz,
Single
ended
Total
THD harmonic 1.65 V ≤ VDDA = VREF+ ≤
dB
distortion
3.6 V,
Differential
Voltage scaling Range 2
1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
V
DDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
Figure 31. ADC accuracy characteristics
VSSA
4095
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4094
4093
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
EO = offset error: maximum deviation
between the first actual transition and
the first ideal one.
EG = gain error: deviation between the last
ideal transition and the last actual one.
ED = differential linearity error: maximum
deviation between actual steps and the ideal ones.
EL = integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
(2)
ET
(3)
7
(1)
6
5
4
3
2
1
EO
EL
ED
1 LSB IDEAL
0
4096
VDDA
4094 4095
7
4093
2
3
4
5
6
1
MS19880V2
DS12469 Rev 8
149/192
164
Electrical characteristics
STM32L412xx
Figure 32. Typical connection diagram using the ADC
VDDA
VT
Sample and hold ADC converter
(1)
RAIN
RADC
AINx
12-bit
converter
(2)
(3)
Cparasitic
CADC
VT
Ilkg
VAIN
MS33900V5
1. Refer to Table 75: ADC characteristics for the values of RAIN and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 69: I/O static characteristics for the value of the pad capacitance). A high
C
parasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 69: I/O static characteristics for the values of Ilkg.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 18: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
150/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
6.3.19
Comparator characteristics
(1)
Table 81. COMP characteristics
Conditions
Symbol
VDDA
Parameter
Min
Typ
Max
Unit
Analog supply voltage
-
-
1.62
-
3.6
Comparator input voltage
range
VIN
0
-
VDDA
V
(2)
VBG
Scaler input voltage
Scaler offset voltage
-
VREFINT
VSC
-
BRG_EN=0 (bridge disable)
BRG_EN=1 (bridge enable)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±5
200
0.8
100
-
±10
300
1
mV
nA
µA
µs
Scaler static consumption
from VDDA
I
DDA(SCALER)
tSTART_SCALER Scaler startup time
200
5
VDDA ≥ 2.7 V
High-speed
mode
V
V
V
DDA < 2.7 V
DDA ≥ 2.7 V
DDA < 2.7 V
-
7
Comparator startup time to
reach propagation delay
specification
tSTART
-
15
25
40
80
100
0.9
7
µs
Medium mode
-
Ultra-low-power mode
-
VDDA ≥ 2.7 V
VDDA < 2.7 V
55
65
0.55
4
High-speed
mode
ns
Propagation delay with
100 mV overdrive
(3)
tD
Medium mode
µs
Ultra-low-power mode
Full common
mode range
Voffset
Comparator offset error
Comparator hysteresis
-
-
±5
±20
mV
No hysteresis
-
-
-
-
0
8
-
-
-
-
Low hysteresis
Medium hysteresis
High hysteresis
Vhys
mV
15
27
DS12469 Rev 8
151/192
164
Electrical characteristics
STM32L412xx
(1)
Table 81. COMP characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static
-
400
600
Ultra-low-
power mode
With 50 kHz
±100 mV overdrive
square signal
nA
-
-
-
-
-
1200
5
-
Static
7
Comparator consumption
With 50 kHz
±100 mV overdrive
square signal
IDDA(COMP)
Medium mode
from VDDA
6
-
100
-
µA
nA
Static
70
75
High-speed
mode
With 50 kHz
±100 mV overdrive
square signal
Comparator input bias
current
(4)
-
-
-
-
I
bias
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 24: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 69: I/O static characteristics.
6.3.20
Operational amplifiers characteristics
(1)
Table 82. OPAMP characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply
voltage(2)
VDDA
CMIR
-
1.8
-
3.6
V
Common mode
input range
-
0
-
VDDA
V
25 °C, No Load on output.
All voltage/Temp.
Normal mode
-
-
-
-
-
-
±1.5
Input offset
voltage
VIOFFSET
mV
±3
-
±5
±10
Input offset
voltage drift
ꢀVIOFFSET
μV/°C
Low-power mode
-
Offset trim step
TRIMOFFSETP at low common
TRIMLPOFFSETP input voltage
-
-
-
-
0.8
1
1.1
(0.1 ₓ VDDA
)
mV
Offset trim step
TRIMOFFSETN at high common
TRIMLPOFFSETN input voltage
1.35
(0.9 ₓ VDDA
)
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Electrical characteristics
(1)
Table 82. OPAMP characteristics (continued)
Parameter Conditions Min
Symbol
Typ
Max
Unit
Normal mode
-
-
-
-
-
-
-
-
500
100
450
50
ILOAD
Drive current
VDDA ≥ 2 V
VDDA ≥ 2 V
Low-power mode
Normal mode
µA
Drive current in
PGA mode
ILOAD_PGA
Low-power mode
Resistive load
(connected to
VSSA or to
VDDA)
Normal mode
4
-
-
-
-
-
-
-
-
RLOAD
V
DDA < 2 V
Low-power mode
Normal mode
20
4.5
40
kΩ
Resistive load
in PGA mode
(connected to
VSSA or to
RLOAD_PGA
VDDA < 2 V
Low-power mode
V
)
DDA
CLOAD
CMRR
Capacitive load
-
-
-
-
-
50
-
pF
dB
Normal mode
-85
-90
Common mode
rejection ratio
Low-power mode
-
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ DC
Normal mode
70
72
85
90
-
-
Power supply
rejection ratio
PSRR
GBW
dB
CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ DC
Low-power mode
Normal mode
550
100
250
40
-
1600 2200
VDDA ≥ 2.4 V
(OPA_RANGE = 1)
Low-power mode
Normal mode
420
700
180
700
180
300
80
600
Gain Bandwidth
Product
kHz
950
VDDA < 2.4 V
(OPA_RANGE = 0)
Low-power mode
Normal mode
280
-
-
-
-
-
-
VDDA ≥ 2.4 V
Slew rate
Low-power mode
Normal mode
-
(from 10 and
90% of output
voltage)
SR(3)
V/ms
dB
-
VDDA < 2.4 V
Low-power mode
Normal mode
-
55
45
110
110
AO
Open loop gain
Low-power mode
VDDA
100
-
-
Normal mode
-
-
-
-
High saturation
voltage
Iload = max or Rload
=
=
(3)
VOHSAT
min Input at VDDA
.
VDDA
50
Low-power mode
mV
Normal mode
-
-
-
-
-
100
Low saturation
voltage
Iload = max or Rload
min Input at 0.
(3)
VOLSAT
Low-power mode
Normal mode
-
50
-
74
66
φm
Phase margin
°
Low-power mode
-
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Electrical characteristics
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(1)
Table 82. OPAMP characteristics (continued)
Parameter Conditions Min
Symbol
Typ
Max
Unit
Normal mode
-
-
13
20
-
-
GM
Gain margin
dB
Low-power mode
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
follower
Normal mode
-
5
10
30
configuration
Wake up time
from OFF state.
tWAKEUP
µs
CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ
follower
Low-power mode
-
-
10
-
configuration
OPAMP input
bias current
(4)
Ibias
General purpose input
-
nA
-
-
-
-
-
-
2
4
-
-
-
-
-
Non inverting
gain value
PGA gain(3)
-
8
16
PGA Gain = 2
PGA Gain = 4
80/80
120/
40
-
-
-
-
-
-
R2/R1 internal
resistance
Rnetwork
kΩ/kΩ
140/
20
values in PGA
PGA Gain = 8
PGA Gain = 16
mode(5)
150/
10
Resistance
variation (R1 or
R2)
Delta R
-
-15
-
-
15
%
%
PGA gain error
PGA gain error
-
-1
-
1
-
GBW/
2
Gain = 2
-
-
-
-
GBW/
4
Gain = 4
Gain = 8
Gain = 16
-
-
-
-
-
-
PGA bandwidth
for different non
inverting gain
PGA BW
MHz
GBW/
8
GBW/
16
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DS12469 Rev 8
STM32L412xx
Symbol
Electrical characteristics
(1)
Table 82. OPAMP characteristics (continued)
Parameter Conditions Min
at 1 kHz, Output
Typ
Max
Unit
Normal mode
-
-
-
-
500
-
loaded with 4 kΩ
at 1 kHz, Output
loaded with 20 kΩ
Low-power mode
Normal mode
600
180
290
-
-
-
Voltage noise
density
en
nV/√Hz
at 10 kHz, Output
loaded with 4 kΩ
at 10 kHz, Output
loaded with 20 kΩ
Low-power mode
OPAMP
Normal mode
-
-
120
45
260
100
no Load, quiescent
mode
IDDA(OPAMP)(3) consumption
from VDDA
µA
Low-power mode
1. Guaranteed by design, unless otherwise specified.
2. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V
3. Guaranteed by characterization results.
4. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 69: I/O static characteristics.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
6.3.21
Temperature sensor characteristics
Table 83. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VTS linearity with temperature
-
±1
2.5
±2
2.7
°C
mV/°C
V
Avg_Slope(2) Average slope
2.3
V30
Voltage at 30°C (±5 °C)(3)
0.742
0.76
0.785
tSTART
Sensor Buffer Start-up time in continuous mode(4)
-
8
15
µs
(TS_BUF)(1)
Start-up time when entering in continuous mode(4)
ADC sampling time when reading the temperature
-
70
-
120
-
µs
µs
(1)
tSTART
(1)
tS_temp
5
Temperature sensor consumption from VDD, when
selected by ADC
I
DD(TS)(1)
-
4.7
7
µA
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 8:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
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Electrical characteristics
STM32L412xx
6.3.22
V
monitoring characteristics
BAT
Table 84. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
39
3
-
-
-
kΩ
-
Ratio on VBAT measurement
Error on Q
Er(1)
-10
12
10
-
%
µs
(1)
tS_vbat
ADC sampling time when reading the VBAT
-
1. Guaranteed by design.
Table 85. V
charging characteristics
BAT
Symbol
Parameter Conditions
Min
Typ
5
Max
Unit
Battery
charging
resistor
VBRS = 0
VBRS = 1
-
-
-
-
RBC
kΩ
1.5
6.3.23
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 86. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
-
1
12.5
0
-
tTIMxCLK
ns
tres(TIM)
Timer resolution time
fTIMxCLK = 80 MHz
-
-
fTIMxCLK/2
40
MHz
MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 80 MHz
0
TIMx (except
TIM2)
-
16
ResTIM
Timer resolution
bit
TIM2
-
-
32
1
65536
819.2
tTIMxCLK
µs
16-bit counter clock
period
tCOUNTER
fTIMxCLK = 80 MHz 0.0125
-
-
-
65536 × 65536 tTIMxCLK
53.68
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 80 MHz
s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
156/192
DS12469 Rev 8
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Electrical characteristics
(1)
Table 87. IWDG min/max timeout period at 32 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
/8
0
0.125
0.250
0.500
1.0
512
1024
2048
4096
8192
16384
32768
1
/16
/32
/64
/128
/256
2
3
4
ms
2.0
5
4.0
6 or 7
8.0
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Table 88. WWDG min/max timeout value at 80 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0512
0.1024
0.2048
0.4096
3.2768
6.5536
ms
13.1072
26.2144
6.3.24
Communication interfaces characteristics
I2C interface characteristics
2
The I2C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0394 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
is disabled, but is still present. Only FT_f I/O pins
DDIOx
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
DS12469 Rev 8
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Electrical characteristics
STM32L412xx
(1)
Table 89. I2C analog filter characteristics
Symbol
Parameter
Min
Max
260(3)
Unit
Maximum pulse width of spikes
that are suppressed by the analog
filter
tAF
50(2)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
158/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
SPI characteristics
Unless otherwise specified, the parameters given in Table 90 for SPI are derived from tests
performed under the ambient temperature, f frequency and supply voltage conditions
PCLKx
summarized in Table 21: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 ₓ V
DD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 90. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode receiver/full duplex
2.7 < VDD < 3.6 V
40
Voltage Range 1
Master mode receiver/full duplex
1.71 < VDD < 3.6 V
Voltage Range 1
16
40
Master mode transmitter
1.71 < VDD < 3.6 V
Voltage Range 1
fSCK
1/tc(SCK)
SPI clock frequency
Slave mode receiver
1.71 < VDD < 3.6 V
Voltage Range 1
-
-
MHz
40
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V
Voltage Range 1
37(2)
20(2)
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V
Voltage Range 1
Voltage Range 2
13
-
tsu(NSS) NSS setup time
th(NSS) NSS hold time
tw(SCKH)
Slave mode, SPI prescaler = 2
Slave mode, SPI prescaler = 2
4ₓTPCLK
2ₓTPCLK
-
-
ns
ns
-
SCK high and low time Master mode
TPCLK-2
TPCLK
TPCLK+2 ns
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
Master mode
Slave mode
Master mode
Slave mode
4
1.5
6.5
1.5
9
-
-
-
-
-
-
-
Data input setup time
Data input hold time
ns
-
-
ns
th(SI)
-
ta(SO) Data output access time Slave mode
tdis(SO) Data output disable time Slave mode
36
16
ns
ns
9
DS12469 Rev 8
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Electrical characteristics
STM32L412xx
(1)
Table 90. SPI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Slave mode 2.7 < VDD < 3.6 V
Voltage Range 1
-
12.5
13.5
Slave mode 1.71 < VDD < 3.6 V
Voltage Range 1
tv(SO)
-
-
12.5
12.5
24
33
Data output valid time
ns
Slave mode 1.71 < VDD < 3.6 V
Voltage Range 2
tv(MO)
th(SO)
th(MO)
Master mode
Slave mode
Master mode
-
4.5
6
-
7
0
-
-
Data output hold time
ns
-
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
Figure 33. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tsu(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
th(SO)
tf(SCK)
Last bit OUT
tdis(SO)
MISO output
MOSI input
First bit OUT
th(SI)
Next bits OUT
tsu(SI)
First bit IN
Next bits IN
Last bit IN
MSv41658V1
160/192
DS12469 Rev 8
STM32L412xx
Electrical characteristics
Figure 34. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
tf(SCK)
th(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO)
tw(SCKL)
tv(SO)
First bit OUT
tsu(SI) th(SI)
First bit IN
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
MISO output
MOSI input
Last bit OUT
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
Figure 35. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
BIT6 IN
LSB IN
MSB IN
t
h(MI)
MOSI
OUTPUT
BIT1 OUT
LSB OUT
MSB OUT
t
t
h(MO)
v(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
DS12469 Rev 8
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Electrical characteristics
STM32L412xx
Quad SPI characteristics
Unless otherwise specified, the parameters given in Table 91 and Table 92 for Quad SPI
are derived from tests performed under the ambient temperature, f frequency and V
AHB
DD
supply voltage conditions summarized in Table 21: General operating conditions, with the
following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 15 or 20 pF
Measurement points are done at CMOS levels: 0.5 ₓ V
DD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
Table 91. Quad SPI characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.71 < VDD< 3.6 V, CLOAD = 20 pF
Voltage Range 1
-
-
40
1.71 < VDD< 3.6 V, CLOAD = 15 pF
Voltage Range 1
-
-
-
-
-
-
48
60
26
FCK
Quad SPI clock frequency
MHz
1/t(CK)
2.7 < VDD< 3.6 V, CLOAD = 15 pF
Voltage Range 1
1.71 < VDD < 3.6 V CLOAD = 20 pF
Voltage Range 2
tw(CKH)
tw(CKL)
t
(CK)/2-2
-
-
t(CK)/2
Quad SPI clock high and
low time
fAHBCLK= 48 MHz, presc=0
t(CK)/2
t(CK)/2+2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
2
3.5
5
-
-
-
ts(IN)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
-
-
-
th(IN)
ns
6.5
-
-
-
1
3
-
5
5
-
tv(OUT)
-
0
th(OUT)
0
-
-
1. Guaranteed by characterization results.
162/192
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STM32L412xx
Symbol
Electrical characteristics
(1)
Table 92. QUADSPI characteristics in DDR mode
Parameter
Conditions
Min
Typ
Max
Unit
1.71 < VDD < 3.6 V, CLOAD = 20 pF
Voltage Range 1
-
-
-
-
-
40
2 < VDD < 3.6 V, CLOAD = 20 pF
Voltage Range 1
-
-
-
48
48
26
FCK
Quad SPI clock
frequency
MHz
1/t(CK)
1.71 < VDD < 3.6 V, CLOAD = 15 pF
Voltage Range 1
1.71 < VDD < 3.6 V CLOAD = 20 pF
Voltage Range 2
tw(CKH)
tw(CKL)
t
(CK)/2-2
t(CK)/2
1
-
-
t(CK)/2
Quad SPI clock high
and low time
fAHBCLK = 48 MHz, presc=0
t(CK)/2+2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Voltage Range 1
Voltage Range 2
Data input setup time
on rising edge
tsr(IN)
-
-
-
-
-
-
-
-
3.5
1
Data input setup time
on falling edge
tsf(IN)
1.5
6
Data input hold time
on rising edge
thr(IN)
6.5
5.5
5.5
Data input hold time
on falling edge
thf(IN)
ns
5
9.5
5
5.5
14
Data output valid time
on rising edge
tvr(OUT)
tvf(OUT)
thr(OUT)
thf(OUT)
-
-
8.5
19
Data output valid time
on falling edge
15
-
3.5
8
Data output hold time
on rising edge
-
-
-
3.5
13
-
Data output hold time
on falling edge
-
1. Guaranteed by characterization results.
DS12469 Rev 8
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Electrical characteristics
STM32L412xx
Figure 36. Quad SPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D0
D1
D2
ts(IN)
th(IN)
Data input
D0
D1
D2
MSv36878V1
Figure 37. Quad SPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT) thr(OUT)
IO0
tvr(OUT)
thf(OUT)
IO3
Data output
IO1
IO2
IO4
tsr(IN)thr(IN)
IO5
tsf(IN) thf(IN)
Data input
IO0
IO1
IO2
IO3
IO4
IO5
MSv36879V3
USB characteristics
The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF
certified (for Full-speed device operation).
(1)
Table 93. USB electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDUSB
USB transceiver operating voltage
3.0(2)
-15
-
-
3.6
85
V
Tcrystal_less USB crystal less operation temperature
-
-
°C
μs
(3)
tSTARTUP
RPUI
USB transceiver startup time
1.0
Embedded USB_DP pull-up value during idle
900
1250
1600
Ω
Ω
Embedded USB_DP pull-up value during
reception
RPUR
1400
28
2300
36
3200
44
Driving high
Output driver impedance(4)
and low
(3)
ZDRV
1. TA = -40 to 125 °C unless otherwise specified.
2. The STM32L412xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics
which are degraded in the 2.7-to-3.0 V voltage range.
3. Guaranteed by design.
4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
164/192
DS12469 Rev 8
STM32L412xx
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
DS12469 Rev 8
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189
Package information
STM32L412xx
7.1
LQFP64 package information
This LQFP is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 38. LQFP64 - Outline
SEATING PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
D1
D3
L
L1
33
48
32
49
64
b
17
16
1
PIN 1
e
IDENTIFICATION
5W_ME_V3
1. Drawing is not to scale.
Table 94. LQFP64 - Mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
-
-
-
-
12.000
10.000
7.500
12.000
10.000
-
-
-
-
-
-
-
-
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
-
-
-
-
-
D1
D3
E
E1
166/192
DS12469 Rev 8
STM32L412xx
Package information
Table 94. LQFP64 - Mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E3
e
-
7.500
0.500
3.5°
-
-
0.2953
0.0197
3.5°
-
-
-
7°
-
-
7°
K
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
Figure 39. LQFP64 - Recommended footprint
48
33
0.3
0.5
49
32
12.7
10.3
10.3
7.8
17
64
1.2
16
1
12.7
ai14909c
1. Dimensions are expressed in millimeters.
Device marking
The following figures give examples of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
DS12469 Rev 8
167/192
189
Package information
STM32L412xx
Figure 40. LQFP64 marking (package top view)
Revision code
Product identification(1)
A
STM32L412
RBT6
Date code
YWW
Pin 1 identifier
MS49693V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Figure 41. LQFP64 (external SMPS device) marking (package top view)
Revision code
Product identification(1)
A
STM32L412
RBT6P
Date code
YWW
Pin 1 identifier
MS49694V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
168/192
DS12469 Rev 8
STM32L412xx
Package information
7.2
UFBGA64 package information
This UFBGA is a 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package.
Figure 42. UFBGA64 - Outline
Z Seating plane
ddd Z
A4
A3 A2
A1
A
E1
X
A1 ball
A1 ball
E
identifier index area
e
F
A
H
F
D1
D
e
Y
8
1
Øb (64 balls)
Øeee M Z Y X
Øfff M Z
BOTTOM VIEW
TOP VIEW
A019_ME_V1
1. Drawing is not to scale.
Table 95. UFBGA64 - Mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A2
A3
A4
b
0.460
0.050
0.400
0.080
0.270
0.170
4.850
3.450
4.850
3.450
-
0.530
0.080
0.450
0.130
0.320
0.280
5.000
3.500
5.000
3.500
0.500
0.750
0.600
0.110
0.500
0.180
0.370
0.330
5.150
3.550
5.150
3.550
-
0.0181
0.0020
0.0157
0.0031
0.0106
0.0067
0.1909
0.1358
0.1909
0.1358
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.1969
0.1378
0.1969
0.1378
0.0197
0.0295
0.0236
0.0043
0.0197
0.0071
0.0146
0.0130
0.2028
0.1398
0.2028
0.1398
-
D
D1
E
E1
e
F
0.700
0.800
0.0276
0.0315
DS12469 Rev 8
169/192
189
Package information
Symbol
STM32L412xx
Table 95. UFBGA64 - Mechanical data (continued)
millimeters
Typ
inches(1)
Min
Max
Min
Typ
Max
ddd
eee
fff
-
-
-
-
-
-
0.080
0.150
0.050
-
-
-
-
-
-
0.0031
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 43. UFBGA64 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 96. UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.280 mm
Between 0.100 mm and 0.125 mm
0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
170/192
DS12469 Rev 8
STM32L412xx
Package information
Figure 44. UFBGA64 marking (package top view)
Product identification(1)
L412RBI6
Date code
Y WW
A
Pin 1 identifier
MS49695V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Figure 45. UFBGA64 marking (package top view)
Product identification(1)
L412RB6P
Date code
Y WW
A
Pin 1 identifier
MS53657V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12469 Rev 8
171/192
189
Package information
STM32L412xx
7.3
LQFP48 package information
This LQFP is a 48 pins, 7 x 7 mm low-profile quad flat package
Figure 46. LQFP48 - Outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
D
L
D1
D3
L1
36
25
37
24
b
48
13
PIN 1
IDENTIFICATION
1
12
e
5B_ME_V2
1. Drawing is not to scale.
172/192
DS12469 Rev 8
STM32L412xx
Package information
inches(1)
Table 97. LQFP48 - Mechanical data
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS12469 Rev 8
173/192
189
Package information
STM32L412xx
Figure 47. LQFP48 - Recommended footprint
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911d
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 48. LQFP48 marking (package top view)
STM32L412
Product identification(1)
CBT6
Date code
Y WW
Pin 1 identifier
Revision code
A
MS49696V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
174/192
DS12469 Rev 8
STM32L412xx
Package information
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
7.4
UFQFPN48 package information
This UFQFPN is a 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.
Figure 49. UFQFPN48 - Outline
Pin 1 identifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500x45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DS12469 Rev 8
175/192
189
Package information
STM32L412xx
Table 98. UFQFPN48 - Mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 50. UFQFPN48 - Recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
176/192
DS12469 Rev 8
STM32L412xx
Package information
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 51. UFQFPN48 marking (package top view)
STM32L412
Product identification(1)
CBU6
Date code
Y WW
Pin 1 identifier
Revision code
A
MS49697V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12469 Rev 8
177/192
189
Package information
STM32L412xx
7.5
WLCSP36 package information
This WLCSP is a 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 52. WLCSP36 - Outline
bbb
Z
A1 ball location
F
A1
e1
G
A6
B6
C6
D6
E6
F6
A5
B5
C5
D5
E5
F5
A4
B4
C4
D4
E4
F4
A3
A2
B2
C2
D2
E2
F2
A1
B1
C1
D1
E1
F1
B3
C3
D3
E3
F3
DETAIL A
e2
E
e
e
A
D
A2
aaa
(4X)
BOTTOM VIEW
TOP VIEW
SIDE VIEW
A3
BUMP
FRONT VIEW
eee Z
Z
b(36x)
ccc
Y
Z X
Z
ddd
DETAIL A
ROTATED 90
SEATING PLANE
B03P_WLCSP36_DIE464_ME_V1
1. Drawing is not to scale.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
178/192
DS12469 Rev 8
STM32L412xx
Package information
inches(1)
Table 99. WLCSP36 - Mechanical data
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A(2)
A1
A2
A3(3)
b
-
-
0.59
-
-
0.023
-
0.18
0.38
0.025
0.25
2.58
3.07
0.40
2.00
2.00
0.290
0.535
0.10
0.10
0.10
0.05
0.05
-
-
0.007
0.015
0.001
0.010
0.102
0.121
0.016
0.079
0.079
0.0114
0.0211
0.004
0.004
0.004
0.002
0.002
-
-
-
-
-
-
-
-
-
0.22
0.28
0.009
0.011
D
2.55
2.61
0.100
0.103
E
3.04
3.10
0.120
0.122
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
F(4)
G(4)
aaa
bbb
ccc
ddd
eee
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place
Figure 53. WLCSP36 - Recommended footprint
Dpad
Dsm
B03P_WLCSP36_DIE464_FP_V1
1. Dimensions are expressed in millimeters.
DS12469 Rev 8
179/192
189
Package information
STM32L412xx
Table 100. WLCSP36 - Recommended PCB design rules
Dimension Recommended values
Pitch
Dpad
Dsm
0.4 mm
0,225 mm
0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening
0.250 mm
0.100 mm
Stencil thickness
Device marking
The following figure gives an example of topside marking orientation versus ball 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 54. WLCSP36 marking (package top view)
Ball A1 identifier
Product identification(1)
L412B6
A
Revision code
Date code
Y WW
MS51421V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
180/192
DS12469 Rev 8
STM32L412xx
Package information
7.6
UFQFPN32 package information
This UFQFPN is a 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package.
Figure 55. UFQFPN32 - Outline
D
A
ddd C
A1
A3
e
C
SEATINGPLANE
D1
b
e
b
E2
E1
E
1
L
32
D2
L
PIN 1 Identifier
A0B8_ME_V3
1. Drawing is not to scale.
2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.
DS12469 Rev 8
181/192
189
Package information
STM32L412xx
Table 101. UFQFPN32 - Mechanical data
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
A
A1
A3
b
0.500
-
0.550
-
0.600
0.050
-
0.0197
-
0.0217
-
0.0236
0.0020
-
-
0.152
0.230
5.000
3.500
3.500
5.000
3.500
3.500
0.500
0.400
-
-
0.0060
0.0091
0.1969
0.1378
0.1378
0.1969
0.1378
0.1378
0.0197
0.0157
-
0.180
4.900
3.400
3.400
4.900
3.400
3.400
-
0.280
5.100
3.600
3.600
5.100
3.600
3.600
-
0.0071
0.1929
0.1339
0.1339
0.1929
0.1339
0.1339
-
0.0110
0.2008
0.1417
0.1417
0.2008
0.1417
0.1417
-
D
D1
D2
E
E1
E2
e
L
0.300
-
0.500
0.080
0.0118
-
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 56. UFQFPN32 - Recommended footprint
5.30
3.80
0.60
25
32
1
24
3.45
3.80
5.30
3.45
0.50
8
17
0.30
16
9
0.75
3.80
A0B8_FP_V2
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
182/192
DS12469 Rev 8
STM32L412xx
Package information
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 57. UFQFPN32 marking (package top view)
Product identification(1)
L412KB6
Revision code
Date code
Y WW A
Pin 1 identifier
MS49698V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS12469 Rev 8
183/192
189
Package information
STM32L412xx
7.7
LQFP32 package information
This LQFP is a 32 pins, 7 x 7 mm low-profile quad flat package.
Figure 58. LQFP32 - Outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
K
D
D1
D3
L
L1
24
17
16
25
32
9
PIN 1
IDENTIFICATION
1
8
e
5V_ME_V2
1. Drawing is not to scale.
184/192
DS12469 Rev 8
STM32L412xx
Package information
inches(1)
Table 102. LQFP32 - Mechanical data
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.300
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.450
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
-
-
-
1.400
0.370
-
0.0551
0.0146
-
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 59. LQFP32 - Recommended footprint
0.80
1.20
24
17
25
16
0.50
0.30
7.30
6.10
9.70
7.30
32
9
8
1
1.20
6.10
9.70
5V_FP_V2
1. Dimensions are expressed in millimeters.
DS12469 Rev 8
185/192
189
Package information
STM32L412xx
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 60. LQFP32 marking (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
186/192
DS12469 Rev 8
STM32L412xx
Package information
7.8
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of all I
and V
, expressed in Watts. This is the
DDXXX
INT
DDXXX
maximum chip internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ ((V
– V ) × I ),
I/O
OL
OL
DDIOx OH OH
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 103. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
66
63
30
68
85
68
37
Thermal resistance junction-ambient
UFBGA64 - 5 × 5 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFQFPN48 - 7 × 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm / 0.5 mm pitch
ΘJA
°C/W
Thermal resistance junction-ambient
WLCSP36 - 2.58 x 3.07 mm / 0.4 mm pitch
Thermal resistance junction-ambient
LQFP32 - 7 x 7 / 0.8 mm pitch
Thermal resistance junction-ambient
UFQFPN32- 5 × 5 mm / 0.5 mm pitch
7.8.1
7.8.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
DS12469 Rev 8
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189
Package information
STM32L412xx
As applications do not commonly use the STM32L412xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 72 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V = 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW:
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Using the values obtained in Table 103 T
is calculated as follows:
Jmax
–
T
For LQFP64, 66 °C/W
= 72 °C + (66 °C/W × 447 mW) = 72 °C + 29.502 °C = 101.502 °C
Jmax
This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Section 8:
J
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see Part
numbering).
Note:
With this given P
user can find the T
allowed for a given device temperature range
Dmax
Amax
(order code suffix 6 or 37).
Suffix 6: T
Suffix 3: T
= T
= T
- (66°C/W × 447 mW) = 105-29.502 = 75.498 °C
- (46°C/W × 447 mW) = 130-29.502 = 100.498 °C
Amax
Amax
Jmax
Jmax
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T remains within the
J
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
= 100 °C (measured according to JESD51-2),
Amax
I
= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V
OL
OL
P
P
= 20 mA × 3.5 V = 70 mW
INTmax
= 20 × 8 mA × 0.4 V = 64 mW
IOmax
This gives: P
= 70 mW and P
= 64 mW:
IOmax
INTmax
P
= 70 + 64 = 134 mW
Dmax
Thus: P
= 134 mW
Dmax
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DS12469 Rev 8
STM32L412xx
Package information
Using the values obtained in Table 103 T
is calculated as follows:
Jmax
–
T
For LQFP64, 66 °C/W
= 100 °C + (66 °C/W × 134 mW) = 100 °C + 8.844 °C = 108.844 °C
Jmax
This is above the range of the suffix 6 version parts (–40 < T < 105 °C).
J
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
DS12469 Rev 8
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189
Ordering information
STM32L412xx
8
Ordering information
Table 104. STM32L412xx ordering information scheme
STM32 412
Example:
Device family
L
R
B
T
6
P TR
®
STM32 = Arm based 32-bit microcontroller
Product type
L = ultra-low-power
Device subfamily
412 = STM32L412xx
Pin count
K = 32 pins
T = 36 pins
C = 48 pins
R = 64 pins
Flash memory size
B = 128 KB of Flash memory
8 = 64 KB of Flash memory
Package
T = LQFP ECOPACK2
U = QFN ECOPACK2
I = UFBGA ECOPACK2
Y = CSP ECOPACK2
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
3 = Industrial temperature range, -40 to 125 °C (130 °C junction)
Option
Blank = Standard production with integrated LDO
P = Dedicated pinout supporting external SMPS
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (such as speed, package) or for further information on any
aspect of this device contact the nearest ST sales office.
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STM32L412xx
Revision history
9
Revision history
Table 105. Document revision history
Date
Revision
Changes
02-Oct-2018
1
Initial release.
Updated:
– Features
– Table 25: Current consumption in Run and Low-power
run modes, code with data processing running from
Flash, ART enable (Cache ON Prefetch OFF),
Table 27: Current consumption in Run and Low-power
run modes, code with data processing running from
Flash, ART disable, Table 29: Current consumption in
Run and Low-power run modes, code with data
processing running from SRAM1, Table 40: Current
consumption in Sleep and Low-power sleep modes,
Flash ON, Table 42: Current consumption in Low-
power sleep modes, Flash in power-down, Table 43:
Current consumption in Stop 2 mode, Table 48:
Current consumption in VBAT mode, Table 49:
Peripheral current consumption
18-Oct-2018
2
Updated Table 46: Current consumption in Standby
mode, Table 22: Operating conditions at power-up /
power-down, Table 23: Embedded reset and power
control block characteristics, Table 65: EMI
characteristics.
03-Dec-2018
3
Removed Figure 5: STM32L412Vx, external SMPS
device, LQFP100 pinout
18-Dec-2018
11-Feb-2019
4
5
Updated Table 99: WLCSP36 - Mechanical data.
Added Figure 12: STM32L412Tx, external SMPS,
WLCSP36 ballout(1)
.
Updated Table 14: STM32L412xx pin definitions.
03-Jun-2019
26-Sep-2019
6
7
Updated Table 16: Alternate function AF8 to AF15
Updated Table 2: STM32L412xx family device features
and peripheral counts
Updated Table 16: Alternate function AF8 to AF15
Added UFBGA64 SMPS in Table 14: STM32L412xx pin
definitions, Figure 8: STM32L412Rx UFBGA64, external
SMPS, ballout(1)
03-Nov-2020
8
DS12469 Rev 8
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191
STM32L412xx
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
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product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
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